Index: branches/v4/communication/gate_2/caba/metadata/gate_2.sd
===================================================================
--- branches/v4/communication/gate_2/caba/metadata/gate_2.sd	(revision 371)
+++ branches/v4/communication/gate_2/caba/metadata/gate_2.sd	(revision 371)
@@ -0,0 +1,32 @@
+# -*- python -*-
+
+__id__ = "$Id: gate.sd 917 2009-03-12 10:10:06Z nipo $"
+__version__ = "$Revision: 917 $"
+
+Signal('caba:gate_2',
+	   classname = 'soclib::caba::GateSignals2',
+	   accepts = {'caba:gate_initiator_2':1,
+		      'caba:gate_target_2':1},
+	   header_files = ['../source/include/gate_signals_2.h'],
+           tmpl_parameters = [
+                parameter.Int('ring_cmd_data_size'),
+                parameter.Int('ring_rsp_data_size'),
+           ],
+  
+	   )
+
+PortDecl('caba:gate_initiator_2',
+         classname = 'soclib::caba::GateInitiator2',
+	 signal = 'caba:gate_2',
+	 header_files = ['../source/include/gate_ports_2.h'],
+	 
+	 )
+
+PortDecl('caba:gate_target_2',
+         classname = 'soclib::caba::GateTarget2',
+	 signal = 'caba:gate_2',
+	 header_files = ['../source/include/gate_ports_2.h'],
+	 
+	 )
+
+
Index: branches/v4/communication/gate_2/caba/source/include/gate_ports_2.h
===================================================================
--- branches/v4/communication/gate_2/caba/source/include/gate_ports_2.h	(revision 371)
+++ branches/v4/communication/gate_2/caba/source/include/gate_ports_2.h	(revision 371)
@@ -0,0 +1,139 @@
+/* -*- c++ -*-
+ * SOCLIB_LGPL_HEADER_BEGIN
+ * 
+ * This file is part of SoCLib, GNU LGPLv2.1.
+ * 
+ * SoCLib is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU Lesser General Public License as published
+ * by the Free Software Foundation; version 2.1 of the License.
+ * 
+ * SoCLib is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * Lesser General Public License for more details.
+ * 
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with SoCLib; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301 USA
+ * 
+ * SOCLIB_LGPL_HEADER_END
+ *
+ * Authors  : Franck WAJSBÜRT, Abdelmalek SI MERABET 
+ * Date     : january 2009
+ * Copyright: UPMC - LIP6
+ */
+
+#ifndef SOCLIB_CABA_GATE_PORTS_H_
+#define SOCLIB_CABA_GATE_PORTS_H_
+
+#include "gate_signals_2.h"
+
+namespace soclib { namespace caba {
+
+template<int ring_cmd_data_size, int ring_rsp_data_size>
+class GateTarget2
+{
+public:
+
+	sc_core::sc_out<sc_dt::sc_uint<ring_cmd_data_size> > cmd_data;
+	sc_core::sc_in<bool> cmd_wok;
+	sc_core::sc_out<bool> cmd_w;
+
+	sc_core::sc_in<sc_dt::sc_uint<ring_rsp_data_size> > rsp_data;
+	sc_core::sc_out<bool> rsp_r;
+	sc_core::sc_in<bool> rsp_rok;
+
+	GateTarget2(const std::string &name = sc_core::sc_gen_unique_name("gate_target_2_"))
+		:   cmd_data     ((name+"cmd_data").c_str()),
+		    cmd_wok      ((name+"cmd_wok").c_str()),
+                    cmd_w        ((name+"cmd_w").c_str()),
+
+		    rsp_data     ((name+"rsp_data").c_str()),
+		    rsp_r        ((name+"rsp_r").c_str()),
+                    rsp_rok      ((name+"rsp_rok").c_str())
+		{ }
+    
+	void operator () (GateSignals2<ring_cmd_data_size, ring_rsp_data_size> &sig)
+	{
+		
+                cmd_data    		(sig.cmd_data);	
+		cmd_wok    		(sig.cmd_r_wok);	
+		cmd_w    		(sig.cmd_w_rok);	
+		
+		rsp_data    		(sig.rsp_data);
+		rsp_r    		(sig.rsp_r_wok);
+		rsp_rok    		(sig.rsp_w_rok);
+		
+	}
+
+        void operator () (GateTarget2 &port)
+	{
+	      	cmd_data    		(port.cmd_data);	
+		cmd_wok    		(port.cmd_wok);	
+		cmd_w    		(port.cmd_w);	
+		
+		rsp_data    		(port.rsp_data);
+		rsp_r    		(port.rsp_r);
+		rsp_rok    		(port.rsp_rok);
+  		
+	}
+
+};
+
+template<int ring_cmd_data_size, int ring_rsp_data_size>
+class GateInitiator2
+{
+public:
+	
+	sc_core::sc_in<sc_dt::sc_uint<ring_cmd_data_size> > cmd_data;
+	sc_core::sc_out<bool> cmd_r;
+	sc_core::sc_in<bool> cmd_rok;
+
+	sc_core::sc_out<sc_dt::sc_uint<ring_rsp_data_size> > rsp_data;
+	sc_core::sc_in<bool> rsp_wok;
+	sc_core::sc_out<bool> rsp_w;
+	
+	GateInitiator2(const std::string &name = sc_core::sc_gen_unique_name("gate_initiator_2_"))
+		:  
+
+		cmd_data     ((name+"cmd_data").c_str()),
+		cmd_r        ((name+"cmd_r").c_str()),
+                cmd_rok      ((name+"cmd_rok").c_str()),
+
+		rsp_data     ((name+"rsp_data").c_str()),
+		rsp_wok      ((name+"rsp_wok").c_str()),
+                rsp_w        ((name+"rsp_w").c_str())
+    		{ }
+    
+	void operator () (GateSignals2<ring_cmd_data_size, ring_rsp_data_size> &sig)
+	{
+		cmd_data    		(sig.cmd_data);
+		cmd_r    		(sig.cmd_r_wok);
+		cmd_rok    		(sig.cmd_w_rok);
+		
+                rsp_data    		(sig.rsp_data);	
+		rsp_wok    		(sig.rsp_r_wok);	
+		rsp_w    		(sig.rsp_w_rok);
+	}
+
+        void operator () (GateInitiator2 &port)
+	{
+
+		cmd_data    		(port.cmd_data);
+		cmd_r    		(port.cmd_r);
+		cmd_rok    		(port.cmd_rok);
+
+	      	rsp_data    		(port.rsp_data);	
+		rsp_wok    		(port.rsp_wok);	
+		rsp_w    		(port.rsp_w);
+	}
+	    
+	
+};
+
+}}
+
+#endif // SOCLIB_CABA_GATE_PORTS_H_
+
+
Index: branches/v4/communication/gate_2/caba/source/include/gate_signals_2.h
===================================================================
--- branches/v4/communication/gate_2/caba/source/include/gate_signals_2.h	(revision 371)
+++ branches/v4/communication/gate_2/caba/source/include/gate_signals_2.h	(revision 371)
@@ -0,0 +1,62 @@
+/* -*- c++ -*-
+ * SOCLIB_LGPL_HEADER_BEGIN
+ * 
+ * This file is part of SoCLib, GNU LGPLv2.1.
+ * 
+ * SoCLib is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU Lesser General Public License as published
+ * by the Free Software Foundation; version 2.1 of the License.
+ * 
+ * SoCLib is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * Lesser General Public License for more details.
+ * 
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with SoCLib; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301 USA
+ * 
+ * SOCLIB_LGPL_HEADER_END
+ *
+ * Authors  : Franck WAJSBÜRT, Abdelmalek SI MERABET 
+ * Date     : january 2009
+ * Copyright: UPMC - LIP6
+ */
+
+#ifndef SOCLIB_CABA_GATE_SIGNALS_H_
+#define SOCLIB_CABA_GATE_SIGNALS_H_
+
+#include "systemc.h" 
+
+namespace soclib { namespace caba {
+using namespace sc_core;
+using namespace sc_dt;
+
+template<int ring_cmd_data_size, int ring_rsp_data_size>
+class GateSignals2
+{
+public:
+
+	sc_core::sc_signal<sc_dt::sc_uint<ring_cmd_data_size> > cmd_data;
+	sc_core::sc_signal<bool> cmd_r_wok;
+	sc_core::sc_signal<bool> cmd_w_rok;
+
+	sc_core::sc_signal<sc_dt::sc_uint<ring_rsp_data_size> > rsp_data;
+	sc_core::sc_signal<bool> rsp_r_wok;
+	sc_core::sc_signal<bool> rsp_w_rok;
+
+	GateSignals2(std::string name = (std::string)sc_core::sc_gen_unique_name("gate_signals_2_"))
+	  : 	cmd_data	((name+"cmd_data").c_str()),
+		cmd_r_wok       ((name+"cmd_r_wok").c_str()),
+		cmd_w_rok	((name+"cmd_w_rok").c_str()),
+		
+		rsp_data	((name+"rsp_data").c_str()),
+		rsp_r_wok       ((name+"rsp_r_wok").c_str()),
+		rsp_w_rok	((name+"rsp_w_rok").c_str())
+	  { }
+};
+
+}} // end namespace
+
+#endif /* SOCLIB_CABA_GATE_SIGNALS_H_ */
Index: branches/v4/lib/generic_cache_tsar/include/generic_cache.h
===================================================================
--- branches/v4/lib/generic_cache_tsar/include/generic_cache.h	(revision 371)
+++ branches/v4/lib/generic_cache_tsar/include/generic_cache.h	(revision 371)
@@ -0,0 +1,1029 @@
+/* -*- c++ -*-
+ *
+ * SOCLIB_LGPL_HEADER_BEGIN
+ *
+ * This file is part of SoCLib, GNU LGPLv2.1.
+ *
+ * SoCLib is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU Lesser General Public License as published
+ * by the Free Software Foundation; version 2.1 of the License.
+ *
+ * SoCLib is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with SoCLib; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301 USA
+ *
+ * SOCLIB_LGPL_HEADER_END
+ *
+ * Copyright (c) UPMC, Lip6
+ *         Alain Greiner <alain.greiner@lip6.fr> July 2008
+ *
+ * Maintainers: alain
+ */
+
+////////////////////////////////////////////////////////////////////////////////
+// File         : generic_cache.h
+// Date         : 07/01/2012
+// Authors      : Alain Greiner
+/////////////////////////////////////////////////////////////////////////////////
+// This object is a generic, set associative, cache.
+// Each slot can be in three states: VALID, EMPTY or ZOMBI.
+// The ZOMBI state is used by cache coherence protocoles to indicate
+// a pending cleanup request.
+// Hit if ( (matching tag) and (state == VALID).
+// The replacement policy is pseudo-LRU. The victim selection process cannot
+// fail if the ZOMBI state is not used. 
+// But it can fail if all ways are in ZOMBI state.
+/////////////////////////////////////////////////////////////////////////////////
+// Implementation note
+// The DATA part is implemented as an uint32_t array[nways*nsets*nwords].
+// The DIRECTORY part is implemented as an uint32_t array[nways*nsets].
+// All methods requiring a dual port RAM or cache modification using
+// an associative search have been deprecated.
+/////////////////////////////////////////////////////////////////////////////////
+// Constructor parameters are :
+// - std::string    &name
+// - size_t         nways   : number of associativity levels 
+// - size_t         nsets   : number of sets
+// - size_t         nwords  : number of words in a cache line
+// The nways, nsets, nwords parameters must be power of 2
+// The nsets parameter cannot be larger than 1024
+// The nways parameter cannot be larger than 16
+// The nwords parameter cannot be larger than 64
+/////////////////////////////////////////////////////////////////////////////////
+// Template parameter is :
+// - addr_t : address format to access the cache 
+// The address can be larger than 32 bits, but the TAG field 
+// cannot be larger than 32 bits.
+/////////////////////////////////////////////////////////////////////////////////
+
+#ifndef SOCLIB_GENERIC_CACHE_H
+#define SOCLIB_GENERIC_CACHE_H
+
+#include <systemc>
+#include <cassert>
+#include "arithmetics.h"
+#include "static_assert.h"
+#include "mapping_table.h"
+#include <cstring>
+
+namespace soclib { 
+
+enum cache_slot_state_e
+{
+    CACHE_SLOT_STATE_EMPTY,
+    CACHE_SLOT_STATE_VALID,
+    CACHE_SLOT_STATE_ZOMBI,
+};
+
+//////////////////////////
+template<typename addr_t>
+class GenericCache 
+//////////////////////////
+{
+    typedef uint32_t    data_t;
+    typedef uint32_t    tag_t;
+    typedef uint32_t    be_t;
+
+    data_t              *r_data ;
+    tag_t               *r_tag ;
+    int                 *r_state;
+    bool                *r_lru ;
+
+    size_t              m_ways;	
+    size_t              m_sets;	
+    size_t              m_words;
+
+    const soclib::common::AddressMaskingTable<addr_t>  m_x ;
+    const soclib::common::AddressMaskingTable<addr_t>  m_y ;
+    const soclib::common::AddressMaskingTable<addr_t>  m_z ;
+
+    //////////////////////////////////////////////////////////////
+    inline data_t &cache_data(size_t way, size_t set, size_t word)
+    {
+        return r_data[(way*m_sets*m_words)+(set*m_words)+word];
+    }
+
+    //////////////////////////////////////////////
+    inline tag_t &cache_tag(size_t way, size_t set)
+    {
+        return r_tag[(way*m_sets)+set];
+    }
+
+    //////////////////////////////////////////////
+    inline bool &cache_lru(size_t way, size_t set)
+    {
+        return r_lru[(way*m_sets)+set];
+    }
+
+    //////////////////////////////////////////////
+    inline int &cache_state(size_t way, size_t set)
+    {
+        return r_state[(way*m_sets)+set];
+    }
+
+    /////////////////////////////////////////////////
+    inline void cache_set_lru(size_t way, size_t set)
+    {
+	    size_t way2;
+
+        cache_lru(way, set) = true;
+
+	    for (way2 = 0; way2 < m_ways; way2++ ) 
+        {
+	        if (cache_lru(way2, set) == false) return;
+	    }
+ 	    // all lines are new -> they all become old 
+	    for (way2 = 0; way2 < m_ways; way2++ ) 
+        {
+	        cache_lru(way2, set) = false;
+	    }
+    }
+
+    /////////////////////////////////////////////
+    inline data_t be2mask( be_t be )
+    {
+        data_t mask = 0;
+        if ( (be & 0x1) == 0x1 ) mask = mask | 0x000000FF;
+        if ( (be & 0x2) == 0x2 ) mask = mask | 0x0000FF00;
+        if ( (be & 0x4) == 0x4 ) mask = mask | 0x00FF0000;
+        if ( (be & 0x8) == 0x8 ) mask = mask | 0xFF000000;
+        return mask;
+    }
+
+public:
+
+    //////////////////////////////////////////////
+    GenericCache(   const std::string   &name,
+                    size_t              nways, 
+                    size_t              nsets, 
+                    size_t              nwords)
+        : m_ways(nways),
+          m_sets(nsets),
+          m_words(nwords),
+
+#define l2 soclib::common::uint32_log2
+
+          m_x( l2(nwords), l2(sizeof(data_t))),
+          m_y( l2(nsets), l2(nwords) + l2(sizeof(data_t))),
+          m_z( 8*sizeof(addr_t) - l2(nsets) - l2(nwords) - l2(sizeof(data_t)),
+               l2(nsets) + l2(nwords) + l2(sizeof(data_t)))
+#undef l2
+    {
+        assert(IS_POW_OF_2(nways));
+        assert(IS_POW_OF_2(nsets));
+        assert(IS_POW_OF_2(nwords));
+        assert(nwords);
+        assert(nsets);
+        assert(nways);
+        assert(nwords <= 64);
+        assert(nsets <= 1024);
+        assert(nways <= 16);
+
+#ifdef GENERIC_CACHE_DEBUG
+        std::cout
+            << " m_x: " << m_x
+            << " m_y: " << m_y
+            << " m_z: " << m_z
+            << std::endl;
+#endif
+
+        r_data    = new data_t[nways*nsets*nwords];
+        r_tag     = new tag_t[nways*nsets];
+        r_state   = new int[nways*nsets];
+        r_lru     = new bool[nways*nsets];
+    }
+
+    ////////////////
+    ~GenericCache()
+    {
+        delete [] r_data;
+        delete [] r_tag;
+        delete [] r_state;
+        delete [] r_lru;
+    }
+
+    ////////////////////
+    inline void reset( )
+    {
+        std::memset(r_data, 0, sizeof(*r_data)*m_ways*m_sets*m_words);
+        std::memset(r_tag, 0, sizeof(*r_tag)*m_ways*m_sets);
+        std::memset(r_state, CACHE_SLOT_STATE_EMPTY, sizeof(*r_state)*m_ways*m_sets);
+        std::memset(r_lru, 0, sizeof(*r_lru)*m_ways*m_sets);
+    }
+
+    /////////////////////////////////////////////////////////////////////
+    // Read a single 32 bits word.
+    // returns true if (matching tag) and (state == VALID) 
+    // Both data & directory are accessed. 
+    /////////////////////////////////////////////////////////////////////
+    inline bool read( addr_t 	ad, 
+                      data_t* 	dt)
+    {
+        const tag_t       tag  = m_z[ad];
+        const size_t      set  = m_y[ad];
+        const size_t      word = m_x[ad];
+
+        for ( size_t way = 0; way < m_ways; way++ ) 
+        {
+            if ( (tag == cache_tag(way, set))  
+                   && (cache_state(way, set) == CACHE_SLOT_STATE_VALID) )
+            {
+                *dt = cache_data(way, set, word);
+                cache_set_lru(way, set);
+                return true;
+            }
+        }
+        return false;
+    }
+
+    ////////////////////////////////////////////////////////////////////
+    // Read a single 32 bits word.
+    // returns true if (matching tag) and (state == VALID) 
+    // Both data & directory are accessed. 
+    // The selected way, set and word index are returned in case of hit.
+    /////////////////////////////////////////////////////////////////////
+    inline bool read( addr_t 	ad, 
+                      data_t* 	dt,
+                      size_t*   selway,
+                      size_t*   selset,
+                      size_t*   selword) 
+    {
+        const tag_t       tag  = m_z[ad];
+        const size_t      set  = m_y[ad];
+        const size_t      word = m_x[ad];
+
+        for ( size_t way = 0; way < m_ways; way++ ) 
+        {
+            if ( (tag == cache_tag(way, set)) and
+                 (cache_state(way, set) == CACHE_SLOT_STATE_VALID) )
+            {
+                *selway  = way;
+                *selset  = set;
+                *selword = word;
+                *dt = cache_data(way, set, word);
+                cache_set_lru(way, set);
+                return true;
+            }
+        }
+        return false;
+    }
+
+    ////////////////////////////////////////////////////////////////////
+    // Read a single 32 bits word when the ZOMBI state is used.
+    // Both data and directory are accessed.
+    // returns the access status in the state argument:
+    // - VALID : (matching tag) and (state == VALID) 
+    // - ZOMBI : (matching tag) and (state == ZOMBI) 
+    // - MISS  : no matching tag or EMPTY state
+    // If VALID or ZOMBI, the data, the way, set and word index are 
+    // returned in the other arguments.
+    ////////////////////////////////////////////////////////////////////
+    inline void read( addr_t    ad,
+                      data_t*   dt,
+                      size_t*   selway,
+                      size_t*   selset,
+                      size_t*   selword,
+                      int*      state ) 
+    {
+        const tag_t       tag  = m_z[ad];
+        const size_t      set  = m_y[ad];
+        const size_t      word = m_x[ad];
+
+        // default return values 
+        *state   = CACHE_SLOT_STATE_EMPTY;
+        *selway  = 0;
+        *selset  = 0;
+        *selword = 0;
+        *dt      = 0;
+
+        for ( size_t way = 0; way < m_ways; way++ ) 
+        {
+            if ( tag == cache_tag(way, set) )  // matching tag
+            {
+
+                if ( cache_state(way, set) == CACHE_SLOT_STATE_VALID )
+                {
+                    *state   = CACHE_SLOT_STATE_VALID;
+                    *selway  = way;
+                    *selset  = set;
+                    *selword = word;
+                    *dt      = cache_data(way, set, word);
+                    cache_set_lru(way, set);
+                }
+                else if ( cache_state(way, set) == CACHE_SLOT_STATE_ZOMBI )
+                {
+                    *state   = CACHE_SLOT_STATE_ZOMBI;
+                    *selway  = way;
+                    *selset  = set;
+                    *selword = word;
+                }
+            }
+        }
+    }
+              
+    ////////////////////////////////////////////////////////////////////
+    // Read a single 32 bits word, without LRU update.
+    // returns true if (matching tag) and (state == VALID) 
+    // Both data & directory are accessed. 
+    // The selected way, set and word index are returned in case of hit.
+    /////////////////////////////////////////////////////////////////////
+    inline bool read_neutral( addr_t 	ad, 
+	            		      data_t* 	dt,
+			                  size_t*   selway,
+			                  size_t*   selset,
+			                  size_t*   selword) 
+    {
+        const tag_t       tag  = m_z[ad];
+        const size_t      set  = m_y[ad];
+        const size_t      word = m_x[ad];
+
+        for ( size_t way = 0; way < m_ways; way++ ) 
+        {
+            if ( (tag == cache_tag(way, set))  
+                   && (cache_state(way, set) == CACHE_SLOT_STATE_VALID) )
+            {
+                *selway  = way;
+                *selset  = set;
+                *selword = word;
+                *dt = cache_data(way, set, word);
+                return true;
+            }
+        }
+        return false;
+    }
+
+    /////////////////////////////////////////////////////////////////////////////
+    // Read one or two 32 bits word.
+    // Both data & directory are accessed. 
+    // Hit if (matching tag) and (valid == true) and (zombi == false) 
+    // If the addressed word is not the last in the cache line,
+    // two successive words are returned.
+    // The selected way, set and first word index are returned in case of hit.
+    // This function is used by the cc_vcache to get a 64 bits page table entry.
+    /////////////////////////////////////////////////////////////////////////////
+    inline bool read( addr_t 	ad, 
+                      data_t* 	dt, 
+                      data_t*	dt_next,
+                      size_t*	selway,
+                      size_t*	selset,
+                      size_t*   selword)
+    {
+        const tag_t       tag  = m_z[ad];
+        const size_t      set  = m_y[ad];
+        const size_t      word = m_x[ad];
+
+        for ( size_t way = 0; way < m_ways; way++ ) 
+        {
+            if ( (tag == cache_tag(way, set))   
+                   && (cache_state(way, set) == CACHE_SLOT_STATE_VALID) ) 
+            {
+                *dt      = cache_data(way, set, word);
+                if ( word+1 < m_words) 
+                {
+                    *dt_next = cache_data(way, set, word+1);
+                }
+                *selway  = way;
+                *selset  = set;
+                *selword = word;
+                cache_set_lru(way, set);
+                return true;
+            }
+        }
+        return false;
+    }
+
+    ////////////////////////////////////////////////////////////////////
+    // Read one or two 32 bits word.
+    // Both data and directory are accessed.
+    // returns the access status in the state argument:
+    // - VALID : (matching tag) and (state == VALID) 
+    // - ZOMBI : (matching tag) and (state == ZOMBI) 
+    // - MISS  : no matching tag or EMPTY state
+    // If VALID or ZOMBI, the data, the way, set and word index are 
+    // returned in the other arguments.
+    ////////////////////////////////////////////////////////////////////
+    inline void read( addr_t    ad,
+                      data_t*   dt,
+                      data_t*   dt_next,
+                      size_t*   selway,
+                      size_t*   selset,
+                      size_t*   selword,
+                      int*      state ) 
+    {
+        const tag_t       tag  = m_z[ad];
+        const size_t      set  = m_y[ad];
+        const size_t      word = m_x[ad];
+
+        // default return values 
+        *state   = CACHE_SLOT_STATE_EMPTY;
+        *selway  = 0;
+        *selset  = 0;
+        *selword = 0;
+        *dt      = 0;
+
+        for ( size_t way = 0; way < m_ways; way++ ) 
+        {
+            if ( tag == cache_tag(way, set) )  // matching tag
+            {
+
+                if ( cache_state(way, set) == CACHE_SLOT_STATE_VALID )
+                {
+                    *state   = CACHE_SLOT_STATE_VALID;
+                    *selway  = way;
+                    *selset  = set;
+                    *selword = word;
+                    *dt      = cache_data(way, set, word);
+                    if ( word+1 < m_words) 
+                    {
+                        *dt_next = cache_data(way, set, word+1);
+                    }
+                    cache_set_lru(way, set);
+                }
+                else if ( cache_state(way, set) == CACHE_SLOT_STATE_ZOMBI )
+                {
+                    *state   = CACHE_SLOT_STATE_ZOMBI;
+                    *selway  = way;
+                    *selset  = set;
+                    *selword = word;
+                }
+            }
+        }
+    }
+
+    ///////////////////////////////////////////////////////////////////////////////
+    // Checks the cache state for a given address.
+    // Only the directory is accessed. 
+    // returns true if (matching tag) and (state == VALID) 
+    // The selected way, set and first word index are returned in case of hit.
+    // This function can be used when we need to access the directory
+    // while we write in the data part with a different address in the same cycle.
+    ///////////////////////////////////////////////////////////////////////////////
+    inline bool hit(  addr_t 	ad, 
+                      size_t*	selway,
+                      size_t*	selset,
+                      size_t*   selword)
+    {
+        const tag_t       tag  = m_z[ad];
+        const size_t      set  = m_y[ad];
+        const size_t      word = m_x[ad];
+
+        for ( size_t way = 0; way < m_ways; way++ ) 
+        {
+            if ( (tag == cache_tag(way, set)) 
+                   && (cache_state(way, set) == CACHE_SLOT_STATE_VALID) ) 
+            {
+                *selway  = way;
+                *selset  = set;
+                *selword = word;
+                cache_set_lru(way, set);
+                return true;
+            }
+        }
+        return false;
+    }
+  
+    ///////////////////////////////////////////////////////////////////////////////
+    // Checks the cache state for a given address, wehn the ZOMBI state is used.
+    // Only the directory is accessed. 
+    // Returns the access status in the state argument:
+    // - VALID if (matching tag) and (state == VALID) 
+    // - ZOMBI if (matching tag) and (state == ZOMBI) 
+    // - EMPTY if no match or (state == EMPTY)
+    // The selected way, set and first word index are returned if not empty.
+    // This function can be used when we need to access the directory
+    // while we write in the data part with a different address in the same cycle.
+    ///////////////////////////////////////////////////////////////////////////////
+    inline void read_dir(  addr_t 	ad, 
+                           int*     state,
+                           size_t*	way,
+                           size_t*	set,
+                           size_t*  word)
+    {
+        const tag_t       ad_tag  = m_z[ad];
+        const size_t      ad_set  = m_y[ad];
+        const size_t      ad_word = m_x[ad];
+
+        for ( size_t _way = 0; _way < m_ways; _way++ ) 
+        {
+            if ( (ad_tag == cache_tag(_way, ad_set) ) and 
+                 (cache_state(_way, ad_set) != CACHE_SLOT_STATE_EMPTY) ) 
+            {
+                *state = cache_state(_way, ad_set);
+                *way   = _way;
+                *set   = ad_set;
+                *word  = ad_word;
+                return;
+            }
+        }
+        
+        // return value if not (VALID or ZOMBI)
+        *state = CACHE_SLOT_STATE_EMPTY;
+    }
+
+    ///////////////////////////////////////////////////////////////////////////////
+    // Checks the cache state for a slot (set,way), when the ZOMBI state is used.
+    // Only the directory is accessed. 
+    // Returns the access status and the tag value in the state and tag argument.
+    ///////////////////////////////////////////////////////////////////////////////
+    inline void read_dir(  size_t 	way,
+                           size_t 	set,
+                           tag_t*   tag,
+                           int*     state )
+    {
+        *state = cache_state(way, set);
+        *tag   = cache_tag(way, set);
+    }
+
+    ////////////////////////////////////////////
+    inline tag_t get_tag(size_t way, size_t set)
+    {
+        return cache_tag(way, set);
+    }
+
+    ///////////////////////////////////////////////////////////////////
+    // This function writes a complete 32 bits word
+    // It does not use the directory and cannot miss.
+    //////////////////////////////////////////////////////////////////
+    inline void write(size_t 	way, 
+                      size_t 	set, 
+                      size_t 	word, 
+                      data_t 	data)
+    {
+        cache_data(way, set, word) = data;
+        cache_set_lru(way, set);
+    }
+
+    ////////////////////////////////////////////////////////////////////////////
+    // this function writes up to 4 bytes, taking into account the byte enable.
+    // It does not use the directory and cannot miss.
+    ////////////////////////////////////////////////////////////////////////////
+    inline void write(size_t 	way, 
+                      size_t 	set, 
+                      size_t 	word, 
+                      data_t 	data, 
+                      be_t 	    be)
+    {
+        data_t mask = be2mask(be);
+        data_t prev = cache_data(way, set, word);
+        cache_data(way, set, word) = (mask & data) | (~mask & prev);
+        cache_set_lru(way, set);
+    }
+
+    //////////////////////////////////////////////////////////////////////////
+    // This function invalidates a cache line identified by the set and way.
+    // It returns true if the line was valid, and returns the line index.
+    //////////////////////////////////////////////////////////////////////////
+    inline bool inval(size_t 	way, 
+                      size_t 	set, 
+                      addr_t* 	nline)
+    {
+        if ( cache_state(way,set) == CACHE_SLOT_STATE_VALID ) 
+        {
+            cache_state(way,set) = CACHE_SLOT_STATE_EMPTY;
+            *nline = (data_t)cache_tag(way,set)* m_sets + set;
+            return true;
+        }
+        return false;
+    }
+
+    //////////////////////////////////////////////////////////////////////////////////
+    // This function selects a victim slot in an associative set.
+    // It cannot fail, as a slot in ZOMBI state is considered EMPTY.
+    // - we search first an EMPTY slot 
+    // - if no EMPTY slot, we search an OLD slot, using lru
+    // It returns the line index (Z + Y fields), the selected slot way and set, 
+    // and a Boolean indicating that a cleanup is requested.
+    //////////////////////////////////////////////////////////////////////////////////
+    inline bool victim_select(addr_t 	ad, 
+                              addr_t* 	victim, 
+                              size_t*   way, 
+                              size_t*   set)
+    {
+        bool   found   = false;
+        bool   cleanup = false;
+
+        *set = m_y[ad];
+        *way = 0;
+
+        // Search first empty slot 
+        for ( size_t _way = 0 ; _way < m_ways && !found ; _way++ )
+        {
+            if ( cache_state(_way, *set) != CACHE_SLOT_STATE_VALID )  // empty
+            {
+                found   = true;
+                cleanup = false;
+                *way    = _way;
+            }
+        }
+
+        // If no empty slot, search first  old slot (lru == false) 
+        if ( !found )
+        { 
+            for ( size_t _way = 0 ; _way < m_ways && !found ; _way++ )
+            {
+                if ( not cache_lru(_way, *set) )
+                {
+                    found   = true;
+                    cleanup = true;
+                    *way    = _way;
+                }
+            }
+        }
+
+        assert(found && "all ways can't be new at the same time");
+        *victim = (addr_t)((cache_tag(*way,*set) * m_sets) + *set);
+        return cleanup;
+    }
+
+    //////////////////////////////////////////////////////////////////////////////////
+    // This function selects a victim slot in an associative set.
+    // It can fail if all ways are in ZOMBI state.
+    // - we search first an EMPTY slot
+    // - if no empty slot, we search an OLD slot not in ZOMBI state,
+    // - if not found, we take the first not ZOMBI slot.
+    // It returns the line index (Z + Y fields), the selected slot way and set, 
+    // and two Boolean indicating success and a required cleanup.
+    //////////////////////////////////////////////////////////////////////////////////
+    inline void read_select(addr_t 	  ad, 
+                            addr_t*   victim, 
+                            size_t*   way, 
+                            size_t*   set,
+                            bool*     found,
+                            bool*     cleanup )
+    {
+        size_t _set = m_y[ad];
+
+        *found = false;
+
+        // Search first empty slot 
+        for ( size_t _way = 0 ; _way < m_ways && !(*found) ; _way++ )
+        {
+            if ( cache_state(_way, _set) == CACHE_SLOT_STATE_EMPTY )
+            {
+                *found   = true;
+                *cleanup = false;
+                *way     = _way;
+                *set     = m_y[ad];
+                return;
+            }
+        }
+        // Search first not zombi old slot 
+        for ( size_t _way = 0 ; _way < m_ways && !(*found) ; _way++ )
+        {
+            if ( not cache_lru(_way, _set) and 
+                 (cache_state(_way, _set) != CACHE_SLOT_STATE_ZOMBI) )
+            {
+                *found   = true;
+                *cleanup = true;
+                *way     = _way;
+                *set     = m_y[ad];
+                *victim  = (addr_t)((cache_tag(*way,_set) * m_sets) + _set);
+                return;
+            }
+        }
+        // Search first not zombi slot
+        for ( size_t _way = 0 ; _way < m_ways && !(*found) ; _way++ )
+        {
+            if ( cache_state(_way, _set) != CACHE_SLOT_STATE_ZOMBI) 
+            {
+                *found   = true;
+                *cleanup = true;
+                *way    = _way;
+                *set     = m_y[ad];
+                *victim  = (addr_t)((cache_tag(*way,_set) * m_sets) + _set);
+                return;
+            }
+        }
+
+        // no slot found...
+        *found   = false;
+        *cleanup = false;
+    }
+
+    //////////////////////////////////////////////////////////////////
+    // This function update the directory part of a slot
+    // identified by the way & set.
+    //////////////////////////////////////////////////////////////////
+    inline void victim_update_tag( addr_t 	ad, 
+                                   size_t 	way, 
+                                   size_t 	set )
+    {
+        tag_t  tag     = m_z[ad];
+
+        cache_tag(way, set)   = tag;
+        cache_state(way, set) = CACHE_SLOT_STATE_VALID;
+        cache_set_lru(way, set);
+    }
+
+    //////////////////////////////////////////////////////////////////
+    // This function write the directory part of a slot
+    // identified by the way & set, when using the ZOMBI state.
+    //////////////////////////////////////////////////////////////////
+    inline void write_dir( addr_t 	ad, 
+                           size_t 	way, 
+                           size_t 	set,
+                           int      state)
+    {
+        tag_t  tag     = m_z[ad];
+
+        assert( ( (state == CACHE_SLOT_STATE_VALID) or 
+                  (state == CACHE_SLOT_STATE_ZOMBI) or
+                  (state == CACHE_SLOT_STATE_EMPTY) ) and
+        "illegal slot state argument in Generic Cache write_dir()");
+
+        assert( (way < m_ways) and
+        "too large way index argument in Generic Cache write_dir()");
+
+        assert( (set < m_sets) and
+        "too large set index argument in Generic Cache write_dir()");
+
+        cache_tag(way, set)   = tag;
+        cache_state(way, set) = state;
+
+        if ( state == CACHE_SLOT_STATE_VALID ) cache_set_lru(way, set);
+    }
+
+    //////////////////////////////////////////////////////////////////
+    // This function write the directory part of a slot
+    // identified by the way & set, when using the ZOMBI state.
+    // Does not affect the tag
+    //////////////////////////////////////////////////////////////////
+    inline void write_dir( size_t 	way, 
+                           size_t 	set,
+                           int      state)
+    {
+        assert( ( (state == CACHE_SLOT_STATE_VALID) or 
+                  (state == CACHE_SLOT_STATE_ZOMBI) or
+                  (state == CACHE_SLOT_STATE_EMPTY) ) and
+        "illegal slot state argument in Generic Cache write_dir()");
+
+        assert( (way < m_ways) and
+        "too large way index argument in Generic Cache write_dir()");
+
+        assert( (set < m_sets) and
+        "too large set index argument in Generic Cache write_dir()");
+
+        cache_state(way, set) = state;
+
+        if ( state == CACHE_SLOT_STATE_VALID ) cache_set_lru(way, set);
+    }
+
+    ///////////////////////////////////////////////////////////////////
+    // This function writes a full cache line in one single cycle.
+    // The target slot is identified by the way & set arguments.
+    // Both DATA and DIRECTORY are written
+    ///////////////////////////////////////////////////////////////////
+    inline void update(addr_t 	ad, 
+                       size_t 	way, 
+                       size_t 	set, 
+                       data_t* 	buf)
+    {
+        tag_t tag = m_z[ad];
+
+        cache_tag(way, set)   = tag;
+        cache_state(way, set) = CACHE_SLOT_STATE_VALID;
+        cache_set_lru(way, set);
+        for ( size_t word = 0 ; word < m_words ; word++ ) 
+        {
+            cache_data(way, set, word) = buf[word] ;
+        }
+    }
+
+    ///////////////////////////
+    void fileTrace(FILE* file)
+    {
+        for( size_t nway = 0 ; nway < m_ways ; nway++) 
+        {
+            for( size_t nset = 0 ; nset < m_sets ; nset++) 
+            {
+                fprintf(file, "%d / ", (int)cache_state(nway, nset));
+                fprintf(file, "way %d / ", (int)nway);
+                fprintf(file, "set %d / ", (int)nset);
+                fprintf(file, "@ = %08zX / ", 
+                        ((cache_tag(nway, nset)*m_sets+nset)*m_words*4));
+                for( size_t nword = m_words ; nword > 0 ; nword--) 
+                {
+                    unsigned int data = cache_data(nway, nset, nword-1);
+                    fprintf(file, "%08X ", data );
+                }
+                fprintf(file, "\n");
+            }
+        }
+    }
+
+    ////////////////////////
+    inline void printTrace()
+    {
+        for ( size_t way = 0; way < m_ways ; way++ ) 
+        {
+            for ( size_t set = 0 ; set < m_sets ; set++ )
+            {
+                std::cout << std::dec << cache_state(way, set) << " | " ;
+                std::cout << "way " << way << " | " ;
+                std::cout << "set " << set << std::hex << " | " ;
+                std::cout << "@ " << (cache_tag(way,set)*m_words*m_sets+m_words*set)*4 ;
+                for ( size_t word = 0 ; word < m_words ; word++ )
+                {
+                    std::cout << " | " << cache_data(way,set,word) ;
+                }
+                std::cout << std::endl ;
+            }
+        }
+    }
+
+    ///////////////////////////////////////////////////////////////////////////
+    // This function is deprecated as it is difficult to implement in 1 cycle.
+    ///////////////////////////////////////////////////////////////////////////
+    __attribute__((deprecated))
+    inline bool inval(addr_t 	ad)
+    {
+        bool              hit = false;
+        const tag_t       tag = m_z[ad];
+        const size_t      set = m_y[ad];
+
+        for ( size_t way = 0 ; way < m_ways && !hit ; way++ ) 
+        {
+            if ( (tag == cache_tag(way, set)) and
+                 (cache_state(way, set) == CACHE_SLOT_STATE_VALID) ) 
+            {
+                hit                   = true;
+                cache_state(way, set) = CACHE_SLOT_STATE_EMPTY;
+                cache_lru(way, set)   = false;
+            }
+        }
+        return hit;
+    }
+
+    ////////////////////////////////////////////////////////////////////////////////
+    // This function is deprecated as it is difficult to implement in 1 cycle.
+    ////////////////////////////////////////////////////////////////////////////////
+    __attribute__((deprecated))
+    inline bool inval( addr_t 	ad, 
+                       size_t* 	selway, 
+                       size_t* 	selset )
+    {
+        bool    	hit = false;
+        const tag_t     tag = m_z[ad];
+        const size_t    set = m_y[ad];
+
+        for ( size_t way = 0 ; way < m_ways && !hit ; way++ ) 
+        {
+            if ( (tag == cache_tag(way, set)) and 
+                 (cache_state(way, set) == CACHE_SLOT_STATE_VALID) ) 
+            {
+                hit                   = true;
+                cache_state(way, set) = CACHE_SLOT_STATE_EMPTY;
+                cache_lru(way, set)   = false;
+                *selway             = way;
+                *selset             = set;
+            }
+        }
+        return hit;
+    }
+
+    ////////////////////////////////////////////////////////////////////////////////
+    // This function is deprecated as the directory must be a dual port RAM...
+    ////////////////////////////////////////////////////////////////////////////////
+    __attribute__((deprecated))
+    inline bool update( addr_t 	ad, 
+                        data_t* buf, 
+                        addr_t* victim )
+    {
+        size_t set, way;
+        bool   cleanup = victim_select(ad, victim, &way, &set);
+        victim_update_tag (ad, way, set);
+
+        for ( size_t word = 0 ; word < m_words ; word++ ) {
+            cache_data(way, set, word) = buf[word] ;
+        }
+
+        return cleanup;
+    }
+
+    ////////////////////////////////////////////////////////////////////////////
+    // this function is deprecated, as it is difficult to implement in 1 cycle. 
+    ////////////////////////////////////////////////////////////////////////////
+    __attribute__((deprecated))
+    inline bool write(addr_t 	ad, 
+                      data_t 	dt)
+    {
+        const tag_t       tag  = m_z[ad];
+        const size_t      set  = m_y[ad];
+        const size_t      word = m_x[ad];
+
+        for ( size_t way = 0; way < m_ways; way++ ) 
+        {
+            if ( (tag == cache_tag(way, set)) and
+                 (cache_state(way, set) == CACHE_SLOT_STATE_VALID) ) 
+            {
+                cache_data(way, set, word) = dt;
+                cache_set_lru(way, set);
+                return true;
+            }
+        }
+        return false;
+    }
+
+    ////////////////////////////////////////////////////////////////////////////
+    // this function is deprecated, as it is difficult to implement in 1 cycle. 
+    ////////////////////////////////////////////////////////////////////////////
+    __attribute__((deprecated))
+    inline bool write(addr_t 	ad, 
+                      data_t 	dt, 
+                      be_t 	be)
+    {
+        tag_t       tag  = m_z[ad];
+        const size_t      set  = m_y[ad];
+        const size_t      word = m_x[ad];
+
+        for ( size_t way = 0; way < m_ways; way++ ) 
+        {
+            if ( (tag == cache_tag(way, set)) and 
+                 (cache_state(way, set) == CACHE_SLOT_STATE_VALID) ) 
+            {
+                data_t mask = be2mask(be);
+                data_t prev = cache_data(way, set, word);
+                cache_data(way, set, word) = (mask & dt) | (~mask & prev);
+                cache_set_lru(way, set);
+                return true;
+            }
+        }
+        return false;
+    }
+    
+    /////////////////////////////////////////////////////////////////////////////
+    // this function is deprecated, as it is difficult to implement in 1 cycle. 
+    /////////////////////////////////////////////////////////////////////////////
+    __attribute__((deprecated))
+    inline bool write(addr_t 	ad, 
+                      data_t 	dt, 
+                      size_t* 	nway)
+    {
+        const tag_t       tag  = m_z[ad];
+        const size_t      set  = m_y[ad];
+        const size_t      word = m_x[ad];
+
+        for ( size_t way = 0; way < m_ways; way++ ) 
+        {
+            if ( (tag == cache_tag(way, set)) and
+                 (cache_state(way, set) == CACHE_SLOT_STATE_VALID) ) 
+            {
+                cache_data(way, set, word) = dt;
+                cache_set_lru(way, set);
+                *nway = way;
+                return true;
+            }
+        }
+        return false;
+    }
+
+    /////////////////////////////////////////////////////////////////////////////
+    // this function is deprecated, as it is difficult to implement in 1 cycle. 
+    /////////////////////////////////////////////////////////////////////////////
+    __attribute__((deprecated))
+    inline bool write(addr_t 	ad, 
+                      data_t 	dt, 
+                      size_t* 	nway, 
+                      be_t 	be)
+    {
+        const tag_t       tag  = m_z[ad];
+        const size_t      set  = m_y[ad];
+        const size_t      word = m_x[ad];
+
+        for ( size_t way = 0; way < m_ways; way++ ) 
+        {
+            if ( (tag == cache_tag(way, set)) and 
+                 (cache_state(way, set) == CACHE_SLOT_STATE_VALID) ) 
+            {
+                data_t mask = be2mask(be);
+                data_t prev = cache_data(way, set, word);
+                cache_data(way, set, word) = (mask & dt) | (~mask & prev);
+                cache_set_lru(way, set);
+                *nway = way;
+                return true;
+            }
+        }
+        return false;
+    }
+    
+};
+
+} // namespace soclib
+
+#endif
+
+// Local Variables:
+// tab-width: 4
+// c-basic-offset: 4
+// c-file-offsets:((innamespace . 0)(inline-open . 0))
+// indent-tabs-mode: nil
+// End:
+
+// vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4
+
Index: branches/v4/lib/generic_cache_tsar/metadata/generic_cache.sd
===================================================================
--- branches/v4/lib/generic_cache_tsar/metadata/generic_cache.sd	(revision 371)
+++ branches/v4/lib/generic_cache_tsar/metadata/generic_cache.sd	(revision 371)
@@ -0,0 +1,15 @@
+
+# -*- python -*-
+
+__version__ = "$Revision: 917 $"
+
+Module('caba:generic_cache_tsar',
+	classname = 'soclib::GenericCache',
+	header_files = ['../include/generic_cache.h',],
+	   tmpl_parameters = [
+	parameter.Type('addr_t'),
+	],
+	uses = [Uses('common:mapping_table'),
+			Uses('common:address_masking_table',
+				 data_t = parameter.Reference('addr_t')),],
+)
Index: branches/v4/lib/generic_llsc_global_table/include/generic_llsc_global_table.h
===================================================================
--- branches/v4/lib/generic_llsc_global_table/include/generic_llsc_global_table.h	(revision 371)
+++ branches/v4/lib/generic_llsc_global_table/include/generic_llsc_global_table.h	(revision 371)
@@ -0,0 +1,504 @@
+/* -*- c++ -*-
+ *
+ * SOCLIB_LGPL_HEADER_BEGIN
+ *
+ * This file is part of SoCLib, GNU LGPLv2.1.
+ *
+ * SoCLib is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU Lesser General Public License as published
+ * by the Free Software Foundation; version 2.1 of the License.
+ *
+ * SoCLib is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with SoCLib; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301 USA
+ *
+ * SOCLIB_LGPL_HEADER_END
+ *
+ * Alexandre JOANNOU <alexandre.joannou@lip6.fr>
+ *
+ */
+
+#ifndef SOCLIB_GENERIC_LLSC_GLOBAL_TABLE_H
+#define SOCLIB_GENERIC_LLSC_GLOBAL_TABLE_H
+
+#include <systemc>
+#include <arithmetics.h>
+#include <cassert>
+#include <cstring>
+#include <cmath>
+#include <iostream>
+#include <iomanip>
+
+namespace soclib
+{
+
+//////////////////////////
+//TODO switch to this
+/*
+template
+<
+size_t          nb_slots,   // max number of concerned shared resources
+typename        key_t,      // key type => max number of key; TODO wich one ?
+unsigned int    t_network,  // max number of cycle spent in the network when responding to a client (or more)
+unsigned int    t_inter_op, // min number of cycle between 2 reservation operation (or less but > 0)
+typename        addr_t      // ressource identifier type
+>
+*/
+template
+<
+size_t          nb_slots,   // desired number of slots
+unsigned int    nb_procs,   // number of processors in the system
+unsigned int    life_span,  // registratioÃ§n life span (in # of LL operations)
+typename        addr_t      // address type
+>
+class GenericLLSCGlobalTable
+////////////////////////////
+{
+    private :
+
+    const std::string           name              ; // component name
+
+    uint32_t                    r_key  [nb_slots] ; // array of key
+    addr_t                      r_addr [nb_slots] ; // array of addresses
+    bool                        r_val  [nb_slots] ; // array of valid bits
+
+    uint32_t                    r_next_key        ; // value of the next key
+    sc_dt::sc_uint<nb_slots>    r_block_mask      ; // mask for the slots blocks
+    sc_dt::sc_uint<nb_slots>    r_last_counter    ; // mask for the slots blocks
+    size_t                      r_write_ptr       ; // index of next slot to replace
+    size_t                      r_last_empty      ; // index of last empty slot used
+
+    uint32_t                    m_cpt_evic        ; // number of eviction in the table
+    uint32_t                    m_cpt_ll          ; // number of ll accesses to the table
+    uint32_t                    m_cpt_ll_update   ; // number of ll accesses to the table that trigger an update TODO check that
+    uint32_t                    m_cpt_sc          ; // number of sc accesses to the table
+    uint32_t                    m_cpt_sc_success  ; // number of sc accesses to the table that are successful
+    uint32_t                    m_cpt_sw          ; // number of sw accesses to the table
+
+    ////////////////////////////////////////////////////////////////////////////
+    inline void upNextKey()
+    //  This function generates a new value for the next key
+    {
+        // generating a new key in r_next_key
+        r_next_key++;
+    }
+
+    ////////////////////////////////////////////////////////////////////////////
+    /*
+    inline void updateVictimSlot()
+    //  This function selects the next slot to be evicted
+    //  This is done by updating the value of r_write_ptr
+    {
+        // updates the position of the next slot to be replaced
+
+        static unsigned int count = 0;
+
+
+        // for each slot, check if it actually is the slot to replace
+        // this is done by checking count % 2^(i+1) == (2^i)-1
+        // 2^(i+1) being the period
+        // (2^i)-1 being the first apparition
+        // NB : the -1 in (2^i)-1 is here because of the 0 indexed array
+
+        for (size_t i = 0 ; i < nb_slots; i++)
+            if (count % (int)pow(2,i+1) == pow(2,i)-1)
+                r_write_ptr = i;
+
+        count = (count + 1) % (int) pow(2,nb_slots);    // mustn't go further than 2^nb_slots
+                                                        // or (2^nb_slots)+1 for a 1 indexed array
+                                                        // 2^32 = periodicity of slot #31
+    }
+    */
+    ////////////////////////////////////////////////////////////////////////////
+    inline void updateVictimSlot()
+    //  This function selects the next slot to be evicted
+    //  This is done by updating the value of r_write_ptr
+    {
+        sc_dt::sc_uint<nb_slots> new_counter;
+        sc_dt::sc_uint<nb_slots> xor_counter;
+
+        new_counter = newCounter(r_block_mask, r_last_counter);
+        xor_counter = new_counter ^ r_last_counter;
+
+        for (size_t i = nb_slots - 1; i >= 0; --i)
+        {
+            if(xor_counter[i])
+            {
+                r_write_ptr = i;
+                break;
+            }
+        }
+
+        r_last_counter = new_counter;
+    }
+
+    ////////////////////////////////////////////////////////////////////////////
+    inline sc_dt::sc_uint<nb_slots> newCounter(const sc_dt::sc_uint<nb_slots>& mask,
+                                               const sc_dt::sc_uint<nb_slots>& counter)
+    // This function generates the new counter //TODO comment more
+    {
+        //
+        return ((((~counter) & (counter << 1)) & mask) | (counter + 1));
+    }
+
+    ////////////////////////////////////////////////////////////////////////////
+    inline void init_block_mask()
+    //TODO
+    //This function selects the block mask to be used
+    //Need to provide another way to do that ?
+    {
+        /*
+        //try to dynamically compute the block mask ...
+        #define L2 soclib::common::uint32_log2
+        unsigned int budget = nb_slots - (L2(nb_procs) + 1); //TODO +1?
+        #undef L2
+        */
+
+        switch(nb_slots)
+        {
+            case 12:
+            r_block_mask = sc_dt::sc_uint<nb_slots>("0x000");
+            break;
+            case 16 :
+            r_block_mask = sc_dt::sc_uint<nb_slots>("0xA800");
+            break;
+            case 20 :
+            r_block_mask = sc_dt::sc_uint<nb_slots>("0xD5500");
+            break;
+            case 24 :
+            r_block_mask = sc_dt::sc_uint<nb_slots>("0xDB5540");
+            break;
+            case 28 :
+            r_block_mask = sc_dt::sc_uint<nb_slots>("0xEEDAAA0");
+            break;
+            case 32 :
+            r_block_mask = sc_dt::sc_uint<nb_slots>("0xF776D550");
+            break;
+            case 36 :
+            r_block_mask = sc_dt::sc_uint<nb_slots>("0xFBDDDB550");
+            break;
+            case 40 :
+            r_block_mask = sc_dt::sc_uint<nb_slots>("0xFDF7BB6D50");
+            break;
+            case 44 :
+            r_block_mask = sc_dt::sc_uint<nb_slots>("0xFEFBDEEDAA8");
+            break;
+            case 48 :
+            r_block_mask = sc_dt::sc_uint<nb_slots>("0xFF7EFBDDDAA8");
+            break;
+            case 52 :
+            r_block_mask = sc_dt::sc_uint<nb_slots>("0xFFBFBF7BBB6A8");
+            break;
+            case 56 :
+            r_block_mask = sc_dt::sc_uint<nb_slots>("0xFFDFEFDF7BB6A8");
+            break;
+            case 60 :
+            r_block_mask = sc_dt::sc_uint<nb_slots>("0xFFF7FDFDF7BB6A8");
+            break;
+            case 64 :
+            r_block_mask = sc_dt::sc_uint<nb_slots>("0xFFFBFF7FBF7BB6A8");
+            break;
+            default:
+            assert(false && "nb_slots must be either 12, 16, 20, 24, 28, 32, 36, 40, 44, 48, 52, 56, 60 or 64");
+        }
+    }
+
+    ////////////////////////////////////////////////////////////////////////////
+    inline int nextEmptySlot()
+    //  This function returns :
+    //  - the position of the first next empty slot in the table
+    //    (starting from the last empty slot used)
+    //    and updates the r_last_empty_slot register
+    //  - -1 if the table is full
+    {
+        size_t i = r_last_empty;
+        do
+        {
+            // checking if current slot is empty
+            if(!r_val[i])
+            {
+                // updating last empty slot and returning its position
+                r_last_empty = i;
+                return i;
+            }
+            // selecting next slot
+            i = (i+1) % nb_slots;
+        }
+        // stop if all slots have been tested
+        while(i != r_last_empty);
+
+        // the table is full
+        return -1;
+    }
+
+    ////////////////////////////////////////////////////////////////////////////
+    inline int hitAddr(const addr_t ad)
+    //  HIT on the address only
+    //  This function takes an addr_t ad
+    //  It returns :
+    //  - the position of the first HIT in the table
+    //  - -1 in case of MISS
+    //  NB : HIT = (slot addr == ad) AND (slot is valid)
+    {
+        // checking all slots
+        for (size_t i = 0; i < nb_slots; i++)
+        {
+            // if HIT, returning its position
+            if(ad == r_addr[i] && r_val[i]) return i;
+        }
+
+        // MISS
+        return -1;
+    }
+
+    ////////////////////////////////////////////////////////////////////////////
+    inline int hitAddrKey(const addr_t ad, const uint32_t key)
+    //  HIT on the address AND the on the signature
+    //  This function takes an addr_t ad and a uint32_t key
+    //  It returns :
+    //  - the position of the first HIT in the table
+    //  - -1 in case of MISS
+    //  NB : HIT = (slot addr == ad) AND (slot key == key)
+    //                               AND (slot is valid)
+    {
+        // checking all slots
+        for (size_t i = 0; i < nb_slots; i++)
+        {
+            // if HIT, returning its position
+            if(ad == r_addr[i] && key == r_key[i] && r_val[i]) return i;
+        }
+
+        // MISS
+        return -1;
+    }
+
+    ////////////////////////////////////////////////////////////////////////////
+    inline void reset()
+    {
+        // init the table
+        init();
+
+        // init stat counters
+        m_cpt_evic          = 0;
+        m_cpt_ll            = 0;
+        m_cpt_ll_update     = 0;
+        m_cpt_sc            = 0;
+        m_cpt_sc_success    = 0;
+        m_cpt_sw            = 0;
+    }
+
+
+    public:
+
+    ////////////////////////////////////////////////////////////////////////////
+    GenericLLSCGlobalTable( const std::string   &n = "llsc_global_table" )
+    :   name(n)
+    {
+        #define L2 soclib::common::uint32_log2
+        assert(nb_procs > 1); //nb_procs must be more than 1
+        //TODO >= or > ?
+        assert(nb_slots >= L2(nb_procs)); // nb_slot cannot be less then log2(nb_procs)
+        #undef L2
+        init();
+        init_block_mask();
+    }
+
+    ////////////////////////////////////////////////////////////////////////////
+    ~GenericLLSCGlobalTable()
+    {
+    }
+
+    ////////////////////////////////////////////////////////////////////////////
+    //  This function initializes the table (all slots empty)
+    inline void init()
+    {
+        // making all slots available by reseting all valid bits
+        std::memset(r_val, 0, sizeof(*r_val)*nb_slots);
+
+        // init registers
+        r_next_key          = 0;
+        r_last_counter      = 0; //TODO static in updateVictimSlot() ?
+        r_write_ptr         = 0;
+        r_last_empty        = 0;
+    }
+
+    ////////////////////////////////////////////////////////////////////////////
+    inline uint32_t ll(const addr_t ad)
+    //  This method registers an LL in the table and returns the key associated
+    //  with the registration
+    {
+        // increment the ll access counter (for stats)
+        m_cpt_ll++;
+
+        // hit addr ?
+        // YES
+        //      enough time left ?
+        //      YES
+        //          use this registration, return key
+        //      NO
+        //          update this registration with a new key, return new key
+        // NO
+        //      table has an empty slot ?
+        //      YES
+        //              select empty slot
+        //      NO
+        //              select victim slot (r_write_ptr)
+        //              update next victim
+        //      open registration on selected slot
+        //      update next key
+        //      return the registration key
+
+        //  Is the address found in the table ?
+        int pos = hitAddr(ad);
+
+        //  Yes, then return the associated key
+        if (pos >= 0)
+        {
+            if(r_key[pos] - r_next_key > life_span)
+                return r_key[pos];
+            r_key[pos] = r_next_key;
+            upNextKey();
+            m_cpt_ll_update++;
+            return r_key[pos];
+        }
+
+        //  No, then try to find an empty slot
+        pos = nextEmptySlot();
+
+        //  If there is no empty slot,
+        //  evict an existing registration
+        if (pos == -1)
+        {
+            //  get the position of the evicted registration
+            pos = r_write_ptr;
+            //  update the victim slot for the next eviction
+            updateVictimSlot();
+            // increment the eviction counter (for stats)
+            m_cpt_evic++;
+        }
+
+        // get the key for the new registration
+        uint32_t key    = r_next_key;
+        //  update the registration slot
+        r_key[pos]      = key   ;
+        r_addr[pos]     = ad    ;
+        r_val[pos]      = true  ;
+        //  compute the next key
+        upNextKey();
+
+        // return the key of the new registration
+        return key;
+
+    }
+
+    ////////////////////////////////////////////////////////////////////////////
+    inline bool sc(const addr_t ad, const uint32_t key)
+    //  This method checks if there is a valid registration for the SC (ad &&
+    //  key) and, in case of hit,invalidates the registration and returns true
+    //  (returns false otherwise)
+    //
+    //  The return value can be used to tell if the SC is atomic
+    {
+        // increment the sc access counter (for stats)
+        m_cpt_sc++;
+        // hit addr && hit key ?
+        // NO
+        //      return miss
+        // YES
+        //      inval registration and return hit
+
+        //  Is there a valid registration in the table ?
+        int pos = hitAddrKey(ad, key);
+        if(pos >= 0)
+        {
+            // increment the sc success counter (for stats)
+            m_cpt_sc_success++;
+            // invalidate the registration
+            r_val[pos] = false;
+            // return the success of the sc operation
+            return true;
+        }
+        else
+        {
+            // return the failure of the sc operation
+            return false;
+        }
+    }
+
+    ////////////////////////////////////////////////////////////////////////////
+    inline void sw(const addr_t ad)
+    //  This method checks if there is a valid registration for the given
+    //  address and, in case of hit, invalidates the registration
+    {
+        // increment the sw access counter (for stats)
+        m_cpt_sw++;
+        // hit addr ?
+        // YES
+        //      inval registration
+        // NO
+        //      nothing
+
+        //  Is there a registration for the given address ?
+        int pos = hitAddr(ad);
+        //  If there is one, invalidate it
+        if(pos >= 0) r_val[pos] = false;
+
+    }
+
+    ////////////////////////////////////////////////////////////////////////////
+    /*
+    void fileTrace(FILE* file)
+    {
+    }
+    */
+
+    ////////////////////////////////////////////////////////////////////////////
+    inline void print_trace(std::ostream& out = std::cout)
+    {
+        out <<  " ___________________________________" << std::endl
+            <<  "| " << std::setw(33) << "generic_llsc_global_table" << " |" << std::endl
+            <<  "| " << std::setw(33) << name << " |" << std::endl
+            <<  " ===================================" << std::endl
+            <<  "| "
+            <<  std::setw(11) << "addr"   << " | "
+            <<  std::setw(11) << "key"    << " | "
+            <<  std::setw(5)  << "val"
+            << " |" << std::endl
+            <<  " -----------------------------------" << std::endl;
+        for ( size_t i = 0; i < nb_slots ; i++ )
+        {
+            out << "| "
+                << std::showbase
+                << std::setw(11) << std::setfill('0')   << std::hex       << r_addr[i]    << " | "
+                << std::noshowbase
+                << std::setw(11) << std::setfill('0')   << std::dec       << r_key[i]     << " | "
+                << std::setw(5)  << std::setfill(' ')   << std::boolalpha << r_val[i]     << " |" << std::endl ;
+        }
+        out <<  " -----------------------------------" << std::endl
+            << std::noshowbase << std::dec << std::endl ;
+    }
+
+    ////////////////////////////////////////////////////////////////////////////
+    inline void print_stats(std::ostream& out = std::cout)
+    {
+        out << "# of ll accesses : " << m_cpt_ll            << std::endl
+            << "# of ll updates  : " << m_cpt_ll_update     << std::endl
+            << "# of sc accesses : " << m_cpt_sc            << std::endl
+            << "# of sc success  : " << m_cpt_sc_success    << std::endl
+            << "# of sw accesses : " << m_cpt_sw            << std::endl
+            << "# of evictions   : " << m_cpt_evic          << std::endl ;
+    }
+
+};
+
+} // end namespace soclib
+
+#endif
+
+// vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4
Index: branches/v4/lib/generic_llsc_global_table/metadata/generic_llsc_global_table.sd
===================================================================
--- branches/v4/lib/generic_llsc_global_table/metadata/generic_llsc_global_table.sd	(revision 371)
+++ branches/v4/lib/generic_llsc_global_table/metadata/generic_llsc_global_table.sd	(revision 371)
@@ -0,0 +1,13 @@
+# -*- python -*-
+
+Module(
+    'caba:generic_llsc_global_table',
+    classname       = 'soclib::GenericLLSCGlobalTable',
+    header_files    = ['../include/generic_llsc_global_table.h'],
+    tmpl_parameters = 
+        [
+            parameter.Int('nb_slots', min = 2, max = 64, default = 32),
+            parameter.Int('nb_procs', min = 2, max = 4096, default = 4095), # default should be 4096, but soclib-cc problem
+            parameter.Type('addr_t', default = 'sc_dt::sc_uint<40>')
+        ]
+)
Index: branches/v4/lib/generic_llsc_local_table/include/generic_llsc_local_table.h
===================================================================
--- branches/v4/lib/generic_llsc_local_table/include/generic_llsc_local_table.h	(revision 371)
+++ branches/v4/lib/generic_llsc_local_table/include/generic_llsc_local_table.h	(revision 371)
@@ -0,0 +1,504 @@
+/* -*- c++ -*-
+ *
+ * SOCLIB_LGPL_HEADER_BEGIN
+ *
+ * This file is part of SoCLib, GNU LGPLv2.1.
+ *
+ * SoCLib is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU Lesser General Public License as published
+ * by the Free Software Foundation; version 2.1 of the License.
+ *
+ * SoCLib is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with SoCLib; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301 USA
+ *
+ * SOCLIB_LGPL_HEADER_END
+ *
+ * Alexandre JOANNOU <alexandre.joannou@lip6.fr>
+ *
+ */
+
+#ifndef SOCLIB_GENERIC_LLSC_LOCAL_TABLE_H
+#define SOCLIB_GENERIC_LLSC_LOCAL_TABLE_H
+
+#include <systemc>
+#include <cassert>
+#include <cstring>
+#include <iostream>
+#include <iomanip>
+
+namespace soclib {
+
+//////////////////////////
+//TODO switch to this
+/*
+template
+<
+size_t          nb_slots,   // max number of authorized atomic operation per agent
+typename        key_t,      // key type => max number of key; TODO wich one ?
+unsigned int    t_network,  // max number of cycle spent in the network when responding to a client (or more)
+unsigned int    t_inter_op, // min number of cycle between 2 reservation operation (or less but > 0)
+typename        addr_t      // ressource identifier type
+>
+*/
+template
+<
+uint32_t    life_span               ,   // desired life-span for a reservation
+size_t      nb_slots    = 1         ,   // desired number of reservation
+typename    addr_t      = uint32_t  ,   // ressource identifier type
+typename    index_t     = size_t    ,   // transaction index/identifier type (trdid size)
+typename    key_t       = uint32_t      // key identifier type
+>
+class GenericLLSCLocalTable
+///////////////////////////
+{
+    public:
+
+    // command type
+    enum cmd_t
+    {
+        LL_CMD  = 0x8,  // create a reservation in the table (to be called when an ll cmd is emited)
+        LL_RSP  = 0x4,  // updates a reservation in the table (to be called when an ll rsp is received)
+        SC_CMD  = 0x2,  // invalidate a reservation (if necessary) and reset the wait register
+        SW_CMD  = 0x1,  // invalidate a reservation (if necessary)
+        NOP     = 0x0   // no operation (internal updates only : aging counters)
+    };
+
+    struct in_t
+    {
+        addr_t  address ;   // the address  argument of the command
+        index_t index   ;   // the index    argument of the command
+        key_t   key     ;   // the key      argument of the command
+        cmd_t   cmd     ;   // the command for the table to execute
+    };
+
+    struct out_t
+    {
+        bool    done    ;   // true if operation was actually performed
+        bool    hit     ;   // true if there was a hit on the address
+        key_t   key     ;   // the matching key for an SC_CMD
+        index_t index   ;   // the index of the reservation for a LL_CMD
+    };
+
+    private :
+
+    const std::string           name                ;   // component name
+
+    addr_t                      r_addr  [nb_slots]  ;   // array of addresses
+    key_t                       r_key   [nb_slots]  ;   // array of keys
+    uint32_t                    r_cnt   [nb_slots]  ;   // array of aging counters
+    bool                        r_val   [nb_slots]  ;   // array of valid bits
+
+    uint32_t                    r_wait              ;   // number of cycles to wait (when trying to perform a reservation)
+    uint32_t                    r_wait_cnt          ;   // counter counting down from r_wait to 0
+    size_t                      r_write_ptr         ;   // index of next slot to replace
+    size_t                      r_last_empty        ;   // index of last empty slot used
+
+    uint32_t                    m_cpt_ll_cmd        ;   // number of ll_cmd accesses to the table
+    uint32_t                    m_cpt_ll_cmd_done   ;   // number of ll_cmd accesses to the table (effectivelly done)
+    uint32_t                    m_cpt_ll_rsp        ;   // number of ll_rsp accesses to the table
+    uint32_t                    m_cpt_sc_cmd        ;   // number of sc_cmd accesses to the table
+    uint32_t                    m_cpt_sw_cmd        ;   // number of sw_cmd accesses to the table
+    uint32_t                    m_cpt_nop           ;   // number of nop    accesses to the table
+    uint32_t                    m_cpt_evic          ;   // number of eviction in the table
+    uint32_t                    m_cpt_death         ;   // number of death of reservations due to aging
+
+    ////////////////////////////////////////////////////////////////////////////
+    inline int hitAddr(const addr_t & address)
+    //  HIT on the address only
+    //  This function takes an addr_t address
+    //  It returns :
+    //  - the position of the first HIT in the table
+    //  - -1 in case of MISS
+    //  NB : HIT = (slot addr == ad) AND (slot is valid)
+    {
+        // checking all slots
+        for (size_t i = 0; i < nb_slots; i++)
+        {
+            // if HIT, returning its position
+            if(address == r_addr[i] && r_val[i]) return i;
+        }
+
+        // MISS
+        return -1;
+    }
+
+    ////////////////////////////////////////////////////////////////////////////
+    inline int nextEmptySlot()
+    //  This function returns :
+    //  - the position of the first next empty slot in the table
+    //    (starting from the last empty slot used)
+    //    and updates the r_last_empty_slot register
+    //  - -1 if the table is full
+    {
+        size_t i = r_last_empty;
+        do
+        {
+            // checking if current slot is empty
+            if(!r_val[i])
+            {
+                // updating last empty slot and returning its position
+                r_last_empty = i;
+                return i;
+            }
+            // selecting next slot
+            i = (i+1) % nb_slots;
+        }
+        // stop if all slots have been tested
+        while(i != r_last_empty);
+
+        // the table is full
+        return -1;
+    }
+
+    ////////////////////////////////////////////////////////////////////////////
+    inline void updateVictimSlot()
+    //  This function selects the next slot to be evicted
+    //  This is done by updating the value of r_write_ptr
+    {
+        r_write_ptr = 0;
+    }
+
+    public:
+
+    ////////////////////////////////////////////////////////////////////////////
+    GenericLLSCLocalTable(  const std::string    &n = "llsc_local_table" )
+    :   name(n)
+    {
+        init();
+    }
+
+    ////////////////////////////////////////////////////////////////////////////
+    ~GenericLLSCLocalTable()
+    {
+    }
+
+    ////////////////////////////////////////////////////////////////////////////
+    inline void init()
+    //  This function initializes the table (all slots empty)
+    {
+        // making all slots available by reseting all valid bits
+        std::memset(r_val, 0, sizeof(*r_val)*nb_slots);
+
+        // init registers
+        r_wait              = 0;
+        r_wait_cnt          = 0;
+        r_write_ptr         = 0;
+        r_last_empty        = 0;
+
+        // init stat counters
+        m_cpt_ll_cmd        = 0;
+        m_cpt_ll_cmd_done   = 0;
+        m_cpt_ll_rsp        = 0;
+        m_cpt_sc_cmd        = 0;
+        m_cpt_sw_cmd        = 0;
+        m_cpt_nop           = 0;
+        m_cpt_evic          = 0;
+        m_cpt_death         = 0;
+    }
+
+    ////////////////////////////////////////////////////////////////////////////
+    inline void exec(const in_t & in, out_t & out)
+    // This function has to be called every cycle !
+    // It implements the behaviour of the generic_llsc_local_table.
+    // 5 commands can be performed :
+    // - LL_CMD
+    // - LL_RSP
+    // - SC_CMD
+    // - SW_CMD
+    // - NOP
+    // Each one of them are described further below
+    {
+        // First check the command
+        switch(in.cmd)
+        {
+            case LL_CMD :
+            // INPUTS :
+            // - address
+            //
+            // Check if r_wait_cnt has reached 0
+            // - YES
+            //      - the wait counter is re initialized with the content of the
+            //        r_wait register
+            //      - the r_wait register is doubled (<< 1) (delay mechanism)
+            //      - check if there is an empty slot
+            //          if YES, select the empty slot
+            //          if NO, select victim slot and update next victim
+            //      - the address of the selected slot is initialized with the given
+            //        address
+            //      - the aging counter of the selected slot is initialized with
+            //        the life-span of a reservation
+            //      - the valid bit of the selected slot is set to true
+            //
+            //          - out.hit   <= don't care
+            //          - out.done  <= true
+            //          - out.key   <= don't care
+            //          - out.index <= i the index of the selected slot
+            //
+            // - NO
+            //      - decrement r_wait_cnt
+            //
+            //          - out.hit   <= don't care
+            //          - out.done  <= false
+            //          - out.key   <= don't care
+            //          - out.index <= don't care
+            {
+                // increment the ll_cmd access counter (for stats)
+                m_cpt_ll_cmd++;
+
+                if(r_wait_cnt == 0)
+                {
+                    // increment the ll_cmd access counter (effectivelly done) (for stats)
+                    m_cpt_ll_cmd_done++;
+
+                    // increase the lenght of the next waiting session
+                    //r_wait      = (r_wait << 1) + 1 ;
+                    // re initialize the wait counter //TODO check this...
+                    //r_wait_cnt  = r_wait;
+
+                    // select a slot for the reservation
+                    // first check for an empty slot ...
+                    int pos = nextEmptySlot();
+                    // If there is no empty slot,
+                    // evict an existing registration
+                    if (pos == -1)
+                    {
+                        // get the position of the evicted registration
+                        pos = r_write_ptr;
+                        // update the victim slot for the next eviction
+                        updateVictimSlot();
+                        // increment the eviction counter (for stats)
+                        m_cpt_evic++;
+                    }
+
+                    // inscription in the slot
+                    r_addr  [pos]   =   in.address  ;
+                    r_cnt   [pos]   =   life_span   ;
+                    r_val   [pos]   =   true        ;
+
+                    // construct out argument
+                    //out.hit   = don't care;
+                    out.done    = 1;
+                    //out.key   = don't care;
+                    out.index   = pos;
+                }
+                else
+                {
+                    // decrement the wait counter
+                    r_wait_cnt--;
+
+                    // construct out argument
+                    //out.hit   = don't care;
+                    out.done    = 0;
+                    //out.key   = don't care;
+                    //out.index = don't care;
+                }
+            }
+            break;
+            case LL_RSP :
+            // INPUTS :
+            // - index
+            // - key
+            //
+            //  - the key of the reservation is updated with the given key
+            //
+            //      - out.hit   <= don't care
+            //      - out.done  <= true
+            //      - out.key   <= don't care
+            //      - out.index <= don't care
+            {
+                // increment the ll_rsp access counter (for stats)
+                m_cpt_ll_rsp++;
+
+                // insert new key in reservation
+                r_key[in.index]  = in.key;
+
+                // construct out argument
+                out.hit     = 1;
+                out.done    = 1;
+                //out.key   = don't care;
+                //out.index = don't care;
+            }
+            break;
+            case SC_CMD :
+            // INPUTS :
+            // - address
+            //
+            // Check if there is a hit for the address
+            // - HIT
+            //      - invalidate reservation
+            //      - reset r_wait to 0
+            //
+            //          - out.hit   <= true
+            //          - out.done  <= true
+            //          - out.key   <= r_key[hit_index]
+            //          - out.index <= don't care
+            //
+            // - NO HIT
+            //
+            //      - out.hit   <= false
+            //      - out.done  <= true
+            //      - out.key   <= don't care
+            //      - out.index <= don't care
+            {
+                // increment the sc_cmd access counter (for stats)
+                m_cpt_sc_cmd++;
+
+                // Is there a valid reservation in the table ?
+                int pos = hitAddr(in.address);
+                if(pos >= 0)
+                {
+                    // invalidate reservation
+                    r_val[pos]  = false     ;
+                    // reset r_wait to 0
+                    r_wait      = 0         ;
+                    // construct out argument
+                    out.hit     = 1         ;
+                    out.done    = 1         ;
+                    out.key     = r_key[pos];
+                }
+                else
+                {
+                    // construct out argument
+                    out.hit     = 0;
+                    out.done    = 1;
+                    //out.key   = don't care;
+                    //out.index = don't care;
+                }
+            }
+            break;
+            case SW_CMD :
+            // INPUTS :
+            // - address
+            //
+            // Check if there is a hit for the address
+            // - HIT
+            //      - invalidate reservation
+            //
+            //          - out.hit   <= true
+            //          - out.done  <= true
+            //          - out.key   <= don't care
+            //          - out.index <= don't care
+            //
+            // - NO HIT
+            //
+            //      - out.hit   <= false
+            //      - out.done  <= true
+            //      - out.key   <= don't care
+            //      - out.index <= don't care
+            {
+                // increment the sw_cmd access counter (for stats)
+                m_cpt_sw_cmd++;
+
+                // Is there a valid reservation in the table ?
+                int pos = hitAddr(in.address);
+                if(pos >= 0)
+                {
+                    // invalidate reservation
+                    r_val[pos]  = false     ;
+                    // construct out argument
+                    out.hit     = 1         ;
+                    out.done    = 1         ;
+                    //out.key   = don't care ;
+                    //out.index = don't care;
+                }
+                else
+                {
+                    // construct out argument
+                    out.hit     = 0;
+                    out.done    = 1;
+                    //out.key   = don't care;
+                    //out.index = don't care;
+                }
+            }
+            break;
+            case NOP :
+            // NOTHING except for the usual aging counter updates
+            //
+            //      - out.hit   <= don't care
+            //      - out.done  <= 1
+            //      - out.key   <= don't care
+            //      - out.index <= don't care
+            {
+                // increment the nop access counter (for stats)
+                m_cpt_nop++;
+                // construct out argument
+                //out.hit   = don't care;
+                out.done    = 1;
+                //out.key   = don't care;
+                //out.index = don't care;
+            }
+            break;
+        }
+        // aging counters ...
+        // for each slot
+        for (size_t i = 0; i < nb_slots; i++)
+        {
+            // decrement the counter
+            r_cnt[i]--;
+            // check if the counter has reached 0 (for an actual reservation,
+            // i.e. a valid reservation)
+            if(r_cnt[i] == 0 && r_val[i])
+            {
+                // increment the death counter (for stats)
+                m_cpt_death++;
+                // invalidate the reservation
+                r_val[i] = false;
+            }
+        }
+    }
+
+    ////////////////////////////////////////////////////////////////////////////
+    inline void print_trace(std::ostream& out = std::cout)
+    {
+        out <<  " _________________________________________________" << std::endl
+            <<  "| " << std::setw(47) << "generic_llsc_local_table" << " |" << std::endl
+            <<  "| " << std::setw(47) << name << " |" << std::endl
+            <<  " =================================================" << std::endl
+            <<  "| "
+            <<  std::setw(11) << "addr"   << " | "
+            <<  std::setw(11) << "key"    << " | "
+            <<  std::setw(11) << "cnt"    << " | "
+            <<  std::setw(5)  << "val"
+            << " |" << std::endl
+            <<  " -------------------------------------------------" << std::endl;
+        for ( size_t i = 0; i < nb_slots ; i++ )
+        {
+            out << "| "
+                << std::showbase
+                << std::setw(11) << std::setfill('0')   << std::hex       << r_addr[i]    << " | "
+                << std::noshowbase
+                << std::setw(11) << std::setfill('0')   << std::dec       << r_key[i]     << " | "
+                << std::setw(11) << std::setfill('0')   << std::dec       << r_cnt[i]     << " | "
+                << std::setw(5)  << std::setfill(' ')   << std::boolalpha << r_val[i]     << " |" << std::endl ;
+        }
+        out <<  " -------------------------------------------------" << std::endl
+            << std::noshowbase << std::dec << std::endl ;
+    }
+
+    ////////////////////////////////////////////////////////////////////////////
+    inline void print_stats(std::ostream& out = std::cout)
+    {
+        out << "# of ll_cmd accesses                     : " << m_cpt_ll_cmd        << std::endl
+            << "# of ll_cmd accesses (effectivelly done) : " << m_cpt_ll_cmd_done   << std::endl
+            << "# of ll_rsp accesses                     : " << m_cpt_ll_rsp        << std::endl
+            << "# of sc_cmd accesses                     : " << m_cpt_sc_cmd        << std::endl
+            << "# of sw_cmd accesses                     : " << m_cpt_sw_cmd        << std::endl
+            << "# of nop    accesses                     : " << m_cpt_nop           << std::endl
+            << "# of eviction                            : " << m_cpt_evic          << std::endl
+            << "# of death by aging                      : " << m_cpt_death         << std::endl ;
+    }
+
+};
+
+} // namespace soclib
+
+#endif
+
+// vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4
Index: branches/v4/lib/generic_llsc_local_table/metadata/generic_llsc_local_table.sd
===================================================================
--- branches/v4/lib/generic_llsc_local_table/metadata/generic_llsc_local_table.sd	(revision 371)
+++ branches/v4/lib/generic_llsc_local_table/metadata/generic_llsc_local_table.sd	(revision 371)
@@ -0,0 +1,12 @@
+# -*- python -*-
+
+Module(
+    'caba:generic_llsc_local_table',
+    classname       = 'soclib::GenericLLSCLocalTable',
+    header_files    = ['../include/generic_llsc_local_table.h'],
+    tmpl_parameters = 
+        [
+            parameter.Int('nb_slots', min = 1, max = 10, default = 1),
+            parameter.Type('addr_t', default = 'sc_dt::sc_uint<40>')
+        ]
+)
Index: branches/v4/modules/vci_block_device_tsar/caba/metadata/vci_block_device_tsar.sd
===================================================================
--- branches/v4/modules/vci_block_device_tsar/caba/metadata/vci_block_device_tsar.sd	(revision 371)
+++ branches/v4/modules/vci_block_device_tsar/caba/metadata/vci_block_device_tsar.sd	(revision 371)
@@ -0,0 +1,43 @@
+
+# -*- python -*-
+
+__id__ = "$Id$"
+__version__ = "$Revision$"
+
+Module('caba:vci_block_device_tsar',
+	   classname = 'soclib::caba::VciBlockDeviceTsar',
+	   tmpl_parameters = [
+	parameter.Module('vci_param',  default = 'caba:vci_param'),
+	],
+	   header_files = ['../source/include/vci_block_device_tsar.h',
+					],
+    interface_files = [
+					   '../../include/soclib/block_device_tsar.h'
+					   ],
+	   implementation_files = ['../source/src/vci_block_device_tsar.cpp',],
+	   ports = [
+	Port('caba:vci_target', 'p_vci_target'),
+	Port('caba:vci_initiator', 'p_vci_initiator'),
+	Port('caba:bit_out', 'p_irq'),
+	Port('caba:bit_in', 'p_resetn', auto = 'resetn'),
+	Port('caba:clock_in', 'p_clk', auto = 'clock'),
+	],
+	   uses = [
+	Uses('caba:base_module'),
+	Uses('caba:vci_target_fsm', default_target = 'true', support_llsc = 'false'),
+	Uses('caba:vci_initiator_simple_read_req'),
+	Uses('caba:vci_initiator_simple_write_req'),
+	Uses('caba:vci_initiator_fsm'),
+	],
+	instance_parameters = [
+        parameter.Module('mt', typename = 'common:mapping_table', auto = 'env:mapping_table'),
+        parameter.IntTab('srcid'),
+        parameter.IntTab('tgtid'),
+        parameter.String('filename'),
+        ],
+	   extensions = [
+	'dsx:addressable=tgtid',
+	'dsx:max_segments=1',
+	'dsx:get_ident=tgtid:p_vci_target:mt,srcid:p_vci_initiator:mt',
+   ],
+)
Index: branches/v4/modules/vci_block_device_tsar/caba/source/include/vci_block_device_tsar.h
===================================================================
--- branches/v4/modules/vci_block_device_tsar/caba/source/include/vci_block_device_tsar.h	(revision 371)
+++ branches/v4/modules/vci_block_device_tsar/caba/source/include/vci_block_device_tsar.h	(revision 371)
@@ -0,0 +1,115 @@
+/* -*- c++ -*-
+ *
+ * SOCLIB_LGPL_HEADER_BEGIN
+ * 
+ * This file is part of SoCLib, GNU LGPLv2.1.
+ * 
+ * SoCLib is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU Lesser General Public License as published
+ * by the Free Software Foundation; version 2.1 of the License.
+ * 
+ * SoCLib is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * Lesser General Public License for more details.
+ * 
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with SoCLib; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301 USA
+ * 
+ * SOCLIB_LGPL_HEADER_END
+ *
+ * Copyright (c) UPMC, Lip6, Asim
+ *         Nicolas Pouillon <nipo@ssji.net>, 2007
+ *         Eric Guthmuller  <eric.guthmuller@polytechnique.edu>
+ *
+ * Maintainers: nipo eric.guthmuller@polytechnique.edu
+ */
+#ifndef SOCLIB_VCI_BLOCK_DEVICE_TSAR_H
+#define SOCLIB_VCI_BLOCK_DEVICE_TSAR_H
+
+#include <stdint.h>
+#include <systemc>
+#include "vci_target_fsm.h"
+#include "vci_initiator_fsm.h"
+#include "caba_base_module.h"
+#include "mapping_table.h"
+
+namespace soclib {
+namespace caba {
+
+using namespace sc_core;
+
+template<typename vci_param>
+class VciBlockDeviceTsar
+	: public caba::BaseModule
+{
+private:
+    soclib::caba::VciTargetFsm<vci_param, true> m_vci_target_fsm;
+    soclib::caba::VciInitiatorFsm<vci_param> m_vci_init_fsm;
+    typedef typename soclib::caba::VciInitiatorReq<vci_param> req_t;
+
+    bool on_write(int seg, typename vci_param::addr_t addr, typename vci_param::data_t data, int be);
+    bool on_read(int seg, typename vci_param::addr_t addr, typename vci_param::data_t &data);
+    void read_done( req_t *req );
+    void write_finish( req_t *req );
+    void open_finish( req_t *req );
+    void next_req();
+    void transition();
+    void genMoore();
+
+	const uint32_t m_block_size;
+    const uint32_t m_burst_size;    // Maximum size of the burst
+
+	int m_fd;
+	int m_op;
+	uint32_t m_buffer;
+	uint32_t m_count;
+	uint64_t m_device_size;
+	uint32_t m_lba;
+    int m_status;
+    uint32_t m_chunck_offset;
+    uint32_t m_transfer_size;
+	bool m_irq_enabled;
+	bool r_irq;
+
+	int m_current_op;
+
+	uint8_t *m_data;
+
+	inline void ended(int status);
+
+protected:
+    SC_HAS_PROCESS(VciBlockDeviceTsar);
+
+public:
+    sc_in<bool> p_clk;
+    sc_in<bool> p_resetn;
+    soclib::caba::VciTarget<vci_param> p_vci_target;
+    soclib::caba::VciInitiator<vci_param> p_vci_initiator;
+    sc_out<bool> p_irq;
+
+	VciBlockDeviceTsar(
+		sc_module_name name,
+		const soclib::common::MappingTable &mt,
+		const soclib::common::IntTab &srcid,
+		const soclib::common::IntTab &tgtid,
+        const std::string &filename,
+        const uint32_t block_size = 512,
+        const uint32_t burst_size = 64);
+};
+
+}}
+
+#endif /* SOCLIB_VCI_BLOCK_DEVICE_TSAR_H */
+
+// Local Variables:
+// tab-width: 4
+// c-basic-offset: 4
+// c-file-offsets:((innamespace . 0)(inline-open . 0))
+// indent-tabs-mode: nil
+// End:
+
+// vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4
+
Index: branches/v4/modules/vci_block_device_tsar/caba/source/src/vci_block_device_tsar.cpp
===================================================================
--- branches/v4/modules/vci_block_device_tsar/caba/source/src/vci_block_device_tsar.cpp	(revision 371)
+++ branches/v4/modules/vci_block_device_tsar/caba/source/src/vci_block_device_tsar.cpp	(revision 371)
@@ -0,0 +1,366 @@
+/* -*- c++ -*-
+ *
+ * SOCLIB_LGPL_HEADER_BEGIN
+ * 
+ * This file is part of SoCLib, GNU LGPLv2.1.
+ * 
+ * SoCLib is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU Lesser General Public License as published
+ * by the Free Software Foundation; version 2.1 of the License.
+ * 
+ * SoCLib is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * Lesser General Public License for more details.
+ * 
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with SoCLib; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301 USA
+ * 
+ * SOCLIB_LGPL_HEADER_END
+ *
+ * Copyright (c) UPMC, Lip6, Asim
+ *         Nicolas Pouillon <nipo@ssji.net>, 2007
+ *         Eric Guthmuller  <eric.guthmuller@polytechnique.edu>, 2009
+ */
+
+#include <stdint.h>
+#include <iostream>
+#include "register.h"
+#include "../include/vci_block_device_tsar.h"
+#include <fcntl.h>
+#include "block_device_tsar.h"
+
+namespace soclib { namespace caba {
+
+#ifdef SOCLIB_MODULE_DEBUG
+    namespace {
+        const char* SoclibBlockDeviceRegisters_str[] = {
+            "BLOCK_DEVICE_BUFFER",
+            "BLOCK_DEVICE_LBA",
+            "BLOCK_DEVICE_COUNT",
+            "BLOCK_DEVICE_OP",
+            "BLOCK_DEVICE_STATUS",
+            "BLOCK_DEVICE_IRQ_ENABLE",
+            "BLOCK_DEVICE_SIZE",
+            "BLOCK_DEVICE_BLOCK_SIZE"
+        };
+        const char* SoclibBlockDeviceOp_str[] = {
+            "BLOCK_DEVICE_NOOP",
+            "BLOCK_DEVICE_READ",
+            "BLOCK_DEVICE_WRITE",
+        };
+        const char* SoclibBlockDeviceStatus_str[] = {
+            "BLOCK_DEVICE_IDLE",
+            "BLOCK_DEVICE_BUSY",
+            "BLOCK_DEVICE_READ_SUCCESS",
+            "BLOCK_DEVICE_WRITE_SUCCESS",
+            "BLOCK_DEVICE_READ_ERROR",
+            "BLOCK_DEVICE_WRITE_ERROR",
+            "BLOCK_DEVICE_ERROR",
+        };
+    }
+#endif
+
+#define tmpl(t) template<typename vci_param> t VciBlockDeviceTsar<vci_param>
+
+tmpl(void)::ended(int status)
+{
+#ifdef SOCLIB_MODULE_DEBUG
+    std::cout 
+        << name()
+        << " finished current operation ("
+        << SoclibBlockDeviceOp_str[m_current_op]
+        << ") with the status "
+        << SoclibBlockDeviceStatus_str[status]
+        << std::endl;
+#endif
+
+	if ( m_irq_enabled )
+		r_irq = true;
+	m_current_op = m_op = BLOCK_DEVICE_NOOP;
+    m_status = status;
+}
+
+tmpl(bool)::on_write(int seg, typename vci_param::addr_t addr, typename vci_param::data_t data, int be)
+{
+    int cell = (int)addr / vci_param::B;
+
+#ifdef SOCLIB_MODULE_DEBUG
+    std::cout 
+        << name()
+        << " write config register "
+        << SoclibBlockDeviceRegisters_str[cell]
+        << " with data 0x"
+        << std::hex << data.read()
+        << std::endl;
+#endif
+
+	switch ((enum SoclibBlockDeviceRegisters)cell) {
+    case BLOCK_DEVICE_BUFFER:
+		m_buffer = data;
+		return true;
+    case BLOCK_DEVICE_COUNT:
+        m_count = data;
+        return true;
+    case BLOCK_DEVICE_LBA:
+		m_lba = data;
+		return true;
+    case BLOCK_DEVICE_OP:
+        if ( m_status == BLOCK_DEVICE_BUSY ) {
+            std::cerr << name() << " warning: receiving a new command while busy, ignored" << std::endl;
+        } else {
+            m_op = data;
+        }
+		return true;
+    case BLOCK_DEVICE_IRQ_ENABLE:
+		m_irq_enabled = data;
+		return true;
+    default:
+        return false;
+	}
+}
+
+tmpl(bool)::on_read(int seg, typename vci_param::addr_t addr, typename vci_param::data_t &data)
+{
+    int cell = (int)addr / vci_param::B;
+
+#ifdef SOCLIB_MODULE_DEBUG
+    std::cout 
+        << name()
+        << " read config register "
+        << SoclibBlockDeviceRegisters_str[cell]
+        << std::endl;
+#endif
+
+	switch ((enum SoclibBlockDeviceRegisters)cell) {
+    case BLOCK_DEVICE_SIZE:
+        data = (typename vci_param::fast_data_t)m_device_size;
+        return true;
+    case BLOCK_DEVICE_BLOCK_SIZE:
+        data = m_block_size;
+        return true;
+    case BLOCK_DEVICE_STATUS:
+        data = m_status;
+        if (m_status != BLOCK_DEVICE_BUSY) {
+            m_status = BLOCK_DEVICE_IDLE;
+            r_irq = false;
+        }
+        return true;
+    default:
+        return false;
+	}
+}
+
+tmpl(void)::read_done( req_t *req )
+{
+    if ( ! req->failed() && m_chunck_offset < m_transfer_size ) {
+#ifdef SOCLIB_MODULE_DEBUG
+    std::cout 
+        << name()
+        << " completed transferring a chunck. Do now the next one..."
+        << std::endl;
+#endif
+        next_req();
+        return;
+    }
+
+	ended( req->failed() ? BLOCK_DEVICE_READ_ERROR : BLOCK_DEVICE_READ_SUCCESS );
+    delete m_data;
+	delete req;
+}
+
+tmpl(void)::write_finish( req_t *req )
+{
+    if ( ! req->failed() && m_chunck_offset < m_transfer_size ) {
+#ifdef SOCLIB_MODULE_DEBUG
+    std::cout 
+        << name()
+        << " completed transferring a chunck. Do now the next one..."
+        << std::endl;
+#endif
+        next_req();
+        return;
+    }
+
+	ended(
+        ( ! req->failed() && ::write( m_fd, (char *)m_data, m_transfer_size ) > 0 )
+        ? BLOCK_DEVICE_WRITE_SUCCESS : BLOCK_DEVICE_WRITE_ERROR );
+    delete m_data;
+	delete req;
+}
+
+tmpl(void)::next_req()
+{
+    switch (m_current_op) {
+    case BLOCK_DEVICE_READ:
+    {
+        m_transfer_size = m_count * m_block_size;
+        if ( m_chunck_offset == 0 ) {
+            if ( m_lba + m_count > m_device_size ) {
+                std::cerr << name() << " warning: trying to read beyond end of device" << std::endl;
+                ended(BLOCK_DEVICE_READ_ERROR);
+                break;
+            }
+            m_data = new uint8_t[m_transfer_size];
+            lseek(m_fd, m_lba*m_block_size, SEEK_SET);
+            int retval = ::read(m_fd, m_data, m_transfer_size);
+            if ( retval < 0 ) {
+                ended(BLOCK_DEVICE_READ_ERROR);
+                break;
+            }
+        }
+        size_t chunck_size = m_transfer_size-m_chunck_offset;
+        if( m_chunck_offset == 0 )
+            chunck_size = ((m_buffer & ~(m_burst_size-1)) + m_burst_size) - m_buffer;
+        if ( chunck_size > m_burst_size )
+            chunck_size = m_burst_size;
+        VciInitSimpleWriteReq<vci_param> *req =
+            new VciInitSimpleWriteReq<vci_param>(
+                m_buffer+m_chunck_offset, m_data+m_chunck_offset, chunck_size );
+        m_chunck_offset += chunck_size;
+        req->setDone( this, ON_T(read_done) );
+        m_vci_init_fsm.doReq( req );
+		m_status = BLOCK_DEVICE_BUSY;
+        break;
+    }
+    case BLOCK_DEVICE_WRITE:
+    {
+        m_transfer_size = m_count * m_block_size;
+        if ( m_chunck_offset == 0 ) {
+            if ( m_lba + m_count > m_device_size ) {
+                std::cerr << name() << " warning: trying to write beyond end of device" << std::endl;
+                ended(BLOCK_DEVICE_WRITE_ERROR);
+                break;
+            }
+            m_data = new uint8_t[m_transfer_size];
+            lseek(m_fd, m_lba*m_block_size, SEEK_SET);
+        }
+        size_t chunck_size = m_transfer_size-m_chunck_offset;
+        if ( (( m_buffer + m_chunck_offset ) & ( m_burst_size-1 )) )
+            chunck_size = 4;
+        if ( chunck_size < m_burst_size )
+            chunck_size = 4;
+        if ( chunck_size > m_burst_size )
+            chunck_size = m_burst_size;
+        VciInitSimpleReadReq<vci_param> *req =
+            new VciInitSimpleReadReq<vci_param>(
+                m_data+m_chunck_offset, m_buffer+m_chunck_offset, chunck_size );
+        m_chunck_offset += chunck_size;
+        req->setDone( this, ON_T(write_finish) );
+        m_vci_init_fsm.doReq( req );
+		m_status = BLOCK_DEVICE_BUSY;
+        break;
+    }
+    default:
+        ended(BLOCK_DEVICE_ERROR);
+        break;
+    }
+}
+
+tmpl(void)::transition()
+{
+	if (!p_resetn) {
+		m_vci_target_fsm.reset();
+		m_vci_init_fsm.reset();
+		r_irq = false;
+		m_irq_enabled = false;
+		m_status = BLOCK_DEVICE_IDLE;
+		return;
+	}
+
+	if ( m_current_op == BLOCK_DEVICE_NOOP &&
+		 m_op != BLOCK_DEVICE_NOOP ) {
+#ifdef SOCLIB_MODULE_DEBUG
+    std::cout 
+        << name()
+        << " launch an operation "
+        << SoclibBlockDeviceOp_str[m_op]
+        << std::endl;
+#endif
+		m_current_op = m_op;
+        m_op = BLOCK_DEVICE_NOOP;
+        m_chunck_offset = 0;
+        next_req();
+	}
+
+	m_vci_target_fsm.transition();
+	m_vci_init_fsm.transition();
+}
+
+tmpl(void)::genMoore()
+{
+	m_vci_target_fsm.genMoore();
+	m_vci_init_fsm.genMoore();
+
+	p_irq = r_irq && m_irq_enabled;
+}
+
+tmpl(/**/)::VciBlockDeviceTsar(
+    sc_module_name name,
+    const MappingTable &mt,
+    const IntTab &srcid,
+    const IntTab &tgtid,
+    const std::string &filename,
+    const uint32_t block_size,
+    const uint32_t burst_size)
+	: caba::BaseModule(name),
+	  m_vci_target_fsm(p_vci_target, mt.getSegmentList(tgtid)),
+	  m_vci_init_fsm(p_vci_initiator, mt.indexForId(srcid)),
+      m_block_size(block_size),
+      m_burst_size(burst_size),
+      p_clk("clk"),
+      p_resetn("resetn"),
+      p_vci_target("vci_target"),
+      p_vci_initiator("vci_initiator"),
+      p_irq("irq")
+{
+	m_vci_target_fsm.on_read_write(on_read, on_write);
+
+    m_fd = ::open(filename.c_str(), O_RDWR);
+    if ( m_fd < 0 ) {
+        throw soclib::exception::RunTimeError(
+            std::string("Unable to open file ")+filename);
+    }
+    m_device_size = lseek(m_fd, 0, SEEK_END) / m_block_size;
+    if ( m_device_size > ((uint64_t)1<<(vci_param::B*8)) ) {
+        std::cerr
+            << "Warning: block device " << filename
+            << " has more blocks than addressable with "
+            << (8*vci_param::B) << "." << std::endl;
+        m_device_size = ((uint64_t)1<<(vci_param::B*8));
+    }
+#ifdef SOCLIB_MODULE_DEBUG
+    std::cout 
+        << name
+        << " = Opened " 
+        << filename
+        << " which has "
+        << m_device_size
+        << " blocks of "
+        << m_block_size
+        << " bytes"
+        << std::endl;
+#endif
+
+	SC_METHOD(transition);
+	dont_initialize();
+	sensitive << p_clk.pos();
+
+	SC_METHOD(genMoore);
+	dont_initialize();
+	sensitive << p_clk.neg();
+}
+
+}}
+
+// Local Variables:
+// tab-width: 4
+// c-basic-offset: 4
+// c-file-offsets:((innamespace . 0)(inline-open . 0))
+// indent-tabs-mode: nil
+// End:
+
+// vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4
+
Index: branches/v4/modules/vci_block_device_tsar/include/soclib/block_device_tsar.h
===================================================================
--- branches/v4/modules/vci_block_device_tsar/include/soclib/block_device_tsar.h	(revision 371)
+++ branches/v4/modules/vci_block_device_tsar/include/soclib/block_device_tsar.h	(revision 371)
@@ -0,0 +1,68 @@
+/*
+ * SOCLIB_LGPL_HEADER_BEGIN
+ * 
+ * This file is part of SoCLib, GNU LGPLv2.1.
+ * 
+ * SoCLib is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU Lesser General Public License as published
+ * by the Free Software Foundation; version 2.1 of the License.
+ * 
+ * SoCLib is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * Lesser General Public License for more details.
+ * 
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with SoCLib; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301 USA
+ * 
+ * SOCLIB_LGPL_HEADER_END
+ *
+ * Copyright (c) UPMC, Lip6, Asim
+ *         Nicolas Pouillon <nipo@ssji.net>, 2007
+ *         Eric Guthmuller  <eric.guthmuller@polytechnique.edu>, 2009
+ *
+ * Maintainers: nipo eric.guthmuller@polytechnique.edu
+ */
+#ifndef BLOCK_DEVICE_TSAR_REGS_H
+#define BLOCK_DEVICE_TSAR_REGS_H
+
+enum SoclibBlockDeviceRegisters {
+    BLOCK_DEVICE_BUFFER,
+    BLOCK_DEVICE_LBA,
+    BLOCK_DEVICE_COUNT,
+    BLOCK_DEVICE_OP,
+    BLOCK_DEVICE_STATUS,
+    BLOCK_DEVICE_IRQ_ENABLE,
+    BLOCK_DEVICE_SIZE,
+    BLOCK_DEVICE_BLOCK_SIZE,
+};
+
+enum SoclibBlockDeviceOp {
+	BLOCK_DEVICE_NOOP,
+	BLOCK_DEVICE_READ,
+	BLOCK_DEVICE_WRITE,
+};
+
+enum SoclibBlockDeviceStatus {
+	BLOCK_DEVICE_IDLE,
+	BLOCK_DEVICE_BUSY,
+	BLOCK_DEVICE_READ_SUCCESS,
+	BLOCK_DEVICE_WRITE_SUCCESS,
+	BLOCK_DEVICE_READ_ERROR,
+	BLOCK_DEVICE_WRITE_ERROR,
+	BLOCK_DEVICE_ERROR,
+};
+
+#endif /* BLOCK_DEVICE_TSAR_REGS_H */
+
+// Local Variables:
+// tab-width: 4
+// c-basic-offset: 4
+// c-file-offsets:((innamespace . 0)(inline-open . 0))
+// indent-tabs-mode: nil
+// End:
+
+// vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4
+
Index: branches/v4/modules/vci_block_device_tsar_v2/caba/metadata/vci_block_device_tsar_v2.sd
===================================================================
--- branches/v4/modules/vci_block_device_tsar_v2/caba/metadata/vci_block_device_tsar_v2.sd	(revision 371)
+++ branches/v4/modules/vci_block_device_tsar_v2/caba/metadata/vci_block_device_tsar_v2.sd	(revision 371)
@@ -0,0 +1,43 @@
+
+# -*- python -*-
+
+__id__ = "$Id$"
+__version__ = "$Revision$"
+
+Module('caba:vci_block_device_tsar_v2',
+	   classname = 'soclib::caba::VciBlockDeviceTsarV2',
+	   tmpl_parameters = [
+	parameter.Module('vci_param',  default = 'caba:vci_param'),
+	],
+	   header_files = ['../source/include/vci_block_device_tsar_v2.h',
+					],
+    interface_files = [
+					   '../../include/soclib/block_device_tsar_v2.h'
+					   ],
+	   implementation_files = ['../source/src/vci_block_device_tsar_v2.cpp',],
+	   ports = [
+	Port('caba:vci_target', 'p_vci_target'),
+	Port('caba:vci_initiator', 'p_vci_initiator'),
+	Port('caba:bit_out', 'p_irq'),
+	Port('caba:bit_in', 'p_resetn', auto = 'resetn'),
+	Port('caba:clock_in', 'p_clk', auto = 'clock'),
+	],
+	   uses = [
+	Uses('caba:base_module'),
+	Uses('caba:vci_target_fsm', default_target = 'true', support_llsc = 'false'),
+	Uses('caba:vci_initiator_simple_read_req'),
+	Uses('caba:vci_initiator_simple_write_req'),
+	Uses('caba:vci_initiator_fsm'),
+	],
+	instance_parameters = [
+        parameter.Module('mt', typename = 'common:mapping_table', auto = 'env:mapping_table'),
+        parameter.IntTab('srcid'),
+        parameter.IntTab('tgtid'),
+        parameter.String('filename'),
+        ],
+	   extensions = [
+	'dsx:addressable=tgtid',
+	'dsx:max_segments=1',
+	'dsx:get_ident=tgtid:p_vci_target:mt,srcid:p_vci_initiator:mt',
+   ],
+)
Index: branches/v4/modules/vci_block_device_tsar_v2/caba/source/include/vci_block_device_tsar_v2.h
===================================================================
--- branches/v4/modules/vci_block_device_tsar_v2/caba/source/include/vci_block_device_tsar_v2.h	(revision 371)
+++ branches/v4/modules/vci_block_device_tsar_v2/caba/source/include/vci_block_device_tsar_v2.h	(revision 371)
@@ -0,0 +1,115 @@
+/* -*- c++ -*-
+ *
+ * SOCLIB_LGPL_HEADER_BEGIN
+ * 
+ * This file is part of SoCLib, GNU LGPLv2.1.
+ * 
+ * SoCLib is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU Lesser General Public License as published
+ * by the Free Software Foundation; version 2.1 of the License.
+ * 
+ * SoCLib is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * Lesser General Public License for more details.
+ * 
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with SoCLib; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301 USA
+ * 
+ * SOCLIB_LGPL_HEADER_END
+ *
+ * Copyright (c) UPMC, Lip6, Asim
+ *         Nicolas Pouillon <nipo@ssji.net>, 2007
+ *         Eric Guthmuller  <eric.guthmuller@polytechnique.edu>
+ *
+ * Maintainers: nipo eric.guthmuller@polytechnique.edu
+ */
+#ifndef SOCLIB_VCI_BLOCK_DEVICE_TSAR_V2_H
+#define SOCLIB_VCI_BLOCK_DEVICE_TSAR_V2_H
+
+#include <stdint.h>
+#include <systemc>
+#include "vci_target_fsm.h"
+#include "vci_initiator_fsm.h"
+#include "caba_base_module.h"
+#include "mapping_table.h"
+
+namespace soclib {
+namespace caba {
+
+using namespace sc_core;
+
+template<typename vci_param>
+class VciBlockDeviceTsarV2
+	: public caba::BaseModule
+{
+private:
+    soclib::caba::VciTargetFsm<vci_param, true> m_vci_target_fsm;
+    soclib::caba::VciInitiatorFsm<vci_param> m_vci_init_fsm;
+    typedef typename soclib::caba::VciInitiatorReq<vci_param> req_t;
+
+    bool on_write(int seg, typename vci_param::addr_t addr, typename vci_param::data_t data, int be);
+    bool on_read(int seg, typename vci_param::addr_t addr, typename vci_param::data_t &data);
+    void read_done( req_t *req );
+    void write_finish( req_t *req );
+    void open_finish( req_t *req );
+    void next_req();
+    void transition();
+    void genMoore();
+
+	const uint32_t m_block_size;
+    const uint32_t m_burst_size;    // Maximum size of the burst
+
+	int m_fd;
+	int m_op;
+	uint32_t m_buffer;
+	uint32_t m_count;
+	uint64_t m_device_size;
+	uint32_t m_lba;
+    int m_status;
+    uint32_t m_chunck_offset;
+    uint32_t m_transfer_size;
+	bool m_irq_enabled;
+	bool r_irq;
+
+	int m_current_op;
+
+	uint8_t *m_data;
+
+	inline void ended(int status);
+
+protected:
+    SC_HAS_PROCESS(VciBlockDeviceTsarV2);
+
+public:
+    sc_in<bool> p_clk;
+    sc_in<bool> p_resetn;
+    soclib::caba::VciTarget<vci_param> p_vci_target;
+    soclib::caba::VciInitiator<vci_param> p_vci_initiator;
+    sc_out<bool> p_irq;
+
+	VciBlockDeviceTsarV2(
+		sc_module_name name,
+		const soclib::common::MappingTable &mt,
+		const soclib::common::IntTab &srcid,
+		const soclib::common::IntTab &tgtid,
+        const std::string &filename,
+        const uint32_t block_size = 512,
+        const uint32_t burst_size = 64);
+};
+
+}}
+
+#endif /* SOCLIB_VCI_BLOCK_DEVICE_TSAR_V2_H */
+
+// Local Variables:
+// tab-width: 4
+// c-basic-offset: 4
+// c-file-offsets:((innamespace . 0)(inline-open . 0))
+// indent-tabs-mode: nil
+// End:
+
+// vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4
+
Index: branches/v4/modules/vci_block_device_tsar_v2/caba/source/src/vci_block_device_tsar_v2.cpp
===================================================================
--- branches/v4/modules/vci_block_device_tsar_v2/caba/source/src/vci_block_device_tsar_v2.cpp	(revision 371)
+++ branches/v4/modules/vci_block_device_tsar_v2/caba/source/src/vci_block_device_tsar_v2.cpp	(revision 371)
@@ -0,0 +1,364 @@
+/* -*- c++ -*-
+ *
+ * SOCLIB_LGPL_HEADER_BEGIN
+ * 
+ * This file is part of SoCLib, GNU LGPLv2.1.
+ * 
+ * SoCLib is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU Lesser General Public License as published
+ * by the Free Software Foundation; version 2.1 of the License.
+ * 
+ * SoCLib is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * Lesser General Public License for more details.
+ * 
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with SoCLib; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301 USA
+ * 
+ * SOCLIB_LGPL_HEADER_END
+ *
+ * Copyright (c) UPMC, Lip6, Asim
+ *         Nicolas Pouillon <nipo@ssji.net>, 2007
+ *         Eric Guthmuller  <eric.guthmuller@polytechnique.edu>, 2009
+ */
+
+#include <stdint.h>
+#include <iostream>
+#include "register.h"
+#include "../include/vci_block_device_tsar_v2.h"
+#include <fcntl.h>
+#include "block_device_tsar_v2.h"
+
+namespace soclib { namespace caba {
+
+#ifdef SOCLIB_MODULE_DEBUG
+    namespace {
+        const char* SoclibBlockDeviceRegisters_str[] = {
+            "BLOCK_DEVICE_BUFFER",
+            "BLOCK_DEVICE_LBA",
+            "BLOCK_DEVICE_COUNT",
+            "BLOCK_DEVICE_OP",
+            "BLOCK_DEVICE_STATUS",
+            "BLOCK_DEVICE_IRQ_ENABLE",
+            "BLOCK_DEVICE_SIZE",
+            "BLOCK_DEVICE_BLOCK_SIZE"
+        };
+        const char* SoclibBlockDeviceOp_str[] = {
+            "BLOCK_DEVICE_NOOP",
+            "BLOCK_DEVICE_READ",
+            "BLOCK_DEVICE_WRITE",
+        };
+        const char* SoclibBlockDeviceStatus_str[] = {
+            "BLOCK_DEVICE_IDLE",
+            "BLOCK_DEVICE_BUSY",
+            "BLOCK_DEVICE_READ_SUCCESS",
+            "BLOCK_DEVICE_WRITE_SUCCESS",
+            "BLOCK_DEVICE_READ_ERROR",
+            "BLOCK_DEVICE_WRITE_ERROR",
+            "BLOCK_DEVICE_ERROR",
+        };
+    }
+#endif
+
+#define tmpl(t) template<typename vci_param> t VciBlockDeviceTsarV2<vci_param>
+
+tmpl(void)::ended(int status)
+{
+#ifdef SOCLIB_MODULE_DEBUG
+    std::cout 
+        << name()
+        << " finished current operation ("
+        << SoclibBlockDeviceOp_str[m_current_op]
+        << ") with the status "
+        << SoclibBlockDeviceStatus_str[status]
+        << std::endl;
+#endif
+
+	if ( m_irq_enabled )
+		r_irq = true;
+	m_current_op = m_op = BLOCK_DEVICE_NOOP;
+    m_status = status;
+}
+
+tmpl(bool)::on_write(int seg, typename vci_param::addr_t addr, typename vci_param::data_t data, int be)
+{
+    int cell = (int)addr / vci_param::B;
+
+#ifdef SOCLIB_MODULE_DEBUG
+    std::cout 
+        << name()
+        << " write config register "
+        << SoclibBlockDeviceRegisters_str[cell]
+        << " with data 0x"
+        << std::hex << data.read()
+        << std::endl;
+#endif
+
+	switch ((enum SoclibBlockDeviceRegisters)cell) {
+    case BLOCK_DEVICE_BUFFER:
+		m_buffer = data;
+		return true;
+    case BLOCK_DEVICE_COUNT:
+        m_count = data;
+        return true;
+    case BLOCK_DEVICE_LBA:
+		m_lba = data;
+		return true;
+    case BLOCK_DEVICE_OP:
+        if ( m_status == BLOCK_DEVICE_BUSY ) {
+            std::cerr << name() << " warning: receiving a new command while busy, ignored" << std::endl;
+        } else {
+            m_op = data;
+        }
+		return true;
+    case BLOCK_DEVICE_IRQ_ENABLE:
+		m_irq_enabled = data;
+		return true;
+    default:
+        return false;
+	}
+}
+
+tmpl(bool)::on_read(int seg, typename vci_param::addr_t addr, typename vci_param::data_t &data)
+{
+    int cell = (int)addr / vci_param::B;
+
+#ifdef SOCLIB_MODULE_DEBUG
+    std::cout 
+        << name()
+        << " read config register "
+        << SoclibBlockDeviceRegisters_str[cell]
+        << std::endl;
+#endif
+
+	switch ((enum SoclibBlockDeviceRegisters)cell) {
+    case BLOCK_DEVICE_SIZE:
+        data = (typename vci_param::fast_data_t)m_device_size;
+        return true;
+    case BLOCK_DEVICE_BLOCK_SIZE:
+        data = m_block_size;
+        return true;
+    case BLOCK_DEVICE_STATUS:
+        data = m_status;
+        if (m_status != BLOCK_DEVICE_BUSY) {
+            m_status = BLOCK_DEVICE_IDLE;
+            r_irq = false;
+        }
+        return true;
+    default:
+        return false;
+	}
+}
+
+tmpl(void)::read_done( req_t *req )
+{
+    if ( ! req->failed() && m_chunck_offset < m_transfer_size ) {
+#ifdef SOCLIB_MODULE_DEBUG
+    std::cout 
+        << name()
+        << " completed transferring a chunck. Do now the next one..."
+        << std::endl;
+#endif
+        next_req();
+        return;
+    }
+
+	ended( req->failed() ? BLOCK_DEVICE_READ_ERROR : BLOCK_DEVICE_READ_SUCCESS );
+    delete m_data;
+	delete req;
+}
+
+tmpl(void)::write_finish( req_t *req )
+{
+    if ( ! req->failed() && m_chunck_offset < m_transfer_size ) {
+#ifdef SOCLIB_MODULE_DEBUG
+    std::cout 
+        << name()
+        << " completed transferring a chunck. Do now the next one..."
+        << std::endl;
+#endif
+        next_req();
+        return;
+    }
+
+	ended(
+        ( ! req->failed() && ::write( m_fd, (char *)m_data, m_transfer_size ) > 0 )
+        ? BLOCK_DEVICE_WRITE_SUCCESS : BLOCK_DEVICE_WRITE_ERROR );
+    delete m_data;
+	delete req;
+}
+
+tmpl(void)::next_req()
+{
+    switch (m_current_op) {
+    case BLOCK_DEVICE_READ:
+    {
+        m_transfer_size = m_count * m_block_size;
+        if ( m_chunck_offset == 0 ) {
+            if ( m_lba + m_count > m_device_size ) {
+                std::cerr << name() << " warning: trying to read beyond end of device" << std::endl;
+                ended(BLOCK_DEVICE_READ_ERROR);
+                break;
+            }
+            m_data = new uint8_t[m_transfer_size];
+            lseek(m_fd, m_lba*m_block_size, SEEK_SET);
+            int retval = ::read(m_fd, m_data, m_transfer_size);
+            if ( retval < 0 ) {
+                ended(BLOCK_DEVICE_READ_ERROR);
+                break;
+            }
+        }
+        size_t chunck_size = m_transfer_size-m_chunck_offset;
+        if( m_chunck_offset == 0 )
+            chunck_size = ((m_buffer & ~(m_burst_size-1)) + m_burst_size) - m_buffer;
+        if ( chunck_size > m_burst_size )
+            chunck_size = m_burst_size;
+        VciInitSimpleWriteReq<vci_param> *req =
+            new VciInitSimpleWriteReq<vci_param>(
+                m_buffer+m_chunck_offset, m_data+m_chunck_offset, chunck_size );
+        m_chunck_offset += chunck_size;
+        req->setDone( this, ON_T(read_done) );
+        m_vci_init_fsm.doReq( req );
+		m_status = BLOCK_DEVICE_BUSY;
+        break;
+    }
+    case BLOCK_DEVICE_WRITE:
+    {
+        m_transfer_size = m_count * m_block_size;
+        if ( m_chunck_offset == 0 ) {
+            if ( m_lba + m_count > m_device_size ) {
+                std::cerr << name() << " warning: trying to write beyond end of device" << std::endl;
+                ended(BLOCK_DEVICE_WRITE_ERROR);
+                break;
+            }
+            m_data = new uint8_t[m_transfer_size];
+            lseek(m_fd, m_lba*m_block_size, SEEK_SET);
+        }
+        size_t chunck_size = m_transfer_size-m_chunck_offset;
+        if ( (( m_buffer + m_chunck_offset ) & ( m_burst_size-1 )) )
+            chunck_size = m_burst_size - (( m_buffer + m_chunck_offset ) & ( m_burst_size-1 ));
+        if ( chunck_size > m_burst_size )
+            chunck_size = m_burst_size;
+        VciInitSimpleReadReq<vci_param> *req =
+            new VciInitSimpleReadReq<vci_param>(
+                m_data+m_chunck_offset, m_buffer+m_chunck_offset, chunck_size );
+        m_chunck_offset += chunck_size;
+        req->setDone( this, ON_T(write_finish) );
+        m_vci_init_fsm.doReq( req );
+		m_status = BLOCK_DEVICE_BUSY;
+        break;
+    }
+    default:
+        ended(BLOCK_DEVICE_ERROR);
+        break;
+    }
+}
+
+tmpl(void)::transition()
+{
+	if (!p_resetn) {
+		m_vci_target_fsm.reset();
+		m_vci_init_fsm.reset();
+		r_irq = false;
+		m_irq_enabled = false;
+		m_status = BLOCK_DEVICE_IDLE;
+		return;
+	}
+
+	if ( m_current_op == BLOCK_DEVICE_NOOP &&
+		 m_op != BLOCK_DEVICE_NOOP ) {
+#ifdef SOCLIB_MODULE_DEBUG
+    std::cout 
+        << name()
+        << " launch an operation "
+        << SoclibBlockDeviceOp_str[m_op]
+        << std::endl;
+#endif
+		m_current_op = m_op;
+        m_op = BLOCK_DEVICE_NOOP;
+        m_chunck_offset = 0;
+        next_req();
+	}
+
+	m_vci_target_fsm.transition();
+	m_vci_init_fsm.transition();
+}
+
+tmpl(void)::genMoore()
+{
+	m_vci_target_fsm.genMoore();
+	m_vci_init_fsm.genMoore();
+
+	p_irq = r_irq && m_irq_enabled;
+}
+
+tmpl(/**/)::VciBlockDeviceTsarV2(
+    sc_module_name name,
+    const MappingTable &mt,
+    const IntTab &srcid,
+    const IntTab &tgtid,
+    const std::string &filename,
+    const uint32_t block_size,
+    const uint32_t burst_size)
+	: caba::BaseModule(name),
+	  m_vci_target_fsm(p_vci_target, mt.getSegmentList(tgtid)),
+	  m_vci_init_fsm(p_vci_initiator, mt.indexForId(srcid)),
+      m_block_size(block_size),
+      m_burst_size(burst_size),
+      p_clk("clk"),
+      p_resetn("resetn"),
+      p_vci_target("vci_target"),
+      p_vci_initiator("vci_initiator"),
+      p_irq("irq")
+{
+	m_vci_target_fsm.on_read_write(on_read, on_write);
+
+    m_fd = ::open(filename.c_str(), O_RDWR);
+    if ( m_fd < 0 ) {
+        throw soclib::exception::RunTimeError(
+            std::string("Unable to open file ")+filename);
+    }
+    m_device_size = lseek(m_fd, 0, SEEK_END) / m_block_size;
+    if ( m_device_size > ((uint64_t)1<<(vci_param::B*8)) ) {
+        std::cerr
+            << "Warning: block device " << filename
+            << " has more blocks than addressable with "
+            << (8*vci_param::B) << "." << std::endl;
+        m_device_size = ((uint64_t)1<<(vci_param::B*8));
+    }
+#ifdef SOCLIB_MODULE_DEBUG
+    std::cout 
+        << name
+        << " = Opened " 
+        << filename
+        << " which has "
+        << m_device_size
+        << " blocks of "
+        << m_block_size
+        << " bytes"
+        << std::endl;
+#endif
+
+	SC_METHOD(transition);
+	dont_initialize();
+	sensitive << p_clk.pos();
+
+	SC_METHOD(genMoore);
+	dont_initialize();
+	sensitive << p_clk.neg();
+}
+
+}}
+
+// Local Variables:
+// tab-width: 4
+// c-basic-offset: 4
+// c-file-offsets:((innamespace . 0)(inline-open . 0))
+// indent-tabs-mode: nil
+// End:
+
+// vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4
+
Index: branches/v4/modules/vci_block_device_tsar_v2/include/soclib/block_device_tsar_v2.h
===================================================================
--- branches/v4/modules/vci_block_device_tsar_v2/include/soclib/block_device_tsar_v2.h	(revision 371)
+++ branches/v4/modules/vci_block_device_tsar_v2/include/soclib/block_device_tsar_v2.h	(revision 371)
@@ -0,0 +1,68 @@
+/*
+ * SOCLIB_LGPL_HEADER_BEGIN
+ * 
+ * This file is part of SoCLib, GNU LGPLv2.1.
+ * 
+ * SoCLib is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU Lesser General Public License as published
+ * by the Free Software Foundation; version 2.1 of the License.
+ * 
+ * SoCLib is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * Lesser General Public License for more details.
+ * 
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with SoCLib; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301 USA
+ * 
+ * SOCLIB_LGPL_HEADER_END
+ *
+ * Copyright (c) UPMC, Lip6, Asim
+ *         Nicolas Pouillon <nipo@ssji.net>, 2007
+ *         Eric Guthmuller  <eric.guthmuller@polytechnique.edu>, 2009
+ *
+ * Maintainers: nipo eric.guthmuller@polytechnique.edu
+ */
+#ifndef BLOCK_DEVICE_TSAR_V2_REGS_H
+#define BLOCK_DEVICE_TSAR_V2_REGS_H
+
+enum SoclibBlockDeviceRegisters {
+    BLOCK_DEVICE_BUFFER,
+    BLOCK_DEVICE_LBA,
+    BLOCK_DEVICE_COUNT,
+    BLOCK_DEVICE_OP,
+    BLOCK_DEVICE_STATUS,
+    BLOCK_DEVICE_IRQ_ENABLE,
+    BLOCK_DEVICE_SIZE,
+    BLOCK_DEVICE_BLOCK_SIZE,
+};
+
+enum SoclibBlockDeviceOp {
+	BLOCK_DEVICE_NOOP,
+	BLOCK_DEVICE_READ,
+	BLOCK_DEVICE_WRITE,
+};
+
+enum SoclibBlockDeviceStatus {
+	BLOCK_DEVICE_IDLE,
+	BLOCK_DEVICE_BUSY,
+	BLOCK_DEVICE_READ_SUCCESS,
+	BLOCK_DEVICE_WRITE_SUCCESS,
+	BLOCK_DEVICE_READ_ERROR,
+	BLOCK_DEVICE_WRITE_ERROR,
+	BLOCK_DEVICE_ERROR,
+};
+
+#endif /* BLOCK_DEVICE_TSAR_V2_REGS_H */
+
+// Local Variables:
+// tab-width: 4
+// c-basic-offset: 4
+// c-file-offsets:((innamespace . 0)(inline-open . 0))
+// indent-tabs-mode: nil
+// End:
+
+// vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4
+
Index: branches/v4/modules/vci_block_device_tsar_v4/caba/metadata/vci_block_device_tsar_v4.sd
===================================================================
--- branches/v4/modules/vci_block_device_tsar_v4/caba/metadata/vci_block_device_tsar_v4.sd	(revision 371)
+++ branches/v4/modules/vci_block_device_tsar_v4/caba/metadata/vci_block_device_tsar_v4.sd	(revision 371)
@@ -0,0 +1,35 @@
+
+# -*- python -*-
+
+Module('caba:vci_block_device_tsar_v4',
+	   classname = 'soclib::caba::VciBlockDeviceTsarV4',
+	   tmpl_parameters = [ parameter.Module('vci_param',  default = 'caba:vci_param'), ],
+	   header_files = ['../source/include/vci_block_device_tsar_v4.h', ],
+           interface_files = ['../../include/soclib/block_device_tsar_v4.h', ],
+	   implementation_files = ['../source/src/vci_block_device_tsar_v4.cpp',],
+	   ports = [
+		Port('caba:vci_target', 'p_vci_target'),
+		Port('caba:vci_initiator', 'p_vci_initiator'),
+		Port('caba:bit_out', 'p_irq'),
+		Port('caba:bit_in', 'p_resetn', auto = 'resetn'),
+		Port('caba:clock_in', 'p_clk', auto = 'clock'), 
+		],
+	   uses = [
+		Uses('caba:base_module'),
+		Uses('common:mapping_table'),
+		],
+	instance_parameters = [
+        	parameter.Module('mt', typename = 'common:mapping_table', auto = 'env:mapping_table'),
+        	parameter.IntTab('srcid'),
+        	parameter.IntTab('tgtid'),
+        	parameter.String('filename'),
+		parameter.Int('block_size'),
+		parameter.Int('burst_size'),
+		parameter.Int('latency'),
+        	],
+	   extensions = [
+		'dsx:addressable=tgtid',
+		'dsx:max_segments=1',
+		'dsx:get_ident=tgtid:p_vci_target:mt,srcid:p_vci_initiator:mt',
+		],
+)
Index: branches/v4/modules/vci_block_device_tsar_v4/caba/source/include/vci_block_device_tsar_v4.h
===================================================================
--- branches/v4/modules/vci_block_device_tsar_v4/caba/source/include/vci_block_device_tsar_v4.h	(revision 371)
+++ branches/v4/modules/vci_block_device_tsar_v4/caba/source/include/vci_block_device_tsar_v4.h	(revision 371)
@@ -0,0 +1,239 @@
+
+/* -*- c++ -*-
+ *
+ * SOCLIB_LGPL_HEADER_BEGIN
+ * 
+ * This file is part of SoCLib, GNU LGPLv2.1.
+ * 
+ * SoCLib is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU Lesser General Public License as published
+ * by the Free Software Foundation; version 2.1 of the License.
+ * 
+ * SoCLib is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * Lesser General Public License for more details.
+ * 
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with SoCLib; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301 USA
+ * 
+ * SOCLIB_LGPL_HEADER_END
+ *
+ * Copyright (c) UPMC, Lip6, Asim
+ *         alain.greiner@lip6.fr april 2011
+ *
+ * Maintainers: alain
+ */
+
+//////////////////////////////////////////////////////////////////////////////////////
+// This component is a simplified disk controller with a VCI interface.
+// This component can perform data transfers between one single file belonging 
+// to the host system and a buffer in the memory of the virtual prototype.
+// The file name is an argument of the constructor.
+// This component has a DMA capability, and is both a target and an initiator.
+// The block size (bytes), and the burst size (bytes) must be power of 2.
+// The burst size is typically a cache line. 
+// If the memory buffer is not constrained to be aligned on a burst boundary. 
+// Both read and write transfers are supported. An IRQ is optionally
+// asserted when the transfer is completed. 
+//
+// As a target this block device controler contains 8 memory mapped registers,
+// taking 32 bytes in the address space.
+// - BLOCK_DEVICE_BUFFER        0x00 (read/write)    Memory buffer base address.
+// - BLOCK_DEVICE_COUNT         0x04 (read/write)    Number of blocks to be transfered.
+// - BLOCK_DEVICE_LBA           0x08 (read/write)    Index of first block in the file.
+// - BLOCK_DEVICE_OP            0x0C (write-only)    Writing here starts the operation.
+// - BLOCK_DEVICE_STATUS        0x10 (read-only)     Block Device status.
+// - BLOCK_DEVICE_IRQ_ENABLE    0x14 (read/write)    IRQ enabled if non zero.
+// - BLOCK_DEVICE_SIZE          0x18 (read-only)     Number of addressable blocks.
+// - BLOCK_DEVICE_BLOCK_SIZE    0x1C (read_only)     Block size in bytes.
+//
+// The following operations codes are supported: 
+// - BLOCK_DEVICE_NOOP          No operation
+// - BLOCK_DEVICE_READ          From block device to memory
+// - BLOCK_DEVICE_WRITE         From memory to block device 
+//
+// The BLOCK_DEVICE_STATUS is actually defined by the initiator FSM state.
+// The following values are defined for device status:
+// -BLOCK_DEVICE_IDLE           0
+// -BLOCK_DEVICE_BUSY           1
+// -BLOCK_DEVICE_READ_SUCCESS   2
+// -BLOCK_DEVICE_WRITE_SUCCESS  3
+// -BLOCK_DEVICE_READ_ERROR     4
+// -BLOCK_DEVICE_WRITE_ERROR    5
+//
+// In the 4 states READ_ERROR, READ_SUCCESS, WRITE_ERROR, WRITE_SUCCESS,
+// the IRQ is asserted (if it is enabled).
+// A read access to the BLOCK_DEVICE_STATUS in these 4 states reset 
+// the initiator FSM state to IDLE, and acknowledge the IRQ.
+// Any write access to registers BUFFER, COUNT, LBA, OP is ignored
+// if the device is not IDLE.
+///////////////////////////////////////////////////////////////////////////
+
+#ifndef SOCLIB_VCI_BLOCK_DEVICE_TSAR_V4_H
+#define SOCLIB_VCI_BLOCK_DEVICE_TSAR_V4_H
+
+#include <stdint.h>
+#include <systemc>
+#include "caba_base_module.h"
+#include "mapping_table.h"
+#include "vci_initiator.h"
+#include "vci_target.h"
+
+namespace soclib {
+namespace caba {
+
+using namespace sc_core;
+
+template<typename vci_param>
+class VciBlockDeviceTsarV4
+	: public caba::BaseModule
+{
+private:
+
+    // Registers
+    sc_signal<int>            	 r_target_fsm;   	 // target fsm state register
+    sc_signal<int>               r_initiator_fsm;    // initiator fsm state register
+    sc_signal<bool>              r_irq_enable;   	 // default value is true
+    sc_signal<uint32_t>          r_nblocks;      	 // number of blocks in transfer
+    sc_signal<uint32_t>          r_buf_address;  	 // memory buffer address
+    sc_signal<uint32_t>          r_lba;          	 // first block index
+    sc_signal<bool>              r_read;         	 // requested operation
+    sc_signal<uint32_t>          r_index;        	 // flit index in local buffer
+    sc_signal<uint32_t>          r_latency_count;    // latency counter 
+    sc_signal<uint32_t>          r_flit_count;   	 // flit counter (in a burst)
+    sc_signal<uint32_t>          r_burst_count;   	 // burst counter (in a block)
+    sc_signal<uint32_t>          r_block_count;  	 // block counter (in a transfer)
+    sc_signal<uint32_t>          r_burst_offset;     // number of non aligned flits
+    sc_signal<uint32_t>          r_burst_nflits;     // number of flits in a burst
+    sc_signal<bool>              r_go;           	 // command from T_FSM to M_FSM
+
+    sc_signal<sc_dt::sc_uint<vci_param::S> >	r_srcid;		// save srcid
+    sc_signal<sc_dt::sc_uint<vci_param::T> >	r_trdid;		// save trdid
+    sc_signal<sc_dt::sc_uint<vci_param::P> >	r_pktid;		// save pktid
+
+    uint32_t*                    r_local_buffer; 	 // capacity is one block 
+
+    // structural parameters
+    soclib::common::Segment      m_segment;      	 // segment associated to target
+    uint32_t                     m_srcid;        	 // initiator index
+    int                          m_fd;           	 // File descriptor
+    uint64_t                     m_device_size;  	 // Total number of blocks
+    const uint32_t               m_flits_per_block;	 // number of flits in a block
+    const uint32_t               m_flits_per_burst;	 // number of flits in a burst
+    const uint32_t               m_bursts_per_block; // number of bursts in a block
+    const uint32_t               m_latency;      	 // device latency
+
+    // methods
+    void transition();
+    void genMoore();
+
+    //  Master FSM states
+    enum {
+    M_IDLE              = 0,
+
+    M_READ_BLOCK        = 1,
+    M_READ_BURST        = 2,
+    M_READ_CMD          = 3,
+    M_READ_RSP          = 4,
+    M_READ_SUCCESS      = 5,
+    M_READ_ERROR        = 6,
+
+    M_WRITE_BURST       = 7,
+    M_WRITE_CMD         = 8,
+    M_WRITE_RSP         = 9,
+    M_WRITE_BLOCK       = 10,
+    M_WRITE_SUCCESS     = 11,
+    M_WRITE_ERROR       = 12,
+    };
+
+    // Target FSM states
+    enum {
+    T_IDLE              = 0,
+    T_WRITE_BUFFER      = 1,
+    T_READ_BUFFER       = 2,
+    T_WRITE_COUNT       = 3,
+    T_READ_COUNT        = 4,
+    T_WRITE_LBA         = 5,
+    T_READ_LBA          = 6,
+    T_WRITE_OP          = 7,
+    T_READ_STATUS       = 8,
+    T_WRITE_IRQEN       = 9,
+    T_READ_IRQEN        = 10,
+    T_READ_SIZE         = 11,
+    T_READ_BLOCK        = 12,
+    T_READ_ERROR        = 13,
+    T_WRITE_ERROR       = 14,
+    };
+
+    // Error codes values
+    enum {
+    VCI_READ_OK		= 0,
+    VCI_READ_ERROR	= 1,
+    VCI_WRITE_OK	= 2,
+    VCI_WRITE_ERROR	= 3,
+    };
+
+    /* transaction type, pktid field */
+    enum transaction_type_e
+    {
+      // b3 unused
+      // b2 READ / NOT READ
+      // Si READ
+      //  b1 DATA / INS
+      //  b0 UNC / MISS
+      // Si NOT READ
+      //  b1 accÃšs table llsc type SW / other
+      //  b2 WRITE/CAS/LL/SC
+      TYPE_READ_DATA_UNC          = 0x0,
+      TYPE_READ_DATA_MISS         = 0x1,
+      TYPE_READ_INS_UNC           = 0x2,
+      TYPE_READ_INS_MISS          = 0x3,
+      TYPE_WRITE                  = 0x4,
+      TYPE_CAS                    = 0x5,
+      TYPE_LL                     = 0x6,
+      TYPE_SC                     = 0x7
+    };
+
+protected:
+
+    SC_HAS_PROCESS(VciBlockDeviceTsarV4);
+
+public:
+
+    // ports
+    sc_in<bool> 					      p_clk;
+    sc_in<bool> 					      p_resetn;
+    soclib::caba::VciInitiator<vci_param> p_vci_initiator;
+    soclib::caba::VciTarget<vci_param>    p_vci_target;
+    sc_out<bool> 					      p_irq;
+
+    void print_trace();
+
+    // Constructor   
+    VciBlockDeviceTsarV4(
+		sc_module_name                      name,
+		const soclib::common::MappingTable 	&mt,
+		const soclib::common::IntTab 		&srcid,
+		const soclib::common::IntTab 		&tgtid,
+        const std::string                   &filename,
+        const uint32_t 	                    block_size = 512,
+        const uint32_t 	                    burst_size = 64,
+        const uint32_t	                    latency = 0);
+};
+
+}}
+
+#endif /* SOCLIB_VCI_BLOCK_DEVICE_TSAR_V4_H */
+
+// Local Variables:
+// tab-width: 4
+// c-basic-offset: 4
+// c-file-offsets:((innamespace . 0)(inline-open . 0))
+// indent-tabs-mode: nil
+// End:
+
+// vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4
+
Index: branches/v4/modules/vci_block_device_tsar_v4/caba/source/src/vci_block_device_tsar_v4.cpp
===================================================================
--- branches/v4/modules/vci_block_device_tsar_v4/caba/source/src/vci_block_device_tsar_v4.cpp	(revision 371)
+++ branches/v4/modules/vci_block_device_tsar_v4/caba/source/src/vci_block_device_tsar_v4.cpp	(revision 371)
@@ -0,0 +1,684 @@
+/* -*- c++ -*-
+ *
+ * SOCLIB_LGPL_HEADER_BEGIN
+ * 
+ * This file is part of SoCLib, GNU LGPLv2.1.
+ * 
+ * SoCLib is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU Lesser General Public License as published
+ * by the Free Software Foundation; version 2.1 of the License.
+ * 
+ * SoCLib is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * Lesser General Public License for more details.
+ * 
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with SoCLib; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301 USA
+ * 
+ * SOCLIB_LGPL_HEADER_END
+ *
+ * Copyright (c) UPMC, Lip6, Asim
+ *         alain.greiner@lip6.fr april 2011
+ *
+ * Maintainers: alain
+ */
+
+#include <stdint.h>
+#include <iostream>
+#include <fcntl.h>
+#include "vci_block_device_tsar_v4.h"
+
+namespace soclib { namespace caba {
+
+#define tmpl(t) template<typename vci_param> t VciBlockDeviceTsarV4<vci_param>
+
+using namespace soclib::caba;
+using namespace soclib::common;
+
+////////////////////////
+tmpl(void)::transition()
+{
+    if(p_resetn.read() == false) 
+    {
+        r_initiator_fsm = M_IDLE;
+        r_target_fsm    = T_IDLE;
+        r_irq_enable    = true;
+        r_go            = false;
+        return;
+    } 
+
+    //////////////////////////////////////////////////////////////////////////////
+    // The Target FSM controls the following registers:
+    // r_target_fsm, r_irq_enable, r_nblocks, r_buf adress, r_lba, r_go, r_read
+    //////////////////////////////////////////////////////////////////////////////
+
+    switch(r_target_fsm) {
+    ////////////
+    case T_IDLE:
+    {
+        if ( p_vci_target.cmdval.read() ) 
+        { 
+            r_srcid = p_vci_target.srcid.read();
+            r_trdid = p_vci_target.trdid.read();
+            r_pktid = p_vci_target.pktid.read();
+            sc_dt::sc_uint<vci_param::N> address = p_vci_target.address.read();
+            bool                  read    = (p_vci_target.cmd.read() == vci_param::CMD_READ);
+            uint32_t              cell    = (uint32_t)((address & 0x1F)>>2);
+
+            if     ( !read && !m_segment.contains(address) )      r_target_fsm = T_WRITE_ERROR;
+            else if(  read && !m_segment.contains(address) )      r_target_fsm = T_READ_ERROR;
+            else if( !read && !p_vci_target.eop.read() )          r_target_fsm = T_WRITE_ERROR;
+            else if(  read && !p_vci_target.eop.read() )          r_target_fsm = T_READ_ERROR;
+            else if( !read && (cell == BLOCK_DEVICE_BUFFER) )     r_target_fsm = T_WRITE_BUFFER;
+            else if(  read && (cell == BLOCK_DEVICE_BUFFER) )     r_target_fsm = T_READ_BUFFER;
+            else if( !read && (cell == BLOCK_DEVICE_COUNT) )      r_target_fsm = T_WRITE_COUNT;
+            else if(  read && (cell == BLOCK_DEVICE_COUNT) )      r_target_fsm = T_READ_COUNT;
+            else if( !read && (cell == BLOCK_DEVICE_LBA) )        r_target_fsm = T_WRITE_LBA;
+            else if(  read && (cell == BLOCK_DEVICE_LBA) )        r_target_fsm = T_READ_LBA;
+            else if( !read && (cell == BLOCK_DEVICE_OP) )         r_target_fsm = T_WRITE_OP;
+            else if(  read && (cell == BLOCK_DEVICE_STATUS) )     r_target_fsm = T_READ_STATUS;
+            else if( !read && (cell == BLOCK_DEVICE_IRQ_ENABLE) ) r_target_fsm = T_WRITE_IRQEN;
+            else if(  read && (cell == BLOCK_DEVICE_IRQ_ENABLE) ) r_target_fsm = T_READ_IRQEN;
+            else if(  read && (cell == BLOCK_DEVICE_SIZE) )       r_target_fsm = T_READ_SIZE;
+            else if(  read && (cell == BLOCK_DEVICE_BLOCK_SIZE) ) r_target_fsm = T_READ_BLOCK;
+        }
+        break;
+    }
+    ////////////////////
+    case T_WRITE_BUFFER:
+    {
+        if ( r_initiator_fsm == M_IDLE )  r_buf_address = (uint32_t)p_vci_target.wdata.read();
+        if ( p_vci_target.rspack.read() ) r_target_fsm = T_IDLE;
+        break;
+    }
+    ///////////////////
+    case T_WRITE_COUNT:
+    {
+        if ( r_initiator_fsm == M_IDLE )  r_nblocks = (uint32_t)p_vci_target.wdata.read();
+        if ( p_vci_target.rspack.read() ) r_target_fsm = T_IDLE;
+        break;
+    }
+    /////////////////
+    case T_WRITE_LBA:
+    {
+        if ( r_initiator_fsm == M_IDLE )  r_lba = (uint32_t)p_vci_target.wdata.read();
+        if ( p_vci_target.rspack.read() ) r_target_fsm = T_IDLE;
+        break;
+    }
+    ////////////////
+    case T_WRITE_OP:
+    {
+        if ( r_initiator_fsm == M_IDLE ) 
+        {
+            if ( (uint32_t)p_vci_target.wdata.read() == BLOCK_DEVICE_READ )
+            {
+                r_read = true;
+                r_go = true;
+            }
+            else if ( (uint32_t)p_vci_target.wdata.read() == BLOCK_DEVICE_WRITE)
+            {
+                r_read = false;
+                r_go = true;
+            }
+        }
+        if ( p_vci_target.rspack.read() ) r_target_fsm = T_IDLE;
+        break;
+    }
+    ///////////////////
+    case T_WRITE_IRQEN:
+    {
+        r_irq_enable = (p_vci_target.wdata.read() != 0);
+        if ( p_vci_target.rspack.read() ) r_target_fsm = T_IDLE;
+        break;
+    }
+    ///////////////////
+    case T_READ_BUFFER:
+    case T_READ_COUNT:
+    case T_READ_LBA:
+    case T_READ_IRQEN:
+    case T_READ_SIZE:
+    case T_READ_BLOCK:
+    case T_READ_ERROR:
+    case T_WRITE_ERROR:
+    {
+        if ( p_vci_target.rspack.read() ) r_target_fsm = T_IDLE;
+        break;
+    }
+    ///////////////////
+    case T_READ_STATUS:
+    {
+        if ( p_vci_target.rspack.read() ) 
+        {
+            r_target_fsm = T_IDLE;
+            if( (r_initiator_fsm == M_READ_SUCCESS ) ||
+                (r_initiator_fsm == M_READ_ERROR   ) ||
+                (r_initiator_fsm == M_WRITE_SUCCESS) ||
+                (r_initiator_fsm == M_WRITE_ERROR  ) ) r_go = false;
+        }
+        break;
+    }
+    } // end switch target fsm
+	
+    //////////////////////////////////////////////////////////////////////////////
+    // The initiator FSM executes a loop, transfering one block per iteration.
+    // Each block is split in bursts, and the number of bursts depends
+    // on the memory buffer alignment on a burst boundary:
+    // - If buffer aligned, all burst have the same length (m_flits_per burst)
+    //   and the number of bursts is (m_bursts_per_block).
+    // - If buffer not aligned, the number of bursts is (m_bursts_per_block + 1)
+    //   and first and last burst are shorter, because all flits in a burst 
+    //   must be contained in a single cache line.
+    //   first burst => nflits = m_flits_per_burst - offset
+    //   last  burst => nflits = offset
+    //   other burst => nflits = m_flits_per_burst
+    //////////////////////////////////////////////////////////////////////////////
+
+    switch( r_initiator_fsm.read() ) {
+    ////////////
+    case M_IDLE: 	// check buffer alignment to compute the number of bursts
+    {
+        if ( r_go.read() ) 
+        {
+            r_index         = 0;
+            r_block_count   = 0;
+            r_burst_count   = 0;
+            r_flit_count    = 0;
+            r_latency_count = m_latency;
+
+            // compute r_burst_offset (zero when buffer aligned)
+            r_burst_offset = (r_buf_address.read()>>2) % m_flits_per_burst;
+
+            // start tranfer
+            if ( r_read.read() ) 	r_initiator_fsm = M_READ_BLOCK;
+            else                    r_initiator_fsm = M_WRITE_BURST;
+        }
+        break;
+    } 
+    //////////////////
+    case M_READ_BLOCK:  // read one block from disk after waiting m_latency cycles
+    {
+        if ( r_latency_count.read() == 0 )
+        {
+            r_latency_count = m_latency;
+            ::lseek(m_fd, (r_lba + r_block_count)*m_flits_per_block*4, SEEK_SET);
+            if( ::read(m_fd, r_local_buffer, m_flits_per_block*4) < 0 )  
+            {
+                r_initiator_fsm = M_READ_ERROR;
+            }
+            else   
+            {
+                r_burst_count   = 0;
+                r_flit_count    = 0;
+                r_initiator_fsm = M_READ_BURST;
+            }
+        }
+        else
+        {
+            r_latency_count = r_latency_count.read() - 1;
+        }
+        break;
+    }
+    //////////////////
+    case M_READ_BURST:  // Compute the number of flits in the burst
+    {
+        uint32_t offset = r_burst_offset.read();
+
+        if ( offset )                  // buffer not aligned
+        {
+            if ( r_burst_count.read() == 0 ) r_burst_nflits = m_flits_per_burst - offset;
+            else if ( r_burst_count.read() == m_bursts_per_block ) r_burst_nflits = offset;
+            else r_burst_nflits = m_flits_per_burst;
+        }
+        else                           // buffer aligned
+        {
+            r_burst_nflits = m_flits_per_burst;
+        }
+        r_initiator_fsm =  M_READ_CMD;
+        break;
+    }
+    ////////////////
+    case M_READ_CMD:	// Send a multi-flits VCI WRITE command
+    {
+        if ( p_vci_initiator.cmdack.read() )
+        {
+            if ( r_flit_count == (r_burst_nflits.read() - 1) ) // last flit in a burst
+            {
+                r_initiator_fsm = M_READ_RSP;
+                r_flit_count = 0;
+            }
+            else                                               // not the last flit
+            {
+                r_flit_count = r_flit_count.read() + 1;
+            }
+
+            // compute next flit address and next local buffer index
+            r_buf_address = r_buf_address.read() + 4;
+            r_index       = r_index.read() + 1;
+        }
+        break;
+    }
+    ////////////////
+    case M_READ_RSP: 	// Wait a single flit VCI WRITE response
+    {
+        if ( p_vci_initiator.rspval.read() )
+        {
+            bool aligned = (r_burst_offset.read() == 0);
+
+            if ( (p_vci_initiator.rerror.read()&0x1) != 0 ) 
+            {
+                r_initiator_fsm = M_READ_ERROR;
+            }
+            else if ( (not aligned and (r_burst_count.read() == m_bursts_per_block)) or 
+                      (aligned and (r_burst_count.read() == (m_bursts_per_block-1))) )
+            {
+                if ( r_block_count.read() == (r_nblocks.read()-1) ) // last burst of last block 
+                {
+                    r_initiator_fsm = M_READ_SUCCESS;
+                }
+                else                                              // last burst not last block
+                {
+                    r_index          = 0;
+                    r_burst_count    = 0;
+                    r_block_count    = r_block_count.read() + 1;
+                    r_initiator_fsm  = M_READ_BLOCK;
+                }
+            }
+            else                                                // not the last burst
+            {
+                r_burst_count = r_burst_count.read() + 1;
+                r_initiator_fsm = M_READ_BURST;
+            }
+        }
+        break;
+    }
+    ///////////////////
+    case M_READ_SUCCESS:
+    case M_READ_ERROR:
+    {
+        if( !r_go ) r_initiator_fsm = M_IDLE;
+        break;
+    }
+    ///////////////////
+    case M_WRITE_BURST:  // Compute the number of flits in the burst
+    {
+        uint32_t offset = r_burst_offset.read();
+
+        if ( offset )                  // buffer not aligned
+        {
+            if ( r_burst_count.read() == 0 ) r_burst_nflits = m_flits_per_burst - offset;
+            else if ( r_burst_count.read() == m_bursts_per_block ) r_burst_nflits = offset;
+            else r_burst_nflits = m_flits_per_burst;
+        }
+        else                           // buffer aligned
+        {
+            r_burst_nflits = m_flits_per_burst;
+        }
+        r_initiator_fsm =  M_WRITE_CMD;
+        break;
+    }
+    /////////////////
+    case M_WRITE_CMD:	// This is actually a single flit VCI READ command
+    {
+	    if ( p_vci_initiator.cmdack.read() ) r_initiator_fsm = M_WRITE_RSP;
+        break;
+    }
+    /////////////////
+    case M_WRITE_RSP:	// This is actually a multi-flits VCI READ response
+    {
+        bool aligned = (r_burst_offset.read() == 0);
+
+        if ( p_vci_initiator.rspval.read() )
+        {
+            r_local_buffer[r_index.read()] = (uint32_t)p_vci_initiator.rdata.read();
+            r_index = r_index.read() + 1;
+
+            if ( p_vci_initiator.reop.read() )  // last flit of the burst
+            {
+	        r_flit_count  = 0;
+                r_buf_address = r_buf_address.read() + (r_burst_nflits.read()<<2); 
+
+	        if( (p_vci_initiator.rerror.read()&0x1) != 0 ) 
+                {
+                    r_initiator_fsm = M_WRITE_ERROR;
+                }
+                else if ( (not aligned and (r_burst_count.read() == m_bursts_per_block)) or 
+                          (aligned and (r_burst_count.read() == (m_bursts_per_block-1))) ) // last burst
+                {
+                    r_initiator_fsm  = M_WRITE_BLOCK;
+                }
+                else                                          // not the last burst
+                {
+                    r_burst_count = r_burst_count.read() + 1;
+                    r_initiator_fsm = M_WRITE_BURST;
+                }
+            }
+            else
+            {
+	            r_flit_count = r_flit_count.read() + 1;
+            }
+        }
+        break;
+    }
+    ///////////////////
+    case M_WRITE_BLOCK:		// write a block to disk after waiting m_latency cycles
+    {
+        if ( r_latency_count == 0 )
+        {
+            r_latency_count = m_latency;
+            ::lseek(m_fd, (r_lba + r_block_count)*m_flits_per_block*vci_param::B, SEEK_SET);
+            if( ::write(m_fd, r_local_buffer, m_flits_per_block*vci_param::B) < 0 )
+            {
+                r_initiator_fsm = M_WRITE_ERROR; 
+            }
+            else if ( r_block_count.read() == r_nblocks.read() - 1 ) 
+            {
+                r_initiator_fsm = M_WRITE_SUCCESS; 
+            }
+            else
+            {
+                r_burst_count    = 0;
+		r_index          = 0;
+                r_block_count    = r_block_count.read() + 1;
+                r_initiator_fsm = M_WRITE_BURST;
+            }
+        } 
+        else
+        {
+            r_latency_count = r_latency_count - 1;
+        }
+        break;
+    }
+    /////////////////////
+    case M_WRITE_SUCCESS:
+    case M_WRITE_ERROR:
+    {
+        if( !r_go ) r_initiator_fsm = M_IDLE;
+        break;
+    }
+    } // end switch r_initiator_fsm
+}  // end transition
+
+//////////////////////
+tmpl(void)::genMoore()
+{
+    // p_vci_target port   
+    p_vci_target.rsrcid = (sc_dt::sc_uint<vci_param::S>)r_srcid.read();
+    p_vci_target.rtrdid = (sc_dt::sc_uint<vci_param::T>)r_trdid.read();
+    p_vci_target.rpktid = (sc_dt::sc_uint<vci_param::P>)r_pktid.read();
+    p_vci_target.reop   = true;
+
+    switch(r_target_fsm) {
+    case T_IDLE:
+        p_vci_target.cmdack = true;
+        p_vci_target.rspval = false;
+        break;
+    case T_READ_STATUS:
+        p_vci_target.cmdack = false;
+        p_vci_target.rspval = true;
+        if     (r_initiator_fsm == M_IDLE)          p_vci_target.rdata = BLOCK_DEVICE_IDLE;
+        else if(r_initiator_fsm == M_READ_SUCCESS)  p_vci_target.rdata = BLOCK_DEVICE_READ_SUCCESS;
+        else if(r_initiator_fsm == M_WRITE_SUCCESS) p_vci_target.rdata = BLOCK_DEVICE_WRITE_SUCCESS;
+        else if(r_initiator_fsm == M_READ_ERROR)   	p_vci_target.rdata = BLOCK_DEVICE_READ_ERROR;
+        else if(r_initiator_fsm == M_WRITE_ERROR)  	p_vci_target.rdata = BLOCK_DEVICE_WRITE_ERROR;
+        else                                    	p_vci_target.rdata = BLOCK_DEVICE_BUSY;
+        p_vci_target.rerror = VCI_READ_OK;
+        break;
+    case T_READ_BUFFER:
+        p_vci_target.cmdack = false;
+        p_vci_target.rspval = true;
+        p_vci_target.rdata  = (uint32_t)r_buf_address.read();
+        p_vci_target.rerror = VCI_READ_OK;
+        break;
+    case T_READ_COUNT:
+        p_vci_target.cmdack = false;
+        p_vci_target.rspval = true;
+        p_vci_target.rdata = (uint32_t)r_nblocks.read();
+        p_vci_target.rerror = VCI_READ_OK;
+        break;
+    case T_READ_LBA:
+        p_vci_target.cmdack = false;
+        p_vci_target.rspval = true;
+        p_vci_target.rdata = (uint32_t)r_lba.read();
+        p_vci_target.rerror = VCI_READ_OK;
+        break;
+    case T_READ_IRQEN:
+        p_vci_target.cmdack = false;
+        p_vci_target.rspval = true;
+        p_vci_target.rdata = (uint32_t)r_irq_enable.read();
+        p_vci_target.rerror = VCI_READ_OK;
+        break;
+    case T_READ_SIZE:
+        p_vci_target.cmdack = false;
+        p_vci_target.rspval = true;
+        p_vci_target.rdata = (uint32_t)m_device_size;
+        p_vci_target.rerror = VCI_READ_OK;
+        break;
+    case T_READ_BLOCK:
+        p_vci_target.cmdack = false;
+        p_vci_target.rspval = true;
+        p_vci_target.rdata = (uint32_t)m_flits_per_block*vci_param::B;
+        p_vci_target.rerror = VCI_READ_OK;
+        break;
+    case T_READ_ERROR:
+        p_vci_target.cmdack = false;
+        p_vci_target.rspval = true;
+        p_vci_target.rdata = 0;
+        p_vci_target.rerror = VCI_READ_ERROR;
+        break;
+    case T_WRITE_ERROR:
+        p_vci_target.cmdack = false;
+        p_vci_target.rspval = true;
+        p_vci_target.rdata = 0;
+        p_vci_target.rerror = VCI_WRITE_ERROR;
+        break;
+    default:
+        p_vci_target.cmdack = false;
+        p_vci_target.rspval = true;
+        p_vci_target.rdata = 0;
+        p_vci_target.rerror = VCI_WRITE_OK;
+        break;
+    } // end switch target fsm
+
+    // p_vci_initiator port
+    p_vci_initiator.srcid  = (sc_dt::sc_uint<vci_param::S>)m_srcid;
+    p_vci_initiator.trdid  = 0;
+    p_vci_initiator.contig = true;
+    p_vci_initiator.cons   = false;
+    p_vci_initiator.wrap   = false;
+    p_vci_initiator.cfixed = false;
+    p_vci_initiator.clen   = 0;
+
+    switch (r_initiator_fsm) {
+    case M_WRITE_CMD:		// It is actually a single flit VCI read command
+        p_vci_initiator.rspack  = false;
+        p_vci_initiator.cmdval  = true;
+        p_vci_initiator.address = (sc_dt::sc_uint<vci_param::N>)r_buf_address.read();
+        p_vci_initiator.cmd     = vci_param::CMD_READ;
+        p_vci_initiator.pktid   = TYPE_READ_DATA_UNC; // or _MISS ?
+        p_vci_initiator.wdata   = 0;
+        p_vci_initiator.be      = (uint32_t)0xF;
+        p_vci_initiator.plen    = (sc_dt::sc_uint<vci_param::K>)(r_burst_nflits.read()<<2);
+        p_vci_initiator.eop     = true;
+        break;
+    case M_READ_CMD:		// It is actually a multi-flits VCI WRITE command 
+        p_vci_initiator.rspack  = false;
+        p_vci_initiator.cmdval  = true;
+        p_vci_initiator.address = (sc_dt::sc_uint<vci_param::N>)r_buf_address.read(); 
+        p_vci_initiator.cmd     = vci_param::CMD_WRITE;
+        p_vci_initiator.pktid   = TYPE_WRITE;
+        p_vci_initiator.wdata   = (uint32_t)r_local_buffer[r_index.read()];
+        p_vci_initiator.be      = 0xF;
+        p_vci_initiator.plen    = (sc_dt::sc_uint<vci_param::K>)(r_burst_nflits.read()<<2);
+        p_vci_initiator.eop     = ( r_flit_count.read() == (r_burst_nflits.read() - 1) );
+        break;
+    case M_READ_RSP:
+    case M_WRITE_RSP:
+        p_vci_initiator.rspack  = true;
+        p_vci_initiator.cmdval  = false;
+        break;
+    default:
+        p_vci_initiator.rspack  = false;
+        p_vci_initiator.cmdval  = false;
+        break;
+    }
+
+    // IRQ signal
+    if(((r_initiator_fsm == M_READ_SUCCESS)    ||
+			    (r_initiator_fsm == M_WRITE_SUCCESS)   ||
+			    (r_initiator_fsm == M_READ_ERROR)      ||
+			    (r_initiator_fsm == M_WRITE_ERROR) ) &&  r_irq_enable) p_irq = true;
+    else			                               p_irq = false;
+} // end GenMoore()
+
+//////////////////////////////////////////////////////////////////////////////
+tmpl(/**/)::VciBlockDeviceTsarV4( sc_core::sc_module_name              name, 
+                                  const soclib::common::MappingTable   &mt,
+                                  const soclib::common::IntTab         &srcid,
+                                  const soclib::common::IntTab         &tgtid,
+                                  const std::string                    &filename,
+                                  const uint32_t                       block_size,
+                                  const uint32_t                       burst_size,
+                                  const uint32_t                       latency)
+
+: caba::BaseModule(name),
+	m_segment(mt.getSegment(tgtid)),
+	m_srcid(mt.indexForId(srcid)),
+	m_flits_per_block(block_size/vci_param::B),
+	m_flits_per_burst(burst_size/vci_param::B),
+	m_bursts_per_block(block_size/burst_size),
+	m_latency(latency),
+	p_clk("p_clk"),
+	p_resetn("p_resetn"),
+	p_vci_initiator("p_vci_initiator"),
+	p_vci_target("p_vci_target"),
+	p_irq("p_irq") 
+{
+	SC_METHOD(transition);
+	sensitive_pos << p_clk;
+
+	SC_METHOD(genMoore);
+	sensitive_neg << p_clk;
+
+	if( (block_size != 64 )  && 
+        (block_size != 128)  && 
+        (block_size != 256)  && 
+        (block_size != 512)  && 
+        (block_size != 1024) &&
+        (block_size != 2048) && 
+        (block_size != 4096) )
+	{
+		std::cout << "Error in component VciBlockDeviceTsarV4 : " << name << std::endl;
+		std::cout << "The block size must be 128, 256, 512, 1024, 2048 or 4096 bytes" << std::endl;
+		exit(1);
+	}
+	if( (burst_size != 1 ) && 
+		(burst_size != 2 ) && 
+		(burst_size != 4 ) && 
+		(burst_size != 8 ) && 
+		(burst_size != 16) && 
+		(burst_size != 32) && 
+		(burst_size != 64) )
+	{
+		std::cout << "Error in component VciBlockDeviceTsarV4 : " << name << std::endl;
+		std::cout << "The burst size must be 1, 2, 4, 8, 16, 32 or 64 bytes" << std::endl;
+		exit(1);
+	}
+	if ( m_segment.size() < 32 ) 
+	{
+		std::cout << "Error in component VciBlockDeviceTsarV4 : " << name << std::endl;
+		std::cout << "The size of the segment cannot be smaller than 32 bytes" << std::endl;
+		exit(1);
+	}
+	if ( (m_segment.baseAddress() & 0x0000001F) != 0 ) 
+	{
+		std::cout << "Error in component VciBlockDeviceTsarV4 : " << name << std::endl;
+		std::cout << "The base address of the segment must be multiple of 32 bytes" << std::endl;
+		exit(1);
+	}
+	if ( vci_param::B != 4 )
+	{
+		std::cout << "Error in component VciBlockDeviceTsarV4 : " << name << std::endl;
+		std::cout << "The VCI data fields must have 32 bits" << std::endl;
+		exit(1);
+	}
+	m_fd = ::open(filename.c_str(), O_RDWR);
+	if ( m_fd < 0 ) 
+	{
+		std::cout << "Error in component VciBlockDeviceTsarV4 : " << name << std::endl;
+		std::cout << "Unable to open file " << filename << std::endl;
+		exit(1);
+	}
+	m_device_size = lseek(m_fd, 0, SEEK_END) / block_size;
+	if ( m_device_size > ((uint64_t)1<<32) ) 
+	{
+		std::cout << "Warning: block device " << name << std::endl;
+		std::cout << "The file " << filename << std::endl;
+		std::cout << "has more blocks than addressable with the 32 bits PIBUS address" << std::endl;
+		m_device_size = ((uint64_t)1<<32);
+	}
+
+	r_local_buffer = new uint32_t[m_flits_per_block];
+
+} // end constructor
+
+//////////////////////////
+tmpl(void)::print_trace()
+{
+	const char* initiator_str[] = {
+		"IDLE",
+
+		"READ_BLOCK",
+		"READ_BURST",
+		"READ_CMD",
+		"READ_RSP",
+		"READ_TEST",
+		"READ_SUCCESS",
+		"READ_ERROR",
+
+		"WRITE_BURST",
+		"WRITE_CMD",
+		"WRITE_RSP",
+		"WRITE_BLOCK",
+		"WRITE_SUCCESS",
+		"WRITE_ERROR",
+	};
+	const char* target_str[] = {
+		"IDLE        ",
+		"WRITE_BUFFER",
+		"READ_BUFFER ",
+		"WRITE_COUNT ",
+		"READ_COUNT  ",
+		"WRITE_LBA   ",
+		"READ_LBA    ",
+		"WRITE_OP    ",
+		"READ_STATUS ",
+		"WRITE_IRQEN ",
+		"READ_IRQEN  ",
+		"READ_SIZE   ",
+		"READ_BLOCK  ",
+		"READ_ERROR  ",
+		"WRITE_ERROR ",
+	};
+
+	std::cout << "BDEV_TGT : " << target_str[r_target_fsm.read()] 
+		  << "  BDEV_INI : " << initiator_str[r_initiator_fsm.read()] 
+		  << "  block = " << r_block_count.read() 
+		  << "  burst = " << r_burst_count.read() 
+		  << "  flit  = " << r_flit_count.read() <<std::endl; 
+}
+
+
+}} // end namespace
+
+// Local Variables:
+// tab-width: 4
+// c-basic-offset: 4
+// c-file-offsets:((innamespace . 0)(inline-open . 0))
+// indent-tabs-mode: nil
+// End:
+
+// vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4
+
Index: branches/v4/modules/vci_block_device_tsar_v4/include/soclib/block_device_tsar_v4.h
===================================================================
--- branches/v4/modules/vci_block_device_tsar_v4/include/soclib/block_device_tsar_v4.h	(revision 371)
+++ branches/v4/modules/vci_block_device_tsar_v4/include/soclib/block_device_tsar_v4.h	(revision 371)
@@ -0,0 +1,66 @@
+/*
+ * SOCLIB_LGPL_HEADER_BEGIN
+ * 
+ * This file is part of SoCLib, GNU LGPLv2.1.
+ * 
+ * SoCLib is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU Lesser General Public License as published
+ * by the Free Software Foundation; version 2.1 of the License.
+ * 
+ * SoCLib is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * Lesser General Public License for more details.
+ * 
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with SoCLib; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301 USA
+ * 
+ * SOCLIB_LGPL_HEADER_END
+ *
+ * Copyright (c) UPMC, Lip6, Asim
+ *         alain greiner
+ *
+ * Maintainers: alain
+ */
+#ifndef BLOCK_DEVICE_TSAR_V4_REGS_H
+#define BLOCK_DEVICE_TSAR_V4_REGS_H
+
+enum SoclibBlockDeviceRegisters {
+    BLOCK_DEVICE_BUFFER,
+    BLOCK_DEVICE_LBA,
+    BLOCK_DEVICE_COUNT,
+    BLOCK_DEVICE_OP,
+    BLOCK_DEVICE_STATUS,
+    BLOCK_DEVICE_IRQ_ENABLE,
+    BLOCK_DEVICE_SIZE,
+    BLOCK_DEVICE_BLOCK_SIZE,
+};
+
+enum SoclibBlockDeviceOp {
+    BLOCK_DEVICE_NOOP,
+    BLOCK_DEVICE_READ,
+    BLOCK_DEVICE_WRITE,
+};
+
+enum SoclibBlockDeviceStatus {
+    BLOCK_DEVICE_IDLE,
+    BLOCK_DEVICE_BUSY,
+    BLOCK_DEVICE_READ_SUCCESS,
+    BLOCK_DEVICE_WRITE_SUCCESS,
+    BLOCK_DEVICE_READ_ERROR,
+    BLOCK_DEVICE_WRITE_ERROR,
+};
+
+#endif /* BLOCK_DEVICE_TSAR_V4_REGS_H */
+
+// Local Variables:
+// tab-width: 4
+// c-basic-offset: 4
+// c-file-offsets:((innamespace . 0)(inline-open . 0))
+// indent-tabs-mode: nil
+// End:
+
+// vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4
+
Index: branches/v4/modules/vci_cc_vcache_wrapper2/caba/metadata/vci_cc_vcache_wrapper2.sd
===================================================================
--- branches/v4/modules/vci_cc_vcache_wrapper2/caba/metadata/vci_cc_vcache_wrapper2.sd	(revision 371)
+++ branches/v4/modules/vci_cc_vcache_wrapper2/caba/metadata/vci_cc_vcache_wrapper2.sd	(revision 371)
@@ -0,0 +1,63 @@
+
+# -*- python -*-
+
+__id__ = "$Id$"
+__version__ = "$Revision$"
+
+Module('caba:vci_cc_vcache_wrapper2',
+	classname = 'soclib::caba::VciCcVCacheWrapper2',
+	   tmpl_parameters = [
+	parameter.Module('vci_param', default = 'caba:vci_param'),
+	parameter.Module('iss_t'),
+	],
+	header_files = [
+	'../source/include/vci_cc_vcache_wrapper2.h',
+	],
+	implementation_files = [
+	'../source/src/vci_cc_vcache_wrapper2.cpp',
+	],
+	uses = [
+	Uses('caba:base_module'),
+	Uses('caba:write_buffer'),
+	Uses('caba:generic_tlb', addr_t = parameter.StringExt('sc_dt::sc_uint<%d> ', parameter.Reference('addr_size'))),
+	Uses('caba:generic_cache', addr_t = parameter.StringExt('sc_dt::sc_uint<%d> ', parameter.Reference('addr_size'))),
+	Uses('common:address_masking_table', data_t = parameter.StringExt('sc_dt::sc_uint<%d> ', parameter.Reference('addr_size'))),
+	Uses('common:iss2'),
+	Uses('common:mapping_table'),
+	],
+	ports = [
+	Port('caba:vci_initiator', 'p_vci_ini'),
+	Port('caba:vci_target', 'p_vci_tgt'),
+	Port('caba:bit_in','p_irq', parameter.Constant('n_irq')),
+	Port('caba:bit_in', 'p_resetn', auto = 'resetn'),
+	Port('caba:clock_in', 'p_clk', auto = 'clock'),
+	],
+	instance_parameters = [
+	parameter.Int('proc_id'),
+	parameter.Module('mt', 'common:mapping_table'),
+	parameter.Module('mc', 'common:mapping_table'),
+	parameter.IntTab('initiator_index'),
+	parameter.IntTab('target_index'),
+    	parameter.Int('itlb_ways'),
+    	parameter.Int('itlb_sets'),
+    	parameter.Int('dtlb_ways'),
+    	parameter.Int('dtlb_sets'),
+    	parameter.Int('icache_ways'),
+    	parameter.Int('icache_sets'),
+    	parameter.Int('icache_words'),
+    	parameter.Int('dcache_ways'),
+    	parameter.Int('dcache_sets'),
+    	parameter.Int('dcache_words'),
+    	parameter.Int('write_buf_size'),
+	],
+	   extensions = [
+	'dsx:get_ident='
+        'initiator_index:p_vci_ini:mt,'
+        'target_index:p_vci_tgt:mc',
+	'dsx:cpu=wrapper:iss_t',
+	'dsx:addressable=target_index',
+    'dsx:on_segment=mc:add_index:initiator_index',
+	'dsx:mapping_type=processor:proc_id',
+   ],
+)
+
Index: branches/v4/modules/vci_cc_vcache_wrapper2/caba/source/include/vci_cc_vcache_wrapper2.h
===================================================================
--- branches/v4/modules/vci_cc_vcache_wrapper2/caba/source/include/vci_cc_vcache_wrapper2.h	(revision 371)
+++ branches/v4/modules/vci_cc_vcache_wrapper2/caba/source/include/vci_cc_vcache_wrapper2.h	(revision 371)
@@ -0,0 +1,549 @@
+/* -*- c++ -*-
+ * File : vci_cc_vcache_wrapper2.h
+ * Copyright (c) UPMC, Lip6, SoC
+ * Authors : Alain GREINER, Yang GAO
+ *
+ * SOCLIB_LGPL_HEADER_BEGIN
+ * 
+ * This file is part of SoCLib, GNU LGPLv2.1.
+ * 
+ * SoCLib is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU Lesser General Public License as published
+ * by the Free Software Foundation; version 2.1 of the License.
+ * 
+ * SoCLib is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * Lesser General Public License for more details.
+ * 
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with SoCLib; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301 USA
+ * 
+ * SOCLIB_LGPL_HEADER_END
+ */
+ 
+#ifndef SOCLIB_CABA_VCI_CC_VCACHE_WRAPPER2_H
+#define SOCLIB_CABA_VCI_CC_VCACHE_WRAPPER2_H
+
+#include <inttypes.h>
+#include <systemc>
+#include "caba_base_module.h"
+#include "write_buffer.h"
+#include "generic_cache.h"
+#include "vci_initiator.h"
+#include "vci_target.h"
+#include "mapping_table.h"
+#include "generic_tlb.h"
+#include "static_assert.h"
+
+namespace soclib {
+namespace caba {
+
+using namespace sc_core;
+
+////////////////////////////////////////////
+template<typename vci_param, typename iss_t>
+class VciCcVCacheWrapper2
+////////////////////////////////////////////
+    : public soclib::caba::BaseModule
+{
+    typedef uint32_t vaddr_t;
+    typedef uint32_t data_t;
+    typedef uint32_t tag_t;
+    typedef uint32_t type_t;
+    typedef typename iss_t::DataOperationType data_op_t;
+
+    typedef typename vci_param::addr_t  paddr_t;
+    typedef typename vci_param::be_t    vci_be_t;
+	typedef typename vci_param::srcid_t vci_srcid_t;
+	typedef typename vci_param::trdid_t vci_trdid_t;
+	typedef typename vci_param::pktid_t vci_pktid_t;
+	typedef typename vci_param::plen_t  vci_plen_t;
+
+    enum icache_fsm_state_e {  
+        ICACHE_IDLE,                // 00
+        ICACHE_BIS,                 // 01
+        ICACHE_TLB1_READ,           // 02
+        ICACHE_TLB1_WRITE,          // 03
+        ICACHE_TLB1_UPDT,           // 04
+        ICACHE_TLB2_READ,           // 05
+        ICACHE_TLB2_WRITE,          // 06
+        ICACHE_TLB2_UPDT,           // 07
+        ICACHE_SW_FLUSH,            // 08
+        ICACHE_CACHE_FLUSH,         // 09
+        ICACHE_TLB_INVAL,           // 0a
+        ICACHE_CACHE_INVAL,         // 0b
+        ICACHE_MISS_WAIT,           // 0c
+        ICACHE_UNC_WAIT,            // 0d
+        ICACHE_MISS_UPDT,           // 0e
+        ICACHE_ERROR,               // 0f
+        ICACHE_CC_INVAL,            // 10
+        ICACHE_TLB_CC_INVAL,        // 11
+        ICACHE_TLB_FLUSH,           // 12
+    };
+
+    enum dcache_fsm_state_e {  
+        DCACHE_IDLE,                // 00
+        DCACHE_BIS,                 // 01
+        DCACHE_DTLB1_READ_CACHE,    // 02
+        DCACHE_TLB1_LL_WAIT,        // 03
+        DCACHE_TLB1_SC_WAIT,        // 04
+        DCACHE_TLB1_READ,           // 05
+        DCACHE_TLB1_READ_UPDT,      // 06
+        DCACHE_TLB1_UPDT,           // 07
+        DCACHE_DTLB2_READ_CACHE,    // 08
+        DCACHE_TLB2_LL_WAIT,        // 09
+        DCACHE_TLB2_SC_WAIT,        // 0a
+        DCACHE_TLB2_READ,           // 0b
+        DCACHE_TLB2_READ_UPDT,      // 0c
+        DCACHE_TLB2_UPDT,           // 0d
+        DCACHE_CTXT_SWITCH,         // 0e
+        DCACHE_ICACHE_FLUSH,        // 0f
+        DCACHE_DCACHE_FLUSH,        // 10
+        DCACHE_ITLB_INVAL,          // 11
+        DCACHE_DTLB_INVAL,          // 12
+        DCACHE_ICACHE_INVAL,        // 13
+        DCACHE_DCACHE_INVAL,        // 14
+        DCACHE_DCACHE_SYNC,         // 15
+        DCACHE_LL_DIRTY_WAIT,       // 16
+        DCACHE_SC_DIRTY_WAIT,       // 17
+        DCACHE_WRITE_UPDT,          // 18
+        DCACHE_WRITE_DIRTY,         // 19
+        DCACHE_WRITE_REQ,           // 1a
+        DCACHE_MISS_WAIT,           // 1b
+        DCACHE_MISS_UPDT,           // 1c
+        DCACHE_UNC_WAIT,            // 1d
+        DCACHE_ERROR,               // 1e
+        DCACHE_ITLB_READ,           // 1f
+        DCACHE_ITLB_UPDT,           // 20
+        DCACHE_ITLB_LL_WAIT,        // 21
+        DCACHE_ITLB_SC_WAIT,        // 22
+        DCACHE_CC_CHECK,            // 23
+        DCACHE_CC_INVAL,            // 24
+        DCACHE_CC_UPDT,             // 25
+        DCACHE_CC_NOP,              // 26
+        DCACHE_TLB_CC_INVAL,        // 27
+        DCACHE_ITLB_CLEANUP,        // 28
+    };
+
+    enum cmd_fsm_state_e {      
+        CMD_IDLE,                   // 00
+        CMD_ITLB_READ,              // 01
+        CMD_ITLB_ACC_LL,            // 02
+        CMD_ITLB_ACC_SC,            // 03
+        CMD_INS_MISS,               // 04
+        CMD_INS_UNC,                // 05
+        CMD_DTLB_READ,              // 06
+        CMD_DTLB_ACC_LL,            // 07
+        CMD_DTLB_ACC_SC,            // 08
+        CMD_DTLB_DIRTY_LL,          // 09
+        CMD_DTLB_DIRTY_SC,          // 0a
+        CMD_DATA_UNC,               // 0b
+        CMD_DATA_MISS,              // 0c
+        CMD_DATA_WRITE,             // 0d
+        CMD_INS_CLEANUP,            // 0e
+        CMD_DATA_CLEANUP,           // 0f
+    };
+
+    enum rsp_fsm_state_e {       
+        RSP_IDLE,                   // 00
+        RSP_ITLB_READ,              // 01
+        RSP_ITLB_ACC_LL,            // 02
+        RSP_ITLB_ACC_SC,            // 03
+        RSP_INS_MISS,               // 04
+        RSP_INS_UNC,                // 05
+        RSP_DTLB_READ,              // 06
+        RSP_DTLB_ACC_LL,            // 07
+        RSP_DTLB_ACC_SC,            // 08
+        RSP_DTLB_DIRTY_LL,          // 09
+        RSP_DTLB_DIRTY_SC,          // 0a
+        RSP_DATA_MISS,              // 0b
+        RSP_DATA_UNC,               // 0c
+        RSP_DATA_WRITE,             // 0d
+        RSP_INS_CLEANUP,            // 0e
+        RSP_DATA_CLEANUP,           // 0f
+    };
+
+    enum tgt_fsm_state_e {  
+        TGT_IDLE,                   // 00
+        TGT_UPDT_WORD,              // 01
+        TGT_UPDT_DATA,              // 02
+        TGT_REQ_BROADCAST,          // 03
+        TGT_REQ_DCACHE,             // 04
+        TGT_RSP_BROADCAST,          // 05
+        TGT_RSP_DCACHE,             // 06
+    };
+
+    enum inval_itlb_fsm_state_e {
+        INVAL_ITLB_IDLE,            // 00
+        INVAL_ITLB_CHECK,           // 01
+        INVAL_ITLB_INVAL,           // 02
+        INVAL_ITLB_CLEAR,           // 03
+    };
+
+    enum inval_dtlb_fsm_state_e {
+        INVAL_DTLB_IDLE,            // 00
+        INVAL_DTLB_CHECK,           // 01
+        INVAL_DTLB_INVAL,           // 02
+        INVAL_DTLB_CLEAR,           // 03
+    };
+
+    // TLB Mode ITLB / DTLB / ICACHE / DCACHE
+    enum {          
+        ALL_DEACTIVE = 0x0000,   // TLBs disactive caches disactive
+        INS_TLB_MASK    = 0x8,
+        DATA_TLB_MASK   = 0x4,
+        INS_CACHE_MASK  = 0x2,
+        DATA_CACHE_MASK = 0x1,
+    };
+
+    // Error Type
+    enum mmu_error_type_e {
+        MMU_NONE                      = 0x0000, // None
+        MMU_WRITE_PT1_UNMAPPED 	      = 0x0001, // Write access of Page fault on Page Table 1          (non fatal error)
+        MMU_WRITE_PT2_UNMAPPED 	      = 0x0002, // Write access of Page fault on Page Table 2          (non fatal error)
+        MMU_WRITE_PRIVILEGE_VIOLATION = 0x0004, // Write access of Protected access in user mode       (user error)
+        MMU_WRITE_ACCES_VIOLATION 	  = 0x0008, // Write access of write access to a non writable page (user error)
+        MMU_WRITE_UNDEFINED_XTN 	  = 0x0020, // Write access of undefined external access address   (user error)
+        MMU_WRITE_PT1_ILLEGAL_ACCESS  = 0x0040, // Write access of Bus Error accessing Table 1         (kernel error)
+        MMU_WRITE_PT2_ILLEGAL_ACCESS  = 0x0080, // Write access of Bus Error accessing Table 2         (kernel error)
+        MMU_WRITE_DATA_ILLEGAL_ACCESS = 0x0100, // Write access of Bus Error in cache access           (kernel error)
+        MMU_READ_PT1_UNMAPPED 	      = 0x1001, // Read access of Page fault on Page Table 1  	       (non fatal error)
+        MMU_READ_PT2_UNMAPPED 	      = 0x1002, // Read access of Page fault on Page Table 2  	       (non fatal error)
+        MMU_READ_PRIVILEGE_VIOLATION  = 0x1004, // Read access of Protected access in user mode 	   (user error)
+        MMU_READ_EXEC_VIOLATION 	  = 0x1010, // Exec access to a non exec page                      (user error)
+        MMU_READ_UNDEFINED_XTN 	      = 0x1020, // Read access of Undefined external access address    (user error)
+        MMU_READ_PT1_ILLEGAL_ACCESS   = 0x1040, // Read access of Bus Error in Table1 access           (kernel error)
+        MMU_READ_PT2_ILLEGAL_ACCESS   = 0x1080, // Read access of Bus Error in Table2 access 	       (kernel error)
+        MMU_READ_DATA_ILLEGAL_ACCESS  = 0x1100, // Read access of Bus Error in cache access 	       (kernel error)
+    };
+
+public:
+    sc_in<bool>                             p_clk;
+    sc_in<bool>                             p_resetn;
+    sc_in<bool>                             p_irq[iss_t::n_irq];
+    soclib::caba::VciInitiator<vci_param>   p_vci_ini;
+    soclib::caba::VciTarget<vci_param>      p_vci_tgt;
+
+private:
+    // STRUCTURAL PARAMETERS
+    soclib::common::AddressDecodingTable<uint32_t, bool>    m_cacheability_table;
+    const soclib::common::Segment                           m_segment;
+    iss_t                                                   m_iss;   
+    const vci_srcid_t                                       m_srcid;
+
+    const size_t  m_itlb_ways;
+    const size_t  m_itlb_sets;
+
+    const size_t  m_dtlb_ways;
+    const size_t  m_dtlb_sets;
+
+    const size_t  m_icache_ways;
+    const size_t  m_icache_sets;
+    const size_t  m_icache_yzmask;
+    const size_t  m_icache_words;
+
+    const size_t  m_dcache_ways;
+    const size_t  m_dcache_sets;
+    const size_t  m_dcache_yzmask;
+    const size_t  m_dcache_words;
+
+    const size_t  m_write_buf_size;  
+    const size_t  m_paddr_nbits;  
+
+    // instruction and data vcache tlb instances 
+    soclib::caba::GenericCcTlb<paddr_t>    icache_tlb;
+    soclib::caba::GenericCcTlb<paddr_t>    dcache_tlb;
+
+    sc_signal<vaddr_t>      r_mmu_ptpr;             // page table pointer register
+    sc_signal<int>          r_mmu_mode;             // tlb mode register
+    sc_signal<int>          r_mmu_params;           // mmu parameters register
+    sc_signal<int>          r_mmu_release;          // mmu release register
+
+    // DCACHE FSM REGISTERS
+    sc_signal<int>          r_dcache_fsm;               // state register
+    sc_signal<paddr_t>      r_dcache_paddr_save;        // physical address
+    sc_signal<data_t>       r_dcache_wdata_save;        // write data
+    sc_signal<data_t>       r_dcache_rdata_save;        // read data
+    sc_signal<type_t>       r_dcache_type_save;         // access type
+    sc_signal<vci_be_t>     r_dcache_be_save;           // byte enable
+    sc_signal<bool>         r_dcache_cached_save;       // used by the write buffer
+    sc_signal<paddr_t>      r_dcache_tlb_paddr;         // physical address of tlb miss
+    sc_signal<bool>         r_dcache_dirty_save;        // used for TLB dirty bit update
+    sc_signal<size_t>       r_dcache_tlb_set_save;      // used for TLB dirty bit update
+    sc_signal<size_t>       r_dcache_tlb_way_save;      // used for TLB dirty bit update
+    sc_signal<vaddr_t>      r_dcache_id1_save;          // used by the PT1 bypass
+    sc_signal<paddr_t>      r_dcache_ptba_save;         // used by the PT1 bypass
+    sc_signal<bool>         r_dcache_ptba_ok;           // used by the PT1 bypass
+    sc_signal<data_t>       r_dcache_pte_update;        // used for page table update
+    sc_signal<data_t>       r_dcache_ppn_update;        // used for physical page number update 
+    sc_signal<tag_t>        r_dcache_ppn_save;          // used for speculative cache access
+    sc_signal<tag_t>        r_dcache_vpn_save;          // used for speculative cache access
+    sc_signal<bool>         r_dtlb_translation_valid;   // used for speculative address
+    sc_signal<bool>         r_dcache_buf_unc_valid;     // used for uncached read
+    sc_signal<bool>         r_dcache_hit_p_save;        // used to save hit_p in case BIS
+
+    sc_signal<data_t>       r_dcache_error_type;        // software visible register
+    sc_signal<vaddr_t>      r_dcache_bad_vaddr;         // software visible register 
+
+    sc_signal<bool>         r_dcache_miss_req;          // used for cached read miss
+    sc_signal<bool>         r_dcache_unc_req;           // used for uncached read miss
+    sc_signal<bool>         r_dcache_write_req;         // used for write 
+    sc_signal<bool>         r_dcache_tlb_read_req;      // used for tlb ptba or pte read
+
+    sc_signal<bool>         r_dcache_llsc_reserved;     // used for check address reserved
+    sc_signal<paddr_t>      r_dcache_llsc_addr_save;    // used for save llsc address
+ 
+    sc_signal<bool>         r_dcache_tlb_ll_acc_req;    // used for tlb access bit update
+    sc_signal<bool>         r_dcache_tlb_sc_acc_req;    // used for tlb access bit update
+    sc_signal<bool>         r_dcache_tlb_ll_dirty_req;  // used for tlb dirty bit update 
+    sc_signal<bool>         r_dcache_tlb_sc_dirty_req;  // used for tlb dirty bit update 
+    sc_signal<bool>         r_dcache_tlb_ptba_read;     // used for tlb ptba read when write dirty bit 
+    sc_signal<bool>         r_dcache_xtn_req;           // used for xtn write for ICACHE
+
+    bool                    *r_dcache_in_itlb;          // indicates some words of dcache line in ins TLB 
+    bool                    *r_dcache_in_dtlb;          // indicates some words of dcache line in data TLB 
+
+    // coherence registers
+    sc_signal<int>          r_dcache_fsm_save;          // state save register
+    sc_signal<size_t>       r_dcache_way;
+    sc_signal<size_t>       r_dcache_set;
+    sc_signal<bool>         r_dcache_cleanup_req;       // data cleanup request
+    sc_signal<paddr_t>      r_dcache_cleanup_line;      // data cleanup NLINE
+    sc_signal<bool>         r_dcache_inval_rsp;         // data cache invalidate
+
+    // ICACHE FSM REGISTERS
+    sc_signal<int>          r_icache_fsm;               // state register
+    sc_signal<paddr_t>      r_icache_paddr_save;        // physical address
+    sc_signal<vaddr_t>      r_icache_id1_save;          // used by the PT1 bypass
+    sc_signal<paddr_t>      r_icache_ptba_save;         // used by the PT1 bypass
+    sc_signal<bool>         r_icache_ptba_ok;           // used by the PT1 bypass
+    sc_signal<data_t>       r_icache_pte_update;        // used for page table update
+    sc_signal<tag_t>        r_icache_ppn_save;          // used for speculative cache access
+    sc_signal<tag_t>        r_icache_vpn_save;          // used for speculative cache access
+    sc_signal<bool>         r_itlb_translation_valid;   // used for speculative physical address
+    sc_signal<bool>         r_icache_buf_unc_valid;     // used for uncached read
+
+    sc_signal<data_t>       r_icache_error_type;        // software visible registers
+    sc_signal<vaddr_t>      r_icache_bad_vaddr;         // software visible registers
+
+    sc_signal<bool>         r_icache_miss_req;          // used for cached read miss
+    sc_signal<bool>         r_icache_unc_req;           // used for uncached read miss
+    sc_signal<bool>         r_dcache_itlb_read_req;     // used for tlb ptba or pte read 
+
+    sc_signal<bool>         r_dcache_itlb_ll_acc_req;   // used for tlb access bit update
+    sc_signal<bool>         r_dcache_itlb_sc_acc_req;   // used for tlb access bit update
+
+    sc_signal<bool>	        r_itlb_read_dcache_req;     // used for instruction tlb miss, request in data cache
+    sc_signal<bool>	        r_itlb_acc_dcache_req;          // used for itlb update access bit via dcache
+    sc_signal<bool>	        r_dcache_rsp_itlb_error;        // used for data cache rsp error when itlb miss
+    sc_signal<data_t>	    r_dcache_rsp_itlb_miss;	        // used for dcache rsp data when itlb miss
+    sc_signal<data_t>	    r_dcache_rsp_itlb_ppn;	        // used for dcache rsp ppn when itlb miss
+
+    // coherence registers
+    sc_signal<int>          r_icache_fsm_save;          // state save register
+    sc_signal<size_t>       r_icache_way;
+    sc_signal<size_t>       r_icache_set;
+    sc_signal<bool>         r_icache_cleanup_req;       // ins cleanup request
+    sc_signal<paddr_t>      r_icache_cleanup_line;      // ins cleanup NLINE
+    sc_signal<bool>         r_icache_inval_rsp;         // ins cache invalidate
+
+    // VCI_CMD FSM REGISTERS
+    sc_signal<int>          r_vci_cmd_fsm;
+    sc_signal<size_t>       r_vci_cmd_min;       
+    sc_signal<size_t>       r_vci_cmd_max;       
+    sc_signal<size_t>       r_vci_cmd_cpt;     
+
+    // VCI_RSP FSM REGISTERS
+    sc_signal<int>          r_vci_rsp_fsm;
+    sc_signal<size_t>       r_vci_rsp_cpt;
+    sc_signal<bool>         r_vci_rsp_ins_error;
+    sc_signal<bool>         r_vci_rsp_data_error;
+
+    data_t                  *r_icache_miss_buf;    
+    data_t                  *r_dcache_miss_buf;  
+
+    // VCI_TGT FSM REGISTERS
+    data_t                  *r_tgt_buf;
+    bool                    *r_tgt_val;
+
+    sc_signal<int>          r_vci_tgt_fsm;
+    sc_signal<paddr_t>      r_tgt_addr;
+    sc_signal<size_t>       r_tgt_word;
+    sc_signal<bool>         r_tgt_update;
+    sc_signal<vci_srcid_t>  r_tgt_srcid;
+    sc_signal<vci_pktid_t>  r_tgt_pktid;
+    sc_signal<vci_trdid_t>  r_tgt_trdid;
+    sc_signal<vci_plen_t>   r_tgt_plen;
+    sc_signal<bool>         r_tgt_req;
+    sc_signal<bool>         r_tgt_icache_req;
+    sc_signal<bool>         r_tgt_dcache_req;
+    sc_signal<bool>         r_tgt_icache_rsp;
+    sc_signal<bool>         r_tgt_dcache_rsp;
+
+    // INVAL CHECK FSM
+    sc_signal<int>          r_inval_itlb_fsm;          
+    sc_signal<bool>         r_dcache_itlb_inval_req;
+    sc_signal<paddr_t>      r_dcache_itlb_inval_line;
+    sc_signal<bool>         r_itlb_cc_check_end;
+    sc_signal<size_t>       r_ccinval_itlb_way; 
+    sc_signal<size_t>       r_ccinval_itlb_set; 
+    sc_signal<bool>         r_icache_inval_tlb_rsp;
+    sc_signal<paddr_t>      r_icache_tlb_nline;
+
+    sc_signal<int>          r_inval_dtlb_fsm;          
+    sc_signal<bool>         r_dcache_dtlb_inval_req;
+    sc_signal<paddr_t>      r_dcache_dtlb_inval_line;
+    sc_signal<bool>         r_dtlb_cc_check_end;
+    sc_signal<size_t>       r_ccinval_dtlb_way; 
+    sc_signal<size_t>       r_ccinval_dtlb_set; 
+    sc_signal<bool>         r_dcache_inval_tlb_rsp;
+    sc_signal<paddr_t>      r_dcache_tlb_nline;
+
+    sc_signal<bool>         r_dcache_itlb_cleanup_req;
+    sc_signal<paddr_t>      r_dcache_itlb_cleanup_line;
+
+    sc_signal<bool>         r_dcache_dtlb_cleanup_req;
+    sc_signal<paddr_t>      r_dcache_dtlb_cleanup_line;
+
+    sc_signal<bool>         r_itlb_inval_req;
+    sc_signal<bool>         r_dcache_cc_check;
+
+    WriteBuffer<paddr_t>     r_wbuf;
+    GenericCache<paddr_t>    r_icache;
+    GenericCache<paddr_t>    r_dcache;
+
+    // Activity counters
+    uint32_t m_cpt_dcache_data_read;        // DCACHE DATA READ
+    uint32_t m_cpt_dcache_data_write;       // DCACHE DATA WRITE
+    uint32_t m_cpt_dcache_dir_read;         // DCACHE DIR READ
+    uint32_t m_cpt_dcache_dir_write;        // DCACHE DIR WRITE
+
+    uint32_t m_cpt_icache_data_read;        // ICACHE DATA READ
+    uint32_t m_cpt_icache_data_write;       // ICACHE DATA WRITE
+    uint32_t m_cpt_icache_dir_read;         // ICACHE DIR READ
+    uint32_t m_cpt_icache_dir_write;        // ICACHE DIR WRITE
+
+    uint32_t m_cpt_frz_cycles;	            // number of cycles where the cpu is frozen
+    uint32_t m_cpt_total_cycles;	        // total number of cycles 
+
+    // Cache activity counters
+    uint32_t m_cpt_read;                    // total number of read data
+    uint32_t m_cpt_write;                   // total number of write data
+    uint32_t m_cpt_data_miss;               // number of read miss
+    uint32_t m_cpt_ins_miss;                // number of instruction miss
+    uint32_t m_cpt_unc_read;                // number of read uncached
+    uint32_t m_cpt_write_cached;            // number of cached write
+    uint32_t m_cpt_ins_read;                // number of instruction read
+
+    uint32_t m_cost_write_frz;              // number of frozen cycles related to write buffer         
+    uint32_t m_cost_data_miss_frz;          // number of frozen cycles related to data miss
+    uint32_t m_cost_unc_read_frz;           // number of frozen cycles related to uncached read
+    uint32_t m_cost_ins_miss_frz;           // number of frozen cycles related to ins miss
+
+    uint32_t m_cpt_imiss_transaction;       // number of VCI instruction miss transactions
+    uint32_t m_cpt_dmiss_transaction;       // number of VCI data miss transactions
+    uint32_t m_cpt_unc_transaction;         // number of VCI uncached read transactions
+    uint32_t m_cpt_write_transaction;       // number of VCI write transactions
+
+    uint32_t m_cost_imiss_transaction;      // cumulated duration for VCI IMISS transactions
+    uint32_t m_cost_dmiss_transaction;      // cumulated duration for VCI DMISS transactions
+    uint32_t m_cost_unc_transaction;        // cumulated duration for VCI UNC transactions
+    uint32_t m_cost_write_transaction;      // cumulated duration for VCI WRITE transactions
+    uint32_t m_length_write_transaction;    // cumulated length for VCI WRITE transactions
+
+    // TLB activity counters
+    uint32_t m_cpt_ins_tlb_read;            // number of instruction tlb read
+    uint32_t m_cpt_ins_tlb_miss;            // number of instruction tlb miss
+    uint32_t m_cpt_ins_tlb_write_et;        // number of instruction tlb write ET
+
+    uint32_t m_cpt_data_tlb_read;           // number of data tlb read
+    uint32_t m_cpt_data_tlb_miss;           // number of data tlb miss
+    uint32_t m_cpt_data_tlb_write_et;       // number of data tlb write ET
+    uint32_t m_cpt_data_tlb_write_dirty;    // number of data tlb write dirty
+    
+    uint32_t m_cost_ins_tlb_miss_frz;       // number of frozen cycles related to instruction tlb miss
+    uint32_t m_cost_data_tlb_miss_frz;      // number of frozen cycles related to data tlb miss
+
+    uint32_t m_cost_ins_waste_wait_frz;     // number of frozen cycles related to ins wait coherence operate 
+    uint32_t m_cost_ins_tlb_sw_frz;         // number of frozen cycles related to ins context switch
+    uint32_t m_cost_ins_cache_flush_frz;    // number of frozen cycles related to ins cache flush 
+
+    uint32_t m_cpt_ins_tlb_cleanup;         // number of ins tlb cleanup 
+    uint32_t m_cost_data_waste_wait_frz;    // number of frozen cycles related to data wait coherence operate
+    uint32_t m_cost_data_tlb_sw_frz;        // number of frozen cycles related to data context switch
+    uint32_t m_cost_data_cache_flush_frz;   // number of frozen cycles related to data cache flush
+
+    uint32_t m_cpt_itlbmiss_transaction;    // number of itlb miss transactions
+    uint32_t m_cpt_itlb_write_transaction;  // number of itlb write ET transactions
+    uint32_t m_cpt_dtlbmiss_transaction;    // number of dtlb miss transactions
+    uint32_t m_cpt_dtlb_write_transaction;  // number of dtlb write ET and dirty transactions
+
+    uint32_t m_cost_itlbmiss_transaction;   // cumulated duration for VCI instruction TLB miss transactions
+    uint32_t m_cost_itlb_write_transaction; // cumulated duration for VCI instruction TLB write ET transactions
+    uint32_t m_cost_dtlbmiss_transaction;   // cumulated duration for VCI data TLB miss transactions
+    uint32_t m_cost_dtlb_write_transaction; // cumulated duration for VCI data TLB write transactions
+
+    uint32_t m_cpt_cc_update;               // number of coherence update packets 
+    uint32_t m_cpt_cc_inval;                // number of coherence inval packets
+    uint32_t m_cpt_cc_broadcast;            // number of coherence broadcast packets
+
+    uint32_t m_cost_ins_tlb_inval_frz;      // number of frozen cycles related to checking ins tlb invalidate
+    uint32_t m_cpt_ins_tlb_inval;           // number of ins tlb invalidate
+
+    uint32_t m_cost_data_tlb_inval_frz;     // number of frozen cycles related to checking data tlb invalidate    
+    uint32_t m_cpt_data_tlb_inval;          // number of data tlb invalidate
+
+protected:
+    SC_HAS_PROCESS(VciCcVCacheWrapper2);
+
+public:
+    VciCcVCacheWrapper2(
+        sc_module_name insname,
+        int proc_id,
+        const soclib::common::MappingTable &mtp,
+        const soclib::common::MappingTable &mtc,
+        const soclib::common::IntTab &initiator_index,
+        const soclib::common::IntTab &target_index,
+        size_t itlb_ways,
+        size_t itlb_sets,
+        size_t dtlb_ways,
+        size_t dtlb_sets,
+        size_t icache_ways,
+        size_t icache_sets,
+        size_t icache_words,
+        size_t dcache_ways,
+        size_t dcache_sets,
+        size_t dcache_words,
+        size_t write_buf_size );
+
+    ~VciCcVCacheWrapper2();
+
+    void print_cpi();
+    void print_stats();
+
+private:
+    void transition();
+    void genMoore();
+
+    soclib_static_assert((int)iss_t::SC_ATOMIC == (int)vci_param::STORE_COND_ATOMIC);
+    soclib_static_assert((int)iss_t::SC_NOT_ATOMIC == (int)vci_param::STORE_COND_NOT_ATOMIC);
+};
+
+}}
+
+#endif /* SOCLIB_CABA_VCI_CC_VCACHE_WRAPPER2_H */
+
+// Local Variables:
+// tab-width: 4
+// c-basic-offset: 4
+// c-file-offsets:((innamespace . 0)(inline-open . 0))
+// indent-tabs-mode: nil
+// End:
+
+// vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4
+
+
+
Index: branches/v4/modules/vci_cc_vcache_wrapper2/caba/source/src/vci_cc_vcache_wrapper2.cpp
===================================================================
--- branches/v4/modules/vci_cc_vcache_wrapper2/caba/source/src/vci_cc_vcache_wrapper2.cpp	(revision 371)
+++ branches/v4/modules/vci_cc_vcache_wrapper2/caba/source/src/vci_cc_vcache_wrapper2.cpp	(revision 371)
@@ -0,0 +1,5426 @@
+/* -*- c++ -*-
+ * File : vci_cc_vcache_wrapper2.cpp
+ * Copyright (c) UPMC, Lip6, SoC
+ * Authors : Alain GREINER, Yang GAO
+ *
+ * SOCLIB_LGPL_HEADER_BEGIN
+ * 
+ * This file is part of SoCLib, GNU LGPLv2.1.
+ * 
+ * SoCLib is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU Lesser General Public License as published
+ * by the Free Software Foundation; version 2.1 of the License.
+ * 
+ * SoCLib is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * Lesser General Public License for more details.
+ * 
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with SoCLib; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301 USA
+ * 
+ * SOCLIB_LGPL_HEADER_END
+ */
+
+#include <cassert>
+#include "arithmetics.h"
+#include "../include/vci_cc_vcache_wrapper2.h"
+
+namespace soclib { 
+namespace caba {
+
+#ifdef SOCLIB_MODULE_DEBUG
+namespace {
+const char *icache_fsm_state_str[] = {
+        "ICACHE_IDLE",
+        "ICACHE_BIS",       
+        "ICACHE_TLB1_READ",  
+        "ICACHE_TLB1_WRITE",  
+        "ICACHE_TLB1_UPDT",  
+        "ICACHE_TLB2_READ",  
+        "ICACHE_TLB2_WRITE",  
+        "ICACHE_TLB2_UPDT",  
+        "ICACHE_SW_FLUSH", 
+        "ICACHE_CACHE_FLUSH", 
+        "ICACHE_TLB_INVAL",  
+        "ICACHE_CACHE_INVAL",
+        "ICACHE_MISS_WAIT",
+        "ICACHE_UNC_WAIT",  
+        "ICACHE_MISS_UPDT",  
+        "ICACHE_ERROR", 	
+        "ICACHE_CC_INVAL", 
+        "ICACHE_TLB_CC_INVAL",        
+        "ICACHE_TLB_FLUSH", 
+    };
+const char *dcache_fsm_state_str[] = {
+        "DCACHE_IDLE",       
+        "DCACHE_BIS",   
+        "DCACHE_DTLB1_READ_CACHE",
+	"DCACHE_TLB1_LL_WAIT",
+	"DCACHE_TLB1_SC_WAIT",    
+        "DCACHE_TLB1_READ",
+        "DCACHE_TLB1_READ_UPDT",  
+        "DCACHE_TLB1_UPDT", 
+        "DCACHE_DTLB2_READ_CACHE", 
+	"DCACHE_TLB2_LL_WAIT",
+	"DCACHE_TLB2_SC_WAIT",   
+        "DCACHE_TLB2_READ",
+        "DCACHE_TLB2_READ_UPDT",  
+        "DCACHE_TLB2_UPDT",   
+        "DCACHE_CTXT_SWITCH",   
+        "DCACHE_ICACHE_FLUSH", 
+        "DCACHE_DCACHE_FLUSH", 
+        "DCACHE_ITLB_INVAL",
+        "DCACHE_DTLB_INVAL",
+        "DCACHE_ICACHE_INVAL",
+        "DCACHE_DCACHE_INVAL",
+	"DCACHE_DCACHE_SYNC",
+	"DCACHE_LL_DIRTY_WAIT",
+	"DCACHE_SC_DIRTY_WAIT",
+        "DCACHE_WRITE_UPDT", 
+        "DCACHE_WRITE_DIRTY",
+        "DCACHE_WRITE_REQ",  
+        "DCACHE_MISS_WAIT",  
+        "DCACHE_MISS_UPDT",  
+        "DCACHE_UNC_WAIT",   
+        "DCACHE_ERROR", 
+        "DCACHE_ITLB_READ",
+        "DCACHE_ITLB_UPDT",
+        "DCACHE_ITLB_LL_WAIT",        
+        "DCACHE_ITLB_SC_WAIT",        
+        "DCACHE_CC_CHECK",
+        "DCACHE_CC_INVAL",
+        "DCACHE_CC_UPDT",
+        "DCACHE_CC_NOP",
+        "DCACHE_TLB_CC_INVAL",
+        "DCACHE_ITLB_CLEANUP",
+    };
+const char *cmd_fsm_state_str[] = {
+        "CMD_IDLE",           
+        "CMD_ITLB_READ", 
+        "CMD_ITLB_ACC_LL",                
+        "CMD_ITLB_ACC_SC",                
+        "CMD_INS_MISS",     
+        "CMD_INS_UNC",     
+        "CMD_DTLB_READ",   
+        "CMD_DTLB_ACC_LL",            
+        "CMD_DTLB_ACC_SC",            
+        "CMD_DTLB_DIRTY_LL",          
+        "CMD_DTLB_DIRTY_SC",          
+        "CMD_DATA_UNC",     
+        "CMD_DATA_MISS",    
+        "CMD_DATA_WRITE", 
+        "CMD_INS_CLEANUP",    
+        "CMD_DATA_CLEANUP",      
+    };
+const char *rsp_fsm_state_str[] = {
+        "RSP_IDLE",                  
+        "RSP_ITLB_READ",             
+        "RSP_ITLB_ACC_LL",                
+        "RSP_ITLB_ACC_SC",                
+        "RSP_INS_MISS",   
+        "RSP_INS_UNC",           
+        "RSP_DTLB_READ",            
+        "RSP_DTLB_ACC_LL",            
+        "RSP_DTLB_ACC_SC",            
+        "RSP_DTLB_DIRTY_LL",          
+        "RSP_DTLB_DIRTY_SC",          
+        "RSP_DATA_MISS",             
+        "RSP_DATA_UNC",              
+        "RSP_DATA_WRITE",     
+        "RSP_INS_CLEANUP",    
+        "RSP_DATA_CLEANUP",        
+    };
+const char *tgt_fsm_state_str[] = {
+        "TGT_IDLE",
+        "TGT_UPDT_WORD",
+        "TGT_UPDT_DATA",
+        "TGT_REQ_BROADCAST",
+        "TGT_REQ_DCACHE",
+        "TGT_RSP_BROADCAST",
+        "TGT_RSP_DCACHE",
+    };	
+const char *inval_itlb_fsm_state_str[] = {
+        "INVAL_ITLB_IDLE",        
+        "INVAL_ITLB_CHECK"  , 
+        "INVAL_ITLB_INVAL",      
+        "INVAL_ITLB_CLEAR",           
+    };
+const char *inval_dtlb_fsm_state_str[] = {
+        "INVAL_DTLB_IDLE",        
+        "INVAL_DTLB_CHECK", 
+        "INVAL_DTLB_INVAL",    
+        "INVAL_DTLB_CLEAR",         
+    };
+}
+#endif
+
+#define tmpl(...)  template<typename vci_param, typename iss_t> __VA_ARGS__ VciCcVCacheWrapper2<vci_param, iss_t>
+
+using soclib::common::uint32_log2;
+
+/***********************************************/
+tmpl(/**/)::VciCcVCacheWrapper2(
+    sc_module_name name,
+    int proc_id,
+    const soclib::common::MappingTable &mtp,
+    const soclib::common::MappingTable &mtc,
+    const soclib::common::IntTab &initiator_index,
+    const soclib::common::IntTab &target_index,
+    size_t itlb_ways,
+    size_t itlb_sets,
+    size_t dtlb_ways,
+    size_t dtlb_sets,
+    size_t icache_ways,
+    size_t icache_sets,
+    size_t icache_words,
+    size_t dcache_ways,
+    size_t dcache_sets,
+    size_t dcache_words,
+    size_t write_buf_size )
+/***********************************************/
+    : soclib::caba::BaseModule(name),
+
+      p_clk("clk"),
+      p_resetn("resetn"),
+      p_vci_ini("vci_ini"),
+      p_vci_tgt("vci_tgt"),
+
+      m_cacheability_table(mtp.getCacheabilityTable()),
+      m_segment(mtc.getSegment(target_index)),
+      m_iss(this->name(), proc_id),
+      m_srcid(mtp.indexForId(initiator_index)),
+
+      m_itlb_ways(itlb_ways),
+      m_itlb_sets(itlb_sets),
+
+      m_dtlb_ways(dtlb_ways),
+      m_dtlb_sets(dtlb_sets),
+
+      m_icache_ways(icache_ways),
+      m_icache_sets(icache_sets),
+      m_icache_yzmask((~0)<<(uint32_log2(icache_words) + 2)),
+      m_icache_words(icache_words),
+
+      m_dcache_ways(dcache_ways),
+      m_dcache_sets(dcache_sets),
+      m_dcache_yzmask((~0)<<(uint32_log2(dcache_words) + 2)),
+      m_dcache_words(dcache_words),
+
+      m_write_buf_size(write_buf_size),	
+      m_paddr_nbits(vci_param::N),
+
+      icache_tlb(itlb_ways,itlb_sets,vci_param::N),
+      dcache_tlb(dtlb_ways,dtlb_sets,vci_param::N),
+
+      r_dcache_fsm("r_dcache_fsm"),
+      r_dcache_paddr_save("r_dcache_paddr_save"),
+      r_dcache_wdata_save("r_dcache_wdata_save"),
+      r_dcache_rdata_save("r_dcache_rdata_save"),
+      r_dcache_type_save("r_dcache_type_save"),
+      r_dcache_be_save("r_dcache_be_save"),
+      r_dcache_cached_save("r_dcache_cached_save"),
+      r_dcache_tlb_paddr("r_dcache_tlb_paddr"),
+      r_dcache_miss_req("r_dcache_miss_req"),
+      r_dcache_unc_req("r_dcache_unc_req"),
+      r_dcache_write_req("r_dcache_write_req"),
+      r_dcache_tlb_read_req("r_dcache_tlb_read_req"),
+
+      r_dcache_tlb_ll_acc_req("r_dcache_tlb_ll_acc_req"),       
+      r_dcache_tlb_sc_acc_req("r_dcache_tlb_sc_acc_req"),       
+      r_dcache_tlb_ll_dirty_req("r_dcache_tlb_ll_dirty_req"),    
+      r_dcache_tlb_sc_dirty_req("r_dcache_tlb_sc_dirty_req"), 
+      r_dcache_tlb_ptba_read("r_dcache_tlb_ptba_read"),
+      r_dcache_xtn_req("r_dcache_xtn_req"),
+
+      r_dcache_fsm_save("r_dcache_fsm_save"),
+      r_dcache_cleanup_req("r_dcache_cleanup_req"),
+      r_dcache_inval_rsp("r_dcache_inval_rsp"),
+
+      r_icache_fsm("r_icache_fsm"),
+      r_icache_paddr_save("r_icache_paddr_save"),
+      r_icache_miss_req("r_icache_miss_req"),
+      r_icache_unc_req("r_icache_unc_req"),
+      r_dcache_itlb_read_req("r_dcache_itlb_read_req"),
+      r_dcache_itlb_ll_acc_req("r_dcache_itlb_ll_acc_req"),     
+      r_dcache_itlb_sc_acc_req("r_dcache_itlb_sc_acc_req"),
+
+      r_itlb_read_dcache_req("r_itlb_read_dcache_req"),
+      r_itlb_acc_dcache_req("r_itlb_acc_dcache_req"),
+      r_dcache_rsp_itlb_error("r_dcache_rsp_itlb_error"),
+
+      r_icache_fsm_save("r_icache_fsm_save"),
+      r_icache_cleanup_req("r_icache_cleanup_req"),
+      r_icache_inval_rsp("r_icache_inval_rsp"),
+
+      r_vci_cmd_fsm("r_vci_cmd_fsm"),
+      r_vci_cmd_min("r_vci_cmd_min"),
+      r_vci_cmd_max("r_vci_cmd_max"),
+      r_vci_cmd_cpt("r_vci_cmd_cpt"),
+
+      r_vci_rsp_fsm("r_vci_rsp_fsm"),
+      r_vci_rsp_cpt("r_vci_rsp_cpt"),
+      r_vci_rsp_ins_error("r_vci_rsp_ins_error"),
+      r_vci_rsp_data_error("r_vci_rsp_data_error"),
+
+      r_vci_tgt_fsm("r_vci_tgt_fsm"),
+      r_tgt_addr("r_tgt_addr"),
+      r_tgt_word("r_tgt_word"),
+      r_tgt_update("r_tgt_update"),
+      r_tgt_srcid("r_tgt_srcid"),
+      r_tgt_pktid("r_tgt_pktid"),
+      r_tgt_trdid("r_tgt_trdid"),
+      r_tgt_icache_req("r_tgt_icache_req"),
+      r_tgt_dcache_req("r_tgt_dcache_req"),
+
+      r_inval_itlb_fsm("r_inval_itlb_fsm"),          
+      r_dcache_itlb_inval_req("r_dcache_itlb_inval_req"),
+      r_dcache_itlb_inval_line("r_dcache_itlb_inval_line"),
+      r_itlb_cc_check_end("r_itlb_cc_check_end"),
+      r_ccinval_itlb_way("r_ccinval_itlb_way"), 
+      r_ccinval_itlb_set("r_ccinval_itlb_set"), 
+      r_icache_inval_tlb_rsp("r_icache_inval_tlb_rsp"),
+      r_icache_tlb_nline("r_icache_tlb_nline"),
+
+      r_inval_dtlb_fsm("r_inval_dtlb_fsm"),          
+      r_dcache_dtlb_inval_req("r_dcache_dtlb_inval_req"),
+      r_dcache_dtlb_inval_line("r_dcache_dtlb_inval_line"),
+      r_dtlb_cc_check_end("r_dtlb_cc_check_end"),
+      r_ccinval_dtlb_way("r_ccinval_dtlb_way"), 
+      r_ccinval_dtlb_set("r_ccinval_dtlb_set"), 
+      r_dcache_inval_tlb_rsp("r_dcache_inval_tlb_rsp"),
+      r_dcache_tlb_nline("r_dcache_tlb_nline"),
+
+      r_dcache_itlb_cleanup_req("r_dcache_itlb_cleanup_req"),
+      r_dcache_itlb_cleanup_line("r_dcache_itlb_cleanup_line"),
+
+      r_dcache_dtlb_cleanup_req("r_dcache_dtlb_cleanup_req"),
+      r_dcache_dtlb_cleanup_line("r_dcache_dtlb_cleanup_line"),
+
+      r_wbuf("wbuf", write_buf_size ),
+      r_icache("icache", icache_ways, icache_sets, icache_words),
+      r_dcache("dcache", dcache_ways, dcache_sets, dcache_words)
+{
+    r_icache_miss_buf = new data_t[icache_words];
+    r_dcache_miss_buf = new data_t[dcache_words];
+    r_tgt_buf         = new data_t[dcache_words];
+    r_tgt_val         = new bool[dcache_words];
+    r_dcache_in_itlb  = new bool[dcache_ways*dcache_sets];           
+    r_dcache_in_dtlb  = new bool[dcache_ways*dcache_sets];          
+
+    SC_METHOD(transition);
+    dont_initialize();
+    sensitive << p_clk.pos();
+  
+    SC_METHOD(genMoore);
+    dont_initialize();
+    sensitive << p_clk.neg();
+
+    typename iss_t::CacheInfo cache_info;
+    cache_info.has_mmu = true;
+    cache_info.icache_line_size = icache_words*sizeof(data_t);
+    cache_info.icache_assoc = icache_ways;
+    cache_info.icache_n_lines = icache_sets;
+    cache_info.dcache_line_size = dcache_words*sizeof(data_t);
+    cache_info.dcache_assoc = dcache_ways;
+    cache_info.dcache_n_lines = dcache_sets;
+    m_iss.setCacheInfo(cache_info);
+}
+
+/////////////////////////////////////
+tmpl(/**/)::~VciCcVCacheWrapper2()
+/////////////////////////////////////
+{
+    delete [] r_icache_miss_buf;
+    delete [] r_dcache_miss_buf;
+    delete [] r_tgt_val;
+    delete [] r_tgt_buf;
+    delete [] r_dcache_in_itlb;           
+    delete [] r_dcache_in_dtlb;          
+}
+
+////////////////////////
+tmpl(void)::print_cpi()
+////////////////////////
+{
+    std::cout << name() << " CPI = " 
+        << (float)m_cpt_total_cycles/(m_cpt_total_cycles - m_cpt_frz_cycles) << std::endl ;
+}
+
+////////////////////////
+tmpl(void)::print_stats()
+////////////////////////
+{
+    float run_cycles = (float)(m_cpt_total_cycles - m_cpt_frz_cycles);
+    std::cout << name() << std::endl
+    	      << "- CPI                    = " << (float)m_cpt_total_cycles/run_cycles << std::endl 
+    	      << "- READ RATE              = " << (float)m_cpt_read/run_cycles << std::endl 
+    	      << "- WRITE RATE             = " << (float)m_cpt_write/run_cycles << std::endl
+    	      << "- UNCACHED READ RATE     = " << (float)m_cpt_unc_read/m_cpt_read << std::endl 
+    	      << "- CACHED WRITE RATE      = " << (float)m_cpt_write_cached/m_cpt_write << std::endl 
+    	      << "- IMISS_RATE             = " << (float)m_cpt_ins_miss/m_cpt_ins_read << std::endl    
+    	      << "- DMISS RATE             = " << (float)m_cpt_data_miss/(m_cpt_read-m_cpt_unc_read) << std::endl 
+    	      << "- INS MISS COST          = " << (float)m_cost_ins_miss_frz/m_cpt_ins_miss << std::endl
+    	      << "- IMISS TRANSACTION      = " << (float)m_cost_imiss_transaction/m_cpt_imiss_transaction << std::endl
+    	      << "- DMISS COST             = " << (float)m_cost_data_miss_frz/m_cpt_data_miss << std::endl
+    	      << "- DMISS TRANSACTION      = " << (float)m_cost_dmiss_transaction/m_cpt_dmiss_transaction << std::endl
+    	      << "- UNC COST               = " << (float)m_cost_unc_read_frz/m_cpt_unc_read << std::endl
+    	      << "- UNC TRANSACTION        = " << (float)m_cost_unc_transaction/m_cpt_unc_transaction << std::endl
+    	      << "- WRITE COST             = " << (float)m_cost_write_frz/m_cpt_write << std::endl
+    	      << "- WRITE TRANSACTION      = " << (float)m_cost_write_transaction/m_cpt_write_transaction << std::endl
+    	      << "- WRITE LENGTH           = " << (float)m_length_write_transaction/m_cpt_write_transaction << std::endl
+    	      << "- INS TLB MISS RATE      = " << (float)m_cpt_ins_tlb_miss/m_cpt_ins_tlb_read << std::endl
+    	      << "- DATA TLB MISS RATE     = " << (float)m_cpt_data_tlb_miss/m_cpt_data_tlb_read << std::endl
+    	      << "- ITLB MISS TRANSACTION  = " << (float)m_cost_itlbmiss_transaction/m_cpt_itlbmiss_transaction << std::endl
+    	      << "- ITLB WRITE TRANSACTION = " << (float)m_cost_itlb_write_transaction/m_cpt_itlb_write_transaction << std::endl
+    	      << "- ITLB MISS COST         = " << (float)m_cost_ins_tlb_miss_frz/(m_cpt_ins_tlb_miss+m_cpt_ins_tlb_write_et) << std::endl
+    	      << "- DTLB MISS TRANSACTION  = " << (float)m_cost_dtlbmiss_transaction/m_cpt_dtlbmiss_transaction << std::endl
+    	      << "- DTLB WRITE TRANSACTION = " << (float)m_cost_dtlb_write_transaction/m_cpt_dtlb_write_transaction << std::endl
+    	      << "- DTLB MISS COST         = " << (float)m_cost_data_tlb_miss_frz/(m_cpt_data_tlb_miss+m_cpt_data_tlb_write_et+m_cpt_data_tlb_write_dirty) << std::endl;
+}
+
+/*************************************************/
+tmpl(void)::transition()
+/*************************************************/
+{
+    if ( ! p_resetn.read() ) 
+    {
+        m_iss.reset();
+
+        r_dcache_fsm = DCACHE_IDLE;
+        r_icache_fsm = ICACHE_IDLE;
+        r_vci_cmd_fsm = CMD_IDLE;
+        r_vci_rsp_fsm = RSP_IDLE;
+        r_vci_tgt_fsm = TGT_IDLE;
+        r_inval_itlb_fsm = INVAL_ITLB_IDLE;          
+        r_inval_dtlb_fsm = INVAL_DTLB_IDLE;          
+
+        // write buffer & caches
+        r_wbuf.reset();
+        r_icache.reset();
+        r_dcache.reset();
+
+        icache_tlb.reset();    
+        dcache_tlb.reset();    
+
+        std::memset(r_dcache_in_itlb, 0, sizeof(*r_dcache_in_itlb)*m_icache_ways*m_icache_sets);
+        std::memset(r_dcache_in_dtlb, 0, sizeof(*r_dcache_in_dtlb)*m_dcache_ways*m_dcache_sets);
+
+        r_mmu_mode = ALL_DEACTIVE;
+        r_mmu_params = (uint32_log2(m_dtlb_ways) << 29)   | (uint32_log2(m_dtlb_sets) << 25)   |
+                       (uint32_log2(m_dcache_ways) << 22) | (uint32_log2(m_dcache_sets) << 18) |
+                       (uint32_log2(m_itlb_ways) << 15)   | (uint32_log2(m_itlb_sets) << 11)   |
+                       (uint32_log2(m_icache_ways) << 8)  | (uint32_log2(m_icache_sets) << 4)  |
+                       (uint32_log2(m_icache_words * 4));
+        r_mmu_release = (uint32_t)(1 << 16) | 0x1;
+
+        r_icache_miss_req         = false;
+        r_icache_unc_req          = false;
+        r_dcache_itlb_read_req    = false;
+
+        r_itlb_read_dcache_req    = false;      
+        r_itlb_acc_dcache_req     = false;   
+        r_dcache_rsp_itlb_error   = false;
+ 
+        r_dcache_miss_req         = false;
+        r_dcache_unc_req          = false;
+        r_dcache_write_req        = false;
+        r_dcache_tlb_read_req     = false;
+        r_dcache_tlb_ptba_read    = false;
+        r_dcache_xtn_req          = false;
+	r_dcache_llsc_reserved    = false;
+
+        r_dcache_tlb_ll_acc_req   = false;    
+        r_dcache_tlb_sc_acc_req   = false;    
+        r_dcache_tlb_ll_dirty_req = false;   
+        r_dcache_tlb_sc_dirty_req = false;   
+        r_dcache_itlb_ll_acc_req  = false;   
+        r_dcache_itlb_sc_acc_req  = false;   
+
+        r_icache_cleanup_req      = false;
+        r_dcache_cleanup_req      = false;
+
+        r_tgt_icache_req          = false;
+        r_tgt_dcache_req          = false;
+
+        r_icache_inval_rsp        = false;
+        r_dcache_inval_rsp        = false;
+
+        r_dcache_dirty_save       = false;
+        r_dcache_hit_p_save       = false;
+
+        r_icache_buf_unc_valid    = false;
+        r_dcache_buf_unc_valid    = false;
+
+        r_vci_rsp_ins_error       = false;
+        r_vci_rsp_data_error      = false;
+
+        r_icache_id1_save         = 0;
+        r_icache_ppn_save         = 0;
+        r_icache_vpn_save         = 0;
+        r_itlb_translation_valid  = false;
+
+        r_dcache_id1_save         = 0;
+        r_dcache_ppn_save         = 0;
+        r_dcache_vpn_save         = 0;
+        r_dtlb_translation_valid  = false;
+
+        r_icache_ptba_ok          = false;
+        r_dcache_ptba_ok          = false;
+
+        r_icache_error_type       = MMU_NONE;
+        r_dcache_error_type       = MMU_NONE;
+
+        // coherence registers
+        r_icache_way              = 0;
+        r_icache_set              = 0;
+        r_icache_cleanup_req      = false;
+        r_icache_inval_rsp        = false;
+
+        r_dcache_way              = 0;
+        r_dcache_set              = 0;
+        r_dcache_cleanup_req      = false;
+        r_dcache_inval_rsp        = false;
+
+	r_itlb_inval_req 	  = false;
+        r_dcache_itlb_inval_req   = false;
+        r_itlb_cc_check_end       = false;
+        r_ccinval_itlb_way        = 0; 
+        r_ccinval_itlb_set        = 0; 
+        r_icache_inval_tlb_rsp    = false;
+
+        r_dcache_dtlb_inval_req   = false;
+        r_dtlb_cc_check_end       = false;
+        r_ccinval_dtlb_way        = 0; 
+        r_ccinval_dtlb_set        = 0; 
+        r_dcache_inval_tlb_rsp    = false;
+
+        r_dcache_itlb_cleanup_req = false;
+        r_dcache_dtlb_cleanup_req = false;
+
+	r_dcache_cc_check         = false;
+
+        // activity counters
+        m_cpt_dcache_data_read  = 0;
+        m_cpt_dcache_data_write = 0;
+        m_cpt_dcache_dir_read   = 0;
+        m_cpt_dcache_dir_write  = 0;
+        m_cpt_icache_data_read  = 0;
+        m_cpt_icache_data_write = 0;
+        m_cpt_icache_dir_read   = 0;
+        m_cpt_icache_dir_write  = 0;
+
+	m_cpt_frz_cycles   = 0;
+        m_cpt_total_cycles = 0;
+
+        m_cpt_read         = 0;
+        m_cpt_write        = 0;
+        m_cpt_data_miss    = 0;
+        m_cpt_ins_miss     = 0;
+        m_cpt_unc_read     = 0;
+        m_cpt_write_cached = 0;
+        m_cpt_ins_read     = 0;
+
+        m_cost_write_frz     = 0;
+        m_cost_data_miss_frz = 0;
+        m_cost_unc_read_frz  = 0;
+        m_cost_ins_miss_frz  = 0;
+
+        m_cpt_imiss_transaction = 0;
+        m_cpt_dmiss_transaction = 0;
+        m_cpt_unc_transaction   = 0;
+        m_cpt_write_transaction = 0;
+
+        m_cost_imiss_transaction   = 0;
+        m_cost_dmiss_transaction   = 0;
+        m_cost_unc_transaction     = 0;
+        m_cost_write_transaction   = 0;
+        m_length_write_transaction = 0;
+
+        m_cpt_ins_tlb_read         = 0;             
+        m_cpt_ins_tlb_miss         = 0;             
+        m_cpt_ins_tlb_write_et     = 0;         
+
+        m_cpt_data_tlb_read        = 0;           
+        m_cpt_data_tlb_miss        = 0;           
+        m_cpt_data_tlb_write_et    = 0;       
+        m_cpt_data_tlb_write_dirty = 0;    
+
+        m_cost_ins_tlb_miss_frz    = 0;      
+        m_cost_data_tlb_miss_frz   = 0;      
+
+        m_cpt_itlbmiss_transaction   = 0;    
+        m_cpt_itlb_write_transaction = 0;  
+        m_cpt_dtlbmiss_transaction   = 0;  
+        m_cpt_dtlb_write_transaction = 0;  
+ 
+        m_cost_itlbmiss_transaction   = 0;   
+        m_cost_itlb_write_transaction = 0;  
+        m_cost_dtlbmiss_transaction   = 0;   
+        m_cost_dtlb_write_transaction = 0;   
+        return;
+    }
+
+#ifdef SOCLIB_MODULE_DEBUG
+std::cout << name() << "cycle = " << m_cpt_total_cycles  
+       	  << " tgt fsm: " << tgt_fsm_state_str[r_vci_tgt_fsm]
+       	  << " dcache fsm: " << dcache_fsm_state_str[r_dcache_fsm]
+       	  << " icache fsm: " << icache_fsm_state_str[r_icache_fsm]
+       	  << " cmd fsm: " << cmd_fsm_state_str[r_vci_cmd_fsm]
+       	  << " rsp fsm: " << rsp_fsm_state_str[r_vci_rsp_fsm] 
+       	  << " inval itlb fsm: " << inval_itlb_fsm_state_str[r_inval_itlb_fsm] 
+          << " inval dtlb fsm: " << inval_dtlb_fsm_state_str[r_inval_dtlb_fsm] << std::endl;
+#endif
+
+    m_cpt_total_cycles++;
+
+    typename iss_t::InstructionRequest ireq = ISS_IREQ_INITIALIZER;
+    typename iss_t::InstructionResponse irsp = ISS_IRSP_INITIALIZER;
+
+    typename iss_t::DataRequest dreq = ISS_DREQ_INITIALIZER;
+    typename iss_t::DataResponse drsp = ISS_DRSP_INITIALIZER;
+
+    m_iss.getRequests( ireq, dreq );
+
+#ifdef SOCLIB_MODULE_DEBUG
+    std::cout << name() << " Instruction Request: " << ireq << std::endl;
+    std::cout << name() << " Data Request: " << dreq << std::endl;
+#endif
+
+    /////////////////////////////////////////////////////////////////////
+    // The TGT_FSM controls the following ressources:
+    // - r_vci_tgt_fsm
+    // - r_tgt_buf[nwords]
+    // - r_tgt_val[nwords]
+    // - r_tgt_update
+    // - r_tgt_word
+    // - r_tgt_addr
+    // - r_tgt_srcid
+    // - r_tgt_trdid
+    // - r_tgt_pktid
+    // All VCI commands must be CMD_WRITE.
+    // If the VCI address offset is null, the command is an invalidate 
+    // request. It is an update request otherwise.
+    // The VCI_TGT FSM stores the external request arguments in the
+    // IDLE, UPDT_WORD & UPDT_DATA states. It sets the r_tgt_icache_req 
+    // & r_tgt_dcache_req flip-flops to signal the external request to 
+    // the ICACHE & DCACHE FSMs in the REQ state. It waits the completion
+    // of the update or invalidate request in the RSP state.
+    // -  for an invalidate request the VCI packet length is 1 word.
+    // The WDATA field contains the line index (i.e. the Z & Y fields).
+    // -  for an update request the VCI packet length is (n+2) words.
+    // The WDATA field of the first VCI word contains the line number.
+    // The WDATA field of the second VCI word contains the word index.
+    // The WDATA field of the n following words contains the values.
+    // -  for both invalidate & update requests, the VCI response
+    // is one single word.
+    // In case of errors in the VCI command packet, the simulation
+    // is stopped with an error message.
+    /////////////////////////////////////////////////////////////////////
+    
+    switch(r_vci_tgt_fsm) {
+    //////////////
+    case TGT_IDLE:
+    {
+        if ( p_vci_tgt.cmdval.read() ) 
+        {
+            paddr_t address = p_vci_tgt.address.read();
+
+            if ( p_vci_tgt.cmd.read() != vci_param::CMD_WRITE) 
+            {
+                std::cout << "error in component VCI_CC_VCACHE_WRAPPER " << name() << std::endl;
+                std::cout << "the received VCI command is not a write" << std::endl;
+                exit(0);
+            }
+
+            // multi-update or multi-invalidate for data type
+            if ( ( address != 0x3 ) && ( ! m_segment.contains(address)) ) 
+            {
+                std::cout << "error in component VCI_CC_VCACHE_WRAPPER " << name() << std::endl;
+                std::cout << "out of segment VCI command received for a multi-updt or multi-inval request" << std::endl;
+                exit(0);
+            }
+
+            r_tgt_srcid = p_vci_tgt.srcid.read();
+            r_tgt_trdid = p_vci_tgt.trdid.read();
+            r_tgt_pktid = p_vci_tgt.pktid.read();
+            r_tgt_plen  = p_vci_tgt.plen.read(); // todo: wait L2 modification
+            r_tgt_addr = (paddr_t)p_vci_tgt.wdata.read() * m_dcache_words * 4; 
+
+            if ( address == 0x3 ) // broadcast invalidate for data or instruction type
+            {
+                if ( ! p_vci_tgt.eop.read() ) 
+                {
+                    std::cout << "error in component VCI_CC_VCACHE_WRAPPER " << name() << std::endl;
+                    std::cout << "the BROADCAST INVALIDATE command length must be one word" << std::endl;
+                    exit(0);
+                }
+                r_tgt_update = false; 
+                r_vci_tgt_fsm = TGT_REQ_BROADCAST;
+                m_cpt_cc_broadcast++;
+            }
+            else                // multi-update or multi-invalidate for data type
+            {
+                paddr_t cell = address - m_segment.baseAddress();   
+
+                if (cell == 0)                      // invalidate   
+                {                         
+                    if ( ! p_vci_tgt.eop.read() ) 
+                    {
+                        std::cout << "error in component VCI_CC_VCACHE_WRAPPER " << name() << std::endl;
+                        std::cout << "the MULTI-INVALIDATE command length must be one word" << std::endl;
+                        exit(0);
+                    }
+                    r_tgt_update = false; 
+                    r_vci_tgt_fsm = TGT_REQ_DCACHE;
+                    m_cpt_cc_inval++ ;
+                } 
+                else                                // update
+                {                                
+                    if ( p_vci_tgt.eop.read() ) 
+                    {
+                        std::cout << "error in component VCI_CC_VCACHE_WRAPPER " << name() << std::endl;
+                        std::cout << "the MULTI-UPDATE command length must be N+2 words" << std::endl;
+                        exit(0);
+                    }
+                    r_tgt_update = true; 
+                    r_vci_tgt_fsm = TGT_UPDT_WORD;
+                    m_cpt_cc_update++ ;
+                }     
+            } // end if address    
+        } // end if cmdval
+        break;
+    }
+    ///////////////////
+    case TGT_UPDT_WORD:
+    {
+        if (p_vci_tgt.cmdval.read()) 
+        {
+            if ( p_vci_tgt.eop.read() ) 
+            {
+                std::cout << "error in component VCI_CC_VCACHE_WRAPPER " << name() << std::endl;
+                std::cout << "the MULTI-UPDATE command length must be N+2 words" << std::endl;
+                exit(0);
+            }
+            for ( size_t i=0 ; i<m_dcache_words ; i++ ) r_tgt_val[i] = false;
+            r_tgt_word = p_vci_tgt.wdata.read(); // the first modified word index
+            r_vci_tgt_fsm = TGT_UPDT_DATA;
+        }
+        break;
+    }
+    ///////////////////
+    case TGT_UPDT_DATA:
+    {
+        if (p_vci_tgt.cmdval.read()) 
+        {
+            size_t word = r_tgt_word.read();
+            if (word >= m_dcache_words) 
+            {
+                std::cout << "error in component VCI_CC_VCACHE_WRAPPER " << name() << std::endl;
+                std::cout << "the reveived MULTI-UPDATE command length is wrong" << std::endl;
+                exit(0);
+            }
+            r_tgt_buf[word] = p_vci_tgt.wdata.read();
+            if(p_vci_tgt.be.read())    r_tgt_val[word] = true;
+            r_tgt_word = word + 1;
+            if (p_vci_tgt.eop.read())  r_vci_tgt_fsm = TGT_REQ_DCACHE;
+        }
+        break;
+    }
+    ////////////////////////
+    case TGT_REQ_BROADCAST:
+    {
+        if ( !r_tgt_icache_req.read() && !r_tgt_dcache_req.read() ) 
+        {
+            r_vci_tgt_fsm = TGT_RSP_BROADCAST; 
+            r_tgt_icache_req = true;
+            r_tgt_dcache_req = true;
+        }
+        break;
+    }
+    /////////////////////
+    case TGT_REQ_DCACHE:
+    {
+        if ( !r_tgt_dcache_req.read() ) 
+        {
+            r_vci_tgt_fsm = TGT_RSP_DCACHE; 
+            r_tgt_dcache_req = true;
+        }
+        break;
+    }
+    ///////////////////////
+    case TGT_RSP_BROADCAST:
+    {
+        // no response
+        if ( !r_tgt_icache_rsp.read() && !r_tgt_dcache_rsp.read() && !r_tgt_icache_req.read() && !r_tgt_dcache_req.read() )
+        {
+            r_vci_tgt_fsm = TGT_IDLE;
+            break;
+        }
+
+        if ( p_vci_tgt.rspack.read() && !r_tgt_icache_req.read() && !r_tgt_dcache_req.read() ) 
+        {
+            // one response
+            if ( !r_tgt_icache_rsp || !r_tgt_dcache_rsp )
+            {
+                r_vci_tgt_fsm = TGT_IDLE; 
+                r_tgt_icache_rsp = false;
+                r_tgt_dcache_rsp = false;
+            }
+
+            // if data and instruction have the inval line, need two responses  
+            if ( r_tgt_icache_rsp && r_tgt_dcache_rsp )
+            {
+                r_tgt_icache_rsp = false; // only reset one for respond the second time 
+            }
+        }
+        break;
+    }
+    /////////////////////
+    case TGT_RSP_DCACHE:
+    {
+        if ( p_vci_tgt.rspack.read() && !r_tgt_dcache_req.read() ) 
+        {
+            r_vci_tgt_fsm = TGT_IDLE;
+            r_tgt_dcache_rsp = false; 
+        }
+        break;
+    }
+    } // end switch TGT_FSM
+
+    ////////////////////////////////////////////////////////////////////////////////////////
+    //      ICACHE_FSM
+    //
+    // There is 9 mutually exclusive conditions to exit the IDLE state.
+    // Four configurations corresponding to an XTN request from processor,
+    // - Flush TLB (in case of Context switch) => TLB_FLUSH state 
+    // - Flush cache => CACHE_FLUSH state 
+    // - Invalidate a TLB entry => TLB_INVAL state
+    // - Invalidate a cache line => CACHE_INVAL state
+    // Five configurations corresponding to various TLB or cache MISS :
+    // - TLB miss(in case hit_p miss) => TLB1_READ state
+    // - TLB miss(in case hit_p hit) => TLB2_READ state
+    // - Hit in TLB but VPN changed => BIS state
+    // - Cached read miss => MISS_REQ state
+    // - Uncache read miss => UNC_REQ state
+    // 
+    // In case of MISS, the controller writes a request in the r_icache_paddr_save register 
+    // and sets the corresponding request flip-flop : r_dcache_itlb_read_req, r_icache_miss_req 
+    // or r_icache_unc_req. These request flip-flops are reset by the VCI_RSP controller 
+    // when the response is ready in the ICACHE buffer.
+    //
+    // The DCACHE FSM signals XTN processor requests using the r_dcache_xtn_req flip-flop. 
+    // The request opcod and the address to be invalidated are transmitted
+    // in the r_dcache_paddr_save & r_dcache_wdata_save registers respectively.
+    // The request flip-flop is reset by the ICACHE_FSM when the operation is completed.
+    //
+    // The r_vci_rsp_ins_error flip-flop is set by the VCI_RSP FSM and reset
+    // by the ICACHE-FSM in the ICACHE_ERROR state.
+    //
+    //----------------------------------------------------------------------------------- 
+    // Instruction TLB: 
+    //  
+    // - int        ET          (00: unmapped; 01: unused or PTD)
+    //                          (10: PTE new;  11: PTE old      )
+    // - bool       cachable    (cached bit)
+    // - bool       writable    (** not used alwayse false) 
+    // - bool       executable  (executable bit)
+    // - bool       user        (access in user mode allowed)
+    // - bool       global      (PTE not invalidated by a TLB flush)
+    // - bool       dirty       (** not used alwayse false) 
+    // - uint32_t   vpn         (virtual page number)
+    // - uint32_t   ppn         (physical page number)
+    ////////////////////////////////////////////////////////////////////////////////////////
+
+    switch(r_icache_fsm) {
+
+    ////////////////
+    case ICACHE_IDLE:
+    {
+        pte_info_t  icache_pte_info;
+        paddr_t     tlb_ipaddr       = 0;    	// physical address obtained from TLB                         
+        paddr_t     spc_ipaddr       = 0;    	// physical adress obtained from PPN_save (speculative)       
+        data_t      icache_ins       = 0;    	// read instruction
+        bool        icache_hit_c     = false;	// Cache hit
+        bool        icache_cached    = false;	// cacheable access (read)
+        bool        icache_hit_t     = false;	// hit on TLB
+        bool        icache_hit_x     = false;	// VPN unmodified (can use spc_dpaddr)
+        bool        icache_hit_p     = false;	// PTP unmodified (can skip first level page table walk)
+        size_t      icache_tlb_way   = 0;    	// selected way (in case of cache hit)
+        size_t      icache_tlb_set   = 0;    	// selected set (Y field in address)
+        paddr_t     icache_tlb_nline = 0;  	// TLB NLINE 
+
+        // Decoding processor XTN requests
+        // They are sent by DCACHE FSM  
+
+        if (r_dcache_xtn_req)
+        {
+            if ( ireq.valid ) m_cost_ins_waste_wait_frz++;
+            
+            if ((int)r_dcache_type_save == (int)iss_t::XTN_PTPR )  
+            {
+                r_icache_way = 0;
+                r_icache_set = 0;
+                r_icache_fsm = ICACHE_SW_FLUSH;   
+                break;
+            }
+            if ((int)r_dcache_type_save == (int)iss_t::XTN_ICACHE_FLUSH)
+            {
+                r_icache_way = 0;
+                r_icache_set = 0;
+                r_icache_fsm = ICACHE_CACHE_FLUSH;   
+                break;
+            }
+            if ((int)r_dcache_type_save == (int)iss_t::XTN_ITLB_INVAL) 
+            {
+                r_icache_fsm = ICACHE_TLB_INVAL;   
+                break;
+            }
+            if ((int)r_dcache_type_save == (int)iss_t::XTN_ICACHE_INVAL) 
+            {
+                r_icache_fsm = ICACHE_CACHE_INVAL;   
+                break;
+            }
+            if ((int)r_dcache_type_save == (int)iss_t::XTN_DCACHE_FLUSH )  
+            {
+                // special for ins tlb miss via data cache
+                r_icache_fsm = ICACHE_TLB_FLUSH;   
+                break;
+            }
+        } // end if xtn_req
+
+        // external cache invalidate request
+        if ( r_tgt_icache_req )
+        {
+            if ( ireq.valid ) m_cost_ins_waste_wait_frz++;
+            r_icache_fsm = ICACHE_CC_INVAL;
+            r_icache_fsm_save = r_icache_fsm;
+            break;
+        }
+
+        // external tlb invalidate request
+        if ( r_dcache_itlb_inval_req )
+        {
+            if ( ireq.valid ) m_cost_ins_waste_wait_frz++;
+	    r_itlb_inval_req = true;
+            r_icache_fsm = ICACHE_TLB_CC_INVAL;
+            r_icache_fsm_save = r_icache_fsm;
+            break;
+        }
+
+        // icache_hit_t_m, icache_hit_t_k, icache_hit_x, icache_hit_p 
+        // icache_pte_info, icache_tlb_way, icache_tlb_set & ipaddr & cacheability 
+        // - If MMU activated : cacheability is defined by the cachable bit in the TLB
+        // - If MMU not activated : cacheability is defined by the segment table.
+
+        if ( !(r_mmu_mode.read() & INS_TLB_MASK) )   // MMU not activated 
+        {
+            icache_hit_t  = true;         
+            icache_hit_x  = true;         
+            icache_hit_p  = true;         
+            tlb_ipaddr    = ireq.addr;
+            spc_ipaddr    = ireq.addr;
+            icache_cached = m_cacheability_table[ireq.addr];
+        } 
+        else                                                                // MMU activated
+        { 
+            m_cpt_ins_tlb_read++;
+            icache_hit_t  = icache_tlb.cctranslate(ireq.addr, &tlb_ipaddr, &icache_pte_info, 
+                                                   &icache_tlb_nline, &icache_tlb_way, &icache_tlb_set); 
+            icache_hit_x  = (((vaddr_t)r_icache_vpn_save << PAGE_K_NBITS) == (ireq.addr & ~PAGE_K_MASK)) && r_itlb_translation_valid;
+            icache_hit_p  = (((ireq.addr >> PAGE_M_NBITS) == r_icache_id1_save) && r_icache_ptba_ok); 
+            spc_ipaddr    = ((paddr_t)r_icache_ppn_save << PAGE_K_NBITS) | (paddr_t)(ireq.addr & PAGE_K_MASK);
+            icache_cached = icache_pte_info.c; 
+        }
+
+        if ( !(r_mmu_mode.read() & INS_CACHE_MASK) )   // cache not actived
+        {
+            icache_cached = false;
+        }
+
+        if ( ireq.valid ) 
+        {
+            m_cpt_icache_dir_read += m_icache_ways;
+            m_cpt_icache_data_read += m_icache_ways;
+
+            // icache_hit_c & icache_ins
+            if ( icache_cached )    // using speculative physical address for cached access
+            {
+                icache_hit_c = r_icache.read(spc_ipaddr, &icache_ins);
+            }
+            else                    // using actual physical address for uncached access
+            {
+                icache_hit_c = ( r_icache_buf_unc_valid && (tlb_ipaddr == (paddr_t)r_icache_paddr_save) );
+                icache_ins = r_icache_miss_buf[0];
+            }
+
+            if ( r_mmu_mode.read() & INS_TLB_MASK ) 
+            {
+                if ( icache_hit_t ) 
+                {
+                    // check access rights
+                    if ( !icache_pte_info.u && (ireq.mode == iss_t::MODE_USER)) 
+                    {
+                        r_icache_error_type = MMU_READ_PRIVILEGE_VIOLATION;  
+                        r_icache_bad_vaddr = ireq.addr;
+                        irsp.valid = true;
+                        irsp.error = true;
+                        irsp.instruction = 0;
+                        break;
+                    }
+                    if ( !icache_pte_info.x ) 
+                    {
+                        r_icache_error_type = MMU_READ_EXEC_VIOLATION;  
+                        r_icache_bad_vaddr = ireq.addr;
+                        irsp.valid = true;
+                        irsp.error = true;
+                        irsp.instruction = 0;
+                        break;
+                    }
+                }
+
+                // update LRU, save ppn, vpn and page type
+                if ( icache_hit_t )
+                {  
+                    icache_tlb.setlru(icache_tlb_way,icache_tlb_set);     
+                    r_icache_ppn_save = tlb_ipaddr >> PAGE_K_NBITS;
+                    r_icache_vpn_save = ireq.addr >> PAGE_K_NBITS;
+                    r_icache_tlb_nline = icache_tlb_nline;
+                    r_itlb_translation_valid = true;
+                }
+                else
+                {
+                    r_itlb_translation_valid = false;
+                }
+
+            } // end if MMU activated
+
+            // compute next state 
+            if ( !icache_hit_t && !icache_hit_p )      // TLB miss
+            {
+                // walk page table  level 1
+                r_icache_paddr_save = (paddr_t)r_mmu_ptpr << (INDEX1_NBITS+2) | (paddr_t)((ireq.addr>>PAGE_M_NBITS)<<2);
+                r_itlb_read_dcache_req = true;
+                r_icache_fsm = ICACHE_TLB1_READ;
+                m_cpt_ins_tlb_miss++;
+                m_cost_ins_tlb_miss_frz++;
+            }
+            else if ( !icache_hit_t && icache_hit_p )  // TLB Miss with possibility of bypass first level page
+            {
+                // walk page table level 2
+                r_icache_paddr_save = (paddr_t)r_icache_ptba_save | 
+                                      (paddr_t)(((ireq.addr&PTD_ID2_MASK)>>PAGE_K_NBITS) << 3);
+                r_itlb_read_dcache_req = true;
+                r_icache_fsm = ICACHE_TLB2_READ;
+                m_cpt_ins_tlb_miss++;
+                m_cost_ins_tlb_miss_frz++;
+            }
+            else if ( icache_hit_t && !icache_hit_x && icache_cached ) // cached access with an ucorrect speculative physical address
+            {
+                r_icache_paddr_save = tlb_ipaddr;   // save actual physical address for BIS
+                r_icache_fsm = ICACHE_BIS;
+                m_cost_ins_miss_frz++;
+            }
+            else    // cached or uncached access with a correct speculative physical address 
+            {        
+                m_cpt_ins_read++; 
+                if ( !icache_hit_c ) 
+                {
+                    m_cpt_ins_miss++;
+                    m_cost_ins_miss_frz++;
+                    if ( icache_cached ) 
+                    {
+                        r_icache_miss_req = true;
+                    	r_icache_paddr_save = spc_ipaddr; 
+                        r_icache_fsm = ICACHE_MISS_WAIT;
+                    } 
+                    else 
+                    {
+                        r_icache_unc_req = true;
+                        r_icache_buf_unc_valid = false;
+                    	r_icache_paddr_save = tlb_ipaddr; 
+                        r_icache_fsm = ICACHE_UNC_WAIT;
+                    } 
+                } 
+                else 
+                {
+                    r_icache_buf_unc_valid = false;
+                    r_icache_fsm = ICACHE_IDLE;
+                }
+                irsp.valid = icache_hit_c;
+                irsp.instruction = icache_ins;
+            } // end if next states
+            
+        } // end if ireq.valid
+        break;
+    }
+    ////////////////
+    case ICACHE_BIS: 
+    {
+        m_cost_ins_miss_frz++;
+        // external cache invalidate request
+        if ( r_tgt_icache_req )
+        {
+            r_icache_fsm = ICACHE_CC_INVAL;
+            r_icache_fsm_save = r_icache_fsm;
+            m_cost_ins_waste_wait_frz++;
+            break;
+        }
+
+        // external tlb invalidate request
+        if ( r_dcache_itlb_inval_req )
+        {
+	    r_itlb_inval_req = true;
+            r_icache_fsm = ICACHE_TLB_CC_INVAL;
+            r_icache_fsm_save = r_icache_fsm;
+            m_cost_ins_waste_wait_frz++;
+            break;
+        }
+      
+        // using page is invalidated 
+        if ( r_icache_inval_tlb_rsp )
+        {
+            r_icache_inval_tlb_rsp = false;
+            r_icache_fsm = ICACHE_IDLE;
+            m_cost_ins_tlb_miss_frz++;
+            break;
+        }
+ 
+        data_t	icache_ins = 0;
+        bool	icache_hit_c = false;
+        bool    icache_hit_t = false;
+        paddr_t	tlb_ipaddr = 0;
+
+	icache_hit_t = icache_tlb.translate(ireq.addr, &tlb_ipaddr);
+
+	if ( (tlb_ipaddr == r_icache_paddr_save.read()) && ireq.valid && icache_hit_t )		// unmodified & valid
+	{
+            m_cpt_ins_read++;
+
+            // acces is always cached in this state
+            icache_hit_c = r_icache.read(r_icache_paddr_save, &icache_ins);
+
+            if ( !icache_hit_c )
+            {
+                r_icache_miss_req = true;
+                r_icache_fsm = ICACHE_MISS_WAIT;
+                m_cpt_ins_miss++;
+            } 
+            else
+            {
+                r_icache_fsm = ICACHE_IDLE; 
+            }
+            irsp.valid = icache_hit_c;
+            irsp.error = false;
+            irsp.instruction = icache_ins;
+	}
+	else	// modified or invalid
+	{
+            irsp.valid = false;
+            irsp.error = false;
+            irsp.instruction = 0;
+            r_icache_fsm = ICACHE_IDLE;
+	}
+        break;
+    }
+    //////////////////////
+    case ICACHE_TLB1_READ:
+    {
+        m_cost_ins_tlb_miss_frz++;
+
+        // external cache invalidate request
+        if ( r_tgt_icache_req )
+        {
+            r_icache_fsm = ICACHE_CC_INVAL;
+            r_icache_fsm_save = r_icache_fsm;
+            m_cost_ins_waste_wait_frz++;
+            break;
+        }
+
+        // external tlb invalidate request
+        if ( r_dcache_itlb_inval_req )
+        {
+	    r_itlb_inval_req = true;
+            r_icache_fsm = ICACHE_TLB_CC_INVAL;
+            r_icache_fsm_save = r_icache_fsm;
+            m_cost_ins_waste_wait_frz++;
+            break;
+        }
+
+        if ( !r_itlb_read_dcache_req && !r_icache_inval_tlb_rsp ) // TLB miss read response and no invalidation
+        {
+            if ( !r_dcache_rsp_itlb_error ) // vci response ok
+            {  
+		if ( !(r_dcache_rsp_itlb_miss >> PTE_V_SHIFT) ) // unmapped
+		{
+            	    r_icache_ptba_ok    = false;	
+                    r_icache_error_type = MMU_READ_PT1_UNMAPPED;  
+                    r_icache_bad_vaddr  = ireq.addr;
+                    r_icache_fsm        = ICACHE_ERROR;
+		}
+		else if ( (r_dcache_rsp_itlb_miss & PTE_T_MASK ) >> PTE_T_SHIFT ) // PTD
+		{
+            	    r_icache_ptba_ok       = true;	
+                    r_icache_ptba_save     = (paddr_t)(r_dcache_rsp_itlb_miss & ((1<<(m_paddr_nbits - PAGE_K_NBITS))-1)) << PAGE_K_NBITS; 
+                    r_icache_id1_save      = ireq.addr >> PAGE_M_NBITS;
+                    r_icache_paddr_save    = (paddr_t)(r_dcache_rsp_itlb_miss & ((1<<(m_paddr_nbits - PAGE_K_NBITS))-1)) << PAGE_K_NBITS |
+                                             (paddr_t)(((ireq.addr & PTD_ID2_MASK) >> PAGE_K_NBITS) << 3); 
+                    r_itlb_read_dcache_req = true;
+                    r_icache_fsm           = ICACHE_TLB2_READ;
+		}	
+		else
+		{
+            	    r_icache_ptba_ok = false;
+	
+		    if ( (m_srcid >> 4) == ((r_dcache_rsp_itlb_miss & ((1<<(m_paddr_nbits - PAGE_M_NBITS))-1)) >> (m_paddr_nbits - PAGE_M_NBITS -10)) ) // local
+		    {
+			if ( (r_dcache_rsp_itlb_miss & PTE_L_MASK ) >> PTE_L_SHIFT ) // L bit is set
+			{
+                            r_icache_pte_update = r_dcache_rsp_itlb_miss;
+                            r_icache_fsm        = ICACHE_TLB1_UPDT;
+			}
+			else
+			{
+                            r_icache_pte_update   = r_dcache_rsp_itlb_miss | PTE_L_MASK;
+                            r_itlb_acc_dcache_req = true;
+                            r_icache_fsm          = ICACHE_TLB1_WRITE;
+                            m_cpt_ins_tlb_write_et++;
+			}
+    	            }
+		    else // remotely
+		    {
+			if ( (r_dcache_rsp_itlb_miss & PTE_R_MASK ) >> PTE_R_SHIFT ) // R bit is set
+			{
+                            r_icache_pte_update = r_dcache_rsp_itlb_miss;
+                            r_icache_fsm        = ICACHE_TLB1_UPDT;
+			}
+			else
+			{
+                            r_icache_pte_update   = r_dcache_rsp_itlb_miss | PTE_R_MASK;
+                            r_itlb_acc_dcache_req = true;
+                            r_icache_fsm          = ICACHE_TLB1_WRITE;
+                            m_cpt_ins_tlb_write_et++;
+			}
+		    }
+		}
+            }
+            else                        // vci response error
+            {  
+                r_icache_fsm = ICACHE_ERROR;
+                r_icache_error_type = MMU_READ_PT1_ILLEGAL_ACCESS;    
+                r_icache_bad_vaddr = ireq.addr;
+            }
+        }
+
+        if ( !r_itlb_read_dcache_req && r_icache_inval_tlb_rsp ) // TLB miss read response and invalidation
+        {
+            if ( r_dcache_rsp_itlb_error ) 
+            {
+                r_icache_inval_tlb_rsp = false;
+                r_icache_error_type = MMU_READ_PT1_ILLEGAL_ACCESS;    
+                r_icache_bad_vaddr = ireq.addr;
+                r_icache_fsm = ICACHE_ERROR;
+            } 
+            else 
+            {
+                r_icache_inval_tlb_rsp = false;
+                r_icache_fsm = ICACHE_IDLE;  
+            } 
+        }
+        break;
+    }
+    ///////////////////////
+    case ICACHE_TLB1_WRITE:  
+    {
+        m_cost_ins_tlb_miss_frz++;
+
+        // external cache invalidate request
+        if ( r_tgt_icache_req )
+        {
+            r_icache_fsm = ICACHE_CC_INVAL;
+            r_icache_fsm_save = r_icache_fsm;
+            m_cost_ins_waste_wait_frz++;
+            break;
+        }
+        // external tlb invalidate request
+        if ( r_dcache_itlb_inval_req )
+        {
+	    r_itlb_inval_req = true;
+            r_icache_fsm = ICACHE_TLB_CC_INVAL;
+            r_icache_fsm_save = r_icache_fsm;
+            m_cost_ins_waste_wait_frz++;
+            break;
+        }
+
+        if (!r_itlb_acc_dcache_req && !r_icache_inval_tlb_rsp ) // TLB access bits write response and no invalidation        
+        { 
+            if ( r_dcache_rsp_itlb_error ) 
+            {
+                r_icache_error_type = MMU_READ_PT1_ILLEGAL_ACCESS;  
+                r_icache_bad_vaddr = ireq.addr;
+                r_icache_fsm = ICACHE_ERROR;
+            } 
+            else  
+            {
+                r_icache_fsm = ICACHE_TLB1_UPDT;  
+            }
+        } 
+
+        if (!r_itlb_acc_dcache_req && r_icache_inval_tlb_rsp) // TLB ET write response and invalidation     
+        {   
+            if ( r_dcache_rsp_itlb_error ) 
+            {
+                r_icache_inval_tlb_rsp = false;
+                r_icache_error_type = MMU_READ_PT1_ILLEGAL_ACCESS;  
+                r_icache_bad_vaddr = ireq.addr;
+                r_icache_fsm = ICACHE_ERROR;
+            } 
+            else  
+            {
+                r_icache_inval_tlb_rsp = false;
+                r_icache_fsm = ICACHE_IDLE;    
+            }
+        }
+        break;
+    }
+    //////////////////////
+    case ICACHE_TLB1_UPDT:
+    {
+        m_cost_ins_tlb_miss_frz++;
+
+        // external cache invalidate request
+        if ( r_tgt_icache_req )
+        {
+            r_icache_fsm = ICACHE_CC_INVAL;
+            r_icache_fsm_save = r_icache_fsm;
+            m_cost_ins_waste_wait_frz++;
+            break;
+        }
+
+        // external tlb invalidate request
+        if ( r_dcache_itlb_inval_req ) 
+        {
+	    r_itlb_inval_req = true;
+            r_icache_fsm = ICACHE_TLB_CC_INVAL;
+            r_icache_fsm_save = r_icache_fsm;
+            m_cost_ins_waste_wait_frz++;
+            break;
+        }
+
+        // TLB update and invalidate different PTE
+        if ( !r_dcache_itlb_cleanup_req && !r_icache_inval_tlb_rsp )  
+        {
+            paddr_t victim_index = 0;
+            r_dcache_itlb_cleanup_req = icache_tlb.update(r_icache_pte_update,ireq.addr,(r_icache_paddr_save.read() >> (uint32_log2(m_dcache_words)+2)),&victim_index);
+            r_dcache_itlb_cleanup_line = victim_index;
+            r_icache_fsm = ICACHE_IDLE;
+        }
+
+        // TLB update and invalidate same PTE
+        if ( r_icache_inval_tlb_rsp )                                 
+        {
+            r_icache_inval_tlb_rsp = false;
+            r_icache_fsm = ICACHE_IDLE;
+        }
+        break;
+    }
+    /////////////////////
+    case ICACHE_TLB2_READ:
+    {
+        m_cost_ins_tlb_miss_frz++;
+
+        // external cache invalidate request
+        if ( r_tgt_icache_req )
+        {
+            r_icache_fsm = ICACHE_CC_INVAL;
+            r_icache_fsm_save = r_icache_fsm;
+            m_cost_ins_waste_wait_frz++;
+            break;
+        }
+
+        // external tlb invalidate request
+        if ( r_dcache_itlb_inval_req )
+        {
+	    r_itlb_inval_req = true;
+            r_icache_fsm = ICACHE_TLB_CC_INVAL;
+            r_icache_fsm_save = r_icache_fsm;
+            m_cost_ins_waste_wait_frz++;
+            break;
+        }
+
+        if ( !r_itlb_read_dcache_req && !r_icache_inval_tlb_rsp ) // TLB miss read response 
+        {
+            if ( !r_dcache_rsp_itlb_error ) // VCI response ok        
+            {
+		if ( !(r_dcache_rsp_itlb_miss >> PTE_V_SHIFT) ) // unmapped
+		{
+                    r_icache_error_type = MMU_READ_PT2_UNMAPPED;  
+                    r_icache_bad_vaddr  = ireq.addr;
+                    r_icache_fsm = ICACHE_ERROR;
+		}
+		else
+		{
+		    if ( (m_srcid >> 4) == ((r_dcache_rsp_itlb_miss & ((1<<(m_paddr_nbits - PAGE_M_NBITS))-1)) >> (m_paddr_nbits - PAGE_M_NBITS -10)) ) // local
+		    {
+			if ( (r_dcache_rsp_itlb_miss & PTE_L_MASK ) >> PTE_L_SHIFT ) // L bit is set
+			{
+                    	    r_icache_fsm        = ICACHE_TLB2_UPDT;
+                    	    r_icache_pte_update = r_dcache_rsp_itlb_miss;
+			}
+			else
+			{
+                    	    r_icache_pte_update   = r_dcache_rsp_itlb_miss | PTE_L_MASK;
+                    	    r_itlb_acc_dcache_req = true;
+                    	    r_icache_fsm          = ICACHE_TLB2_WRITE;
+                     	    m_cpt_ins_tlb_write_et++;
+			}
+    	            }
+		    else // remotely
+		    {
+			if ( (r_dcache_rsp_itlb_miss & PTE_R_MASK ) >> PTE_R_SHIFT ) // R bit is set
+			{
+                    	    r_icache_fsm        = ICACHE_TLB2_UPDT;
+                    	    r_icache_pte_update = r_dcache_rsp_itlb_miss;
+			}
+			else
+			{
+                    	    r_icache_pte_update   = r_dcache_rsp_itlb_miss | PTE_R_MASK;
+                    	    r_itlb_acc_dcache_req = true;
+                    	    r_icache_fsm          = ICACHE_TLB2_WRITE;
+                    	    m_cpt_ins_tlb_write_et++;
+			}
+		    }
+		}
+            }
+            else                            // VCI response error        
+            {
+                r_icache_error_type = MMU_READ_PT2_ILLEGAL_ACCESS;
+                r_icache_bad_vaddr = ireq.addr;
+                r_icache_fsm = ICACHE_ERROR;
+            }
+        }
+
+        if ( !r_itlb_read_dcache_req && r_icache_inval_tlb_rsp ) // TLB miss read response and invalidation
+        {
+            if ( r_dcache_rsp_itlb_error ) 
+            {
+                r_icache_inval_tlb_rsp = false;
+                r_icache_error_type = MMU_READ_PT2_ILLEGAL_ACCESS;    
+                r_icache_bad_vaddr = ireq.addr;
+                r_icache_fsm = ICACHE_ERROR;
+            } 
+            else 
+            {
+                r_icache_inval_tlb_rsp = false;
+                r_icache_fsm = ICACHE_IDLE;  
+            } 
+        }
+        break;
+    }
+    /////////////////////////
+    case ICACHE_TLB2_WRITE:
+    {  
+        m_cost_ins_tlb_miss_frz++;
+
+        // external cache invalidate request
+        if ( r_tgt_icache_req )
+        {
+            r_icache_fsm = ICACHE_CC_INVAL;
+            r_icache_fsm_save = r_icache_fsm;
+            m_cost_ins_waste_wait_frz++;
+            break;
+        }
+        // external tlb invalidate request
+        if ( r_dcache_itlb_inval_req )
+        {
+	    r_itlb_inval_req = true;
+            r_icache_fsm = ICACHE_TLB_CC_INVAL;
+            r_icache_fsm_save = r_icache_fsm;
+            m_cost_ins_waste_wait_frz++;
+            break;
+        }
+
+        if (!r_itlb_acc_dcache_req && !r_icache_inval_tlb_rsp ) // TLB access bits write response          
+        {
+            if ( r_dcache_rsp_itlb_error )             
+            {
+                r_icache_error_type = MMU_READ_PT2_ILLEGAL_ACCESS;  
+                r_icache_bad_vaddr = ireq.addr;
+                r_icache_fsm = ICACHE_ERROR;
+            } 
+            else  
+            {
+                r_icache_fsm = ICACHE_TLB2_UPDT;  
+            }
+        } 
+        if (!r_itlb_acc_dcache_req && r_icache_inval_tlb_rsp) // TLB ET write response and invalidation     
+        {   
+            if ( r_dcache_rsp_itlb_error ) 
+            {
+                r_icache_inval_tlb_rsp = false;
+                r_icache_error_type = MMU_READ_PT2_ILLEGAL_ACCESS;  
+                r_icache_bad_vaddr = ireq.addr;
+                r_icache_fsm = ICACHE_ERROR;
+            } 
+            else  
+            {
+                r_icache_inval_tlb_rsp = false;
+                r_icache_fsm = ICACHE_IDLE;    
+            }
+        }
+        break;
+    }
+    /////////////////////
+    case ICACHE_TLB2_UPDT: 
+    {
+        m_cost_ins_tlb_miss_frz++;
+
+        // external cache invalidate request
+        if ( r_tgt_icache_req )
+        {
+            r_icache_fsm = ICACHE_CC_INVAL;
+            r_icache_fsm_save = r_icache_fsm;
+            m_cost_ins_waste_wait_frz++;
+            break;
+        }
+
+        // external tlb invalidate request
+        if ( r_dcache_itlb_inval_req ) 
+        {
+	    r_itlb_inval_req = true;
+            r_icache_fsm = ICACHE_TLB_CC_INVAL;
+            r_icache_fsm_save = r_icache_fsm;
+            m_cost_ins_waste_wait_frz++;
+            break;
+        }
+
+        // TLB update and invalidate different PTE
+        if ( !r_dcache_itlb_cleanup_req && !r_icache_inval_tlb_rsp ) 
+        {
+            paddr_t victim_index = 0;
+            r_dcache_itlb_cleanup_req = icache_tlb.update(r_icache_pte_update,r_dcache_rsp_itlb_ppn,ireq.addr,(r_icache_paddr_save.read() >> (uint32_log2(m_dcache_words)+2)),&victim_index);
+            r_dcache_itlb_cleanup_line = victim_index;
+            r_icache_fsm = ICACHE_IDLE;
+        }
+        // TLB update and invalidate same PTE
+        if ( r_icache_inval_tlb_rsp )                            
+        {
+            r_icache_inval_tlb_rsp = false;
+            r_icache_fsm = ICACHE_IDLE;
+        }
+        break;
+    }
+    /////////////////////////////
+    case ICACHE_SW_FLUSH:
+    {
+        size_t way = r_icache_way;
+        size_t set = r_icache_set;
+        bool clean = false;
+
+        if ( ireq.valid ) m_cost_ins_waste_wait_frz++;
+        m_cost_ins_tlb_sw_frz++;
+
+        // 4K page size TLB flush leads to cleanup req to data cache 
+        if ( !r_dcache_itlb_cleanup_req )    // last cleanup finish
+        {
+            paddr_t victim_index = 0;
+            for ( ; way < m_itlb_ways; way++)
+            {
+                for ( ; set < m_itlb_sets; set++)
+                {
+                    if(icache_tlb.checkcleanup(way, set, &victim_index))
+                    {
+                        clean = true;
+                        r_dcache_itlb_cleanup_req = true;
+                        r_dcache_itlb_cleanup_line = victim_index;
+                        r_icache_way = way + ((set+1)/m_itlb_sets);
+                        r_icache_set = (set+1) % m_itlb_sets;
+                        break;
+                    }
+                }
+                if (clean) break;
+            }
+
+            if ((way == m_itlb_ways) && (set == m_itlb_sets))
+            {
+                r_dcache_xtn_req = false;
+        	r_itlb_translation_valid = false;
+        	r_icache_ptba_ok = false;
+                r_icache_fsm = ICACHE_IDLE;
+                break;
+            }
+        }
+        break;
+    }
+    /////////////////////
+    case ICACHE_TLB_FLUSH:
+    {   
+        if ( ireq.valid ) m_cost_ins_waste_wait_frz++;
+
+        // data cache flush leads to ins tlb flush, flush all tlb entry 
+        icache_tlb.flush(true);    // global entries are invalidated
+        r_dcache_xtn_req = false;
+        r_icache_fsm = ICACHE_IDLE;
+        break;
+    }
+    ////////////////////////
+    case ICACHE_CACHE_FLUSH:
+    {
+        // external cache invalidate request
+        if ( r_tgt_icache_req )
+        {
+            r_tgt_icache_req = false;
+        }
+
+        size_t way = r_icache_way;
+        size_t set = r_icache_set;
+        bool clean = false;
+
+        m_cost_ins_cache_flush_frz++;
+        if ( ireq.valid ) m_cost_ins_waste_wait_frz++;
+
+        // cache flush and send cleanup to external
+        if ( !r_icache_cleanup_req )
+        {
+            paddr_t victim_index = 0;
+            for ( ; way < m_icache_ways; way++ )
+            {    
+                for ( ; set < m_icache_sets; set++ )
+                {    
+                    if ( r_icache.flush(way, set, &victim_index) )
+                    {
+                        clean = true;
+                        r_icache_cleanup_req = true;
+                        r_icache_cleanup_line = victim_index;
+                        r_icache_way = way + ((set+1)/m_icache_sets);
+                        r_icache_set = (set+1) % m_icache_sets;
+                        break;
+                    }
+                }
+                if (clean) break;
+            }
+            if ((way == m_icache_ways) && (set == m_icache_sets))
+            {
+                r_dcache_xtn_req = false;
+                r_icache_fsm = ICACHE_IDLE;
+                break;
+            }
+        }
+        break;
+    }
+    /////////////////////
+    case ICACHE_TLB_INVAL:  
+    {
+        if ( ireq.valid ) m_cost_ins_waste_wait_frz++;
+        paddr_t victim_index = 0;
+
+        if ( !r_dcache_itlb_cleanup_req )
+        {
+            r_dcache_itlb_cleanup_req = icache_tlb.inval(r_dcache_wdata_save, &victim_index);
+            r_dcache_itlb_cleanup_line = victim_index;
+            r_dcache_xtn_req = false;
+            r_itlb_translation_valid = false;
+            r_icache_ptba_ok = false;
+            r_icache_fsm = ICACHE_IDLE;
+        }
+        break;
+    }
+    ////////////////////////
+    case ICACHE_CACHE_INVAL:
+    {	
+        if ( ireq.valid ) m_cost_ins_waste_wait_frz++;
+
+        paddr_t ipaddr = 0;                     
+        bool    icache_hit_t = false;
+
+        if ( !r_icache_cleanup_req )
+        {    
+            if ( r_mmu_mode.read() & INS_TLB_MASK ) 
+            {
+                icache_hit_t = icache_tlb.translate(r_dcache_wdata_save, &ipaddr); 
+            } 
+            else 
+            {
+                ipaddr = (paddr_t)r_dcache_wdata_save;
+                icache_hit_t = true;
+            }
+            if ( icache_hit_t )
+            {
+                // invalidate and cleanup if necessary
+                r_icache_cleanup_req = r_icache.inval(ipaddr);
+                r_icache_cleanup_line = ipaddr >> (uint32_log2(m_icache_words) + 2);   
+            }
+            r_dcache_xtn_req = false; 
+            r_icache_fsm = ICACHE_IDLE;
+        }
+        break;
+    }
+    ///////////////////////
+    case ICACHE_MISS_WAIT:
+    {
+        m_cost_ins_miss_frz++;
+
+        // external cache invalidate request
+        if ( r_tgt_icache_req )     
+        {
+            r_icache_fsm = ICACHE_CC_INVAL;
+            r_icache_fsm_save = r_icache_fsm;
+            m_cost_ins_waste_wait_frz++;
+            break;
+        }
+
+        // external tlb invalidate request
+        if ( r_dcache_itlb_inval_req )
+        {
+	    r_itlb_inval_req = true;
+            r_icache_fsm = ICACHE_TLB_CC_INVAL;
+            r_icache_fsm_save = r_icache_fsm;
+            m_cost_ins_waste_wait_frz++;
+            break;
+        }
+       
+	if ( !r_icache_miss_req )
+	{
+	    if ( r_vci_rsp_ins_error ) 
+            {
+                r_icache_error_type = MMU_READ_DATA_ILLEGAL_ACCESS; 
+                r_icache_bad_vaddr = ireq.addr;
+                r_icache_fsm = ICACHE_ERROR;
+
+            	if ( r_icache_inval_tlb_rsp ) r_icache_inval_tlb_rsp = false;
+            	if ( r_icache_inval_rsp ) r_icache_inval_rsp = false;
+		break;
+            }
+
+            if ( r_icache_inval_tlb_rsp ) // Miss read response and tlb invalidation
+            {
+                r_icache_fsm = ICACHE_IDLE;
+                r_icache_inval_tlb_rsp = false;
+                m_cost_ins_tlb_miss_frz++;
+                break;
+            }
+	
+            if ( r_icache_inval_rsp ) // Miss read response and tlb invalidation
+            {
+                r_icache_fsm = ICACHE_IDLE;
+                r_icache_inval_rsp = false;
+                break;
+            }
+            r_icache_fsm = ICACHE_MISS_UPDT;  
+	}	
+        break;
+    }
+    ////////////////////
+    case ICACHE_UNC_WAIT:
+    {
+        m_cost_ins_miss_frz++;
+
+        // external cache invalidate request
+        if ( r_tgt_icache_req ) 
+        {
+            r_icache_fsm = ICACHE_CC_INVAL;
+            r_icache_fsm_save = r_icache_fsm;
+            m_cost_ins_waste_wait_frz++;
+            break;
+        }
+
+        // external tlb invalidate request
+        if ( r_dcache_itlb_inval_req )
+        {
+	    r_itlb_inval_req = true;
+            r_icache_fsm = ICACHE_TLB_CC_INVAL;
+            r_icache_fsm_save = r_icache_fsm;
+            m_cost_ins_waste_wait_frz++;
+            break;
+        }
+
+	if ( !r_icache_unc_req )
+	{
+	    if ( r_vci_rsp_ins_error ) 
+            {
+                r_icache_error_type = MMU_READ_DATA_ILLEGAL_ACCESS;    
+                r_icache_bad_vaddr = ireq.addr;
+                r_icache_fsm = ICACHE_ERROR;
+
+            	if ( r_icache_inval_tlb_rsp ) r_icache_inval_tlb_rsp = false;
+            	//if ( r_icache_inval_rsp ) r_icache_inval_rsp = false;
+		break;
+            }
+
+	    if ( r_icache_inval_tlb_rsp ) // Miss read response and tlb invalidation
+            {
+                r_icache_inval_tlb_rsp = false;
+                r_icache_fsm = ICACHE_IDLE;
+		break;
+            }
+/*	    
+	    if ( r_icache_inval_rsp ) // Miss read response and cache invalidation
+            {
+                r_icache_inval_rsp = false;
+                r_icache_fsm = ICACHE_IDLE;
+		break;
+            }
+*/
+	    // Miss read response and no invalidation
+            r_icache_buf_unc_valid = true;
+            r_icache_fsm = ICACHE_IDLE;
+	}	
+        break;
+    }
+    //////////////////////
+    case ICACHE_MISS_UPDT:
+    {
+        m_cost_ins_miss_frz++;
+
+        // external cache invalidate request
+        if ( r_tgt_icache_req )   
+        {
+            r_icache_fsm = ICACHE_CC_INVAL;
+            r_icache_fsm_save = r_icache_fsm;
+            m_cost_ins_waste_wait_frz++;
+            break;
+        }
+
+        // external tlb invalidate request
+        if ( r_dcache_itlb_inval_req )
+        {
+	    r_itlb_inval_req = true;
+            r_icache_fsm = ICACHE_TLB_CC_INVAL;
+            r_icache_fsm_save = r_icache_fsm;
+            m_cost_ins_waste_wait_frz++;
+            break;
+        }
+
+        if ( r_icache_inval_tlb_rsp ) // tlb invalidation
+        {
+            r_icache_inval_tlb_rsp = false;
+            r_icache_fsm = ICACHE_IDLE;
+            m_cost_ins_tlb_miss_frz++;
+            break;
+        }
+
+        if ( r_icache_inval_rsp ) // invalidation
+        {
+            r_icache_inval_rsp = false;
+            r_icache_fsm = ICACHE_IDLE;
+            break;
+        } 
+
+        if ( !r_icache_cleanup_req ) // Miss update and no invalidation
+        {
+            data_t* buf = r_icache_miss_buf;
+            paddr_t  victim_index = 0;
+            m_cpt_icache_dir_write++;
+            m_cpt_icache_data_write++;
+
+            r_icache_cleanup_req = r_icache.update(r_icache_paddr_save.read(), buf, &victim_index);
+            r_icache_cleanup_line = victim_index;            
+
+            r_icache_fsm = ICACHE_IDLE;
+        }
+        break;
+    }
+    ///////////////////
+    case ICACHE_ERROR:
+    {
+        r_vci_rsp_ins_error = false;
+        r_dcache_rsp_itlb_error = false;
+        irsp.valid = true;
+        irsp.error = true;
+        irsp.instruction = 0; 
+        r_icache_fsm = ICACHE_IDLE;
+        break;
+    }
+    /////////////////////
+    case ICACHE_CC_INVAL:  
+    {                       
+        if ( ireq.valid ) m_cost_ins_waste_wait_frz++;
+        m_cpt_icache_dir_read += m_icache_ways;
+
+        // invalidate cache
+        if( (( r_icache_fsm_save == ICACHE_MISS_WAIT ) || ( r_icache_fsm_save == ICACHE_MISS_UPDT ) /*|| 
+             ( r_icache_fsm_save == ICACHE_UNC_WAIT )*/ ) && 
+            ((r_icache_paddr_save.read() & ~((m_icache_words<<2)-1)) == (r_tgt_addr.read() & ~((m_icache_words<<2)-1))) ) 
+        {
+            r_icache_inval_rsp = true;
+        } 
+        else 
+        {
+            r_tgt_icache_rsp = r_icache.inval(r_tgt_addr.read());
+        }
+        r_tgt_icache_req = false;
+        r_icache_fsm = r_icache_fsm_save;
+        break;
+    }
+    /////////////////////////
+    case ICACHE_TLB_CC_INVAL:
+    {
+        if ( ireq.valid ) m_cost_ins_waste_wait_frz++;        
+
+	if ( r_itlb_inval_req ) break;
+
+        // invalidate cache
+        if( (( r_icache_fsm_save == ICACHE_TLB1_READ ) || ( r_icache_fsm_save == ICACHE_TLB2_READ )  ||
+             ( r_icache_fsm_save == ICACHE_TLB1_WRITE )|| ( r_icache_fsm_save == ICACHE_TLB2_WRITE ) ||
+             ( r_icache_fsm_save == ICACHE_TLB1_UPDT ) || ( r_icache_fsm_save == ICACHE_TLB2_UPDT )) && 
+            (((r_icache_paddr_save.read() & ~((m_icache_words<<2)-1)) >> (uint32_log2(m_icache_words) + 2) ) == r_dcache_itlb_inval_line.read()) ) 
+        {
+            r_icache_inval_tlb_rsp = true;
+        } 
+        else if (((r_icache_fsm_save == ICACHE_BIS)||(r_icache_fsm_save == ICACHE_MISS_WAIT) ||
+                 (r_icache_fsm_save == ICACHE_UNC_WAIT)||(r_icache_fsm_save == ICACHE_MISS_UPDT)) && 
+                (r_icache_tlb_nline == r_dcache_itlb_inval_line))
+        {
+            r_icache_inval_tlb_rsp = true;
+        }
+	r_dcache_itlb_inval_req = false;
+        r_icache_fsm = r_icache_fsm_save;
+        break;
+    }
+    } // end switch r_icache_fsm
+
+#ifdef SOCLIB_MODULE_DEBUG
+    std::cout << name() << " Instruction Response: " << irsp << std::endl;
+#endif
+
+    ////////////////////////////////////////////////////////////////////////////////////
+    //      INVAL ITLB CHECK FSM 
+    ////////////////////////////////////////////////////////////////////////////////////////
+    switch(r_inval_itlb_fsm) {
+    /////////////////////
+    case INVAL_ITLB_IDLE:
+    {
+        if ( r_itlb_inval_req )
+        {
+            r_ccinval_itlb_way = 0; 
+            r_ccinval_itlb_set = 0;
+            r_inval_itlb_fsm = INVAL_ITLB_CHECK;   
+            m_cost_ins_tlb_inval_frz++; 
+        }   
+        break;
+    }
+    ////////////////////////////
+    case INVAL_ITLB_CHECK:
+    {
+        m_cost_ins_tlb_inval_frz++; 
+
+        size_t way = r_ccinval_itlb_way; 
+        size_t set = r_ccinval_itlb_set;
+        bool end = false;        
+        bool tlb_hit = icache_tlb.cccheck(r_dcache_itlb_inval_line.read(), way, set, &way, &set, &end); 
+    
+        if ( tlb_hit )
+        {
+            r_ccinval_itlb_way = way; 
+            r_ccinval_itlb_set = set;
+            r_itlb_cc_check_end = end;
+            r_inval_itlb_fsm = INVAL_ITLB_INVAL; 
+            m_cpt_ins_tlb_inval++;   
+        }        
+        else
+        {
+            r_inval_itlb_fsm = INVAL_ITLB_CLEAR;    
+        }
+        break;
+    }
+    /////////////////////////
+    case INVAL_ITLB_INVAL:
+    {
+        m_cost_ins_tlb_inval_frz++;
+ 
+        icache_tlb.ccinval(r_ccinval_itlb_way, r_ccinval_itlb_set);
+
+        if ( !r_itlb_cc_check_end )
+        {
+            r_inval_itlb_fsm = INVAL_ITLB_CHECK; 
+        }
+        else
+        {
+            r_inval_itlb_fsm = INVAL_ITLB_CLEAR;    
+        }
+        break;
+    }
+    ////////////////////
+    case INVAL_ITLB_CLEAR:
+    {
+        r_itlb_inval_req = false;
+        r_itlb_cc_check_end = false;
+        r_ccinval_itlb_way = 0; 
+        r_ccinval_itlb_set = 0; 
+        r_inval_itlb_fsm = INVAL_ITLB_IDLE;    
+        m_cost_ins_tlb_inval_frz++; 
+        break;
+    }
+    } // end switch r_inval_itlb_fsm
+
+    ////////////////////////////////////////////////////////////////////////////////////
+    //      DCACHE FSM 
+    //
+    // Both the Cacheability Table, and the MMU cached bit are used to define
+    // the cacheability.
+    // 
+    // There is 14 mutually exclusive conditions to exit the IDLE state.
+    // Seven configurations corresponding to an XTN request from processor:
+    // - Context switch => CTXT_SWITCH state
+    // - Flush dcache => DCACHE_FLUSH state 
+    // - Flush icache => ICACHE_FLUSH state 
+    // - Invalidate a dtlb entry => DTLB_INVAL state
+    // - Invalidate a itlb entry => ITLB_INVAL state
+    // - Invalidate a dcache line => DCACHE_INVAL state
+    // - Invalidate a icache line => ICACHE_INVAL state
+    // Seven configurations corresponding to various read miss or write requests: 
+    // - TLB miss(in case hit_p miss) => TLB1_READ state
+    // - TLB miss(in case hit_p hit) => TLB2_READ state
+    // - Hit in TLB but VPN changed => BIS state
+    // - Cached read miss => MISS_REQ state
+    // - Uncache read miss => UNC_REQ state
+    // - Write hit => WRITE_UPDT state
+    // - Write miss => WRITE_REQ
+    //
+    // The r_vci_rsp_data_error flip-flop is set by the VCI_RSP controller and reset 
+    // by DCACHE-FSM when its state is in DCACHE_ERROR. 
+    //--------------------------------------------------------------------- 
+    // Data TLB: 
+    //  
+    // - int        ET          (00: unmapped; 01: unused or PTD)
+    //                          (10: PTE new;  11: PTE old      )
+    // - bool       cachable    (cached bit)
+    // - bool       writable    (writable bit) 
+    // - bool       executable  (** not used alwayse false)
+    // - bool       user        (access in user mode allowed)
+    // - bool       global      (PTE not invalidated by a TLB flush)
+    // - bool       dirty       (page has been modified) 
+    // - uint32_t   vpn         (virtual page number)
+    // - uint32_t   ppn         (physical page number)
+    ////////////////////////////////////////////////////////////////////////////////////////
+
+    switch (r_dcache_fsm) {
+    //////////////////////
+    case DCACHE_WRITE_REQ:
+    {
+        // external cache invalidate request
+        if ( r_tgt_dcache_req ) 
+        {
+            r_dcache_fsm = DCACHE_CC_CHECK;
+            r_dcache_fsm_save = r_dcache_fsm;
+            if ( dreq.valid ) m_cost_data_waste_wait_frz++; 
+            break;
+        }
+
+        // try to post the write request in the write buffer
+        if ( !r_dcache_write_req )     // no previous write transaction     
+        {
+            if ( r_wbuf.wok(r_dcache_paddr_save) )   // write request in the same cache line 
+            {    
+                r_wbuf.write(r_dcache_paddr_save.read(), r_dcache_be_save.read(), r_dcache_wdata_save);
+                // closing the write packet if uncached
+                if ( !r_dcache_cached_save )
+                { 
+                    r_dcache_write_req = true;
+                }
+            } 
+            else 
+            {    // close the write packet if write request not in the same cache line
+                r_dcache_write_req = true;
+                m_cost_write_frz++;
+                break;  //  posting not possible : stay in DCACHE_WRITEREQ state
+            }
+        } 
+        else     //  previous write transaction not completed
+        {
+            m_cost_write_frz++;
+            break;  //  posting not possible : stay in DCACHE_WRITEREQ state
+        }
+
+        // close the write packet if the next processor request is not a write 
+        if ( !dreq.valid || (dreq.type != iss_t::DATA_WRITE)) 
+        {
+            r_dcache_write_req = true;
+        }
+        
+        // The next state and the processor request parameters are computed 
+        // as in the DCACHE_IDLE state (see below ...)
+    }
+    /////////////////
+    case DCACHE_IDLE:
+    {
+        // external cache invalidate request
+        if ( r_tgt_dcache_req )   
+        {
+            r_dcache_fsm = DCACHE_CC_CHECK;
+            r_dcache_fsm_save = DCACHE_IDLE;
+            if ( dreq.valid ) m_cost_data_waste_wait_frz++;
+            break;
+        }        
+
+        // ins tlb cleanup
+        if ( r_dcache_itlb_cleanup_req )
+        {
+            r_dcache_fsm = DCACHE_ITLB_CLEANUP;
+            m_cpt_ins_tlb_cleanup++;
+            if ( dreq.valid ) m_cost_data_waste_wait_frz++;
+            break;
+        }    
+        // ins tlb miss
+    	if ( r_itlb_read_dcache_req )
+    	{
+            data_t rsp_itlb_miss;
+	    data_t rsp_itlb_ppn;
+
+    	    bool itlb_hit_dcache = r_dcache.read(r_icache_paddr_save, &rsp_itlb_miss);
+	    if ( (r_icache_fsm == ICACHE_TLB2_READ) && itlb_hit_dcache )
+	    {	
+	        bool itlb_hit_ppn = r_dcache.read(r_icache_paddr_save.read()+4, &rsp_itlb_ppn);
+		assert(itlb_hit_ppn && "Address of pte[64-32] and pte[31-0] should be successive");
+	    }
+
+            m_cpt_dcache_data_read += m_dcache_ways;
+            m_cpt_dcache_dir_read += m_dcache_ways;
+
+    	    if ( itlb_hit_dcache )  // ins TLB request hits in data cache 
+    	    {
+                r_dcache_rsp_itlb_miss = rsp_itlb_miss; 
+                r_dcache_rsp_itlb_ppn = rsp_itlb_ppn; 
+    	    	r_itlb_read_dcache_req = false;
+                r_dcache_fsm = DCACHE_IDLE;
+                
+                // set TLB bit if it's a PTE
+                if ( !((rsp_itlb_miss & PTE_T_MASK ) >> PTE_T_SHIFT) )
+                {
+                    r_dcache.setinbit(r_icache_paddr_save, r_dcache_in_itlb, true);
+                }
+    	    }
+    	    else                    // ins TLB request miss in data cache
+    	    {
+                r_dcache_itlb_read_req = true;
+                r_dcache_fsm = DCACHE_ITLB_READ;
+            }
+            if ( dreq.valid ) m_cost_data_waste_wait_frz++; 
+    	}
+    	else if ( r_itlb_acc_dcache_req ) // ins tlb write access bit
+    	{
+            bool write_hit = r_dcache.write(r_icache_paddr_save, r_icache_pte_update);
+            assert(write_hit && "Write on miss ignores data");
+            r_dcache_itlb_ll_acc_req = true;
+	    r_dcache_fsm = DCACHE_ITLB_LL_WAIT;	    		
+            if ( dreq.valid ) m_cost_data_waste_wait_frz++; 
+    	}
+        else if (dreq.valid) 
+        {
+            pte_info_t  dcache_pte_info;
+            int         xtn_opcod        = (int)dreq.addr/4;
+            paddr_t     tlb_dpaddr       = 0;        // physical address obtained from TLB
+            paddr_t     spc_dpaddr       = 0;        // physical adress obtained from PPN_save (speculative)
+            bool        dcache_hit_t     = false;    // hit on 4Kilo TLB
+            bool        dcache_hit_x     = false;    // VPN unmodified (can use spc_dpaddr)
+            bool        dcache_hit_p     = false;    // PTP unmodified (can skip first level page table walk)
+            bool        dcache_hit_c     = false;    // Cache hit
+            bool        dcache_cached    = false;    // cacheable access (read or write)
+            size_t      dcache_tlb_way   = 0;        // selected way (in case of cache hit)
+            size_t      dcache_tlb_set   = 0;        // selected set (Y field in address)
+            data_t      dcache_rdata     = 0;        // read data
+            paddr_t     dcache_tlb_nline = 0;       // TLB NLINE 
+
+            m_cpt_dcache_data_read += m_dcache_ways;
+            m_cpt_dcache_dir_read += m_dcache_ways;
+
+            // Decoding READ XTN requests from processor
+            // They are executed in this DCACHE_IDLE state
+
+            if (dreq.type == iss_t::XTN_READ) 
+            {
+                switch(xtn_opcod) {
+                case iss_t::XTN_INS_ERROR_TYPE:
+                    drsp.rdata = (uint32_t)r_icache_error_type;
+                    r_icache_error_type = MMU_NONE;
+                    drsp.valid = true;
+                    drsp.error = false;
+                    break;
+                case iss_t::XTN_DATA_ERROR_TYPE:
+                    drsp.rdata = (uint32_t)r_dcache_error_type;
+                    r_dcache_error_type = MMU_NONE;
+                    drsp.valid = true;
+                    drsp.error = false;
+                    break;
+                case iss_t::XTN_INS_BAD_VADDR:
+                    drsp.rdata = (uint32_t)r_icache_bad_vaddr;       
+                    drsp.valid = true;
+                    drsp.error = false;
+                    break;
+                case iss_t::XTN_DATA_BAD_VADDR:
+                    drsp.rdata = (uint32_t)r_dcache_bad_vaddr;        
+                    drsp.valid = true;
+                    drsp.error = false;
+                    break;
+                case iss_t::XTN_PTPR:
+                    drsp.rdata = (uint32_t)r_mmu_ptpr;
+                    drsp.valid = true;
+                    drsp.error = false;
+                    break;
+                case iss_t::XTN_TLB_MODE:
+                    drsp.rdata = (uint32_t)r_mmu_mode;
+                    drsp.valid = true;
+                    drsp.error = false;
+                    break;
+                case iss_t::XTN_MMU_PARAMS:
+                    drsp.rdata = (uint32_t)r_mmu_params;
+                    drsp.valid = true;
+                    drsp.error = false;
+                    break;
+                case iss_t::XTN_MMU_RELEASE:
+                    drsp.rdata = (uint32_t)r_mmu_release;
+                    drsp.valid = true;
+                    drsp.error = false;
+                    break;
+                default:
+                    r_dcache_error_type = MMU_READ_UNDEFINED_XTN; 
+                    r_dcache_bad_vaddr  = dreq.addr;
+                    drsp.valid = true;
+                    drsp.error = true;
+                    break;
+                }
+                r_dcache_fsm = DCACHE_IDLE;
+                break;
+            }
+
+            // Decoding WRITE XTN requests from processor
+            // If there is no privilege violation, they are not executed in this DCACHE_IDLE state,
+            // but in the next state, because they generally require access to the caches or the TLBs 
+
+            if (dreq.type == iss_t::XTN_WRITE) 
+            {
+                drsp.valid = false;
+                drsp.error = false;
+                drsp.rdata = 0;
+                r_dcache_wdata_save = dreq.wdata;   
+                switch(xtn_opcod) {     
+
+                case iss_t::XTN_PTPR:       // context switch : checking the kernel mode
+                                            // both instruction & data TLBs must be flushed
+                    if ((dreq.mode == iss_t::MODE_HYPER) || (dreq.mode == iss_t::MODE_KERNEL)) 
+                    {
+                        r_mmu_ptpr = dreq.wdata;
+                        r_icache_error_type = MMU_NONE;
+                        r_dcache_error_type = MMU_NONE;
+                        r_dcache_type_save = dreq.addr/4; 
+                        r_dcache_xtn_req = true;
+                        r_dcache_fsm = DCACHE_CTXT_SWITCH;
+                    } 
+                    else 
+                    { 
+                        r_dcache_error_type = MMU_WRITE_PRIVILEGE_VIOLATION; 
+                        r_dcache_bad_vaddr  = dreq.addr;
+                        drsp.valid = true;
+                        drsp.error = true;
+                	r_dcache_fsm = DCACHE_IDLE;
+                    }
+                    break;
+
+                case iss_t::XTN_TLB_MODE:     // modifying TLBs mode : checking the kernel mode
+                    if ((dreq.mode == iss_t::MODE_HYPER) || (dreq.mode == iss_t::MODE_KERNEL)) 
+                    {
+                        r_mmu_mode = (int)dreq.wdata;
+                        drsp.valid = true;
+                    } 
+                    else 
+                    {
+                        r_dcache_error_type = MMU_WRITE_PRIVILEGE_VIOLATION; 
+                        r_dcache_bad_vaddr  = dreq.addr;
+                        drsp.valid = true;
+                        drsp.error = true;
+                    }
+                    r_dcache_fsm = DCACHE_IDLE;
+                    break;
+
+                case iss_t::XTN_DTLB_INVAL:     //  checking the kernel mode
+                    if ((dreq.mode == iss_t::MODE_HYPER) || (dreq.mode == iss_t::MODE_KERNEL)) 
+                    {
+                        r_dcache_fsm = DCACHE_DTLB_INVAL;  
+                    } 
+                    else 
+                    {
+                        r_dcache_error_type = MMU_WRITE_PRIVILEGE_VIOLATION; 
+                        r_dcache_bad_vaddr  = dreq.addr;
+                        drsp.valid = true;
+                        drsp.error = true;
+                	r_dcache_fsm = DCACHE_IDLE;
+                    }
+                    break;
+
+                case iss_t::XTN_ITLB_INVAL:     //  checking the kernel mode
+                    if ((dreq.mode == iss_t::MODE_HYPER) || (dreq.mode == iss_t::MODE_KERNEL)) 
+                    {
+                        r_dcache_xtn_req = true;
+                        r_dcache_type_save = dreq.addr/4;
+                        r_dcache_fsm = DCACHE_ITLB_INVAL;  
+                    } 
+                    else 
+                    {
+                        r_dcache_error_type = MMU_WRITE_PRIVILEGE_VIOLATION; 
+                        r_dcache_bad_vaddr  = dreq.addr;
+                        drsp.valid = true;
+                        drsp.error = true;
+                	r_dcache_fsm = DCACHE_IDLE;
+                    }
+                    break;
+
+                case iss_t::XTN_DCACHE_INVAL:   // cache inval can be executed in user mode.
+                    r_dcache_fsm = DCACHE_DCACHE_INVAL;
+                    break;
+
+                case iss_t::XTN_DCACHE_FLUSH:   // cache flush can be executed in user mode.
+                    r_dcache_type_save = dreq.addr/4; 
+                    r_dcache_xtn_req = true;
+                    r_dcache_way = 0;
+                    r_dcache_set = 0;
+                    r_dcache_fsm = DCACHE_DCACHE_FLUSH; 
+                    break;
+
+                case iss_t::XTN_ICACHE_INVAL:   // cache inval can be executed in user mode.
+                    r_dcache_type_save = dreq.addr/4; 
+                    r_dcache_xtn_req = true;
+                    r_dcache_fsm = DCACHE_ICACHE_INVAL; 
+                    break;
+
+                case iss_t::XTN_ICACHE_FLUSH:   // cache flush can be executed in user mode.
+                    r_dcache_type_save = dreq.addr/4; 
+                    r_dcache_xtn_req = true; 
+                    r_dcache_fsm = DCACHE_ICACHE_FLUSH;
+                    break;
+
+                case iss_t::XTN_SYNC:           // cache synchronization can be executed in user mode.
+                    if (r_wbuf.rok())
+                    {
+                        r_dcache_fsm = DCACHE_DCACHE_SYNC; 
+                    }
+                    else
+                    {
+                        drsp.valid = true;
+                        r_dcache_fsm = DCACHE_IDLE;
+                    }
+		    break;
+	
+                default:
+                    r_dcache_error_type = MMU_WRITE_UNDEFINED_XTN; 
+                    r_dcache_bad_vaddr  = dreq.addr;
+                    drsp.valid = true;
+                    drsp.error = true;
+                    r_dcache_fsm = DCACHE_IDLE;
+                    break;
+                } // end switch xtn_opcod
+
+                break;
+            } // end if XTN_WRITE
+
+            // Evaluating dcache_hit_t, dcache_hit_x, dcache_hit_p, dcache_hit_c,
+            // dcache_pte_info, dcache_tlb_way, dcache_tlb_set & dpaddr & cacheability 
+            // - If MMU activated : cacheability is defined by the cachable bit in the TLB
+            // - If MMU not activated : cacheability is defined by the segment table.
+
+            if ( !(r_mmu_mode.read() & DATA_TLB_MASK) ) // MMU not activated
+            {
+                dcache_hit_t  = true;       
+                dcache_hit_x  = true;   
+                dcache_hit_p  = true;  
+                tlb_dpaddr    = dreq.addr; 
+                spc_dpaddr    = dreq.addr;    
+                dcache_cached = m_cacheability_table[dreq.addr] && 
+                                ((dreq.type != iss_t::DATA_LL)  && (dreq.type != iss_t::DATA_SC) &&
+                                 (dreq.type != iss_t::XTN_READ) && (dreq.type != iss_t::XTN_WRITE));     
+            } 
+            else                                                            // MMU activated
+            {
+                m_cpt_data_tlb_read++;
+                dcache_hit_t  = dcache_tlb.cctranslate(dreq.addr, &tlb_dpaddr, &dcache_pte_info, 
+                                                       &dcache_tlb_nline, &dcache_tlb_way, &dcache_tlb_set);                  
+                dcache_hit_x  = (((vaddr_t)r_dcache_vpn_save << PAGE_K_NBITS) == (dreq.addr & ~PAGE_K_MASK)) && r_dtlb_translation_valid; 
+                dcache_hit_p  = (((dreq.addr >> PAGE_M_NBITS) == r_dcache_id1_save) && r_dcache_ptba_ok );
+                spc_dpaddr    = ((paddr_t)r_dcache_ppn_save << PAGE_K_NBITS) | (paddr_t)((dreq.addr & PAGE_K_MASK));
+                dcache_cached = dcache_pte_info.c && 
+                                ((dreq.type != iss_t::DATA_LL)  && (dreq.type != iss_t::DATA_SC) &&
+                                 (dreq.type != iss_t::XTN_READ) && (dreq.type != iss_t::XTN_WRITE));    
+            }
+
+            if ( !(r_mmu_mode.read() & DATA_CACHE_MASK) )   // cache not actived
+            {
+                dcache_cached = false;
+            }
+
+            // dcache_hit_c & dcache_rdata
+            if ( dcache_cached )    // using speculative physical address for cached access
+            {
+                dcache_hit_c = r_dcache.read(spc_dpaddr, &dcache_rdata);
+            } 
+            else                    // using actual physical address for uncached access
+            {
+                dcache_hit_c = ((tlb_dpaddr == (paddr_t)r_dcache_paddr_save) && r_dcache_buf_unc_valid ); 
+                dcache_rdata = r_dcache_miss_buf[0];
+            }
+
+            if ( r_mmu_mode.read() & DATA_TLB_MASK ) 
+            {
+                // Checking access rights
+                if ( dcache_hit_t ) 
+                {
+                    if (!dcache_pte_info.u && (dreq.mode == iss_t::MODE_USER)) 
+                    {
+                        if ((dreq.type == iss_t::DATA_READ)||(dreq.type == iss_t::DATA_LL))
+                        {
+                            r_dcache_error_type = MMU_READ_PRIVILEGE_VIOLATION;
+                        }
+                        else /*if ((dreq.type == iss_t::DATA_WRITE)||(dreq.type == iss_t::DATA_SC))*/
+                        {
+                            r_dcache_error_type = MMU_WRITE_PRIVILEGE_VIOLATION;
+                        }  
+                        r_dcache_bad_vaddr = dreq.addr;
+                        drsp.valid = true;
+                        drsp.error = true;
+                        drsp.rdata = 0;
+                        r_dcache_fsm = DCACHE_IDLE;
+                        break;
+                    }
+                    if (!dcache_pte_info.w && ((dreq.type == iss_t::DATA_WRITE)||(dreq.type == iss_t::DATA_SC))) 
+                    {
+                        r_dcache_error_type = MMU_WRITE_ACCES_VIOLATION;  
+                        r_dcache_bad_vaddr = dreq.addr;
+                        drsp.valid = true;
+                        drsp.error = true;
+                        drsp.rdata = 0;
+                        r_dcache_fsm = DCACHE_IDLE;
+                        break;
+                    }
+                }
+
+                // update LRU, save ppn, vpn and page type
+                if ( dcache_hit_t ) {
+                    dcache_tlb.setlru(dcache_tlb_way,dcache_tlb_set); 
+                    r_dcache_ppn_save = tlb_dpaddr >> PAGE_K_NBITS;
+                    r_dcache_vpn_save = dreq.addr >> PAGE_K_NBITS;
+                    r_dcache_tlb_nline = dcache_tlb_nline;
+                    r_dtlb_translation_valid = true;
+                }
+                else
+                {
+                    r_dtlb_translation_valid = false;
+                }
+
+            } // end if MMU activated
+
+            // compute next state 
+            if ( !dcache_hit_p && !dcache_hit_t )  // TLB miss
+            {
+                r_dcache_tlb_paddr = (paddr_t)r_mmu_ptpr << (INDEX1_NBITS+2) | (paddr_t)((dreq.addr>>PAGE_M_NBITS)<<2);
+                r_dcache_fsm = DCACHE_DTLB1_READ_CACHE;
+                m_cpt_data_tlb_miss++;
+                m_cost_data_tlb_miss_frz++;
+            }
+            else if ( dcache_hit_p && !dcache_hit_t )  // TLB Miss with possibility of bypass first level page
+            {
+                // walk page table level 2
+                r_dcache_tlb_paddr = (paddr_t)r_dcache_ptba_save | 
+                                     (paddr_t)(((dreq.addr&PTD_ID2_MASK)>>PAGE_K_NBITS) << 3); 
+                r_dcache_fsm = DCACHE_DTLB2_READ_CACHE;
+                m_cpt_data_tlb_miss++;
+                m_cost_data_tlb_miss_frz++;
+            }
+            else if ( dcache_hit_t && !dcache_hit_x && dcache_cached )// cached access with an ucorrect speculative physical address
+            {
+                r_dcache_hit_p_save = dcache_hit_p;
+                r_dcache_fsm = DCACHE_BIS;
+                m_cost_data_miss_frz++;
+            }
+            else  // cached or uncached access with a correct speculative physical address
+            {
+                switch( dreq.type ) {
+                    case iss_t::DATA_READ:
+                    case iss_t::DATA_LL:
+                    case iss_t::DATA_SC:
+                        m_cpt_read++;
+                        if ( dcache_hit_c ) 
+                        {
+                            r_dcache_buf_unc_valid = false;
+                            r_dcache_fsm = DCACHE_IDLE;
+                            drsp.valid = true;
+                            drsp.rdata = dcache_rdata;
+                        } 
+                        else 
+                        {
+                            if ( dcache_cached ) 
+                            {
+                                r_dcache_miss_req = true;
+                                r_dcache_fsm = DCACHE_MISS_WAIT;
+                                m_cpt_data_miss++;
+                                m_cost_data_miss_frz++;
+                            } 
+                            else 
+                            {
+                                r_dcache_unc_req = true;
+                                r_dcache_fsm = DCACHE_UNC_WAIT;
+                                m_cpt_unc_read++;
+                                m_cost_unc_read_frz++;
+                            }
+                        }
+                        break;
+/*
+                    case iss_t::DATA_READ:
+                        m_cpt_read++;
+                        if ( dcache_hit_c ) 
+                        {
+                            r_dcache_buf_unc_valid = false;
+                            r_dcache_fsm = DCACHE_IDLE;
+                            drsp.valid = true;
+                            drsp.rdata = dcache_rdata;
+                        } 
+                        else 
+                        {
+                            if ( dcache_cached ) 
+                            {
+                                r_dcache_miss_req = true;
+                                r_dcache_fsm = DCACHE_MISS_WAIT;
+                                m_cpt_data_miss++;
+                                m_cost_data_miss_frz++;
+                            } 
+                            else 
+                            {
+                                r_dcache_unc_req = true;
+                                r_dcache_fsm = DCACHE_UNC_WAIT;
+                                m_cpt_unc_read++;
+                                m_cost_unc_read_frz++;
+                            }
+                        }
+                        break;
+                    case iss_t::DATA_LL:
+			if (r_dcache_llsc_reserved && (r_dcache_llsc_addr_save == tlb_dpaddr) && r_dcache_buf_unc_valid)
+			{
+                            r_dcache_buf_unc_valid = false;
+                            r_dcache_fsm = DCACHE_IDLE;
+                            drsp.valid = true;
+                            drsp.rdata = dcache_rdata;
+			}
+			else
+			{
+			    r_dcache_llsc_reserved = true;
+			    r_dcache_llsc_addr_save = tlb_dpaddr;
+                            r_dcache_unc_req = true;
+                            r_dcache_fsm = DCACHE_UNC_WAIT;
+			}
+			break;
+                    case iss_t::DATA_SC:
+			if (r_dcache_llsc_reserved && (r_dcache_llsc_addr_save == tlb_dpaddr))
+			{
+			    r_dcache_llsc_reserved = false;
+                            r_dcache_unc_req = true;
+                            r_dcache_fsm = DCACHE_UNC_WAIT;
+			}
+			else
+			{   
+			    if ( r_dcache_buf_unc_valid )
+			    {                         
+			        r_dcache_llsc_reserved = false;
+			        r_dcache_buf_unc_valid = false;
+                                drsp.valid = true;
+                                drsp.rdata = dcache_rdata;
+			    }
+                            r_dcache_fsm = DCACHE_IDLE;
+			}			
+			break;
+*/
+                    case iss_t::DATA_WRITE:
+                        m_cpt_write++;
+                        if ( dcache_cached ) m_cpt_write_cached++;
+
+                        if ( dcache_hit_c && dcache_cached )    // cache update required
+                        {
+                            r_dcache_fsm = DCACHE_WRITE_UPDT;
+                        } 
+                        else if ( !dcache_pte_info.d && (r_mmu_mode.read() & DATA_TLB_MASK) )   // dirty bit update required
+                        {
+                            if ( dcache_tlb.getpagesize(dcache_tlb_way, dcache_tlb_set) )	// 2M page size, one level page table 
+                            {
+                                r_dcache_pte_update = dcache_tlb.getpte(dcache_tlb_way, dcache_tlb_set) | PTE_D_MASK;
+                                r_dcache_tlb_paddr = (paddr_t)r_mmu_ptpr << (INDEX1_NBITS+2) | (paddr_t)((dreq.addr>>PAGE_M_NBITS)<<2);
+                                r_dcache_tlb_ll_dirty_req = true;
+                                r_dcache_fsm = DCACHE_LL_DIRTY_WAIT;
+                                m_cpt_data_tlb_write_dirty++;
+                            }
+                            else	// 4k page size, two levels page table 
+                            {   
+                                if (dcache_hit_p) 
+                                {
+                                    r_dcache_pte_update = dcache_tlb.getpte(dcache_tlb_way, dcache_tlb_set) | PTE_D_MASK;
+                                    r_dcache_tlb_paddr = (paddr_t)r_dcache_ptba_save | (paddr_t)(((dreq.addr&PTD_ID2_MASK)>>PAGE_K_NBITS) << 3);
+                                    r_dcache_tlb_ll_dirty_req = true;
+                                    r_dcache_fsm = DCACHE_LL_DIRTY_WAIT;
+                                    m_cpt_data_tlb_write_dirty++;
+                                }
+                                else    // get PTBA to calculate the physical address of PTE
+                                {
+                                    r_dcache_pte_update = dcache_tlb.getpte(dcache_tlb_way, dcache_tlb_set) | PTE_D_MASK;
+                                    r_dcache_tlb_paddr = (paddr_t)r_mmu_ptpr << (INDEX1_NBITS+2) | (paddr_t)((dreq.addr>>PAGE_M_NBITS)<<2);
+                                    r_dcache_tlb_ptba_read = true;
+                                    r_dcache_fsm = DCACHE_DTLB1_READ_CACHE;
+                                }
+                            }
+                            m_cost_data_tlb_miss_frz++;
+                        }
+                        else                                    // no cache update, not dirty bit update
+                        {
+                            r_dcache_fsm = DCACHE_WRITE_REQ;
+                            drsp.valid = true;
+                            drsp.rdata = 0;
+                        }
+                        break;
+                    default:
+                        break;
+                } // end switch dreq.type
+            } // end if next states
+
+            // save values for the next states
+            r_dcache_paddr_save   = tlb_dpaddr;
+            r_dcache_type_save    = dreq.type;
+            r_dcache_wdata_save   = dreq.wdata;
+            r_dcache_be_save      = dreq.be;
+            r_dcache_rdata_save   = dcache_rdata;
+            r_dcache_cached_save  = dcache_cached;
+            r_dcache_dirty_save   = dcache_pte_info.d;
+            r_dcache_tlb_set_save = dcache_tlb_set;
+            r_dcache_tlb_way_save = dcache_tlb_way;
+
+        } // end if dreq.valid
+        else 
+        {   
+            r_dcache_fsm = DCACHE_IDLE;
+        }
+
+        // processor request are not accepted in the WRITE_REQ state 
+        // when the write buffer is not writeable
+
+        if ((r_dcache_fsm == DCACHE_WRITE_REQ) && 
+            (r_dcache_write_req || !r_wbuf.wok(r_dcache_paddr_save))) 
+        {
+            drsp.valid = false;
+        }
+        break;
+    }
+    /////////////////
+    case DCACHE_BIS:
+    {
+        // external cache invalidate request
+        if ( r_tgt_dcache_req )   
+        {
+            r_dcache_fsm = DCACHE_CC_CHECK;
+            r_dcache_fsm_save = r_dcache_fsm;
+            m_cost_data_waste_wait_frz++;
+            break;
+        }
+
+        // Using tlb entry is invalidated 
+        if ( r_dcache_inval_tlb_rsp )
+        {
+            r_dcache_inval_tlb_rsp = false;
+            r_dcache_fsm = DCACHE_IDLE;
+            m_cost_data_tlb_miss_frz++;
+            break;
+        }
+
+        data_t  dcache_rdata = 0;
+        bool    dcache_hit_c = false;
+        bool    dcache_hit_t = false;
+        paddr_t tlb_dpaddr   = 0;
+
+	dcache_hit_t = dcache_tlb.translate(dreq.addr, &tlb_dpaddr);
+
+	if ( (tlb_dpaddr == r_dcache_paddr_save.read()) && dreq.valid && dcache_hit_t ) 
+	{
+	    // acces always cached in this state
+	    dcache_hit_c = r_dcache.read(r_dcache_paddr_save, &dcache_rdata);
+	    
+	    if ( dreq.type == iss_t::DATA_READ )  // cached read
+	    {
+	        m_cpt_read++;
+	        if ( !dcache_hit_c ) 
+	        {
+	            r_dcache_miss_req = true;
+	            r_dcache_fsm = DCACHE_MISS_WAIT;
+	            m_cpt_data_miss++;
+	            m_cost_data_miss_frz++;
+	        }
+	        else
+	        {
+	            r_dcache_fsm = DCACHE_IDLE;
+	        }
+	        drsp.valid = dcache_hit_c;
+	        drsp.error = false;
+	        drsp.rdata = dcache_rdata;
+	    }
+	    else    // cached write
+	    {
+	        m_cpt_write++;
+	        m_cpt_write_cached++;
+	        if ( dcache_hit_c )    // cache update required
+	        {
+	            r_dcache_rdata_save = dcache_rdata;
+	            r_dcache_fsm = DCACHE_WRITE_UPDT;
+	        } 
+	        else if (!r_dcache_dirty_save && (r_mmu_mode.read() & DATA_TLB_MASK))   // dirty bit update required
+	        {
+	            if (dcache_tlb.getpagesize(r_dcache_tlb_way_save, r_dcache_tlb_set_save)) 
+	            {
+	                r_dcache_pte_update = dcache_tlb.getpte(r_dcache_tlb_way_save, r_dcache_tlb_set_save) | PTE_D_MASK;
+	                r_dcache_tlb_paddr = (paddr_t)r_mmu_ptpr << (INDEX1_NBITS+2) | (paddr_t)((dreq.addr>>PAGE_M_NBITS)<<2);
+	                r_dcache_tlb_ll_dirty_req = true;
+	                r_dcache_fsm = DCACHE_LL_DIRTY_WAIT;
+	                m_cpt_data_tlb_write_dirty++;
+	            }
+	            else
+	            {   
+	                if (r_dcache_hit_p_save) 
+	                {
+	                    r_dcache_pte_update = dcache_tlb.getpte(r_dcache_tlb_way_save, r_dcache_tlb_set_save) | PTE_D_MASK;
+	                    r_dcache_tlb_paddr = (paddr_t)r_dcache_ptba_save|(paddr_t)(((dreq.addr&PTD_ID2_MASK)>>PAGE_K_NBITS) << 3);
+	                    r_dcache_tlb_ll_dirty_req = true;
+	                    r_dcache_fsm = DCACHE_LL_DIRTY_WAIT;
+	                    m_cpt_data_tlb_write_dirty++;
+	                }
+	                else
+	                {
+	                    r_dcache_pte_update = dcache_tlb.getpte(r_dcache_tlb_way_save, r_dcache_tlb_set_save) | PTE_D_MASK;
+	                    r_dcache_tlb_paddr = (paddr_t)r_mmu_ptpr << (INDEX1_NBITS+2) | (paddr_t)((dreq.addr>>PAGE_M_NBITS)<<2);
+	                    r_dcache_tlb_ptba_read = true;
+	                    r_dcache_fsm = DCACHE_DTLB1_READ_CACHE;
+	                }
+	            }
+	            m_cost_data_tlb_miss_frz++;
+	        }
+	        else                                    // no cache update, not dirty bit update
+	        {
+	            r_dcache_fsm = DCACHE_WRITE_REQ;
+	            drsp.valid = true;
+	            drsp.rdata = 0;
+	        }
+	    }
+	}
+	else
+	{
+            drsp.valid = false;
+            drsp.error = false;
+            drsp.rdata = 0;
+            r_dcache_fsm = DCACHE_IDLE;
+	}
+        break;
+    }
+    //////////////////////////
+    case DCACHE_LL_DIRTY_WAIT:
+    {
+        // external cache invalidate request
+        if ( r_tgt_dcache_req )   
+        {
+            r_dcache_fsm = DCACHE_CC_CHECK;
+            r_dcache_fsm_save = r_dcache_fsm;
+            m_cost_data_waste_wait_frz++;
+            break;
+        }
+
+	if (!r_dcache_tlb_ll_dirty_req)
+	{
+            if ( r_vci_rsp_data_error ) // VCI response ko
+            {
+		if (dcache_tlb.getpagesize(r_dcache_tlb_way_save, r_dcache_tlb_set_save)) 
+		{
+                    r_dcache_error_type = MMU_WRITE_PT1_ILLEGAL_ACCESS;     
+		}
+		else
+		{
+                    r_dcache_error_type = MMU_WRITE_PT2_ILLEGAL_ACCESS;     
+		}
+                r_dcache_bad_vaddr = dreq.addr;
+                r_dcache_fsm = DCACHE_ERROR; 
+
+		if (r_dcache_inval_tlb_rsp) r_dcache_inval_tlb_rsp = false;
+		if (r_dcache_inval_rsp) r_dcache_inval_rsp = false;
+            }
+	    else
+	    {
+		if ( !(r_dcache_miss_buf[0] >> PTE_V_SHIFT) )	// unmapped
+	        {
+		    if (dcache_tlb.getpagesize(r_dcache_tlb_way_save, r_dcache_tlb_set_save))
+		    { 
+			r_dcache_error_type = MMU_WRITE_PT1_UNMAPPED;       
+		    }
+		    else
+		    {
+			r_dcache_error_type = MMU_WRITE_PT2_UNMAPPED;       
+	  	    }
+                    r_dcache_bad_vaddr = dreq.addr;
+                    r_dcache_fsm = DCACHE_ERROR;
+
+		    if (r_dcache_inval_tlb_rsp) r_dcache_inval_tlb_rsp = false;
+		    if (r_dcache_inval_rsp) r_dcache_inval_rsp = false;
+	        }
+        	else if ( r_dcache_inval_tlb_rsp )
+        	{
+        	    r_dcache_inval_tlb_rsp = false;
+        	    r_dcache_fsm = DCACHE_IDLE;
+        	    m_cost_data_tlb_miss_frz++;
+        	}
+		else if ( r_dcache_inval_rsp )
+		{
+        	    r_dcache_inval_rsp = false;
+		    r_dcache_fsm = DCACHE_IDLE;
+		}
+		else
+		{
+		    r_dcache_tlb_sc_dirty_req = true;
+		    r_dcache_pte_update = r_dcache_miss_buf[0] | r_dcache_pte_update.read();
+                    r_dcache_fsm = DCACHE_SC_DIRTY_WAIT; 
+		}
+	    }
+	}
+	break;
+    }
+    //////////////////////////
+    case DCACHE_SC_DIRTY_WAIT:
+    {
+        // external cache invalidate request
+        if ( r_tgt_dcache_req )   
+        {
+            r_dcache_fsm = DCACHE_CC_CHECK;
+            r_dcache_fsm_save = r_dcache_fsm;
+            m_cost_data_waste_wait_frz++;
+            break;
+        }
+
+	if ( !r_dcache_tlb_sc_dirty_req )
+	{
+	    if ( r_vci_rsp_data_error ) // VCI response ko
+	    {
+	        if (dcache_tlb.getpagesize(r_dcache_tlb_way_save, r_dcache_tlb_set_save))
+	        {
+	            r_dcache_error_type = MMU_WRITE_PT1_ILLEGAL_ACCESS;    
+	        }
+	        else
+	        {
+	            r_dcache_error_type = MMU_WRITE_PT2_ILLEGAL_ACCESS;    
+	        }
+	        r_dcache_bad_vaddr = dreq.addr;
+	        r_dcache_fsm = DCACHE_ERROR;
+
+		if (r_dcache_inval_tlb_rsp) r_dcache_inval_tlb_rsp = false;
+		if (r_dcache_inval_rsp) r_dcache_inval_rsp = false;		 		         }
+	    else 
+	    {
+                // Using tlb entry is invalidated 
+                if ( r_dcache_inval_tlb_rsp )
+                {
+                    r_dcache_inval_tlb_rsp = false;
+                    r_dcache_fsm = DCACHE_IDLE;
+                    m_cost_data_tlb_miss_frz++;
+                }
+		else if ( r_dcache_inval_rsp )
+		{
+        	    r_dcache_inval_rsp = false;
+		    r_dcache_fsm = DCACHE_IDLE;
+		}
+		else if ( r_dcache_tlb_ll_dirty_req )
+	        {
+	            r_dcache_fsm = DCACHE_LL_DIRTY_WAIT; 
+	        }
+		else
+		{
+	            r_dcache_fsm = DCACHE_WRITE_DIRTY; 
+		}
+	    }
+	}
+	break;
+    }
+    ////////////////////////////
+    case DCACHE_DTLB1_READ_CACHE:
+    {
+        m_cost_data_tlb_miss_frz++;
+
+        // external cache invalidate request
+        if ( r_tgt_dcache_req )   
+        {
+            r_dcache_fsm = DCACHE_CC_CHECK;
+            r_dcache_fsm_save = r_dcache_fsm;
+            m_cost_data_waste_wait_frz++;
+            break;
+        }        
+
+        // Using tlb entry is invalidated 
+        if ( r_dcache_inval_tlb_rsp )
+        {
+            r_dcache_inval_tlb_rsp = false;
+            r_dcache_fsm = DCACHE_IDLE;
+            m_cost_data_tlb_miss_frz++;
+            break;
+        }
+
+        data_t tlb_data = 0;
+	bool write_hit = false;
+        bool tlb_hit_cache = r_dcache.read(r_dcache_tlb_paddr, &tlb_data);
+
+        // DTLB request hit in cache
+        if ( tlb_hit_cache )
+        {
+	    if ( !(tlb_data >> PTE_V_SHIFT) )	// unmapped
+	    {
+                r_dcache_ptba_ok    = false;
+                if ((r_dcache_type_save == iss_t::DATA_READ)||(r_dcache_type_save == iss_t::DATA_LL))
+                {
+                    r_dcache_error_type = MMU_READ_PT1_UNMAPPED;
+                }
+                else /*if ((dreq.type == iss_t::DATA_WRITE)||(dreq.type == iss_t::DATA_SC))*/
+                {
+                    r_dcache_error_type = MMU_WRITE_PT1_UNMAPPED;
+                }  
+                r_dcache_bad_vaddr  = dreq.addr;
+                r_dcache_fsm        = DCACHE_ERROR;
+	    }
+	    else if ( (tlb_data & PTE_T_MASK) >> PTE_T_SHIFT )	// PTD
+	    {
+                r_dcache_ptba_ok   = true;
+                r_dcache_ptba_save = (paddr_t)(tlb_data & ((1<<(m_paddr_nbits - PAGE_K_NBITS))-1)) << PAGE_K_NBITS;  
+                r_dcache_id1_save  = dreq.addr >> PAGE_M_NBITS;
+                r_dcache_tlb_paddr = (paddr_t)(tlb_data & ((1<<(m_paddr_nbits - PAGE_K_NBITS))-1)) << PAGE_K_NBITS | 
+                                     (paddr_t)(((dreq.addr & PTD_ID2_MASK) >> PAGE_K_NBITS) << 3);
+                if ( r_dcache_tlb_ptba_read )
+                {
+                    r_dcache_tlb_ptba_read = false;
+                    write_hit = r_dcache.write(((paddr_t)(tlb_data & ((1<<(m_paddr_nbits - PAGE_K_NBITS))-1)) << PAGE_K_NBITS | 
+                                                (paddr_t)(((dreq.addr & PTD_ID2_MASK) >> PAGE_K_NBITS) << 3)), r_dcache_pte_update);
+                    assert(write_hit && "Write on miss ignores data");
+                    r_dcache_tlb_ll_dirty_req = true;
+                    r_dcache_fsm = DCACHE_LL_DIRTY_WAIT;
+                    m_cpt_data_tlb_write_dirty++;
+                }
+                else
+                {
+                    r_dcache_fsm = DCACHE_DTLB2_READ_CACHE;
+                }
+	    }
+	    else	// PTE
+	    {
+                r_dcache_ptba_ok = false;
+	        if ( (m_srcid >> 4) == ((r_dcache_tlb_paddr.read() & ((1<<(m_paddr_nbits - PAGE_M_NBITS))-1)) >> (m_paddr_nbits - PAGE_M_NBITS -10)) ) // local
+		{
+		    if ( (tlb_data & PTE_L_MASK ) >> PTE_L_SHIFT ) // L bit is set
+		    {
+                        r_dcache_pte_update = tlb_data;
+                        r_dcache_fsm = DCACHE_TLB1_UPDT;
+		    }
+		    else
+		    {
+                        r_dcache_pte_update = tlb_data | PTE_L_MASK;
+                        r_dcache_tlb_ll_acc_req = true;
+                	write_hit = r_dcache.write(r_dcache_tlb_paddr,(tlb_data | PTE_L_MASK));  
+                	assert(write_hit && "Write on miss ignores data");  
+                        r_dcache_fsm = DCACHE_TLB1_LL_WAIT;
+                        m_cpt_ins_tlb_write_et++;
+		    }
+    	        }
+		else // remotely
+		{
+		    if ( (tlb_data & PTE_R_MASK ) >> PTE_R_SHIFT ) // R bit is set
+		    {
+                        r_dcache_pte_update = tlb_data;
+                        r_dcache_fsm = DCACHE_TLB1_UPDT;
+		    }
+		    else
+		    {
+                        r_dcache_pte_update = tlb_data | PTE_R_MASK;
+                        r_dcache_tlb_ll_acc_req = true;
+                	write_hit = r_dcache.write(r_dcache_tlb_paddr,(tlb_data | PTE_R_MASK));  
+                	assert(write_hit && "Write on miss ignores data");  
+                        r_dcache_fsm = DCACHE_TLB1_LL_WAIT;
+                        m_cpt_ins_tlb_write_et++;
+		    }
+		}
+	    }
+        }
+        else
+        {
+            // DTLB request miss in cache and walk page table level 1
+            r_dcache_tlb_read_req = true;
+            r_dcache_fsm = DCACHE_TLB1_READ;
+        }
+        break;
+    }
+    ///////////////////////
+    case DCACHE_TLB1_LL_WAIT:
+    {
+        // external cache invalidate request
+        if ( r_tgt_dcache_req )   
+        {
+            r_dcache_fsm = DCACHE_CC_CHECK;
+            r_dcache_fsm_save = r_dcache_fsm;
+            m_cost_data_waste_wait_frz++;
+            break;
+        }
+
+	if (!r_dcache_tlb_ll_acc_req)
+	{
+            if ( r_vci_rsp_data_error ) // VCI response ko
+            {
+                if ((r_dcache_type_save == iss_t::DATA_READ)||(r_dcache_type_save == iss_t::DATA_LL))
+                {
+                    r_dcache_error_type = MMU_READ_PT1_ILLEGAL_ACCESS;
+                }
+                else /*if ((dreq.type == iss_t::DATA_WRITE)||(dreq.type == iss_t::DATA_SC))*/
+                {
+                    r_dcache_error_type = MMU_WRITE_PT1_ILLEGAL_ACCESS;
+                } 
+                r_dcache_bad_vaddr = dreq.addr;
+                r_dcache_fsm = DCACHE_ERROR;
+
+		if (r_dcache_inval_tlb_rsp) r_dcache_inval_tlb_rsp = false;
+		if (r_dcache_inval_rsp) r_dcache_inval_rsp = false;		 
+            }
+	    else
+	    {
+		if ( !(r_dcache_miss_buf[0] >> PTE_V_SHIFT) )	// unmapped
+	        {
+               	    if ((r_dcache_type_save == iss_t::DATA_READ)||(r_dcache_type_save == iss_t::DATA_LL))
+               	    {
+               	        r_dcache_error_type = MMU_READ_PT1_UNMAPPED;
+               	    }
+               	    else /*if ((dreq.type == iss_t::DATA_WRITE)||(dreq.type == iss_t::DATA_SC))*/
+               	    {
+               	        r_dcache_error_type = MMU_WRITE_PT1_UNMAPPED;
+               	    }  
+                    r_dcache_bad_vaddr  = dreq.addr;
+                    r_dcache_fsm        = DCACHE_ERROR;
+
+		    if (r_dcache_inval_tlb_rsp) r_dcache_inval_tlb_rsp = false;
+		    if (r_dcache_inval_rsp) r_dcache_inval_rsp = false;	
+	        }
+       		else if ( r_dcache_inval_tlb_rsp )
+       		{
+       		    r_dcache_inval_tlb_rsp = false;
+       		    r_dcache_fsm = DCACHE_IDLE;
+       		    m_cost_data_tlb_miss_frz++;
+       		}
+		else if ( r_dcache_inval_rsp )
+       		{
+       		    r_dcache_inval_rsp = false;
+       		    r_dcache_fsm = DCACHE_IDLE;
+       		}
+		else
+		{
+		    r_dcache_tlb_sc_acc_req = true;
+		    r_dcache_pte_update = r_dcache_miss_buf[0] | r_dcache_pte_update.read();
+                    r_dcache_fsm = DCACHE_TLB1_SC_WAIT; 
+		}
+	    }
+	}
+	break;
+    }
+    ///////////////////////
+    case DCACHE_TLB1_SC_WAIT:
+    {
+        // external cache invalidate request
+        if ( r_tgt_dcache_req )   
+        {
+            r_dcache_fsm = DCACHE_CC_CHECK;
+            r_dcache_fsm_save = r_dcache_fsm;
+            m_cost_data_waste_wait_frz++;
+            break;
+        }
+
+	if ( !r_dcache_tlb_sc_acc_req )
+	{
+	    if ( r_vci_rsp_data_error ) // VCI response ko
+	    {
+                if ((r_dcache_type_save == iss_t::DATA_READ)||(r_dcache_type_save == iss_t::DATA_LL))
+                {
+                    r_dcache_error_type = MMU_READ_PT1_ILLEGAL_ACCESS;
+                }
+                else /*if ((dreq.type == iss_t::DATA_WRITE)||(dreq.type == iss_t::DATA_SC))*/
+                {
+                    r_dcache_error_type = MMU_WRITE_PT1_ILLEGAL_ACCESS;
+                } 
+	        r_dcache_bad_vaddr = dreq.addr;
+	        r_dcache_fsm = DCACHE_ERROR; 
+
+		if (r_dcache_inval_tlb_rsp) r_dcache_inval_tlb_rsp = false;
+		if (r_dcache_inval_rsp) r_dcache_inval_rsp = false;	
+	    }
+	    else
+	    {
+        	// Using tlb entry is invalidated 
+        	if ( r_dcache_inval_tlb_rsp )
+        	{
+        	    r_dcache_inval_tlb_rsp = false;
+        	    r_dcache_fsm = DCACHE_IDLE;
+        	    m_cost_data_tlb_miss_frz++;
+        	}
+		else if ( r_dcache_inval_rsp )
+        	{
+        	    r_dcache_inval_rsp = false;
+        	    r_dcache_fsm = DCACHE_IDLE;
+        	}
+	    	else if ( r_dcache_tlb_ll_acc_req )
+	    	{
+	    	    r_dcache_fsm = DCACHE_TLB1_LL_WAIT; 
+	    	}
+	    	else 
+	    	{
+	    	    r_dcache_fsm = DCACHE_TLB1_UPDT; 
+	    	}
+	    }
+	}
+	break;
+    }
+    //////////////////////
+    case DCACHE_TLB1_READ:
+    {
+        m_cost_data_tlb_miss_frz++;
+
+        // external cache invalidate request
+        if ( r_tgt_dcache_req )   
+        {
+            r_dcache_fsm = DCACHE_CC_CHECK;
+            r_dcache_fsm_save = r_dcache_fsm;
+            m_cost_data_waste_wait_frz++;
+            break;
+        }        
+
+	if ( !r_dcache_tlb_read_req )
+	{	
+            if ( r_vci_rsp_data_error ) // VCI response ko
+            {
+                if ((r_dcache_type_save == iss_t::DATA_READ)||(r_dcache_type_save == iss_t::DATA_LL))
+                {
+                    r_dcache_error_type = MMU_READ_PT1_ILLEGAL_ACCESS;
+                }
+                else /*if ((dreq.type == iss_t::DATA_WRITE)||(dreq.type == iss_t::DATA_SC))*/
+                {
+                    r_dcache_error_type = MMU_WRITE_PT1_ILLEGAL_ACCESS;
+                } 
+                r_dcache_bad_vaddr = dreq.addr;
+                r_dcache_fsm = DCACHE_ERROR; 
+
+		if (r_dcache_inval_tlb_rsp) r_dcache_inval_tlb_rsp = false;
+		if (r_dcache_inval_rsp) r_dcache_inval_rsp = false;	
+		break;
+            }
+
+            if ( r_dcache_inval_tlb_rsp )  // TLB miss response and invalidation
+            {
+                r_dcache_fsm = DCACHE_IDLE; 
+            	r_dcache_inval_tlb_rsp = false;
+		break;
+            }
+
+	    if ( r_dcache_inval_rsp ) // TLB miss response and cache invalidation
+	    {
+                r_dcache_fsm = DCACHE_IDLE; 
+            	r_dcache_inval_rsp = false;
+		break;	    
+	    }
+	    // TLB miss response and no invalidation
+	    r_dcache_fsm = DCACHE_TLB1_READ_UPDT;
+	}
+        break;
+    }
+    //////////////////////////
+    case DCACHE_TLB1_READ_UPDT:
+    {
+        m_cost_data_tlb_miss_frz++;
+
+        // external cache invalidate request
+        if ( r_tgt_dcache_req )   
+        {
+            r_dcache_fsm = DCACHE_CC_CHECK;
+            r_dcache_fsm_save = r_dcache_fsm;
+            m_cost_data_waste_wait_frz++;
+            break;
+        }        
+
+        // Using tlb entry is invalidated 
+        if ( r_dcache_inval_tlb_rsp )
+        {
+            r_dcache_inval_tlb_rsp = false;
+            r_dcache_fsm = DCACHE_IDLE;
+            m_cost_data_tlb_miss_frz++;
+            break;
+        }
+
+        // Using tlb entry is in the invalidated cache line  
+        if ( r_dcache_inval_rsp )
+        {
+            r_dcache_inval_rsp = false;
+            r_dcache_fsm = DCACHE_IDLE;
+            m_cost_data_tlb_miss_frz++;
+            break;
+        }
+
+        if ( !r_dcache_cleanup_req ) // Miss update and no invalidation
+        {
+            // update dcache
+            data_t   rsp_dtlb_miss = 0;
+            paddr_t  victim_index = 0;
+	    bool write_hit = false;
+            size_t way = 0;
+            size_t set = 0;
+
+            bool cleanup_req = r_dcache.find(r_dcache_tlb_paddr, r_dcache_in_itlb, r_dcache_in_dtlb, &way, &set, &victim_index);
+            
+	    if ( cleanup_req )
+	    {	    
+		// ins tlb invalidate verification    
+                r_dcache_itlb_inval_req = r_dcache_in_itlb[m_dcache_sets*way+set];
+                r_dcache_itlb_inval_line = victim_index;
+                r_dcache_in_itlb[way*m_dcache_sets+set] = false;
+
+                // data tlb invalidate verification
+                r_dcache_dtlb_inval_req = r_dcache_in_dtlb[m_dcache_sets*way+set]; 
+                r_dcache_dtlb_inval_line = victim_index;
+                r_dcache_in_dtlb[way*m_dcache_sets+set] = false;
+
+                r_dcache_cleanup_req = true; 
+                r_dcache_cleanup_line = victim_index;
+		r_dcache_fsm = DCACHE_TLB_CC_INVAL;
+                r_dcache_fsm_save = r_dcache_fsm;
+		break;
+	    }
+
+	    r_dcache.update(r_dcache_tlb_paddr, way, set, r_dcache_miss_buf);
+            r_dcache.read(r_dcache_tlb_paddr, &rsp_dtlb_miss);	
+
+	    if ( !(rsp_dtlb_miss >> PTE_V_SHIFT) )	// unmapped
+	    {
+                r_dcache_ptba_ok    = false;
+                if ((r_dcache_type_save == iss_t::DATA_READ)||(r_dcache_type_save == iss_t::DATA_LL))
+                {
+                    r_dcache_error_type = MMU_READ_PT1_UNMAPPED;
+                }
+                else /*if ((dreq.type == iss_t::DATA_WRITE)||(dreq.type == iss_t::DATA_SC))*/
+                {
+                    r_dcache_error_type = MMU_WRITE_PT1_UNMAPPED;
+                } 
+                r_dcache_bad_vaddr  = dreq.addr;
+                r_dcache_fsm        = DCACHE_ERROR;
+	    }
+	    else if ( (rsp_dtlb_miss & PTE_T_MASK) >> PTE_T_SHIFT ) // PTD
+	    {
+                r_dcache_ptba_ok   = true;
+                r_dcache_ptba_save = (paddr_t)(rsp_dtlb_miss & ((1<<(m_paddr_nbits - PAGE_K_NBITS))-1)) << PAGE_K_NBITS;  
+                r_dcache_id1_save  = dreq.addr >> PAGE_M_NBITS;
+                r_dcache_tlb_paddr = (paddr_t)(rsp_dtlb_miss & ((1<<(m_paddr_nbits - PAGE_K_NBITS))-1)) << PAGE_K_NBITS | 
+                                     (paddr_t)(((dreq.addr & PTD_ID2_MASK) >> PAGE_K_NBITS) << 3);
+                if ( r_dcache_tlb_ptba_read )
+                {
+                    r_dcache_tlb_ptba_read = false;
+                    write_hit = r_dcache.write(((paddr_t)(rsp_dtlb_miss & ((1<<(m_paddr_nbits - PAGE_K_NBITS))-1)) << PAGE_K_NBITS | 
+                                                (paddr_t)(((dreq.addr & PTD_ID2_MASK) >> PAGE_K_NBITS) << 3)),r_dcache_pte_update);
+                    assert(write_hit && "Write on miss ignores data");
+                    r_dcache_tlb_ll_dirty_req = true;
+                    r_dcache_fsm = DCACHE_LL_DIRTY_WAIT;
+                    m_cpt_data_tlb_write_dirty++;
+                }
+                else
+                {
+                    r_dcache_fsm = DCACHE_DTLB2_READ_CACHE;
+                }
+	    }
+	    else	// PTE
+	    {
+                r_dcache_ptba_ok = false;
+	        if ( (m_srcid >> 4) == ((r_dcache_tlb_paddr.read() & ((1<<(m_paddr_nbits - PAGE_M_NBITS))-1)) >> (m_paddr_nbits - PAGE_M_NBITS -10)) ) // local
+		{
+		    if ( (rsp_dtlb_miss & PTE_L_MASK ) >> PTE_L_SHIFT ) // L bit is set
+		    {
+                        r_dcache_pte_update = rsp_dtlb_miss;
+                        r_dcache_fsm        = DCACHE_TLB1_UPDT;
+		    }
+		    else
+		    {
+                        r_dcache_pte_update = rsp_dtlb_miss | PTE_L_MASK;
+                        r_dcache_tlb_ll_acc_req = true;
+                	write_hit = r_dcache.write(r_dcache_tlb_paddr,(rsp_dtlb_miss | PTE_L_MASK));  
+                	assert(write_hit && "Write on miss ignores data");  
+                        r_dcache_fsm        = DCACHE_TLB1_LL_WAIT;
+                        m_cpt_ins_tlb_write_et++;
+		    }
+    	        }
+		else // remotely
+		{
+		    if ( (rsp_dtlb_miss & PTE_R_MASK ) >> PTE_R_SHIFT ) // R bit is set
+		    {
+                        r_dcache_pte_update = rsp_dtlb_miss;
+                        r_dcache_fsm        = DCACHE_TLB1_UPDT;
+		    }
+		    else
+		    {
+                        r_dcache_pte_update = rsp_dtlb_miss | PTE_R_MASK;
+                        r_dcache_tlb_ll_acc_req = true;
+                	write_hit = r_dcache.write(r_dcache_tlb_paddr,(rsp_dtlb_miss | PTE_R_MASK));  
+                	assert(write_hit && "Write on miss ignores data");  
+                        r_dcache_fsm        = DCACHE_TLB1_LL_WAIT;
+                        m_cpt_ins_tlb_write_et++;
+		    }
+		}
+	    }
+        }
+        break;
+    }
+    //////////////////////
+    case DCACHE_TLB1_UPDT: 
+    {
+        m_cost_data_tlb_miss_frz++;
+
+        // external cache invalidate request
+        if ( r_tgt_dcache_req )   
+        {
+            r_dcache_fsm = DCACHE_CC_CHECK;
+            r_dcache_fsm_save = r_dcache_fsm;
+            m_cost_data_waste_wait_frz++;
+            break;
+        }        
+
+        if ( !r_dcache_inval_tlb_rsp && !r_dcache_inval_rsp )
+        {
+            paddr_t victim_index = 0;
+            if (dcache_tlb.update(r_dcache_pte_update,dreq.addr,(r_dcache_tlb_paddr.read() >> (uint32_log2(m_dcache_words)+2)),&victim_index))
+            {
+                r_dcache.setinbit((paddr_t)victim_index*m_dcache_words*2, r_dcache_in_dtlb, false);
+            }
+            r_dcache.setinbit(r_dcache_tlb_paddr, r_dcache_in_dtlb, true);
+            r_dcache_fsm = DCACHE_IDLE;
+        }
+        else  
+        {
+            if ( r_dcache_inval_tlb_rsp ) r_dcache_inval_tlb_rsp = false;
+            if ( r_dcache_inval_rsp ) r_dcache_inval_rsp = false;
+            r_dcache_fsm = DCACHE_IDLE;
+        }
+        break;
+    }
+    /////////////////////////////
+    case DCACHE_DTLB2_READ_CACHE:
+    {
+        m_cost_data_tlb_miss_frz++;
+
+        // external cache invalidate request
+        if ( r_tgt_dcache_req )   
+        {
+            r_dcache_fsm = DCACHE_CC_CHECK;
+            r_dcache_fsm_save = r_dcache_fsm;
+            m_cost_data_waste_wait_frz++;
+            break;
+        }        
+
+        // Using tlb entry is invalidated 
+        if ( r_dcache_inval_tlb_rsp )
+        {
+            r_dcache_inval_tlb_rsp = false;
+            r_dcache_fsm = DCACHE_IDLE;
+            m_cost_data_tlb_miss_frz++;
+            break;
+        }
+
+        data_t tlb_data = 0;
+        data_t tlb_data_ppn = 0;
+	bool write_hit = false;
+        bool tlb_hit_cache = r_dcache.read(r_dcache_tlb_paddr, &tlb_data);
+
+	if ( tlb_hit_cache )
+	{
+            bool tlb_hit_ppn = r_dcache.read(r_dcache_tlb_paddr.read()+4, &tlb_data_ppn);
+	    assert(tlb_hit_ppn && "Address of pte[64-32] and pte[31-0] should be successive");
+	}
+
+        // DTLB request hit in cache
+        if ( tlb_hit_cache )
+        {
+	    if ( !(tlb_data >> PTE_V_SHIFT) )	// unmapped
+	    {
+                if ((r_dcache_type_save == iss_t::DATA_READ)||(r_dcache_type_save == iss_t::DATA_LL))
+                {
+                    r_dcache_error_type = MMU_READ_PT2_UNMAPPED;
+                }
+                else /*if ((dreq.type == iss_t::DATA_WRITE)||(dreq.type == iss_t::DATA_SC))*/
+                {
+                    r_dcache_error_type = MMU_WRITE_PT2_UNMAPPED;
+                } 
+                r_dcache_bad_vaddr  = dreq.addr;
+                r_dcache_fsm        = DCACHE_ERROR;
+	    }
+	    else if ( (tlb_data & PTE_T_MASK) >> PTE_T_SHIFT ) //PTD
+	    {
+                r_dcache_pte_update = tlb_data;
+	        r_dcache_ppn_update = tlb_data_ppn;
+		r_dcache_fsm = DCACHE_TLB2_UPDT;
+	    }
+	    else 
+	    {
+	        if ( (m_srcid >> 4) == ((r_dcache_tlb_paddr.read() & ((1<<(m_paddr_nbits - PAGE_M_NBITS))-1)) >> (m_paddr_nbits - PAGE_M_NBITS -10)) ) // local
+		{
+		    if ( (tlb_data & PTE_L_MASK ) >> PTE_L_SHIFT ) // L bit is set
+		    {
+                        r_dcache_pte_update = tlb_data;
+			r_dcache_ppn_update = tlb_data_ppn;
+                        r_dcache_fsm        = DCACHE_TLB2_UPDT;
+		    }
+		    else
+		    {
+                        r_dcache_pte_update = tlb_data | PTE_L_MASK;
+	        	r_dcache_ppn_update = tlb_data_ppn;
+                        r_dcache_tlb_ll_acc_req = true;
+                	write_hit = r_dcache.write(r_dcache_tlb_paddr,(tlb_data | PTE_L_MASK));  
+                	assert(write_hit && "Write on miss ignores data");  
+                        r_dcache_fsm = DCACHE_TLB2_LL_WAIT;
+                        m_cpt_ins_tlb_write_et++;
+		    }
+    	        }
+		else // remotely
+		{
+		    if ( (tlb_data & PTE_R_MASK ) >> PTE_R_SHIFT ) // R bit is set
+		    {
+                        r_dcache_pte_update = tlb_data;
+			r_dcache_ppn_update = tlb_data_ppn;
+                        r_dcache_fsm        = DCACHE_TLB2_UPDT;
+		    }
+		    else
+		    {
+                        r_dcache_pte_update = tlb_data | PTE_R_MASK;
+	        	r_dcache_ppn_update = tlb_data_ppn;
+                        r_dcache_tlb_ll_acc_req = true;
+                	write_hit = r_dcache.write(r_dcache_tlb_paddr,(tlb_data | PTE_R_MASK));  
+                	assert(write_hit && "Write on miss ignores data");  
+                        r_dcache_fsm = DCACHE_TLB2_LL_WAIT;
+                        m_cpt_ins_tlb_write_et++;
+		    }
+		}
+	    }
+        }
+        else
+        {
+            // DTLB request miss in cache and walk page table level 2
+            r_dcache_tlb_read_req = true;
+            r_dcache_fsm = DCACHE_TLB2_READ;
+        }
+        break;
+    }
+    ///////////////////////
+    case DCACHE_TLB2_LL_WAIT:
+    {
+        // external cache invalidate request
+        if ( r_tgt_dcache_req )   
+        {
+            r_dcache_fsm = DCACHE_CC_CHECK;
+            r_dcache_fsm_save = r_dcache_fsm;
+            m_cost_data_waste_wait_frz++;
+            break;
+        }
+
+	if (!r_dcache_tlb_ll_acc_req)
+	{
+            if ( r_vci_rsp_data_error ) // VCI response ko
+            {
+                if ((r_dcache_type_save == iss_t::DATA_READ)||(r_dcache_type_save == iss_t::DATA_LL))
+                {
+                    r_dcache_error_type = MMU_READ_PT2_ILLEGAL_ACCESS;
+                }
+                else /*if ((dreq.type == iss_t::DATA_WRITE)||(dreq.type == iss_t::DATA_SC))*/
+                {
+                    r_dcache_error_type = MMU_WRITE_PT2_ILLEGAL_ACCESS;
+                } 
+                r_dcache_bad_vaddr = dreq.addr;
+                r_dcache_fsm = DCACHE_ERROR; 
+
+		if (r_dcache_inval_tlb_rsp) r_dcache_inval_tlb_rsp = false;
+		if (r_dcache_inval_rsp) r_dcache_inval_rsp = false;
+            }
+	    else
+	    {
+	        if ( !(r_dcache_miss_buf[0] >> PTE_V_SHIFT) )	// unmapped
+	        {
+               	    if ((r_dcache_type_save == iss_t::DATA_READ)||(r_dcache_type_save == iss_t::DATA_LL))
+               	    {
+               	        r_dcache_error_type = MMU_READ_PT2_UNMAPPED;
+               	    }
+               	    else /*if ((dreq.type == iss_t::DATA_WRITE)||(dreq.type == iss_t::DATA_SC))*/
+               	    {
+               	        r_dcache_error_type = MMU_WRITE_PT2_UNMAPPED;
+               	    } 
+                    r_dcache_bad_vaddr = dreq.addr;
+                    r_dcache_fsm = DCACHE_ERROR;
+
+		    if (r_dcache_inval_tlb_rsp) r_dcache_inval_tlb_rsp = false;
+		    if (r_dcache_inval_rsp) r_dcache_inval_rsp = false;
+	        }
+        	else if ( r_dcache_inval_tlb_rsp )
+        	{
+        	    r_dcache_inval_tlb_rsp = false;
+        	    r_dcache_fsm = DCACHE_IDLE;
+        	    m_cost_data_tlb_miss_frz++;
+        	}
+		else if ( r_dcache_inval_rsp )
+		{
+        	    r_dcache_inval_rsp = false;
+		    r_dcache_fsm = DCACHE_IDLE;
+		}
+		else
+		{
+		    r_dcache_tlb_sc_acc_req = true;
+		    r_dcache_pte_update = r_dcache_miss_buf[0] | r_dcache_pte_update.read();
+                    r_dcache_fsm = DCACHE_TLB2_SC_WAIT; 
+		}
+	    }
+	}
+	break;
+    }
+    ///////////////////////
+    case DCACHE_TLB2_SC_WAIT:
+    {
+        // external cache invalidate request
+        if ( r_tgt_dcache_req )   
+        {
+            r_dcache_fsm = DCACHE_CC_CHECK;
+            r_dcache_fsm_save = r_dcache_fsm;
+            m_cost_data_waste_wait_frz++;
+            break;
+        }
+
+	if ( !r_dcache_tlb_sc_acc_req )
+	{
+	    if ( r_vci_rsp_data_error ) // VCI response ko
+	    {
+                if ((r_dcache_type_save == iss_t::DATA_READ)||(r_dcache_type_save == iss_t::DATA_LL))
+                {
+                    r_dcache_error_type = MMU_READ_PT2_ILLEGAL_ACCESS;
+                }
+                else /*if ((dreq.type == iss_t::DATA_WRITE)||(dreq.type == iss_t::DATA_SC))*/
+                {
+                    r_dcache_error_type = MMU_WRITE_PT2_ILLEGAL_ACCESS;
+                } 
+	        r_dcache_bad_vaddr = dreq.addr;
+	        r_dcache_fsm = DCACHE_ERROR; 
+
+		if (r_dcache_inval_tlb_rsp) r_dcache_inval_tlb_rsp = false;
+		if (r_dcache_inval_rsp) r_dcache_inval_rsp = false;	
+	    }
+	    else
+	    { 
+                // Using tlb entry is invalidated 
+                if ( r_dcache_inval_tlb_rsp )
+                {
+                    r_dcache_inval_tlb_rsp = false;
+                    r_dcache_fsm = DCACHE_IDLE;
+                    m_cost_data_tlb_miss_frz++;
+                }
+		else if ( r_dcache_inval_rsp )
+		{
+        	    r_dcache_inval_rsp = false;
+		    r_dcache_fsm = DCACHE_IDLE;
+		}
+	        else if ( r_dcache_tlb_ll_acc_req )
+	        {
+	            r_dcache_fsm = DCACHE_TLB2_LL_WAIT; 
+	        }
+	        else 
+	        {
+	            r_dcache_fsm = DCACHE_TLB2_UPDT; 
+	        }
+	    }
+	}
+	break;
+    }
+    /////////////////////
+    case DCACHE_TLB2_READ:
+    {
+        m_cost_data_tlb_miss_frz++;
+
+        // external cache invalidate request
+        if ( r_tgt_dcache_req )   
+        {
+            r_dcache_fsm = DCACHE_CC_CHECK;
+            r_dcache_fsm_save = r_dcache_fsm;
+            m_cost_data_waste_wait_frz++;
+            break;
+        }        
+
+	if ( !r_dcache_tlb_read_req )
+	{
+            if ( r_vci_rsp_data_error ) // VCI response ko
+            {
+                if ((r_dcache_type_save == iss_t::DATA_READ)||(r_dcache_type_save == iss_t::DATA_LL))
+                {
+                    r_dcache_error_type = MMU_READ_PT2_ILLEGAL_ACCESS;
+                }
+                else /*if ((dreq.type == iss_t::DATA_WRITE)||(dreq.type == iss_t::DATA_SC))*/
+                {
+                    r_dcache_error_type = MMU_WRITE_PT2_ILLEGAL_ACCESS;
+                } 
+                r_dcache_bad_vaddr = dreq.addr;
+                r_dcache_fsm = DCACHE_ERROR; 
+
+		if (r_dcache_inval_tlb_rsp) r_dcache_inval_tlb_rsp = false;
+		if (r_dcache_inval_rsp) r_dcache_inval_rsp = false;
+		break;
+            }	
+
+            if ( r_dcache_inval_tlb_rsp )  // TLB miss response and invalidation
+            {
+                r_dcache_fsm = DCACHE_IDLE; 
+                r_dcache_inval_tlb_rsp = false;
+		break;
+            }   
+
+	    if ( r_dcache_inval_rsp ) // TLB miss response and cache invalidation
+	    {
+                r_dcache_fsm = DCACHE_IDLE; 
+            	r_dcache_inval_rsp = false;
+		break;	    
+	    }
+	    // TLB miss response and no invalidation
+	    r_dcache_fsm = DCACHE_TLB2_READ_UPDT; 
+	}	
+        break;
+    }
+    //////////////////////////
+    case DCACHE_TLB2_READ_UPDT:
+    {
+        m_cost_data_tlb_miss_frz++;
+
+        // external cache invalidate request
+        if ( r_tgt_dcache_req )   
+        {
+            r_dcache_fsm = DCACHE_CC_CHECK;
+            r_dcache_fsm_save = r_dcache_fsm;
+            m_cost_data_waste_wait_frz++;
+            break;
+        }        
+
+        // Using tlb entry is invalidated 
+        if ( r_dcache_inval_tlb_rsp )
+        {
+            r_dcache_inval_tlb_rsp = false;
+            r_dcache_fsm = DCACHE_IDLE;
+            m_cost_data_tlb_miss_frz++;
+            break;
+        }
+
+        // Using tlb entry is in the invalidated cache line  
+        if ( r_dcache_inval_rsp )
+        {
+            r_dcache_inval_rsp = false;
+            r_dcache_fsm = DCACHE_IDLE;
+            m_cost_data_tlb_miss_frz++;
+            break;
+        }
+
+        if ( !r_dcache_cleanup_req )
+        {
+            // update cache
+            data_t rsp_dtlb_miss;
+            data_t tlb_data_ppn;
+	    bool write_hit = false;
+            paddr_t  victim_index = 0;
+            size_t way = 0;
+            size_t set = 0;
+
+            bool cleanup_req = r_dcache.find(r_dcache_tlb_paddr, r_dcache_in_itlb, r_dcache_in_dtlb, &way, &set, &victim_index);
+
+	    if ( cleanup_req )
+	    {	    
+		// ins tlb invalidate verification    
+                r_dcache_itlb_inval_req = r_dcache_in_itlb[m_dcache_sets*way+set];
+                r_dcache_itlb_inval_line = victim_index;
+                r_dcache_in_itlb[way*m_dcache_sets+set] = false;
+
+                // data tlb invalidate verification
+                r_dcache_dtlb_inval_req = r_dcache_in_dtlb[m_dcache_sets*way+set]; 
+                r_dcache_dtlb_inval_line = victim_index;
+                r_dcache_in_dtlb[way*m_dcache_sets+set] = false;
+
+                r_dcache_cleanup_req = true; 
+                r_dcache_cleanup_line = victim_index;
+		r_dcache_fsm = DCACHE_TLB_CC_INVAL;
+                r_dcache_fsm_save = r_dcache_fsm;
+		break;
+	    }
+
+	    r_dcache.update(r_dcache_tlb_paddr, way, set, r_dcache_miss_buf);
+	    r_dcache.read(r_dcache_tlb_paddr, &rsp_dtlb_miss);
+
+	    bool tlb_hit_ppn = r_dcache.read(r_dcache_tlb_paddr.read()+4, &tlb_data_ppn);
+	    assert(tlb_hit_ppn && "Address of pte[64-32] and pte[31-0] should be successive");
+
+	    if ( !(rsp_dtlb_miss >> PTE_V_SHIFT) )	// unmapped
+	    {
+                if ((r_dcache_type_save == iss_t::DATA_READ)||(r_dcache_type_save == iss_t::DATA_LL))
+                {
+                    r_dcache_error_type = MMU_READ_PT2_UNMAPPED;
+                }
+                else /*if ((dreq.type == iss_t::DATA_WRITE)||(dreq.type == iss_t::DATA_SC))*/
+                {
+                    r_dcache_error_type = MMU_WRITE_PT2_UNMAPPED;
+                }  
+                r_dcache_bad_vaddr  = dreq.addr;
+                r_dcache_fsm        = DCACHE_ERROR;
+	    }
+	    else if ( (rsp_dtlb_miss & PTE_T_MASK) >> PTE_T_SHIFT ) // PTD
+	    {
+                r_dcache_pte_update = rsp_dtlb_miss;
+	        r_dcache_ppn_update = tlb_data_ppn;
+		r_dcache_fsm = DCACHE_TLB2_UPDT;
+	    }
+	    else
+	    {
+	        if ( (m_srcid >> 4) == ((r_dcache_tlb_paddr.read() & ((1<<(m_paddr_nbits - PAGE_M_NBITS))-1)) >> (m_paddr_nbits - PAGE_M_NBITS -10)) ) // local
+		{
+		    if ( (rsp_dtlb_miss & PTE_L_MASK ) >> PTE_L_SHIFT ) // L bit is set
+		    {
+                        r_dcache_pte_update = rsp_dtlb_miss;
+			r_dcache_ppn_update = tlb_data_ppn;
+                        r_dcache_fsm        = DCACHE_TLB2_UPDT;
+		    }
+		    else
+		    {
+                        r_dcache_pte_update = rsp_dtlb_miss | PTE_L_MASK;
+	        	r_dcache_ppn_update = tlb_data_ppn;
+                        r_dcache_tlb_ll_acc_req = true;
+                	write_hit = r_dcache.write(r_dcache_tlb_paddr,(rsp_dtlb_miss | PTE_L_MASK));  
+                	assert(write_hit && "Write on miss ignores data");  
+                        r_dcache_fsm = DCACHE_TLB2_LL_WAIT;
+                        m_cpt_ins_tlb_write_et++;
+		    }
+    	        }
+		else // remotely
+		{
+		    if ( (rsp_dtlb_miss & PTE_R_MASK ) >> PTE_R_SHIFT ) // R bit is set
+		    {
+                        r_dcache_pte_update = rsp_dtlb_miss;
+			r_dcache_ppn_update = tlb_data_ppn;
+                        r_dcache_fsm        = DCACHE_TLB2_UPDT;
+		    }
+		    else
+		    {
+                        r_dcache_pte_update = rsp_dtlb_miss | PTE_R_MASK;
+	        	r_dcache_ppn_update = tlb_data_ppn;
+                        r_dcache_tlb_ll_acc_req = true;
+                	write_hit = r_dcache.write(r_dcache_tlb_paddr,(rsp_dtlb_miss | PTE_R_MASK));  
+                	assert(write_hit && "Write on miss ignores data");  
+                        r_dcache_fsm = DCACHE_TLB2_LL_WAIT;
+                        m_cpt_ins_tlb_write_et++;
+		    }
+		}
+	    }
+        }
+        break;
+    }
+    //////////////////////
+    case DCACHE_TLB2_UPDT:  
+    {
+        m_cost_data_tlb_miss_frz++;
+
+        // external cache invalidate request
+        if ( r_tgt_dcache_req )   
+        {
+            r_dcache_fsm = DCACHE_CC_CHECK;
+            r_dcache_fsm_save = r_dcache_fsm;
+            m_cost_data_waste_wait_frz++;
+            break;
+        }        
+
+        if ( !r_dcache_inval_tlb_rsp && !r_dcache_inval_rsp )
+        {
+            paddr_t victim_index = 0;
+            if (dcache_tlb.update(r_dcache_pte_update,r_dcache_ppn_update,dreq.addr,(r_dcache_tlb_paddr.read() >> (uint32_log2(m_dcache_words)+2)),&victim_index))
+            {
+                r_dcache.setinbit((paddr_t)victim_index*m_dcache_words*2, r_dcache_in_dtlb, false);
+            }
+            r_dcache.setinbit(r_dcache_tlb_paddr, r_dcache_in_dtlb, true);
+            r_dcache_fsm = DCACHE_IDLE;
+        }
+        else  
+        {
+            if ( r_dcache_inval_tlb_rsp ) r_dcache_inval_tlb_rsp = false;
+            if ( r_dcache_inval_rsp ) r_dcache_inval_rsp = false;
+            r_dcache_fsm = DCACHE_IDLE;
+        }
+        break;
+    }
+    ///////////////////////
+    case DCACHE_CTXT_SWITCH:
+    {
+        // TLB flush leads to cleanup corresponding data cache line 
+        m_cost_data_tlb_sw_frz++;
+
+        paddr_t victim_index = 0;
+        size_t way = 0;
+        size_t set = 0;
+
+        if ( r_dcache_itlb_cleanup_req )
+        {    
+            r_dcache.setinbit(((paddr_t)r_dcache_itlb_cleanup_line.read()*m_dcache_words*2), r_dcache_in_itlb, false);
+            r_dcache_itlb_cleanup_req = false;
+	}
+
+        for ( way = 0; way < m_dtlb_ways; way++)
+        {
+            for ( set = 0; set < m_dtlb_sets; set++)
+            {
+                if(dcache_tlb.checkcleanup(way, set, &victim_index))
+                {
+                    r_dcache.setinbit((paddr_t)(victim_index << (m_dcache_words+2)), r_dcache_in_dtlb, false); 
+                }
+            }
+        }
+
+        if ((way == m_dtlb_ways) && (set == m_dtlb_sets) && (!r_dcache_xtn_req))
+        {
+            r_dcache_fsm = DCACHE_IDLE;
+            r_dtlb_translation_valid = false;
+            r_dcache_ptba_ok = false;
+            drsp.valid = true;
+        }
+        break;
+    }
+    ////////////////////////
+    case DCACHE_ICACHE_FLUSH:
+    case DCACHE_ICACHE_INVAL:
+    case DCACHE_ITLB_INVAL:
+    {
+        if ( !r_dcache_xtn_req ) 
+        {
+            r_dcache_fsm = DCACHE_IDLE;
+            drsp.valid = true;
+        }
+        break;
+    }
+    ////////////////////////
+    case DCACHE_DCACHE_FLUSH:
+    {
+        // external cache invalidate request
+        if ( r_tgt_dcache_req )
+        {
+            r_tgt_dcache_req = false;
+        }   
+
+        size_t way = r_dcache_way;
+        size_t set = r_dcache_set;
+        bool clean = false;
+        
+        m_cost_data_cache_flush_frz++;
+
+        // cache flush and send cleanup to external
+        if ( !r_dcache_cleanup_req )
+        {
+            paddr_t victim_index = 0;
+            for ( ; way < m_dcache_ways; way++ )
+            {    
+                for ( ; set < m_dcache_sets; set++ )
+                {  
+                    if ( r_dcache.flush(way, set, &victim_index) )
+                    {
+                        clean = true;
+                        r_dcache_cleanup_req = true;
+                        r_dcache_cleanup_line = victim_index;
+                        r_dcache_way = way + ((set+1)/m_dcache_sets);
+                        r_dcache_set = (set+1) % m_dcache_sets;
+                        break;
+                    }
+                }
+                if (clean) break;
+            }
+
+            if ((way == m_dcache_ways) && (set == m_dcache_sets) && !r_dcache_xtn_req ) 
+            {
+                // data TLB flush 
+                dcache_tlb.flush(true);      // global entries are not invalidated
+
+                for (size_t line = 0; line < m_dcache_ways*m_dcache_sets; line++)
+                {
+                    r_dcache_in_itlb[line] = false;
+                    r_dcache_in_dtlb[line] = false;
+                }
+
+                r_dcache_fsm = DCACHE_IDLE;
+                drsp.valid = true;
+                break;
+            }
+        }
+	break;
+    }
+    //////////////////////
+    case DCACHE_DTLB_INVAL: 
+    {
+        paddr_t victim_index = 0;
+        // clean indicate data tlb bit
+        if ( dcache_tlb.inval(r_dcache_wdata_save, &victim_index) )
+        {  
+            r_dcache.setinbit((paddr_t)(victim_index << (m_dcache_words+2)), r_dcache_in_dtlb, false); 
+        }
+        r_dtlb_translation_valid = false;
+        r_dcache_ptba_ok = false;
+        r_dcache_fsm = DCACHE_IDLE;
+        drsp.valid = true;
+        break;
+    }
+    ////////////////////////
+    case DCACHE_DCACHE_INVAL:
+    {
+        m_cpt_dcache_dir_read += m_dcache_ways;
+        vaddr_t invadr = dreq.wdata;
+        paddr_t dpaddr = 0;
+        bool dcache_hit_t = false; 
+        size_t way = 0;
+        size_t set = 0;
+
+	if ( !r_dcache_cleanup_req )
+	{
+            if ( r_mmu_mode.read() & DATA_TLB_MASK ) 
+            {
+                dcache_hit_t = dcache_tlb.translate(invadr, &dpaddr); 
+            } 
+            else 
+            {
+                dpaddr = invadr;  
+                dcache_hit_t = true;
+            }
+
+            if ( dcache_hit_t )
+            {
+		r_dcache_cleanup_req = r_dcache.inval(dpaddr, &way, &set);
+		r_dcache_cleanup_line = dpaddr >> (uint32_log2(m_dcache_words)+2);
+		
+		if ( r_dcache_in_itlb[way*m_dcache_sets+set] || r_dcache_in_dtlb[way*m_dcache_sets+set] ) 
+		{	
+		    // ins tlb invalidate verification
+		    r_dcache_itlb_inval_req = r_dcache_in_itlb[way*m_dcache_sets+set];
+		    r_dcache_itlb_inval_line = dpaddr >> (uint32_log2(m_dcache_words)+2);
+		    r_dcache_in_itlb[way*m_dcache_sets+set] = false;
+		
+		    // data tlb invalidate verification
+		    r_dcache_dtlb_inval_req = r_dcache_in_dtlb[way*m_dcache_sets+set];
+		    r_dcache_dtlb_inval_line = dpaddr >> (uint32_log2(m_dcache_words)+2);
+		    r_dcache_in_dtlb[way*m_dcache_sets+set] = false;
+		    r_dcache_fsm = DCACHE_TLB_CC_INVAL;
+		    r_dcache_fsm_save = r_dcache_fsm;
+		    break;
+		}
+            }
+            r_dcache_fsm = DCACHE_IDLE;
+            drsp.valid = true;
+	}
+        break;
+    }
+    /////////////////////////
+    case DCACHE_DCACHE_SYNC:
+    {
+        if ( !r_dcache_write_req ) 
+        {
+            r_dcache_write_req = r_wbuf.rok();
+            drsp.valid = true;
+            r_dcache_fsm = DCACHE_IDLE;
+        }    
+        break;
+    }
+    /////////////////////
+    case DCACHE_MISS_WAIT:
+    {
+        m_cost_data_miss_frz++; 
+
+        // external cache invalidate request
+        if ( r_tgt_dcache_req ) 
+        {
+            r_dcache_fsm = DCACHE_CC_CHECK;
+            r_dcache_fsm_save = r_dcache_fsm;
+            m_cost_data_waste_wait_frz++;
+            break;
+        }
+
+	if ( !r_dcache_miss_req )
+	{
+            if ( r_vci_rsp_data_error ) 
+            {
+                r_dcache_error_type = MMU_READ_DATA_ILLEGAL_ACCESS; 
+                r_dcache_bad_vaddr = dreq.addr;
+                r_dcache_fsm = DCACHE_ERROR;
+
+		if (r_dcache_inval_tlb_rsp) r_dcache_inval_tlb_rsp = false;
+		if (r_dcache_inval_rsp) r_dcache_inval_rsp = false;
+		break;
+            } 
+
+            if ( r_dcache_inval_tlb_rsp ) // Miss read response and tlb invalidation
+            {
+                r_dcache_fsm = DCACHE_IDLE;
+                r_dcache_inval_tlb_rsp = false;
+		break;
+            }	
+
+	    if ( r_dcache_inval_rsp ) // TLB miss response and cache invalidation
+	    {
+                r_dcache_fsm = DCACHE_IDLE; 
+            	r_dcache_inval_rsp = false;
+		break;	    
+	    }
+	    // Miss read response and no tlb invalidation
+	    r_dcache_fsm = DCACHE_MISS_UPDT;
+	}	
+        break;
+    }
+    /////////////////////
+    case DCACHE_MISS_UPDT:
+    {
+        m_cost_data_miss_frz++;
+
+        // external cache invalidate request
+        if ( r_tgt_dcache_req ) 
+        {
+            r_dcache_fsm = DCACHE_CC_CHECK;
+            r_dcache_fsm_save = r_dcache_fsm;
+            m_cost_data_waste_wait_frz++;
+            break;
+        }
+
+        if ( r_dcache_inval_tlb_rsp ) // tlb invalidation
+        {
+            r_dcache_inval_tlb_rsp = false;
+            r_dcache_fsm = DCACHE_IDLE;
+            m_cost_data_tlb_miss_frz++;
+            break;
+        }
+
+        // Using tlb entry is in the invalidated cache line  
+        if ( r_dcache_inval_rsp )
+        {
+            r_dcache_inval_rsp = false;
+            r_dcache_fsm = DCACHE_IDLE;
+            m_cost_data_tlb_miss_frz++;
+            break;
+        }
+
+        if (!r_dcache_cleanup_req ) // Miss update and no invalidation
+        {
+            paddr_t  victim_index = 0;
+            size_t way = 0;
+            size_t set = 0;
+
+	    m_cpt_dcache_data_write++;
+            m_cpt_dcache_dir_write++;
+
+            bool cleanup_req = r_dcache.find(r_dcache_paddr_save.read(), r_dcache_in_itlb, r_dcache_in_dtlb, &way, &set, &victim_index);
+
+	    if ( cleanup_req )
+	    {	    
+		// ins tlb invalidate verification    
+                r_dcache_itlb_inval_req = r_dcache_in_itlb[m_dcache_sets*way+set];
+                r_dcache_itlb_inval_line = victim_index;
+                r_dcache_in_itlb[way*m_dcache_sets+set] = false;
+
+                // data tlb invalidate verification
+                r_dcache_dtlb_inval_req = r_dcache_in_dtlb[m_dcache_sets*way+set]; 
+                r_dcache_dtlb_inval_line = victim_index;
+                r_dcache_in_dtlb[way*m_dcache_sets+set] = false;
+
+                r_dcache_cleanup_req = true; 
+                r_dcache_cleanup_line = victim_index;
+		r_dcache_fsm = DCACHE_TLB_CC_INVAL;
+                r_dcache_fsm_save = r_dcache_fsm;
+		break;
+	    }
+
+	    r_dcache.update(r_dcache_paddr_save.read(), way, set, r_dcache_miss_buf);
+            r_dcache_fsm = DCACHE_IDLE;
+        }
+	break;
+    }
+    //////////////////////
+    case DCACHE_UNC_WAIT:
+    {
+        m_cost_unc_read_frz++;
+
+        // external cache invalidate request
+        if ( r_tgt_dcache_req ) 
+        {
+            r_dcache_fsm = DCACHE_CC_CHECK;
+            r_dcache_fsm_save = r_dcache_fsm;
+            m_cost_data_waste_wait_frz++;
+            break;
+        }
+
+	if ( !r_dcache_unc_req )
+	{
+            if ( r_vci_rsp_data_error ) 
+            {
+                r_dcache_error_type = MMU_READ_DATA_ILLEGAL_ACCESS; 
+                r_dcache_bad_vaddr = dreq.addr;
+                r_dcache_fsm = DCACHE_ERROR;
+
+		if (r_dcache_inval_tlb_rsp) r_dcache_inval_tlb_rsp = false;
+		//if (r_dcache_inval_rsp) r_dcache_inval_rsp = false;
+		break;
+            }
+
+            if ( r_dcache_inval_tlb_rsp ) // Miss read response and tlb invalidation
+            {
+                r_dcache_fsm = DCACHE_IDLE;
+                r_dcache_inval_tlb_rsp = false;
+		break;
+            }
+/*
+	    if ( r_dcache_inval_rsp ) // TLB miss response and cache invalidation
+	    {
+                r_dcache_fsm = DCACHE_IDLE; 
+            	r_dcache_inval_rsp = false;
+
+		if ((dreq.type == iss_t::DATA_LL) || (dreq.type == iss_t::DATA_SC))
+		{
+        	    r_dcache_buf_unc_valid = false;
+		    r_dcache_llsc_reserved = false;
+		}
+		break;	    
+	    }
+*/  
+            if(dreq.type == iss_t::DATA_SC) 
+	    {
+                // Simulate an invalidate request
+                r_dcache.inval(r_dcache_paddr_save);
+            }		
+            r_dcache_buf_unc_valid = true;
+	    r_dcache_fsm = DCACHE_IDLE;
+	}	
+        break;
+    }
+    ///////////////////////
+    case DCACHE_WRITE_UPDT:
+    {
+        m_cost_write_frz++;
+        size_t way = 0;
+        size_t set = 0;
+	bool write_hit = false;
+        data_t mask = vci_param::be2mask(r_dcache_be_save.read());
+        data_t wdata = (mask & r_dcache_wdata_save) | (~mask & r_dcache_rdata_save);
+        write_hit = r_dcache.write(r_dcache_paddr_save, wdata, &way, &set);
+        assert(write_hit && "Write on miss ignores data");
+        
+        if (r_dcache_in_itlb[way*m_dcache_sets+set] || r_dcache_in_dtlb[m_dcache_sets*way+set])
+        {
+	    // ins tlb invalidate verification    
+            r_dcache_itlb_inval_req = r_dcache_in_itlb[m_dcache_sets*way+set];
+            r_dcache_itlb_inval_line = (r_dcache.get_tag(way, set) * m_dcache_sets) + set;
+            r_dcache_in_itlb[way*m_dcache_sets+set] = false;
+
+            // data tlb invalidate verification
+            r_dcache_dtlb_inval_req = r_dcache_in_dtlb[m_dcache_sets*way+set]; 
+            r_dcache_dtlb_inval_line = (r_dcache.get_tag(way, set) * m_dcache_sets) + set;
+            r_dcache_in_dtlb[way*m_dcache_sets+set] = false;
+
+            r_dcache_cleanup_req = true; 
+            r_dcache_cleanup_line = (r_dcache.get_tag(way, set) * m_dcache_sets) + set;
+	    r_dcache_fsm = DCACHE_TLB_CC_INVAL;
+            r_dcache_fsm_save = r_dcache_fsm;
+            break;
+	}
+
+        if ( !r_dcache_dirty_save && (r_mmu_mode.read() & DATA_TLB_MASK) )   
+        {
+            if ( dcache_tlb.getpagesize(r_dcache_tlb_way_save, r_dcache_tlb_set_save) )	// 2M page size, one level page table 
+            {
+                r_dcache_pte_update = dcache_tlb.getpte(r_dcache_tlb_way_save, r_dcache_tlb_set_save) | PTE_D_MASK;
+                r_dcache_tlb_paddr = (paddr_t)r_mmu_ptpr << (INDEX1_NBITS+2) | (paddr_t)((dreq.addr>>PAGE_M_NBITS)<<2);
+                //write_hit = r_dcache.write((paddr_t)r_mmu_ptpr << (INDEX1_NBITS+2) | (paddr_t)((dreq.addr>>PAGE_M_NBITS)<<2), 
+                //                     (dcache_tlb.getpte(r_dcache_tlb_way_save, r_dcache_tlb_set_save) | PTE_D_MASK));
+                //assert(write_hit && "Write on miss ignores data");
+                r_dcache_tlb_ll_dirty_req = true;
+                r_dcache_fsm = DCACHE_LL_DIRTY_WAIT;
+                m_cpt_data_tlb_write_dirty++;
+            }
+            else
+            {   
+                if (r_dcache_hit_p_save) 
+                {
+                    r_dcache_pte_update = dcache_tlb.getpte(r_dcache_tlb_way_save, r_dcache_tlb_set_save) | PTE_D_MASK;
+                    r_dcache_tlb_paddr = (paddr_t)r_dcache_ptba_save|(paddr_t)(((dreq.addr&PTD_ID2_MASK)>>PAGE_K_NBITS) << 3);
+                    //write_hit = r_dcache.write(((paddr_t)r_dcache_ptba_save|(paddr_t)(((dreq.addr&PTD_ID2_MASK)>>PAGE_K_NBITS) << 3)), 
+                    //                 (dcache_tlb.getpte(r_dcache_tlb_way_save, r_dcache_tlb_set_save) | PTE_D_MASK));
+                    //assert(write_hit && "Write on miss ignores data");
+                    r_dcache_tlb_ll_dirty_req = true;
+                    r_dcache_fsm = DCACHE_LL_DIRTY_WAIT;
+                    m_cpt_data_tlb_write_dirty++;
+                }
+                else
+                {
+                    r_dcache_pte_update = dcache_tlb.getpte(r_dcache_tlb_way_save, r_dcache_tlb_set_save) | PTE_D_MASK;
+                    r_dcache_tlb_paddr = (paddr_t)r_mmu_ptpr << (INDEX1_NBITS+2) | (paddr_t)((dreq.addr>>PAGE_M_NBITS)<<2);
+                    r_dcache_tlb_ptba_read = true;
+                    r_dcache_fsm = DCACHE_DTLB1_READ_CACHE;
+                }
+            }
+        }
+        else
+        {
+            r_dcache_fsm = DCACHE_WRITE_REQ;
+            drsp.valid = true;
+            drsp.rdata = 0;
+        }
+        break;
+    }
+    ////////////////////////
+    case DCACHE_WRITE_DIRTY:
+    {
+        m_cost_data_tlb_miss_frz++;
+
+        // external cache invalidate request
+        if ( r_tgt_dcache_req ) 
+        {
+            r_dcache_fsm = DCACHE_CC_CHECK;
+            r_dcache_fsm_save = r_dcache_fsm;
+            m_cost_data_waste_wait_frz++;
+            break;
+        }
+
+        if ( r_dcache_inval_tlb_rsp ) // Miss read response and tlb invalidation
+        {
+            r_dcache_fsm = DCACHE_IDLE;
+            r_dcache_inval_tlb_rsp = false;
+	    break;
+        }
+
+	if ( r_dcache_inval_rsp ) // TLB miss response and cache invalidation
+	{
+            r_dcache_fsm = DCACHE_IDLE; 
+            r_dcache_inval_rsp = false;
+	    break;	    
+	}
+
+        r_dcache.write(r_dcache_tlb_paddr, r_dcache_pte_update);
+        dcache_tlb.setdirty(r_dcache_tlb_way_save, r_dcache_tlb_set_save);
+        r_dcache_fsm = DCACHE_WRITE_REQ;
+        drsp.valid = true;
+        drsp.rdata = 0;
+        break;
+    }
+    /////////////////
+    case DCACHE_ERROR:
+    {
+        r_vci_rsp_data_error = false;
+        drsp.valid = true;
+        drsp.error = true;
+        drsp.rdata = 0;
+        r_dcache_fsm = DCACHE_IDLE;
+        break;
+    }   
+    ////////////////////// 
+    case DCACHE_ITLB_READ:
+    {
+        m_cost_data_waste_wait_frz++;
+
+        // external cache invalidate request
+        if ( r_tgt_dcache_req ) 
+        {
+            r_dcache_fsm = DCACHE_CC_CHECK;
+            r_dcache_fsm_save = r_dcache_fsm;
+            m_cost_data_waste_wait_frz++;
+            break;
+        }
+
+    	if ( !r_dcache_itlb_read_req ) // vci response ok
+        {  
+            if ( r_vci_rsp_data_error )
+            {
+                r_dcache_rsp_itlb_error = true;	
+                r_itlb_read_dcache_req = false;
+                r_vci_rsp_data_error = false;
+                r_dcache_fsm = DCACHE_IDLE;
+
+		if (r_dcache_inval_rsp) r_dcache_inval_rsp = false;
+		break;
+            }
+
+	    if ( r_dcache_inval_rsp ) // TLB miss response and cache invalidation
+	    {
+                r_dcache_fsm = DCACHE_IDLE; 
+            	r_dcache_inval_rsp = false;
+		break;	    
+	    }
+            r_dcache_fsm = DCACHE_ITLB_UPDT;
+        }
+	break;    	
+    }
+    //////////////////////
+    case DCACHE_ITLB_UPDT:
+    {
+        m_cost_data_waste_wait_frz++;
+
+        // external cache invalidate request
+        if ( r_tgt_dcache_req ) 
+        {
+            r_dcache_fsm = DCACHE_CC_CHECK;
+            r_dcache_fsm_save = r_dcache_fsm;
+            m_cost_data_waste_wait_frz++;
+            break;
+        }
+
+        // Using tlb entry is in the invalidated cache line  
+        if ( r_dcache_inval_rsp )
+        {
+            r_dcache_inval_rsp = false;
+            r_dcache_fsm = DCACHE_IDLE;
+            m_cost_data_tlb_miss_frz++;
+            break;
+        }
+
+        if ( !r_dcache_cleanup_req )
+        {
+            data_t rsp_itlb_miss = 0;
+	    data_t rsp_itlb_ppn = 0;
+
+            paddr_t  victim_index = 0;
+            size_t way = 0;
+            size_t set = 0;
+            
+            bool cleanup = r_dcache.find(r_icache_paddr_save, r_dcache_in_itlb, r_dcache_in_dtlb, &way, &set, &victim_index);
+
+	    if ( cleanup )
+	    {	    
+		// ins tlb invalidate verification    
+                r_dcache_itlb_inval_req = r_dcache_in_itlb[m_dcache_sets*way+set];
+                r_dcache_itlb_inval_line = victim_index;
+                r_dcache_in_itlb[way*m_dcache_sets+set] = false;
+
+                // data tlb invalidate verification
+                r_dcache_dtlb_inval_req = r_dcache_in_dtlb[m_dcache_sets*way+set]; 
+                r_dcache_dtlb_inval_line = victim_index;
+                r_dcache_in_dtlb[way*m_dcache_sets+set] = false;
+
+                r_dcache_cleanup_req = true; 
+                r_dcache_cleanup_line = victim_index;
+		r_dcache_fsm = DCACHE_TLB_CC_INVAL;
+                r_dcache_fsm_save = r_dcache_fsm;
+		break;
+	    }
+
+            r_dcache.update(r_icache_paddr_save, way, set, r_dcache_miss_buf);
+
+            r_dcache.setinbit(r_icache_paddr_save, r_dcache_in_itlb, true);
+            bool itlb_hit_dcache = r_dcache.read(r_icache_paddr_save, &rsp_itlb_miss);	
+ 
+	    if ( (r_icache_fsm == ICACHE_TLB2_READ) && itlb_hit_dcache )
+	    {	
+            	bool itlb_hit_ppn = r_dcache.read(r_icache_paddr_save.read()+4, &rsp_itlb_ppn);
+		assert(itlb_hit_ppn && "Address of pte[64-32] and pte[31-0] should be successive");
+	    }
+
+            r_dcache_rsp_itlb_miss = rsp_itlb_miss;
+            r_dcache_rsp_itlb_ppn = rsp_itlb_ppn;
+            r_dcache_rsp_itlb_error = false;	
+            r_itlb_read_dcache_req = false;
+            r_dcache_fsm = DCACHE_IDLE;
+        }
+        break;
+    }
+    //////////////////////////
+    case DCACHE_ITLB_LL_WAIT:
+    {
+        // external cache invalidate request
+        if ( r_tgt_dcache_req )   
+        {
+            r_dcache_fsm = DCACHE_CC_CHECK;
+            r_dcache_fsm_save = r_dcache_fsm;
+            m_cost_data_waste_wait_frz++;
+            break;
+        }
+
+	if (!r_dcache_itlb_ll_acc_req)
+	{
+            if ( r_vci_rsp_data_error ) // VCI response ko
+            {
+                r_dcache_rsp_itlb_error = true;  
+                r_vci_rsp_data_error = false;
+                r_itlb_acc_dcache_req = false;
+		r_dcache_fsm = DCACHE_IDLE;
+		if (r_dcache_inval_rsp) r_dcache_inval_rsp = false;	
+            }
+	    else
+	    {
+	        if ( !(r_dcache_miss_buf[0] >> PTE_V_SHIFT) )	// unmapped
+	        {
+                    r_dcache_rsp_itlb_error = true;  
+                    r_itlb_acc_dcache_req = false;
+		    r_dcache_fsm = DCACHE_IDLE;	
+		    if (r_dcache_inval_rsp) r_dcache_inval_rsp = false;	
+	        }
+       		else if ( r_dcache_inval_rsp )
+       		{
+       		    r_dcache_inval_rsp = false;
+       		    r_dcache_fsm = DCACHE_IDLE;
+       		    m_cost_data_tlb_miss_frz++;
+       		}
+		else
+		{
+		    r_dcache_itlb_sc_acc_req = true;
+		    r_icache_pte_update = r_dcache_miss_buf[0] | r_icache_pte_update.read();	
+                    r_dcache_fsm = DCACHE_ITLB_SC_WAIT; 
+		}
+	    }
+	}
+	break;
+    }
+    //////////////////////////
+    case DCACHE_ITLB_SC_WAIT:
+    {
+        // external cache invalidate request
+        if ( r_tgt_dcache_req )   
+        {
+            r_dcache_fsm = DCACHE_CC_CHECK;
+            r_dcache_fsm_save = r_dcache_fsm;
+            m_cost_data_waste_wait_frz++;
+            break;
+        }
+	
+        if ( !r_dcache_itlb_sc_acc_req ) 
+	{
+	    if ( r_vci_rsp_data_error ) // VCI response ko
+	    {
+	        r_dcache_rsp_itlb_error = true;  
+	        r_vci_rsp_data_error = false;
+	        r_itlb_acc_dcache_req = false;
+	        r_dcache_fsm = DCACHE_IDLE;
+		if (r_dcache_inval_rsp) r_dcache_inval_rsp = false;		
+	    }
+	    else
+	    {
+	        if ( r_dcache_inval_rsp )
+	        {
+	            r_dcache_inval_rsp = false;
+	            r_dcache_fsm = DCACHE_IDLE;
+	            m_cost_data_tlb_miss_frz++;
+	        }
+	        else if ( r_dcache_itlb_ll_acc_req )
+	        {
+	            r_dcache_fsm = DCACHE_ITLB_LL_WAIT; 
+	        }
+	        else 
+	        {
+	            r_itlb_acc_dcache_req = false;
+	            r_dcache_fsm = DCACHE_IDLE; 
+	        }
+	    }
+	}
+	break;
+    }
+    /////////////////////
+    case DCACHE_CC_CHECK:   // read directory in case of invalidate or update request
+    {
+        if ( dreq.valid ) m_cost_data_waste_wait_frz++;
+
+        m_cpt_dcache_dir_read += m_dcache_ways;
+        m_cpt_dcache_data_read += m_dcache_ways;
+
+        data_t dcache_rdata = 0;
+        size_t way = 0;
+        size_t set = 0;
+
+        bool dcache_hit = r_dcache.read(r_tgt_addr.read(), &dcache_rdata, &way, &set);
+
+        if ( dcache_hit )
+        {
+            if ( r_dcache_in_dtlb[m_dcache_sets*way+set] || r_dcache_in_itlb[m_dcache_sets*way+set] )
+	    {
+		// ins tlb invalidate verification    
+                r_dcache_itlb_inval_req = r_dcache_in_itlb[m_dcache_sets*way+set];
+                r_dcache_itlb_inval_line = r_tgt_addr.read() >> (uint32_log2(m_dcache_words)+2);
+                r_dcache_in_itlb[way*m_dcache_sets+set] = false;
+
+                // data tlb invalidate verification
+                r_dcache_dtlb_inval_req = r_dcache_in_dtlb[m_dcache_sets*way+set]; 
+                r_dcache_dtlb_inval_line = r_tgt_addr.read() >> (uint32_log2(m_dcache_words)+2);
+                r_dcache_in_dtlb[way*m_dcache_sets+set] = false;
+		
+		r_dcache_cc_check = true;
+		r_dcache_fsm = DCACHE_TLB_CC_INVAL;
+		break;
+	    }
+
+            if(( /*( r_dcache_fsm_save == DCACHE_UNC_WAIT ) ||*/
+	         ( r_dcache_fsm_save == DCACHE_MISS_WAIT ) || ( r_dcache_fsm_save == DCACHE_MISS_UPDT ) ) && 
+               ( (r_dcache_paddr_save.read() & ~((m_dcache_words<<2)-1)) == (r_tgt_addr.read() & ~((m_dcache_words<<2)-1)))) 
+            {
+	        r_dcache_inval_rsp = true;
+            } 
+
+            if(( ( r_dcache_fsm_save == DCACHE_TLB1_READ )      || ( r_dcache_fsm_save == DCACHE_TLB2_READ )      ||
+		 ( r_dcache_fsm_save == DCACHE_TLB1_READ_UPDT ) || ( r_dcache_fsm_save == DCACHE_TLB2_READ_UPDT ) ||
+                 ( r_dcache_fsm_save == DCACHE_TLB1_UPDT )      || ( r_dcache_fsm_save == DCACHE_TLB2_UPDT )	  ||
+		 ( r_dcache_fsm_save == DCACHE_TLB1_LL_WAIT )   || ( r_dcache_fsm_save == DCACHE_TLB2_LL_WAIT )   ||
+		 ( r_dcache_fsm_save == DCACHE_TLB1_SC_WAIT )   || ( r_dcache_fsm_save == DCACHE_TLB2_SC_WAIT )   ||
+		 ( r_dcache_fsm_save == DCACHE_LL_DIRTY_WAIT )  || ( r_dcache_fsm_save == DCACHE_SC_DIRTY_WAIT )  ||
+		 ( r_dcache_fsm_save == DCACHE_WRITE_DIRTY ) ) && 
+               ( (r_dcache_tlb_paddr.read() & ~((m_dcache_words<<2)-1)) == (r_tgt_addr.read() & ~((m_dcache_words<<2)-1))) ) 
+            {
+                r_dcache_inval_rsp = true;
+            }
+
+            if(( ( r_dcache_fsm_save == DCACHE_ITLB_READ ) || ( r_dcache_fsm_save == DCACHE_ITLB_UPDT ) ||
+                 ( r_dcache_fsm_save == DCACHE_ITLB_LL_WAIT ) || ( r_dcache_fsm_save == DCACHE_ITLB_SC_WAIT ) ) && 
+               ( (r_icache_paddr_save.read() & ~((m_dcache_words<<2)-1)) == (r_tgt_addr.read() & ~((m_dcache_words<<2)-1))) ) 
+            {
+                r_dcache_inval_rsp = true;
+            }
+
+            if ( r_tgt_update ) // update 
+            {
+                r_dcache_fsm = DCACHE_CC_UPDT;
+            } 
+            else                // invalidate 
+            {
+                r_dcache_fsm = DCACHE_CC_INVAL;
+            }
+        }
+        else                    // nothing
+        {
+            r_dcache_fsm = DCACHE_CC_NOP;
+        }
+        break;
+    }
+    ///////////////////
+    case DCACHE_CC_UPDT:    // update directory and data cache        
+    {
+        if ( dreq.valid ) m_cost_data_waste_wait_frz++;
+
+        m_cpt_dcache_dir_write++;
+        m_cpt_dcache_data_write++;
+        data_t* buf = r_tgt_buf;
+        for( size_t i = 0; i < m_dcache_words; i++ )
+        {
+            if( r_tgt_val[i] ) r_dcache.write( r_tgt_addr.read() + i*4, buf[i] );
+        }
+           
+        r_tgt_dcache_req = false;
+        r_dcache_fsm = r_dcache_fsm_save;
+        break;
+    }
+    /////////////////////
+    case DCACHE_CC_INVAL:   // invalidate a cache line
+    {
+        if ( dreq.valid ) m_cost_data_waste_wait_frz++;
+
+        r_tgt_dcache_rsp = r_dcache.inval(r_tgt_addr.read());
+        r_tgt_dcache_req = false;
+        r_dcache_fsm = r_dcache_fsm_save;
+        break;
+    }
+    ///////////////////
+    case DCACHE_CC_NOP:     // no external hit
+    {
+        if ( dreq.valid ) m_cost_data_waste_wait_frz++;
+
+        r_tgt_dcache_req = false;
+        r_dcache_fsm = r_dcache_fsm_save;
+        break;
+    }   
+    /////////////////////////
+    case DCACHE_TLB_CC_INVAL:
+    {
+        if ( dreq.valid ) m_cost_data_waste_wait_frz++;
+
+	if ( r_dcache_itlb_inval_req || r_dcache_dtlb_inval_req ) break;
+
+        if( (( r_dcache_fsm_save == DCACHE_TLB1_READ )        || ( r_dcache_fsm_save == DCACHE_TLB2_READ )        ||
+             ( r_dcache_fsm_save == DCACHE_TLB1_READ_UPDT )   || ( r_dcache_fsm_save == DCACHE_TLB2_READ_UPDT )   ||
+             ( r_dcache_fsm_save == DCACHE_TLB1_LL_WAIT )     || ( r_dcache_fsm_save == DCACHE_TLB2_LL_WAIT )     ||
+             ( r_dcache_fsm_save == DCACHE_TLB1_SC_WAIT )     || ( r_dcache_fsm_save == DCACHE_TLB2_SC_WAIT )     ||
+             ( r_dcache_fsm_save == DCACHE_TLB1_UPDT )        || ( r_dcache_fsm_save == DCACHE_TLB2_UPDT )        ||
+             ( r_dcache_fsm_save == DCACHE_DTLB1_READ_CACHE ) || ( r_dcache_fsm_save == DCACHE_DTLB2_READ_CACHE ) ||
+             ( r_dcache_fsm_save == DCACHE_LL_DIRTY_WAIT )    || ( r_dcache_fsm_save == DCACHE_SC_DIRTY_WAIT )    ||
+	     ( r_dcache_fsm_save == DCACHE_WRITE_DIRTY )) && 
+            (((r_dcache_tlb_paddr.read() & ~((m_dcache_words<<2)-1)) >> (uint32_log2(m_dcache_words) + 2)) == r_dcache_dtlb_inval_line.read()) ) 
+        {
+            r_dcache_inval_tlb_rsp = true;
+        } 
+
+        if (((r_dcache_fsm_save == DCACHE_BIS)||(r_dcache_fsm_save == DCACHE_MISS_WAIT) ||
+             (r_dcache_fsm_save == DCACHE_UNC_WAIT)||(r_dcache_fsm_save == DCACHE_MISS_UPDT)) && 
+             (r_dcache_tlb_nline == r_dcache_dtlb_inval_line))
+        {
+            r_dcache_inval_tlb_rsp = true;
+        }
+
+	if ( !r_dcache_cc_check )
+	{
+            r_dcache_fsm = r_dcache_fsm_save;
+	}
+	else
+	{
+            r_dcache_fsm = DCACHE_CC_CHECK;
+	    r_dcache_cc_check = false;
+	}
+        break;
+    }
+    /////////////////////////
+    case DCACHE_ITLB_CLEANUP:
+    {
+        if ( dreq.valid ) m_cost_data_waste_wait_frz++;
+
+        r_dcache.setinbit(((paddr_t)r_dcache_itlb_cleanup_line.read()*m_dcache_words*2), r_dcache_in_itlb, false);
+        r_dcache_itlb_cleanup_req = false;
+        r_dcache_fsm = DCACHE_IDLE;
+        break;
+    }
+    } // end switch r_dcache_fsm
+
+#ifdef SOCLIB_MODULE_DEBUG
+    std::cout << name() << " Data Response: " << drsp << std::endl;
+#endif
+
+    ////////////////////////////////////////////////////////////////////////////////////
+    //      INVAL DTLB CHECK FSM 
+    ////////////////////////////////////////////////////////////////////////////////////////
+    switch(r_inval_dtlb_fsm) {
+    /////////////////////
+    case INVAL_DTLB_IDLE:
+    {
+        if ( r_dcache_dtlb_inval_req ) 
+        {
+            r_ccinval_dtlb_way = 0;
+            r_ccinval_dtlb_set = 0;
+            r_inval_dtlb_fsm = INVAL_DTLB_CHECK;    
+            m_cost_data_tlb_inval_frz++;
+        }   
+        break;
+    }
+    ////////////////////////////
+    case INVAL_DTLB_CHECK:
+    {
+        m_cost_data_tlb_inval_frz++;
+
+        size_t way = r_ccinval_dtlb_way; 
+        size_t set = r_ccinval_dtlb_set;
+        bool end = false;        
+        bool tlb_hit = dcache_tlb.cccheck(r_dcache_dtlb_inval_line.read(), way, set, &way, &set, &end); 
+    
+        if ( tlb_hit )
+        {
+            r_ccinval_dtlb_way = way; 
+            r_ccinval_dtlb_set = set;
+            r_dtlb_cc_check_end = end;
+            r_inval_dtlb_fsm = INVAL_DTLB_INVAL;
+            m_cpt_data_tlb_inval++;    
+        }        
+        else
+        {
+            r_inval_dtlb_fsm = INVAL_DTLB_CLEAR;    
+        }
+        break;
+    }
+    /////////////////////////
+    case INVAL_DTLB_INVAL:
+    {
+        m_cost_data_tlb_inval_frz++;
+
+        dcache_tlb.ccinval(r_ccinval_dtlb_way, r_ccinval_dtlb_set);
+
+        if ( !r_dtlb_cc_check_end )
+        {
+            r_inval_dtlb_fsm = INVAL_DTLB_CHECK; 
+        }
+        else
+        {
+            r_inval_dtlb_fsm = INVAL_DTLB_CLEAR;    
+        }
+        break;
+    }
+    ////////////////////
+    case INVAL_DTLB_CLEAR:
+    {
+        r_dcache_dtlb_inval_req = false;
+        r_dtlb_cc_check_end = false;
+        r_ccinval_dtlb_way = 0; 
+        r_ccinval_dtlb_set = 0; 
+        r_inval_dtlb_fsm = INVAL_DTLB_IDLE;   
+        m_cpt_data_tlb_inval++;    
+        break;
+    }
+    } // end switch r_inval_itlb_fsm
+
+    /////////// execute one iss cycle /////////////////////////////////
+    {
+    uint32_t it = 0;
+    for (size_t i=0; i<(size_t)iss_t::n_irq; i++) if(p_irq[i].read()) it |= (1<<i);
+    m_iss.executeNCycles(1, irsp, drsp, it);
+    }
+
+    ////////////// number of frozen cycles //////////////////////////
+    if ( (ireq.valid && !irsp.valid) || (dreq.valid && !drsp.valid) )
+    {
+        m_cpt_frz_cycles++;
+    }
+
+    ////////////////////////////////////////////////////////////////////////////
+    //     VCI_CMD FSM 
+    //
+    // This FSM handles requests from both the DCACHE controler
+    // (request registers) and the ICACHE controler (request registers).
+    // There is 10 VCI transaction types :
+    // - INS_TLB_READ
+    // - INS_TLB_WRITE
+    // - INS_MISS
+    // - INS_UNC_MISS
+    // - DATA_TLB_READ
+    // - DATA_TLB_WRITE
+    // - DATA_TLB_DIRTY
+    // - DATA_MISS
+    // - DATA_UNC 
+    // - DATA_WRITE
+    // The ICACHE requests have the highest priority.
+    // There is at most one (CMD/RSP) VCI transaction, as both CMD_FSM and RSP_FSM
+    // exit simultaneously the IDLE state.
+    //////////////////////////////////////////////////////////////////////////////
+
+    switch (r_vci_cmd_fsm) {
+    
+    case CMD_IDLE:
+        if (r_vci_rsp_fsm != RSP_IDLE)
+            break;
+
+        r_vci_cmd_cpt = 0;
+
+        if (r_dcache_itlb_read_req)           
+        {            
+            r_vci_cmd_fsm = CMD_ITLB_READ;
+            m_cpt_itlbmiss_transaction++; 
+        } 
+	else if (r_dcache_itlb_ll_acc_req)
+	{
+	    r_vci_cmd_fsm = CMD_ITLB_ACC_LL;
+            m_cpt_itlb_write_transaction++; 
+	}
+	else if (r_dcache_itlb_sc_acc_req)
+	{
+	    r_vci_cmd_fsm = CMD_ITLB_ACC_SC;
+            m_cpt_itlb_write_transaction++; 
+	}
+        else if (r_icache_miss_req) 
+        {    
+            r_vci_cmd_fsm = CMD_INS_MISS;
+            m_cpt_imiss_transaction++; 
+        }
+        else if (r_icache_unc_req) 
+        {    
+            r_vci_cmd_fsm = CMD_INS_UNC;
+            m_cpt_imiss_transaction++; 
+        }  
+        else if (r_dcache_tlb_read_req) 
+        {            
+            r_vci_cmd_fsm = CMD_DTLB_READ;
+            m_cpt_dtlbmiss_transaction++; 
+        } 
+        else if (r_dcache_tlb_ll_acc_req) 
+        {  
+            r_vci_cmd_fsm = CMD_DTLB_ACC_LL;
+            m_cpt_dtlb_write_transaction++; 
+        } 
+        else if (r_dcache_tlb_sc_acc_req) 
+        {  
+            r_vci_cmd_fsm = CMD_DTLB_ACC_SC;
+            m_cpt_dtlb_write_transaction++; 
+        } 
+        else if (r_dcache_tlb_ll_dirty_req) 
+        {  
+            r_vci_cmd_fsm = CMD_DTLB_DIRTY_LL;
+            m_cpt_dtlb_write_transaction++; 
+        } 
+        else if (r_dcache_tlb_sc_dirty_req) 
+        {  
+            r_vci_cmd_fsm = CMD_DTLB_DIRTY_SC;
+            m_cpt_dtlb_write_transaction++; 
+        } 
+        else if (r_dcache_write_req)
+        {
+            r_vci_cmd_fsm = CMD_DATA_WRITE;
+            r_vci_cmd_cpt = r_wbuf.getMin();
+            r_vci_cmd_min = r_wbuf.getMin();
+            r_vci_cmd_max = r_wbuf.getMax(); 
+            m_cpt_write_transaction++; 
+            m_length_write_transaction += (r_wbuf.getMax() - r_wbuf.getMin() + 1);
+        }
+        else if (r_dcache_miss_req)  
+        {
+            r_vci_cmd_fsm = CMD_DATA_MISS;
+            m_cpt_dmiss_transaction++; 
+        }
+        else if (r_dcache_unc_req)  
+        {
+            r_vci_cmd_fsm = CMD_DATA_UNC;
+            m_cpt_unc_transaction++; 
+        }
+        else if (r_icache_cleanup_req)
+        {
+            r_vci_cmd_fsm = CMD_INS_CLEANUP;
+        }
+        else if (r_dcache_cleanup_req)
+        {
+            r_vci_cmd_fsm = CMD_DATA_CLEANUP;
+        }
+        break;
+
+    case CMD_DATA_WRITE:
+        if ( p_vci_ini.cmdack.read() ) 
+        {
+            r_vci_cmd_cpt = r_vci_cmd_cpt + 1;
+            if (r_vci_cmd_cpt == r_vci_cmd_max) 
+            {
+                r_vci_cmd_fsm = CMD_IDLE;
+                r_wbuf.reset();
+            }
+        }
+        break;
+
+    default:
+        if ( p_vci_ini.cmdack.read() )
+        {  
+            r_vci_cmd_fsm = CMD_IDLE;
+        }
+        break;
+
+    } // end  switch r_vci_cmd_fsm
+
+    //////////////////////////////////////////////////////////////////////////
+    //      VCI_RSP FSM 
+    //
+    // This FSM is synchronized with the VCI_CMD FSM, as both FSMs exit the
+    // IDLE state simultaneously.
+    //////////////////////////////////////////////////////////////////////////
+
+    switch (r_vci_rsp_fsm) {
+
+    case RSP_IDLE:
+        assert( ! p_vci_ini.rspval.read() && "Unexpected response" );
+
+        if (r_vci_cmd_fsm != CMD_IDLE)
+            break;
+
+        r_vci_rsp_cpt = 0;
+        if (r_dcache_itlb_read_req)          // ITLB miss response
+        {            
+            r_vci_rsp_fsm = RSP_ITLB_READ;
+        } 
+        else if (r_dcache_itlb_ll_acc_req)   // ITLB linked load response
+        {   
+            r_vci_rsp_fsm = RSP_ITLB_ACC_LL;
+        } 
+        else if (r_dcache_itlb_sc_acc_req)   // ITLB store conditional response
+        {   
+            r_vci_rsp_fsm = RSP_ITLB_ACC_SC;
+        } 
+        else if (r_icache_miss_req)          // ICACHE cached miss response
+        {   
+            r_vci_rsp_fsm = RSP_INS_MISS;
+        }
+        else if (r_icache_unc_req)           // ICACHE uncached miss response
+        {   
+            r_vci_rsp_fsm = RSP_INS_UNC;
+        }  
+        else if (r_dcache_tlb_read_req)      // ITLB miss response
+        {
+            r_vci_rsp_fsm = RSP_DTLB_READ; 
+        }
+        else if (r_dcache_tlb_ll_acc_req)    // DTLB access bits linked load response
+        {
+            r_vci_rsp_fsm = RSP_DTLB_ACC_LL; 
+        }
+        else if (r_dcache_tlb_sc_acc_req)    // DTLB access bits store conditional response
+        {
+            r_vci_rsp_fsm = RSP_DTLB_ACC_SC; 
+        }
+        else if (r_dcache_tlb_ll_dirty_req)  // DTLB dirty bit linked load response
+        {
+            r_vci_rsp_fsm = RSP_DTLB_DIRTY_LL; 
+        }
+        else if (r_dcache_tlb_sc_dirty_req)  // DTLB dirty bit store conditional response
+        {
+            r_vci_rsp_fsm = RSP_DTLB_DIRTY_SC; 
+        }
+        else if (r_dcache_write_req)         // DCACHE write response
+        {
+            r_vci_rsp_fsm = RSP_DATA_WRITE;
+        }
+        else if (r_dcache_miss_req)          // DCACHE read response
+        {
+            r_vci_rsp_fsm = RSP_DATA_MISS;
+        }
+        else if (r_dcache_unc_req)           // DCACHE uncached read response
+        {
+            r_vci_rsp_fsm = RSP_DATA_UNC;
+        }
+        else if (r_icache_cleanup_req)	     // ICACHE cleanup response 
+        {
+            r_vci_rsp_fsm = RSP_INS_CLEANUP;
+        }
+        else if (r_dcache_cleanup_req)	     // DCACHE cleanup response
+        {
+            r_vci_rsp_fsm = RSP_DATA_CLEANUP;
+        }
+        break;
+
+    case RSP_ITLB_READ:
+        m_cost_itlbmiss_transaction++;
+        if ( ! p_vci_ini.rspval.read() )
+            break;
+
+        assert(r_vci_rsp_cpt != m_dcache_words &&
+               "illegal VCI response packet for data read miss");
+
+        r_vci_rsp_cpt = r_vci_rsp_cpt + 1;
+        r_dcache_miss_buf[r_vci_rsp_cpt] = (data_t)p_vci_ini.rdata.read();
+        if ( p_vci_ini.reop.read() ) 
+        {
+            assert(r_vci_rsp_cpt == m_dcache_words - 1 &&
+                    "illegal VCI response packet for data read miss");
+            r_dcache_itlb_read_req = false;
+            r_vci_rsp_fsm = RSP_IDLE;
+        } 
+        if ( p_vci_ini.rerror.read() != vci_param::ERR_NORMAL )
+        {
+            r_vci_rsp_data_error = true;
+        }
+        break;
+
+    case RSP_ITLB_ACC_LL:
+        if ( ! p_vci_ini.rspval.read() )
+            break;
+
+        assert(p_vci_ini.reop.read() &&
+               "illegal VCI response packet for ll tlb");
+
+        if ( p_vci_ini.rerror.read() != vci_param::ERR_NORMAL ) 
+        {
+            r_vci_rsp_data_error = true;
+        }
+	else
+	{
+	    r_dcache_miss_buf[0] = (data_t)p_vci_ini.rdata.read();
+	}
+        r_dcache_itlb_ll_acc_req = false;
+        r_vci_rsp_fsm = RSP_IDLE;
+	break;
+
+    case RSP_ITLB_ACC_SC:
+        if ( ! p_vci_ini.rspval.read() )
+            break;
+
+        assert(p_vci_ini.reop.read() &&
+               "illegal VCI response packet for sc tlb");
+
+        if ( p_vci_ini.rerror.read() != vci_param::ERR_NORMAL ) 
+        {
+            r_vci_rsp_data_error = true;
+        }
+	else if ( p_vci_ini.rdata.read() == 1 ) // store conditional is not successful
+	{
+	    r_dcache_itlb_ll_acc_req = true;
+	}
+        r_dcache_itlb_sc_acc_req = false;
+        r_vci_rsp_fsm = RSP_IDLE;
+	break;
+
+    case RSP_INS_MISS:
+        m_cost_imiss_transaction++;
+        if ( ! p_vci_ini.rspval.read() )
+            break;
+
+        assert( (r_vci_rsp_cpt < m_icache_words) && 
+               "The VCI response packet for instruction miss is too long");
+        r_vci_rsp_cpt = r_vci_rsp_cpt + 1;
+        r_icache_miss_buf[r_vci_rsp_cpt] = (data_t)p_vci_ini.rdata.read();
+
+        if ( p_vci_ini.reop.read() ) 
+        {
+            assert( (r_vci_rsp_cpt == m_icache_words - 1) &&
+                       "The VCI response packet for instruction miss is too short");
+            r_icache_miss_req = false;
+            r_vci_rsp_fsm = RSP_IDLE;
+                
+        } 
+        if ( p_vci_ini.rerror.read() != vci_param::ERR_NORMAL )
+        {
+            r_vci_rsp_ins_error = true;
+        }
+        break;
+
+    case RSP_INS_UNC:
+        m_cost_imiss_transaction++;
+        if ( ! p_vci_ini.rspval.read() )
+            break;
+
+        assert(p_vci_ini.reop.read() &&
+               "illegal VCI response packet for uncached instruction");
+
+        r_icache_miss_buf[0] = (data_t)p_vci_ini.rdata.read();
+        r_icache_buf_unc_valid = true;
+        r_icache_unc_req = false;
+        r_vci_rsp_fsm = RSP_IDLE;
+
+        if ( p_vci_ini.rerror.read() != vci_param::ERR_NORMAL )
+        {
+            r_vci_rsp_ins_error = true;
+        }
+        break;
+
+    case RSP_DTLB_READ:
+        m_cost_dtlbmiss_transaction++;
+        if ( ! p_vci_ini.rspval.read() )
+            break;
+
+        assert(r_vci_rsp_cpt != m_dcache_words &&
+               "illegal VCI response packet for data read miss");
+
+        r_vci_rsp_cpt = r_vci_rsp_cpt + 1;
+        r_dcache_miss_buf[r_vci_rsp_cpt] = (data_t)p_vci_ini.rdata.read();
+        if ( p_vci_ini.reop.read() ) 
+        {
+            assert(r_vci_rsp_cpt == m_dcache_words - 1 &&
+                    "illegal VCI response packet for data read miss");
+            r_dcache_tlb_read_req = false;
+            r_vci_rsp_fsm = RSP_IDLE;
+        } 
+        if ( p_vci_ini.rerror.read() != vci_param::ERR_NORMAL )
+        {
+            r_vci_rsp_data_error = true;
+        }
+        break;
+
+    case RSP_DTLB_ACC_LL:
+        if ( ! p_vci_ini.rspval.read() )
+            break;
+
+        assert(p_vci_ini.reop.read() &&
+               "illegal VCI response packet for ll tlb");
+
+        if ( p_vci_ini.rerror.read() != vci_param::ERR_NORMAL ) 
+        {
+            r_vci_rsp_data_error = true;
+        }
+	else
+	{
+	    r_dcache_miss_buf[0] = (data_t)p_vci_ini.rdata.read();
+	}
+        r_dcache_tlb_ll_acc_req = false;
+        r_vci_rsp_fsm = RSP_IDLE;
+	break;
+
+    case RSP_DTLB_ACC_SC:
+        if ( ! p_vci_ini.rspval.read() )
+            break;
+
+        assert(p_vci_ini.reop.read() &&
+               "illegal VCI response packet for sc tlb");
+
+        if ( p_vci_ini.rerror.read() != vci_param::ERR_NORMAL ) 
+        {
+            r_vci_rsp_data_error = true;
+        }
+	else if ( p_vci_ini.rdata.read() == 1 ) // store conditional is not successful
+	{
+	    r_dcache_tlb_ll_acc_req = true;
+	}
+        r_dcache_tlb_sc_acc_req = false;
+        r_vci_rsp_fsm = RSP_IDLE;
+	break;
+
+    case RSP_DTLB_DIRTY_LL:
+        if ( ! p_vci_ini.rspval.read() )
+            break;
+
+        assert(p_vci_ini.reop.read() &&
+               "illegal VCI response packet for ll tlb");
+
+        if ( p_vci_ini.rerror.read() != vci_param::ERR_NORMAL ) 
+        {
+            r_vci_rsp_data_error = true;
+        }
+	else
+	{
+	    r_dcache_miss_buf[0] = (data_t)p_vci_ini.rdata.read();
+	}
+        r_dcache_tlb_ll_dirty_req = false;
+        r_vci_rsp_fsm = RSP_IDLE;
+	break;
+
+    case RSP_DTLB_DIRTY_SC:
+        if ( ! p_vci_ini.rspval.read() )
+            break;
+
+        assert(p_vci_ini.reop.read() &&
+               "illegal VCI response packet for sc tlb");
+
+        if ( p_vci_ini.rerror.read() != vci_param::ERR_NORMAL ) 
+        {
+            r_vci_rsp_data_error = true;
+        }
+	else if ( p_vci_ini.rdata.read() == 1 ) // store conditional is not successful
+	{
+	    r_dcache_tlb_ll_dirty_req = true;
+	}
+        r_dcache_tlb_sc_dirty_req = false;
+        r_vci_rsp_fsm = RSP_IDLE;
+	break;
+
+    case RSP_DATA_UNC:
+        m_cost_unc_transaction++;
+        if ( ! p_vci_ini.rspval.read() ) 
+            break;
+
+        assert(p_vci_ini.reop.read() &&
+               "illegal VCI response packet for data read uncached");
+
+        if ( p_vci_ini.rerror.read() != vci_param::ERR_NORMAL ) 
+        {
+            r_vci_rsp_data_error = true;
+        }
+        else
+        {
+            r_dcache_miss_buf[0] = (data_t)p_vci_ini.rdata.read();
+            r_dcache_buf_unc_valid = true;
+        }
+        r_dcache_unc_req = false;
+        r_vci_rsp_fsm = RSP_IDLE;
+        break;
+
+    case RSP_DATA_MISS:
+        m_cost_dmiss_transaction++;
+        if ( ! p_vci_ini.rspval.read() )
+            break;
+
+        assert(r_vci_rsp_cpt != m_dcache_words &&
+               "illegal VCI response packet for data read miss");
+
+        r_vci_rsp_cpt = r_vci_rsp_cpt + 1;
+        r_dcache_miss_buf[r_vci_rsp_cpt] = (data_t)p_vci_ini.rdata.read();
+        if ( p_vci_ini.reop.read() ) 
+        {
+            assert(r_vci_rsp_cpt == m_dcache_words - 1 &&
+                    "illegal VCI response packet for data read miss");
+            r_dcache_miss_req = false;
+            r_vci_rsp_fsm = RSP_IDLE;
+        } 
+        if ( p_vci_ini.rerror.read() != vci_param::ERR_NORMAL )
+        {
+            r_vci_rsp_data_error = true;
+        }
+        break;
+
+    case RSP_DATA_WRITE:
+        m_cost_write_transaction++;
+        if ( ! p_vci_ini.rspval.read() )
+            break;
+
+        if ( p_vci_ini.reop.read() ) 
+        {
+            r_vci_rsp_fsm = RSP_IDLE;
+            r_dcache_write_req = false;
+        }
+        if ( p_vci_ini.rerror.read() != vci_param::ERR_NORMAL ) 
+        {
+            m_iss.setWriteBerr();
+        }
+        break;
+
+    case RSP_INS_CLEANUP:
+    case RSP_DATA_CLEANUP:
+        if ( ! p_vci_ini.rspval.read() )
+            break;
+        assert( p_vci_ini.reop.read() &&
+                "illegal VCI response packet for icache cleanup");
+        assert( (p_vci_ini.rerror.read() == vci_param::ERR_NORMAL) &&
+                "error in response packet for icache cleanup");
+
+        if ( r_vci_rsp_fsm == RSP_INS_CLEANUP ) 
+        {
+            r_icache_cleanup_req = false;
+        }
+        else
+        {                                    
+            r_dcache_cleanup_req = false;
+        }
+        r_vci_rsp_fsm = RSP_IDLE;
+        break;
+
+    } // end switch r_vci_rsp_fsm
+} // end transition()
+
+///////////////////////
+tmpl(void)::genMoore()
+///////////////////////
+{
+    // VCI initiator response
+
+    p_vci_ini.rspack = true;
+
+    // VCI initiator command
+
+    p_vci_ini.pktid  = 0;
+    p_vci_ini.srcid  = m_srcid;
+    p_vci_ini.cons   = false;
+    p_vci_ini.wrap   = false;
+    p_vci_ini.contig = true;
+    p_vci_ini.clen   = 0;
+    p_vci_ini.cfixed = false;
+
+    switch (r_vci_cmd_fsm) {
+
+    case CMD_IDLE:
+        p_vci_ini.cmdval  = false;
+        p_vci_ini.address = 0;
+        p_vci_ini.wdata   = 0;
+        p_vci_ini.be      = 0;
+        p_vci_ini.trdid   = 0;
+        p_vci_ini.plen    = 0;
+        p_vci_ini.cmd     = vci_param::CMD_NOP;
+        p_vci_ini.eop     = false;
+        break;
+
+    case CMD_ITLB_READ:     
+        p_vci_ini.cmdval  = true;
+        p_vci_ini.address = r_icache_paddr_save.read() & m_dcache_yzmask;
+        p_vci_ini.wdata   = 0;
+        p_vci_ini.be      = 0xF;
+        p_vci_ini.trdid   = 1; // via data cache cached read
+        p_vci_ini.plen    = m_dcache_words << 2;
+        p_vci_ini.cmd     = vci_param::CMD_READ;
+        p_vci_ini.eop     = true;
+        break;
+
+    case CMD_ITLB_ACC_LL:
+        p_vci_ini.cmdval  = true;
+        p_vci_ini.address = r_icache_paddr_save.read() & ~0x3;
+        p_vci_ini.wdata   = 0;
+        p_vci_ini.be      = 0xF;
+        p_vci_ini.trdid   = 0; // data cache uncached read
+        p_vci_ini.plen    = 4;
+        p_vci_ini.cmd     = vci_param::CMD_LOCKED_READ;
+        p_vci_ini.eop     = true;
+	break;
+
+    case CMD_ITLB_ACC_SC:
+        p_vci_ini.cmdval  = true;
+        p_vci_ini.address = r_icache_paddr_save.read() & ~0x3;
+        p_vci_ini.wdata   = r_icache_pte_update.read();
+        p_vci_ini.be      = 0xF;
+        p_vci_ini.trdid   = 0; // data cache uncached read
+        p_vci_ini.plen    = 4;
+        p_vci_ini.cmd     = vci_param::CMD_STORE_COND;
+        p_vci_ini.eop     = true;
+	break;	
+
+    case CMD_INS_MISS:
+        p_vci_ini.cmdval  = true;
+        p_vci_ini.address = r_icache_paddr_save.read() & m_icache_yzmask;
+        p_vci_ini.wdata   = 0;
+        p_vci_ini.be      = 0xF;
+        p_vci_ini.trdid   = 3; // ins cache cached read
+        p_vci_ini.plen    = m_icache_words << 2;
+        p_vci_ini.cmd     = vci_param::CMD_READ;
+        p_vci_ini.eop     = true;
+        break;
+
+    case CMD_INS_UNC:
+        p_vci_ini.cmdval  = true;
+        p_vci_ini.address = r_icache_paddr_save.read() & ~0x3;
+        p_vci_ini.wdata   = 0;
+        p_vci_ini.be      = 0xF;
+        p_vci_ini.trdid   = 2; // ins cache uncached read
+        p_vci_ini.plen    = 4;
+        p_vci_ini.cmd     = vci_param::CMD_READ;
+        p_vci_ini.eop     = true;
+        break;
+
+    case CMD_DTLB_READ:     
+        p_vci_ini.cmdval  = true;
+        p_vci_ini.address = r_dcache_tlb_paddr.read() & m_dcache_yzmask;
+        p_vci_ini.wdata   = 0;
+        p_vci_ini.be      = 0xF;
+        p_vci_ini.trdid   = 1; // via dcache cached read
+        p_vci_ini.plen    = m_dcache_words << 2;
+        p_vci_ini.cmd     = vci_param::CMD_READ;
+        p_vci_ini.eop     = true;
+        break;
+
+    case CMD_DTLB_ACC_LL:
+        p_vci_ini.cmdval  = true;
+        p_vci_ini.address = r_dcache_tlb_paddr.read() & ~0x3;
+        p_vci_ini.wdata   = 0;
+        p_vci_ini.be      = 0xF;
+        p_vci_ini.trdid   = 0; // data cache uncached read
+        p_vci_ini.plen    = 4;
+        p_vci_ini.cmd     = vci_param::CMD_LOCKED_READ;
+        p_vci_ini.eop     = true;
+	break;
+
+    case CMD_DTLB_ACC_SC:
+        p_vci_ini.cmdval  = true;
+        p_vci_ini.address = r_dcache_tlb_paddr.read() & ~0x3;
+        p_vci_ini.wdata   = r_dcache_pte_update.read();
+        p_vci_ini.be      = 0xF;
+        p_vci_ini.trdid   = 0; // data cache uncached read
+        p_vci_ini.plen    = 4;
+        p_vci_ini.cmd     = vci_param::CMD_STORE_COND;
+        p_vci_ini.eop     = true;
+	break;	
+
+    case CMD_DTLB_DIRTY_LL:
+        p_vci_ini.cmdval  = true;
+        p_vci_ini.address = r_dcache_tlb_paddr.read() & ~0x3;
+        p_vci_ini.wdata   = 0;
+        p_vci_ini.be      = 0xF;
+        p_vci_ini.trdid   = 0; // data cache uncached read
+        p_vci_ini.plen    = 4;
+        p_vci_ini.cmd     = vci_param::CMD_LOCKED_READ;
+        p_vci_ini.eop     = true;
+	break;
+
+    case CMD_DTLB_DIRTY_SC:
+        p_vci_ini.cmdval  = true;
+        p_vci_ini.address = r_dcache_tlb_paddr.read() & ~0x3;
+        p_vci_ini.wdata   = r_dcache_pte_update.read();
+        p_vci_ini.be      = 0xF;
+        p_vci_ini.trdid   = 0; // data cache uncached read
+        p_vci_ini.plen    = 4;
+        p_vci_ini.cmd     = vci_param::CMD_STORE_COND;
+        p_vci_ini.eop     = true;
+	break;	
+
+    case CMD_DATA_UNC:
+        p_vci_ini.cmdval  = true;
+        p_vci_ini.address = r_dcache_paddr_save.read() & ~0x3;
+        p_vci_ini.trdid   = 0; // data cache uncached read
+        p_vci_ini.plen    = 4;
+        p_vci_ini.eop     = true;
+        switch(r_dcache_type_save) {
+        case iss_t::DATA_READ:
+            p_vci_ini.wdata = 0;
+            p_vci_ini.be    = r_dcache_be_save.read();
+            p_vci_ini.cmd   = vci_param::CMD_READ;
+            break;
+        case iss_t::DATA_LL:
+            p_vci_ini.wdata = 0;
+            p_vci_ini.be    = 0xF;
+            p_vci_ini.cmd   = vci_param::CMD_LOCKED_READ;
+            break;
+        case iss_t::DATA_SC:
+            p_vci_ini.wdata = r_dcache_wdata_save.read();
+            p_vci_ini.be    = 0xF;
+            p_vci_ini.cmd   = vci_param::CMD_STORE_COND;
+            break;
+        default:
+            assert("this should not happen");
+        }
+        break;
+
+    case CMD_DATA_WRITE:
+        p_vci_ini.cmdval  = true;
+        p_vci_ini.address = r_wbuf.getAddress(r_vci_cmd_cpt);
+        p_vci_ini.wdata   = r_wbuf.getData(r_vci_cmd_cpt);
+        p_vci_ini.be      = r_wbuf.getBe(r_vci_cmd_cpt);
+        p_vci_ini.trdid   = 0; // data cache write
+        p_vci_ini.plen    = (r_vci_cmd_max - r_vci_cmd_min + 1)<<2;
+        p_vci_ini.cmd     = vci_param::CMD_WRITE;
+        p_vci_ini.eop     = (r_vci_cmd_cpt == r_vci_cmd_max);
+        break;
+
+    case CMD_DATA_MISS:
+        p_vci_ini.cmdval  = true;
+        p_vci_ini.address = r_dcache_paddr_save.read() & m_dcache_yzmask;
+        p_vci_ini.wdata   = 0;
+        p_vci_ini.be      = 0xF;
+        p_vci_ini.trdid   = 1; // data cache cached read
+        p_vci_ini.plen    = m_dcache_words << 2;
+        p_vci_ini.cmd     = vci_param::CMD_READ;
+        p_vci_ini.eop     = true;
+        break;
+
+    case CMD_INS_CLEANUP:
+    case CMD_DATA_CLEANUP:
+        p_vci_ini.cmdval = true;
+        if ( r_vci_cmd_fsm == CMD_INS_CLEANUP ) p_vci_ini.address = r_icache_cleanup_line.read() * (m_icache_words<<2);
+        else                                    p_vci_ini.address = r_dcache_cleanup_line.read() * (m_dcache_words<<2);
+        p_vci_ini.wdata  = 0;
+        p_vci_ini.be     = 0;
+        p_vci_ini.trdid  = 1; // cleanup for distinguish from a write
+        p_vci_ini.plen   = 4;
+        p_vci_ini.cmd    = vci_param::CMD_WRITE;
+        p_vci_ini.contig = false;
+        p_vci_ini.eop    = true;
+        break;
+
+    } // end switch r_vci_cmd_fsm
+
+    // VCI_TGT
+    switch ( r_vci_tgt_fsm.read() ) {
+
+    case TGT_IDLE:
+    case TGT_UPDT_WORD:
+    case TGT_UPDT_DATA:
+        p_vci_tgt.cmdack  = true;
+        p_vci_tgt.rspval  = false;
+        break;
+
+    case TGT_RSP_BROADCAST:
+        p_vci_tgt.cmdack  = false;
+        p_vci_tgt.rspval  = !r_tgt_icache_req.read() && !r_tgt_dcache_req.read() && ( r_tgt_icache_rsp | r_tgt_dcache_rsp );
+        p_vci_tgt.rsrcid  = r_tgt_srcid.read();
+        p_vci_tgt.rpktid  = r_tgt_pktid.read();
+        p_vci_tgt.rtrdid  = r_tgt_trdid.read();
+        p_vci_tgt.rdata   = 0;
+        p_vci_tgt.rerror  = 0;
+        p_vci_tgt.reop    = true;
+        break;
+
+    case TGT_RSP_DCACHE:
+        p_vci_tgt.cmdack  = false;
+        p_vci_tgt.rspval  = !r_tgt_dcache_req.read();
+        p_vci_tgt.rsrcid  = r_tgt_srcid.read();
+        p_vci_tgt.rpktid  = r_tgt_pktid.read();
+        p_vci_tgt.rtrdid  = r_tgt_trdid.read();
+        p_vci_tgt.rdata   = 0;
+        p_vci_tgt.rerror  = 0;
+        p_vci_tgt.reop    = true;
+        break;
+
+    case TGT_REQ_BROADCAST:
+    case TGT_REQ_DCACHE:
+        p_vci_tgt.cmdack  = false;
+        p_vci_tgt.rspval  = false;
+        break;
+
+    } // end switch TGT_FSM
+
+#ifdef SOCLIB_MODULE_DEBUG 
+   std::cout << name() 
+      	     << "Moore:" << std::hex
+      	     << " p_vci_ini.cmdval: " << p_vci_ini.cmdval
+      	     << " p_vci_ini.address: " << p_vci_ini.address
+      	     << " p_vci_ini.wdata: " << p_vci_ini.wdata
+      	     << " p_vci_ini.cmd: " << p_vci_ini.cmd
+      	     << " p_vci_ini.eop: " << p_vci_ini.eop
+      	     << std::endl;
+#endif
+}
+
+}}
+
+// Local Variables:
+// tab-width: 4
+// c-basic-offset: 4
+// c-file-offsets:((innamespace . 0)(inline-open . 0))
+// indent-tabs-mode: nil
+// End:
+
+// vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4
+
+
+
+
+
+
+
+
Index: branches/v4/modules/vci_cc_vcache_wrapper2_multi/caba/metadata/vci_cc_vcache_wrapper2_multi.sd
===================================================================
--- branches/v4/modules/vci_cc_vcache_wrapper2_multi/caba/metadata/vci_cc_vcache_wrapper2_multi.sd	(revision 371)
+++ branches/v4/modules/vci_cc_vcache_wrapper2_multi/caba/metadata/vci_cc_vcache_wrapper2_multi.sd	(revision 371)
@@ -0,0 +1,69 @@
+
+# -*- python -*-
+
+__id__ = "$Id$"
+__version__ = "$Revision$"
+
+Module('caba:vci_cc_vcache_wrapper2_multi',
+	classname = 'soclib::caba::VciCcVCacheWrapper2Multi',
+	   tmpl_parameters = [
+	parameter.Module('vci_param', default = 'caba:vci_param'),
+	parameter.Module('iss_t'),
+	],
+	header_files = [
+	'../source/include/vci_cc_vcache_wrapper2_multi.h',
+	],
+	implementation_files = [
+	'../source/src/vci_cc_vcache_wrapper2_multi.cpp',
+	],
+	uses = [
+	Uses('caba:base_module'),
+	Uses('caba:multi_write_buffer'),
+	Uses('caba:generic_tlb', addr_t = parameter.StringExt('sc_dt::sc_uint<%d> ', parameter.Reference('addr_size'))),
+	Uses('caba:generic_cache', addr_t = parameter.StringExt('sc_dt::sc_uint<%d> ', parameter.Reference('addr_size'))),
+	Uses('common:address_masking_table', data_t = parameter.StringExt('sc_dt::sc_uint<%d> ', parameter.Reference('addr_size'))),
+	Uses('common:iss2'),
+	Uses('common:mapping_table'),
+	],
+	ports = [
+	Port('caba:vci_initiator', 'p_vci_ini_rw'),
+	Port('caba:vci_initiator', 'p_vci_ini_c'),
+	Port('caba:vci_target', 'p_vci_tgt'),
+	Port('caba:bit_in','p_irq', parameter.Constant('n_irq')),
+	Port('caba:bit_in', 'p_resetn', auto = 'resetn'),
+	Port('caba:clock_in', 'p_clk', auto = 'clock'),
+	],
+	instance_parameters = [
+	parameter.Int('proc_id'),
+	parameter.Module('mt', 'common:mapping_table'),
+	parameter.Module('mc', 'common:mapping_table'),
+	parameter.IntTab('initiator_rw_index'),
+	parameter.IntTab('initiator_c_index'),
+	parameter.IntTab('target_index'),
+    	parameter.Int('itlb_ways'),
+    	parameter.Int('itlb_sets'),
+    	parameter.Int('dtlb_ways'),
+    	parameter.Int('dtlb_sets'),
+    	parameter.Int('icache_ways'),
+    	parameter.Int('icache_sets'),
+    	parameter.Int('icache_words'),
+    	parameter.Int('dcache_ways'),
+    	parameter.Int('dcache_sets'),
+    	parameter.Int('dcache_words'),
+    	parameter.Int('write_buf_nwords'),
+    	parameter.Int('write_buf_nlines'),
+	],
+	   extensions = [
+	'dsx:get_ident='
+        'initiator_rw_index:p_vci_ini_rw:mt,'
+        'initiator_c_index:p_vci_ini_c:mc,'
+        'target_index:p_vci_tgt:mc',
+	'dsx:cpu=wrapper:iss_t',
+	'dsx:addressable=target_index',
+    'dsx:on_segment=mc:add_index:initiator_rw_index',
+	'dsx:mapping_type=processor:proc_id',
+   ],
+)
+
+
+
Index: branches/v4/modules/vci_cc_vcache_wrapper2_multi/caba/source/include/vci_cc_vcache_wrapper2_multi.h
===================================================================
--- branches/v4/modules/vci_cc_vcache_wrapper2_multi/caba/source/include/vci_cc_vcache_wrapper2_multi.h	(revision 371)
+++ branches/v4/modules/vci_cc_vcache_wrapper2_multi/caba/source/include/vci_cc_vcache_wrapper2_multi.h	(revision 371)
@@ -0,0 +1,585 @@
+/* -*- c++ -*-
+ * File : vci_cc_vcache_wrapper2_multi.h
+ * Copyright (c) UPMC, Lip6, SoC
+ * Authors : Alain GREINER, Yang GAO
+ *
+ * SOCLIB_LGPL_HEADER_BEGIN
+ * 
+ * This file is part of SoCLib, GNU LGPLv2.1.
+ * 
+ * SoCLib is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU Lesser General Public License as published
+ * by the Free Software Foundation; version 2.1 of the License.
+ * 
+ * SoCLib is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * Lesser General Public License for more details.
+ * 
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with SoCLib; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301 USA
+ * 
+ * SOCLIB_LGPL_HEADER_END
+ */
+ 
+#ifndef SOCLIB_CABA_VCI_CC_VCACHE_WRAPPER2_MULTI_H
+#define SOCLIB_CABA_VCI_CC_VCACHE_WRAPPER2_MULTI_H
+
+#include <inttypes.h>
+#include <systemc>
+#include "caba_base_module.h"
+#include "multi_write_buffer.h"
+#include "generic_cache.h"
+#include "vci_initiator.h"
+#include "vci_target.h"
+#include "mapping_table.h"
+#include "generic_tlb.h"
+#include "static_assert.h"
+
+namespace soclib {
+namespace caba {
+
+using namespace sc_core;
+
+////////////////////////////////////////////
+template<typename vci_param, typename iss_t>
+class VciCcVCacheWrapper2Multi
+////////////////////////////////////////////
+    : public soclib::caba::BaseModule
+{
+    typedef uint32_t vaddr_t;
+    typedef uint32_t data_t;
+    typedef uint32_t tag_t;
+    typedef uint32_t type_t;
+    typedef typename iss_t::DataOperationType data_op_t;
+
+    typedef typename vci_param::addr_t  paddr_t;
+    typedef typename vci_param::be_t    vci_be_t;
+	typedef typename vci_param::srcid_t vci_srcid_t;
+	typedef typename vci_param::trdid_t vci_trdid_t;
+	typedef typename vci_param::pktid_t vci_pktid_t;
+	typedef typename vci_param::plen_t  vci_plen_t;
+
+    enum icache_fsm_state_e {  
+        ICACHE_IDLE,                // 00
+        ICACHE_BIS,                 // 01
+        ICACHE_TLB1_READ,           // 02
+        ICACHE_TLB1_WRITE,          // 03
+        ICACHE_TLB1_UPDT,           // 04
+        ICACHE_TLB2_READ,           // 05
+        ICACHE_TLB2_WRITE,          // 06
+        ICACHE_TLB2_UPDT,           // 07
+        ICACHE_SW_FLUSH,            // 08
+        ICACHE_TLB_FLUSH,           // 09
+        ICACHE_CACHE_FLUSH,         // 0a
+        ICACHE_TLB_INVAL,           // 0b
+        ICACHE_CACHE_INVAL,         // 0c
+        ICACHE_CACHE_INVAL_PA,	    // 0d
+        ICACHE_MISS_WAIT,           // 0e
+        ICACHE_UNC_WAIT,            // 0f
+        ICACHE_MISS_UPDT,           // 10
+        ICACHE_ERROR,               // 11
+        ICACHE_CC_INVAL,            // 12
+        ICACHE_TLB_CC_INVAL,        // 13
+    };
+
+    enum dcache_fsm_state_e {  
+        DCACHE_IDLE,                // 00
+        DCACHE_BIS,                 // 01
+        DCACHE_DTLB1_READ_CACHE,    // 02
+        DCACHE_TLB1_LL_WAIT,        // 03
+        DCACHE_TLB1_SC_WAIT,        // 04
+        DCACHE_TLB1_READ,           // 05
+        DCACHE_TLB1_READ_UPDT,      // 06
+        DCACHE_TLB1_UPDT,           // 07
+        DCACHE_DTLB2_READ_CACHE,    // 08
+        DCACHE_TLB2_LL_WAIT,        // 09
+        DCACHE_TLB2_SC_WAIT,        // 0a
+        DCACHE_TLB2_READ,           // 0b
+        DCACHE_TLB2_READ_UPDT,      // 0c
+        DCACHE_TLB2_UPDT,           // 0d
+        DCACHE_CTXT_SWITCH,         // 0e
+        DCACHE_ICACHE_FLUSH,        // 0f
+        DCACHE_DCACHE_FLUSH,        // 10
+        DCACHE_ITLB_INVAL,          // 11
+        DCACHE_DTLB_INVAL,          // 12
+        DCACHE_ICACHE_INVAL,        // 13
+        DCACHE_DCACHE_INVAL,        // 14
+        DCACHE_ICACHE_INVAL_PA,     // 29
+        DCACHE_DCACHE_INVAL_PA,     // 2a
+        DCACHE_DCACHE_SYNC,         // 15
+        DCACHE_LL_DIRTY_WAIT,       // 16
+        DCACHE_SC_DIRTY_WAIT,       // 17
+        DCACHE_WRITE_UPDT,          // 18
+        DCACHE_WRITE_DIRTY,         // 19
+        DCACHE_WRITE_REQ,           // 1a
+        DCACHE_MISS_WAIT,           // 1b
+        DCACHE_MISS_UPDT,           // 1c
+        DCACHE_UNC_WAIT,            // 1d
+        DCACHE_ERROR,               // 1e
+        DCACHE_ITLB_READ,           // 1f
+        DCACHE_ITLB_UPDT,           // 20
+        DCACHE_ITLB_LL_WAIT,        // 21
+        DCACHE_ITLB_SC_WAIT,        // 22
+        DCACHE_CC_CHECK,            // 23
+        DCACHE_CC_INVAL,            // 24
+        DCACHE_CC_UPDT,             // 25
+        DCACHE_CC_NOP,              // 26
+        DCACHE_TLB_CC_INVAL,        // 27
+        DCACHE_ITLB_CLEANUP,        // 28
+    };
+
+    enum cmd_fsm_state_e {      
+        CMD_IDLE,                   // 00
+        CMD_ITLB_READ,              // 01
+        CMD_ITLB_ACC_LL,            // 02
+        CMD_ITLB_ACC_SC,            // 03
+        CMD_INS_MISS,               // 04
+        CMD_INS_UNC,                // 05
+        CMD_DTLB_READ,              // 06
+        CMD_DTLB_ACC_LL,            // 07
+        CMD_DTLB_ACC_SC,            // 08
+        CMD_DTLB_DIRTY_LL,          // 09
+        CMD_DTLB_DIRTY_SC,          // 0a
+        CMD_DATA_UNC,               // 0b
+        CMD_DATA_MISS,              // 0c
+        CMD_DATA_WRITE,             // 0d
+    };
+
+    enum rsp_fsm_state_e {       
+        RSP_IDLE,                   // 00
+        RSP_ITLB_READ,              // 01
+        RSP_ITLB_ACC_LL,            // 02
+        RSP_ITLB_ACC_SC,            // 03
+        RSP_INS_MISS,               // 04
+        RSP_INS_UNC,                // 05
+        RSP_DTLB_READ,              // 06
+        RSP_DTLB_ACC_LL,            // 07
+        RSP_DTLB_ACC_SC,            // 08
+        RSP_DTLB_DIRTY_LL,          // 09
+        RSP_DTLB_DIRTY_SC,          // 0a
+        RSP_DATA_MISS,              // 0b
+        RSP_DATA_UNC,               // 0c
+        RSP_DATA_WRITE,             // 0d
+    };
+
+    enum tgt_fsm_state_e {  
+        TGT_IDLE,                   // 00
+        TGT_UPDT_WORD,              // 01
+        TGT_UPDT_DATA,              // 02
+        TGT_REQ_BROADCAST,          // 03
+        TGT_REQ_ICACHE,             // 04
+        TGT_REQ_DCACHE,             // 05
+        TGT_RSP_BROADCAST,          // 06
+        TGT_RSP_ICACHE,             // 07
+        TGT_RSP_DCACHE,             // 08
+    };
+
+    enum inval_itlb_fsm_state_e {
+        INVAL_ITLB_IDLE,            // 00
+        INVAL_ITLB_CHECK,           // 01
+        INVAL_ITLB_INVAL,           // 02
+        INVAL_ITLB_CLEAR,           // 03
+    };
+
+    enum inval_dtlb_fsm_state_e {
+        INVAL_DTLB_IDLE,            // 00
+        INVAL_DTLB_CHECK,           // 01
+        INVAL_DTLB_INVAL,           // 02
+        INVAL_DTLB_CLEAR,           // 03
+    };
+
+    enum cleanup_fsm_state_e {
+        CLEANUP_CMD,                // 00
+        CLEANUP_ICACHE_RSP,         // 01
+        CLEANUP_DCACHE_RSP,         // 02
+    };
+
+    // TLB Mode ITLB / DTLB / ICACHE / DCACHE
+    enum {          
+        ALL_DEACTIVE = 0x0000,   // TLBs disactive caches disactive
+        INS_TLB_MASK    = 0x8,
+        DATA_TLB_MASK   = 0x4,
+        INS_CACHE_MASK  = 0x2,
+        DATA_CACHE_MASK = 0x1,
+    };
+
+    // Error Type
+    enum mmu_error_type_e {
+        MMU_NONE                      = 0x0000, // None
+        MMU_WRITE_PT1_UNMAPPED 	      = 0x0001, // Write access of Page fault on Page Table 1          (non fatal error)
+        MMU_WRITE_PT2_UNMAPPED 	      = 0x0002, // Write access of Page fault on Page Table 2          (non fatal error)
+        MMU_WRITE_PRIVILEGE_VIOLATION = 0x0004, // Write access of Protected access in user mode       (user error)
+        MMU_WRITE_ACCES_VIOLATION 	  = 0x0008, // Write access of write access to a non writable page (user error)
+        MMU_WRITE_UNDEFINED_XTN 	  = 0x0020, // Write access of undefined external access address   (user error)
+        MMU_WRITE_PT1_ILLEGAL_ACCESS  = 0x0040, // Write access of Bus Error accessing Table 1         (kernel error)
+        MMU_WRITE_PT2_ILLEGAL_ACCESS  = 0x0080, // Write access of Bus Error accessing Table 2         (kernel error)
+        MMU_WRITE_DATA_ILLEGAL_ACCESS = 0x0100, // Write access of Bus Error in cache access           (kernel error)
+        MMU_READ_PT1_UNMAPPED 	      = 0x1001, // Read access of Page fault on Page Table 1  	       (non fatal error)
+        MMU_READ_PT2_UNMAPPED 	      = 0x1002, // Read access of Page fault on Page Table 2  	       (non fatal error)
+        MMU_READ_PRIVILEGE_VIOLATION  = 0x1004, // Read access of Protected access in user mode 	   (user error)
+        MMU_READ_EXEC_VIOLATION 	  = 0x1010, // Exec access to a non exec page                      (user error)
+        MMU_READ_UNDEFINED_XTN 	      = 0x1020, // Read access of Undefined external access address    (user error)
+        MMU_READ_PT1_ILLEGAL_ACCESS   = 0x1040, // Read access of Bus Error in Table1 access           (kernel error)
+        MMU_READ_PT2_ILLEGAL_ACCESS   = 0x1080, // Read access of Bus Error in Table2 access 	       (kernel error)
+        MMU_READ_DATA_ILLEGAL_ACCESS  = 0x1100, // Read access of Bus Error in cache access 	       (kernel error)
+    };
+
+    enum transaction_type_e {
+        TYPE_DATA_UNC    = 0x0,
+        TYPE_DATA_MISS   = 0x1,
+        TYPE_INS_UNC     = 0x2,
+        TYPE_INS_MISS    = 0x3,
+        TYPE_INS_LL_ACC  = 0x4,
+        TYPE_INS_TLB     = 0x5,
+        TYPE_INS_SC_ACC  = 0x8,
+        TYPE_DATA_TLB    = 0x9,
+        TYPE_DATA_LL_ACC = 0xc,
+        TYPE_DATA_SC_ACC = 0x10,
+        TYPE_DATA_LL_D   = 0x14,
+        TYPE_DATA_SC_D   = 0x18,
+    };
+
+public:
+    sc_in<bool>                             p_clk;
+    sc_in<bool>                             p_resetn;
+    sc_in<bool>                             p_irq[iss_t::n_irq];
+    soclib::caba::VciInitiator<vci_param>   p_vci_ini_rw;
+    soclib::caba::VciInitiator<vci_param>   p_vci_ini_c;
+    soclib::caba::VciTarget<vci_param>      p_vci_tgt;
+
+private:
+    // STRUCTURAL PARAMETERS
+    soclib::common::AddressDecodingTable<uint32_t, bool>    m_cacheability_table;
+    const soclib::common::Segment                           m_segment;
+    iss_t                                                   m_iss;   
+    const vci_srcid_t                                       m_srcid_rw;
+    const vci_srcid_t                                       m_srcid_c;
+
+    const size_t  m_itlb_ways;
+    const size_t  m_itlb_sets;
+
+    const size_t  m_dtlb_ways;
+    const size_t  m_dtlb_sets;
+
+    const size_t  m_icache_ways;
+    const size_t  m_icache_sets;
+    const size_t  m_icache_yzmask;
+    const size_t  m_icache_words;
+
+    const size_t  m_dcache_ways;
+    const size_t  m_dcache_sets;
+    const size_t  m_dcache_yzmask;
+    const size_t  m_dcache_words;
+
+    //const size_t  m_write_buf_size;
+    const size_t  m_wbuf_nlines;  
+    const size_t  m_paddr_nbits;  
+
+    // instruction and data vcache tlb instances 
+    soclib::caba::GenericCcTlb<paddr_t>    icache_tlb;
+    soclib::caba::GenericCcTlb<paddr_t>    dcache_tlb;
+
+    sc_signal<vaddr_t>      r_mmu_ptpr;             // page table pointer register
+    sc_signal<int>          r_mmu_mode;             // tlb mode register
+    sc_signal<int>          r_mmu_params;           // mmu parameters register
+    sc_signal<int>          r_mmu_release;          // mmu release register
+    sc_signal<int>          r_mmu_word_lo;          // mmu misc data low
+    sc_signal<int>          r_mmu_word_hi;          // mmu mmu misc data hight
+
+    // DCACHE FSM REGISTERS
+    sc_signal<int>          r_dcache_fsm;               // state register
+    sc_signal<paddr_t>      r_dcache_paddr_save;        // physical address
+    sc_signal<data_t>       r_dcache_wdata_save;        // write data
+    sc_signal<data_t>       r_dcache_rdata_save;        // read data
+    sc_signal<type_t>       r_dcache_type_save;         // access type
+    sc_signal<vci_be_t>     r_dcache_be_save;           // byte enable
+    sc_signal<bool>         r_dcache_cached_save;       // used by the write buffer
+    sc_signal<paddr_t>      r_dcache_tlb_paddr;         // physical address of tlb miss
+    sc_signal<bool>         r_dcache_dirty_save;        // used for TLB dirty bit update
+    sc_signal<size_t>       r_dcache_tlb_set_save;      // used for TLB dirty bit update
+    sc_signal<size_t>       r_dcache_tlb_way_save;      // used for TLB dirty bit update
+    sc_signal<vaddr_t>      r_dcache_id1_save;          // used by the PT1 bypass
+    sc_signal<paddr_t>      r_dcache_ptba_save;         // used by the PT1 bypass
+    sc_signal<bool>         r_dcache_ptba_ok;           // used by the PT1 bypass
+    sc_signal<data_t>       r_dcache_pte_update;        // used for page table update
+    sc_signal<data_t>       r_dcache_ppn_update;        // used for physical page number update 
+    sc_signal<tag_t>        r_dcache_ppn_save;          // used for speculative cache access
+    sc_signal<tag_t>        r_dcache_vpn_save;          // used for speculative cache access
+    sc_signal<bool>         r_dtlb_translation_valid;   // used for speculative address
+    sc_signal<bool>         r_dcache_buf_unc_valid;     // used for uncached read
+    sc_signal<bool>         r_dcache_hit_p_save;        // used to save hit_p in case BIS
+
+    sc_signal<data_t>       r_dcache_error_type;        // software visible register
+    sc_signal<vaddr_t>      r_dcache_bad_vaddr;         // software visible register 
+
+    sc_signal<bool>         r_dcache_miss_req;          // used for cached read miss
+    sc_signal<bool>         r_dcache_unc_req;           // used for uncached read miss
+    sc_signal<bool>         r_dcache_write_req;         // used for write 
+    sc_signal<bool>         r_dcache_tlb_read_req;      // used for tlb ptba or pte read
+
+    sc_signal<bool>         r_dcache_llsc_reserved;     // used for check address reserved
+    sc_signal<paddr_t>      r_dcache_llsc_addr_save;    // used for save llsc address
+ 
+    sc_signal<bool>         r_dcache_tlb_ll_acc_req;    // used for tlb access bit update
+    sc_signal<bool>         r_dcache_tlb_sc_acc_req;    // used for tlb access bit update
+    sc_signal<bool>         r_dcache_tlb_ll_dirty_req;  // used for tlb dirty bit update 
+    sc_signal<bool>         r_dcache_tlb_sc_dirty_req;  // used for tlb dirty bit update 
+    sc_signal<bool>         r_dcache_tlb_ptba_read;     // used for tlb ptba read when write dirty bit 
+    sc_signal<bool>         r_dcache_xtn_req;           // used for xtn write for ICACHE
+
+    bool                    *r_dcache_in_itlb;          // indicates some words of dcache line in ins TLB 
+    bool                    *r_dcache_in_dtlb;          // indicates some words of dcache line in data TLB 
+
+    // coherence registers
+    sc_signal<int>          r_dcache_fsm_save;          // state save register
+    sc_signal<size_t>       r_dcache_way;
+    sc_signal<size_t>       r_dcache_set;
+    sc_signal<bool>         r_dcache_cleanup_req;       // data cleanup request
+    sc_signal<paddr_t>      r_dcache_cleanup_line;      // data cleanup NLINE
+    sc_signal<bool>         r_dcache_inval_rsp;         // data cache invalidate
+
+    // ICACHE FSM REGISTERS
+    sc_signal<int>          r_icache_fsm;               // state register
+    sc_signal<paddr_t>      r_icache_paddr_save;        // physical address
+    sc_signal<vaddr_t>      r_icache_id1_save;          // used by the PT1 bypass
+    sc_signal<paddr_t>      r_icache_ptba_save;         // used by the PT1 bypass
+    sc_signal<bool>         r_icache_ptba_ok;           // used by the PT1 bypass
+    sc_signal<data_t>       r_icache_pte_update;        // used for page table update
+    sc_signal<tag_t>        r_icache_ppn_save;          // used for speculative cache access
+    sc_signal<tag_t>        r_icache_vpn_save;          // used for speculative cache access
+    sc_signal<bool>         r_itlb_translation_valid;   // used for speculative physical address
+    sc_signal<bool>         r_icache_buf_unc_valid;     // used for uncached read
+
+    sc_signal<data_t>       r_icache_error_type;        // software visible registers
+    sc_signal<vaddr_t>      r_icache_bad_vaddr;         // software visible registers
+
+    sc_signal<bool>         r_icache_miss_req;          // used for cached read miss
+    sc_signal<bool>         r_icache_unc_req;           // used for uncached read miss
+    sc_signal<bool>         r_dcache_itlb_read_req;     // used for tlb ptba or pte read 
+
+    sc_signal<bool>         r_dcache_itlb_ll_acc_req;   // used for tlb access bit update
+    sc_signal<bool>         r_dcache_itlb_sc_acc_req;   // used for tlb access bit update
+
+    sc_signal<bool>	        r_itlb_read_dcache_req;     // used for instruction tlb miss, request in data cache
+    sc_signal<bool>	        r_itlb_k_read_dcache;       // used for instruction tlb miss, request in data cache
+    sc_signal<bool>	        r_itlb_acc_dcache_req;          // used for itlb update access bit via dcache
+    sc_signal<bool>	        r_dcache_rsp_itlb_error;        // used for data cache rsp error when itlb miss
+    sc_signal<data_t>	    r_dcache_rsp_itlb_miss;	        // used for dcache rsp data when itlb miss
+    sc_signal<data_t>	    r_dcache_rsp_itlb_ppn;	        // used for dcache rsp ppn when itlb miss
+    sc_signal<vaddr_t>      r_icache_vaddr_req;                 // virtual address requested by the CPU
+
+    // coherence registers
+    sc_signal<int>          r_icache_fsm_save;          // state save register
+    sc_signal<size_t>       r_icache_way;
+    sc_signal<size_t>       r_icache_set;
+    sc_signal<bool>         r_icache_cleanup_req;       // ins cleanup request
+    sc_signal<paddr_t>      r_icache_cleanup_line;      // ins cleanup NLINE
+    sc_signal<bool>         r_icache_inval_rsp;         // ins cache invalidate
+
+    // VCI_CMD FSM REGISTERS
+    sc_signal<int>          r_vci_cmd_fsm;
+    sc_signal<size_t>       r_vci_cmd_min;       
+    sc_signal<size_t>       r_vci_cmd_max;       
+    sc_signal<size_t>       r_vci_cmd_cpt;     
+
+    // VCI_RSP FSM REGISTERS
+    sc_signal<int>          r_vci_rsp_fsm;
+    sc_signal<size_t>       r_vci_rsp_cpt;
+    sc_signal<bool>         r_vci_rsp_ins_error;
+    sc_signal<bool>         r_vci_rsp_data_error;
+    sc_signal<bool>         r_vci_rsp_ins_ok;
+    sc_signal<bool>         r_vci_rsp_data_ok;
+    sc_signal<bool>         r_dcache_tlb_sc_fail;
+
+    data_t                  *r_icache_miss_buf;    
+    data_t                  *r_dcache_miss_buf;  
+
+    // VCI_TGT FSM REGISTERS
+    data_t                  *r_tgt_buf;
+    bool                    *r_tgt_val;
+
+    sc_signal<int>          r_vci_tgt_fsm;
+    sc_signal<paddr_t>      r_tgt_addr;
+    sc_signal<size_t>       r_tgt_word;
+    sc_signal<bool>         r_tgt_update;
+    sc_signal<vci_srcid_t>  r_tgt_srcid;
+    sc_signal<vci_pktid_t>  r_tgt_pktid;
+    sc_signal<vci_trdid_t>  r_tgt_trdid;
+    sc_signal<vci_plen_t>   r_tgt_plen;
+    sc_signal<bool>         r_tgt_req;
+    sc_signal<bool>         r_tgt_icache_req;
+    sc_signal<bool>         r_tgt_dcache_req;
+    sc_signal<bool>         r_tgt_icache_rsp;
+    sc_signal<bool>         r_tgt_dcache_rsp;
+
+    // INVAL CHECK FSM
+    sc_signal<int>          r_inval_itlb_fsm;          
+    sc_signal<bool>         r_dcache_itlb_inval_req;
+    sc_signal<paddr_t>      r_dcache_itlb_inval_line;
+    sc_signal<bool>         r_itlb_cc_check_end;
+    sc_signal<size_t>       r_ccinval_itlb_way; 
+    sc_signal<size_t>       r_ccinval_itlb_set; 
+    sc_signal<bool>         r_icache_inval_tlb_rsp;
+    sc_signal<paddr_t>      r_icache_tlb_nline;
+
+    sc_signal<int>          r_inval_dtlb_fsm;          
+    sc_signal<bool>         r_dcache_dtlb_inval_req;
+    sc_signal<paddr_t>      r_dcache_dtlb_inval_line;
+    sc_signal<bool>         r_dtlb_cc_check_end;
+    sc_signal<size_t>       r_ccinval_dtlb_way; 
+    sc_signal<size_t>       r_ccinval_dtlb_set; 
+    sc_signal<bool>         r_dcache_inval_tlb_rsp;
+    sc_signal<paddr_t>      r_dcache_tlb_nline;
+
+    sc_signal<bool>         r_dcache_itlb_cleanup_req;
+    sc_signal<paddr_t>      r_dcache_itlb_cleanup_line;
+
+    sc_signal<bool>         r_dcache_dtlb_cleanup_req;
+    sc_signal<paddr_t>      r_dcache_dtlb_cleanup_line;
+
+    sc_signal<bool>         r_itlb_inval_req;
+    sc_signal<bool>         r_dcache_cc_check;
+    sc_signal<int>          r_cleanup_fsm; 
+
+    MultiWriteBuffer<paddr_t>   r_wbuf;
+    GenericCache<paddr_t>       r_icache;
+    GenericCache<paddr_t>       r_dcache;
+
+    // Activity counters
+    uint32_t m_cpt_dcache_data_read;        // DCACHE DATA READ
+    uint32_t m_cpt_dcache_data_write;       // DCACHE DATA WRITE
+    uint32_t m_cpt_dcache_dir_read;         // DCACHE DIR READ
+    uint32_t m_cpt_dcache_dir_write;        // DCACHE DIR WRITE
+
+    uint32_t m_cpt_icache_data_read;        // ICACHE DATA READ
+    uint32_t m_cpt_icache_data_write;       // ICACHE DATA WRITE
+    uint32_t m_cpt_icache_dir_read;         // ICACHE DIR READ
+    uint32_t m_cpt_icache_dir_write;        // ICACHE DIR WRITE
+
+    uint32_t m_cpt_frz_cycles;	            // number of cycles where the cpu is frozen
+    uint32_t m_cpt_total_cycles;	        // total number of cycles 
+
+    // Cache activity counters
+    uint32_t m_cpt_read;                    // total number of read data
+    uint32_t m_cpt_write;                   // total number of write data
+    uint32_t m_cpt_data_miss;               // number of read miss
+    uint32_t m_cpt_ins_miss;                // number of instruction miss
+    uint32_t m_cpt_unc_read;                // number of read uncached
+    uint32_t m_cpt_write_cached;            // number of cached write
+    uint32_t m_cpt_ins_read;                // number of instruction read
+
+    uint32_t m_cost_write_frz;              // number of frozen cycles related to write buffer         
+    uint32_t m_cost_data_miss_frz;          // number of frozen cycles related to data miss
+    uint32_t m_cost_unc_read_frz;           // number of frozen cycles related to uncached read
+    uint32_t m_cost_ins_miss_frz;           // number of frozen cycles related to ins miss
+
+    uint32_t m_cpt_imiss_transaction;       // number of VCI instruction miss transactions
+    uint32_t m_cpt_dmiss_transaction;       // number of VCI data miss transactions
+    uint32_t m_cpt_unc_transaction;         // number of VCI uncached read transactions
+    uint32_t m_cpt_write_transaction;       // number of VCI write transactions
+
+    uint32_t m_cost_imiss_transaction;      // cumulated duration for VCI IMISS transactions
+    uint32_t m_cost_dmiss_transaction;      // cumulated duration for VCI DMISS transactions
+    uint32_t m_cost_unc_transaction;        // cumulated duration for VCI UNC transactions
+    uint32_t m_cost_write_transaction;      // cumulated duration for VCI WRITE transactions
+    uint32_t m_length_write_transaction;    // cumulated length for VCI WRITE transactions
+
+    // TLB activity counters
+    uint32_t m_cpt_ins_tlb_read;            // number of instruction tlb read
+    uint32_t m_cpt_ins_tlb_miss;            // number of instruction tlb miss
+    uint32_t m_cpt_ins_tlb_write_et;        // number of instruction tlb write ET
+
+    uint32_t m_cpt_data_tlb_read;           // number of data tlb read
+    uint32_t m_cpt_data_tlb_miss;           // number of data tlb miss
+    uint32_t m_cpt_data_tlb_write_et;       // number of data tlb write ET
+    uint32_t m_cpt_data_tlb_write_dirty;    // number of data tlb write dirty
+    
+    uint32_t m_cost_ins_tlb_miss_frz;       // number of frozen cycles related to instruction tlb miss
+    uint32_t m_cost_data_tlb_miss_frz;      // number of frozen cycles related to data tlb miss
+
+    uint32_t m_cost_ins_waste_wait_frz;     // number of frozen cycles related to ins wait coherence operate 
+    uint32_t m_cost_ins_tlb_sw_frz;         // number of frozen cycles related to ins context switch
+    uint32_t m_cost_ins_cache_flush_frz;    // number of frozen cycles related to ins cache flush 
+
+    uint32_t m_cpt_ins_tlb_cleanup;         // number of ins tlb cleanup 
+    uint32_t m_cost_data_waste_wait_frz;    // number of frozen cycles related to data wait coherence operate
+    uint32_t m_cost_data_tlb_sw_frz;        // number of frozen cycles related to data context switch
+    uint32_t m_cost_data_cache_flush_frz;   // number of frozen cycles related to data cache flush
+
+    uint32_t m_cpt_itlbmiss_transaction;    // number of itlb miss transactions
+    uint32_t m_cpt_itlb_write_transaction;  // number of itlb write ET transactions
+    uint32_t m_cpt_dtlbmiss_transaction;    // number of dtlb miss transactions
+    uint32_t m_cpt_dtlb_write_transaction;  // number of dtlb write ET and dirty transactions
+
+    uint32_t m_cost_itlbmiss_transaction;   // cumulated duration for VCI instruction TLB miss transactions
+    uint32_t m_cost_itlb_write_transaction; // cumulated duration for VCI instruction TLB write ET transactions
+    uint32_t m_cost_dtlbmiss_transaction;   // cumulated duration for VCI data TLB miss transactions
+    uint32_t m_cost_dtlb_write_transaction; // cumulated duration for VCI data TLB write transactions
+
+    uint32_t m_cpt_cc_update;               // number of coherence update packets 
+    uint32_t m_cpt_cc_inval;                // number of coherence inval packets
+    uint32_t m_cpt_cc_broadcast;            // number of coherence broadcast packets
+
+    uint32_t m_cost_ins_tlb_inval_frz;      // number of frozen cycles related to checking ins tlb invalidate
+    uint32_t m_cpt_ins_tlb_inval;           // number of ins tlb invalidate
+
+    uint32_t m_cost_data_tlb_inval_frz;     // number of frozen cycles related to checking data tlb invalidate    
+    uint32_t m_cpt_data_tlb_inval;          // number of data tlb invalidate
+
+protected:
+    SC_HAS_PROCESS(VciCcVCacheWrapper2Multi);
+
+public:
+    VciCcVCacheWrapper2Multi(
+        sc_module_name insname,
+        int proc_id,
+        const soclib::common::MappingTable &mtp,
+        const soclib::common::MappingTable &mtc,
+        const soclib::common::IntTab &initiator_index_rw,
+        const soclib::common::IntTab &initiator_index_c,
+        const soclib::common::IntTab &target_index,
+        size_t itlb_ways,
+        size_t itlb_sets,
+        size_t dtlb_ways,
+        size_t dtlb_sets,
+        size_t icache_ways,
+        size_t icache_sets,
+        size_t icache_words,
+        size_t dcache_ways,
+        size_t dcache_sets,
+        size_t dcache_words,
+        size_t wbuf_nwords,
+        size_t wbuf_nlines );
+
+    ~VciCcVCacheWrapper2Multi();
+
+    void print_cpi();
+    void print_stats();
+
+private:
+    void transition();
+    void genMoore();
+
+    soclib_static_assert((int)iss_t::SC_ATOMIC == (int)vci_param::STORE_COND_ATOMIC);
+    soclib_static_assert((int)iss_t::SC_NOT_ATOMIC == (int)vci_param::STORE_COND_NOT_ATOMIC);
+};
+
+}}
+
+#endif /* SOCLIB_CABA_VCI_CC_VCACHE_WRAPPER2_MULTI_H */
+
+// Local Variables:
+// tab-width: 4
+// c-basic-offset: 4
+// c-file-offsets:((innamespace . 0)(inline-open . 0))
+// indent-tabs-mode: nil
+// End:
+
+// vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4
+
+
+
+
Index: branches/v4/modules/vci_cc_vcache_wrapper2_multi/caba/source/src/vci_cc_vcache_wrapper2_multi.cpp
===================================================================
--- branches/v4/modules/vci_cc_vcache_wrapper2_multi/caba/source/src/vci_cc_vcache_wrapper2_multi.cpp	(revision 371)
+++ branches/v4/modules/vci_cc_vcache_wrapper2_multi/caba/source/src/vci_cc_vcache_wrapper2_multi.cpp	(revision 371)
@@ -0,0 +1,5873 @@
+/* -*- c++ -*-
+ * File : vci_cc_vcache_wrapper2_multi.cpp
+ * Copyright (c) UPMC, Lip6, SoC
+ * Authors : Alain GREINER, Yang GAO
+ *
+ * SOCLIB_LGPL_HEADER_BEGIN
+ * 
+ * This file is part of SoCLib, GNU LGPLv2.1.
+ * 
+ * SoCLib is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU Lesser General Public License as published
+ * by the Free Software Foundation; version 2.1 of the License.
+ * 
+ * SoCLib is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * Lesser General Public License for more details.
+ * 
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with SoCLib; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301 USA
+ * 
+ * SOCLIB_LGPL_HEADER_END
+ */
+
+#include <cassert>
+#include "arithmetics.h"
+#include "../include/vci_cc_vcache_wrapper2_multi.h"
+
+namespace soclib { 
+namespace caba {
+
+//#define SOCLIB_MODULE_DEBUG
+#ifdef SOCLIB_MODULE_DEBUG
+namespace {
+const char *icache_fsm_state_str[] = {
+        "ICACHE_IDLE",
+        "ICACHE_BIS",       
+        "ICACHE_TLB1_READ",  
+        "ICACHE_TLB1_WRITE",  
+        "ICACHE_TLB1_UPDT",  
+        "ICACHE_TLB2_READ",  
+        "ICACHE_TLB2_WRITE",  
+        "ICACHE_TLB2_UPDT",  
+        "ICACHE_SW_FLUSH", 
+        "ICACHE_TLB_FLUSH", 
+        "ICACHE_CACHE_FLUSH", 
+        "ICACHE_TLB_INVAL",  
+        "ICACHE_CACHE_INVAL",
+	"ICACHE_CACHE_INVAL_PA",
+        "ICACHE_MISS_WAIT",
+        "ICACHE_UNC_WAIT",  
+        "ICACHE_MISS_UPDT",  
+        "ICACHE_ERROR", 
+        "ICACHE_CC_INVAL", 
+        "ICACHE_TLB_CC_INVAL",        
+    };
+const char *dcache_fsm_state_str[] = {
+        "DCACHE_IDLE",       
+        "DCACHE_BIS",   
+        "DCACHE_DTLB1_READ_CACHE",
+	"DCACHE_TLB1_LL_WAIT",
+	"DCACHE_TLB1_SC_WAIT",    
+        "DCACHE_TLB1_READ",
+        "DCACHE_TLB1_READ_UPDT",  
+        "DCACHE_TLB1_UPDT", 
+        "DCACHE_DTLB2_READ_CACHE", 
+	"DCACHE_TLB2_LL_WAIT",
+	"DCACHE_TLB2_SC_WAIT",   
+        "DCACHE_TLB2_READ",
+        "DCACHE_TLB2_READ_UPDT",  
+        "DCACHE_TLB2_UPDT",   
+        "DCACHE_CTXT_SWITCH",   
+        "DCACHE_ICACHE_FLUSH", 
+        "DCACHE_DCACHE_FLUSH", 
+        "DCACHE_ITLB_INVAL",
+        "DCACHE_DTLB_INVAL",
+        "DCACHE_ICACHE_INVAL",
+        "DCACHE_DCACHE_INVAL",
+	"DCACHE_ICACHE_INVAL_PA",
+	"DCACHE_DCACHE_INVAL_PA",
+	"DCACHE_DCACHE_SYNC",
+	"DCACHE_LL_DIRTY_WAIT",
+	"DCACHE_SC_DIRTY_WAIT",
+        "DCACHE_WRITE_UPDT", 
+        "DCACHE_WRITE_DIRTY",
+        "DCACHE_WRITE_REQ",  
+        "DCACHE_MISS_WAIT",  
+        "DCACHE_MISS_UPDT",  
+        "DCACHE_UNC_WAIT",   
+        "DCACHE_ERROR", 
+        "DCACHE_ITLB_READ",
+        "DCACHE_ITLB_UPDT",
+        "DCACHE_ITLB_LL_WAIT",        
+        "DCACHE_ITLB_SC_WAIT",        
+        "DCACHE_CC_CHECK",
+        "DCACHE_CC_INVAL",
+        "DCACHE_CC_UPDT",
+        "DCACHE_CC_NOP",
+        "DCACHE_TLB_CC_INVAL",
+        "DCACHE_ITLB_CLEANUP",
+    };
+const char *cmd_fsm_state_str[] = {
+        "CMD_IDLE",           
+        "CMD_ITLB_READ", 
+        "CMD_ITLB_ACC_LL",                
+        "CMD_ITLB_ACC_SC",                
+        "CMD_INS_MISS",     
+        "CMD_INS_UNC",     
+        "CMD_DTLB_READ",   
+        "CMD_DTLB_ACC_LL",            
+        "CMD_DTLB_ACC_SC",            
+        "CMD_DTLB_DIRTY_LL",          
+        "CMD_DTLB_DIRTY_SC",          
+        "CMD_DATA_UNC",     
+        "CMD_DATA_MISS",    
+        "CMD_DATA_WRITE", 
+    };
+const char *rsp_fsm_state_str[] = {
+        "RSP_IDLE",                  
+        "RSP_ITLB_READ",             
+        "RSP_ITLB_ACC_LL",                
+        "RSP_ITLB_ACC_SC",                
+        "RSP_INS_MISS",   
+        "RSP_INS_UNC",           
+        "RSP_DTLB_READ",            
+        "RSP_DTLB_ACC_LL",            
+        "RSP_DTLB_ACC_SC",            
+        "RSP_DTLB_DIRTY_LL",          
+        "RSP_DTLB_DIRTY_SC",          
+        "RSP_DATA_MISS",             
+        "RSP_DATA_UNC",              
+        "RSP_DATA_WRITE",     
+    };
+const char *tgt_fsm_state_str[] = {
+        "TGT_IDLE",
+        "TGT_UPDT_WORD",
+        "TGT_UPDT_DATA",
+        "TGT_REQ_BROADCAST",
+        "TGT_REQ_ICACHE",
+        "TGT_REQ_DCACHE",
+        "TGT_RSP_BROADCAST",
+        "TGT_RSP_ICACHE",
+        "TGT_RSP_DCACHE",
+    };	
+const char *inval_itlb_fsm_state_str[] = {
+        "INVAL_ITLB_IDLE",        
+        "INVAL_ITLB_CHECK"  , 
+        "INVAL_ITLB_INVAL",      
+        "INVAL_ITLB_CLEAR",           
+    };
+const char *inval_dtlb_fsm_state_str[] = {
+        "INVAL_DTLB_IDLE",        
+        "INVAL_DTLB_CHECK", 
+        "INVAL_DTLB_INVAL",    
+        "INVAL_DTLB_CLEAR",         
+    };
+const char *cleanup_fsm_state_str[] = {
+        "CLEANUP_CMD",
+	"CLEANUP_ICACHE_RSP",
+        "CLEANUP_DCACHE_RSP",
+    };
+}
+#endif
+
+#define tmpl(...)  template<typename vci_param, typename iss_t> __VA_ARGS__ VciCcVCacheWrapper2Multi<vci_param, iss_t>
+
+using soclib::common::uint32_log2;
+
+/***********************************************/
+tmpl(/**/)::VciCcVCacheWrapper2Multi(
+    sc_module_name name,
+    int proc_id,
+    const soclib::common::MappingTable &mtp,
+    const soclib::common::MappingTable &mtc,
+    const soclib::common::IntTab &initiator_index_rw,
+    const soclib::common::IntTab &initiator_index_c,
+    const soclib::common::IntTab &target_index,
+    size_t itlb_ways,
+    size_t itlb_sets,
+    size_t dtlb_ways,
+    size_t dtlb_sets,
+    size_t icache_ways,
+    size_t icache_sets,
+    size_t icache_words,
+    size_t dcache_ways,
+    size_t dcache_sets,
+    size_t dcache_words,
+    size_t wbuf_nwords,
+    size_t wbuf_nlines )
+/***********************************************/
+    : soclib::caba::BaseModule(name),
+
+      p_clk("clk"),
+      p_resetn("resetn"),
+      p_vci_ini_rw("vci_ini_rw"),
+      p_vci_ini_c("vci_ini_c"),
+      p_vci_tgt("vci_tgt"),
+
+      m_cacheability_table(mtp.getCacheabilityTable()),
+      m_segment(mtc.getSegment(target_index)),
+      m_iss(this->name(), proc_id),
+      m_srcid_rw(mtp.indexForId(initiator_index_rw)),
+      m_srcid_c(mtp.indexForId(initiator_index_c)),
+
+      m_itlb_ways(itlb_ways),
+      m_itlb_sets(itlb_sets),
+
+      m_dtlb_ways(dtlb_ways),
+      m_dtlb_sets(dtlb_sets),
+
+      m_icache_ways(icache_ways),
+      m_icache_sets(icache_sets),
+      m_icache_yzmask((~0)<<(uint32_log2(icache_words) + 2)),
+      m_icache_words(icache_words),
+
+      m_dcache_ways(dcache_ways),
+      m_dcache_sets(dcache_sets),
+      m_dcache_yzmask((~0)<<(uint32_log2(dcache_words) + 2)),
+      m_dcache_words(dcache_words),
+
+      m_wbuf_nlines(wbuf_nlines),
+      m_paddr_nbits(vci_param::N),
+
+      icache_tlb(itlb_ways,itlb_sets,vci_param::N),
+      dcache_tlb(dtlb_ways,dtlb_sets,vci_param::N),
+
+      r_dcache_fsm("r_dcache_fsm"),
+      r_dcache_paddr_save("r_dcache_paddr_save"),
+      r_dcache_wdata_save("r_dcache_wdata_save"),
+      r_dcache_rdata_save("r_dcache_rdata_save"),
+      r_dcache_type_save("r_dcache_type_save"),
+      r_dcache_be_save("r_dcache_be_save"),
+      r_dcache_cached_save("r_dcache_cached_save"),
+      r_dcache_tlb_paddr("r_dcache_tlb_paddr"),
+      r_dcache_miss_req("r_dcache_miss_req"),
+      r_dcache_unc_req("r_dcache_unc_req"),
+      r_dcache_write_req("r_dcache_write_req"),
+      r_dcache_tlb_read_req("r_dcache_tlb_read_req"),
+
+      r_dcache_tlb_ll_acc_req("r_dcache_tlb_ll_acc_req"),       
+      r_dcache_tlb_sc_acc_req("r_dcache_tlb_sc_acc_req"),       
+      r_dcache_tlb_ll_dirty_req("r_dcache_tlb_ll_dirty_req"),    
+      r_dcache_tlb_sc_dirty_req("r_dcache_tlb_sc_dirty_req"), 
+      r_dcache_tlb_ptba_read("r_dcache_tlb_ptba_read"),
+      r_dcache_xtn_req("r_dcache_xtn_req"),
+
+      r_dcache_fsm_save("r_dcache_fsm_save"),
+      r_dcache_cleanup_req("r_dcache_cleanup_req"),
+      r_dcache_inval_rsp("r_dcache_inval_rsp"),
+
+      r_icache_fsm("r_icache_fsm"),
+      r_icache_paddr_save("r_icache_paddr_save"),
+      r_icache_miss_req("r_icache_miss_req"),
+      r_icache_unc_req("r_icache_unc_req"),
+      r_dcache_itlb_read_req("r_dcache_itlb_read_req"),
+      r_dcache_itlb_ll_acc_req("r_dcache_itlb_ll_acc_req"),     
+      r_dcache_itlb_sc_acc_req("r_dcache_itlb_sc_acc_req"),
+
+      r_itlb_read_dcache_req("r_itlb_read_dcache_req"),
+      r_itlb_k_read_dcache("r_itlb_k_read_dcache"),
+      r_itlb_acc_dcache_req("r_itlb_acc_dcache_req"),
+      r_dcache_rsp_itlb_error("r_dcache_rsp_itlb_error"),
+
+      r_icache_fsm_save("r_icache_fsm_save"),
+      r_icache_cleanup_req("r_icache_cleanup_req"),
+      r_icache_inval_rsp("r_icache_inval_rsp"),
+
+      r_vci_cmd_fsm("r_vci_cmd_fsm"),
+      r_vci_cmd_min("r_vci_cmd_min"),
+      r_vci_cmd_max("r_vci_cmd_max"),
+      r_vci_cmd_cpt("r_vci_cmd_cpt"),
+
+      r_vci_rsp_fsm("r_vci_rsp_fsm"),
+      r_vci_rsp_cpt("r_vci_rsp_cpt"),
+      r_vci_rsp_ins_error("r_vci_rsp_ins_error"),
+      r_vci_rsp_data_error("r_vci_rsp_data_error"),
+      r_vci_rsp_ins_ok("r_vci_rsp_ins_ok"),
+      r_vci_rsp_data_ok("r_vci_rsp_data_ok"),
+      r_dcache_tlb_sc_fail("r_dcache_tlb_sc_fail"),
+
+      r_vci_tgt_fsm("r_vci_tgt_fsm"),
+      r_tgt_addr("r_tgt_addr"),
+      r_tgt_word("r_tgt_word"),
+      r_tgt_update("r_tgt_update"),
+      r_tgt_srcid("r_tgt_srcid"),
+      r_tgt_pktid("r_tgt_pktid"),
+      r_tgt_trdid("r_tgt_trdid"),
+      r_tgt_icache_req("r_tgt_icache_req"),
+      r_tgt_dcache_req("r_tgt_dcache_req"),
+
+      r_inval_itlb_fsm("r_inval_itlb_fsm"),          
+      r_dcache_itlb_inval_req("r_dcache_itlb_inval_req"),
+      r_dcache_itlb_inval_line("r_dcache_itlb_inval_line"),
+      r_itlb_cc_check_end("r_itlb_cc_check_end"),
+      r_ccinval_itlb_way("r_ccinval_itlb_way"), 
+      r_ccinval_itlb_set("r_ccinval_itlb_set"), 
+      r_icache_inval_tlb_rsp("r_icache_inval_tlb_rsp"),
+      r_icache_tlb_nline("r_icache_tlb_nline"),
+
+      r_inval_dtlb_fsm("r_inval_dtlb_fsm"),          
+      r_dcache_dtlb_inval_req("r_dcache_dtlb_inval_req"),
+      r_dcache_dtlb_inval_line("r_dcache_dtlb_inval_line"),
+      r_dtlb_cc_check_end("r_dtlb_cc_check_end"),
+      r_ccinval_dtlb_way("r_ccinval_dtlb_way"), 
+      r_ccinval_dtlb_set("r_ccinval_dtlb_set"), 
+      r_dcache_inval_tlb_rsp("r_dcache_inval_tlb_rsp"),
+      r_dcache_tlb_nline("r_dcache_tlb_nline"),
+
+      r_dcache_itlb_cleanup_req("r_dcache_itlb_cleanup_req"),
+      r_dcache_itlb_cleanup_line("r_dcache_itlb_cleanup_line"),
+
+      r_dcache_dtlb_cleanup_req("r_dcache_dtlb_cleanup_req"),
+      r_dcache_dtlb_cleanup_line("r_dcache_dtlb_cleanup_line"),
+      r_cleanup_fsm("r_cleanup_fsm"),
+
+      r_wbuf("wbuf", wbuf_nwords, wbuf_nlines ),
+      r_icache("icache", icache_ways, icache_sets, icache_words),
+      r_dcache("dcache", dcache_ways, dcache_sets, dcache_words)
+{
+    r_icache_miss_buf = new data_t[icache_words];
+    r_dcache_miss_buf = new data_t[dcache_words];
+    r_tgt_buf         = new data_t[dcache_words];
+    r_tgt_val         = new bool[dcache_words];
+    r_dcache_in_itlb  = new bool[dcache_ways*dcache_sets];           
+    r_dcache_in_dtlb  = new bool[dcache_ways*dcache_sets];          
+
+    SC_METHOD(transition);
+    dont_initialize();
+    sensitive << p_clk.pos();
+  
+    SC_METHOD(genMoore);
+    dont_initialize();
+    sensitive << p_clk.neg();
+
+    typename iss_t::CacheInfo cache_info;
+    cache_info.has_mmu = true;
+    cache_info.icache_line_size = icache_words*sizeof(data_t);
+    cache_info.icache_assoc = icache_ways;
+    cache_info.icache_n_lines = icache_sets;
+    cache_info.dcache_line_size = dcache_words*sizeof(data_t);
+    cache_info.dcache_assoc = dcache_ways;
+    cache_info.dcache_n_lines = dcache_sets;
+    m_iss.setCacheInfo(cache_info);
+}
+
+/////////////////////////////////////
+tmpl(/**/)::~VciCcVCacheWrapper2Multi()
+/////////////////////////////////////
+{
+    delete [] r_icache_miss_buf;
+    delete [] r_dcache_miss_buf;
+    delete [] r_tgt_val;
+    delete [] r_tgt_buf;
+    delete [] r_dcache_in_itlb;           
+    delete [] r_dcache_in_dtlb;          
+}
+
+////////////////////////
+tmpl(void)::print_cpi()
+////////////////////////
+{
+    std::cout << name() << " CPI = " 
+        << (float)m_cpt_total_cycles/(m_cpt_total_cycles - m_cpt_frz_cycles) << std::endl ;
+}
+
+////////////////////////
+tmpl(void)::print_stats()
+////////////////////////
+{
+    float run_cycles = (float)(m_cpt_total_cycles - m_cpt_frz_cycles);
+    std::cout << name() << std::endl
+    	      << "- CPI                    = " << (float)m_cpt_total_cycles/run_cycles << std::endl 
+    	      << "- READ RATE              = " << (float)m_cpt_read/run_cycles << std::endl 
+    	      << "- WRITE RATE             = " << (float)m_cpt_write/run_cycles << std::endl
+    	      << "- UNCACHED READ RATE     = " << (float)m_cpt_unc_read/m_cpt_read << std::endl 
+    	      << "- CACHED WRITE RATE      = " << (float)m_cpt_write_cached/m_cpt_write << std::endl 
+    	      << "- IMISS_RATE             = " << (float)m_cpt_ins_miss/m_cpt_ins_read << std::endl    
+    	      << "- DMISS RATE             = " << (float)m_cpt_data_miss/(m_cpt_read-m_cpt_unc_read) << std::endl 
+    	      << "- INS MISS COST          = " << (float)m_cost_ins_miss_frz/m_cpt_ins_miss << std::endl
+    	      << "- IMISS TRANSACTION      = " << (float)m_cost_imiss_transaction/m_cpt_imiss_transaction << std::endl
+    	      << "- DMISS COST             = " << (float)m_cost_data_miss_frz/m_cpt_data_miss << std::endl
+    	      << "- DMISS TRANSACTION      = " << (float)m_cost_dmiss_transaction/m_cpt_dmiss_transaction << std::endl
+    	      << "- UNC COST               = " << (float)m_cost_unc_read_frz/m_cpt_unc_read << std::endl
+    	      << "- UNC TRANSACTION        = " << (float)m_cost_unc_transaction/m_cpt_unc_transaction << std::endl
+    	      << "- WRITE COST             = " << (float)m_cost_write_frz/m_cpt_write << std::endl
+    	      << "- WRITE TRANSACTION      = " << (float)m_cost_write_transaction/m_cpt_write_transaction << std::endl
+    	      << "- WRITE LENGTH           = " << (float)m_length_write_transaction/m_cpt_write_transaction << std::endl
+    	      << "- INS TLB MISS RATE      = " << (float)m_cpt_ins_tlb_miss/m_cpt_ins_tlb_read << std::endl
+    	      << "- DATA TLB MISS RATE     = " << (float)m_cpt_data_tlb_miss/m_cpt_data_tlb_read << std::endl
+    	      << "- ITLB MISS TRANSACTION  = " << (float)m_cost_itlbmiss_transaction/m_cpt_itlbmiss_transaction << std::endl
+    	      << "- ITLB WRITE TRANSACTION = " << (float)m_cost_itlb_write_transaction/m_cpt_itlb_write_transaction << std::endl
+    	      << "- ITLB MISS COST         = " << (float)m_cost_ins_tlb_miss_frz/(m_cpt_ins_tlb_miss+m_cpt_ins_tlb_write_et) << std::endl
+    	      << "- DTLB MISS TRANSACTION  = " << (float)m_cost_dtlbmiss_transaction/m_cpt_dtlbmiss_transaction << std::endl
+    	      << "- DTLB WRITE TRANSACTION = " << (float)m_cost_dtlb_write_transaction/m_cpt_dtlb_write_transaction << std::endl
+    	      << "- DTLB MISS COST         = " << (float)m_cost_data_tlb_miss_frz/(m_cpt_data_tlb_miss+m_cpt_data_tlb_write_et+m_cpt_data_tlb_write_dirty) << std::endl;
+}
+
+/*************************************************/
+tmpl(void)::transition()
+/*************************************************/
+{
+    if ( ! p_resetn.read() ) 
+    {
+        m_iss.reset();
+
+        r_dcache_fsm = DCACHE_IDLE;
+        r_icache_fsm = ICACHE_IDLE;
+        r_vci_cmd_fsm = CMD_IDLE;
+        r_vci_rsp_fsm = RSP_IDLE;
+        r_vci_tgt_fsm = TGT_IDLE;
+        r_inval_itlb_fsm = INVAL_ITLB_IDLE;          
+        r_inval_dtlb_fsm = INVAL_DTLB_IDLE;    
+  	r_cleanup_fsm = CLEANUP_CMD;	
+
+        // write buffer & caches
+        r_wbuf.reset();
+        r_icache.reset();
+        r_dcache.reset();
+
+        icache_tlb.reset();    
+        dcache_tlb.reset();    
+
+        std::memset(r_dcache_in_itlb, 0, sizeof(*r_dcache_in_itlb)*m_icache_ways*m_icache_sets);
+        std::memset(r_dcache_in_dtlb, 0, sizeof(*r_dcache_in_dtlb)*m_dcache_ways*m_dcache_sets);
+
+        //r_mmu_mode = ALL_DEACTIVE;
+        r_mmu_mode = 0x3;
+        r_mmu_params = (uint32_log2(m_dtlb_ways) << 29)   | (uint32_log2(m_dtlb_sets) << 25)   |
+                       (uint32_log2(m_dcache_ways) << 22) | (uint32_log2(m_dcache_sets) << 18) |
+                       (uint32_log2(m_itlb_ways) << 15)   | (uint32_log2(m_itlb_sets) << 11)   |
+                       (uint32_log2(m_icache_ways) << 8)  | (uint32_log2(m_icache_sets) << 4)  |
+                       (uint32_log2(m_icache_words * 4));
+        r_mmu_release = (uint32_t)(1 << 16) | 0x1;
+
+        r_icache_miss_req         = false;
+        r_icache_unc_req          = false;
+        r_dcache_itlb_read_req    = false;
+
+        r_itlb_read_dcache_req    = false;      
+        r_itlb_k_read_dcache      = false;      
+        r_itlb_acc_dcache_req     = false;   
+        r_dcache_rsp_itlb_error   = false;
+ 
+        r_dcache_miss_req         = false;
+        r_dcache_unc_req          = false;
+        r_dcache_write_req        = false;
+        r_dcache_tlb_read_req     = false;
+        r_dcache_tlb_ptba_read    = false;
+        r_dcache_xtn_req          = false;
+	r_dcache_llsc_reserved    = false;
+
+        r_dcache_tlb_ll_acc_req   = false;    
+        r_dcache_tlb_sc_acc_req   = false;    
+        r_dcache_tlb_ll_dirty_req = false;   
+        r_dcache_tlb_sc_dirty_req = false;   
+        r_dcache_itlb_ll_acc_req  = false;   
+        r_dcache_itlb_sc_acc_req  = false;   
+
+        r_icache_cleanup_req      = false;
+        r_dcache_cleanup_req      = false;
+
+        r_tgt_icache_req          = false;
+        r_tgt_dcache_req          = false;
+
+        r_icache_inval_rsp        = false;
+        r_dcache_inval_rsp        = false;
+
+        r_dcache_dirty_save       = false;
+        r_dcache_hit_p_save       = false;
+
+        r_vci_rsp_ins_error       = false;
+        r_vci_rsp_data_error      = false;
+
+	r_vci_rsp_ins_ok          = false;
+        r_vci_rsp_data_ok         = false;
+
+        r_icache_id1_save         = 0;
+        r_icache_ppn_save         = 0;
+        r_icache_vpn_save         = 0;
+        r_itlb_translation_valid  = false;
+
+        r_dcache_id1_save         = 0;
+        r_dcache_ppn_save         = 0;
+        r_dcache_vpn_save         = 0;
+        r_dtlb_translation_valid  = false;
+
+        r_icache_ptba_ok          = false;
+        r_dcache_ptba_ok          = false;
+
+        r_icache_error_type       = MMU_NONE;
+        r_dcache_error_type       = MMU_NONE;
+
+        // coherence registers
+        r_icache_way              = 0;
+        r_icache_set              = 0;
+        r_icache_cleanup_req      = false;
+        r_icache_inval_rsp        = false;
+
+        r_dcache_way              = 0;
+        r_dcache_set              = 0;
+        r_dcache_cleanup_req      = false;
+        r_dcache_inval_rsp        = false;
+
+	r_itlb_inval_req 	  = false;
+        r_dcache_itlb_inval_req   = false;
+        r_itlb_cc_check_end       = false;
+        r_ccinval_itlb_way        = 0; 
+        r_ccinval_itlb_set        = 0; 
+        r_icache_inval_tlb_rsp    = false;
+
+        r_dcache_dtlb_inval_req   = false;
+        r_dtlb_cc_check_end       = false;
+        r_ccinval_dtlb_way        = 0; 
+        r_ccinval_dtlb_set        = 0; 
+        r_dcache_inval_tlb_rsp    = false;
+
+        r_dcache_itlb_cleanup_req = false;
+        r_dcache_dtlb_cleanup_req = false;
+
+	r_dcache_cc_check         = false;
+	r_dcache_tlb_sc_fail	  = false;
+
+        // activity counters
+        m_cpt_dcache_data_read  = 0;
+        m_cpt_dcache_data_write = 0;
+        m_cpt_dcache_dir_read   = 0;
+        m_cpt_dcache_dir_write  = 0;
+        m_cpt_icache_data_read  = 0;
+        m_cpt_icache_data_write = 0;
+        m_cpt_icache_dir_read   = 0;
+        m_cpt_icache_dir_write  = 0;
+
+	m_cpt_frz_cycles   = 0;
+        m_cpt_total_cycles = 0;
+
+        m_cpt_read         = 0;
+        m_cpt_write        = 0;
+        m_cpt_data_miss    = 0;
+        m_cpt_ins_miss     = 0;
+        m_cpt_unc_read     = 0;
+        m_cpt_write_cached = 0;
+        m_cpt_ins_read     = 0;
+
+        m_cost_write_frz     = 0;
+        m_cost_data_miss_frz = 0;
+        m_cost_unc_read_frz  = 0;
+        m_cost_ins_miss_frz  = 0;
+
+        m_cpt_imiss_transaction = 0;
+        m_cpt_dmiss_transaction = 0;
+        m_cpt_unc_transaction   = 0;
+        m_cpt_write_transaction = 0;
+
+        m_cost_imiss_transaction   = 0;
+        m_cost_dmiss_transaction   = 0;
+        m_cost_unc_transaction     = 0;
+        m_cost_write_transaction   = 0;
+        m_length_write_transaction = 0;
+
+        m_cpt_ins_tlb_read         = 0;             
+        m_cpt_ins_tlb_miss         = 0;             
+        m_cpt_ins_tlb_write_et     = 0;         
+
+        m_cpt_data_tlb_read        = 0;           
+        m_cpt_data_tlb_miss        = 0;           
+        m_cpt_data_tlb_write_et    = 0;       
+        m_cpt_data_tlb_write_dirty = 0;    
+
+        m_cost_ins_tlb_miss_frz    = 0;      
+        m_cost_data_tlb_miss_frz   = 0;      
+
+        m_cpt_itlbmiss_transaction   = 0;    
+        m_cpt_itlb_write_transaction = 0;  
+        m_cpt_dtlbmiss_transaction   = 0;  
+        m_cpt_dtlb_write_transaction = 0;  
+ 
+        m_cost_itlbmiss_transaction   = 0;   
+        m_cost_itlb_write_transaction = 0;  
+        m_cost_dtlbmiss_transaction   = 0;   
+        m_cost_dtlb_write_transaction = 0;   
+        return;
+    }
+
+#ifdef SOCLIB_MODULE_DEBUG
+std::cout << name() << "cycle = " << m_cpt_total_cycles  
+       	  << " tgt fsm: " << tgt_fsm_state_str[r_vci_tgt_fsm]
+       	  << " dcache fsm: " << dcache_fsm_state_str[r_dcache_fsm]
+       	  << " icache fsm: " << icache_fsm_state_str[r_icache_fsm]
+       	  << " cmd fsm: " << cmd_fsm_state_str[r_vci_cmd_fsm]
+       	  << " rsp fsm: " << rsp_fsm_state_str[r_vci_rsp_fsm] 
+       	  << " inval itlb fsm: " << inval_itlb_fsm_state_str[r_inval_itlb_fsm] 
+          << " inval dtlb fsm: " << inval_dtlb_fsm_state_str[r_inval_dtlb_fsm] << std::endl;
+#endif
+
+    m_cpt_total_cycles++;
+
+    typename iss_t::InstructionRequest ireq = ISS_IREQ_INITIALIZER;
+    typename iss_t::InstructionResponse irsp = ISS_IRSP_INITIALIZER;
+
+    typename iss_t::DataRequest dreq = ISS_DREQ_INITIALIZER;
+    typename iss_t::DataResponse drsp = ISS_DRSP_INITIALIZER;
+
+    m_iss.getRequests( ireq, dreq );
+
+#ifdef SOCLIB_MODULE_DEBUG
+    std::cout << name() << " Instruction Request: " << ireq << std::endl;
+    std::cout << name() << " Data Request: " << dreq << std::endl;
+#endif
+
+    /////////////////////////////////////////////////////////////////////
+    // The TGT_FSM controls the following ressources:
+    // - r_vci_tgt_fsm
+    // - r_tgt_buf[nwords]
+    // - r_tgt_val[nwords]
+    // - r_tgt_update
+    // - r_tgt_word
+    // - r_tgt_addr
+    // - r_tgt_srcid
+    // - r_tgt_trdid
+    // - r_tgt_pktid
+    // All VCI commands must be CMD_WRITE.
+    // If the VCI address offset is null, the command is an invalidate 
+    // request. It is an update request otherwise.
+    // The VCI_TGT FSM stores the external request arguments in the
+    // IDLE, UPDT_WORD & UPDT_DATA states. It sets the r_tgt_icache_req 
+    // & r_tgt_dcache_req flip-flops to signal the external request to 
+    // the ICACHE & DCACHE FSMs in the REQ state. It waits the completion
+    // of the update or invalidate request in the RSP state.
+    // -  for an invalidate request the VCI packet length is 1 word.
+    // The WDATA field contains the line index (i.e. the Z & Y fields).
+    // -  for an update request the VCI packet length is (n+2) words.
+    // The WDATA field of the first VCI word contains the line number.
+    // The WDATA field of the second VCI word contains the word index.
+    // The WDATA field of the n following words contains the values.
+    // -  for both invalidate & update requests, the VCI response
+    // is one single word.
+    // In case of errors in the VCI command packet, the simulation
+    // is stopped with an error message.
+    /////////////////////////////////////////////////////////////////////
+    
+    switch(r_vci_tgt_fsm) {
+    //////////////
+    case TGT_IDLE:
+    {
+        if ( p_vci_tgt.cmdval.read() ) 
+        {
+            paddr_t address = p_vci_tgt.address.read();
+
+            if ( p_vci_tgt.cmd.read() != vci_param::CMD_WRITE) 
+            {
+                std::cout << "error in component VCI_CC_VCACHE_WRAPPER " << name() << std::endl;
+                std::cout << "the received VCI command is not a write" << std::endl;
+                exit(0);
+            }
+
+            // multi-update or multi-invalidate for data type
+            if ( ( address != 0x3 ) && ( ! m_segment.contains(address)) ) 
+            {
+                std::cout << "error in component VCI_CC_VCACHE_WRAPPER " << name() << std::endl;
+                std::cout << "out of segment VCI command received for a multi-updt or multi-inval request" << std::endl;
+                exit(0);
+            }
+
+            r_tgt_srcid = p_vci_tgt.srcid.read();
+            r_tgt_trdid = p_vci_tgt.trdid.read();
+            r_tgt_pktid = p_vci_tgt.pktid.read();
+            r_tgt_plen  = p_vci_tgt.plen.read(); 
+            r_tgt_addr  = (paddr_t)(p_vci_tgt.be.read() & 0x3) << 32 |
+			  (paddr_t)p_vci_tgt.wdata.read() * m_dcache_words * 4; 
+
+            if ( address == 0x3 ) // broadcast invalidate for data or instruction type
+            {
+                if ( ! p_vci_tgt.eop.read() ) 
+                {
+                    std::cout << "error in component VCI_CC_VCACHE_WRAPPER " << name() << std::endl;
+                    std::cout << "the BROADCAST INVALIDATE command length must be one word" << std::endl;
+                    exit(0);
+                }
+                r_tgt_update = false; 
+                r_vci_tgt_fsm = TGT_REQ_BROADCAST;
+                m_cpt_cc_broadcast++;
+            }
+            else                // multi-update or multi-invalidate for data type
+            {
+                paddr_t cell = address - m_segment.baseAddress();   
+
+                if (cell == 0)                      // invalidate   
+                {                         
+                    if ( ! p_vci_tgt.eop.read() ) 
+                    {
+                        std::cout << "error in component VCI_CC_VCACHE_WRAPPER " << name() << std::endl;
+                        std::cout << "the MULTI-INVALIDATE command length must be one word" << std::endl;
+                        exit(0);
+                    }
+                    r_tgt_update = false; 
+                    r_vci_tgt_fsm = TGT_REQ_DCACHE;
+                    m_cpt_cc_inval++ ;
+                }
+                else if (cell == 4)                // update 
+                {                                
+                    if ( p_vci_tgt.eop.read() ) 
+                    {
+                        std::cout << "error in component VCI_CC_VCACHE_WRAPPER " << name() << std::endl;
+                        std::cout << "the MULTI-UPDATE command length must be N+2 words" << std::endl;
+                        exit(0);
+                    }
+                    r_tgt_update = true; 
+                    r_vci_tgt_fsm = TGT_UPDT_WORD;
+                    m_cpt_cc_update++ ;
+                }     
+		else if (cell == 8)
+		{
+                    if ( ! p_vci_tgt.eop.read() ) 
+                    {
+                        std::cout << "error in component VCI_CC_VCACHE_WRAPPER " << name() << std::endl;
+                        std::cout << "the MULTI-INVALIDATE command length must be one word" << std::endl;
+                        exit(0);
+                    }
+                    r_tgt_update = false; 
+                    r_vci_tgt_fsm = TGT_REQ_ICACHE;
+                    m_cpt_cc_inval++ ;
+
+		}
+            } // end if address    
+        } // end if cmdval
+        break;
+    }
+    ///////////////////
+    case TGT_UPDT_WORD:
+    {
+        if (p_vci_tgt.cmdval.read()) 
+        {
+            if ( p_vci_tgt.eop.read() ) 
+            {
+                std::cout << "error in component VCI_CC_VCACHE_WRAPPER " << name() << std::endl;
+                std::cout << "the MULTI-UPDATE command length must be N+2 words" << std::endl;
+                exit(0);
+            }
+            for ( size_t i=0 ; i<m_dcache_words ; i++ ) r_tgt_val[i] = false;
+            r_tgt_word = p_vci_tgt.wdata.read(); // the first modified word index
+            r_vci_tgt_fsm = TGT_UPDT_DATA;
+        }
+        break;
+    }
+    ///////////////////
+    case TGT_UPDT_DATA:
+    {
+        if (p_vci_tgt.cmdval.read()) 
+        {
+            size_t word = r_tgt_word.read();
+            if (word >= m_dcache_words) 
+            {
+                std::cout << "error in component VCI_CC_VCACHE_WRAPPER " << name() << std::endl;
+                std::cout << "the reveived MULTI-UPDATE command length is wrong" << std::endl;
+                exit(0);
+            }
+            r_tgt_buf[word] = p_vci_tgt.wdata.read();
+            if(p_vci_tgt.be.read())    r_tgt_val[word] = true;
+            r_tgt_word = word + 1;
+            if (p_vci_tgt.eop.read())  r_vci_tgt_fsm = TGT_REQ_DCACHE;
+        }
+        break;
+    }
+    ////////////////////////
+    case TGT_REQ_BROADCAST:
+    {
+        if ( !r_tgt_icache_req.read() && !r_tgt_dcache_req.read() ) 
+        {
+            r_vci_tgt_fsm = TGT_RSP_BROADCAST; 
+            r_tgt_icache_req = true;
+            r_tgt_dcache_req = true;
+        }
+        break;
+    }
+    /////////////////////
+    case TGT_REQ_ICACHE:
+    {
+        if ( !r_tgt_icache_req.read() ) 
+        {
+            r_vci_tgt_fsm = TGT_RSP_ICACHE; 
+            r_tgt_icache_req = true;
+        }
+        break;
+    }
+    /////////////////////
+    case TGT_REQ_DCACHE:
+    {
+        if ( !r_tgt_dcache_req.read() ) 
+        {
+            r_vci_tgt_fsm = TGT_RSP_DCACHE; 
+            r_tgt_dcache_req = true;
+        }
+        break;
+    }
+    ///////////////////////
+    case TGT_RSP_BROADCAST:
+    {
+        // no response
+        if ( !r_tgt_icache_rsp.read() && !r_tgt_dcache_rsp.read() && !r_tgt_icache_req.read() && !r_tgt_dcache_req.read() )
+        {
+            r_vci_tgt_fsm = TGT_IDLE;
+            break;
+        }
+
+        if ( p_vci_tgt.rspack.read() && !r_tgt_icache_req.read() && !r_tgt_dcache_req.read() ) 
+        {
+            // one response
+            if ( !r_tgt_icache_rsp || !r_tgt_dcache_rsp )
+            {
+                r_vci_tgt_fsm = TGT_IDLE; 
+                r_tgt_icache_rsp = false;
+                r_tgt_dcache_rsp = false;
+            }
+
+            // if data and instruction have the inval line, need two responses  
+            if ( r_tgt_icache_rsp && r_tgt_dcache_rsp )
+            {
+                r_tgt_icache_rsp = false; // only reset one for respond the second time 
+            }
+        }
+        break;
+    }
+    /////////////////////
+    case TGT_RSP_ICACHE:
+    {
+	if ( (p_vci_tgt.rspack.read() || !r_tgt_icache_rsp.read()) && !r_tgt_icache_req.read() ) 
+        {
+            r_vci_tgt_fsm = TGT_IDLE;
+            r_tgt_icache_rsp = false; 
+        }
+        break;
+    }
+    /////////////////////
+    case TGT_RSP_DCACHE:
+    {
+	if ( (p_vci_tgt.rspack.read() || !r_tgt_dcache_rsp.read()) && !r_tgt_dcache_req.read() )
+        {
+            r_vci_tgt_fsm = TGT_IDLE;
+            r_tgt_dcache_rsp = false; 
+        }
+        break;
+    }
+    } // end switch TGT_FSM
+
+    ////////////////////////////////////////////////////////////////////////////////////////
+    //      ICACHE_FSM
+    //
+    // There is 9 mutually exclusive conditions to exit the IDLE state.
+    // Four configurations corresponding to an XTN request from processor,
+    // - Flush TLB (in case of Context switch) => TLB_FLUSH state 
+    // - Flush cache => CACHE_FLUSH state 
+    // - Invalidate a TLB entry => TLB_INVAL state
+    // - Invalidate a cache line => CACHE_INVAL state
+    // Five configurations corresponding to various TLB or cache MISS :
+    // - TLB miss(in case hit_p miss) => TLB1_READ state
+    // - TLB miss(in case hit_p hit) => TLB2_READ state
+    // - Hit in TLB but VPN changed => BIS state
+    // - Cached read miss => MISS_REQ state
+    // - Uncache read miss => UNC_REQ state
+    // 
+    // In case of MISS, the controller writes a request in the r_icache_paddr_save register 
+    // and sets the corresponding request flip-flop : r_dcache_itlb_read_req, r_icache_miss_req 
+    // or r_icache_unc_req. These request flip-flops are reset by the VCI_RSP controller 
+    // when the response is ready in the ICACHE buffer.
+    //
+    // The DCACHE FSM signals XTN processor requests using the r_dcache_xtn_req flip-flop. 
+    // The request opcod and the address to be invalidated are transmitted
+    // in the r_dcache_paddr_save & r_dcache_wdata_save registers respectively.
+    // The request flip-flop is reset by the ICACHE_FSM when the operation is completed.
+    //
+    // The r_vci_rsp_ins_error flip-flop is set by the VCI_RSP FSM and reset
+    // by the ICACHE-FSM in the ICACHE_ERROR state.
+    //
+    //----------------------------------------------------------------------------------- 
+    // Instruction TLB: 
+    //  
+    // - int        ET          (00: unmapped; 01: unused or PTD)
+    //                          (10: PTE new;  11: PTE old      )
+    // - bool       cachable    (cached bit)
+    // - bool       writable    (** not used alwayse false) 
+    // - bool       executable  (executable bit)
+    // - bool       user        (access in user mode allowed)
+    // - bool       global      (PTE not invalidated by a TLB flush)
+    // - bool       dirty       (** not used alwayse false) 
+    // - uint32_t   vpn         (virtual page number)
+    // - uint32_t   ppn         (physical page number)
+    ////////////////////////////////////////////////////////////////////////////////////////
+
+    switch(r_icache_fsm) {
+
+    ////////////////
+    case ICACHE_IDLE:
+    {
+        pte_info_t  icache_pte_info;
+        paddr_t     tlb_ipaddr       = 0;    	// physical address obtained from TLB                         
+        paddr_t     spc_ipaddr       = 0;    	// physical adress obtained from PPN_save (speculative)       
+        data_t      icache_ins       = 0;    	// read instruction
+        bool        icache_hit_c     = false;	// Cache hit
+        bool        icache_cached    = false;	// cacheable access (read)
+        bool        icache_hit_t     = false;	// hit on TLB
+        bool        icache_hit_x     = false;	// VPN unmodified (can use spc_dpaddr)
+        bool        icache_hit_p     = false;	// PTP unmodified (can skip first level page table walk)
+        size_t      icache_tlb_way   = 0;    	// selected way (in case of cache hit)
+        size_t      icache_tlb_set   = 0;    	// selected set (Y field in address)
+        paddr_t     icache_tlb_nline = 0;  	// TLB NLINE 
+
+        // Decoding processor XTN requests
+        // They are sent by DCACHE FSM  
+
+        if (r_dcache_xtn_req)
+        {
+            if ( ireq.valid ) m_cost_ins_waste_wait_frz++;
+            
+            if ((int)r_dcache_type_save == (int)iss_t::XTN_PTPR )  
+            {
+                r_icache_way = 0;
+                r_icache_set = 0;
+                r_icache_fsm = ICACHE_SW_FLUSH;   
+                break;
+            }
+            if ((int)r_dcache_type_save == (int)iss_t::XTN_ICACHE_FLUSH)
+            {
+                r_icache_way = 0;
+                r_icache_set = 0;
+                r_icache_fsm = ICACHE_CACHE_FLUSH;   
+                break;
+            }
+            if ((int)r_dcache_type_save == (int)iss_t::XTN_ITLB_INVAL) 
+            {
+                r_icache_fsm = ICACHE_TLB_INVAL;   
+                break;
+            }
+            if ((int)r_dcache_type_save == (int)iss_t::XTN_ICACHE_INVAL) 
+            {
+                r_icache_fsm = ICACHE_CACHE_INVAL;   
+                break;
+            }
+            if ((int)r_dcache_type_save == (int)iss_t::XTN_MMU_ICACHE_PA_INV) 
+            {
+                r_icache_fsm = ICACHE_CACHE_INVAL_PA;   
+                break;
+            }
+            if ((int)r_dcache_type_save == (int)iss_t::XTN_DCACHE_FLUSH )  
+            {
+                // special for ins tlb miss via data cache
+                r_icache_fsm = ICACHE_TLB_FLUSH;   
+                break;
+            }
+        } // end if xtn_req
+
+        // external cache invalidate request
+        if ( r_tgt_icache_req )
+        {
+            if ( ireq.valid ) m_cost_ins_waste_wait_frz++;
+            r_icache_fsm = ICACHE_CC_INVAL;
+            r_icache_fsm_save = r_icache_fsm;
+            break;
+        }
+
+        // external tlb invalidate request
+        if ( r_dcache_itlb_inval_req )
+        {
+            if ( ireq.valid ) m_cost_ins_waste_wait_frz++;
+	    r_itlb_inval_req = true;
+            r_icache_fsm = ICACHE_TLB_CC_INVAL;
+            r_icache_fsm_save = r_icache_fsm;
+            break;
+        }
+
+        // icache_hit_t_m, icache_hit_t_k, icache_hit_x, icache_hit_p 
+        // icache_pte_info, icache_tlb_way, icache_tlb_set & ipaddr & cacheability 
+        // - If MMU activated : cacheability is defined by the cachable bit in the TLB
+        // - If MMU not activated : cacheability is defined by the segment table.
+
+        if ( !(r_mmu_mode.read() & INS_TLB_MASK) )   // MMU not activated 
+        {
+            icache_hit_t  = true;         
+            icache_hit_x  = true;         
+            icache_hit_p  = true;         
+            tlb_ipaddr    = ireq.addr;
+            spc_ipaddr    = ireq.addr;
+            icache_cached = m_cacheability_table[ireq.addr];
+        } 
+        else                                                                // MMU activated
+        { 
+            m_cpt_ins_tlb_read++;
+            icache_hit_t  = icache_tlb.cctranslate(ireq.addr, &tlb_ipaddr, &icache_pte_info, 
+                                                   &icache_tlb_nline, &icache_tlb_way, &icache_tlb_set); 
+            icache_hit_x  = (((vaddr_t)r_icache_vpn_save << PAGE_K_NBITS) == (ireq.addr & ~PAGE_K_MASK)) && r_itlb_translation_valid;
+            icache_hit_p  = (((ireq.addr >> PAGE_M_NBITS) == r_icache_id1_save) && r_icache_ptba_ok); 
+            spc_ipaddr    = ((paddr_t)r_icache_ppn_save << PAGE_K_NBITS) | (paddr_t)(ireq.addr & PAGE_K_MASK);
+            icache_cached = icache_pte_info.c; 
+        }
+
+        if ( !(r_mmu_mode.read() & INS_CACHE_MASK) )   // cache not actived
+        {
+            icache_cached = false;
+        }
+
+        if ( ireq.valid ) 
+        {
+            m_cpt_icache_dir_read += m_icache_ways;
+            m_cpt_icache_data_read += m_icache_ways;
+
+            // icache_hit_c & icache_ins
+            if ( icache_cached )    // using speculative physical address for cached access
+            {
+                icache_hit_c = r_icache.read(spc_ipaddr, &icache_ins);
+            }
+            else                    // using actual physical address for uncached access
+            {
+                icache_hit_c = ( r_vci_rsp_ins_ok && (tlb_ipaddr == (paddr_t)r_icache_paddr_save) );
+                icache_ins = r_icache_miss_buf[0];
+            }
+
+            if ( r_mmu_mode.read() & INS_TLB_MASK ) 
+            {
+                if ( icache_hit_t ) 
+                {
+                    // check access rights
+                    if ( !icache_pte_info.u && (ireq.mode == iss_t::MODE_USER)) 
+                    {
+                        r_icache_error_type = MMU_READ_PRIVILEGE_VIOLATION;  
+                        r_icache_bad_vaddr = ireq.addr;
+                        irsp.valid = true;
+                        irsp.error = true;
+                        irsp.instruction = 0;
+                        break;
+                    }
+                    if ( !icache_pte_info.x ) 
+                    {
+                        r_icache_error_type = MMU_READ_EXEC_VIOLATION;  
+                        r_icache_bad_vaddr = ireq.addr;
+                        irsp.valid = true;
+                        irsp.error = true;
+                        irsp.instruction = 0;
+                        break;
+                    }
+                }
+
+                // update LRU, save ppn, vpn and page type
+                if ( icache_hit_t )
+                {  
+                    icache_tlb.setlru(icache_tlb_way,icache_tlb_set);     
+                    r_icache_ppn_save = tlb_ipaddr >> PAGE_K_NBITS;
+                    r_icache_vpn_save = ireq.addr >> PAGE_K_NBITS;
+                    r_icache_tlb_nline = icache_tlb_nline;
+                    r_itlb_translation_valid = true;
+                }
+                else
+                {
+                    r_itlb_translation_valid = false;
+                }
+
+            } // end if MMU activated
+
+            // compute next state 
+            if ( !icache_hit_t && !icache_hit_p )      // TLB miss
+            {
+                // walk page table  level 1
+                r_icache_paddr_save = (paddr_t)r_mmu_ptpr << (INDEX1_NBITS+2) | (paddr_t)((ireq.addr>>PAGE_M_NBITS)<<2);
+                r_itlb_read_dcache_req = true;
+		r_icache_vaddr_req = ireq.addr;
+                r_icache_fsm = ICACHE_TLB1_READ;
+                m_cpt_ins_tlb_miss++;
+                m_cost_ins_tlb_miss_frz++;
+            }
+            else if ( !icache_hit_t && icache_hit_p )  // TLB Miss with possibility of bypass first level page
+            {
+                // walk page table level 2
+                r_icache_paddr_save = (paddr_t)r_icache_ptba_save | 
+                                      (paddr_t)(((ireq.addr&PTD_ID2_MASK)>>PAGE_K_NBITS) << 3);
+                r_itlb_read_dcache_req = true;
+		r_icache_vaddr_req = ireq.addr;
+		r_itlb_k_read_dcache = true;
+                r_icache_fsm = ICACHE_TLB2_READ;
+                m_cpt_ins_tlb_miss++;
+                m_cost_ins_tlb_miss_frz++;
+            }
+            else if ( icache_hit_t && !icache_hit_x && icache_cached ) // cached access with an ucorrect speculative physical address
+            {
+                r_icache_paddr_save = tlb_ipaddr;   // save actual physical address for BIS
+		r_icache_vaddr_req = ireq.addr;
+                r_icache_fsm = ICACHE_BIS;
+                m_cost_ins_miss_frz++;
+            }
+            else    // cached or uncached access with a correct speculative physical address 
+            {        
+                m_cpt_ins_read++; 
+                if ( !icache_hit_c ) 
+                {
+                    m_cpt_ins_miss++;
+                    m_cost_ins_miss_frz++;
+                    if ( icache_cached ) 
+                    {
+                        r_icache_miss_req = true;
+			r_vci_rsp_ins_ok = false;
+                    	r_icache_paddr_save = spc_ipaddr; 
+			r_icache_vaddr_req = ireq.addr;
+                        r_icache_fsm = ICACHE_MISS_WAIT;
+                    } 
+                    else 
+                    {
+                        r_icache_unc_req = true;
+			r_vci_rsp_ins_ok = false;
+                    	r_icache_paddr_save = tlb_ipaddr; 
+			r_icache_vaddr_req = ireq.addr;
+                        r_icache_fsm = ICACHE_UNC_WAIT;
+                    } 
+                } 
+                else 
+                {
+		    r_vci_rsp_ins_ok = false;
+                    r_icache_fsm = ICACHE_IDLE;
+                }
+                irsp.valid = icache_hit_c;
+                irsp.instruction = icache_ins;
+            } // end if next states
+            
+        } // end if ireq.valid
+        break;
+    }
+    ////////////////
+    case ICACHE_BIS: 
+    {
+        m_cost_ins_miss_frz++;
+        // external cache invalidate request
+        if ( r_tgt_icache_req )
+        {
+            r_icache_fsm = ICACHE_CC_INVAL;
+            r_icache_fsm_save = r_icache_fsm;
+            m_cost_ins_waste_wait_frz++;
+            break;
+        }
+
+        // external tlb invalidate request
+        if ( r_dcache_itlb_inval_req )
+        {
+	    r_itlb_inval_req = true;
+            r_icache_fsm = ICACHE_TLB_CC_INVAL;
+            r_icache_fsm_save = r_icache_fsm;
+            m_cost_ins_waste_wait_frz++;
+            break;
+        }
+      
+        // using page is invalidated 
+        if ( r_icache_inval_tlb_rsp )
+        {
+            r_icache_inval_tlb_rsp = false;
+            r_icache_fsm = ICACHE_IDLE;
+            m_cost_ins_tlb_miss_frz++;
+            break;
+        }
+ 
+        data_t	icache_ins = 0;
+        bool	icache_hit_c = false;
+        bool    icache_hit_t = false;
+        paddr_t	tlb_ipaddr = 0;
+
+	icache_hit_t = icache_tlb.translate(ireq.addr, &tlb_ipaddr);
+
+	if ( (tlb_ipaddr == r_icache_paddr_save.read()) && ireq.valid && icache_hit_t )		// unmodified & valid
+	{
+            m_cpt_ins_read++;
+
+            // acces is always cached in this state
+            icache_hit_c = r_icache.read(r_icache_paddr_save, &icache_ins);
+
+            if ( !icache_hit_c )
+            {
+                r_icache_miss_req = true;
+		r_vci_rsp_ins_ok = false;
+                r_icache_fsm = ICACHE_MISS_WAIT;
+                m_cpt_ins_miss++;
+            } 
+            else
+            {
+                r_icache_fsm = ICACHE_IDLE; 
+            }
+            irsp.valid = icache_hit_c;
+	    if (irsp.valid)
+	      assert((r_icache_vaddr_req.read() == ireq.addr) &&
+	          "vaddress should not be modified while ICACHE_BIS");
+            irsp.error = false;
+            irsp.instruction = icache_ins;
+	}
+	else	// modified or invalid
+	{
+            irsp.valid = false;
+            irsp.error = false;
+            irsp.instruction = 0;
+            r_icache_fsm = ICACHE_IDLE;
+	}
+        break;
+    }
+    //////////////////////
+    case ICACHE_TLB1_READ:
+    {
+        m_cost_ins_tlb_miss_frz++;
+
+        // external cache invalidate request
+        if ( r_tgt_icache_req )
+        {
+            r_icache_fsm = ICACHE_CC_INVAL;
+            r_icache_fsm_save = r_icache_fsm;
+            m_cost_ins_waste_wait_frz++;
+            break;
+        }
+
+        // external tlb invalidate request
+        if ( r_dcache_itlb_inval_req )
+        {
+	    r_itlb_inval_req = true;
+            r_icache_fsm = ICACHE_TLB_CC_INVAL;
+            r_icache_fsm_save = r_icache_fsm;
+            m_cost_ins_waste_wait_frz++;
+            break;
+        }
+
+	if ( !r_itlb_read_dcache_req )
+	{
+	    if (r_icache_vaddr_req.read() != ireq.addr || !ireq.valid) 
+	    {
+		/* request modified, drop response and restart */
+		r_icache_ptba_ok = false;
+            	if ( r_icache_inval_tlb_rsp )	r_icache_inval_tlb_rsp = false;
+                if ( r_dcache_rsp_itlb_error )	r_dcache_rsp_itlb_error = false;
+		r_icache_fsm = ICACHE_IDLE;
+		break;
+	    }
+
+            if ( !r_icache_inval_tlb_rsp ) // TLB miss read response and no invalidation
+            {
+                if ( !r_dcache_rsp_itlb_error ) // vci response ok
+                {  
+            	    if ( !(r_dcache_rsp_itlb_miss >> PTE_V_SHIFT) ) // unmapped
+            	    {
+                	r_icache_ptba_ok    = false;	
+                        r_icache_error_type = MMU_READ_PT1_UNMAPPED;  
+                        r_icache_bad_vaddr  = r_icache_vaddr_req.read();
+                        r_icache_fsm        = ICACHE_ERROR;
+            	    }
+            	    else if ( (r_dcache_rsp_itlb_miss & PTE_T_MASK ) >> PTE_T_SHIFT ) // PTD
+            	    {
+                	r_icache_ptba_ok       = true;	
+                        r_icache_ptba_save     = (paddr_t)(r_dcache_rsp_itlb_miss & ((1<<(m_paddr_nbits - PAGE_K_NBITS))-1)) << PAGE_K_NBITS; 
+                        r_icache_id1_save      = r_icache_vaddr_req.read() >> PAGE_M_NBITS;
+                        r_icache_paddr_save    = (paddr_t)(r_dcache_rsp_itlb_miss & ((1<<(m_paddr_nbits - PAGE_K_NBITS))-1)) << PAGE_K_NBITS |
+                                                 (paddr_t)(((r_icache_vaddr_req.read() & PTD_ID2_MASK) >> PAGE_K_NBITS) << 3); 
+                        r_itlb_read_dcache_req = true;
+			r_itlb_k_read_dcache   = true;
+                        r_icache_fsm           = ICACHE_TLB2_READ;
+             	    }	
+            	    else
+            	    {
+                	r_icache_ptba_ok = false;
+            
+            	        if ( (m_srcid_rw >> 4) == ((r_dcache_rsp_itlb_miss & ((1<<(m_paddr_nbits - PAGE_M_NBITS))-1)) >> (m_paddr_nbits - PAGE_M_NBITS -10)) ) // local
+            	        {
+            		    if ( (r_dcache_rsp_itlb_miss & PTE_L_MASK ) >> PTE_L_SHIFT ) // L bit is set
+            		    {
+                                r_icache_pte_update = r_dcache_rsp_itlb_miss;
+                                r_icache_fsm        = ICACHE_TLB1_UPDT;
+            		    }
+            		    else
+            		    {
+                                r_icache_pte_update   = r_dcache_rsp_itlb_miss | PTE_L_MASK;
+                                r_itlb_acc_dcache_req = true;
+                                r_icache_fsm          = ICACHE_TLB1_WRITE;
+                                m_cpt_ins_tlb_write_et++;
+            		    }
+                        }
+            	        else // remotely
+            	        {
+            		    if ( (r_dcache_rsp_itlb_miss & PTE_R_MASK ) >> PTE_R_SHIFT ) // R bit is set
+            		    {
+                                r_icache_pte_update = r_dcache_rsp_itlb_miss;
+                                r_icache_fsm        = ICACHE_TLB1_UPDT;
+            		    }
+            		    else
+            		    {
+                                r_icache_pte_update   = r_dcache_rsp_itlb_miss | PTE_R_MASK;
+                                r_itlb_acc_dcache_req = true;
+                                r_icache_fsm          = ICACHE_TLB1_WRITE;
+                                m_cpt_ins_tlb_write_et++;
+            		    }
+            	        }
+            	    }
+                }
+                else                        // vci response error
+                {  
+                    r_icache_fsm = ICACHE_ERROR;
+                    r_icache_error_type = MMU_READ_PT1_ILLEGAL_ACCESS;    
+                    r_icache_bad_vaddr = r_icache_vaddr_req.read();
+                }
+            }
+
+            if ( r_icache_inval_tlb_rsp ) // TLB miss read response and invalidation
+            {
+                if ( r_dcache_rsp_itlb_error ) 
+                {
+                    r_icache_inval_tlb_rsp = false;
+                    r_icache_error_type = MMU_READ_PT1_ILLEGAL_ACCESS;    
+                    r_icache_bad_vaddr = r_icache_vaddr_req.read();
+                    r_icache_fsm = ICACHE_ERROR;
+                } 
+                else 
+                {
+                    r_icache_inval_tlb_rsp = false;
+                    r_icache_fsm = ICACHE_IDLE;  
+                } 
+            }
+	}
+        break;
+    }
+    ///////////////////////
+    case ICACHE_TLB1_WRITE:  
+    {
+        m_cost_ins_tlb_miss_frz++;
+
+        // external cache invalidate request
+        if ( r_tgt_icache_req )
+        {
+            r_icache_fsm = ICACHE_CC_INVAL;
+            r_icache_fsm_save = r_icache_fsm;
+            m_cost_ins_waste_wait_frz++;
+            break;
+        }
+        // external tlb invalidate request
+        if ( r_dcache_itlb_inval_req )
+        {
+	    r_itlb_inval_req = true;
+            r_icache_fsm = ICACHE_TLB_CC_INVAL;
+            r_icache_fsm_save = r_icache_fsm;
+            m_cost_ins_waste_wait_frz++;
+            break;
+        }
+
+        if ( !r_itlb_acc_dcache_req ) // TLB access bits write response 
+	{        
+            if ( !r_icache_inval_tlb_rsp ) // TLB access bits write response and no invalidation        
+            { 
+                if ( r_dcache_rsp_itlb_error ) 
+                {
+                    r_icache_error_type = MMU_READ_PT1_ILLEGAL_ACCESS;  
+                    r_icache_bad_vaddr = r_icache_vaddr_req.read();
+                    r_icache_fsm = ICACHE_ERROR;
+                } 
+                else  
+                {
+                    r_icache_fsm = ICACHE_TLB1_UPDT;  
+                }
+            } 
+
+            if ( r_icache_inval_tlb_rsp) // TLB ET write response and invalidation     
+            {   
+                if ( r_dcache_rsp_itlb_error ) 
+                {
+                    r_icache_inval_tlb_rsp = false;
+                    r_icache_error_type = MMU_READ_PT1_ILLEGAL_ACCESS;  
+                    r_icache_bad_vaddr = r_icache_vaddr_req.read();
+                    r_icache_fsm = ICACHE_ERROR;
+                } 
+                else  
+                {
+                    r_icache_inval_tlb_rsp = false;
+                    r_icache_fsm = ICACHE_IDLE;    
+                }
+            }
+	}
+        break;
+    }
+    //////////////////////
+    case ICACHE_TLB1_UPDT:
+    {
+        m_cost_ins_tlb_miss_frz++;
+
+        // external cache invalidate request
+        if ( r_tgt_icache_req )
+        {
+            r_icache_fsm = ICACHE_CC_INVAL;
+            r_icache_fsm_save = r_icache_fsm;
+            m_cost_ins_waste_wait_frz++;
+            break;
+        }
+
+        // external tlb invalidate request
+        if ( r_dcache_itlb_inval_req ) 
+        {
+	    r_itlb_inval_req = true;
+            r_icache_fsm = ICACHE_TLB_CC_INVAL;
+            r_icache_fsm_save = r_icache_fsm;
+            m_cost_ins_waste_wait_frz++;
+            break;
+        }
+
+        // TLB update and invalidate different PTE
+        if ( !r_dcache_itlb_cleanup_req && !r_icache_inval_tlb_rsp )  
+        {
+            paddr_t victim_index = 0;
+            r_dcache_itlb_cleanup_req = icache_tlb.update(r_icache_pte_update,r_icache_vaddr_req.read(),(r_icache_paddr_save.read() >> (uint32_log2(m_dcache_words)+2)),&victim_index);
+            r_dcache_itlb_cleanup_line = victim_index;
+            r_icache_fsm = ICACHE_IDLE;
+        }
+
+        // TLB update and invalidate same PTE
+        if ( r_icache_inval_tlb_rsp )                                 
+        {
+            r_icache_inval_tlb_rsp = false;
+            r_icache_fsm = ICACHE_IDLE;
+        }
+        break;
+    }
+    /////////////////////
+    case ICACHE_TLB2_READ:
+    {
+        m_cost_ins_tlb_miss_frz++;
+
+        // external cache invalidate request
+        if ( r_tgt_icache_req )
+        {
+            r_icache_fsm = ICACHE_CC_INVAL;
+            r_icache_fsm_save = r_icache_fsm;
+            m_cost_ins_waste_wait_frz++;
+            break;
+        }
+
+        // external tlb invalidate request
+        if ( r_dcache_itlb_inval_req )
+        {
+	    r_itlb_inval_req = true;
+            r_icache_fsm = ICACHE_TLB_CC_INVAL;
+            r_icache_fsm_save = r_icache_fsm;
+            m_cost_ins_waste_wait_frz++;
+            break;
+        }
+
+        if ( !r_itlb_read_dcache_req  ) // TLB miss read response
+	{ 
+	    if (r_icache_vaddr_req.read() != ireq.addr || !ireq.valid) 
+	    {
+		/* request modified, drop response and restart */
+		r_icache_ptba_ok = false;
+            	if ( r_icache_inval_tlb_rsp )	r_icache_inval_tlb_rsp = false;
+                if ( r_dcache_rsp_itlb_error )	r_dcache_rsp_itlb_error = false;
+		r_icache_fsm = ICACHE_IDLE;
+		break;
+	    }
+
+            if ( !r_icache_inval_tlb_rsp ) // TLB miss read response 
+            {
+                if ( !r_dcache_rsp_itlb_error ) // VCI response ok        
+                {
+            	    if ( !(r_dcache_rsp_itlb_miss >> PTE_V_SHIFT) ) // unmapped
+            	    {
+                        r_icache_error_type = MMU_READ_PT2_UNMAPPED;  
+                        r_icache_bad_vaddr  = r_icache_vaddr_req.read();
+                        r_icache_fsm = ICACHE_ERROR;
+            	    }
+            	    else
+            	    {
+            	        if ( (m_srcid_rw >> 4) == ((r_dcache_rsp_itlb_miss & ((1<<(m_paddr_nbits - PAGE_M_NBITS))-1)) >> (m_paddr_nbits - PAGE_M_NBITS -10)) ) // local
+            	        {
+            		    if ( (r_dcache_rsp_itlb_miss & PTE_L_MASK ) >> PTE_L_SHIFT ) // L bit is set
+            		    {
+                        	r_icache_fsm        = ICACHE_TLB2_UPDT;
+                        	r_icache_pte_update = r_dcache_rsp_itlb_miss;
+            		    }
+            		    else
+            		    {
+                        	r_icache_pte_update   = r_dcache_rsp_itlb_miss | PTE_L_MASK;
+                        	r_itlb_acc_dcache_req = true;
+                        	r_icache_fsm          = ICACHE_TLB2_WRITE;
+                         	m_cpt_ins_tlb_write_et++;
+            		    }
+                        }
+            	    	else // remotely
+            	    	{
+            		    if ( (r_dcache_rsp_itlb_miss & PTE_R_MASK ) >> PTE_R_SHIFT ) // R bit is set
+            		    {
+                        	r_icache_fsm        = ICACHE_TLB2_UPDT;
+                        	r_icache_pte_update = r_dcache_rsp_itlb_miss;
+            		    }
+            		    else
+            		    {
+                        	r_icache_pte_update   = r_dcache_rsp_itlb_miss | PTE_R_MASK;
+                        	r_itlb_acc_dcache_req = true;
+                        	r_icache_fsm          = ICACHE_TLB2_WRITE;
+                        	m_cpt_ins_tlb_write_et++;
+            		    }
+            	        }
+            	    }
+                }
+                else                            // VCI response error        
+                {
+                    r_icache_error_type = MMU_READ_PT2_ILLEGAL_ACCESS;
+                    r_icache_bad_vaddr = r_icache_vaddr_req.read();
+                    r_icache_fsm = ICACHE_ERROR;
+                }
+            }
+            
+            if ( r_icache_inval_tlb_rsp ) // TLB miss read response and invalidation
+            {
+                if ( r_dcache_rsp_itlb_error ) 
+                {
+                    r_icache_inval_tlb_rsp = false;
+                    r_icache_error_type = MMU_READ_PT2_ILLEGAL_ACCESS;    
+                    r_icache_bad_vaddr = r_icache_vaddr_req.read();
+                    r_icache_fsm = ICACHE_ERROR;
+                } 
+                else 
+                {
+                    r_icache_inval_tlb_rsp = false;
+                    r_icache_fsm = ICACHE_IDLE;  
+                } 
+            }
+	}
+        break;
+    }
+    /////////////////////////
+    case ICACHE_TLB2_WRITE:
+    {  
+        m_cost_ins_tlb_miss_frz++;
+
+        // external cache invalidate request
+        if ( r_tgt_icache_req )
+        {
+            r_icache_fsm = ICACHE_CC_INVAL;
+            r_icache_fsm_save = r_icache_fsm;
+            m_cost_ins_waste_wait_frz++;
+            break;
+        }
+        // external tlb invalidate request
+        if ( r_dcache_itlb_inval_req )
+        {
+	    r_itlb_inval_req = true;
+            r_icache_fsm = ICACHE_TLB_CC_INVAL;
+            r_icache_fsm_save = r_icache_fsm;
+            m_cost_ins_waste_wait_frz++;
+            break;
+        }
+
+        if ( !r_itlb_acc_dcache_req ) // TLB access bits write response          
+	{
+            if ( !r_icache_inval_tlb_rsp ) // TLB access bits write response          
+            {
+                if ( r_dcache_rsp_itlb_error )             
+                {
+                    r_icache_error_type = MMU_READ_PT2_ILLEGAL_ACCESS;  
+                    r_icache_bad_vaddr = r_icache_vaddr_req.read();
+                    r_icache_fsm = ICACHE_ERROR;
+                } 
+                else  
+                {
+                    r_icache_fsm = ICACHE_TLB2_UPDT;  
+                }
+            }
+ 
+            if ( r_icache_inval_tlb_rsp ) // TLB ET write response and invalidation     
+            {   
+                if ( r_dcache_rsp_itlb_error ) 
+                {
+                    r_icache_inval_tlb_rsp = false;
+                    r_icache_error_type = MMU_READ_PT2_ILLEGAL_ACCESS;  
+                    r_icache_bad_vaddr = r_icache_vaddr_req.read();
+                    r_icache_fsm = ICACHE_ERROR;
+                } 
+                else  
+                {
+                    r_icache_inval_tlb_rsp = false;
+                    r_icache_fsm = ICACHE_IDLE;    
+                }
+            }
+	}
+        break;
+    }
+    /////////////////////
+    case ICACHE_TLB2_UPDT: 
+    {
+        m_cost_ins_tlb_miss_frz++;
+
+        // external cache invalidate request
+        if ( r_tgt_icache_req )
+        {
+            r_icache_fsm = ICACHE_CC_INVAL;
+            r_icache_fsm_save = r_icache_fsm;
+            m_cost_ins_waste_wait_frz++;
+            break;
+        }
+
+        // external tlb invalidate request
+        if ( r_dcache_itlb_inval_req ) 
+        {
+	    r_itlb_inval_req = true;
+            r_icache_fsm = ICACHE_TLB_CC_INVAL;
+            r_icache_fsm_save = r_icache_fsm;
+            m_cost_ins_waste_wait_frz++;
+            break;
+        }
+
+        // TLB update and invalidate different PTE
+        if ( !r_dcache_itlb_cleanup_req && !r_icache_inval_tlb_rsp ) 
+        {
+            paddr_t victim_index = 0;
+            r_dcache_itlb_cleanup_req = icache_tlb.update(r_icache_pte_update,r_dcache_rsp_itlb_ppn,r_icache_vaddr_req.read(),(r_icache_paddr_save.read() >> (uint32_log2(m_dcache_words)+2)),&victim_index);
+            r_dcache_itlb_cleanup_line = victim_index;
+            r_icache_fsm = ICACHE_IDLE;
+        }
+        // TLB update and invalidate same PTE
+        if ( r_icache_inval_tlb_rsp )                            
+        {
+            r_icache_inval_tlb_rsp = false;
+            r_icache_fsm = ICACHE_IDLE;
+        }
+        break;
+    }
+    /////////////////////////////
+    case ICACHE_SW_FLUSH:
+    {
+        size_t way = r_icache_way;
+        size_t set = r_icache_set;
+        bool clean = false;
+
+        if ( ireq.valid ) m_cost_ins_waste_wait_frz++;
+        m_cost_ins_tlb_sw_frz++;
+
+        // 4K page size TLB flush leads to cleanup req to data cache 
+        if ( !r_dcache_itlb_cleanup_req )    // last cleanup finish
+        {
+            paddr_t victim_index = 0;
+            for ( ; way < m_itlb_ways; way++)
+            {
+                for ( ; set < m_itlb_sets; set++)
+                {
+                    if(icache_tlb.checkcleanup(way, set, &victim_index))
+                    {
+                        clean = true;
+                        r_dcache_itlb_cleanup_req = true;
+                        r_dcache_itlb_cleanup_line = victim_index;
+                        r_icache_way = way + ((set+1)/m_itlb_sets);
+                        r_icache_set = (set+1) % m_itlb_sets;
+                        break;
+                    }
+                }
+                if (clean) break;
+            }
+
+            if (way == m_itlb_ways)
+            {
+                r_dcache_xtn_req = false;
+        	r_itlb_translation_valid = false;
+        	r_icache_ptba_ok = false;
+                r_icache_fsm = ICACHE_IDLE;
+                break;
+            }
+        }
+        break;
+    }
+    /////////////////////
+    case ICACHE_TLB_FLUSH:
+    {   
+        if ( ireq.valid ) m_cost_ins_waste_wait_frz++;
+
+        // data cache flush leads to ins tlb flush, flush all tlb entry 
+        icache_tlb.flush(true);    // global entries are invalidated
+        r_dcache_xtn_req = false;
+        r_itlb_translation_valid = false;
+        r_icache_ptba_ok = false;
+        r_icache_fsm = ICACHE_IDLE;
+        break;
+    }
+    ////////////////////////
+    case ICACHE_CACHE_FLUSH:
+    {
+        // external cache invalidate request
+        if ( r_tgt_icache_req )
+        {
+	    r_icache_fsm = ICACHE_CC_INVAL;
+    	    r_icache_fsm_save = r_icache_fsm;
+	    m_cost_ins_waste_wait_frz++;
+            break;	    
+        }
+
+        size_t way = r_icache_way;
+        size_t set = r_icache_set;
+        bool clean = false;
+
+        m_cost_ins_cache_flush_frz++;
+        if ( ireq.valid ) m_cost_ins_waste_wait_frz++;
+
+        // cache flush and send cleanup to external
+        if ( !r_icache_cleanup_req )
+        {
+            paddr_t victim_index = 0;
+            for ( ; way < m_icache_ways; way++ )
+            {    
+                for ( ; set < m_icache_sets; set++ )
+                {    
+                    if ( r_icache.flush(way, set, &victim_index) )
+                    {
+                        clean = true;
+                        r_icache_cleanup_req = true;
+                        r_icache_cleanup_line = victim_index;
+                        r_icache_way = way + ((set+1)/m_icache_sets);
+                        r_icache_set = (set+1) % m_icache_sets;
+                        break;
+                    }
+                }
+                if (clean) break;
+            }
+            if (way == m_icache_ways)
+            {
+                r_dcache_xtn_req = false;
+                r_icache_fsm = ICACHE_IDLE;
+                break;
+            }
+        }
+        break;
+    }
+    /////////////////////
+    case ICACHE_TLB_INVAL:  
+    {
+        if ( ireq.valid ) m_cost_ins_waste_wait_frz++;
+        paddr_t victim_index = 0;
+
+        if ( !r_dcache_itlb_cleanup_req )
+        {
+            r_dcache_itlb_cleanup_req = icache_tlb.inval(r_dcache_wdata_save, &victim_index);
+            r_dcache_itlb_cleanup_line = victim_index;
+            r_dcache_xtn_req = false;
+            r_itlb_translation_valid = false;
+            r_icache_ptba_ok = false;
+            r_icache_fsm = ICACHE_IDLE;
+        }
+        break;
+    }
+    ////////////////////////
+    case ICACHE_CACHE_INVAL:
+    {	
+        if ( ireq.valid ) m_cost_ins_waste_wait_frz++;
+        // external cache invalidate request
+        if ( r_tgt_icache_req )
+        {
+	    r_icache_fsm = ICACHE_CC_INVAL;
+    	    r_icache_fsm_save = r_icache_fsm;
+	    m_cost_ins_waste_wait_frz++;
+            break;	    
+        }
+
+        paddr_t ipaddr = 0;                     
+        bool    icache_hit_t = false;
+
+        if ( !r_icache_cleanup_req )
+        {    
+            if ( r_mmu_mode.read() & INS_TLB_MASK ) 
+            {
+                icache_hit_t = icache_tlb.translate(r_dcache_wdata_save, &ipaddr); 
+            } 
+            else 
+            {
+                ipaddr = (paddr_t)r_dcache_wdata_save;
+                icache_hit_t = true;
+            }
+            if ( icache_hit_t )
+            {
+                // invalidate and cleanup if necessary
+                r_icache_cleanup_req = r_icache.inval(ipaddr);
+                r_icache_cleanup_line = ipaddr >> (uint32_log2(m_icache_words) + 2);   
+            }
+            r_dcache_xtn_req = false; 
+            r_icache_fsm = ICACHE_IDLE;
+        }
+        break;
+    }
+    ////////////////////////
+    case ICACHE_CACHE_INVAL_PA:
+    {	
+	// external cache invalidate request
+        if ( r_tgt_icache_req )
+        {
+	    r_icache_fsm = ICACHE_CC_INVAL;
+    	    r_icache_fsm_save = r_icache_fsm;
+	    m_cost_ins_waste_wait_frz++;
+            break;	    
+        }    
+
+        paddr_t ipaddr = (paddr_t)r_mmu_word_hi.read() << 32 | r_mmu_word_lo.read();
+
+        if ( !r_icache_cleanup_req )
+        {    
+            // invalidate and cleanup if necessary
+            r_icache_cleanup_req = r_icache.inval(ipaddr);
+            r_icache_cleanup_line = ipaddr >> (uint32_log2(m_icache_words) + 2);   
+            r_dcache_xtn_req = false; 
+            r_icache_fsm = ICACHE_IDLE;
+        }
+        break;
+    }
+    ///////////////////////
+    case ICACHE_MISS_WAIT:
+    {
+        m_cost_ins_miss_frz++;
+
+        // external cache invalidate request
+        if ( r_tgt_icache_req )     
+        {
+            r_icache_fsm = ICACHE_CC_INVAL;
+            r_icache_fsm_save = r_icache_fsm;
+            m_cost_ins_waste_wait_frz++;
+            break;
+        }
+
+        // external tlb invalidate request
+        if ( r_dcache_itlb_inval_req )
+        {
+	    r_itlb_inval_req = true;
+            r_icache_fsm = ICACHE_TLB_CC_INVAL;
+            r_icache_fsm_save = r_icache_fsm;
+            m_cost_ins_waste_wait_frz++;
+            break;
+        }
+       
+	if ( r_vci_rsp_ins_ok )
+	{
+	    if ( r_vci_rsp_ins_error ) 
+            {
+                r_icache_error_type = MMU_READ_DATA_ILLEGAL_ACCESS; 
+                r_icache_bad_vaddr = ireq.addr;
+                r_icache_fsm = ICACHE_ERROR;
+
+            	if ( r_icache_inval_tlb_rsp ) r_icache_inval_tlb_rsp = false;
+            	if ( r_icache_inval_rsp ) r_icache_inval_rsp = false;
+		break;
+            }
+
+            if ( r_icache_inval_tlb_rsp ) // Miss read response and tlb invalidation
+            {
+		if ( r_icache_cleanup_req ) break;
+                r_icache_cleanup_req = true;
+                r_icache_cleanup_line = r_icache_paddr_save.read() >> (uint32_log2(m_icache_words) + 2);  
+                r_icache_fsm = ICACHE_IDLE;
+                r_icache_inval_tlb_rsp = false;
+                if ( r_icache_inval_rsp ) r_icache_inval_rsp = false;
+                m_cost_ins_tlb_miss_frz++;
+                break;
+            }
+	
+            if ( r_icache_inval_rsp ) // Miss read response and tlb invalidation
+            {
+		if ( r_icache_cleanup_req ) break;
+                r_icache_cleanup_req = true;
+                r_icache_cleanup_line = r_icache_paddr_save.read() >> (uint32_log2(m_icache_words) + 2);  
+                r_icache_fsm = ICACHE_IDLE;
+                r_icache_inval_rsp = false;
+                break;
+            }
+            r_icache_fsm = ICACHE_MISS_UPDT;  
+	}	
+        break;
+    }
+    ////////////////////
+    case ICACHE_UNC_WAIT:
+    {
+        m_cost_ins_miss_frz++;
+
+        // external cache invalidate request
+        if ( r_tgt_icache_req ) 
+        {
+            r_icache_fsm = ICACHE_CC_INVAL;
+            r_icache_fsm_save = r_icache_fsm;
+            m_cost_ins_waste_wait_frz++;
+            break;
+        }
+
+        // external tlb invalidate request
+        if ( r_dcache_itlb_inval_req )
+        {
+	    r_itlb_inval_req = true;
+            r_icache_fsm = ICACHE_TLB_CC_INVAL;
+            r_icache_fsm_save = r_icache_fsm;
+            m_cost_ins_waste_wait_frz++;
+            break;
+        }
+
+	if ( r_vci_rsp_ins_ok )
+	{
+	    if ( r_vci_rsp_ins_error ) 
+            {
+                r_icache_error_type = MMU_READ_DATA_ILLEGAL_ACCESS;    
+                r_icache_bad_vaddr = ireq.addr;
+                r_icache_fsm = ICACHE_ERROR;
+
+            	if ( r_icache_inval_tlb_rsp ) r_icache_inval_tlb_rsp = false;
+		break;
+            }
+
+	    if ( r_icache_inval_tlb_rsp ) // Miss read response and tlb invalidation
+            {
+                r_icache_inval_tlb_rsp = false;
+                r_icache_fsm = ICACHE_IDLE;
+		break;
+            }
+
+	    // Miss read response and no invalidation
+            r_icache_fsm = ICACHE_IDLE;
+	}	
+        break;
+    }
+    //////////////////////
+    case ICACHE_MISS_UPDT:
+    {
+        m_cost_ins_miss_frz++;
+
+        // external cache invalidate request
+        if ( r_tgt_icache_req )   
+        {
+            r_icache_fsm = ICACHE_CC_INVAL;
+            r_icache_fsm_save = r_icache_fsm;
+            m_cost_ins_waste_wait_frz++;
+            break;
+        }
+
+        // external tlb invalidate request
+        if ( r_dcache_itlb_inval_req )
+        {
+	    r_itlb_inval_req = true;
+            r_icache_fsm = ICACHE_TLB_CC_INVAL;
+            r_icache_fsm_save = r_icache_fsm;
+            m_cost_ins_waste_wait_frz++;
+            break;
+        }
+
+        if ( r_icache_inval_tlb_rsp ) // tlb invalidation
+        {
+            if ( r_icache_cleanup_req ) break;
+            r_icache_cleanup_req = true;
+            r_icache_cleanup_line = r_icache_paddr_save.read() >> (uint32_log2(m_icache_words) + 2);  
+            r_icache_inval_tlb_rsp = false;
+            if ( r_icache_inval_rsp ) r_icache_inval_rsp = false;
+            r_icache_fsm = ICACHE_IDLE;
+            m_cost_ins_tlb_miss_frz++;
+            break;
+        }
+
+        if ( !r_icache_cleanup_req ) // Miss update and no invalidation
+        {
+            if ( r_icache_inval_rsp ) // invalidation
+            {
+                r_icache_cleanup_req = true;
+                r_icache_cleanup_line = r_icache_paddr_save.read() >> (uint32_log2(m_icache_words) + 2);  
+                r_icache_fsm = ICACHE_IDLE;
+                r_icache_inval_rsp = false;
+            } 
+	    else
+	    {
+                data_t* buf = r_icache_miss_buf;
+                paddr_t  victim_index = 0;
+                m_cpt_icache_dir_write++;
+                m_cpt_icache_data_write++;
+
+                r_icache_cleanup_req = r_icache.update(r_icache_paddr_save.read(), buf, &victim_index);
+                r_icache_cleanup_line = victim_index;            
+
+                r_icache_fsm = ICACHE_IDLE;
+	    }
+        }
+        break;
+    }
+    ///////////////////
+    case ICACHE_ERROR:
+    {
+        r_vci_rsp_ins_error = false;
+        r_dcache_rsp_itlb_error = false;
+        irsp.valid = true;
+        irsp.error = true;
+        irsp.instruction = 0; 
+        r_icache_fsm = ICACHE_IDLE;
+        break;
+    }
+    /////////////////////
+    case ICACHE_CC_INVAL:  
+    {                       
+        if ( ireq.valid ) m_cost_ins_waste_wait_frz++;
+        m_cpt_icache_dir_read += m_icache_ways;
+
+        // invalidate cache
+        if( (( r_icache_fsm_save == ICACHE_MISS_WAIT ) || ( r_icache_fsm_save == ICACHE_MISS_UPDT ) /*|| 
+             ( r_icache_fsm_save == ICACHE_UNC_WAIT )*/ ) && 
+            ((r_icache_paddr_save.read() & ~((m_icache_words<<2)-1)) == (r_tgt_addr.read() & ~((m_icache_words<<2)-1))) ) 
+        {
+            r_icache_inval_rsp = true;
+	    r_tgt_icache_rsp = false;
+        } 
+        else 
+        {
+            r_tgt_icache_rsp = r_icache.inval(r_tgt_addr.read());
+        }
+        r_tgt_icache_req = false;
+        r_icache_fsm = r_icache_fsm_save;
+        break;
+    }
+    /////////////////////////
+    case ICACHE_TLB_CC_INVAL:
+    {
+        if ( ireq.valid ) m_cost_ins_waste_wait_frz++;        
+
+	if ( r_itlb_inval_req ) break;
+        // invalidate cache
+        if( (( r_icache_fsm_save == ICACHE_TLB1_READ ) || ( r_icache_fsm_save == ICACHE_TLB2_READ )  ||
+          /* ( r_icache_fsm_save == ICACHE_TLB1_WRITE )|| ( r_icache_fsm_save == ICACHE_TLB2_WRITE ) ||*/
+             ( r_icache_fsm_save == ICACHE_TLB1_UPDT ) || ( r_icache_fsm_save == ICACHE_TLB2_UPDT )) && 
+            (((r_icache_paddr_save.read() & ~((m_icache_words<<2)-1)) >> (uint32_log2(m_icache_words) + 2) ) == r_dcache_itlb_inval_line.read()) ) 
+        {
+            r_icache_inval_tlb_rsp = true;
+        } 
+        else if (((r_icache_fsm_save == ICACHE_BIS)||(r_icache_fsm_save == ICACHE_MISS_WAIT) ||
+              /*  (r_icache_fsm_save == ICACHE_UNC_WAIT)||*/(r_icache_fsm_save == ICACHE_MISS_UPDT)) && 
+                (r_icache_tlb_nline == r_dcache_itlb_inval_line))
+        {
+            r_icache_inval_tlb_rsp = true;
+        }
+	r_dcache_itlb_inval_req = false;
+        r_itlb_translation_valid = false;
+        r_icache_ptba_ok = false;
+        r_icache_fsm = r_icache_fsm_save;
+        break;
+    }
+    } // end switch r_icache_fsm
+
+#ifdef SOCLIB_MODULE_DEBUG
+    std::cout << name() << " Instruction Response: " << irsp << std::endl;
+#endif
+
+    ////////////////////////////////////////////////////////////////////////////////////
+    //      INVAL ITLB CHECK FSM 
+    ////////////////////////////////////////////////////////////////////////////////////////
+    switch(r_inval_itlb_fsm) {
+    /////////////////////
+    case INVAL_ITLB_IDLE:
+    {
+        if ( r_itlb_inval_req )
+        {
+            r_ccinval_itlb_way = 0; 
+            r_ccinval_itlb_set = 0;
+            r_inval_itlb_fsm = INVAL_ITLB_CHECK;   
+            m_cost_ins_tlb_inval_frz++; 
+        }   
+        break;
+    }
+    ////////////////////////////
+    case INVAL_ITLB_CHECK:
+    {
+        m_cost_ins_tlb_inval_frz++; 
+
+        size_t way = r_ccinval_itlb_way; 
+        size_t set = r_ccinval_itlb_set;
+        bool end = false;        
+        bool tlb_hit = icache_tlb.cccheck(r_dcache_itlb_inval_line.read(), way, set, &way, &set, &end); 
+    
+        if ( tlb_hit )
+        {
+            r_ccinval_itlb_way = way; 
+            r_ccinval_itlb_set = set;
+            r_itlb_cc_check_end = end;
+            r_inval_itlb_fsm = INVAL_ITLB_INVAL; 
+            m_cpt_ins_tlb_inval++;   
+        }        
+        else
+        {
+            r_inval_itlb_fsm = INVAL_ITLB_CLEAR;    
+        }
+        break;
+    }
+    /////////////////////////
+    case INVAL_ITLB_INVAL:
+    {
+        m_cost_ins_tlb_inval_frz++;
+ 
+        icache_tlb.ccinval(r_ccinval_itlb_way, r_ccinval_itlb_set);
+
+        if ( !r_itlb_cc_check_end )
+        {
+            r_inval_itlb_fsm = INVAL_ITLB_CHECK; 
+        }
+        else
+        {
+            r_inval_itlb_fsm = INVAL_ITLB_CLEAR;    
+        }
+        break;
+    }
+    ////////////////////
+    case INVAL_ITLB_CLEAR:
+    {
+        r_itlb_inval_req = false;
+        r_itlb_cc_check_end = false;
+        r_ccinval_itlb_way = 0; 
+        r_ccinval_itlb_set = 0; 
+        r_inval_itlb_fsm = INVAL_ITLB_IDLE;    
+        m_cost_ins_tlb_inval_frz++; 
+        break;
+    }
+    } // end switch r_inval_itlb_fsm
+
+    ////////////////////////////////////////////////////////////////////////////////////
+    //      DCACHE FSM 
+    //
+    // Both the Cacheability Table, and the MMU cached bit are used to define
+    // the cacheability.
+    // 
+    // There is 14 mutually exclusive conditions to exit the IDLE state.
+    // Seven configurations corresponding to an XTN request from processor:
+    // - Context switch => CTXT_SWITCH state
+    // - Flush dcache => DCACHE_FLUSH state 
+    // - Flush icache => ICACHE_FLUSH state 
+    // - Invalidate a dtlb entry => DTLB_INVAL state
+    // - Invalidate a itlb entry => ITLB_INVAL state
+    // - Invalidate a dcache line => DCACHE_INVAL state
+    // - Invalidate a icache line => ICACHE_INVAL state
+    // Seven configurations corresponding to various read miss or write requests: 
+    // - TLB miss(in case hit_p miss) => TLB1_READ state
+    // - TLB miss(in case hit_p hit) => TLB2_READ state
+    // - Hit in TLB but VPN changed => BIS state
+    // - Cached read miss => MISS_REQ state
+    // - Uncache read miss => UNC_REQ state
+    // - Write hit => WRITE_UPDT state
+    // - Write miss => WRITE_REQ
+    //
+    // The r_vci_rsp_data_error flip-flop is set by the VCI_RSP controller and reset 
+    // by DCACHE-FSM when its state is in DCACHE_ERROR. 
+    //--------------------------------------------------------------------- 
+    // Data TLB: 
+    //  
+    // - int        ET          (00: unmapped; 01: unused or PTD)
+    //                          (10: PTE new;  11: PTE old      )
+    // - bool       cachable    (cached bit)
+    // - bool       writable    (writable bit) 
+    // - bool       executable  (** not used alwayse false)
+    // - bool       user        (access in user mode allowed)
+    // - bool       global      (PTE not invalidated by a TLB flush)
+    // - bool       dirty       (page has been modified) 
+    // - uint32_t   vpn         (virtual page number)
+    // - uint32_t   ppn         (physical page number)
+    ////////////////////////////////////////////////////////////////////////////////////////
+
+    switch (r_dcache_fsm) {
+    //////////////////////
+    case DCACHE_WRITE_REQ:
+    {
+        // external cache invalidate request
+        if ( r_tgt_dcache_req ) 
+        {
+            r_dcache_fsm = DCACHE_CC_CHECK;
+            r_dcache_fsm_save = r_dcache_fsm;
+            if ( dreq.valid ) m_cost_data_waste_wait_frz++; 
+            break;
+        }
+
+	if ( !r_wbuf.wok(r_dcache_paddr_save) )
+        {
+            m_cost_write_frz++;
+            drsp.valid = false;
+            drsp.rdata = 0;
+            break;
+        }       
+        // The next state and the processor request parameters are computed 
+        // as in the DCACHE_IDLE state (see below ...)
+    }
+    /////////////////
+    case DCACHE_IDLE:
+    {
+        // external cache invalidate request
+        if ( r_tgt_dcache_req )   
+        {
+            r_dcache_fsm = DCACHE_CC_CHECK;
+            r_dcache_fsm_save = DCACHE_IDLE;
+            if ( dreq.valid ) m_cost_data_waste_wait_frz++;
+            break;
+        }        
+
+        // ins tlb cleanup
+        if ( r_dcache_itlb_cleanup_req )
+        {
+            r_dcache_fsm = DCACHE_ITLB_CLEANUP;
+            m_cpt_ins_tlb_cleanup++;
+            if ( dreq.valid ) m_cost_data_waste_wait_frz++;
+            break;
+        }    
+        // ins tlb miss
+    	if ( r_itlb_read_dcache_req )
+    	{
+            data_t rsp_itlb_miss;
+	    data_t rsp_itlb_ppn;
+
+    	    bool itlb_hit_dcache = r_dcache.read(r_icache_paddr_save, &rsp_itlb_miss);
+	    if ( r_itlb_k_read_dcache && itlb_hit_dcache )
+	    {	
+		r_itlb_k_read_dcache = false;
+	        bool itlb_hit_ppn = r_dcache.read(r_icache_paddr_save.read()+4, &rsp_itlb_ppn);
+		assert(itlb_hit_ppn && "Address of pte[64-32] and pte[31-0] should be successive");
+	    }
+
+            m_cpt_dcache_data_read += m_dcache_ways;
+            m_cpt_dcache_dir_read += m_dcache_ways;
+
+    	    if ( itlb_hit_dcache )  // ins TLB request hits in data cache 
+    	    {
+                r_dcache_rsp_itlb_miss = rsp_itlb_miss; 
+                r_dcache_rsp_itlb_ppn = rsp_itlb_ppn; 
+    	    	r_itlb_read_dcache_req = false;
+                r_dcache_fsm = DCACHE_IDLE;
+                
+                // set TLB bit if it's a PTE
+                if ( !((rsp_itlb_miss & PTE_T_MASK ) >> PTE_T_SHIFT) )
+                {
+                    r_dcache.setinbit(r_icache_paddr_save, r_dcache_in_itlb, true);
+                }
+    	    }
+    	    else                    // ins TLB request miss in data cache
+    	    {
+                r_dcache_itlb_read_req = true;
+		r_vci_rsp_data_ok = false;
+                r_dcache_fsm = DCACHE_ITLB_READ;
+            }
+            if ( dreq.valid ) m_cost_data_waste_wait_frz++; 
+    	}
+    	else if ( r_itlb_acc_dcache_req ) // ins tlb write access bit
+    	{
+            bool write_hit = r_dcache.write(r_icache_paddr_save, r_icache_pte_update);
+            assert(write_hit && "Write on miss ignores data");
+            r_dcache_itlb_ll_acc_req = true;
+	    r_vci_rsp_data_ok = false; 
+	    r_dcache_fsm = DCACHE_ITLB_LL_WAIT;	    		
+            if ( dreq.valid ) m_cost_data_waste_wait_frz++; 
+    	}
+        else if (dreq.valid) 
+        {
+            pte_info_t  dcache_pte_info;
+            int         xtn_opcod        = (int)dreq.addr/4;
+            paddr_t     tlb_dpaddr       = 0;        // physical address obtained from TLB
+            paddr_t     spc_dpaddr       = 0;        // physical adress obtained from PPN_save (speculative)
+            bool        dcache_hit_t     = false;    // hit on 4Kilo TLB
+            bool        dcache_hit_x     = false;    // VPN unmodified (can use spc_dpaddr)
+            bool        dcache_hit_p     = false;    // PTP unmodified (can skip first level page table walk)
+            bool        dcache_hit_c     = false;    // Cache hit
+            bool        dcache_cached    = false;    // cacheable access (read or write)
+            size_t      dcache_tlb_way   = 0;        // selected way (in case of cache hit)
+            size_t      dcache_tlb_set   = 0;        // selected set (Y field in address)
+            data_t      dcache_rdata     = 0;        // read data
+            paddr_t     dcache_tlb_nline = 0;       // TLB NLINE 
+
+            m_cpt_dcache_data_read += m_dcache_ways;
+            m_cpt_dcache_dir_read += m_dcache_ways;
+
+            // Decoding READ XTN requests from processor
+            // They are executed in this DCACHE_IDLE state
+
+            if (dreq.type == iss_t::XTN_READ) 
+            {
+                switch(xtn_opcod) {
+                case iss_t::XTN_INS_ERROR_TYPE:
+                    drsp.rdata = (uint32_t)r_icache_error_type;
+                    r_icache_error_type = MMU_NONE;
+                    drsp.valid = true;
+                    drsp.error = false;
+                    break;
+                case iss_t::XTN_DATA_ERROR_TYPE:
+                    drsp.rdata = (uint32_t)r_dcache_error_type;
+                    r_dcache_error_type = MMU_NONE;
+                    drsp.valid = true;
+                    drsp.error = false;
+                    break;
+                case iss_t::XTN_INS_BAD_VADDR:
+                    drsp.rdata = (uint32_t)r_icache_bad_vaddr;       
+                    drsp.valid = true;
+                    drsp.error = false;
+                    break;
+                case iss_t::XTN_DATA_BAD_VADDR:
+                    drsp.rdata = (uint32_t)r_dcache_bad_vaddr;        
+                    drsp.valid = true;
+                    drsp.error = false;
+                    break;
+                case iss_t::XTN_PTPR:
+                    drsp.rdata = (uint32_t)r_mmu_ptpr;
+                    drsp.valid = true;
+                    drsp.error = false;
+                    break;
+                case iss_t::XTN_TLB_MODE:
+                    drsp.rdata = (uint32_t)r_mmu_mode;
+                    drsp.valid = true;
+                    drsp.error = false;
+                    break;
+                case iss_t::XTN_MMU_PARAMS:
+                    drsp.rdata = (uint32_t)r_mmu_params;
+                    drsp.valid = true;
+                    drsp.error = false;
+                    break;
+                case iss_t::XTN_MMU_RELEASE:
+                    drsp.rdata = (uint32_t)r_mmu_release;
+                    drsp.valid = true;
+                    drsp.error = false;
+                    break;
+                case iss_t::XTN_MMU_WORD_LO:
+                    drsp.rdata = (uint32_t)r_mmu_word_lo;
+                    drsp.valid = true;
+                    drsp.error = false;
+                    break;
+                case iss_t::XTN_MMU_WORD_HI:
+                    drsp.rdata = (uint32_t)r_mmu_word_hi;
+                    drsp.valid = true;
+                    drsp.error = false;
+                    break;
+                default:
+                    r_dcache_error_type = MMU_READ_UNDEFINED_XTN; 
+                    r_dcache_bad_vaddr  = dreq.addr;
+                    drsp.valid = true;
+                    drsp.error = true;
+                    break;
+                }
+                r_dcache_fsm = DCACHE_IDLE;
+                break;
+            }
+
+            // Decoding WRITE XTN requests from processor
+            // If there is no privilege violation, they are not executed in this DCACHE_IDLE state,
+            // but in the next state, because they generally require access to the caches or the TLBs 
+
+            if (dreq.type == iss_t::XTN_WRITE) 
+            {
+                drsp.valid = false;
+                drsp.error = false;
+                drsp.rdata = 0;
+                r_dcache_wdata_save = dreq.wdata;   
+                switch(xtn_opcod) {     
+
+                case iss_t::XTN_PTPR:       // context switch : checking the kernel mode
+                                            // both instruction & data TLBs must be flushed
+                    if ((dreq.mode == iss_t::MODE_HYPER) || (dreq.mode == iss_t::MODE_KERNEL)) 
+                    {
+                        r_mmu_ptpr = dreq.wdata;
+                        r_icache_error_type = MMU_NONE;
+                        r_dcache_error_type = MMU_NONE;
+                        r_dcache_type_save = dreq.addr/4; 
+                        r_dcache_xtn_req = true;
+                        r_dcache_fsm = DCACHE_CTXT_SWITCH;
+                    } 
+                    else 
+                    { 
+                        r_dcache_error_type = MMU_WRITE_PRIVILEGE_VIOLATION; 
+                        r_dcache_bad_vaddr  = dreq.addr;
+                        drsp.valid = true;
+                        drsp.error = true;
+                	r_dcache_fsm = DCACHE_IDLE;
+                    }
+                    break;
+
+                case iss_t::XTN_TLB_MODE:     // modifying TLBs mode : checking the kernel mode
+                    if ((dreq.mode == iss_t::MODE_HYPER) || (dreq.mode == iss_t::MODE_KERNEL)) 
+                    {
+                        r_mmu_mode = (int)dreq.wdata;
+                        drsp.valid = true;
+                    } 
+                    else 
+                    {
+                        r_dcache_error_type = MMU_WRITE_PRIVILEGE_VIOLATION; 
+                        r_dcache_bad_vaddr  = dreq.addr;
+                        drsp.valid = true;
+                        drsp.error = true;
+                    }
+                    r_dcache_fsm = DCACHE_IDLE;
+                    break;
+
+                case iss_t::XTN_DTLB_INVAL:     //  checking the kernel mode
+                    if ((dreq.mode == iss_t::MODE_HYPER) || (dreq.mode == iss_t::MODE_KERNEL)) 
+                    {
+                        r_dcache_fsm = DCACHE_DTLB_INVAL;  
+                    } 
+                    else 
+                    {
+                        r_dcache_error_type = MMU_WRITE_PRIVILEGE_VIOLATION; 
+                        r_dcache_bad_vaddr  = dreq.addr;
+                        drsp.valid = true;
+                        drsp.error = true;
+                	r_dcache_fsm = DCACHE_IDLE;
+                    }
+                    break;
+
+                case iss_t::XTN_ITLB_INVAL:     //  checking the kernel mode
+                    if ((dreq.mode == iss_t::MODE_HYPER) || (dreq.mode == iss_t::MODE_KERNEL)) 
+                    {
+                        r_dcache_xtn_req = true;
+                        r_dcache_type_save = dreq.addr/4;
+                        r_dcache_fsm = DCACHE_ITLB_INVAL;  
+                    } 
+                    else 
+                    {
+                        r_dcache_error_type = MMU_WRITE_PRIVILEGE_VIOLATION; 
+                        r_dcache_bad_vaddr  = dreq.addr;
+                        drsp.valid = true;
+                        drsp.error = true;
+                	r_dcache_fsm = DCACHE_IDLE;
+                    }
+                    break;
+
+                case iss_t::XTN_DCACHE_INVAL:   // cache inval can be executed in user mode.
+                    r_dcache_fsm = DCACHE_DCACHE_INVAL;
+                    break;
+
+                case iss_t::XTN_MMU_DCACHE_PA_INV:   // cache inval can be executed in user mode.
+                    r_dcache_fsm = DCACHE_DCACHE_INVAL_PA;
+                    break;
+
+                case iss_t::XTN_DCACHE_FLUSH:   // cache flush can be executed in user mode.
+                    r_dcache_type_save = dreq.addr/4; 
+                    r_dcache_xtn_req = true;
+                    r_dcache_way = 0;
+                    r_dcache_set = 0;
+                    r_dcache_fsm = DCACHE_DCACHE_FLUSH; 
+                    break;
+
+                case iss_t::XTN_ICACHE_INVAL:   // cache inval can be executed in user mode.
+                    r_dcache_type_save = dreq.addr/4; 
+                    r_dcache_xtn_req = true;
+                    r_dcache_fsm = DCACHE_ICACHE_INVAL; 
+                    break;
+
+                case iss_t::XTN_MMU_ICACHE_PA_INV:   // cache inval can be executed in user mode.
+                    r_dcache_type_save = dreq.addr/4; 
+                    r_dcache_xtn_req = true;
+                    r_dcache_fsm = DCACHE_ICACHE_INVAL_PA; 
+                    break;
+
+                case iss_t::XTN_ICACHE_FLUSH:   // cache flush can be executed in user mode.
+                    r_dcache_type_save = dreq.addr/4; 
+                    r_dcache_xtn_req = true; 
+                    r_dcache_fsm = DCACHE_ICACHE_FLUSH;
+                    break;
+
+                case iss_t::XTN_SYNC:           // cache synchronization can be executed in user mode.
+                    if (r_wbuf.rok())
+                    {
+                        r_dcache_fsm = DCACHE_DCACHE_SYNC; 
+                    }
+                    else
+                    {
+                        drsp.valid = true;
+                        r_dcache_fsm = DCACHE_IDLE;
+                    }
+		    break;
+
+                case iss_t::XTN_MMU_WORD_LO: // modifying MMU misc registers
+                    if ((dreq.mode == iss_t::MODE_HYPER) || (dreq.mode == iss_t::MODE_KERNEL)) 
+                    {
+                        r_mmu_word_lo = (int)dreq.wdata;
+                        drsp.valid = true;
+                    } 
+                    else 
+                    {
+                        r_dcache_error_type = MMU_WRITE_PRIVILEGE_VIOLATION; 
+                        r_dcache_bad_vaddr  = dreq.addr;
+                        drsp.valid = true;
+                        drsp.error = true;
+                    }
+                    r_dcache_fsm = DCACHE_IDLE;
+                    break;
+
+                case iss_t::XTN_MMU_WORD_HI: // modifying MMU misc registers
+                    if ((dreq.mode == iss_t::MODE_HYPER) || (dreq.mode == iss_t::MODE_KERNEL)) 
+                    {
+                        r_mmu_word_hi = (int)dreq.wdata;
+                        drsp.valid = true;
+                    } 
+                    else 
+                    {
+                        r_dcache_error_type = MMU_WRITE_PRIVILEGE_VIOLATION; 
+                        r_dcache_bad_vaddr  = dreq.addr;
+                        drsp.valid = true;
+                        drsp.error = true;
+                    }
+                    r_dcache_fsm = DCACHE_IDLE;
+                    break;
+
+		  case iss_t::XTN_ICACHE_PREFETCH:
+		  case iss_t::XTN_DCACHE_PREFETCH:
+		    drsp.valid = true;
+                    drsp.error = false;
+		    break;
+	
+                default:
+                    r_dcache_error_type = MMU_WRITE_UNDEFINED_XTN; 
+                    r_dcache_bad_vaddr  = dreq.addr;
+                    drsp.valid = true;
+                    drsp.error = true;
+                    r_dcache_fsm = DCACHE_IDLE;
+                    break;
+                } // end switch xtn_opcod
+
+                break;
+            } // end if XTN_WRITE
+
+            // Evaluating dcache_hit_t, dcache_hit_x, dcache_hit_p, dcache_hit_c,
+            // dcache_pte_info, dcache_tlb_way, dcache_tlb_set & dpaddr & cacheability 
+            // - If MMU activated : cacheability is defined by the cachable bit in the TLB
+            // - If MMU not activated : cacheability is defined by the segment table.
+
+            if ( !(r_mmu_mode.read() & DATA_TLB_MASK) ) // MMU not activated
+            {
+                dcache_hit_t  = true;       
+                dcache_hit_x  = true;   
+                dcache_hit_p  = true;  
+                tlb_dpaddr    = dreq.addr; 
+                spc_dpaddr    = dreq.addr;    
+                dcache_cached = m_cacheability_table[dreq.addr] && 
+                                ((dreq.type != iss_t::DATA_LL)  && (dreq.type != iss_t::DATA_SC) &&
+                                 (dreq.type != iss_t::XTN_READ) && (dreq.type != iss_t::XTN_WRITE));     
+            } 
+            else                                                            // MMU activated
+            {
+                m_cpt_data_tlb_read++;
+                dcache_hit_t  = dcache_tlb.cctranslate(dreq.addr, &tlb_dpaddr, &dcache_pte_info, 
+                                                       &dcache_tlb_nline, &dcache_tlb_way, &dcache_tlb_set);                  
+                dcache_hit_x  = (((vaddr_t)r_dcache_vpn_save << PAGE_K_NBITS) == (dreq.addr & ~PAGE_K_MASK)) && r_dtlb_translation_valid; 
+                dcache_hit_p  = (((dreq.addr >> PAGE_M_NBITS) == r_dcache_id1_save) && r_dcache_ptba_ok );
+                spc_dpaddr    = ((paddr_t)r_dcache_ppn_save << PAGE_K_NBITS) | (paddr_t)((dreq.addr & PAGE_K_MASK));
+                dcache_cached = dcache_pte_info.c && 
+                                ((dreq.type != iss_t::DATA_LL)  && (dreq.type != iss_t::DATA_SC) &&
+                                 (dreq.type != iss_t::XTN_READ) && (dreq.type != iss_t::XTN_WRITE));    
+            }
+
+            if ( !(r_mmu_mode.read() & DATA_CACHE_MASK) )   // cache not actived
+            {
+                dcache_cached = false;
+            }
+
+            // dcache_hit_c & dcache_rdata
+            if ( dcache_cached )    // using speculative physical address for cached access
+            {
+                dcache_hit_c = r_dcache.read(spc_dpaddr, &dcache_rdata);
+            } 
+            else                    // using actual physical address for uncached access
+            {
+                dcache_hit_c = ((tlb_dpaddr == (paddr_t)r_dcache_paddr_save) && r_vci_rsp_data_ok ); 
+                dcache_rdata = r_dcache_miss_buf[0];
+            }
+
+            if ( r_mmu_mode.read() & DATA_TLB_MASK ) 
+            {
+                // Checking access rights
+                if ( dcache_hit_t ) 
+                {
+                    if (!dcache_pte_info.u && (dreq.mode == iss_t::MODE_USER)) 
+                    {
+                        if ((dreq.type == iss_t::DATA_READ)||(dreq.type == iss_t::DATA_LL))
+                        {
+                            r_dcache_error_type = MMU_READ_PRIVILEGE_VIOLATION;
+                        }
+                        else /*if ((dreq.type == iss_t::DATA_WRITE)||(dreq.type == iss_t::DATA_SC))*/
+                        {
+                            r_dcache_error_type = MMU_WRITE_PRIVILEGE_VIOLATION;
+                        }  
+                        r_dcache_bad_vaddr = dreq.addr;
+                        drsp.valid = true;
+                        drsp.error = true;
+                        drsp.rdata = 0;
+                        r_dcache_fsm = DCACHE_IDLE;
+                        break;
+                    }
+                    if (!dcache_pte_info.w && ((dreq.type == iss_t::DATA_WRITE)||(dreq.type == iss_t::DATA_SC))) 
+                    {
+                        r_dcache_error_type = MMU_WRITE_ACCES_VIOLATION;  
+                        r_dcache_bad_vaddr = dreq.addr;
+                        drsp.valid = true;
+                        drsp.error = true;
+                        drsp.rdata = 0;
+                        r_dcache_fsm = DCACHE_IDLE;
+                        break;
+                    }
+                }
+
+                // update LRU, save ppn, vpn and page type
+                if ( dcache_hit_t ) {
+                    dcache_tlb.setlru(dcache_tlb_way,dcache_tlb_set); 
+                    r_dcache_ppn_save = tlb_dpaddr >> PAGE_K_NBITS;
+                    r_dcache_vpn_save = dreq.addr >> PAGE_K_NBITS;
+                    r_dcache_tlb_nline = dcache_tlb_nline;
+                    r_dtlb_translation_valid = true;
+                }
+                else
+                {
+                    r_dtlb_translation_valid = false;
+                }
+
+            } // end if MMU activated
+
+            // compute next state 
+            if ( !dcache_hit_p && !dcache_hit_t )  // TLB miss
+            {
+                r_dcache_tlb_paddr = (paddr_t)r_mmu_ptpr << (INDEX1_NBITS+2) | (paddr_t)((dreq.addr>>PAGE_M_NBITS)<<2);
+                r_dcache_fsm = DCACHE_DTLB1_READ_CACHE;
+                m_cpt_data_tlb_miss++;
+                m_cost_data_tlb_miss_frz++;
+            }
+            else if ( dcache_hit_p && !dcache_hit_t )  // TLB Miss with possibility of bypass first level page
+            {
+                // walk page table level 2
+                r_dcache_tlb_paddr = (paddr_t)r_dcache_ptba_save | 
+                                     (paddr_t)(((dreq.addr&PTD_ID2_MASK)>>PAGE_K_NBITS) << 3); 
+                r_dcache_fsm = DCACHE_DTLB2_READ_CACHE;
+                m_cpt_data_tlb_miss++;
+                m_cost_data_tlb_miss_frz++;
+            }
+            else if ( dcache_hit_t && !dcache_hit_x && dcache_cached )// cached access with an ucorrect speculative physical address
+            {
+                r_dcache_hit_p_save = dcache_hit_p;
+                r_dcache_fsm = DCACHE_BIS;
+                m_cost_data_miss_frz++;
+            }
+            else  // cached or uncached access with a correct speculative physical address
+            {
+                switch( dreq.type ) {
+                    case iss_t::DATA_READ:
+                    case iss_t::DATA_LL:
+                    case iss_t::DATA_SC:
+                        m_cpt_read++;
+                        if ( dcache_hit_c ) 
+                        {
+                            r_vci_rsp_data_ok = false;
+                            r_dcache_fsm = DCACHE_IDLE;
+                            drsp.valid = true;
+                            drsp.rdata = dcache_rdata;
+                        } 
+                        else 
+                        {
+                            if ( dcache_cached ) 
+                            {
+                                r_dcache_miss_req = true;
+				r_vci_rsp_data_ok = false;
+                                r_dcache_fsm = DCACHE_MISS_WAIT;
+                                m_cpt_data_miss++;
+                                m_cost_data_miss_frz++;
+                            } 
+                            else 
+                            {
+                                r_dcache_unc_req = true;
+				r_vci_rsp_data_ok = false;
+                                r_dcache_fsm = DCACHE_UNC_WAIT;
+                                m_cpt_unc_read++;
+                                m_cost_unc_read_frz++;
+                            }
+                        }
+                        break;
+/*
+                    case iss_t::DATA_READ:
+                        m_cpt_read++;
+                        if ( dcache_hit_c ) 
+                        {
+                            r_dcache_buf_unc_valid = false;
+                            r_dcache_fsm = DCACHE_IDLE;
+                            drsp.valid = true;
+                            drsp.rdata = dcache_rdata;
+                        } 
+                        else 
+                        {
+                            if ( dcache_cached ) 
+                            {
+                                r_dcache_miss_req = true;
+                                r_dcache_fsm = DCACHE_MISS_WAIT;
+                                m_cpt_data_miss++;
+                                m_cost_data_miss_frz++;
+                            } 
+                            else 
+                            {
+                                r_dcache_unc_req = true;
+                                r_dcache_fsm = DCACHE_UNC_WAIT;
+                                m_cpt_unc_read++;
+                                m_cost_unc_read_frz++;
+                            }
+                        }
+                        break;
+                    case iss_t::DATA_LL:
+			if (r_dcache_llsc_reserved && (r_dcache_llsc_addr_save == tlb_dpaddr) && r_dcache_buf_unc_valid)
+			{
+                            r_dcache_buf_unc_valid = false;
+                            r_dcache_fsm = DCACHE_IDLE;
+                            drsp.valid = true;
+                            drsp.rdata = dcache_rdata;
+			}
+			else
+			{
+			    r_dcache_llsc_reserved = true;
+			    r_dcache_llsc_addr_save = tlb_dpaddr;
+                            r_dcache_unc_req = true;
+                            r_dcache_fsm = DCACHE_UNC_WAIT;
+			}
+			break;
+                    case iss_t::DATA_SC:
+			if (r_dcache_llsc_reserved && (r_dcache_llsc_addr_save == tlb_dpaddr))
+			{
+			    r_dcache_llsc_reserved = false;
+                            r_dcache_unc_req = true;
+                            r_dcache_fsm = DCACHE_UNC_WAIT;
+			}
+			else
+			{   
+			    if ( r_dcache_buf_unc_valid )
+			    {                         
+			        r_dcache_llsc_reserved = false;
+			        r_dcache_buf_unc_valid = false;
+                                drsp.valid = true;
+                                drsp.rdata = dcache_rdata;
+			    }
+                            r_dcache_fsm = DCACHE_IDLE;
+			}			
+			break;
+*/
+                    case iss_t::DATA_WRITE:
+                        m_cpt_write++;
+                        if ( dcache_cached ) m_cpt_write_cached++;
+
+                        if ( dcache_hit_c && dcache_cached )    // cache update required
+                        {
+                            r_dcache_fsm = DCACHE_WRITE_UPDT;
+                        } 
+                        else if ( !dcache_pte_info.d && (r_mmu_mode.read() & DATA_TLB_MASK) )   // dirty bit update required
+                        {
+                            if ( dcache_tlb.getpagesize(dcache_tlb_way, dcache_tlb_set) )	// 2M page size, one level page table 
+                            {
+                                r_dcache_pte_update = dcache_tlb.getpte(dcache_tlb_way, dcache_tlb_set) | PTE_D_MASK;
+                                r_dcache_tlb_paddr = (paddr_t)r_mmu_ptpr << (INDEX1_NBITS+2) | (paddr_t)((dreq.addr>>PAGE_M_NBITS)<<2);
+                                r_dcache_tlb_ll_dirty_req = true;
+				r_vci_rsp_data_ok = false;
+                                r_dcache_fsm = DCACHE_LL_DIRTY_WAIT;
+                                m_cpt_data_tlb_write_dirty++;
+                            }
+                            else	// 4k page size, two levels page table 
+                            {   
+                                if (dcache_hit_p) 
+                                {
+                                    r_dcache_pte_update = dcache_tlb.getpte(dcache_tlb_way, dcache_tlb_set) | PTE_D_MASK;
+                                    r_dcache_tlb_paddr = (paddr_t)r_dcache_ptba_save | (paddr_t)(((dreq.addr&PTD_ID2_MASK)>>PAGE_K_NBITS) << 3);
+                                    r_dcache_tlb_ll_dirty_req = true;
+				    r_vci_rsp_data_ok = false;
+                                    r_dcache_fsm = DCACHE_LL_DIRTY_WAIT;
+                                    m_cpt_data_tlb_write_dirty++;
+                                }
+                                else    // get PTBA to calculate the physical address of PTE
+                                {
+                                    r_dcache_pte_update = dcache_tlb.getpte(dcache_tlb_way, dcache_tlb_set) | PTE_D_MASK;
+                                    r_dcache_tlb_paddr = (paddr_t)r_mmu_ptpr << (INDEX1_NBITS+2) | (paddr_t)((dreq.addr>>PAGE_M_NBITS)<<2);
+                                    r_dcache_tlb_ptba_read = true;
+                                    r_dcache_fsm = DCACHE_DTLB1_READ_CACHE;
+                                }
+                            }
+                            m_cost_data_tlb_miss_frz++;
+                        }
+                        else                                    // no cache update, not dirty bit update
+                        {
+                            r_dcache_fsm = DCACHE_WRITE_REQ;
+                            drsp.valid = true;
+                            drsp.rdata = 0;
+                        }
+                        break;
+                    default:
+                        break;
+                } // end switch dreq.type
+            } // end if next states
+
+            // save values for the next states
+            r_dcache_paddr_save   = tlb_dpaddr;
+            r_dcache_type_save    = dreq.type;
+            r_dcache_wdata_save   = dreq.wdata;
+            r_dcache_be_save      = dreq.be;
+            r_dcache_rdata_save   = dcache_rdata;
+            r_dcache_cached_save  = dcache_cached;
+            r_dcache_dirty_save   = dcache_pte_info.d;
+            r_dcache_tlb_set_save = dcache_tlb_set;
+            r_dcache_tlb_way_save = dcache_tlb_way;
+
+        } // end if dreq.valid
+        else 
+        {   
+            r_dcache_fsm = DCACHE_IDLE;
+        }
+        break;
+    }
+    /////////////////
+    case DCACHE_BIS:
+    {
+        // external cache invalidate request
+        if ( r_tgt_dcache_req )   
+        {
+            r_dcache_fsm = DCACHE_CC_CHECK;
+            r_dcache_fsm_save = r_dcache_fsm;
+            m_cost_data_waste_wait_frz++;
+            break;
+        }
+
+        // Using tlb entry is invalidated 
+        if ( r_dcache_inval_tlb_rsp )
+        {
+            r_dcache_inval_tlb_rsp = false;
+            r_dcache_fsm = DCACHE_IDLE;
+            m_cost_data_tlb_miss_frz++;
+            break;
+        }
+
+        data_t  dcache_rdata = 0;
+        bool    dcache_hit_c = false;
+        bool    dcache_hit_t = false;
+        paddr_t tlb_dpaddr   = 0;
+
+	dcache_hit_t = dcache_tlb.translate(dreq.addr, &tlb_dpaddr);
+
+	if ( (tlb_dpaddr == r_dcache_paddr_save.read()) && dreq.valid && dcache_hit_t ) 
+	{
+	    // acces always cached in this state
+	    dcache_hit_c = r_dcache.read(r_dcache_paddr_save, &dcache_rdata);
+	    
+	    if ( dreq.type == iss_t::DATA_READ )  // cached read
+	    {
+	        m_cpt_read++;
+	        if ( !dcache_hit_c ) 
+	        {
+	            r_dcache_miss_req = true;
+		    r_vci_rsp_data_ok = false;
+	            r_dcache_fsm = DCACHE_MISS_WAIT;
+	            m_cpt_data_miss++;
+	            m_cost_data_miss_frz++;
+	        }
+	        else
+	        {
+	            r_dcache_fsm = DCACHE_IDLE;
+	        }
+	        drsp.valid = dcache_hit_c;
+	        drsp.error = false;
+	        drsp.rdata = dcache_rdata;
+	    }
+	    else    // cached write
+	    {
+	        m_cpt_write++;
+	        m_cpt_write_cached++;
+	        if ( dcache_hit_c )    // cache update required
+	        {
+	            r_dcache_rdata_save = dcache_rdata;
+	            r_dcache_fsm = DCACHE_WRITE_UPDT;
+	        } 
+	        else if (!r_dcache_dirty_save && (r_mmu_mode.read() & DATA_TLB_MASK))   // dirty bit update required
+	        {
+	            if (dcache_tlb.getpagesize(r_dcache_tlb_way_save, r_dcache_tlb_set_save)) 
+	            {
+	                r_dcache_pte_update = dcache_tlb.getpte(r_dcache_tlb_way_save, r_dcache_tlb_set_save) | PTE_D_MASK;
+	                r_dcache_tlb_paddr = (paddr_t)r_mmu_ptpr << (INDEX1_NBITS+2) | (paddr_t)((dreq.addr>>PAGE_M_NBITS)<<2);
+	                r_dcache_tlb_ll_dirty_req = true;
+			r_vci_rsp_data_ok = false;
+	                r_dcache_fsm = DCACHE_LL_DIRTY_WAIT;
+	                m_cpt_data_tlb_write_dirty++;
+	            }
+	            else
+	            {   
+	                if (r_dcache_hit_p_save) 
+	                {
+	                    r_dcache_pte_update = dcache_tlb.getpte(r_dcache_tlb_way_save, r_dcache_tlb_set_save) | PTE_D_MASK;
+	                    r_dcache_tlb_paddr = (paddr_t)r_dcache_ptba_save|(paddr_t)(((dreq.addr&PTD_ID2_MASK)>>PAGE_K_NBITS) << 3);
+	                    r_dcache_tlb_ll_dirty_req = true;
+			    r_vci_rsp_data_ok = false;
+	                    r_dcache_fsm = DCACHE_LL_DIRTY_WAIT;
+	                    m_cpt_data_tlb_write_dirty++;
+	                }
+	                else
+	                {
+	                    r_dcache_pte_update = dcache_tlb.getpte(r_dcache_tlb_way_save, r_dcache_tlb_set_save) | PTE_D_MASK;
+	                    r_dcache_tlb_paddr = (paddr_t)r_mmu_ptpr << (INDEX1_NBITS+2) | (paddr_t)((dreq.addr>>PAGE_M_NBITS)<<2);
+	                    r_dcache_tlb_ptba_read = true;
+	                    r_dcache_fsm = DCACHE_DTLB1_READ_CACHE;
+	                }
+	            }
+	            m_cost_data_tlb_miss_frz++;
+	        }
+	        else                                    // no cache update, not dirty bit update
+	        {
+	            r_dcache_fsm = DCACHE_WRITE_REQ;
+	            drsp.valid = true;
+	            drsp.rdata = 0;
+	        }
+	    }
+	}
+	else
+	{
+            drsp.valid = false;
+            drsp.error = false;
+            drsp.rdata = 0;
+            r_dcache_fsm = DCACHE_IDLE;
+	}
+        break;
+    }
+    //////////////////////////
+    case DCACHE_LL_DIRTY_WAIT:
+    {
+        // external cache invalidate request
+        if ( r_tgt_dcache_req )   
+        {
+            r_dcache_fsm = DCACHE_CC_CHECK;
+            r_dcache_fsm_save = r_dcache_fsm;
+            m_cost_data_waste_wait_frz++;
+            break;
+        }
+
+	if ( r_vci_rsp_data_ok )
+	{
+            if ( r_vci_rsp_data_error ) // VCI response ko
+            {
+		if (dcache_tlb.getpagesize(r_dcache_tlb_way_save, r_dcache_tlb_set_save)) 
+		{
+                    r_dcache_error_type = MMU_WRITE_PT1_ILLEGAL_ACCESS;     
+		}
+		else
+		{
+                    r_dcache_error_type = MMU_WRITE_PT2_ILLEGAL_ACCESS;     
+		}
+                r_dcache_bad_vaddr = dreq.addr;
+                r_dcache_fsm = DCACHE_ERROR; 
+
+		if (r_dcache_inval_tlb_rsp) r_dcache_inval_tlb_rsp = false;
+		if (r_dcache_inval_rsp) r_dcache_inval_rsp = false;
+            }
+	    else
+	    {
+		if ( !(r_dcache_miss_buf[0] >> PTE_V_SHIFT) )	// unmapped
+	        {
+		    if (dcache_tlb.getpagesize(r_dcache_tlb_way_save, r_dcache_tlb_set_save))
+		    { 
+			r_dcache_error_type = MMU_WRITE_PT1_UNMAPPED;       
+		    }
+		    else
+		    {
+			r_dcache_error_type = MMU_WRITE_PT2_UNMAPPED;       
+	  	    }
+                    r_dcache_bad_vaddr = dreq.addr;
+                    r_dcache_fsm = DCACHE_ERROR;
+
+		    if (r_dcache_inval_tlb_rsp) r_dcache_inval_tlb_rsp = false;
+		    if (r_dcache_inval_rsp) r_dcache_inval_rsp = false;
+	        }
+        	else if ( r_dcache_inval_tlb_rsp )
+        	{
+        	    r_dcache_inval_tlb_rsp = false;
+        	    r_dcache_fsm = DCACHE_IDLE;
+        	    m_cost_data_tlb_miss_frz++;
+        	}
+		else if ( r_dcache_inval_rsp )
+		{
+        	    r_dcache_inval_rsp = false;
+		    r_dcache_fsm = DCACHE_IDLE;
+		}
+		else
+		{
+		    r_dcache_tlb_sc_dirty_req = true;
+		    r_vci_rsp_data_ok = false;
+		    r_dcache_pte_update = r_dcache_miss_buf[0] | r_dcache_pte_update.read();
+                    r_dcache_fsm = DCACHE_SC_DIRTY_WAIT; 
+		}
+	    }
+	}
+	break;
+    }
+    //////////////////////////
+    case DCACHE_SC_DIRTY_WAIT:
+    {
+        // external cache invalidate request
+        if ( r_tgt_dcache_req )   
+        {
+            r_dcache_fsm = DCACHE_CC_CHECK;
+            r_dcache_fsm_save = r_dcache_fsm;
+            m_cost_data_waste_wait_frz++;
+            break;
+        }
+
+	if ( r_vci_rsp_data_ok )
+	{
+	    if ( r_vci_rsp_data_error ) // VCI response ko
+	    {
+	        if (dcache_tlb.getpagesize(r_dcache_tlb_way_save, r_dcache_tlb_set_save))
+	        {
+	            r_dcache_error_type = MMU_WRITE_PT1_ILLEGAL_ACCESS;    
+	        }
+	        else
+	        {
+	            r_dcache_error_type = MMU_WRITE_PT2_ILLEGAL_ACCESS;    
+	        }
+	        r_dcache_bad_vaddr = dreq.addr;
+	        r_dcache_fsm = DCACHE_ERROR;
+
+		if (r_dcache_inval_tlb_rsp) r_dcache_inval_tlb_rsp = false;
+		if (r_dcache_inval_rsp) r_dcache_inval_rsp = false;		 	    
+	    }
+	    else 
+	    {
+                // Using tlb entry is invalidated 
+                if ( r_dcache_inval_tlb_rsp )
+                {
+                    r_dcache_inval_tlb_rsp = false;
+                    r_dcache_fsm = DCACHE_IDLE;
+		    if ( r_dcache_tlb_sc_fail ) r_dcache_tlb_sc_fail = false;
+                    m_cost_data_tlb_miss_frz++;
+                }
+		else if ( r_dcache_inval_rsp )
+		{
+        	    r_dcache_inval_rsp = false;
+		    r_dcache_fsm = DCACHE_IDLE;
+		    if ( r_dcache_tlb_sc_fail ) r_dcache_tlb_sc_fail = false;
+		}
+		else if ( r_dcache_tlb_sc_fail )
+	        {
+		    r_dcache_tlb_ll_dirty_req = true;
+		    r_vci_rsp_data_ok = false;
+		    r_dcache_tlb_sc_fail = false;
+	            r_dcache_fsm = DCACHE_LL_DIRTY_WAIT; 
+	        }
+		else
+		{
+		    r_vci_rsp_data_ok = false;	
+	            r_dcache_fsm = DCACHE_WRITE_DIRTY; 
+		}
+	    }
+	}
+	break;
+    }
+    ////////////////////////////
+    case DCACHE_DTLB1_READ_CACHE:
+    {
+        m_cost_data_tlb_miss_frz++;
+
+        // external cache invalidate request
+        if ( r_tgt_dcache_req )   
+        {
+            r_dcache_fsm = DCACHE_CC_CHECK;
+            r_dcache_fsm_save = r_dcache_fsm;
+            m_cost_data_waste_wait_frz++;
+            break;
+        }        
+
+        // Using tlb entry is invalidated 
+        if ( r_dcache_inval_tlb_rsp )
+        {
+            r_dcache_inval_tlb_rsp = false;
+            r_dcache_fsm = DCACHE_IDLE;
+            m_cost_data_tlb_miss_frz++;
+            break;
+        }
+
+        data_t tlb_data = 0;
+	bool write_hit = false;
+        bool tlb_hit_cache = r_dcache.read(r_dcache_tlb_paddr, &tlb_data);
+
+        // DTLB request hit in cache
+        if ( tlb_hit_cache )
+        {
+	    if ( !(tlb_data >> PTE_V_SHIFT) )	// unmapped
+	    {
+                r_dcache_ptba_ok    = false;
+                if ((r_dcache_type_save == iss_t::DATA_READ)||(r_dcache_type_save == iss_t::DATA_LL))
+                {
+                    r_dcache_error_type = MMU_READ_PT1_UNMAPPED;
+                }
+                else /*if ((dreq.type == iss_t::DATA_WRITE)||(dreq.type == iss_t::DATA_SC))*/
+                {
+                    r_dcache_error_type = MMU_WRITE_PT1_UNMAPPED;
+                }  
+                r_dcache_bad_vaddr  = dreq.addr;
+                r_dcache_fsm        = DCACHE_ERROR;
+	    }
+	    else if ( (tlb_data & PTE_T_MASK) >> PTE_T_SHIFT )	// PTD
+	    {
+                r_dcache_ptba_ok   = true;
+                r_dcache_ptba_save = (paddr_t)(tlb_data & ((1<<(m_paddr_nbits - PAGE_K_NBITS))-1)) << PAGE_K_NBITS;  
+                r_dcache_id1_save  = dreq.addr >> PAGE_M_NBITS;
+                r_dcache_tlb_paddr = (paddr_t)(tlb_data & ((1<<(m_paddr_nbits - PAGE_K_NBITS))-1)) << PAGE_K_NBITS | 
+                                     (paddr_t)(((dreq.addr & PTD_ID2_MASK) >> PAGE_K_NBITS) << 3);
+                if ( r_dcache_tlb_ptba_read )
+                {
+                    r_dcache_tlb_ptba_read = false;
+                    write_hit = r_dcache.write(((paddr_t)(tlb_data & ((1<<(m_paddr_nbits - PAGE_K_NBITS))-1)) << PAGE_K_NBITS | 
+                                                (paddr_t)(((dreq.addr & PTD_ID2_MASK) >> PAGE_K_NBITS) << 3)), r_dcache_pte_update);
+                    //assert(write_hit && "Write on miss ignores data");
+                    r_dcache_tlb_ll_dirty_req = true;
+		    r_vci_rsp_data_ok = false;
+                    r_dcache_fsm = DCACHE_LL_DIRTY_WAIT;
+                    m_cpt_data_tlb_write_dirty++;
+                }
+                else
+                {
+                    r_dcache_fsm = DCACHE_DTLB2_READ_CACHE;
+                }
+	    }
+	    else	// PTE
+	    {
+                r_dcache_ptba_ok = false;
+	        if ( (m_srcid_rw >> 4) == ((r_dcache_tlb_paddr.read() & ((1<<(m_paddr_nbits - PAGE_M_NBITS))-1)) >> (m_paddr_nbits - PAGE_M_NBITS -10)) ) // local
+		{
+		    if ( (tlb_data & PTE_L_MASK ) >> PTE_L_SHIFT ) // L bit is set
+		    {
+                        r_dcache_pte_update = tlb_data;
+                        r_dcache_fsm = DCACHE_TLB1_UPDT;
+		    }
+		    else
+		    {
+                        r_dcache_pte_update = tlb_data | PTE_L_MASK;
+                        r_dcache_tlb_ll_acc_req = true;
+			r_vci_rsp_data_ok = false;
+                	write_hit = r_dcache.write(r_dcache_tlb_paddr,(tlb_data | PTE_L_MASK));  
+                	assert(write_hit && "Write on miss ignores data");  
+                        r_dcache_fsm = DCACHE_TLB1_LL_WAIT;
+                        m_cpt_ins_tlb_write_et++;
+		    }
+    	        }
+		else // remotely
+		{
+		    if ( (tlb_data & PTE_R_MASK ) >> PTE_R_SHIFT ) // R bit is set
+		    {
+                        r_dcache_pte_update = tlb_data;
+                        r_dcache_fsm = DCACHE_TLB1_UPDT;
+		    }
+		    else
+		    {
+                        r_dcache_pte_update = tlb_data | PTE_R_MASK;
+                        r_dcache_tlb_ll_acc_req = true;
+			r_vci_rsp_data_ok = false;
+                	write_hit = r_dcache.write(r_dcache_tlb_paddr,(tlb_data | PTE_R_MASK));  
+                	assert(write_hit && "Write on miss ignores data");  
+                        r_dcache_fsm = DCACHE_TLB1_LL_WAIT;
+                        m_cpt_ins_tlb_write_et++;
+		    }
+		}
+	    }
+        }
+        else
+        {
+            // DTLB request miss in cache and walk page table level 1
+            r_dcache_tlb_read_req = true;
+	    r_vci_rsp_data_ok = false;
+            r_dcache_fsm = DCACHE_TLB1_READ;
+        }
+        break;
+    }
+    ///////////////////////
+    case DCACHE_TLB1_LL_WAIT:
+    {
+        // external cache invalidate request
+        if ( r_tgt_dcache_req )   
+        {
+            r_dcache_fsm = DCACHE_CC_CHECK;
+            r_dcache_fsm_save = r_dcache_fsm;
+            m_cost_data_waste_wait_frz++;
+            break;
+        }
+
+	if ( r_vci_rsp_data_ok )
+	{
+            if ( r_vci_rsp_data_error ) // VCI response ko
+            {
+                if ((r_dcache_type_save == iss_t::DATA_READ)||(r_dcache_type_save == iss_t::DATA_LL))
+                {
+                    r_dcache_error_type = MMU_READ_PT1_ILLEGAL_ACCESS;
+                }
+                else /*if ((dreq.type == iss_t::DATA_WRITE)||(dreq.type == iss_t::DATA_SC))*/
+                {
+                    r_dcache_error_type = MMU_WRITE_PT1_ILLEGAL_ACCESS;
+                } 
+                r_dcache_bad_vaddr = dreq.addr;
+                r_dcache_fsm = DCACHE_ERROR;
+
+		if (r_dcache_inval_tlb_rsp) r_dcache_inval_tlb_rsp = false;
+		if (r_dcache_inval_rsp) r_dcache_inval_rsp = false;		 
+            }
+	    else
+	    {
+		if ( !(r_dcache_miss_buf[0] >> PTE_V_SHIFT) )	// unmapped
+	        {
+               	    if ((r_dcache_type_save == iss_t::DATA_READ)||(r_dcache_type_save == iss_t::DATA_LL))
+               	    {
+               	        r_dcache_error_type = MMU_READ_PT1_UNMAPPED;
+               	    }
+               	    else /*if ((dreq.type == iss_t::DATA_WRITE)||(dreq.type == iss_t::DATA_SC))*/
+               	    {
+               	        r_dcache_error_type = MMU_WRITE_PT1_UNMAPPED;
+               	    }  
+                    r_dcache_bad_vaddr  = dreq.addr;
+                    r_dcache_fsm        = DCACHE_ERROR;
+
+		    if (r_dcache_inval_tlb_rsp) r_dcache_inval_tlb_rsp = false;
+		    if (r_dcache_inval_rsp) r_dcache_inval_rsp = false;	
+	        }
+       		else if ( r_dcache_inval_tlb_rsp )
+       		{
+       		    r_dcache_inval_tlb_rsp = false;
+       		    r_dcache_fsm = DCACHE_IDLE;
+       		    m_cost_data_tlb_miss_frz++;
+       		}
+		else if ( r_dcache_inval_rsp )
+       		{
+       		    r_dcache_inval_rsp = false;
+       		    r_dcache_fsm = DCACHE_IDLE;
+       		}
+		else
+		{
+		    r_dcache_tlb_sc_acc_req = true;
+		    r_vci_rsp_data_ok = false;
+		    r_dcache_pte_update = r_dcache_miss_buf[0] | r_dcache_pte_update.read();
+                    r_dcache_fsm = DCACHE_TLB1_SC_WAIT; 
+		}
+	    }
+	}
+	break;
+    }
+    ///////////////////////
+    case DCACHE_TLB1_SC_WAIT:
+    {
+        // external cache invalidate request
+        if ( r_tgt_dcache_req )   
+        {
+            r_dcache_fsm = DCACHE_CC_CHECK;
+            r_dcache_fsm_save = r_dcache_fsm;
+            m_cost_data_waste_wait_frz++;
+            break;
+        }
+
+	if ( r_vci_rsp_data_ok )
+	{
+	    if ( r_vci_rsp_data_error ) // VCI response ko
+	    {
+                if ((r_dcache_type_save == iss_t::DATA_READ)||(r_dcache_type_save == iss_t::DATA_LL))
+                {
+                    r_dcache_error_type = MMU_READ_PT1_ILLEGAL_ACCESS;
+                }
+                else /*if ((dreq.type == iss_t::DATA_WRITE)||(dreq.type == iss_t::DATA_SC))*/
+                {
+                    r_dcache_error_type = MMU_WRITE_PT1_ILLEGAL_ACCESS;
+                } 
+	        r_dcache_bad_vaddr = dreq.addr;
+	        r_dcache_fsm = DCACHE_ERROR; 
+
+		if (r_dcache_inval_tlb_rsp) r_dcache_inval_tlb_rsp = false;
+		if (r_dcache_inval_rsp) r_dcache_inval_rsp = false;	
+	    }
+	    else
+	    {
+        	// Using tlb entry is invalidated 
+        	if ( r_dcache_inval_tlb_rsp )
+        	{
+        	    r_dcache_inval_tlb_rsp = false;
+        	    r_dcache_fsm = DCACHE_IDLE;
+		    if ( r_dcache_tlb_sc_fail ) r_dcache_tlb_sc_fail = false;
+        	    m_cost_data_tlb_miss_frz++;
+        	}
+		else if ( r_dcache_inval_rsp )
+        	{
+        	    r_dcache_inval_rsp = false;
+        	    r_dcache_fsm = DCACHE_IDLE;
+		    if ( r_dcache_tlb_sc_fail ) r_dcache_tlb_sc_fail = false;
+        	}
+	    	else if ( r_dcache_tlb_sc_fail )
+	    	{
+		    r_dcache_tlb_ll_acc_req = true;
+		    r_vci_rsp_data_ok = false;
+		    r_dcache_tlb_sc_fail = false;
+	    	    r_dcache_fsm = DCACHE_TLB1_LL_WAIT; 
+	    	}
+	    	else 
+	    	{
+		    r_vci_rsp_data_ok = false;	
+	    	    r_dcache_fsm = DCACHE_TLB1_UPDT; 
+	    	}
+	    }
+	}
+	break;
+    }
+    //////////////////////
+    case DCACHE_TLB1_READ:
+    {
+        m_cost_data_tlb_miss_frz++;
+
+        // external cache invalidate request
+        if ( r_tgt_dcache_req )   
+        {
+            r_dcache_fsm = DCACHE_CC_CHECK;
+            r_dcache_fsm_save = r_dcache_fsm;
+            m_cost_data_waste_wait_frz++;
+            break;
+        }        
+
+	if ( r_vci_rsp_data_ok )
+	{	
+            if ( r_vci_rsp_data_error ) // VCI response ko
+            {
+                if ((r_dcache_type_save == iss_t::DATA_READ)||(r_dcache_type_save == iss_t::DATA_LL))
+                {
+                    r_dcache_error_type = MMU_READ_PT1_ILLEGAL_ACCESS;
+                }
+                else /*if ((dreq.type == iss_t::DATA_WRITE)||(dreq.type == iss_t::DATA_SC))*/
+                {
+                    r_dcache_error_type = MMU_WRITE_PT1_ILLEGAL_ACCESS;
+                } 
+                r_dcache_bad_vaddr = dreq.addr;
+                r_dcache_fsm = DCACHE_ERROR; 
+
+		if (r_dcache_inval_tlb_rsp) r_dcache_inval_tlb_rsp = false;
+		if (r_dcache_inval_rsp) r_dcache_inval_rsp = false;	
+		break;
+            }
+
+            if ( r_dcache_inval_tlb_rsp )  // TLB miss response and invalidation
+            {
+                r_dcache_fsm = DCACHE_IDLE; 
+            	r_dcache_inval_tlb_rsp = false;
+		break;
+            }
+
+	    if ( r_dcache_inval_rsp ) // TLB miss response and cache invalidation
+	    {
+	        if ( r_dcache_cleanup_req ) break;
+                r_dcache_cleanup_req = true;
+                r_dcache_cleanup_line = r_dcache_tlb_paddr.read() >> (uint32_log2(m_dcache_words) + 2);  
+                r_dcache_fsm = DCACHE_IDLE;
+                r_dcache_inval_rsp = false;
+                break;
+	    }
+
+	    // TLB miss response and no invalidation
+	    r_vci_rsp_data_ok = false;
+	    r_dcache_fsm = DCACHE_TLB1_READ_UPDT;
+	}
+        break;
+    }
+    //////////////////////////
+    case DCACHE_TLB1_READ_UPDT:
+    {
+        m_cost_data_tlb_miss_frz++;
+
+        // external cache invalidate request
+        if ( r_tgt_dcache_req )   
+        {
+            r_dcache_fsm = DCACHE_CC_CHECK;
+            r_dcache_fsm_save = r_dcache_fsm;
+            m_cost_data_waste_wait_frz++;
+            break;
+        }        
+
+        // Using tlb entry is invalidated 
+        if ( r_dcache_inval_tlb_rsp )
+        {
+            r_dcache_inval_tlb_rsp = false;
+            r_dcache_fsm = DCACHE_IDLE;
+            m_cost_data_tlb_miss_frz++;
+            break;
+        }
+
+        if ( !r_dcache_cleanup_req ) // Miss update and no invalidation
+        {
+            // update dcache
+            data_t   rsp_dtlb_miss = 0;
+            paddr_t  victim_index = 0;
+	    bool write_hit = false;
+            size_t way = 0;
+            size_t set = 0;
+
+            // Using tlb entry is in the invalidated cache line  
+            if ( r_dcache_inval_rsp )
+            {
+                r_dcache_cleanup_req = true;
+                r_dcache_cleanup_line = r_dcache_tlb_paddr.read() >> (uint32_log2(m_dcache_words) + 2);  
+                r_dcache_fsm = DCACHE_IDLE;
+                r_dcache_inval_rsp = false;
+                break;
+            }
+
+            bool cleanup_req = r_dcache.find(r_dcache_tlb_paddr, r_dcache_in_itlb, r_dcache_in_dtlb, &way, &set, &victim_index);
+            
+	    if ( cleanup_req )
+	    {	    
+		// ins tlb invalidate verification    
+                r_dcache_itlb_inval_req = r_dcache_in_itlb[m_dcache_sets*way+set];
+                r_dcache_itlb_inval_line = victim_index;
+                r_dcache_in_itlb[way*m_dcache_sets+set] = false;
+
+                // data tlb invalidate verification
+                r_dcache_dtlb_inval_req = r_dcache_in_dtlb[m_dcache_sets*way+set]; 
+                r_dcache_dtlb_inval_line = victim_index;
+                r_dcache_in_dtlb[way*m_dcache_sets+set] = false;
+
+                r_dcache_cleanup_req = true; 
+                r_dcache_cleanup_line = victim_index;
+		r_dcache_fsm = DCACHE_TLB_CC_INVAL;
+                r_dcache_fsm_save = r_dcache_fsm;
+		break;
+	    }
+
+	    r_dcache.update(r_dcache_tlb_paddr, way, set, r_dcache_miss_buf);
+            r_dcache.read(r_dcache_tlb_paddr, &rsp_dtlb_miss);	
+
+	    if ( !(rsp_dtlb_miss >> PTE_V_SHIFT) )	// unmapped
+	    {
+                r_dcache_ptba_ok    = false;
+                if ((r_dcache_type_save == iss_t::DATA_READ)||(r_dcache_type_save == iss_t::DATA_LL))
+                {
+                    r_dcache_error_type = MMU_READ_PT1_UNMAPPED;
+                }
+                else /*if ((dreq.type == iss_t::DATA_WRITE)||(dreq.type == iss_t::DATA_SC))*/
+                {
+                    r_dcache_error_type = MMU_WRITE_PT1_UNMAPPED;
+                } 
+                r_dcache_bad_vaddr  = dreq.addr;
+                r_dcache_fsm        = DCACHE_ERROR;
+	    }
+	    else if ( (rsp_dtlb_miss & PTE_T_MASK) >> PTE_T_SHIFT ) // PTD
+	    {
+                r_dcache_ptba_ok   = true;
+                r_dcache_ptba_save = (paddr_t)(rsp_dtlb_miss & ((1<<(m_paddr_nbits - PAGE_K_NBITS))-1)) << PAGE_K_NBITS;  
+                r_dcache_id1_save  = dreq.addr >> PAGE_M_NBITS;
+                r_dcache_tlb_paddr = (paddr_t)(rsp_dtlb_miss & ((1<<(m_paddr_nbits - PAGE_K_NBITS))-1)) << PAGE_K_NBITS | 
+                                     (paddr_t)(((dreq.addr & PTD_ID2_MASK) >> PAGE_K_NBITS) << 3);
+                if ( r_dcache_tlb_ptba_read )
+                {
+                    r_dcache_tlb_ptba_read = false;
+                    write_hit = r_dcache.write(((paddr_t)(rsp_dtlb_miss & ((1<<(m_paddr_nbits - PAGE_K_NBITS))-1)) << PAGE_K_NBITS | 
+                                                (paddr_t)(((dreq.addr & PTD_ID2_MASK) >> PAGE_K_NBITS) << 3)),r_dcache_pte_update);
+                    //assert(write_hit && "Write on miss ignores data");
+                    r_dcache_tlb_ll_dirty_req = true;
+		    r_vci_rsp_data_ok = false;
+                    r_dcache_fsm = DCACHE_LL_DIRTY_WAIT;
+                    m_cpt_data_tlb_write_dirty++;
+                }
+                else
+                {
+                    r_dcache_fsm = DCACHE_DTLB2_READ_CACHE;
+                }
+	    }
+	    else	// PTE
+	    {
+                r_dcache_ptba_ok = false;
+	        if ( (m_srcid_rw >> 4) == ((r_dcache_tlb_paddr.read() & ((1<<(m_paddr_nbits - PAGE_M_NBITS))-1)) >> (m_paddr_nbits - PAGE_M_NBITS -10)) ) // local
+		{
+		    if ( (rsp_dtlb_miss & PTE_L_MASK ) >> PTE_L_SHIFT ) // L bit is set
+		    {
+                        r_dcache_pte_update = rsp_dtlb_miss;
+                        r_dcache_fsm        = DCACHE_TLB1_UPDT;
+		    }
+		    else
+		    {
+                        r_dcache_pte_update = rsp_dtlb_miss | PTE_L_MASK;
+                        r_dcache_tlb_ll_acc_req = true;
+			r_vci_rsp_data_ok = false;
+                	write_hit = r_dcache.write(r_dcache_tlb_paddr,(rsp_dtlb_miss | PTE_L_MASK));  
+                	assert(write_hit && "Write on miss ignores data");  
+                        r_dcache_fsm        = DCACHE_TLB1_LL_WAIT;
+                        m_cpt_ins_tlb_write_et++;
+		    }
+    	        }
+		else // remotely
+		{
+		    if ( (rsp_dtlb_miss & PTE_R_MASK ) >> PTE_R_SHIFT ) // R bit is set
+		    {
+                        r_dcache_pte_update = rsp_dtlb_miss;
+                        r_dcache_fsm        = DCACHE_TLB1_UPDT;
+		    }
+		    else
+		    {
+                        r_dcache_pte_update = rsp_dtlb_miss | PTE_R_MASK;
+                        r_dcache_tlb_ll_acc_req = true;
+			r_vci_rsp_data_ok = false;
+                	write_hit = r_dcache.write(r_dcache_tlb_paddr,(rsp_dtlb_miss | PTE_R_MASK));  
+                	assert(write_hit && "Write on miss ignores data");  
+                        r_dcache_fsm        = DCACHE_TLB1_LL_WAIT;
+                        m_cpt_ins_tlb_write_et++;
+		    }
+		}
+	    }
+        }
+        break;
+    }
+    //////////////////////
+    case DCACHE_TLB1_UPDT: 
+    {
+        m_cost_data_tlb_miss_frz++;
+
+        // external cache invalidate request
+        if ( r_tgt_dcache_req )   
+        {
+            r_dcache_fsm = DCACHE_CC_CHECK;
+            r_dcache_fsm_save = r_dcache_fsm;
+            m_cost_data_waste_wait_frz++;
+            break;
+        }        
+
+        if ( !r_dcache_inval_tlb_rsp && !r_dcache_inval_rsp )
+        {
+            paddr_t victim_index = 0;
+            if (dcache_tlb.update(r_dcache_pte_update,dreq.addr,(r_dcache_tlb_paddr.read() >> (uint32_log2(m_dcache_words)+2)),&victim_index))
+            {
+                r_dcache.setinbit((paddr_t)victim_index*m_dcache_words*2, r_dcache_in_dtlb, false);
+            }
+            r_dcache.setinbit(r_dcache_tlb_paddr, r_dcache_in_dtlb, true);
+            r_dcache_fsm = DCACHE_IDLE;
+        }
+        else  
+        {
+            if ( r_dcache_inval_tlb_rsp ) r_dcache_inval_tlb_rsp = false;
+            if ( r_dcache_inval_rsp ) r_dcache_inval_rsp = false;
+            r_dcache_fsm = DCACHE_IDLE;
+        }
+        break;
+    }
+    /////////////////////////////
+    case DCACHE_DTLB2_READ_CACHE:
+    {
+        m_cost_data_tlb_miss_frz++;
+
+        // external cache invalidate request
+        if ( r_tgt_dcache_req )   
+        {
+            r_dcache_fsm = DCACHE_CC_CHECK;
+            r_dcache_fsm_save = r_dcache_fsm;
+            m_cost_data_waste_wait_frz++;
+            break;
+        }        
+
+        // Using tlb entry is invalidated 
+        if ( r_dcache_inval_tlb_rsp )
+        {
+            r_dcache_inval_tlb_rsp = false;
+            r_dcache_fsm = DCACHE_IDLE;
+            m_cost_data_tlb_miss_frz++;
+            break;
+        }
+
+        data_t tlb_data = 0;
+        data_t tlb_data_ppn = 0;
+	bool write_hit = false;
+        bool tlb_hit_cache = r_dcache.read(r_dcache_tlb_paddr, &tlb_data);
+
+	if ( tlb_hit_cache )
+	{
+            bool tlb_hit_ppn = r_dcache.read(r_dcache_tlb_paddr.read()+4, &tlb_data_ppn);
+	    assert(tlb_hit_ppn && "Address of pte[64-32] and pte[31-0] should be successive");
+	}
+
+        // DTLB request hit in cache
+        if ( tlb_hit_cache )
+        {
+	    if ( !(tlb_data >> PTE_V_SHIFT) )	// unmapped
+	    {
+                if ((r_dcache_type_save == iss_t::DATA_READ)||(r_dcache_type_save == iss_t::DATA_LL))
+                {
+                    r_dcache_error_type = MMU_READ_PT2_UNMAPPED;
+                }
+                else /*if ((dreq.type == iss_t::DATA_WRITE)||(dreq.type == iss_t::DATA_SC))*/
+                {
+                    r_dcache_error_type = MMU_WRITE_PT2_UNMAPPED;
+                } 
+                r_dcache_bad_vaddr  = dreq.addr;
+                r_dcache_fsm        = DCACHE_ERROR;
+	    }
+	    else if ( (tlb_data & PTE_T_MASK) >> PTE_T_SHIFT ) //PTD
+	    {
+                r_dcache_pte_update = tlb_data;
+	        r_dcache_ppn_update = tlb_data_ppn;
+		r_dcache_fsm = DCACHE_TLB2_UPDT;
+	    }
+	    else 
+	    {
+	        if ( (m_srcid_rw >> 4) == ((r_dcache_tlb_paddr.read() & ((1<<(m_paddr_nbits - PAGE_M_NBITS))-1)) >> (m_paddr_nbits - PAGE_M_NBITS -10)) ) // local
+		{
+		    if ( (tlb_data & PTE_L_MASK ) >> PTE_L_SHIFT ) // L bit is set
+		    {
+                        r_dcache_pte_update = tlb_data;
+			r_dcache_ppn_update = tlb_data_ppn;
+                        r_dcache_fsm        = DCACHE_TLB2_UPDT;
+		    }
+		    else
+		    {
+                        r_dcache_pte_update = tlb_data | PTE_L_MASK;
+	        	r_dcache_ppn_update = tlb_data_ppn;
+                        r_dcache_tlb_ll_acc_req = true;
+			r_vci_rsp_data_ok = false;
+                	write_hit = r_dcache.write(r_dcache_tlb_paddr,(tlb_data | PTE_L_MASK));  
+                	assert(write_hit && "Write on miss ignores data");  
+                        r_dcache_fsm = DCACHE_TLB2_LL_WAIT;
+                        m_cpt_ins_tlb_write_et++;
+		    }
+    	        }
+		else // remotely
+		{
+		    if ( (tlb_data & PTE_R_MASK ) >> PTE_R_SHIFT ) // R bit is set
+		    {
+                        r_dcache_pte_update = tlb_data;
+			r_dcache_ppn_update = tlb_data_ppn;
+                        r_dcache_fsm        = DCACHE_TLB2_UPDT;
+		    }
+		    else
+		    {
+                        r_dcache_pte_update = tlb_data | PTE_R_MASK;
+	        	r_dcache_ppn_update = tlb_data_ppn;
+                        r_dcache_tlb_ll_acc_req = true;
+			r_vci_rsp_data_ok = false;
+                	write_hit = r_dcache.write(r_dcache_tlb_paddr,(tlb_data | PTE_R_MASK));  
+                	assert(write_hit && "Write on miss ignores data");  
+                        r_dcache_fsm = DCACHE_TLB2_LL_WAIT;
+                        m_cpt_ins_tlb_write_et++;
+		    }
+		}
+	    }
+        }
+        else
+        {
+            // DTLB request miss in cache and walk page table level 2
+            r_dcache_tlb_read_req = true;
+	    r_vci_rsp_data_ok = false;
+            r_dcache_fsm = DCACHE_TLB2_READ;
+        }
+        break;
+    }
+    ///////////////////////
+    case DCACHE_TLB2_LL_WAIT:
+    {
+        // external cache invalidate request
+        if ( r_tgt_dcache_req )   
+        {
+            r_dcache_fsm = DCACHE_CC_CHECK;
+            r_dcache_fsm_save = r_dcache_fsm;
+            m_cost_data_waste_wait_frz++;
+            break;
+        }
+
+	if ( r_vci_rsp_data_ok )
+	{
+            if ( r_vci_rsp_data_error ) // VCI response ko
+            {
+                if ((r_dcache_type_save == iss_t::DATA_READ)||(r_dcache_type_save == iss_t::DATA_LL))
+                {
+                    r_dcache_error_type = MMU_READ_PT2_ILLEGAL_ACCESS;
+                }
+                else /*if ((dreq.type == iss_t::DATA_WRITE)||(dreq.type == iss_t::DATA_SC))*/
+                {
+                    r_dcache_error_type = MMU_WRITE_PT2_ILLEGAL_ACCESS;
+                } 
+                r_dcache_bad_vaddr = dreq.addr;
+                r_dcache_fsm = DCACHE_ERROR; 
+
+		if (r_dcache_inval_tlb_rsp) r_dcache_inval_tlb_rsp = false;
+		if (r_dcache_inval_rsp) r_dcache_inval_rsp = false;
+            }
+	    else
+	    {
+	        if ( !(r_dcache_miss_buf[0] >> PTE_V_SHIFT) )	// unmapped
+	        {
+               	    if ((r_dcache_type_save == iss_t::DATA_READ)||(r_dcache_type_save == iss_t::DATA_LL))
+               	    {
+               	        r_dcache_error_type = MMU_READ_PT2_UNMAPPED;
+               	    }
+               	    else /*if ((dreq.type == iss_t::DATA_WRITE)||(dreq.type == iss_t::DATA_SC))*/
+               	    {
+               	        r_dcache_error_type = MMU_WRITE_PT2_UNMAPPED;
+               	    } 
+                    r_dcache_bad_vaddr = dreq.addr;
+                    r_dcache_fsm = DCACHE_ERROR;
+
+		    if (r_dcache_inval_tlb_rsp) r_dcache_inval_tlb_rsp = false;
+		    if (r_dcache_inval_rsp) r_dcache_inval_rsp = false;
+	        }
+        	else if ( r_dcache_inval_tlb_rsp )
+        	{
+        	    r_dcache_inval_tlb_rsp = false;
+        	    r_dcache_fsm = DCACHE_IDLE;
+        	    m_cost_data_tlb_miss_frz++;
+        	}
+		else if ( r_dcache_inval_rsp )
+		{
+        	    r_dcache_inval_rsp = false;
+		    r_dcache_fsm = DCACHE_IDLE;
+		}
+		else
+		{
+		    r_dcache_tlb_sc_acc_req = true;
+		    r_vci_rsp_data_ok = false;
+		    r_dcache_pte_update = r_dcache_miss_buf[0] | r_dcache_pte_update.read();
+                    r_dcache_fsm = DCACHE_TLB2_SC_WAIT; 
+		}
+	    }
+	}
+	break;
+    }
+    ///////////////////////
+    case DCACHE_TLB2_SC_WAIT:
+    {
+        // external cache invalidate request
+        if ( r_tgt_dcache_req )   
+        {
+            r_dcache_fsm = DCACHE_CC_CHECK;
+            r_dcache_fsm_save = r_dcache_fsm;
+            m_cost_data_waste_wait_frz++;
+            break;
+        }
+
+	if ( r_vci_rsp_data_ok )
+	{
+	    if ( r_vci_rsp_data_error ) // VCI response ko
+	    {
+                if ((r_dcache_type_save == iss_t::DATA_READ)||(r_dcache_type_save == iss_t::DATA_LL))
+                {
+                    r_dcache_error_type = MMU_READ_PT2_ILLEGAL_ACCESS;
+                }
+                else /*if ((dreq.type == iss_t::DATA_WRITE)||(dreq.type == iss_t::DATA_SC))*/
+                {
+                    r_dcache_error_type = MMU_WRITE_PT2_ILLEGAL_ACCESS;
+                } 
+	        r_dcache_bad_vaddr = dreq.addr;
+	        r_dcache_fsm = DCACHE_ERROR; 
+
+		if (r_dcache_inval_tlb_rsp) r_dcache_inval_tlb_rsp = false;
+		if (r_dcache_inval_rsp) r_dcache_inval_rsp = false;	
+	    }
+	    else
+	    { 
+                // Using tlb entry is invalidated 
+                if ( r_dcache_inval_tlb_rsp )
+                {
+                    r_dcache_inval_tlb_rsp = false;
+                    r_dcache_fsm = DCACHE_IDLE;
+		    if ( r_dcache_tlb_sc_fail ) r_dcache_tlb_sc_fail = false;
+                    m_cost_data_tlb_miss_frz++;
+                }
+		else if ( r_dcache_inval_rsp )
+		{
+        	    r_dcache_inval_rsp = false;
+		    r_dcache_fsm = DCACHE_IDLE;
+		    if ( r_dcache_tlb_sc_fail ) r_dcache_tlb_sc_fail = false;
+		}
+	        else if ( r_dcache_tlb_sc_fail )
+	        {
+		    r_dcache_tlb_ll_acc_req = true;
+		    r_dcache_tlb_sc_fail = false;
+		    r_vci_rsp_data_ok = false;
+	            r_dcache_fsm = DCACHE_TLB2_LL_WAIT; 
+	        }
+	        else 
+	        {
+		    r_vci_rsp_data_ok = false;	
+	            r_dcache_fsm = DCACHE_TLB2_UPDT; 
+	        }
+	    }
+	}
+	break;
+    }
+    /////////////////////
+    case DCACHE_TLB2_READ:
+    {
+        m_cost_data_tlb_miss_frz++;
+
+        // external cache invalidate request
+        if ( r_tgt_dcache_req )   
+        {
+            r_dcache_fsm = DCACHE_CC_CHECK;
+            r_dcache_fsm_save = r_dcache_fsm;
+            m_cost_data_waste_wait_frz++;
+            break;
+        }        
+
+	if ( r_vci_rsp_data_ok )
+	{
+            if ( r_vci_rsp_data_error ) // VCI response ko
+            {
+                if ((r_dcache_type_save == iss_t::DATA_READ)||(r_dcache_type_save == iss_t::DATA_LL))
+                {
+                    r_dcache_error_type = MMU_READ_PT2_ILLEGAL_ACCESS;
+                }
+                else /*if ((dreq.type == iss_t::DATA_WRITE)||(dreq.type == iss_t::DATA_SC))*/
+                {
+                    r_dcache_error_type = MMU_WRITE_PT2_ILLEGAL_ACCESS;
+                } 
+                r_dcache_bad_vaddr = dreq.addr;
+                r_dcache_fsm = DCACHE_ERROR; 
+
+		if (r_dcache_inval_tlb_rsp) r_dcache_inval_tlb_rsp = false;
+		if (r_dcache_inval_rsp) r_dcache_inval_rsp = false;
+		break;
+            }	
+
+            if ( r_dcache_inval_tlb_rsp )  // TLB miss response and invalidation
+            {
+                r_dcache_fsm = DCACHE_IDLE; 
+                r_dcache_inval_tlb_rsp = false;
+		break;
+            }  
+
+	    if ( r_dcache_inval_rsp ) // TLB miss response and cache invalidation
+	    {
+	        if ( r_dcache_cleanup_req ) break;
+                r_dcache_cleanup_req = true;
+                r_dcache_cleanup_line = r_dcache_tlb_paddr.read() >> (uint32_log2(m_dcache_words) + 2);  
+                r_dcache_fsm = DCACHE_IDLE;
+                r_dcache_inval_rsp = false;
+                break;
+	    } 
+
+	    // TLB miss response and no invalidation
+	    r_vci_rsp_data_ok = false;
+	    r_dcache_fsm = DCACHE_TLB2_READ_UPDT;
+	}	
+        break;
+    }
+    //////////////////////////
+    case DCACHE_TLB2_READ_UPDT:
+    {
+        m_cost_data_tlb_miss_frz++;
+
+        // external cache invalidate request
+        if ( r_tgt_dcache_req )   
+        {
+            r_dcache_fsm = DCACHE_CC_CHECK;
+            r_dcache_fsm_save = r_dcache_fsm;
+            m_cost_data_waste_wait_frz++;
+            break;
+        }        
+
+        // Using tlb entry is invalidated 
+        if ( r_dcache_inval_tlb_rsp )
+        {
+            r_dcache_inval_tlb_rsp = false;
+            r_dcache_fsm = DCACHE_IDLE;
+            m_cost_data_tlb_miss_frz++;
+            break;
+        }
+
+        if ( !r_dcache_cleanup_req )
+        {
+            // update cache
+            data_t rsp_dtlb_miss;
+            data_t tlb_data_ppn;
+	    bool write_hit = false;
+            paddr_t  victim_index = 0;
+            size_t way = 0;
+            size_t set = 0;
+
+            // Using tlb entry is in the invalidated cache line  
+            if ( r_dcache_inval_rsp )
+            {
+                r_dcache_cleanup_req = true;
+                r_dcache_cleanup_line = r_dcache_tlb_paddr.read() >> (uint32_log2(m_dcache_words) + 2);  
+                r_dcache_fsm = DCACHE_IDLE;
+                r_dcache_inval_rsp = false;
+                break;
+            }
+
+            bool cleanup_req = r_dcache.find(r_dcache_tlb_paddr, r_dcache_in_itlb, r_dcache_in_dtlb, &way, &set, &victim_index);
+
+	    if ( cleanup_req )
+	    {	    
+		// ins tlb invalidate verification    
+                r_dcache_itlb_inval_req = r_dcache_in_itlb[m_dcache_sets*way+set];
+                r_dcache_itlb_inval_line = victim_index;
+                r_dcache_in_itlb[way*m_dcache_sets+set] = false;
+
+                // data tlb invalidate verification
+                r_dcache_dtlb_inval_req = r_dcache_in_dtlb[m_dcache_sets*way+set]; 
+                r_dcache_dtlb_inval_line = victim_index;
+                r_dcache_in_dtlb[way*m_dcache_sets+set] = false;
+
+                r_dcache_cleanup_req = true; 
+                r_dcache_cleanup_line = victim_index;
+		r_dcache_fsm = DCACHE_TLB_CC_INVAL;
+                r_dcache_fsm_save = r_dcache_fsm;
+		break;
+	    }
+
+	    r_dcache.update(r_dcache_tlb_paddr, way, set, r_dcache_miss_buf);
+	    r_dcache.read(r_dcache_tlb_paddr, &rsp_dtlb_miss);
+
+	    bool tlb_hit_ppn = r_dcache.read(r_dcache_tlb_paddr.read()+4, &tlb_data_ppn);
+	    assert(tlb_hit_ppn && "Address of pte[64-32] and pte[31-0] should be successive");
+
+	    if ( !(rsp_dtlb_miss >> PTE_V_SHIFT) )	// unmapped
+	    {
+                if ((r_dcache_type_save == iss_t::DATA_READ)||(r_dcache_type_save == iss_t::DATA_LL))
+                {
+                    r_dcache_error_type = MMU_READ_PT2_UNMAPPED;
+                }
+                else /*if ((dreq.type == iss_t::DATA_WRITE)||(dreq.type == iss_t::DATA_SC))*/
+                {
+                    r_dcache_error_type = MMU_WRITE_PT2_UNMAPPED;
+                }  
+                r_dcache_bad_vaddr  = dreq.addr;
+                r_dcache_fsm        = DCACHE_ERROR;
+	    }
+	    else if ( (rsp_dtlb_miss & PTE_T_MASK) >> PTE_T_SHIFT ) // PTD
+	    {
+                r_dcache_pte_update = rsp_dtlb_miss;
+	        r_dcache_ppn_update = tlb_data_ppn;
+		r_dcache_fsm = DCACHE_TLB2_UPDT;
+	    }
+	    else
+	    {
+	        if ( (m_srcid_rw >> 4) == ((r_dcache_tlb_paddr.read() & ((1<<(m_paddr_nbits - PAGE_M_NBITS))-1)) >> (m_paddr_nbits - PAGE_M_NBITS -10)) ) // local
+		{
+		    if ( (rsp_dtlb_miss & PTE_L_MASK ) >> PTE_L_SHIFT ) // L bit is set
+		    {
+                        r_dcache_pte_update = rsp_dtlb_miss;
+			r_dcache_ppn_update = tlb_data_ppn;
+                        r_dcache_fsm        = DCACHE_TLB2_UPDT;
+		    }
+		    else
+		    {
+                        r_dcache_pte_update = rsp_dtlb_miss | PTE_L_MASK;
+	        	r_dcache_ppn_update = tlb_data_ppn;
+                        r_dcache_tlb_ll_acc_req = true;
+			r_vci_rsp_data_ok = false;
+                	write_hit = r_dcache.write(r_dcache_tlb_paddr,(rsp_dtlb_miss | PTE_L_MASK));  
+                	assert(write_hit && "Write on miss ignores data");  
+                        r_dcache_fsm = DCACHE_TLB2_LL_WAIT;
+                        m_cpt_ins_tlb_write_et++;
+		    }
+    	        }
+		else // remotely
+		{
+		    if ( (rsp_dtlb_miss & PTE_R_MASK ) >> PTE_R_SHIFT ) // R bit is set
+		    {
+                        r_dcache_pte_update = rsp_dtlb_miss;
+			r_dcache_ppn_update = tlb_data_ppn;
+                        r_dcache_fsm        = DCACHE_TLB2_UPDT;
+		    }
+		    else
+		    {
+                        r_dcache_pte_update = rsp_dtlb_miss | PTE_R_MASK;
+	        	r_dcache_ppn_update = tlb_data_ppn;
+                        r_dcache_tlb_ll_acc_req = true;
+			r_vci_rsp_data_ok = false;
+                	write_hit = r_dcache.write(r_dcache_tlb_paddr,(rsp_dtlb_miss | PTE_R_MASK));  
+                	assert(write_hit && "Write on miss ignores data");  
+                        r_dcache_fsm = DCACHE_TLB2_LL_WAIT;
+                        m_cpt_ins_tlb_write_et++;
+		    }
+		}
+	    }
+        }
+        break;
+    }
+    //////////////////////
+    case DCACHE_TLB2_UPDT:  
+    {
+        m_cost_data_tlb_miss_frz++;
+
+        // external cache invalidate request
+        if ( r_tgt_dcache_req )   
+        {
+            r_dcache_fsm = DCACHE_CC_CHECK;
+            r_dcache_fsm_save = r_dcache_fsm;
+            m_cost_data_waste_wait_frz++;
+            break;
+        }        
+
+        if ( !r_dcache_inval_tlb_rsp && !r_dcache_inval_rsp )
+        {
+            paddr_t victim_index = 0;
+            if (dcache_tlb.update(r_dcache_pte_update,r_dcache_ppn_update,dreq.addr,(r_dcache_tlb_paddr.read() >> (uint32_log2(m_dcache_words)+2)),&victim_index))
+            {
+                r_dcache.setinbit((paddr_t)victim_index*m_dcache_words*2, r_dcache_in_dtlb, false);
+            }
+            r_dcache.setinbit(r_dcache_tlb_paddr, r_dcache_in_dtlb, true);
+            r_dcache_fsm = DCACHE_IDLE;
+        }
+        else  
+        {
+            if ( r_dcache_inval_tlb_rsp ) r_dcache_inval_tlb_rsp = false;
+            if ( r_dcache_inval_rsp ) r_dcache_inval_rsp = false;
+            r_dcache_fsm = DCACHE_IDLE;
+        }
+        break;
+    }
+    ///////////////////////
+    case DCACHE_CTXT_SWITCH:
+    {
+        // TLB flush leads to cleanup corresponding data cache line 
+        m_cost_data_tlb_sw_frz++;
+
+        paddr_t victim_index = 0;
+        size_t way = 0;
+        size_t set = 0;
+
+        if ( r_dcache_itlb_cleanup_req )
+        {    
+            r_dcache.setinbit(((paddr_t)r_dcache_itlb_cleanup_line.read()*m_dcache_words*2), r_dcache_in_itlb, false);
+            r_dcache_itlb_cleanup_req = false;
+	}
+
+        for ( way = 0; way < m_dtlb_ways; way++)
+        {
+            for ( set = 0; set < m_dtlb_sets; set++)
+            {
+                if(dcache_tlb.checkcleanup(way, set, &victim_index))
+                {
+                    r_dcache.setinbit((paddr_t)(victim_index << (m_dcache_words+2)), r_dcache_in_dtlb, false); 
+                }
+            }
+        }
+
+        if ( !r_dcache_xtn_req )
+        {
+            r_dcache_fsm = DCACHE_IDLE;
+            r_dtlb_translation_valid = false;
+            r_dcache_ptba_ok = false;
+            drsp.valid = true;
+        }
+        break;
+    }
+    ////////////////////////
+    case DCACHE_ICACHE_FLUSH:
+    case DCACHE_ICACHE_INVAL:
+    case DCACHE_ICACHE_INVAL_PA:
+    case DCACHE_ITLB_INVAL:
+    {
+        if ( !r_dcache_xtn_req ) 
+        {
+            r_dcache_fsm = DCACHE_IDLE;
+            drsp.valid = true;
+        }
+        break;
+    }
+    ////////////////////////
+    case DCACHE_DCACHE_FLUSH:
+    {
+        // external cache invalidate request
+        if ( r_tgt_dcache_req )
+        {
+	    r_dcache_fsm = DCACHE_CC_CHECK;
+            r_dcache_fsm_save = r_dcache_fsm;	   
+	    m_cost_data_waste_wait_frz++;
+	    break; 
+        }   
+
+        size_t way = r_dcache_way;
+        size_t set = r_dcache_set;
+        bool clean = false;
+        
+        m_cost_data_cache_flush_frz++;
+
+        // cache flush and send cleanup to external
+        if ( !r_dcache_cleanup_req )
+        {
+            paddr_t victim_index = 0;
+            for ( ; way < m_dcache_ways; way++ )
+            {    
+                for ( ; set < m_dcache_sets; set++ )
+                {  
+                    if ( r_dcache.flush(way, set, &victim_index) )
+                    {
+                        clean = true;
+                        r_dcache_cleanup_req = true;
+                        r_dcache_cleanup_line = victim_index;
+                        r_dcache_way = way + ((set+1)/m_dcache_sets);
+                        r_dcache_set = (set+1) % m_dcache_sets;
+                        break;
+                    }
+                }
+                if (clean) break;
+            }
+
+            if ((way == m_dcache_ways) && !r_dcache_xtn_req ) 
+            {
+                // data TLB flush 
+                dcache_tlb.flush(true);      // global entries are not invalidated
+            	r_dtlb_translation_valid = false;
+            	r_dcache_ptba_ok = false;
+
+                for (size_t line = 0; line < m_dcache_ways*m_dcache_sets; line++)
+                {
+                    r_dcache_in_itlb[line] = false;
+                    r_dcache_in_dtlb[line] = false;
+                }
+
+                r_dcache_fsm = DCACHE_IDLE;
+                drsp.valid = true;
+                break;
+            }
+        }
+	break;
+    }
+    //////////////////////
+    case DCACHE_DTLB_INVAL: 
+    {
+        paddr_t victim_index = 0;
+        // clean indicate data tlb bit
+        if ( dcache_tlb.inval(r_dcache_wdata_save, &victim_index) )
+        {  
+            r_dcache.setinbit((paddr_t)(victim_index << (m_dcache_words+2)), r_dcache_in_dtlb, false); 
+        }
+        r_dtlb_translation_valid = false;
+        r_dcache_ptba_ok = false;
+        r_dcache_fsm = DCACHE_IDLE;
+        drsp.valid = true;
+        break;
+    }
+    ////////////////////////
+    case DCACHE_DCACHE_INVAL:
+    {
+        // external cache invalidate request
+        if ( r_tgt_dcache_req )
+        {
+	    r_dcache_fsm = DCACHE_CC_CHECK;
+            r_dcache_fsm_save = r_dcache_fsm;	   
+	    m_cost_data_waste_wait_frz++;
+	    break; 
+        }   
+
+        m_cpt_dcache_dir_read += m_dcache_ways;
+        vaddr_t invadr = dreq.wdata;
+        paddr_t dpaddr = 0;
+        bool dcache_hit_t = false; 
+        size_t way = 0;
+        size_t set = 0;
+
+	if ( !r_dcache_cleanup_req )
+	{
+            if ( r_mmu_mode.read() & DATA_TLB_MASK ) 
+            {
+                dcache_hit_t = dcache_tlb.translate(invadr, &dpaddr); 
+            } 
+            else 
+            {
+                dpaddr = invadr;  
+                dcache_hit_t = true;
+            }
+
+            if ( dcache_hit_t )
+            {
+		r_dcache_cleanup_req = r_dcache.inval(dpaddr, &way, &set);
+		r_dcache_cleanup_line = dpaddr >> (uint32_log2(m_dcache_words)+2);
+		
+		if ( r_dcache_in_itlb[way*m_dcache_sets+set] || r_dcache_in_dtlb[way*m_dcache_sets+set] ) 
+		{	
+		    // ins tlb invalidate verification
+		    r_dcache_itlb_inval_req = r_dcache_in_itlb[way*m_dcache_sets+set];
+		    r_dcache_itlb_inval_line = dpaddr >> (uint32_log2(m_dcache_words)+2);
+		    r_dcache_in_itlb[way*m_dcache_sets+set] = false;
+		
+		    // data tlb invalidate verification
+		    r_dcache_dtlb_inval_req = r_dcache_in_dtlb[way*m_dcache_sets+set];
+		    r_dcache_dtlb_inval_line = dpaddr >> (uint32_log2(m_dcache_words)+2);
+		    r_dcache_in_dtlb[way*m_dcache_sets+set] = false;
+		    r_dcache_fsm = DCACHE_TLB_CC_INVAL;
+		    r_dcache_fsm_save = r_dcache_fsm;
+		    break;
+		}
+            }
+            r_dcache_fsm = DCACHE_IDLE;
+            drsp.valid = true;
+	}
+        break;
+    }
+    ////////////////////////
+    case DCACHE_DCACHE_INVAL_PA:
+    {
+        // external cache invalidate request
+        if ( r_tgt_dcache_req )
+        {
+	    r_dcache_fsm = DCACHE_CC_CHECK;
+            r_dcache_fsm_save = r_dcache_fsm;	   
+	    m_cost_data_waste_wait_frz++;
+	    break; 
+        }   	    
+        m_cpt_dcache_dir_read += m_dcache_ways;
+        paddr_t dpaddr = (paddr_t)r_mmu_word_hi.read() << 32 | r_mmu_word_lo.read();
+        size_t way = 0;
+        size_t set = 0;
+
+	if ( !r_dcache_cleanup_req )
+	{
+	    r_dcache_cleanup_req = r_dcache.inval(dpaddr, &way, &set);
+	    r_dcache_cleanup_line = dpaddr >> (uint32_log2(m_dcache_words)+2);
+	    
+	    if ( r_dcache_in_itlb[way*m_dcache_sets+set] || r_dcache_in_dtlb[way*m_dcache_sets+set] ) 
+	    {	
+	        // ins tlb invalidate verification
+	        r_dcache_itlb_inval_req = r_dcache_in_itlb[way*m_dcache_sets+set];
+	        r_dcache_itlb_inval_line = dpaddr >> (uint32_log2(m_dcache_words)+2);
+	        r_dcache_in_itlb[way*m_dcache_sets+set] = false;
+	    
+	        // data tlb invalidate verification
+	        r_dcache_dtlb_inval_req = r_dcache_in_dtlb[way*m_dcache_sets+set];
+	        r_dcache_dtlb_inval_line = dpaddr >> (uint32_log2(m_dcache_words)+2);
+	        r_dcache_in_dtlb[way*m_dcache_sets+set] = false;
+	        r_dcache_fsm = DCACHE_TLB_CC_INVAL;
+	        r_dcache_fsm_save = r_dcache_fsm;
+	        break;
+	    }
+            r_dcache_fsm = DCACHE_IDLE;
+            drsp.valid = true;
+	}
+        break;
+    }
+    /////////////////////////
+    case DCACHE_DCACHE_SYNC:
+    {
+        if ( r_wbuf.empty() ) 
+        {    
+            drsp.valid = true;
+            r_dcache_fsm = DCACHE_IDLE;  
+        }      
+        break;
+    }
+    /////////////////////
+    case DCACHE_MISS_WAIT:
+    {
+        m_cost_data_miss_frz++; 
+
+        // external cache invalidate request
+        if ( r_tgt_dcache_req ) 
+        {
+            r_dcache_fsm = DCACHE_CC_CHECK;
+            r_dcache_fsm_save = r_dcache_fsm;
+            m_cost_data_waste_wait_frz++;
+            break;
+        }
+
+	if ( r_vci_rsp_data_ok )
+	{
+            if ( r_vci_rsp_data_error ) 
+            {
+                r_dcache_error_type = MMU_READ_DATA_ILLEGAL_ACCESS; 
+                r_dcache_bad_vaddr = dreq.addr;
+                r_dcache_fsm = DCACHE_ERROR;
+
+		if (r_dcache_inval_tlb_rsp) r_dcache_inval_tlb_rsp = false;
+		if (r_dcache_inval_rsp) r_dcache_inval_rsp = false;
+		break;
+            } 
+
+            if ( r_dcache_inval_tlb_rsp ) // Miss read response and tlb invalidation
+            {
+                if ( r_dcache_cleanup_req ) break;
+                r_dcache_cleanup_req = true;
+                r_dcache_cleanup_line = r_dcache_paddr_save.read() >> (uint32_log2(m_dcache_words) + 2);  
+                r_dcache_fsm = DCACHE_IDLE;
+                r_dcache_inval_tlb_rsp = false;
+                if ( r_dcache_inval_rsp ) r_dcache_inval_rsp = false;
+                break;
+            }	
+
+	    if ( r_dcache_inval_rsp ) // TLB miss response and cache invalidation
+	    {
+                if ( r_dcache_cleanup_req ) break;
+                r_dcache_cleanup_req = true;
+                r_dcache_cleanup_line = r_dcache_paddr_save.read() >> (uint32_log2(m_dcache_words) + 2);  
+                r_dcache_fsm = DCACHE_IDLE;
+                r_dcache_inval_rsp = false;
+                break;
+	    }
+	    // Miss read response and no tlb invalidation
+	    r_dcache_fsm = DCACHE_MISS_UPDT;
+	}	
+        break;
+    }
+    /////////////////////
+    case DCACHE_MISS_UPDT:
+    {
+        m_cost_data_miss_frz++;
+
+        // external cache invalidate request
+        if ( r_tgt_dcache_req ) 
+        {
+            r_dcache_fsm = DCACHE_CC_CHECK;
+            r_dcache_fsm_save = r_dcache_fsm;
+            m_cost_data_waste_wait_frz++;
+            break;
+        }
+
+        if ( r_dcache_inval_tlb_rsp ) // tlb invalidation
+        {
+            if ( r_dcache_cleanup_req ) break;
+            r_dcache_cleanup_req = true;
+            r_dcache_cleanup_line = r_dcache_paddr_save.read() >> (uint32_log2(m_dcache_words) + 2);  
+            r_dcache_inval_tlb_rsp = false;
+            r_dcache_inval_rsp = false;
+            r_dcache_fsm = DCACHE_IDLE;
+            m_cost_data_tlb_miss_frz++;
+            break;
+        }
+
+        if (!r_dcache_cleanup_req ) // Miss update and no invalidation
+        {
+            paddr_t  victim_index = 0;
+            size_t way = 0;
+            size_t set = 0;
+
+	    m_cpt_dcache_data_write++;
+            m_cpt_dcache_dir_write++;
+
+            // Using tlb entry is in the invalidated cache line  
+            if ( r_dcache_inval_rsp )
+            {
+                r_dcache_cleanup_req = true;
+                r_dcache_cleanup_line = r_dcache_paddr_save.read() >> (uint32_log2(m_dcache_words) + 2);  
+                r_dcache_fsm = DCACHE_IDLE;
+                r_dcache_inval_rsp = false;
+                break;
+            }
+
+            bool cleanup_req = r_dcache.find(r_dcache_paddr_save.read(), r_dcache_in_itlb, r_dcache_in_dtlb, &way, &set, &victim_index);
+
+	    if ( cleanup_req )
+	    {	    
+		// ins tlb invalidate verification    
+                r_dcache_itlb_inval_req = r_dcache_in_itlb[m_dcache_sets*way+set];
+                r_dcache_itlb_inval_line = victim_index;
+                r_dcache_in_itlb[way*m_dcache_sets+set] = false;
+
+                // data tlb invalidate verification
+                r_dcache_dtlb_inval_req = r_dcache_in_dtlb[m_dcache_sets*way+set]; 
+                r_dcache_dtlb_inval_line = victim_index;
+                r_dcache_in_dtlb[way*m_dcache_sets+set] = false;
+
+                r_dcache_cleanup_req = true; 
+                r_dcache_cleanup_line = victim_index;
+		if ( r_dcache_in_itlb[m_dcache_sets*way+set] || r_dcache_in_dtlb[m_dcache_sets*way+set] )
+		{
+		    r_dcache_fsm = DCACHE_TLB_CC_INVAL;
+                    r_dcache_fsm_save = r_dcache_fsm;
+		    break;
+		}
+	    }
+
+	    r_dcache.update(r_dcache_paddr_save.read(), way, set, r_dcache_miss_buf);
+            r_dcache_fsm = DCACHE_IDLE;
+        }
+	break;
+    }
+    //////////////////////
+    case DCACHE_UNC_WAIT:
+    {
+        m_cost_unc_read_frz++;
+
+        // external cache invalidate request
+        if ( r_tgt_dcache_req ) 
+        {
+            r_dcache_fsm = DCACHE_CC_CHECK;
+            r_dcache_fsm_save = r_dcache_fsm;
+            m_cost_data_waste_wait_frz++;
+            break;
+        }
+
+	if ( r_vci_rsp_data_ok )
+	{
+            if ( r_vci_rsp_data_error ) 
+            {
+                r_dcache_error_type = MMU_READ_DATA_ILLEGAL_ACCESS; 
+                r_dcache_bad_vaddr = dreq.addr;
+                r_dcache_fsm = DCACHE_ERROR;
+
+		if (r_dcache_inval_tlb_rsp) r_dcache_inval_tlb_rsp = false;
+		break;
+            }
+
+            if ( r_dcache_inval_tlb_rsp ) // Miss read response and tlb invalidation
+            {
+                r_dcache_inval_tlb_rsp = false;
+            }
+
+            if(dreq.type == iss_t::DATA_SC) 
+	    {
+		size_t way = 0;
+		size_t set = 0;
+                // Simulate an invalidate request
+		r_dcache_cleanup_req = r_dcache.inval(r_dcache_paddr_save, &way, &set);
+		r_dcache_cleanup_line = r_dcache_paddr_save.read() >> (uint32_log2(m_dcache_words)+2);
+		
+		if ( r_dcache_in_itlb[way*m_dcache_sets+set] || r_dcache_in_dtlb[way*m_dcache_sets+set] ) 
+		{	
+		    // ins tlb invalidate verification
+		    r_dcache_itlb_inval_req = r_dcache_in_itlb[way*m_dcache_sets+set];
+		    r_dcache_itlb_inval_line = r_dcache_paddr_save.read() >> (uint32_log2(m_dcache_words)+2);
+		    r_dcache_in_itlb[way*m_dcache_sets+set] = false;
+		
+		    // data tlb invalidate verification
+		    r_dcache_dtlb_inval_req = r_dcache_in_dtlb[way*m_dcache_sets+set];
+		    r_dcache_dtlb_inval_line = r_dcache_paddr_save.read() >> (uint32_log2(m_dcache_words)+2);
+		    r_dcache_in_dtlb[way*m_dcache_sets+set] = false;
+		    r_dcache_fsm = DCACHE_TLB_CC_INVAL;
+		    r_dcache_fsm_save = r_dcache_fsm;
+		    break;
+		}
+
+            }		
+	    r_dcache_fsm = DCACHE_IDLE;
+	}	
+        break;
+    }
+    ///////////////////////
+    case DCACHE_WRITE_UPDT:
+    {
+        m_cost_write_frz++;
+        size_t way = 0;
+        size_t set = 0;
+	bool write_hit = false;
+        data_t mask = vci_param::be2mask(r_dcache_be_save.read());
+        data_t wdata = (mask & r_dcache_wdata_save) | (~mask & r_dcache_rdata_save);
+        write_hit = r_dcache.write(r_dcache_paddr_save, wdata, &way, &set);
+        assert(write_hit && "Write on miss ignores data");
+        
+        if (r_dcache_in_itlb[way*m_dcache_sets+set] || r_dcache_in_dtlb[m_dcache_sets*way+set])
+        {
+	    // ins tlb invalidate verification    
+            r_dcache_itlb_inval_req = r_dcache_in_itlb[m_dcache_sets*way+set];
+            r_dcache_itlb_inval_line = (r_dcache.get_tag(way, set) * m_dcache_sets) + set;
+            r_dcache_in_itlb[way*m_dcache_sets+set] = false;
+
+            // data tlb invalidate verification
+            r_dcache_dtlb_inval_req = r_dcache_in_dtlb[m_dcache_sets*way+set]; 
+            r_dcache_dtlb_inval_line = (r_dcache.get_tag(way, set) * m_dcache_sets) + set;
+            r_dcache_in_dtlb[way*m_dcache_sets+set] = false;
+
+	    r_dcache_fsm = DCACHE_TLB_CC_INVAL;
+            r_dcache_fsm_save = r_dcache_fsm;
+            break;
+	}
+
+        if ( !r_dcache_dirty_save && (r_mmu_mode.read() & DATA_TLB_MASK) )   
+        {
+            if ( dcache_tlb.getpagesize(r_dcache_tlb_way_save, r_dcache_tlb_set_save) )	// 2M page size, one level page table 
+            {
+                r_dcache_pte_update = dcache_tlb.getpte(r_dcache_tlb_way_save, r_dcache_tlb_set_save) | PTE_D_MASK;
+                r_dcache_tlb_paddr = (paddr_t)r_mmu_ptpr << (INDEX1_NBITS+2) | (paddr_t)((dreq.addr>>PAGE_M_NBITS)<<2);
+                r_dcache_tlb_ll_dirty_req = true;
+		r_vci_rsp_data_ok = false;
+                r_dcache_fsm = DCACHE_LL_DIRTY_WAIT;
+                m_cpt_data_tlb_write_dirty++;
+            }
+            else
+            {   
+                if (r_dcache_hit_p_save) 
+                {
+                    r_dcache_pte_update = dcache_tlb.getpte(r_dcache_tlb_way_save, r_dcache_tlb_set_save) | PTE_D_MASK;
+                    r_dcache_tlb_paddr = (paddr_t)r_dcache_ptba_save|(paddr_t)(((dreq.addr&PTD_ID2_MASK)>>PAGE_K_NBITS) << 3);
+                    r_dcache_tlb_ll_dirty_req = true;
+		    r_vci_rsp_data_ok = false;
+                    r_dcache_fsm = DCACHE_LL_DIRTY_WAIT;
+                    m_cpt_data_tlb_write_dirty++;
+                }
+                else
+                {
+                    r_dcache_pte_update = dcache_tlb.getpte(r_dcache_tlb_way_save, r_dcache_tlb_set_save) | PTE_D_MASK;
+                    r_dcache_tlb_paddr = (paddr_t)r_mmu_ptpr << (INDEX1_NBITS+2) | (paddr_t)((dreq.addr>>PAGE_M_NBITS)<<2);
+                    r_dcache_tlb_ptba_read = true;
+                    r_dcache_fsm = DCACHE_DTLB1_READ_CACHE;
+                }
+            }
+        }
+        else
+        {
+            r_dcache_fsm = DCACHE_WRITE_REQ;
+            drsp.valid = true;
+            drsp.rdata = 0;
+        }
+        break;
+    }
+    ////////////////////////
+    case DCACHE_WRITE_DIRTY:
+    {
+        m_cost_data_tlb_miss_frz++;
+
+        // external cache invalidate request
+        if ( r_tgt_dcache_req ) 
+        {
+            r_dcache_fsm = DCACHE_CC_CHECK;
+            r_dcache_fsm_save = r_dcache_fsm;
+            m_cost_data_waste_wait_frz++;
+            break;
+        }
+
+        if ( r_dcache_inval_tlb_rsp ) // Miss read response and tlb invalidation
+        {
+            r_dcache_fsm = DCACHE_IDLE;
+            r_dcache_inval_tlb_rsp = false;
+	    break;
+        }
+
+	if ( r_dcache_inval_rsp ) // TLB miss response and cache invalidation
+	{
+            r_dcache_fsm = DCACHE_IDLE; 
+            r_dcache_inval_rsp = false;
+	    break;	    
+	}
+
+        r_dcache.write(r_dcache_tlb_paddr, r_dcache_pte_update);
+        dcache_tlb.setdirty(r_dcache_tlb_way_save, r_dcache_tlb_set_save);
+        r_dcache_fsm = DCACHE_WRITE_REQ;
+        drsp.valid = true;
+        drsp.rdata = 0;
+        break;
+    }
+    /////////////////
+    case DCACHE_ERROR:
+    {
+        r_vci_rsp_data_error = false;
+        drsp.valid = true;
+        drsp.error = true;
+        drsp.rdata = 0;
+        r_dcache_fsm = DCACHE_IDLE;
+        break;
+    }   
+    ////////////////////// 
+    case DCACHE_ITLB_READ:
+    {
+        m_cost_data_waste_wait_frz++;
+
+        // external cache invalidate request
+        if ( r_tgt_dcache_req ) 
+        {
+            r_dcache_fsm = DCACHE_CC_CHECK;
+            r_dcache_fsm_save = r_dcache_fsm;
+            m_cost_data_waste_wait_frz++;
+            break;
+        }
+
+    	if ( r_vci_rsp_data_ok ) // vci response ok
+        {  
+            if ( r_vci_rsp_data_error )
+            {
+                r_dcache_rsp_itlb_error = true;	
+                r_itlb_read_dcache_req = false;
+                r_vci_rsp_data_error = false;
+                r_dcache_fsm = DCACHE_IDLE;
+
+		if (r_dcache_inval_rsp) r_dcache_inval_rsp = false;
+		break;
+            }
+
+	    if ( r_dcache_inval_rsp ) // TLB miss response and cache invalidation
+	    {
+	        if ( r_dcache_cleanup_req ) break;
+                r_dcache_cleanup_req = true;
+                r_dcache_cleanup_line = r_icache_paddr_save.read() >> (uint32_log2(m_dcache_words) + 2);  
+                r_dcache_fsm = DCACHE_IDLE;
+                r_dcache_inval_rsp = false;
+                break;
+	    }
+
+            r_dcache_fsm = DCACHE_ITLB_UPDT;
+        }
+	break;    	
+    }
+    //////////////////////
+    case DCACHE_ITLB_UPDT:
+    {
+        m_cost_data_waste_wait_frz++;
+
+        // external cache invalidate request
+        if ( r_tgt_dcache_req ) 
+        {
+            r_dcache_fsm = DCACHE_CC_CHECK;
+            r_dcache_fsm_save = r_dcache_fsm;
+            m_cost_data_waste_wait_frz++;
+            break;
+        }
+
+        if ( !r_dcache_cleanup_req )
+        {
+            data_t rsp_itlb_miss = 0;
+	    data_t rsp_itlb_ppn = 0;
+
+            paddr_t  victim_index = 0;
+            size_t way = 0;
+            size_t set = 0;
+
+	    if ( r_dcache_inval_rsp ) // TLB miss response and cache invalidation
+	    {
+                r_dcache_cleanup_req = true;
+                r_dcache_cleanup_line = r_icache_paddr_save.read() >> (uint32_log2(m_dcache_words) + 2);  
+                r_dcache_fsm = DCACHE_IDLE;
+                r_dcache_inval_rsp = false;
+                break;
+	    }           
+ 
+            bool cleanup = r_dcache.find(r_icache_paddr_save, r_dcache_in_itlb, r_dcache_in_dtlb, &way, &set, &victim_index);
+
+	    if ( cleanup )
+	    {	    
+		// ins tlb invalidate verification    
+                r_dcache_itlb_inval_req = r_dcache_in_itlb[m_dcache_sets*way+set];
+                r_dcache_itlb_inval_line = victim_index;
+                r_dcache_in_itlb[way*m_dcache_sets+set] = false;
+
+                // data tlb invalidate verification
+                r_dcache_dtlb_inval_req = r_dcache_in_dtlb[m_dcache_sets*way+set]; 
+                r_dcache_dtlb_inval_line = victim_index;
+                r_dcache_in_dtlb[way*m_dcache_sets+set] = false;
+
+                r_dcache_cleanup_req = true; 
+                r_dcache_cleanup_line = victim_index;
+		if ( r_dcache_in_itlb[m_dcache_sets*way+set] || r_dcache_in_dtlb[m_dcache_sets*way+set] )
+		{
+		    r_dcache_fsm = DCACHE_TLB_CC_INVAL;
+                    r_dcache_fsm_save = r_dcache_fsm;
+		    break;
+		}
+	    }
+
+            r_dcache.update(r_icache_paddr_save, way, set, r_dcache_miss_buf);
+
+            r_dcache.setinbit(r_icache_paddr_save, r_dcache_in_itlb, true);
+            bool itlb_hit_dcache = r_dcache.read(r_icache_paddr_save, &rsp_itlb_miss);	
+ 
+	    if ( r_itlb_k_read_dcache && itlb_hit_dcache )
+	    {	
+		r_itlb_k_read_dcache = false;
+            	bool itlb_hit_ppn = r_dcache.read(r_icache_paddr_save.read()+4, &rsp_itlb_ppn);
+		assert(itlb_hit_ppn && "Address of pte[64-32] and pte[31-0] should be successive");
+	    }
+
+            r_dcache_rsp_itlb_miss = rsp_itlb_miss;
+            r_dcache_rsp_itlb_ppn = rsp_itlb_ppn;
+            r_dcache_rsp_itlb_error = false;	
+            r_itlb_read_dcache_req = false;
+            r_dcache_fsm = DCACHE_IDLE;
+        }
+        break;
+    }
+    //////////////////////////
+    case DCACHE_ITLB_LL_WAIT:
+    {
+        // external cache invalidate request
+        if ( r_tgt_dcache_req )   
+        {
+            r_dcache_fsm = DCACHE_CC_CHECK;
+            r_dcache_fsm_save = r_dcache_fsm;
+            m_cost_data_waste_wait_frz++;
+            break;
+        }
+
+	if ( r_vci_rsp_data_ok )
+	{
+            if ( r_vci_rsp_data_error ) // VCI response ko
+            {
+                r_dcache_rsp_itlb_error = true;  
+                r_vci_rsp_data_error = false;
+                r_itlb_acc_dcache_req = false;
+		r_dcache_fsm = DCACHE_IDLE;
+		if (r_dcache_inval_rsp) r_dcache_inval_rsp = false;	
+            }
+	    else
+	    {
+	        if ( !(r_dcache_miss_buf[0] >> PTE_V_SHIFT) )	// unmapped
+	        {
+                    r_dcache_rsp_itlb_error = true;  
+                    r_itlb_acc_dcache_req = false;
+		    r_dcache_fsm = DCACHE_IDLE;	
+		    if (r_dcache_inval_rsp) r_dcache_inval_rsp = false;	
+	        }
+       		else if ( r_dcache_inval_rsp )
+       		{
+       		    r_dcache_inval_rsp = false;
+       		    r_dcache_fsm = DCACHE_IDLE;
+       		    m_cost_data_tlb_miss_frz++;
+       		}
+		else
+		{
+		    r_dcache_itlb_sc_acc_req = true;
+		    r_vci_rsp_data_ok = false;
+		    r_icache_pte_update = r_dcache_miss_buf[0] | r_icache_pte_update.read();	
+                    r_dcache_fsm = DCACHE_ITLB_SC_WAIT; 
+		}
+	    }
+	}
+	break;
+    }
+    //////////////////////////
+    case DCACHE_ITLB_SC_WAIT:
+    {
+        // external cache invalidate request
+        if ( r_tgt_dcache_req )   
+        {
+            r_dcache_fsm = DCACHE_CC_CHECK;
+            r_dcache_fsm_save = r_dcache_fsm;
+            m_cost_data_waste_wait_frz++;
+            break;
+        }
+	
+        if ( r_vci_rsp_data_ok ) 
+	{
+	    if ( r_vci_rsp_data_error ) // VCI response ko
+	    {
+	        r_dcache_rsp_itlb_error = true;  
+	        r_vci_rsp_data_error = false;
+	        r_itlb_acc_dcache_req = false;
+	        r_dcache_fsm = DCACHE_IDLE;
+		if (r_dcache_inval_rsp) r_dcache_inval_rsp = false;		
+	    }
+	    else
+	    {
+	        if ( r_dcache_inval_rsp )
+	        {
+	            r_dcache_inval_rsp = false;
+	            r_dcache_fsm = DCACHE_IDLE;
+		    if ( r_dcache_tlb_sc_fail ) r_dcache_tlb_sc_fail = false;
+	            m_cost_data_tlb_miss_frz++;
+	        }
+	        else if ( r_dcache_tlb_sc_fail )
+	        {
+		    r_dcache_itlb_ll_acc_req = true;
+		    r_vci_rsp_data_ok = false;
+		    r_dcache_tlb_sc_fail = false;
+	            r_dcache_fsm = DCACHE_ITLB_LL_WAIT; 
+	        }
+	        else 
+	        {
+	            r_itlb_acc_dcache_req = false;
+	            r_dcache_fsm = DCACHE_IDLE; 
+	        }
+	    }
+	}
+	break;
+    }
+    /////////////////////
+    case DCACHE_CC_CHECK:   // read directory in case of invalidate or update request
+    {
+        if ( dreq.valid ) m_cost_data_waste_wait_frz++;
+
+        m_cpt_dcache_dir_read += m_dcache_ways;
+        m_cpt_dcache_data_read += m_dcache_ways;
+
+        if((( /*( r_dcache_fsm_save == DCACHE_UNC_WAIT ) ||*/
+	     ( r_dcache_fsm_save == DCACHE_MISS_WAIT ) || ( r_dcache_fsm_save == DCACHE_MISS_UPDT ) ) && 
+           ( (r_dcache_paddr_save.read() & ~((m_dcache_words<<2)-1)) == (r_tgt_addr.read() & ~((m_dcache_words<<2)-1)))) 
+        || (( ( r_dcache_fsm_save == DCACHE_TLB1_READ )      || ( r_dcache_fsm_save == DCACHE_TLB2_READ )      ||
+	     ( r_dcache_fsm_save == DCACHE_TLB1_READ_UPDT ) || ( r_dcache_fsm_save == DCACHE_TLB2_READ_UPDT ) ||
+             ( r_dcache_fsm_save == DCACHE_TLB1_UPDT )      || ( r_dcache_fsm_save == DCACHE_TLB2_UPDT )  /*	  ||
+	     ( r_dcache_fsm_save == DCACHE_TLB1_LL_WAIT )   || ( r_dcache_fsm_save == DCACHE_TLB2_LL_WAIT )   ||
+	     ( r_dcache_fsm_save == DCACHE_TLB1_SC_WAIT )   || ( r_dcache_fsm_save == DCACHE_TLB2_SC_WAIT )   ||
+	     ( r_dcache_fsm_save == DCACHE_LL_DIRTY_WAIT )  || ( r_dcache_fsm_save == DCACHE_SC_DIRTY_WAIT )  ||
+	     ( r_dcache_fsm_save == DCACHE_WRITE_DIRTY ) */ ) && 
+           ( (r_dcache_tlb_paddr.read() & ~((m_dcache_words<<2)-1)) == (r_tgt_addr.read() & ~((m_dcache_words<<2)-1))) ) 
+        || (( ( r_dcache_fsm_save == DCACHE_ITLB_READ ) || ( r_dcache_fsm_save == DCACHE_ITLB_UPDT ) /*||
+             ( r_dcache_fsm_save == DCACHE_ITLB_LL_WAIT ) || ( r_dcache_fsm_save == DCACHE_ITLB_SC_WAIT )*/ ) && 
+           ( (r_icache_paddr_save.read() & ~((m_dcache_words<<2)-1)) == (r_tgt_addr.read() & ~((m_dcache_words<<2)-1))) ) ) 
+        {
+            r_dcache_inval_rsp = true;
+            r_tgt_dcache_req = false;
+            if ( r_tgt_update )
+	    {    // Also send a cleanup and answer
+                r_tgt_dcache_rsp = true;
+            } 
+	    else 
+	    {            // Also send a cleanup but don't answer
+                r_tgt_dcache_rsp = false;
+            }
+            r_dcache_fsm = r_dcache_fsm_save;
+        }
+	else
+	{
+            data_t dcache_rdata = 0;
+            size_t way = 0;
+            size_t set = 0;
+
+            bool dcache_hit = r_dcache.read(r_tgt_addr.read(), &dcache_rdata, &way, &set);
+
+            if ( dcache_hit )
+            {
+                if ( r_dcache_in_dtlb[m_dcache_sets*way+set] || r_dcache_in_itlb[m_dcache_sets*way+set] )
+                {
+            	    // ins tlb invalidate verification    
+                    r_dcache_itlb_inval_req = r_dcache_in_itlb[m_dcache_sets*way+set];
+                    r_dcache_itlb_inval_line = r_tgt_addr.read() >> (uint32_log2(m_dcache_words)+2);
+                    r_dcache_in_itlb[way*m_dcache_sets+set] = false;
+
+                    // data tlb invalidate verification
+                    r_dcache_dtlb_inval_req = r_dcache_in_dtlb[m_dcache_sets*way+set]; 
+                    r_dcache_dtlb_inval_line = r_tgt_addr.read() >> (uint32_log2(m_dcache_words)+2);
+                    r_dcache_in_dtlb[way*m_dcache_sets+set] = false;
+            	
+            	    r_dcache_cc_check = true;
+            	    r_dcache_fsm = DCACHE_TLB_CC_INVAL;
+            	    break;
+                }
+
+                if ( r_tgt_update ) // update 
+                {
+                    r_dcache_fsm = DCACHE_CC_UPDT;
+                } 
+                else                // invalidate 
+                {
+                    r_dcache_fsm = DCACHE_CC_INVAL;
+                }
+            }
+            else                    // nothing
+            {
+                r_dcache_fsm = DCACHE_CC_NOP;
+            }
+	}
+        break;
+    }
+    ///////////////////
+    case DCACHE_CC_UPDT:    // update directory and data cache        
+    {
+        if ( dreq.valid ) m_cost_data_waste_wait_frz++;
+
+        m_cpt_dcache_dir_write++;
+        m_cpt_dcache_data_write++;
+        data_t* buf = r_tgt_buf;
+        for( size_t i = 0; i < m_dcache_words; i++ )
+        {
+            if( r_tgt_val[i] ) r_dcache.write( r_tgt_addr.read() + i*4, buf[i] );
+        }
+           
+        r_tgt_dcache_req = false;
+	r_tgt_dcache_rsp = true;
+        r_dcache_fsm = r_dcache_fsm_save;
+        break;
+    }
+    /////////////////////
+    case DCACHE_CC_INVAL:   // invalidate a cache line
+    {
+        if ( dreq.valid ) m_cost_data_waste_wait_frz++;
+
+        r_tgt_dcache_rsp = r_dcache.inval(r_tgt_addr.read());
+        r_tgt_dcache_req = false;
+        r_dcache_fsm = r_dcache_fsm_save;
+        break;
+    }
+    ///////////////////
+    case DCACHE_CC_NOP:     // no external hit
+    {
+        if ( dreq.valid ) m_cost_data_waste_wait_frz++;
+
+        r_tgt_dcache_req = false;
+        if ( r_tgt_update )
+	{
+            r_tgt_dcache_rsp = true;
+        } 
+	else 
+	{
+            r_tgt_dcache_rsp = false;
+        }
+
+        r_dcache_fsm = r_dcache_fsm_save;
+        break;
+    }   
+    /////////////////////////
+    case DCACHE_TLB_CC_INVAL:
+    {
+        if ( dreq.valid ) m_cost_data_waste_wait_frz++;
+
+	if ( r_dcache_itlb_inval_req || r_dcache_dtlb_inval_req ) break;
+
+        if( (( r_dcache_fsm_save == DCACHE_TLB1_READ )        || ( r_dcache_fsm_save == DCACHE_TLB2_READ )        ||
+             ( r_dcache_fsm_save == DCACHE_TLB1_READ_UPDT )   || ( r_dcache_fsm_save == DCACHE_TLB2_READ_UPDT )   ||
+             ( r_dcache_fsm_save == DCACHE_TLB1_LL_WAIT )     || ( r_dcache_fsm_save == DCACHE_TLB2_LL_WAIT )     ||
+             ( r_dcache_fsm_save == DCACHE_TLB1_SC_WAIT )     || ( r_dcache_fsm_save == DCACHE_TLB2_SC_WAIT )     ||
+             ( r_dcache_fsm_save == DCACHE_TLB1_UPDT )        || ( r_dcache_fsm_save == DCACHE_TLB2_UPDT )        ||
+             ( r_dcache_fsm_save == DCACHE_DTLB1_READ_CACHE ) || ( r_dcache_fsm_save == DCACHE_DTLB2_READ_CACHE ) ||
+             ( r_dcache_fsm_save == DCACHE_LL_DIRTY_WAIT )    || ( r_dcache_fsm_save == DCACHE_SC_DIRTY_WAIT )    ||
+	     ( r_dcache_fsm_save == DCACHE_WRITE_DIRTY )) && 
+            (((r_dcache_tlb_paddr.read() & ~((m_dcache_words<<2)-1)) >> (uint32_log2(m_dcache_words) + 2)) == r_dcache_dtlb_inval_line.read()) ) 
+        {
+            r_dcache_inval_tlb_rsp = true;
+        } 
+
+        if (((r_dcache_fsm_save == DCACHE_BIS)||(r_dcache_fsm_save == DCACHE_MISS_WAIT) ||
+             (r_dcache_fsm_save == DCACHE_UNC_WAIT)||(r_dcache_fsm_save == DCACHE_MISS_UPDT)) && 
+             (r_dcache_tlb_nline == r_dcache_dtlb_inval_line))
+        {
+            r_dcache_inval_tlb_rsp = true;
+        }
+
+	if ( !r_dcache_cc_check )
+	{
+            r_dcache_fsm = r_dcache_fsm_save;
+	}
+	else
+	{
+            r_dcache_fsm = DCACHE_CC_CHECK;
+	    r_dcache_cc_check = false;
+	}
+	r_dtlb_translation_valid = false;
+        r_dcache_ptba_ok = false;
+        break;
+    }
+    /////////////////////////
+    case DCACHE_ITLB_CLEANUP:
+    {
+        if ( dreq.valid ) m_cost_data_waste_wait_frz++;
+
+        r_dcache.setinbit(((paddr_t)r_dcache_itlb_cleanup_line.read()*m_dcache_words*2), r_dcache_in_itlb, false);
+        r_dcache_itlb_cleanup_req = false;
+        r_dcache_fsm = DCACHE_IDLE;
+        break;
+    }
+    } // end switch r_dcache_fsm
+
+#ifdef SOCLIB_MODULE_DEBUG
+    std::cout << name() << " Data Response: " << drsp << std::endl;
+#endif
+
+    ////////////////////////////////////////////////////////////////////////////////////
+    //      INVAL DTLB CHECK FSM 
+    ////////////////////////////////////////////////////////////////////////////////////////
+    switch(r_inval_dtlb_fsm) {
+    /////////////////////
+    case INVAL_DTLB_IDLE:
+    {
+        if ( r_dcache_dtlb_inval_req ) 
+        {
+            r_ccinval_dtlb_way = 0;
+            r_ccinval_dtlb_set = 0;
+            r_inval_dtlb_fsm = INVAL_DTLB_CHECK;    
+            m_cost_data_tlb_inval_frz++;
+        }   
+        break;
+    }
+    ////////////////////////////
+    case INVAL_DTLB_CHECK:
+    {
+        m_cost_data_tlb_inval_frz++;
+
+        size_t way = r_ccinval_dtlb_way; 
+        size_t set = r_ccinval_dtlb_set;
+        bool end = false;        
+        bool tlb_hit = dcache_tlb.cccheck(r_dcache_dtlb_inval_line.read(), way, set, &way, &set, &end); 
+    
+        if ( tlb_hit )
+        {
+            r_ccinval_dtlb_way = way; 
+            r_ccinval_dtlb_set = set;
+            r_dtlb_cc_check_end = end;
+            r_inval_dtlb_fsm = INVAL_DTLB_INVAL;
+            m_cpt_data_tlb_inval++;    
+        }        
+        else
+        {
+            r_inval_dtlb_fsm = INVAL_DTLB_CLEAR;    
+        }
+        break;
+    }
+    /////////////////////////
+    case INVAL_DTLB_INVAL:
+    {
+        m_cost_data_tlb_inval_frz++;
+
+        dcache_tlb.ccinval(r_ccinval_dtlb_way, r_ccinval_dtlb_set);
+
+        if ( !r_dtlb_cc_check_end )
+        {
+            r_inval_dtlb_fsm = INVAL_DTLB_CHECK; 
+        }
+        else
+        {
+            r_inval_dtlb_fsm = INVAL_DTLB_CLEAR;    
+        }
+        break;
+    }
+    ////////////////////
+    case INVAL_DTLB_CLEAR:
+    {
+        r_dcache_dtlb_inval_req = false;
+        r_dtlb_cc_check_end = false;
+        r_ccinval_dtlb_way = 0; 
+        r_ccinval_dtlb_set = 0; 
+        r_inval_dtlb_fsm = INVAL_DTLB_IDLE;   
+        m_cpt_data_tlb_inval++;    
+        break;
+    }
+    } // end switch r_inval_itlb_fsm
+
+    if ( r_dcache_fsm == DCACHE_WRITE_REQ )
+    {
+        r_wbuf.write(true, r_dcache_paddr_save.read(), r_dcache_be_save.read(), r_dcache_wdata_save); 
+    }
+    else
+    {
+        r_wbuf.write(false, 0, 0, 0);
+    }
+    /////////// execute one iss cycle /////////////////////////////////
+    {
+    uint32_t it = 0;
+    for (size_t i=0; i<(size_t)iss_t::n_irq; i++) if(p_irq[i].read()) it |= (1<<i);
+    m_iss.executeNCycles(1, irsp, drsp, it);
+    }
+
+    ////////////// number of frozen cycles //////////////////////////
+    if ( (ireq.valid && !irsp.valid) || (dreq.valid && !drsp.valid) )
+    {
+        m_cpt_frz_cycles++;
+    }
+
+    ////////////////////////////////////////////////////////////////////////////
+    // This CLEANUP FSM controls the transmission of the cleanup transactions
+    // on the coherence network. It controls the following ressources:
+    // - r_cleanup_fsm
+    // - r_dcache_cleanup_req reset
+    // - r_icache_cleanup_req reset
+    // 
+    // This FSM handles cleanup requests from both the DCACHE FSM & ICACHE FSM
+    // 1 - Instruction Cleanup  : r_icache_cleanup_req 
+    // 2 - Data Cleanup         : r_dcache_cleanup_req 
+    // In case of simultaneous requests, the data request have highest priority.
+    // There is only one cleanup transaction at a given time (sequencial behavior)
+    // because the same FSM controls both command & response. 
+    // The the r_icache_cleanup_req & r_dcache_cleanup_req are reset only
+    // when the response packet is received.
+    // Error handling :
+    // As the coherence trafic is controled by hardware, errors are not reported
+    // to software : In case of errors, the simulation stops.
+    ////////////////////////////////////////////////////////////////////////////
+
+    switch (r_cleanup_fsm) {
+    //////////////////	
+    case CLEANUP_CMD:
+    {
+        if ( p_vci_ini_c.cmdack.read() )
+        {
+            if ( r_icache_cleanup_req ) 
+	    {
+	        r_cleanup_fsm = CLEANUP_ICACHE_RSP;
+	    }	
+            else if ( r_dcache_cleanup_req ) 
+	    {
+	        r_cleanup_fsm = CLEANUP_DCACHE_RSP;
+	    }
+	}    
+        break;
+    }
+    ////////////////////////
+    case CLEANUP_ICACHE_RSP:
+    {
+        if ( ! p_vci_ini_c.rspval.read() )
+            break;
+        assert( p_vci_ini_c.reop.read() && (p_vci_ini_c.rtrdid.read() == 1) &&
+                "illegal VCI response packet for icache cleanup");
+        assert( (p_vci_ini_c.rerror.read() == vci_param::ERR_NORMAL) &&
+                "error in response packet for icache cleanup");
+
+        r_icache_cleanup_req = false;
+        r_cleanup_fsm = CLEANUP_CMD;
+        break;
+    }
+    /////////////////////////		
+    case CLEANUP_DCACHE_RSP:
+    {
+        if ( ! p_vci_ini_c.rspval.read() )
+            break;
+        assert( p_vci_ini_c.reop.read() && (p_vci_ini_c.rtrdid.read() == 0) &&
+                "illegal VCI response packet for dcache cleanup");
+        assert( (p_vci_ini_c.rerror.read() == vci_param::ERR_NORMAL) &&
+                "error in response packet for dcache cleanup");
+
+        r_dcache_cleanup_req = false;
+        r_cleanup_fsm = CLEANUP_CMD;
+        break;
+    }
+    } // end switch r_cleanup_fsm
+
+    ////////////////////////////////////////////////////////////////////////////
+    //     VCI_CMD FSM 
+    //
+    // This FSM handles requests from both the DCACHE controler
+    // (request registers) and the ICACHE controler (request registers).
+    // There is 10 VCI transaction types :
+    // - INS_TLB_READ
+    // - INS_TLB_WRITE
+    // - INS_MISS
+    // - INS_UNC_MISS
+    // - DATA_TLB_READ
+    // - DATA_TLB_WRITE
+    // - DATA_TLB_DIRTY
+    // - DATA_MISS
+    // - DATA_UNC 
+    // - DATA_WRITE
+    // The ICACHE requests have the highest priority.
+    // There is at most one (CMD/RSP) VCI transaction, as both CMD_FSM and RSP_FSM
+    // exit simultaneously the IDLE state.
+    //////////////////////////////////////////////////////////////////////////////
+
+    switch (r_vci_cmd_fsm) {
+    
+    case CMD_IDLE:
+        if (r_dcache_itlb_read_req && r_wbuf.miss( r_icache_paddr_save ))           
+        {            
+            r_vci_cmd_fsm = CMD_ITLB_READ;
+	    r_dcache_itlb_read_req = false;
+            m_cpt_itlbmiss_transaction++; 
+        } 
+	else if (r_dcache_itlb_ll_acc_req && r_wbuf.miss( r_icache_paddr_save ))
+	{
+	    r_vci_cmd_fsm = CMD_ITLB_ACC_LL;
+	    r_dcache_itlb_ll_acc_req = false;
+            m_cpt_itlb_write_transaction++; 
+	}
+	else if (r_dcache_itlb_sc_acc_req && r_wbuf.miss( r_icache_paddr_save ))
+	{
+	    r_vci_cmd_fsm = CMD_ITLB_ACC_SC;
+	    r_dcache_itlb_sc_acc_req = false;	    
+	    m_cpt_itlb_write_transaction++; 
+	}
+        else if (r_icache_miss_req && r_wbuf.miss( r_icache_paddr_save )) 
+        {    
+            r_vci_cmd_fsm = CMD_INS_MISS;
+	    r_icache_miss_req = false;
+            m_cpt_imiss_transaction++; 
+        }
+        else if (r_icache_unc_req && r_wbuf.miss( r_icache_paddr_save )) 
+        {    
+            r_vci_cmd_fsm = CMD_INS_UNC;
+	    r_icache_unc_req = false;
+            m_cpt_imiss_transaction++; 
+        }  
+        else if (r_dcache_tlb_read_req && r_wbuf.miss( r_dcache_tlb_paddr )) 
+        {            
+            r_vci_cmd_fsm = CMD_DTLB_READ;
+	    r_dcache_tlb_read_req = false;	    
+	    m_cpt_dtlbmiss_transaction++; 
+        } 
+        else if (r_dcache_tlb_ll_acc_req && r_wbuf.miss( r_dcache_tlb_paddr )) 
+        {  
+            r_vci_cmd_fsm = CMD_DTLB_ACC_LL;
+	    r_dcache_tlb_ll_acc_req = false;
+            m_cpt_dtlb_write_transaction++; 
+        } 
+        else if (r_dcache_tlb_sc_acc_req && r_wbuf.miss( r_dcache_tlb_paddr )) 
+        {  
+            r_vci_cmd_fsm = CMD_DTLB_ACC_SC;
+	    r_dcache_tlb_sc_acc_req = false;
+            m_cpt_dtlb_write_transaction++; 
+        } 
+        else if (r_dcache_tlb_ll_dirty_req && r_wbuf.miss( r_dcache_tlb_paddr )) 
+        {  
+            r_vci_cmd_fsm = CMD_DTLB_DIRTY_LL;
+	    r_dcache_tlb_ll_dirty_req = false;
+            m_cpt_dtlb_write_transaction++; 
+        } 
+        else if (r_dcache_tlb_sc_dirty_req && r_wbuf.miss( r_dcache_tlb_paddr )) 
+        {  
+            r_vci_cmd_fsm = CMD_DTLB_DIRTY_SC;
+	    r_dcache_tlb_sc_dirty_req = false;
+            m_cpt_dtlb_write_transaction++; 
+        } 
+        else if (r_dcache_miss_req && r_wbuf.miss( r_dcache_paddr_save ))  
+        {
+            r_vci_cmd_fsm = CMD_DATA_MISS;
+	    r_dcache_miss_req = false;
+            m_cpt_dmiss_transaction++; 
+        }
+        else if (r_dcache_unc_req && r_wbuf.miss( r_dcache_paddr_save ))  
+        {
+            r_vci_cmd_fsm = CMD_DATA_UNC;
+	    r_dcache_unc_req = false;
+            m_cpt_unc_transaction++; 
+        }
+	else if ( r_wbuf.rok() )
+        {
+            r_vci_cmd_fsm = CMD_DATA_WRITE;
+            r_vci_cmd_cpt = r_wbuf.getMin();
+            r_vci_cmd_min = r_wbuf.getMin();
+            r_vci_cmd_max = r_wbuf.getMax(); 
+            m_cpt_write_transaction++; 
+            m_length_write_transaction += (r_wbuf.getMax() - r_wbuf.getMin() + 1);
+        }
+        break;
+
+    case CMD_DATA_WRITE:
+        if ( p_vci_ini_rw.cmdack.read() ) 
+        {
+            r_vci_cmd_cpt = r_vci_cmd_cpt + 1;
+            if (r_vci_cmd_cpt == r_vci_cmd_max) 
+            {
+                r_vci_cmd_fsm = CMD_IDLE;
+                r_wbuf.sent();
+            }
+        }
+        break;
+
+    default:
+        if ( p_vci_ini_rw.cmdack.read() )
+        {  
+            r_vci_cmd_fsm = CMD_IDLE;
+        }
+        break;
+
+    } // end  switch r_vci_cmd_fsm
+
+    //////////////////////////////////////////////////////////////////////////
+    //      VCI_RSP FSM 
+    //
+    // This FSM is synchronized with the VCI_CMD FSM, as both FSMs exit the
+    // IDLE state simultaneously.
+    //////////////////////////////////////////////////////////////////////////
+
+    switch (r_vci_rsp_fsm) {
+
+    case RSP_IDLE:
+	if ( p_vci_ini_rw.rspval.read() )
+	{	
+            r_vci_rsp_cpt = 0;
+	    if ( (p_vci_ini_rw.rtrdid.read() & 0x20) != 0 )         // DCACHE write response
+            {
+                r_vci_rsp_fsm = RSP_DATA_WRITE;
+            }
+            else if ( p_vci_ini_rw.rtrdid.read() == TYPE_INS_TLB )          // ITLB miss response
+            {            
+                r_vci_rsp_fsm = RSP_ITLB_READ;
+            } 
+            else if ( p_vci_ini_rw.rtrdid.read() == TYPE_INS_LL_ACC )   // ITLB linked load response
+            {   
+                r_vci_rsp_fsm = RSP_ITLB_ACC_LL;
+            } 
+            else if ( p_vci_ini_rw.rtrdid.read() == TYPE_INS_SC_ACC )   // ITLB store conditional response
+            {   
+                r_vci_rsp_fsm = RSP_ITLB_ACC_SC;
+            } 
+            else if ( p_vci_ini_rw.rtrdid.read() == TYPE_INS_MISS )          // ICACHE cached miss response
+            {   
+                r_vci_rsp_fsm = RSP_INS_MISS;
+            }
+            else if ( p_vci_ini_rw.rtrdid.read() == TYPE_INS_UNC )           // ICACHE uncached miss response
+            {   
+                r_vci_rsp_fsm = RSP_INS_UNC;
+            }  
+            else if ( p_vci_ini_rw.rtrdid.read() == TYPE_DATA_TLB )      // ITLB miss response
+            {
+                r_vci_rsp_fsm = RSP_DTLB_READ; 
+            }
+            else if ( p_vci_ini_rw.rtrdid.read() == TYPE_DATA_LL_ACC )    // DTLB access bits linked load response
+            {
+                r_vci_rsp_fsm = RSP_DTLB_ACC_LL; 
+            }
+            else if ( p_vci_ini_rw.rtrdid.read() == TYPE_DATA_SC_ACC )    // DTLB access bits store conditional response
+            {
+                r_vci_rsp_fsm = RSP_DTLB_ACC_SC; 
+            }
+            else if ( p_vci_ini_rw.rtrdid.read() == TYPE_DATA_LL_D )  // DTLB dirty bit linked load response
+            {
+                r_vci_rsp_fsm = RSP_DTLB_DIRTY_LL; 
+            }
+            else if ( p_vci_ini_rw.rtrdid.read() == TYPE_DATA_SC_D )  // DTLB dirty bit store conditional response
+            {
+                r_vci_rsp_fsm = RSP_DTLB_DIRTY_SC; 
+            }
+            else if ( p_vci_ini_rw.rtrdid.read() == TYPE_DATA_MISS )          // DCACHE read response
+            {
+                r_vci_rsp_fsm = RSP_DATA_MISS;
+            }
+            else if ( p_vci_ini_rw.rtrdid.read() == TYPE_DATA_UNC )           // DCACHE uncached read response
+            {
+                r_vci_rsp_fsm = RSP_DATA_UNC;
+            }
+	}
+        break;
+
+    case RSP_ITLB_READ:
+        m_cost_itlbmiss_transaction++;
+        if ( ! p_vci_ini_rw.rspval.read() )
+            break;
+
+        assert(r_vci_rsp_cpt != m_dcache_words &&
+               "illegal VCI response packet for data read miss");
+
+        r_vci_rsp_cpt = r_vci_rsp_cpt + 1;
+        r_dcache_miss_buf[r_vci_rsp_cpt] = (data_t)p_vci_ini_rw.rdata.read();
+        if ( p_vci_ini_rw.reop.read() ) 
+        {
+            assert(r_vci_rsp_cpt == m_dcache_words - 1 &&
+                    "illegal VCI response packet for data read miss");
+
+	    r_vci_rsp_data_ok = true;
+            r_vci_rsp_fsm = RSP_IDLE;
+        } 
+        if ( p_vci_ini_rw.rerror.read() != vci_param::ERR_NORMAL )
+        {
+            r_vci_rsp_data_error = true;
+        }
+        break;
+
+    case RSP_ITLB_ACC_LL:
+        if ( ! p_vci_ini_rw.rspval.read() )
+            break;
+
+        assert(p_vci_ini_rw.reop.read() &&
+               "illegal VCI response packet for ll tlb");
+
+        if ( p_vci_ini_rw.rerror.read() != vci_param::ERR_NORMAL ) 
+        {
+            r_vci_rsp_data_error = true;
+        }
+	else
+	{
+	    r_dcache_miss_buf[0] = (data_t)p_vci_ini_rw.rdata.read();
+	}
+	r_vci_rsp_data_ok = true;
+        r_vci_rsp_fsm = RSP_IDLE;
+	break;
+
+    case RSP_ITLB_ACC_SC:
+        if ( ! p_vci_ini_rw.rspval.read() )
+            break;
+
+        assert(p_vci_ini_rw.reop.read() &&
+               "illegal VCI response packet for sc tlb");
+
+        if ( p_vci_ini_rw.rerror.read() != vci_param::ERR_NORMAL ) 
+        {
+            r_vci_rsp_data_error = true;
+        }
+	else if ( p_vci_ini_rw.rdata.read() == 1 ) // store conditional is not successful
+	{
+	    r_dcache_tlb_sc_fail = true;
+	}
+	r_vci_rsp_data_ok = true;
+        r_vci_rsp_fsm = RSP_IDLE;
+	break;
+
+    case RSP_INS_MISS:
+        m_cost_imiss_transaction++;
+        if ( ! p_vci_ini_rw.rspval.read() )
+            break;
+
+        assert( (r_vci_rsp_cpt < m_icache_words) && 
+               "The VCI response packet for instruction miss is too long");
+        r_vci_rsp_cpt = r_vci_rsp_cpt + 1;
+        r_icache_miss_buf[r_vci_rsp_cpt] = (data_t)p_vci_ini_rw.rdata.read();
+
+        if ( p_vci_ini_rw.reop.read() ) 
+        {
+            assert( (r_vci_rsp_cpt == m_icache_words - 1) &&
+                       "The VCI response packet for instruction miss is too short");
+	    r_vci_rsp_ins_ok = true;
+            r_vci_rsp_fsm = RSP_IDLE;
+                
+        } 
+        if ( p_vci_ini_rw.rerror.read() != vci_param::ERR_NORMAL )
+        {
+            r_vci_rsp_ins_error = true;
+        }
+        break;
+
+    case RSP_INS_UNC:
+        m_cost_imiss_transaction++;
+        if ( ! p_vci_ini_rw.rspval.read() )
+            break;
+
+        assert(p_vci_ini_rw.reop.read() &&
+               "illegal VCI response packet for uncached instruction");
+
+        r_icache_miss_buf[0] = (data_t)p_vci_ini_rw.rdata.read();
+	r_vci_rsp_ins_ok = true;
+        r_vci_rsp_fsm = RSP_IDLE;
+
+        if ( p_vci_ini_rw.rerror.read() != vci_param::ERR_NORMAL )
+        {
+            r_vci_rsp_ins_error = true;
+        }
+        break;
+
+    case RSP_DTLB_READ:
+        m_cost_dtlbmiss_transaction++;
+        if ( ! p_vci_ini_rw.rspval.read() )
+            break;
+
+        assert(r_vci_rsp_cpt != m_dcache_words &&
+               "illegal VCI response packet for data read miss");
+
+        r_vci_rsp_cpt = r_vci_rsp_cpt + 1;
+        r_dcache_miss_buf[r_vci_rsp_cpt] = (data_t)p_vci_ini_rw.rdata.read();
+        if ( p_vci_ini_rw.reop.read() ) 
+        {
+            assert(r_vci_rsp_cpt == m_dcache_words - 1 &&
+                    "illegal VCI response packet for data read miss");
+	    r_vci_rsp_data_ok = true;
+            r_vci_rsp_fsm = RSP_IDLE;
+        } 
+        if ( p_vci_ini_rw.rerror.read() != vci_param::ERR_NORMAL )
+        {
+            r_vci_rsp_data_error = true;
+        }
+        break;
+
+    case RSP_DTLB_ACC_LL:
+        if ( ! p_vci_ini_rw.rspval.read() )
+            break;
+
+        assert(p_vci_ini_rw.reop.read() &&
+               "illegal VCI response packet for ll tlb");
+
+        if ( p_vci_ini_rw.rerror.read() != vci_param::ERR_NORMAL ) 
+        {
+            r_vci_rsp_data_error = true;
+        }
+	else
+	{
+	    r_dcache_miss_buf[0] = (data_t)p_vci_ini_rw.rdata.read();
+	}
+	r_vci_rsp_data_ok = true;
+        r_vci_rsp_fsm = RSP_IDLE;
+	break;
+
+    case RSP_DTLB_ACC_SC:
+        if ( ! p_vci_ini_rw.rspval.read() )
+            break;
+
+        assert(p_vci_ini_rw.reop.read() &&
+               "illegal VCI response packet for sc tlb");
+
+        if ( p_vci_ini_rw.rerror.read() != vci_param::ERR_NORMAL ) 
+        {
+            r_vci_rsp_data_error = true;
+        }
+	else if ( p_vci_ini_rw.rdata.read() == 1 ) // store conditional is not successful
+	{
+	    r_dcache_tlb_sc_fail = true;
+	}
+	r_vci_rsp_data_ok = true;
+        r_vci_rsp_fsm = RSP_IDLE;
+	break;
+
+    case RSP_DTLB_DIRTY_LL:
+        if ( ! p_vci_ini_rw.rspval.read() )
+            break;
+
+        assert(p_vci_ini_rw.reop.read() &&
+               "illegal VCI response packet for ll tlb");
+
+        if ( p_vci_ini_rw.rerror.read() != vci_param::ERR_NORMAL ) 
+        {
+            r_vci_rsp_data_error = true;
+        }
+	else
+	{
+	    r_dcache_miss_buf[0] = (data_t)p_vci_ini_rw.rdata.read();
+	}
+	r_vci_rsp_data_ok = true;
+        r_vci_rsp_fsm = RSP_IDLE;
+	break;
+
+    case RSP_DTLB_DIRTY_SC:
+        if ( ! p_vci_ini_rw.rspval.read() )
+            break;
+
+        assert(p_vci_ini_rw.reop.read() &&
+               "illegal VCI response packet for sc tlb");
+
+        if ( p_vci_ini_rw.rerror.read() != vci_param::ERR_NORMAL ) 
+        {
+            r_vci_rsp_data_error = true;
+        }
+	else if ( p_vci_ini_rw.rdata.read() == 1 ) // store conditional is not successful
+	{
+	    r_dcache_tlb_sc_fail = true;
+	}
+	r_vci_rsp_data_ok = true;
+        r_vci_rsp_fsm = RSP_IDLE;
+	break;
+
+    case RSP_DATA_UNC:
+        m_cost_unc_transaction++;
+        if ( ! p_vci_ini_rw.rspval.read() ) 
+            break;
+
+        assert(p_vci_ini_rw.reop.read() &&
+               "illegal VCI response packet for data read uncached");
+
+        if ( p_vci_ini_rw.rerror.read() != vci_param::ERR_NORMAL ) 
+        {
+            r_vci_rsp_data_error = true;
+        }
+        else
+        {
+            r_dcache_miss_buf[0] = (data_t)p_vci_ini_rw.rdata.read();
+	    r_vci_rsp_data_ok = true;
+        }
+        r_vci_rsp_fsm = RSP_IDLE;
+        break;
+
+    case RSP_DATA_MISS:
+        m_cost_dmiss_transaction++;
+        if ( ! p_vci_ini_rw.rspval.read() )
+            break;
+
+        assert(r_vci_rsp_cpt != m_dcache_words &&
+               "illegal VCI response packet for data read miss");
+
+        r_vci_rsp_cpt = r_vci_rsp_cpt + 1;
+        r_dcache_miss_buf[r_vci_rsp_cpt] = (data_t)p_vci_ini_rw.rdata.read();
+        if ( p_vci_ini_rw.reop.read() ) 
+        {
+            assert(r_vci_rsp_cpt == m_dcache_words - 1 &&
+                    "illegal VCI response packet for data read miss");
+	    r_vci_rsp_data_ok = true;
+            r_vci_rsp_fsm = RSP_IDLE;
+        } 
+        if ( p_vci_ini_rw.rerror.read() != vci_param::ERR_NORMAL )
+        {
+            r_vci_rsp_data_error = true;
+        }
+        break;
+
+    case RSP_DATA_WRITE:
+        m_cost_write_transaction++;
+        if ( ! p_vci_ini_rw.rspval.read() )
+            break;
+
+        if ( p_vci_ini_rw.reop.read() ) 
+        {
+            r_vci_rsp_fsm = RSP_IDLE;
+	    r_wbuf.completed( p_vci_ini_rw.rtrdid.read() & 0x1f );
+        }
+        if ( p_vci_ini_rw.rerror.read() != vci_param::ERR_NORMAL ) 
+        {
+            m_iss.setWriteBerr();
+        }
+        break;
+    } // end switch r_vci_rsp_fsm
+} // end transition()
+
+///////////////////////
+tmpl(void)::genMoore()
+///////////////////////
+{
+    switch ( r_cleanup_fsm.read() ) {
+
+    case CLEANUP_CMD:
+	p_vci_ini_c.rspack  = false;
+        p_vci_ini_c.cmdval  = r_icache_cleanup_req || r_dcache_cleanup_req;
+        if ( r_icache_cleanup_req ) 
+	{
+	    p_vci_ini_c.address = r_icache_cleanup_line.read() * (m_icache_words<<2);
+            p_vci_ini_c.trdid  = 1; // cleanup instruction
+	}
+        else 
+	{                                    
+	    p_vci_ini_c.address = r_dcache_cleanup_line.read() * (m_dcache_words<<2);
+            p_vci_ini_c.trdid  = 0; // cleanup data
+	}
+        p_vci_ini_c.wdata  = 0;
+        p_vci_ini_c.be     = 0xF;
+        p_vci_ini_c.plen   = 4;
+        p_vci_ini_c.cmd    = vci_param::CMD_WRITE;
+        p_vci_ini_c.pktid  = 0;
+        p_vci_ini_c.srcid  = m_srcid_c;
+        p_vci_ini_c.cons   = false;
+        p_vci_ini_c.wrap   = false;
+        p_vci_ini_c.contig = false;
+        p_vci_ini_c.clen   = 0;
+        p_vci_ini_c.cfixed = false;
+        p_vci_ini_c.eop = true;
+        break;
+
+    case CLEANUP_ICACHE_RSP:
+    case CLEANUP_DCACHE_RSP:
+        p_vci_ini_c.rspack  = true;
+        p_vci_ini_c.cmdval  = false;
+        p_vci_ini_c.address = 0;
+        p_vci_ini_c.wdata   = 0;
+        p_vci_ini_c.be      = 0;
+        p_vci_ini_c.plen    = 0;
+        p_vci_ini_c.cmd     = vci_param::CMD_NOP;
+        p_vci_ini_c.trdid   = 0;
+        p_vci_ini_c.pktid   = 0;
+        p_vci_ini_c.srcid   = m_srcid_c;
+        p_vci_ini_c.cons    = false;
+        p_vci_ini_c.wrap    = false;
+        p_vci_ini_c.contig  = false;
+        p_vci_ini_c.clen    = 0;
+        p_vci_ini_c.cfixed  = false;
+        p_vci_ini_c.eop     = false;
+	break;
+    } // end switch r_cleanup_fsm
+
+    // VCI initiator response
+    p_vci_ini_rw.rspack = ( r_vci_rsp_fsm != RSP_IDLE );
+
+    // VCI initiator command
+    p_vci_ini_rw.srcid  = m_srcid_rw;
+    p_vci_ini_rw.cons   = false;
+    p_vci_ini_rw.wrap   = false;
+    p_vci_ini_rw.contig = true;
+    p_vci_ini_rw.clen   = 0;
+    p_vci_ini_rw.cfixed = false;
+
+    switch (r_vci_cmd_fsm) {
+
+    case CMD_IDLE:
+        p_vci_ini_rw.cmdval  = false;
+        p_vci_ini_rw.address = 0;
+        p_vci_ini_rw.wdata   = 0;
+        p_vci_ini_rw.be      = 0;
+        p_vci_ini_rw.trdid   = 0;
+	p_vci_ini_rw.pktid   = 0;
+        p_vci_ini_rw.plen    = 0;
+        p_vci_ini_rw.cmd     = vci_param::CMD_NOP;
+        p_vci_ini_rw.eop     = false;
+        break;
+
+    case CMD_ITLB_READ:     
+        p_vci_ini_rw.cmdval  = true;
+        p_vci_ini_rw.address = r_icache_paddr_save.read() & m_dcache_yzmask;
+        p_vci_ini_rw.wdata   = 0;
+        p_vci_ini_rw.be      = 0xF;
+        p_vci_ini_rw.trdid   = TYPE_INS_TLB; // via data cache cached read
+	p_vci_ini_rw.pktid   = 0;
+        p_vci_ini_rw.plen    = m_dcache_words << 2;
+        p_vci_ini_rw.cmd     = vci_param::CMD_READ;
+        p_vci_ini_rw.eop     = true;
+        break;
+
+    case CMD_ITLB_ACC_LL:
+        p_vci_ini_rw.cmdval  = true;
+        p_vci_ini_rw.address = r_icache_paddr_save.read() & ~0x3;
+        p_vci_ini_rw.wdata   = 0;
+        p_vci_ini_rw.be      = 0xF;
+        p_vci_ini_rw.trdid   = TYPE_INS_LL_ACC; // data cache uncached read
+	p_vci_ini_rw.pktid   = 0;
+        p_vci_ini_rw.plen    = 4;
+        p_vci_ini_rw.cmd     = vci_param::CMD_LOCKED_READ;
+        p_vci_ini_rw.eop     = true;
+	break;
+
+    case CMD_ITLB_ACC_SC:
+        p_vci_ini_rw.cmdval  = true;
+        p_vci_ini_rw.address = r_icache_paddr_save.read() & ~0x3;
+        p_vci_ini_rw.wdata   = r_icache_pte_update.read();
+        p_vci_ini_rw.be      = 0xF;
+        p_vci_ini_rw.trdid   = TYPE_INS_SC_ACC; // data cache uncached read
+	p_vci_ini_rw.pktid   = 0;
+        p_vci_ini_rw.plen    = 4;
+        p_vci_ini_rw.cmd     = vci_param::CMD_STORE_COND;
+        p_vci_ini_rw.eop     = true;
+	break;	
+
+    case CMD_INS_MISS:
+        p_vci_ini_rw.cmdval  = true;
+        p_vci_ini_rw.address = r_icache_paddr_save.read() & m_icache_yzmask;
+        p_vci_ini_rw.wdata   = 0;
+        p_vci_ini_rw.be      = 0xF;
+        p_vci_ini_rw.trdid   = TYPE_INS_MISS; // ins cache cached read
+	p_vci_ini_rw.pktid   = 0;
+        p_vci_ini_rw.plen    = m_icache_words << 2;
+        p_vci_ini_rw.cmd     = vci_param::CMD_READ;
+        p_vci_ini_rw.eop     = true;
+        break;
+
+    case CMD_INS_UNC:
+        p_vci_ini_rw.cmdval  = true;
+        p_vci_ini_rw.address = r_icache_paddr_save.read() & ~0x3;
+        p_vci_ini_rw.wdata   = 0;
+        p_vci_ini_rw.be      = 0xF;
+        p_vci_ini_rw.trdid   = TYPE_INS_UNC; // ins cache uncached read
+	p_vci_ini_rw.pktid   = 0;
+        p_vci_ini_rw.plen    = 4;
+        p_vci_ini_rw.cmd     = vci_param::CMD_READ;
+        p_vci_ini_rw.eop     = true;
+        break;
+
+    case CMD_DTLB_READ:     
+        p_vci_ini_rw.cmdval  = true;
+        p_vci_ini_rw.address = r_dcache_tlb_paddr.read() & m_dcache_yzmask;
+        p_vci_ini_rw.wdata   = 0;
+        p_vci_ini_rw.be      = 0xF;
+        p_vci_ini_rw.trdid   = TYPE_DATA_TLB; // via dcache cached read
+	p_vci_ini_rw.pktid   = 0;
+        p_vci_ini_rw.plen    = m_dcache_words << 2;
+        p_vci_ini_rw.cmd     = vci_param::CMD_READ;
+        p_vci_ini_rw.eop     = true;
+        break;
+
+    case CMD_DTLB_ACC_LL:
+        p_vci_ini_rw.cmdval  = true;
+        p_vci_ini_rw.address = r_dcache_tlb_paddr.read() & ~0x3;
+        p_vci_ini_rw.wdata   = 0;
+        p_vci_ini_rw.be      = 0xF;
+        p_vci_ini_rw.trdid   = TYPE_DATA_LL_ACC; // data cache uncached read
+	p_vci_ini_rw.pktid   = 0;
+        p_vci_ini_rw.plen    = 4;
+        p_vci_ini_rw.cmd     = vci_param::CMD_LOCKED_READ;
+        p_vci_ini_rw.eop     = true;
+	break;
+
+    case CMD_DTLB_ACC_SC:
+        p_vci_ini_rw.cmdval  = true;
+        p_vci_ini_rw.address = r_dcache_tlb_paddr.read() & ~0x3;
+        p_vci_ini_rw.wdata   = r_dcache_pte_update.read();
+        p_vci_ini_rw.be      = 0xF;
+        p_vci_ini_rw.trdid   = TYPE_DATA_SC_ACC; // data cache uncached read
+	p_vci_ini_rw.pktid   = 0;
+        p_vci_ini_rw.plen    = 4;
+        p_vci_ini_rw.cmd     = vci_param::CMD_STORE_COND;
+        p_vci_ini_rw.eop     = true;
+	break;	
+
+    case CMD_DTLB_DIRTY_LL:
+        p_vci_ini_rw.cmdval  = true;
+        p_vci_ini_rw.address = r_dcache_tlb_paddr.read() & ~0x3;
+        p_vci_ini_rw.wdata   = 0;
+        p_vci_ini_rw.be      = 0xF;
+        p_vci_ini_rw.trdid   = TYPE_DATA_LL_D; // data cache uncached read
+	p_vci_ini_rw.pktid   = 0;
+        p_vci_ini_rw.plen    = 4;
+        p_vci_ini_rw.cmd     = vci_param::CMD_LOCKED_READ;
+        p_vci_ini_rw.eop     = true;
+	break;
+
+    case CMD_DTLB_DIRTY_SC:
+        p_vci_ini_rw.cmdval  = true;
+        p_vci_ini_rw.address = r_dcache_tlb_paddr.read() & ~0x3;
+        p_vci_ini_rw.wdata   = r_dcache_pte_update.read();
+        p_vci_ini_rw.be      = 0xF;
+        p_vci_ini_rw.trdid   = TYPE_DATA_SC_D; // data cache uncached read
+	p_vci_ini_rw.pktid   = 0;
+        p_vci_ini_rw.plen    = 4;
+        p_vci_ini_rw.cmd     = vci_param::CMD_STORE_COND;
+        p_vci_ini_rw.eop     = true;
+	break;	
+
+    case CMD_DATA_UNC:
+        p_vci_ini_rw.cmdval  = true;
+        p_vci_ini_rw.address = r_dcache_paddr_save.read() & ~0x3;
+        p_vci_ini_rw.trdid   = TYPE_DATA_UNC; // data cache uncached read
+	p_vci_ini_rw.pktid   = 0;
+        p_vci_ini_rw.plen    = 4;
+        p_vci_ini_rw.eop     = true;
+        switch(r_dcache_type_save) {
+        case iss_t::DATA_READ:
+            p_vci_ini_rw.wdata = 0;
+            p_vci_ini_rw.be    = r_dcache_be_save.read();
+            p_vci_ini_rw.cmd   = vci_param::CMD_READ;
+            break;
+        case iss_t::DATA_LL:
+            p_vci_ini_rw.wdata = 0;
+            p_vci_ini_rw.be    = 0xF;
+            p_vci_ini_rw.cmd   = vci_param::CMD_LOCKED_READ;
+            break;
+        case iss_t::DATA_SC:
+            p_vci_ini_rw.wdata = r_dcache_wdata_save.read();
+            p_vci_ini_rw.be    = 0xF;
+            p_vci_ini_rw.cmd   = vci_param::CMD_STORE_COND;
+            break;
+        default:
+            assert("this should not happen");
+        }
+        break;
+
+    case CMD_DATA_WRITE:
+        p_vci_ini_rw.cmdval  = true;
+        p_vci_ini_rw.address = r_wbuf.getAddress(r_vci_cmd_cpt);
+        p_vci_ini_rw.wdata   = r_wbuf.getData(r_vci_cmd_cpt);
+        p_vci_ini_rw.be      = r_wbuf.getBe(r_vci_cmd_cpt);
+        p_vci_ini_rw.trdid   = (r_wbuf.getIndex() | 0x20); // data cache write
+	p_vci_ini_rw.pktid   = 0;
+        p_vci_ini_rw.plen    = (r_vci_cmd_max - r_vci_cmd_min + 1)<<2;
+        p_vci_ini_rw.cmd     = vci_param::CMD_WRITE;
+        p_vci_ini_rw.eop     = (r_vci_cmd_cpt == r_vci_cmd_max);
+        break;
+
+    case CMD_DATA_MISS:
+        p_vci_ini_rw.cmdval  = true;
+        p_vci_ini_rw.address = r_dcache_paddr_save.read() & m_dcache_yzmask;
+        p_vci_ini_rw.wdata   = 0;
+        p_vci_ini_rw.be      = 0xF;
+        p_vci_ini_rw.trdid   = TYPE_DATA_MISS; // data cache cached read
+	p_vci_ini_rw.pktid   = 0;
+        p_vci_ini_rw.plen    = m_dcache_words << 2;
+        p_vci_ini_rw.cmd     = vci_param::CMD_READ;
+        p_vci_ini_rw.eop     = true;
+        break;
+
+    } // end switch r_vci_cmd_fsm
+
+    // VCI_TGT
+    switch ( r_vci_tgt_fsm.read() ) {
+
+    case TGT_IDLE:
+    case TGT_UPDT_WORD:
+    case TGT_UPDT_DATA:
+        p_vci_tgt.cmdack  = true;
+        p_vci_tgt.rspval  = false;
+        break;
+
+    case TGT_RSP_BROADCAST:
+        p_vci_tgt.cmdack  = false;
+        p_vci_tgt.rspval  = !r_tgt_icache_req.read() && !r_tgt_dcache_req.read() && ( r_tgt_icache_rsp | r_tgt_dcache_rsp );
+        p_vci_tgt.rsrcid  = r_tgt_srcid.read();
+        p_vci_tgt.rpktid  = r_tgt_pktid.read();
+        p_vci_tgt.rtrdid  = r_tgt_trdid.read();
+        p_vci_tgt.rdata   = 0;
+        p_vci_tgt.rerror  = 0;
+        p_vci_tgt.reop    = true;
+        break;
+
+    case TGT_RSP_ICACHE:
+        p_vci_tgt.cmdack  = false;
+        p_vci_tgt.rspval  = !r_tgt_icache_req.read() && r_tgt_icache_rsp.read();
+        p_vci_tgt.rsrcid  = r_tgt_srcid.read();
+        p_vci_tgt.rpktid  = r_tgt_pktid.read();
+        p_vci_tgt.rtrdid  = r_tgt_trdid.read();
+        p_vci_tgt.rdata   = 0;
+        p_vci_tgt.rerror  = 0;
+        p_vci_tgt.reop    = true;
+        break;
+
+    case TGT_RSP_DCACHE:
+        p_vci_tgt.cmdack  = false;
+        p_vci_tgt.rspval  = !r_tgt_dcache_req.read() && r_tgt_dcache_rsp.read();
+        p_vci_tgt.rsrcid  = r_tgt_srcid.read();
+        p_vci_tgt.rpktid  = r_tgt_pktid.read();
+        p_vci_tgt.rtrdid  = r_tgt_trdid.read();
+        p_vci_tgt.rdata   = 0;
+        p_vci_tgt.rerror  = 0;
+        p_vci_tgt.reop    = true;
+        break;
+
+    case TGT_REQ_BROADCAST:
+    case TGT_REQ_ICACHE:
+    case TGT_REQ_DCACHE:
+        p_vci_tgt.cmdack  = false;
+        p_vci_tgt.rspval  = false;
+        break;
+
+    } // end switch TGT_FSM
+
+#ifdef SOCLIB_MODULE_DEBUG 
+   std::cout << name() 
+      	     << "Moore R/W:" << std::hex
+      	     << " p_vci_ini_rw.cmdval: " << p_vci_ini_rw.cmdval
+      	     << " p_vci_ini_rw.address: " << p_vci_ini_rw.address
+      	     << " p_vci_ini_rw.wdata: " << p_vci_ini_rw.wdata
+      	     << " p_vci_ini_rw.cmd: " << p_vci_ini_rw.cmd
+      	     << " p_vci_ini_rw.trdid: " << p_vci_ini_rw.trdid
+      	     << " p_vci_ini_rw.eop: " << p_vci_ini_rw.eop
+      	     << std::endl;
+
+   std::cout << name() 
+      	     << "Moore Cleanup:" << std::hex
+      	     << " p_vci_ini_c.cmdval: " << p_vci_ini_c.cmdval
+      	     << " p_vci_ini_c.address: " << p_vci_ini_c.address
+      	     << " p_vci_ini_c.trdid: " << p_vci_ini_c.trdid
+      	     << " p_vci_ini_c.cmd: " << p_vci_ini_c.cmd
+      	     << " p_vci_ini_c.eop: " << p_vci_ini_c.eop
+      	     << std::endl;
+
+   std::cout << name() 
+      	     << "Moore TGT:" << std::hex
+      	     << " p_vci_tgt.cmdack: " << p_vci_tgt.cmdack
+      	     << " p_vci_tgt.rspval: " << p_vci_tgt.rspval
+      	     << " p_vci_tgt.rtrdid: " << p_vci_tgt.rtrdid
+      	     << " p_vci_tgt.rsrcid: " << p_vci_tgt.rsrcid
+      	     << " p_vci_tgt.reop: " << p_vci_ini_c.reop
+      	     << std::endl;
+
+#endif
+}
+
+}}
+
+// Local Variables:
+// tab-width: 4
+// c-basic-offset: 4
+// c-file-offsets:((innamespace . 0)(inline-open . 0))
+// indent-tabs-mode: nil
+// End:
+
+// vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4
+
+
+
+
+
+
+
+
+
Index: branches/v4/modules/vci_cc_vcache_wrapper2_ring/caba/metadata/vci_cc_vcache_wrapper2_ring.sd
===================================================================
--- branches/v4/modules/vci_cc_vcache_wrapper2_ring/caba/metadata/vci_cc_vcache_wrapper2_ring.sd	(revision 371)
+++ branches/v4/modules/vci_cc_vcache_wrapper2_ring/caba/metadata/vci_cc_vcache_wrapper2_ring.sd	(revision 371)
@@ -0,0 +1,66 @@
+
+# -*- python -*-
+
+__id__ = "$Id$"
+__version__ = "$Revision$"
+
+Module('caba:vci_cc_vcache_wrapper2_ring',
+	classname = 'soclib::caba::VciCcVCacheWrapper2Ring',
+	   tmpl_parameters = [
+	parameter.Module('vci_param', default = 'caba:vci_param'),
+	parameter.Module('iss_t'),
+	],
+	header_files = [
+	'../source/include/vci_cc_vcache_wrapper2_ring.h',
+	],
+	implementation_files = [
+	'../source/src/vci_cc_vcache_wrapper2_ring.cpp',
+	],
+	uses = [
+	Uses('caba:base_module'),
+	Uses('caba:write_buffer'),
+	Uses('caba:generic_tlb', addr_t = parameter.StringExt('sc_dt::sc_uint<%d> ', parameter.Reference('addr_size'))),
+	Uses('caba:generic_cache', addr_t = parameter.StringExt('sc_dt::sc_uint<%d> ', parameter.Reference('addr_size'))),
+	Uses('common:address_masking_table', data_t = parameter.StringExt('sc_dt::sc_uint<%d> ', parameter.Reference('addr_size'))),
+	Uses('common:iss2'),
+	Uses('common:mapping_table'),
+	],
+	ports = [
+	Port('caba:vci_initiator', 'p_vci_ini_rw'),
+	Port('caba:vci_initiator', 'p_vci_ini_c'),
+	Port('caba:vci_target', 'p_vci_tgt'),
+	Port('caba:bit_in','p_irq', parameter.Constant('n_irq')),
+	Port('caba:bit_in', 'p_resetn', auto = 'resetn'),
+	Port('caba:clock_in', 'p_clk', auto = 'clock'),
+	],
+	instance_parameters = [
+	parameter.Int('proc_id'),
+	parameter.Module('mt', 'common:mapping_table'),
+	parameter.IntTab('initiator_rw_index'),
+	parameter.IntTab('initiator_c_index'),
+	parameter.IntTab('target_index'),
+    	parameter.Int('itlb_ways'),
+    	parameter.Int('itlb_sets'),
+    	parameter.Int('dtlb_ways'),
+    	parameter.Int('dtlb_sets'),
+    	parameter.Int('icache_ways'),
+    	parameter.Int('icache_sets'),
+    	parameter.Int('icache_words'),
+    	parameter.Int('dcache_ways'),
+    	parameter.Int('dcache_sets'),
+    	parameter.Int('dcache_words'),
+    	parameter.Int('write_buf_size'),
+	],
+	   extensions = [
+	'dsx:get_ident='
+        'initiator_rw_index:p_vci_ini_rw:mt,'
+        'initiator_c_index:p_vci_ini_c:mt,'
+        'target_index:p_vci_tgt:mt',
+	'dsx:cpu=wrapper:iss_t',
+	'dsx:addressable=target_index',
+    'dsx:on_segment=mc:add_index:initiator_rw_index',
+	'dsx:mapping_type=processor:proc_id',
+   ],
+)
+
+
Index: branches/v4/modules/vci_cc_vcache_wrapper2_ring/caba/source/include/vci_cc_vcache_wrapper2_ring.h
===================================================================
--- branches/v4/modules/vci_cc_vcache_wrapper2_ring/caba/source/include/vci_cc_vcache_wrapper2_ring.h	(revision 371)
+++ branches/v4/modules/vci_cc_vcache_wrapper2_ring/caba/source/include/vci_cc_vcache_wrapper2_ring.h	(revision 371)
@@ -0,0 +1,563 @@
+/* -*- c++ -*-
+ * File : vci_cc_vcache_wrapper2_ring.h
+ * Copyright (c) UPMC, Lip6, SoC
+ * Authors : Alain GREINER, Yang GAO
+ *
+ * SOCLIB_LGPL_HEADER_BEGIN
+ * 
+ * This file is part of SoCLib, GNU LGPLv2.1.
+ * 
+ * SoCLib is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU Lesser General Public License as published
+ * by the Free Software Foundation; version 2.1 of the License.
+ * 
+ * SoCLib is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * Lesser General Public License for more details.
+ * 
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with SoCLib; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301 USA
+ * 
+ * SOCLIB_LGPL_HEADER_END
+ */
+ 
+#ifndef SOCLIB_CABA_VCI_CC_VCACHE_WRAPPER2_RING_H
+#define SOCLIB_CABA_VCI_CC_VCACHE_WRAPPER2_RING_H
+
+#include <inttypes.h>
+#include <systemc>
+#include "caba_base_module.h"
+#include "write_buffer.h"
+#include "generic_cache.h"
+#include "vci_initiator.h"
+#include "vci_target.h"
+#include "mapping_table.h"
+#include "generic_tlb.h"
+#include "static_assert.h"
+
+namespace soclib {
+namespace caba {
+
+using namespace sc_core;
+
+////////////////////////////////////////////
+template<typename vci_param, typename iss_t>
+class VciCcVCacheWrapper2Ring
+////////////////////////////////////////////
+    : public soclib::caba::BaseModule
+{
+    typedef uint32_t vaddr_t;
+    typedef uint32_t data_t;
+    typedef uint32_t tag_t;
+    typedef uint32_t type_t;
+    typedef typename iss_t::DataOperationType data_op_t;
+
+    typedef typename vci_param::addr_t  paddr_t;
+    typedef typename vci_param::be_t    vci_be_t;
+	typedef typename vci_param::srcid_t vci_srcid_t;
+	typedef typename vci_param::trdid_t vci_trdid_t;
+	typedef typename vci_param::pktid_t vci_pktid_t;
+	typedef typename vci_param::plen_t  vci_plen_t;
+
+    enum icache_fsm_state_e {  
+        ICACHE_IDLE,                // 00
+        ICACHE_BIS,                 // 01
+        ICACHE_TLB1_READ,           // 02
+        ICACHE_TLB1_WRITE,          // 03
+        ICACHE_TLB1_UPDT,           // 04
+        ICACHE_TLB2_READ,           // 05
+        ICACHE_TLB2_WRITE,          // 06
+        ICACHE_TLB2_UPDT,           // 07
+        ICACHE_SW_FLUSH,            // 08
+        ICACHE_CACHE_FLUSH,         // 09
+        ICACHE_TLB_INVAL,           // 0a
+        ICACHE_CACHE_INVAL,         // 0b
+        ICACHE_MISS_WAIT,           // 0c
+        ICACHE_UNC_WAIT,            // 0d
+        ICACHE_MISS_UPDT,           // 0e
+        ICACHE_ERROR,               // 0f
+        ICACHE_CC_INVAL,            // 10
+        ICACHE_TLB_CC_INVAL,        // 11
+        ICACHE_TLB_FLUSH,           // 12
+    };
+
+    enum dcache_fsm_state_e {  
+        DCACHE_IDLE,                // 00
+        DCACHE_BIS,                 // 01
+        DCACHE_DTLB1_READ_CACHE,    // 02
+        DCACHE_TLB1_LL_WAIT,        // 03
+        DCACHE_TLB1_SC_WAIT,        // 04
+        DCACHE_TLB1_READ,           // 05
+        DCACHE_TLB1_READ_UPDT,      // 06
+        DCACHE_TLB1_UPDT,           // 07
+        DCACHE_DTLB2_READ_CACHE,    // 08
+        DCACHE_TLB2_LL_WAIT,        // 09
+        DCACHE_TLB2_SC_WAIT,        // 0a
+        DCACHE_TLB2_READ,           // 0b
+        DCACHE_TLB2_READ_UPDT,      // 0c
+        DCACHE_TLB2_UPDT,           // 0d
+        DCACHE_CTXT_SWITCH,         // 0e
+        DCACHE_ICACHE_FLUSH,        // 0f
+        DCACHE_DCACHE_FLUSH,        // 10
+        DCACHE_ITLB_INVAL,          // 11
+        DCACHE_DTLB_INVAL,          // 12
+        DCACHE_ICACHE_INVAL,        // 13
+        DCACHE_DCACHE_INVAL,        // 14
+        DCACHE_DCACHE_SYNC,         // 15
+        DCACHE_LL_DIRTY_WAIT,       // 16
+        DCACHE_SC_DIRTY_WAIT,       // 17
+        DCACHE_WRITE_UPDT,          // 18
+        DCACHE_WRITE_DIRTY,         // 19
+        DCACHE_WRITE_REQ,           // 1a
+        DCACHE_MISS_WAIT,           // 1b
+        DCACHE_MISS_UPDT,           // 1c
+        DCACHE_UNC_WAIT,            // 1d
+        DCACHE_ERROR,               // 1e
+        DCACHE_ITLB_READ,           // 1f
+        DCACHE_ITLB_UPDT,           // 20
+        DCACHE_ITLB_LL_WAIT,        // 21
+        DCACHE_ITLB_SC_WAIT,        // 22
+        DCACHE_CC_CHECK,            // 23
+        DCACHE_CC_INVAL,            // 24
+        DCACHE_CC_UPDT,             // 25
+        DCACHE_CC_NOP,              // 26
+        DCACHE_TLB_CC_INVAL,        // 27
+        DCACHE_ITLB_CLEANUP,        // 28
+    };
+
+    enum cmd_fsm_state_e {      
+        CMD_IDLE,                   // 00
+        CMD_ITLB_READ,              // 01
+        CMD_ITLB_ACC_LL,            // 02
+        CMD_ITLB_ACC_SC,            // 03
+        CMD_INS_MISS,               // 04
+        CMD_INS_UNC,                // 05
+        CMD_DTLB_READ,              // 06
+        CMD_DTLB_ACC_LL,            // 07
+        CMD_DTLB_ACC_SC,            // 08
+        CMD_DTLB_DIRTY_LL,          // 09
+        CMD_DTLB_DIRTY_SC,          // 0a
+        CMD_DATA_UNC,               // 0b
+        CMD_DATA_MISS,              // 0c
+        CMD_DATA_WRITE,             // 0d
+    };
+
+    enum rsp_fsm_state_e {       
+        RSP_IDLE,                   // 00
+        RSP_ITLB_READ,              // 01
+        RSP_ITLB_ACC_LL,            // 02
+        RSP_ITLB_ACC_SC,            // 03
+        RSP_INS_MISS,               // 04
+        RSP_INS_UNC,                // 05
+        RSP_DTLB_READ,              // 06
+        RSP_DTLB_ACC_LL,            // 07
+        RSP_DTLB_ACC_SC,            // 08
+        RSP_DTLB_DIRTY_LL,          // 09
+        RSP_DTLB_DIRTY_SC,          // 0a
+        RSP_DATA_MISS,              // 0b
+        RSP_DATA_UNC,               // 0c
+        RSP_DATA_WRITE,             // 0d
+    };
+
+    enum cmd_cleanup_fsm_state_e {      
+        CMD_CLEANUP_INS_IDLE,       // 00
+        CMD_CLEANUP_DATA_IDLE,      // 00
+        CMD_CLEANUP_INS,            // 01
+        CMD_CLEANUP_DATA,           // 02
+    };
+
+    enum rsp_cleanup_fsm_state_e {       
+        RSP_CLEANUP_INS_IDLE,       // 00
+        RSP_CLEANUP_DATA_IDLE,      // 00
+        RSP_CLEANUP_INS,            // 01
+        RSP_CLEANUP_DATA,           // 02
+    };
+
+    enum tgt_fsm_state_e {  
+        TGT_IDLE,                   // 00
+        TGT_UPDT_WORD,              // 01
+        TGT_UPDT_DATA,              // 02
+        TGT_REQ_BROADCAST,          // 03
+        TGT_REQ_DCACHE,             // 04
+        TGT_RSP_BROADCAST,          // 05
+        TGT_RSP_DCACHE,             // 06
+    };
+
+    enum inval_itlb_fsm_state_e {
+        INVAL_ITLB_IDLE,            // 00
+        INVAL_ITLB_CHECK,           // 01
+        INVAL_ITLB_INVAL,           // 02
+        INVAL_ITLB_CLEAR,           // 03
+    };
+
+    enum inval_dtlb_fsm_state_e {
+        INVAL_DTLB_IDLE,            // 00
+        INVAL_DTLB_CHECK,           // 01
+        INVAL_DTLB_INVAL,           // 02
+        INVAL_DTLB_CLEAR,           // 03
+    };
+
+    // TLB Mode ITLB / DTLB / ICACHE / DCACHE
+    enum {          
+        ALL_DEACTIVE = 0x0000,   // TLBs disactive caches disactive
+        INS_TLB_MASK    = 0x8,
+        DATA_TLB_MASK   = 0x4,
+        INS_CACHE_MASK  = 0x2,
+        DATA_CACHE_MASK = 0x1,
+    };
+
+    // Error Type
+    enum mmu_error_type_e {
+        MMU_NONE                      = 0x0000, // None
+        MMU_WRITE_PT1_UNMAPPED 	      = 0x0001, // Write access of Page fault on Page Table 1          (non fatal error)
+        MMU_WRITE_PT2_UNMAPPED 	      = 0x0002, // Write access of Page fault on Page Table 2          (non fatal error)
+        MMU_WRITE_PRIVILEGE_VIOLATION = 0x0004, // Write access of Protected access in user mode       (user error)
+        MMU_WRITE_ACCES_VIOLATION 	  = 0x0008, // Write access of write access to a non writable page (user error)
+        MMU_WRITE_UNDEFINED_XTN 	  = 0x0020, // Write access of undefined external access address   (user error)
+        MMU_WRITE_PT1_ILLEGAL_ACCESS  = 0x0040, // Write access of Bus Error accessing Table 1         (kernel error)
+        MMU_WRITE_PT2_ILLEGAL_ACCESS  = 0x0080, // Write access of Bus Error accessing Table 2         (kernel error)
+        MMU_WRITE_DATA_ILLEGAL_ACCESS = 0x0100, // Write access of Bus Error in cache access           (kernel error)
+        MMU_READ_PT1_UNMAPPED 	      = 0x1001, // Read access of Page fault on Page Table 1  	       (non fatal error)
+        MMU_READ_PT2_UNMAPPED 	      = 0x1002, // Read access of Page fault on Page Table 2  	       (non fatal error)
+        MMU_READ_PRIVILEGE_VIOLATION  = 0x1004, // Read access of Protected access in user mode 	   (user error)
+        MMU_READ_EXEC_VIOLATION 	  = 0x1010, // Exec access to a non exec page                      (user error)
+        MMU_READ_UNDEFINED_XTN 	      = 0x1020, // Read access of Undefined external access address    (user error)
+        MMU_READ_PT1_ILLEGAL_ACCESS   = 0x1040, // Read access of Bus Error in Table1 access           (kernel error)
+        MMU_READ_PT2_ILLEGAL_ACCESS   = 0x1080, // Read access of Bus Error in Table2 access 	       (kernel error)
+        MMU_READ_DATA_ILLEGAL_ACCESS  = 0x1100, // Read access of Bus Error in cache access 	       (kernel error)
+    };
+
+public:
+    sc_in<bool>                             p_clk;
+    sc_in<bool>                             p_resetn;
+    sc_in<bool>                             p_irq[iss_t::n_irq];
+    soclib::caba::VciInitiator<vci_param>   p_vci_ini_rw;
+    soclib::caba::VciInitiator<vci_param>   p_vci_ini_c;
+    soclib::caba::VciTarget<vci_param>      p_vci_tgt;
+
+private:
+    // STRUCTURAL PARAMETERS
+    soclib::common::AddressDecodingTable<uint32_t, bool>    m_cacheability_table;
+    const soclib::common::Segment                           m_segment;
+    iss_t                                                   m_iss;   
+    const vci_srcid_t                                       m_srcid_rw;
+    const vci_srcid_t                                       m_srcid_c;
+
+    const size_t  m_itlb_ways;
+    const size_t  m_itlb_sets;
+
+    const size_t  m_dtlb_ways;
+    const size_t  m_dtlb_sets;
+
+    const size_t  m_icache_ways;
+    const size_t  m_icache_sets;
+    const size_t  m_icache_yzmask;
+    const size_t  m_icache_words;
+
+    const size_t  m_dcache_ways;
+    const size_t  m_dcache_sets;
+    const size_t  m_dcache_yzmask;
+    const size_t  m_dcache_words;
+
+    const size_t  m_write_buf_size;  
+    const size_t  m_paddr_nbits;  
+
+    // instruction and data vcache tlb instances 
+    soclib::caba::GenericCcTlb<paddr_t>    icache_tlb;
+    soclib::caba::GenericCcTlb<paddr_t>    dcache_tlb;
+
+    sc_signal<vaddr_t>      r_mmu_ptpr;             // page table pointer register
+    sc_signal<int>          r_mmu_mode;             // tlb mode register
+
+    // DCACHE FSM REGISTERS
+    sc_signal<int>          r_dcache_fsm;               // state register
+    sc_signal<paddr_t>      r_dcache_paddr_save;        // physical address
+    sc_signal<data_t>       r_dcache_wdata_save;        // write data
+    sc_signal<data_t>       r_dcache_rdata_save;        // read data
+    sc_signal<type_t>       r_dcache_type_save;         // access type
+    sc_signal<vci_be_t>     r_dcache_be_save;           // byte enable
+    sc_signal<bool>         r_dcache_cached_save;       // used by the write buffer
+    sc_signal<paddr_t>      r_dcache_tlb_paddr;         // physical address of tlb miss
+    sc_signal<bool>         r_dcache_dirty_save;        // used for TLB dirty bit update
+    sc_signal<size_t>       r_dcache_tlb_set_save;      // used for TLB dirty bit update
+    sc_signal<size_t>       r_dcache_tlb_way_save;      // used for TLB dirty bit update
+    sc_signal<vaddr_t>      r_dcache_id1_save;          // used by the PT1 bypass
+    sc_signal<paddr_t>      r_dcache_ptba_save;         // used by the PT1 bypass
+    sc_signal<bool>         r_dcache_ptba_ok;           // used by the PT1 bypass
+    sc_signal<data_t>       r_dcache_pte_update;        // used for page table update
+    sc_signal<data_t>       r_dcache_ppn_update;        // used for physical page number update 
+    sc_signal<tag_t>        r_dcache_ppn_save;          // used for speculative cache access
+    sc_signal<tag_t>        r_dcache_vpn_save;          // used for speculative cache access
+    sc_signal<bool>         r_dtlb_translation_valid;   // used for speculative address
+    sc_signal<bool>         r_dcache_buf_unc_valid;     // used for uncached read
+    sc_signal<bool>         r_dcache_hit_p_save;        // used to save hit_p in case BIS
+
+    sc_signal<data_t>       r_dcache_error_type;        // software visible register
+    sc_signal<vaddr_t>      r_dcache_bad_vaddr;         // software visible register 
+
+    sc_signal<bool>         r_dcache_miss_req;          // used for cached read miss
+    sc_signal<bool>         r_dcache_unc_req;           // used for uncached read miss
+    sc_signal<bool>         r_dcache_write_req;         // used for write 
+    sc_signal<bool>         r_dcache_tlb_read_req;      // used for tlb ptba or pte read 
+    sc_signal<bool>         r_dcache_llsc_reserved;     // used for check address reserved
+    sc_signal<paddr_t>      r_dcache_llsc_addr_save;    // used for save llsc address
+ 
+    sc_signal<bool>         r_dcache_tlb_ll_acc_req;    // used for tlb access bit update
+    sc_signal<bool>         r_dcache_tlb_sc_acc_req;    // used for tlb access bit update
+    sc_signal<bool>         r_dcache_tlb_ll_dirty_req;  // used for tlb dirty bit update 
+    sc_signal<bool>         r_dcache_tlb_sc_dirty_req;  // used for tlb dirty bit update 
+    sc_signal<bool>         r_dcache_tlb_ptba_read;     // used for tlb ptba read when write dirty bit 
+    sc_signal<bool>         r_dcache_xtn_req;           // used for xtn write for ICACHE
+
+    bool                    *r_dcache_in_itlb;          // indicates some words of dcache line in ins TLB 
+    bool                    *r_dcache_in_dtlb;          // indicates some words of dcache line in data TLB 
+
+    // coherence registers
+    sc_signal<int>          r_dcache_fsm_save;          // state save register
+    sc_signal<size_t>       r_dcache_way;
+    sc_signal<size_t>       r_dcache_set;
+    sc_signal<bool>         r_dcache_cleanup_req;       // data cleanup request
+    sc_signal<data_t>       r_dcache_cleanup_line;      // data cleanup NLINE
+    sc_signal<bool>         r_dcache_inval_rsp;         // data cache invalidate
+
+    // ICACHE FSM REGISTERS
+    sc_signal<int>          r_icache_fsm;               // state register
+    sc_signal<paddr_t>      r_icache_paddr_save;        // physical address
+    sc_signal<vaddr_t>      r_icache_id1_save;          // used by the PT1 bypass
+    sc_signal<paddr_t>      r_icache_ptba_save;         // used by the PT1 bypass
+    sc_signal<bool>         r_icache_ptba_ok;           // used by the PT1 bypass
+    sc_signal<data_t>       r_icache_pte_update;        // used for page table update
+    sc_signal<tag_t>        r_icache_ppn_save;          // used for speculative cache access
+    sc_signal<tag_t>        r_icache_vpn_save;          // used for speculative cache access
+    sc_signal<bool>         r_itlb_translation_valid;   // used for speculative physical address
+    sc_signal<bool>         r_icache_buf_unc_valid;     // used for uncached read
+
+    sc_signal<data_t>       r_icache_error_type;        // software visible registers
+    sc_signal<vaddr_t>      r_icache_bad_vaddr;         // software visible registers
+
+    sc_signal<bool>         r_icache_miss_req;          // used for cached read miss
+    sc_signal<bool>         r_icache_unc_req;           // used for uncached read miss
+    sc_signal<bool>         r_dcache_itlb_read_req;     // used for tlb ptba or pte read 
+    sc_signal<bool>         r_dcache_itlb_ll_acc_req;   // used for tlb access bit update
+    sc_signal<bool>         r_dcache_itlb_sc_acc_req;   // used for tlb access bit update
+
+    sc_signal<bool>	        r_itlb_read_dcache_req;     // used for instruction tlb miss, request in data cache
+    sc_signal<bool>	        r_itlb_acc_dcache_req;      // used for itlb update entry type bits via dcache
+    sc_signal<bool>	        r_dcache_rsp_itlb_error;    // used for data cache rsp error when itlb miss
+    sc_signal<data_t>	    r_dcache_rsp_itlb_miss;	    // used for dcache rsp data when itlb miss
+    sc_signal<data_t>	    r_dcache_rsp_itlb_ppn;	    // used for dcache rsp ppn when itlb miss
+
+    // coherence registers
+    sc_signal<int>          r_icache_fsm_save;          // state save register
+    sc_signal<size_t>       r_icache_way;
+    sc_signal<size_t>       r_icache_set;
+    sc_signal<bool>         r_icache_cleanup_req;       // ins cleanup request
+    sc_signal<data_t>       r_icache_cleanup_line;      // ins cleanup NLINE
+    sc_signal<bool>         r_icache_inval_rsp;         // ins cache invalidate
+
+    // VCI_CMD FSM REGISTERS
+    sc_signal<int>          r_vci_cmd_fsm;
+    sc_signal<size_t>       r_vci_cmd_min;       
+    sc_signal<size_t>       r_vci_cmd_max;       
+    sc_signal<size_t>       r_vci_cmd_cpt;     
+
+    // VCI_RSP FSM REGISTERS
+    sc_signal<int>          r_vci_rsp_fsm;
+    sc_signal<size_t>       r_vci_rsp_cpt;
+    sc_signal<bool>         r_vci_rsp_ins_error;
+    sc_signal<bool>         r_vci_rsp_data_error;
+
+    data_t                  *r_icache_miss_buf;    
+    data_t                  *r_dcache_miss_buf;  
+
+    // VCI CLEANUP FSM REGISTERS
+    sc_signal<int>          r_vci_cmd_cleanup_fsm;
+    sc_signal<int>          r_vci_rsp_cleanup_fsm;
+
+    // VCI_TGT FSM REGISTERS
+    data_t                  *r_tgt_buf;
+    bool                    *r_tgt_val;
+
+    sc_signal<int>          r_vci_tgt_fsm;
+    sc_signal<paddr_t>      r_tgt_addr;
+    sc_signal<size_t>       r_tgt_word;
+    sc_signal<bool>         r_tgt_update;
+    sc_signal<vci_srcid_t>  r_tgt_srcid;
+    sc_signal<vci_pktid_t>  r_tgt_pktid;
+    sc_signal<vci_trdid_t>  r_tgt_trdid;
+    sc_signal<vci_plen_t>   r_tgt_plen;
+    sc_signal<bool>         r_tgt_req;
+    sc_signal<bool>         r_tgt_icache_req;
+    sc_signal<bool>         r_tgt_dcache_req;
+    sc_signal<bool>         r_tgt_icache_rsp;
+    sc_signal<bool>         r_tgt_dcache_rsp;
+
+    // INVAL CHECK FSM
+    sc_signal<int>          r_inval_itlb_fsm;          
+    sc_signal<bool>         r_dcache_itlb_inval_req;
+    sc_signal<paddr_t>      r_dcache_itlb_inval_line;
+    sc_signal<bool>         r_itlb_cc_check_end;
+    sc_signal<size_t>       r_ccinval_itlb_way; 
+    sc_signal<size_t>       r_ccinval_itlb_set; 
+    sc_signal<bool>         r_icache_inval_tlb_rsp;
+    sc_signal<paddr_t>      r_icache_tlb_nline;
+
+    sc_signal<int>          r_inval_dtlb_fsm;          
+    sc_signal<bool>         r_dcache_dtlb_inval_req;
+    sc_signal<paddr_t>      r_dcache_dtlb_inval_line;
+    sc_signal<bool>         r_dtlb_cc_check_end;
+    sc_signal<size_t>       r_ccinval_dtlb_way; 
+    sc_signal<size_t>       r_ccinval_dtlb_set; 
+    sc_signal<bool>         r_dcache_inval_tlb_rsp;
+    sc_signal<paddr_t>      r_dcache_tlb_nline;
+
+    sc_signal<bool>         r_dcache_itlb_cleanup_req;
+    sc_signal<paddr_t>      r_dcache_itlb_cleanup_line;
+
+    sc_signal<bool>         r_dcache_dtlb_cleanup_req;
+    sc_signal<paddr_t>      r_dcache_dtlb_cleanup_line;
+
+    sc_signal<bool>         r_itlb_inval_req;
+    sc_signal<bool>         r_dcache_cc_check;
+
+    WriteBuffer<paddr_t>     r_wbuf;
+    GenericCache<paddr_t>    r_icache;
+    GenericCache<paddr_t>    r_dcache;
+
+    // Activity counters
+    uint32_t m_cpt_dcache_data_read;        // DCACHE DATA READ
+    uint32_t m_cpt_dcache_data_write;       // DCACHE DATA WRITE
+    uint32_t m_cpt_dcache_dir_read;         // DCACHE DIR READ
+    uint32_t m_cpt_dcache_dir_write;        // DCACHE DIR WRITE
+
+    uint32_t m_cpt_icache_data_read;        // ICACHE DATA READ
+    uint32_t m_cpt_icache_data_write;       // ICACHE DATA WRITE
+    uint32_t m_cpt_icache_dir_read;         // ICACHE DIR READ
+    uint32_t m_cpt_icache_dir_write;        // ICACHE DIR WRITE
+
+    uint32_t m_cpt_frz_cycles;	            // number of cycles where the cpu is frozen
+    uint32_t m_cpt_total_cycles;	        // total number of cycles 
+
+    // Cache activity counters
+    uint32_t m_cpt_read;                    // total number of read data
+    uint32_t m_cpt_write;                   // total number of write data
+    uint32_t m_cpt_data_miss;               // number of read miss
+    uint32_t m_cpt_ins_miss;                // number of instruction miss
+    uint32_t m_cpt_unc_read;                // number of read uncached
+    uint32_t m_cpt_write_cached;            // number of cached write
+    uint32_t m_cpt_ins_read;                // number of instruction read
+
+    uint32_t m_cost_write_frz;              // number of frozen cycles related to write buffer         
+    uint32_t m_cost_data_miss_frz;          // number of frozen cycles related to data miss
+    uint32_t m_cost_unc_read_frz;           // number of frozen cycles related to uncached read
+    uint32_t m_cost_ins_miss_frz;           // number of frozen cycles related to ins miss
+
+    uint32_t m_cpt_imiss_transaction;       // number of VCI instruction miss transactions
+    uint32_t m_cpt_dmiss_transaction;       // number of VCI data miss transactions
+    uint32_t m_cpt_unc_transaction;         // number of VCI uncached read transactions
+    uint32_t m_cpt_write_transaction;       // number of VCI write transactions
+
+    uint32_t m_cost_imiss_transaction;      // cumulated duration for VCI IMISS transactions
+    uint32_t m_cost_dmiss_transaction;      // cumulated duration for VCI DMISS transactions
+    uint32_t m_cost_unc_transaction;        // cumulated duration for VCI UNC transactions
+    uint32_t m_cost_write_transaction;      // cumulated duration for VCI WRITE transactions
+    uint32_t m_length_write_transaction;    // cumulated length for VCI WRITE transactions
+
+    // TLB activity counters
+    uint32_t m_cpt_ins_tlb_read;            // number of instruction tlb read
+    uint32_t m_cpt_ins_tlb_miss;            // number of instruction tlb miss
+    uint32_t m_cpt_ins_tlb_write_et;        // number of instruction tlb write ET
+
+    uint32_t m_cpt_data_tlb_read;           // number of data tlb read
+    uint32_t m_cpt_data_tlb_miss;           // number of data tlb miss
+    uint32_t m_cpt_data_tlb_write_et;       // number of data tlb write ET
+    uint32_t m_cpt_data_tlb_write_dirty;    // number of data tlb write dirty
+    
+    uint32_t m_cost_ins_tlb_miss_frz;       // number of frozen cycles related to instruction tlb miss
+    uint32_t m_cost_data_tlb_miss_frz;      // number of frozen cycles related to data tlb miss
+
+    uint32_t m_cost_ins_waste_wait_frz;     // number of frozen cycles related to ins wait coherence operate 
+    uint32_t m_cost_ins_tlb_sw_frz;         // number of frozen cycles related to ins context switch
+    uint32_t m_cost_ins_cache_flush_frz;    // number of frozen cycles related to ins cache flush 
+
+    uint32_t m_cpt_ins_tlb_cleanup;         // number of ins tlb cleanup 
+    uint32_t m_cost_data_waste_wait_frz;    // number of frozen cycles related to data wait coherence operate
+    uint32_t m_cost_data_tlb_sw_frz;        // number of frozen cycles related to data context switch
+    uint32_t m_cost_data_cache_flush_frz;   // number of frozen cycles related to data cache flush
+
+    uint32_t m_cpt_itlbmiss_transaction;    // number of itlb miss transactions
+    uint32_t m_cpt_itlb_write_transaction;  // number of itlb write ET transactions
+    uint32_t m_cpt_dtlbmiss_transaction;    // number of dtlb miss transactions
+    uint32_t m_cpt_dtlb_write_transaction;  // number of dtlb write ET and dirty transactions
+
+    uint32_t m_cost_itlbmiss_transaction;   // cumulated duration for VCI instruction TLB miss transactions
+    uint32_t m_cost_itlb_write_transaction; // cumulated duration for VCI instruction TLB write ET transactions
+    uint32_t m_cost_dtlbmiss_transaction;   // cumulated duration for VCI data TLB miss transactions
+    uint32_t m_cost_dtlb_write_transaction; // cumulated duration for VCI data TLB write transactions
+
+    uint32_t m_cpt_cc_update;               // number of coherence update packets 
+    uint32_t m_cpt_cc_inval;                // number of coherence inval packets
+    uint32_t m_cpt_cc_broadcast;            // number of coherence broadcast packets
+
+    uint32_t m_cost_ins_tlb_inval_frz;      // number of frozen cycles related to checking ins tlb invalidate
+    uint32_t m_cpt_ins_tlb_inval;           // number of ins tlb invalidate
+
+    uint32_t m_cost_data_tlb_inval_frz;     // number of frozen cycles related to checking data tlb invalidate    
+    uint32_t m_cpt_data_tlb_inval;          // number of data tlb invalidate
+
+protected:
+    SC_HAS_PROCESS(VciCcVCacheWrapper2Ring);
+
+public:
+    VciCcVCacheWrapper2Ring(
+        sc_module_name insname,
+        int proc_id,
+        const soclib::common::MappingTable &mtp,
+        const soclib::common::MappingTable &mtc,
+        const soclib::common::IntTab &initiator_index_rw,
+        const soclib::common::IntTab &initiator_index_c,
+        const soclib::common::IntTab &target_index,
+        size_t itlb_ways,
+        size_t itlb_sets,
+        size_t dtlb_ways,
+        size_t dtlb_sets,
+        size_t icache_ways,
+        size_t icache_sets,
+        size_t icache_words,
+        size_t dcache_ways,
+        size_t dcache_sets,
+        size_t dcache_words,
+        size_t write_buf_size );
+
+    ~VciCcVCacheWrapper2Ring();
+
+    void print_cpi();
+    void print_stats();
+
+private:
+    void transition();
+    void genMoore();
+
+    soclib_static_assert((int)iss_t::SC_ATOMIC == (int)vci_param::STORE_COND_ATOMIC);
+    soclib_static_assert((int)iss_t::SC_NOT_ATOMIC == (int)vci_param::STORE_COND_NOT_ATOMIC);
+};
+
+}}
+
+#endif /* SOCLIB_CABA_VCI_CC_VCACHE_WRAPPER2_RING_H */
+
+// Local Variables:
+// tab-width: 4
+// c-basic-offset: 4
+// c-file-offsets:((innamespace . 0)(inline-open . 0))
+// indent-tabs-mode: nil
+// End:
+
+// vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4
+
+
+
+
Index: branches/v4/modules/vci_cc_vcache_wrapper2_ring/caba/source/src/vci_cc_vcache_wrapper2_ring.cpp
===================================================================
--- branches/v4/modules/vci_cc_vcache_wrapper2_ring/caba/source/src/vci_cc_vcache_wrapper2_ring.cpp	(revision 371)
+++ branches/v4/modules/vci_cc_vcache_wrapper2_ring/caba/source/src/vci_cc_vcache_wrapper2_ring.cpp	(revision 371)
@@ -0,0 +1,5545 @@
+/* -*- c++ -*-
+ * File : vci_cc_vcache_wrapper2_ring.cpp
+ * Copyright (c) UPMC, Lip6, SoC
+ * Authors : Alain GREINER, Yang GAO
+ *
+ * SOCLIB_LGPL_HEADER_BEGIN
+ * 
+ * This file is part of SoCLib, GNU LGPLv2.1.
+ * 
+ * SoCLib is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU Lesser General Public License as published
+ * by the Free Software Foundation; version 2.1 of the License.
+ * 
+ * SoCLib is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * Lesser General Public License for more details.
+ * 
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with SoCLib; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301 USA
+ * 
+ * SOCLIB_LGPL_HEADER_END
+ */
+
+#include <cassert>
+#include "arithmetics.h"
+#include "../include/vci_cc_vcache_wrapper2_ring.h"
+
+namespace soclib { 
+namespace caba {
+
+#ifdef SOCLIB_MODULE_DEBUG
+namespace {
+const char *icache_fsm_state_str[] = {
+        "ICACHE_IDLE",
+        "ICACHE_BIS",       
+        "ICACHE_TLB1_READ",  
+        "ICACHE_TLB1_WRITE",  
+        "ICACHE_TLB1_UPDT",  
+        "ICACHE_TLB2_READ",  
+        "ICACHE_TLB2_WRITE",  
+        "ICACHE_TLB2_UPDT",  
+        "ICACHE_SW_FLUSH", 
+        "ICACHE_CACHE_FLUSH", 
+        "ICACHE_TLB_INVAL",  
+        "ICACHE_CACHE_INVAL",
+        "ICACHE_MISS_WAIT",
+        "ICACHE_UNC_WAIT",  
+        "ICACHE_MISS_UPDT",  
+        "ICACHE_ERROR", 	
+        "ICACHE_CC_INVAL", 
+        "ICACHE_TLB_CC_INVAL",        
+        "ICACHE_TLB_FLUSH",
+    };
+const char *dcache_fsm_state_str[] = {
+        "DCACHE_IDLE",       
+        "DCACHE_BIS",   
+        "DCACHE_DTLB1_READ_CACHE",
+	"DCACHE_TLB1_LL_WAIT",
+	"DCACHE_TLB1_SC_WAIT",    
+        "DCACHE_TLB1_READ",
+        "DCACHE_TLB1_READ_UPDT",  
+        "DCACHE_TLB1_UPDT", 
+        "DCACHE_DTLB2_READ_CACHE", 
+	"DCACHE_TLB2_LL_WAIT",
+	"DCACHE_TLB2_SC_WAIT",   
+        "DCACHE_TLB2_READ",
+        "DCACHE_TLB2_READ_UPDT",  
+        "DCACHE_TLB2_UPDT",   
+        "DCACHE_CTXT_SWITCH",   
+        "DCACHE_ICACHE_FLUSH", 
+        "DCACHE_DCACHE_FLUSH", 
+        "DCACHE_ITLB_INVAL",
+        "DCACHE_DTLB_INVAL",
+        "DCACHE_ICACHE_INVAL",
+        "DCACHE_DCACHE_INVAL",
+	"DCACHE_DCACHE_SYNC",
+	"DCACHE_LL_DIRTY_WAIT",
+	"DCACHE_SC_DIRTY_WAIT",
+        "DCACHE_WRITE_UPDT", 
+        "DCACHE_WRITE_DIRTY",
+        "DCACHE_WRITE_REQ",  
+        "DCACHE_MISS_WAIT",  
+        "DCACHE_MISS_UPDT",  
+        "DCACHE_UNC_WAIT",   
+        "DCACHE_ERROR", 
+        "DCACHE_ITLB_READ",
+        "DCACHE_ITLB_UPDT",
+        "DCACHE_ITLB_LL_WAIT",        
+        "DCACHE_ITLB_SC_WAIT",        
+        "DCACHE_CC_CHECK",
+        "DCACHE_CC_INVAL",
+        "DCACHE_CC_UPDT",
+        "DCACHE_CC_NOP",
+        "DCACHE_TLB_CC_INVAL",
+        "DCACHE_ITLB_CLEANUP",
+    };
+const char *cmd_fsm_state_str[] = {
+        "CMD_IDLE",           
+        "CMD_ITLB_READ", 
+        "CMD_ITLB_ACC_LL",                
+        "CMD_ITLB_ACC_SC",                
+        "CMD_INS_MISS",     
+        "CMD_INS_UNC",     
+        "CMD_DTLB_READ",   
+        "CMD_DTLB_ACC_LL",            
+        "CMD_DTLB_ACC_SC",            
+        "CMD_DTLB_DIRTY_LL",          
+        "CMD_DTLB_DIRTY_SC",          
+        "CMD_DATA_UNC",     
+        "CMD_DATA_MISS",    
+        "CMD_DATA_WRITE", 
+    };
+const char *rsp_fsm_state_str[] = {
+        "RSP_IDLE",                  
+        "RSP_ITLB_READ",             
+        "RSP_ITLB_ACC_LL",                
+        "RSP_ITLB_ACC_SC",                
+        "RSP_INS_MISS",   
+        "RSP_INS_UNC",           
+        "RSP_DTLB_READ",            
+        "RSP_DTLB_ACC_LL",            
+        "RSP_DTLB_ACC_SC",            
+        "RSP_DTLB_DIRTY_LL",          
+        "RSP_DTLB_DIRTY_SC",          
+        "RSP_DATA_MISS",             
+        "RSP_DATA_UNC",              
+        "RSP_DATA_WRITE",  
+    };
+const char *cmd_cleanup_fsm_state_str[] = {
+        "CMD_CLEANUP_INS_IDLE",           
+        "CMD_CLEANUP_DATA_IDLE",           
+        "CMD_CLEANUP_INS",    
+        "CMD_CLEANUP_DATA",      
+    };
+const char *rsp_cleanup_fsm_state_str[] = {
+        "RSP_CLEANUP_INS_IDLE",                  
+        "RSP_CLEANUP_DATA_IDLE",                  
+        "RSP_CLEANUP_INS",    
+        "RSP_CLEANUP_DATA",        
+    };
+const char *tgt_fsm_state_str[] = {
+        "TGT_IDLE",
+        "TGT_UPDT_WORD",
+        "TGT_UPDT_DATA",
+        "TGT_REQ_BROADCAST",
+        "TGT_REQ_DCACHE",
+        "TGT_RSP_BROADCAST",
+        "TGT_RSP_DCACHE",
+    };	
+const char *inval_itlb_fsm_state_str[] = {
+        "INVAL_ITLB_IDLE",        
+        "INVAL_ITLB_CHECK"  , 
+        "INVAL_ITLB_INVAL",      
+        "INVAL_ITLB_CLEAR",           
+    };
+const char *inval_dtlb_fsm_state_str[] = {
+        "INVAL_DTLB_IDLE",        
+        "INVAL_DTLB_CHECK", 
+        "INVAL_DTLB_INVAL",    
+        "INVAL_DTLB_CLEAR",         
+    };
+}
+#endif
+
+#define tmpl(...)  template<typename vci_param, typename iss_t> __VA_ARGS__ VciCcVCacheWrapper2Ring<vci_param, iss_t>
+
+using soclib::common::uint32_log2;
+
+/***********************************************/
+tmpl(/**/)::VciCcVCacheWrapper2Ring(
+    sc_module_name name,
+    int proc_id,
+    const soclib::common::MappingTable &mtp,
+    const soclib::common::MappingTable &mtc,
+    const soclib::common::IntTab &initiator_index_rw,
+    const soclib::common::IntTab &initiator_index_c,
+    const soclib::common::IntTab &target_index,
+    size_t itlb_ways,
+    size_t itlb_sets,
+    size_t dtlb_ways,
+    size_t dtlb_sets,
+    size_t icache_ways,
+    size_t icache_sets,
+    size_t icache_words,
+    size_t dcache_ways,
+    size_t dcache_sets,
+    size_t dcache_words,    
+    size_t write_buf_size )
+/***********************************************/
+    : soclib::caba::BaseModule(name),
+
+      p_clk("clk"),
+      p_resetn("resetn"),
+      p_vci_ini_rw("vci_ini_rw"),
+      p_vci_ini_c("vci_ini_c"),
+      p_vci_tgt("vci_tgt"),
+
+      m_cacheability_table(mtp.getCacheabilityTable()),
+      m_segment(mtc.getSegment(target_index)),
+      m_iss(this->name(), proc_id),
+      m_srcid_rw(mtp.indexForId(initiator_index_rw)),
+      m_srcid_c(mtc.indexForId(initiator_index_c)),
+
+      m_itlb_ways(itlb_ways),
+      m_itlb_sets(itlb_sets),
+
+      m_dtlb_ways(dtlb_ways),
+      m_dtlb_sets(dtlb_sets),
+
+      m_icache_ways(icache_ways),
+      m_icache_sets(icache_sets),
+      m_icache_yzmask((~0)<<(uint32_log2(icache_words) + 2)),
+      m_icache_words(icache_words),
+
+      m_dcache_ways(dcache_ways),
+      m_dcache_sets(dcache_sets),
+      m_dcache_yzmask((~0)<<(uint32_log2(dcache_words) + 2)),
+      m_dcache_words(dcache_words),
+
+      m_write_buf_size(write_buf_size),	
+      m_paddr_nbits(vci_param::N),
+
+      icache_tlb(itlb_ways,itlb_sets,vci_param::N),
+      dcache_tlb(dtlb_ways,dtlb_sets,vci_param::N),
+
+      r_dcache_fsm("r_dcache_fsm"),
+      r_dcache_paddr_save("r_dcache_paddr_save"),
+      r_dcache_wdata_save("r_dcache_wdata_save"),
+      r_dcache_rdata_save("r_dcache_rdata_save"),
+      r_dcache_type_save("r_dcache_type_save"),
+      r_dcache_be_save("r_dcache_be_save"),
+      r_dcache_cached_save("r_dcache_cached_save"),
+      r_dcache_tlb_paddr("r_dcache_tlb_paddr"),
+      r_dcache_miss_req("r_dcache_miss_req"),
+      r_dcache_unc_req("r_dcache_unc_req"),
+      r_dcache_write_req("r_dcache_write_req"),
+      r_dcache_tlb_read_req("r_dcache_tlb_read_req"),
+      r_dcache_tlb_ll_acc_req("r_dcache_tlb_ll_acc_req"),       
+      r_dcache_tlb_sc_acc_req("r_dcache_tlb_sc_acc_req"),       
+      r_dcache_tlb_ll_dirty_req("r_dcache_tlb_ll_dirty_req"),    
+      r_dcache_tlb_sc_dirty_req("r_dcache_tlb_sc_dirty_req"), 
+      r_dcache_tlb_ptba_read("r_dcache_tlb_ptba_read"),
+      r_dcache_xtn_req("r_dcache_xtn_req"),
+
+      r_dcache_fsm_save("r_dcache_fsm_save"),
+      r_dcache_cleanup_req("r_dcache_cleanup_req"),
+      r_dcache_inval_rsp("r_dcache_inval_rsp"),
+
+      r_icache_fsm("r_icache_fsm"),
+      r_icache_paddr_save("r_icache_paddr_save"),
+      r_icache_miss_req("r_icache_miss_req"),
+      r_icache_unc_req("r_icache_unc_req"),
+      r_dcache_itlb_read_req("r_dcache_itlb_read_req"),
+      r_dcache_itlb_ll_acc_req("r_dcache_itlb_ll_acc_req"),     
+      r_dcache_itlb_sc_acc_req("r_dcache_itlb_sc_acc_req"),
+      r_itlb_read_dcache_req("r_itlb_read_dcache_req"),
+      r_itlb_acc_dcache_req("r_itlb_acc_dcache_req"),
+      r_dcache_rsp_itlb_error("r_dcache_rsp_itlb_error"),
+
+      r_icache_fsm_save("r_icache_fsm_save"),
+      r_icache_cleanup_req("r_icache_cleanup_req"),
+      r_icache_inval_rsp("r_icache_inval_rsp"),
+
+      r_vci_cmd_fsm("r_vci_cmd_fsm"),
+      r_vci_cmd_min("r_vci_cmd_min"),
+      r_vci_cmd_max("r_vci_cmd_max"),
+      r_vci_cmd_cpt("r_vci_cmd_cpt"),
+
+      r_vci_rsp_fsm("r_vci_rsp_fsm"),
+      r_vci_rsp_cpt("r_vci_rsp_cpt"),
+      r_vci_rsp_ins_error("r_vci_rsp_ins_error"),
+      r_vci_rsp_data_error("r_vci_rsp_data_error"),
+
+      r_vci_cmd_cleanup_fsm("r_vci_cmd_cleanup_fsm"),
+      r_vci_rsp_cleanup_fsm("r_vci_rsp_cleanup_fsm"),
+
+      r_vci_tgt_fsm("r_vci_tgt_fsm"),
+      r_tgt_addr("r_tgt_addr"),
+      r_tgt_word("r_tgt_word"),
+      r_tgt_update("r_tgt_update"),
+      r_tgt_srcid("r_tgt_srcid"),
+      r_tgt_pktid("r_tgt_pktid"),
+      r_tgt_trdid("r_tgt_trdid"),
+      r_tgt_icache_req("r_tgt_icache_req"),
+      r_tgt_dcache_req("r_tgt_dcache_req"),
+
+      r_inval_itlb_fsm("r_inval_itlb_fsm"),          
+      r_dcache_itlb_inval_req("r_dcache_itlb_inval_req"),
+      r_dcache_itlb_inval_line("r_dcache_itlb_inval_line"),
+      r_itlb_cc_check_end("r_itlb_cc_check_end"),
+      r_ccinval_itlb_way("r_ccinval_itlb_way"), 
+      r_ccinval_itlb_set("r_ccinval_itlb_set"), 
+      r_icache_inval_tlb_rsp("r_icache_inval_tlb_rsp"),
+      r_icache_tlb_nline("r_icache_tlb_nline"),
+
+      r_inval_dtlb_fsm("r_inval_dtlb_fsm"),          
+      r_dcache_dtlb_inval_req("r_dcache_dtlb_inval_req"),
+      r_dcache_dtlb_inval_line("r_dcache_dtlb_inval_line"),
+      r_dtlb_cc_check_end("r_dtlb_cc_check_end"),
+      r_ccinval_dtlb_way("r_ccinval_dtlb_way"), 
+      r_ccinval_dtlb_set("r_ccinval_dtlb_set"), 
+      r_dcache_inval_tlb_rsp("r_dcache_inval_tlb_rsp"),
+      r_dcache_tlb_nline("r_dcache_tlb_nline"),
+
+      r_dcache_itlb_cleanup_req("r_dcache_itlb_cleanup_req"),
+      r_dcache_itlb_cleanup_line("r_dcache_itlb_cleanup_line"),
+
+      r_dcache_dtlb_cleanup_req("r_dcache_dtlb_cleanup_req"),
+      r_dcache_dtlb_cleanup_line("r_dcache_dtlb_cleanup_line"),
+
+      r_wbuf("wbuf", write_buf_size ),
+      r_icache("icache", icache_ways, icache_sets, icache_words),
+      r_dcache("dcache", dcache_ways, dcache_sets, dcache_words)
+{
+    r_icache_miss_buf = new data_t[icache_words];
+    r_dcache_miss_buf = new data_t[dcache_words];
+    r_tgt_buf         = new data_t[dcache_words];
+    r_tgt_val         = new bool[dcache_words];
+    r_dcache_in_itlb  = new bool[dcache_ways*dcache_sets];           
+    r_dcache_in_dtlb  = new bool[dcache_ways*dcache_sets];          
+
+    SC_METHOD(transition);
+    dont_initialize();
+    sensitive << p_clk.pos();
+  
+    SC_METHOD(genMoore);
+    dont_initialize();
+    sensitive << p_clk.neg();
+
+    typename iss_t::CacheInfo cache_info;
+    cache_info.has_mmu = true;
+    cache_info.icache_line_size = icache_words*sizeof(data_t);
+    cache_info.icache_assoc = icache_ways;
+    cache_info.icache_n_lines = icache_sets;
+    cache_info.dcache_line_size = dcache_words*sizeof(data_t);
+    cache_info.dcache_assoc = dcache_ways;
+    cache_info.dcache_n_lines = dcache_sets;
+    m_iss.setCacheInfo(cache_info);
+}
+
+/////////////////////////////////////
+tmpl(/**/)::~VciCcVCacheWrapper2Ring()
+/////////////////////////////////////
+{
+    delete [] r_icache_miss_buf;
+    delete [] r_dcache_miss_buf;
+    delete [] r_tgt_val;
+    delete [] r_tgt_buf;
+    delete [] r_dcache_in_itlb;           
+    delete [] r_dcache_in_dtlb;          
+}
+
+////////////////////////
+tmpl(void)::print_cpi()
+////////////////////////
+{
+    std::cout << name() << " CPI = " 
+        << (float)m_cpt_total_cycles/(m_cpt_total_cycles - m_cpt_frz_cycles) << std::endl ;
+}
+
+////////////////////////
+tmpl(void)::print_stats()
+////////////////////////
+{
+    float run_cycles = (float)(m_cpt_total_cycles - m_cpt_frz_cycles);
+    std::cout << name() << std::endl
+              << "- CPI                    = " << (float)m_cpt_total_cycles/run_cycles << std::endl 
+              << "- READ RATE              = " << (float)m_cpt_read/run_cycles << std::endl 
+              << "- WRITE RATE             = " << (float)m_cpt_write/run_cycles << std::endl
+              << "- UNCACHED READ RATE     = " << (float)m_cpt_unc_read/m_cpt_read << std::endl 
+              << "- CACHED WRITE RATE      = " << (float)m_cpt_write_cached/m_cpt_write << std::endl 
+              << "- IMISS_RATE             = " << (float)m_cpt_ins_miss/m_cpt_ins_read << std::endl    
+              << "- DMISS RATE             = " << (float)m_cpt_data_miss/(m_cpt_read-m_cpt_unc_read) << std::endl 
+              << "- INS MISS COST          = " << (float)m_cost_ins_miss_frz/m_cpt_ins_miss << std::endl
+              << "- IMISS TRANSACTION      = " << (float)m_cost_imiss_transaction/m_cpt_imiss_transaction << std::endl
+              << "- DMISS COST             = " << (float)m_cost_data_miss_frz/m_cpt_data_miss << std::endl
+              << "- DMISS TRANSACTION      = " << (float)m_cost_dmiss_transaction/m_cpt_dmiss_transaction << std::endl
+              << "- UNC COST               = " << (float)m_cost_unc_read_frz/m_cpt_unc_read << std::endl
+              << "- UNC TRANSACTION        = " << (float)m_cost_unc_transaction/m_cpt_unc_transaction << std::endl
+              << "- WRITE COST             = " << (float)m_cost_write_frz/m_cpt_write << std::endl
+              << "- WRITE TRANSACTION      = " << (float)m_cost_write_transaction/m_cpt_write_transaction << std::endl
+              << "- WRITE LENGTH           = " << (float)m_length_write_transaction/m_cpt_write_transaction << std::endl
+              << "- INS TLB MISS RATE      = " << (float)m_cpt_ins_tlb_miss/m_cpt_ins_tlb_read << std::endl
+              << "- DATA TLB MISS RATE     = " << (float)m_cpt_data_tlb_miss/m_cpt_data_tlb_read << std::endl
+              << "- ITLB MISS TRANSACTION  = " << (float)m_cost_itlbmiss_transaction/m_cpt_itlbmiss_transaction << std::endl
+              << "- ITLB WRITE TRANSACTION = " << (float)m_cost_itlb_write_transaction/m_cpt_itlb_write_transaction << std::endl
+              << "- ITLB MISS COST         = " << (float)m_cost_ins_tlb_miss_frz/(m_cpt_ins_tlb_miss+m_cpt_ins_tlb_write_et) << std::endl
+              << "- DTLB MISS TRANSACTION  = " << (float)m_cost_dtlbmiss_transaction/m_cpt_dtlbmiss_transaction << std::endl
+              << "- DTLB WRITE TRANSACTION = " << (float)m_cost_dtlb_write_transaction/m_cpt_dtlb_write_transaction << std::endl
+              << "- DTLB MISS COST         = " << (float)m_cost_data_tlb_miss_frz/(m_cpt_data_tlb_miss+m_cpt_data_tlb_write_et+m_cpt_data_tlb_write_dirty) << std::endl;
+}
+
+/*************************************************/
+tmpl(void)::transition()
+/*************************************************/
+{
+    if ( ! p_resetn.read() ) 
+    {
+        m_iss.reset();
+
+        r_dcache_fsm = DCACHE_IDLE;
+        r_icache_fsm = ICACHE_IDLE;
+        r_vci_cmd_fsm = CMD_IDLE;
+        r_vci_rsp_fsm = RSP_IDLE;
+        r_vci_cmd_cleanup_fsm = CMD_CLEANUP_INS_IDLE;
+        r_vci_rsp_cleanup_fsm = RSP_CLEANUP_INS_IDLE;
+        r_vci_tgt_fsm = TGT_IDLE;
+        r_inval_itlb_fsm = INVAL_ITLB_IDLE;          
+        r_inval_dtlb_fsm = INVAL_DTLB_IDLE;          
+
+        // write buffer & caches
+        r_wbuf.reset();
+        r_icache.reset();
+        r_dcache.reset();
+
+        icache_tlb.reset();    
+        dcache_tlb.reset();    
+
+        std::memset(r_dcache_in_itlb, 0, sizeof(*r_dcache_in_itlb)*m_icache_ways*m_icache_sets);
+        std::memset(r_dcache_in_dtlb, 0, sizeof(*r_dcache_in_dtlb)*m_dcache_ways*m_dcache_sets);
+
+        r_mmu_mode = ALL_DEACTIVE;
+
+        r_icache_miss_req         = false;
+        r_icache_unc_req          = false;
+        r_dcache_itlb_read_req    = false;
+
+        r_itlb_read_dcache_req 	  = false;      
+        r_itlb_acc_dcache_req     = false;   
+        r_dcache_rsp_itlb_error   = false;
+ 
+        r_dcache_miss_req         = false;
+        r_dcache_unc_req          = false;
+        r_dcache_write_req        = false;
+        r_dcache_tlb_read_req     = false;
+        r_dcache_tlb_ptba_read    = false;
+        r_dcache_xtn_req          = false;
+	r_dcache_llsc_reserved    = false;
+
+        r_dcache_tlb_ll_acc_req   = false;    
+        r_dcache_tlb_sc_acc_req   = false;    
+        r_dcache_tlb_ll_dirty_req = false;   
+        r_dcache_tlb_sc_dirty_req = false;   
+        r_dcache_itlb_ll_acc_req  = false;   
+        r_dcache_itlb_sc_acc_req  = false;   
+
+        r_icache_cleanup_req      = false;
+        r_dcache_cleanup_req      = false;
+
+        r_tgt_icache_req          = false;
+        r_tgt_dcache_req          = false;
+
+        r_icache_inval_rsp        = false;
+        r_dcache_inval_rsp        = false;
+
+        r_dcache_dirty_save       = false;
+        r_dcache_hit_p_save       = false;
+
+        r_icache_buf_unc_valid    = false;
+        r_dcache_buf_unc_valid    = false;
+
+        r_vci_rsp_ins_error       = false;
+        r_vci_rsp_data_error      = false;
+
+        r_icache_id1_save         = 0;
+        r_icache_ppn_save         = 0;
+        r_icache_vpn_save         = 0;
+        r_itlb_translation_valid  = false;
+
+        r_dcache_id1_save         = 0;
+        r_dcache_ppn_save         = 0;
+        r_dcache_vpn_save         = 0;
+        r_dtlb_translation_valid  = false;
+
+        r_icache_ptba_ok          = false;
+        r_dcache_ptba_ok          = false;
+
+        r_icache_error_type       = MMU_NONE;
+        r_dcache_error_type       = MMU_NONE;
+
+        // coherence registers
+        r_icache_way              = 0;
+        r_icache_set              = 0;
+        r_icache_cleanup_req      = false;
+        r_icache_inval_rsp        = false;
+
+        r_dcache_way              = 0;
+        r_dcache_set              = 0;
+        r_dcache_cleanup_req      = false;
+        r_dcache_inval_rsp        = false;
+
+	r_itlb_inval_req 	  = false;
+        r_dcache_itlb_inval_req   = false;
+        r_itlb_cc_check_end       = false;
+        r_ccinval_itlb_way        = 0; 
+        r_ccinval_itlb_set        = 0; 
+        r_icache_inval_tlb_rsp    = false;
+
+        r_dcache_dtlb_inval_req   = false;
+        r_dtlb_cc_check_end       = false;
+        r_ccinval_dtlb_way        = 0; 
+        r_ccinval_dtlb_set        = 0; 
+        r_dcache_inval_tlb_rsp    = false;
+
+        r_dcache_itlb_cleanup_req = false;
+        r_dcache_dtlb_cleanup_req = false;
+
+	r_dcache_cc_check         = false;
+
+        // activity counters
+        m_cpt_dcache_data_read  = 0;
+        m_cpt_dcache_data_write = 0;
+        m_cpt_dcache_dir_read   = 0;
+        m_cpt_dcache_dir_write  = 0;
+        m_cpt_icache_data_read  = 0;
+        m_cpt_icache_data_write = 0;
+        m_cpt_icache_dir_read   = 0;
+        m_cpt_icache_dir_write  = 0;
+
+	m_cpt_frz_cycles   = 0;
+        m_cpt_total_cycles = 0;
+
+        m_cpt_read         = 0;
+        m_cpt_write        = 0;
+        m_cpt_data_miss    = 0;
+        m_cpt_ins_miss     = 0;
+        m_cpt_unc_read     = 0;
+        m_cpt_write_cached = 0;
+        m_cpt_ins_read     = 0;
+
+        m_cost_write_frz     = 0;
+        m_cost_data_miss_frz = 0;
+        m_cost_unc_read_frz  = 0;
+        m_cost_ins_miss_frz  = 0;
+
+        m_cpt_imiss_transaction = 0;
+        m_cpt_dmiss_transaction = 0;
+        m_cpt_unc_transaction   = 0;
+        m_cpt_write_transaction = 0;
+
+        m_cost_imiss_transaction   = 0;
+        m_cost_dmiss_transaction   = 0;
+        m_cost_unc_transaction     = 0;
+        m_cost_write_transaction   = 0;
+        m_length_write_transaction = 0;
+
+        m_cpt_ins_tlb_read         = 0;             
+        m_cpt_ins_tlb_miss         = 0;             
+        m_cpt_ins_tlb_write_et     = 0;         
+
+        m_cpt_data_tlb_read        = 0;           
+        m_cpt_data_tlb_miss        = 0;           
+        m_cpt_data_tlb_write_et    = 0;       
+        m_cpt_data_tlb_write_dirty = 0;    
+
+        m_cost_ins_tlb_miss_frz    = 0;      
+        m_cost_data_tlb_miss_frz   = 0;      
+
+        m_cpt_itlbmiss_transaction   = 0;    
+        m_cpt_itlb_write_transaction = 0;  
+        m_cpt_dtlbmiss_transaction   = 0;  
+        m_cpt_dtlb_write_transaction = 0;  
+ 
+        m_cost_itlbmiss_transaction   = 0;   
+        m_cost_itlb_write_transaction = 0;  
+        m_cost_dtlbmiss_transaction   = 0;   
+        m_cost_dtlb_write_transaction = 0;   
+        return;
+    }
+
+
+#ifdef SOCLIB_MODULE_DEBUG
+std::cout << name() << "cycle = " << m_cpt_total_cycles  
+       	  << " tgt fsm: " << tgt_fsm_state_str[r_vci_tgt_fsm]
+       	  << " dcache fsm: " << dcache_fsm_state_str[r_dcache_fsm]
+       	  << " icache fsm: " << icache_fsm_state_str[r_icache_fsm]
+       	  << " cmd fsm: " << cmd_fsm_state_str[r_vci_cmd_fsm]
+       	  << " rsp fsm: " << rsp_fsm_state_str[r_vci_rsp_fsm] 
+       	  << " cmd cleanup fsm: " << cmd_cleanup_fsm_state_str[r_vci_cmd_cleanup_fsm]
+       	  << " rsp cleanup fsm: " << rsp_cleanup_fsm_state_str[r_vci_rsp_cleanup_fsm] 
+       	  << " inval itlb fsm: " << inval_itlb_fsm_state_str[r_inval_itlb_fsm] 
+       	  << " inval dtlb fsm: " << inval_dtlb_fsm_state_str[r_inval_dtlb_fsm] << std::endl;
+#endif
+    m_cpt_total_cycles++;
+
+    typename iss_t::InstructionRequest ireq = ISS_IREQ_INITIALIZER;
+    typename iss_t::InstructionResponse irsp = ISS_IRSP_INITIALIZER;
+
+    typename iss_t::DataRequest dreq = ISS_DREQ_INITIALIZER;
+    typename iss_t::DataResponse drsp = ISS_DRSP_INITIALIZER;
+
+    m_iss.getRequests( ireq, dreq );
+
+#ifdef SOCLIB_MODULE_DEBUG
+    std::cout << name() << " Instruction Request: " << ireq << std::endl;
+    std::cout << name() << " Data Request: " << dreq << std::endl;
+#endif
+
+    /////////////////////////////////////////////////////////////////////
+    // The TGT_FSM controls the following ressources:
+    // - r_vci_tgt_fsm
+    // - r_tgt_buf[nwords]
+    // - r_tgt_val[nwords]
+    // - r_tgt_update
+    // - r_tgt_word
+    // - r_tgt_addr
+    // - r_tgt_srcid
+    // - r_tgt_trdid
+    // - r_tgt_pktid
+    // All VCI commands must be CMD_WRITE.
+    // If the VCI address offset is null, the command is an invalidate 
+    // request. It is an update request otherwise.
+    // The VCI_TGT FSM stores the external request arguments in the
+    // IDLE, UPDT_WORD & UPDT_DATA states. It sets the r_tgt_icache_req 
+    // & r_tgt_dcache_req flip-flops to signal the external request to 
+    // the ICACHE & DCACHE FSMs in the REQ state. It waits the completion
+    // of the update or invalidate request in the RSP state.
+    // -  for an invalidate request the VCI packet length is 1 word.
+    // The WDATA field contains the line index (i.e. the Z & Y fields).
+    // -  for an update request the VCI packet length is (n+2) words.
+    // The WDATA field of the first VCI word contains the line number.
+    // The WDATA field of the second VCI word contains the word index.
+    // The WDATA field of the n following words contains the values.
+    // -  for both invalidate & update requests, the VCI response
+    // is one single word.
+    // In case of errors in the VCI command packet, the simulation
+    // is stopped with an error message.
+    /////////////////////////////////////////////////////////////////////
+    
+    switch(r_vci_tgt_fsm) {
+    //////////////
+    case TGT_IDLE:
+    {
+        if ( p_vci_tgt.cmdval.read() ) 
+        {
+            paddr_t address = p_vci_tgt.address.read();
+
+            if ( p_vci_tgt.cmd.read() != vci_param::CMD_WRITE) 
+            {
+                std::cout << "error in component VCI_CC_VCACHE_WRAPPER " << name() << std::endl;
+                std::cout << "the received VCI command is not a write" << std::endl;
+                exit(0);
+            }
+
+            // multi-update or multi-invalidate for data type
+            if ( ( address != 0x3 ) && ( ! m_segment.contains(address)) ) 
+            {
+                std::cout << "error in component VCI_CC_VCACHE_WRAPPER " << name() << std::endl;
+                std::cout << "out of segment VCI command received for a multi-updt or multi-inval request" << std::endl;
+                exit(0);
+            }
+
+            r_tgt_srcid = p_vci_tgt.srcid.read();
+            r_tgt_trdid = p_vci_tgt.trdid.read();
+            r_tgt_pktid = p_vci_tgt.pktid.read();
+            r_tgt_plen  = p_vci_tgt.plen.read(); // todo: wait L2 modification
+            r_tgt_addr = (paddr_t)p_vci_tgt.wdata.read() * m_dcache_words * 4; 
+
+            if ( address == 0x3 ) // broadcast invalidate for data or instruction type
+            {
+                if ( ! p_vci_tgt.eop.read() ) 
+                {
+                    std::cout << "error in component VCI_CC_VCACHE_WRAPPER " << name() << std::endl;
+                    std::cout << "the BROADCAST INVALIDATE command length must be one word" << std::endl;
+                    exit(0);
+                }
+                r_tgt_update = false; 
+                r_vci_tgt_fsm = TGT_REQ_BROADCAST;
+                m_cpt_cc_broadcast++;
+            }
+            else                // multi-update or multi-invalidate for data type
+            {
+                paddr_t cell = address - m_segment.baseAddress();   
+
+                if (cell == 0)                      // invalidate   
+                {                         
+                    if ( ! p_vci_tgt.eop.read() ) 
+                    {
+                        std::cout << "error in component VCI_CC_VCACHE_WRAPPER " << name() << std::endl;
+                        std::cout << "the MULTI-INVALIDATE command length must be one word" << std::endl;
+                        exit(0);
+                    }
+                    r_tgt_update = false; 
+                    r_vci_tgt_fsm = TGT_REQ_DCACHE;
+                    m_cpt_cc_inval++ ;
+                } 
+                else                                // update
+                {                                
+                    if ( p_vci_tgt.eop.read() ) 
+                    {
+                        std::cout << "error in component VCI_CC_VCACHE_WRAPPER " << name() << std::endl;
+                        std::cout << "the MULTI-UPDATE command length must be N+2 words" << std::endl;
+                        exit(0);
+                    }
+                    r_tgt_update = true; 
+                    r_vci_tgt_fsm = TGT_UPDT_WORD;
+                    m_cpt_cc_update++ ;
+                }     
+            } // end if address    
+        } // end if cmdval
+        break;
+    }
+    ////////////////////
+    case TGT_UPDT_WORD:
+    {
+        if (p_vci_tgt.cmdval.read()) 
+        {
+            if ( p_vci_tgt.eop.read() ) 
+            {
+                std::cout << "error in component VCI_CC_VCACHE_WRAPPER " << name() << std::endl;
+                std::cout << "the MULTI-UPDATE command length must be N+2 words" << std::endl;
+                exit(0);
+            }
+            for ( size_t i=0 ; i<m_dcache_words ; i++ ) r_tgt_val[i] = false;
+            r_tgt_word = p_vci_tgt.wdata.read(); // the first modified word index
+            r_vci_tgt_fsm = TGT_UPDT_DATA;
+        }
+        break;
+    }
+    ////////////////////
+    case TGT_UPDT_DATA:
+    {
+        if (p_vci_tgt.cmdval.read()) 
+        {
+            size_t word = r_tgt_word.read();
+            if (word >= m_dcache_words) 
+            {
+                std::cout << "error in component VCI_CC_VCACHE_WRAPPER " << name() << std::endl;
+                std::cout << "the reveived MULTI-UPDATE command length is wrong" << std::endl;
+                exit(0);
+            }
+            r_tgt_buf[word] = p_vci_tgt.wdata.read();
+            if(p_vci_tgt.be.read())    r_tgt_val[word] = true;
+            r_tgt_word = word + 1;
+            if (p_vci_tgt.eop.read())  r_vci_tgt_fsm = TGT_REQ_DCACHE;
+        }
+        break;
+    }
+    ///////////////////////
+    case TGT_REQ_BROADCAST:
+    {
+        if ( !r_tgt_icache_req.read() && !r_tgt_dcache_req.read() ) 
+        {
+            r_vci_tgt_fsm = TGT_RSP_BROADCAST; 
+            r_tgt_icache_req = true;
+            r_tgt_dcache_req = true;
+        }
+        break;
+    }
+    ////////////////////
+    case TGT_REQ_DCACHE:
+    {
+        if ( !r_tgt_dcache_req.read() ) 
+        {
+            r_vci_tgt_fsm = TGT_RSP_DCACHE; 
+            r_tgt_dcache_req = true;
+        }
+        break;
+    }
+    ///////////////////////
+    case TGT_RSP_BROADCAST:
+    {
+        // no response
+        if ( !r_tgt_icache_rsp.read() && !r_tgt_dcache_rsp.read() && !r_tgt_icache_req.read() && !r_tgt_dcache_req.read() )
+        {
+            r_vci_tgt_fsm = TGT_IDLE;
+            break;
+        }
+
+        if ( p_vci_tgt.rspack.read() && !r_tgt_icache_req.read() && !r_tgt_dcache_req.read() ) 
+        {
+            // one response
+            if ( !r_tgt_icache_rsp || !r_tgt_dcache_rsp )
+            {
+                r_vci_tgt_fsm = TGT_IDLE; 
+                r_tgt_icache_rsp = false;
+                r_tgt_dcache_rsp = false;
+            }
+
+            // if data and instruction have the inval line, need two responses  
+            if ( r_tgt_icache_rsp && r_tgt_dcache_rsp )
+            {
+                r_tgt_icache_rsp = false; // only reset one for respond the second time 
+            }
+        }
+        break;
+    }
+    ////////////////////
+    case TGT_RSP_DCACHE:
+    {
+        if ( p_vci_tgt.rspack.read() && !r_tgt_dcache_req.read() ) 
+        {
+            r_vci_tgt_fsm = TGT_IDLE;
+            r_tgt_dcache_rsp = false; 
+        }
+        break;
+    }
+    } // end switch TGT_FSM
+
+    ////////////////////////////////////////////////////////////////////////////////////////
+    //      ICACHE_FSM
+    //
+    // There is 9 mutually exclusive conditions to exit the IDLE state.
+    // Four configurations corresponding to an XTN request from processor,
+    // - Flush TLB (in case of Context switch) => TLB_FLUSH state 
+    // - Flush cache => CACHE_FLUSH state 
+    // - Invalidate a TLB entry => TLB_INVAL state
+    // - Invalidate a cache line => CACHE_INVAL state
+    // Five configurations corresponding to various TLB or cache MISS :
+    // - TLB miss(in case hit_p miss) => TLB1_READ state
+    // - TLB miss(in case hit_p hit) => TLB2_READ state
+    // - Hit in TLB but VPN changed => BIS state
+    // - Cached read miss => MISS_REQ state
+    // - Uncache read miss => UNC_REQ state
+    // 
+    // In case of MISS, the controller writes a request in the r_icache_paddr_save register 
+    // and sets the corresponding request flip-flop : r_dcache_itlb_read_req, r_icache_miss_req 
+    // or r_icache_unc_req. These request flip-flops are reset by the VCI_RSP controller 
+    // when the response is ready in the ICACHE buffer.
+    //
+    // The DCACHE FSM signals XTN processor requests using the r_dcache_xtn_req flip-flop. 
+    // The request opcod and the address to be invalidated are transmitted
+    // in the r_dcache_paddr_save & r_dcache_wdata_save registers respectively.
+    // The request flip-flop is reset by the ICACHE_FSM when the operation is completed.
+    //
+    // The r_vci_rsp_ins_error flip-flop is set by the VCI_RSP FSM and reset
+    // by the ICACHE-FSM in the ICACHE_ERROR state.
+    //
+    //----------------------------------------------------------------------------------- 
+    // Instruction TLB: 
+    //  
+    // - int        ET          (00: unmapped; 01: unused or PTD)
+    //                          (10: PTE new;  11: PTE old      )
+    // - bool       cachable    (cached bit)
+    // - bool       writable    (** not used alwayse false) 
+    // - bool       executable  (executable bit)
+    // - bool       user        (access in user mode allowed)
+    // - bool       global      (PTE not invalidated by a TLB flush)
+    // - bool       dirty       (** not used alwayse false) 
+    // - uint32_t   vpn         (virtual page number)
+    // - uint32_t   ppn         (physical page number)
+    ////////////////////////////////////////////////////////////////////////////////////////
+
+    switch(r_icache_fsm) {
+
+    ////////////////
+    case ICACHE_IDLE:
+    {
+        pte_info_t  icache_pte_info;
+        paddr_t     tlb_ipaddr       = 0;    	// physical address obtained from TLB                         
+        paddr_t     spc_ipaddr       = 0;    	// physical adress obtained from PPN_save (speculative)       
+        data_t      icache_ins       = 0;    	// read instruction
+        bool        icache_hit_c     = false;	// Cache hit
+        bool        icache_cached    = false;	// cacheable access (read)
+        bool        icache_hit_t     = false;	// hit on TLB
+        bool        icache_hit_x     = false;	// VPN unmodified (can use spc_dpaddr)
+        bool        icache_hit_p     = false;	// PTP unmodified (can skip first level page table walk)
+        size_t      icache_tlb_way   = 0;    	// selected way (in case of cache hit)
+        size_t      icache_tlb_set   = 0;    	// selected set (Y field in address)
+        paddr_t     icache_tlb_nline = 0;  	// TLB NLINE 
+
+        // Decoding processor XTN requests
+        // They are sent by DCACHE FSM  
+
+        if (r_dcache_xtn_req)
+        {
+            if ( ireq.valid ) m_cost_ins_waste_wait_frz++;
+            
+            if ((int)r_dcache_type_save == (int)iss_t::XTN_PTPR )  
+            {
+                r_icache_way = 0;
+                r_icache_set = 0;
+                r_icache_fsm = ICACHE_SW_FLUSH;   
+                break;
+            }
+            if ((int)r_dcache_type_save == (int)iss_t::XTN_ICACHE_FLUSH)
+            {
+                r_icache_way = 0;
+                r_icache_set = 0;
+                r_icache_fsm = ICACHE_CACHE_FLUSH;   
+                break;
+            }
+            if ((int)r_dcache_type_save == (int)iss_t::XTN_ITLB_INVAL) 
+            {
+                r_icache_fsm = ICACHE_TLB_INVAL;   
+                break;
+            }
+            if ((int)r_dcache_type_save == (int)iss_t::XTN_ICACHE_INVAL) 
+            {
+                r_icache_fsm = ICACHE_CACHE_INVAL;   
+                break;
+            }
+            if ((int)r_dcache_type_save == (int)iss_t::XTN_DCACHE_FLUSH )  
+            {
+                // special for ins tlb miss via data cache
+                r_icache_fsm = ICACHE_TLB_FLUSH;   
+                break;
+            }
+        } // end if xtn_req
+
+        // external cache invalidate request
+        if ( r_tgt_icache_req )
+        {
+            if ( ireq.valid ) m_cost_ins_waste_wait_frz++;
+            r_icache_fsm = ICACHE_CC_INVAL;
+            r_icache_fsm_save = r_icache_fsm;
+            break;
+        }
+
+        // external tlb invalidate request
+        if ( r_dcache_itlb_inval_req )
+        {
+            if ( ireq.valid ) m_cost_ins_waste_wait_frz++;
+	    r_itlb_inval_req = true;
+            r_icache_fsm = ICACHE_TLB_CC_INVAL;
+            r_icache_fsm_save = r_icache_fsm;
+            break;
+        }
+
+        // icache_hit_t_m, icache_hit_t_k, icache_hit_x, icache_hit_p 
+        // icache_pte_info, icache_tlb_way, icache_tlb_set & ipaddr & cacheability 
+        // - If MMU activated : cacheability is defined by the cachable bit in the TLB
+        // - If MMU not activated : cacheability is defined by the segment table.
+
+        if ( !(r_mmu_mode.read() & INS_TLB_MASK) )   // MMU not activated 
+        {
+            icache_hit_t  = true;         
+            icache_hit_x  = true;         
+            icache_hit_p  = true;         
+            tlb_ipaddr    = ireq.addr;
+            spc_ipaddr    = ireq.addr;
+            icache_cached = m_cacheability_table[ireq.addr];
+        } 
+        else                                                                // MMU activated
+        { 
+            m_cpt_ins_tlb_read++;
+            icache_hit_t  = icache_tlb.cctranslate(ireq.addr, &tlb_ipaddr, &icache_pte_info, 
+                                                   &icache_tlb_nline, &icache_tlb_way, &icache_tlb_set); 
+            icache_hit_x  = (((vaddr_t)r_icache_vpn_save << PAGE_K_NBITS) == (ireq.addr & ~PAGE_K_MASK)) && r_itlb_translation_valid;
+            icache_hit_p  = (((ireq.addr >> PAGE_M_NBITS) == r_icache_id1_save) && r_icache_ptba_ok); 
+            spc_ipaddr    = ((paddr_t)r_icache_ppn_save << PAGE_K_NBITS) | (paddr_t)(ireq.addr & PAGE_K_MASK);
+            icache_cached = icache_pte_info.c; 
+        }
+
+        if ( !(r_mmu_mode.read() & INS_CACHE_MASK) )   // cache not actived
+        {
+            icache_cached = false;
+        }
+
+        if ( ireq.valid ) 
+        {
+            m_cpt_icache_dir_read += m_icache_ways;
+            m_cpt_icache_data_read += m_icache_ways;
+
+            // icache_hit_c & icache_ins
+            if ( icache_cached )    // using speculative physical address for cached access
+            {
+                icache_hit_c = r_icache.read(spc_ipaddr, &icache_ins);
+            }
+            else                    // using actual physical address for uncached access
+            {
+                icache_hit_c = ( r_icache_buf_unc_valid && (tlb_ipaddr == (paddr_t)r_icache_paddr_save) );
+                icache_ins = r_icache_miss_buf[0];
+            }
+
+            if ( r_mmu_mode.read() & INS_TLB_MASK ) 
+            {
+                if ( icache_hit_t ) 
+                {
+                    // check access rights
+                    if ( !icache_pte_info.u && (ireq.mode == iss_t::MODE_USER)) 
+                    {
+                        r_icache_error_type = MMU_READ_PRIVILEGE_VIOLATION;  
+                        r_icache_bad_vaddr = ireq.addr;
+                        irsp.valid = true;
+                        irsp.error = true;
+                        irsp.instruction = 0;
+                        break;
+                    }
+                    if ( !icache_pte_info.x ) 
+                    {
+                        r_icache_error_type = MMU_READ_EXEC_VIOLATION;  
+                        r_icache_bad_vaddr = ireq.addr;
+                        irsp.valid = true;
+                        irsp.error = true;
+                        irsp.instruction = 0;
+                        break;
+                    }
+                }
+
+                // update LRU, save ppn, vpn and page type
+                if ( icache_hit_t )
+                {  
+                    icache_tlb.setlru(icache_tlb_way,icache_tlb_set);     
+                    r_icache_ppn_save = tlb_ipaddr >> PAGE_K_NBITS;
+                    r_icache_vpn_save = ireq.addr >> PAGE_K_NBITS;
+                    r_icache_tlb_nline = icache_tlb_nline;
+                    r_itlb_translation_valid = true;
+                }
+                else
+                {
+                    r_itlb_translation_valid = false;
+                }
+
+            } // end if MMU activated
+
+            // compute next state 
+            if ( !icache_hit_t && !icache_hit_p )      // TLB miss
+            {
+                // walk page table  level 1
+                r_icache_paddr_save = (paddr_t)r_mmu_ptpr << (INDEX1_NBITS+2) | (paddr_t)((ireq.addr>>PAGE_M_NBITS)<<2);
+                r_itlb_read_dcache_req = true;
+                r_icache_fsm = ICACHE_TLB1_READ;
+                m_cpt_ins_tlb_miss++;
+                m_cost_ins_tlb_miss_frz++;
+            }
+            else if ( !icache_hit_t && icache_hit_p )  // TLB Miss with possibility of bypass first level page
+            {
+                // walk page table level 2
+                r_icache_paddr_save = (paddr_t)r_icache_ptba_save | 
+                                      (paddr_t)(((ireq.addr&PTD_ID2_MASK)>>PAGE_K_NBITS) << 3);
+                r_itlb_read_dcache_req = true;
+                r_icache_fsm = ICACHE_TLB2_READ;
+                m_cpt_ins_tlb_miss++;
+                m_cost_ins_tlb_miss_frz++;
+            }
+            else if ( icache_hit_t && !icache_hit_x && icache_cached ) // cached access with an ucorrect speculative physical address
+            {
+                r_icache_paddr_save = tlb_ipaddr;   // save actual physical address for BIS
+                r_icache_fsm = ICACHE_BIS;
+                m_cost_ins_miss_frz++;
+            }
+            else    // cached or uncached access with a correct speculative physical address 
+            {        
+                m_cpt_ins_read++; 
+                if ( !icache_hit_c ) 
+                {
+                    m_cpt_ins_miss++;
+                    m_cost_ins_miss_frz++;
+                    if ( icache_cached ) 
+                    {
+                        r_icache_miss_req = true;
+                    	r_icache_paddr_save = spc_ipaddr; 
+                        r_icache_fsm = ICACHE_MISS_WAIT;
+                    } 
+                    else 
+                    {
+                        r_icache_unc_req = true;
+                        r_icache_buf_unc_valid = false;
+                    	r_icache_paddr_save = tlb_ipaddr; 
+                        r_icache_fsm = ICACHE_UNC_WAIT;
+                    } 
+                } 
+                else 
+                {
+                    r_icache_buf_unc_valid = false;
+                    r_icache_fsm = ICACHE_IDLE;
+                }
+                irsp.valid = icache_hit_c;
+                irsp.instruction = icache_ins;
+            } // end if next states
+            
+        } // end if ireq.valid
+        break;
+    }
+    ////////////////
+    case ICACHE_BIS: 
+    {
+        m_cost_ins_miss_frz++;
+        // external cache invalidate request
+        if ( r_tgt_icache_req )
+        {
+            r_icache_fsm = ICACHE_CC_INVAL;
+            r_icache_fsm_save = r_icache_fsm;
+            m_cost_ins_waste_wait_frz++;
+            break;
+        }
+
+        // external tlb invalidate request
+        if ( r_dcache_itlb_inval_req )
+        {
+	    r_itlb_inval_req = true;
+            r_icache_fsm = ICACHE_TLB_CC_INVAL;
+            r_icache_fsm_save = r_icache_fsm;
+            m_cost_ins_waste_wait_frz++;
+            break;
+        }
+      
+        // using page is invalidated 
+        if ( r_icache_inval_tlb_rsp )
+        {
+            r_icache_inval_tlb_rsp = false;
+            r_icache_fsm = ICACHE_IDLE;
+            m_cost_ins_tlb_miss_frz++;
+            break;
+        }
+ 
+        data_t  icache_ins = 0;
+        bool    icache_hit = false;
+
+        // acces is always cached in this state
+        icache_hit = r_icache.read(r_icache_paddr_save, &icache_ins);
+
+        m_cpt_ins_read++;
+        if ( !icache_hit )
+        {
+            r_icache_miss_req = true;
+            r_icache_fsm = ICACHE_MISS_WAIT;
+            m_cpt_ins_miss++;
+        } 
+        else
+        {
+            r_icache_fsm = ICACHE_IDLE; 
+        }
+
+        irsp.valid = icache_hit;
+        irsp.error = false;
+        irsp.instruction = icache_ins;
+        break;
+    }
+    //////////////////////
+    case ICACHE_TLB1_READ:
+    {
+        m_cost_ins_tlb_miss_frz++;
+
+        // external cache invalidate request
+        if ( r_tgt_icache_req )
+        {
+            r_icache_fsm = ICACHE_CC_INVAL;
+            r_icache_fsm_save = r_icache_fsm;
+            m_cost_ins_waste_wait_frz++;
+            break;
+        }
+
+        // external tlb invalidate request
+        if ( r_dcache_itlb_inval_req )
+        {
+	    r_itlb_inval_req = true;
+            r_icache_fsm = ICACHE_TLB_CC_INVAL;
+            r_icache_fsm_save = r_icache_fsm;
+            m_cost_ins_waste_wait_frz++;
+            break;
+        }
+
+        if ( !r_itlb_read_dcache_req && !r_icache_inval_tlb_rsp ) // TLB miss read response and no invalidation
+        {
+            if ( !r_dcache_rsp_itlb_error ) // vci response ok
+            {  
+		if ( !(r_dcache_rsp_itlb_miss >> PTE_V_SHIFT) ) // unmapped
+		{
+            	    r_icache_ptba_ok    = false;	
+                    r_icache_error_type = MMU_READ_PT1_UNMAPPED;  
+                    r_icache_bad_vaddr  = ireq.addr;
+                    r_icache_fsm        = ICACHE_ERROR;
+		}
+		else if ( (r_dcache_rsp_itlb_miss & PTE_T_MASK ) >> PTE_T_SHIFT ) // PTD
+		{
+            	    r_icache_ptba_ok       = true;	
+                    r_icache_ptba_save     = (paddr_t)(r_dcache_rsp_itlb_miss & ((1<<(m_paddr_nbits - PAGE_K_NBITS))-1)) << PAGE_K_NBITS; 
+                    r_icache_id1_save      = ireq.addr >> PAGE_M_NBITS;
+                    r_icache_paddr_save    = (paddr_t)(r_dcache_rsp_itlb_miss & ((1<<(m_paddr_nbits - PAGE_K_NBITS))-1)) << PAGE_K_NBITS |
+                                             (paddr_t)(((ireq.addr & PTD_ID2_MASK) >> PAGE_K_NBITS) << 3); 
+                    r_itlb_read_dcache_req = true;
+                    r_icache_fsm           = ICACHE_TLB2_READ;
+		}	
+		else
+		{
+            	    r_icache_ptba_ok = false;
+	
+		    if ( (m_srcid_rw >> 4) == ((r_dcache_rsp_itlb_miss & ((1<<(m_paddr_nbits - PAGE_M_NBITS))-1)) >> (m_paddr_nbits - PAGE_M_NBITS -10)) ) // local
+		    {
+			if ( (r_dcache_rsp_itlb_miss & PTE_L_MASK ) >> PTE_L_SHIFT ) // L bit is set
+			{
+                            r_icache_pte_update = r_dcache_rsp_itlb_miss;
+                            r_icache_fsm        = ICACHE_TLB1_UPDT;
+			}
+			else
+			{
+                            r_icache_pte_update   = r_dcache_rsp_itlb_miss | PTE_L_MASK;
+                            r_itlb_acc_dcache_req = true;
+                            r_icache_fsm          = ICACHE_TLB1_WRITE;
+                            m_cpt_ins_tlb_write_et++;
+			}
+    	            }
+		    else // remotely
+		    {
+			if ( (r_dcache_rsp_itlb_miss & PTE_R_MASK ) >> PTE_R_SHIFT ) // R bit is set
+			{
+                            r_icache_pte_update = r_dcache_rsp_itlb_miss;
+                            r_icache_fsm        = ICACHE_TLB1_UPDT;
+			}
+			else
+			{
+                            r_icache_pte_update   = r_dcache_rsp_itlb_miss | PTE_R_MASK;
+                            r_itlb_acc_dcache_req = true;
+                            r_icache_fsm          = ICACHE_TLB1_WRITE;
+                            m_cpt_ins_tlb_write_et++;
+			}
+		    }
+		}
+            }
+            else                        // vci response error
+            {  
+                r_icache_fsm = ICACHE_ERROR;
+                r_icache_error_type = MMU_READ_PT1_ILLEGAL_ACCESS;    
+                r_icache_bad_vaddr = ireq.addr;
+            }
+        }
+
+        if ( !r_itlb_read_dcache_req && r_icache_inval_tlb_rsp ) // TLB miss read response and invalidation
+        {
+            if ( r_dcache_rsp_itlb_error ) 
+            {
+                r_icache_inval_tlb_rsp = false;
+                r_icache_error_type = MMU_READ_PT1_ILLEGAL_ACCESS;    
+                r_icache_bad_vaddr = ireq.addr;
+                r_icache_fsm = ICACHE_ERROR;
+            } 
+            else 
+            {
+                r_icache_inval_tlb_rsp = false;
+                r_icache_fsm = ICACHE_IDLE;  
+            } 
+        }
+        break;
+    }
+    ///////////////////////
+    case ICACHE_TLB1_WRITE:  
+    {
+        m_cost_ins_tlb_miss_frz++;
+
+        // external cache invalidate request
+        if ( r_tgt_icache_req )
+        {
+            r_icache_fsm = ICACHE_CC_INVAL;
+            r_icache_fsm_save = r_icache_fsm;
+            m_cost_ins_waste_wait_frz++;
+            break;
+        }
+        // external tlb invalidate request
+        if ( r_dcache_itlb_inval_req )
+        {
+	    r_itlb_inval_req = true;
+            r_icache_fsm = ICACHE_TLB_CC_INVAL;
+            r_icache_fsm_save = r_icache_fsm;
+            m_cost_ins_waste_wait_frz++;
+            break;
+        }
+
+        if (!r_itlb_acc_dcache_req && !r_icache_inval_tlb_rsp ) // TLB access bits write response and no invalidation        
+        { 
+            if ( r_dcache_rsp_itlb_error ) 
+            {
+                r_icache_error_type = MMU_READ_PT1_ILLEGAL_ACCESS;  
+                r_icache_bad_vaddr = ireq.addr;
+                r_icache_fsm = ICACHE_ERROR;
+            } 
+            else  
+            {
+                r_icache_fsm = ICACHE_TLB1_UPDT;  
+            }
+        } 
+
+        if (!r_itlb_acc_dcache_req && r_icache_inval_tlb_rsp) // TLB ET write response and invalidation     
+        {   
+            if ( r_dcache_rsp_itlb_error ) 
+            {
+                r_icache_inval_tlb_rsp = false;
+                r_icache_error_type = MMU_READ_PT1_ILLEGAL_ACCESS;  
+                r_icache_bad_vaddr = ireq.addr;
+                r_icache_fsm = ICACHE_ERROR;
+            } 
+            else  
+            {
+                r_icache_inval_tlb_rsp = false;
+                r_icache_fsm = ICACHE_IDLE;    
+            }
+        }
+        break;
+    }
+    //////////////////////
+    case ICACHE_TLB1_UPDT:
+    {
+        m_cost_ins_tlb_miss_frz++;
+
+        // external cache invalidate request
+        if ( r_tgt_icache_req )
+        {
+            r_icache_fsm = ICACHE_CC_INVAL;
+            r_icache_fsm_save = r_icache_fsm;
+            m_cost_ins_waste_wait_frz++;
+            break;
+        }
+
+        // external tlb invalidate request
+        if ( r_dcache_itlb_inval_req ) 
+        {
+	    r_itlb_inval_req = true;
+            r_icache_fsm = ICACHE_TLB_CC_INVAL;
+            r_icache_fsm_save = r_icache_fsm;
+            m_cost_ins_waste_wait_frz++;
+            break;
+        }
+
+        // TLB update and invalidate different PTE
+        if ( !r_dcache_itlb_cleanup_req && !r_icache_inval_tlb_rsp )  
+        {
+            paddr_t victim_index = 0;
+            r_dcache_itlb_cleanup_req = icache_tlb.update(r_icache_pte_update,ireq.addr,(r_icache_paddr_save.read() >> (uint32_log2(m_dcache_words)+2)),&victim_index);
+            r_dcache_itlb_cleanup_line = victim_index;
+            r_icache_fsm = ICACHE_IDLE;
+        }
+
+        // TLB update and invalidate same PTE
+        if ( r_icache_inval_tlb_rsp )                                 
+        {
+            r_icache_inval_tlb_rsp = false;
+            r_icache_fsm = ICACHE_IDLE;
+        }
+        break;
+    }
+    /////////////////////
+    case ICACHE_TLB2_READ:
+    {
+        m_cost_ins_tlb_miss_frz++;
+
+        // external cache invalidate request
+        if ( r_tgt_icache_req )
+        {
+            r_icache_fsm = ICACHE_CC_INVAL;
+            r_icache_fsm_save = r_icache_fsm;
+            m_cost_ins_waste_wait_frz++;
+            break;
+        }
+
+        // external tlb invalidate request
+        if ( r_dcache_itlb_inval_req )
+        {
+	    r_itlb_inval_req = true;
+            r_icache_fsm = ICACHE_TLB_CC_INVAL;
+            r_icache_fsm_save = r_icache_fsm;
+            m_cost_ins_waste_wait_frz++;
+            break;
+        }
+
+        if ( !r_itlb_read_dcache_req && !r_icache_inval_tlb_rsp ) // TLB miss read response 
+        {
+            if ( !r_dcache_rsp_itlb_error ) // VCI response ok        
+            {
+		if ( !(r_dcache_rsp_itlb_miss >> PTE_V_SHIFT) ) // unmapped
+		{
+                    r_icache_error_type = MMU_READ_PT2_UNMAPPED;  
+                    r_icache_bad_vaddr  = ireq.addr;
+                    r_icache_fsm = ICACHE_ERROR;
+		}
+		else
+		{
+		    if ( (m_srcid_rw >> 4) == ((r_dcache_rsp_itlb_miss & ((1<<(m_paddr_nbits - PAGE_M_NBITS))-1)) >> (m_paddr_nbits - PAGE_M_NBITS -10)) ) // local
+		    {
+			if ( (r_dcache_rsp_itlb_miss & PTE_L_MASK ) >> PTE_L_SHIFT ) // L bit is set
+			{
+                    	    r_icache_fsm        = ICACHE_TLB2_UPDT;
+                    	    r_icache_pte_update = r_dcache_rsp_itlb_miss;
+			}
+			else
+			{
+                    	    r_icache_pte_update   = r_dcache_rsp_itlb_miss | PTE_L_MASK;
+                    	    r_itlb_acc_dcache_req = true;
+                    	    r_icache_fsm          = ICACHE_TLB2_WRITE;
+                     	    m_cpt_ins_tlb_write_et++;
+			}
+    	            }
+		    else // remotely
+		    {
+			if ( (r_dcache_rsp_itlb_miss & PTE_R_MASK ) >> PTE_R_SHIFT ) // R bit is set
+			{
+                    	    r_icache_fsm        = ICACHE_TLB2_UPDT;
+                    	    r_icache_pte_update = r_dcache_rsp_itlb_miss;
+			}
+			else
+			{
+                    	    r_icache_pte_update   = r_dcache_rsp_itlb_miss | PTE_R_MASK;
+                    	    r_itlb_acc_dcache_req = true;
+                    	    r_icache_fsm          = ICACHE_TLB2_WRITE;
+                    	    m_cpt_ins_tlb_write_et++;
+			}
+		    }
+		}
+            }
+            else                            // VCI response error        
+            {
+                r_icache_error_type = MMU_READ_PT2_ILLEGAL_ACCESS;
+                r_icache_bad_vaddr = ireq.addr;
+                r_icache_fsm = ICACHE_ERROR;
+            }
+        }
+
+        if ( !r_itlb_read_dcache_req && r_icache_inval_tlb_rsp ) // TLB miss read response and invalidation
+        {
+            if ( r_dcache_rsp_itlb_error ) 
+            {
+                r_icache_inval_tlb_rsp = false;
+                r_icache_error_type = MMU_READ_PT2_ILLEGAL_ACCESS;    
+                r_icache_bad_vaddr = ireq.addr;
+                r_icache_fsm = ICACHE_ERROR;
+            } 
+            else 
+            {
+                r_icache_inval_tlb_rsp = false;
+                r_icache_fsm = ICACHE_IDLE;  
+            } 
+        }
+        break;
+    }
+    /////////////////////////
+    case ICACHE_TLB2_WRITE:
+    {  
+        m_cost_ins_tlb_miss_frz++;
+
+        // external cache invalidate request
+        if ( r_tgt_icache_req )
+        {
+            r_icache_fsm = ICACHE_CC_INVAL;
+            r_icache_fsm_save = r_icache_fsm;
+            m_cost_ins_waste_wait_frz++;
+            break;
+        }
+        // external tlb invalidate request
+        if ( r_dcache_itlb_inval_req )
+        {
+	    r_itlb_inval_req = true;
+            r_icache_fsm = ICACHE_TLB_CC_INVAL;
+            r_icache_fsm_save = r_icache_fsm;
+            m_cost_ins_waste_wait_frz++;
+            break;
+        }
+
+        if (!r_itlb_acc_dcache_req && !r_icache_inval_tlb_rsp ) // TLB access bits write response          
+        {
+            if ( r_dcache_rsp_itlb_error )             
+            {
+                r_icache_error_type = MMU_READ_PT2_ILLEGAL_ACCESS;  
+                r_icache_bad_vaddr = ireq.addr;
+                r_icache_fsm = ICACHE_ERROR;
+            } 
+            else  
+            {
+                r_icache_fsm = ICACHE_TLB2_UPDT;  
+            }
+        } 
+        if (!r_itlb_acc_dcache_req && r_icache_inval_tlb_rsp) // TLB ET write response and invalidation     
+        {   
+            if ( r_dcache_rsp_itlb_error ) 
+            {
+                r_icache_inval_tlb_rsp = false;
+                r_icache_error_type = MMU_READ_PT2_ILLEGAL_ACCESS;  
+                r_icache_bad_vaddr = ireq.addr;
+                r_icache_fsm = ICACHE_ERROR;
+            } 
+            else  
+            {
+                r_icache_inval_tlb_rsp = false;
+                r_icache_fsm = ICACHE_IDLE;    
+            }
+        }
+        break;
+    }
+    /////////////////////
+    case ICACHE_TLB2_UPDT: 
+    {
+        m_cost_ins_tlb_miss_frz++;
+
+        // external cache invalidate request
+        if ( r_tgt_icache_req )
+        {
+            r_icache_fsm = ICACHE_CC_INVAL;
+            r_icache_fsm_save = r_icache_fsm;
+            m_cost_ins_waste_wait_frz++;
+            break;
+        }
+
+        // external tlb invalidate request
+        if ( r_dcache_itlb_inval_req ) 
+        {
+	    r_itlb_inval_req = true;
+            r_icache_fsm = ICACHE_TLB_CC_INVAL;
+            r_icache_fsm_save = r_icache_fsm;
+            m_cost_ins_waste_wait_frz++;
+            break;
+        }
+
+        // TLB update and invalidate different PTE
+        if ( !r_dcache_itlb_cleanup_req && !r_icache_inval_tlb_rsp ) 
+        {
+            paddr_t victim_index = 0;
+            r_dcache_itlb_cleanup_req = icache_tlb.update(r_icache_pte_update,r_dcache_rsp_itlb_ppn,ireq.addr,(r_icache_paddr_save.read() >> (uint32_log2(m_dcache_words)+2)),&victim_index);
+            r_dcache_itlb_cleanup_line = victim_index;
+            r_icache_fsm = ICACHE_IDLE;
+        }
+        // TLB update and invalidate same PTE
+        if ( r_icache_inval_tlb_rsp )                            
+        {
+            r_icache_inval_tlb_rsp = false;
+            r_icache_fsm = ICACHE_IDLE;
+        }
+        break;
+    }
+    /////////////////////////////
+    case ICACHE_SW_FLUSH:
+    {
+        size_t way = r_icache_way;
+        size_t set = r_icache_set;
+        bool clean = false;
+
+        if ( ireq.valid ) m_cost_ins_waste_wait_frz++;
+        m_cost_ins_tlb_sw_frz++;
+
+        // 4K page size TLB flush leads to cleanup req to data cache 
+        if ( !r_dcache_itlb_cleanup_req )    // last cleanup finish
+        {
+            paddr_t victim_index = 0;
+            for ( ; way < m_itlb_ways; way++)
+            {
+                for ( ; set < m_itlb_sets; set++)
+                {
+                    if(icache_tlb.checkcleanup(way, set, &victim_index))
+                    {
+                        clean = true;
+                        r_dcache_itlb_cleanup_req = true;
+                        r_dcache_itlb_cleanup_line = victim_index;
+                        r_icache_way = way + ((set+1)/m_itlb_sets);
+                        r_icache_set = (set+1) % m_itlb_sets;
+                        break;
+                    }
+                }
+                if (clean) break;
+            }
+
+            if ((way == m_itlb_ways) && (set == m_itlb_sets))
+            {
+                r_dcache_xtn_req = false;
+                r_icache_fsm = ICACHE_IDLE;
+                break;
+            }
+        }
+        break;
+    }
+    /////////////////////
+    case ICACHE_TLB_FLUSH:
+    {   
+        if ( ireq.valid ) m_cost_ins_waste_wait_frz++;
+
+        // data cache flush leads to ins tlb flush, flush all tlb entry 
+        icache_tlb.flush(true);    // global entries are invalidated
+        r_dcache_xtn_req = false;
+        r_icache_fsm = ICACHE_IDLE;
+        break;
+    }
+    ////////////////////////
+    case ICACHE_CACHE_FLUSH:
+    {
+        // external cache invalidate request
+        if ( r_tgt_icache_req )
+        {
+            r_tgt_icache_req = false;
+        }
+
+        size_t way = r_icache_way;
+        size_t set = r_icache_set;
+        bool clean = false;
+
+        m_cost_ins_cache_flush_frz++;
+        if ( ireq.valid ) m_cost_ins_waste_wait_frz++;
+
+        // cache flush and send cleanup to external
+        if ( !r_icache_cleanup_req )
+        {
+            paddr_t victim_index = 0;
+            for ( ; way < m_icache_ways; way++ )
+            {    
+                for ( ; set < m_icache_sets; set++ )
+                {    
+                    if ( r_icache.flush(way, set, &victim_index) )
+                    {
+                        clean = true;
+                        r_icache_cleanup_req = true;
+                        r_icache_cleanup_line = victim_index;
+                        r_icache_way = way + ((set+1)/m_icache_sets);
+                        r_icache_set = (set+1) % m_icache_sets;
+                        break;
+                    }
+                }
+                if (clean) break;
+            }
+            if ((way == m_icache_ways) && (set == m_icache_sets))
+            {
+                r_dcache_xtn_req = false;
+                r_icache_fsm = ICACHE_IDLE;
+                break;
+            }
+        }
+        break;
+    }
+    /////////////////////
+    case ICACHE_TLB_INVAL:  
+    {
+        if ( ireq.valid ) m_cost_ins_waste_wait_frz++;
+        paddr_t victim_index = 0;
+
+        if ( !r_dcache_itlb_cleanup_req )
+        {
+            r_dcache_itlb_cleanup_req = icache_tlb.inval(r_dcache_wdata_save, &victim_index);
+            r_dcache_itlb_cleanup_line = victim_index;
+            r_dcache_xtn_req = false;
+            r_icache_fsm = ICACHE_IDLE;
+        }
+        break;
+    }
+    ////////////////////////
+    case ICACHE_CACHE_INVAL:
+    {	
+        if ( ireq.valid ) m_cost_ins_waste_wait_frz++;
+
+        paddr_t ipaddr = 0;                     
+        bool    icache_hit_t = false;
+
+        if ( !r_icache_cleanup_req )
+        {    
+            if ( r_mmu_mode.read() & INS_TLB_MASK ) 
+            {
+                icache_hit_t = icache_tlb.translate(r_dcache_wdata_save, &ipaddr); 
+            } 
+            else 
+            {
+                ipaddr = (paddr_t)r_dcache_wdata_save;
+                icache_hit_t = true;
+            }
+            if ( icache_hit_t )
+            {
+                // invalidate and cleanup if necessary
+                r_icache_cleanup_req = r_icache.inval(ipaddr);
+                r_icache_cleanup_line = ipaddr >> (uint32_log2(m_icache_words) + 2);   
+            }
+            r_dcache_xtn_req = false; 
+            r_icache_fsm = ICACHE_IDLE;
+        }
+        break;
+    }
+    ///////////////////////
+    case ICACHE_MISS_WAIT:
+    {
+        m_cost_ins_miss_frz++;
+
+        // external cache invalidate request
+        if ( r_tgt_icache_req )     
+        {
+            r_icache_fsm = ICACHE_CC_INVAL;
+            r_icache_fsm_save = r_icache_fsm;
+            m_cost_ins_waste_wait_frz++;
+            break;
+        }
+
+        // external tlb invalidate request
+        if ( r_dcache_itlb_inval_req )
+        {
+	    r_itlb_inval_req = true;
+            r_icache_fsm = ICACHE_TLB_CC_INVAL;
+            r_icache_fsm_save = r_icache_fsm;
+            m_cost_ins_waste_wait_frz++;
+            break;
+        }
+       
+	if ( !r_icache_miss_req )
+	{
+	    if ( r_vci_rsp_ins_error ) 
+            {
+                r_icache_error_type = MMU_READ_DATA_ILLEGAL_ACCESS; 
+                r_icache_bad_vaddr = ireq.addr;
+                r_icache_fsm = ICACHE_ERROR;
+
+            	if ( r_icache_inval_tlb_rsp ) r_icache_inval_tlb_rsp = false;
+            	if ( r_icache_inval_rsp ) r_icache_inval_rsp = false;
+		break;
+            }
+
+            if ( r_icache_inval_tlb_rsp ) // Miss read response and tlb invalidation
+            {
+                r_icache_fsm = ICACHE_IDLE;
+                r_icache_inval_tlb_rsp = false;
+                m_cost_ins_tlb_miss_frz++;
+                break;
+            }
+	
+            if ( r_icache_inval_rsp ) // Miss read response and tlb invalidation
+            {
+                r_icache_fsm = ICACHE_IDLE;
+                r_icache_inval_rsp = false;
+                break;
+            }
+            r_icache_fsm = ICACHE_MISS_UPDT;  
+	}	
+        break;
+    }
+    ////////////////////
+    case ICACHE_UNC_WAIT:
+    {
+        m_cost_ins_miss_frz++;
+
+        // external cache invalidate request
+        if ( r_tgt_icache_req ) 
+        {
+            r_icache_fsm = ICACHE_CC_INVAL;
+            r_icache_fsm_save = r_icache_fsm;
+            m_cost_ins_waste_wait_frz++;
+            break;
+        }
+
+        // external tlb invalidate request
+        if ( r_dcache_itlb_inval_req )
+        {
+	    r_itlb_inval_req = true;
+            r_icache_fsm = ICACHE_TLB_CC_INVAL;
+            r_icache_fsm_save = r_icache_fsm;
+            m_cost_ins_waste_wait_frz++;
+            break;
+        }
+
+	if ( !r_icache_unc_req )
+	{
+	    if ( r_vci_rsp_ins_error ) 
+            {
+                r_icache_error_type = MMU_READ_DATA_ILLEGAL_ACCESS;    
+                r_icache_bad_vaddr = ireq.addr;
+                r_icache_fsm = ICACHE_ERROR;
+
+            	if ( r_icache_inval_tlb_rsp ) r_icache_inval_tlb_rsp = false;
+            	//if ( r_icache_inval_rsp ) r_icache_inval_rsp = false;
+		break;
+            }
+
+	    if ( r_icache_inval_tlb_rsp ) // Miss read response and tlb invalidation
+            {
+                r_icache_inval_tlb_rsp = false;
+                r_icache_fsm = ICACHE_IDLE;
+		break;
+            }
+/*	    
+	    if ( r_icache_inval_rsp ) // Miss read response and cache invalidation
+            {
+                r_icache_inval_rsp = false;
+                r_icache_fsm = ICACHE_IDLE;
+		break;
+            }
+*/
+	    // Miss read response and no invalidation
+            r_icache_buf_unc_valid = true;
+            r_icache_fsm = ICACHE_IDLE;
+	}	
+        break;
+    }
+    //////////////////////
+    case ICACHE_MISS_UPDT:
+    {
+        m_cost_ins_miss_frz++;
+
+        // external cache invalidate request
+        if ( r_tgt_icache_req )   
+        {
+            r_icache_fsm = ICACHE_CC_INVAL;
+            r_icache_fsm_save = r_icache_fsm;
+            m_cost_ins_waste_wait_frz++;
+            break;
+        }
+
+        // external tlb invalidate request
+        if ( r_dcache_itlb_inval_req )
+        {
+	    r_itlb_inval_req = true;
+            r_icache_fsm = ICACHE_TLB_CC_INVAL;
+            r_icache_fsm_save = r_icache_fsm;
+            m_cost_ins_waste_wait_frz++;
+            break;
+        }
+
+        if ( r_icache_inval_tlb_rsp ) // tlb invalidation
+        {
+            r_icache_inval_tlb_rsp = false;
+            r_icache_fsm = ICACHE_IDLE;
+            m_cost_ins_tlb_miss_frz++;
+            break;
+        }
+
+        if ( r_icache_inval_rsp ) // invalidation
+        {
+            r_icache_inval_rsp = false;
+            r_icache_fsm = ICACHE_IDLE;
+            break;
+        } 
+
+        if ( !r_icache_cleanup_req ) // Miss update and no invalidation
+        {
+            data_t* buf = r_icache_miss_buf;
+            paddr_t  victim_index = 0;
+            m_cpt_icache_dir_write++;
+            m_cpt_icache_data_write++;
+
+            r_icache_cleanup_req = r_icache.update(r_icache_paddr_save.read(), buf, &victim_index);
+            r_icache_cleanup_line = victim_index;            
+
+            r_icache_fsm = ICACHE_IDLE;
+        }
+        break;
+    }
+    ///////////////////
+    case ICACHE_ERROR:
+    {
+        r_vci_rsp_ins_error = false;
+        r_dcache_rsp_itlb_error = false;
+        irsp.valid = true;
+        irsp.error = true;
+        irsp.instruction = 0; 
+        r_icache_fsm = ICACHE_IDLE;
+        break;
+    }
+    /////////////////////
+    case ICACHE_CC_INVAL:  
+    {                       
+        if ( ireq.valid ) m_cost_ins_waste_wait_frz++;
+        m_cpt_icache_dir_read += m_icache_ways;
+
+        // invalidate cache
+        if( (( r_icache_fsm_save == ICACHE_MISS_WAIT ) || ( r_icache_fsm_save == ICACHE_MISS_UPDT ) /*|| 
+             ( r_icache_fsm_save == ICACHE_UNC_WAIT )*/ ) && 
+            ((r_icache_paddr_save.read() & ~((m_icache_words<<2)-1)) == (r_tgt_addr.read() & ~((m_icache_words<<2)-1))) ) 
+        {
+            r_icache_inval_rsp = true;
+        } 
+        else 
+        {
+            r_tgt_icache_rsp = r_icache.inval(r_tgt_addr.read());
+        }
+        r_tgt_icache_req = false;
+        r_icache_fsm = r_icache_fsm_save;
+        break;
+    }
+    /////////////////////////
+    case ICACHE_TLB_CC_INVAL:
+    {
+        if ( ireq.valid ) m_cost_ins_waste_wait_frz++;        
+
+	if ( r_itlb_inval_req ) break;
+
+        // invalidate cache
+        if( (( r_icache_fsm_save == ICACHE_TLB1_READ ) || ( r_icache_fsm_save == ICACHE_TLB2_READ )  ||
+             ( r_icache_fsm_save == ICACHE_TLB1_WRITE )|| ( r_icache_fsm_save == ICACHE_TLB2_WRITE ) ||
+             ( r_icache_fsm_save == ICACHE_TLB1_UPDT ) || ( r_icache_fsm_save == ICACHE_TLB2_UPDT )) && 
+            (((r_icache_paddr_save.read() & ~((m_icache_words<<2)-1)) >> (uint32_log2(m_icache_words) + 2) ) == r_dcache_itlb_inval_line.read()) ) 
+        {
+            r_icache_inval_tlb_rsp = true;
+        } 
+        else if (((r_icache_fsm_save == ICACHE_BIS)||(r_icache_fsm_save == ICACHE_MISS_WAIT) ||
+                 (r_icache_fsm_save == ICACHE_UNC_WAIT)||(r_icache_fsm_save == ICACHE_MISS_UPDT)) && 
+                (r_icache_tlb_nline == r_dcache_itlb_inval_line))
+        {
+            r_icache_inval_tlb_rsp = true;
+        }
+	r_dcache_itlb_inval_req = false;
+        r_icache_fsm = r_icache_fsm_save;
+        break;
+    }
+    } // end switch r_icache_fsm
+
+#ifdef SOCLIB_MODULE_DEBUG
+    std::cout << name() << " Instruction Response: " << irsp << std::endl;
+#endif
+
+    ////////////////////////////////////////////////////////////////////////////////////
+    //      INVAL ITLB CHECK FSM 
+    ////////////////////////////////////////////////////////////////////////////////////////
+    switch(r_inval_itlb_fsm) {
+    /////////////////////
+    case INVAL_ITLB_IDLE:
+    {
+        if ( r_itlb_inval_req )
+        {
+            r_ccinval_itlb_way = 0; 
+            r_ccinval_itlb_set = 0;
+            r_inval_itlb_fsm = INVAL_ITLB_CHECK;   
+            m_cost_ins_tlb_inval_frz++; 
+        }   
+        break;
+    }
+    ////////////////////////////
+    case INVAL_ITLB_CHECK:
+    {
+        m_cost_ins_tlb_inval_frz++; 
+
+        size_t way = r_ccinval_itlb_way; 
+        size_t set = r_ccinval_itlb_set;
+        bool end = false;        
+        bool tlb_hit = icache_tlb.cccheck(r_dcache_itlb_inval_line.read(), way, set, &way, &set, &end); 
+    
+        if ( tlb_hit )
+        {
+            r_ccinval_itlb_way = way; 
+            r_ccinval_itlb_set = set;
+            r_itlb_cc_check_end = end;
+            r_inval_itlb_fsm = INVAL_ITLB_INVAL; 
+            m_cpt_ins_tlb_inval++;   
+        }        
+        else
+        {
+            r_inval_itlb_fsm = INVAL_ITLB_CLEAR;    
+        }
+        break;
+    }
+    /////////////////////////
+    case INVAL_ITLB_INVAL:
+    {
+        m_cost_ins_tlb_inval_frz++;
+ 
+        icache_tlb.ccinval(r_ccinval_itlb_way, r_ccinval_itlb_set);
+
+        if ( !r_itlb_cc_check_end )
+        {
+            r_inval_itlb_fsm = INVAL_ITLB_CHECK; 
+        }
+        else
+        {
+            r_inval_itlb_fsm = INVAL_ITLB_CLEAR;    
+        }
+        break;
+    }
+    ////////////////////
+    case INVAL_ITLB_CLEAR:
+    {
+        r_itlb_inval_req = false;
+        r_itlb_cc_check_end = false;
+        r_ccinval_itlb_way = 0; 
+        r_ccinval_itlb_set = 0; 
+        r_inval_itlb_fsm = INVAL_ITLB_IDLE;    
+        m_cost_ins_tlb_inval_frz++; 
+        break;
+    }
+    } // end switch r_inval_itlb_fsm
+
+    ////////////////////////////////////////////////////////////////////////////////////
+    //      DCACHE FSM 
+    //
+    // Both the Cacheability Table, and the MMU cached bit are used to define
+    // the cacheability.
+    // 
+    // There is 14 mutually exclusive conditions to exit the IDLE state.
+    // Seven configurations corresponding to an XTN request from processor:
+    // - Context switch => CTXT_SWITCH state
+    // - Flush dcache => DCACHE_FLUSH state 
+    // - Flush icache => ICACHE_FLUSH state 
+    // - Invalidate a dtlb entry => DTLB_INVAL state
+    // - Invalidate a itlb entry => ITLB_INVAL state
+    // - Invalidate a dcache line => DCACHE_INVAL state
+    // - Invalidate a icache line => ICACHE_INVAL state
+    // Seven configurations corresponding to various read miss or write requests: 
+    // - TLB miss(in case hit_p miss) => TLB1_READ state
+    // - TLB miss(in case hit_p hit) => TLB2_READ state
+    // - Hit in TLB but VPN changed => BIS state
+    // - Cached read miss => MISS_REQ state
+    // - Uncache read miss => UNC_REQ state
+    // - Write hit => WRITE_UPDT state
+    // - Write miss => WRITE_REQ
+    //
+    // The r_vci_rsp_data_error flip-flop is set by the VCI_RSP controller and reset 
+    // by DCACHE-FSM when its state is in DCACHE_ERROR. 
+    //--------------------------------------------------------------------- 
+    // Data TLB: 
+    //  
+    // - int        ET          (00: unmapped; 01: unused or PTD)
+    //                          (10: PTE new;  11: PTE old      )
+    // - bool       cachable    (cached bit)
+    // - bool       writable    (writable bit) 
+    // - bool       executable  (** not used alwayse false)
+    // - bool       user        (access in user mode allowed)
+    // - bool       global      (PTE not invalidated by a TLB flush)
+    // - bool       dirty       (page has been modified) 
+    // - uint32_t   vpn         (virtual page number)
+    // - uint32_t   ppn         (physical page number)
+    ////////////////////////////////////////////////////////////////////////////////////////
+
+    switch (r_dcache_fsm) {
+    //////////////////////
+    case DCACHE_WRITE_REQ:
+    {
+        // external cache invalidate request
+        if ( r_tgt_dcache_req ) 
+        {
+            r_dcache_fsm = DCACHE_CC_CHECK;
+            r_dcache_fsm_save = r_dcache_fsm;
+            if ( dreq.valid ) m_cost_data_waste_wait_frz++; 
+            break;
+        }
+
+        // try to post the write request in the write buffer
+        if ( !r_dcache_write_req )     // no previous write transaction     
+        {
+            if ( r_wbuf.wok(r_dcache_paddr_save) )   // write request in the same cache line 
+            {    
+                r_wbuf.write(r_dcache_paddr_save.read(), r_dcache_be_save.read(), r_dcache_wdata_save);
+                // closing the write packet if uncached
+                if ( !r_dcache_cached_save )
+                { 
+                    r_dcache_write_req = true;
+                }
+            } 
+            else 
+            {    // close the write packet if write request not in the same cache line
+                r_dcache_write_req = true;
+                m_cost_write_frz++;
+                break;  //  posting not possible : stay in DCACHE_WRITEREQ state
+            }
+        } 
+        else     //  previous write transaction not completed
+        {
+            m_cost_write_frz++;
+            break;  //  posting not possible : stay in DCACHE_WRITEREQ state
+        }
+
+        // close the write packet if the next processor request is not a write 
+        if ( !dreq.valid || (dreq.type != iss_t::DATA_WRITE)) 
+        {
+            r_dcache_write_req = true;
+        }
+        
+        // The next state and the processor request parameters are computed 
+        // as in the DCACHE_IDLE state (see below ...)
+    }
+    /////////////////
+    case DCACHE_IDLE:
+    {
+        // external cache invalidate request
+        if ( r_tgt_dcache_req )   
+        {
+            r_dcache_fsm = DCACHE_CC_CHECK;
+            r_dcache_fsm_save = DCACHE_IDLE;
+            if ( dreq.valid ) m_cost_data_waste_wait_frz++;
+            break;
+        }        
+
+        // ins tlb cleanup
+        if ( r_dcache_itlb_cleanup_req )
+        {
+            r_dcache_fsm = DCACHE_ITLB_CLEANUP;
+            m_cpt_ins_tlb_cleanup++;
+            if ( dreq.valid ) m_cost_data_waste_wait_frz++;
+            break;
+        }    
+        // ins tlb miss
+    	if ( r_itlb_read_dcache_req )
+    	{
+            data_t rsp_itlb_miss;
+	    data_t rsp_itlb_ppn;
+
+    	    bool itlb_hit_dcache = r_dcache.read(r_icache_paddr_save, &rsp_itlb_miss);
+	    if ( (r_icache_fsm == ICACHE_TLB2_READ) && itlb_hit_dcache )
+	    {	
+	        bool itlb_hit_ppn = r_dcache.read(r_icache_paddr_save.read()+4, &rsp_itlb_ppn);
+		assert(itlb_hit_ppn && "Address of pte[64-32] and pte[31-0] should be successive");
+	    }
+
+            m_cpt_dcache_data_read += m_dcache_ways;
+            m_cpt_dcache_dir_read += m_dcache_ways;
+
+    	    if ( itlb_hit_dcache )  // ins TLB request hits in data cache 
+    	    {
+                r_dcache_rsp_itlb_miss = rsp_itlb_miss; 
+                r_dcache_rsp_itlb_ppn = rsp_itlb_ppn; 
+    	    	r_itlb_read_dcache_req = false;
+                r_dcache_fsm = DCACHE_IDLE;
+                
+                // set TLB bit if it's a PTE
+                if ( !((rsp_itlb_miss & PTE_T_MASK ) >> PTE_T_SHIFT) )
+                {
+                    r_dcache.setinbit(r_icache_paddr_save, r_dcache_in_itlb, true);
+                }
+    	    }
+    	    else                    // ins TLB request miss in data cache
+    	    {
+                r_dcache_itlb_read_req = true;
+                r_dcache_fsm = DCACHE_ITLB_READ;
+            }
+            if ( dreq.valid ) m_cost_data_waste_wait_frz++; 
+    	}
+    	else if ( r_itlb_acc_dcache_req ) // ins tlb write access bit
+    	{
+            bool write_hit = r_dcache.write(r_icache_paddr_save, r_icache_pte_update);
+            assert(write_hit && "Write on miss ignores data");
+            r_dcache_itlb_ll_acc_req = true;
+	    r_dcache_fsm = DCACHE_ITLB_LL_WAIT;	    		
+            if ( dreq.valid ) m_cost_data_waste_wait_frz++; 
+    	}
+        else if (dreq.valid) 
+        {
+            pte_info_t  dcache_pte_info;
+            int         xtn_opcod        = (int)dreq.addr/4;
+            paddr_t     tlb_dpaddr       = 0;        // physical address obtained from TLB
+            paddr_t     spc_dpaddr       = 0;        // physical adress obtained from PPN_save (speculative)
+            bool        dcache_hit_t     = false;    // hit on 4Kilo TLB
+            bool        dcache_hit_x     = false;    // VPN unmodified (can use spc_dpaddr)
+            bool        dcache_hit_p     = false;    // PTP unmodified (can skip first level page table walk)
+            bool        dcache_hit_c     = false;    // Cache hit
+            bool        dcache_cached    = false;    // cacheable access (read or write)
+            size_t      dcache_tlb_way   = 0;        // selected way (in case of cache hit)
+            size_t      dcache_tlb_set   = 0;        // selected set (Y field in address)
+            data_t      dcache_rdata     = 0;        // read data
+            paddr_t     dcache_tlb_nline = 0;       // TLB NLINE 
+	    bool 	write_hit	 = false;
+
+            m_cpt_dcache_data_read += m_dcache_ways;
+            m_cpt_dcache_dir_read += m_dcache_ways;
+
+            // Decoding READ XTN requests from processor
+            // They are executed in this DCACHE_IDLE state
+
+            if (dreq.type == iss_t::XTN_READ) 
+            {
+                switch(xtn_opcod) {
+                case iss_t::XTN_INS_ERROR_TYPE:
+                    drsp.rdata = (uint32_t)r_icache_error_type;
+                    r_icache_error_type = MMU_NONE;
+                    drsp.valid = true;
+                    drsp.error = false;
+                    break;
+                case iss_t::XTN_DATA_ERROR_TYPE:
+                    drsp.rdata = (uint32_t)r_dcache_error_type;
+                    r_dcache_error_type = MMU_NONE;
+                    drsp.valid = true;
+                    drsp.error = false;
+                    break;
+                case iss_t::XTN_INS_BAD_VADDR:
+                    drsp.rdata = (uint32_t)r_icache_bad_vaddr;       
+                    drsp.valid = true;
+                    drsp.error = false;
+                    break;
+                case iss_t::XTN_DATA_BAD_VADDR:
+                    drsp.rdata = (uint32_t)r_dcache_bad_vaddr;        
+                    drsp.valid = true;
+                    drsp.error = false;
+                    break;
+                case iss_t::XTN_PTPR:
+                    drsp.rdata = (uint32_t)r_mmu_ptpr;
+                    drsp.valid = true;
+                    drsp.error = false;
+                    break;
+                case iss_t::XTN_TLB_MODE:
+                    drsp.rdata = (uint32_t)r_mmu_mode;
+                    drsp.valid = true;
+                    drsp.error = false;
+                    break;
+                default:
+                    r_dcache_error_type = MMU_READ_UNDEFINED_XTN; 
+                    r_dcache_bad_vaddr  = dreq.addr;
+                    drsp.valid = true;
+                    drsp.error = true;
+                    break;
+                }
+                r_dcache_fsm = DCACHE_IDLE;
+                break;
+            }
+
+            // Decoding WRITE XTN requests from processor
+            // If there is no privilege violation, they are not executed in this DCACHE_IDLE state,
+            // but in the next state, because they generally require access to the caches or the TLBs 
+
+            if (dreq.type == iss_t::XTN_WRITE) 
+            {
+                drsp.valid = false;
+                drsp.error = false;
+                drsp.rdata = 0;
+                r_dcache_wdata_save = dreq.wdata;   
+                switch(xtn_opcod) {     
+
+                case iss_t::XTN_PTPR:       // context switch : checking the kernel mode
+                                            // both instruction & data TLBs must be flushed
+                    if ((dreq.mode == iss_t::MODE_HYPER) || (dreq.mode == iss_t::MODE_KERNEL)) 
+                    {
+                        r_mmu_ptpr = dreq.wdata;
+                        r_icache_error_type = MMU_NONE;
+                        r_dcache_error_type = MMU_NONE;
+                        r_dcache_type_save = dreq.addr/4; 
+                        r_dcache_xtn_req = true;
+                        r_dcache_fsm = DCACHE_CTXT_SWITCH;
+                    } 
+                    else 
+                    { 
+                        r_dcache_error_type = MMU_WRITE_PRIVILEGE_VIOLATION; 
+                        r_dcache_bad_vaddr  = dreq.addr;
+                        drsp.valid = true;
+                        drsp.error = true;
+                	r_dcache_fsm = DCACHE_IDLE;
+                    }
+                    break;
+
+                case iss_t::XTN_TLB_MODE:     // modifying TLBs mode : checking the kernel mode
+                    if ((dreq.mode == iss_t::MODE_HYPER) || (dreq.mode == iss_t::MODE_KERNEL)) 
+                    {
+                        r_mmu_mode = (int)dreq.wdata;
+                        drsp.valid = true;
+                    } 
+                    else 
+                    {
+                        r_dcache_error_type = MMU_WRITE_PRIVILEGE_VIOLATION; 
+                        r_dcache_bad_vaddr  = dreq.addr;
+                        drsp.valid = true;
+                        drsp.error = true;
+                    }
+                    r_dcache_fsm = DCACHE_IDLE;
+                    break;
+
+                case iss_t::XTN_DTLB_INVAL:     //  checking the kernel mode
+                    if ((dreq.mode == iss_t::MODE_HYPER) || (dreq.mode == iss_t::MODE_KERNEL)) 
+                    {
+                        r_dcache_fsm = DCACHE_DTLB_INVAL;  
+                    } 
+                    else 
+                    {
+                        r_dcache_error_type = MMU_WRITE_PRIVILEGE_VIOLATION; 
+                        r_dcache_bad_vaddr  = dreq.addr;
+                        drsp.valid = true;
+                        drsp.error = true;
+                	r_dcache_fsm = DCACHE_IDLE;
+                    }
+                    break;
+
+                case iss_t::XTN_ITLB_INVAL:     //  checking the kernel mode
+                    if ((dreq.mode == iss_t::MODE_HYPER) || (dreq.mode == iss_t::MODE_KERNEL)) 
+                    {
+                        r_dcache_xtn_req = true;
+                        r_dcache_type_save = dreq.addr/4;
+                        r_dcache_fsm = DCACHE_ITLB_INVAL;  
+                    } 
+                    else 
+                    {
+                        r_dcache_error_type = MMU_WRITE_PRIVILEGE_VIOLATION; 
+                        r_dcache_bad_vaddr  = dreq.addr;
+                        drsp.valid = true;
+                        drsp.error = true;
+                	r_dcache_fsm = DCACHE_IDLE;
+                    }
+                    break;
+
+                case iss_t::XTN_DCACHE_INVAL:   // cache inval can be executed in user mode.
+                    r_dcache_fsm = DCACHE_DCACHE_INVAL;
+                    break;
+
+                case iss_t::XTN_DCACHE_FLUSH:   // cache flush can be executed in user mode.
+                    r_dcache_type_save = dreq.addr/4; 
+                    r_dcache_xtn_req = true;
+                    r_dcache_way = 0;
+                    r_dcache_set = 0;
+                    r_dcache_fsm = DCACHE_DCACHE_FLUSH; 
+                    break;
+
+                case iss_t::XTN_ICACHE_INVAL:   // cache inval can be executed in user mode.
+                    r_dcache_type_save = dreq.addr/4; 
+                    r_dcache_xtn_req = true;
+                    r_dcache_fsm = DCACHE_ICACHE_INVAL; 
+                    break;
+
+                case iss_t::XTN_ICACHE_FLUSH:   // cache flush can be executed in user mode.
+                    r_dcache_type_save = dreq.addr/4; 
+                    r_dcache_xtn_req = true; 
+                    r_dcache_fsm = DCACHE_ICACHE_FLUSH;
+                    break;
+
+                case iss_t::XTN_SYNC:           // cache synchronization can be executed in user mode.
+                    if (r_wbuf.rok())
+                    {
+                        r_dcache_fsm = DCACHE_DCACHE_SYNC; 
+                    }
+                    else
+                    {
+                        drsp.valid = true;
+                        r_dcache_fsm = DCACHE_IDLE;
+                    }
+		    break;
+
+                default:
+                    r_dcache_error_type = MMU_WRITE_UNDEFINED_XTN; 
+                    r_dcache_bad_vaddr  = dreq.addr;
+                    drsp.valid = true;
+                    drsp.error = true;
+                    r_dcache_fsm = DCACHE_IDLE;
+                    break;
+                } // end switch xtn_opcod
+
+                break;
+            } // end if XTN_WRITE
+
+            // Evaluating dcache_hit_t, dcache_hit_x, dcache_hit_p, dcache_hit_c,
+            // dcache_pte_info, dcache_tlb_way, dcache_tlb_set & dpaddr & cacheability 
+            // - If MMU activated : cacheability is defined by the cachable bit in the TLB
+            // - If MMU not activated : cacheability is defined by the segment table.
+
+            if ( !(r_mmu_mode.read() & DATA_TLB_MASK) ) // MMU not activated
+            {
+                dcache_hit_t  = true;       
+                dcache_hit_x  = true;   
+                dcache_hit_p  = true;  
+                tlb_dpaddr    = dreq.addr; 
+                spc_dpaddr    = dreq.addr;    
+                dcache_cached = m_cacheability_table[dreq.addr] && 
+                                ((dreq.type != iss_t::DATA_LL)  && (dreq.type != iss_t::DATA_SC) &&
+                                 (dreq.type != iss_t::XTN_READ) && (dreq.type != iss_t::XTN_WRITE));     
+            } 
+            else                                                            // MMU activated
+            {
+                m_cpt_data_tlb_read++;
+                dcache_hit_t  = dcache_tlb.cctranslate(dreq.addr, &tlb_dpaddr, &dcache_pte_info, 
+                                                       &dcache_tlb_nline, &dcache_tlb_way, &dcache_tlb_set);                  
+                dcache_hit_x  = (((vaddr_t)r_dcache_vpn_save << PAGE_K_NBITS) == (dreq.addr & ~PAGE_K_MASK)) && r_dtlb_translation_valid; 
+                dcache_hit_p  = (((dreq.addr >> PAGE_M_NBITS) == r_dcache_id1_save) && r_dcache_ptba_ok );
+                spc_dpaddr    = ((paddr_t)r_dcache_ppn_save << PAGE_K_NBITS) | (paddr_t)((dreq.addr & PAGE_K_MASK));
+                dcache_cached = dcache_pte_info.c && 
+                                ((dreq.type != iss_t::DATA_LL)  && (dreq.type != iss_t::DATA_SC) &&
+                                 (dreq.type != iss_t::XTN_READ) && (dreq.type != iss_t::XTN_WRITE));    
+            }
+
+            if ( !(r_mmu_mode.read() & DATA_CACHE_MASK) )   // cache not actived
+            {
+                dcache_cached = false;
+            }
+
+            // dcache_hit_c & dcache_rdata
+            if ( dcache_cached )    // using speculative physical address for cached access
+            {
+                dcache_hit_c = r_dcache.read(spc_dpaddr, &dcache_rdata);
+            } 
+            else                    // using actual physical address for uncached access
+            {
+                dcache_hit_c = ((tlb_dpaddr == (paddr_t)r_dcache_paddr_save) && r_dcache_buf_unc_valid ); 
+                dcache_rdata = r_dcache_miss_buf[0];
+            }
+
+            if ( r_mmu_mode.read() & DATA_TLB_MASK ) 
+            {
+                // Checking access rights
+                if ( dcache_hit_t ) 
+                {
+                    if (!dcache_pte_info.u && (dreq.mode == iss_t::MODE_USER)) 
+                    {
+                        if ((dreq.type == iss_t::DATA_READ)||(dreq.type == iss_t::DATA_LL))
+                        {
+                            r_dcache_error_type = MMU_READ_PRIVILEGE_VIOLATION;
+                        }
+                        else /*if ((dreq.type == iss_t::DATA_WRITE)||(dreq.type == iss_t::DATA_SC))*/
+                        {
+                            r_dcache_error_type = MMU_WRITE_PRIVILEGE_VIOLATION;
+                        }  
+                        r_dcache_bad_vaddr = dreq.addr;
+                        drsp.valid = true;
+                        drsp.error = true;
+                        drsp.rdata = 0;
+                        r_dcache_fsm = DCACHE_IDLE;
+                        break;
+                    }
+                    if (!dcache_pte_info.w && ((dreq.type == iss_t::DATA_WRITE)||(dreq.type == iss_t::DATA_SC))) 
+                    {
+                        r_dcache_error_type = MMU_WRITE_ACCES_VIOLATION;  
+                        r_dcache_bad_vaddr = dreq.addr;
+                        drsp.valid = true;
+                        drsp.error = true;
+                        drsp.rdata = 0;
+                        r_dcache_fsm = DCACHE_IDLE;
+                        break;
+                    }
+                }
+
+                // update LRU, save ppn, vpn and page type
+                if ( dcache_hit_t ) {
+                    dcache_tlb.setlru(dcache_tlb_way,dcache_tlb_set); 
+                    r_dcache_ppn_save = tlb_dpaddr >> PAGE_K_NBITS;
+                    r_dcache_vpn_save = dreq.addr >> PAGE_K_NBITS;
+                    r_dcache_tlb_nline = dcache_tlb_nline;
+                    r_dtlb_translation_valid = true;
+                }
+                else
+                {
+                    r_dtlb_translation_valid = false;
+                }
+
+            } // end if MMU activated
+
+            // compute next state 
+            if ( !dcache_hit_p && !dcache_hit_t )  // TLB miss
+            {
+                r_dcache_tlb_paddr = (paddr_t)r_mmu_ptpr << (INDEX1_NBITS+2) | (paddr_t)((dreq.addr>>PAGE_M_NBITS)<<2);
+                r_dcache_fsm = DCACHE_DTLB1_READ_CACHE;
+                m_cpt_data_tlb_miss++;
+                m_cost_data_tlb_miss_frz++;
+            }
+            else if ( dcache_hit_p && !dcache_hit_t )  // TLB Miss with possibility of bypass first level page
+            {
+                // walk page table level 2
+                r_dcache_tlb_paddr = (paddr_t)r_dcache_ptba_save | 
+                                     (paddr_t)(((dreq.addr&PTD_ID2_MASK)>>PAGE_K_NBITS) << 3); 
+                r_dcache_fsm = DCACHE_DTLB2_READ_CACHE;
+                m_cpt_data_tlb_miss++;
+                m_cost_data_tlb_miss_frz++;
+            }
+            else if ( dcache_hit_t && !dcache_hit_x && dcache_cached )// cached access with an ucorrect speculative physical address
+            {
+                r_dcache_hit_p_save = dcache_hit_p;
+                r_dcache_fsm = DCACHE_BIS;
+                m_cost_data_miss_frz++;
+            }
+            else  // cached or uncached access with a correct speculative physical address
+            {
+                switch( dreq.type ) {
+                    case iss_t::DATA_READ:
+                    case iss_t::DATA_LL:
+                    case iss_t::DATA_SC:
+                        m_cpt_read++;
+                        if ( dcache_hit_c ) 
+                        {
+                            r_dcache_buf_unc_valid = false;
+                            r_dcache_fsm = DCACHE_IDLE;
+                            drsp.valid = true;
+                            drsp.rdata = dcache_rdata;
+                        } 
+                        else 
+                        {
+                            if ( dcache_cached ) 
+                            {
+                                r_dcache_miss_req = true;
+                                r_dcache_fsm = DCACHE_MISS_WAIT;
+                                m_cpt_data_miss++;
+                                m_cost_data_miss_frz++;
+                            } 
+                            else 
+                            {
+                                r_dcache_unc_req = true;
+                                r_dcache_fsm = DCACHE_UNC_WAIT;
+                                m_cpt_unc_read++;
+                                m_cost_unc_read_frz++;
+                            }
+                        }
+                        break;
+/*
+                    case iss_t::DATA_READ:
+                        m_cpt_read++;
+                        if ( dcache_hit_c ) 
+                        {
+                            r_dcache_buf_unc_valid = false;
+                            r_dcache_fsm = DCACHE_IDLE;
+                            drsp.valid = true;
+                            drsp.rdata = dcache_rdata;
+                        } 
+                        else 
+                        {
+                            if ( dcache_cached ) 
+                            {
+                                r_dcache_miss_req = true;
+                                r_dcache_fsm = DCACHE_MISS_WAIT;
+                                m_cpt_data_miss++;
+                                m_cost_data_miss_frz++;
+                            } 
+                            else 
+                            {
+                                r_dcache_unc_req = true;
+                                r_dcache_fsm = DCACHE_UNC_WAIT;
+                                m_cpt_unc_read++;
+                                m_cost_unc_read_frz++;
+                            }
+                        }
+                        break;
+                    case iss_t::DATA_LL:
+			if (r_dcache_llsc_reserved && (r_dcache_llsc_addr_save == tlb_dpaddr) && r_dcache_buf_unc_valid)
+			{
+                            r_dcache_buf_unc_valid = false;
+                            r_dcache_fsm = DCACHE_IDLE;
+                            drsp.valid = true;
+                            drsp.rdata = dcache_rdata;
+			}
+			else
+			{
+			    r_dcache_llsc_reserved = true;
+			    r_dcache_llsc_addr_save = tlb_dpaddr;
+                            r_dcache_unc_req = true;
+                            r_dcache_fsm = DCACHE_UNC_WAIT;
+			}
+			break;
+                    case iss_t::DATA_SC:
+			if (r_dcache_llsc_reserved && (r_dcache_llsc_addr_save == tlb_dpaddr))
+			{
+			    r_dcache_llsc_reserved = false;
+                            r_dcache_unc_req = true;
+                            r_dcache_fsm = DCACHE_UNC_WAIT;
+			}
+			else
+			{   
+			    if ( r_dcache_buf_unc_valid )
+			    {                         
+			        r_dcache_llsc_reserved = false;
+			        r_dcache_buf_unc_valid = false;
+                                drsp.valid = true;
+                                drsp.rdata = dcache_rdata;
+			    }
+                            r_dcache_fsm = DCACHE_IDLE;
+			}			
+			break;
+*/
+                    case iss_t::DATA_WRITE:
+                        m_cpt_write++;
+                        if ( dcache_cached ) m_cpt_write_cached++;
+
+                        if ( dcache_hit_c && dcache_cached )    // cache update required
+                        {
+                            r_dcache_fsm = DCACHE_WRITE_UPDT;
+                        } 
+                        else if ( !dcache_pte_info.d && (r_mmu_mode.read() & DATA_TLB_MASK) )   // dirty bit update required
+                        {
+                            if ( dcache_tlb.getpagesize(dcache_tlb_way, dcache_tlb_set) )	// 2M page size, one level page table 
+                            {
+                                r_dcache_pte_update = dcache_tlb.getpte(dcache_tlb_way, dcache_tlb_set) | PTE_D_MASK;
+                                r_dcache_tlb_paddr = (paddr_t)r_mmu_ptpr << (INDEX1_NBITS+2) | (paddr_t)((dreq.addr>>PAGE_M_NBITS)<<2);
+                                write_hit = r_dcache.write((paddr_t)r_mmu_ptpr << (INDEX1_NBITS+2) | (paddr_t)((dreq.addr>>PAGE_M_NBITS)<<2), 
+                                                           (dcache_tlb.getpte(dcache_tlb_way, dcache_tlb_set) | PTE_D_MASK));
+                                assert(write_hit && "Write on miss ignores data");
+                                r_dcache_tlb_ll_dirty_req = true;
+                                r_dcache_fsm = DCACHE_LL_DIRTY_WAIT;
+                                m_cpt_data_tlb_write_dirty++;
+                            }
+                            else	// 4k page size, two levels page table 
+                            {   
+                                if (dcache_hit_p) 
+                                {
+                                    r_dcache_pte_update = dcache_tlb.getpte(dcache_tlb_way, dcache_tlb_set) | PTE_D_MASK;
+                                    r_dcache_tlb_paddr = (paddr_t)r_dcache_ptba_save | (paddr_t)(((dreq.addr&PTD_ID2_MASK)>>PAGE_K_NBITS) << 3);
+                                    write_hit = r_dcache.write(((paddr_t)r_dcache_ptba_save | (paddr_t)(((dreq.addr&PTD_ID2_MASK)>>PAGE_K_NBITS) << 3)), 
+                                                       (dcache_tlb.getpte(dcache_tlb_way, dcache_tlb_set) | PTE_D_MASK));
+                                    assert(write_hit && "Write on miss ignores data");
+                                    r_dcache_tlb_ll_dirty_req = true;
+                                    r_dcache_fsm = DCACHE_LL_DIRTY_WAIT;
+                                    m_cpt_data_tlb_write_dirty++;
+                                }
+                                else    // get PTBA to calculate the physical address of PTE
+                                {
+                                    r_dcache_pte_update = dcache_tlb.getpte(dcache_tlb_way, dcache_tlb_set) | PTE_D_MASK;
+                                    r_dcache_tlb_paddr = (paddr_t)r_mmu_ptpr << (INDEX1_NBITS+2) | (paddr_t)((dreq.addr>>PAGE_M_NBITS)<<2);
+                                    r_dcache_tlb_ptba_read = true;
+                                    r_dcache_fsm = DCACHE_DTLB1_READ_CACHE;
+                                }
+                            }
+                            m_cost_data_tlb_miss_frz++;
+                        }
+                        else                                    // no cache update, not dirty bit update
+                        {
+                            r_dcache_fsm = DCACHE_WRITE_REQ;
+                            drsp.valid = true;
+                            drsp.rdata = 0;
+                        }
+                        break;
+                    default:
+                        break;
+                } // end switch dreq.type
+            } // end if next states
+
+            // save values for the next states
+            r_dcache_paddr_save   = tlb_dpaddr;
+            r_dcache_type_save    = dreq.type;
+            r_dcache_wdata_save   = dreq.wdata;
+            r_dcache_be_save      = dreq.be;
+            r_dcache_rdata_save   = dcache_rdata;
+            r_dcache_cached_save  = dcache_cached;
+            r_dcache_dirty_save   = dcache_pte_info.d;
+            r_dcache_tlb_set_save = dcache_tlb_set;
+            r_dcache_tlb_way_save = dcache_tlb_way;
+
+        } // end if dreq.valid
+        else 
+        {   
+            r_dcache_fsm = DCACHE_IDLE;
+        }
+
+        // processor request are not accepted in the WRITE_REQ state 
+        // when the write buffer is not writeable
+
+        if ((r_dcache_fsm == DCACHE_WRITE_REQ) && 
+            (r_dcache_write_req || !r_wbuf.wok(r_dcache_paddr_save))) 
+        {
+            drsp.valid = false;
+        }
+        break;
+    }
+    /////////////////
+    case DCACHE_BIS:
+    {
+        // external cache invalidate request
+        if ( r_tgt_dcache_req )   
+        {
+            r_dcache_fsm = DCACHE_CC_CHECK;
+            r_dcache_fsm_save = r_dcache_fsm;
+            m_cost_data_waste_wait_frz++;
+            break;
+        }
+
+        // Using tlb entry is invalidated 
+        if ( r_dcache_inval_tlb_rsp )
+        {
+            r_dcache_inval_tlb_rsp = false;
+            r_dcache_fsm = DCACHE_IDLE;
+            m_cost_data_tlb_miss_frz++;
+            break;
+        }
+
+        bool    dcache_hit   = false;
+        bool    write_hit    = false;
+        data_t  dcache_rdata = 0;
+
+        // acces always cached in this state
+        dcache_hit = r_dcache.read(r_dcache_paddr_save, &dcache_rdata);
+
+        if ( dreq.type == iss_t::DATA_READ )  // cached read
+        {
+            m_cpt_read++;
+            if ( !dcache_hit ) 
+            {
+                r_dcache_miss_req = true;
+                r_dcache_fsm = DCACHE_MISS_WAIT;
+                m_cpt_data_miss++;
+                m_cost_data_miss_frz++;
+            }
+            else
+            {
+                r_dcache_fsm = DCACHE_IDLE;
+            }
+            drsp.valid = dcache_hit;
+            drsp.error = false;
+            drsp.rdata = dcache_rdata;
+        }
+        else    // cached write
+        {
+            m_cpt_write++;
+            m_cpt_write_cached++;
+            if ( dcache_hit )    // cache update required
+            {
+            	r_dcache_rdata_save = dcache_rdata;
+                r_dcache_fsm = DCACHE_WRITE_UPDT;
+            } 
+            else if (!r_dcache_dirty_save && (r_mmu_mode.read() & DATA_TLB_MASK))   // dirty bit update required
+            {
+                if (dcache_tlb.getpagesize(r_dcache_tlb_way_save, r_dcache_tlb_set_save)) 
+                {
+                    r_dcache_pte_update = dcache_tlb.getpte(r_dcache_tlb_way_save, r_dcache_tlb_set_save) | PTE_D_MASK;
+                    r_dcache_tlb_paddr = (paddr_t)r_mmu_ptpr << (INDEX1_NBITS+2) | (paddr_t)((dreq.addr>>PAGE_M_NBITS)<<2);
+                    write_hit = r_dcache.write((paddr_t)r_mmu_ptpr << (INDEX1_NBITS+2) | (paddr_t)((dreq.addr>>PAGE_M_NBITS)<<2), 
+                                               (dcache_tlb.getpte(r_dcache_tlb_way_save, r_dcache_tlb_set_save) | PTE_D_MASK));
+                    assert(write_hit && "Write on miss ignores data");
+                    r_dcache_tlb_ll_dirty_req = true;
+                    r_dcache_fsm = DCACHE_LL_DIRTY_WAIT;
+                    m_cpt_data_tlb_write_dirty++;
+                }
+                else
+                {   
+                    if (r_dcache_hit_p_save) 
+                    {
+                        r_dcache_pte_update = dcache_tlb.getpte(r_dcache_tlb_way_save, r_dcache_tlb_set_save) | PTE_D_MASK;
+                        r_dcache_tlb_paddr = (paddr_t)r_dcache_ptba_save|(paddr_t)(((dreq.addr&PTD_ID2_MASK)>>PAGE_K_NBITS) << 3);
+                        write_hit = r_dcache.write(((paddr_t)r_dcache_ptba_save|(paddr_t)(((dreq.addr&PTD_ID2_MASK)>>PAGE_K_NBITS) << 3)), 
+                                                    (dcache_tlb.getpte(r_dcache_tlb_way_save, r_dcache_tlb_set_save) | PTE_D_MASK));
+                        assert(write_hit && "Write on miss ignores data");
+                        r_dcache_tlb_ll_dirty_req = true;
+                        r_dcache_fsm = DCACHE_LL_DIRTY_WAIT;
+                        m_cpt_data_tlb_write_dirty++;
+                    }
+                    else
+                    {
+                        r_dcache_pte_update = dcache_tlb.getpte(r_dcache_tlb_way_save, r_dcache_tlb_set_save) | PTE_D_MASK;
+                        r_dcache_tlb_paddr = (paddr_t)r_mmu_ptpr << (INDEX1_NBITS+2) | (paddr_t)((dreq.addr>>PAGE_M_NBITS)<<2);
+                        r_dcache_tlb_ptba_read = true;
+                        r_dcache_fsm = DCACHE_DTLB1_READ_CACHE;
+                    }
+                }
+                m_cost_data_tlb_miss_frz++;
+            }
+            else                                    // no cache update, not dirty bit update
+            {
+                r_dcache_fsm = DCACHE_WRITE_REQ;
+                drsp.valid = true;
+                drsp.rdata = 0;
+            }
+        }
+        break;
+    }
+    //////////////////////////
+    case DCACHE_LL_DIRTY_WAIT:
+    {
+        // external cache invalidate request
+        if ( r_tgt_dcache_req )   
+        {
+            r_dcache_fsm = DCACHE_CC_CHECK;
+            r_dcache_fsm_save = r_dcache_fsm;
+            m_cost_data_waste_wait_frz++;
+            break;
+        }
+
+	if (!r_dcache_tlb_ll_dirty_req)
+	{
+            if ( r_vci_rsp_data_error ) // VCI response ko
+            {
+		if (dcache_tlb.getpagesize(r_dcache_tlb_way_save, r_dcache_tlb_set_save)) 
+		{
+                    r_dcache_error_type = MMU_WRITE_PT1_ILLEGAL_ACCESS;     
+		}
+		else
+		{
+                    r_dcache_error_type = MMU_WRITE_PT2_ILLEGAL_ACCESS;     
+		}
+                r_dcache_bad_vaddr = dreq.addr;
+                r_dcache_fsm = DCACHE_ERROR; 
+
+		if (r_dcache_inval_tlb_rsp) r_dcache_inval_tlb_rsp = false;
+		if (r_dcache_inval_rsp) r_dcache_inval_rsp = false;
+            }
+	    else
+	    {
+		if ( !(r_dcache_miss_buf[0] >> PTE_V_SHIFT) )	// unmapped
+	        {
+		    if (dcache_tlb.getpagesize(r_dcache_tlb_way_save, r_dcache_tlb_set_save))
+		    { 
+			r_dcache_error_type = MMU_WRITE_PT1_UNMAPPED;       
+		    }
+		    else
+		    {
+			r_dcache_error_type = MMU_WRITE_PT2_UNMAPPED;       
+	  	    }
+                    r_dcache_bad_vaddr = dreq.addr;
+                    r_dcache_fsm = DCACHE_ERROR;
+
+		    if (r_dcache_inval_tlb_rsp) r_dcache_inval_tlb_rsp = false;
+		    if (r_dcache_inval_rsp) r_dcache_inval_rsp = false;
+	        }
+        	else if ( r_dcache_inval_tlb_rsp )
+        	{
+        	    r_dcache_inval_tlb_rsp = false;
+        	    r_dcache_fsm = DCACHE_IDLE;
+        	    m_cost_data_tlb_miss_frz++;
+        	}
+		else if ( r_dcache_inval_rsp )
+		{
+        	    r_dcache_inval_rsp = false;
+		    r_dcache_fsm = DCACHE_IDLE;
+		}
+		else
+		{
+		    r_dcache_tlb_sc_dirty_req = true;
+		    r_dcache_pte_update = r_dcache_miss_buf[0] | r_dcache_pte_update.read();
+                    r_dcache_fsm = DCACHE_SC_DIRTY_WAIT; 
+		}
+	    }
+	}
+	break;
+    }
+    //////////////////////////
+    case DCACHE_SC_DIRTY_WAIT:
+    {
+        // external cache invalidate request
+        if ( r_tgt_dcache_req )   
+        {
+            r_dcache_fsm = DCACHE_CC_CHECK;
+            r_dcache_fsm_save = r_dcache_fsm;
+            m_cost_data_waste_wait_frz++;
+            break;
+        }
+
+	if ( !r_dcache_tlb_sc_dirty_req )
+	{
+	    if ( r_vci_rsp_data_error ) // VCI response ko
+	    {
+	        if (dcache_tlb.getpagesize(r_dcache_tlb_way_save, r_dcache_tlb_set_save))
+	        {
+	            r_dcache_error_type = MMU_WRITE_PT1_ILLEGAL_ACCESS;    
+	        }
+	        else
+	        {
+	            r_dcache_error_type = MMU_WRITE_PT2_ILLEGAL_ACCESS;    
+	        }
+	        r_dcache_bad_vaddr = dreq.addr;
+	        r_dcache_fsm = DCACHE_ERROR;
+
+		if (r_dcache_inval_tlb_rsp) r_dcache_inval_tlb_rsp = false;
+		if (r_dcache_inval_rsp) r_dcache_inval_rsp = false;		 		         }
+	    else 
+	    {
+                // Using tlb entry is invalidated 
+                if ( r_dcache_inval_tlb_rsp )
+                {
+                    r_dcache_inval_tlb_rsp = false;
+                    r_dcache_fsm = DCACHE_IDLE;
+                    m_cost_data_tlb_miss_frz++;
+                }
+		else if ( r_dcache_inval_rsp )
+		{
+        	    r_dcache_inval_rsp = false;
+		    r_dcache_fsm = DCACHE_IDLE;
+		}
+		else if ( r_dcache_tlb_ll_dirty_req )
+	        {
+	            r_dcache_fsm = DCACHE_LL_DIRTY_WAIT; 
+	        }
+		else
+		{
+	            r_dcache_fsm = DCACHE_WRITE_DIRTY; 
+		}
+	    }
+	}
+	break;
+    }
+    ////////////////////////////
+    case DCACHE_DTLB1_READ_CACHE:
+    {
+        m_cost_data_tlb_miss_frz++;
+
+        // external cache invalidate request
+        if ( r_tgt_dcache_req )   
+        {
+            r_dcache_fsm = DCACHE_CC_CHECK;
+            r_dcache_fsm_save = r_dcache_fsm;
+            m_cost_data_waste_wait_frz++;
+            break;
+        }        
+
+        // Using tlb entry is invalidated 
+        if ( r_dcache_inval_tlb_rsp )
+        {
+            r_dcache_inval_tlb_rsp = false;
+            r_dcache_fsm = DCACHE_IDLE;
+            m_cost_data_tlb_miss_frz++;
+            break;
+        }
+
+        data_t tlb_data = 0;
+	bool write_hit = false;
+        bool tlb_hit_cache = r_dcache.read(r_dcache_tlb_paddr, &tlb_data);
+
+        // DTLB request hit in cache
+        if ( tlb_hit_cache )
+        {
+	    if ( !(tlb_data >> PTE_V_SHIFT) )	// unmapped
+	    {
+                r_dcache_ptba_ok    = false;
+                if ((r_dcache_type_save == iss_t::DATA_READ)||(r_dcache_type_save == iss_t::DATA_LL))
+                {
+                    r_dcache_error_type = MMU_READ_PT1_UNMAPPED;
+                }
+                else /*if ((dreq.type == iss_t::DATA_WRITE)||(dreq.type == iss_t::DATA_SC))*/
+                {
+                    r_dcache_error_type = MMU_WRITE_PT1_UNMAPPED;
+                }  
+                r_dcache_bad_vaddr  = dreq.addr;
+                r_dcache_fsm        = DCACHE_ERROR;
+	    }
+	    else if ( (tlb_data & PTE_T_MASK) >> PTE_T_SHIFT )	// PTD
+	    {
+                r_dcache_ptba_ok   = true;
+                r_dcache_ptba_save = (paddr_t)(tlb_data & ((1<<(m_paddr_nbits - PAGE_K_NBITS))-1)) << PAGE_K_NBITS;  
+                r_dcache_id1_save  = dreq.addr >> PAGE_M_NBITS;
+                r_dcache_tlb_paddr = (paddr_t)(tlb_data & ((1<<(m_paddr_nbits - PAGE_K_NBITS))-1)) << PAGE_K_NBITS | 
+                                     (paddr_t)(((dreq.addr & PTD_ID2_MASK) >> PAGE_K_NBITS) << 3);
+                if ( r_dcache_tlb_ptba_read )
+                {
+                    r_dcache_tlb_ptba_read = false;
+                    write_hit = r_dcache.write(((paddr_t)(tlb_data & ((1<<(m_paddr_nbits - PAGE_K_NBITS))-1)) << PAGE_K_NBITS | 
+                                                (paddr_t)(((dreq.addr & PTD_ID2_MASK) >> PAGE_K_NBITS) << 3)), r_dcache_pte_update);
+                    assert(write_hit && "Write on miss ignores data");
+                    r_dcache_tlb_ll_dirty_req = true;
+                    r_dcache_fsm = DCACHE_LL_DIRTY_WAIT;
+                    m_cpt_data_tlb_write_dirty++;
+                }
+                else
+                {
+                    r_dcache_fsm = DCACHE_DTLB2_READ_CACHE;
+                }
+	    }
+	    else	// PTE
+	    {
+                r_dcache_ptba_ok = false;
+	        if ( (m_srcid_rw >> 4) == ((r_dcache_tlb_paddr.read() & ((1<<(m_paddr_nbits - PAGE_M_NBITS))-1)) >> (m_paddr_nbits - PAGE_M_NBITS -10)) ) // local
+		{
+		    if ( (tlb_data & PTE_L_MASK ) >> PTE_L_SHIFT ) // L bit is set
+		    {
+                        r_dcache_pte_update = tlb_data;
+                        r_dcache_fsm = DCACHE_TLB1_UPDT;
+		    }
+		    else
+		    {
+                        r_dcache_pte_update = tlb_data | PTE_L_MASK;
+                        r_dcache_tlb_ll_acc_req = true;
+                	write_hit = r_dcache.write(r_dcache_tlb_paddr,(tlb_data | PTE_L_MASK));  
+                	assert(write_hit && "Write on miss ignores data");  
+                        r_dcache_fsm = DCACHE_TLB1_LL_WAIT;
+                        m_cpt_ins_tlb_write_et++;
+		    }
+    	        }
+		else // remotely
+		{
+		    if ( (tlb_data & PTE_R_MASK ) >> PTE_R_SHIFT ) // R bit is set
+		    {
+                        r_dcache_pte_update = tlb_data;
+                        r_dcache_fsm = DCACHE_TLB1_UPDT;
+		    }
+		    else
+		    {
+                        r_dcache_pte_update = tlb_data | PTE_R_MASK;
+                        r_dcache_tlb_ll_acc_req = true;
+                	write_hit = r_dcache.write(r_dcache_tlb_paddr,(tlb_data | PTE_R_MASK));  
+                	assert(write_hit && "Write on miss ignores data");  
+                        r_dcache_fsm = DCACHE_TLB1_LL_WAIT;
+                        m_cpt_ins_tlb_write_et++;
+		    }
+		}
+	    }
+        }
+        else
+        {
+            // DTLB request miss in cache and walk page table level 1
+            r_dcache_tlb_read_req = true;
+            r_dcache_fsm = DCACHE_TLB1_READ;
+        }
+        break;
+    }
+    ///////////////////////
+    case DCACHE_TLB1_LL_WAIT:
+    {
+        // external cache invalidate request
+        if ( r_tgt_dcache_req )   
+        {
+            r_dcache_fsm = DCACHE_CC_CHECK;
+            r_dcache_fsm_save = r_dcache_fsm;
+            m_cost_data_waste_wait_frz++;
+            break;
+        }
+
+	if (!r_dcache_tlb_ll_acc_req)
+	{
+            if ( r_vci_rsp_data_error ) // VCI response ko
+            {
+                if ((r_dcache_type_save == iss_t::DATA_READ)||(r_dcache_type_save == iss_t::DATA_LL))
+                {
+                    r_dcache_error_type = MMU_READ_PT1_ILLEGAL_ACCESS;
+                }
+                else /*if ((dreq.type == iss_t::DATA_WRITE)||(dreq.type == iss_t::DATA_SC))*/
+                {
+                    r_dcache_error_type = MMU_WRITE_PT1_ILLEGAL_ACCESS;
+                } 
+                r_dcache_bad_vaddr = dreq.addr;
+                r_dcache_fsm = DCACHE_ERROR;
+
+		if (r_dcache_inval_tlb_rsp) r_dcache_inval_tlb_rsp = false;
+		if (r_dcache_inval_rsp) r_dcache_inval_rsp = false;		 
+            }
+	    else
+	    {
+		if ( !(r_dcache_miss_buf[0] >> PTE_V_SHIFT) )	// unmapped
+	        {
+               	    if ((r_dcache_type_save == iss_t::DATA_READ)||(r_dcache_type_save == iss_t::DATA_LL))
+               	    {
+               	        r_dcache_error_type = MMU_READ_PT1_UNMAPPED;
+               	    }
+               	    else /*if ((dreq.type == iss_t::DATA_WRITE)||(dreq.type == iss_t::DATA_SC))*/
+               	    {
+               	        r_dcache_error_type = MMU_WRITE_PT1_UNMAPPED;
+               	    } 
+                    r_dcache_bad_vaddr  = dreq.addr;
+                    r_dcache_fsm        = DCACHE_ERROR;
+
+		    if (r_dcache_inval_tlb_rsp) r_dcache_inval_tlb_rsp = false;
+		    if (r_dcache_inval_rsp) r_dcache_inval_rsp = false;	
+	        }
+       		else if ( r_dcache_inval_tlb_rsp )
+       		{
+       		    r_dcache_inval_tlb_rsp = false;
+       		    r_dcache_fsm = DCACHE_IDLE;
+       		    m_cost_data_tlb_miss_frz++;
+       		}
+		else if ( r_dcache_inval_rsp )
+       		{
+       		    r_dcache_inval_rsp = false;
+       		    r_dcache_fsm = DCACHE_IDLE;
+       		}
+		else
+		{
+		    r_dcache_tlb_sc_acc_req = true;
+		    r_dcache_pte_update = r_dcache_miss_buf[0] | r_dcache_pte_update.read();
+                    r_dcache_fsm = DCACHE_TLB1_SC_WAIT; 
+		}
+	    }
+	}
+	break;
+    }
+    ///////////////////////
+    case DCACHE_TLB1_SC_WAIT:
+    {
+        // external cache invalidate request
+        if ( r_tgt_dcache_req )   
+        {
+            r_dcache_fsm = DCACHE_CC_CHECK;
+            r_dcache_fsm_save = r_dcache_fsm;
+            m_cost_data_waste_wait_frz++;
+            break;
+        }
+
+	if ( !r_dcache_tlb_sc_acc_req )
+	{
+	    if ( r_vci_rsp_data_error ) // VCI response ko
+	    {
+                if ((r_dcache_type_save == iss_t::DATA_READ)||(r_dcache_type_save == iss_t::DATA_LL))
+                {
+                    r_dcache_error_type = MMU_READ_PT1_ILLEGAL_ACCESS;
+                }
+                else /*if ((dreq.type == iss_t::DATA_WRITE)||(dreq.type == iss_t::DATA_SC))*/
+                {
+                    r_dcache_error_type = MMU_WRITE_PT1_ILLEGAL_ACCESS;
+                } 
+	        r_dcache_bad_vaddr = dreq.addr;
+	        r_dcache_fsm = DCACHE_ERROR; 
+
+		if (r_dcache_inval_tlb_rsp) r_dcache_inval_tlb_rsp = false;
+		if (r_dcache_inval_rsp) r_dcache_inval_rsp = false;	
+	    }
+	    else
+	    {
+        	// Using tlb entry is invalidated 
+        	if ( r_dcache_inval_tlb_rsp )
+        	{
+        	    r_dcache_inval_tlb_rsp = false;
+        	    r_dcache_fsm = DCACHE_IDLE;
+        	    m_cost_data_tlb_miss_frz++;
+        	}
+		else if ( r_dcache_inval_rsp )
+        	{
+        	    r_dcache_inval_rsp = false;
+        	    r_dcache_fsm = DCACHE_IDLE;
+        	}
+	    	else if ( r_dcache_tlb_ll_acc_req )
+	    	{
+	    	    r_dcache_fsm = DCACHE_TLB1_LL_WAIT; 
+	    	}
+	    	else 
+	    	{
+	    	    r_dcache_fsm = DCACHE_TLB1_UPDT; 
+	    	}
+	    }
+	}
+	break;
+    }
+    //////////////////////
+    case DCACHE_TLB1_READ:
+    {
+        m_cost_data_tlb_miss_frz++;
+
+        // external cache invalidate request
+        if ( r_tgt_dcache_req )   
+        {
+            r_dcache_fsm = DCACHE_CC_CHECK;
+            r_dcache_fsm_save = r_dcache_fsm;
+            m_cost_data_waste_wait_frz++;
+            break;
+        }        
+
+	if ( !r_dcache_tlb_read_req )
+	{	
+            if ( r_vci_rsp_data_error ) // VCI response ko
+            {
+                if ((r_dcache_type_save == iss_t::DATA_READ)||(r_dcache_type_save == iss_t::DATA_LL))
+                {
+                    r_dcache_error_type = MMU_READ_PT1_ILLEGAL_ACCESS;
+                }
+                else /*if ((dreq.type == iss_t::DATA_WRITE)||(dreq.type == iss_t::DATA_SC))*/
+                {
+                    r_dcache_error_type = MMU_WRITE_PT1_ILLEGAL_ACCESS;
+                } 
+                r_dcache_bad_vaddr = dreq.addr;
+                r_dcache_fsm = DCACHE_ERROR; 
+
+		if (r_dcache_inval_tlb_rsp) r_dcache_inval_tlb_rsp = false;
+		if (r_dcache_inval_rsp) r_dcache_inval_rsp = false;	
+		break;
+            }
+
+            if ( r_dcache_inval_tlb_rsp )  // TLB miss response and invalidation
+            {
+                r_dcache_fsm = DCACHE_IDLE; 
+            	r_dcache_inval_tlb_rsp = false;
+		break;
+            }
+
+	    if ( r_dcache_inval_rsp ) // TLB miss response and cache invalidation
+	    {
+                r_dcache_fsm = DCACHE_IDLE; 
+            	r_dcache_inval_rsp = false;
+		break;	    
+	    }
+	    // TLB miss response and no invalidation
+	    r_dcache_fsm = DCACHE_TLB1_READ_UPDT;
+	}
+        break;
+    }
+    //////////////////////////
+    case DCACHE_TLB1_READ_UPDT:
+    {
+        m_cost_data_tlb_miss_frz++;
+
+        // external cache invalidate request
+        if ( r_tgt_dcache_req )   
+        {
+            r_dcache_fsm = DCACHE_CC_CHECK;
+            r_dcache_fsm_save = r_dcache_fsm;
+            m_cost_data_waste_wait_frz++;
+            break;
+        }        
+
+        // Using tlb entry is invalidated 
+        if ( r_dcache_inval_tlb_rsp )
+        {
+            r_dcache_inval_tlb_rsp = false;
+            r_dcache_fsm = DCACHE_IDLE;
+            m_cost_data_tlb_miss_frz++;
+            break;
+        }
+
+        // Using tlb entry is in the invalidated cache line  
+        if ( r_dcache_inval_rsp )
+        {
+            r_dcache_inval_rsp = false;
+            r_dcache_fsm = DCACHE_IDLE;
+            m_cost_data_tlb_miss_frz++;
+            break;
+        }
+
+        if ( !r_dcache_cleanup_req ) // Miss update and no invalidation
+        {
+            // update dcache
+            data_t   rsp_dtlb_miss = 0;
+            paddr_t  victim_index = 0;
+	    bool write_hit = false;
+            size_t way = 0;
+            size_t set = 0;
+
+            bool cleanup_req = r_dcache.find(r_dcache_tlb_paddr, r_dcache_in_itlb, r_dcache_in_dtlb, &way, &set, &victim_index);
+            
+	    if ( cleanup_req )
+	    {	    
+		// ins tlb invalidate verification    
+                r_dcache_itlb_inval_req = r_dcache_in_itlb[m_dcache_sets*way+set];
+                r_dcache_itlb_inval_line = victim_index;
+                r_dcache_in_itlb[way*m_dcache_sets+set] = false;
+
+                // data tlb invalidate verification
+                r_dcache_dtlb_inval_req = r_dcache_in_dtlb[m_dcache_sets*way+set]; 
+                r_dcache_dtlb_inval_line = victim_index;
+                r_dcache_in_dtlb[way*m_dcache_sets+set] = false;
+
+                r_dcache_cleanup_req = true; 
+                r_dcache_cleanup_line = victim_index;
+		r_dcache_fsm = DCACHE_TLB_CC_INVAL;
+                r_dcache_fsm_save = r_dcache_fsm;
+		break;
+	    }
+
+	    r_dcache.update(r_dcache_tlb_paddr, way, set, r_dcache_miss_buf);
+            r_dcache.read(r_dcache_tlb_paddr, &rsp_dtlb_miss);	
+
+	    if ( !(rsp_dtlb_miss >> PTE_V_SHIFT) )	// unmapped
+	    {
+                r_dcache_ptba_ok    = false;
+                if ((r_dcache_type_save == iss_t::DATA_READ)||(r_dcache_type_save == iss_t::DATA_LL))
+                {
+                    r_dcache_error_type = MMU_READ_PT1_UNMAPPED;
+                }
+                else /*if ((dreq.type == iss_t::DATA_WRITE)||(dreq.type == iss_t::DATA_SC))*/
+                {
+                    r_dcache_error_type = MMU_WRITE_PT1_UNMAPPED;
+                } 
+                r_dcache_bad_vaddr  = dreq.addr;
+                r_dcache_fsm        = DCACHE_ERROR;
+	    }
+	    else if ( (rsp_dtlb_miss & PTE_T_MASK) >> PTE_T_SHIFT ) // PTD
+	    {
+                r_dcache_ptba_ok   = true;
+                r_dcache_ptba_save = (paddr_t)(rsp_dtlb_miss & ((1<<(m_paddr_nbits - PAGE_K_NBITS))-1)) << PAGE_K_NBITS;  
+                r_dcache_id1_save  = dreq.addr >> PAGE_M_NBITS;
+                r_dcache_tlb_paddr = (paddr_t)(rsp_dtlb_miss & ((1<<(m_paddr_nbits - PAGE_K_NBITS))-1)) << PAGE_K_NBITS | 
+                                     (paddr_t)(((dreq.addr & PTD_ID2_MASK) >> PAGE_K_NBITS) << 3);
+                if ( r_dcache_tlb_ptba_read )
+                {
+                    r_dcache_tlb_ptba_read = false;
+                    write_hit = r_dcache.write(((paddr_t)(rsp_dtlb_miss & ((1<<(m_paddr_nbits - PAGE_K_NBITS))-1)) << PAGE_K_NBITS | 
+                                                (paddr_t)(((dreq.addr & PTD_ID2_MASK) >> PAGE_K_NBITS) << 3)),r_dcache_pte_update);
+                    assert(write_hit && "Write on miss ignores data");
+                    r_dcache_tlb_ll_dirty_req = true;
+                    r_dcache_fsm = DCACHE_LL_DIRTY_WAIT;
+                    m_cpt_data_tlb_write_dirty++;
+                }
+                else
+                {
+                    r_dcache_fsm = DCACHE_DTLB2_READ_CACHE;
+                }
+	    }
+	    else	// PTE
+	    {
+                r_dcache_ptba_ok = false;
+	        if ( (m_srcid_rw >> 4) == ((r_dcache_tlb_paddr.read() & ((1<<(m_paddr_nbits - PAGE_M_NBITS))-1)) >> (m_paddr_nbits - PAGE_M_NBITS -10)) ) // local
+		{
+		    if ( (rsp_dtlb_miss & PTE_L_MASK ) >> PTE_L_SHIFT ) // L bit is set
+		    {
+                        r_dcache_pte_update = rsp_dtlb_miss;
+                        r_dcache_fsm        = DCACHE_TLB1_UPDT;
+		    }
+		    else
+		    {
+                        r_dcache_pte_update = rsp_dtlb_miss | PTE_L_MASK;
+                        r_dcache_tlb_ll_acc_req = true;
+                	write_hit = r_dcache.write(r_dcache_tlb_paddr,(rsp_dtlb_miss | PTE_L_MASK));  
+                	assert(write_hit && "Write on miss ignores data");  
+                        r_dcache_fsm        = DCACHE_TLB1_LL_WAIT;
+                        m_cpt_ins_tlb_write_et++;
+		    }
+    	        }
+		else // remotely
+		{
+		    if ( (rsp_dtlb_miss & PTE_R_MASK ) >> PTE_R_SHIFT ) // R bit is set
+		    {
+                        r_dcache_pte_update = rsp_dtlb_miss;
+                        r_dcache_fsm        = DCACHE_TLB1_UPDT;
+		    }
+		    else
+		    {
+                        r_dcache_pte_update = rsp_dtlb_miss | PTE_R_MASK;
+                        r_dcache_tlb_ll_acc_req = true;
+                	write_hit = r_dcache.write(r_dcache_tlb_paddr,(rsp_dtlb_miss | PTE_R_MASK));  
+                	assert(write_hit && "Write on miss ignores data");  
+                        r_dcache_fsm        = DCACHE_TLB1_LL_WAIT;
+                        m_cpt_ins_tlb_write_et++;
+		    }
+		}
+	    }
+        }
+        break;
+    }
+    //////////////////////
+    case DCACHE_TLB1_UPDT: 
+    {
+        m_cost_data_tlb_miss_frz++;
+
+        // external cache invalidate request
+        if ( r_tgt_dcache_req )   
+        {
+            r_dcache_fsm = DCACHE_CC_CHECK;
+            r_dcache_fsm_save = r_dcache_fsm;
+            m_cost_data_waste_wait_frz++;
+            break;
+        }        
+
+        if ( !r_dcache_inval_tlb_rsp && !r_dcache_inval_rsp )
+        {
+            paddr_t victim_index = 0;
+            if (dcache_tlb.update(r_dcache_pte_update,dreq.addr,(r_dcache_tlb_paddr.read() >> (uint32_log2(m_dcache_words)+2)),&victim_index))
+            {
+                r_dcache.setinbit((paddr_t)victim_index*m_dcache_words*2, r_dcache_in_dtlb, false);
+            }
+            r_dcache.setinbit(r_dcache_tlb_paddr, r_dcache_in_dtlb, true);
+            r_dcache_fsm = DCACHE_IDLE;
+        }
+        else  
+        {
+            if ( r_dcache_inval_tlb_rsp ) r_dcache_inval_tlb_rsp = false;
+            if ( r_dcache_inval_rsp ) r_dcache_inval_rsp = false;
+            r_dcache_fsm = DCACHE_IDLE;
+        }
+        break;
+    }
+    /////////////////////////////
+    case DCACHE_DTLB2_READ_CACHE:
+    {
+        m_cost_data_tlb_miss_frz++;
+
+        // external cache invalidate request
+        if ( r_tgt_dcache_req )   
+        {
+            r_dcache_fsm = DCACHE_CC_CHECK;
+            r_dcache_fsm_save = r_dcache_fsm;
+            m_cost_data_waste_wait_frz++;
+            break;
+        }        
+
+        // Using tlb entry is invalidated 
+        if ( r_dcache_inval_tlb_rsp )
+        {
+            r_dcache_inval_tlb_rsp = false;
+            r_dcache_fsm = DCACHE_IDLE;
+            m_cost_data_tlb_miss_frz++;
+            break;
+        }
+
+        data_t tlb_data = 0;
+        data_t tlb_data_ppn = 0;
+	bool write_hit = false;
+        bool tlb_hit_cache = r_dcache.read(r_dcache_tlb_paddr, &tlb_data);
+
+	if ( tlb_hit_cache )
+	{
+            bool tlb_hit_ppn = r_dcache.read(r_dcache_tlb_paddr.read()+4, &tlb_data_ppn);
+	    assert(tlb_hit_ppn && "Address of pte[64-32] and pte[31-0] should be successive");
+	}
+
+        // DTLB request hit in cache
+        if ( tlb_hit_cache )
+        {
+	    if ( !(tlb_data >> PTE_V_SHIFT) )	// unmapped
+	    {
+                if ((r_dcache_type_save == iss_t::DATA_READ)||(r_dcache_type_save == iss_t::DATA_LL))
+                {
+                    r_dcache_error_type = MMU_READ_PT2_UNMAPPED;
+                }
+                else /*if ((dreq.type == iss_t::DATA_WRITE)||(dreq.type == iss_t::DATA_SC))*/
+                {
+                    r_dcache_error_type = MMU_WRITE_PT2_UNMAPPED;
+                } 
+                r_dcache_bad_vaddr  = dreq.addr;
+                r_dcache_fsm        = DCACHE_ERROR;
+	    }
+	    else if ( (tlb_data & PTE_T_MASK) >> PTE_T_SHIFT ) //PTD
+	    {
+                r_dcache_pte_update = tlb_data;
+	        r_dcache_ppn_update = tlb_data_ppn;
+		r_dcache_fsm = DCACHE_TLB2_UPDT;
+	    }
+	    else 
+	    {
+	        if ( (m_srcid_rw >> 4) == ((r_dcache_tlb_paddr.read() & ((1<<(m_paddr_nbits - PAGE_M_NBITS))-1)) >> (m_paddr_nbits - PAGE_M_NBITS -10)) ) // local
+		{
+		    if ( (tlb_data & PTE_L_MASK ) >> PTE_L_SHIFT ) // L bit is set
+		    {
+                        r_dcache_pte_update = tlb_data;
+			r_dcache_ppn_update = tlb_data_ppn;
+                        r_dcache_fsm        = DCACHE_TLB2_UPDT;
+		    }
+		    else
+		    {
+                        r_dcache_pte_update = tlb_data | PTE_L_MASK;
+	        	r_dcache_ppn_update = tlb_data_ppn;
+                        r_dcache_tlb_ll_acc_req = true;
+                	write_hit = r_dcache.write(r_dcache_tlb_paddr,(tlb_data | PTE_L_MASK));  
+                	assert(write_hit && "Write on miss ignores data");  
+                        r_dcache_fsm = DCACHE_TLB2_LL_WAIT;
+                        m_cpt_ins_tlb_write_et++;
+		    }
+    	        }
+		else // remotely
+		{
+		    if ( (tlb_data & PTE_R_MASK ) >> PTE_R_SHIFT ) // R bit is set
+		    {
+                        r_dcache_pte_update = tlb_data;
+			r_dcache_ppn_update = tlb_data_ppn;
+                        r_dcache_fsm        = DCACHE_TLB2_UPDT;
+		    }
+		    else
+		    {
+                        r_dcache_pte_update = tlb_data | PTE_R_MASK;
+	        	r_dcache_ppn_update = tlb_data_ppn;
+                        r_dcache_tlb_ll_acc_req = true;
+                	write_hit = r_dcache.write(r_dcache_tlb_paddr,(tlb_data | PTE_R_MASK));  
+                	assert(write_hit && "Write on miss ignores data");  
+                        r_dcache_fsm = DCACHE_TLB2_LL_WAIT;
+                        m_cpt_ins_tlb_write_et++;
+		    }
+		}
+	    }
+        }
+        else
+        {
+            // DTLB request miss in cache and walk page table level 2
+            r_dcache_tlb_read_req = true;
+            r_dcache_fsm = DCACHE_TLB2_READ;
+        }
+        break;
+    }
+    ///////////////////////
+    case DCACHE_TLB2_LL_WAIT:
+    {
+        // external cache invalidate request
+        if ( r_tgt_dcache_req )   
+        {
+            r_dcache_fsm = DCACHE_CC_CHECK;
+            r_dcache_fsm_save = r_dcache_fsm;
+            m_cost_data_waste_wait_frz++;
+            break;
+        }
+
+	if (!r_dcache_tlb_ll_acc_req)
+	{
+            if ( r_vci_rsp_data_error ) // VCI response ko
+            {
+                if ((r_dcache_type_save == iss_t::DATA_READ)||(r_dcache_type_save == iss_t::DATA_LL))
+                {
+                    r_dcache_error_type = MMU_READ_PT2_ILLEGAL_ACCESS;
+                }
+                else /*if ((dreq.type == iss_t::DATA_WRITE)||(dreq.type == iss_t::DATA_SC))*/
+                {
+                    r_dcache_error_type = MMU_WRITE_PT2_ILLEGAL_ACCESS;
+                } 
+                r_dcache_bad_vaddr = dreq.addr;
+                r_dcache_fsm = DCACHE_ERROR; 
+
+		if (r_dcache_inval_tlb_rsp) r_dcache_inval_tlb_rsp = false;
+		if (r_dcache_inval_rsp) r_dcache_inval_rsp = false;
+            }
+	    else
+	    {
+	        if ( !(r_dcache_miss_buf[0] >> PTE_V_SHIFT) )	// unmapped
+	        {
+               	    if ((r_dcache_type_save == iss_t::DATA_READ)||(r_dcache_type_save == iss_t::DATA_LL))
+               	    {
+               	        r_dcache_error_type = MMU_READ_PT2_UNMAPPED;
+               	    }
+               	    else /*if ((dreq.type == iss_t::DATA_WRITE)||(dreq.type == iss_t::DATA_SC))*/
+               	    {
+               	        r_dcache_error_type = MMU_WRITE_PT2_UNMAPPED;
+               	    } 
+                    r_dcache_bad_vaddr = dreq.addr;
+                    r_dcache_fsm = DCACHE_ERROR;
+
+		    if (r_dcache_inval_tlb_rsp) r_dcache_inval_tlb_rsp = false;
+		    if (r_dcache_inval_rsp) r_dcache_inval_rsp = false;
+	        }
+        	else if ( r_dcache_inval_tlb_rsp )
+        	{
+        	    r_dcache_inval_tlb_rsp = false;
+        	    r_dcache_fsm = DCACHE_IDLE;
+        	    m_cost_data_tlb_miss_frz++;
+        	}
+		else if ( r_dcache_inval_rsp )
+		{
+        	    r_dcache_inval_rsp = false;
+		    r_dcache_fsm = DCACHE_IDLE;
+		}
+		else
+		{
+		    r_dcache_tlb_sc_acc_req = true;
+		    r_dcache_pte_update = r_dcache_miss_buf[0] | r_dcache_pte_update.read();
+                    r_dcache_fsm = DCACHE_TLB2_SC_WAIT; 
+		}
+	    }
+	}
+	break;
+    }
+    ///////////////////////
+    case DCACHE_TLB2_SC_WAIT:
+    {
+        // external cache invalidate request
+        if ( r_tgt_dcache_req )   
+        {
+            r_dcache_fsm = DCACHE_CC_CHECK;
+            r_dcache_fsm_save = r_dcache_fsm;
+            m_cost_data_waste_wait_frz++;
+            break;
+        }
+
+	if ( !r_dcache_tlb_sc_acc_req )
+	{
+	    if ( r_vci_rsp_data_error ) // VCI response ko
+	    {
+                if ((r_dcache_type_save == iss_t::DATA_READ)||(r_dcache_type_save == iss_t::DATA_LL))
+                {
+                    r_dcache_error_type = MMU_READ_PT2_ILLEGAL_ACCESS;
+                }
+                else /*if ((dreq.type == iss_t::DATA_WRITE)||(dreq.type == iss_t::DATA_SC))*/
+                {
+                    r_dcache_error_type = MMU_WRITE_PT2_ILLEGAL_ACCESS;
+                } 
+	        r_dcache_bad_vaddr = dreq.addr;
+	        r_dcache_fsm = DCACHE_ERROR; 
+
+		if (r_dcache_inval_tlb_rsp) r_dcache_inval_tlb_rsp = false;
+		if (r_dcache_inval_rsp) r_dcache_inval_rsp = false;	
+	    }
+	    else
+	    { 
+                // Using tlb entry is invalidated 
+                if ( r_dcache_inval_tlb_rsp )
+                {
+                    r_dcache_inval_tlb_rsp = false;
+                    r_dcache_fsm = DCACHE_IDLE;
+                    m_cost_data_tlb_miss_frz++;
+                }
+		else if ( r_dcache_inval_rsp )
+		{
+        	    r_dcache_inval_rsp = false;
+		    r_dcache_fsm = DCACHE_IDLE;
+		}
+	        else if ( r_dcache_tlb_ll_acc_req )
+	        {
+	            r_dcache_fsm = DCACHE_TLB2_LL_WAIT; 
+	        }
+	        else 
+	        {
+	            r_dcache_fsm = DCACHE_TLB2_UPDT; 
+	        }
+	    }
+	}
+	break;
+    }
+    /////////////////////
+    case DCACHE_TLB2_READ:
+    {
+        m_cost_data_tlb_miss_frz++;
+
+        // external cache invalidate request
+        if ( r_tgt_dcache_req )   
+        {
+            r_dcache_fsm = DCACHE_CC_CHECK;
+            r_dcache_fsm_save = r_dcache_fsm;
+            m_cost_data_waste_wait_frz++;
+            break;
+        }        
+
+	if ( !r_dcache_tlb_read_req )
+	{
+            if ( r_vci_rsp_data_error ) // VCI response ko
+            {
+                if ((r_dcache_type_save == iss_t::DATA_READ)||(r_dcache_type_save == iss_t::DATA_LL))
+                {
+                    r_dcache_error_type = MMU_READ_PT2_ILLEGAL_ACCESS;
+                }
+                else /*if ((dreq.type == iss_t::DATA_WRITE)||(dreq.type == iss_t::DATA_SC))*/
+                {
+                    r_dcache_error_type = MMU_WRITE_PT2_ILLEGAL_ACCESS;
+                } 
+                r_dcache_bad_vaddr = dreq.addr;
+                r_dcache_fsm = DCACHE_ERROR; 
+
+		if (r_dcache_inval_tlb_rsp) r_dcache_inval_tlb_rsp = false;
+		if (r_dcache_inval_rsp) r_dcache_inval_rsp = false;
+		break;
+            }	
+
+            if ( r_dcache_inval_tlb_rsp )  // TLB miss response and invalidation
+            {
+                r_dcache_fsm = DCACHE_IDLE; 
+                r_dcache_inval_tlb_rsp = false;
+		break;
+            }   
+
+	    if ( r_dcache_inval_rsp ) // TLB miss response and cache invalidation
+	    {
+                r_dcache_fsm = DCACHE_IDLE; 
+            	r_dcache_inval_rsp = false;
+		break;	    
+	    }
+	    // TLB miss response and no invalidation
+	    r_dcache_fsm = DCACHE_TLB2_READ_UPDT; 
+	}	
+        break;
+    }
+    //////////////////////////
+    case DCACHE_TLB2_READ_UPDT:
+    {
+        m_cost_data_tlb_miss_frz++;
+
+        // external cache invalidate request
+        if ( r_tgt_dcache_req )   
+        {
+            r_dcache_fsm = DCACHE_CC_CHECK;
+            r_dcache_fsm_save = r_dcache_fsm;
+            m_cost_data_waste_wait_frz++;
+            break;
+        }        
+
+        // Using tlb entry is invalidated 
+        if ( r_dcache_inval_tlb_rsp )
+        {
+            r_dcache_inval_tlb_rsp = false;
+            r_dcache_fsm = DCACHE_IDLE;
+            m_cost_data_tlb_miss_frz++;
+            break;
+        }
+
+        // Using tlb entry is in the invalidated cache line  
+        if ( r_dcache_inval_rsp )
+        {
+            r_dcache_inval_rsp = false;
+            r_dcache_fsm = DCACHE_IDLE;
+            m_cost_data_tlb_miss_frz++;
+            break;
+        }
+
+        if ( !r_dcache_cleanup_req )
+        {
+            // update cache
+            data_t rsp_dtlb_miss;
+            data_t tlb_data_ppn;
+	    bool write_hit = false;
+            paddr_t  victim_index = 0;
+            size_t way = 0;
+            size_t set = 0;
+
+            bool cleanup_req = r_dcache.find(r_dcache_tlb_paddr, r_dcache_in_itlb, r_dcache_in_dtlb, &way, &set, &victim_index);
+
+	    if ( cleanup_req )
+	    {	    
+		// ins tlb invalidate verification    
+                r_dcache_itlb_inval_req = r_dcache_in_itlb[m_dcache_sets*way+set];
+                r_dcache_itlb_inval_line = victim_index;
+                r_dcache_in_itlb[way*m_dcache_sets+set] = false;
+
+                // data tlb invalidate verification
+                r_dcache_dtlb_inval_req = r_dcache_in_dtlb[m_dcache_sets*way+set]; 
+                r_dcache_dtlb_inval_line = victim_index;
+                r_dcache_in_dtlb[way*m_dcache_sets+set] = false;
+
+                r_dcache_cleanup_req = true; 
+                r_dcache_cleanup_line = victim_index;
+		r_dcache_fsm = DCACHE_TLB_CC_INVAL;
+                r_dcache_fsm_save = r_dcache_fsm;
+		break;
+	    }
+
+	    r_dcache.update(r_dcache_tlb_paddr, way, set, r_dcache_miss_buf);
+	    r_dcache.read(r_dcache_tlb_paddr, &rsp_dtlb_miss);
+
+	    bool tlb_hit_ppn = r_dcache.read(r_dcache_tlb_paddr.read()+4, &tlb_data_ppn);
+	    assert(tlb_hit_ppn && "Address of pte[64-32] and pte[31-0] should be successive");
+
+	    if ( !(rsp_dtlb_miss >> PTE_V_SHIFT) )	// unmapped
+	    {
+                if ((r_dcache_type_save == iss_t::DATA_READ)||(r_dcache_type_save == iss_t::DATA_LL))
+                {
+                    r_dcache_error_type = MMU_READ_PT2_UNMAPPED;
+                }
+                else /*if ((dreq.type == iss_t::DATA_WRITE)||(dreq.type == iss_t::DATA_SC))*/
+                {
+                    r_dcache_error_type = MMU_WRITE_PT2_UNMAPPED;
+                }  
+                r_dcache_bad_vaddr  = dreq.addr;
+                r_dcache_fsm        = DCACHE_ERROR;
+	    }
+	    else if ( (rsp_dtlb_miss & PTE_T_MASK) >> PTE_T_SHIFT ) // PTD
+	    {
+                r_dcache_pte_update = rsp_dtlb_miss;
+	        r_dcache_ppn_update = tlb_data_ppn;
+		r_dcache_fsm = DCACHE_TLB2_UPDT;
+	    }
+	    else
+	    {
+	        if ( (m_srcid_rw >> 4) == ((r_dcache_tlb_paddr.read() & ((1<<(m_paddr_nbits - PAGE_M_NBITS))-1)) >> (m_paddr_nbits - PAGE_M_NBITS -10)) ) // local
+		{
+		    if ( (rsp_dtlb_miss & PTE_L_MASK ) >> PTE_L_SHIFT ) // L bit is set
+		    {
+                        r_dcache_pte_update = rsp_dtlb_miss;
+			r_dcache_ppn_update = tlb_data_ppn;
+                        r_dcache_fsm        = DCACHE_TLB2_UPDT;
+		    }
+		    else
+		    {
+                        r_dcache_pte_update = rsp_dtlb_miss | PTE_L_MASK;
+	        	r_dcache_ppn_update = tlb_data_ppn;
+                        r_dcache_tlb_ll_acc_req = true;
+                	write_hit = r_dcache.write(r_dcache_tlb_paddr,(rsp_dtlb_miss | PTE_L_MASK));  
+                	assert(write_hit && "Write on miss ignores data");  
+                        r_dcache_fsm = DCACHE_TLB2_LL_WAIT;
+                        m_cpt_ins_tlb_write_et++;
+		    }
+    	        }
+		else // remotely
+		{
+		    if ( (rsp_dtlb_miss & PTE_R_MASK ) >> PTE_R_SHIFT ) // R bit is set
+		    {
+                        r_dcache_pte_update = rsp_dtlb_miss;
+			r_dcache_ppn_update = tlb_data_ppn;
+                        r_dcache_fsm        = DCACHE_TLB2_UPDT;
+		    }
+		    else
+		    {
+                        r_dcache_pte_update = rsp_dtlb_miss | PTE_R_MASK;
+	        	r_dcache_ppn_update = tlb_data_ppn;
+                        r_dcache_tlb_ll_acc_req = true;
+                	write_hit = r_dcache.write(r_dcache_tlb_paddr,(rsp_dtlb_miss | PTE_R_MASK));  
+                	assert(write_hit && "Write on miss ignores data");  
+                        r_dcache_fsm = DCACHE_TLB2_LL_WAIT;
+                        m_cpt_ins_tlb_write_et++;
+		    }
+		}
+	    }
+        }
+        break;
+    }
+    //////////////////////
+    case DCACHE_TLB2_UPDT:  
+    {
+        m_cost_data_tlb_miss_frz++;
+
+        // external cache invalidate request
+        if ( r_tgt_dcache_req )   
+        {
+            r_dcache_fsm = DCACHE_CC_CHECK;
+            r_dcache_fsm_save = r_dcache_fsm;
+            m_cost_data_waste_wait_frz++;
+            break;
+        }        
+
+        if ( !r_dcache_inval_tlb_rsp && !r_dcache_inval_rsp )
+        {
+            paddr_t victim_index = 0;
+            if (dcache_tlb.update(r_dcache_pte_update,r_dcache_ppn_update,dreq.addr,(r_dcache_tlb_paddr.read() >> (uint32_log2(m_dcache_words)+2)),&victim_index))
+            {
+                r_dcache.setinbit((paddr_t)victim_index*m_dcache_words*2, r_dcache_in_dtlb, false);
+            }
+            r_dcache.setinbit(r_dcache_tlb_paddr, r_dcache_in_dtlb, true);
+            r_dcache_fsm = DCACHE_IDLE;
+        }
+        else  
+        {
+            if ( r_dcache_inval_tlb_rsp ) r_dcache_inval_tlb_rsp = false;
+            if ( r_dcache_inval_rsp ) r_dcache_inval_rsp = false;
+            r_dcache_fsm = DCACHE_IDLE;
+        }
+        break;
+    }
+    ///////////////////////
+    case DCACHE_CTXT_SWITCH:
+    {
+        // TLB flush leads to cleanup corresponding data cache line 
+        m_cost_data_tlb_sw_frz++;
+
+        paddr_t victim_index = 0;
+        size_t way = 0;
+        size_t set = 0;
+
+        if ( r_dcache_itlb_cleanup_req )
+        {    
+            r_dcache.setinbit(((paddr_t)r_dcache_itlb_cleanup_line.read()*m_dcache_words*2), r_dcache_in_itlb, false);
+            r_dcache_itlb_cleanup_req = false;
+	}
+
+        for ( way = 0; way < m_dtlb_ways; way++)
+        {
+            for ( set = 0; set < m_dtlb_sets; set++)
+            {
+                if(dcache_tlb.checkcleanup(way, set, &victim_index))
+                {
+                    r_dcache.setinbit((paddr_t)(victim_index << (m_dcache_words+2)), r_dcache_in_dtlb, false); 
+                }
+            }
+        }
+
+        if ((way == m_dtlb_ways) && (set == m_dtlb_sets) && (!r_dcache_xtn_req))
+        {
+            r_dcache_fsm = DCACHE_IDLE;
+            drsp.valid = true;
+        }
+        break;
+    }
+    ////////////////////////
+    case DCACHE_ICACHE_FLUSH:
+    case DCACHE_ICACHE_INVAL:
+    case DCACHE_ITLB_INVAL:
+    {
+        if ( !r_dcache_xtn_req ) 
+        {
+            r_dcache_fsm = DCACHE_IDLE;
+            drsp.valid = true;
+        }
+        break;
+    }
+    ////////////////////////
+    case DCACHE_DCACHE_FLUSH:
+    {
+        // external cache invalidate request
+        if ( r_tgt_dcache_req )
+        {
+            r_tgt_dcache_req = false;
+        }   
+
+        size_t way = r_dcache_way;
+        size_t set = r_dcache_set;
+        bool clean = false;
+        
+        m_cost_data_cache_flush_frz++;
+
+        // cache flush and send cleanup to external
+        if ( !r_dcache_cleanup_req )
+        {
+            paddr_t victim_index = 0;
+            for ( ; way < m_dcache_ways; way++ )
+            {    
+                for ( ; set < m_dcache_sets; set++ )
+                {  
+                    if ( r_dcache.flush(way, set, &victim_index) )
+                    {
+                        clean = true;
+                        r_dcache_cleanup_req = true;
+                        r_dcache_cleanup_line = victim_index;
+                        r_dcache_way = way + ((set+1)/m_dcache_sets);
+                        r_dcache_set = (set+1) % m_dcache_sets;
+                        break;
+                    }
+                }
+                if (clean) break;
+            }
+
+            if ((way == m_dcache_ways) && (set == m_dcache_sets) && !r_dcache_xtn_req ) 
+            {
+                // data TLB flush 
+                dcache_tlb.flush(true);      // global entries are not invalidated
+
+                for (size_t line = 0; line < m_dcache_ways*m_dcache_sets; line++)
+                {
+                    r_dcache_in_itlb[line] = false;
+                    r_dcache_in_dtlb[line] = false;
+                }
+
+                r_dcache_fsm = DCACHE_IDLE;
+                drsp.valid = true;
+                break;
+            }
+        }
+	break;
+    }
+    //////////////////////
+    case DCACHE_DTLB_INVAL: 
+    {
+        paddr_t victim_index = 0;
+        // clean indicate data tlb bit
+        if ( dcache_tlb.inval(r_dcache_wdata_save, &victim_index) )
+        {  
+            r_dcache.setinbit((paddr_t)(victim_index << (m_dcache_words+2)), r_dcache_in_dtlb, false); 
+        }
+        r_dcache_fsm = DCACHE_IDLE;
+        drsp.valid = true;
+        break;
+    }
+    ////////////////////////
+    case DCACHE_DCACHE_INVAL:
+    {
+        m_cpt_dcache_dir_read += m_dcache_ways;
+        vaddr_t invadr = dreq.wdata;
+        paddr_t dpaddr = 0;
+        bool dcache_hit_t = false; 
+        size_t way = 0;
+        size_t set = 0;
+
+	if ( !r_dcache_cleanup_req )
+	{
+            if ( r_mmu_mode.read() & DATA_TLB_MASK ) 
+            {
+                dcache_hit_t = dcache_tlb.translate(invadr, &dpaddr); 
+            } 
+            else 
+            {
+                dpaddr = invadr;  
+                dcache_hit_t = true;
+            }
+
+            if ( dcache_hit_t )
+            {
+		r_dcache_cleanup_req = r_dcache.inval(dpaddr, &way, &set);
+		r_dcache_cleanup_line = dpaddr >> (uint32_log2(m_dcache_words)+2);
+		
+		if ( r_dcache_in_itlb[way*m_dcache_sets+set] || r_dcache_in_dtlb[way*m_dcache_sets+set] ) 
+		{	
+		    // ins tlb invalidate verification
+		    r_dcache_itlb_inval_req = r_dcache_in_itlb[way*m_dcache_sets+set];
+		    r_dcache_itlb_inval_line = dpaddr >> (uint32_log2(m_dcache_words)+2);
+		    r_dcache_in_itlb[way*m_dcache_sets+set] = false;
+		
+		    // data tlb invalidate verification
+		    r_dcache_dtlb_inval_req = r_dcache_in_dtlb[way*m_dcache_sets+set];
+		    r_dcache_dtlb_inval_line = dpaddr >> (uint32_log2(m_dcache_words)+2);
+		    r_dcache_in_dtlb[way*m_dcache_sets+set] = false;
+		    r_dcache_fsm = DCACHE_TLB_CC_INVAL;
+		    r_dcache_fsm_save = r_dcache_fsm;
+		    break;
+		}
+            }
+            r_dcache_fsm = DCACHE_IDLE;
+            drsp.valid = true;
+	}
+        break;
+    }
+    /////////////////////////
+    case DCACHE_DCACHE_SYNC:
+    {
+        if ( !r_dcache_write_req ) 
+        {
+            r_dcache_write_req = r_wbuf.rok();
+            drsp.valid = true;
+            r_dcache_fsm = DCACHE_IDLE;
+        }    
+        break;
+    }
+    /////////////////////
+    case DCACHE_MISS_WAIT:
+    {
+        m_cost_data_miss_frz++; 
+
+        // external cache invalidate request
+        if ( r_tgt_dcache_req ) 
+        {
+            r_dcache_fsm = DCACHE_CC_CHECK;
+            r_dcache_fsm_save = r_dcache_fsm;
+            m_cost_data_waste_wait_frz++;
+            break;
+        }
+
+	if ( !r_dcache_miss_req )
+	{
+            if ( r_vci_rsp_data_error ) 
+            {
+                r_dcache_error_type = MMU_READ_DATA_ILLEGAL_ACCESS; 
+                r_dcache_bad_vaddr = dreq.addr;
+                r_dcache_fsm = DCACHE_ERROR;
+
+		if (r_dcache_inval_tlb_rsp) r_dcache_inval_tlb_rsp = false;
+		if (r_dcache_inval_rsp) r_dcache_inval_rsp = false;
+		break;
+            } 
+
+            if ( r_dcache_inval_tlb_rsp ) // Miss read response and tlb invalidation
+            {
+                r_dcache_fsm = DCACHE_IDLE;
+                r_dcache_inval_tlb_rsp = false;
+		break;
+            }	
+
+	    if ( r_dcache_inval_rsp ) // TLB miss response and cache invalidation
+	    {
+                r_dcache_fsm = DCACHE_IDLE; 
+            	r_dcache_inval_rsp = false;
+		break;	    
+	    }
+	    // Miss read response and no tlb invalidation
+	    r_dcache_fsm = DCACHE_MISS_UPDT;
+	}	
+        break;
+    }
+    /////////////////////
+    case DCACHE_MISS_UPDT:
+    {
+        m_cost_data_miss_frz++;
+
+        // external cache invalidate request
+        if ( r_tgt_dcache_req ) 
+        {
+            r_dcache_fsm = DCACHE_CC_CHECK;
+            r_dcache_fsm_save = r_dcache_fsm;
+            m_cost_data_waste_wait_frz++;
+            break;
+        }
+
+        if ( r_dcache_inval_tlb_rsp ) // tlb invalidation
+        {
+            r_dcache_inval_tlb_rsp = false;
+            r_dcache_fsm = DCACHE_IDLE;
+            m_cost_data_tlb_miss_frz++;
+            break;
+        }
+
+        // Using tlb entry is in the invalidated cache line  
+        if ( r_dcache_inval_rsp )
+        {
+            r_dcache_inval_rsp = false;
+            r_dcache_fsm = DCACHE_IDLE;
+            m_cost_data_tlb_miss_frz++;
+            break;
+        }
+
+        if (!r_dcache_cleanup_req ) // Miss update and no invalidation
+        {
+            paddr_t  victim_index = 0;
+            size_t way = 0;
+            size_t set = 0;
+
+	    m_cpt_dcache_data_write++;
+            m_cpt_dcache_dir_write++;
+
+            bool cleanup_req = r_dcache.find(r_dcache_paddr_save.read(), r_dcache_in_itlb, r_dcache_in_dtlb, &way, &set, &victim_index);
+
+	    if ( cleanup_req )
+	    {	    
+		// ins tlb invalidate verification    
+                r_dcache_itlb_inval_req = r_dcache_in_itlb[m_dcache_sets*way+set];
+                r_dcache_itlb_inval_line = victim_index;
+                r_dcache_in_itlb[way*m_dcache_sets+set] = false;
+
+                // data tlb invalidate verification
+                r_dcache_dtlb_inval_req = r_dcache_in_dtlb[m_dcache_sets*way+set]; 
+                r_dcache_dtlb_inval_line = victim_index;
+                r_dcache_in_dtlb[way*m_dcache_sets+set] = false;
+
+                r_dcache_cleanup_req = true; 
+                r_dcache_cleanup_line = victim_index;
+		r_dcache_fsm = DCACHE_TLB_CC_INVAL;
+                r_dcache_fsm_save = r_dcache_fsm;
+		break;
+	    }
+
+	    r_dcache.update(r_dcache_paddr_save.read(), way, set, r_dcache_miss_buf);
+            r_dcache_fsm = DCACHE_IDLE;
+        }
+	break;
+    }
+    //////////////////////
+    case DCACHE_UNC_WAIT:
+    {
+        m_cost_unc_read_frz++;
+
+        // external cache invalidate request
+        if ( r_tgt_dcache_req ) 
+        {
+            r_dcache_fsm = DCACHE_CC_CHECK;
+            r_dcache_fsm_save = r_dcache_fsm;
+            m_cost_data_waste_wait_frz++;
+            break;
+        }
+
+	if ( !r_dcache_unc_req )
+	{
+            if ( r_vci_rsp_data_error ) 
+            {
+                r_dcache_error_type = MMU_READ_DATA_ILLEGAL_ACCESS; 
+                r_dcache_bad_vaddr = dreq.addr;
+                r_dcache_fsm = DCACHE_ERROR;
+
+		if (r_dcache_inval_tlb_rsp) r_dcache_inval_tlb_rsp = false;
+		//if (r_dcache_inval_rsp) r_dcache_inval_rsp = false;
+		break;
+            }
+
+            if ( r_dcache_inval_tlb_rsp ) // Miss read response and tlb invalidation
+            {
+                r_dcache_fsm = DCACHE_IDLE;
+                r_dcache_inval_tlb_rsp = false;
+		break;
+            }
+/*
+	    if ( r_dcache_inval_rsp ) // TLB miss response and cache invalidation
+	    {
+                r_dcache_fsm = DCACHE_IDLE; 
+            	r_dcache_inval_rsp = false;
+
+		if ((dreq.type == iss_t::DATA_LL) || (dreq.type == iss_t::DATA_SC))
+		{
+        	    r_dcache_buf_unc_valid = false;
+		    r_dcache_llsc_reserved = false;
+		}
+		break;	    
+	    }
+*/  
+            if(dreq.type == iss_t::DATA_SC) 
+	    {
+                // Simulate an invalidate request
+                r_dcache.inval(r_dcache_paddr_save);
+            }		
+            r_dcache_buf_unc_valid = true;
+	    r_dcache_fsm = DCACHE_IDLE;
+	}	
+        break;
+    }
+    ///////////////////////
+    case DCACHE_WRITE_UPDT:
+    {
+        m_cost_write_frz++;
+        size_t way = 0;
+        size_t set = 0;
+	bool write_hit = false;
+        data_t mask = vci_param::be2mask(r_dcache_be_save.read());
+        data_t wdata = (mask & r_dcache_wdata_save) | (~mask & r_dcache_rdata_save);
+        write_hit = r_dcache.write(r_dcache_paddr_save, wdata, &way, &set);
+        assert(write_hit && "Write on miss ignores data");
+        
+        if (r_dcache_in_itlb[way*m_dcache_sets+set] || r_dcache_in_dtlb[m_dcache_sets*way+set])
+        {
+	    // ins tlb invalidate verification    
+            r_dcache_itlb_inval_req = r_dcache_in_itlb[m_dcache_sets*way+set];
+            r_dcache_itlb_inval_line = (r_dcache.get_tag(way, set) * m_dcache_sets) + set;
+            r_dcache_in_itlb[way*m_dcache_sets+set] = false;
+
+            // data tlb invalidate verification
+            r_dcache_dtlb_inval_req = r_dcache_in_dtlb[m_dcache_sets*way+set]; 
+            r_dcache_dtlb_inval_line = (r_dcache.get_tag(way, set) * m_dcache_sets) + set;
+            r_dcache_in_dtlb[way*m_dcache_sets+set] = false;
+
+            r_dcache_cleanup_req = true; 
+            r_dcache_cleanup_line = (r_dcache.get_tag(way, set) * m_dcache_sets) + set;
+	    r_dcache_fsm = DCACHE_TLB_CC_INVAL;
+            r_dcache_fsm_save = r_dcache_fsm;
+            break;
+	}
+
+        if ( !r_dcache_dirty_save && (r_mmu_mode.read() & DATA_TLB_MASK) )   
+        {
+            if ( dcache_tlb.getpagesize(r_dcache_tlb_way_save, r_dcache_tlb_set_save) )	// 2M page size, one level page table 
+            {
+                r_dcache_pte_update = dcache_tlb.getpte(r_dcache_tlb_way_save, r_dcache_tlb_set_save) | PTE_D_MASK;
+                r_dcache_tlb_paddr = (paddr_t)r_mmu_ptpr << (INDEX1_NBITS+2) | (paddr_t)((dreq.addr>>PAGE_M_NBITS)<<2);
+                write_hit = r_dcache.write((paddr_t)r_mmu_ptpr << (INDEX1_NBITS+2) | (paddr_t)((dreq.addr>>PAGE_M_NBITS)<<2), 
+                                     (dcache_tlb.getpte(r_dcache_tlb_way_save, r_dcache_tlb_set_save) | PTE_D_MASK));
+                assert(write_hit && "Write on miss ignores data");
+                r_dcache_tlb_ll_dirty_req = true;
+                r_dcache_fsm = DCACHE_LL_DIRTY_WAIT;
+                m_cpt_data_tlb_write_dirty++;
+            }
+            else
+            {   
+                if (r_dcache_hit_p_save) 
+                {
+                    r_dcache_pte_update = dcache_tlb.getpte(r_dcache_tlb_way_save, r_dcache_tlb_set_save) | PTE_D_MASK;
+                    r_dcache_tlb_paddr = (paddr_t)r_dcache_ptba_save|(paddr_t)(((dreq.addr&PTD_ID2_MASK)>>PAGE_K_NBITS) << 3);
+                    write_hit = r_dcache.write(((paddr_t)r_dcache_ptba_save|(paddr_t)(((dreq.addr&PTD_ID2_MASK)>>PAGE_K_NBITS) << 3)), 
+                                     (dcache_tlb.getpte(r_dcache_tlb_way_save, r_dcache_tlb_set_save) | PTE_D_MASK));
+                    assert(write_hit && "Write on miss ignores data");
+                    r_dcache_tlb_ll_dirty_req = true;
+                    r_dcache_fsm = DCACHE_LL_DIRTY_WAIT;
+                    m_cpt_data_tlb_write_dirty++;
+                }
+                else
+                {
+                    r_dcache_pte_update = dcache_tlb.getpte(r_dcache_tlb_way_save, r_dcache_tlb_set_save) | PTE_D_MASK;
+                    r_dcache_tlb_paddr = (paddr_t)r_mmu_ptpr << (INDEX1_NBITS+2) | (paddr_t)((dreq.addr>>PAGE_M_NBITS)<<2);
+                    r_dcache_tlb_ptba_read = true;
+                    r_dcache_fsm = DCACHE_DTLB1_READ_CACHE;
+                }
+            }
+        }
+        else
+        {
+            r_dcache_fsm = DCACHE_WRITE_REQ;
+            drsp.valid = true;
+            drsp.rdata = 0;
+        }
+        break;
+    }
+    ////////////////////////
+    case DCACHE_WRITE_DIRTY:
+    {
+        m_cost_data_tlb_miss_frz++;
+
+        // external cache invalidate request
+        if ( r_tgt_dcache_req ) 
+        {
+            r_dcache_fsm = DCACHE_CC_CHECK;
+            r_dcache_fsm_save = r_dcache_fsm;
+            m_cost_data_waste_wait_frz++;
+            break;
+        }
+
+        if ( r_dcache_inval_tlb_rsp ) // Miss read response and tlb invalidation
+        {
+            r_dcache_fsm = DCACHE_IDLE;
+            r_dcache_inval_tlb_rsp = false;
+	    break;
+        }
+
+	if ( r_dcache_inval_rsp ) // TLB miss response and cache invalidation
+	{
+            r_dcache_fsm = DCACHE_IDLE; 
+            r_dcache_inval_rsp = false;
+	    break;	    
+	}
+
+        dcache_tlb.setdirty(r_dcache_tlb_way_save, r_dcache_tlb_set_save);
+        r_dcache_fsm = DCACHE_WRITE_REQ;
+        drsp.valid = true;
+        drsp.rdata = 0;
+        break;
+    }
+    /////////////////
+    case DCACHE_ERROR:
+    {
+        r_vci_rsp_data_error = false;
+        drsp.valid = true;
+        drsp.error = true;
+        drsp.rdata = 0;
+        r_dcache_fsm = DCACHE_IDLE;
+        break;
+    }   
+    ////////////////////// 
+    case DCACHE_ITLB_READ:
+    {
+        m_cost_data_waste_wait_frz++;
+
+        // external cache invalidate request
+        if ( r_tgt_dcache_req ) 
+        {
+            r_dcache_fsm = DCACHE_CC_CHECK;
+            r_dcache_fsm_save = r_dcache_fsm;
+            m_cost_data_waste_wait_frz++;
+            break;
+        }
+
+    	if ( !r_dcache_itlb_read_req ) // vci response ok
+        {  
+            if ( r_vci_rsp_data_error )
+            {
+                r_dcache_rsp_itlb_error = true;	
+                r_itlb_read_dcache_req = false;
+                r_vci_rsp_data_error = false;
+                r_dcache_fsm = DCACHE_IDLE;
+
+		if (r_dcache_inval_rsp) r_dcache_inval_rsp = false;
+		break;
+            }
+
+	    if ( r_dcache_inval_rsp ) // TLB miss response and cache invalidation
+	    {
+                r_dcache_fsm = DCACHE_IDLE; 
+            	r_dcache_inval_rsp = false;
+		break;	    
+	    }
+            r_dcache_fsm = DCACHE_ITLB_UPDT;
+        }
+	break;    	
+    }
+    //////////////////////
+    case DCACHE_ITLB_UPDT:
+    {
+        m_cost_data_waste_wait_frz++;
+
+        // external cache invalidate request
+        if ( r_tgt_dcache_req ) 
+        {
+            r_dcache_fsm = DCACHE_CC_CHECK;
+            r_dcache_fsm_save = r_dcache_fsm;
+            m_cost_data_waste_wait_frz++;
+            break;
+        }
+
+        // Using tlb entry is in the invalidated cache line  
+        if ( r_dcache_inval_rsp )
+        {
+            r_dcache_inval_rsp = false;
+            r_dcache_fsm = DCACHE_IDLE;
+            m_cost_data_tlb_miss_frz++;
+            break;
+        }
+
+        if ( !r_dcache_cleanup_req )
+        {
+            data_t rsp_itlb_miss = 0;
+	    data_t rsp_itlb_ppn = 0;
+
+            paddr_t  victim_index = 0;
+            size_t way = 0;
+            size_t set = 0;
+            
+            bool cleanup = r_dcache.find(r_icache_paddr_save, r_dcache_in_itlb, r_dcache_in_dtlb, &way, &set, &victim_index);
+
+	    if ( cleanup )
+	    {	    
+		// ins tlb invalidate verification    
+                r_dcache_itlb_inval_req = r_dcache_in_itlb[m_dcache_sets*way+set];
+                r_dcache_itlb_inval_line = victim_index;
+                r_dcache_in_itlb[way*m_dcache_sets+set] = false;
+
+                // data tlb invalidate verification
+                r_dcache_dtlb_inval_req = r_dcache_in_dtlb[m_dcache_sets*way+set]; 
+                r_dcache_dtlb_inval_line = victim_index;
+                r_dcache_in_dtlb[way*m_dcache_sets+set] = false;
+
+                r_dcache_cleanup_req = true; 
+                r_dcache_cleanup_line = victim_index;
+		r_dcache_fsm = DCACHE_TLB_CC_INVAL;
+                r_dcache_fsm_save = r_dcache_fsm;
+		break;
+	    }
+
+            r_dcache.update(r_icache_paddr_save, way, set, r_dcache_miss_buf);
+
+            r_dcache.setinbit(r_icache_paddr_save, r_dcache_in_itlb, true);
+            bool itlb_hit_dcache = r_dcache.read(r_icache_paddr_save, &rsp_itlb_miss);	
+ 
+	    if ( (r_icache_fsm == ICACHE_TLB2_READ) && itlb_hit_dcache )
+	    {	
+            	bool itlb_hit_ppn = r_dcache.read(r_icache_paddr_save.read()+4, &rsp_itlb_ppn);
+		assert(itlb_hit_ppn && "Address of pte[64-32] and pte[31-0] should be successive");
+	    }
+
+            r_dcache_rsp_itlb_miss = rsp_itlb_miss;
+            r_dcache_rsp_itlb_ppn = rsp_itlb_ppn;
+            r_dcache_rsp_itlb_error = false;	
+            r_itlb_read_dcache_req = false;
+            r_dcache_fsm = DCACHE_IDLE;
+        }
+        break;
+    }
+    //////////////////////////
+    case DCACHE_ITLB_LL_WAIT:
+    {
+        // external cache invalidate request
+        if ( r_tgt_dcache_req )   
+        {
+            r_dcache_fsm = DCACHE_CC_CHECK;
+            r_dcache_fsm_save = r_dcache_fsm;
+            m_cost_data_waste_wait_frz++;
+            break;
+        }
+
+	if (!r_dcache_itlb_ll_acc_req)
+	{
+            if ( r_vci_rsp_data_error ) // VCI response ko
+            {
+                r_dcache_rsp_itlb_error = true;  
+                r_vci_rsp_data_error = false;
+                r_itlb_acc_dcache_req = false;
+		r_dcache_fsm = DCACHE_IDLE;
+		if (r_dcache_inval_rsp) r_dcache_inval_rsp = false;	
+            }
+	    else
+	    {
+	        if ( !(r_dcache_miss_buf[0] >> PTE_V_SHIFT) )	// unmapped
+	        {
+                    r_dcache_rsp_itlb_error = true;  
+                    r_itlb_acc_dcache_req = false;
+		    r_dcache_fsm = DCACHE_IDLE;	
+		    if (r_dcache_inval_rsp) r_dcache_inval_rsp = false;	
+	        }
+       		else if ( r_dcache_inval_rsp )
+       		{
+       		    r_dcache_inval_rsp = false;
+       		    r_dcache_fsm = DCACHE_IDLE;
+       		    m_cost_data_tlb_miss_frz++;
+       		}
+		else
+		{
+		    r_dcache_itlb_sc_acc_req = true;
+		    r_icache_pte_update = r_dcache_miss_buf[0] | r_icache_pte_update.read();	
+                    r_dcache_fsm = DCACHE_ITLB_SC_WAIT; 
+		}
+	    }
+	}
+	break;
+    }
+    //////////////////////////
+    case DCACHE_ITLB_SC_WAIT:
+    {
+        // external cache invalidate request
+        if ( r_tgt_dcache_req )   
+        {
+            r_dcache_fsm = DCACHE_CC_CHECK;
+            r_dcache_fsm_save = r_dcache_fsm;
+            m_cost_data_waste_wait_frz++;
+            break;
+        }
+	
+        if ( !r_dcache_itlb_sc_acc_req ) 
+	{
+	    if ( r_vci_rsp_data_error ) // VCI response ko
+	    {
+	        r_dcache_rsp_itlb_error = true;  
+	        r_vci_rsp_data_error = false;
+	        r_itlb_acc_dcache_req = false;
+	        r_dcache_fsm = DCACHE_IDLE;
+		if (r_dcache_inval_rsp) r_dcache_inval_rsp = false;		
+	    }
+	    else
+	    {
+	        if ( r_dcache_inval_rsp )
+	        {
+	            r_dcache_inval_rsp = false;
+	            r_dcache_fsm = DCACHE_IDLE;
+	            m_cost_data_tlb_miss_frz++;
+	        }
+	        else if ( r_dcache_itlb_ll_acc_req )
+	        {
+	            r_dcache_fsm = DCACHE_ITLB_LL_WAIT; 
+	        }
+	        else 
+	        {
+	            r_itlb_acc_dcache_req = false;
+	            r_dcache_fsm = DCACHE_IDLE; 
+	        }
+	    }
+	}
+	break;
+    }
+    /////////////////////
+    case DCACHE_CC_CHECK:   // read directory in case of invalidate or update request
+    {
+        if ( dreq.valid ) m_cost_data_waste_wait_frz++;
+
+        m_cpt_dcache_dir_read += m_dcache_ways;
+        m_cpt_dcache_data_read += m_dcache_ways;
+
+        data_t dcache_rdata = 0;
+        size_t way = 0;
+        size_t set = 0;
+
+        bool dcache_hit = r_dcache.read(r_tgt_addr.read(), &dcache_rdata, &way, &set);
+
+        if ( dcache_hit )
+        {
+            if ( r_dcache_in_dtlb[m_dcache_sets*way+set] || r_dcache_in_itlb[m_dcache_sets*way+set] )
+	    {
+		// ins tlb invalidate verification    
+                r_dcache_itlb_inval_req = r_dcache_in_itlb[m_dcache_sets*way+set];
+                r_dcache_itlb_inval_line = r_tgt_addr.read() >> (uint32_log2(m_dcache_words)+2);
+                r_dcache_in_itlb[way*m_dcache_sets+set] = false;
+
+                // data tlb invalidate verification
+                r_dcache_dtlb_inval_req = r_dcache_in_dtlb[m_dcache_sets*way+set]; 
+                r_dcache_dtlb_inval_line = r_tgt_addr.read() >> (uint32_log2(m_dcache_words)+2);
+                r_dcache_in_dtlb[way*m_dcache_sets+set] = false;
+		
+		r_dcache_cc_check = true;
+		r_dcache_fsm = DCACHE_TLB_CC_INVAL;
+		break;
+	    }
+
+            if(( /*( r_dcache_fsm_save == DCACHE_UNC_WAIT ) ||*/
+	         ( r_dcache_fsm_save == DCACHE_MISS_WAIT ) || ( r_dcache_fsm_save == DCACHE_MISS_UPDT ) ) && 
+               ( (r_dcache_paddr_save.read() & ~((m_dcache_words<<2)-1)) == (r_tgt_addr.read() & ~((m_dcache_words<<2)-1)))) 
+            {
+	        r_dcache_inval_rsp = true;
+            } 
+
+            if(( ( r_dcache_fsm_save == DCACHE_TLB1_READ )      || ( r_dcache_fsm_save == DCACHE_TLB2_READ )      ||
+		 ( r_dcache_fsm_save == DCACHE_TLB1_READ_UPDT ) || ( r_dcache_fsm_save == DCACHE_TLB2_READ_UPDT ) ||
+                 ( r_dcache_fsm_save == DCACHE_TLB1_UPDT )      || ( r_dcache_fsm_save == DCACHE_TLB2_UPDT )	  ||
+		 ( r_dcache_fsm_save == DCACHE_TLB1_LL_WAIT )   || ( r_dcache_fsm_save == DCACHE_TLB2_LL_WAIT )   ||
+		 ( r_dcache_fsm_save == DCACHE_TLB1_SC_WAIT )   || ( r_dcache_fsm_save == DCACHE_TLB2_SC_WAIT )   ||
+		 ( r_dcache_fsm_save == DCACHE_LL_DIRTY_WAIT )  || ( r_dcache_fsm_save == DCACHE_SC_DIRTY_WAIT )  ||
+		 ( r_dcache_fsm_save == DCACHE_WRITE_DIRTY ) ) && 
+               ( (r_dcache_tlb_paddr.read() & ~((m_dcache_words<<2)-1)) == (r_tgt_addr.read() & ~((m_dcache_words<<2)-1))) ) 
+            {
+                r_dcache_inval_rsp = true;
+            }
+
+            if(( ( r_dcache_fsm_save == DCACHE_ITLB_READ ) || ( r_dcache_fsm_save == DCACHE_ITLB_UPDT ) ||
+                 ( r_dcache_fsm_save == DCACHE_ITLB_LL_WAIT ) || ( r_dcache_fsm_save == DCACHE_ITLB_SC_WAIT ) ) && 
+               ( (r_icache_paddr_save.read() & ~((m_dcache_words<<2)-1)) == (r_tgt_addr.read() & ~((m_dcache_words<<2)-1))) ) 
+            {
+                r_dcache_inval_rsp = true;
+            }
+
+            if ( r_tgt_update ) // update 
+            {
+                r_dcache_fsm = DCACHE_CC_UPDT;
+            } 
+            else                // invalidate 
+            {
+                r_dcache_fsm = DCACHE_CC_INVAL;
+            }
+        }
+        else                    // nothing
+        {
+            r_dcache_fsm = DCACHE_CC_NOP;
+        }
+        break;
+    }
+    ///////////////////
+    case DCACHE_CC_UPDT:    // update directory and data cache        
+    {
+        if ( dreq.valid ) m_cost_data_waste_wait_frz++;
+
+        m_cpt_dcache_dir_write++;
+        m_cpt_dcache_data_write++;
+        data_t* buf = r_tgt_buf;
+        for( size_t i = 0; i < m_dcache_words; i++ )
+        {
+            if( r_tgt_val[i] ) r_dcache.write( r_tgt_addr.read() + i*4, buf[i] );
+        }
+           
+        r_tgt_dcache_req = false;
+        r_dcache_fsm = r_dcache_fsm_save;
+        break;
+    }
+    /////////////////////
+    case DCACHE_CC_INVAL:   // invalidate a cache line
+    {
+        if ( dreq.valid ) m_cost_data_waste_wait_frz++;
+
+        r_tgt_dcache_rsp = r_dcache.inval(r_tgt_addr.read());
+        r_tgt_dcache_req = false;
+        r_dcache_fsm = r_dcache_fsm_save;
+        break;
+    }
+    ///////////////////
+    case DCACHE_CC_NOP:     // no external hit
+    {
+        if ( dreq.valid ) m_cost_data_waste_wait_frz++;
+
+        r_tgt_dcache_req = false;
+        r_dcache_fsm = r_dcache_fsm_save;
+        break;
+    }   
+    /////////////////////////
+    case DCACHE_TLB_CC_INVAL:
+    {
+        if ( dreq.valid ) m_cost_data_waste_wait_frz++;
+
+	if ( r_dcache_itlb_inval_req || r_dcache_dtlb_inval_req ) break;
+
+        if( (( r_dcache_fsm_save == DCACHE_TLB1_READ )        || ( r_dcache_fsm_save == DCACHE_TLB2_READ )        ||
+             ( r_dcache_fsm_save == DCACHE_TLB1_READ_UPDT )   || ( r_dcache_fsm_save == DCACHE_TLB2_READ_UPDT )   ||
+             ( r_dcache_fsm_save == DCACHE_TLB1_LL_WAIT )     || ( r_dcache_fsm_save == DCACHE_TLB2_LL_WAIT )     ||
+             ( r_dcache_fsm_save == DCACHE_TLB1_SC_WAIT )     || ( r_dcache_fsm_save == DCACHE_TLB2_SC_WAIT )     ||
+             ( r_dcache_fsm_save == DCACHE_TLB1_UPDT )        || ( r_dcache_fsm_save == DCACHE_TLB2_UPDT )        ||
+             ( r_dcache_fsm_save == DCACHE_DTLB1_READ_CACHE ) || ( r_dcache_fsm_save == DCACHE_DTLB2_READ_CACHE ) ||
+             ( r_dcache_fsm_save == DCACHE_LL_DIRTY_WAIT )    || ( r_dcache_fsm_save == DCACHE_SC_DIRTY_WAIT )    ||
+	     ( r_dcache_fsm_save == DCACHE_WRITE_DIRTY )) && 
+            (((r_dcache_tlb_paddr.read() & ~((m_dcache_words<<2)-1)) >> (uint32_log2(m_dcache_words) + 2)) == r_dcache_dtlb_inval_line.read()) ) 
+        {
+            r_dcache_inval_tlb_rsp = true;
+        } 
+
+        if (((r_dcache_fsm_save == DCACHE_BIS)||(r_dcache_fsm_save == DCACHE_MISS_WAIT) ||
+             (r_dcache_fsm_save == DCACHE_UNC_WAIT)||(r_dcache_fsm_save == DCACHE_MISS_UPDT)) && 
+             (r_dcache_tlb_nline == r_dcache_dtlb_inval_line))
+        {
+            r_dcache_inval_tlb_rsp = true;
+        }
+
+	if ( !r_dcache_cc_check )
+	{
+            r_dcache_fsm = r_dcache_fsm_save;
+	}
+	else
+	{
+            r_dcache_fsm = DCACHE_CC_CHECK;
+	    r_dcache_cc_check = false;
+	}
+        break;
+    }
+    /////////////////////////
+    case DCACHE_ITLB_CLEANUP:
+    {
+        if ( dreq.valid ) m_cost_data_waste_wait_frz++;
+
+        r_dcache.setinbit(((paddr_t)r_dcache_itlb_cleanup_line.read()*m_dcache_words*2), r_dcache_in_itlb, false);
+        r_dcache_itlb_cleanup_req = false;
+        r_dcache_fsm = DCACHE_IDLE;
+        break;
+    }
+    } // end switch r_dcache_fsm
+
+#ifdef SOCLIB_MODULE_DEBUG
+    std::cout << name() << " Data Response: " << drsp << std::endl;
+#endif
+
+    ////////////////////////////////////////////////////////////////////////////////////
+    //      INVAL DTLB CHECK FSM 
+    ////////////////////////////////////////////////////////////////////////////////////////
+    switch(r_inval_dtlb_fsm) {
+    /////////////////////
+    case INVAL_DTLB_IDLE:
+    {
+        if ( r_dcache_dtlb_inval_req ) 
+        {
+            r_ccinval_dtlb_way = 0;
+            r_ccinval_dtlb_set = 0;
+            r_inval_dtlb_fsm = INVAL_DTLB_CHECK;    
+            m_cost_data_tlb_inval_frz++;
+        }   
+        break;
+    }
+    ////////////////////////////
+    case INVAL_DTLB_CHECK:
+    {
+        m_cost_data_tlb_inval_frz++;
+
+        size_t way = r_ccinval_dtlb_way; 
+        size_t set = r_ccinval_dtlb_set;
+        bool end = false;        
+        bool tlb_hit = dcache_tlb.cccheck(r_dcache_dtlb_inval_line.read(), way, set, &way, &set, &end); 
+    
+        if ( tlb_hit )
+        {
+            r_ccinval_dtlb_way = way; 
+            r_ccinval_dtlb_set = set;
+            r_dtlb_cc_check_end = end;
+            r_inval_dtlb_fsm = INVAL_DTLB_INVAL;
+            m_cpt_data_tlb_inval++;    
+        }        
+        else
+        {
+            r_inval_dtlb_fsm = INVAL_DTLB_CLEAR;    
+        }
+        break;
+    }
+    /////////////////////////
+    case INVAL_DTLB_INVAL:
+    {
+        m_cost_data_tlb_inval_frz++;
+
+        dcache_tlb.ccinval(r_ccinval_dtlb_way, r_ccinval_dtlb_set);
+
+        if ( !r_dtlb_cc_check_end )
+        {
+            r_inval_dtlb_fsm = INVAL_DTLB_CHECK; 
+        }
+        else
+        {
+            r_inval_dtlb_fsm = INVAL_DTLB_CLEAR;    
+        }
+        break;
+    }
+    ////////////////////
+    case INVAL_DTLB_CLEAR:
+    {
+        r_dcache_dtlb_inval_req = false;
+        r_dtlb_cc_check_end = false;
+        r_ccinval_dtlb_way = 0; 
+        r_ccinval_dtlb_set = 0; 
+        r_inval_dtlb_fsm = INVAL_DTLB_IDLE;   
+        m_cpt_data_tlb_inval++;    
+        break;
+    }
+    } // end switch r_inval_itlb_fsm
+
+    /////////// execute one iss cycle /////////////////////////////////
+    {
+    uint32_t it = 0;
+    for (size_t i=0; i<(size_t)iss_t::n_irq; i++) if(p_irq[i].read()) it |= (1<<i);
+    m_iss.executeNCycles(1, irsp, drsp, it);
+    }
+
+    ////////////// number of frozen cycles //////////////////////////
+    if ( (ireq.valid && !irsp.valid) || (dreq.valid && !drsp.valid) )
+    {
+        m_cpt_frz_cycles++;
+    }
+
+    ////////////////////////////////////////////////////////////////////////////
+    //     VCI_CMD FSM 
+    //
+    // This FSM handles requests from both the DCACHE controler
+    // (request registers) and the ICACHE controler (request registers).
+    // There is 10 VCI transaction types :
+    // - INS_TLB_READ
+    // - INS_TLB_WRITE
+    // - INS_MISS
+    // - INS_UNC_MISS
+    // - DATA_TLB_READ
+    // - DATA_TLB_WRITE
+    // - DATA_TLB_DIRTY
+    // - DATA_MISS
+    // - DATA_UNC 
+    // - DATA_WRITE
+    // The ICACHE requests have the highest priority.
+    // There is at most one (CMD/RSP) VCI transaction, as both CMD_FSM and RSP_FSM
+    // exit simultaneously the IDLE state.
+    //////////////////////////////////////////////////////////////////////////////
+
+    switch (r_vci_cmd_fsm) {
+    
+    case CMD_IDLE:
+        if (r_vci_rsp_fsm != RSP_IDLE)
+            break;
+
+        r_vci_cmd_cpt = 0;
+
+        if (r_dcache_itlb_read_req)           
+        {            
+            r_vci_cmd_fsm = CMD_ITLB_READ;
+            m_cpt_itlbmiss_transaction++; 
+        } 
+	else if (r_dcache_itlb_ll_acc_req)
+	{
+	    r_vci_cmd_fsm = CMD_ITLB_ACC_LL;
+            m_cpt_itlb_write_transaction++; 
+	}
+	else if (r_dcache_itlb_sc_acc_req)
+	{
+	    r_vci_cmd_fsm = CMD_ITLB_ACC_SC;
+            m_cpt_itlb_write_transaction++; 
+	}
+        else if (r_icache_miss_req) 
+        {    
+            r_vci_cmd_fsm = CMD_INS_MISS;
+            m_cpt_imiss_transaction++; 
+        }
+        else if (r_icache_unc_req) 
+        {    
+            r_vci_cmd_fsm = CMD_INS_UNC;
+            m_cpt_imiss_transaction++; 
+        }  
+        else if (r_dcache_tlb_read_req) 
+        {            
+            r_vci_cmd_fsm = CMD_DTLB_READ;
+            m_cpt_dtlbmiss_transaction++; 
+        } 
+        else if (r_dcache_tlb_ll_acc_req) 
+        {  
+            r_vci_cmd_fsm = CMD_DTLB_ACC_LL;
+            m_cpt_dtlb_write_transaction++; 
+        } 
+        else if (r_dcache_tlb_sc_acc_req) 
+        {  
+            r_vci_cmd_fsm = CMD_DTLB_ACC_SC;
+            m_cpt_dtlb_write_transaction++; 
+        } 
+        else if (r_dcache_tlb_ll_dirty_req) 
+        {  
+            r_vci_cmd_fsm = CMD_DTLB_DIRTY_LL;
+            m_cpt_dtlb_write_transaction++; 
+        } 
+        else if (r_dcache_tlb_sc_dirty_req) 
+        {  
+            r_vci_cmd_fsm = CMD_DTLB_DIRTY_SC;
+            m_cpt_dtlb_write_transaction++; 
+        } 
+        else if (r_dcache_write_req)
+        {
+            r_vci_cmd_fsm = CMD_DATA_WRITE;
+            r_vci_cmd_cpt = r_wbuf.getMin();
+            r_vci_cmd_min = r_wbuf.getMin();
+            r_vci_cmd_max = r_wbuf.getMax(); 
+            m_cpt_write_transaction++; 
+            m_length_write_transaction += (r_wbuf.getMax() - r_wbuf.getMin() + 1);
+        }
+        else if (r_dcache_miss_req)  
+        {
+            r_vci_cmd_fsm = CMD_DATA_MISS;
+            m_cpt_dmiss_transaction++; 
+        }
+        else if (r_dcache_unc_req)  
+        {
+            r_vci_cmd_fsm = CMD_DATA_UNC;
+            m_cpt_unc_transaction++; 
+        }
+        break;
+
+    case CMD_DATA_WRITE:
+        if ( p_vci_ini_rw.cmdack.read() ) 
+        {
+            r_vci_cmd_cpt = r_vci_cmd_cpt + 1;
+            if (r_vci_cmd_cpt == r_vci_cmd_max) 
+            {
+                r_vci_cmd_fsm = CMD_IDLE;
+                r_wbuf.reset();
+            }
+        }
+        break;
+
+    default:
+        if ( p_vci_ini_rw.cmdack.read() )
+        {  
+            r_vci_cmd_fsm = CMD_IDLE;
+        }
+        break;
+
+    } // end  switch r_vci_cmd_fsm
+
+    //////////////////////////////////////////////////////////////////////////
+    //      VCI_RSP FSM 
+    //
+    // This FSM is synchronized with the VCI_CMD FSM, as both FSMs exit the
+    // IDLE state simultaneously.
+    //////////////////////////////////////////////////////////////////////////
+
+    switch (r_vci_rsp_fsm) {
+
+    case RSP_IDLE:
+        assert( ! p_vci_ini_rw.rspval.read() && "Unexpected response" );
+
+        if (r_vci_cmd_fsm != CMD_IDLE)
+            break;
+
+        r_vci_rsp_cpt = 0;
+        if (r_dcache_itlb_read_req)          // ITLB miss response
+        {            
+            r_vci_rsp_fsm = RSP_ITLB_READ;
+        } 
+        else if (r_dcache_itlb_ll_acc_req)   // ITLB linked load response
+        {   
+            r_vci_rsp_fsm = RSP_ITLB_ACC_LL;
+        } 
+        else if (r_dcache_itlb_sc_acc_req)   // ITLB store conditional response
+        {   
+            r_vci_rsp_fsm = RSP_ITLB_ACC_SC;
+        } 
+        else if (r_icache_miss_req)         // ICACHE cached miss response
+        {   
+            r_vci_rsp_fsm = RSP_INS_MISS;
+        }
+        else if (r_icache_unc_req)          // ICACHE uncached miss response
+        {   
+            r_vci_rsp_fsm = RSP_INS_UNC;
+        }  
+        else if (r_dcache_tlb_read_req)     // ITLB miss response
+        {
+            r_vci_rsp_fsm = RSP_DTLB_READ; 
+        }
+        else if (r_dcache_tlb_ll_acc_req)    // DTLB access bits linked load response
+        {
+            r_vci_rsp_fsm = RSP_DTLB_ACC_LL; 
+        }
+        else if (r_dcache_tlb_sc_acc_req)    // DTLB access bits store conditional response
+        {
+            r_vci_rsp_fsm = RSP_DTLB_ACC_SC; 
+        }
+        else if (r_dcache_tlb_ll_dirty_req)  // DTLB dirty bit linked load response
+        {
+            r_vci_rsp_fsm = RSP_DTLB_DIRTY_LL; 
+        }
+        else if (r_dcache_tlb_sc_dirty_req)  // DTLB dirty bit store conditional response
+        {
+            r_vci_rsp_fsm = RSP_DTLB_DIRTY_SC; 
+        }
+        else if (r_dcache_write_req)        // DCACHE write request
+        {
+            r_vci_rsp_fsm = RSP_DATA_WRITE;
+        }
+        else if (r_dcache_miss_req)         // DCACHE read request
+        {
+            r_vci_rsp_fsm = RSP_DATA_MISS;
+        }
+        else if (r_dcache_unc_req)          // DCACHE uncached read request
+        {
+            r_vci_rsp_fsm = RSP_DATA_UNC;
+        }
+        break;
+
+    case RSP_ITLB_READ:
+        m_cost_itlbmiss_transaction++;
+        if ( ! p_vci_ini_rw.rspval.read() )
+            break;
+
+        assert(r_vci_rsp_cpt != m_dcache_words &&
+               "illegal VCI response packet for data read miss");
+
+        r_vci_rsp_cpt = r_vci_rsp_cpt + 1;
+        r_dcache_miss_buf[r_vci_rsp_cpt] = (data_t)p_vci_ini_rw.rdata.read();
+
+        if ( p_vci_ini_rw.reop.read() ) 
+        {
+            assert(r_vci_rsp_cpt == m_dcache_words - 1 &&
+                    "illegal VCI response packet for data read miss");
+            r_dcache_itlb_read_req = false;
+            r_vci_rsp_fsm = RSP_IDLE;
+        } 
+        if ( p_vci_ini_rw.rerror.read() != vci_param::ERR_NORMAL )
+        {
+            r_vci_rsp_data_error = true;
+        }
+        break;
+
+    case RSP_ITLB_ACC_LL:
+        if ( ! p_vci_ini_rw.rspval.read() )
+            break;
+
+        assert(p_vci_ini_rw.reop.read() &&
+               "illegal VCI response packet for ll tlb");
+
+        if ( p_vci_ini_rw.rerror.read() != vci_param::ERR_NORMAL ) 
+        {
+            r_vci_rsp_data_error = true;
+        }
+	else
+	{
+	    r_dcache_miss_buf[0] = (data_t)p_vci_ini_rw.rdata.read();
+	}
+        r_dcache_itlb_ll_acc_req = false;
+        r_vci_rsp_fsm = RSP_IDLE;
+	break;
+
+    case RSP_ITLB_ACC_SC:
+        if ( ! p_vci_ini_rw.rspval.read() )
+            break;
+
+        assert(p_vci_ini_rw.reop.read() &&
+               "illegal VCI response packet for sc tlb");
+
+        if ( p_vci_ini_rw.rerror.read() != vci_param::ERR_NORMAL ) 
+        {
+            r_vci_rsp_data_error = true;
+        }
+	else if ( p_vci_ini_rw.rdata.read() == 1 ) // store conditional is not successful
+	{
+	    r_dcache_itlb_ll_acc_req = true;
+	}
+        r_dcache_itlb_sc_acc_req = false;
+        r_vci_rsp_fsm = RSP_IDLE;
+	break;
+
+    case RSP_INS_MISS:
+        m_cost_imiss_transaction++;
+        if ( ! p_vci_ini_rw.rspval.read() )
+            break;
+
+        assert( (r_vci_rsp_cpt < m_icache_words) && 
+               "The VCI response packet for instruction miss is too long");
+        r_vci_rsp_cpt = r_vci_rsp_cpt + 1;
+        r_icache_miss_buf[r_vci_rsp_cpt] = (data_t)p_vci_ini_rw.rdata.read();
+
+        if ( p_vci_ini_rw.reop.read() ) 
+        {
+            assert( (r_vci_rsp_cpt == m_icache_words - 1) &&
+                       "The VCI response packet for instruction miss is too short");
+            r_icache_miss_req = false;
+            r_vci_rsp_fsm = RSP_IDLE;
+                
+        } 
+        if ( p_vci_ini_rw.rerror.read() != vci_param::ERR_NORMAL )
+        {
+            r_vci_rsp_ins_error = true;
+        }
+        break;
+
+    case RSP_INS_UNC:
+        m_cost_imiss_transaction++;
+        if ( ! p_vci_ini_rw.rspval.read() )
+            break;
+
+        assert(p_vci_ini_rw.reop.read() &&
+               "illegal VCI response packet for uncached instruction");
+
+        r_icache_miss_buf[0] = (data_t)p_vci_ini_rw.rdata.read();
+        r_icache_buf_unc_valid = true;
+        r_icache_unc_req = false;
+        r_vci_rsp_fsm = RSP_IDLE;
+
+        if ( p_vci_ini_rw.rerror.read() != vci_param::ERR_NORMAL )
+        {
+            r_vci_rsp_ins_error = true;
+        }
+        break;
+
+    case RSP_DTLB_READ:
+        m_cost_dtlbmiss_transaction++;
+        if ( ! p_vci_ini_rw.rspval.read() )
+            break;
+
+        assert(r_vci_rsp_cpt != m_dcache_words &&
+               "illegal VCI response packet for data read miss");
+
+        r_vci_rsp_cpt = r_vci_rsp_cpt + 1;
+        r_dcache_miss_buf[r_vci_rsp_cpt] = (data_t)p_vci_ini_rw.rdata.read();
+        if ( p_vci_ini_rw.reop.read() ) 
+        {
+            assert(r_vci_rsp_cpt == m_dcache_words - 1 &&
+                    "illegal VCI response packet for data read miss");
+            r_dcache_tlb_read_req = false;
+            r_vci_rsp_fsm = RSP_IDLE;
+        } 
+        if ( p_vci_ini_rw.rerror.read() != vci_param::ERR_NORMAL )
+        {
+            r_vci_rsp_data_error = true;
+        }
+        break;
+
+    case RSP_DTLB_ACC_LL:
+        if ( ! p_vci_ini_rw.rspval.read() )
+            break;
+
+        assert(p_vci_ini_rw.reop.read() &&
+               "illegal VCI response packet for ll tlb");
+
+        if ( p_vci_ini_rw.rerror.read() != vci_param::ERR_NORMAL ) 
+        {
+            r_vci_rsp_data_error = true;
+        }
+	else
+	{
+	    r_dcache_miss_buf[0] = (data_t)p_vci_ini_rw.rdata.read();
+	}
+        r_dcache_tlb_ll_acc_req = false;
+        r_vci_rsp_fsm = RSP_IDLE;
+	break;
+
+    case RSP_DTLB_ACC_SC:
+        if ( ! p_vci_ini_rw.rspval.read() )
+            break;
+
+        assert(p_vci_ini_rw.reop.read() &&
+               "illegal VCI response packet for sc tlb");
+
+        if ( p_vci_ini_rw.rerror.read() != vci_param::ERR_NORMAL ) 
+        {
+            r_vci_rsp_data_error = true;
+        }
+	else if ( p_vci_ini_rw.rdata.read() == 1 ) // store conditional is not successful
+	{
+	    r_dcache_tlb_ll_acc_req = true;
+	}
+        r_dcache_tlb_sc_acc_req = false;
+        r_vci_rsp_fsm = RSP_IDLE;
+	break;
+
+    case RSP_DTLB_DIRTY_LL:
+        if ( ! p_vci_ini_rw.rspval.read() )
+            break;
+
+        assert(p_vci_ini_rw.reop.read() &&
+               "illegal VCI response packet for ll tlb");
+
+        if ( p_vci_ini_rw.rerror.read() != vci_param::ERR_NORMAL ) 
+        {
+            r_vci_rsp_data_error = true;
+        }
+	else
+	{
+	    r_dcache_miss_buf[0] = (data_t)p_vci_ini_rw.rdata.read();
+	}
+        r_dcache_tlb_ll_dirty_req = false;
+        r_vci_rsp_fsm = RSP_IDLE;
+	break;
+
+    case RSP_DTLB_DIRTY_SC:
+        if ( ! p_vci_ini_rw.rspval.read() )
+            break;
+
+        assert(p_vci_ini_rw.reop.read() &&
+               "illegal VCI response packet for sc tlb");
+
+        if ( p_vci_ini_rw.rerror.read() != vci_param::ERR_NORMAL ) 
+        {
+            r_vci_rsp_data_error = true;
+        }
+	else if ( p_vci_ini_rw.rdata.read() == 1 ) // store conditional is not successful
+	{
+	    r_dcache_tlb_ll_dirty_req = true;
+	}
+        r_dcache_tlb_sc_dirty_req = false;
+        r_vci_rsp_fsm = RSP_IDLE;
+	break;
+
+    case RSP_DATA_UNC:
+        m_cost_unc_transaction++;
+        if ( ! p_vci_ini_rw.rspval.read() ) 
+            break;
+
+        assert(p_vci_ini_rw.reop.read() &&
+               "illegal VCI response packet for data read uncached");
+
+        if ( p_vci_ini_rw.rerror.read() != vci_param::ERR_NORMAL ) 
+        {
+            r_vci_rsp_data_error = true;
+        }
+        else
+        {
+            r_dcache_miss_buf[0] = (data_t)p_vci_ini_rw.rdata.read();
+            r_dcache_buf_unc_valid = true;
+        }
+        r_dcache_unc_req = false;
+        r_vci_rsp_fsm = RSP_IDLE;
+        break;
+
+    case RSP_DATA_MISS:
+        m_cost_dmiss_transaction++;
+        if ( ! p_vci_ini_rw.rspval.read() )
+            break;
+
+        assert(r_vci_rsp_cpt != m_dcache_words &&
+               "illegal VCI response packet for data read miss");
+
+        r_vci_rsp_cpt = r_vci_rsp_cpt + 1;
+        r_dcache_miss_buf[r_vci_rsp_cpt] = (data_t)p_vci_ini_rw.rdata.read();
+        if ( p_vci_ini_rw.reop.read() ) 
+        {
+            assert(r_vci_rsp_cpt == m_dcache_words - 1 &&
+                    "illegal VCI response packet for data read miss");
+            r_dcache_miss_req = false;
+            r_vci_rsp_fsm = RSP_IDLE;
+        } 
+        if ( p_vci_ini_rw.rerror.read() != vci_param::ERR_NORMAL )
+        {
+            r_vci_rsp_data_error = true;
+        }
+        break;
+
+    case RSP_DATA_WRITE:
+        m_cost_write_transaction++;
+        if ( ! p_vci_ini_rw.rspval.read() )
+            break;
+
+        if ( p_vci_ini_rw.reop.read() ) 
+        {
+            r_vci_rsp_fsm = RSP_IDLE;
+            r_dcache_write_req = false;
+        }
+        if ( p_vci_ini_rw.rerror.read() != vci_param::ERR_NORMAL ) 
+        {
+            m_iss.setWriteBerr();
+        }
+        break;
+    } // end switch r_vci_rsp_fsm
+
+    ////////////////////////////////////////////////////////////////////////////
+    //     VCI_CMD_CLEANUP FSM 
+    //
+    // This FSM handles requests from both the DCACHE controler
+    // (request registers) and the ICACHE controler (request registers).
+    // There is 10 VCI transaction types :
+    // - INS_TLB_READ
+    // - INS_TLB_WRITE
+    // - INS_MISS
+    // - INS_UNC_MISS
+    // - DATA_TLB_READ
+    // - DATA_TLB_WRITE
+    // - DATA_TLB_DIRTY
+    // - DATA_MISS
+    // - DATA_UNC 
+    // - DATA_WRITE
+    // The ICACHE requests have the highest priority.
+    // There is at most one (CMD/RSP) VCI transaction, as both CMD_FSM and RSP_FSM
+    // exit simultaneously the IDLE state.
+    //////////////////////////////////////////////////////////////////////////////
+
+    switch (r_vci_cmd_cleanup_fsm) {
+    
+    case CMD_CLEANUP_INS_IDLE:
+        if ((r_vci_rsp_cleanup_fsm != RSP_CLEANUP_INS_IDLE) && (r_vci_rsp_cleanup_fsm != RSP_CLEANUP_DATA_IDLE))
+            break;
+
+        if (r_icache_cleanup_req)           
+        {            
+            r_vci_cmd_cleanup_fsm = CMD_CLEANUP_INS;
+            //m_cpt_ins_cleanup_transaction++; 
+        } 
+        else if (r_dcache_cleanup_req)      
+        {  
+            r_vci_cmd_cleanup_fsm = CMD_CLEANUP_DATA;
+            //m_cpt_data_cleanup_transaction++; 
+        } 
+        break;
+
+    case CMD_CLEANUP_DATA_IDLE:
+        if ((r_vci_rsp_cleanup_fsm != RSP_CLEANUP_INS_IDLE) && (r_vci_rsp_cleanup_fsm != RSP_CLEANUP_DATA_IDLE))
+            break;
+
+        if (r_dcache_cleanup_req)           
+        {           
+            r_vci_cmd_cleanup_fsm = CMD_CLEANUP_DATA;
+            //m_cpt_data_cleanup_transaction++; 
+        } 
+        else if (r_icache_cleanup_req)      
+        {  
+            r_vci_cmd_cleanup_fsm = CMD_CLEANUP_INS;
+            //m_cpt_ins_cleanup_transaction++; 
+        } 
+        break;
+
+    case CMD_CLEANUP_INS:
+        if ( p_vci_ini_c.cmdack.read() )
+        {  
+            r_vci_cmd_cleanup_fsm = CMD_CLEANUP_DATA_IDLE;
+        }
+	break;
+
+    case CMD_CLEANUP_DATA:
+        if ( p_vci_ini_c.cmdack.read() )
+        {  
+            r_vci_cmd_cleanup_fsm = CMD_CLEANUP_INS_IDLE;
+        }
+	break;
+    } // end  switch r_vci_cmd_cleanup_fsm
+
+    //////////////////////////////////////////////////////////////////////////
+    //      VCI_RSP FSM 
+    //
+    // This FSM is synchronized with the VCI_CMD FSM, as both FSMs exit the
+    // IDLE state simultaneously.
+    //////////////////////////////////////////////////////////////////////////
+
+    switch (r_vci_rsp_cleanup_fsm) {
+
+    case RSP_CLEANUP_INS_IDLE:
+        assert( ! p_vci_ini_c.rspval.read() && "Unexpected response" );
+
+        if ((r_vci_cmd_cleanup_fsm != CMD_CLEANUP_INS_IDLE) && (r_vci_cmd_cleanup_fsm != CMD_CLEANUP_DATA_IDLE)) 
+            break;
+
+        if (r_icache_cleanup_req)
+        {
+            r_vci_rsp_cleanup_fsm = RSP_CLEANUP_INS;
+        }
+        else if (r_dcache_cleanup_req)
+        {
+            r_vci_rsp_cleanup_fsm = RSP_CLEANUP_DATA;
+        }
+        break;
+
+    case RSP_CLEANUP_DATA_IDLE:
+        assert( ! p_vci_ini_c.rspval.read() && "Unexpected response" );
+
+        if ((r_vci_cmd_cleanup_fsm != CMD_CLEANUP_INS_IDLE) && (r_vci_cmd_cleanup_fsm != CMD_CLEANUP_DATA_IDLE)) 
+            break;
+
+        if (r_dcache_cleanup_req)
+        {
+            r_vci_rsp_cleanup_fsm = RSP_CLEANUP_DATA;
+        }
+        else if (r_icache_cleanup_req)
+        {
+            r_vci_rsp_cleanup_fsm = RSP_CLEANUP_INS;
+        }
+        break;
+
+    case RSP_CLEANUP_INS:
+        if ( ! p_vci_ini_c.rspval.read() )
+            break;
+        assert( p_vci_ini_c.reop.read() &&
+                "illegal VCI CLEANUP response packet for icache cleanup");
+        assert( (p_vci_ini_c.rerror.read() == vci_param::ERR_NORMAL) &&
+                "error in response packet for icache cleanup");
+
+        r_icache_cleanup_req = false;
+        r_vci_rsp_cleanup_fsm = RSP_CLEANUP_DATA_IDLE;
+        break;
+
+    case RSP_CLEANUP_DATA:
+        if ( ! p_vci_ini_c.rspval.read() )
+            break;
+        assert( p_vci_ini_c.reop.read() &&
+                "illegal VCI CLEANUP response packet for icache cleanup");
+        assert( (p_vci_ini_c.rerror.read() == vci_param::ERR_NORMAL) &&
+                "error in response packet for icache cleanup");
+
+        r_dcache_cleanup_req = false;
+        r_vci_rsp_cleanup_fsm = RSP_CLEANUP_INS_IDLE;
+        break;
+
+    } // end switch r_vci_rsp_cleanup_fsm
+} // end transition()
+
+///////////////////////
+tmpl(void)::genMoore()
+///////////////////////
+{
+    // VCI initiator response
+
+    p_vci_ini_rw.rspack = true;
+
+    // VCI initiator command
+
+    p_vci_ini_rw.pktid  = 0;
+    p_vci_ini_rw.srcid  = m_srcid_rw;
+    p_vci_ini_rw.cons   = false;
+    p_vci_ini_rw.wrap   = false;
+    p_vci_ini_rw.contig = true;
+    p_vci_ini_rw.clen   = 0;
+    p_vci_ini_rw.cfixed = false;
+
+    switch (r_vci_cmd_fsm) {
+
+    case CMD_IDLE:
+        p_vci_ini_rw.cmdval  = false;
+        p_vci_ini_rw.address = 0;
+        p_vci_ini_rw.wdata   = 0;
+        p_vci_ini_rw.be      = 0;
+        p_vci_ini_rw.trdid   = 0;
+        p_vci_ini_rw.plen    = 0;
+        p_vci_ini_rw.cmd     = vci_param::CMD_NOP;
+        p_vci_ini_rw.eop     = false;
+        break;
+
+    case CMD_ITLB_READ:     
+        p_vci_ini_rw.cmdval  = true;
+        p_vci_ini_rw.address = r_icache_paddr_save.read() & m_dcache_yzmask;
+        p_vci_ini_rw.wdata   = 0;
+        p_vci_ini_rw.be      = 0xF;
+        p_vci_ini_rw.trdid   = 1; // via data cache cached read
+        p_vci_ini_rw.plen    = m_dcache_words << 2;
+        p_vci_ini_rw.cmd     = vci_param::CMD_READ;
+        p_vci_ini_rw.eop     = true;
+        break;
+
+    case CMD_ITLB_ACC_LL:
+        p_vci_ini_rw.cmdval  = true;
+        p_vci_ini_rw.address = r_icache_paddr_save.read() & ~0x3;
+        p_vci_ini_rw.wdata   = 0;
+        p_vci_ini_rw.be      = 0xF;
+        p_vci_ini_rw.trdid   = 0; // data cache uncached read
+        p_vci_ini_rw.plen    = 4;
+        p_vci_ini_rw.cmd     = vci_param::CMD_LOCKED_READ;
+        p_vci_ini_rw.eop     = true;
+	break;
+
+    case CMD_ITLB_ACC_SC:
+        p_vci_ini_rw.cmdval  = true;
+        p_vci_ini_rw.address = r_icache_paddr_save.read() & ~0x3;
+        p_vci_ini_rw.wdata   = r_icache_pte_update.read();
+        p_vci_ini_rw.be      = 0xF;
+        p_vci_ini_rw.trdid   = 0; // data cache uncached read
+        p_vci_ini_rw.plen    = 4;
+        p_vci_ini_rw.cmd     = vci_param::CMD_STORE_COND;
+        p_vci_ini_rw.eop     = true;
+	break;	
+
+    case CMD_INS_MISS:
+        p_vci_ini_rw.cmdval  = true;
+        p_vci_ini_rw.address = r_icache_paddr_save.read() & m_icache_yzmask;
+        p_vci_ini_rw.wdata   = 0;
+        p_vci_ini_rw.be      = 0xF;
+        p_vci_ini_rw.trdid   = 3; // ins cache cached read
+        p_vci_ini_rw.plen    = m_icache_words << 2;
+        p_vci_ini_rw.cmd     = vci_param::CMD_READ;
+        p_vci_ini_rw.eop     = true;
+        break;
+
+    case CMD_INS_UNC:
+        p_vci_ini_rw.cmdval  = true;
+        p_vci_ini_rw.address = r_icache_paddr_save.read() & ~0x3;
+        p_vci_ini_rw.wdata   = 0;
+        p_vci_ini_rw.be      = 0xF;
+        p_vci_ini_rw.trdid   = 2; // ins cache uncached read
+        p_vci_ini_rw.plen    = 4;
+        p_vci_ini_rw.cmd     = vci_param::CMD_READ;
+        p_vci_ini_rw.eop     = true;
+        break;
+
+    case CMD_DTLB_READ:     
+        p_vci_ini_rw.cmdval  = true;
+        p_vci_ini_rw.address = r_dcache_tlb_paddr.read() & m_dcache_yzmask;
+        p_vci_ini_rw.wdata   = 0;
+        p_vci_ini_rw.be      = 0xF;
+        p_vci_ini_rw.trdid   = 1; // via dcache cached read
+        p_vci_ini_rw.plen    = m_dcache_words << 2;
+        p_vci_ini_rw.cmd     = vci_param::CMD_READ;
+        p_vci_ini_rw.eop     = true;
+        break;
+
+    case CMD_DTLB_ACC_LL:
+        p_vci_ini_rw.cmdval  = true;
+        p_vci_ini_rw.address = r_dcache_tlb_paddr.read() & ~0x3;
+        p_vci_ini_rw.wdata   = 0;
+        p_vci_ini_rw.be      = 0xF;
+        p_vci_ini_rw.trdid   = 0; // data cache uncached read
+        p_vci_ini_rw.plen    = 4;
+        p_vci_ini_rw.cmd     = vci_param::CMD_LOCKED_READ;
+        p_vci_ini_rw.eop     = true;
+	break;
+
+    case CMD_DTLB_ACC_SC:
+        p_vci_ini_rw.cmdval  = true;
+        p_vci_ini_rw.address = r_dcache_tlb_paddr.read() & ~0x3;
+        p_vci_ini_rw.wdata   = r_dcache_pte_update.read();
+        p_vci_ini_rw.be      = 0xF;
+        p_vci_ini_rw.trdid   = 0; // data cache uncached read
+        p_vci_ini_rw.plen    = 4;
+        p_vci_ini_rw.cmd     = vci_param::CMD_STORE_COND;
+        p_vci_ini_rw.eop     = true;
+	break;	
+
+    case CMD_DTLB_DIRTY_LL:
+        p_vci_ini_rw.cmdval  = true;
+        p_vci_ini_rw.address = r_dcache_tlb_paddr.read() & ~0x3;
+        p_vci_ini_rw.wdata   = 0;
+        p_vci_ini_rw.be      = 0xF;
+        p_vci_ini_rw.trdid   = 0; // data cache uncached read
+        p_vci_ini_rw.plen    = 4;
+        p_vci_ini_rw.cmd     = vci_param::CMD_LOCKED_READ;
+        p_vci_ini_rw.eop     = true;
+	break;
+
+    case CMD_DTLB_DIRTY_SC:
+        p_vci_ini_rw.cmdval  = true;
+        p_vci_ini_rw.address = r_dcache_tlb_paddr.read() & ~0x3;
+        p_vci_ini_rw.wdata   = r_dcache_pte_update.read();
+        p_vci_ini_rw.be      = 0xF;
+        p_vci_ini_rw.trdid   = 0; // data cache uncached read
+        p_vci_ini_rw.plen    = 4;
+        p_vci_ini_rw.cmd     = vci_param::CMD_STORE_COND;
+        p_vci_ini_rw.eop     = true;
+	break;	
+
+    case CMD_DATA_UNC:
+        p_vci_ini_rw.cmdval  = true;
+        p_vci_ini_rw.address = r_dcache_paddr_save.read() & ~0x3;
+        p_vci_ini_rw.trdid   = 0; // data cache uncached read
+        p_vci_ini_rw.plen    = 4;
+        p_vci_ini_rw.eop     = true;
+        switch(r_dcache_type_save) {
+        case iss_t::DATA_READ:
+            p_vci_ini_rw.wdata = 0;
+            p_vci_ini_rw.be    = r_dcache_be_save.read();
+            p_vci_ini_rw.cmd   = vci_param::CMD_READ;
+            break;
+        case iss_t::DATA_LL:
+            p_vci_ini_rw.wdata = 0;
+            p_vci_ini_rw.be    = 0xF;
+            p_vci_ini_rw.cmd   = vci_param::CMD_LOCKED_READ;
+            break;
+        case iss_t::DATA_SC:
+            p_vci_ini_rw.wdata = r_dcache_wdata_save.read();
+            p_vci_ini_rw.be    = 0xF;
+            p_vci_ini_rw.cmd   = vci_param::CMD_STORE_COND;
+            break;
+        default:
+            assert("this should not happen");
+        }
+        break;
+
+    case CMD_DATA_WRITE:
+        p_vci_ini_rw.cmdval  = true;
+        p_vci_ini_rw.address = r_wbuf.getAddress(r_vci_cmd_cpt);
+        p_vci_ini_rw.wdata   = r_wbuf.getData(r_vci_cmd_cpt);
+        p_vci_ini_rw.be      = r_wbuf.getBe(r_vci_cmd_cpt);
+        p_vci_ini_rw.trdid   = 0; // data cache write
+        p_vci_ini_rw.plen    = (r_vci_cmd_max - r_vci_cmd_min + 1)<<2;
+        p_vci_ini_rw.cmd     = vci_param::CMD_WRITE;
+        p_vci_ini_rw.eop     = (r_vci_cmd_cpt == r_vci_cmd_max);
+        break;
+
+    case CMD_DATA_MISS:
+        p_vci_ini_rw.cmdval  = true;
+        p_vci_ini_rw.address = r_dcache_paddr_save.read() & m_dcache_yzmask;
+        p_vci_ini_rw.wdata   = 0;
+        p_vci_ini_rw.be      = 0xF;
+        p_vci_ini_rw.trdid   = 1; // data cache cached read
+        p_vci_ini_rw.plen    = m_dcache_words << 2;
+        p_vci_ini_rw.cmd     = vci_param::CMD_READ;
+        p_vci_ini_rw.eop     = true;
+        break;
+    } // end switch r_vci_cmd_fsm
+
+    // VCI initiator response
+
+    p_vci_ini_c.rspack = true;
+
+    // VCI initiator command
+
+    p_vci_ini_c.pktid  = 0;
+    p_vci_ini_c.srcid  = m_srcid_c;
+    p_vci_ini_c.cons   = false;
+    p_vci_ini_c.wrap   = false;
+    p_vci_ini_c.contig = true;
+    p_vci_ini_c.clen   = 0;
+    p_vci_ini_c.cfixed = false;
+
+    switch (r_vci_cmd_cleanup_fsm) {
+
+    case CMD_CLEANUP_INS_IDLE:
+    case CMD_CLEANUP_DATA_IDLE:
+        p_vci_ini_c.cmdval  = false;
+        p_vci_ini_c.address = 0;
+        p_vci_ini_c.wdata   = 0;
+        p_vci_ini_c.be      = 0;
+        p_vci_ini_c.trdid   = 0;
+        p_vci_ini_c.plen    = 0;
+        p_vci_ini_c.cmd     = vci_param::CMD_NOP;
+        p_vci_ini_c.eop     = false;
+        break;
+
+    case CMD_CLEANUP_INS:
+    case CMD_CLEANUP_DATA:
+        p_vci_ini_c.cmdval = true;
+        if ( r_vci_cmd_cleanup_fsm == CMD_CLEANUP_INS ) p_vci_ini_c.address = r_icache_cleanup_line.read() * (m_icache_words<<2);
+        else                                            p_vci_ini_c.address = r_dcache_cleanup_line.read() * (m_dcache_words<<2);
+        p_vci_ini_c.wdata  = 0;
+        p_vci_ini_c.be     = 0;
+        p_vci_ini_c.trdid  = 1; // cleanup for distinguish from a write
+        p_vci_ini_c.plen   = 4;
+        p_vci_ini_c.cmd    = vci_param::CMD_WRITE;
+        p_vci_ini_c.contig = false;
+        p_vci_ini_c.eop    = true;
+        break;
+
+    } // end switch r_vci_cmd_cleanup_fsm
+
+    // VCI_TGT
+    switch ( r_vci_tgt_fsm.read() ) {
+
+    case TGT_IDLE:
+    case TGT_UPDT_WORD:
+    case TGT_UPDT_DATA:
+        p_vci_tgt.cmdack  = true;
+        p_vci_tgt.rspval  = false;
+        break;
+
+    case TGT_RSP_BROADCAST:
+        p_vci_tgt.cmdack  = false;
+        p_vci_tgt.rspval  = !r_tgt_icache_req.read() && !r_tgt_dcache_req.read() && ( r_tgt_icache_rsp | r_tgt_dcache_rsp );
+        p_vci_tgt.rsrcid  = r_tgt_srcid.read();
+        p_vci_tgt.rpktid  = r_tgt_pktid.read();
+        p_vci_tgt.rtrdid  = r_tgt_trdid.read();
+        p_vci_tgt.rdata   = 0;
+        p_vci_tgt.rerror  = 0;
+        p_vci_tgt.reop    = true;
+        break;
+
+    case TGT_RSP_DCACHE:
+        p_vci_tgt.cmdack  = false;
+        p_vci_tgt.rspval  = !r_tgt_dcache_req.read();
+        p_vci_tgt.rsrcid  = r_tgt_srcid.read();
+        p_vci_tgt.rpktid  = r_tgt_pktid.read();
+        p_vci_tgt.rtrdid  = r_tgt_trdid.read();
+        p_vci_tgt.rdata   = 0;
+        p_vci_tgt.rerror  = 0;
+        p_vci_tgt.reop    = true;
+        break;
+
+    case TGT_REQ_BROADCAST:
+    case TGT_REQ_DCACHE:
+        p_vci_tgt.cmdack  = false;
+        p_vci_tgt.rspval  = false;
+        break;
+
+    } // end switch TGT_FSM
+
+#ifdef SOCLIB_MODULE_DEBUG 
+   std::cout << name() 
+      	     << "Moore:" << std::hex
+      	     << " p_vci_ini_rw.cmdval: " << p_vci_ini_rw.cmdval
+      	     << " p_vci_ini_rw.address: " << p_vci_ini_rw.address
+      	     << " p_vci_ini_rw.wdata: " << p_vci_ini_rw.wdata
+      	     << " p_vci_ini_rw.cmd: " << p_vci_ini_rw.cmd
+      	     << " p_vci_ini_rw.eop: " << p_vci_ini_rw.eop
+      	     << std::endl;
+
+   std::cout << name() 
+             << "Moore:" << std::hex
+             << " p_vci_ini_c.cmdval: " << p_vci_ini_c.cmdval
+             << " p_vci_ini_c.address: " << p_vci_ini_c.address
+             << " p_vci_ini_c.wdata: " << p_vci_ini_c.wdata
+             << " p_vci_ini_c.cmd: " << p_vci_ini_c.cmd
+             << " p_vci_ini_c.eop: " << p_vci_ini_c.eop
+             << std::endl;
+#endif
+
+}
+
+}}
+
+// Local Variables:
+// tab-width: 4
+// c-basic-offset: 4
+// c-file-offsets:((innamespace . 0)(inline-open . 0))
+// indent-tabs-mode: nil
+// End:
+
+// vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4
+
+
+
+
+
+
+
+
+
+
Index: branches/v4/modules/vci_cc_vcache_wrapper2_v1/caba/metadata/vci_cc_vcache_wrapper2_v1.sd
===================================================================
--- branches/v4/modules/vci_cc_vcache_wrapper2_v1/caba/metadata/vci_cc_vcache_wrapper2_v1.sd	(revision 371)
+++ branches/v4/modules/vci_cc_vcache_wrapper2_v1/caba/metadata/vci_cc_vcache_wrapper2_v1.sd	(revision 371)
@@ -0,0 +1,67 @@
+
+# -*- python -*-
+
+__id__ = "$Id$"
+__version__ = "$Revision$"
+
+Module('caba:vci_cc_vcache_wrapper2_v1',
+	classname = 'soclib::caba::VciCcVCacheWrapper2V1',
+	   tmpl_parameters = [
+	parameter.Module('vci_param', default = 'caba:vci_param'),
+	parameter.Module('iss_t'),
+	],
+	header_files = [
+	'../source/include/vci_cc_vcache_wrapper2_v1.h',
+	],
+	implementation_files = [
+	'../source/src/vci_cc_vcache_wrapper2_v1.cpp',
+	],
+	uses = [
+	Uses('caba:base_module'),
+	Uses('caba:write_buffer'),
+	Uses('caba:generic_tlb', addr_t = parameter.StringExt('sc_dt::sc_uint<%d> ', parameter.Reference('addr_size'))),
+	Uses('caba:generic_cache', addr_t = parameter.StringExt('sc_dt::sc_uint<%d> ', parameter.Reference('addr_size'))),
+	Uses('common:address_masking_table', data_t = parameter.StringExt('sc_dt::sc_uint<%d> ', parameter.Reference('addr_size'))),
+	Uses('common:iss2'),
+	Uses('common:mapping_table'),
+	],
+	ports = [
+	Port('caba:vci_initiator', 'p_vci_ini_rw'),
+	Port('caba:vci_initiator', 'p_vci_ini_c'),
+	Port('caba:vci_target', 'p_vci_tgt'),
+	Port('caba:bit_in','p_irq', parameter.Constant('n_irq')),
+	Port('caba:bit_in', 'p_resetn', auto = 'resetn'),
+	Port('caba:clock_in', 'p_clk', auto = 'clock'),
+	],
+	instance_parameters = [
+	parameter.Int('proc_id'),
+	parameter.Module('mt', 'common:mapping_table'),
+	parameter.Module('mc', 'common:mapping_table'),
+	parameter.IntTab('initiator_rw_index'),
+	parameter.IntTab('initiator_c_index'),
+	parameter.IntTab('target_index'),
+    	parameter.Int('itlb_ways'),
+    	parameter.Int('itlb_sets'),
+    	parameter.Int('dtlb_ways'),
+    	parameter.Int('dtlb_sets'),
+    	parameter.Int('icache_ways'),
+    	parameter.Int('icache_sets'),
+    	parameter.Int('icache_words'),
+    	parameter.Int('dcache_ways'),
+    	parameter.Int('dcache_sets'),
+    	parameter.Int('dcache_words'),
+    	parameter.Int('write_buf_size'),
+	],
+	   extensions = [
+	'dsx:get_ident='
+        'initiator_rw_index:p_vci_ini_rw:mt,'
+        'initiator_c_index:p_vci_ini_c:mc,'
+        'target_index:p_vci_tgt:mc',
+	'dsx:cpu=wrapper:iss_t',
+	'dsx:addressable=target_index',
+    'dsx:on_segment=mc:add_index:initiator_rw_index',
+	'dsx:mapping_type=processor:proc_id',
+   ],
+)
+
+
Index: branches/v4/modules/vci_cc_vcache_wrapper2_v1/caba/source/include/vci_cc_vcache_wrapper2_v1.h
===================================================================
--- branches/v4/modules/vci_cc_vcache_wrapper2_v1/caba/source/include/vci_cc_vcache_wrapper2_v1.h	(revision 371)
+++ branches/v4/modules/vci_cc_vcache_wrapper2_v1/caba/source/include/vci_cc_vcache_wrapper2_v1.h	(revision 371)
@@ -0,0 +1,606 @@
+/* -*- c++ -*-
+ * File : vci_cc_vcache_wrapper2_v1.h
+ * Copyright (c) UPMC, Lip6, SoC
+ * Authors : Alain GREINER, Yang GAO
+ *
+ * SOCLIB_LGPL_HEADER_BEGIN
+ * 
+ * This file is part of SoCLib, GNU LGPLv2.1.
+ * 
+ * SoCLib is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU Lesser General Public License as published
+ * by the Free Software Foundation; version 2.1 of the License.
+ * 
+ * SoCLib is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * Lesser General Public License for more details.
+ * 
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with SoCLib; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301 USA
+ * 
+ * SOCLIB_LGPL_HEADER_END
+ */
+ 
+#ifndef SOCLIB_CABA_VCI_CC_VCACHE_WRAPPER2_V1_H
+#define SOCLIB_CABA_VCI_CC_VCACHE_WRAPPER2_V1_H
+
+#include <inttypes.h>
+#include <systemc>
+#include "caba_base_module.h"
+#include "write_buffer.h"
+#include "generic_cache.h"
+#include "vci_initiator.h"
+#include "vci_target.h"
+#include "mapping_table.h"
+#include "generic_tlb.h"
+#include "static_assert.h"
+
+namespace soclib {
+namespace caba {
+
+using namespace sc_core;
+
+////////////////////////////////////////////
+template<typename vci_param, typename iss_t>
+class VciCcVCacheWrapper2V1
+////////////////////////////////////////////
+    : public soclib::caba::BaseModule
+{
+    typedef uint32_t vaddr_t;
+    typedef uint32_t data_t;
+    typedef uint32_t tag_t;
+    typedef uint32_t type_t;
+    typedef typename iss_t::DataOperationType data_op_t;
+
+    typedef typename vci_param::addr_t  paddr_t;
+    typedef typename vci_param::be_t    vci_be_t;
+	typedef typename vci_param::srcid_t vci_srcid_t;
+	typedef typename vci_param::trdid_t vci_trdid_t;
+	typedef typename vci_param::pktid_t vci_pktid_t;
+	typedef typename vci_param::plen_t  vci_plen_t;
+
+    enum icache_fsm_state_e {  
+        ICACHE_IDLE,                // 00
+        ICACHE_BIS,                 // 01
+        ICACHE_TLB1_READ,           // 02
+        ICACHE_TLB1_WRITE,          // 03
+        ICACHE_TLB1_UPDT_SEL,       // 04
+        ICACHE_TLB1_UPDT,           // 05
+        ICACHE_TLB2_READ,           // 06
+        ICACHE_TLB2_WRITE,          // 07
+        ICACHE_TLB2_UPDT_SEL,       // 08
+        ICACHE_TLB2_UPDT,           // 09
+        ICACHE_SW_FLUSH,            // 0a
+        ICACHE_TLB_FLUSH,           // 0b
+        ICACHE_CACHE_FLUSH,         // 0c
+        ICACHE_TLB_INVAL,           // 0d
+        ICACHE_CACHE_INVAL,         // 0e
+        ICACHE_CACHE_INVAL_PA,      // 0f
+        ICACHE_MISS_WAIT,           // 10
+        ICACHE_UNC_WAIT,            // 11
+        ICACHE_MISS_UPDT,           // 12
+        ICACHE_ERROR,               // 13
+        ICACHE_CC_INVAL,            // 14
+        ICACHE_TLB_CC_INVAL,        // 15
+    };
+
+    enum dcache_fsm_state_e {  
+        DCACHE_IDLE,                // 00
+        DCACHE_BIS,                 // 01
+        DCACHE_DTLB1_READ_CACHE,    // 02
+        DCACHE_TLB1_LL_WAIT,        // 03
+        DCACHE_TLB1_SC_WAIT,        // 04
+        DCACHE_TLB1_READ,           // 05
+        DCACHE_TLB1_READ_UPDT,      // 06
+        DCACHE_TLB1_UPDT_SEL,       // 07
+        DCACHE_TLB1_UPDT,           // 08
+        DCACHE_DTLB2_READ_CACHE,    // 09
+        DCACHE_TLB2_LL_WAIT,        // 0a
+        DCACHE_TLB2_SC_WAIT,        // 0b
+        DCACHE_TLB2_READ,           // 0c
+        DCACHE_TLB2_READ_UPDT,      // 0d
+        DCACHE_TLB2_UPDT_SEL,       // 0e
+        DCACHE_TLB2_UPDT,           // 0f
+        DCACHE_CTXT_SWITCH,         // 10
+        DCACHE_ICACHE_FLUSH,        // 11
+        DCACHE_DCACHE_FLUSH,        // 12
+        DCACHE_ITLB_INVAL,          // 13
+        DCACHE_DTLB_INVAL,          // 14
+        DCACHE_ICACHE_INVAL,        // 15
+        DCACHE_DCACHE_INVAL,        // 16
+	    DCACHE_ICACHE_INVAL_PA,     // 17
+	    DCACHE_DCACHE_INVAL_PA,     // 18
+        DCACHE_DCACHE_SYNC,         // 19
+        DCACHE_LL_DIRTY_WAIT,       // 1a
+        DCACHE_SC_DIRTY_WAIT,       // 1b
+        DCACHE_WRITE_UPDT,          // 1c
+        DCACHE_WRITE_DIRTY,         // 1d
+        DCACHE_WRITE_REQ,           // 1e
+        DCACHE_MISS_WAIT,           // 1f
+        DCACHE_MISS_UPDT,           // 20
+        DCACHE_UNC_WAIT,            // 21
+        DCACHE_ERROR,               // 22
+        DCACHE_ITLB_READ,           // 23
+        DCACHE_ITLB_UPDT,           // 24
+        DCACHE_ITLB_LL_WAIT,        // 25
+        DCACHE_ITLB_SC_WAIT,        // 26
+        DCACHE_CC_CHECK,            // 27
+        DCACHE_CC_INVAL,            // 28
+        DCACHE_CC_UPDT,             // 29
+        DCACHE_CC_NOP,              // 2a
+        DCACHE_TLB_CC_INVAL,        // 2b
+        DCACHE_ITLB_CLEANUP,        // 2c
+    };
+
+    enum cmd_fsm_state_e {      
+        CMD_IDLE,                   // 00
+        CMD_ITLB_READ,              // 01
+        CMD_ITLB_ACC_LL,            // 02
+        CMD_ITLB_ACC_SC,            // 03
+        CMD_INS_MISS,               // 04
+        CMD_INS_UNC,                // 05
+        CMD_DTLB_READ,              // 06
+        CMD_DTLB_ACC_LL,            // 07
+        CMD_DTLB_ACC_SC,            // 08
+        CMD_DTLB_DIRTY_LL,          // 09
+        CMD_DTLB_DIRTY_SC,          // 0a
+        CMD_DATA_UNC,               // 0b
+        CMD_DATA_MISS,              // 0c
+        CMD_DATA_WRITE,             // 0d
+    };
+
+    enum rsp_fsm_state_e {       
+        RSP_IDLE,                   // 00
+        RSP_ITLB_READ,              // 01
+        RSP_ITLB_ACC_LL,            // 02
+        RSP_ITLB_ACC_SC,            // 03
+        RSP_INS_MISS,               // 04
+        RSP_INS_UNC,                // 05
+        RSP_DTLB_READ,              // 06
+        RSP_DTLB_ACC_LL,            // 07
+        RSP_DTLB_ACC_SC,            // 08
+        RSP_DTLB_DIRTY_LL,          // 09
+        RSP_DTLB_DIRTY_SC,          // 0a
+        RSP_DATA_MISS,              // 0b
+        RSP_DATA_UNC,               // 0c
+        RSP_DATA_WRITE,             // 0d
+    };
+    enum cleanup_cmd_fsm_state_e {
+        CLEANUP_CMD_IDLE,               // 00
+        CLEANUP_CMD_DATA,               // 01
+        CLEANUP_CMD_INS,                // 02
+    };
+
+    enum cleanup_rsp_fsm_state_e {
+        CLEANUP_RSP_IDLE,               // 00
+        CLEANUP_RSP_DATA,               // 01
+        CLEANUP_RSP_INS,                // 02
+    };
+
+    enum tgt_fsm_state_e {  
+        TGT_IDLE,                   // 00
+        TGT_UPDT_WORD,              // 01
+        TGT_UPDT_DATA,              // 02
+        TGT_REQ_BROADCAST,          // 03
+        TGT_REQ_ICACHE,             // 04
+        TGT_REQ_DCACHE,             // 05
+        TGT_RSP_BROADCAST,          // 06
+        TGT_RSP_ICACHE,             // 07
+        TGT_RSP_DCACHE,             // 08
+    };
+
+    enum inval_itlb_fsm_state_e {
+        INVAL_ITLB_IDLE,            // 00
+        INVAL_ITLB_CHECK,           // 01
+        INVAL_ITLB_INVAL,           // 02
+        INVAL_ITLB_CLEAR,           // 03
+    };
+
+    enum inval_dtlb_fsm_state_e {
+        INVAL_DTLB_IDLE,            // 00
+        INVAL_DTLB_CHECK,           // 01
+        INVAL_DTLB_INVAL,           // 02
+        INVAL_DTLB_CLEAR,           // 03
+    };
+
+    // TLB Mode ITLB / DTLB / ICACHE / DCACHE
+    enum {          
+        ALL_DEACTIVE = 0x0000,   // TLBs disactive caches disactive
+        INS_TLB_MASK    = 0x8,
+        DATA_TLB_MASK   = 0x4,
+        INS_CACHE_MASK  = 0x2,
+        DATA_CACHE_MASK = 0x1,
+    };
+
+    // Error Type
+    enum mmu_error_type_e {
+        MMU_NONE                      = 0x0000, // None
+        MMU_WRITE_PT1_UNMAPPED 	      = 0x0001, // Write access of Page fault on Page Table 1          (non fatal error)
+        MMU_WRITE_PT2_UNMAPPED 	      = 0x0002, // Write access of Page fault on Page Table 2          (non fatal error)
+        MMU_WRITE_PRIVILEGE_VIOLATION = 0x0004, // Write access of Protected access in user mode       (user error)
+        MMU_WRITE_ACCES_VIOLATION 	  = 0x0008, // Write access of write access to a non writable page (user error)
+        MMU_WRITE_UNDEFINED_XTN 	  = 0x0020, // Write access of undefined external access address   (user error)
+        MMU_WRITE_PT1_ILLEGAL_ACCESS  = 0x0040, // Write access of Bus Error accessing Table 1         (kernel error)
+        MMU_WRITE_PT2_ILLEGAL_ACCESS  = 0x0080, // Write access of Bus Error accessing Table 2         (kernel error)
+        MMU_WRITE_DATA_ILLEGAL_ACCESS = 0x0100, // Write access of Bus Error in cache access           (kernel error)
+        MMU_READ_PT1_UNMAPPED 	      = 0x1001, // Read access of Page fault on Page Table 1  	       (non fatal error)
+        MMU_READ_PT2_UNMAPPED 	      = 0x1002, // Read access of Page fault on Page Table 2  	       (non fatal error)
+        MMU_READ_PRIVILEGE_VIOLATION  = 0x1004, // Read access of Protected access in user mode 	   (user error)
+        MMU_READ_EXEC_VIOLATION 	  = 0x1010, // Exec access to a non exec page                      (user error)
+        MMU_READ_UNDEFINED_XTN 	      = 0x1020, // Read access of Undefined external access address    (user error)
+        MMU_READ_PT1_ILLEGAL_ACCESS   = 0x1040, // Read access of Bus Error in Table1 access           (kernel error)
+        MMU_READ_PT2_ILLEGAL_ACCESS   = 0x1080, // Read access of Bus Error in Table2 access 	       (kernel error)
+        MMU_READ_DATA_ILLEGAL_ACCESS  = 0x1100, // Read access of Bus Error in cache access 	       (kernel error)
+    };
+
+public:
+    sc_in<bool>                             p_clk;
+    sc_in<bool>                             p_resetn;
+    sc_in<bool>                             p_irq[iss_t::n_irq];
+    soclib::caba::VciInitiator<vci_param>   p_vci_ini_rw;
+    soclib::caba::VciInitiator<vci_param>   p_vci_ini_c;
+    soclib::caba::VciTarget<vci_param>      p_vci_tgt;
+
+private:
+    // STRUCTURAL PARAMETERS
+    soclib::common::AddressDecodingTable<uint32_t, bool>    m_cacheability_table;
+    const soclib::common::Segment                           m_segment;
+    iss_t                                                   m_iss;   
+    const vci_srcid_t                                       m_srcid_rw;
+    const vci_srcid_t                                       m_srcid_c;
+
+    const size_t  m_itlb_ways;
+    const size_t  m_itlb_sets;
+
+    const size_t  m_dtlb_ways;
+    const size_t  m_dtlb_sets;
+
+    const size_t  m_icache_ways;
+    const size_t  m_icache_sets;
+    const size_t  m_icache_yzmask;
+    const size_t  m_icache_words;
+
+    const size_t  m_dcache_ways;
+    const size_t  m_dcache_sets;
+    const size_t  m_dcache_yzmask;
+    const size_t  m_dcache_words;
+
+    const size_t  m_write_buf_size;  
+    const size_t  m_paddr_nbits;  
+
+    // instruction and data vcache tlb instances 
+    soclib::caba::GenericCcTlb<paddr_t>    icache_tlb;
+    soclib::caba::GenericCcTlb<paddr_t>    dcache_tlb;
+
+    sc_signal<vaddr_t>      r_mmu_ptpr;             // page table pointer register
+    sc_signal<int>          r_mmu_mode;             // tlb mode register
+    sc_signal<int>          r_mmu_params;           // mmu parameters register
+    sc_signal<int>          r_mmu_release;          // mmu release register
+    sc_signal<int>          r_mmu_word_lo;          // mmu misc data low
+    sc_signal<int>          r_mmu_word_hi;          // mmu mmu misc data hight
+
+    // DCACHE FSM REGISTERS
+    sc_signal<int>          r_dcache_fsm;               // state register
+    sc_signal<paddr_t>      r_dcache_paddr_save;        // physical address
+    sc_signal<data_t>       r_dcache_wdata_save;        // write data
+    sc_signal<data_t>       r_dcache_rdata_save;        // read data
+    sc_signal<type_t>       r_dcache_type_save;         // access type
+    sc_signal<vci_be_t>     r_dcache_be_save;           // byte enable
+    sc_signal<bool>         r_dcache_cached_save;       // used by the write buffer
+    sc_signal<paddr_t>      r_dcache_tlb_paddr;         // physical address of tlb miss
+    sc_signal<bool>         r_dcache_dirty_save;        // used for TLB dirty bit update
+    sc_signal<size_t>       r_dcache_tlb_set_save;      // used for TLB dirty bit update
+    sc_signal<size_t>       r_dcache_tlb_way_save;      // used for TLB dirty bit update
+    sc_signal<vaddr_t>      r_dcache_id1_save;          // used by the PT1 bypass
+    sc_signal<paddr_t>      r_dcache_ptba_save;         // used by the PT1 bypass
+    sc_signal<bool>         r_dcache_ptba_ok;           // used by the PT1 bypass
+    sc_signal<data_t>       r_dcache_pte_update;        // used for page table update
+    sc_signal<data_t>       r_dcache_ppn_update;        // used for physical page number update 
+    sc_signal<tag_t>        r_dcache_ppn_save;          // used for speculative cache access
+    sc_signal<tag_t>        r_dcache_vpn_save;          // used for speculative cache access
+    sc_signal<bool>         r_dtlb_translation_valid;   // used for speculative address
+    sc_signal<bool>         r_dcache_buf_unc_valid;     // used for uncached read
+    sc_signal<bool>         r_dcache_hit_p_save;        // used to save hit_p in case BIS
+
+    sc_signal<data_t>       r_dcache_error_type;        // software visible register
+    sc_signal<vaddr_t>      r_dcache_bad_vaddr;         // software visible register 
+
+    sc_signal<bool>         r_dcache_miss_req;          // used for cached read miss
+    sc_signal<bool>         r_dcache_unc_req;           // used for uncached read miss
+    sc_signal<bool>         r_dcache_write_req;         // used for write 
+    sc_signal<bool>         r_dcache_tlb_read_req;      // used for tlb ptba or pte read
+
+    sc_signal<bool>         r_dcache_llsc_reserved;     // used for check address reserved
+    sc_signal<paddr_t>      r_dcache_llsc_addr_save;    // used for save llsc address
+ 
+    sc_signal<bool>         r_dcache_tlb_ll_acc_req;    // used for tlb access bit update
+    sc_signal<bool>         r_dcache_tlb_sc_acc_req;    // used for tlb access bit update
+    sc_signal<bool>         r_dcache_tlb_ll_dirty_req;  // used for tlb dirty bit update 
+    sc_signal<bool>         r_dcache_tlb_sc_dirty_req;  // used for tlb dirty bit update 
+    sc_signal<bool>         r_dcache_sc_updt_dirty;     // used for tlb dirty bit update 
+    sc_signal<bool>         r_dcache_tlb_ptba_read;     // used for tlb ptba read when write dirty bit 
+    sc_signal<bool>         r_dcache_xtn_req;           // used for xtn write for ICACHE
+
+    bool                    *r_dcache_in_itlb;          // indicates some words of dcache line in ins TLB 
+    bool                    *r_dcache_in_dtlb;          // indicates some words of dcache line in data TLB 
+
+    // coherence registers
+    sc_signal<int>          r_dcache_fsm_save;          // state save register
+    sc_signal<size_t>       r_dcache_way;
+    sc_signal<size_t>       r_dcache_set;
+    sc_signal<bool>         r_dcache_cleanup_req;       // data cleanup request
+    sc_signal<paddr_t>      r_dcache_cleanup_line;      // data cleanup NLINE
+    sc_signal<bool>         r_dcache_inval_rsp;         // data cache invalidate
+
+    // ICACHE FSM REGISTERS
+    sc_signal<int>          r_icache_fsm;               // state register
+    sc_signal<paddr_t>      r_icache_paddr_save;        // physical address
+    sc_signal<vaddr_t>      r_icache_id1_save;          // used by the PT1 bypass
+    sc_signal<paddr_t>      r_icache_ptba_save;         // used by the PT1 bypass
+    sc_signal<bool>         r_icache_ptba_ok;           // used by the PT1 bypass
+    sc_signal<data_t>       r_icache_pte_update;        // used for page table update
+    sc_signal<tag_t>        r_icache_ppn_save;          // used for speculative cache access
+    sc_signal<tag_t>        r_icache_vpn_save;          // used for speculative cache access
+    sc_signal<bool>         r_itlb_translation_valid;   // used for speculative physical address
+    sc_signal<bool>         r_icache_buf_unc_valid;     // used for uncached read
+
+    sc_signal<data_t>       r_icache_error_type;        // software visible registers
+    sc_signal<vaddr_t>      r_icache_bad_vaddr;         // software visible registers
+
+    sc_signal<bool>         r_icache_miss_req;          // used for cached read miss
+    sc_signal<bool>         r_icache_unc_req;           // used for uncached read miss
+    sc_signal<bool>         r_dcache_itlb_read_req;     // used for tlb ptba or pte read 
+
+    sc_signal<bool>         r_dcache_itlb_ll_acc_req;   // used for tlb access bit update
+    sc_signal<bool>         r_dcache_itlb_sc_acc_req;   // used for tlb access bit update
+
+    sc_signal<bool>	        r_itlb_read_dcache_req;     // used for instruction tlb miss, request in data cache
+    sc_signal<bool>	        r_itlb_k_read_dcache;       // used for instruction tlb miss, request in data cache
+    sc_signal<bool>	        r_itlb_acc_dcache_req;      // used for itlb update access bit via dcache
+    sc_signal<bool>	        r_itlb_acc_redo_req;        // used for itlb update access bit via dcache
+    sc_signal<bool>	        r_dcache_rsp_itlb_error;    // used for data cache rsp error when itlb miss
+    sc_signal<data_t>	    r_dcache_rsp_itlb_miss;	    // used for dcache rsp data when itlb miss
+    sc_signal<data_t>	    r_dcache_rsp_itlb_ppn;	    // used for dcache rsp ppn when itlb miss
+    sc_signal<vaddr_t>      r_icache_vaddr_req;			// virtual address requested by the CPU
+
+    // coherence registers
+    sc_signal<int>          r_icache_fsm_save;          // state save register
+    sc_signal<size_t>       r_icache_way;
+    sc_signal<size_t>       r_icache_set;
+    sc_signal<bool>         r_icache_cleanup_req;       // ins cleanup request
+    sc_signal<paddr_t>      r_icache_cleanup_line;      // ins cleanup NLINE
+    sc_signal<bool>         r_icache_inval_rsp;         // ins cache invalidate
+
+    // VCI_CMD FSM REGISTERS
+    sc_signal<int>          r_vci_cmd_fsm;
+    sc_signal<size_t>       r_vci_cmd_min;       
+    sc_signal<size_t>       r_vci_cmd_max;       
+    sc_signal<size_t>       r_vci_cmd_cpt;     
+
+    // VCI_RSP FSM REGISTERS
+    sc_signal<int>          r_vci_rsp_fsm;
+    sc_signal<size_t>       r_vci_rsp_cpt;
+    sc_signal<bool>         r_vci_rsp_ins_error;
+    sc_signal<bool>         r_vci_rsp_data_error;
+    sc_signal<bool>         r_dcache_tlb_sc_fail;
+
+    data_t                  *r_icache_miss_buf;    
+    data_t                  *r_dcache_miss_buf;  
+
+    sc_signal<int>          r_cleanup_cmd_fsm;
+    sc_signal<int>          r_cleanup_rsp_fsm;
+
+    // VCI_TGT FSM REGISTERS
+    data_t                  *r_tgt_buf;
+    bool                    *r_tgt_val;
+
+    sc_signal<int>          r_vci_tgt_fsm;
+    sc_signal<paddr_t>      r_tgt_addr;
+    sc_signal<size_t>       r_tgt_word;
+    sc_signal<bool>         r_tgt_update;
+    sc_signal<vci_srcid_t>  r_tgt_srcid;
+    sc_signal<vci_pktid_t>  r_tgt_pktid;
+    sc_signal<vci_trdid_t>  r_tgt_trdid;
+    sc_signal<vci_plen_t>   r_tgt_plen;
+    sc_signal<bool>         r_tgt_req;
+    sc_signal<bool>         r_tgt_icache_req;
+    sc_signal<bool>         r_tgt_dcache_req;
+    sc_signal<bool>         r_tgt_icache_rsp;
+    sc_signal<bool>         r_tgt_dcache_rsp;
+
+    // INVAL CHECK FSM
+    sc_signal<int>          r_inval_itlb_fsm;          
+    sc_signal<bool>         r_dcache_itlb_inval_req;
+    sc_signal<paddr_t>      r_dcache_itlb_inval_line;
+    sc_signal<bool>         r_itlb_cc_check_end;
+    sc_signal<size_t>       r_ccinval_itlb_way; 
+    sc_signal<size_t>       r_ccinval_itlb_set; 
+    sc_signal<bool>         r_icache_inval_tlb_rsp;
+    sc_signal<paddr_t>      r_icache_tlb_nline;
+
+    sc_signal<int>          r_inval_dtlb_fsm;          
+    sc_signal<bool>         r_dcache_dtlb_inval_req;
+    sc_signal<paddr_t>      r_dcache_dtlb_inval_line;
+    sc_signal<bool>         r_dtlb_cc_check_end;
+    sc_signal<size_t>       r_ccinval_dtlb_way; 
+    sc_signal<size_t>       r_ccinval_dtlb_set; 
+    sc_signal<bool>         r_dcache_inval_tlb_rsp;
+    sc_signal<paddr_t>      r_dcache_tlb_nline;
+
+    sc_signal<bool>         r_dcache_itlb_cleanup_req;
+    sc_signal<paddr_t>      r_dcache_itlb_cleanup_line;
+
+    sc_signal<bool>         r_dcache_dtlb_cleanup_req;
+    sc_signal<paddr_t>      r_dcache_dtlb_cleanup_line;
+
+    sc_signal<bool>         r_itlb_inval_req;
+    sc_signal<bool>         r_dcache_cc_check;
+
+    WriteBuffer<paddr_t>     r_wbuf;
+    GenericCache<paddr_t>    r_icache;
+    GenericCache<paddr_t>    r_dcache;
+
+    // Activity counters
+    uint32_t m_cpt_dcache_data_read;        // DCACHE DATA READ
+    uint32_t m_cpt_dcache_data_write;       // DCACHE DATA WRITE
+    uint32_t m_cpt_dcache_dir_read;         // DCACHE DIR READ
+    uint32_t m_cpt_dcache_dir_write;        // DCACHE DIR WRITE
+
+    uint32_t m_cpt_icache_data_read;        // ICACHE DATA READ
+    uint32_t m_cpt_icache_data_write;       // ICACHE DATA WRITE
+    uint32_t m_cpt_icache_dir_read;         // ICACHE DIR READ
+    uint32_t m_cpt_icache_dir_write;        // ICACHE DIR WRITE
+
+    uint32_t m_cpt_frz_cycles;	            // number of cycles where the cpu is frozen
+    uint32_t m_cpt_total_cycles;	        // total number of cycles
+    uint32_t m_cpt_dcache_frz_cycles;       // number of cycles where the data cache is frozen    
+
+    // Cache activity counters
+    uint32_t m_cpt_read;                    // total number of read data
+    uint32_t m_cpt_write;                   // total number of write data
+    uint32_t m_cpt_data_miss;               // number of read miss
+    uint32_t m_cpt_ins_miss;                // number of instruction miss
+    uint32_t m_cpt_unc_read;                // number of read uncached
+    uint32_t m_cpt_write_cached;            // number of cached write
+    uint32_t m_cpt_ins_read;                // number of instruction read
+
+    uint32_t m_cost_write_frz;              // number of frozen cycles related to write buffer         
+    uint32_t m_cost_data_miss_frz;          // number of frozen cycles related to data miss
+    uint32_t m_cost_unc_read_frz;           // number of frozen cycles related to uncached read
+    uint32_t m_cost_ins_miss_frz;           // number of frozen cycles related to ins miss
+
+    uint32_t m_cpt_imiss_transaction;       // number of VCI instruction miss transactions
+    uint32_t m_cpt_dmiss_transaction;       // number of VCI data miss transactions
+    uint32_t m_cpt_unc_transaction;         // number of VCI uncached read transactions
+    uint32_t m_cpt_write_transaction;       // number of VCI write transactions
+    uint32_t m_cpt_icache_unc_transaction;
+
+    uint32_t m_cost_imiss_transaction;      // cumulated duration for VCI IMISS transactions
+    uint32_t m_cost_dmiss_transaction;      // cumulated duration for VCI DMISS transactions
+    uint32_t m_cost_unc_transaction;        // cumulated duration for VCI UNC transactions
+    uint32_t m_cost_write_transaction;      // cumulated duration for VCI WRITE transactions
+    uint32_t m_cost_icache_unc_transaction; // cumulated duration for VCI IUNC transactions    
+    uint32_t m_length_write_transaction;    // cumulated length for VCI WRITE transactions
+
+    // TLB activity counters
+    uint32_t m_cpt_ins_tlb_read;            // number of instruction tlb read
+    uint32_t m_cpt_ins_tlb_miss;            // number of instruction tlb miss
+    uint32_t m_cpt_ins_tlb_update_acc;      // number of instruction tlb update acc
+    uint32_t m_cpt_data_tlb_read;           // number of data tlb read
+    uint32_t m_cpt_data_tlb_miss;           // number of data tlb miss
+    uint32_t m_cpt_data_tlb_update_acc;     // number of data tlb update acc
+    uint32_t m_cpt_data_tlb_update_dirty;   // number of data tlb update dirty
+    uint32_t m_cpt_ins_tlb_hit_dcache;      // number of instruction tlb hit in data cache
+    uint32_t m_cpt_data_tlb_hit_dcache;     // number of data tlb hit in data cache
+    uint32_t m_cpt_ins_tlb_occup_cache;     // number of instruction tlb occupy data cache line 
+    uint32_t m_cpt_data_tlb_occup_cache;    // number of data tlb occupy data cache line
+    uint32_t m_cpt_tlb_occup_dcache;
+    
+    uint32_t m_cost_ins_tlb_miss_frz;       // number of frozen cycles related to instruction tlb miss
+    uint32_t m_cost_data_tlb_miss_frz;      // number of frozen cycles related to data tlb miss
+    uint32_t m_cost_ins_tlb_update_acc_frz;    // number of frozen cycles related to instruction tlb update acc
+    uint32_t m_cost_data_tlb_update_acc_frz;   // number of frozen cycles related to data tlb update acc
+    uint32_t m_cost_data_tlb_update_dirty_frz; // number of frozen cycles related to data tlb update dirty
+    uint32_t m_cost_ins_tlb_occup_cache_frz;   // number of frozen cycles related to instruction tlb miss operate in dcache
+    uint32_t m_cost_data_tlb_occup_cache_frz;  // number of frozen cycles related to data tlb miss operate in dcache
+
+    uint32_t m_cpt_itlbmiss_transaction;       // number of itlb miss transactions
+    uint32_t m_cpt_itlb_ll_transaction;        // number of itlb ll acc transactions
+    uint32_t m_cpt_itlb_sc_transaction;        // number of itlb sc acc transactions
+    uint32_t m_cpt_dtlbmiss_transaction;       // number of dtlb miss transactions
+    uint32_t m_cpt_dtlb_ll_transaction;        // number of dtlb ll acc transactions
+    uint32_t m_cpt_dtlb_sc_transaction;        // number of dtlb sc acc transactions
+    uint32_t m_cpt_dtlb_ll_dirty_transaction;  // number of dtlb ll dirty transactions
+    uint32_t m_cpt_dtlb_sc_dirty_transaction;  // number of dtlb sc dirty transactions
+
+    uint32_t m_cost_itlbmiss_transaction;     // cumulated duration for VCI instruction TLB miss transactions
+    uint32_t m_cost_itlb_ll_transaction;      // cumulated duration for VCI instruction TLB ll acc transactions
+    uint32_t m_cost_itlb_sc_transaction;      // cumulated duration for VCI instruction TLB sc acc transactions
+    uint32_t m_cost_dtlbmiss_transaction;     // cumulated duration for VCI data TLB miss transactions
+    uint32_t m_cost_dtlb_ll_transaction;      // cumulated duration for VCI data TLB ll acc transactions
+    uint32_t m_cost_dtlb_sc_transaction;      // cumulated duration for VCI data TLB sc acc transactions
+    uint32_t m_cost_dtlb_ll_dirty_transaction;// cumulated duration for VCI data TLB ll dirty transactions
+    uint32_t m_cost_dtlb_sc_dirty_transaction;// cumulated duration for VCI data TLB sc dirty transactions
+
+    uint32_t m_cpt_cc_update_data;              // number of coherence update data packets 
+    uint32_t m_cpt_cc_inval_ins;                // number of coherence inval instruction packets
+    uint32_t m_cpt_cc_inval_data;               // number of coherence inval data packets
+    uint32_t m_cpt_cc_broadcast;                // number of coherence broadcast packets
+    
+    uint32_t m_cost_updt_data_frz;              // number of frozen cycles related to coherence update data packets
+    uint32_t m_cost_inval_ins_frz;              // number of frozen cycles related to coherence inval instruction packets
+    uint32_t m_cost_inval_data_frz;             // number of frozen cycles related to coherence inval data packets
+    uint32_t m_cost_broadcast_frz;              // number of frozen cycles related to coherence broadcast packets
+
+    uint32_t m_cpt_cc_cleanup_ins;              // number of coherence cleanup packets
+    uint32_t m_cpt_cc_cleanup_data;             // number of coherence cleanup packets
+
+    uint32_t m_cpt_icleanup_transaction;        // number of instruction cleanup transactions
+    uint32_t m_cpt_dcleanup_transaction;        // number of instructinumber of data cleanup transactions
+    uint32_t m_cost_icleanup_transaction;       // cumulated duration for VCI instruction cleanup transactions
+    uint32_t m_cost_dcleanup_transaction;       // cumulated duration for VCI data cleanup transactions
+
+    uint32_t m_cost_ins_tlb_inval_frz;      // number of frozen cycles related to checking ins tlb invalidate
+    uint32_t m_cpt_ins_tlb_inval;           // number of ins tlb invalidate
+
+    uint32_t m_cost_data_tlb_inval_frz;     // number of frozen cycles related to checking data tlb invalidate    
+    uint32_t m_cpt_data_tlb_inval;          // number of data tlb invalidate
+
+protected:
+    SC_HAS_PROCESS(VciCcVCacheWrapper2V1);
+
+public:
+    VciCcVCacheWrapper2V1(
+        sc_module_name insname,
+        int proc_id,
+        const soclib::common::MappingTable &mtp,
+        const soclib::common::MappingTable &mtc,
+        const soclib::common::IntTab &initiator_index_rw,
+        const soclib::common::IntTab &initiator_index_c,
+        const soclib::common::IntTab &target_index,
+        size_t itlb_ways,
+        size_t itlb_sets,
+        size_t dtlb_ways,
+        size_t dtlb_sets,
+        size_t icache_ways,
+        size_t icache_sets,
+        size_t icache_words,
+        size_t dcache_ways,
+        size_t dcache_sets,
+        size_t dcache_words,
+        size_t write_buf_size );
+
+    ~VciCcVCacheWrapper2V1();
+
+    void print_cpi();
+    void print_stats();
+    void clear_stats();
+    void print_trace(size_t mode = 0);
+
+private:
+    void transition();
+    void genMoore();
+
+    soclib_static_assert((int)iss_t::SC_ATOMIC == (int)vci_param::STORE_COND_ATOMIC);
+    soclib_static_assert((int)iss_t::SC_NOT_ATOMIC == (int)vci_param::STORE_COND_NOT_ATOMIC);
+};
+
+}}
+
+#endif /* SOCLIB_CABA_VCI_CC_VCACHE_WRAPPER2_V1_H */
+
+// Local Variables:
+// tab-width: 4
+// c-basic-offset: 4
+// c-file-offsets:((innamespace . 0)(inline-open . 0))
+// indent-tabs-mode: nil
+// End:
+
+// vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4
+
+
+
+
Index: branches/v4/modules/vci_cc_vcache_wrapper2_v1/caba/source/src/vci_cc_vcache_wrapper2_v1.cpp
===================================================================
--- branches/v4/modules/vci_cc_vcache_wrapper2_v1/caba/source/src/vci_cc_vcache_wrapper2_v1.cpp	(revision 371)
+++ branches/v4/modules/vci_cc_vcache_wrapper2_v1/caba/source/src/vci_cc_vcache_wrapper2_v1.cpp	(revision 371)
@@ -0,0 +1,6385 @@
+/* -*- c++ -*-
+ * File : vci_cc_vcache_wrapper2_v1.cpp
+ * Copyright (c) UPMC, Lip6, SoC
+ * Authors : Alain GREINER, Yang GAO
+ *
+ * SOCLIB_LGPL_HEADER_BEGIN
+ * 
+ * This file is part of SoCLib, GNU LGPLv2.1.
+ * 
+ * SoCLib is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU Lesser General Public License as published
+ * by the Free Software Foundation; version 2.1 of the License.
+ * 
+ * SoCLib is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * Lesser General Public License for more details.
+ * 
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with SoCLib; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301 USA
+ * 
+ * SOCLIB_LGPL_HEADER_END
+ */
+
+#include <cassert>
+#include "arithmetics.h"
+#include "../include/vci_cc_vcache_wrapper2_v1.h"
+
+namespace soclib { 
+namespace caba {
+
+//#define SOCLIB_MODULE_DEBUG
+//#define EVALUATION_CACHE
+
+//#ifdef SOCLIB_MODULE_DEBUG
+namespace {
+const char *icache_fsm_state_str[] = {
+        "ICACHE_IDLE",
+        "ICACHE_BIS",       
+        "ICACHE_TLB1_READ",  
+        "ICACHE_TLB1_WRITE",
+	"ICACHE_TLB1_UPDT_SEL",  
+        "ICACHE_TLB1_UPDT",  
+        "ICACHE_TLB2_READ",  
+        "ICACHE_TLB2_WRITE",
+	"ICACHE_TLB2_UPDT_SEL",  
+        "ICACHE_TLB2_UPDT",  
+        "ICACHE_SW_FLUSH", 
+        "ICACHE_TLB_FLUSH", 
+        "ICACHE_CACHE_FLUSH", 
+        "ICACHE_TLB_INVAL",  
+        "ICACHE_CACHE_INVAL",
+	"ICACHE_CACHE_INVAL_PA",
+        "ICACHE_MISS_WAIT",
+        "ICACHE_UNC_WAIT",  
+        "ICACHE_MISS_UPDT",  
+        "ICACHE_ERROR", 
+        "ICACHE_CC_INVAL", 
+        "ICACHE_TLB_CC_INVAL",        
+    };
+const char *dcache_fsm_state_str[] = {
+        "DCACHE_IDLE",       
+        "DCACHE_BIS",   
+        "DCACHE_DTLB1_READ_CACHE",
+	"DCACHE_TLB1_LL_WAIT",
+	"DCACHE_TLB1_SC_WAIT",    
+        "DCACHE_TLB1_READ",
+        "DCACHE_TLB1_READ_UPDT",
+	"DCACHE_TLB1_UPDT_SEL",  
+        "DCACHE_TLB1_UPDT", 
+        "DCACHE_DTLB2_READ_CACHE", 
+	"DCACHE_TLB2_LL_WAIT",
+	"DCACHE_TLB2_SC_WAIT",   
+        "DCACHE_TLB2_READ",
+        "DCACHE_TLB2_READ_UPDT",  
+	"DCACHE_TLB2_UPDT_SEL",
+        "DCACHE_TLB2_UPDT",   
+        "DCACHE_CTXT_SWITCH",   
+        "DCACHE_ICACHE_FLUSH", 
+        "DCACHE_DCACHE_FLUSH", 
+        "DCACHE_ITLB_INVAL",
+        "DCACHE_DTLB_INVAL",
+        "DCACHE_ICACHE_INVAL",
+        "DCACHE_DCACHE_INVAL",
+	"DCACHE_ICACHE_INVAL_PA",
+	"DCACHE_DCACHE_INVAL_PA",
+	"DCACHE_DCACHE_SYNC",
+	"DCACHE_LL_DIRTY_WAIT",
+	"DCACHE_SC_DIRTY_WAIT",
+        "DCACHE_WRITE_UPDT", 
+        "DCACHE_WRITE_DIRTY",
+        "DCACHE_WRITE_REQ",  
+        "DCACHE_MISS_WAIT",  
+        "DCACHE_MISS_UPDT",  
+        "DCACHE_UNC_WAIT",   
+        "DCACHE_ERROR", 
+        "DCACHE_ITLB_READ",
+        "DCACHE_ITLB_UPDT",
+        "DCACHE_ITLB_LL_WAIT",        
+        "DCACHE_ITLB_SC_WAIT",        
+        "DCACHE_CC_CHECK",
+        "DCACHE_CC_INVAL",
+        "DCACHE_CC_UPDT",
+        "DCACHE_CC_NOP",
+        "DCACHE_TLB_CC_INVAL",
+        "DCACHE_ITLB_CLEANUP",
+    };
+const char *cmd_fsm_state_str[] = {
+        "CMD_IDLE",           
+        "CMD_ITLB_READ", 
+        "CMD_ITLB_ACC_LL",                
+        "CMD_ITLB_ACC_SC",                
+        "CMD_INS_MISS",     
+        "CMD_INS_UNC",     
+        "CMD_DTLB_READ",   
+        "CMD_DTLB_ACC_LL",            
+        "CMD_DTLB_ACC_SC",            
+        "CMD_DTLB_DIRTY_LL",          
+        "CMD_DTLB_DIRTY_SC",          
+        "CMD_DATA_UNC",     
+        "CMD_DATA_MISS",    
+        "CMD_DATA_WRITE", 
+    };
+const char *rsp_fsm_state_str[] = {
+        "RSP_IDLE",                  
+        "RSP_ITLB_READ",             
+        "RSP_ITLB_ACC_LL",                
+        "RSP_ITLB_ACC_SC",                
+        "RSP_INS_MISS",   
+        "RSP_INS_UNC",           
+        "RSP_DTLB_READ",            
+        "RSP_DTLB_ACC_LL",            
+        "RSP_DTLB_ACC_SC",            
+        "RSP_DTLB_DIRTY_LL",          
+        "RSP_DTLB_DIRTY_SC",          
+        "RSP_DATA_MISS",             
+        "RSP_DATA_UNC",              
+        "RSP_DATA_WRITE",     
+    };
+const char *cleanup_cmd_fsm_state_str[] = {
+        "CLEANUP_CMD_IDLE",           
+        "CLEANUP_CMD_DATA",    
+        "CLEANUP_CMD_INS",      
+    };
+const char *cleanup_rsp_fsm_state_str[] = {
+        "CLEANUP_RSP_IDLE",           
+        "CLEANUP_RSP_DATA",    
+        "CLEANUP_RSP_INS",      
+    };
+const char *tgt_fsm_state_str[] = {
+        "TGT_IDLE",
+        "TGT_UPDT_WORD",
+        "TGT_UPDT_DATA",
+        "TGT_REQ_BROADCAST",
+        "TGT_REQ_ICACHE",
+        "TGT_REQ_DCACHE",
+        "TGT_RSP_BROADCAST",
+        "TGT_RSP_ICACHE",
+        "TGT_RSP_DCACHE",
+    };	
+const char *inval_itlb_fsm_state_str[] = {
+        "INVAL_ITLB_IDLE",        
+        "INVAL_ITLB_CHECK"  , 
+        "INVAL_ITLB_INVAL",      
+        "INVAL_ITLB_CLEAR",           
+    };
+const char *inval_dtlb_fsm_state_str[] = {
+        "INVAL_DTLB_IDLE",        
+        "INVAL_DTLB_CHECK", 
+        "INVAL_DTLB_INVAL",    
+        "INVAL_DTLB_CLEAR",         
+    };
+}
+//#endif
+
+#define tmpl(...)  template<typename vci_param, typename iss_t> __VA_ARGS__ VciCcVCacheWrapper2V1<vci_param, iss_t>
+
+using soclib::common::uint32_log2;
+
+/***********************************************/
+tmpl(/**/)::VciCcVCacheWrapper2V1(
+    sc_module_name name,
+    int proc_id,
+    const soclib::common::MappingTable &mtp,
+    const soclib::common::MappingTable &mtc,
+    const soclib::common::IntTab &initiator_index_rw,
+    const soclib::common::IntTab &initiator_index_c,
+    const soclib::common::IntTab &target_index,
+    size_t itlb_ways,
+    size_t itlb_sets,
+    size_t dtlb_ways,
+    size_t dtlb_sets,
+    size_t icache_ways,
+    size_t icache_sets,
+    size_t icache_words,
+    size_t dcache_ways,
+    size_t dcache_sets,
+    size_t dcache_words,
+    size_t write_buf_size )
+/***********************************************/
+    : soclib::caba::BaseModule(name),
+
+      p_clk("clk"),
+      p_resetn("resetn"),
+      p_vci_ini_rw("vci_ini_rw"),
+      p_vci_ini_c("vci_ini_c"),
+      p_vci_tgt("vci_tgt"),
+
+      m_cacheability_table(mtp.getCacheabilityTable()),
+      m_segment(mtc.getSegment(target_index)),
+      m_iss(this->name(), proc_id),
+      m_srcid_rw(mtp.indexForId(initiator_index_rw)),
+      m_srcid_c(mtp.indexForId(initiator_index_c)),
+
+      m_itlb_ways(itlb_ways),
+      m_itlb_sets(itlb_sets),
+
+      m_dtlb_ways(dtlb_ways),
+      m_dtlb_sets(dtlb_sets),
+
+      m_icache_ways(icache_ways),
+      m_icache_sets(icache_sets),
+      m_icache_yzmask((~0)<<(uint32_log2(icache_words) + 2)),
+      m_icache_words(icache_words),
+
+      m_dcache_ways(dcache_ways),
+      m_dcache_sets(dcache_sets),
+      m_dcache_yzmask((~0)<<(uint32_log2(dcache_words) + 2)),
+      m_dcache_words(dcache_words),
+
+      m_write_buf_size(write_buf_size),	
+      m_paddr_nbits(vci_param::N),
+
+      icache_tlb(itlb_ways,itlb_sets,vci_param::N),
+      dcache_tlb(dtlb_ways,dtlb_sets,vci_param::N),
+
+      r_dcache_fsm("r_dcache_fsm"),
+      r_dcache_paddr_save("r_dcache_paddr_save"),
+      r_dcache_wdata_save("r_dcache_wdata_save"),
+      r_dcache_rdata_save("r_dcache_rdata_save"),
+      r_dcache_type_save("r_dcache_type_save"),
+      r_dcache_be_save("r_dcache_be_save"),
+      r_dcache_cached_save("r_dcache_cached_save"),
+      r_dcache_tlb_paddr("r_dcache_tlb_paddr"),
+      r_dcache_miss_req("r_dcache_miss_req"),
+      r_dcache_unc_req("r_dcache_unc_req"),
+      r_dcache_write_req("r_dcache_write_req"),
+      r_dcache_tlb_read_req("r_dcache_tlb_read_req"),
+
+      r_dcache_tlb_ll_acc_req("r_dcache_tlb_ll_acc_req"),       
+      r_dcache_tlb_sc_acc_req("r_dcache_tlb_sc_acc_req"),       
+      r_dcache_tlb_ll_dirty_req("r_dcache_tlb_ll_dirty_req"),    
+      r_dcache_tlb_sc_dirty_req("r_dcache_tlb_sc_dirty_req"), 
+      r_dcache_tlb_ptba_read("r_dcache_tlb_ptba_read"),
+      r_dcache_xtn_req("r_dcache_xtn_req"),
+
+      r_dcache_fsm_save("r_dcache_fsm_save"),
+      r_dcache_cleanup_req("r_dcache_cleanup_req"),
+      r_dcache_inval_rsp("r_dcache_inval_rsp"),
+
+      r_icache_fsm("r_icache_fsm"),
+      r_icache_paddr_save("r_icache_paddr_save"),
+      r_icache_miss_req("r_icache_miss_req"),
+      r_icache_unc_req("r_icache_unc_req"),
+      r_dcache_itlb_read_req("r_dcache_itlb_read_req"),
+      r_dcache_itlb_ll_acc_req("r_dcache_itlb_ll_acc_req"),     
+      r_dcache_itlb_sc_acc_req("r_dcache_itlb_sc_acc_req"),
+
+      r_itlb_read_dcache_req("r_itlb_read_dcache_req"),
+      r_itlb_k_read_dcache("r_itlb_k_read_dcache"),
+      r_itlb_acc_dcache_req("r_itlb_acc_dcache_req"),
+      r_dcache_rsp_itlb_error("r_dcache_rsp_itlb_error"),
+
+      r_icache_fsm_save("r_icache_fsm_save"),
+      r_icache_cleanup_req("r_icache_cleanup_req"),
+      r_icache_inval_rsp("r_icache_inval_rsp"),
+
+      r_vci_cmd_fsm("r_vci_cmd_fsm"),
+      r_vci_cmd_min("r_vci_cmd_min"),
+      r_vci_cmd_max("r_vci_cmd_max"),
+      r_vci_cmd_cpt("r_vci_cmd_cpt"),
+
+      r_vci_rsp_fsm("r_vci_rsp_fsm"),
+      r_vci_rsp_cpt("r_vci_rsp_cpt"),
+      r_vci_rsp_ins_error("r_vci_rsp_ins_error"),
+      r_vci_rsp_data_error("r_vci_rsp_data_error"),
+      r_dcache_tlb_sc_fail("r_dcache_tlb_sc_fail"),
+
+      r_cleanup_cmd_fsm("r_cleanup_cmd_fsm"),
+      r_cleanup_rsp_fsm("r_cleanup_rsp_fsm"),
+
+      r_vci_tgt_fsm("r_vci_tgt_fsm"),
+      r_tgt_addr("r_tgt_addr"),
+      r_tgt_word("r_tgt_word"),
+      r_tgt_update("r_tgt_update"),
+      r_tgt_srcid("r_tgt_srcid"),
+      r_tgt_pktid("r_tgt_pktid"),
+      r_tgt_trdid("r_tgt_trdid"),
+      r_tgt_icache_req("r_tgt_icache_req"),
+      r_tgt_dcache_req("r_tgt_dcache_req"),
+
+      r_inval_itlb_fsm("r_inval_itlb_fsm"),          
+      r_dcache_itlb_inval_req("r_dcache_itlb_inval_req"),
+      r_dcache_itlb_inval_line("r_dcache_itlb_inval_line"),
+      r_itlb_cc_check_end("r_itlb_cc_check_end"),
+      r_ccinval_itlb_way("r_ccinval_itlb_way"), 
+      r_ccinval_itlb_set("r_ccinval_itlb_set"), 
+      r_icache_inval_tlb_rsp("r_icache_inval_tlb_rsp"),
+      r_icache_tlb_nline("r_icache_tlb_nline"),
+
+      r_inval_dtlb_fsm("r_inval_dtlb_fsm"),          
+      r_dcache_dtlb_inval_req("r_dcache_dtlb_inval_req"),
+      r_dcache_dtlb_inval_line("r_dcache_dtlb_inval_line"),
+      r_dtlb_cc_check_end("r_dtlb_cc_check_end"),
+      r_ccinval_dtlb_way("r_ccinval_dtlb_way"), 
+      r_ccinval_dtlb_set("r_ccinval_dtlb_set"), 
+      r_dcache_inval_tlb_rsp("r_dcache_inval_tlb_rsp"),
+      r_dcache_tlb_nline("r_dcache_tlb_nline"),
+
+      r_dcache_itlb_cleanup_req("r_dcache_itlb_cleanup_req"),
+      r_dcache_itlb_cleanup_line("r_dcache_itlb_cleanup_line"),
+
+      r_dcache_dtlb_cleanup_req("r_dcache_dtlb_cleanup_req"),
+      r_dcache_dtlb_cleanup_line("r_dcache_dtlb_cleanup_line"),
+
+      r_wbuf("wbuf", write_buf_size ),
+      r_icache("icache", icache_ways, icache_sets, icache_words),
+      r_dcache("dcache", dcache_ways, dcache_sets, dcache_words)
+{
+    r_icache_miss_buf = new data_t[icache_words];
+    r_dcache_miss_buf = new data_t[dcache_words];
+    r_tgt_buf         = new data_t[dcache_words];
+    r_tgt_val         = new bool[dcache_words];
+    r_dcache_in_itlb  = new bool[dcache_ways*dcache_sets];           
+    r_dcache_in_dtlb  = new bool[dcache_ways*dcache_sets];          
+
+    SC_METHOD(transition);
+    dont_initialize();
+    sensitive << p_clk.pos();
+  
+    SC_METHOD(genMoore);
+    dont_initialize();
+    sensitive << p_clk.neg();
+
+    typename iss_t::CacheInfo cache_info;
+    cache_info.has_mmu = true;
+    cache_info.icache_line_size = icache_words*sizeof(data_t);
+    cache_info.icache_assoc = icache_ways;
+    cache_info.icache_n_lines = icache_sets;
+    cache_info.dcache_line_size = dcache_words*sizeof(data_t);
+    cache_info.dcache_assoc = dcache_ways;
+    cache_info.dcache_n_lines = dcache_sets;
+    m_iss.setCacheInfo(cache_info);
+}
+
+/////////////////////////////////////
+tmpl(/**/)::~VciCcVCacheWrapper2V1()
+/////////////////////////////////////
+{
+    delete [] r_icache_miss_buf;
+    delete [] r_dcache_miss_buf;
+    delete [] r_tgt_val;
+    delete [] r_tgt_buf;
+    delete [] r_dcache_in_itlb;           
+    delete [] r_dcache_in_dtlb;          
+}
+
+////////////////////////
+tmpl(void)::print_cpi()
+////////////////////////
+{
+    std::cout << name() << " CPI = " 
+        << (float)m_cpt_total_cycles/(m_cpt_total_cycles - m_cpt_frz_cycles) << std::endl ;
+}
+
+////////////////////////////////////
+tmpl(void)::print_trace(size_t mode)
+////////////////////////////////////
+{
+    typename iss_t::InstructionRequest  ireq;
+    typename iss_t::DataRequest         dreq;
+
+    m_iss.getRequests( ireq, dreq );
+   
+    std::cout << std::dec << "L1_(" << name() << ") cycle: " << m_cpt_total_cycles << std::endl;
+    std::cout << " Proc state: PC = " << std::hex << ireq.addr << " / AD = " << dreq.addr 
+              << std::dec << " / V = " << dreq.valid << " / TYPE = " << dreq.type << std::endl;
+    
+    std::cout << " Cache state:"
+              << " tgt fsm: " << tgt_fsm_state_str[r_vci_tgt_fsm]
+              << " dcache fsm: " << dcache_fsm_state_str[r_dcache_fsm]
+              << " icache fsm: " << icache_fsm_state_str[r_icache_fsm]
+              << " cmd fsm: " << cmd_fsm_state_str[r_vci_cmd_fsm]
+              << " rsp fsm: " << rsp_fsm_state_str[r_vci_rsp_fsm] 
+              << " cleanup cmd fsm: " << cleanup_cmd_fsm_state_str[r_cleanup_cmd_fsm]
+              << " cleanup rsp fsm: " << cleanup_rsp_fsm_state_str[r_cleanup_rsp_fsm]
+              << " inval itlb fsm: " << inval_itlb_fsm_state_str[r_inval_itlb_fsm] 
+              << " inval dtlb fsm: " << inval_dtlb_fsm_state_str[r_inval_dtlb_fsm] << std::endl;
+
+    if( r_vci_tgt_fsm != TGT_IDLE ) 
+        std::cout << "    ... coherence request address = " << std::hex << r_tgt_addr.read() << std::endl;
+    
+    if(mode & 0x1)
+    {
+        r_wbuf.printTrace();
+    }
+}
+
+////////////////////////
+tmpl(void)::print_stats()
+////////////////////////
+{
+    float run_cycles = (float)(m_cpt_total_cycles - m_cpt_frz_cycles);
+    std::cout << name() << std::endl
+        << "- CPI                    = " << (float)m_cpt_total_cycles/run_cycles << std::endl 
+        << "- READ RATE              = " << (float)m_cpt_read/run_cycles << std::endl 
+        << "- WRITE RATE             = " << (float)m_cpt_write/run_cycles << std::endl
+        << "- IMISS_RATE             = " << (float)m_cpt_ins_miss/m_cpt_ins_read << std::endl
+        << "- DMISS RATE             = " << (float)m_cpt_data_miss/(m_cpt_read-m_cpt_unc_read) << std::endl  
+        << "- INS MISS COST          = " << (float)m_cost_ins_miss_frz/m_cpt_ins_miss << std::endl     
+        << "- DATA MISS COST         = " << (float)m_cost_data_miss_frz/m_cpt_data_miss << std::endl 
+        << "- WRITE COST             = " << (float)m_cost_write_frz/m_cpt_write << std::endl        
+        << "- UNC COST               = " << (float)m_cost_unc_read_frz/m_cpt_unc_read << std::endl
+        << "- UNCACHED READ RATE     = " << (float)m_cpt_unc_read/m_cpt_read << std::endl 
+        << "- CACHED WRITE RATE      = " << (float)m_cpt_write_cached/m_cpt_write << std::endl 
+        << "- INS TLB MISS RATE      = " << (float)m_cpt_ins_tlb_miss/m_cpt_ins_tlb_read << std::endl
+        << "- DATA TLB MISS RATE     = " << (float)m_cpt_data_tlb_miss/m_cpt_data_tlb_read << std::endl
+        << "- ITLB MISS COST         = " << (float)m_cost_ins_tlb_miss_frz/m_cpt_ins_tlb_miss << std::endl
+        << "- DTLB MISS COST         = " << (float)m_cost_data_tlb_miss_frz/m_cpt_data_tlb_miss << std::endl   
+        << "- ITLB UPDATE ACC COST   = " << (float)m_cost_ins_tlb_update_acc_frz/m_cpt_ins_tlb_update_acc << std::endl
+        << "- DTLB UPDATE ACC COST   = " << (float)m_cost_data_tlb_update_acc_frz/m_cpt_data_tlb_update_acc << std::endl
+        << "- DTLB UPDATE DIRTY COST = " << (float)m_cost_data_tlb_update_dirty_frz/m_cpt_data_tlb_update_dirty << std::endl
+        << "- ITLB HIT IN DCACHE RATE= " << (float)m_cpt_ins_tlb_hit_dcache/m_cpt_ins_tlb_miss << std::endl
+        << "- DTLB HIT IN DCACHE RATE= " << (float)m_cpt_data_tlb_hit_dcache/m_cpt_data_tlb_miss << std::endl
+        << "- DCACHE FROZEN BY ITLB  = " << (float)m_cost_ins_tlb_occup_cache_frz/m_cpt_dcache_frz_cycles << std::endl
+        << "- DCACHE FOR TLB %       = " << (float)m_cpt_tlb_occup_dcache/(m_dcache_ways*m_dcache_sets) << std::endl
+        << "- NB CC BROADCAST        = " << m_cpt_cc_broadcast << std::endl
+        << "- NB CC UPDATE DATA      = " << m_cpt_cc_update_data << std::endl
+        << "- NB CC INVAL DATA       = " << m_cpt_cc_inval_data << std::endl
+        << "- NB CC INVAL INS        = " << m_cpt_cc_inval_ins << std::endl
+        << "- CC BROADCAST COST      = " << (float)m_cost_broadcast_frz/m_cpt_cc_broadcast << std::endl
+        << "- CC UPDATE DATA COST    = " << (float)m_cost_updt_data_frz/m_cpt_cc_update_data << std::endl
+        << "- CC INVAL DATA COST     = " << (float)m_cost_inval_data_frz/m_cpt_cc_inval_data << std::endl
+        << "- CC INVAL INS COST      = " << (float)m_cost_inval_ins_frz/m_cpt_cc_inval_ins << std::endl
+        << "- NB CC CLEANUP DATA     = " << m_cpt_cc_cleanup_data << std::endl
+        << "- NB CC CLEANUP INS      = " << m_cpt_cc_cleanup_ins << std::endl
+        << "- IMISS TRANSACTION      = " << (float)m_cost_imiss_transaction/m_cpt_imiss_transaction << std::endl
+        << "- DMISS TRANSACTION      = " << (float)m_cost_dmiss_transaction/m_cpt_dmiss_transaction << std::endl
+        << "- UNC TRANSACTION        = " << (float)m_cost_unc_transaction/m_cpt_unc_transaction << std::endl
+        << "- WRITE TRANSACTION      = " << (float)m_cost_write_transaction/m_cpt_write_transaction << std::endl
+        << "- WRITE LENGTH           = " << (float)m_length_write_transaction/m_cpt_write_transaction << std::endl
+        << "- ITLB MISS TRANSACTION  = " << (float)m_cost_itlbmiss_transaction/m_cpt_itlbmiss_transaction << std::endl
+        << "- DTLB MISS TRANSACTION  = " << (float)m_cost_dtlbmiss_transaction/m_cpt_dtlbmiss_transaction << std::endl;
+}
+
+////////////////////////
+tmpl(void)::clear_stats()
+////////////////////////
+{
+    m_cpt_dcache_data_read  = 0;
+    m_cpt_dcache_data_write = 0;
+    m_cpt_dcache_dir_read   = 0;
+    m_cpt_dcache_dir_write  = 0;
+    m_cpt_icache_data_read  = 0;
+    m_cpt_icache_data_write = 0;
+    m_cpt_icache_dir_read   = 0;
+    m_cpt_icache_dir_write  = 0;
+    
+    m_cpt_frz_cycles        = 0;
+    m_cpt_dcache_frz_cycles = 0;
+    m_cpt_total_cycles      = 0;
+    
+    m_cpt_read         = 0;
+    m_cpt_write        = 0;
+    m_cpt_data_miss    = 0;
+    m_cpt_ins_miss     = 0;
+    m_cpt_unc_read     = 0;
+    m_cpt_write_cached = 0;
+    m_cpt_ins_read     = 0;
+    
+    m_cost_write_frz     = 0;
+    m_cost_data_miss_frz = 0;
+    m_cost_unc_read_frz  = 0;
+    m_cost_ins_miss_frz  = 0;
+    
+    m_cpt_imiss_transaction      = 0;
+    m_cpt_dmiss_transaction      = 0;
+    m_cpt_unc_transaction        = 0;
+    m_cpt_write_transaction      = 0;
+    m_cpt_icache_unc_transaction = 0;	
+    
+    m_cost_imiss_transaction      = 0;
+    m_cost_dmiss_transaction      = 0;
+    m_cost_unc_transaction        = 0;
+    m_cost_write_transaction      = 0;
+    m_cost_icache_unc_transaction = 0;
+    m_length_write_transaction    = 0;
+    
+    m_cpt_ins_tlb_read       = 0;             
+    m_cpt_ins_tlb_miss       = 0;             
+    m_cpt_ins_tlb_update_acc = 0;         
+    
+    m_cpt_data_tlb_read         = 0;           
+    m_cpt_data_tlb_miss         = 0;           
+    m_cpt_data_tlb_update_acc   = 0;       
+    m_cpt_data_tlb_update_dirty = 0;    
+    m_cpt_ins_tlb_hit_dcache    = 0;
+    m_cpt_data_tlb_hit_dcache   = 0;
+    m_cpt_ins_tlb_occup_cache   = 0;
+    m_cpt_data_tlb_occup_cache  = 0;
+    
+    m_cost_ins_tlb_miss_frz          = 0;      
+    m_cost_data_tlb_miss_frz         = 0;      
+    m_cost_ins_tlb_update_acc_frz    = 0;
+    m_cost_data_tlb_update_acc_frz   = 0;
+    m_cost_data_tlb_update_dirty_frz = 0;
+    m_cost_ins_tlb_occup_cache_frz   = 0;
+    m_cost_data_tlb_occup_cache_frz  = 0;
+    
+    m_cpt_itlbmiss_transaction      = 0;    
+    m_cpt_itlb_ll_transaction       = 0;  
+    m_cpt_itlb_sc_transaction       = 0;  
+    m_cpt_dtlbmiss_transaction      = 0;  
+    m_cpt_dtlb_ll_transaction       = 0;  
+    m_cpt_dtlb_sc_transaction       = 0;  
+    m_cpt_dtlb_ll_dirty_transaction = 0;  
+    m_cpt_dtlb_sc_dirty_transaction = 0;  
+    
+    m_cost_itlbmiss_transaction      = 0;   
+    m_cost_itlb_ll_transaction       = 0;  
+    m_cost_itlb_sc_transaction       = 0;  
+    m_cost_dtlbmiss_transaction      = 0;   
+    m_cost_dtlb_ll_transaction       = 0;   
+    m_cost_dtlb_sc_transaction       = 0;   
+    m_cost_dtlb_ll_dirty_transaction = 0;   
+    m_cost_dtlb_sc_dirty_transaction = 0;
+
+    m_cpt_cc_update_data = 0;
+    m_cpt_cc_inval_ins   = 0;
+    m_cpt_cc_inval_data  = 0;
+    m_cpt_cc_broadcast   = 0;
+
+    m_cost_updt_data_frz  = 0;
+    m_cost_inval_ins_frz  = 0;
+    m_cost_inval_data_frz = 0;
+    m_cost_broadcast_frz  = 0;
+
+    m_cpt_cc_cleanup_data = 0;
+    m_cpt_cc_cleanup_ins  = 0;
+}
+
+/*************************************************/
+tmpl(void)::transition()
+/*************************************************/
+{
+    if ( ! p_resetn.read() ) 
+    {
+        m_iss.reset();
+
+        r_dcache_fsm = DCACHE_IDLE;
+        r_icache_fsm = ICACHE_IDLE;
+        r_vci_cmd_fsm = CMD_IDLE;
+        r_vci_rsp_fsm = RSP_IDLE;
+        r_vci_tgt_fsm = TGT_IDLE;
+        r_inval_itlb_fsm = INVAL_ITLB_IDLE;          
+        r_inval_dtlb_fsm = INVAL_DTLB_IDLE;          
+        r_cleanup_cmd_fsm = CLEANUP_CMD_IDLE;
+        r_cleanup_rsp_fsm = CLEANUP_RSP_IDLE;
+
+        // write buffer & caches
+        r_wbuf.reset();
+        r_icache.reset();
+        r_dcache.reset();
+
+        icache_tlb.reset();    
+        dcache_tlb.reset();    
+
+        std::memset(r_dcache_in_itlb, 0, sizeof(*r_dcache_in_itlb)*m_icache_ways*m_icache_sets);
+        std::memset(r_dcache_in_dtlb, 0, sizeof(*r_dcache_in_dtlb)*m_dcache_ways*m_dcache_sets);
+
+        //r_mmu_mode = ALL_DEACTIVE;
+        r_mmu_mode = 0x3;
+        r_mmu_params = (uint32_log2(m_dtlb_ways) << 29)   | (uint32_log2(m_dtlb_sets) << 25)   |
+                       (uint32_log2(m_dcache_ways) << 22) | (uint32_log2(m_dcache_sets) << 18) |
+                       (uint32_log2(m_itlb_ways) << 15)   | (uint32_log2(m_itlb_sets) << 11)   |
+                       (uint32_log2(m_icache_ways) << 8)  | (uint32_log2(m_icache_sets) << 4)  |
+                       (uint32_log2(m_icache_words * 4));
+        r_mmu_release = (uint32_t)(1 << 16) | 0x1;
+
+        r_icache_miss_req         = false;
+        r_icache_unc_req          = false;
+        r_dcache_itlb_read_req    = false;
+
+        r_itlb_read_dcache_req    = false;      
+        r_itlb_k_read_dcache      = false;      
+        r_itlb_acc_dcache_req     = false;   
+	r_itlb_acc_redo_req 	  = false;
+        r_dcache_rsp_itlb_error   = false;
+ 
+        r_dcache_miss_req         = false;
+        r_dcache_unc_req          = false;
+        r_dcache_write_req        = false;
+        r_dcache_tlb_read_req     = false;
+        r_dcache_tlb_ptba_read    = false;
+        r_dcache_xtn_req          = false;
+	r_dcache_llsc_reserved    = false;
+
+        r_dcache_tlb_ll_acc_req   = false;    
+        r_dcache_tlb_sc_acc_req   = false;    
+        r_dcache_tlb_ll_dirty_req = false;   
+        r_dcache_tlb_sc_dirty_req = false; 
+        r_dcache_sc_updt_dirty    = false;	
+        r_dcache_itlb_ll_acc_req  = false;   
+        r_dcache_itlb_sc_acc_req  = false;   
+
+        r_icache_cleanup_req      = false;
+        r_dcache_cleanup_req      = false;
+
+        r_tgt_icache_req          = false;
+        r_tgt_dcache_req          = false;
+
+        r_icache_inval_rsp        = false;
+        r_dcache_inval_rsp        = false;
+
+        r_dcache_dirty_save       = false;
+        r_dcache_hit_p_save       = false;
+        r_dcache_cached_save      = false;
+
+        r_icache_buf_unc_valid    = false;
+        r_dcache_buf_unc_valid    = false;
+
+        r_vci_rsp_ins_error       = false;
+        r_vci_rsp_data_error      = false;
+
+        r_icache_id1_save         = 0;
+        r_icache_ppn_save         = 0;
+        r_icache_vpn_save         = 0;
+        r_itlb_translation_valid  = false;
+
+        r_dcache_id1_save         = 0;
+        r_dcache_ppn_save         = 0;
+        r_dcache_vpn_save         = 0;
+        r_dtlb_translation_valid  = false;
+
+        r_icache_ptba_ok          = false;
+        r_dcache_ptba_ok          = false;
+
+        r_icache_error_type       = MMU_NONE;
+        r_dcache_error_type       = MMU_NONE;
+
+        // coherence registers
+        r_icache_way              = 0;
+        r_icache_set              = 0;
+        r_icache_cleanup_req      = false;
+        r_icache_inval_rsp        = false;
+
+        r_dcache_way              = 0;
+        r_dcache_set              = 0;
+        r_dcache_cleanup_req      = false;
+        r_dcache_inval_rsp        = false;
+
+	r_itlb_inval_req 	  = false;
+        r_dcache_itlb_inval_req   = false;
+        r_itlb_cc_check_end       = false;
+        r_ccinval_itlb_way        = 0; 
+        r_ccinval_itlb_set        = 0; 
+        r_icache_inval_tlb_rsp    = false;
+
+        r_dcache_dtlb_inval_req   = false;
+        r_dtlb_cc_check_end       = false;
+        r_ccinval_dtlb_way        = 0; 
+        r_ccinval_dtlb_set        = 0; 
+        r_dcache_inval_tlb_rsp    = false;
+
+        r_dcache_itlb_cleanup_req = false;
+        r_dcache_dtlb_cleanup_req = false;
+
+	r_dcache_cc_check         = false;
+	r_dcache_tlb_sc_fail	  = false;
+
+        // activity counters
+        m_cpt_dcache_data_read  = 0;
+        m_cpt_dcache_data_write = 0;
+        m_cpt_dcache_dir_read   = 0;
+        m_cpt_dcache_dir_write  = 0;
+        m_cpt_icache_data_read  = 0;
+        m_cpt_icache_data_write = 0;
+        m_cpt_icache_dir_read   = 0;
+        m_cpt_icache_dir_write  = 0;
+
+	m_cpt_frz_cycles        = 0;
+        m_cpt_dcache_frz_cycles = 0;
+	m_cpt_total_cycles      = 0;
+
+        m_cpt_read         = 0;
+        m_cpt_write        = 0;
+        m_cpt_data_miss    = 0;
+        m_cpt_ins_miss     = 0;
+        m_cpt_unc_read     = 0;
+        m_cpt_write_cached = 0;
+        m_cpt_ins_read     = 0;
+
+        m_cost_write_frz     = 0;
+        m_cost_data_miss_frz = 0;
+        m_cost_unc_read_frz  = 0;
+        m_cost_ins_miss_frz  = 0;
+
+        m_cpt_imiss_transaction      = 0;
+        m_cpt_dmiss_transaction      = 0;
+        m_cpt_unc_transaction        = 0;
+        m_cpt_write_transaction      = 0;
+        m_cpt_icache_unc_transaction = 0;	
+
+        m_cost_imiss_transaction      = 0;
+        m_cost_dmiss_transaction      = 0;
+        m_cost_unc_transaction        = 0;
+        m_cost_write_transaction      = 0;
+	m_cost_icache_unc_transaction = 0;
+        m_length_write_transaction    = 0;
+
+        m_cpt_ins_tlb_read       = 0;             
+        m_cpt_ins_tlb_miss       = 0;             
+        m_cpt_ins_tlb_update_acc = 0;         
+
+        m_cpt_data_tlb_read         = 0;           
+        m_cpt_data_tlb_miss         = 0;           
+        m_cpt_data_tlb_update_acc   = 0;       
+        m_cpt_data_tlb_update_dirty = 0;    
+        m_cpt_ins_tlb_hit_dcache    = 0;
+        m_cpt_data_tlb_hit_dcache   = 0;
+        m_cpt_ins_tlb_occup_cache   = 0;
+        m_cpt_data_tlb_occup_cache  = 0;
+
+        m_cost_ins_tlb_miss_frz          = 0;      
+        m_cost_data_tlb_miss_frz         = 0;      
+        m_cost_ins_tlb_update_acc_frz    = 0;
+        m_cost_data_tlb_update_acc_frz   = 0;
+        m_cost_data_tlb_update_dirty_frz = 0;
+        m_cost_ins_tlb_occup_cache_frz   = 0;
+        m_cost_data_tlb_occup_cache_frz  = 0;
+
+    	m_cpt_ins_tlb_inval       = 0;           
+    	m_cpt_data_tlb_inval      = 0;          
+    	m_cost_ins_tlb_inval_frz  = 0;     
+    	m_cost_data_tlb_inval_frz = 0;         
+
+   	m_cpt_cc_update_data = 0;
+   	m_cpt_cc_inval_ins   = 0;
+   	m_cpt_cc_inval_data  = 0;
+   	m_cpt_cc_broadcast   = 0;
+
+   	m_cost_updt_data_frz  = 0;
+   	m_cost_inval_ins_frz  = 0;
+   	m_cost_inval_data_frz = 0;
+   	m_cost_broadcast_frz  = 0;
+
+   	m_cpt_cc_cleanup_data = 0;
+   	m_cpt_cc_cleanup_ins  = 0;
+
+        m_cpt_itlbmiss_transaction      = 0;    
+        m_cpt_itlb_ll_transaction       = 0;  
+        m_cpt_itlb_sc_transaction       = 0;  
+        m_cpt_dtlbmiss_transaction      = 0;  
+        m_cpt_dtlb_ll_transaction       = 0;  
+        m_cpt_dtlb_sc_transaction       = 0;  
+        m_cpt_dtlb_ll_dirty_transaction = 0;  
+        m_cpt_dtlb_sc_dirty_transaction = 0;  
+ 
+        m_cost_itlbmiss_transaction      = 0;   
+        m_cost_itlb_ll_transaction       = 0;  
+        m_cost_itlb_sc_transaction       = 0;  
+        m_cost_dtlbmiss_transaction      = 0;   
+        m_cost_dtlb_ll_transaction       = 0;   
+        m_cost_dtlb_sc_transaction       = 0;   
+        m_cost_dtlb_ll_dirty_transaction = 0;   
+        m_cost_dtlb_sc_dirty_transaction = 0;    
+        return;
+    }
+
+#ifdef SOCLIB_MODULE_DEBUG
+std::cout << name() << " cycle = " << std::dec << m_cpt_total_cycles  
+       	  << " tgt fsm: " << tgt_fsm_state_str[r_vci_tgt_fsm]
+       	  << " dcache fsm: " << dcache_fsm_state_str[r_dcache_fsm]
+       	  << " icache fsm: " << icache_fsm_state_str[r_icache_fsm]
+       	  << " cmd fsm: " << cmd_fsm_state_str[r_vci_cmd_fsm]
+       	  << " rsp fsm: " << rsp_fsm_state_str[r_vci_rsp_fsm] 
+          << " cleanup cmd fsm: " << cleanup_cmd_fsm_state_str[r_cleanup_cmd_fsm]
+          << " cleanup rsp fsm: " << cleanup_rsp_fsm_state_str[r_cleanup_rsp_fsm]
+       	  << " inval itlb fsm: " << inval_itlb_fsm_state_str[r_inval_itlb_fsm] 
+          << " inval dtlb fsm: " << inval_dtlb_fsm_state_str[r_inval_dtlb_fsm] << std::endl;
+#endif
+
+    m_cpt_total_cycles++;
+
+    typename iss_t::InstructionRequest ireq = ISS_IREQ_INITIALIZER;
+    typename iss_t::InstructionResponse irsp = ISS_IRSP_INITIALIZER;
+
+    typename iss_t::DataRequest dreq = ISS_DREQ_INITIALIZER;
+    typename iss_t::DataResponse drsp = ISS_DRSP_INITIALIZER;
+
+    m_iss.getRequests( ireq, dreq );
+
+#ifdef SOCLIB_MODULE_DEBUG
+    std::cout << name() << " Instruction Request: " << ireq << std::endl;
+    std::cout << name() << " Data Request: " << dreq << std::endl;
+#endif
+
+    /////////////////////////////////////////////////////////////////////
+    // The TGT_FSM controls the following ressources:
+    // - r_vci_tgt_fsm
+    // - r_tgt_buf[nwords]
+    // - r_tgt_val[nwords]
+    // - r_tgt_update
+    // - r_tgt_word
+    // - r_tgt_addr
+    // - r_tgt_srcid
+    // - r_tgt_trdid
+    // - r_tgt_pktid
+    // All VCI commands must be CMD_WRITE.
+    // If the VCI address offset is null, the command is an invalidate 
+    // request. It is an update request otherwise.
+    // The VCI_TGT FSM stores the external request arguments in the
+    // IDLE, UPDT_WORD & UPDT_DATA states. It sets the r_tgt_icache_req 
+    // & r_tgt_dcache_req flip-flops to signal the external request to 
+    // the ICACHE & DCACHE FSMs in the REQ state. It waits the completion
+    // of the update or invalidate request in the RSP state.
+    // -  for an invalidate request the VCI packet length is 1 word.
+    // The WDATA field contains the line index (i.e. the Z & Y fields).
+    // -  for an update request the VCI packet length is (n+2) words.
+    // The WDATA field of the first VCI word contains the line number.
+    // The WDATA field of the second VCI word contains the word index.
+    // The WDATA field of the n following words contains the values.
+    // -  for both invalidate & update requests, the VCI response
+    // is one single word.
+    // In case of errors in the VCI command packet, the simulation
+    // is stopped with an error message.
+    /////////////////////////////////////////////////////////////////////
+    
+    switch(r_vci_tgt_fsm) {
+    //////////////
+    case TGT_IDLE:
+    {
+        if ( p_vci_tgt.cmdval.read() ) 
+        {
+            paddr_t address = p_vci_tgt.address.read();
+
+            if ( p_vci_tgt.cmd.read() != vci_param::CMD_WRITE) 
+            {
+                std::cout << "error in component VCI_CC_VCACHE_WRAPPER " << name() << std::endl;
+                std::cout << "the received VCI command is not a write" << std::endl;
+                exit(0);
+            }
+
+            // multi-update or multi-invalidate for data type
+            if ( ( (address & 0x3) != 0x3 ) && ( ! m_segment.contains(address)) ) 
+            {
+                std::cout << "error in component VCI_CC_VCACHE_WRAPPER " << name() << std::endl;
+                std::cout << "out of segment VCI command received for a multi-updt or multi-inval request" << std::endl;
+                exit(0);
+            }
+
+            r_tgt_srcid = p_vci_tgt.srcid.read();
+            r_tgt_trdid = p_vci_tgt.trdid.read();
+            r_tgt_pktid = p_vci_tgt.pktid.read();
+            r_tgt_plen  = p_vci_tgt.plen.read(); // todo: wait L2 modification
+            r_tgt_addr  = (paddr_t)(p_vci_tgt.be.read() & 0x3) << 32 |
+			  (paddr_t)p_vci_tgt.wdata.read() * m_dcache_words * 4; 
+
+            if ( (address&0x3) == 0x3 ) // broadcast invalidate for data or instruction type
+            {
+                if ( ! p_vci_tgt.eop.read() ) 
+                {
+                    std::cout << "error in component VCI_CC_VCACHE_WRAPPER " << name() << std::endl;
+                    std::cout << "the BROADCAST INVALIDATE command length must be one word" << std::endl;
+                    exit(0);
+                }
+                r_tgt_update = false; 
+                r_vci_tgt_fsm = TGT_REQ_BROADCAST;
+                m_cpt_cc_broadcast++;
+		m_cost_broadcast_frz++;
+            }
+            else                // multi-update or multi-invalidate for data type
+            {
+                paddr_t cell = address - m_segment.baseAddress();   
+
+                if (cell == 0)                      // invalidate   
+                {                         
+                    if ( ! p_vci_tgt.eop.read() ) 
+                    {
+                        std::cout << "error in component VCI_CC_VCACHE_WRAPPER " << name() << std::endl;
+                        std::cout << "the MULTI-INVALIDATE command length must be one word" << std::endl;
+                        exit(0);
+                    }
+                    r_tgt_update = false; 
+                    r_vci_tgt_fsm = TGT_REQ_DCACHE;
+                    m_cpt_cc_inval_data++ ;
+	    	    m_cost_inval_data_frz++;
+                }
+                else if (cell == 4)                // update 
+                {                                
+                    if ( p_vci_tgt.eop.read() ) 
+                    {
+                        std::cout << "error in component VCI_CC_VCACHE_WRAPPER " << name() << std::endl;
+                        std::cout << "the MULTI-UPDATE command length must be N+2 words" << std::endl;
+                        exit(0);
+                    }
+                    r_tgt_update = true; 
+                    r_vci_tgt_fsm = TGT_UPDT_WORD;
+                    m_cpt_cc_update_data++ ;
+		    m_cost_updt_data_frz++;
+                }     
+		else if (cell == 8)
+		{
+                    if ( ! p_vci_tgt.eop.read() ) 
+                    {
+                        std::cout << "error in component VCI_CC_VCACHE_WRAPPER " << name() << std::endl;
+                        std::cout << "the MULTI-INVALIDATE command length must be one word" << std::endl;
+                        exit(0);
+                    }
+                    r_tgt_update = false; 
+                    r_vci_tgt_fsm = TGT_REQ_ICACHE;
+                    m_cpt_cc_inval_ins++ ;
+		    m_cost_inval_ins_frz++;
+		}
+            } // end if address    
+        } // end if cmdval
+        break;
+    }
+    ///////////////////
+    case TGT_UPDT_WORD:
+    {
+	m_cost_updt_data_frz++;
+
+        if (p_vci_tgt.cmdval.read()) 
+        {
+            if ( p_vci_tgt.eop.read() ) 
+            {
+                std::cout << "error in component VCI_CC_VCACHE_WRAPPER " << name() << std::endl;
+                std::cout << "the MULTI-UPDATE command length must be N+2 words" << std::endl;
+                exit(0);
+            }
+            for ( size_t i=0 ; i<m_dcache_words ; i++ ) r_tgt_val[i] = false;
+            r_tgt_word = p_vci_tgt.wdata.read(); // the first modified word index
+            r_vci_tgt_fsm = TGT_UPDT_DATA;
+        }
+        break;
+    }
+    ///////////////////
+    case TGT_UPDT_DATA:
+    {
+	m_cost_updt_data_frz++;
+
+        if (p_vci_tgt.cmdval.read()) 
+        {
+            size_t word = r_tgt_word.read();
+            if (word >= m_dcache_words) 
+            {
+                std::cout << "error in component VCI_CC_VCACHE_WRAPPER " << name() << std::endl;
+                std::cout << "the reveived MULTI-UPDATE command length is wrong" << std::endl;
+                exit(0);
+            }
+            r_tgt_buf[word] = p_vci_tgt.wdata.read();
+            if(p_vci_tgt.be.read())    r_tgt_val[word] = true;
+            r_tgt_word = word + 1;
+            if (p_vci_tgt.eop.read())  r_vci_tgt_fsm = TGT_REQ_DCACHE;
+        }
+        break;
+    }
+    ////////////////////////
+    case TGT_REQ_BROADCAST:
+    {
+	m_cost_broadcast_frz++;
+
+        if ( !r_tgt_icache_req.read() && !r_tgt_dcache_req.read() ) 
+        {
+            r_vci_tgt_fsm = TGT_RSP_BROADCAST; 
+            r_tgt_icache_req = true;
+            r_tgt_dcache_req = true;
+        }
+        break;
+    }
+    /////////////////////
+    case TGT_REQ_ICACHE:
+    {
+	m_cost_inval_ins_frz++;
+
+        if ( !r_tgt_icache_req.read() ) 
+        {
+            r_vci_tgt_fsm = TGT_RSP_ICACHE; 
+            r_tgt_icache_req = true;
+        }
+        break;
+    }
+    /////////////////////
+    case TGT_REQ_DCACHE:
+    {
+	if (r_tgt_update) 
+	    m_cost_updt_data_frz++;
+	else 
+	    m_cost_inval_data_frz++;
+
+        if ( !r_tgt_dcache_req.read() ) 
+        {
+            r_vci_tgt_fsm = TGT_RSP_DCACHE; 
+            r_tgt_dcache_req = true;
+        }
+        break;
+    }
+    ///////////////////////
+    case TGT_RSP_BROADCAST:
+    {
+	m_cost_broadcast_frz++;
+
+        // no response
+        if ( !r_tgt_icache_rsp.read() && !r_tgt_dcache_rsp.read() && !r_tgt_icache_req.read() && !r_tgt_dcache_req.read() )
+        {
+            r_vci_tgt_fsm = TGT_IDLE;
+            break;
+        }
+
+        if ( p_vci_tgt.rspack.read() && !r_tgt_icache_req.read() && !r_tgt_dcache_req.read() ) 
+        {
+            // one response
+            if ( !r_tgt_icache_rsp || !r_tgt_dcache_rsp )
+            {
+                r_vci_tgt_fsm = TGT_IDLE; 
+                r_tgt_icache_rsp = false;
+                r_tgt_dcache_rsp = false;
+            }
+
+            // if data and instruction have the inval line, need two responses  
+            if ( r_tgt_icache_rsp && r_tgt_dcache_rsp )
+            {
+                r_tgt_icache_rsp = false; // only reset one for respond the second time 
+            }
+        }
+        break;
+    }
+    /////////////////////
+    case TGT_RSP_ICACHE:
+    {
+	m_cost_inval_ins_frz++;
+
+	if ( (p_vci_tgt.rspack.read() || !r_tgt_icache_rsp.read()) && !r_tgt_icache_req.read() ) 
+        {
+            r_vci_tgt_fsm = TGT_IDLE;
+            r_tgt_icache_rsp = false; 
+        }
+        break;
+    }
+    /////////////////////
+    case TGT_RSP_DCACHE:
+    {
+	if (r_tgt_update) 
+	    m_cost_updt_data_frz++;
+	else 
+	    m_cost_inval_data_frz++;
+
+	if ( (p_vci_tgt.rspack.read() || !r_tgt_dcache_rsp.read()) && !r_tgt_dcache_req.read() )
+        {
+            r_vci_tgt_fsm = TGT_IDLE;
+            r_tgt_dcache_rsp = false; 
+        }
+        break;
+    }
+    } // end switch TGT_FSM
+
+    ////////////////////////////////////////////////////////////////////////////////////////
+    //      ICACHE_FSM
+    //
+    // There is 9 mutually exclusive conditions to exit the IDLE state.
+    // Four configurations corresponding to an XTN request from processor,
+    // - Flush TLB (in case of Context switch) => TLB_FLUSH state 
+    // - Flush cache => CACHE_FLUSH state 
+    // - Invalidate a TLB entry => TLB_INVAL state
+    // - Invalidate a cache line => CACHE_INVAL state
+    // Five configurations corresponding to various TLB or cache MISS :
+    // - TLB miss(in case hit_p miss) => TLB1_READ state
+    // - TLB miss(in case hit_p hit) => TLB2_READ state
+    // - Hit in TLB but VPN changed => BIS state
+    // - Cached read miss => MISS_REQ state
+    // - Uncache read miss => UNC_REQ state
+    // 
+    // In case of MISS, the controller writes a request in the r_icache_paddr_save register 
+    // and sets the corresponding request flip-flop : r_dcache_itlb_read_req, r_icache_miss_req 
+    // or r_icache_unc_req. These request flip-flops are reset by the VCI_RSP controller 
+    // when the response is ready in the ICACHE buffer.
+    //
+    // The DCACHE FSM signals XTN processor requests using the r_dcache_xtn_req flip-flop. 
+    // The request opcod and the address to be invalidated are transmitted
+    // in the r_dcache_paddr_save & r_dcache_wdata_save registers respectively.
+    // The request flip-flop is reset by the ICACHE_FSM when the operation is completed.
+    //
+    // The r_vci_rsp_ins_error flip-flop is set by the VCI_RSP FSM and reset
+    // by the ICACHE-FSM in the ICACHE_ERROR state.
+    //
+    //----------------------------------------------------------------------------------- 
+    // Instruction TLB: 
+    //  
+    // - int        ET          (00: unmapped; 01: unused or PTD)
+    //                          (10: PTE new;  11: PTE old      )
+    // - bool       cachable    (cached bit)
+    // - bool       writable    (** not used alwayse false) 
+    // - bool       executable  (executable bit)
+    // - bool       user        (access in user mode allowed)
+    // - bool       global      (PTE not invalidated by a TLB flush)
+    // - bool       dirty       (** not used alwayse false) 
+    // - uint32_t   vpn         (virtual page number)
+    // - uint32_t   ppn         (physical page number)
+    ////////////////////////////////////////////////////////////////////////////////////////
+
+    switch(r_icache_fsm) {
+
+    ////////////////
+    case ICACHE_IDLE:
+    {
+        pte_info_t  icache_pte_info;
+        paddr_t     tlb_ipaddr       = 0;    	// physical address obtained from TLB                         
+        paddr_t     spc_ipaddr       = 0;    	// physical adress obtained from PPN_save (speculative)       
+        data_t      icache_ins       = 0;    	// read instruction
+        bool        icache_hit_c     = false;	// Cache hit
+        bool        icache_cached    = false;	// cacheable access (read)
+        bool        icache_hit_t     = false;	// hit on TLB
+        bool        icache_hit_x     = false;	// VPN unmodified (can use spc_dpaddr)
+        bool        icache_hit_p     = false;	// PTP unmodified (can skip first level page table walk)
+        size_t      icache_tlb_way   = 0;    	// selected way (in case of cache hit)
+        size_t      icache_tlb_set   = 0;    	// selected set (Y field in address)
+        paddr_t     icache_tlb_nline = 0;  	// TLB NLINE 
+
+        // Decoding processor XTN requests
+        // They are sent by DCACHE FSM  
+
+        if (r_dcache_xtn_req)
+        {
+            if ((int)r_dcache_type_save == (int)iss_t::XTN_PTPR )  
+            {
+                r_icache_way = 0;
+                r_icache_set = 0;
+                r_icache_fsm = ICACHE_SW_FLUSH;   
+                break;
+            }
+            if ((int)r_dcache_type_save == (int)iss_t::XTN_ICACHE_FLUSH)
+            {
+                r_icache_way = 0;
+                r_icache_set = 0;
+                r_icache_fsm = ICACHE_CACHE_FLUSH;   
+                break;
+            }
+            if ((int)r_dcache_type_save == (int)iss_t::XTN_ITLB_INVAL) 
+            {
+                r_icache_fsm = ICACHE_TLB_INVAL;   
+                break;
+            }
+            if ((int)r_dcache_type_save == (int)iss_t::XTN_ICACHE_INVAL) 
+            {
+                r_icache_fsm = ICACHE_CACHE_INVAL;   
+                break;
+            }
+            if ((int)r_dcache_type_save == (int)iss_t::XTN_MMU_ICACHE_PA_INV) 
+            {
+                r_icache_fsm = ICACHE_CACHE_INVAL_PA;   
+                break;
+            }
+            if ((int)r_dcache_type_save == (int)iss_t::XTN_DCACHE_FLUSH )  
+            {
+                // special for ins tlb miss via data cache
+                r_icache_fsm = ICACHE_TLB_FLUSH;   
+                break;
+            }
+        } // end if xtn_req
+
+        // external cache invalidate request
+        if ( r_tgt_icache_req )
+        {
+            r_icache_fsm = ICACHE_CC_INVAL;
+            r_icache_fsm_save = r_icache_fsm;
+            break;
+        }
+
+        // external tlb invalidate request
+        if ( r_dcache_itlb_inval_req )
+        {
+	    r_itlb_inval_req = true;
+            r_icache_fsm = ICACHE_TLB_CC_INVAL;
+            r_icache_fsm_save = r_icache_fsm;
+            break;
+        }
+
+        // icache_hit_t_m, icache_hit_t_k, icache_hit_x, icache_hit_p 
+        // icache_pte_info, icache_tlb_way, icache_tlb_set & ipaddr & cacheability 
+        // - If MMU activated : cacheability is defined by the cachable bit in the TLB
+        // - If MMU not activated : cacheability is defined by the segment table.
+
+        if ( !(r_mmu_mode.read() & INS_TLB_MASK) )   // MMU not activated 
+        {
+            icache_hit_t  = true;         
+            icache_hit_x  = true;         
+            icache_hit_p  = true;         
+            tlb_ipaddr    = ireq.addr;
+            spc_ipaddr    = ireq.addr;
+            icache_cached = m_cacheability_table[ireq.addr];
+        } 
+        else                                                                // MMU activated
+        { 
+            m_cpt_ins_tlb_read++;
+            icache_hit_t  = icache_tlb.cctranslate(ireq.addr, &tlb_ipaddr, &icache_pte_info, 
+                                                   &icache_tlb_nline, &icache_tlb_way, &icache_tlb_set); 
+            icache_hit_x  = (((vaddr_t)r_icache_vpn_save << PAGE_K_NBITS) == (ireq.addr & ~PAGE_K_MASK)) && r_itlb_translation_valid;
+            icache_hit_p  = (((ireq.addr >> PAGE_M_NBITS) == r_icache_id1_save) && r_icache_ptba_ok); 
+            spc_ipaddr    = ((paddr_t)r_icache_ppn_save << PAGE_K_NBITS) | (paddr_t)(ireq.addr & PAGE_K_MASK);
+            icache_cached = icache_pte_info.c; 
+        }
+
+        if ( !(r_mmu_mode.read() & INS_CACHE_MASK) )   // cache not actived
+        {
+            icache_cached = false;
+        }
+
+        if ( ireq.valid ) 
+        {
+            m_cpt_icache_dir_read += m_icache_ways;
+            m_cpt_icache_data_read += m_icache_ways;
+
+            // icache_hit_c & icache_ins
+            if ( icache_cached )    // using speculative physical address for cached access
+            {
+                icache_hit_c = r_icache.read(spc_ipaddr, &icache_ins);
+            }
+            else                    // using actual physical address for uncached access
+            {
+                icache_hit_c = ( r_icache_buf_unc_valid && (tlb_ipaddr == (paddr_t)r_icache_paddr_save) );
+                icache_ins = r_icache_miss_buf[0];
+            }
+
+            if ( r_mmu_mode.read() & INS_TLB_MASK ) 
+            {
+                if ( icache_hit_t ) 
+                {
+                    // check access rights
+                    if ( !icache_pte_info.u && (ireq.mode == iss_t::MODE_USER)) 
+                    {
+                        r_icache_error_type = MMU_READ_PRIVILEGE_VIOLATION;  
+                        r_icache_bad_vaddr = ireq.addr;
+                        irsp.valid = true;
+                        irsp.error = true;
+                        irsp.instruction = 0;
+                        break;
+                    }
+                    if ( !icache_pte_info.x ) 
+                    {
+                        r_icache_error_type = MMU_READ_EXEC_VIOLATION;  
+                        r_icache_bad_vaddr = ireq.addr;
+                        irsp.valid = true;
+                        irsp.error = true;
+                        irsp.instruction = 0;
+                        break;
+                    }
+                }
+
+                // update LRU, save ppn, vpn and page type
+                if ( icache_hit_t )
+                {  
+                    icache_tlb.setlru(icache_tlb_way,icache_tlb_set);     
+                    r_icache_ppn_save = tlb_ipaddr >> PAGE_K_NBITS;
+                    r_icache_vpn_save = ireq.addr >> PAGE_K_NBITS;
+                    r_icache_tlb_nline = icache_tlb_nline;
+                    r_itlb_translation_valid = true;
+                }
+                else
+                {
+                    r_itlb_translation_valid = false;
+                }
+
+            } // end if MMU activated
+
+            // compute next state 
+            if ( !icache_hit_t && !icache_hit_p )      // TLB miss
+            {
+                // walk page table  level 1
+                r_icache_paddr_save = (paddr_t)r_mmu_ptpr << (INDEX1_NBITS+2) | (paddr_t)((ireq.addr>>PAGE_M_NBITS)<<2);
+                r_itlb_read_dcache_req = true;
+		r_icache_vaddr_req = ireq.addr;
+                r_icache_fsm = ICACHE_TLB1_READ;
+                m_cpt_ins_tlb_miss++;
+                m_cost_ins_tlb_miss_frz++;
+            }
+            else if ( !icache_hit_t && icache_hit_p )  // TLB Miss with possibility of bypass first level page
+            {
+                // walk page table level 2
+                r_icache_paddr_save = (paddr_t)r_icache_ptba_save | 
+                                      (paddr_t)(((ireq.addr&PTD_ID2_MASK)>>PAGE_K_NBITS) << 3);
+                r_itlb_read_dcache_req = true;
+		r_icache_vaddr_req = ireq.addr;
+		r_itlb_k_read_dcache   = true;
+                r_icache_fsm = ICACHE_TLB2_READ;
+                m_cpt_ins_tlb_miss++;
+                m_cost_ins_tlb_miss_frz++;
+            }
+            else if ( icache_hit_t && !icache_hit_x && icache_cached ) // cached access with an ucorrect speculative physical address
+            {
+                r_icache_paddr_save = tlb_ipaddr;   // save actual physical address for BIS
+		r_icache_vaddr_req = ireq.addr;
+                r_icache_fsm = ICACHE_BIS;
+                //m_cost_ins_miss_frz++;
+            }
+            else    // cached or uncached access with a correct speculative physical address 
+            {        
+                m_cpt_ins_read++; 
+                if ( !icache_hit_c ) 
+                {
+                    if ( icache_cached ) 
+                    {
+                        r_icache_miss_req = true;
+                    	r_icache_paddr_save = spc_ipaddr; 
+			r_icache_vaddr_req = ireq.addr;
+                        r_icache_fsm = ICACHE_MISS_WAIT;
+                    	m_cpt_ins_miss++;
+                    	m_cost_ins_miss_frz++;
+                    } 
+                    else 
+                    {
+                        r_icache_unc_req = true;
+                        r_icache_buf_unc_valid = false;
+                    	r_icache_paddr_save = tlb_ipaddr; 
+			r_icache_vaddr_req = ireq.addr;
+                        r_icache_fsm = ICACHE_UNC_WAIT;
+                    } 
+                } 
+                else 
+                {
+                    r_icache_buf_unc_valid = false;
+                    r_icache_fsm = ICACHE_IDLE;
+                }
+                irsp.valid = icache_hit_c;
+                irsp.instruction = icache_ins;
+            } // end if next states
+            
+        } // end if ireq.valid
+        break;
+    }
+    ////////////////
+    case ICACHE_BIS: 
+    {
+        // external cache invalidate request
+        if ( r_tgt_icache_req )
+        {
+            r_icache_fsm = ICACHE_CC_INVAL;
+            r_icache_fsm_save = r_icache_fsm;
+            break;
+        }
+
+        // external tlb invalidate request
+        if ( r_dcache_itlb_inval_req )
+        {
+	    r_itlb_inval_req = true;
+            r_icache_fsm = ICACHE_TLB_CC_INVAL;
+            r_icache_fsm_save = r_icache_fsm;
+            break;
+        }
+      
+        // using page is invalidated 
+        if ( r_icache_inval_tlb_rsp )
+        {
+            r_icache_inval_tlb_rsp = false;
+            r_icache_fsm = ICACHE_IDLE;
+            break;
+        }
+ 
+        data_t	icache_ins = 0;
+        bool	icache_hit_c = false;
+        bool    icache_hit_t = false;
+        paddr_t	tlb_ipaddr = 0;
+
+	icache_hit_t = icache_tlb.translate(ireq.addr, &tlb_ipaddr);
+
+	if ( (tlb_ipaddr == r_icache_paddr_save.read()) && ireq.valid && icache_hit_t )		// unmodified & valid
+	{
+            m_cpt_ins_read++;
+
+            // acces is always cached in this state
+            icache_hit_c = r_icache.read(r_icache_paddr_save, &icache_ins);
+
+            if ( !icache_hit_c )
+            {
+                r_icache_miss_req = true;
+                r_icache_fsm = ICACHE_MISS_WAIT;
+                m_cpt_ins_miss++;
+                m_cost_ins_miss_frz++;
+            } 
+            else
+            {
+                r_icache_fsm = ICACHE_IDLE; 
+            }
+            irsp.valid = icache_hit_c;
+	    if (irsp.valid)
+	      assert((r_icache_vaddr_req.read() == ireq.addr) &&
+	          "vaddress should not be modified while ICACHE_BIS");
+            irsp.error = false;
+            irsp.instruction = icache_ins;
+	}
+	else	// modified or invalid
+	{
+            irsp.valid = false;
+            irsp.error = false;
+            irsp.instruction = 0;
+            r_icache_fsm = ICACHE_IDLE;
+	}
+        break;
+    }
+    //////////////////////
+    case ICACHE_TLB1_READ:
+    {
+        if ( ireq.valid ) m_cost_ins_tlb_miss_frz++;
+
+        // external cache invalidate request
+        if ( r_tgt_icache_req )
+        {
+            r_icache_fsm = ICACHE_CC_INVAL;
+            r_icache_fsm_save = r_icache_fsm;
+            break;
+        }
+
+        // external tlb invalidate request
+        if ( r_dcache_itlb_inval_req )
+        {
+	    r_itlb_inval_req = true;
+            r_icache_fsm = ICACHE_TLB_CC_INVAL;
+            r_icache_fsm_save = r_icache_fsm;
+            break;
+        }
+
+	if ( !r_itlb_read_dcache_req )
+	{
+	    if (r_icache_vaddr_req.read() != ireq.addr || !ireq.valid) 
+	    {
+		/* request modified, drop response and restart */
+		r_icache_ptba_ok = false;
+            	if ( r_icache_inval_tlb_rsp )	r_icache_inval_tlb_rsp = false;
+                if ( r_dcache_rsp_itlb_error )	r_dcache_rsp_itlb_error = false;
+		r_icache_fsm = ICACHE_IDLE;
+		break;
+	    }
+
+            if ( !r_icache_inval_tlb_rsp ) // TLB miss read response and no invalidation
+            {
+                if ( !r_dcache_rsp_itlb_error ) // vci response ok
+                {  
+		    if (r_itlb_acc_redo_req)
+		    {
+	                r_itlb_acc_redo_req = false;
+                        r_itlb_read_dcache_req = true;
+                    	//r_icache_fsm = ICACHE_IDLE;  
+		    }
+            	    else if ( !(r_dcache_rsp_itlb_miss >> PTE_V_SHIFT) ) // unmapped
+            	    {
+                	r_icache_ptba_ok    = false;	
+                        r_icache_error_type = MMU_READ_PT1_UNMAPPED;  
+                        r_icache_bad_vaddr  = r_icache_vaddr_req.read();
+                        r_icache_fsm        = ICACHE_ERROR;
+            	    }
+            	    else if ( (r_dcache_rsp_itlb_miss & PTE_T_MASK ) >> PTE_T_SHIFT ) // PTD
+            	    {
+                	r_icache_ptba_ok       = true;	
+                        r_icache_ptba_save     = (paddr_t)(r_dcache_rsp_itlb_miss & ((1<<(m_paddr_nbits - PAGE_K_NBITS))-1)) << PAGE_K_NBITS; 
+                        r_icache_id1_save      = r_icache_vaddr_req.read() >> PAGE_M_NBITS;
+                        r_icache_paddr_save    = (paddr_t)(r_dcache_rsp_itlb_miss & ((1<<(m_paddr_nbits - PAGE_K_NBITS))-1)) << PAGE_K_NBITS |
+                                                 (paddr_t)(((r_icache_vaddr_req.read() & PTD_ID2_MASK) >> PAGE_K_NBITS) << 3); 
+                        r_itlb_read_dcache_req = true;
+			r_itlb_k_read_dcache   = true;
+                        r_icache_fsm           = ICACHE_TLB2_READ;
+             	    }	
+            	    else
+            	    {
+                	r_icache_ptba_ok = false;
+            
+            	        if ( (m_srcid_rw >> 4) == ((r_dcache_rsp_itlb_miss & ((1<<(m_paddr_nbits - PAGE_M_NBITS))-1)) >> (m_paddr_nbits - PAGE_M_NBITS -10)) ) // local
+            	        {
+            		    if ( (r_dcache_rsp_itlb_miss & PTE_L_MASK ) >> PTE_L_SHIFT ) // L bit is set
+            		    {
+                                r_icache_pte_update = r_dcache_rsp_itlb_miss;
+                                r_icache_fsm        = ICACHE_TLB1_UPDT_SEL;
+            		    }
+            		    else
+            		    {
+                                r_icache_pte_update   = r_dcache_rsp_itlb_miss | PTE_L_MASK;
+                                r_itlb_acc_dcache_req = true;
+                                r_icache_fsm          = ICACHE_TLB1_WRITE;
+                                m_cpt_ins_tlb_update_acc++;
+                                m_cost_ins_tlb_update_acc_frz++;
+            		    }
+                        }
+            	        else // remotely
+            	        {
+            		    if ( (r_dcache_rsp_itlb_miss & PTE_R_MASK ) >> PTE_R_SHIFT ) // R bit is set
+            		    {
+                                r_icache_pte_update = r_dcache_rsp_itlb_miss;
+                                r_icache_fsm        = ICACHE_TLB1_UPDT_SEL;
+            		    }
+            		    else
+            		    {
+                                r_icache_pte_update   = r_dcache_rsp_itlb_miss | PTE_R_MASK;
+                                r_itlb_acc_dcache_req = true;
+                                r_icache_fsm          = ICACHE_TLB1_WRITE;
+                                m_cpt_ins_tlb_update_acc++;
+                                m_cost_ins_tlb_update_acc_frz++;
+            		    }
+            	        }
+            	    }
+                }
+                else                        // vci response error
+                {  
+                    r_icache_fsm = ICACHE_ERROR;
+                    r_icache_error_type = MMU_READ_PT1_ILLEGAL_ACCESS;    
+                    r_icache_bad_vaddr = r_icache_vaddr_req.read();
+                }
+            }
+	    else  // TLB miss read response and invalidation
+            {
+                if ( r_dcache_rsp_itlb_error ) 
+                {
+                    r_icache_inval_tlb_rsp = false;
+                    r_icache_error_type = MMU_READ_PT1_ILLEGAL_ACCESS;    
+                    r_icache_bad_vaddr = r_icache_vaddr_req.read();
+                    r_icache_fsm = ICACHE_ERROR;
+                } 
+                else 
+                {
+	            if ( r_itlb_acc_redo_req ) r_itlb_acc_redo_req = false;
+                    r_icache_inval_tlb_rsp = false;
+                    r_icache_fsm = ICACHE_IDLE;  
+                } 
+            }
+	}
+        break;
+    }
+    ///////////////////////
+    case ICACHE_TLB1_WRITE:  
+    {
+        if ( ireq.valid ) m_cost_ins_tlb_miss_frz++;
+        m_cost_ins_tlb_update_acc_frz++;
+
+        // external cache invalidate request
+        if ( r_tgt_icache_req )
+        {
+            r_icache_fsm = ICACHE_CC_INVAL;
+            r_icache_fsm_save = r_icache_fsm;
+            break;
+        }
+        // external tlb invalidate request
+        if ( r_dcache_itlb_inval_req )
+        {
+	    r_itlb_inval_req = true;
+            r_icache_fsm = ICACHE_TLB_CC_INVAL;
+            r_icache_fsm_save = r_icache_fsm;
+            break;
+        }
+
+        if ( !r_itlb_acc_dcache_req ) // TLB access bits write response 
+	{        
+            if ( !r_icache_inval_tlb_rsp ) // TLB access bits write response and no invalidation        
+            { 
+                if ( r_dcache_rsp_itlb_error ) 
+                {
+                    r_icache_error_type = MMU_READ_PT1_ILLEGAL_ACCESS;  
+                    r_icache_bad_vaddr = r_icache_vaddr_req.read();
+                    r_icache_fsm = ICACHE_ERROR;
+                } 
+	        else if ( r_itlb_acc_redo_req )
+		{
+		    r_itlb_acc_redo_req = false;
+                    r_icache_fsm = ICACHE_IDLE;    
+		}
+                else  
+                {
+                    r_icache_fsm = ICACHE_TLB1_UPDT_SEL;  
+                }
+            } 
+	    else   // TLB ET write response and invalidation     
+            {   
+                if ( r_dcache_rsp_itlb_error ) 
+                {
+                    r_icache_inval_tlb_rsp = false;
+                    r_icache_error_type = MMU_READ_PT1_ILLEGAL_ACCESS;  
+                    r_icache_bad_vaddr = r_icache_vaddr_req.read();
+                    r_icache_fsm = ICACHE_ERROR;
+                } 
+	        else if ( r_itlb_acc_redo_req )
+		{
+		    r_itlb_acc_redo_req = false;
+                    r_icache_inval_tlb_rsp = false;
+                    r_icache_fsm = ICACHE_IDLE;    
+		}
+                else  
+                {
+                    r_icache_inval_tlb_rsp = false;
+                    r_icache_fsm = ICACHE_IDLE;    
+                }
+            }
+	}
+        break;
+    }
+    //////////////////////
+    case ICACHE_TLB1_UPDT_SEL:
+    {
+        if ( ireq.valid ) m_cost_ins_tlb_miss_frz++;
+        m_cost_ins_tlb_update_acc_frz++;
+
+        // external cache invalidate request
+        if ( r_tgt_icache_req )
+        {
+            r_icache_fsm = ICACHE_CC_INVAL;
+            r_icache_fsm_save = r_icache_fsm;
+            break;
+        }
+
+        // external tlb invalidate request
+        if ( r_dcache_itlb_inval_req ) 
+        {
+	    r_itlb_inval_req = true;
+            r_icache_fsm = ICACHE_TLB_CC_INVAL;
+            r_icache_fsm_save = r_icache_fsm;
+            break;
+        }
+
+        // TLB update and invalidate same PTE
+        if ( r_icache_inval_tlb_rsp )                                 
+        {
+            r_icache_inval_tlb_rsp = false;
+            r_icache_fsm = ICACHE_IDLE;
+	    break;
+        }
+
+	if ( r_dcache_itlb_cleanup_req ) break; 
+
+	size_t way = 0;
+	size_t set = 0;
+	paddr_t victim_index = 0;
+
+	bool cleanup = icache_tlb.select((r_icache_vaddr_req.read()>> PAGE_M_NBITS),&victim_index,&way,&set);
+	r_icache_way = way;
+	r_icache_set = set;
+	if (cleanup)
+	{
+	    r_dcache_itlb_cleanup_req = true;
+	    r_dcache_itlb_cleanup_line = victim_index;
+	    //m_cpt_cc_cleanup_ins++;
+	}
+	r_icache_fsm = ICACHE_TLB1_UPDT;
+	break; 
+    }
+    /////////////////////
+    case ICACHE_TLB1_UPDT:
+    {
+        if ( ireq.valid ) m_cost_ins_tlb_miss_frz++;
+        m_cost_ins_tlb_update_acc_frz++;
+
+	icache_tlb.update(r_icache_pte_update,r_icache_vaddr_req.read(),r_icache_way.read(),r_icache_set.read(),(r_icache_paddr_save.read() >> (uint32_log2(m_dcache_words)+2)));
+	r_icache_fsm = ICACHE_IDLE;
+        break;
+    }
+    /////////////////////
+    case ICACHE_TLB2_READ:
+    {
+        if ( ireq.valid ) m_cost_ins_tlb_miss_frz++;
+
+        // external cache invalidate request
+        if ( r_tgt_icache_req )
+        {
+            r_icache_fsm = ICACHE_CC_INVAL;
+            r_icache_fsm_save = r_icache_fsm;
+            break;
+        }
+
+        // external tlb invalidate request
+        if ( r_dcache_itlb_inval_req )
+        {
+	    r_itlb_inval_req = true;
+            r_icache_fsm = ICACHE_TLB_CC_INVAL;
+            r_icache_fsm_save = r_icache_fsm;
+            break;
+        }
+
+        if ( !r_itlb_read_dcache_req  ) // TLB miss read response
+	{ 
+	    if (r_icache_vaddr_req.read() != ireq.addr || !ireq.valid) 
+	    {
+		/* request modified, drop response and restart */
+		r_icache_ptba_ok = false;
+            	if ( r_icache_inval_tlb_rsp )	r_icache_inval_tlb_rsp = false;
+                if ( r_dcache_rsp_itlb_error )	r_dcache_rsp_itlb_error = false;
+		r_icache_fsm = ICACHE_IDLE;
+		break;
+	    }
+
+            if ( !r_icache_inval_tlb_rsp ) // TLB miss read response 
+            {
+                if ( !r_dcache_rsp_itlb_error ) // VCI response ok        
+                {
+		    if (r_itlb_acc_redo_req)
+		    {
+	                r_itlb_acc_redo_req = false;
+                        r_itlb_read_dcache_req = true;
+		    }
+            	    else if ( !(r_dcache_rsp_itlb_miss >> PTE_V_SHIFT) ) // unmapped
+            	    {
+                        r_icache_error_type = MMU_READ_PT2_UNMAPPED;  
+                        r_icache_bad_vaddr  = r_icache_vaddr_req.read();
+                        r_icache_fsm = ICACHE_ERROR;
+            	    }
+            	    else
+            	    {
+            	        if ( (m_srcid_rw >> 4) == ((r_dcache_rsp_itlb_miss & ((1<<(m_paddr_nbits - PAGE_M_NBITS))-1)) >> (m_paddr_nbits - PAGE_M_NBITS -10)) ) // local
+            	        {
+            		    if ( (r_dcache_rsp_itlb_miss & PTE_L_MASK ) >> PTE_L_SHIFT ) // L bit is set
+            		    {
+                        	r_icache_fsm        = ICACHE_TLB2_UPDT_SEL;
+                        	r_icache_pte_update = r_dcache_rsp_itlb_miss;
+            		    }
+            		    else
+            		    {
+                        	r_icache_pte_update   = r_dcache_rsp_itlb_miss | PTE_L_MASK;
+                        	r_itlb_acc_dcache_req = true;
+                        	r_icache_fsm          = ICACHE_TLB2_WRITE;
+                                m_cpt_ins_tlb_update_acc++;
+                                m_cost_ins_tlb_update_acc_frz++;
+            		    }
+                        }
+            	    	else // remotely
+            	    	{
+            		    if ( (r_dcache_rsp_itlb_miss & PTE_R_MASK ) >> PTE_R_SHIFT ) // R bit is set
+            		    {
+                        	r_icache_fsm        = ICACHE_TLB2_UPDT_SEL;
+                        	r_icache_pte_update = r_dcache_rsp_itlb_miss;
+            		    }
+            		    else
+            		    {
+                        	r_icache_pte_update   = r_dcache_rsp_itlb_miss | PTE_R_MASK;
+                        	r_itlb_acc_dcache_req = true;
+                        	r_icache_fsm          = ICACHE_TLB2_WRITE;
+                                m_cpt_ins_tlb_update_acc++;
+                                m_cost_ins_tlb_update_acc_frz++;
+            		    }
+            	        }
+            	    }
+                }
+                else                            // VCI response error        
+                {
+                    r_icache_error_type = MMU_READ_PT2_ILLEGAL_ACCESS;
+                    r_icache_bad_vaddr = r_icache_vaddr_req.read();
+                    r_icache_fsm = ICACHE_ERROR;
+                }
+            }
+	    else  // TLB miss read response and invalidation
+            {
+                if ( r_dcache_rsp_itlb_error ) 
+                {
+                    r_icache_inval_tlb_rsp = false;
+                    r_icache_error_type = MMU_READ_PT2_ILLEGAL_ACCESS;    
+                    r_icache_bad_vaddr = r_icache_vaddr_req.read();
+                    r_icache_fsm = ICACHE_ERROR;
+                } 
+                else 
+                {
+	            if ( r_itlb_acc_redo_req ) r_itlb_acc_redo_req = false;
+                    r_icache_inval_tlb_rsp = false;
+                    r_icache_fsm = ICACHE_IDLE;  
+                } 
+            }
+	}
+        break;
+    }
+    /////////////////////////
+    case ICACHE_TLB2_WRITE:
+    {  
+        if ( ireq.valid ) m_cost_ins_tlb_miss_frz++;
+        m_cost_ins_tlb_update_acc_frz++;
+
+        // external cache invalidate request
+        if ( r_tgt_icache_req )
+        {
+            r_icache_fsm = ICACHE_CC_INVAL;
+            r_icache_fsm_save = r_icache_fsm;
+            break;
+        }
+        // external tlb invalidate request
+        if ( r_dcache_itlb_inval_req )
+        {
+	    r_itlb_inval_req = true;
+            r_icache_fsm = ICACHE_TLB_CC_INVAL;
+            r_icache_fsm_save = r_icache_fsm;
+            break;
+        }
+
+        if ( !r_itlb_acc_dcache_req ) // TLB access bits write response          
+	{
+            if ( !r_icache_inval_tlb_rsp ) // TLB access bits write response          
+            {
+                if ( r_dcache_rsp_itlb_error )             
+                {
+                    r_icache_error_type = MMU_READ_PT2_ILLEGAL_ACCESS;  
+                    r_icache_bad_vaddr = r_icache_vaddr_req.read();
+                    r_icache_fsm = ICACHE_ERROR;
+                } 
+	        else if ( r_itlb_acc_redo_req )
+		{
+		    r_itlb_acc_redo_req = false;
+                    r_icache_fsm = ICACHE_IDLE;    
+		}
+                else  
+                {
+                    r_icache_fsm = ICACHE_TLB2_UPDT_SEL;  
+                }
+            }
+	    else // TLB ET write response and invalidation     
+            {   
+                if ( r_dcache_rsp_itlb_error ) 
+                {
+                    r_icache_inval_tlb_rsp = false;
+                    r_icache_error_type = MMU_READ_PT2_ILLEGAL_ACCESS;  
+                    r_icache_bad_vaddr = r_icache_vaddr_req.read();
+                    r_icache_fsm = ICACHE_ERROR;
+                } 
+	        else if ( r_itlb_acc_redo_req )
+		{
+		    r_itlb_acc_redo_req = false;
+                    r_icache_inval_tlb_rsp = false;
+                    r_icache_fsm = ICACHE_IDLE;    
+		}
+                else  
+                {
+                    r_icache_inval_tlb_rsp = false;
+                    r_icache_fsm = ICACHE_IDLE;    
+                }
+            }
+	}
+        break;
+    }
+    //////////////////////////
+    case ICACHE_TLB2_UPDT_SEL: 
+    {
+        if ( ireq.valid ) m_cost_ins_tlb_miss_frz++;
+        m_cost_ins_tlb_update_acc_frz++;
+
+        // external cache invalidate request
+        if ( r_tgt_icache_req )
+        {
+            r_icache_fsm = ICACHE_CC_INVAL;
+            r_icache_fsm_save = r_icache_fsm;
+            break;
+        }
+
+        // external tlb invalidate request
+        if ( r_dcache_itlb_inval_req ) 
+        {
+	    r_itlb_inval_req = true;
+            r_icache_fsm = ICACHE_TLB_CC_INVAL;
+            r_icache_fsm_save = r_icache_fsm;
+            break;
+        }
+
+        // TLB update and invalidate same PTE
+        if ( r_icache_inval_tlb_rsp )                            
+        {
+            r_icache_inval_tlb_rsp = false;
+            r_icache_fsm = ICACHE_IDLE;
+	    break;
+        }
+
+	if ( r_dcache_itlb_cleanup_req ) break; 
+
+	size_t way = 0;
+	size_t set = 0;
+	paddr_t victim_index = 0;
+
+	bool cleanup = icache_tlb.select((r_icache_vaddr_req.read()>> PAGE_K_NBITS),&victim_index,&way,&set);
+	r_icache_way = way;
+	r_icache_set = set;
+	if (cleanup)
+	{
+	    r_dcache_itlb_cleanup_req = true;
+	    r_dcache_itlb_cleanup_line = victim_index;
+	    //m_cpt_cc_cleanup_ins++;
+	}
+	r_icache_fsm = ICACHE_TLB2_UPDT;
+        break;
+    }
+    /////////////////////
+    case ICACHE_TLB2_UPDT: 
+    {
+        if ( ireq.valid ) m_cost_ins_tlb_miss_frz++;
+        m_cost_ins_tlb_update_acc_frz++;
+
+        icache_tlb.update(r_icache_pte_update,r_dcache_rsp_itlb_ppn,r_icache_vaddr_req.read(),r_icache_way.read(),r_icache_set.read(),(r_icache_paddr_save.read() >> (uint32_log2(m_dcache_words)+2)));
+        r_icache_fsm = ICACHE_IDLE;
+	break;
+    }
+    /////////////////////////////
+    case ICACHE_SW_FLUSH:
+    {
+        size_t way = r_icache_way;
+        size_t set = r_icache_set;
+        bool clean = false;
+
+        // 4K page size TLB flush leads to cleanup req to data cache 
+        if ( !r_dcache_itlb_cleanup_req )    // last cleanup finish
+        {
+            paddr_t victim_index = 0;
+            for ( ; way < m_itlb_ways; way++)
+            {
+                for ( ; set < m_itlb_sets; set++)
+                {
+                    if(icache_tlb.checkcleanup(way, set, &victim_index))
+                    {
+                        clean = true;
+                        r_dcache_itlb_cleanup_req = true;
+                        r_dcache_itlb_cleanup_line = victim_index;
+                        r_icache_way = way + ((set+1)/m_itlb_sets);
+                        r_icache_set = (set+1) % m_itlb_sets;
+                        break;
+                    }
+                }
+                if (clean) break;
+		set = 0;
+            }
+
+            if (way == m_itlb_ways)
+            {
+                r_dcache_xtn_req = false;
+        	r_itlb_translation_valid = false;
+        	r_icache_ptba_ok = false;
+                r_icache_fsm = ICACHE_IDLE;
+                break;
+            }
+        }
+        break;
+    }
+    /////////////////////
+    case ICACHE_TLB_FLUSH:
+    {   
+        // data cache flush leads to ins tlb flush, flush all tlb entry 
+        icache_tlb.flush(true);    // global entries are invalidated
+        r_dcache_xtn_req = false;
+	r_itlb_translation_valid = false;
+        r_icache_ptba_ok = false;
+        r_icache_fsm = ICACHE_IDLE;
+        break;
+    }
+    ////////////////////////
+    case ICACHE_CACHE_FLUSH:
+    {
+        // external cache invalidate request
+        if ( r_tgt_icache_req )
+        {
+            r_icache_fsm = ICACHE_CC_INVAL;
+            r_icache_fsm_save = r_icache_fsm;
+            break;
+        }
+
+        size_t way = r_icache_way;
+        size_t set = r_icache_set;
+        bool clean = false;
+
+        // cache flush and send cleanup to external
+        if ( !r_icache_cleanup_req )
+        {
+            paddr_t victim_index = 0;
+            for ( ; way < m_icache_ways; way++ )
+            {    
+                for ( ; set < m_icache_sets; set++ )
+                {    
+                    if ( r_icache.flush(way, set, &victim_index) )
+                    {
+                        clean = true;
+                        r_icache_cleanup_req = true;
+                        r_icache_cleanup_line = victim_index;
+			m_cpt_cc_cleanup_ins++;
+                        r_icache_way = way + ((set+1)/m_icache_sets);
+                        r_icache_set = (set+1) % m_icache_sets;
+                        break;
+                    }
+                }
+                if (clean) break;
+		set = 0;
+            }
+            if (way == m_icache_ways)
+            {
+                r_dcache_xtn_req = false;
+                r_icache_fsm = ICACHE_IDLE;
+                break;
+            }
+        }
+        break;
+    }
+    /////////////////////
+    case ICACHE_TLB_INVAL:  
+    {
+        paddr_t victim_index = 0;
+
+        if ( !r_dcache_itlb_cleanup_req )
+        {
+            bool dcache_itlb_cleanup_req = icache_tlb.inval(r_dcache_wdata_save, &victim_index);
+            r_dcache_itlb_cleanup_req = dcache_itlb_cleanup_req;
+            r_dcache_itlb_cleanup_line = victim_index;
+	    //if (dcache_itlb_cleanup_req) m_cpt_cc_cleanup_ins++;
+            r_dcache_xtn_req = false;
+            r_itlb_translation_valid = false;
+            r_icache_ptba_ok = false;
+            r_icache_fsm = ICACHE_IDLE;
+        }
+        break;
+    }
+    ////////////////////////
+    case ICACHE_CACHE_INVAL:
+    {	
+        // external cache invalidate request
+        if ( r_tgt_icache_req )
+        {
+            r_icache_fsm = ICACHE_CC_INVAL;
+            r_icache_fsm_save = r_icache_fsm;
+            break;
+        }
+
+        paddr_t ipaddr = 0;                     
+        bool    icache_hit_t = false;
+
+        if ( !r_icache_cleanup_req )
+        {    
+            if ( r_mmu_mode.read() & INS_TLB_MASK ) 
+            {
+                icache_hit_t = icache_tlb.translate(r_dcache_wdata_save, &ipaddr); 
+            } 
+            else 
+            {
+                ipaddr = (paddr_t)r_dcache_wdata_save;
+                icache_hit_t = true;
+            }
+            if ( icache_hit_t )
+            {
+                // invalidate and cleanup if necessary
+                bool icache_cleanup_req = r_icache.inval(ipaddr);
+                r_icache_cleanup_req = icache_cleanup_req;
+                r_icache_cleanup_line = ipaddr >> (uint32_log2(m_icache_words) + 2);  
+	        if (icache_cleanup_req) m_cpt_cc_cleanup_ins++;	
+            }
+            r_dcache_xtn_req = false; 
+            r_icache_fsm = ICACHE_IDLE;
+        }
+        break;
+    }
+    ////////////////////////
+    case ICACHE_CACHE_INVAL_PA:
+    {
+        // external cache invalidate request
+        if ( r_tgt_icache_req )
+        {
+            r_icache_fsm = ICACHE_CC_INVAL;
+            r_icache_fsm_save = r_icache_fsm;
+            break;
+        }
+	
+        paddr_t ipaddr = (paddr_t)r_mmu_word_hi.read() << 32 | r_mmu_word_lo.read();
+
+        if ( !r_icache_cleanup_req )
+        {    
+            // invalidate and cleanup if necessary
+            bool icache_cleanup_req = r_icache.inval(ipaddr);
+            r_icache_cleanup_req = icache_cleanup_req;
+            r_icache_cleanup_line = ipaddr >> (uint32_log2(m_icache_words) + 2);  
+	    if (icache_cleanup_req) m_cpt_cc_cleanup_ins++; 
+            r_dcache_xtn_req = false; 
+            r_icache_fsm = ICACHE_IDLE;
+        }
+        break;
+    }
+    ///////////////////////
+    case ICACHE_MISS_WAIT:
+    {
+        m_cost_ins_miss_frz++;
+
+        // external cache invalidate request
+        if ( r_tgt_icache_req )     
+        {
+            r_icache_fsm = ICACHE_CC_INVAL;
+            r_icache_fsm_save = r_icache_fsm;
+            break;
+        }
+
+        // external tlb invalidate request
+        if ( r_dcache_itlb_inval_req )
+        {
+	    r_itlb_inval_req = true;
+            r_icache_fsm = ICACHE_TLB_CC_INVAL;
+            r_icache_fsm_save = r_icache_fsm;
+            break;
+        }
+       
+	if ( !r_icache_miss_req )
+	{
+	    if ( r_vci_rsp_ins_error ) 
+            {
+                r_icache_error_type = MMU_READ_DATA_ILLEGAL_ACCESS; 
+                r_icache_bad_vaddr = ireq.addr;
+                r_icache_fsm = ICACHE_ERROR;
+
+            	if ( r_icache_inval_tlb_rsp ) r_icache_inval_tlb_rsp = false;
+            	if ( r_icache_inval_rsp ) r_icache_inval_rsp = false;
+		break;
+            }
+
+            if ( r_icache_inval_tlb_rsp ) // Miss read response and tlb invalidation
+            {
+		if ( r_icache_cleanup_req ) break;
+                r_icache_cleanup_req = true;
+                r_icache_cleanup_line = r_icache_paddr_save.read() >> (uint32_log2(m_icache_words) + 2); 
+	        m_cpt_cc_cleanup_ins++;	
+                r_icache_fsm = ICACHE_IDLE;
+                r_icache_inval_tlb_rsp = false;
+                if ( r_icache_inval_rsp ) r_icache_inval_rsp = false;
+                break;
+            }
+	
+            if ( r_icache_inval_rsp ) // Miss read response and tlb invalidation
+            {
+		if ( r_icache_cleanup_req ) break;
+                r_icache_cleanup_req = true;
+                r_icache_cleanup_line = r_icache_paddr_save.read() >> (uint32_log2(m_icache_words) + 2);  
+		m_cpt_cc_cleanup_ins++;
+                r_icache_fsm = ICACHE_IDLE;
+                r_icache_inval_rsp = false;
+                break;
+            }
+            r_icache_fsm = ICACHE_MISS_UPDT;  
+	}	
+        break;
+    }
+    ////////////////////
+    case ICACHE_UNC_WAIT:
+    {
+        // external cache invalidate request
+        if ( r_tgt_icache_req ) 
+        {
+            r_icache_fsm = ICACHE_CC_INVAL;
+            r_icache_fsm_save = r_icache_fsm;
+            break;
+        }
+
+        // external tlb invalidate request
+        if ( r_dcache_itlb_inval_req )
+        {
+	    r_itlb_inval_req = true;
+            r_icache_fsm = ICACHE_TLB_CC_INVAL;
+            r_icache_fsm_save = r_icache_fsm;
+            break;
+        }
+
+	if ( !r_icache_unc_req )
+	{
+	    if ( r_vci_rsp_ins_error ) 
+            {
+                r_icache_error_type = MMU_READ_DATA_ILLEGAL_ACCESS;    
+                r_icache_bad_vaddr = ireq.addr;
+                r_icache_fsm = ICACHE_ERROR;
+
+            	if ( r_icache_inval_tlb_rsp ) r_icache_inval_tlb_rsp = false;
+		break;
+            }
+
+	    if ( r_icache_inval_tlb_rsp ) // Miss read response and tlb invalidation
+            {
+                r_icache_inval_tlb_rsp = false;
+                r_icache_fsm = ICACHE_IDLE;
+		break;
+            }
+
+	    // Miss read response and no invalidation
+            r_icache_buf_unc_valid = true;
+            r_icache_fsm = ICACHE_IDLE;
+	}	
+        break;
+    }
+    //////////////////////
+    case ICACHE_MISS_UPDT:
+    {
+        m_cost_ins_miss_frz++;
+
+        // external cache invalidate request
+        if ( r_tgt_icache_req )   
+        {
+            r_icache_fsm = ICACHE_CC_INVAL;
+            r_icache_fsm_save = r_icache_fsm;
+            break;
+        }
+
+        // external tlb invalidate request
+        if ( r_dcache_itlb_inval_req )
+        {
+	    r_itlb_inval_req = true;
+            r_icache_fsm = ICACHE_TLB_CC_INVAL;
+            r_icache_fsm_save = r_icache_fsm;
+            break;
+        }
+
+        if ( r_icache_inval_tlb_rsp ) // tlb invalidation
+        {
+            if ( r_icache_cleanup_req ) break;
+            r_icache_cleanup_req = true;
+            r_icache_cleanup_line = r_icache_paddr_save.read() >> (uint32_log2(m_icache_words) + 2); 
+	    m_cpt_cc_cleanup_ins++; 
+            r_icache_inval_tlb_rsp = false;
+            if ( r_icache_inval_rsp ) r_icache_inval_rsp = false;
+            r_icache_fsm = ICACHE_IDLE;
+            break;
+        }
+
+        if ( !r_icache_cleanup_req ) // Miss update and no invalidation
+        {
+            if ( r_icache_inval_rsp ) // invalidation
+            {
+                r_icache_cleanup_req = true;
+                r_icache_cleanup_line = r_icache_paddr_save.read() >> (uint32_log2(m_icache_words) + 2); 
+	        m_cpt_cc_cleanup_ins++;	
+                r_icache_fsm = ICACHE_IDLE;
+                r_icache_inval_rsp = false;
+            } 
+	    else
+	    {
+                data_t* buf = r_icache_miss_buf;
+                paddr_t  victim_index = 0;
+                m_cpt_icache_dir_write++;
+                m_cpt_icache_data_write++;
+
+                bool icache_cleanup_req = r_icache.update(r_icache_paddr_save.read(), buf, &victim_index);
+                r_icache_cleanup_req = icache_cleanup_req;
+                r_icache_cleanup_line = victim_index;                        
+		if (icache_cleanup_req) m_cpt_cc_cleanup_ins++;
+                r_icache_fsm = ICACHE_IDLE;
+	    }
+        }
+        break;
+    }
+    ///////////////////
+    case ICACHE_ERROR:
+    {
+        r_vci_rsp_ins_error = false;
+        r_dcache_rsp_itlb_error = false;
+        irsp.valid = true;
+        irsp.error = true;
+        irsp.instruction = 0; 
+        r_icache_fsm = ICACHE_IDLE;
+        break;
+    }
+    /////////////////////
+    case ICACHE_CC_INVAL:  
+    {                       
+        m_cpt_icache_dir_read += m_icache_ways;
+        /* activity counter */
+        if ( (( r_icache_fsm_save == ICACHE_BIS ) ||( r_icache_fsm_save == ICACHE_MISS_WAIT ) || ( r_icache_fsm_save == ICACHE_MISS_UPDT ) ) && ( ireq.valid ) )        
+        {
+            m_cost_ins_miss_frz++;
+        }
+        if( (( r_icache_fsm_save == ICACHE_TLB1_READ )     || ( r_icache_fsm_save == ICACHE_TLB2_READ )      ||
+             ( r_icache_fsm_save == ICACHE_TLB1_WRITE )    || ( r_icache_fsm_save == ICACHE_TLB2_WRITE )     ||
+             ( r_icache_fsm_save == ICACHE_TLB1_UPDT_SEL ) || ( r_icache_fsm_save == ICACHE_TLB2_UPDT_SEL )) && (ireq.valid) )
+        {
+            m_cost_ins_tlb_miss_frz++;
+        }
+
+        // invalidate cache
+        if( (( r_icache_fsm_save == ICACHE_MISS_WAIT ) || ( r_icache_fsm_save == ICACHE_MISS_UPDT ) /*|| 
+             ( r_icache_fsm_save == ICACHE_UNC_WAIT )*/ ) && 
+            ((r_icache_paddr_save.read() & ~((m_icache_words<<2)-1)) == (r_tgt_addr.read() & ~((m_icache_words<<2)-1))) ) 
+        {
+            r_icache_inval_rsp = true;
+	    r_tgt_icache_rsp = false;
+        } 
+        else 
+        {
+            r_tgt_icache_rsp = r_icache.inval(r_tgt_addr.read());
+        }
+        r_tgt_icache_req = false;
+        r_icache_fsm = r_icache_fsm_save;
+        break;
+    }
+    /////////////////////////
+    case ICACHE_TLB_CC_INVAL:
+    {
+        /* activity counter */
+        if ( (( r_icache_fsm_save == ICACHE_BIS ) ||( r_icache_fsm_save == ICACHE_MISS_WAIT ) || ( r_icache_fsm_save == ICACHE_MISS_UPDT ) ) && ( ireq.valid ) )        
+        {
+            m_cost_ins_miss_frz++;
+        }
+        if( (( r_icache_fsm_save == ICACHE_TLB1_READ )     || ( r_icache_fsm_save == ICACHE_TLB2_READ )      ||
+             ( r_icache_fsm_save == ICACHE_TLB1_WRITE )    || ( r_icache_fsm_save == ICACHE_TLB2_WRITE )     ||
+             ( r_icache_fsm_save == ICACHE_TLB1_UPDT_SEL ) || ( r_icache_fsm_save == ICACHE_TLB2_UPDT_SEL )) && (ireq.valid) )
+        {
+            m_cost_ins_tlb_miss_frz++;
+        }
+
+	if ( r_itlb_inval_req ) break;
+        // invalidate cache
+        if( (( r_icache_fsm_save == ICACHE_TLB1_READ )     || ( r_icache_fsm_save == ICACHE_TLB2_READ )  ||
+             ( r_icache_fsm_save == ICACHE_TLB1_WRITE )    || ( r_icache_fsm_save == ICACHE_TLB2_WRITE ) ||
+             ( r_icache_fsm_save == ICACHE_TLB1_UPDT_SEL ) || ( r_icache_fsm_save == ICACHE_TLB2_UPDT_SEL )) && 
+            (((r_icache_paddr_save.read() & ~((m_icache_words<<2)-1)) >> (uint32_log2(m_icache_words) + 2) ) == r_dcache_itlb_inval_line.read()) ) 
+        {
+            r_icache_inval_tlb_rsp = true;
+        } 
+        else if (((r_icache_fsm_save == ICACHE_BIS)||(r_icache_fsm_save == ICACHE_MISS_WAIT) ||
+               /* (r_icache_fsm_save == ICACHE_UNC_WAIT)||*/(r_icache_fsm_save == ICACHE_MISS_UPDT)) && 
+                (r_icache_tlb_nline.read() == r_dcache_itlb_inval_line.read()))
+        {
+            r_icache_inval_tlb_rsp = true;
+        }
+	r_dcache_itlb_inval_req = false;
+	r_itlb_translation_valid = false;
+        r_icache_ptba_ok = false;
+        r_icache_fsm = r_icache_fsm_save;
+        break;
+    }
+    } // end switch r_icache_fsm
+
+#ifdef SOCLIB_MODULE_DEBUG
+    std::cout << name() << " Instruction Response: " << irsp << std::endl;
+#endif
+
+    ////////////////////////////////////////////////////////////////////////////////////
+    //      INVAL ITLB CHECK FSM 
+    ////////////////////////////////////////////////////////////////////////////////////////
+    switch(r_inval_itlb_fsm) {
+    /////////////////////
+    case INVAL_ITLB_IDLE:
+    {
+        if ( r_itlb_inval_req )
+        {
+            r_ccinval_itlb_way = 0; 
+            r_ccinval_itlb_set = 0;
+            r_inval_itlb_fsm = INVAL_ITLB_CHECK;   
+            m_cost_ins_tlb_inval_frz++; 
+        }   
+        break;
+    }
+    ////////////////////////////
+    case INVAL_ITLB_CHECK:
+    {
+        m_cost_ins_tlb_inval_frz++; 
+
+        size_t way = r_ccinval_itlb_way; 
+        size_t set = r_ccinval_itlb_set;
+        bool end = false;        
+        bool tlb_hit = icache_tlb.cccheck(r_dcache_itlb_inval_line.read(), way, set, &way, &set, &end); 
+    
+        if ( tlb_hit )
+        {
+            r_ccinval_itlb_way = way; 
+            r_ccinval_itlb_set = set;
+            r_itlb_cc_check_end = end;
+            r_inval_itlb_fsm = INVAL_ITLB_INVAL; 
+            m_cpt_ins_tlb_inval++;   
+        }        
+        else
+        {
+            r_inval_itlb_fsm = INVAL_ITLB_CLEAR;    
+        }
+        break;
+    }
+    /////////////////////////
+    case INVAL_ITLB_INVAL:
+    {
+        m_cost_ins_tlb_inval_frz++;
+ 
+        icache_tlb.ccinval(r_ccinval_itlb_way, r_ccinval_itlb_set);
+
+        if ( !r_itlb_cc_check_end )
+        {
+            r_inval_itlb_fsm = INVAL_ITLB_CHECK; 
+        }
+        else
+        {
+            r_inval_itlb_fsm = INVAL_ITLB_CLEAR;    
+        }
+        break;
+    }
+    ////////////////////
+    case INVAL_ITLB_CLEAR:
+    {
+        r_itlb_inval_req = false;
+        r_itlb_cc_check_end = false;
+        r_ccinval_itlb_way = 0; 
+        r_ccinval_itlb_set = 0; 
+        r_inval_itlb_fsm = INVAL_ITLB_IDLE;    
+        m_cost_ins_tlb_inval_frz++; 
+        break;
+    }
+    } // end switch r_inval_itlb_fsm
+
+    ////////////////////////////////////////////////////////////////////////////////////
+    //      DCACHE FSM 
+    //
+    // Both the Cacheability Table, and the MMU cached bit are used to define
+    // the cacheability.
+    // 
+    // There is 14 mutually exclusive conditions to exit the IDLE state.
+    // Seven configurations corresponding to an XTN request from processor:
+    // - Context switch => CTXT_SWITCH state
+    // - Flush dcache => DCACHE_FLUSH state 
+    // - Flush icache => ICACHE_FLUSH state 
+    // - Invalidate a dtlb entry => DTLB_INVAL state
+    // - Invalidate a itlb entry => ITLB_INVAL state
+    // - Invalidate a dcache line => DCACHE_INVAL state
+    // - Invalidate a icache line => ICACHE_INVAL state
+    // Seven configurations corresponding to various read miss or write requests: 
+    // - TLB miss(in case hit_p miss) => TLB1_READ state
+    // - TLB miss(in case hit_p hit) => TLB2_READ state
+    // - Hit in TLB but VPN changed => BIS state
+    // - Cached read miss => MISS_REQ state
+    // - Uncache read miss => UNC_REQ state
+    // - Write hit => WRITE_UPDT state
+    // - Write miss => WRITE_REQ
+    //
+    // The r_vci_rsp_data_error flip-flop is set by the VCI_RSP controller and reset 
+    // by DCACHE-FSM when its state is in DCACHE_ERROR. 
+    //--------------------------------------------------------------------- 
+    // Data TLB: 
+    //  
+    // - int        ET          (00: unmapped; 01: unused or PTD)
+    //                          (10: PTE new;  11: PTE old      )
+    // - bool       cachable    (cached bit)
+    // - bool       writable    (writable bit) 
+    // - bool       executable  (** not used alwayse false)
+    // - bool       user        (access in user mode allowed)
+    // - bool       global      (PTE not invalidated by a TLB flush)
+    // - bool       dirty       (page has been modified) 
+    // - uint32_t   vpn         (virtual page number)
+    // - uint32_t   ppn         (physical page number)
+    ////////////////////////////////////////////////////////////////////////////////////////
+
+    switch (r_dcache_fsm) {
+    //////////////////////
+    case DCACHE_WRITE_REQ:
+    {
+        // external cache invalidate request
+        if ( r_tgt_dcache_req ) 
+        {
+            r_dcache_fsm = DCACHE_CC_CHECK;
+            r_dcache_fsm_save = r_dcache_fsm;
+            break;
+        }
+
+        // try to post the write request in the write buffer
+        if ( !r_dcache_write_req )     // no previous write transaction     
+        {
+            if ( r_wbuf.wok(r_dcache_paddr_save) )   // write request in the same cache line 
+            {    
+                r_wbuf.write(r_dcache_paddr_save.read(), r_dcache_be_save.read(), r_dcache_wdata_save);
+                // closing the write packet if uncached
+                if ( !r_dcache_cached_save )
+                { 
+                    r_dcache_write_req = true;
+                }
+            } 
+            else 
+            {    // close the write packet if write request not in the same cache line
+                r_dcache_write_req = true;
+                m_cost_write_frz++;
+                break;  //  posting not possible : stay in DCACHE_WRITEREQ state
+            }
+        } 
+        else     //  previous write transaction not completed
+        {
+            m_cost_write_frz++;
+            break;  //  posting not possible : stay in DCACHE_WRITEREQ state
+        }
+
+        // close the write packet if the next processor request is not a write 
+        if ( !dreq.valid || (dreq.type != iss_t::DATA_WRITE)) 
+        {
+            r_dcache_write_req = true;
+        }
+        
+        // The next state and the processor request parameters are computed 
+        // as in the DCACHE_IDLE state (see below ...)
+    }
+    /////////////////
+    case DCACHE_IDLE:
+    {
+        // external cache invalidate request
+        if ( r_tgt_dcache_req )   
+        {
+            r_dcache_fsm = DCACHE_CC_CHECK;
+            r_dcache_fsm_save = DCACHE_IDLE;
+            break;
+        }        
+
+        // ins tlb cleanup
+        if ( r_dcache_itlb_cleanup_req )
+        {
+            r_dcache_fsm = DCACHE_ITLB_CLEANUP;
+            break;
+        }    
+        // ins tlb miss
+    	if ( r_itlb_read_dcache_req )
+    	{
+            if ( dreq.valid ) m_cost_ins_tlb_occup_cache_frz++;		
+            data_t rsp_itlb_miss;
+	    data_t rsp_itlb_ppn;
+
+    	    bool itlb_hit_dcache = r_dcache.read(r_icache_paddr_save, &rsp_itlb_miss);
+	    if ( r_itlb_k_read_dcache && itlb_hit_dcache )
+	    {	
+		r_itlb_k_read_dcache = false;
+	        bool itlb_hit_ppn = r_dcache.read(r_icache_paddr_save.read()+4, &rsp_itlb_ppn);
+		assert(itlb_hit_ppn && "Address of pte[64-32] and pte[31-0] should be successive");
+	    }
+
+            m_cpt_dcache_data_read += m_dcache_ways;
+            m_cpt_dcache_dir_read += m_dcache_ways;
+
+    	    if ( itlb_hit_dcache )  // ins TLB request hits in data cache 
+    	    {
+                if (!((rsp_itlb_miss & PTE_T_MASK ) >> PTE_T_SHIFT)) m_cpt_ins_tlb_hit_dcache++;		    
+                r_dcache_rsp_itlb_miss = rsp_itlb_miss; 
+                r_dcache_rsp_itlb_ppn = rsp_itlb_ppn; 
+    	    	r_itlb_read_dcache_req = false;
+                r_dcache_fsm = DCACHE_IDLE;
+                
+                // set TLB bit if it's a PTE
+                if ( !((rsp_itlb_miss & PTE_T_MASK ) >> PTE_T_SHIFT) )
+                {
+                    bool set_hit = r_dcache.setinbit(r_icache_paddr_save, r_dcache_in_itlb, true);
+            	    assert(set_hit && "D$ IDLE ITLB set hit error");  
+                }
+    	    }
+    	    else                    // ins TLB request miss in data cache
+    	    {
+                r_dcache_itlb_read_req = true;
+                r_dcache_fsm = DCACHE_ITLB_READ;
+            }
+    	}
+    	else if ( r_itlb_acc_dcache_req ) // ins tlb write access bit
+    	{
+	    if ( dreq.valid ) m_cost_ins_tlb_occup_cache_frz++;
+
+	    data_t rsp_itlb_miss;
+    	    bool itlb_hit_dcache = r_dcache.read(r_icache_paddr_save, &rsp_itlb_miss);
+	    if ( itlb_hit_dcache )
+	    {
+                r_dcache_itlb_ll_acc_req = true;
+	        r_dcache_fsm = DCACHE_ITLB_LL_WAIT;	    	
+                m_cpt_dcache_data_write++;	    
+	    }
+	    else
+	    {
+		r_itlb_acc_dcache_req = false;
+		r_itlb_acc_redo_req = true;
+		r_dcache_fsm = DCACHE_IDLE;
+	    }    
+    	}
+        else if (dreq.valid) 
+        {
+            pte_info_t  dcache_pte_info;
+            int         xtn_opcod        = (int)dreq.addr/4;
+            paddr_t     tlb_dpaddr       = 0;        // physical address obtained from TLB
+            paddr_t     spc_dpaddr       = 0;        // physical adress obtained from PPN_save (speculative)
+            bool        dcache_hit_t     = false;    // hit on 4Kilo TLB
+            bool        dcache_hit_x     = false;    // VPN unmodified (can use spc_dpaddr)
+            bool        dcache_hit_p     = false;    // PTP unmodified (can skip first level page table walk)
+            bool        dcache_hit_c     = false;    // Cache hit
+            bool        dcache_cached    = false;    // cacheable access (read or write)
+            size_t      dcache_tlb_way   = 0;        // selected way (in case of cache hit)
+            size_t      dcache_tlb_set   = 0;        // selected set (Y field in address)
+            data_t      dcache_rdata     = 0;        // read data
+            paddr_t     dcache_tlb_nline = 0;       // TLB NLINE 
+
+            m_cpt_dcache_data_read += m_dcache_ways;
+            m_cpt_dcache_dir_read += m_dcache_ways;
+
+            // Decoding READ XTN requests from processor
+            // They are executed in this DCACHE_IDLE state
+
+            if (dreq.type == iss_t::XTN_READ) 
+            {
+                switch(xtn_opcod) {
+                case iss_t::XTN_INS_ERROR_TYPE:
+                    drsp.rdata = (uint32_t)r_icache_error_type;
+                    r_icache_error_type = MMU_NONE;
+                    drsp.valid = true;
+                    drsp.error = false;
+                    break;
+                case iss_t::XTN_DATA_ERROR_TYPE:
+                    drsp.rdata = (uint32_t)r_dcache_error_type;
+                    r_dcache_error_type = MMU_NONE;
+                    drsp.valid = true;
+                    drsp.error = false;
+                    break;
+                case iss_t::XTN_INS_BAD_VADDR:
+                    drsp.rdata = (uint32_t)r_icache_bad_vaddr;       
+                    drsp.valid = true;
+                    drsp.error = false;
+                    break;
+                case iss_t::XTN_DATA_BAD_VADDR:
+                    drsp.rdata = (uint32_t)r_dcache_bad_vaddr;        
+                    drsp.valid = true;
+                    drsp.error = false;
+                    break;
+                case iss_t::XTN_PTPR:
+                    drsp.rdata = (uint32_t)r_mmu_ptpr;
+                    drsp.valid = true;
+                    drsp.error = false;
+                    break;
+                case iss_t::XTN_TLB_MODE:
+                    drsp.rdata = (uint32_t)r_mmu_mode;
+                    drsp.valid = true;
+                    drsp.error = false;
+                    break;
+                case iss_t::XTN_MMU_PARAMS:
+                    drsp.rdata = (uint32_t)r_mmu_params;
+                    drsp.valid = true;
+                    drsp.error = false;
+                    break;
+                case iss_t::XTN_MMU_RELEASE:
+                    drsp.rdata = (uint32_t)r_mmu_release;
+                    drsp.valid = true;
+                    drsp.error = false;
+                    break;
+                case iss_t::XTN_MMU_WORD_LO:
+                    drsp.rdata = (uint32_t)r_mmu_word_lo;
+                    drsp.valid = true;
+                    drsp.error = false;
+                    break;
+                case iss_t::XTN_MMU_WORD_HI:
+                    drsp.rdata = (uint32_t)r_mmu_word_hi;
+                    drsp.valid = true;
+                    drsp.error = false;
+                    break;
+                default:
+                    r_dcache_error_type = MMU_READ_UNDEFINED_XTN; 
+                    r_dcache_bad_vaddr  = dreq.addr;
+                    drsp.valid = true;
+                    drsp.error = true;
+                    break;
+                }
+                r_dcache_fsm = DCACHE_IDLE;
+                break;
+            }
+
+            // Decoding WRITE XTN requests from processor
+            // If there is no privilege violation, they are not executed in this DCACHE_IDLE state,
+            // but in the next state, because they generally require access to the caches or the TLBs 
+
+            if (dreq.type == iss_t::XTN_WRITE) 
+            {
+                drsp.valid = false;
+                drsp.error = false;
+                drsp.rdata = 0;
+                r_dcache_wdata_save = dreq.wdata;   
+                switch(xtn_opcod) {     
+
+                case iss_t::XTN_PTPR:       // context switch : checking the kernel mode
+                                            // both instruction & data TLBs must be flushed
+                    if ((dreq.mode == iss_t::MODE_HYPER) || (dreq.mode == iss_t::MODE_KERNEL)) 
+                    {
+                        r_mmu_ptpr = dreq.wdata;
+                        r_icache_error_type = MMU_NONE;
+                        r_dcache_error_type = MMU_NONE;
+                        r_dcache_type_save = dreq.addr/4; 
+                        r_dcache_xtn_req = true;
+                        r_dcache_fsm = DCACHE_CTXT_SWITCH;
+                    } 
+                    else 
+                    { 
+                        r_dcache_error_type = MMU_WRITE_PRIVILEGE_VIOLATION; 
+                        r_dcache_bad_vaddr  = dreq.addr;
+                        drsp.valid = true;
+                        drsp.error = true;
+                	r_dcache_fsm = DCACHE_IDLE;
+                    }
+                    break;
+
+                case iss_t::XTN_TLB_MODE:     // modifying TLBs mode : checking the kernel mode
+                    if ((dreq.mode == iss_t::MODE_HYPER) || (dreq.mode == iss_t::MODE_KERNEL)) 
+                    {
+                        r_mmu_mode = (int)dreq.wdata;
+                        drsp.valid = true;
+                    } 
+                    else 
+                    {
+                        r_dcache_error_type = MMU_WRITE_PRIVILEGE_VIOLATION; 
+                        r_dcache_bad_vaddr  = dreq.addr;
+                        drsp.valid = true;
+                        drsp.error = true;
+                    }
+                    r_dcache_fsm = DCACHE_IDLE;
+                    break;
+
+                case iss_t::XTN_DTLB_INVAL:     //  checking the kernel mode
+                    if ((dreq.mode == iss_t::MODE_HYPER) || (dreq.mode == iss_t::MODE_KERNEL)) 
+                    {
+                        r_dcache_fsm = DCACHE_DTLB_INVAL;  
+                    } 
+                    else 
+                    {
+                        r_dcache_error_type = MMU_WRITE_PRIVILEGE_VIOLATION; 
+                        r_dcache_bad_vaddr  = dreq.addr;
+                        drsp.valid = true;
+                        drsp.error = true;
+                	r_dcache_fsm = DCACHE_IDLE;
+                    }
+                    break;
+
+                case iss_t::XTN_ITLB_INVAL:     //  checking the kernel mode
+                    if ((dreq.mode == iss_t::MODE_HYPER) || (dreq.mode == iss_t::MODE_KERNEL)) 
+                    {
+                        r_dcache_xtn_req = true;
+                        r_dcache_type_save = dreq.addr/4;
+                        r_dcache_fsm = DCACHE_ITLB_INVAL;  
+                    } 
+                    else 
+                    {
+                        r_dcache_error_type = MMU_WRITE_PRIVILEGE_VIOLATION; 
+                        r_dcache_bad_vaddr  = dreq.addr;
+                        drsp.valid = true;
+                        drsp.error = true;
+                	r_dcache_fsm = DCACHE_IDLE;
+                    }
+                    break;
+
+                case iss_t::XTN_DCACHE_INVAL:   // cache inval can be executed in user mode.
+                    r_dcache_fsm = DCACHE_DCACHE_INVAL;
+                    break;
+
+                case iss_t::XTN_MMU_DCACHE_PA_INV:   // cache inval can be executed in user mode.
+                    r_dcache_fsm = DCACHE_DCACHE_INVAL_PA;
+                    break;
+
+                case iss_t::XTN_DCACHE_FLUSH:   // cache flush can be executed in user mode.
+                    r_dcache_type_save = dreq.addr/4; 
+                    r_dcache_xtn_req = true;
+                    r_dcache_way = 0;
+                    r_dcache_set = 0;
+                    r_dcache_fsm = DCACHE_DCACHE_FLUSH; 
+                    break;
+
+                case iss_t::XTN_ICACHE_INVAL:   // cache inval can be executed in user mode.
+                    r_dcache_type_save = dreq.addr/4; 
+                    r_dcache_xtn_req = true;
+                    r_dcache_fsm = DCACHE_ICACHE_INVAL; 
+                    break;
+
+                case iss_t::XTN_MMU_ICACHE_PA_INV:   // cache inval can be executed in user mode.
+                    r_dcache_type_save = dreq.addr/4; 
+                    r_dcache_xtn_req = true;
+                    r_dcache_fsm = DCACHE_ICACHE_INVAL_PA; 
+                    break;
+
+                case iss_t::XTN_ICACHE_FLUSH:   // cache flush can be executed in user mode.
+                    r_dcache_type_save = dreq.addr/4; 
+                    r_dcache_xtn_req = true; 
+                    r_dcache_fsm = DCACHE_ICACHE_FLUSH;
+                    break;
+
+                case iss_t::XTN_SYNC:           // cache synchronization can be executed in user mode.
+                    if (r_wbuf.rok())
+                    {
+                        r_dcache_fsm = DCACHE_DCACHE_SYNC; 
+                    }
+                    else
+                    {
+                        drsp.valid = true;
+                        r_dcache_fsm = DCACHE_IDLE;
+                    }
+		    break;
+
+                case iss_t::XTN_MMU_WORD_LO: // modifying MMU misc registers
+                    if ((dreq.mode == iss_t::MODE_HYPER) || (dreq.mode == iss_t::MODE_KERNEL)) 
+                    {
+                        r_mmu_word_lo = (int)dreq.wdata;
+                        drsp.valid = true;
+                    } 
+                    else 
+                    {
+                        r_dcache_error_type = MMU_WRITE_PRIVILEGE_VIOLATION; 
+                        r_dcache_bad_vaddr  = dreq.addr;
+                        drsp.valid = true;
+                        drsp.error = true;
+                    }
+                    r_dcache_fsm = DCACHE_IDLE;
+                    break;
+
+                case iss_t::XTN_MMU_WORD_HI: // modifying MMU misc registers
+                    if ((dreq.mode == iss_t::MODE_HYPER) || (dreq.mode == iss_t::MODE_KERNEL)) 
+                    {
+                        r_mmu_word_hi = (int)dreq.wdata;
+                        drsp.valid = true;
+                    } 
+                    else 
+                    {
+                        r_dcache_error_type = MMU_WRITE_PRIVILEGE_VIOLATION; 
+                        r_dcache_bad_vaddr  = dreq.addr;
+                        drsp.valid = true;
+                        drsp.error = true;
+                    }
+                    r_dcache_fsm = DCACHE_IDLE;
+                    break;
+
+		  case iss_t::XTN_ICACHE_PREFETCH:
+		  case iss_t::XTN_DCACHE_PREFETCH:
+		    drsp.valid = true;
+                    drsp.error = false;
+		    break;
+	
+                default:
+                    r_dcache_error_type = MMU_WRITE_UNDEFINED_XTN; 
+                    r_dcache_bad_vaddr  = dreq.addr;
+                    drsp.valid = true;
+                    drsp.error = true;
+                    r_dcache_fsm = DCACHE_IDLE;
+                    break;
+                } // end switch xtn_opcod
+
+                break;
+            } // end if XTN_WRITE
+
+            // Evaluating dcache_hit_t, dcache_hit_x, dcache_hit_p, dcache_hit_c,
+            // dcache_pte_info, dcache_tlb_way, dcache_tlb_set & dpaddr & cacheability 
+            // - If MMU activated : cacheability is defined by the cachable bit in the TLB
+            // - If MMU not activated : cacheability is defined by the segment table.
+
+            if ( !(r_mmu_mode.read() & DATA_TLB_MASK) ) // MMU not activated
+            {
+                dcache_hit_t  = true;       
+                dcache_hit_x  = true;   
+                dcache_hit_p  = true;  
+                tlb_dpaddr    = dreq.addr; 
+                spc_dpaddr    = dreq.addr;    
+                dcache_cached = m_cacheability_table[dreq.addr] && 
+                                ((dreq.type != iss_t::DATA_LL)  && (dreq.type != iss_t::DATA_SC) &&
+                                 (dreq.type != iss_t::XTN_READ) && (dreq.type != iss_t::XTN_WRITE));     
+            } 
+            else                                                            // MMU activated
+            {
+                m_cpt_data_tlb_read++;
+                dcache_hit_t  = dcache_tlb.cctranslate(dreq.addr, &tlb_dpaddr, &dcache_pte_info, 
+                                                       &dcache_tlb_nline, &dcache_tlb_way, &dcache_tlb_set);                  
+                dcache_hit_x  = (((vaddr_t)r_dcache_vpn_save << PAGE_K_NBITS) == (dreq.addr & ~PAGE_K_MASK)) && r_dtlb_translation_valid; 
+                dcache_hit_p  = (((dreq.addr >> PAGE_M_NBITS) == r_dcache_id1_save) && r_dcache_ptba_ok );
+                spc_dpaddr    = ((paddr_t)r_dcache_ppn_save << PAGE_K_NBITS) | (paddr_t)((dreq.addr & PAGE_K_MASK));
+                dcache_cached = dcache_pte_info.c && 
+                                ((dreq.type != iss_t::DATA_LL)  && (dreq.type != iss_t::DATA_SC) &&
+                                 (dreq.type != iss_t::XTN_READ) && (dreq.type != iss_t::XTN_WRITE));    
+            }
+
+            if ( !(r_mmu_mode.read() & DATA_CACHE_MASK) )   // cache not actived
+            {
+                dcache_cached = false;
+            }
+
+            // dcache_hit_c & dcache_rdata
+            if ( dcache_cached )    // using speculative physical address for cached access
+            {
+                dcache_hit_c = r_dcache.read(spc_dpaddr, &dcache_rdata);
+            } 
+            else                    // using actual physical address for uncached access
+            {
+		dcache_hit_c = false;
+            }
+            if ( r_mmu_mode.read() & DATA_TLB_MASK ) 
+            {
+                // Checking access rights
+                if ( dcache_hit_t ) 
+                {
+                    if (!dcache_pte_info.u && (dreq.mode == iss_t::MODE_USER)) 
+                    {
+                        if ((dreq.type == iss_t::DATA_READ)||(dreq.type == iss_t::DATA_LL))
+                        {
+                            r_dcache_error_type = MMU_READ_PRIVILEGE_VIOLATION;
+                        }
+                        else /*if ((dreq.type == iss_t::DATA_WRITE)||(dreq.type == iss_t::DATA_SC))*/
+                        {
+                            r_dcache_error_type = MMU_WRITE_PRIVILEGE_VIOLATION;
+                        }  
+                        r_dcache_bad_vaddr = dreq.addr;
+                        drsp.valid = true;
+                        drsp.error = true;
+                        drsp.rdata = 0;
+                        r_dcache_fsm = DCACHE_IDLE;
+                        break;
+                    }
+                    if (!dcache_pte_info.w && ((dreq.type == iss_t::DATA_WRITE)||(dreq.type == iss_t::DATA_SC))) 
+                    {
+                        r_dcache_error_type = MMU_WRITE_ACCES_VIOLATION;  
+                        r_dcache_bad_vaddr = dreq.addr;
+                        drsp.valid = true;
+                        drsp.error = true;
+                        drsp.rdata = 0;
+                        r_dcache_fsm = DCACHE_IDLE;
+                        break;
+                    }
+                }
+
+                // update LRU, save ppn, vpn and page type
+                if ( dcache_hit_t ) {
+                    dcache_tlb.setlru(dcache_tlb_way,dcache_tlb_set); 
+                    r_dcache_ppn_save = tlb_dpaddr >> PAGE_K_NBITS;
+                    r_dcache_vpn_save = dreq.addr >> PAGE_K_NBITS;
+                    r_dcache_tlb_nline = dcache_tlb_nline;
+                    r_dtlb_translation_valid = true;
+                }
+                else
+                {
+                    r_dtlb_translation_valid = false;
+                }
+
+            } // end if MMU activated
+
+            // compute next state 
+            if ( !dcache_hit_p && !dcache_hit_t )  // TLB miss
+            {
+                r_dcache_tlb_paddr = (paddr_t)r_mmu_ptpr << (INDEX1_NBITS+2) | (paddr_t)((dreq.addr>>PAGE_M_NBITS)<<2);
+                r_dcache_fsm = DCACHE_DTLB1_READ_CACHE;
+                m_cpt_data_tlb_miss++;
+                m_cost_data_tlb_miss_frz++;
+            }
+            else if ( dcache_hit_p && !dcache_hit_t )  // TLB Miss with possibility of bypass first level page
+            {
+                // walk page table level 2
+                r_dcache_tlb_paddr = (paddr_t)r_dcache_ptba_save | 
+                                     (paddr_t)(((dreq.addr&PTD_ID2_MASK)>>PAGE_K_NBITS) << 3); 
+                r_dcache_fsm = DCACHE_DTLB2_READ_CACHE;
+                m_cpt_data_tlb_miss++;
+                m_cost_data_tlb_miss_frz++;
+            }
+            else if ( dcache_hit_t && !dcache_hit_x && dcache_cached )// cached access with an ucorrect speculative physical address
+            {
+                r_dcache_hit_p_save = dcache_hit_p;
+                r_dcache_fsm = DCACHE_BIS;
+                //m_cost_data_tlb_miss_frz++;
+            }
+            else  // cached or uncached access with a correct speculative physical address
+            {
+                switch( dreq.type ) {
+                    case iss_t::DATA_READ:
+                    case iss_t::DATA_LL:
+                    case iss_t::DATA_SC:
+                        m_cpt_read++;
+                        if ( dcache_hit_c ) 
+                        {
+                            r_dcache_fsm = DCACHE_IDLE;
+                            drsp.valid = true;
+                            drsp.rdata = dcache_rdata;
+                        } 
+                        else 
+                        {
+                            if ( dcache_cached ) 
+                            {
+                                r_dcache_miss_req = true;
+                                r_dcache_fsm = DCACHE_MISS_WAIT;
+                                m_cpt_data_miss++;
+                                m_cost_data_miss_frz++;
+                            } 
+                            else 
+                            {
+				if ((dreq.type == iss_t::DATA_SC) && !dcache_pte_info.d && (r_mmu_mode.read() & DATA_TLB_MASK))
+				{
+			    	    m_cpt_data_tlb_update_dirty++;
+                                    m_cost_data_tlb_update_dirty_frz++;
+				    r_dcache_sc_updt_dirty = true;
+                                    if ( dcache_tlb.getpagesize(dcache_tlb_way, dcache_tlb_set) )	// 2M page size, one level page table 
+                            	    {
+                                        r_dcache_pte_update = dcache_tlb.getpte(dcache_tlb_way, dcache_tlb_set) | PTE_D_MASK;
+                                        r_dcache_tlb_paddr = (paddr_t)r_mmu_ptpr << (INDEX1_NBITS+2) | (paddr_t)((dreq.addr>>PAGE_M_NBITS)<<2);
+                                        r_dcache_tlb_ll_dirty_req = true;
+                                        r_dcache_fsm = DCACHE_LL_DIRTY_WAIT;
+                            	    }
+                                    else	// 4k page size, two levels page table 
+                                    {   
+                                        if (dcache_hit_p) 
+                                        {
+                                            r_dcache_pte_update = dcache_tlb.getpte(dcache_tlb_way, dcache_tlb_set) | PTE_D_MASK;
+                                            r_dcache_tlb_paddr = (paddr_t)r_dcache_ptba_save | (paddr_t)(((dreq.addr&PTD_ID2_MASK)>>PAGE_K_NBITS) << 3);
+                                            r_dcache_tlb_ll_dirty_req = true;
+                                            r_dcache_fsm = DCACHE_LL_DIRTY_WAIT;
+                                        }
+                                        else    // get PTBA to calculate the physical address of PTE
+                                        {
+					    data_t ptba;
+            				    if (r_dcache.read((paddr_t)r_mmu_ptpr << (INDEX1_NBITS+2) | (paddr_t)((dreq.addr>>PAGE_M_NBITS)<<2), &ptba))
+					    {
+                                                r_dcache_pte_update = dcache_tlb.getpte(dcache_tlb_way, dcache_tlb_set) | PTE_D_MASK;
+                				r_dcache_tlb_paddr = (paddr_t)(ptba & ((1<<(m_paddr_nbits - PAGE_K_NBITS))-1)) << PAGE_K_NBITS | 
+                                     (paddr_t)(((dreq.addr & PTD_ID2_MASK) >> PAGE_K_NBITS) << 3);
+                                            	r_dcache_tlb_ll_dirty_req = true;
+                                            	r_dcache_fsm = DCACHE_LL_DIRTY_WAIT;
+						
+					    }
+					    else
+					    {
+                                                r_dcache_pte_update = dcache_tlb.getpte(dcache_tlb_way, dcache_tlb_set) | PTE_D_MASK;
+                                                r_dcache_tlb_paddr = (paddr_t)r_mmu_ptpr << (INDEX1_NBITS+2) | (paddr_t)((dreq.addr>>PAGE_M_NBITS)<<2);
+                                                r_dcache_tlb_ptba_read = true;
+                                                r_dcache_fsm = DCACHE_DTLB1_READ_CACHE;
+					    }
+                                        }
+                                    }				
+				}
+				else
+				{	
+                                    r_dcache_unc_req = true;
+                                    r_dcache_fsm = DCACHE_UNC_WAIT;
+                                    m_cpt_unc_read++;
+				}
+                                m_cost_unc_read_frz++;
+                            }
+                        }
+                        break;
+                    case iss_t::DATA_WRITE:
+                        m_cpt_write++;
+                        if ( dcache_cached ) m_cpt_write_cached++;
+			m_cost_write_frz++;
+                        if ( dcache_hit_c && dcache_cached )    // cache update required
+                        {
+                            r_dcache_fsm = DCACHE_WRITE_UPDT;
+                        } 
+                        else if ( !dcache_pte_info.d && (r_mmu_mode.read() & DATA_TLB_MASK) )   // dirty bit update required
+                        {
+			    m_cpt_data_tlb_update_dirty++;
+                            m_cost_data_tlb_update_dirty_frz++;
+                            if ( dcache_tlb.getpagesize(dcache_tlb_way, dcache_tlb_set) )	// 2M page size, one level page table 
+                            {
+                                r_dcache_pte_update = dcache_tlb.getpte(dcache_tlb_way, dcache_tlb_set) | PTE_D_MASK;
+                                r_dcache_tlb_paddr = (paddr_t)r_mmu_ptpr << (INDEX1_NBITS+2) | (paddr_t)((dreq.addr>>PAGE_M_NBITS)<<2);
+                                r_dcache_tlb_ll_dirty_req = true;
+                                r_dcache_fsm = DCACHE_LL_DIRTY_WAIT;
+                            }
+                            else	// 4k page size, two levels page table 
+                            {   
+                                if (dcache_hit_p) 
+                                {
+                                    r_dcache_pte_update = dcache_tlb.getpte(dcache_tlb_way, dcache_tlb_set) | PTE_D_MASK;
+                                    r_dcache_tlb_paddr = (paddr_t)r_dcache_ptba_save | (paddr_t)(((dreq.addr&PTD_ID2_MASK)>>PAGE_K_NBITS) << 3);
+                                    r_dcache_tlb_ll_dirty_req = true;
+                                    r_dcache_fsm = DCACHE_LL_DIRTY_WAIT;
+                                }
+                                else    // get PTBA to calculate the physical address of PTE
+                                {
+                                    r_dcache_pte_update = dcache_tlb.getpte(dcache_tlb_way, dcache_tlb_set) | PTE_D_MASK;
+			            data_t ptba;
+            		            if (r_dcache.read((paddr_t)r_mmu_ptpr << (INDEX1_NBITS+2) | (paddr_t)((dreq.addr>>PAGE_M_NBITS)<<2), &ptba))
+			            {
+                			r_dcache_tlb_paddr = (paddr_t)(ptba & ((1<<(m_paddr_nbits - PAGE_K_NBITS))-1)) << PAGE_K_NBITS | (paddr_t)(((dreq.addr & PTD_ID2_MASK) >> PAGE_K_NBITS) << 3);
+                                        r_dcache_tlb_ll_dirty_req = true;
+                                        r_dcache_fsm = DCACHE_LL_DIRTY_WAIT;
+			            }
+				    else
+				    {
+                                        r_dcache_tlb_paddr = (paddr_t)r_mmu_ptpr << (INDEX1_NBITS+2) | (paddr_t)((dreq.addr>>PAGE_M_NBITS)<<2);
+                                        r_dcache_tlb_ptba_read = true;
+                                        r_dcache_fsm = DCACHE_DTLB1_READ_CACHE;
+				    }
+                                }
+                            }
+                        }
+                        else                                    // no cache update, not dirty bit update
+                        {
+                            r_dcache_fsm = DCACHE_WRITE_REQ;
+                            drsp.valid = true;
+                            drsp.rdata = 0;
+                        }
+                        break;
+                    default:
+                        break;
+                } // end switch dreq.type
+            } // end if next states
+
+            // save values for the next states
+            r_dcache_paddr_save   = tlb_dpaddr;
+            r_dcache_type_save    = dreq.type;
+            r_dcache_wdata_save   = dreq.wdata;
+            r_dcache_be_save      = dreq.be;
+            r_dcache_rdata_save   = dcache_rdata;
+            r_dcache_cached_save  = dcache_cached;
+            r_dcache_dirty_save   = dcache_pte_info.d;
+            r_dcache_tlb_set_save = dcache_tlb_set;
+            r_dcache_tlb_way_save = dcache_tlb_way;
+
+        } // end if dreq.valid
+        else 
+        {   
+            r_dcache_fsm = DCACHE_IDLE;
+        }
+
+        // processor request are not accepted in the WRITE_REQ state 
+        // when the write buffer is not writeable
+
+        if ((r_dcache_fsm == DCACHE_WRITE_REQ) && 
+            (r_dcache_write_req || !r_wbuf.wok(r_dcache_paddr_save))) 
+        {
+            drsp.valid = false;
+        }
+        break;
+    }
+    /////////////////
+    case DCACHE_BIS:
+    {
+        // external cache invalidate request
+        if ( r_tgt_dcache_req )   
+        {
+            r_dcache_fsm = DCACHE_CC_CHECK;
+            r_dcache_fsm_save = r_dcache_fsm;
+            break;
+        }
+
+        // Using tlb entry is invalidated 
+        if ( r_dcache_inval_tlb_rsp )
+        {
+            r_dcache_inval_tlb_rsp = false;
+            r_dcache_fsm = DCACHE_IDLE;
+            break;
+        }
+
+        data_t  dcache_rdata = 0;
+        bool    dcache_hit_c = false;
+        bool    dcache_hit_t = false;
+        paddr_t tlb_dpaddr   = 0;
+
+	dcache_hit_t = dcache_tlb.translate(dreq.addr, &tlb_dpaddr);
+
+	if ( (tlb_dpaddr == r_dcache_paddr_save.read()) && dreq.valid && dcache_hit_t ) 
+	{
+	    // acces always cached in this state
+	    dcache_hit_c = r_dcache.read(r_dcache_paddr_save, &dcache_rdata);
+	    
+	    if ( dreq.type == iss_t::DATA_READ )  // cached read
+	    {
+	        m_cpt_read++;
+	        if ( !dcache_hit_c ) 
+	        {
+	            r_dcache_miss_req = true;
+	            r_dcache_fsm = DCACHE_MISS_WAIT;
+	            m_cpt_data_miss++;
+	            m_cost_data_miss_frz++;
+	        }
+	        else
+	        {
+	            r_dcache_fsm = DCACHE_IDLE;
+	        }
+	        drsp.valid = dcache_hit_c;
+	        drsp.error = false;
+	        drsp.rdata = dcache_rdata;
+	    }
+	    else    // cached write
+	    {
+	        m_cpt_write++;
+	        m_cpt_write_cached++;
+	        if ( dcache_hit_c )    // cache update required
+	        {
+	            r_dcache_rdata_save = dcache_rdata;
+	            r_dcache_fsm = DCACHE_WRITE_UPDT;
+	        } 
+	        else if (!r_dcache_dirty_save && (r_mmu_mode.read() & DATA_TLB_MASK))   // dirty bit update required
+	        {
+                    m_cpt_data_tlb_update_dirty++;
+                    m_cost_data_tlb_update_dirty_frz++;  			
+	            if (dcache_tlb.getpagesize(r_dcache_tlb_way_save, r_dcache_tlb_set_save)) 
+	            {
+	                r_dcache_pte_update = dcache_tlb.getpte(r_dcache_tlb_way_save, r_dcache_tlb_set_save) | PTE_D_MASK;
+	                r_dcache_tlb_paddr = (paddr_t)r_mmu_ptpr << (INDEX1_NBITS+2) | (paddr_t)((dreq.addr>>PAGE_M_NBITS)<<2);
+	                r_dcache_tlb_ll_dirty_req = true;
+	                r_dcache_fsm = DCACHE_LL_DIRTY_WAIT;
+	            }
+	            else
+	            {   
+	                if (r_dcache_hit_p_save) 
+	                {
+	                    r_dcache_pte_update = dcache_tlb.getpte(r_dcache_tlb_way_save, r_dcache_tlb_set_save) | PTE_D_MASK;
+	                    r_dcache_tlb_paddr = (paddr_t)r_dcache_ptba_save|(paddr_t)(((dreq.addr&PTD_ID2_MASK)>>PAGE_K_NBITS) << 3);
+	                    r_dcache_tlb_ll_dirty_req = true;
+	                    r_dcache_fsm = DCACHE_LL_DIRTY_WAIT;
+	                }
+	                else
+	                {
+	                    r_dcache_pte_update = dcache_tlb.getpte(r_dcache_tlb_way_save, r_dcache_tlb_set_save) | PTE_D_MASK;
+			    data_t ptba;
+            		    if (r_dcache.read((paddr_t)r_mmu_ptpr << (INDEX1_NBITS+2) | (paddr_t)((dreq.addr>>PAGE_M_NBITS)<<2), &ptba))
+			    {
+                	        r_dcache_tlb_paddr = (paddr_t)(ptba & ((1<<(m_paddr_nbits - PAGE_K_NBITS))-1)) << PAGE_K_NBITS | (paddr_t)(((dreq.addr & PTD_ID2_MASK) >> PAGE_K_NBITS) << 3);
+                                r_dcache_tlb_ll_dirty_req = true;
+                                r_dcache_fsm = DCACHE_LL_DIRTY_WAIT;
+			    }
+			    else
+			    {
+                                r_dcache_tlb_paddr = (paddr_t)r_mmu_ptpr << (INDEX1_NBITS+2) | (paddr_t)((dreq.addr>>PAGE_M_NBITS)<<2);
+                                r_dcache_tlb_ptba_read = true;
+                                r_dcache_fsm = DCACHE_DTLB1_READ_CACHE;
+			    }
+	                }
+	            }
+	        }
+	        else                                    // no cache update, not dirty bit update
+	        {
+	            r_dcache_fsm = DCACHE_WRITE_REQ;
+	            drsp.valid = true;
+	            drsp.rdata = 0;
+	        }
+	    }
+	}
+	else
+	{
+            drsp.valid = false;
+            drsp.error = false;
+            drsp.rdata = 0;
+            r_dcache_fsm = DCACHE_IDLE;
+	}
+        break;
+    }
+    //////////////////////////
+    case DCACHE_LL_DIRTY_WAIT:
+    {
+	m_cost_data_tlb_update_dirty_frz++;
+
+        // external cache invalidate request
+        if ( r_tgt_dcache_req )   
+        {
+            r_dcache_fsm = DCACHE_CC_CHECK;
+            r_dcache_fsm_save = r_dcache_fsm;
+            break;
+        }
+
+	if (!r_dcache_tlb_ll_dirty_req)
+	{
+            if ( r_vci_rsp_data_error ) // VCI response ko
+            {
+		if (dcache_tlb.getpagesize(r_dcache_tlb_way_save, r_dcache_tlb_set_save)) 
+		{
+                    r_dcache_error_type = MMU_WRITE_PT1_ILLEGAL_ACCESS;     
+		}
+		else
+		{
+                    r_dcache_error_type = MMU_WRITE_PT2_ILLEGAL_ACCESS;     
+		}
+                r_dcache_bad_vaddr = dreq.addr;
+                r_dcache_fsm = DCACHE_ERROR; 
+
+		if (r_dcache_inval_tlb_rsp) r_dcache_inval_tlb_rsp = false;
+		if (r_dcache_inval_rsp) r_dcache_inval_rsp = false;
+		if (r_dcache_sc_updt_dirty) r_dcache_sc_updt_dirty = false;
+            }
+	    else
+	    {
+		if ( !(r_dcache_miss_buf[0] >> PTE_V_SHIFT) )	// unmapped
+	        {
+		    if (dcache_tlb.getpagesize(r_dcache_tlb_way_save, r_dcache_tlb_set_save))
+		    { 
+			r_dcache_error_type = MMU_WRITE_PT1_UNMAPPED;       
+		    }
+		    else
+		    {
+			r_dcache_error_type = MMU_WRITE_PT2_UNMAPPED;       
+	  	    }
+                    r_dcache_bad_vaddr = dreq.addr;
+                    r_dcache_fsm = DCACHE_ERROR;
+
+		    if (r_dcache_inval_tlb_rsp) r_dcache_inval_tlb_rsp = false;
+		    if (r_dcache_inval_rsp) r_dcache_inval_rsp = false;
+		    if (r_dcache_sc_updt_dirty) r_dcache_sc_updt_dirty = false;
+	        }
+        	else if ( r_dcache_inval_tlb_rsp )
+        	{
+        	    r_dcache_inval_tlb_rsp = false;
+        	    r_dcache_fsm = DCACHE_IDLE;
+		    if (r_dcache_sc_updt_dirty) r_dcache_sc_updt_dirty = false;
+        	}
+		else if ( r_dcache_inval_rsp )
+		{
+        	    r_dcache_inval_rsp = false;
+		    r_dcache_fsm = DCACHE_IDLE;
+		    if (r_dcache_sc_updt_dirty) r_dcache_sc_updt_dirty = false;
+		}
+		else
+		{
+		    r_dcache_tlb_sc_dirty_req = true;
+		    r_dcache_pte_update = r_dcache_miss_buf[0] | r_dcache_pte_update.read();
+                    r_dcache_fsm = DCACHE_SC_DIRTY_WAIT; 
+		}
+	    }
+	}
+	break;
+    }
+    //////////////////////////
+    case DCACHE_SC_DIRTY_WAIT:
+    {
+        m_cost_data_tlb_update_dirty_frz++;	    
+        // external cache invalidate request
+        if ( r_tgt_dcache_req )   
+        {
+            r_dcache_fsm = DCACHE_CC_CHECK;
+            r_dcache_fsm_save = r_dcache_fsm;
+            break;
+        }
+
+	if ( !r_dcache_tlb_sc_dirty_req )
+	{
+	    if ( r_vci_rsp_data_error ) // VCI response ko
+	    {
+	        if (dcache_tlb.getpagesize(r_dcache_tlb_way_save, r_dcache_tlb_set_save))
+	        {
+	            r_dcache_error_type = MMU_WRITE_PT1_ILLEGAL_ACCESS;    
+	        }
+	        else
+	        {
+	            r_dcache_error_type = MMU_WRITE_PT2_ILLEGAL_ACCESS;    
+	        }
+	        r_dcache_bad_vaddr = dreq.addr;
+	        r_dcache_fsm = DCACHE_ERROR;
+
+		if (r_dcache_inval_tlb_rsp) r_dcache_inval_tlb_rsp = false;
+		if (r_dcache_inval_rsp) r_dcache_inval_rsp = false;		 	    
+		if (r_dcache_sc_updt_dirty) r_dcache_sc_updt_dirty = false;
+	    }
+	    else 
+	    {
+                // Using tlb entry is invalidated 
+                if ( r_dcache_inval_tlb_rsp )
+                {
+                    r_dcache_inval_tlb_rsp = false;
+                    r_dcache_fsm = DCACHE_IDLE;
+		    if (r_dcache_tlb_sc_fail) r_dcache_tlb_sc_fail = false;
+		    if (r_dcache_sc_updt_dirty) r_dcache_sc_updt_dirty = false;
+                }
+		else if ( r_dcache_inval_rsp )
+		{
+        	    r_dcache_inval_rsp = false;
+		    r_dcache_fsm = DCACHE_IDLE;
+		    if (r_dcache_tlb_sc_fail) r_dcache_tlb_sc_fail = false;
+		    if (r_dcache_sc_updt_dirty) r_dcache_sc_updt_dirty = false;
+		}
+		else if ( r_dcache_tlb_sc_fail )
+	        {
+		    r_dcache_tlb_ll_dirty_req = true;
+		    r_dcache_tlb_sc_fail = false;
+	            r_dcache_fsm = DCACHE_LL_DIRTY_WAIT;
+		    m_cpt_data_tlb_update_dirty++; 
+	        }
+		else
+		{
+                    bool write_hit = r_dcache.write(r_dcache_tlb_paddr, r_dcache_pte_update);
+		    assert(write_hit && "Write on miss ignores data for data MMU update dirty bit");
+	            r_dcache_fsm = DCACHE_WRITE_DIRTY; 
+		    m_cpt_dcache_data_write++; 
+		}
+	    }
+	}
+	break;
+    }
+    ////////////////////////////
+    case DCACHE_DTLB1_READ_CACHE:
+    {
+        m_cost_data_tlb_miss_frz++;
+        if ( r_dcache_tlb_ptba_read ) m_cost_data_tlb_update_dirty_frz++;
+
+        // external cache invalidate request
+        if ( r_tgt_dcache_req )   
+        {
+            r_dcache_fsm = DCACHE_CC_CHECK;
+            r_dcache_fsm_save = r_dcache_fsm;
+            break;
+        }        
+
+        // Using tlb entry is invalidated 
+        if ( r_dcache_inval_tlb_rsp )
+        {
+            r_dcache_inval_tlb_rsp = false;
+            r_dcache_fsm = DCACHE_IDLE;
+            if ( r_dcache_tlb_ptba_read ) r_dcache_tlb_ptba_read = false;
+            break;
+        }
+
+        data_t tlb_data = 0;
+        bool tlb_hit_cache = r_dcache.read(r_dcache_tlb_paddr, &tlb_data);
+
+        // DTLB request hit in cache
+        if ( tlb_hit_cache )
+        {
+	    if ( !(tlb_data >> PTE_V_SHIFT) )	// unmapped
+	    {
+                r_dcache_ptba_ok    = false;
+                if ((r_dcache_type_save == iss_t::DATA_READ)||(r_dcache_type_save == iss_t::DATA_LL))
+                {
+                    r_dcache_error_type = MMU_READ_PT1_UNMAPPED;
+                }
+                else /*if ((dreq.type == iss_t::DATA_WRITE)||(dreq.type == iss_t::DATA_SC))*/
+                {
+                    r_dcache_error_type = MMU_WRITE_PT1_UNMAPPED;
+                }  
+                r_dcache_bad_vaddr  = dreq.addr;
+                r_dcache_fsm        = DCACHE_ERROR;
+	    }
+	    else if ( (tlb_data & PTE_T_MASK) >> PTE_T_SHIFT )	// PTD
+	    {
+                r_dcache_ptba_ok   = true;
+                r_dcache_ptba_save = (paddr_t)(tlb_data & ((1<<(m_paddr_nbits - PAGE_K_NBITS))-1)) << PAGE_K_NBITS;  
+                r_dcache_id1_save  = dreq.addr >> PAGE_M_NBITS;
+                r_dcache_tlb_paddr = (paddr_t)(tlb_data & ((1<<(m_paddr_nbits - PAGE_K_NBITS))-1)) << PAGE_K_NBITS | 
+                                     (paddr_t)(((dreq.addr & PTD_ID2_MASK) >> PAGE_K_NBITS) << 3);
+                if ( r_dcache_tlb_ptba_read )
+                {
+                    paddr_t tlb_dpaddr;
+		    data_t data;
+                    r_dcache_tlb_ptba_read = false;
+		    if (dcache_tlb.translate(dreq.addr, &tlb_dpaddr) && r_dcache.read( (paddr_t)(tlb_data & ((1<<(m_paddr_nbits - PAGE_K_NBITS))-1)) << PAGE_K_NBITS | (paddr_t)(((dreq.addr & PTD_ID2_MASK) >> PAGE_K_NBITS) << 3) ,&data))
+		    {
+                        r_dcache_tlb_ll_dirty_req = true;
+                        r_dcache_fsm = DCACHE_LL_DIRTY_WAIT;
+ 		    }	        
+		    else
+		    {
+		    	r_dcache_fsm = DCACHE_IDLE;
+                    }
+                }
+                else
+                {
+                    r_dcache_fsm = DCACHE_DTLB2_READ_CACHE;
+                }
+	    }
+	    else	// PTE
+	    {
+		m_cpt_data_tlb_hit_dcache++;
+                r_dcache_ptba_ok = false;
+	        if ( (m_srcid_rw >> 4) == ((r_dcache_tlb_paddr.read() & ((1<<(m_paddr_nbits - PAGE_M_NBITS))-1)) >> (m_paddr_nbits - PAGE_M_NBITS -10)) ) // local
+		{
+		    if ( (tlb_data & PTE_L_MASK ) >> PTE_L_SHIFT ) // L bit is set
+		    {
+                        r_dcache_pte_update = tlb_data;
+                        r_dcache_fsm = DCACHE_TLB1_UPDT_SEL;
+		    }
+		    else
+		    {
+                        r_dcache_pte_update = tlb_data | PTE_L_MASK;
+                        r_dcache_tlb_ll_acc_req = true;
+                        r_dcache_fsm = DCACHE_TLB1_LL_WAIT;
+                        m_cpt_data_tlb_update_acc++;
+                        m_cost_data_tlb_update_acc_frz++;
+		    }
+    	        }
+		else // remotely
+		{
+		    if ( (tlb_data & PTE_R_MASK ) >> PTE_R_SHIFT ) // R bit is set
+		    {
+                        r_dcache_pte_update = tlb_data;
+                        r_dcache_fsm = DCACHE_TLB1_UPDT_SEL;
+		    }
+		    else
+		    {
+                        r_dcache_pte_update = tlb_data | PTE_R_MASK;
+                        r_dcache_tlb_ll_acc_req = true;
+                        r_dcache_fsm = DCACHE_TLB1_LL_WAIT;
+                        m_cpt_data_tlb_update_acc++;
+                        m_cost_data_tlb_update_acc_frz++;
+		    }
+		}
+	    }
+        }
+        else
+        {
+            // DTLB request miss in cache and walk page table level 1
+            r_dcache_tlb_read_req = true;
+            r_dcache_fsm = DCACHE_TLB1_READ;
+        }
+        break;
+    }
+    ///////////////////////
+    case DCACHE_TLB1_LL_WAIT:
+    {
+        if ( dreq.valid ) m_cost_data_tlb_miss_frz++;
+        m_cost_data_tlb_update_acc_frz++;
+	    
+        // external cache invalidate request
+        if ( r_tgt_dcache_req )   
+        {
+            r_dcache_fsm = DCACHE_CC_CHECK;
+            r_dcache_fsm_save = r_dcache_fsm;
+            break;
+        }
+
+	if (!r_dcache_tlb_ll_acc_req)
+	{
+            if ( r_vci_rsp_data_error ) // VCI response ko
+            {
+                if ((r_dcache_type_save == iss_t::DATA_READ)||(r_dcache_type_save == iss_t::DATA_LL))
+                {
+                    r_dcache_error_type = MMU_READ_PT1_ILLEGAL_ACCESS;
+                }
+                else /*if ((dreq.type == iss_t::DATA_WRITE)||(dreq.type == iss_t::DATA_SC))*/
+                {
+                    r_dcache_error_type = MMU_WRITE_PT1_ILLEGAL_ACCESS;
+                } 
+                r_dcache_bad_vaddr = dreq.addr;
+                r_dcache_fsm = DCACHE_ERROR;
+
+		if (r_dcache_inval_tlb_rsp) r_dcache_inval_tlb_rsp = false;
+		if (r_dcache_inval_rsp) r_dcache_inval_rsp = false;		 
+            }
+	    else
+	    {
+		if ( !(r_dcache_miss_buf[0] >> PTE_V_SHIFT) )	// unmapped
+	        {
+               	    if ((r_dcache_type_save == iss_t::DATA_READ)||(r_dcache_type_save == iss_t::DATA_LL))
+               	    {
+               	        r_dcache_error_type = MMU_READ_PT1_UNMAPPED;
+               	    }
+               	    else /*if ((dreq.type == iss_t::DATA_WRITE)||(dreq.type == iss_t::DATA_SC))*/
+               	    {
+               	        r_dcache_error_type = MMU_WRITE_PT1_UNMAPPED;
+               	    }  
+                    r_dcache_bad_vaddr  = dreq.addr;
+                    r_dcache_fsm        = DCACHE_ERROR;
+
+		    if (r_dcache_inval_tlb_rsp) r_dcache_inval_tlb_rsp = false;
+		    if (r_dcache_inval_rsp) r_dcache_inval_rsp = false;	
+	        }
+       		else if ( r_dcache_inval_tlb_rsp )
+       		{
+       		    r_dcache_inval_tlb_rsp = false;
+       		    r_dcache_fsm = DCACHE_IDLE;
+       		}
+		else if ( r_dcache_inval_rsp )
+       		{
+       		    r_dcache_inval_rsp = false;
+       		    r_dcache_fsm = DCACHE_IDLE;
+       		}
+		else
+		{
+		    r_dcache_tlb_sc_acc_req = true;
+		    r_dcache_pte_update = r_dcache_miss_buf[0] | r_dcache_pte_update.read();
+                    r_dcache_fsm = DCACHE_TLB1_SC_WAIT; 
+		}
+	    }
+	}
+	break;
+    }
+    ///////////////////////
+    case DCACHE_TLB1_SC_WAIT:
+    {
+        if ( dreq.valid ) m_cost_data_tlb_miss_frz++;
+        m_cost_data_tlb_update_acc_frz++;	    
+        // external cache invalidate request
+        if ( r_tgt_dcache_req )   
+        {
+            r_dcache_fsm = DCACHE_CC_CHECK;
+            r_dcache_fsm_save = r_dcache_fsm;
+            break;
+        }
+
+	if ( !r_dcache_tlb_sc_acc_req )
+	{
+	    if ( r_vci_rsp_data_error ) // VCI response ko
+	    {
+                if ((r_dcache_type_save == iss_t::DATA_READ)||(r_dcache_type_save == iss_t::DATA_LL))
+                {
+                    r_dcache_error_type = MMU_READ_PT1_ILLEGAL_ACCESS;
+                }
+                else /*if ((dreq.type == iss_t::DATA_WRITE)||(dreq.type == iss_t::DATA_SC))*/
+                {
+                    r_dcache_error_type = MMU_WRITE_PT1_ILLEGAL_ACCESS;
+                } 
+	        r_dcache_bad_vaddr = dreq.addr;
+	        r_dcache_fsm = DCACHE_ERROR; 
+
+		if (r_dcache_inval_tlb_rsp) r_dcache_inval_tlb_rsp = false;
+		if (r_dcache_inval_rsp) r_dcache_inval_rsp = false;	
+	    }
+	    else
+	    {
+        	// Using tlb entry is invalidated 
+        	if ( r_dcache_inval_tlb_rsp )
+        	{
+        	    r_dcache_inval_tlb_rsp = false;
+        	    r_dcache_fsm = DCACHE_IDLE;
+		    if (r_dcache_tlb_sc_fail) r_dcache_tlb_sc_fail = false;
+        	}
+		else if ( r_dcache_inval_rsp )
+        	{
+        	    r_dcache_inval_rsp = false;
+		    if (r_dcache_tlb_sc_fail) r_dcache_tlb_sc_fail = false;
+        	    r_dcache_fsm = DCACHE_IDLE;
+        	}
+	    	else if ( r_dcache_tlb_sc_fail )
+	    	{
+		    r_dcache_tlb_sc_fail = false;
+		    r_dcache_tlb_ll_acc_req = true;
+	    	    r_dcache_fsm = DCACHE_TLB1_LL_WAIT;
+                    m_cpt_data_tlb_update_acc++;
+	    	}
+	    	else 
+	    	{
+		    bool write_hit = r_dcache.write(r_dcache_tlb_paddr,r_dcache_pte_update);  
+                    assert(write_hit && "Write on miss ignores data for data MMU update data access bit"); 
+	    	    r_dcache_fsm = DCACHE_TLB1_UPDT_SEL; 
+		    m_cpt_dcache_data_write++;
+	    	}
+	    }
+	}
+	break;
+    }
+    //////////////////////
+    case DCACHE_TLB1_READ:
+    {
+        if ( dreq.valid ) m_cost_data_tlb_miss_frz++;
+        if ( r_dcache_tlb_ptba_read ) m_cost_data_tlb_update_dirty_frz++;
+
+        // external cache invalidate request
+        if ( r_tgt_dcache_req )   
+        {
+            r_dcache_fsm = DCACHE_CC_CHECK;
+            r_dcache_fsm_save = r_dcache_fsm;
+            break;
+        }        
+
+	if ( !r_dcache_tlb_read_req )
+	{	
+            if ( r_vci_rsp_data_error ) // VCI response ko
+            {
+                if ((r_dcache_type_save == iss_t::DATA_READ)||(r_dcache_type_save == iss_t::DATA_LL))
+                {
+                    r_dcache_error_type = MMU_READ_PT1_ILLEGAL_ACCESS;
+                }
+                else /*if ((dreq.type == iss_t::DATA_WRITE)||(dreq.type == iss_t::DATA_SC))*/
+                {
+                    r_dcache_error_type = MMU_WRITE_PT1_ILLEGAL_ACCESS;
+                } 
+                r_dcache_bad_vaddr = dreq.addr;
+                r_dcache_fsm = DCACHE_ERROR; 
+
+		if (r_dcache_inval_tlb_rsp) r_dcache_inval_tlb_rsp = false;
+		if (r_dcache_inval_rsp) r_dcache_inval_rsp = false;	
+                if ( r_dcache_tlb_ptba_read ) r_dcache_tlb_ptba_read = false;
+		break;
+            }
+
+            if ( r_dcache_inval_tlb_rsp )  // TLB miss response and invalidation
+            {
+                r_dcache_fsm = DCACHE_IDLE; 
+            	r_dcache_inval_tlb_rsp = false;
+                if ( r_dcache_tlb_ptba_read ) r_dcache_tlb_ptba_read = false;
+		break;
+            }
+
+	    if ( r_dcache_inval_rsp ) // TLB miss response and cache invalidation
+	    {
+	        if ( r_dcache_cleanup_req ) break;
+                r_dcache_cleanup_req = true;
+                r_dcache_cleanup_line = r_dcache_tlb_paddr.read() >> (uint32_log2(m_dcache_words) + 2);  
+		m_cpt_cc_cleanup_data++;
+                r_dcache_fsm = DCACHE_IDLE;
+                r_dcache_inval_rsp = false;
+                if ( r_dcache_tlb_ptba_read ) r_dcache_tlb_ptba_read = false;
+                break;
+	    }
+
+	    // TLB miss response and no invalidation
+	    r_dcache_fsm = DCACHE_TLB1_READ_UPDT;
+	}
+        break;
+    }
+    //////////////////////////
+    case DCACHE_TLB1_READ_UPDT:
+    {
+        m_cost_data_tlb_miss_frz++;
+        if ( r_dcache_tlb_ptba_read ) m_cost_data_tlb_update_dirty_frz++;
+
+        // external cache invalidate request
+        if ( r_tgt_dcache_req )   
+        {
+            r_dcache_fsm = DCACHE_CC_CHECK;
+            r_dcache_fsm_save = r_dcache_fsm;
+            break;
+        }        
+
+        // Using tlb entry is invalidated 
+        if ( r_dcache_inval_tlb_rsp )
+        {
+            r_dcache_inval_tlb_rsp = false;
+            r_dcache_fsm = DCACHE_IDLE;
+            if ( r_dcache_tlb_ptba_read ) r_dcache_tlb_ptba_read = false;
+            break;
+        }
+
+        if ( !r_dcache_cleanup_req ) // Miss update and no invalidation
+        {
+            // update dcache
+            data_t   rsp_dtlb_miss = 0;
+            paddr_t  victim_index = 0;
+            size_t way = 0;
+            size_t set = 0;
+
+            // Using tlb entry is in the invalidated cache line  
+            if ( r_dcache_inval_rsp )
+            {
+                r_dcache_cleanup_req = true;
+                r_dcache_cleanup_line = r_dcache_tlb_paddr.read() >> (uint32_log2(m_dcache_words) + 2); 
+	        m_cpt_cc_cleanup_data++;	
+                r_dcache_fsm = DCACHE_IDLE;
+                r_dcache_inval_rsp = false;
+                if ( r_dcache_tlb_ptba_read ) r_dcache_tlb_ptba_read = false;
+                break;
+            }
+
+            bool cleanup_req = r_dcache.find(r_dcache_tlb_paddr, r_dcache_in_itlb, r_dcache_in_dtlb, &way, &set, &victim_index);
+            
+	    if ( cleanup_req )
+	    {	    
+		// ins tlb invalidate verification    
+                r_dcache_itlb_inval_req = r_dcache_in_itlb[m_dcache_sets*way+set];
+                r_dcache_itlb_inval_line = victim_index;
+                r_dcache_in_itlb[way*m_dcache_sets+set] = false;
+
+                // data tlb invalidate verification
+                r_dcache_dtlb_inval_req = r_dcache_in_dtlb[m_dcache_sets*way+set]; 
+                r_dcache_dtlb_inval_line = victim_index;
+                r_dcache_in_dtlb[way*m_dcache_sets+set] = false;
+
+                r_dcache_cleanup_req = true; 
+                r_dcache_cleanup_line = victim_index;
+		m_cpt_cc_cleanup_data++;
+		r_dcache_fsm = DCACHE_TLB_CC_INVAL;
+                r_dcache_fsm_save = r_dcache_fsm;
+		break;
+	    }
+
+	    r_dcache.update(r_dcache_tlb_paddr, way, set, r_dcache_miss_buf);
+            r_dcache.read(r_dcache_tlb_paddr, &rsp_dtlb_miss);	
+	    m_cpt_data_tlb_occup_cache++;
+
+	    if ( !(rsp_dtlb_miss >> PTE_V_SHIFT) )	// unmapped
+	    {
+                r_dcache_ptba_ok    = false;
+                if ((r_dcache_type_save == iss_t::DATA_READ)||(r_dcache_type_save == iss_t::DATA_LL))
+                {
+                    r_dcache_error_type = MMU_READ_PT1_UNMAPPED;
+                }
+                else /*if ((dreq.type == iss_t::DATA_WRITE)||(dreq.type == iss_t::DATA_SC))*/
+                {
+                    r_dcache_error_type = MMU_WRITE_PT1_UNMAPPED;
+                } 
+                r_dcache_bad_vaddr  = dreq.addr;
+                r_dcache_fsm        = DCACHE_ERROR;
+                if ( r_dcache_tlb_ptba_read ) r_dcache_tlb_ptba_read = false;
+	    }
+	    else if ( (rsp_dtlb_miss & PTE_T_MASK) >> PTE_T_SHIFT ) // PTD
+	    {
+                r_dcache_ptba_ok   = true;
+                r_dcache_ptba_save = (paddr_t)(rsp_dtlb_miss & ((1<<(m_paddr_nbits - PAGE_K_NBITS))-1)) << PAGE_K_NBITS;  
+                r_dcache_id1_save  = dreq.addr >> PAGE_M_NBITS;
+                r_dcache_tlb_paddr = (paddr_t)(rsp_dtlb_miss & ((1<<(m_paddr_nbits - PAGE_K_NBITS))-1)) << PAGE_K_NBITS | 
+                                     (paddr_t)(((dreq.addr & PTD_ID2_MASK) >> PAGE_K_NBITS) << 3);
+                if ( r_dcache_tlb_ptba_read )
+                {
+                    paddr_t tlb_dpaddr;
+		    data_t data;
+                    r_dcache_tlb_ptba_read = false;
+		    if (dcache_tlb.translate(dreq.addr, &tlb_dpaddr) && r_dcache.read((paddr_t)(rsp_dtlb_miss & ((1<<(m_paddr_nbits - PAGE_K_NBITS))-1)) << PAGE_K_NBITS | (paddr_t)(((dreq.addr & PTD_ID2_MASK) >> PAGE_K_NBITS) << 3),&data))
+		    {
+                        r_dcache_tlb_ll_dirty_req = true;
+                        r_dcache_fsm = DCACHE_LL_DIRTY_WAIT;
+ 		    }	        
+		    else
+		    {
+		    	r_dcache_fsm = DCACHE_IDLE;
+                    }
+                }
+                else
+                {
+                    r_dcache_fsm = DCACHE_DTLB2_READ_CACHE;
+                }
+	    }
+	    else	// PTE
+	    {
+                r_dcache_ptba_ok = false;
+	        if ( (m_srcid_rw >> 4) == ((r_dcache_tlb_paddr.read() & ((1<<(m_paddr_nbits - PAGE_M_NBITS))-1)) >> (m_paddr_nbits - PAGE_M_NBITS -10)) ) // local
+		{
+		    if ( (rsp_dtlb_miss & PTE_L_MASK ) >> PTE_L_SHIFT ) // L bit is set
+		    {
+                        r_dcache_pte_update = rsp_dtlb_miss;
+                        r_dcache_fsm        = DCACHE_TLB1_UPDT_SEL;
+		    }
+		    else
+		    {
+                        r_dcache_pte_update = rsp_dtlb_miss | PTE_L_MASK;
+                        r_dcache_tlb_ll_acc_req = true;
+                        r_dcache_fsm        = DCACHE_TLB1_LL_WAIT;
+			m_cpt_data_tlb_update_acc++;
+                        m_cost_data_tlb_update_acc_frz++;
+		    }
+    	        }
+		else // remotely
+		{
+		    if ( (rsp_dtlb_miss & PTE_R_MASK ) >> PTE_R_SHIFT ) // R bit is set
+		    {
+                        r_dcache_pte_update = rsp_dtlb_miss;
+                        r_dcache_fsm        = DCACHE_TLB1_UPDT_SEL;
+		    }
+		    else
+		    {
+                        r_dcache_pte_update = rsp_dtlb_miss | PTE_R_MASK;
+                        r_dcache_tlb_ll_acc_req = true;
+                        r_dcache_fsm        = DCACHE_TLB1_LL_WAIT;
+			m_cpt_data_tlb_update_acc++;
+                        m_cost_data_tlb_update_acc_frz++;
+		    }
+		}
+	    }
+        }
+        break;
+    }
+    /////////////////////////
+    case DCACHE_TLB1_UPDT_SEL: 
+    {
+        m_cost_data_tlb_miss_frz++;
+        m_cost_data_tlb_update_acc_frz++;
+	
+        // external cache invalidate request
+        if ( r_tgt_dcache_req )   
+        {
+            r_dcache_fsm = DCACHE_CC_CHECK;
+            r_dcache_fsm_save = r_dcache_fsm;
+            break;
+        }        
+
+        if ( !r_dcache_inval_tlb_rsp && !r_dcache_inval_rsp )
+        {
+	    size_t way = 0;
+	    size_t set = 0;
+            paddr_t victim_index = 0;
+	    bool cleanup = dcache_tlb.select((dreq.addr >> PAGE_M_NBITS),&victim_index,&way,&set);
+	    if (cleanup)
+	    {
+	        r_dcache_dtlb_cleanup_req = true;
+		r_dcache_dtlb_cleanup_line = victim_index;
+		//m_cpt_cc_cleanup_data++;
+	    }
+	    r_dcache_way = way;
+	    r_dcache_set = set;
+            r_dcache_fsm = DCACHE_TLB1_UPDT;
+        }
+        else  
+        {
+            if ( r_dcache_inval_tlb_rsp ) r_dcache_inval_tlb_rsp = false;
+            if ( r_dcache_inval_rsp ) r_dcache_inval_rsp = false;
+            r_dcache_fsm = DCACHE_IDLE;
+        }
+        break;
+    }
+    //////////////////////
+    case DCACHE_TLB1_UPDT: 
+    {
+        m_cost_data_tlb_miss_frz++;
+        m_cost_data_tlb_update_acc_frz++;
+
+	if (r_dcache_dtlb_cleanup_req) r_dcache.setinbit(r_dcache_dtlb_cleanup_line.read() << (uint32_log2(m_dcache_words)+2), r_dcache_in_dtlb, false);
+        bool set_hit = r_dcache.setinbit(r_dcache_tlb_paddr, r_dcache_in_dtlb, true);
+        assert(set_hit && "TLB1_UPDT set hit error");  
+	dcache_tlb.update(r_dcache_pte_update,dreq.addr,r_dcache_way.read(),r_dcache_set.read(),(r_dcache_tlb_paddr.read() >> (uint32_log2(m_dcache_words)+2)));
+        r_dcache_fsm = DCACHE_IDLE;
+	break;
+    }
+    /////////////////////////////
+    case DCACHE_DTLB2_READ_CACHE:
+    {
+        m_cost_data_tlb_miss_frz++;
+
+        // external cache invalidate request
+        if ( r_tgt_dcache_req )   
+        {
+            r_dcache_fsm = DCACHE_CC_CHECK;
+            r_dcache_fsm_save = r_dcache_fsm;
+            break;
+        }        
+
+        // Using tlb entry is invalidated 
+        if ( r_dcache_inval_tlb_rsp )
+        {
+            r_dcache_inval_tlb_rsp = false;
+            r_dcache_fsm = DCACHE_IDLE;
+            break;
+        }
+
+        data_t tlb_data = 0;
+        data_t tlb_data_ppn = 0;
+        bool tlb_hit_cache = r_dcache.read(r_dcache_tlb_paddr, &tlb_data);
+
+	if ( tlb_hit_cache )
+	{
+            bool tlb_hit_ppn = r_dcache.read(r_dcache_tlb_paddr.read()+4, &tlb_data_ppn);
+	    assert(tlb_hit_ppn && "Address of pte[64-32] and pte[31-0] should be successive");
+	}
+
+        // DTLB request hit in cache
+        if ( tlb_hit_cache )
+        {
+	    if ( !(tlb_data >> PTE_V_SHIFT) )	// unmapped
+	    {
+                if ((r_dcache_type_save == iss_t::DATA_READ)||(r_dcache_type_save == iss_t::DATA_LL))
+                {
+                    r_dcache_error_type = MMU_READ_PT2_UNMAPPED;
+                }
+                else /*if ((dreq.type == iss_t::DATA_WRITE)||(dreq.type == iss_t::DATA_SC))*/
+                {
+                    r_dcache_error_type = MMU_WRITE_PT2_UNMAPPED;
+                } 
+                r_dcache_bad_vaddr  = dreq.addr;
+                r_dcache_fsm        = DCACHE_ERROR;
+	    }
+	    else if ( (tlb_data & PTE_T_MASK) >> PTE_T_SHIFT ) //PTD
+	    {
+                r_dcache_pte_update = tlb_data;
+	        r_dcache_ppn_update = tlb_data_ppn;
+		r_dcache_fsm = DCACHE_TLB2_UPDT_SEL;
+	    }
+	    else 
+	    {
+		m_cpt_data_tlb_hit_dcache++;
+	        if ( (m_srcid_rw >> 4) == ((r_dcache_tlb_paddr.read() & ((1<<(m_paddr_nbits - PAGE_M_NBITS))-1)) >> (m_paddr_nbits - PAGE_M_NBITS -10)) ) // local
+		{
+		    if ( (tlb_data & PTE_L_MASK ) >> PTE_L_SHIFT ) // L bit is set
+		    {
+                        r_dcache_pte_update = tlb_data;
+			r_dcache_ppn_update = tlb_data_ppn;
+                        r_dcache_fsm        = DCACHE_TLB2_UPDT_SEL;
+		    }
+		    else
+		    {
+                        r_dcache_pte_update = tlb_data | PTE_L_MASK;
+	        	r_dcache_ppn_update = tlb_data_ppn;
+                        r_dcache_tlb_ll_acc_req = true;
+                        r_dcache_fsm = DCACHE_TLB2_LL_WAIT;
+                        m_cpt_data_tlb_update_acc++;
+                        m_cost_data_tlb_update_acc_frz++;
+		    }
+    	        }
+		else // remotely
+		{
+		    if ( (tlb_data & PTE_R_MASK ) >> PTE_R_SHIFT ) // R bit is set
+		    {
+                        r_dcache_pte_update = tlb_data;
+			r_dcache_ppn_update = tlb_data_ppn;
+                        r_dcache_fsm        = DCACHE_TLB2_UPDT_SEL;
+		    }
+		    else
+		    {
+                        r_dcache_pte_update = tlb_data | PTE_R_MASK;
+	        	r_dcache_ppn_update = tlb_data_ppn;
+                        r_dcache_tlb_ll_acc_req = true;
+                        r_dcache_fsm = DCACHE_TLB2_LL_WAIT;
+                        m_cpt_data_tlb_update_acc++;
+                        m_cost_data_tlb_update_acc_frz++;
+		    }
+		}
+	    }
+        }
+        else
+        {
+            // DTLB request miss in cache and walk page table level 2
+            r_dcache_tlb_read_req = true;
+            r_dcache_fsm = DCACHE_TLB2_READ;
+        }
+        break;
+    }
+    ///////////////////////
+    case DCACHE_TLB2_LL_WAIT:
+    {
+        if ( dreq.valid ) m_cost_data_tlb_miss_frz++;
+        m_cost_data_tlb_update_acc_frz++;
+
+        // external cache invalidate request
+        if ( r_tgt_dcache_req )   
+        {
+            r_dcache_fsm = DCACHE_CC_CHECK;
+            r_dcache_fsm_save = r_dcache_fsm;
+            break;
+        }
+
+	if (!r_dcache_tlb_ll_acc_req)
+	{
+            if ( r_vci_rsp_data_error ) // VCI response ko
+            {
+                if ((r_dcache_type_save == iss_t::DATA_READ)||(r_dcache_type_save == iss_t::DATA_LL))
+                {
+                    r_dcache_error_type = MMU_READ_PT2_ILLEGAL_ACCESS;
+                }
+                else /*if ((dreq.type == iss_t::DATA_WRITE)||(dreq.type == iss_t::DATA_SC))*/
+                {
+                    r_dcache_error_type = MMU_WRITE_PT2_ILLEGAL_ACCESS;
+                } 
+                r_dcache_bad_vaddr = dreq.addr;
+                r_dcache_fsm = DCACHE_ERROR; 
+
+		if (r_dcache_inval_tlb_rsp) r_dcache_inval_tlb_rsp = false;
+		if (r_dcache_inval_rsp) r_dcache_inval_rsp = false;
+            }
+	    else
+	    {
+	        if ( !(r_dcache_miss_buf[0] >> PTE_V_SHIFT) )	// unmapped
+	        {
+               	    if ((r_dcache_type_save == iss_t::DATA_READ)||(r_dcache_type_save == iss_t::DATA_LL))
+               	    {
+               	        r_dcache_error_type = MMU_READ_PT2_UNMAPPED;
+               	    }
+               	    else /*if ((dreq.type == iss_t::DATA_WRITE)||(dreq.type == iss_t::DATA_SC))*/
+               	    {
+               	        r_dcache_error_type = MMU_WRITE_PT2_UNMAPPED;
+               	    } 
+                    r_dcache_bad_vaddr = dreq.addr;
+                    r_dcache_fsm = DCACHE_ERROR;
+
+		    if (r_dcache_inval_tlb_rsp) r_dcache_inval_tlb_rsp = false;
+		    if (r_dcache_inval_rsp) r_dcache_inval_rsp = false;
+	        }
+        	else if ( r_dcache_inval_tlb_rsp )
+        	{
+        	    r_dcache_inval_tlb_rsp = false;
+        	    r_dcache_fsm = DCACHE_IDLE;
+        	}
+		else if ( r_dcache_inval_rsp )
+		{
+        	    r_dcache_inval_rsp = false;
+		    r_dcache_fsm = DCACHE_IDLE;
+		}
+		else
+		{
+		    r_dcache_tlb_sc_acc_req = true;
+		    r_dcache_pte_update = r_dcache_miss_buf[0] | r_dcache_pte_update.read();
+                    r_dcache_fsm = DCACHE_TLB2_SC_WAIT; 
+		}
+	    }
+	}
+	break;
+    }
+    ///////////////////////
+    case DCACHE_TLB2_SC_WAIT:
+    {
+        if ( dreq.valid ) m_cost_data_tlb_miss_frz++;
+        m_cost_data_tlb_update_acc_frz++;	    
+        // external cache invalidate request
+        if ( r_tgt_dcache_req )   
+        {
+            r_dcache_fsm = DCACHE_CC_CHECK;
+            r_dcache_fsm_save = r_dcache_fsm;
+            break;
+        }
+
+	if ( !r_dcache_tlb_sc_acc_req )
+	{
+	    if ( r_vci_rsp_data_error ) // VCI response ko
+	    {
+                if ((r_dcache_type_save == iss_t::DATA_READ)||(r_dcache_type_save == iss_t::DATA_LL))
+                {
+                    r_dcache_error_type = MMU_READ_PT2_ILLEGAL_ACCESS;
+                }
+                else /*if ((dreq.type == iss_t::DATA_WRITE)||(dreq.type == iss_t::DATA_SC))*/
+                {
+                    r_dcache_error_type = MMU_WRITE_PT2_ILLEGAL_ACCESS;
+                } 
+	        r_dcache_bad_vaddr = dreq.addr;
+	        r_dcache_fsm = DCACHE_ERROR; 
+
+		if (r_dcache_inval_tlb_rsp) r_dcache_inval_tlb_rsp = false;
+		if (r_dcache_inval_rsp) r_dcache_inval_rsp = false;	
+	    }
+	    else
+	    { 
+                // Using tlb entry is invalidated 
+                if ( r_dcache_inval_tlb_rsp )
+                {
+                    r_dcache_inval_tlb_rsp = false;
+		    if (r_dcache_tlb_sc_fail) r_dcache_tlb_sc_fail = false;
+                    r_dcache_fsm = DCACHE_IDLE;
+                }
+		else if ( r_dcache_inval_rsp )
+		{
+        	    r_dcache_inval_rsp = false;
+		    if (r_dcache_tlb_sc_fail) r_dcache_tlb_sc_fail = false;
+		    r_dcache_fsm = DCACHE_IDLE;
+		}
+	        else if ( r_dcache_tlb_sc_fail )
+	        {
+	            r_dcache_tlb_ll_acc_req = true;
+		    r_dcache_tlb_sc_fail = false;
+	            r_dcache_fsm = DCACHE_TLB2_LL_WAIT;
+		    m_cpt_data_tlb_update_acc++;
+	        }
+	        else 
+	        {
+		    bool write_hit = r_dcache.write(r_dcache_tlb_paddr,r_dcache_pte_update);  
+                    assert(write_hit && "Write on miss ignores data for data MMU update data access bit"); 
+	            r_dcache_fsm = DCACHE_TLB2_UPDT_SEL; 
+		    m_cpt_dcache_data_write++;
+	        }
+	    }
+	}
+	break;
+    }
+    /////////////////////
+    case DCACHE_TLB2_READ:
+    {
+        m_cost_data_tlb_miss_frz++;
+
+        // external cache invalidate request
+        if ( r_tgt_dcache_req )   
+        {
+            r_dcache_fsm = DCACHE_CC_CHECK;
+            r_dcache_fsm_save = r_dcache_fsm;
+            break;
+        }        
+
+	if ( !r_dcache_tlb_read_req )
+	{
+            if ( r_vci_rsp_data_error ) // VCI response ko
+            {
+                if ((r_dcache_type_save == iss_t::DATA_READ)||(r_dcache_type_save == iss_t::DATA_LL))
+                {
+                    r_dcache_error_type = MMU_READ_PT2_ILLEGAL_ACCESS;
+                }
+                else /*if ((dreq.type == iss_t::DATA_WRITE)||(dreq.type == iss_t::DATA_SC))*/
+                {
+                    r_dcache_error_type = MMU_WRITE_PT2_ILLEGAL_ACCESS;
+                } 
+                r_dcache_bad_vaddr = dreq.addr;
+                r_dcache_fsm = DCACHE_ERROR; 
+
+		if (r_dcache_inval_tlb_rsp) r_dcache_inval_tlb_rsp = false;
+		if (r_dcache_inval_rsp) r_dcache_inval_rsp = false;
+		break;
+            }	
+
+            if ( r_dcache_inval_tlb_rsp )  // TLB miss response and invalidation
+            {
+                r_dcache_fsm = DCACHE_IDLE; 
+                r_dcache_inval_tlb_rsp = false;
+		break;
+            }  
+
+	    if ( r_dcache_inval_rsp ) // TLB miss response and cache invalidation
+	    {
+	        if ( r_dcache_cleanup_req ) break;
+                r_dcache_cleanup_req = true;
+                r_dcache_cleanup_line = r_dcache_tlb_paddr.read() >> (uint32_log2(m_dcache_words) + 2);  
+		m_cpt_cc_cleanup_data++;
+                r_dcache_fsm = DCACHE_IDLE;
+                r_dcache_inval_rsp = false;
+                break;
+	    } 
+
+	    // TLB miss response and no invalidation
+	    r_dcache_fsm = DCACHE_TLB2_READ_UPDT;
+	}	
+        break;
+    }
+    //////////////////////////
+    case DCACHE_TLB2_READ_UPDT:
+    {
+        m_cost_data_tlb_miss_frz++;
+
+        // external cache invalidate request
+        if ( r_tgt_dcache_req )   
+        {
+            r_dcache_fsm = DCACHE_CC_CHECK;
+            r_dcache_fsm_save = r_dcache_fsm;
+            break;
+        }        
+
+        // Using tlb entry is invalidated 
+        if ( r_dcache_inval_tlb_rsp )
+        {
+            r_dcache_inval_tlb_rsp = false;
+            r_dcache_fsm = DCACHE_IDLE;
+            break;
+        }
+
+        if ( !r_dcache_cleanup_req )
+        {
+            // update cache
+            data_t rsp_dtlb_miss;
+            data_t tlb_data_ppn;
+            paddr_t  victim_index = 0;
+            size_t way = 0;
+            size_t set = 0;
+
+            // Using tlb entry is in the invalidated cache line  
+            if ( r_dcache_inval_rsp )
+            {
+                r_dcache_cleanup_req = true;
+                r_dcache_cleanup_line = r_dcache_tlb_paddr.read() >> (uint32_log2(m_dcache_words) + 2);  
+		m_cpt_cc_cleanup_data++;
+                r_dcache_fsm = DCACHE_IDLE;
+                r_dcache_inval_rsp = false;
+                break;
+            }
+
+            bool cleanup_req = r_dcache.find(r_dcache_tlb_paddr, r_dcache_in_itlb, r_dcache_in_dtlb, &way, &set, &victim_index);
+
+	    if ( cleanup_req )
+	    {	    
+		// ins tlb invalidate verification    
+                r_dcache_itlb_inval_req = r_dcache_in_itlb[m_dcache_sets*way+set];
+                r_dcache_itlb_inval_line = victim_index;
+                r_dcache_in_itlb[way*m_dcache_sets+set] = false;
+
+                // data tlb invalidate verification
+                r_dcache_dtlb_inval_req = r_dcache_in_dtlb[m_dcache_sets*way+set]; 
+                r_dcache_dtlb_inval_line = victim_index;
+                r_dcache_in_dtlb[way*m_dcache_sets+set] = false;
+
+                r_dcache_cleanup_req = true; 
+                r_dcache_cleanup_line = victim_index;
+		m_cpt_cc_cleanup_data++;
+		r_dcache_fsm = DCACHE_TLB_CC_INVAL;
+                r_dcache_fsm_save = r_dcache_fsm;
+		break;
+	    }
+
+	    r_dcache.update(r_dcache_tlb_paddr, way, set, r_dcache_miss_buf);
+	    r_dcache.read(r_dcache_tlb_paddr, &rsp_dtlb_miss);
+	    m_cpt_data_tlb_occup_cache++;
+
+	    bool tlb_hit_ppn = r_dcache.read(r_dcache_tlb_paddr.read()+4, &tlb_data_ppn);
+	    assert(tlb_hit_ppn && "Address of pte[64-32] and pte[31-0] should be successive");
+
+	    if ( !(rsp_dtlb_miss >> PTE_V_SHIFT) )	// unmapped
+	    {
+                if ((r_dcache_type_save == iss_t::DATA_READ)||(r_dcache_type_save == iss_t::DATA_LL))
+                {
+                    r_dcache_error_type = MMU_READ_PT2_UNMAPPED;
+                }
+                else /*if ((dreq.type == iss_t::DATA_WRITE)||(dreq.type == iss_t::DATA_SC))*/
+                {
+                    r_dcache_error_type = MMU_WRITE_PT2_UNMAPPED;
+                }  
+                r_dcache_bad_vaddr  = dreq.addr;
+                r_dcache_fsm        = DCACHE_ERROR;
+	    }
+	    else if ( (rsp_dtlb_miss & PTE_T_MASK) >> PTE_T_SHIFT ) // PTD
+	    {
+                r_dcache_pte_update = rsp_dtlb_miss;
+	        r_dcache_ppn_update = tlb_data_ppn;
+		r_dcache_fsm = DCACHE_TLB2_UPDT_SEL;
+	    }
+	    else
+	    {
+	        if ( (m_srcid_rw >> 4) == ((r_dcache_tlb_paddr.read() & ((1<<(m_paddr_nbits - PAGE_M_NBITS))-1)) >> (m_paddr_nbits - PAGE_M_NBITS -10)) ) // local
+		{
+		    if ( (rsp_dtlb_miss & PTE_L_MASK ) >> PTE_L_SHIFT ) // L bit is set
+		    {
+                        r_dcache_pte_update = rsp_dtlb_miss;
+			r_dcache_ppn_update = tlb_data_ppn;
+                        r_dcache_fsm        = DCACHE_TLB2_UPDT_SEL;
+		    }
+		    else
+		    {
+                        r_dcache_pte_update = rsp_dtlb_miss | PTE_L_MASK;
+	        	r_dcache_ppn_update = tlb_data_ppn;
+                        r_dcache_tlb_ll_acc_req = true;
+                        r_dcache_fsm = DCACHE_TLB2_LL_WAIT;
+                        m_cpt_data_tlb_update_acc++;
+                        m_cost_data_tlb_update_acc_frz++;
+		    }
+    	        }
+		else // remotely
+		{
+		    if ( (rsp_dtlb_miss & PTE_R_MASK ) >> PTE_R_SHIFT ) // R bit is set
+		    {
+                        r_dcache_pte_update = rsp_dtlb_miss;
+			r_dcache_ppn_update = tlb_data_ppn;
+                        r_dcache_fsm        = DCACHE_TLB2_UPDT_SEL;
+		    }
+		    else
+		    {
+                        r_dcache_pte_update = rsp_dtlb_miss | PTE_R_MASK;
+	        	r_dcache_ppn_update = tlb_data_ppn;
+                        r_dcache_tlb_ll_acc_req = true;
+                        r_dcache_fsm = DCACHE_TLB2_LL_WAIT;
+                        m_cpt_data_tlb_update_acc++;
+                        m_cost_data_tlb_update_acc_frz++;
+		    }
+		}
+	    }
+        }
+        break;
+    }
+    //////////////////////////
+    case DCACHE_TLB2_UPDT_SEL:  
+    {
+        m_cost_data_tlb_miss_frz++;
+        m_cost_data_tlb_update_acc_frz++;
+
+        // external cache invalidate request
+        if ( r_tgt_dcache_req )   
+        {
+            r_dcache_fsm = DCACHE_CC_CHECK;
+            r_dcache_fsm_save = r_dcache_fsm;
+            break;
+        }        
+
+        if ( !r_dcache_inval_tlb_rsp && !r_dcache_inval_rsp )
+        {
+	    size_t way = 0;
+	    size_t set = 0;
+            paddr_t victim_index = 0;
+	    bool cleanup = dcache_tlb.select((dreq.addr >> PAGE_K_NBITS),&victim_index,&way,&set);
+	    if (cleanup) 
+	    {
+	        r_dcache_dtlb_cleanup_req = true;
+		r_dcache_dtlb_cleanup_line = victim_index;
+		//m_cpt_cc_cleanup_data++;
+	    }
+	    r_dcache_way = way;
+	    r_dcache_set = set;
+            r_dcache_fsm = DCACHE_TLB2_UPDT;
+        }
+        else  
+        {
+            if ( r_dcache_inval_tlb_rsp ) r_dcache_inval_tlb_rsp = false;
+            if ( r_dcache_inval_rsp ) r_dcache_inval_rsp = false;
+            r_dcache_fsm = DCACHE_IDLE;
+        }
+        break;
+    }
+    //////////////////////
+    case DCACHE_TLB2_UPDT:  
+    {
+        m_cost_data_tlb_miss_frz++;
+        m_cost_data_tlb_update_acc_frz++;
+
+	if (r_dcache_dtlb_cleanup_req) r_dcache.setinbit(r_dcache_dtlb_cleanup_line.read() << (uint32_log2(m_dcache_words)+2), r_dcache_in_dtlb, false);
+        bool set_hit = r_dcache.setinbit(r_dcache_tlb_paddr, r_dcache_in_dtlb, true);
+        assert(set_hit && "TLB2_UPDT set hit error");  
+        dcache_tlb.update(r_dcache_pte_update,r_dcache_ppn_update,dreq.addr,r_dcache_way.read(),r_dcache_set.read(),(r_dcache_tlb_paddr.read() >> (uint32_log2(m_dcache_words)+2)));
+        r_dcache_fsm = DCACHE_IDLE;
+	break;
+    }
+    ///////////////////////
+    case DCACHE_CTXT_SWITCH:
+    {
+        // TLB flush leads to cleanup corresponding data cache line 
+        paddr_t victim_index = 0;
+        size_t way = 0;
+        size_t set = 0;
+
+        if ( r_dcache_itlb_cleanup_req )
+        {    
+            r_dcache.setinbit(((paddr_t)r_dcache_itlb_cleanup_line.read() << (uint32_log2(m_dcache_words)+2)), r_dcache_in_itlb, false);
+            r_dcache_itlb_cleanup_req = false;
+	}
+
+        for ( way = 0; way < m_dtlb_ways; way++)
+        {
+            for ( set = 0; set < m_dtlb_sets; set++)
+            {
+                if(dcache_tlb.checkcleanup(way, set, &victim_index))
+                {
+                    r_dcache.setinbit((paddr_t)(victim_index << (uint32_log2(m_dcache_words)+2)), r_dcache_in_dtlb, false); 
+                }
+            }
+        }
+
+        if ( !r_dcache_xtn_req )
+        {
+            r_dcache_fsm = DCACHE_IDLE;
+            r_dtlb_translation_valid = false;
+            r_dcache_ptba_ok = false;
+            drsp.valid = true;
+        }
+        break;
+    }
+    ////////////////////////
+    case DCACHE_ICACHE_FLUSH:
+    case DCACHE_ICACHE_INVAL:
+    case DCACHE_ICACHE_INVAL_PA:
+    case DCACHE_ITLB_INVAL:
+    {
+        // external cache invalidate request
+        if ( r_tgt_dcache_req )   
+        {
+            r_dcache_fsm = DCACHE_CC_CHECK;
+            r_dcache_fsm_save = r_dcache_fsm;
+            break;
+        }  
+        if ( !r_dcache_xtn_req ) 
+        {
+            r_dcache_fsm = DCACHE_IDLE;
+            drsp.valid = true;
+        }
+        break;
+    }
+    ////////////////////////
+    case DCACHE_DCACHE_FLUSH:
+    {
+        // external cache invalidate request
+        if ( r_tgt_dcache_req )   
+        {
+            r_dcache_fsm = DCACHE_CC_CHECK;
+            r_dcache_fsm_save = r_dcache_fsm;
+            break;
+        }  
+        size_t way = r_dcache_way;
+        size_t set = r_dcache_set;
+        bool clean = false;
+        
+        // cache flush and send cleanup to external
+        if ( !r_dcache_cleanup_req )
+        {
+            paddr_t victim_index = 0;
+            for ( ; way < m_dcache_ways; way++ )
+            {    
+                for ( ; set < m_dcache_sets; set++ )
+                {  
+                    if ( r_dcache.flush(way, set, &victim_index) )
+                    {
+                        clean = true;
+                        r_dcache_cleanup_req = true;
+                        r_dcache_cleanup_line = victim_index;
+			m_cpt_cc_cleanup_data++;
+                        r_dcache_way = way + ((set+1)/m_dcache_sets);
+                        r_dcache_set = (set+1) % m_dcache_sets;
+                        break;
+                    }
+                }
+                if (clean) break;
+		set = 0;
+            }
+
+            if ((way == m_dcache_ways) && !r_dcache_xtn_req ) 
+            {
+                // data TLB flush 
+                dcache_tlb.flush(true);      // global entries are invalidated
+            	r_dtlb_translation_valid = false;
+            	r_dcache_ptba_ok = false;
+
+                for (size_t line = 0; line < m_dcache_ways*m_dcache_sets; line++)
+                {
+                    r_dcache_in_itlb[line] = false;
+                    r_dcache_in_dtlb[line] = false;
+                }
+
+                r_dcache_fsm = DCACHE_IDLE;
+                drsp.valid = true;
+                break;
+            }
+        }
+	break;
+    }
+    //////////////////////
+    case DCACHE_DTLB_INVAL: 
+    {
+        paddr_t victim_index = 0;
+        // clean indicate data tlb bit
+        if ( dcache_tlb.inval(r_dcache_wdata_save, &victim_index) )
+        {  
+            r_dcache.setinbit((paddr_t)(victim_index << (uint32_log2(m_dcache_words)+2)), r_dcache_in_dtlb, false); 
+        }
+        r_dtlb_translation_valid = false;
+        r_dcache_ptba_ok = false;
+        r_dcache_fsm = DCACHE_IDLE;
+        drsp.valid = true;
+        break;
+    }
+    ////////////////////////
+    case DCACHE_DCACHE_INVAL:
+    {
+        // external cache invalidate request
+        if ( r_tgt_dcache_req )   
+        {
+            r_dcache_fsm = DCACHE_CC_CHECK;
+            r_dcache_fsm_save = r_dcache_fsm;
+            break;
+        }  
+
+        m_cpt_dcache_dir_read += m_dcache_ways;
+        vaddr_t invadr = dreq.wdata;
+        paddr_t dpaddr = 0;
+        bool dcache_hit_t = false; 
+        size_t way = 0;
+        size_t set = 0;
+
+	if ( !r_dcache_cleanup_req )
+	{
+            if ( r_mmu_mode.read() & DATA_TLB_MASK ) 
+            {
+                dcache_hit_t = dcache_tlb.translate(invadr, &dpaddr); 
+            } 
+            else 
+            {
+                dpaddr = invadr;  
+                dcache_hit_t = true;
+            }
+
+            if ( dcache_hit_t )
+            {
+		bool dcache_cleanup_req = r_dcache.inval(dpaddr, &way, &set);
+		r_dcache_cleanup_req = dcache_cleanup_req;
+		r_dcache_cleanup_line = dpaddr >> (uint32_log2(m_dcache_words)+2);
+		if (dcache_cleanup_req) m_cpt_cc_cleanup_data++;
+		
+		if ( r_dcache_in_itlb[way*m_dcache_sets+set] || r_dcache_in_dtlb[way*m_dcache_sets+set] ) 
+		{	
+		    // ins tlb invalidate verification
+		    r_dcache_itlb_inval_req = r_dcache_in_itlb[way*m_dcache_sets+set];
+		    r_dcache_itlb_inval_line = dpaddr >> (uint32_log2(m_dcache_words)+2);
+		    r_dcache_in_itlb[way*m_dcache_sets+set] = false;
+		
+		    // data tlb invalidate verification
+		    r_dcache_dtlb_inval_req = r_dcache_in_dtlb[way*m_dcache_sets+set];
+		    r_dcache_dtlb_inval_line = dpaddr >> (uint32_log2(m_dcache_words)+2);
+		    r_dcache_in_dtlb[way*m_dcache_sets+set] = false;
+		    r_dcache_fsm = DCACHE_TLB_CC_INVAL;
+		    r_dcache_fsm_save = r_dcache_fsm;
+		    break;
+		}
+            }
+            r_dcache_fsm = DCACHE_IDLE;
+            drsp.valid = true;
+	}
+        break;
+    }
+    ////////////////////////
+    case DCACHE_DCACHE_INVAL_PA:
+    {
+        // external cache invalidate request
+        if ( r_tgt_dcache_req )   
+        {
+            r_dcache_fsm = DCACHE_CC_CHECK;
+            r_dcache_fsm_save = r_dcache_fsm;
+            break;
+        }  
+        m_cpt_dcache_dir_read += m_dcache_ways;
+        paddr_t dpaddr = (paddr_t)r_mmu_word_hi.read() << 32 | r_mmu_word_lo.read();
+        size_t way = 0;
+        size_t set = 0;
+
+	if ( !r_dcache_cleanup_req )
+	{
+	    bool dcache_cleanup_req = r_dcache.inval(dpaddr, &way, &set);
+	    r_dcache_cleanup_req = dcache_cleanup_req;
+	    r_dcache_cleanup_line = dpaddr >> (uint32_log2(m_dcache_words)+2);
+	    if (dcache_cleanup_req) m_cpt_cc_cleanup_data++;
+	    
+	    if ( r_dcache_in_itlb[way*m_dcache_sets+set] || r_dcache_in_dtlb[way*m_dcache_sets+set] ) 
+	    {	
+	        // ins tlb invalidate verification
+	        r_dcache_itlb_inval_req = r_dcache_in_itlb[way*m_dcache_sets+set];
+	        r_dcache_itlb_inval_line = dpaddr >> (uint32_log2(m_dcache_words)+2);
+	        r_dcache_in_itlb[way*m_dcache_sets+set] = false;
+	    
+	        // data tlb invalidate verification
+	        r_dcache_dtlb_inval_req = r_dcache_in_dtlb[way*m_dcache_sets+set];
+	        r_dcache_dtlb_inval_line = dpaddr >> (uint32_log2(m_dcache_words)+2);
+	        r_dcache_in_dtlb[way*m_dcache_sets+set] = false;
+	        r_dcache_fsm = DCACHE_TLB_CC_INVAL;
+	        r_dcache_fsm_save = r_dcache_fsm;
+	        break;
+	    }
+            r_dcache_fsm = DCACHE_IDLE;
+            drsp.valid = true;
+	}
+        break;
+    }
+    /////////////////////////
+    case DCACHE_DCACHE_SYNC:
+    {
+        // external cache invalidate request
+        if ( r_tgt_dcache_req )   
+        {
+            r_dcache_fsm = DCACHE_CC_CHECK;
+            r_dcache_fsm_save = r_dcache_fsm;
+            break;
+        }  
+        if ( !r_dcache_write_req ) 
+        {
+            r_dcache_write_req = r_wbuf.rok();
+            drsp.valid = true;
+            r_dcache_fsm = DCACHE_IDLE;
+        }    
+        break;
+    }
+    /////////////////////
+    case DCACHE_MISS_WAIT:
+    {
+        m_cost_data_miss_frz++; 
+
+        // external cache invalidate request
+        if ( r_tgt_dcache_req ) 
+        {
+            r_dcache_fsm = DCACHE_CC_CHECK;
+            r_dcache_fsm_save = r_dcache_fsm;
+            break;
+        }
+
+	if ( !r_dcache_miss_req )
+	{
+            if ( r_vci_rsp_data_error ) 
+            {
+                r_dcache_error_type = MMU_READ_DATA_ILLEGAL_ACCESS; 
+                r_dcache_bad_vaddr = dreq.addr;
+                r_dcache_fsm = DCACHE_ERROR;
+
+		if (r_dcache_inval_tlb_rsp) r_dcache_inval_tlb_rsp = false;
+		if (r_dcache_inval_rsp) r_dcache_inval_rsp = false;
+		break;
+            } 
+
+            if ( r_dcache_inval_tlb_rsp ) // Miss read response and tlb invalidation
+            {
+                if ( r_dcache_cleanup_req ) break;
+                r_dcache_cleanup_req = true;
+                r_dcache_cleanup_line = r_dcache_paddr_save.read() >> (uint32_log2(m_dcache_words) + 2);  
+		m_cpt_cc_cleanup_data++;
+                r_dcache_fsm = DCACHE_IDLE;
+                r_dcache_inval_tlb_rsp = false;
+                if ( r_dcache_inval_rsp ) r_dcache_inval_rsp = false;
+                break;
+            }	
+
+	    if ( r_dcache_inval_rsp ) // TLB miss response and cache invalidation
+	    {
+                if ( r_dcache_cleanup_req ) break;
+                r_dcache_cleanup_req = true;
+                r_dcache_cleanup_line = r_dcache_paddr_save.read() >> (uint32_log2(m_dcache_words) + 2);  
+		m_cpt_cc_cleanup_data++;
+                r_dcache_fsm = DCACHE_IDLE;
+                r_dcache_inval_rsp = false;
+                break;
+	    }
+	    // Miss read response and no tlb invalidation
+	    r_dcache_fsm = DCACHE_MISS_UPDT;
+	}	
+        break;
+    }
+    /////////////////////
+    case DCACHE_MISS_UPDT:
+    {
+        m_cost_data_miss_frz++;
+
+        // external cache invalidate request
+        if ( r_tgt_dcache_req ) 
+        {
+            r_dcache_fsm = DCACHE_CC_CHECK;
+            r_dcache_fsm_save = r_dcache_fsm;
+            break;
+        }
+
+        if ( r_dcache_inval_tlb_rsp ) // tlb invalidation
+        {
+            if ( r_dcache_cleanup_req ) break;
+            r_dcache_cleanup_req = true;
+            r_dcache_cleanup_line = r_dcache_paddr_save.read() >> (uint32_log2(m_dcache_words) + 2);  
+	    m_cpt_cc_cleanup_data++;
+            r_dcache_inval_tlb_rsp = false;
+            r_dcache_inval_rsp = false;
+            r_dcache_fsm = DCACHE_IDLE;
+            break;
+        }
+
+        if (!r_dcache_cleanup_req ) // Miss update and no invalidation
+        {
+            paddr_t  victim_index = 0;
+            size_t way = 0;
+            size_t set = 0;
+
+            // Using tlb entry is in the invalidated cache line  
+            if ( r_dcache_inval_rsp )
+            {
+                r_dcache_cleanup_req = true;
+                r_dcache_cleanup_line = r_dcache_paddr_save.read() >> (uint32_log2(m_dcache_words) + 2);  
+		m_cpt_cc_cleanup_data++;
+                r_dcache_fsm = DCACHE_IDLE;
+                r_dcache_inval_rsp = false;
+                break;
+            }
+
+            bool cleanup_req = r_dcache.find(r_dcache_paddr_save.read(), r_dcache_in_itlb, r_dcache_in_dtlb, &way, &set, &victim_index);
+
+	    if ( cleanup_req )
+	    {	    
+		// ins tlb invalidate verification    
+                r_dcache_itlb_inval_req = r_dcache_in_itlb[m_dcache_sets*way+set];
+                r_dcache_itlb_inval_line = victim_index;
+
+                // data tlb invalidate verification
+                r_dcache_dtlb_inval_req = r_dcache_in_dtlb[m_dcache_sets*way+set]; 
+                r_dcache_dtlb_inval_line = victim_index;
+
+                r_dcache_cleanup_req = true; 
+                r_dcache_cleanup_line = victim_index;
+		m_cpt_cc_cleanup_data++;
+
+		if ( r_dcache_in_itlb[m_dcache_sets*way+set] || r_dcache_in_dtlb[m_dcache_sets*way+set] )
+		{
+		    r_dcache_fsm = DCACHE_TLB_CC_INVAL;
+                    r_dcache_fsm_save = r_dcache_fsm;
+                    r_dcache_in_itlb[way*m_dcache_sets+set] = false;
+                    r_dcache_in_dtlb[way*m_dcache_sets+set] = false;
+		    break;
+		}
+	    }
+	    m_cpt_dcache_dir_write++;
+	    m_cpt_dcache_data_write++;
+	    r_dcache.update(r_dcache_paddr_save.read(), way, set, r_dcache_miss_buf);
+            r_dcache_fsm = DCACHE_IDLE;
+        }
+	break;
+    }
+    //////////////////////
+    case DCACHE_UNC_WAIT:
+    {
+        m_cost_unc_read_frz++;
+
+        // external cache invalidate request
+        if ( r_tgt_dcache_req ) 
+        {
+            r_dcache_fsm = DCACHE_CC_CHECK;
+            r_dcache_fsm_save = r_dcache_fsm;
+            break;
+        }
+
+	if ( !r_dcache_unc_req )
+	{
+            if ( r_vci_rsp_data_error ) 
+            {
+                r_dcache_error_type = MMU_READ_DATA_ILLEGAL_ACCESS; 
+                r_dcache_bad_vaddr = dreq.addr;
+                r_dcache_fsm = DCACHE_ERROR;
+
+		if (r_dcache_inval_tlb_rsp) r_dcache_inval_tlb_rsp = false;
+		break;
+            }
+
+            if ( r_dcache_inval_tlb_rsp ) // Miss read response and tlb invalidation
+            {
+                r_dcache_inval_tlb_rsp = false;
+            }
+
+	    drsp.valid = true;
+	    drsp.rdata = r_dcache_miss_buf[0];
+	    r_dcache_fsm = DCACHE_IDLE;
+	}	
+        break;
+    }
+    ///////////////////////
+    case DCACHE_WRITE_UPDT:
+    {
+        m_cost_write_frz++;
+	m_cpt_dcache_data_write++; 
+        size_t way = 0;
+        size_t set = 0;
+	bool write_hit = false;
+        data_t mask = vci_param::be2mask(r_dcache_be_save.read());
+        data_t wdata = (mask & r_dcache_wdata_save) | (~mask & r_dcache_rdata_save);
+        write_hit = r_dcache.write(r_dcache_paddr_save, wdata, &way, &set);
+        assert(write_hit && "Write on miss ignores data");
+        
+        if (r_dcache_in_itlb[way*m_dcache_sets+set] || r_dcache_in_dtlb[m_dcache_sets*way+set])
+        {
+	    // ins tlb invalidate verification    
+            r_dcache_itlb_inval_req = r_dcache_in_itlb[m_dcache_sets*way+set];
+            r_dcache_itlb_inval_line = (r_dcache.get_tag(way, set) * m_dcache_sets) + set;
+            r_dcache_in_itlb[way*m_dcache_sets+set] = false;
+
+            // data tlb invalidate verification
+            r_dcache_dtlb_inval_req = r_dcache_in_dtlb[m_dcache_sets*way+set]; 
+            r_dcache_dtlb_inval_line = (r_dcache.get_tag(way, set) * m_dcache_sets) + set;
+            r_dcache_in_dtlb[way*m_dcache_sets+set] = false;
+
+	    r_dcache_fsm = DCACHE_TLB_CC_INVAL;
+            r_dcache_fsm_save = r_dcache_fsm;
+            break;
+	}
+
+        if ( !r_dcache_dirty_save && (r_mmu_mode.read() & DATA_TLB_MASK) )   
+        {
+            m_cpt_data_tlb_update_dirty++;
+            m_cost_data_tlb_update_dirty_frz++;	
+            if ( dcache_tlb.getpagesize(r_dcache_tlb_way_save, r_dcache_tlb_set_save) )	// 2M page size, one level page table 
+            {		    
+                r_dcache_pte_update = dcache_tlb.getpte(r_dcache_tlb_way_save, r_dcache_tlb_set_save) | PTE_D_MASK;
+                r_dcache_tlb_paddr = (paddr_t)r_mmu_ptpr << (INDEX1_NBITS+2) | (paddr_t)((dreq.addr>>PAGE_M_NBITS)<<2);
+                r_dcache_tlb_ll_dirty_req = true;
+                r_dcache_fsm = DCACHE_LL_DIRTY_WAIT;          
+            }
+            else
+            {   
+                if (r_dcache_hit_p_save) 
+                {
+                    r_dcache_pte_update = dcache_tlb.getpte(r_dcache_tlb_way_save, r_dcache_tlb_set_save) | PTE_D_MASK;
+                    r_dcache_tlb_paddr = (paddr_t)r_dcache_ptba_save|(paddr_t)(((dreq.addr&PTD_ID2_MASK)>>PAGE_K_NBITS) << 3);
+                    r_dcache_tlb_ll_dirty_req = true;
+                    r_dcache_fsm = DCACHE_LL_DIRTY_WAIT;
+                }
+                else
+                {
+                    r_dcache_pte_update = dcache_tlb.getpte(r_dcache_tlb_way_save, r_dcache_tlb_set_save) | PTE_D_MASK;
+		    data_t ptba;
+            	    if (r_dcache.read((paddr_t)r_mmu_ptpr << (INDEX1_NBITS+2) | (paddr_t)((dreq.addr>>PAGE_M_NBITS)<<2), &ptba))
+		    {
+                        r_dcache_tlb_paddr = (paddr_t)(ptba & ((1<<(m_paddr_nbits - PAGE_K_NBITS))-1)) << PAGE_K_NBITS | (paddr_t)(((dreq.addr & PTD_ID2_MASK) >> PAGE_K_NBITS) << 3);
+                    	r_dcache_tlb_ll_dirty_req = true;
+                    	r_dcache_fsm = DCACHE_LL_DIRTY_WAIT;
+		        
+		    }
+		    else
+		    {
+                        r_dcache_tlb_paddr = (paddr_t)r_mmu_ptpr << (INDEX1_NBITS+2) | (paddr_t)((dreq.addr>>PAGE_M_NBITS)<<2);
+                        r_dcache_tlb_ptba_read = true;
+                        r_dcache_fsm = DCACHE_DTLB1_READ_CACHE;
+		    }
+                }
+            }
+        }
+        else
+        {
+            r_dcache_fsm = DCACHE_WRITE_REQ;
+            drsp.valid = true;
+            drsp.rdata = 0;
+        }
+        break;
+    }
+    ////////////////////////
+    case DCACHE_WRITE_DIRTY:
+    {
+	m_cost_data_tlb_update_dirty_frz++;
+
+        // external cache invalidate request
+        if ( r_tgt_dcache_req ) 
+        {
+            r_dcache_fsm = DCACHE_CC_CHECK;
+            r_dcache_fsm_save = r_dcache_fsm;
+            break;
+        }
+
+        if ( r_dcache_inval_tlb_rsp ) // Miss read response and tlb invalidation
+        {
+            r_dcache_fsm = DCACHE_IDLE;
+	    if ( r_dcache_sc_updt_dirty ) r_dcache_sc_updt_dirty = false;
+            r_dcache_inval_tlb_rsp = false;
+	    break;
+        }
+
+	if ( r_dcache_inval_rsp ) // TLB miss response and cache invalidation
+	{
+            r_dcache_fsm = DCACHE_IDLE; 
+	    if ( r_dcache_sc_updt_dirty ) r_dcache_sc_updt_dirty = false;
+            r_dcache_inval_rsp = false;
+	    break;	    
+	}
+
+        dcache_tlb.setdirty(r_dcache_tlb_way_save, r_dcache_tlb_set_save);
+	if (  r_dcache_sc_updt_dirty )
+	{
+	    r_dcache_sc_updt_dirty = false;
+            r_dcache_unc_req = true;
+            r_dcache_fsm = DCACHE_UNC_WAIT;
+            m_cpt_unc_read++;
+	}
+	else
+	{
+            r_dcache_fsm = DCACHE_WRITE_REQ;
+            drsp.valid = true;
+            drsp.rdata = 0;	
+	}	
+        break;
+    }
+    /////////////////
+    case DCACHE_ERROR:
+    {
+        r_vci_rsp_data_error = false;
+        drsp.valid = true;
+        drsp.error = true;
+        drsp.rdata = 0;
+        r_dcache_fsm = DCACHE_IDLE;
+        break;
+    }   
+    ////////////////////// 
+    case DCACHE_ITLB_READ:
+    {
+       if ( dreq.valid ) m_cost_ins_tlb_occup_cache_frz++;
+
+        // external cache invalidate request
+        if ( r_tgt_dcache_req ) 
+        {
+            r_dcache_fsm = DCACHE_CC_CHECK;
+            r_dcache_fsm_save = r_dcache_fsm;
+            break;
+        }
+
+    	if ( !r_dcache_itlb_read_req ) // vci response ok
+        {  
+            if ( r_vci_rsp_data_error )
+            {
+                r_dcache_rsp_itlb_error = true;	
+                r_itlb_read_dcache_req = false;
+                r_vci_rsp_data_error = false;
+                r_dcache_fsm = DCACHE_IDLE;
+
+		if (r_dcache_inval_rsp) r_dcache_inval_rsp = false;
+            }
+	    else if ( r_dcache_inval_rsp ) // TLB miss response and cache invalidation
+	    {
+	        if ( r_dcache_cleanup_req ) break;
+                r_dcache_cleanup_req = true;
+                r_dcache_cleanup_line = r_icache_paddr_save.read() >> (uint32_log2(m_dcache_words) + 2);  
+		m_cpt_cc_cleanup_data++;
+                r_dcache_fsm = DCACHE_IDLE;
+                r_dcache_inval_rsp = false;
+                r_itlb_read_dcache_req = false;
+	        r_itlb_acc_redo_req = true;
+	    }
+	    else
+	    {
+                r_dcache_fsm = DCACHE_ITLB_UPDT;
+	    }
+        }
+	break;    	
+    }
+    //////////////////////
+    case DCACHE_ITLB_UPDT:
+    {
+        if ( dreq.valid ) m_cost_ins_tlb_occup_cache_frz++;  
+
+        // external cache invalidate request
+        if ( r_tgt_dcache_req ) 
+        {
+            r_dcache_fsm = DCACHE_CC_CHECK;
+            r_dcache_fsm_save = r_dcache_fsm;
+            break;
+        }
+
+        if ( !r_dcache_cleanup_req )
+        {
+            data_t rsp_itlb_miss = 0;
+	    data_t rsp_itlb_ppn = 0;
+
+            paddr_t  victim_index = 0;
+            size_t way = 0;
+            size_t set = 0;
+
+	    if ( r_dcache_inval_rsp ) // TLB miss response and cache invalidation
+	    {
+                r_dcache_cleanup_req = true;
+                r_dcache_cleanup_line = r_icache_paddr_save.read() >> (uint32_log2(m_dcache_words) + 2);  
+		m_cpt_cc_cleanup_data++;
+                r_dcache_fsm = DCACHE_IDLE;
+                r_dcache_inval_rsp = false;
+                r_itlb_read_dcache_req = false;
+	        r_itlb_acc_redo_req = true;
+                break;
+	    }           
+ 
+            bool cleanup = r_dcache.find(r_icache_paddr_save, r_dcache_in_itlb, r_dcache_in_dtlb, &way, &set, &victim_index);
+
+	    if ( cleanup )
+	    {	    
+		// ins tlb invalidate verification    
+                r_dcache_itlb_inval_req = r_dcache_in_itlb[m_dcache_sets*way+set];
+                r_dcache_itlb_inval_line = victim_index;
+
+                // data tlb invalidate verification
+                r_dcache_dtlb_inval_req = r_dcache_in_dtlb[m_dcache_sets*way+set]; 
+                r_dcache_dtlb_inval_line = victim_index;
+
+                r_dcache_cleanup_req = true; 
+                r_dcache_cleanup_line = victim_index;
+		m_cpt_cc_cleanup_data++;
+		if ( r_dcache_in_itlb[m_dcache_sets*way+set] || r_dcache_in_dtlb[m_dcache_sets*way+set] )
+		{
+		    r_dcache_fsm = DCACHE_TLB_CC_INVAL;
+                    r_dcache_fsm_save = r_dcache_fsm;
+                    r_dcache_in_itlb[way*m_dcache_sets+set] = false;
+                    r_dcache_in_dtlb[way*m_dcache_sets+set] = false;
+		    break;
+		}
+	    }
+
+            r_dcache.update(r_icache_paddr_save, way, set, r_dcache_miss_buf);
+
+            bool set_hit = r_dcache.setinbit(r_icache_paddr_save, r_dcache_in_itlb, true);
+            assert(set_hit && "ITLB_UPDT set hit error");  
+            bool itlb_hit_dcache = r_dcache.read(r_icache_paddr_save, &rsp_itlb_miss);	
+            m_cpt_ins_tlb_occup_cache++; 
+
+	    if ( r_itlb_k_read_dcache && itlb_hit_dcache )
+	    {	
+		r_itlb_k_read_dcache = false;
+            	bool itlb_hit_ppn = r_dcache.read(r_icache_paddr_save.read()+4, &rsp_itlb_ppn);
+		assert(itlb_hit_ppn && "Address of pte[64-32] and pte[31-0] should be successive");
+	    }
+
+            r_dcache_rsp_itlb_miss = rsp_itlb_miss;
+            r_dcache_rsp_itlb_ppn = rsp_itlb_ppn;
+            r_dcache_rsp_itlb_error = false;	
+            r_itlb_read_dcache_req = false;
+            r_dcache_fsm = DCACHE_IDLE;
+        }
+        break;
+    }
+    //////////////////////////
+    case DCACHE_ITLB_LL_WAIT:
+    {
+        if ( dreq.valid ) m_cost_ins_tlb_occup_cache_frz++;	    
+        // external cache invalidate request
+        if ( r_tgt_dcache_req )   
+        {
+            r_dcache_fsm = DCACHE_CC_CHECK;
+            r_dcache_fsm_save = r_dcache_fsm;
+            break;
+        }
+
+	if (!r_dcache_itlb_ll_acc_req)
+	{
+            if ( r_vci_rsp_data_error ) // VCI response ko
+            {
+                r_dcache_rsp_itlb_error = true;  
+                r_vci_rsp_data_error = false;
+                r_itlb_acc_dcache_req = false;
+		r_dcache_fsm = DCACHE_IDLE;
+		if (r_dcache_inval_rsp) r_dcache_inval_rsp = false;	
+            }
+	    else
+	    {
+	        if ( !(r_dcache_miss_buf[0] >> PTE_V_SHIFT) )	// unmapped
+	        {
+                    r_dcache_rsp_itlb_error = true;  
+                    r_itlb_acc_dcache_req = false;
+		    r_dcache_fsm = DCACHE_IDLE;	
+		    if (r_dcache_inval_rsp) r_dcache_inval_rsp = false;	
+	        }
+       		else if ( r_dcache_inval_rsp )
+       		{
+       		    r_dcache_inval_rsp = false;
+       		    r_dcache_fsm = DCACHE_IDLE;
+       		}
+		else
+		{
+		    r_dcache_itlb_sc_acc_req = true;
+		    r_icache_pte_update = r_dcache_miss_buf[0] | r_icache_pte_update.read();	
+                    r_dcache_fsm = DCACHE_ITLB_SC_WAIT; 
+		}
+	    }
+	}
+	break;
+    }
+    //////////////////////////
+    case DCACHE_ITLB_SC_WAIT:
+    {
+        if ( dreq.valid ) m_cost_ins_tlb_occup_cache_frz++; 	    
+        // external cache invalidate request
+        if ( r_tgt_dcache_req )   
+        {
+            r_dcache_fsm = DCACHE_CC_CHECK;
+            r_dcache_fsm_save = r_dcache_fsm;
+            break;
+        }
+	
+        if ( !r_dcache_itlb_sc_acc_req ) 
+	{
+	    if ( r_vci_rsp_data_error ) // VCI response ko
+	    {
+	        r_dcache_rsp_itlb_error = true;  
+	        r_vci_rsp_data_error = false;
+	        r_itlb_acc_dcache_req = false;
+	        r_dcache_fsm = DCACHE_IDLE;
+		if (r_dcache_inval_rsp) r_dcache_inval_rsp = false;		
+	    }
+	    else
+	    {
+	        if ( r_dcache_inval_rsp )
+	        {
+	            r_itlb_acc_dcache_req = false;
+	            r_itlb_acc_redo_req = true;
+	            r_dcache_inval_rsp = false;
+	            r_dcache_fsm = DCACHE_IDLE;
+		    if (r_dcache_tlb_sc_fail) r_dcache_tlb_sc_fail = false;
+	        }
+	        else if ( r_dcache_tlb_sc_fail )
+	        {
+		    r_dcache_tlb_sc_fail = false;
+		    r_dcache_itlb_ll_acc_req = true;
+	            r_dcache_fsm = DCACHE_ITLB_LL_WAIT; 
+	        }
+	        else 
+	        {
+		    bool write_hit = r_dcache.write(r_icache_paddr_save, r_icache_pte_update);
+                    assert(write_hit && "Write on miss ignores data for data MMU update ins access bit");
+	            r_itlb_acc_dcache_req = false;
+	            r_dcache_fsm = DCACHE_IDLE; 
+	        }
+	    }
+	}
+	break;
+    }
+    /////////////////////
+    case DCACHE_CC_CHECK:   // read directory in case of invalidate or update request
+    {
+        m_cpt_dcache_dir_read += m_dcache_ways;
+        m_cpt_dcache_data_read += m_dcache_ways;
+
+        /* activity counter */
+        if ( (( r_dcache_fsm_save == DCACHE_BIS ) ||( r_dcache_fsm_save == DCACHE_MISS_WAIT ) || ( r_dcache_fsm_save == DCACHE_MISS_UPDT ) ) && ( dreq.valid ) )        
+        {
+            m_cost_data_miss_frz++;
+        }
+        if( (( r_dcache_fsm_save == DCACHE_DTLB1_READ_CACHE ) || ( r_dcache_fsm_save == DCACHE_DTLB2_READ_CACHE ) ||
+             ( r_dcache_fsm_save == DCACHE_TLB1_READ )        || ( r_dcache_fsm_save == DCACHE_TLB2_READ )        ||
+             ( r_dcache_fsm_save == DCACHE_TLB1_LL_WAIT )     || ( r_dcache_fsm_save == DCACHE_TLB2_LL_WAIT )     ||
+             ( r_dcache_fsm_save == DCACHE_TLB1_SC_WAIT )     || ( r_dcache_fsm_save == DCACHE_TLB2_SC_WAIT )     || 
+             ( r_dcache_fsm_save == DCACHE_TLB1_READ_UPDT )   || ( r_dcache_fsm_save == DCACHE_TLB2_READ_UPDT )   ||
+             ( r_dcache_fsm_save == DCACHE_TLB1_UPDT_SEL )    || ( r_dcache_fsm_save == DCACHE_TLB2_UPDT_SEL )) && (dreq.valid) )
+        {
+            m_cost_data_tlb_miss_frz++;
+        }
+
+        if ( ( r_dcache_fsm_save == DCACHE_ITLB_READ ) ||( r_dcache_fsm_save == DCACHE_ITLB_UPDT ) || ( r_dcache_fsm_save == DCACHE_ITLB_LL_WAIT ) || ( r_dcache_fsm_save == DCACHE_ITLB_SC_WAIT ) )        
+        {
+            m_cost_ins_tlb_occup_cache_frz++;
+        }
+
+	// DCACHE_TLB1_LL_WAIT  DCACHE_TLB1_SC_WAIT  DCACHE_LL_DIRTY_WAIT  DCACHE_WRITE_DIRTY DCACHE_ITLB_LL_WAIT  DCACHE_ITLB_SC_WAIT
+	// DCACHE_TLB2_LL_WAIT  DCACHE_TLB2_SC_WAIT  DCACHE_SC_DIRTY_WAIT
+        if((( /*( r_dcache_fsm_save == DCACHE_UNC_WAIT ) ||*/
+	     ( r_dcache_fsm_save == DCACHE_MISS_WAIT ) || ( r_dcache_fsm_save == DCACHE_MISS_UPDT ) ) && 
+           ( (r_dcache_paddr_save.read() & ~((m_dcache_words<<2)-1)) == (r_tgt_addr.read() & ~((m_dcache_words<<2)-1)))) 
+        || (( ( r_dcache_fsm_save == DCACHE_TLB1_READ )      || ( r_dcache_fsm_save == DCACHE_TLB2_READ )      ||
+	     ( r_dcache_fsm_save == DCACHE_TLB1_READ_UPDT ) || ( r_dcache_fsm_save == DCACHE_TLB2_READ_UPDT ) ) && 
+           ( (r_dcache_tlb_paddr.read() & ~((m_dcache_words<<2)-1)) == (r_tgt_addr.read() & ~((m_dcache_words<<2)-1))) ) 
+        || (( ( r_dcache_fsm_save == DCACHE_ITLB_READ ) ) && 
+           ( (r_icache_paddr_save.read() & ~((m_dcache_words<<2)-1)) == (r_tgt_addr.read() & ~((m_dcache_words<<2)-1))) ) ) 
+        {
+            r_dcache_inval_rsp = true;
+            r_tgt_dcache_req = false;
+            if ( r_tgt_update )
+	    {    // Also send a cleanup and answer
+                r_tgt_dcache_rsp = true;
+            } 
+	    else 
+	    {            // Also send a cleanup but don't answer
+                r_tgt_dcache_rsp = false;
+            }
+            r_dcache_fsm = r_dcache_fsm_save;
+        }
+	else
+	{
+            data_t dcache_rdata = 0;
+            size_t way = 0;
+            size_t set = 0;
+
+            bool dcache_hit = r_dcache.read(r_tgt_addr.read(), &dcache_rdata, &way, &set);
+
+            if ( dcache_hit )
+            {
+		if (((( r_dcache_fsm_save == DCACHE_TLB1_UPDT_SEL ) || ( r_dcache_fsm_save == DCACHE_TLB2_UPDT_SEL ) ||
+		      ( r_dcache_fsm_save == DCACHE_TLB1_LL_WAIT )  || ( r_dcache_fsm_save == DCACHE_TLB2_LL_WAIT )  ||
+	              ( r_dcache_fsm_save == DCACHE_TLB1_SC_WAIT )  || ( r_dcache_fsm_save == DCACHE_TLB2_SC_WAIT )  ||
+	              ( r_dcache_fsm_save == DCACHE_LL_DIRTY_WAIT ) || ( r_dcache_fsm_save == DCACHE_SC_DIRTY_WAIT ) ||
+		      ( r_dcache_fsm_save == DCACHE_WRITE_DIRTY )) &&
+	            ((r_dcache_tlb_paddr.read() & ~((m_dcache_words<<2)-1)) == (r_tgt_addr.read() & ~((m_dcache_words<<2)-1)) )) ||
+		    ((( r_dcache_fsm_save == DCACHE_ITLB_UPDT )    ||
+                      ( r_dcache_fsm_save == DCACHE_ITLB_LL_WAIT ) || ( r_dcache_fsm_save == DCACHE_ITLB_SC_WAIT ) ) && 
+                    ((r_icache_paddr_save.read() & ~((m_dcache_words<<2)-1)) == (r_tgt_addr.read() & ~((m_dcache_words<<2)-1)))))
+		{
+		    r_dcache_inval_rsp = true;
+		}
+
+                if ( r_dcache_in_dtlb[m_dcache_sets*way+set] || r_dcache_in_itlb[m_dcache_sets*way+set] )
+                {
+            	    // ins tlb invalidate verification    
+                    r_dcache_itlb_inval_req = r_dcache_in_itlb[m_dcache_sets*way+set];
+                    r_dcache_itlb_inval_line = r_tgt_addr.read() >> (uint32_log2(m_dcache_words)+2);
+                    r_dcache_in_itlb[way*m_dcache_sets+set] = false;
+
+                    // data tlb invalidate verification
+                    r_dcache_dtlb_inval_req = r_dcache_in_dtlb[m_dcache_sets*way+set]; 
+                    r_dcache_dtlb_inval_line = r_tgt_addr.read() >> (uint32_log2(m_dcache_words)+2);
+                    r_dcache_in_dtlb[way*m_dcache_sets+set] = false;
+            	
+            	    r_dcache_cc_check = true;
+            	    r_dcache_fsm = DCACHE_TLB_CC_INVAL;
+            	    break;
+                }
+
+                if ( r_tgt_update ) // update 
+                {
+                    r_dcache_fsm = DCACHE_CC_UPDT;
+                } 
+                else                // invalidate 
+                {
+                    r_dcache_fsm = DCACHE_CC_INVAL;
+                }
+            }
+            else                    // nothing
+            {
+                r_dcache_fsm = DCACHE_CC_NOP;
+            }
+	}
+        break;
+    }
+    ///////////////////
+    case DCACHE_CC_UPDT:    // update directory and data cache        
+    {
+        /* activity counter */
+        if ( (( r_dcache_fsm_save == DCACHE_BIS ) ||( r_dcache_fsm_save == DCACHE_MISS_WAIT ) || ( r_dcache_fsm_save == DCACHE_MISS_UPDT ) ) && ( dreq.valid ) )        
+        {
+            m_cost_data_miss_frz++;
+        }
+        if( (( r_dcache_fsm_save == DCACHE_DTLB1_READ_CACHE ) || ( r_dcache_fsm_save == DCACHE_DTLB2_READ_CACHE ) ||
+             ( r_dcache_fsm_save == DCACHE_TLB1_READ )        || ( r_dcache_fsm_save == DCACHE_TLB2_READ )        ||
+             ( r_dcache_fsm_save == DCACHE_TLB1_LL_WAIT )     || ( r_dcache_fsm_save == DCACHE_TLB2_LL_WAIT )     ||
+             ( r_dcache_fsm_save == DCACHE_TLB1_SC_WAIT )     || ( r_dcache_fsm_save == DCACHE_TLB2_SC_WAIT )     || 
+             ( r_dcache_fsm_save == DCACHE_TLB1_READ_UPDT )   || ( r_dcache_fsm_save == DCACHE_TLB2_READ_UPDT )   ||
+             ( r_dcache_fsm_save == DCACHE_TLB1_UPDT_SEL )    || ( r_dcache_fsm_save == DCACHE_TLB2_UPDT_SEL )) && (dreq.valid) )
+        {
+            m_cost_data_tlb_miss_frz++;
+        }
+
+        if ( ( r_dcache_fsm_save == DCACHE_ITLB_READ ) ||( r_dcache_fsm_save == DCACHE_ITLB_UPDT ) || ( r_dcache_fsm_save == DCACHE_ITLB_LL_WAIT ) || ( r_dcache_fsm_save == DCACHE_ITLB_SC_WAIT ) )        
+        {
+            m_cost_ins_tlb_occup_cache_frz++;
+        }
+
+        m_cpt_dcache_dir_write++;
+        m_cpt_dcache_data_write++;
+        data_t* buf = r_tgt_buf;
+        for( size_t i = 0; i < m_dcache_words; i++ )
+        {
+            if( r_tgt_val[i] ) r_dcache.write( r_tgt_addr.read() + i*4, buf[i] );
+        }
+           
+        r_tgt_dcache_req = false;
+	r_tgt_dcache_rsp = true;
+        r_dcache_fsm = r_dcache_fsm_save;
+        break;
+    }
+    /////////////////////
+    case DCACHE_CC_INVAL:   // invalidate a cache line
+    {
+        /* activity counter */
+        if ( (( r_dcache_fsm_save == DCACHE_BIS ) ||( r_dcache_fsm_save == DCACHE_MISS_WAIT ) || ( r_dcache_fsm_save == DCACHE_MISS_UPDT ) ) && ( dreq.valid ) )        
+        {
+            m_cost_data_miss_frz++;
+        }
+        if( (( r_dcache_fsm_save == DCACHE_DTLB1_READ_CACHE ) || ( r_dcache_fsm_save == DCACHE_DTLB2_READ_CACHE ) ||
+             ( r_dcache_fsm_save == DCACHE_TLB1_READ )        || ( r_dcache_fsm_save == DCACHE_TLB2_READ )        ||
+             ( r_dcache_fsm_save == DCACHE_TLB1_LL_WAIT )     || ( r_dcache_fsm_save == DCACHE_TLB2_LL_WAIT )     ||
+             ( r_dcache_fsm_save == DCACHE_TLB1_SC_WAIT )     || ( r_dcache_fsm_save == DCACHE_TLB2_SC_WAIT )     || 
+             ( r_dcache_fsm_save == DCACHE_TLB1_READ_UPDT )   || ( r_dcache_fsm_save == DCACHE_TLB2_READ_UPDT )   ||
+             ( r_dcache_fsm_save == DCACHE_TLB1_UPDT_SEL )    || ( r_dcache_fsm_save == DCACHE_TLB2_UPDT_SEL )) && (dreq.valid) )
+        {
+            m_cost_data_tlb_miss_frz++;
+        }
+        if ( ( r_dcache_fsm_save == DCACHE_ITLB_READ ) ||( r_dcache_fsm_save == DCACHE_ITLB_UPDT ) || ( r_dcache_fsm_save == DCACHE_ITLB_LL_WAIT ) || ( r_dcache_fsm_save == DCACHE_ITLB_SC_WAIT ) )        
+        {
+            m_cost_ins_tlb_occup_cache_frz++;
+        }
+
+        r_tgt_dcache_rsp = r_dcache.inval(r_tgt_addr.read());
+        r_tgt_dcache_req = false;
+        r_dcache_fsm = r_dcache_fsm_save;
+        break;
+    }
+    ///////////////////
+    case DCACHE_CC_NOP:     // no external hit
+    {
+        /* activity counter */
+        if ( (( r_dcache_fsm_save == DCACHE_BIS ) ||( r_dcache_fsm_save == DCACHE_MISS_WAIT ) || ( r_dcache_fsm_save == DCACHE_MISS_UPDT ) ) && ( dreq.valid ) )        
+        {
+            m_cost_data_miss_frz++;
+        }
+        if( (( r_dcache_fsm_save == DCACHE_DTLB1_READ_CACHE ) || ( r_dcache_fsm_save == DCACHE_DTLB2_READ_CACHE ) ||
+             ( r_dcache_fsm_save == DCACHE_TLB1_READ )        || ( r_dcache_fsm_save == DCACHE_TLB2_READ )        ||
+             ( r_dcache_fsm_save == DCACHE_TLB1_LL_WAIT )     || ( r_dcache_fsm_save == DCACHE_TLB2_LL_WAIT )     ||
+             ( r_dcache_fsm_save == DCACHE_TLB1_SC_WAIT )     || ( r_dcache_fsm_save == DCACHE_TLB2_SC_WAIT )     || 
+             ( r_dcache_fsm_save == DCACHE_TLB1_READ_UPDT )   || ( r_dcache_fsm_save == DCACHE_TLB2_READ_UPDT )   ||
+             ( r_dcache_fsm_save == DCACHE_TLB1_UPDT_SEL )    || ( r_dcache_fsm_save == DCACHE_TLB2_UPDT_SEL )) && (dreq.valid) )
+        {
+            m_cost_data_tlb_miss_frz++;
+        }
+        if ( ( r_dcache_fsm_save == DCACHE_ITLB_READ ) ||( r_dcache_fsm_save == DCACHE_ITLB_UPDT ) || ( r_dcache_fsm_save == DCACHE_ITLB_LL_WAIT ) || ( r_dcache_fsm_save == DCACHE_ITLB_SC_WAIT ) )        
+        {
+            m_cost_ins_tlb_occup_cache_frz++;
+        }
+
+        r_tgt_dcache_req = false;
+        if ( r_tgt_update )
+	{
+            r_tgt_dcache_rsp = true;
+        } 
+	else 
+	{
+            r_tgt_dcache_rsp = false;
+        }
+
+        r_dcache_fsm = r_dcache_fsm_save;
+        break;
+    }   
+    /////////////////////////
+    case DCACHE_TLB_CC_INVAL:
+    {
+        /* activity counter */
+        if ( (( r_dcache_fsm_save == DCACHE_BIS ) ||( r_dcache_fsm_save == DCACHE_MISS_WAIT ) || ( r_dcache_fsm_save == DCACHE_MISS_UPDT ) ) && ( dreq.valid ) )        
+        {
+            m_cost_data_miss_frz++;
+        }
+        if( (( r_dcache_fsm_save == DCACHE_DTLB1_READ_CACHE ) || ( r_dcache_fsm_save == DCACHE_DTLB2_READ_CACHE ) ||
+             ( r_dcache_fsm_save == DCACHE_TLB1_READ )        || ( r_dcache_fsm_save == DCACHE_TLB2_READ )        ||
+             ( r_dcache_fsm_save == DCACHE_TLB1_LL_WAIT )     || ( r_dcache_fsm_save == DCACHE_TLB2_LL_WAIT )     ||
+             ( r_dcache_fsm_save == DCACHE_TLB1_SC_WAIT )     || ( r_dcache_fsm_save == DCACHE_TLB2_SC_WAIT )     || 
+             ( r_dcache_fsm_save == DCACHE_TLB1_READ_UPDT )   || ( r_dcache_fsm_save == DCACHE_TLB2_READ_UPDT )   ||
+             ( r_dcache_fsm_save == DCACHE_TLB1_UPDT_SEL )    || ( r_dcache_fsm_save == DCACHE_TLB2_UPDT_SEL )) && (dreq.valid) )
+        {
+            m_cost_data_tlb_miss_frz++;
+        }
+        if ( ( r_dcache_fsm_save == DCACHE_ITLB_READ ) ||( r_dcache_fsm_save == DCACHE_ITLB_UPDT ) || ( r_dcache_fsm_save == DCACHE_ITLB_LL_WAIT ) || ( r_dcache_fsm_save == DCACHE_ITLB_SC_WAIT ) )        
+        {
+            m_cost_ins_tlb_occup_cache_frz++;
+        }
+
+	if ( r_dcache_itlb_inval_req || r_dcache_dtlb_inval_req ) break;
+
+        if( (( r_dcache_fsm_save == DCACHE_TLB1_READ )        || ( r_dcache_fsm_save == DCACHE_TLB2_READ )        ||
+             ( r_dcache_fsm_save == DCACHE_TLB1_READ_UPDT )   || ( r_dcache_fsm_save == DCACHE_TLB2_READ_UPDT )   ||
+             ( r_dcache_fsm_save == DCACHE_TLB1_LL_WAIT )     || ( r_dcache_fsm_save == DCACHE_TLB2_LL_WAIT )     ||
+             ( r_dcache_fsm_save == DCACHE_TLB1_SC_WAIT )     || ( r_dcache_fsm_save == DCACHE_TLB2_SC_WAIT )     ||
+             ( r_dcache_fsm_save == DCACHE_TLB1_UPDT_SEL )    || ( r_dcache_fsm_save == DCACHE_TLB2_UPDT_SEL )    ||
+             ( r_dcache_fsm_save == DCACHE_DTLB1_READ_CACHE ) || ( r_dcache_fsm_save == DCACHE_DTLB2_READ_CACHE ) ||
+             ( r_dcache_fsm_save == DCACHE_LL_DIRTY_WAIT )    || ( r_dcache_fsm_save == DCACHE_SC_DIRTY_WAIT )    ||
+	     ( r_dcache_fsm_save == DCACHE_WRITE_DIRTY )) && 
+            (((r_dcache_tlb_paddr.read() & ~((m_dcache_words<<2)-1)) >> (uint32_log2(m_dcache_words) + 2)) == r_dcache_dtlb_inval_line.read()) ) 
+        {
+            r_dcache_inval_tlb_rsp = true;
+        } 
+
+        if (((r_dcache_fsm_save == DCACHE_BIS)||(r_dcache_fsm_save == DCACHE_MISS_WAIT) ||
+             (r_dcache_fsm_save == DCACHE_MISS_UPDT)) && 
+             (r_dcache_tlb_nline.read() == r_dcache_dtlb_inval_line.read()))
+        {
+            r_dcache_inval_tlb_rsp = true;
+        }
+
+	if ( !r_dcache_cc_check )
+	{
+            r_dcache_fsm = r_dcache_fsm_save;
+	}
+	else
+	{
+            r_dcache_fsm = DCACHE_CC_CHECK;
+	    r_dcache_cc_check = false;
+	}
+	r_dtlb_translation_valid = false;
+        r_dcache_ptba_ok = false;
+        break;
+    }
+    /////////////////////////
+    case DCACHE_ITLB_CLEANUP:
+    {
+        r_dcache.setinbit(((paddr_t)r_dcache_itlb_cleanup_line.read()<<(uint32_log2(m_dcache_words)+2)), r_dcache_in_itlb, false);
+        r_dcache_itlb_cleanup_req = false;
+        r_dcache_fsm = DCACHE_IDLE;
+        break;
+    }
+    } // end switch r_dcache_fsm
+
+#ifdef SOCLIB_MODULE_DEBUG
+    std::cout << name() << " Data Response: " << drsp << std::endl;
+#endif
+    ////////////////////////////////////////////////////////////////////////////////////
+    //      INVAL DTLB CHECK FSM 
+    ////////////////////////////////////////////////////////////////////////////////////////
+    switch(r_inval_dtlb_fsm) {
+    /////////////////////
+    case INVAL_DTLB_IDLE:
+    {
+        if ( r_dcache_dtlb_inval_req ) 
+        {
+            r_ccinval_dtlb_way = 0;
+            r_ccinval_dtlb_set = 0;
+            r_inval_dtlb_fsm = INVAL_DTLB_CHECK;    
+            m_cost_data_tlb_inval_frz++;
+        }   
+        break;
+    }
+    ////////////////////////////
+    case INVAL_DTLB_CHECK:
+    {
+        m_cost_data_tlb_inval_frz++;
+
+        size_t way = r_ccinval_dtlb_way; 
+        size_t set = r_ccinval_dtlb_set;
+        bool end = false;        
+        bool tlb_hit = dcache_tlb.cccheck(r_dcache_dtlb_inval_line.read(), way, set, &way, &set, &end); 
+    
+        if ( tlb_hit )
+        {
+            r_ccinval_dtlb_way = way; 
+            r_ccinval_dtlb_set = set;
+            r_dtlb_cc_check_end = end;
+            r_inval_dtlb_fsm = INVAL_DTLB_INVAL;
+            m_cpt_data_tlb_inval++;    
+        }        
+        else
+        {
+            r_inval_dtlb_fsm = INVAL_DTLB_CLEAR;    
+        }
+        break;
+    }
+    /////////////////////////
+    case INVAL_DTLB_INVAL:
+    {
+        m_cost_data_tlb_inval_frz++;
+
+        dcache_tlb.ccinval(r_ccinval_dtlb_way, r_ccinval_dtlb_set);
+
+        if ( !r_dtlb_cc_check_end )
+        {
+            r_inval_dtlb_fsm = INVAL_DTLB_CHECK; 
+        }
+        else
+        {
+            r_inval_dtlb_fsm = INVAL_DTLB_CLEAR;    
+        }
+        break;
+    }
+    ////////////////////
+    case INVAL_DTLB_CLEAR:
+    {
+        r_dcache_dtlb_inval_req = false;
+        r_dtlb_cc_check_end = false;
+        r_ccinval_dtlb_way = 0; 
+        r_ccinval_dtlb_set = 0; 
+        r_inval_dtlb_fsm = INVAL_DTLB_IDLE;   
+        m_cpt_data_tlb_inval++;    
+        break;
+    }
+    } // end switch r_inval_itlb_fsm
+
+    /////////// execute one iss cycle /////////////////////////////////
+    {
+    uint32_t it = 0;
+    for (size_t i=0; i<(size_t)iss_t::n_irq; i++) if(p_irq[i].read()) it |= (1<<i);
+    m_iss.executeNCycles(1, irsp, drsp, it);
+    }
+
+    ////////////// number of frozen cycles //////////////////////////
+    if ( (ireq.valid && !irsp.valid) || (dreq.valid && !drsp.valid) )
+    {
+        m_cpt_frz_cycles++;
+    }
+    if ( dreq.valid && !drsp.valid ) 
+    {
+        m_cpt_dcache_frz_cycles++;
+    }
+#ifdef EVALUATION_CACHE
+    for (size_t way = 0; way < m_dcache_ways; way++ )
+    {    
+        for (size_t set = 0; set < m_dcache_sets; set++ )
+        {
+	    if (r_dcache_in_itlb[way*m_dcache_sets+set] || r_dcache_in_dtlb[way*m_dcache_sets+set])
+		m_cpt_tlb_occup_dcache++;
+	}
+    }
+#endif
+    ////////////////////////////////////////////////////////////////////////////
+    //     VCI_CMD FSM 
+    //
+    // This FSM handles requests from both the DCACHE controler
+    // (request registers) and the ICACHE controler (request registers).
+    // There is 10 VCI transaction types :
+    // - INS_TLB_READ
+    // - INS_TLB_WRITE
+    // - INS_MISS
+    // - INS_UNC_MISS
+    // - DATA_TLB_READ
+    // - DATA_TLB_WRITE
+    // - DATA_TLB_DIRTY
+    // - DATA_MISS
+    // - DATA_UNC 
+    // - DATA_WRITE
+    // The ICACHE requests have the highest priority.
+    // There is at most one (CMD/RSP) VCI transaction, as both CMD_FSM and RSP_FSM
+    // exit simultaneously the IDLE state.
+    //////////////////////////////////////////////////////////////////////////////
+
+    switch (r_vci_cmd_fsm) {
+    
+    case CMD_IDLE:
+        if (r_vci_rsp_fsm != RSP_IDLE)
+            break;
+
+        r_vci_cmd_cpt = 0;
+
+	if ( (r_dcache_cleanup_req && r_dcache_itlb_read_req && (((r_icache_paddr_save.read() & ~((m_dcache_words<<2)-1)) >> (uint32_log2(m_dcache_words) + 2)) == r_dcache_cleanup_line.read())) 
+	  || (r_dcache_cleanup_req && r_dcache_tlb_read_req && (((r_dcache_tlb_paddr.read() & ~((m_dcache_words<<2)-1)) >> (uint32_log2(m_dcache_words) + 2)) == r_dcache_cleanup_line.read()))
+	  || (r_dcache_cleanup_req && r_dcache_miss_req && (((r_dcache_paddr_save.read() & ~((m_dcache_words<<2)-1)) >> (uint32_log2(m_dcache_words) + 2)) == r_dcache_cleanup_line.read()))
+	  || (r_icache_cleanup_req && r_icache_miss_req && (((r_icache_paddr_save.read() & ~((m_icache_words<<2)-1)) >> (uint32_log2(m_icache_words) + 2)) == r_icache_cleanup_line.read())) )
+	{
+	    break;
+	}
+
+        if (r_dcache_itlb_read_req)           
+        {            
+            r_vci_cmd_fsm = CMD_ITLB_READ;
+            m_cpt_itlbmiss_transaction++; 
+        } 
+	else if (r_dcache_itlb_ll_acc_req)
+	{
+	    r_vci_cmd_fsm = CMD_ITLB_ACC_LL;
+            m_cpt_itlb_ll_transaction++; 
+	}
+	else if (r_dcache_itlb_sc_acc_req)
+	{
+	    r_vci_cmd_fsm = CMD_ITLB_ACC_SC;
+            m_cpt_itlb_sc_transaction++; 
+	}
+        else if (r_icache_miss_req) 
+        {    
+            r_vci_cmd_fsm = CMD_INS_MISS;
+            m_cpt_imiss_transaction++; 
+        }
+        else if (r_icache_unc_req) 
+        {    
+            r_vci_cmd_fsm = CMD_INS_UNC;
+            m_cpt_icache_unc_transaction++; 
+        }  
+        else if (r_dcache_tlb_read_req) 
+        {            
+            r_vci_cmd_fsm = CMD_DTLB_READ;
+            m_cpt_dtlbmiss_transaction++; 
+        } 
+        else if (r_dcache_tlb_ll_acc_req) 
+        {  
+            r_vci_cmd_fsm = CMD_DTLB_ACC_LL;
+            m_cpt_dtlb_ll_transaction++; 
+        } 
+        else if (r_dcache_tlb_sc_acc_req) 
+        {  
+            r_vci_cmd_fsm = CMD_DTLB_ACC_SC;
+            m_cpt_dtlb_sc_transaction++; 
+        } 
+        else if (r_dcache_tlb_ll_dirty_req) 
+        {  
+            r_vci_cmd_fsm = CMD_DTLB_DIRTY_LL;
+            m_cpt_dtlb_ll_dirty_transaction++; 
+        } 
+        else if (r_dcache_tlb_sc_dirty_req) 
+        {  
+            r_vci_cmd_fsm = CMD_DTLB_DIRTY_SC;
+            m_cpt_dtlb_sc_dirty_transaction++; 
+        } 
+        else if (r_dcache_write_req)
+        {
+            r_vci_cmd_fsm = CMD_DATA_WRITE;
+            r_vci_cmd_cpt = r_wbuf.getMin();
+            r_vci_cmd_min = r_wbuf.getMin();
+            r_vci_cmd_max = r_wbuf.getMax(); 
+            m_cpt_write_transaction++; 
+            m_length_write_transaction += (r_wbuf.getMax() - r_wbuf.getMin() + 1);
+        }
+        else if (r_dcache_miss_req)  
+        {
+            r_vci_cmd_fsm = CMD_DATA_MISS;
+            m_cpt_dmiss_transaction++; 
+        }
+        else if (r_dcache_unc_req)  
+        {
+            r_vci_cmd_fsm = CMD_DATA_UNC;
+            m_cpt_unc_transaction++; 
+        }
+        break;
+
+    case CMD_DATA_WRITE:
+        if ( p_vci_ini_rw.cmdack.read() ) 
+        {
+            r_vci_cmd_cpt = r_vci_cmd_cpt + 1;
+            if (r_vci_cmd_cpt == r_vci_cmd_max) 
+            {
+                r_vci_cmd_fsm = CMD_IDLE;
+                r_wbuf.reset();
+            }
+        }
+        break;
+
+    default:
+        if ( p_vci_ini_rw.cmdack.read() )
+        {  
+            r_vci_cmd_fsm = CMD_IDLE;
+        }
+        break;
+
+    } // end  switch r_vci_cmd_fsm
+
+    //////////////////////////////////////////////////////////////////////////
+    //      VCI_RSP FSM 
+    //
+    // This FSM is synchronized with the VCI_CMD FSM, as both FSMs exit the
+    // IDLE state simultaneously.
+    //////////////////////////////////////////////////////////////////////////
+
+    switch (r_vci_rsp_fsm) {
+
+    case RSP_IDLE:
+        assert( !p_vci_ini_rw.rspval.read() && "Unexpected response" );
+
+        if (r_vci_cmd_fsm != CMD_IDLE)
+            break;
+
+        r_vci_rsp_cpt = 0;
+
+	if ( (r_dcache_cleanup_req && r_dcache_itlb_read_req && (((r_icache_paddr_save.read() & ~((m_dcache_words<<2)-1)) >> (uint32_log2(m_dcache_words) + 2)) == r_dcache_cleanup_line.read())) 
+	  || (r_dcache_cleanup_req && r_dcache_tlb_read_req && (((r_dcache_tlb_paddr.read() & ~((m_dcache_words<<2)-1)) >> (uint32_log2(m_dcache_words) + 2)) == r_dcache_cleanup_line.read()))
+	  || (r_dcache_cleanup_req && r_dcache_miss_req && (((r_dcache_paddr_save.read() & ~((m_dcache_words<<2)-1)) >> (uint32_log2(m_dcache_words) + 2)) == r_dcache_cleanup_line.read()))
+	  || (r_icache_cleanup_req && r_icache_miss_req && (((r_icache_paddr_save.read() & ~((m_icache_words<<2)-1)) >> (uint32_log2(m_icache_words) + 2)) == r_icache_cleanup_line.read())) )
+	{
+	    break;
+	}
+
+        if (r_dcache_itlb_read_req)          // ITLB miss response
+        {            
+            r_vci_rsp_fsm = RSP_ITLB_READ;
+        } 
+        else if (r_dcache_itlb_ll_acc_req)   // ITLB linked load response
+        {   
+            r_vci_rsp_fsm = RSP_ITLB_ACC_LL;
+        } 
+        else if (r_dcache_itlb_sc_acc_req)   // ITLB store conditional response
+        {   
+            r_vci_rsp_fsm = RSP_ITLB_ACC_SC;
+        } 
+        else if (r_icache_miss_req)          // ICACHE cached miss response
+        {   
+            r_vci_rsp_fsm = RSP_INS_MISS;
+        }
+        else if (r_icache_unc_req)           // ICACHE uncached miss response
+        {   
+            r_vci_rsp_fsm = RSP_INS_UNC;
+        }  
+        else if (r_dcache_tlb_read_req)      // ITLB miss response
+        {
+            r_vci_rsp_fsm = RSP_DTLB_READ; 
+        }
+        else if (r_dcache_tlb_ll_acc_req)    // DTLB access bits linked load response
+        {
+            r_vci_rsp_fsm = RSP_DTLB_ACC_LL; 
+        }
+        else if (r_dcache_tlb_sc_acc_req)    // DTLB access bits store conditional response
+        {
+            r_vci_rsp_fsm = RSP_DTLB_ACC_SC; 
+        }
+        else if (r_dcache_tlb_ll_dirty_req)  // DTLB dirty bit linked load response
+        {
+            r_vci_rsp_fsm = RSP_DTLB_DIRTY_LL; 
+        }
+        else if (r_dcache_tlb_sc_dirty_req)  // DTLB dirty bit store conditional response
+        {
+            r_vci_rsp_fsm = RSP_DTLB_DIRTY_SC; 
+        }
+        else if (r_dcache_write_req)         // DCACHE write response
+        {
+            r_vci_rsp_fsm = RSP_DATA_WRITE;
+        }
+        else if (r_dcache_miss_req)          // DCACHE read response
+        {
+            r_vci_rsp_fsm = RSP_DATA_MISS;
+        }
+        else if (r_dcache_unc_req)           // DCACHE uncached read response
+        {
+            r_vci_rsp_fsm = RSP_DATA_UNC;
+        }
+        break;
+
+    case RSP_ITLB_READ:
+        m_cost_itlbmiss_transaction++;
+        if ( ! p_vci_ini_rw.rspval.read() )
+            break;
+
+        assert(r_vci_rsp_cpt != m_dcache_words &&
+               "illegal VCI response packet for data read miss");
+
+        r_vci_rsp_cpt = r_vci_rsp_cpt + 1;
+        r_dcache_miss_buf[r_vci_rsp_cpt] = (data_t)p_vci_ini_rw.rdata.read();
+        if ( p_vci_ini_rw.reop.read() ) 
+        {
+            assert(r_vci_rsp_cpt == m_dcache_words - 1 &&
+                    "illegal VCI response packet for data read miss");
+            r_dcache_itlb_read_req = false;
+            r_vci_rsp_fsm = RSP_IDLE;
+        } 
+        if ( p_vci_ini_rw.rerror.read() != vci_param::ERR_NORMAL )
+        {
+            r_vci_rsp_data_error = true;
+        }
+        break;
+
+    case RSP_ITLB_ACC_LL:
+	m_cost_itlb_ll_transaction++;
+        if ( ! p_vci_ini_rw.rspval.read() )
+            break;
+
+        assert(p_vci_ini_rw.reop.read() &&
+               "illegal VCI response packet for ll tlb");
+
+        if ( p_vci_ini_rw.rerror.read() != vci_param::ERR_NORMAL ) 
+        {
+            r_vci_rsp_data_error = true;
+        }
+	else
+	{
+	    r_dcache_miss_buf[0] = (data_t)p_vci_ini_rw.rdata.read();
+	}
+        r_dcache_itlb_ll_acc_req = false;
+        r_vci_rsp_fsm = RSP_IDLE;
+	break;
+
+    case RSP_ITLB_ACC_SC:
+	m_cost_itlb_sc_transaction++;
+        if ( ! p_vci_ini_rw.rspval.read() )
+            break;
+
+        assert(p_vci_ini_rw.reop.read() &&
+               "illegal VCI response packet for sc tlb");
+
+        if ( p_vci_ini_rw.rerror.read() != vci_param::ERR_NORMAL ) 
+        {
+            r_vci_rsp_data_error = true;
+        }
+	else if ( p_vci_ini_rw.rdata.read() == 1 ) // store conditional is not successful
+	{
+	    r_dcache_tlb_sc_fail = true;
+	    //r_dcache_itlb_ll_acc_req = true;
+	}
+        r_dcache_itlb_sc_acc_req = false;
+        r_vci_rsp_fsm = RSP_IDLE;
+	break;
+
+    case RSP_INS_MISS:
+        m_cost_imiss_transaction++;
+        if ( ! p_vci_ini_rw.rspval.read() )
+            break;
+
+        assert( (r_vci_rsp_cpt < m_icache_words) && 
+               "The VCI response packet for instruction miss is too long");
+        r_vci_rsp_cpt = r_vci_rsp_cpt + 1;
+        r_icache_miss_buf[r_vci_rsp_cpt] = (data_t)p_vci_ini_rw.rdata.read();
+
+        if ( p_vci_ini_rw.reop.read() ) 
+        {
+            assert( (r_vci_rsp_cpt == m_icache_words - 1) &&
+                       "The VCI response packet for instruction miss is too short");
+            r_icache_miss_req = false;
+            r_vci_rsp_fsm = RSP_IDLE;
+                
+        } 
+        if ( p_vci_ini_rw.rerror.read() != vci_param::ERR_NORMAL )
+        {
+            r_vci_rsp_ins_error = true;
+        }
+        break;
+
+    case RSP_INS_UNC:
+        m_cost_icache_unc_transaction++;
+        if ( ! p_vci_ini_rw.rspval.read() )
+            break;
+
+        assert(p_vci_ini_rw.reop.read() &&
+               "illegal VCI response packet for uncached instruction");
+
+        r_icache_miss_buf[0] = (data_t)p_vci_ini_rw.rdata.read();
+        r_icache_buf_unc_valid = true;
+        r_icache_unc_req = false;
+        r_vci_rsp_fsm = RSP_IDLE;
+
+        if ( p_vci_ini_rw.rerror.read() != vci_param::ERR_NORMAL )
+        {
+            r_vci_rsp_ins_error = true;
+        }
+        break;
+
+    case RSP_DTLB_READ:
+        m_cost_dtlbmiss_transaction++;
+        if ( ! p_vci_ini_rw.rspval.read() )
+            break;
+
+        assert(r_vci_rsp_cpt != m_dcache_words &&
+               "illegal VCI response packet for data read miss");
+
+        r_vci_rsp_cpt = r_vci_rsp_cpt + 1;
+        r_dcache_miss_buf[r_vci_rsp_cpt] = (data_t)p_vci_ini_rw.rdata.read();
+        if ( p_vci_ini_rw.reop.read() ) 
+        {
+            assert(r_vci_rsp_cpt == m_dcache_words - 1 &&
+                    "illegal VCI response packet for data read miss");
+            r_dcache_tlb_read_req = false;
+            r_vci_rsp_fsm = RSP_IDLE;
+        } 
+        if ( p_vci_ini_rw.rerror.read() != vci_param::ERR_NORMAL )
+        {
+            r_vci_rsp_data_error = true;
+        }
+        break;
+
+    case RSP_DTLB_ACC_LL:
+	m_cost_dtlb_ll_transaction++; 
+        if ( ! p_vci_ini_rw.rspval.read() )
+            break;
+
+        assert(p_vci_ini_rw.reop.read() &&
+               "illegal VCI response packet for ll tlb");
+
+        if ( p_vci_ini_rw.rerror.read() != vci_param::ERR_NORMAL ) 
+        {
+            r_vci_rsp_data_error = true;
+        }
+	else
+	{
+	    r_dcache_miss_buf[0] = (data_t)p_vci_ini_rw.rdata.read();
+	}
+        r_dcache_tlb_ll_acc_req = false;
+        r_vci_rsp_fsm = RSP_IDLE;
+	break;
+
+    case RSP_DTLB_ACC_SC:
+	m_cost_dtlb_sc_transaction++;
+        if ( ! p_vci_ini_rw.rspval.read() )
+            break;
+
+        assert(p_vci_ini_rw.reop.read() &&
+               "illegal VCI response packet for sc tlb");
+
+        if ( p_vci_ini_rw.rerror.read() != vci_param::ERR_NORMAL ) 
+        {
+            r_vci_rsp_data_error = true;
+        }
+	else if ( p_vci_ini_rw.rdata.read() == 1 ) // store conditional is not successful
+	{
+	    r_dcache_tlb_sc_fail = true;
+	}
+        r_dcache_tlb_sc_acc_req = false;
+        r_vci_rsp_fsm = RSP_IDLE;
+	break;
+
+    case RSP_DTLB_DIRTY_LL:
+	m_cost_dtlb_ll_dirty_transaction++; 
+        if ( ! p_vci_ini_rw.rspval.read() )
+            break;
+
+        assert(p_vci_ini_rw.reop.read() &&
+               "illegal VCI response packet for ll tlb");
+
+        if ( p_vci_ini_rw.rerror.read() != vci_param::ERR_NORMAL ) 
+        {
+            r_vci_rsp_data_error = true;
+        }
+	else
+	{
+	    r_dcache_miss_buf[0] = (data_t)p_vci_ini_rw.rdata.read();
+	}
+        r_dcache_tlb_ll_dirty_req = false;
+        r_vci_rsp_fsm = RSP_IDLE;
+	break;
+
+    case RSP_DTLB_DIRTY_SC:
+	m_cost_dtlb_sc_dirty_transaction++; 
+        if ( ! p_vci_ini_rw.rspval.read() )
+            break;
+
+        assert(p_vci_ini_rw.reop.read() &&
+               "illegal VCI response packet for sc tlb");
+
+        if ( p_vci_ini_rw.rerror.read() != vci_param::ERR_NORMAL ) 
+        {
+            r_vci_rsp_data_error = true;
+        }
+	else if ( p_vci_ini_rw.rdata.read() == 1 ) // store conditional is not successful
+	{
+	    r_dcache_tlb_sc_fail = true;
+	}
+        r_dcache_tlb_sc_dirty_req = false;
+        r_vci_rsp_fsm = RSP_IDLE;
+	break;
+
+    case RSP_DATA_UNC:
+        m_cost_unc_transaction++;
+        if ( ! p_vci_ini_rw.rspval.read() ) 
+            break;
+
+        assert(p_vci_ini_rw.reop.read() &&
+               "illegal VCI response packet for data read uncached");
+
+        if ( p_vci_ini_rw.rerror.read() != vci_param::ERR_NORMAL ) 
+        {
+            r_vci_rsp_data_error = true;
+        }
+        else
+        {
+            r_dcache_miss_buf[0] = (data_t)p_vci_ini_rw.rdata.read();
+            r_dcache_buf_unc_valid = true;
+        }
+        r_dcache_unc_req = false;
+        r_vci_rsp_fsm = RSP_IDLE;
+        break;
+
+    case RSP_DATA_MISS:
+        m_cost_dmiss_transaction++;
+        if ( ! p_vci_ini_rw.rspval.read() )
+            break;
+
+        assert(r_vci_rsp_cpt != m_dcache_words &&
+               "illegal VCI response packet for data read miss");
+
+        r_vci_rsp_cpt = r_vci_rsp_cpt + 1;
+        r_dcache_miss_buf[r_vci_rsp_cpt] = (data_t)p_vci_ini_rw.rdata.read();
+        if ( p_vci_ini_rw.reop.read() ) 
+        {
+            assert(r_vci_rsp_cpt == m_dcache_words - 1 &&
+                    "illegal VCI response packet for data read miss");
+            r_dcache_miss_req = false;
+            r_vci_rsp_fsm = RSP_IDLE;
+        } 
+        if ( p_vci_ini_rw.rerror.read() != vci_param::ERR_NORMAL )
+        {
+            r_vci_rsp_data_error = true;
+        }
+        break;
+
+    case RSP_DATA_WRITE:
+        m_cost_write_transaction++;
+        if ( ! p_vci_ini_rw.rspval.read() )
+            break;
+
+        if ( p_vci_ini_rw.reop.read() ) 
+        {
+            r_vci_rsp_fsm = RSP_IDLE;
+            r_dcache_write_req = false;
+        }
+        if ( p_vci_ini_rw.rerror.read() != vci_param::ERR_NORMAL ) 
+        {
+            m_iss.setWriteBerr();
+        }
+        break;
+    } // end switch r_vci_rsp_fsm
+
+    //////////////////////////////////////////////////////////////////////////
+    //      CLEANUP CMD FSM 
+    //
+    // This FSM is synchronized with the CLEANUP RSP FSM, as both FSMs exit the
+    // IDLE state simultaneously.
+    //////////////////////////////////////////////////////////////////////////
+
+    switch (r_cleanup_cmd_fsm) {
+    
+    case CLEANUP_CMD_IDLE:
+        if (r_cleanup_rsp_fsm != CLEANUP_RSP_IDLE)
+            break;
+
+        if (r_dcache_cleanup_req)
+        {
+            r_cleanup_cmd_fsm = CLEANUP_CMD_DATA;
+	        m_cpt_dcleanup_transaction++;
+        }
+        else if (r_icache_cleanup_req)
+        {
+            r_cleanup_cmd_fsm = CLEANUP_CMD_INS;
+	        m_cpt_icleanup_transaction++;
+        }
+        break;
+
+    default:
+        if ( p_vci_ini_c.cmdack.read() )
+        {  
+            r_cleanup_cmd_fsm = CLEANUP_CMD_IDLE;
+        }
+        break;
+
+    } // end  switch r_vci_cmd_fsm
+
+    //////////////////////////////////////////////////////////////////////////
+    //      CLEANUP RSP FSM 
+    //
+    // This FSM is synchronized with the CLEANUP CMD FSM, as both FSMs exit the
+    // IDLE state simultaneously.
+    //////////////////////////////////////////////////////////////////////////
+
+    switch (r_cleanup_rsp_fsm) {
+
+    case CLEANUP_RSP_IDLE:	
+    {
+        assert(!p_vci_ini_c.rspval.read() && "Unexpected response" );
+
+        if (r_cleanup_cmd_fsm != CLEANUP_CMD_IDLE)
+            break;
+
+        if (r_dcache_cleanup_req)
+        {
+            r_cleanup_rsp_fsm = CLEANUP_RSP_DATA;
+        }
+        else if (r_icache_cleanup_req)
+        {
+            r_cleanup_rsp_fsm = CLEANUP_RSP_INS;
+        }
+        break;
+    }
+    case CLEANUP_RSP_DATA:
+    {
+	    m_cost_dcleanup_transaction++;
+        if ( ! p_vci_ini_c.rspval.read() )
+            break;
+        assert( p_vci_ini_c.reop.read() &&
+                "illegal VCI response packet for dcache cleanup");
+        assert( (p_vci_ini_c.rerror.read() == vci_param::ERR_NORMAL) &&
+                "error in response packet for dcache cleanup");    
+
+        r_dcache_cleanup_req = false;
+        r_cleanup_rsp_fsm = CLEANUP_RSP_IDLE;    
+	break;  	    
+    }
+    case CLEANUP_RSP_INS:
+    {
+	    m_cost_icleanup_transaction++;
+        if ( ! p_vci_ini_c.rspval.read() )
+            break;
+        assert( p_vci_ini_c.reop.read() &&
+                "illegal VCI response packet for icache cleanup");
+        assert( (p_vci_ini_c.rerror.read() == vci_param::ERR_NORMAL) &&
+                "error in response packet for icache cleanup");    
+
+        r_icache_cleanup_req = false;
+        r_cleanup_rsp_fsm = CLEANUP_RSP_IDLE;    
+	break;    
+    }
+    } // end  switch r_cleanup_fsm
+
+} // end transition()
+
+///////////////////////
+tmpl(void)::genMoore()
+///////////////////////
+{
+    // VCI initiator response
+    p_vci_ini_rw.rspack = true;
+
+    // VCI initiator command
+    p_vci_ini_rw.pktid  = 0;
+    p_vci_ini_rw.srcid  = m_srcid_rw;
+    p_vci_ini_rw.cons   = false;
+    p_vci_ini_rw.wrap   = false;
+    p_vci_ini_rw.contig = true;
+    p_vci_ini_rw.clen   = 0;
+    p_vci_ini_rw.cfixed = false;
+
+    switch (r_vci_cmd_fsm) {
+
+    case CMD_IDLE:
+        p_vci_ini_rw.cmdval  = false;
+        p_vci_ini_rw.address = 0;
+        p_vci_ini_rw.wdata   = 0;
+        p_vci_ini_rw.be      = 0;
+        p_vci_ini_rw.trdid   = 0;
+        p_vci_ini_rw.plen    = 0;
+        p_vci_ini_rw.cmd     = vci_param::CMD_NOP;
+        p_vci_ini_rw.eop     = false;
+        break;
+
+    case CMD_ITLB_READ:     
+        p_vci_ini_rw.cmdval  = true;
+        p_vci_ini_rw.address = r_icache_paddr_save.read() & m_dcache_yzmask;
+        p_vci_ini_rw.wdata   = 0;
+        p_vci_ini_rw.be      = 0xF;
+        p_vci_ini_rw.trdid   = 1; // via data cache cached read
+        p_vci_ini_rw.plen    = m_dcache_words << 2;
+        p_vci_ini_rw.cmd     = vci_param::CMD_READ;
+        p_vci_ini_rw.eop     = true;
+        break;
+
+    case CMD_ITLB_ACC_LL:
+        p_vci_ini_rw.cmdval  = true;
+        p_vci_ini_rw.address = r_icache_paddr_save.read() & ~0x3;
+        p_vci_ini_rw.wdata   = 0;
+        p_vci_ini_rw.be      = 0xF;
+        p_vci_ini_rw.trdid   = 0; // data cache uncached read
+        p_vci_ini_rw.plen    = 4;
+        p_vci_ini_rw.cmd     = vci_param::CMD_LOCKED_READ;
+        p_vci_ini_rw.eop     = true;
+	break;
+
+    case CMD_ITLB_ACC_SC:
+        p_vci_ini_rw.cmdval  = true;
+        p_vci_ini_rw.address = r_icache_paddr_save.read() & ~0x3;
+        p_vci_ini_rw.wdata   = r_icache_pte_update.read();
+        p_vci_ini_rw.be      = 0xF;
+        p_vci_ini_rw.trdid   = 0; // data cache uncached read
+        p_vci_ini_rw.plen    = 4;
+        p_vci_ini_rw.cmd     = vci_param::CMD_STORE_COND;
+        p_vci_ini_rw.eop     = true;
+	break;	
+
+    case CMD_INS_MISS:
+        p_vci_ini_rw.cmdval  = true;
+        p_vci_ini_rw.address = r_icache_paddr_save.read() & m_icache_yzmask;
+        p_vci_ini_rw.wdata   = 0;
+        p_vci_ini_rw.be      = 0xF;
+        p_vci_ini_rw.trdid   = 3; // ins cache cached read
+        p_vci_ini_rw.plen    = m_icache_words << 2;
+        p_vci_ini_rw.cmd     = vci_param::CMD_READ;
+        p_vci_ini_rw.eop     = true;
+        break;
+
+    case CMD_INS_UNC:
+        p_vci_ini_rw.cmdval  = true;
+        p_vci_ini_rw.address = r_icache_paddr_save.read() & ~0x3;
+        p_vci_ini_rw.wdata   = 0;
+        p_vci_ini_rw.be      = 0xF;
+        p_vci_ini_rw.trdid   = 2; // ins cache uncached read
+        p_vci_ini_rw.plen    = 4;
+        p_vci_ini_rw.cmd     = vci_param::CMD_READ;
+        p_vci_ini_rw.eop     = true;
+        break;
+
+    case CMD_DTLB_READ:     
+        p_vci_ini_rw.cmdval  = true;
+        p_vci_ini_rw.address = r_dcache_tlb_paddr.read() & m_dcache_yzmask;
+        p_vci_ini_rw.wdata   = 0;
+        p_vci_ini_rw.be      = 0xF;
+        p_vci_ini_rw.trdid   = 1; // via dcache cached read
+        p_vci_ini_rw.plen    = m_dcache_words << 2;
+        p_vci_ini_rw.cmd     = vci_param::CMD_READ;
+        p_vci_ini_rw.eop     = true;
+        break;
+
+    case CMD_DTLB_ACC_LL:
+        p_vci_ini_rw.cmdval  = true;
+        p_vci_ini_rw.address = r_dcache_tlb_paddr.read() & ~0x3;
+        p_vci_ini_rw.wdata   = 0;
+        p_vci_ini_rw.be      = 0xF;
+        p_vci_ini_rw.trdid   = 0; // data cache uncached read
+        p_vci_ini_rw.plen    = 4;
+        p_vci_ini_rw.cmd     = vci_param::CMD_LOCKED_READ;
+        p_vci_ini_rw.eop     = true;
+	break;
+
+    case CMD_DTLB_ACC_SC:
+        p_vci_ini_rw.cmdval  = true;
+        p_vci_ini_rw.address = r_dcache_tlb_paddr.read() & ~0x3;
+        p_vci_ini_rw.wdata   = r_dcache_pte_update.read();
+        p_vci_ini_rw.be      = 0xF;
+        p_vci_ini_rw.trdid   = 0; // data cache uncached read
+        p_vci_ini_rw.plen    = 4;
+        p_vci_ini_rw.cmd     = vci_param::CMD_STORE_COND;
+        p_vci_ini_rw.eop     = true;
+	break;	
+
+    case CMD_DTLB_DIRTY_LL:
+        p_vci_ini_rw.cmdval  = true;
+        p_vci_ini_rw.address = r_dcache_tlb_paddr.read() & ~0x3;
+        p_vci_ini_rw.wdata   = 0;
+        p_vci_ini_rw.be      = 0xF;
+        p_vci_ini_rw.trdid   = 0; // data cache uncached read
+        p_vci_ini_rw.plen    = 4;
+        p_vci_ini_rw.cmd     = vci_param::CMD_LOCKED_READ;
+        p_vci_ini_rw.eop     = true;
+	break;
+
+    case CMD_DTLB_DIRTY_SC:
+        p_vci_ini_rw.cmdval  = true;
+        p_vci_ini_rw.address = r_dcache_tlb_paddr.read() & ~0x3;
+        p_vci_ini_rw.wdata   = r_dcache_pte_update.read();
+        p_vci_ini_rw.be      = 0xF;
+        p_vci_ini_rw.trdid   = 0; // data cache uncached read
+        p_vci_ini_rw.plen    = 4;
+        p_vci_ini_rw.cmd     = vci_param::CMD_STORE_COND;
+        p_vci_ini_rw.eop     = true;
+	break;	
+
+    case CMD_DATA_UNC:
+        p_vci_ini_rw.cmdval  = true;
+        p_vci_ini_rw.address = r_dcache_paddr_save.read() & ~0x3;
+        p_vci_ini_rw.trdid   = 0; // data cache uncached read
+        p_vci_ini_rw.plen    = 4;
+        p_vci_ini_rw.eop     = true;
+        switch(r_dcache_type_save) {
+        case iss_t::DATA_READ:
+            p_vci_ini_rw.wdata = 0;
+            p_vci_ini_rw.be    = r_dcache_be_save.read();
+            p_vci_ini_rw.cmd   = vci_param::CMD_READ;
+            break;
+        case iss_t::DATA_LL:
+            p_vci_ini_rw.wdata = 0;
+            p_vci_ini_rw.be    = 0xF;
+            p_vci_ini_rw.cmd   = vci_param::CMD_LOCKED_READ;
+            break;
+        case iss_t::DATA_SC:
+            p_vci_ini_rw.wdata = r_dcache_wdata_save.read();
+            p_vci_ini_rw.be    = 0xF;
+            p_vci_ini_rw.cmd   = vci_param::CMD_STORE_COND;
+            break;
+        default:
+            assert("this should not happen");
+        }
+        break;
+
+    case CMD_DATA_WRITE:
+        p_vci_ini_rw.cmdval  = true;
+        p_vci_ini_rw.address = r_wbuf.getAddress(r_vci_cmd_cpt);
+        p_vci_ini_rw.wdata   = r_wbuf.getData(r_vci_cmd_cpt);
+        p_vci_ini_rw.be      = r_wbuf.getBe(r_vci_cmd_cpt);
+        p_vci_ini_rw.trdid   = 0; // data cache write
+        p_vci_ini_rw.plen    = (r_vci_cmd_max - r_vci_cmd_min + 1)<<2;
+        p_vci_ini_rw.cmd     = vci_param::CMD_WRITE;
+        p_vci_ini_rw.eop     = (r_vci_cmd_cpt == r_vci_cmd_max);
+        break;
+
+    case CMD_DATA_MISS:
+        p_vci_ini_rw.cmdval  = true;
+        p_vci_ini_rw.address = r_dcache_paddr_save.read() & m_dcache_yzmask;
+        p_vci_ini_rw.wdata   = 0;
+        p_vci_ini_rw.be      = 0xF;
+        p_vci_ini_rw.trdid   = 1; // data cache cached read
+        p_vci_ini_rw.plen    = m_dcache_words << 2;
+        p_vci_ini_rw.cmd     = vci_param::CMD_READ;
+        p_vci_ini_rw.eop     = true;
+        break;
+    } // end switch r_vci_cmd_fsm
+
+    p_vci_ini_c.rspack = true;
+
+    switch (r_cleanup_cmd_fsm) {
+
+    case CLEANUP_CMD_IDLE:
+        p_vci_ini_c.cmdval  = false;
+	p_vci_ini_c.address = 0;
+        p_vci_ini_c.trdid   = 0; 
+        p_vci_ini_c.wdata   = 0;
+        p_vci_ini_c.be      = 0;
+        p_vci_ini_c.plen    = 0;
+        p_vci_ini_c.cmd     = vci_param::CMD_NOP;
+        p_vci_ini_c.pktid   = 0;
+        p_vci_ini_c.srcid   = m_srcid_c;
+        p_vci_ini_c.cons    = false;
+        p_vci_ini_c.wrap    = false;
+        p_vci_ini_c.contig  = false;
+        p_vci_ini_c.clen    = 0;
+        p_vci_ini_c.cfixed  = false;
+        p_vci_ini_c.eop     = false;
+        break;
+
+    case CLEANUP_CMD_DATA:
+        p_vci_ini_c.cmdval  = true;
+	p_vci_ini_c.address = r_dcache_cleanup_line.read() * (m_dcache_words<<2);
+        p_vci_ini_c.trdid  = 0; // data cleanup 
+        p_vci_ini_c.wdata  = 0;
+        p_vci_ini_c.be     = 0;
+        p_vci_ini_c.plen   = 4;
+        p_vci_ini_c.cmd    = vci_param::CMD_WRITE;
+        p_vci_ini_c.pktid  = 0;
+        p_vci_ini_c.srcid  = m_srcid_c;
+        p_vci_ini_c.cons   = false;
+        p_vci_ini_c.wrap   = false;
+        p_vci_ini_c.contig = false;
+        p_vci_ini_c.clen   = 0;
+        p_vci_ini_c.cfixed = false;
+        p_vci_ini_c.eop    = true;
+        break;
+
+    case CLEANUP_CMD_INS:
+        p_vci_ini_c.cmdval  = true;
+	p_vci_ini_c.address = r_icache_cleanup_line.read() * (m_icache_words<<2);
+        p_vci_ini_c.trdid  = 1; // ins cleanup 
+        p_vci_ini_c.wdata  = 0;
+        p_vci_ini_c.be     = 0;
+        p_vci_ini_c.plen   = 4;
+        p_vci_ini_c.cmd    = vci_param::CMD_WRITE;
+        p_vci_ini_c.pktid  = 0;
+        p_vci_ini_c.srcid  = m_srcid_c;
+        p_vci_ini_c.cons   = false;
+        p_vci_ini_c.wrap   = false;
+        p_vci_ini_c.contig = false;
+        p_vci_ini_c.clen   = 0;
+        p_vci_ini_c.cfixed = false;
+        p_vci_ini_c.eop    = true;
+        break;
+      } // end switch r_vci_cmd_cleanup_fsm
+
+    // VCI_TGT
+    switch ( r_vci_tgt_fsm.read() ) {
+
+    case TGT_IDLE:
+    case TGT_UPDT_WORD:
+    case TGT_UPDT_DATA:
+        p_vci_tgt.cmdack  = true;
+        p_vci_tgt.rspval  = false;
+        break;
+
+    case TGT_RSP_BROADCAST:
+        p_vci_tgt.cmdack  = false;
+        p_vci_tgt.rspval  = !r_tgt_icache_req.read() && !r_tgt_dcache_req.read() && ( r_tgt_icache_rsp | r_tgt_dcache_rsp );
+        p_vci_tgt.rsrcid  = r_tgt_srcid.read();
+        p_vci_tgt.rpktid  = r_tgt_pktid.read();
+        p_vci_tgt.rtrdid  = r_tgt_trdid.read();
+        p_vci_tgt.rdata   = 0;
+        p_vci_tgt.rerror  = 0;
+        p_vci_tgt.reop    = true;
+        break;
+
+    case TGT_RSP_ICACHE:
+        p_vci_tgt.cmdack  = false;
+        p_vci_tgt.rspval  = !r_tgt_icache_req.read() && r_tgt_icache_rsp.read();
+        p_vci_tgt.rsrcid  = r_tgt_srcid.read();
+        p_vci_tgt.rpktid  = r_tgt_pktid.read();
+        p_vci_tgt.rtrdid  = r_tgt_trdid.read();
+        p_vci_tgt.rdata   = 0;
+        p_vci_tgt.rerror  = 0;
+        p_vci_tgt.reop    = true;
+        break;
+
+    case TGT_RSP_DCACHE:
+        p_vci_tgt.cmdack  = false;
+        p_vci_tgt.rspval  = !r_tgt_dcache_req.read() && r_tgt_dcache_rsp.read();
+        p_vci_tgt.rsrcid  = r_tgt_srcid.read();
+        p_vci_tgt.rpktid  = r_tgt_pktid.read();
+        p_vci_tgt.rtrdid  = r_tgt_trdid.read();
+        p_vci_tgt.rdata   = 0;
+        p_vci_tgt.rerror  = 0;
+        p_vci_tgt.reop    = true;
+        break;
+
+    case TGT_REQ_BROADCAST:
+    case TGT_REQ_ICACHE:
+    case TGT_REQ_DCACHE:
+        p_vci_tgt.cmdack  = false;
+        p_vci_tgt.rspval  = false;
+        break;
+
+    } // end switch TGT_FSM
+
+#ifdef SOCLIB_MODULE_DEBUG
+   std::cout << name() 
+      	     << " Moore R/W:" << std::hex
+      	     << " p_vci_ini_rw.cmdval: " << p_vci_ini_rw.cmdval
+      	     << " p_vci_ini_rw.address: " << p_vci_ini_rw.address
+      	     << " p_vci_ini_rw.srcid: " << p_vci_ini_rw.srcid
+      	     << " p_vci_ini_rw.wdata: " << p_vci_ini_rw.wdata
+      	     << " p_vci_ini_rw.cmd: " << p_vci_ini_rw.cmd
+      	     << " p_vci_ini_rw.eop: " << p_vci_ini_rw.eop
+      	     << std::endl;
+
+   std::cout << name() 
+      	     << " Moore TGT:" << std::hex
+      	     << " p_vci_tgt.rspval: " << p_vci_tgt.rspval
+      	     << std::endl;
+
+   std::cout << name() 
+      	     << " Moore Cleanup:" << std::hex
+      	     << " p_vci_ini_c.cmdval: " << p_vci_ini_c.cmdval
+      	     << " p_vci_ini_c.address: " << p_vci_ini_c.address
+      	     << " p_vci_ini_c.trdid: " << p_vci_ini_c.trdid
+      	     << " p_vci_ini_c.cmd: " << p_vci_ini_c.cmd
+      	     << " p_vci_ini_c.eop: " << p_vci_ini_c.eop
+      	     << std::endl;
+#endif
+}
+
+}}
+
+// Local Variables:
+// tab-width: 4
+// c-basic-offset: 4
+// c-file-offsets:((innamespace . 0)(inline-open . 0))
+// indent-tabs-mode: nil
+// End:
+
+// vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4
+
+
+
+
+
+
+
+
+
+
Index: branches/v4/modules/vci_cc_vcache_wrapper_multi/caba/metadata/vci_cc_vcache_wrapper_multi.sd
===================================================================
--- branches/v4/modules/vci_cc_vcache_wrapper_multi/caba/metadata/vci_cc_vcache_wrapper_multi.sd	(revision 371)
+++ branches/v4/modules/vci_cc_vcache_wrapper_multi/caba/metadata/vci_cc_vcache_wrapper_multi.sd	(revision 371)
@@ -0,0 +1,67 @@
+
+# -*- python -*-
+
+__id__ = "$Id: vci_cc_vcache_wrapper_multi.sd 917 2009-03-12 10:10:06Z nipo $"
+__version__ = "$Revision: 917 $"
+
+Module('caba:vci_cc_vcache_wrapper_multi',
+	classname = 'soclib::caba::VciCcVCacheWrapperMulti',
+	   tmpl_parameters = [
+	parameter.Module('vci_param', default = 'caba:vci_param'),
+	parameter.Module('iss_t'),
+	],
+	header_files = [
+	'../source/include/vci_cc_vcache_wrapper_multi.h',
+	],
+	implementation_files = [
+	'../source/src/vci_cc_vcache_wrapper_multi.cpp',
+	],
+	uses = [
+	Uses('caba:base_module'),
+	Uses('caba:multi_write_buffer'),
+	Uses('caba:generic_tlb', addr_t = parameter.StringExt('sc_dt::sc_uint<%d> ', parameter.Reference('addr_size'))),
+	Uses('caba:generic_cache', addr_t = parameter.StringExt('sc_dt::sc_uint<%d> ', parameter.Reference('addr_size'))),
+	Uses('common:address_masking_table', data_t = parameter.StringExt('sc_dt::sc_uint<%d> ', parameter.Reference('addr_size'))),
+	Uses('common:iss2'),
+	Uses('common:mapping_table'),
+	],
+	ports = [
+	Port('caba:vci_initiator', 'p_vci_ini_rw'),
+	Port('caba:vci_initiator', 'p_vci_ini_c'),
+	Port('caba:vci_target', 'p_vci_tgt'),
+	Port('caba:bit_in','p_irq', parameter.Constant('n_irq')),
+	Port('caba:bit_in', 'p_resetn', auto = 'resetn'),
+	Port('caba:clock_in', 'p_clk', auto = 'clock'),
+	],
+	instance_parameters = [
+	parameter.Int('proc_id'),
+	parameter.Module('mt', 'common:mapping_table'),
+	parameter.Module('mc', 'common:mapping_table'),
+	parameter.IntTab('initiator_rw_index'),
+	parameter.IntTab('initiator_c_index'),
+	parameter.IntTab('target_index'),
+    	parameter.Int('itlb_ways'),
+    	parameter.Int('itlb_sets'),
+    	parameter.Int('dtlb_ways'),
+    	parameter.Int('dtlb_sets'),
+    	parameter.Int('icache_ways'),
+    	parameter.Int('icache_sets'),
+    	parameter.Int('icache_words'),
+    	parameter.Int('dcache_ways'),
+    	parameter.Int('dcache_sets'),
+    	parameter.Int('dcache_words'),
+    	parameter.Int('write_buf_nwords'),
+    	parameter.Int('write_buf_nlines'),
+	],
+	   extensions = [
+	'dsx:get_ident='
+        'initiator_rw_index:p_vci_ini_rw:mt,'
+        'initiator_c_index:p_vci_ini_c:mc,'
+        'target_index:p_vci_tgt:mc',
+	'dsx:cpu=wrapper:iss_t',
+	'dsx:addressable=target_index',
+    'dsx:on_segment=mc:add_index:initiator_rw_index',
+	'dsx:mapping_type=processor:proc_id',
+   ],
+)
+
Index: branches/v4/modules/vci_cc_vcache_wrapper_multi/caba/source/include/vci_cc_vcache_wrapper_multi.h
===================================================================
--- branches/v4/modules/vci_cc_vcache_wrapper_multi/caba/source/include/vci_cc_vcache_wrapper_multi.h	(revision 371)
+++ branches/v4/modules/vci_cc_vcache_wrapper_multi/caba/source/include/vci_cc_vcache_wrapper_multi.h	(revision 371)
@@ -0,0 +1,559 @@
+/* -*- c++ -*-
+ * File : vci_cc_vcache_wrapper_multi.h
+ * Copyright (c) UPMC, Lip6, SoC
+ * Authors : Alain GREINER, Yang GAO
+ *
+ * SOCLIB_LGPL_HEADER_BEGIN
+ * 
+ * This file is part of SoCLib, GNU LGPLv2.1.
+ * 
+ * SoCLib is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU Lesser General Public License as published
+ * by the Free Software Foundation; version 2.1 of the License.
+ * 
+ * SoCLib is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * Lesser General Public License for more details.
+ * 
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with SoCLib; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301 USA
+ * 
+ * SOCLIB_LGPL_HEADER_END
+ */
+ 
+#ifndef SOCLIB_CABA_VCI_CC_VCACHE_WRAPPER_MULTI_H
+#define SOCLIB_CABA_VCI_CC_VCACHE_WRAPPER_MULTI_H
+
+#include <inttypes.h>
+#include <systemc>
+#include "caba_base_module.h"
+#include "multi_write_buffer.h"
+#include "generic_cache.h"
+#include "vci_initiator.h"
+#include "vci_target.h"
+#include "mapping_table.h"
+#include "generic_tlb.h"
+#include "static_assert.h"
+
+namespace soclib {
+namespace caba {
+
+using namespace sc_core;
+
+////////////////////////////////////////////
+template<typename vci_param, typename iss_t>
+class VciCcVCacheWrapperMulti
+////////////////////////////////////////////
+    : public soclib::caba::BaseModule
+{
+    typedef uint32_t vaddr_t;
+    typedef uint32_t data_t;
+    typedef uint32_t tag_t;
+    typedef uint32_t type_t;
+    typedef typename iss_t::DataOperationType data_op_t;
+
+    typedef typename vci_param::addr_t  paddr_t;
+    typedef typename vci_param::be_t    vci_be_t;
+	typedef typename vci_param::srcid_t vci_srcid_t;
+	typedef typename vci_param::trdid_t vci_trdid_t;
+	typedef typename vci_param::pktid_t vci_pktid_t;
+	typedef typename vci_param::plen_t  vci_plen_t;
+
+    enum icache_fsm_state_e {  
+        ICACHE_IDLE,                // 00
+        ICACHE_BIS,                 // 01
+        ICACHE_TLB1_READ,           // 02
+        ICACHE_TLB1_LL_WAIT,        // 03
+        ICACHE_TLB1_SC_WAIT,        // 04
+        ICACHE_TLB1_UPDT,           // 05
+        ICACHE_TLB2_READ,           // 06
+        ICACHE_TLB2_LL_WAIT,        // 07
+        ICACHE_TLB2_SC_WAIT,        // 08
+        ICACHE_TLB2_UPDT,           // 09
+        ICACHE_TLB_FLUSH,           // 0a
+        ICACHE_CACHE_FLUSH,         // 0b
+        ICACHE_TLB_INVAL,           // 0c
+        ICACHE_CACHE_INVAL,         // 0d
+        ICACHE_CACHE_INVAL_PA,      // 0e
+        ICACHE_MISS_WAIT,           // 0f
+        ICACHE_UNC_WAIT,            // 10
+        ICACHE_MISS_UPDT,           // 11
+        ICACHE_ERROR,               // 12
+        ICACHE_CC_INVAL,            // 13
+        ICACHE_TLB_CC_INVAL,        // 14
+    };
+
+    enum dcache_fsm_state_e {  
+        DCACHE_IDLE,                // 00
+        DCACHE_BIS,                 // 01
+        DCACHE_TLB1_READ,           // 02
+        DCACHE_TLB1_LL_WAIT,        // 03
+        DCACHE_TLB1_SC_WAIT,        // 04
+        DCACHE_TLB1_UPDT,           // 05
+        DCACHE_TLB2_READ,           // 06
+        DCACHE_TLB2_LL_WAIT,        // 07
+        DCACHE_TLB2_SC_WAIT,        // 08
+        DCACHE_TLB2_UPDT,           // 09
+        DCACHE_CTXT_SWITCH,         // 0a
+        DCACHE_ICACHE_FLUSH,        // 0b
+        DCACHE_DCACHE_FLUSH,        // 0c
+        DCACHE_ITLB_INVAL,          // 0d
+        DCACHE_DTLB_INVAL,          // 0e
+        DCACHE_ICACHE_INVAL,        // 0f
+        DCACHE_DCACHE_INVAL,        // 10
+        DCACHE_ICACHE_INVAL_PA,     // 0f
+        DCACHE_DCACHE_INVAL_PA,     // 10
+        DCACHE_DCACHE_SYNC,         // 11
+        DCACHE_LL_DIRTY_WAIT,       // 12
+        DCACHE_SC_DIRTY_WAIT,       // 13
+        DCACHE_WRITE_UPDT,          // 14
+        DCACHE_WRITE_DIRTY,         // 15
+        DCACHE_WRITE_REQ,           // 16
+        DCACHE_MISS_WAIT,           // 17
+        DCACHE_MISS_UPDT,           // 18
+        DCACHE_UNC_WAIT,            // 19
+        DCACHE_ERROR,               // 1a
+        DCACHE_CC_CHECK,            // 1b 
+        DCACHE_CC_INVAL,            // 1c
+        DCACHE_CC_UPDT,             // 1d
+        DCACHE_CC_NOP,              // 1e
+        DCACHE_TLB_CC_INVAL,        // 1f
+    };
+
+    enum cmd_fsm_state_e {      
+        CMD_IDLE,           // 00
+        CMD_ITLB_READ,      // 01
+        CMD_ITLB_ACC_LL,    // 02
+        CMD_ITLB_ACC_SC,    // 03
+        CMD_INS_MISS,       // 04
+        CMD_INS_UNC,        // 05
+        CMD_DTLB_READ,      // 06
+        CMD_DTLB_ACC_LL,    // 07
+        CMD_DTLB_ACC_SC,    // 08
+        CMD_DTLB_DIRTY_LL,  // 09
+        CMD_DTLB_DIRTY_SC,  // 0a
+        CMD_DATA_UNC,       // 0b
+        CMD_DATA_MISS,      // 0c
+        CMD_DATA_WRITE,     // 0d
+    };
+
+    enum rsp_fsm_state_e {       
+        RSP_IDLE,           // 00
+        RSP_ITLB_READ,      // 01
+        RSP_ITLB_ACC_LL,    // 02
+        RSP_ITLB_ACC_SC,    // 03
+        RSP_INS_MISS,       // 04
+        RSP_INS_UNC,        // 05
+        RSP_DTLB_READ,      // 06
+        RSP_DTLB_ACC_LL,    // 07
+        RSP_DTLB_ACC_SC,    // 08
+        RSP_DTLB_DIRTY_LL,  // 09
+        RSP_DTLB_DIRTY_SC,  // 0a
+        RSP_DATA_MISS,      // 0b
+        RSP_DATA_UNC,       // 0c
+        RSP_DATA_WRITE,     // 0d
+    };
+
+    enum tgt_fsm_state_e {  
+        TGT_IDLE,                   // 00
+        TGT_UPDT_WORD,              // 01
+        TGT_UPDT_DATA,              // 02
+        TGT_REQ_BROADCAST,          // 03
+        TGT_REQ_ICACHE,             // 04
+        TGT_REQ_DCACHE,             // 05
+        TGT_RSP_BROADCAST,          // 06
+        TGT_RSP_ICACHE,             // 07
+        TGT_RSP_DCACHE,             // 08
+    };
+
+    enum inval_itlb_fsm_state_e {
+        INVAL_ITLB_IDLE,        // 00
+        INVAL_ITLB_CHECK,       // 01
+        INVAL_ITLB_INVAL,       // 02
+        INVAL_ITLB_CLEAR,       // 03
+    };
+
+    enum inval_dtlb_fsm_state_e {
+        INVAL_DTLB_IDLE,        // 00
+        INVAL_DTLB_CHECK,       // 01
+        INVAL_DTLB_INVAL,       // 02
+        INVAL_DTLB_CLEAR,       // 03
+    };
+
+    enum cleanup_fsm_state_e {
+        CLEANUP_CMD,                // 00
+        CLEANUP_ICACHE_RSP,         // 01
+        CLEANUP_DCACHE_RSP,         // 02
+    };
+
+    // TLB Mode ITLB / DTLB / ICACHE / DCACHE
+    enum {          
+        ALL_DEACTIVE = 0x0000,   // TLBs disactive caches disactive
+        INS_TLB_MASK    = 0x8,
+        DATA_TLB_MASK   = 0x4,
+        INS_CACHE_MASK  = 0x2,
+        DATA_CACHE_MASK = 0x1,
+    };
+
+    // Error Type
+    enum mmu_error_type_e {
+        MMU_NONE                      = 0x0000, // None
+        MMU_WRITE_PT1_UNMAPPED 	      = 0x0001, // Write access of Page fault on Page Table 1          (non fatal error)
+        MMU_WRITE_PT2_UNMAPPED 	      = 0x0002, // Write access of Page fault on Page Table 2          (non fatal error)
+        MMU_WRITE_PRIVILEGE_VIOLATION = 0x0004, // Write access of Protected access in user mode       (user error)
+        MMU_WRITE_ACCES_VIOLATION 	  = 0x0008, // Write access of write access to a non writable page (user error)
+        MMU_WRITE_UNDEFINED_XTN 	  = 0x0020, // Write access of undefined external access address   (user error)
+        MMU_WRITE_PT1_ILLEGAL_ACCESS  = 0x0040, // Write access of Bus Error accessing Table 1         (kernel error)
+        MMU_WRITE_PT2_ILLEGAL_ACCESS  = 0x0080, // Write access of Bus Error accessing Table 2         (kernel error)
+        MMU_WRITE_DATA_ILLEGAL_ACCESS = 0x0100, // Write access of Bus Error in cache access           (kernel error)
+        MMU_READ_PT1_UNMAPPED 	      = 0x1001, // Read access of Page fault on Page Table 1  	       (non fatal error)
+        MMU_READ_PT2_UNMAPPED 	      = 0x1002, // Read access of Page fault on Page Table 2  	       (non fatal error)
+        MMU_READ_PRIVILEGE_VIOLATION  = 0x1004, // Read access of Protected access in user mode 	   (user error)
+        MMU_READ_EXEC_VIOLATION 	  = 0x1010, // Exec access to a non exec page                      (user error)
+        MMU_READ_UNDEFINED_XTN 	      = 0x1020, // Read access of Undefined external access address    (user error)
+        MMU_READ_PT1_ILLEGAL_ACCESS   = 0x1040, // Read access of Bus Error in Table1 access           (kernel error)
+        MMU_READ_PT2_ILLEGAL_ACCESS   = 0x1080, // Read access of Bus Error in Table2 access 	       (kernel error)
+        MMU_READ_DATA_ILLEGAL_ACCESS  = 0x1100, // Read access of Bus Error in cache access 	       (kernel error)
+    };
+
+    // Cleanup Type
+    enum {
+        NONE,           // reset 
+        CACHE_CLEANUP,  // cache cleanup
+        TLB_CLEANUP,    // TLB cleanup
+    };
+
+    enum transaction_type_e {
+        TYPE_DATA_UNC    = 0x0,  //     000
+        TYPE_DATA_MISS   = 0x1,  //     001
+        TYPE_INS_UNC     = 0x2,  //     010
+        TYPE_INS_MISS    = 0x3,  //     011
+        TYPE_INS_TLB_1   = 0x6,  //     110
+        TYPE_INS_TLB_2   = 0x7,  //     111   
+        TYPE_DATA_TLB_1  = 0x4,  //     100
+        TYPE_DATA_TLB_2  = 0x5,  //     101    
+        TYPE_INS_LL_ACC  = 0xe,  //  01 110
+        TYPE_INS_SC_ACC  = 0x16, //  10 110
+        TYPE_DATA_LL_ACC = 0xc,  //  01 100
+        TYPE_DATA_SC_ACC = 0x14, //  10 100
+        TYPE_DATA_LL_D   = 0x1c, //  11 100
+        TYPE_DATA_SC_D   = 0x24, // 100 100
+    };
+
+public:
+    sc_in<bool>                             p_clk;
+    sc_in<bool>                             p_resetn;
+    sc_in<bool>                             p_irq[iss_t::n_irq];
+    soclib::caba::VciInitiator<vci_param>   p_vci_ini_rw;
+    soclib::caba::VciInitiator<vci_param>   p_vci_ini_c;
+    soclib::caba::VciTarget<vci_param>      p_vci_tgt;
+
+private:
+    // STRUCTURAL PARAMETERS
+    soclib::common::AddressDecodingTable<uint32_t, bool>    m_cacheability_table;
+    const soclib::common::Segment                           m_segment;
+    iss_t                                                   m_iss;   
+    const vci_srcid_t                                       m_srcid_rw;
+    const vci_srcid_t                                       m_srcid_c;
+
+    const size_t  m_itlb_ways;
+    const size_t  m_itlb_sets;
+
+    const size_t  m_dtlb_ways;
+    const size_t  m_dtlb_sets;
+
+    const size_t  m_icache_ways;
+    const size_t  m_icache_sets;
+    const size_t  m_icache_yzmask;
+    const size_t  m_icache_words;
+
+    const size_t  m_dcache_ways;
+    const size_t  m_dcache_sets;
+    const size_t  m_dcache_yzmask;
+    const size_t  m_dcache_words;
+
+    //const size_t  m_write_buf_size;
+    const size_t  m_wbuf_nlines;  
+    const size_t  m_paddr_nbits;  
+
+    // instruction and data vcache tlb instances 
+    soclib::caba::GenericCcTlb<paddr_t>    icache_tlb;
+    soclib::caba::GenericCcTlb<paddr_t>    dcache_tlb;
+
+    sc_signal<vaddr_t>      r_mmu_ptpr;             // page table pointer register
+    sc_signal<int>          r_mmu_mode;             // tlb mode register
+    sc_signal<int>          r_mmu_params;           // mmu parameters register
+    sc_signal<int>          r_mmu_release;          // mmu release register
+    sc_signal<int>          r_mmu_word_lo;          // mmu misc data low
+    sc_signal<int>          r_mmu_word_hi;          // mmu mmu misc data hight
+
+    // DCACHE FSM REGISTERS
+    sc_signal<int>          r_dcache_fsm;               // state register
+    sc_signal<paddr_t>      r_dcache_paddr_save;        // physical address
+    sc_signal<data_t>       r_dcache_wdata_save;        // write data
+    sc_signal<data_t>       r_dcache_rdata_save;        // read data
+    sc_signal<type_t>       r_dcache_type_save;         // access type
+    sc_signal<vci_be_t>     r_dcache_be_save;           // byte enable
+    sc_signal<bool>         r_dcache_cached_save;       // used by the write buffer
+    sc_signal<paddr_t>      r_dcache_tlb_paddr;         // physical address of tlb miss
+    sc_signal<bool>         r_dcache_dirty_save;        // used for TLB dirty bit update
+    sc_signal<size_t>       r_dcache_tlb_set_save;      // used for TLB dirty bit update
+    sc_signal<size_t>       r_dcache_tlb_way_save;      // used for TLB dirty bit update
+    sc_signal<vaddr_t>      r_dcache_id1_save;          // used by the PT1 bypass
+    sc_signal<paddr_t>      r_dcache_ptba_save;         // used by the PT1 bypass
+    sc_signal<bool>         r_dcache_ptba_ok;           // used by the PT1 bypass
+    sc_signal<data_t>       r_dcache_pte_update;        // used for page table update
+    sc_signal<tag_t>        r_dcache_ppn_save;          // used for speculative cache access
+    sc_signal<tag_t>        r_dcache_vpn_save;          // used for speculative cache access
+    sc_signal<bool>         r_dtlb_translation_valid;   // used for speculative address
+    sc_signal<bool>         r_dcache_hit_p_save;        // used to save hit_p in case BIS
+
+    sc_signal<data_t>       r_dcache_error_type;        // software visible register
+    sc_signal<vaddr_t>      r_dcache_bad_vaddr;         // software visible register 
+
+    sc_signal<bool>         r_dcache_miss_req;          // used for cached read miss
+    sc_signal<bool>         r_dcache_unc_req;           // used for uncached read miss
+    sc_signal<bool>         r_dcache_write_req;         // used for write 
+    sc_signal<bool>         r_dcache_tlb_read_req;      // used for tlb ptba or pte read 
+    sc_signal<bool>         r_dcache_tlb_first_req;     // used for tlb ptba or pte read    
+    sc_signal<bool>         r_dcache_tlb_ll_acc_req;    // used for tlb entry type update
+    sc_signal<bool>         r_dcache_tlb_sc_acc_req;    // used for tlb entry type update
+    sc_signal<bool>         r_dcache_tlb_ll_dirty_req;  // used for tlb dirty bit update 
+    sc_signal<bool>         r_dcache_tlb_sc_dirty_req;  // used for tlb dirty bit update 
+    sc_signal<bool>         r_dcache_tlb_sc_fail;       // used for tlb entry sc failed
+    sc_signal<bool>         r_dcache_tlb_ptba_read;     // used for tlb ptba read when write dirty bit 
+    sc_signal<bool>         r_dcache_xtn_req;           // used for xtn write for ICACHE
+    
+    // coherence registers
+    sc_signal<int>          r_dcache_fsm_save;          // state save register
+    sc_signal<size_t>       r_dcache_way;
+    sc_signal<size_t>       r_dcache_set;
+    sc_signal<bool>         r_dcache_cleanup_req;
+    sc_signal<data_t>       r_dcache_cleanup_line;
+    sc_signal<int>          r_dcache_cleanup_type;       
+    sc_signal<bool>         r_dcache_inval_rsp;
+
+    // ICACHE FSM REGISTERS
+    sc_signal<int>          r_icache_fsm;               // state register
+    sc_signal<paddr_t>      r_icache_paddr_save;        // physical address
+    sc_signal<vaddr_t>      r_icache_id1_save;          // used by the PT1 bypass
+    sc_signal<paddr_t>      r_icache_ptba_save;         // used by the PT1 bypass
+    sc_signal<bool>         r_icache_ptba_ok;           // used by the PT1 bypass
+    sc_signal<data_t>       r_icache_pte_update;        // used for page table update
+    sc_signal<tag_t>        r_icache_ppn_save;          // used for speculative cache access
+    sc_signal<tag_t>        r_icache_vpn_save;          // used for speculative cache access
+    sc_signal<bool>         r_itlb_translation_valid;   // used for speculative physical address
+    sc_signal<vaddr_t>      r_icache_vaddr_req;          // used by the PT1 bypass
+
+    sc_signal<data_t>       r_icache_error_type;        // software visible registers
+    sc_signal<vaddr_t>      r_icache_bad_vaddr;         // software visible registers
+
+    sc_signal<bool>         r_icache_miss_req;          // used for cached read miss
+    sc_signal<bool>         r_icache_unc_req;           // used for uncached read miss
+    sc_signal<bool>         r_icache_tlb_read_req;      // used for tlb ptba or pte read
+    sc_signal<bool>         r_icache_tlb_first_req;     // used for tlb ptba or pte read    
+    sc_signal<bool>         r_icache_tlb_ll_req;        // used for tlb entry type update
+    sc_signal<bool>         r_icache_tlb_sc_req;        // used for tlb entry type update
+    sc_signal<bool>         r_icache_tlb_sc_fail;       // used for tlb entry sc failed
+
+    // coherence registers
+    sc_signal<int>          r_icache_fsm_save;
+    sc_signal<size_t>       r_icache_way;
+    sc_signal<size_t>       r_icache_set;
+    sc_signal<bool>         r_icache_cleanup_req;
+    sc_signal<data_t>       r_icache_cleanup_line;
+    sc_signal<int>          r_icache_cleanup_type;          
+    sc_signal<bool>         r_icache_inval_rsp;
+
+    // VCI_CMD FSM REGISTERS
+    sc_signal<int>          r_vci_cmd_fsm;
+    sc_signal<size_t>       r_vci_cmd_min;       
+    sc_signal<size_t>       r_vci_cmd_max;       
+    sc_signal<size_t>       r_vci_cmd_cpt;     
+
+    // VCI_RSP FSM REGISTERS
+    sc_signal<int>          r_vci_rsp_fsm;
+    sc_signal<size_t>       r_vci_rsp_cpt;
+    sc_signal<bool>         r_vci_rsp_ins_ok;
+    sc_signal<bool>         r_vci_rsp_data_ok;
+    sc_signal<bool>         r_vci_rsp_ins_error;
+    sc_signal<bool>         r_vci_rsp_data_error;
+
+    data_t                  *r_icache_miss_buf;    
+    data_t                  *r_dcache_miss_buf;  
+
+    // VCI_TGT FSM REGISTERS
+    data_t                  *r_tgt_buf;
+    bool                    *r_tgt_val;
+
+    sc_signal<int>          r_vci_tgt_fsm;
+    sc_signal<paddr_t>      r_tgt_addr;
+    sc_signal<size_t>       r_tgt_word;
+    sc_signal<bool>         r_tgt_update;
+    sc_signal<bool>         r_tgt_broadcast;
+    sc_signal<vci_srcid_t>  r_tgt_srcid;
+    sc_signal<vci_pktid_t>  r_tgt_pktid;
+    sc_signal<vci_trdid_t>  r_tgt_trdid;
+    sc_signal<vci_plen_t>   r_tgt_plen;
+    sc_signal<bool>         r_tgt_icache_req;
+    sc_signal<bool>         r_tgt_dcache_req;
+    sc_signal<bool>         r_tgt_icache_rsp;
+    sc_signal<bool>         r_tgt_dcache_rsp;
+    sc_signal<size_t>       r_ccinval_itlb_cpt;
+    sc_signal<size_t>       r_ccinval_dtlb_cpt;
+
+    // INVAL CHECK FSM
+    sc_signal<int>          r_inval_itlb_fsm;          
+    sc_signal<bool>         r_icache_tlb_inval_req;    
+    sc_signal<bool>         r_itlb_cc_check_end;
+    sc_signal<size_t>       r_ccinval_itlb_way; 
+    sc_signal<size_t>       r_ccinval_itlb_set; 
+    sc_signal<bool>         r_icache_inval_tlb_rsp;
+    sc_signal<paddr_t>      r_icache_tlb_nline;
+    sc_signal<bool>         r_icache_cc_hit_t;
+
+    sc_signal<int>          r_inval_dtlb_fsm;  
+    sc_signal<bool>         r_dcache_tlb_inval_req;    
+    sc_signal<bool>         r_dtlb_cc_check_end;
+    sc_signal<size_t>       r_ccinval_dtlb_way; 
+    sc_signal<size_t>       r_ccinval_dtlb_set; 
+    sc_signal<bool>         r_dcache_inval_tlb_rsp;
+    sc_signal<paddr_t>      r_dcache_tlb_nline;
+    sc_signal<bool>         r_dcache_cc_hit_t;
+
+    // CLEANUP CHECK FSM
+    sc_signal<int>          r_cleanup_fsm;          
+
+    MultiWriteBuffer<paddr_t>   r_wbuf;
+    GenericCache<paddr_t>       r_icache;
+    GenericCache<paddr_t>       r_dcache;
+
+    // Activity counters
+    uint32_t m_cpt_dcache_data_read;        // DCACHE DATA READ
+    uint32_t m_cpt_dcache_data_write;       // DCACHE DATA WRITE
+    uint32_t m_cpt_dcache_dir_read;         // DCACHE DIR READ
+    uint32_t m_cpt_dcache_dir_write;        // DCACHE DIR WRITE
+
+    uint32_t m_cpt_icache_data_read;        // ICACHE DATA READ
+    uint32_t m_cpt_icache_data_write;       // ICACHE DATA WRITE
+    uint32_t m_cpt_icache_dir_read;         // ICACHE DIR READ
+    uint32_t m_cpt_icache_dir_write;        // ICACHE DIR WRITE
+
+    uint32_t m_cpt_frz_cycles;	            // number of cycles where the cpu is frozen
+    uint32_t m_cpt_total_cycles;	        // total number of cycles 
+
+    // Cache activity counters
+    uint32_t m_cpt_read;                    // total number of read data
+    uint32_t m_cpt_write;                   // total number of write data
+    uint32_t m_cpt_data_miss;               // number of read miss
+    uint32_t m_cpt_ins_miss;                // number of instruction miss
+    uint32_t m_cpt_unc_read;                // number of read uncached
+    uint32_t m_cpt_write_cached;            // number of cached write
+    uint32_t m_cpt_ins_read;                // number of instruction read    
+
+    uint32_t m_cost_write_frz;              // number of frozen cycles related to write buffer of cache         
+    uint32_t m_cost_data_miss_frz;          // number of frozen cycles related to data miss of cache
+    uint32_t m_cost_unc_read_frz;           // number of frozen cycles related to uncached read of cache
+    uint32_t m_cost_ins_miss_frz;           // number of frozen cycles related to ins miss of cache
+    uint32_t m_cost_cc_wait_frz;            // number of frozen cycles related to cc check 
+
+    uint32_t m_cpt_imiss_transaction;       // number of VCI instruction miss transactions
+    uint32_t m_cpt_dmiss_transaction;       // number of VCI data miss transactions
+    uint32_t m_cpt_unc_transaction;         // number of VCI uncached read transactions
+    uint32_t m_cpt_write_transaction;       // number of VCI write transactions
+
+    uint32_t m_cost_imiss_transaction;      // cumulated duration for VCI IMISS transactions
+    uint32_t m_cost_dmiss_transaction;      // cumulated duration for VCI DMISS transactions
+    uint32_t m_cost_unc_transaction;        // cumulated duration for VCI UNC transactions
+    uint32_t m_cost_write_transaction;      // cumulated duration for VCI WRITE transactions
+    uint32_t m_length_write_transaction;    // cumulated length for VCI WRITE transactions
+
+    // TLB activity counters
+    uint32_t m_cpt_ins_tlb_read;            // number of instruction tlb read
+    uint32_t m_cpt_ins_tlb_miss;            // number of instruction tlb miss
+    uint32_t m_cpt_ins_tlb_write_et;        // number of instruction tlb write ET
+
+    uint32_t m_cpt_data_tlb_read;           // number of data tlb read
+    uint32_t m_cpt_data_tlb_miss;           // number of data tlb miss
+    uint32_t m_cpt_data_tlb_write_et;       // number of data tlb write ET
+    uint32_t m_cpt_data_tlb_write_dirty;    // number of data tlb write dirty
+    
+    uint32_t m_cost_ins_tlb_miss_frz;       // number of frozen cycles related to instruction tlb miss
+    uint32_t m_cost_data_tlb_miss_frz;      // number of frozen cycles related to data tlb miss
+    uint32_t m_cost_ins_tlb_flush_frz;      // number of cycles for instruction tlb flush 
+    uint32_t m_cost_data_tlb_flush_frz;     // number of cycles for data tlb flush
+    uint32_t m_cost_ins_cache_flush_frz;    // number of cycles for instruction cache flush 
+    uint32_t m_cost_data_cache_flush_frz;   // number of cycles for data cache flush 
+    uint32_t m_cost_data_waste_wait_frz;
+
+    uint32_t m_cpt_itlbmiss_transaction;    // number of itlb miss transactions
+    uint32_t m_cpt_itlb_write_transaction;  // number of itlb write ET transactions
+    uint32_t m_cpt_dtlbmiss_transaction;    // number of dtlb miss transactions
+    uint32_t m_cpt_dtlb_write_transaction;  // number of dtlb write ET and dirty transactions
+
+    uint32_t m_cost_itlbmiss_transaction;   // cumulated duration for VCI instruction TLB miss transactions
+    uint32_t m_cost_itlb_write_transaction; // cumulated duration for VCI instruction TLB write ET transactions
+    uint32_t m_cost_dtlbmiss_transaction;   // cumulated duration for VCI data TLB miss transactions
+    uint32_t m_cost_dtlb_write_transaction; // cumulated duration for VCI data TLB write transactions
+
+    uint32_t m_cpt_cc_update;               // number of coherence update packets 
+    uint32_t m_cpt_cc_inval;                // number of coherence inval packets
+    uint32_t m_cpt_cc_broadcast;            // number of coherence inval packets
+
+    uint32_t m_cost_cc_update_frz;          // number of waiting cycles for coherence update
+    uint32_t m_cost_cc_inval_frz;           // number of waiting cycles for coherence invalidate
+
+protected:
+    SC_HAS_PROCESS(VciCcVCacheWrapperMulti);
+
+public:
+    VciCcVCacheWrapperMulti(
+        sc_module_name insname,
+        int proc_id,
+        const soclib::common::MappingTable &mtp,
+        const soclib::common::MappingTable &mtc,
+        const soclib::common::IntTab &initiator_index_rw,
+        const soclib::common::IntTab &initiator_index_c,
+        const soclib::common::IntTab &target_index,
+        size_t itlb_ways,
+        size_t itlb_sets,
+        size_t dtlb_ways,
+        size_t dtlb_sets,
+        size_t icache_ways,
+        size_t icache_sets,
+        size_t icache_words,
+        size_t dcache_ways,
+        size_t dcache_sets,
+        size_t dcache_words,
+        size_t wbuf_nwords,
+        size_t wbuf_nlines );
+
+    ~VciCcVCacheWrapperMulti();
+
+    void print_cpi();
+    void print_stats();
+
+private:
+    void transition();
+    void genMoore();
+
+    soclib_static_assert((int)iss_t::SC_ATOMIC == (int)vci_param::STORE_COND_ATOMIC);
+    soclib_static_assert((int)iss_t::SC_NOT_ATOMIC == (int)vci_param::STORE_COND_NOT_ATOMIC);
+};
+
+}}
+
+#endif /* SOCLIB_CABA_VCI_CC_VCACHE_WRAPPER_MULTI_H */
+
+// Local Variables:
+// tab-width: 4
+// c-basic-offset: 4
+// c-file-offsets:((innamespace . 0)(inline-open . 0))
+// indent-tabs-mode: nil
+// End:
+
+// vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4
+
Index: branches/v4/modules/vci_cc_vcache_wrapper_multi/caba/source/src/vci_cc_vcache_wrapper_multi.cpp
===================================================================
--- branches/v4/modules/vci_cc_vcache_wrapper_multi/caba/source/src/vci_cc_vcache_wrapper_multi.cpp	(revision 371)
+++ branches/v4/modules/vci_cc_vcache_wrapper_multi/caba/source/src/vci_cc_vcache_wrapper_multi.cpp	(revision 371)
@@ -0,0 +1,4953 @@
+/* -*- c++ -*-
+ * File : vci_cc_vcache_wrapper_multi.cpp
+ * Copyright (c) UPMC, Lip6, SoC
+ * Authors : Alain GREINER, Yang GAO
+ *
+ * SOCLIB_LGPL_HEADER_BEGIN
+ * 
+ * This file is part of SoCLib, GNU LGPLv2.1.
+ * 
+ * SoCLib is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU Lesser General Public License as published
+ * by the Free Software Foundation; version 2.1 of the License.
+ * 
+ * SoCLib is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * Lesser General Public License for more details.
+ * 
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with SoCLib; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301 USA
+ * 
+ * SOCLIB_LGPL_HEADER_END
+ */
+
+#include <cassert>
+#include "arithmetics.h"
+#include "../include/vci_cc_vcache_wrapper_multi.h"
+
+namespace soclib { 
+namespace caba {
+
+//#define SOCLIB_MODULE_DEBUG
+#ifdef SOCLIB_MODULE_DEBUG
+namespace {
+const char *icache_fsm_state_str[] = {
+        "ICACHE_IDLE",
+        "ICACHE_BIS",       
+        "ICACHE_TLB1_READ",  
+        "ICACHE_TLB1_LL_WAIT",        
+        "ICACHE_TLB1_SC_WAIT",     
+        "ICACHE_TLB1_UPDT",  
+        "ICACHE_TLB2_READ",  
+        "ICACHE_TLB2_LL_WAIT",        
+        "ICACHE_TLB2_SC_WAIT",     
+        "ICACHE_TLB2_UPDT",  
+        "ICACHE_TLB_FLUSH", 
+        "ICACHE_CACHE_FLUSH", 
+        "ICACHE_TLB_INVAL",  
+        "ICACHE_CACHE_INVAL",
+	    "ICACHE_CACHE_INVAL_PA",
+        "ICACHE_MISS_WAIT",
+        "ICACHE_UNC_WAIT",  
+        "ICACHE_MISS_UPDT",  
+        "ICACHE_ERROR", 
+        "ICACHE_CC_INVAL",
+        "ICACHE_TLB_CC_INVAL",
+    };
+const char *dcache_fsm_state_str[] = {
+        "DCACHE_IDLE",       
+        "DCACHE_BIS",     
+        "DCACHE_TLB1_READ",  
+        "DCACHE_TLB1_LL_WAIT",
+        "DCACHE_TLB1_SC_WAIT",
+        "DCACHE_TLB1_UPDT",  
+        "DCACHE_TLB2_READ",  
+        "DCACHE_TLB2_LL_WAIT",
+        "DCACHE_TLB2_SC_WAIT", 
+        "DCACHE_TLB2_UPDT",   
+        "DCACHE_CTXT_SWITCH",   
+        "DCACHE_ICACHE_FLUSH", 
+        "DCACHE_DCACHE_FLUSH", 
+        "DCACHE_ITLB_INVAL",
+        "DCACHE_DTLB_INVAL",
+        "DCACHE_ICACHE_INVAL",
+        "DCACHE_DCACHE_INVAL",
+    	"DCACHE_ICACHE_INVAL_PA",
+	    "DCACHE_DCACHE_INVAL_PA",
+        "DCACHE_DCACHE_SYNC",
+        "DCACHE_LL_DIRTY_WAIT",
+        "DCACHE_SC_DIRTY_WAIT",  
+        "DCACHE_WRITE_UPDT", 
+        "DCACHE_WRITE_DIRTY",
+        "DCACHE_WRITE_REQ",  
+        "DCACHE_MISS_WAIT",  
+        "DCACHE_MISS_UPDT",  
+        "DCACHE_UNC_WAIT",   
+        "DCACHE_ERROR",  
+        "DCACHE_CC_CHECK",
+        "DCACHE_CC_INVAL",
+        "DCACHE_CC_UPDT",
+        "DCACHE_CC_NOP",
+        "DCACHE_TLB_CC_INVAL",
+    };
+const char *cmd_fsm_state_str[] = {
+        "CMD_IDLE",           
+        "CMD_ITLB_READ",      
+        "CMD_ITLB_ACC_LL",
+        "CMD_ITLB_ACC_SC",      
+        "CMD_INS_MISS",     
+        "CMD_INS_UNC",     
+        "CMD_DTLB_READ",  
+        "CMD_DTLB_ACC_LL",
+        "CMD_DTLB_ACC_SC",
+        "CMD_DTLB_DIRTY_LL",
+        "CMD_DTLB_DIRTY_SC",
+        "CMD_DATA_UNC",     
+        "CMD_DATA_MISS",    
+        "CMD_DATA_WRITE",    
+    };
+const char *rsp_fsm_state_str[] = {
+        "RSP_IDLE",                  
+        "RSP_ITLB_READ",             
+        "RSP_ITLB_ACC_LL",
+        "RSP_ITLB_ACC_SC",               
+        "RSP_INS_MISS",   
+        "RSP_INS_UNC",           
+        "RSP_DTLB_READ", 
+        "RSP_DTLB_ACC_LL",
+        "RSP_DTLB_ACC_SC",          
+        "RSP_DTLB_DIRTY_LL",
+        "RSP_DTLB_DIRTY_SC",
+        "RSP_DATA_MISS",             
+        "RSP_DATA_UNC",              
+        "RSP_DATA_WRITE",   
+    };
+const char *tgt_fsm_state_str[] = {
+        "TGT_IDLE",
+        "TGT_UPDT_WORD",
+        "TGT_UPDT_DATA",
+        "TGT_REQ_BROADCAST",
+        "TGT_REQ_ICACHE",
+        "TGT_REQ_DCACHE",
+        "TGT_RSP_BROADCAST",
+        "TGT_RSP_ICACHE",
+        "TGT_RSP_DCACHE",
+    };	
+const char *inval_itlb_fsm_state_str[] = {
+        "INVAL_ITLB_IDLE",        
+        "INVAL_ITLB_CHECK"  , 
+        "INVAL_ITLB_INVAL",      
+        "INVAL_ITLB_CLEAR",           
+    };
+const char *inval_dtlb_fsm_state_str[] = {
+        "INVAL_DTLB_IDLE",        
+        "INVAL_DTLB_CHECK", 
+        "INVAL_DTLB_INVAL",    
+        "INVAL_DTLB_CLEAR",         
+    };
+const char *cleanup_fsm_state_str[] = {
+        "CLEANUP_CMD",
+	    "CLEANUP_ICACHE_RSP",
+        "CLEANUP_DCACHE_RSP",
+    };
+}
+#endif
+
+#define tmpl(...)  template<typename vci_param, typename iss_t> __VA_ARGS__ VciCcVCacheWrapperMulti<vci_param, iss_t>
+
+using soclib::common::uint32_log2;
+
+/***********************************************/
+tmpl(/**/)::VciCcVCacheWrapperMulti(
+    sc_module_name name,
+    int proc_id,
+    const soclib::common::MappingTable &mtp,
+    const soclib::common::MappingTable &mtc,
+    const soclib::common::IntTab &initiator_index_rw,
+    const soclib::common::IntTab &initiator_index_c,
+    const soclib::common::IntTab &target_index,
+    size_t itlb_ways,
+    size_t itlb_sets,
+    size_t dtlb_ways,
+    size_t dtlb_sets,
+    size_t icache_ways,
+    size_t icache_sets,
+    size_t icache_words,
+    size_t dcache_ways,
+    size_t dcache_sets,
+    size_t dcache_words,
+    size_t wbuf_nwords,
+    size_t wbuf_nlines )
+/***********************************************/
+    : soclib::caba::BaseModule(name),
+
+      p_clk("clk"),
+      p_resetn("resetn"),
+      p_vci_ini_rw("vci_ini_rw"),
+      p_vci_ini_c("vci_ini_c"),
+      p_vci_tgt("vci_tgt"),
+
+      m_cacheability_table(mtp.getCacheabilityTable()),
+      m_segment(mtc.getSegment(target_index)),
+      m_iss(this->name(), proc_id),
+      m_srcid_rw(mtp.indexForId(initiator_index_rw)),
+      m_srcid_c(mtp.indexForId(initiator_index_c)),
+
+      m_itlb_ways(itlb_ways),
+      m_itlb_sets(itlb_sets),
+
+      m_dtlb_ways(dtlb_ways),
+      m_dtlb_sets(dtlb_sets),
+
+      m_icache_ways(icache_ways),
+      m_icache_sets(icache_sets),
+      m_icache_yzmask((~0)<<(uint32_log2(icache_words) + 2)),
+      m_icache_words(icache_words),
+
+      m_dcache_ways(dcache_ways),
+      m_dcache_sets(dcache_sets),
+      m_dcache_yzmask((~0)<<(uint32_log2(dcache_words) + 2)),
+      m_dcache_words(dcache_words),
+
+      m_wbuf_nlines(wbuf_nlines),
+      m_paddr_nbits(vci_param::N),
+
+      icache_tlb(itlb_ways,itlb_sets,vci_param::N),
+      dcache_tlb(dtlb_ways,dtlb_sets,vci_param::N),
+
+      r_dcache_fsm("r_dcache_fsm"),
+      r_dcache_paddr_save("r_dcache_paddr_save"),
+      r_dcache_wdata_save("r_dcache_wdata_save"),
+      r_dcache_rdata_save("r_dcache_rdata_save"),
+      r_dcache_type_save("r_dcache_type_save"),
+      r_dcache_be_save("r_dcache_be_save"),
+      r_dcache_cached_save("r_dcache_cached_save"),
+      r_dcache_tlb_paddr("r_dcache_tlb_paddr"),
+      r_dcache_miss_req("r_dcache_miss_req"),
+      r_dcache_unc_req("r_dcache_unc_req"),
+      r_dcache_write_req("r_dcache_write_req"),
+      r_dcache_tlb_read_req("r_dcache_tlb_read_req"),
+      r_dcache_tlb_ll_acc_req("r_dcache_tlb_ll_acc_req"),
+      r_dcache_tlb_sc_acc_req("r_dcache_tlb_sc_acc_req"),
+      r_dcache_tlb_ll_dirty_req("r_dcache_tlb_ll_dirty_req"),
+      r_dcache_tlb_sc_dirty_req("r_dcache_tlb_sc_dirty_req"),
+      r_dcache_tlb_ptba_read("r_dcache_tlb_ptba_read"),
+      r_dcache_xtn_req("r_dcache_xtn_req"),
+
+      r_icache_fsm("r_icache_fsm"),
+      r_icache_paddr_save("r_icache_paddr_save"),
+      r_icache_miss_req("r_icache_miss_req"),
+      r_icache_unc_req("r_icache_unc_req"),
+      r_icache_tlb_read_req("r_icache_tlb_read_req"),
+      r_icache_tlb_ll_req("r_icache_tlb_ll_req"),
+      r_icache_tlb_sc_req("r_icache_tlb_sc_req"),
+
+      r_vci_cmd_fsm("r_vci_cmd_fsm"),
+      r_vci_cmd_min("r_vci_cmd_min"),
+      r_vci_cmd_max("r_vci_cmd_max"),
+      r_vci_cmd_cpt("r_vci_cmd_cpt"),
+
+      r_vci_rsp_fsm("r_vci_rsp_fsm"),
+      r_vci_rsp_cpt("r_vci_rsp_cpt"),
+      r_vci_rsp_ins_error("r_vci_rsp_ins_error"),
+      r_vci_rsp_data_error("r_vci_rsp_data_error"),
+
+      r_vci_tgt_fsm("r_vci_tgt_fsm"),
+      r_tgt_addr("r_tgt_addr"),
+      r_tgt_word("r_tgt_word"),
+      r_tgt_update("r_tgt_update"),
+      r_tgt_broadcast("r_tgt_broadcast"),
+      r_tgt_srcid("r_tgt_srcid"),
+      r_tgt_pktid("r_tgt_pktid"),
+      r_tgt_trdid("r_tgt_trdid"),
+      r_tgt_icache_req("r_tgt_icache_req"),
+      r_tgt_dcache_req("r_tgt_dcache_req"),
+      r_cleanup_fsm("r_cleanup_fsm"),
+
+      r_wbuf("wbuf", wbuf_nwords, wbuf_nlines ),
+      r_icache("icache", icache_ways, icache_sets, icache_words),
+      r_dcache("dcache", dcache_ways, dcache_sets, dcache_words)
+{
+    r_icache_miss_buf = new data_t[icache_words];
+    r_dcache_miss_buf = new data_t[dcache_words];
+    r_tgt_buf         = new data_t[dcache_words];
+    r_tgt_val         = new bool[dcache_words];
+
+    SC_METHOD(transition);
+    dont_initialize();
+    sensitive << p_clk.pos();
+  
+    SC_METHOD(genMoore);
+    dont_initialize();
+    sensitive << p_clk.neg();
+
+    typename iss_t::CacheInfo cache_info;
+    cache_info.has_mmu = true;
+    cache_info.icache_line_size = icache_words*sizeof(data_t);
+    cache_info.icache_assoc = icache_ways;
+    cache_info.icache_n_lines = icache_sets;
+    cache_info.dcache_line_size = dcache_words*sizeof(data_t);
+    cache_info.dcache_assoc = dcache_ways;
+    cache_info.dcache_n_lines = dcache_sets;
+    m_iss.setCacheInfo(cache_info);
+}
+
+/////////////////////////////////////
+tmpl(/**/)::~VciCcVCacheWrapperMulti()
+/////////////////////////////////////
+{
+    delete [] r_icache_miss_buf;
+    delete [] r_dcache_miss_buf;
+    delete [] r_tgt_val;
+    delete [] r_tgt_buf;
+}
+
+////////////////////////
+tmpl(void)::print_cpi()
+////////////////////////
+{
+    std::cout << name() << " CPI = " 
+        << (float)m_cpt_total_cycles/(m_cpt_total_cycles - m_cpt_frz_cycles) << std::endl ;
+}
+
+////////////////////////
+tmpl(void)::print_stats()
+////////////////////////
+{
+    float run_cycles = (float)(m_cpt_total_cycles - m_cpt_frz_cycles);
+    std::cout << name() << std::endl
+              << "- CPI                    = " << (float)m_cpt_total_cycles/run_cycles << std::endl 
+              << "- READ RATE              = " << (float)m_cpt_read/run_cycles << std::endl 
+              << "- WRITE RATE             = " << (float)m_cpt_write/run_cycles << std::endl
+              << "- UNCACHED READ RATE     = " << (float)m_cpt_unc_read/m_cpt_read << std::endl 
+              << "- CACHED WRITE RATE      = " << (float)m_cpt_write_cached/m_cpt_write << std::endl 
+              << "- IMISS_RATE             = " << (float)m_cpt_ins_miss/m_cpt_ins_read << std::endl    
+              << "- DMISS RATE             = " << (float)m_cpt_data_miss/(m_cpt_read-m_cpt_unc_read) << std::endl 
+              << "- INS MISS COST          = " << (float)m_cost_ins_miss_frz/m_cpt_ins_miss << std::endl
+              << "- IMISS TRANSACTION      = " << (float)m_cost_imiss_transaction/m_cpt_imiss_transaction << std::endl
+              << "- DMISS COST             = " << (float)m_cost_data_miss_frz/m_cpt_data_miss << std::endl
+              << "- DMISS TRANSACTION      = " << (float)m_cost_dmiss_transaction/m_cpt_dmiss_transaction << std::endl
+              << "- UNC COST               = " << (float)m_cost_unc_read_frz/m_cpt_unc_read << std::endl
+              << "- UNC TRANSACTION        = " << (float)m_cost_unc_transaction/m_cpt_unc_transaction << std::endl
+              << "- WRITE COST             = " << (float)m_cost_write_frz/m_cpt_write << std::endl
+              << "- WRITE TRANSACTION      = " << (float)m_cost_write_transaction/m_cpt_write_transaction << std::endl
+              << "- WRITE LENGTH           = " << (float)m_length_write_transaction/m_cpt_write_transaction << std::endl
+              << "- INS TLB MISS RATE      = " << (float)m_cpt_ins_tlb_miss/m_cpt_ins_tlb_read << std::endl
+              << "- DATA TLB MISS RATE     = " << (float)m_cpt_data_tlb_miss/m_cpt_data_tlb_read << std::endl
+              << "- ITLB MISS TRANSACTION  = " << (float)m_cost_itlbmiss_transaction/m_cpt_itlbmiss_transaction << std::endl
+              << "- ITLB WRITE TRANSACTION = " << (float)m_cost_itlb_write_transaction/m_cpt_itlb_write_transaction << std::endl
+              << "- ITLB MISS COST         = " << (float)m_cost_ins_tlb_miss_frz/(m_cpt_ins_tlb_miss+m_cpt_ins_tlb_write_et) << std::endl
+              << "- DTLB MISS TRANSACTION  = " << (float)m_cost_dtlbmiss_transaction/m_cpt_dtlbmiss_transaction << std::endl
+              << "- DTLB WRITE TRANSACTION = " << (float)m_cost_dtlb_write_transaction/m_cpt_dtlb_write_transaction << std::endl
+              << "- DTLB MISS COST         = " << (float)m_cost_data_tlb_miss_frz/(m_cpt_data_tlb_miss+m_cpt_data_tlb_write_et+m_cpt_data_tlb_write_dirty) << std::endl;
+}
+
+/*************************************************/
+tmpl(void)::transition()
+/*************************************************/
+{
+    if ( ! p_resetn.read() ) 
+    {
+        m_iss.reset();
+
+        r_dcache_fsm = DCACHE_IDLE;
+        r_icache_fsm = ICACHE_IDLE;
+        r_vci_cmd_fsm = CMD_IDLE;
+        r_vci_rsp_fsm = RSP_IDLE;
+        r_vci_tgt_fsm = TGT_IDLE;
+        r_inval_itlb_fsm = INVAL_ITLB_IDLE;          
+        r_inval_dtlb_fsm = INVAL_DTLB_IDLE;     
+        r_cleanup_fsm = CLEANUP_CMD;
+
+        // write buffer & caches
+        r_wbuf.reset();
+        r_icache.reset();
+        r_dcache.reset();
+
+        icache_tlb.reset();    
+        dcache_tlb.reset();    
+
+        r_mmu_mode = ALL_DEACTIVE;
+        r_mmu_params = (uint32_log2(m_dtlb_ways) << 29)   | (uint32_log2(m_dtlb_sets) << 25)   |
+                       (uint32_log2(m_dcache_ways) << 22) | (uint32_log2(m_dcache_sets) << 18) |
+                       (uint32_log2(m_itlb_ways) << 15)   | (uint32_log2(m_itlb_sets) << 11)   |
+                       (uint32_log2(m_icache_ways) << 8)  | (uint32_log2(m_icache_sets) << 4)  |
+                       (uint32_log2(m_icache_words * 4));
+        r_mmu_release = (uint32_t)(1 << 16) | 0x1;
+
+        r_icache_miss_req          = false;
+        r_icache_unc_req           = false;
+        r_icache_tlb_read_req      = false;
+        r_icache_tlb_first_req     = false;
+        r_icache_tlb_ll_req        = false;
+        r_icache_tlb_sc_req        = false;
+        r_icache_tlb_sc_fail       = false;
+
+        r_dcache_miss_req          = false;
+        r_dcache_unc_req           = false;
+        r_dcache_write_req         = false;
+        r_dcache_tlb_read_req      = false;
+        r_dcache_tlb_first_req     = false;
+        r_dcache_tlb_ll_acc_req    = false;
+        r_dcache_tlb_sc_acc_req    = false;
+        r_dcache_tlb_ll_dirty_req  = false;
+        r_dcache_tlb_sc_dirty_req  = false;
+        r_dcache_tlb_sc_fail       = false;
+        r_dcache_tlb_ptba_read     = false;
+        r_dcache_xtn_req           = false;
+
+        r_icache_cleanup_req       = false;
+        r_icache_cleanup_type      = NONE;
+    
+        r_dcache_cleanup_req       = false;
+        r_dcache_cleanup_type      = NONE; 
+ 
+        r_tgt_icache_req           = false;
+        r_tgt_dcache_req           = false;
+        r_tgt_icache_rsp           = false;
+        r_tgt_dcache_rsp           = false;
+        r_ccinval_itlb_cpt         = 0; 
+        r_ccinval_dtlb_cpt         = 0; 
+
+        r_icache_cc_hit_t          = false;
+        r_dcache_cc_hit_t          = false;
+
+        r_tgt_broadcast            = false;
+        r_tgt_update               = false; 
+ 
+        r_icache_inval_rsp         = false;
+        r_dcache_inval_rsp         = false;
+
+        r_icache_tlb_inval_req     = false;    
+        r_itlb_cc_check_end        = false;
+        r_icache_inval_tlb_rsp     = false;
+        
+        r_dcache_tlb_inval_req     = false;    
+        r_dtlb_cc_check_end        = false;
+        r_dcache_inval_tlb_rsp     = false;
+
+        r_dcache_dirty_save      = false;
+        r_dcache_hit_p_save      = false;
+
+        r_vci_rsp_ins_error      = false;
+        r_vci_rsp_data_error     = false;
+
+        r_icache_id1_save        = 0;
+        r_icache_ppn_save        = 0;
+        r_icache_vpn_save        = 0;
+        r_itlb_translation_valid = false;
+
+        r_dcache_id1_save        = 0;
+        r_dcache_ppn_save        = 0;
+        r_dcache_vpn_save        = 0;
+        r_dtlb_translation_valid = false;
+
+        r_icache_ptba_ok         = false;
+        r_dcache_ptba_ok         = false;
+
+        r_icache_error_type      = MMU_NONE;
+        r_dcache_error_type      = MMU_NONE;
+
+        // activity counters
+        m_cpt_dcache_data_read  = 0;
+        m_cpt_dcache_data_write = 0;
+        m_cpt_dcache_dir_read   = 0;
+        m_cpt_dcache_dir_write  = 0;
+        m_cpt_icache_data_read  = 0;
+        m_cpt_icache_data_write = 0;
+        m_cpt_icache_dir_read   = 0;
+        m_cpt_icache_dir_write  = 0;
+
+	    m_cpt_frz_cycles   = 0;
+        m_cpt_total_cycles = 0;
+
+        m_cpt_read         = 0;
+        m_cpt_write        = 0;
+        m_cpt_data_miss    = 0;
+        m_cpt_ins_miss     = 0;
+        m_cpt_unc_read     = 0;
+        m_cpt_write_cached = 0;
+        m_cpt_ins_read     = 0;  
+
+        m_cost_write_frz     = 0;
+        m_cost_data_miss_frz = 0;
+        m_cost_unc_read_frz  = 0;
+        m_cost_ins_miss_frz  = 0;
+
+        m_cpt_imiss_transaction = 0;
+        m_cpt_dmiss_transaction = 0;
+        m_cpt_unc_transaction   = 0;
+        m_cpt_write_transaction = 0;
+
+        m_cost_imiss_transaction   = 0;
+        m_cost_dmiss_transaction   = 0;
+        m_cost_unc_transaction     = 0;
+        m_cost_write_transaction   = 0;
+        m_length_write_transaction = 0;
+
+        m_cpt_ins_tlb_read         = 0;             
+        m_cpt_ins_tlb_miss         = 0;             
+        m_cpt_ins_tlb_write_et     = 0;         
+
+        m_cpt_data_tlb_read        = 0;           
+        m_cpt_data_tlb_miss        = 0;           
+        m_cpt_data_tlb_write_et    = 0;       
+        m_cpt_data_tlb_write_dirty = 0;    
+
+        m_cost_ins_tlb_miss_frz    = 0;      
+        m_cost_data_tlb_miss_frz   = 0;      
+
+        m_cpt_itlbmiss_transaction   = 0;    
+        m_cpt_itlb_write_transaction = 0;  
+        m_cpt_dtlbmiss_transaction   = 0;  
+        m_cpt_dtlb_write_transaction = 0;  
+ 
+        m_cost_itlbmiss_transaction   = 0;   
+        m_cost_itlb_write_transaction = 0;  
+        m_cost_dtlbmiss_transaction   = 0;   
+        m_cost_dtlb_write_transaction = 0;  
+        return;
+    }
+
+#ifdef SOCLIB_MODULE_DEBUG
+std::cout << name() << "cycle = " << m_cpt_total_cycles  
+          << " tgt fsm: " << tgt_fsm_state_str[r_vci_tgt_fsm]
+          << " dcache fsm: " << dcache_fsm_state_str[r_dcache_fsm]
+          << " icache fsm: " << icache_fsm_state_str[r_icache_fsm]
+          << " cmd fsm: " << cmd_fsm_state_str[r_vci_cmd_fsm]
+          << " rsp fsm: " << rsp_fsm_state_str[r_vci_rsp_fsm] << std::endl
+          << " itlb inval fsm: " << inval_itlb_fsm_state_str[r_inval_itlb_fsm]
+          << " dtlb inval fsm: " << inval_dtlb_fsm_state_str[r_inval_dtlb_fsm]
+          << " cleanup fsm: " << cleanup_fsm_state_str[r_cleanup_fsm] << std::endl;
+#endif
+
+    m_cpt_total_cycles++;
+
+    typename iss_t::InstructionRequest ireq = ISS_IREQ_INITIALIZER;
+    typename iss_t::InstructionResponse irsp = ISS_IRSP_INITIALIZER;
+
+    typename iss_t::DataRequest dreq = ISS_DREQ_INITIALIZER;
+    typename iss_t::DataResponse drsp = ISS_DRSP_INITIALIZER;
+
+    m_iss.getRequests( ireq, dreq );
+
+#ifdef SOCLIB_MODULE_DEBUG
+    std::cout << name() << " Instruction Request: " << ireq << std::endl;
+    std::cout << name() << " Data Request: " << dreq << std::endl;
+#endif
+
+    /////////////////////////////////////////////////////////////////////
+    // The TGT_FSM controls the following ressources:
+    // - r_vci_tgt_fsm
+    // - r_tgt_buf[nwords]
+    // - r_tgt_val[nwords]
+    // - r_tgt_update
+    // - r_tgt_word
+    // - r_tgt_addr
+    // - r_tgt_srcid
+    // - r_tgt_trdid
+    // - r_tgt_pktid
+    // All VCI commands must be CMD_WRITE.
+    // If the VCI address offset is null, the command is an invalidate 
+    // request. It is an update request otherwise.
+    // The VCI_TGT FSM stores the external request arguments in the
+    // IDLE, UPDT_WORD & UPDT_DATA states. It sets the r_tgt_icache_req 
+    // & r_tgt_dcache_req flip-flops to signal the external request to 
+    // the ICACHE & DCACHE FSMs in the REQ state. It waits the completion
+    // of the update or invalidate request in the RSP state.
+    // -  for an invalidate request the VCI packet length is 1 word.
+    // The WDATA field contains the line index (i.e. the Z & Y fields).
+    // -  for an update request the VCI packet length is (n+2) words.
+    // The WDATA field of the first VCI word contains the line number.
+    // The WDATA field of the second VCI word contains the word index.
+    // The WDATA field of the n following words contains the values.
+    // -  for both invalidate & update requests, the VCI response
+    // is one single word.
+    // In case of errors in the VCI command packet, the simulation
+    // is stopped with an error message.
+    /////////////////////////////////////////////////////////////////////
+    
+    switch(r_vci_tgt_fsm) {
+    //////////////
+    case TGT_IDLE:
+    {
+        if ( p_vci_tgt.cmdval.read() ) 
+        {
+            paddr_t address = p_vci_tgt.address.read();
+
+            if ( p_vci_tgt.cmd.read() != vci_param::CMD_WRITE) 
+            {
+                std::cout << "error in component VCI_CC_VCACHE_WRAPPER_MULTI " << name() << std::endl;
+                std::cout << "the received VCI command is not a write" << std::endl;
+                exit(0);
+            }
+
+            // multi-update or multi-invalidate for data type
+            if ( ( address != 0x3 ) && ( ! m_segment.contains(address)) ) 
+            {
+                std::cout << "error in component VCI_CC_VCACHE_WRAPPER_MULTI " << name() << std::endl;
+                std::cout << "out of segment VCI command received for a multi-updt or multi-inval request" << std::endl;
+                exit(0);
+            }
+
+            r_tgt_srcid = p_vci_tgt.srcid.read();
+            r_tgt_trdid = p_vci_tgt.trdid.read();
+            r_tgt_pktid = p_vci_tgt.pktid.read();
+            r_tgt_plen  = p_vci_tgt.plen.read(); 
+            r_tgt_addr  = (paddr_t)(p_vci_tgt.be.read() & 0x3) << 32 |
+			              (paddr_t)p_vci_tgt.wdata.read() * m_dcache_words * 4; 
+
+            if ( address == 0x3 ) // broadcast invalidate for data or instruction type
+            {
+                if ( ! p_vci_tgt.eop.read() ) 
+                {
+                    std::cout << "error in component VCI_CC_VCACHE_WRAPPER_MULTI " << name() << std::endl;
+                    std::cout << "the BROADCAST INVALIDATE command length must be one word" << std::endl;
+                    exit(0);
+                }
+                r_tgt_update = false; 
+                r_tgt_broadcast = true; 
+                r_vci_tgt_fsm = TGT_REQ_BROADCAST;
+                m_cpt_cc_broadcast++;
+            }
+            else                // multi-update or multi-invalidate for data type
+            {
+                r_tgt_broadcast = false; 
+                paddr_t cell = address - m_segment.baseAddress();   
+
+                if (cell == 0)                      // invalidate   
+                {                         
+                    if ( ! p_vci_tgt.eop.read() ) 
+                    {
+                        std::cout << "error in component VCI_CC_VCACHE_WRAPPER_MULTI " << name() << std::endl;
+                        std::cout << "the MULTI-INVALIDATE command length must be one word" << std::endl;
+                        exit(0);
+                    }
+                    r_tgt_update = false; 
+                    r_vci_tgt_fsm = TGT_REQ_DCACHE;
+                    m_cpt_cc_inval++ ;
+                }
+                else if (cell == 4)                // update 
+                {                                
+                    if ( p_vci_tgt.eop.read() ) 
+                    {
+                        std::cout << "error in component VCI_CC_VCACHE_WRAPPER_MULTI " << name() << std::endl;
+                        std::cout << "the MULTI-UPDATE command length must be N+2 words" << std::endl;
+                        exit(0);
+                    }
+                    r_tgt_update = true; 
+                    r_vci_tgt_fsm = TGT_UPDT_WORD;
+                    m_cpt_cc_update++ ;
+                }     
+		        else if (cell == 8)
+		        {
+                    if ( ! p_vci_tgt.eop.read() ) 
+                    {
+                        std::cout << "error in component VCI_CC_VCACHE_WRAPPER_MULTI " << name() << std::endl;
+                        std::cout << "the MULTI-INVALIDATE command length must be one word" << std::endl;
+                        exit(0);
+                    }
+                    r_tgt_update = false; 
+                    r_vci_tgt_fsm = TGT_REQ_ICACHE;
+                    m_cpt_cc_inval++ ;
+		        }
+            } // end if address    
+        } // end if cmdval
+        break;
+    }
+    ///////////////////
+    case TGT_UPDT_WORD:
+    {
+        if (p_vci_tgt.cmdval.read()) 
+        {
+            if ( p_vci_tgt.eop.read() ) 
+            {
+                std::cout << "error in component VCI_CC_VCACHE_WRAPPER_MULTI " << name() << std::endl;
+                std::cout << "the MULTI-UPDATE command length must be N+2 words" << std::endl;
+                exit(0);
+            }
+            for ( size_t i=0 ; i<m_dcache_words ; i++ ) r_tgt_val[i] = false;
+            r_tgt_word = p_vci_tgt.wdata.read(); // the first modified word index
+            r_vci_tgt_fsm = TGT_UPDT_DATA;
+        }
+        break;
+    }
+    ///////////////////
+    case TGT_UPDT_DATA:
+    {
+        if (p_vci_tgt.cmdval.read()) 
+        {
+            size_t word = r_tgt_word.read();
+            if (word >= m_dcache_words) 
+            {
+                std::cout << "error in component VCI_CC_VCACHE_WRAPPER_MULTI " << name() << std::endl;
+                std::cout << "the reveived MULTI-UPDATE command length is wrong" << std::endl;
+                exit(0);
+            }
+            r_tgt_buf[word] = p_vci_tgt.wdata.read();
+            if(p_vci_tgt.be.read())    r_tgt_val[word] = true;
+            r_tgt_word = word + 1;
+            if (p_vci_tgt.eop.read())  r_vci_tgt_fsm = TGT_REQ_DCACHE;
+        }
+        break;
+    }
+    ////////////////////////
+    case TGT_REQ_BROADCAST:
+    {
+        if ( !r_tgt_icache_req.read() && !r_tgt_dcache_req.read() ) 
+        {
+            r_vci_tgt_fsm = TGT_RSP_BROADCAST; 
+            r_tgt_icache_req = true;
+            r_tgt_dcache_req = true;
+        }
+        break;
+    }
+    /////////////////////
+    case TGT_REQ_ICACHE:
+    {
+        if ( !r_tgt_icache_req.read() ) 
+        {
+            r_vci_tgt_fsm = TGT_RSP_ICACHE; 
+            r_tgt_icache_req = true;
+        }
+        break;
+    }
+    /////////////////////
+    case TGT_REQ_DCACHE:
+    {
+        if ( !r_tgt_dcache_req.read() ) 
+        {
+            r_vci_tgt_fsm = TGT_RSP_DCACHE; 
+            r_tgt_dcache_req = true;
+        }
+        break;
+    }
+    ///////////////////////
+    case TGT_RSP_BROADCAST:
+    {
+        // no response
+        if ( !r_tgt_icache_rsp.read() && !r_tgt_dcache_rsp.read() 
+          && !r_ccinval_itlb_cpt.read() && !r_ccinval_dtlb_cpt.read() 
+          && !r_tgt_icache_req.read() && !r_tgt_dcache_req.read() )
+        {
+            r_vci_tgt_fsm = TGT_IDLE;
+            break;
+        }
+
+        if ( p_vci_tgt.rspack.read() && !r_tgt_icache_req.read() && !r_tgt_dcache_req.read() ) 
+        {
+            if ( r_tgt_icache_rsp )
+            {
+                r_tgt_icache_rsp = false;
+                break;
+            }
+            if ( r_tgt_dcache_rsp )
+            {
+                r_tgt_dcache_rsp = false;
+                break;
+            }
+            if ( r_ccinval_itlb_cpt )
+            {
+                r_ccinval_itlb_cpt = r_ccinval_itlb_cpt - 1;
+                break;
+            }
+            if ( r_ccinval_dtlb_cpt )
+            {
+                r_ccinval_dtlb_cpt = r_ccinval_dtlb_cpt - 1;
+                break;
+            }
+        }        
+        break;
+    }
+    /////////////////////
+    case TGT_RSP_ICACHE:
+    {
+	if ( (p_vci_tgt.rspack.read() || !r_tgt_icache_rsp.read()) && !r_tgt_icache_req.read() ) 
+        {
+            r_vci_tgt_fsm = TGT_IDLE;
+            r_tgt_icache_rsp = false; 
+        }
+        break;
+    }
+    /////////////////////
+    case TGT_RSP_DCACHE:
+    {
+	if ( (p_vci_tgt.rspack.read() || !r_tgt_dcache_rsp.read()) && !r_tgt_dcache_req.read() )
+        {
+            r_vci_tgt_fsm = TGT_IDLE;
+            r_tgt_dcache_rsp = false; 
+        }
+        break;
+    }
+    } // end switch TGT_FSM
+
+    ////////////////////////////////////////////////////////////////////////////////////////
+    //      ICACHE_FSM
+    //
+    // There is 9 mutually exclusive conditions to exit the IDLE state.
+    // Four configurations corresponding to an XTN request from processor,
+    // - Flush TLB (in case of Context switch) => TLB_FLUSH state 
+    // - Flush cache => CACHE_FLUSH state 
+    // - Invalidate a TLB entry => TLB_INVAL state
+    // - Invalidate a cache line => CACHE_INVAL state
+    // Five configurations corresponding to various TLB or cache MISS :
+    // - TLB miss(in case hit_p miss) => TLB1_READ state
+    // - TLB miss(in case hit_p hit) => TLB2_READ state
+    // - Hit in TLB but VPN changed => BIS state
+    // - Cached read miss => MISS_REQ state
+    // - Uncache read miss => UNC_REQ state
+    // 
+    // In case of MISS, the controller writes a request in the r_icache_paddr_save register 
+    // and sets the corresponding request flip-flop : r_icache_tlb_read_req, r_icache_miss_req 
+    // or r_icache_unc_req. These request flip-flops are reset by the VCI_RSP controller 
+    // when the response is ready in the ICACHE buffer.
+    //
+    // The DCACHE FSM signals XTN processor requests using the r_dcache_xtn_req flip-flop. 
+    // The request opcod and the address to be invalidated are transmitted
+    // in the r_dcache_paddr_save & r_dcache_wdata_save registers respectively.
+    // The request flip-flop is reset by the ICACHE_FSM when the operation is completed.
+    //
+    // The r_vci_rsp_ins_error flip-flop is set by the VCI_RSP FSM and reset
+    // by the ICACHE-FSM in the ICACHE_ERROR state.
+    //
+    //----------------------------------------------------------------------------------- 
+    // Instruction TLB: 
+    //  
+    // - int        ET          (00: unmapped; 01: unused or PTD)
+    //                          (10: PTE new;  11: PTE old      )
+    // - bool       cachable    (cached bit)
+    // - bool       writable    (** not used alwayse false) 
+    // - bool       executable  (executable bit)
+    // - bool       user        (access in user mode allowed)
+    // - bool       global      (PTE not invalidated by a TLB flush)
+    // - bool       dirty       (** not used alwayse false) 
+    // - uint32_t   vpn         (virtual page number)
+    // - uint32_t   ppn         (physical page number)
+    ////////////////////////////////////////////////////////////////////////////////////////
+
+    switch(r_icache_fsm) {
+
+    ////////////////
+    case ICACHE_IDLE:
+    {
+        pte_info_t  icache_pte_info;
+        paddr_t     tlb_ipaddr     = 0;        // physical address obtained from TLB                                
+        paddr_t     spc_ipaddr     = 0;        // physical adress obtained from PPN_save (speculative)                         
+        data_t      icache_ins     = 0;        // read instruction
+        bool        icache_hit_c   = false;    // Cache hit
+        bool        icache_cached  = false;    // cacheable access (read)
+        bool        icache_hit_t   = false;    // hit on 4Kilo TLB
+        bool        icache_hit_x   = false;    // VPN unmodified (can use spc_dpaddr)
+        bool        icache_hit_p   = false;    // PTP unmodified (can skip first level page table walk)
+        size_t      icache_tlb_way = 0;        // selected way (in case of cache hit)
+        size_t      icache_tlb_set = 0;        // selected set (Y field in address)
+        paddr_t     icache_tlb_nline = 0;      // TLB NLINE
+
+        // Decoding processor XTN requests
+        // They are sent by DCACHE FSM  
+
+        if (r_dcache_xtn_req)
+        {
+            if ( ireq.valid ) m_cost_ins_miss_frz++;
+
+            if ((int)r_dcache_type_save == (int)iss_t::XTN_PTPR)  
+            {
+                r_icache_way = 0;
+                r_icache_set = 0;
+                r_icache_fsm = ICACHE_TLB_FLUSH;   
+                break;
+            }
+            if ((int)r_dcache_type_save == (int)iss_t::XTN_ICACHE_FLUSH)
+            {
+                r_icache_way = 0;
+                r_icache_set = 0;
+                r_icache_fsm = ICACHE_CACHE_FLUSH;   
+                break;
+            }
+            if ((int)r_dcache_type_save == (int)iss_t::XTN_ITLB_INVAL) 
+            {
+                r_icache_fsm = ICACHE_TLB_INVAL;   
+                break;
+            }
+            if ((int)r_dcache_type_save == (int)iss_t::XTN_ICACHE_INVAL) 
+            {
+                r_icache_fsm = ICACHE_CACHE_INVAL;   
+                break;
+            }
+            if ((int)r_dcache_type_save == (int)iss_t::XTN_MMU_ICACHE_PA_INV) 
+            {
+                r_icache_fsm = ICACHE_CACHE_INVAL_PA;   
+                break;
+            }
+        } // end if xtn_req
+
+        // external request from broadcast
+        if ( r_tgt_icache_req )
+        {
+            if ( ireq.valid ) m_cost_ins_miss_frz++;
+            r_icache_fsm = ICACHE_CC_INVAL;
+            r_icache_fsm_save = r_icache_fsm;
+            break;
+        }
+
+        // icache_hit_t, icache_hit_x, icache_hit_p 
+        // icache_pte_info, icache_tlb_way, icache_tlb_set & ipaddr & cacheability 
+        // - If MMU activated : cacheability is defined by the cachable bit in the TLB
+        // - If MMU not activated : cacheability is defined by the segment table.
+
+        if ( !(r_mmu_mode.read() & INS_TLB_MASK) )   // MMU not activated 
+        {
+            icache_hit_t  = true;         
+            icache_hit_x  = true;         
+            icache_hit_p  = true;         
+            tlb_ipaddr    = ireq.addr;
+            spc_ipaddr    = ireq.addr;
+            icache_cached = m_cacheability_table[ireq.addr];
+        } 
+        else                                                                // MMU activated
+        { 
+            m_cpt_ins_tlb_read++;
+            icache_hit_t = icache_tlb.cctranslate(ireq.addr, &tlb_ipaddr, &icache_pte_info, 
+                                                  &icache_tlb_nline, &icache_tlb_way, &icache_tlb_set); 
+            icache_hit_x   = (((vaddr_t)r_icache_vpn_save << PAGE_K_NBITS) == (ireq.addr & ~PAGE_K_MASK)) && r_itlb_translation_valid;
+            icache_hit_p   = (((ireq.addr >> PAGE_M_NBITS) == r_icache_id1_save) && r_icache_ptba_ok); 
+            spc_ipaddr     = ((paddr_t)r_icache_ppn_save << PAGE_K_NBITS) | (paddr_t)(ireq.addr & PAGE_K_MASK);
+            icache_cached  = icache_pte_info.c; 
+        }
+
+        if ( !(r_mmu_mode.read() & INS_CACHE_MASK) )   // cache not actived
+        {
+            icache_cached = false;
+        }
+
+        if ( ireq.valid ) 
+        {
+            m_cpt_icache_dir_read += m_icache_ways;
+            m_cpt_icache_data_read += m_icache_ways;
+
+            // icache_hit_c & icache_ins
+            if ( icache_cached )    // using speculative physical address for cached access
+            {
+                icache_hit_c = r_icache.read(spc_ipaddr, &icache_ins);
+            }
+            else                    // using actual physical address for uncached access
+            {
+                icache_hit_c = ( r_vci_rsp_ins_ok && (tlb_ipaddr == (paddr_t)r_icache_paddr_save) );
+                icache_ins = r_icache_miss_buf[0];
+            }
+
+            if ( r_mmu_mode.read() & INS_TLB_MASK ) 
+            {
+                if ( icache_hit_t ) 
+                {
+                    // check access rights
+                    if ( !icache_pte_info.u && (ireq.mode == iss_t::MODE_USER)) 
+                    {
+                        r_icache_error_type = MMU_READ_PRIVILEGE_VIOLATION;  
+                        r_icache_bad_vaddr = ireq.addr;
+                        irsp.valid = true;
+                        irsp.error = true;
+                        irsp.instruction = 0;
+                        break;
+                    }
+                    if ( !icache_pte_info.x ) 
+                    {
+                        r_icache_error_type = MMU_READ_EXEC_VIOLATION;  
+                        r_icache_bad_vaddr = ireq.addr;
+                        irsp.valid = true;
+                        irsp.error = true;
+                        irsp.instruction = 0;
+                        break;
+                    }
+                }
+
+                // update LRU, save ppn, vpn and page type
+                if ( icache_hit_t )
+                {  
+                    icache_tlb.setlru(icache_tlb_way,icache_tlb_set);     
+                    r_icache_ppn_save = tlb_ipaddr >> PAGE_K_NBITS;
+                    r_icache_vpn_save = ireq.addr >> PAGE_K_NBITS;
+                    r_icache_tlb_nline = icache_tlb_nline;
+                    r_itlb_translation_valid = true;
+                }
+                else
+                {
+                    r_itlb_translation_valid = false;
+                }
+
+            } // end if MMU activated
+
+            // compute next state 
+            if ( !icache_hit_t && !icache_hit_p )      // TLB miss
+            {
+                // walk page table  level 1
+                r_icache_paddr_save = (paddr_t)r_mmu_ptpr << (INDEX1_NBITS+2) | (paddr_t)((ireq.addr>>PAGE_M_NBITS)<<2);
+                r_icache_tlb_read_req = true;
+                r_icache_tlb_first_req = true;
+                r_vci_rsp_ins_ok = false;
+                r_icache_vaddr_req = ireq.addr;
+                r_icache_fsm = ICACHE_TLB1_READ;
+                m_cpt_ins_tlb_miss++;
+                m_cost_ins_tlb_miss_frz++;
+            }
+            else if ( !icache_hit_t && icache_hit_p )  // TLB Miss with possibility of bypass first level page
+            {
+                // walk page table level 2
+                r_icache_paddr_save = (paddr_t)r_icache_ptba_save | 
+                                      (paddr_t)(((ireq.addr&PTD_ID2_MASK)>>PAGE_K_NBITS) << 3);
+                r_icache_tlb_read_req = true;
+                r_icache_tlb_first_req = false;
+                r_vci_rsp_ins_ok = false;
+                r_icache_vaddr_req = ireq.addr;
+                r_icache_fsm = ICACHE_TLB2_READ;
+                m_cpt_ins_tlb_miss++;
+                m_cost_ins_tlb_miss_frz++;
+            }
+            else if ( icache_hit_t && !icache_hit_x && icache_cached ) // cached access with an ucorrect speculative physical address
+            {
+                r_icache_paddr_save = tlb_ipaddr;   // save actual physical address for BIS
+                r_icache_vaddr_req = ireq.addr;
+                r_icache_fsm = ICACHE_BIS;
+                m_cost_ins_miss_frz++;
+            }
+            else    // cached or uncached access with a correct speculative physical address 
+            {   
+                m_cpt_ins_read++;      
+                if ( !icache_hit_c ) 
+                {
+                    m_cpt_ins_miss++;
+                    m_cost_ins_miss_frz++;
+                    if ( icache_cached ) 
+                    {
+                        r_icache_miss_req = true;
+                        r_vci_rsp_ins_ok = false;
+                        r_icache_paddr_save = spc_ipaddr; 
+                        r_icache_vaddr_req = ireq.addr;
+                        r_icache_fsm = ICACHE_MISS_WAIT;
+                    } 
+                    else 
+                    {
+                        r_icache_unc_req = true;
+                        r_vci_rsp_ins_ok = false;
+                        r_icache_paddr_save = tlb_ipaddr;
+                        r_icache_vaddr_req = ireq.addr; 
+                        r_icache_fsm = ICACHE_UNC_WAIT;
+                    } 
+                } 
+                else 
+                {
+                    r_vci_rsp_ins_ok = false;
+                    r_icache_fsm = ICACHE_IDLE;
+                }
+                irsp.valid = icache_hit_c;
+                irsp.instruction = icache_ins;
+            } // end if next states
+            
+        } // end if ireq.valid
+        break;
+    }
+    ////////////////
+    case ICACHE_BIS: 
+    {
+        // external cache invalidate request
+        if ( r_tgt_icache_req )
+        {
+            if ( ireq.valid ) m_cost_ins_miss_frz++;
+            r_icache_fsm = ICACHE_CC_INVAL;
+            r_icache_fsm_save = r_icache_fsm;
+            break;
+        }
+
+        // using page is invalidated
+        if ( r_icache_inval_tlb_rsp )
+        {
+            if ( ireq.valid ) m_cost_ins_miss_frz++;
+            r_icache_inval_tlb_rsp = false;
+            r_icache_fsm = ICACHE_IDLE;
+            break;
+        }
+
+        data_t      icache_ins   = 0;
+        bool        icache_hit_c = false;
+        bool        icache_hit_t = false;
+        paddr_t     tlb_ipaddr   = 0;
+
+        // processor address translation
+        icache_hit_t = icache_tlb.translate(ireq.addr, &tlb_ipaddr);
+
+        // test if processor request modified
+        if ( (tlb_ipaddr == r_icache_paddr_save.read()) && ireq.valid && icache_hit_t ) // unmodified & valid
+        {
+            // acces is always cached in this state
+            icache_hit_c = r_icache.read(r_icache_paddr_save, &icache_ins);
+            m_cpt_ins_read++;
+      
+            if ( !icache_hit_c )
+            {
+                r_icache_miss_req = true;
+                r_vci_rsp_ins_ok = false;
+                r_icache_fsm = ICACHE_MISS_WAIT;
+                m_cpt_ins_miss++;
+                m_cost_ins_miss_frz++;
+            } 
+            else
+            {
+                r_icache_fsm = ICACHE_IDLE; 
+            }
+
+            irsp.valid = icache_hit_c;
+	        if (irsp.valid)
+	            assert((r_icache_vaddr_req.read() == ireq.addr) &&
+		        "vaddress should not be modified while ICACHE_BIS");
+            irsp.error = false;
+            irsp.instruction = icache_ins;
+        }
+        else
+        {
+            irsp.valid = false;
+            irsp.error = false;
+            irsp.instruction = 0;
+            r_icache_fsm = ICACHE_IDLE;
+        }
+        break;
+    }
+    //////////////////////
+    case ICACHE_TLB1_READ:
+    {
+        if ( ireq.valid ) m_cost_ins_tlb_miss_frz++;
+
+        // external cache invalidate request
+        if ( r_tgt_icache_req )
+        {
+            r_icache_fsm = ICACHE_CC_INVAL;
+            r_icache_fsm_save = r_icache_fsm;
+            break;
+        }
+
+        // cleanup PTD in L2, because it's not keep in L1
+		if ( r_icache_cleanup_req ) break;
+
+        if ( r_vci_rsp_ins_ok ) // vci response 
+        {
+	        if (r_icache_vaddr_req.read() != ireq.addr || !ireq.valid) 
+	        {
+	            /* request modified, drop response and restart */
+	            r_icache_ptba_ok = false;
+                if ( r_icache_inval_tlb_rsp )	r_icache_inval_tlb_rsp = false;
+                if ( r_vci_rsp_ins_error )	r_vci_rsp_ins_error = false;
+	            r_icache_fsm = ICACHE_IDLE;
+	            break;
+	        }
+
+            if ( !r_icache_inval_tlb_rsp ) // vci response 
+            {  
+                if ( !r_vci_rsp_ins_error ) // vci response ok
+                { 
+                    if ( !(r_icache_miss_buf[0] >> PTE_V_SHIFT) ) // unmapped
+                    {
+                	    r_icache_ptba_ok    = false;	
+                        r_icache_error_type = MMU_READ_PT1_UNMAPPED;  
+                        r_icache_bad_vaddr  = r_icache_vaddr_req.read();
+                        r_icache_fsm        = ICACHE_ERROR;
+                    }
+	                else if ( (r_icache_miss_buf[0] & PTE_T_MASK ) >> PTE_T_SHIFT ) // PTD
+	                {
+                        r_icache_ptba_ok       = true;	
+                        r_icache_ptba_save     = (paddr_t)(r_icache_miss_buf[0] & ((1<<(m_paddr_nbits - PAGE_K_NBITS))-1)) << PAGE_K_NBITS; 
+                        r_icache_id1_save      = r_icache_vaddr_req.read() >> PAGE_M_NBITS;
+                        r_icache_paddr_save    = (paddr_t)(r_icache_miss_buf[0] & ((1<<(m_paddr_nbits - PAGE_K_NBITS))-1)) << PAGE_K_NBITS |
+                                                 (paddr_t)(((r_icache_vaddr_req.read() & PTD_ID2_MASK) >> PAGE_K_NBITS) << 3); 
+                        r_icache_tlb_read_req  = true;
+                        r_icache_tlb_first_req = false;
+                        r_vci_rsp_ins_ok       = false;
+                        r_icache_fsm           = ICACHE_TLB2_READ;
+
+                        // cleanup PTD in L2, because it's not keep in L1
+                        r_icache_cleanup_req = true;
+                        r_icache_cleanup_line = r_icache_paddr_save.read() >> (uint32_log2(m_icache_words) + 2);  
+                        r_icache_cleanup_type = TLB_CLEANUP;
+	                }	
+	                else        // PTE
+	                {
+                        r_icache_ptba_ok = false;
+	                
+	                    if ( (m_srcid_rw >> 4) == ((r_icache_miss_buf[0] & ((1<<(m_paddr_nbits - PAGE_M_NBITS))-1)) >> (m_paddr_nbits - PAGE_M_NBITS -10)) ) // local
+	                    {
+	                        if ( (r_icache_miss_buf[0] & PTE_L_MASK ) >> PTE_L_SHIFT ) // L bit is set
+	                        {
+                                r_icache_pte_update = r_icache_miss_buf[0];
+                                r_vci_rsp_ins_ok    = false;
+                                r_icache_fsm        = ICACHE_TLB1_UPDT;
+	                        }
+	                        else
+	                        {
+                                r_icache_pte_update = r_icache_miss_buf[0] | PTE_L_MASK;
+                                r_icache_tlb_ll_req = true;
+                                r_vci_rsp_ins_ok    = false;
+                                r_icache_fsm        = ICACHE_TLB1_LL_WAIT;
+                                m_cpt_ins_tlb_write_et++;
+	                        }
+                        }
+	                    else // remotely
+	                    {
+	                        if ( (r_icache_miss_buf[0] & PTE_R_MASK ) >> PTE_R_SHIFT ) // R bit is set
+	                        {
+                                r_icache_pte_update = r_icache_miss_buf[0];
+                                r_vci_rsp_ins_ok    = false;
+                                r_icache_fsm        = ICACHE_TLB1_UPDT;
+	                        }
+	                        else
+	                        {
+                                r_icache_pte_update = r_icache_miss_buf[0] | PTE_R_MASK;
+                                r_icache_tlb_ll_req = true;
+                                r_vci_rsp_ins_ok    = false;
+                                r_icache_fsm        = ICACHE_TLB1_LL_WAIT;
+                                m_cpt_ins_tlb_write_et++;
+	                        }
+	                    }
+	                }
+                }
+                else        // vci response error
+                {
+                    r_icache_fsm = ICACHE_ERROR;
+                    r_icache_error_type = MMU_READ_PT1_ILLEGAL_ACCESS;    
+                    r_icache_bad_vaddr = ireq.addr;
+                }
+            }
+
+            if ( r_icache_inval_tlb_rsp ) // TLB miss read response and invalidation
+            {
+                if ( r_vci_rsp_ins_error ) 
+                {
+                    r_icache_inval_tlb_rsp = false;
+                    r_icache_error_type = MMU_READ_PT1_UNMAPPED;    
+                    r_icache_bad_vaddr = r_icache_vaddr_req.read();
+                    r_icache_fsm = ICACHE_ERROR;
+                } 
+                else 
+                {
+                    r_icache_inval_tlb_rsp = false;
+                    r_icache_cleanup_req = true;
+                    r_icache_cleanup_line = r_icache_paddr_save.read() >> (uint32_log2(m_icache_words) + 2);  
+                    r_icache_cleanup_type = TLB_CLEANUP;
+                    r_icache_fsm = ICACHE_IDLE;  
+                } 
+            }
+        }
+        break;
+    }
+    ///////////////////////
+    case ICACHE_TLB1_LL_WAIT:
+    {
+        // external cache invalidate request
+        if ( r_tgt_icache_req )
+        {
+            r_icache_fsm = ICACHE_CC_INVAL;
+            r_icache_fsm_save = r_icache_fsm;
+            break;
+        }
+
+	    if ( r_vci_rsp_ins_ok )
+	    {
+            if ( r_vci_rsp_ins_error ) // VCI response ko
+            {
+                r_icache_error_type = MMU_READ_PT1_ILLEGAL_ACCESS;    
+                r_icache_bad_vaddr = ireq.addr;
+                r_icache_fsm = ICACHE_ERROR;
+
+		        if (r_icache_inval_tlb_rsp) r_icache_inval_tlb_rsp = false;
+            }
+	        else
+	        {
+	            if ( !(r_icache_miss_buf[0] >> PTE_V_SHIFT) )	// unmapped
+	            {
+                    r_icache_error_type = MMU_READ_PT1_UNMAPPED;       
+                    r_icache_bad_vaddr  = ireq.addr;
+                    r_icache_fsm        = ICACHE_ERROR;
+
+		            if (r_icache_inval_tlb_rsp) r_icache_inval_tlb_rsp = false;
+	            }
+                else if ( r_icache_inval_tlb_rsp )
+                {
+       		        r_icache_inval_tlb_rsp = false;
+       		        r_icache_fsm = ICACHE_IDLE;
+                }
+		        else
+		        {
+		            r_icache_tlb_sc_req = true;
+                    r_vci_rsp_ins_ok    = false;
+                    r_icache_pte_update = r_icache_miss_buf[0] | r_icache_pte_update.read();
+                    r_icache_fsm        = ICACHE_TLB1_SC_WAIT; 
+		        }
+	        }
+	    }
+	    break;
+    }
+    ///////////////////////
+    case ICACHE_TLB1_SC_WAIT:
+    {
+        // external cache invalidate request
+        if ( r_tgt_icache_req )
+        {
+            r_icache_fsm = ICACHE_CC_INVAL;
+            r_icache_fsm_save = r_icache_fsm;
+            break;
+        }
+
+        if ( r_vci_rsp_ins_ok ) // VCI response ko
+        {
+            if ( r_vci_rsp_ins_error ) // VCI response ko
+	        {
+                r_icache_error_type = MMU_READ_PT1_ILLEGAL_ACCESS;    
+                r_icache_bad_vaddr  = ireq.addr; 
+                r_icache_fsm        = ICACHE_ERROR;
+
+		        if (r_icache_inval_tlb_rsp) r_icache_inval_tlb_rsp = false;
+	        }
+            else
+            {
+                if ( r_icache_inval_tlb_rsp )
+                {
+       		        r_icache_inval_tlb_rsp = false;
+                    if (r_icache_tlb_sc_fail) r_icache_tlb_sc_fail = false;
+       		        r_icache_fsm = ICACHE_IDLE;
+                }
+	            else if ( r_icache_tlb_sc_fail )
+	            {
+                    r_icache_tlb_ll_req = true;
+                    r_icache_tlb_sc_fail = false;
+                    r_vci_rsp_ins_ok = false;
+	                r_icache_fsm = ICACHE_TLB1_LL_WAIT; 
+	            }
+	            else 
+	            {
+                    r_vci_rsp_ins_ok = false;
+	                r_icache_fsm = ICACHE_TLB1_UPDT; 
+	            }
+            }
+        }
+	    break;
+    }
+    //////////////////////
+    case ICACHE_TLB1_UPDT:
+    {
+        if ( ireq.valid ) m_cost_ins_tlb_miss_frz++;
+
+        // external cache invalidate request
+        if ( r_tgt_icache_req )
+        {
+            r_icache_fsm = ICACHE_CC_INVAL;
+            r_icache_fsm_save = r_icache_fsm;
+            break;
+        }
+
+        if ( !r_icache_inval_tlb_rsp && !r_icache_cleanup_req )
+        {
+            paddr_t victim_index = 0;
+            r_icache_cleanup_req = icache_tlb.update1(r_icache_pte_update,r_icache_vaddr_req.read(),(r_icache_paddr_save.read() >> (uint32_log2(m_icache_words)+2)),&victim_index);
+            r_icache_cleanup_line = victim_index;
+            r_icache_cleanup_type = TLB_CLEANUP; 
+            r_icache_fsm = ICACHE_IDLE;
+        }
+        
+        // TLB update and invalidate same PTE
+        if ( r_icache_inval_tlb_rsp )                                 
+        {
+            r_icache_inval_tlb_rsp = false;
+            r_icache_fsm = ICACHE_IDLE;
+        }
+        break;
+    }
+    /////////////////////
+    case ICACHE_TLB2_READ:
+    {
+        if ( ireq.valid ) m_cost_ins_tlb_miss_frz++;
+
+        // external cache invalidate request
+        if ( r_tgt_icache_req )
+        {
+            r_icache_fsm = ICACHE_CC_INVAL;
+            r_icache_fsm_save = r_icache_fsm;
+            break;
+        }
+
+        if ( r_vci_rsp_ins_ok ) // vci response 
+        {
+	        if (r_icache_vaddr_req.read() != ireq.addr || !ireq.valid) 
+	        {
+	            /* request modified, drop response and restart */
+	            r_icache_ptba_ok = false;
+                if ( r_icache_inval_tlb_rsp )	r_icache_inval_tlb_rsp = false;
+                if ( r_vci_rsp_ins_error )	r_vci_rsp_ins_error = false;
+	            r_icache_fsm = ICACHE_IDLE;
+	            break;
+	        }
+
+            if ( !r_icache_inval_tlb_rsp ) // vci response 
+            {
+                if ( !r_vci_rsp_ins_error ) // VCI response ok        
+                {
+	                if ( !(r_icache_miss_buf[0] >> PTE_V_SHIFT) ) // unmapped
+	                {
+                        r_icache_error_type = MMU_READ_PT2_UNMAPPED;  
+                        r_icache_bad_vaddr  = r_icache_vaddr_req.read();
+                        r_icache_fsm = ICACHE_ERROR;
+	                }
+	                else
+	                {
+	                    if ( (m_srcid_rw >> 4) == ((r_icache_miss_buf[0] & ((1<<(m_paddr_nbits - PAGE_M_NBITS))-1)) >> (m_paddr_nbits - PAGE_M_NBITS -10)) ) // local
+	                    {
+	                        if ( (r_icache_miss_buf[0] & PTE_L_MASK ) >> PTE_L_SHIFT ) // L bit is set
+	                        {
+                                r_vci_rsp_ins_ok    = false;
+                                r_icache_fsm        = ICACHE_TLB2_UPDT;
+                                r_icache_pte_update = r_icache_miss_buf[0];
+	                        }
+	                        else
+	                        {
+                                r_icache_pte_update = r_icache_miss_buf[0] | PTE_L_MASK;
+                                r_icache_tlb_ll_req = true;
+                                r_vci_rsp_ins_ok    = false;
+                                r_icache_fsm        = ICACHE_TLB2_LL_WAIT;
+                                m_cpt_ins_tlb_write_et++;
+	                        }
+                        }
+	                    else // remotely
+	                    {
+	                        if ( (r_icache_miss_buf[0] & PTE_R_MASK ) >> PTE_R_SHIFT ) // R bit is set
+	                        {
+                                r_vci_rsp_ins_ok    = false;
+                                r_icache_fsm        = ICACHE_TLB2_UPDT;
+                                r_icache_pte_update = r_icache_miss_buf[0];
+	                        }
+	                        else
+	                        {
+                                r_icache_pte_update = r_icache_miss_buf[0] | PTE_R_MASK;
+                                r_icache_tlb_ll_req = true;
+                                r_vci_rsp_ins_ok    = false;
+                                r_icache_fsm        = ICACHE_TLB2_LL_WAIT;
+                                m_cpt_ins_tlb_write_et++;
+	                        }
+	                    }
+	                }
+                }
+                else    // VCI response error
+                {
+                    r_icache_error_type = MMU_READ_PT2_ILLEGAL_ACCESS;
+                    r_icache_bad_vaddr = ireq.addr;
+                    r_icache_fsm = ICACHE_ERROR;
+                }
+            }
+
+            if ( r_icache_inval_tlb_rsp ) // TLB miss read response and invalidation
+            {
+                if ( r_vci_rsp_ins_error ) 
+                {
+                    r_icache_inval_tlb_rsp = false;
+                    r_icache_error_type = MMU_READ_PT2_UNMAPPED;    
+                    r_icache_bad_vaddr = ireq.addr;
+                    r_icache_fsm = ICACHE_ERROR;
+                } 
+                else 
+                {
+                    if (r_icache_cleanup_req) break;
+                    r_icache_inval_tlb_rsp = false;
+                    r_icache_cleanup_req = true;
+                    r_icache_cleanup_line = r_icache_paddr_save.read() >> (uint32_log2(m_icache_words) + 2);  
+                    r_icache_cleanup_type = TLB_CLEANUP;
+                    r_icache_fsm = ICACHE_IDLE;  
+                } 
+            }
+        }
+        break;
+    }
+    ///////////////////////
+    case ICACHE_TLB2_LL_WAIT:
+    {
+        // external cache invalidate request
+        if ( r_tgt_icache_req )
+        {
+            r_icache_fsm = ICACHE_CC_INVAL;
+            r_icache_fsm_save = r_icache_fsm;
+            break;
+        }
+
+	    if ( r_vci_rsp_ins_ok )
+	    {
+            if ( r_vci_rsp_ins_error ) // VCI response ko
+            {
+                r_icache_error_type = MMU_READ_PT2_ILLEGAL_ACCESS;    
+                r_icache_bad_vaddr = ireq.addr;
+                r_icache_fsm = ICACHE_ERROR;
+
+                if (r_icache_inval_tlb_rsp) r_icache_inval_tlb_rsp = false;
+            }
+	        else
+	        {
+	            if ( !(r_icache_miss_buf[0] >> PTE_V_SHIFT) )	// unmapped
+	            {
+                    r_icache_error_type = MMU_READ_PT2_UNMAPPED;       
+                    r_icache_bad_vaddr  = ireq.addr;
+                    r_icache_fsm        = ICACHE_ERROR;
+
+                    if (r_icache_inval_tlb_rsp) r_icache_inval_tlb_rsp = false;
+	            }
+                else if ( r_icache_inval_tlb_rsp )
+                {
+       		        r_icache_inval_tlb_rsp = false;
+       		        r_icache_fsm = ICACHE_IDLE;
+                }
+		        else
+		        {
+		            r_icache_tlb_sc_req = true;
+                    r_vci_rsp_ins_ok    = false;
+                    r_icache_pte_update = r_icache_miss_buf[0] | r_icache_pte_update.read();
+                    r_icache_fsm        = ICACHE_TLB2_SC_WAIT; 
+		        }
+	        }
+	    }
+	    break;
+    }
+    ///////////////////////
+    case ICACHE_TLB2_SC_WAIT:
+    {
+        // external cache invalidate request
+        if ( r_tgt_icache_req )
+        {
+            r_icache_fsm = ICACHE_CC_INVAL;
+            r_icache_fsm_save = r_icache_fsm;
+            break;
+        }
+
+        if ( r_vci_rsp_ins_ok ) // VCI response 
+        {
+            if ( r_vci_rsp_ins_error ) // VCI response ko
+	        {
+                r_icache_error_type = MMU_READ_PT2_ILLEGAL_ACCESS;    
+                r_icache_bad_vaddr  = ireq.addr; 
+                r_icache_fsm        = ICACHE_ERROR;
+
+                if (r_icache_inval_tlb_rsp) r_icache_inval_tlb_rsp = false;
+	        }
+            else
+            {
+                if ( r_icache_inval_tlb_rsp )
+                {
+       		        r_icache_inval_tlb_rsp = false;
+                    if (r_icache_tlb_sc_fail) r_icache_tlb_sc_fail = false;
+       		        r_icache_fsm = ICACHE_IDLE;
+                }
+	            else if ( r_icache_tlb_sc_fail )
+	            {
+                    r_icache_tlb_ll_req = true;
+                    r_icache_tlb_sc_fail = false;
+                    r_vci_rsp_ins_ok = false;
+	                r_icache_fsm = ICACHE_TLB2_LL_WAIT; 
+	            }
+	            else 
+	            {
+                    r_vci_rsp_ins_ok = false;
+	                r_icache_fsm = ICACHE_TLB2_UPDT; 
+	            }
+            }
+        }
+	    break;
+    }
+    /////////////////////
+    case ICACHE_TLB2_UPDT: 
+    {
+        if ( ireq.valid ) m_cost_ins_tlb_miss_frz++;
+
+        // external cache invalidate request
+        if ( r_tgt_icache_req )
+        {
+            r_icache_fsm = ICACHE_CC_INVAL;
+            r_icache_fsm_save = r_icache_fsm;
+            break;
+        }
+
+        if ( !r_icache_inval_tlb_rsp && !r_icache_cleanup_req )
+        {
+            paddr_t victim_index = 0;
+            r_icache_cleanup_req = icache_tlb.update1(r_icache_pte_update,r_icache_miss_buf[1],r_icache_vaddr_req.read(),(r_icache_paddr_save.read() >> (uint32_log2(m_icache_words)+2)),&victim_index);
+            r_icache_cleanup_line = victim_index;
+            r_icache_cleanup_type = TLB_CLEANUP; 
+            r_icache_fsm = ICACHE_IDLE;
+        }
+
+        // TLB update and invalidate same PTE
+        if ( r_icache_inval_tlb_rsp )                            
+        {
+            r_icache_inval_tlb_rsp = false;
+            r_icache_fsm = ICACHE_IDLE;
+        }
+        break;
+    }
+    /////////////////////////////
+    case ICACHE_TLB_FLUSH:
+    {
+        size_t way = r_icache_way;
+        size_t set = r_icache_set;
+        bool clean = false;
+
+        m_cost_ins_tlb_flush_frz++;
+        // 4K page size TLB flush leads to cleanup req to data cache 
+        if ( !r_icache_cleanup_req )    // last cleanup finish
+        {
+            paddr_t victim_index = 0;
+            for ( ; way < m_itlb_ways; way++)
+            {
+                for ( ; set < m_itlb_sets; set++)
+                {
+                    if(icache_tlb.checkcleanup1(way, set, &victim_index))
+                    {
+                        clean = true;
+                        r_icache_cleanup_req = true;
+                        r_icache_cleanup_line = victim_index;
+                        r_icache_cleanup_type = TLB_CLEANUP;
+                        r_icache_way = way + ((set+1)/m_itlb_sets);
+                        r_icache_set = (set+1) % m_itlb_sets;
+                        break;
+                    }
+                }
+                if (clean) break;
+            }
+
+            if (way == m_itlb_ways)
+            {
+                r_dcache_xtn_req = false;
+                r_itlb_translation_valid = false;
+                r_icache_ptba_ok = false;
+                r_icache_fsm = ICACHE_IDLE;
+                break;
+            }
+        }
+        break;
+    }
+    ////////////////////////
+    case ICACHE_CACHE_FLUSH:
+    {
+        // external cache invalidate request
+        if ( r_tgt_icache_req )
+        {
+            r_icache_fsm = ICACHE_CC_INVAL;
+            r_icache_fsm_save = r_icache_fsm;
+            break;
+        }
+
+        size_t way = r_icache_way;
+        size_t set = r_icache_set;
+        bool clean = false;
+
+        m_cost_ins_cache_flush_frz++;
+
+        // cache flush and send cleanup to external
+        if ( !r_icache_cleanup_req )
+        {
+            paddr_t victim_index = 0;
+            for ( ; way < m_icache_ways; way++ )
+            {    
+                for ( ; set < m_icache_sets; set++ )
+                {    
+                    if ( r_icache.flush(way, set, &victim_index) )
+                    {
+                        clean = true;
+                        r_icache_cleanup_req = true;
+                        r_icache_cleanup_line = victim_index;
+                        r_icache_cleanup_type = CACHE_CLEANUP;
+                        r_icache_way = way + ((set+1)/m_icache_sets);
+                        r_icache_set = (set+1) % m_icache_sets;
+                        break;
+                    }
+                }
+                if (clean) break;
+            }
+            if (way == m_icache_ways)
+            {
+                r_dcache_xtn_req = false;
+                r_icache_fsm = ICACHE_IDLE;
+                break;
+            }
+        }
+        break;
+    }
+    /////////////////////
+    case ICACHE_TLB_INVAL:  
+    {
+        paddr_t victim_index = 0;
+
+        if ( !r_icache_cleanup_req )
+        {
+            r_icache_cleanup_req = icache_tlb.inval1(r_dcache_wdata_save,&victim_index);
+            r_icache_cleanup_type = TLB_CLEANUP;
+            r_icache_cleanup_line = victim_index;
+            r_dcache_xtn_req = false;
+            r_itlb_translation_valid = false;
+            r_icache_ptba_ok = false;
+            r_icache_fsm = ICACHE_IDLE;
+        }
+        break;
+	}
+    ////////////////////////
+    case ICACHE_CACHE_INVAL:
+    {
+        // external cache invalidate request
+        if ( r_tgt_icache_req )
+        {
+            r_icache_fsm = ICACHE_CC_INVAL;
+            r_icache_fsm_save = r_icache_fsm;
+            break;
+        }
+	
+        paddr_t ipaddr = 0;                     
+        bool    icache_hit_t = false;
+
+        if ( !r_icache_cleanup_req )
+        {
+            if ( r_mmu_mode.read() & INS_TLB_MASK ) 
+            {
+                icache_hit_t = icache_tlb.translate(r_dcache_wdata_save, &ipaddr); 
+            } 
+            else 
+            {
+                ipaddr = (paddr_t)r_dcache_wdata_save;
+                icache_hit_t = true;
+            }
+            if ( icache_hit_t )
+            {
+                // invalidate and cleanup if necessary
+                r_icache_cleanup_req = r_icache.inval(ipaddr);
+                r_icache_cleanup_line = ipaddr >> (uint32_log2(m_icache_words) + 2);
+                r_icache_cleanup_type = CACHE_CLEANUP;
+            }
+            r_dcache_xtn_req = false; 
+            r_icache_fsm = ICACHE_IDLE;
+        }
+        break;
+    }
+    ////////////////////////
+    case ICACHE_CACHE_INVAL_PA:
+    {
+        // external cache invalidate request
+        if ( r_tgt_icache_req )
+        {
+            r_icache_fsm = ICACHE_CC_INVAL;
+            r_icache_fsm_save = r_icache_fsm;
+            break;
+        }
+	
+        paddr_t ipaddr = (paddr_t)r_mmu_word_hi.read() << 32 | r_mmu_word_lo.read();
+
+        if ( !r_icache_cleanup_req )
+        {    
+            // invalidate and cleanup if necessary
+            r_icache_cleanup_req = r_icache.inval(ipaddr);
+            r_icache_cleanup_line = ipaddr >> (uint32_log2(m_icache_words) + 2);   
+            r_icache_cleanup_type = CACHE_CLEANUP; 
+            r_dcache_xtn_req = false; 
+            r_icache_fsm = ICACHE_IDLE;
+        }
+        break;
+    }
+    ///////////////////////
+    case ICACHE_MISS_WAIT:
+    {
+        m_cost_ins_miss_frz++;
+
+        // external cache invalidate request
+        if ( r_tgt_icache_req )     
+        {
+            r_icache_fsm = ICACHE_CC_INVAL;
+            r_icache_fsm_save = r_icache_fsm;
+            break;
+        }
+
+        if ( r_vci_rsp_ins_ok )
+        {
+            if ( r_vci_rsp_ins_error ) 
+            {
+                r_icache_error_type = MMU_READ_DATA_ILLEGAL_ACCESS; 
+                r_icache_bad_vaddr = ireq.addr;
+                r_icache_fsm = ICACHE_ERROR;
+        
+            	if ( r_icache_inval_tlb_rsp ) r_icache_inval_tlb_rsp = false;
+            	if ( r_icache_inval_rsp ) r_icache_inval_rsp = false;
+        	    break;
+            }
+        
+            if ( r_icache_inval_tlb_rsp ) // Miss read response and tlb invalidation
+            {
+		        if ( r_icache_cleanup_req ) break;
+                r_icache_cleanup_req = true;
+                r_icache_cleanup_line = r_icache_paddr_save.read() >> (uint32_log2(m_icache_words) + 2);  
+                r_icache_cleanup_type = CACHE_CLEANUP; 
+                r_icache_fsm = ICACHE_IDLE;
+                r_icache_inval_tlb_rsp = false;
+                if ( r_icache_inval_rsp ) r_icache_inval_rsp = false;
+                m_cost_ins_tlb_miss_frz++;
+                break;
+            }
+        
+            if ( r_icache_inval_rsp ) // Miss read response and tlb invalidation
+            {
+		        if ( r_icache_cleanup_req ) break;
+                r_icache_cleanup_req = true;
+                r_icache_cleanup_line = r_icache_paddr_save.read() >> (uint32_log2(m_icache_words) + 2);  
+                r_icache_cleanup_type = CACHE_CLEANUP; 
+                r_icache_fsm = ICACHE_IDLE;
+                r_icache_inval_rsp = false;
+                break;
+            }
+            r_icache_fsm = ICACHE_MISS_UPDT;  
+        }	
+        break;
+    }
+    ////////////////////
+    case ICACHE_UNC_WAIT:
+    {
+        m_cost_ins_miss_frz++;
+        // external cache invalidate request
+        if ( r_tgt_icache_req ) 
+        {
+            r_icache_fsm = ICACHE_CC_INVAL;
+            r_icache_fsm_save = r_icache_fsm;
+            break;
+        }
+
+        if ( r_vci_rsp_ins_ok )
+        {
+            if ( r_vci_rsp_ins_error ) 
+            {
+                r_icache_error_type = MMU_READ_DATA_ILLEGAL_ACCESS;    
+                r_icache_bad_vaddr = ireq.addr;
+                r_icache_fsm = ICACHE_ERROR;
+        
+            	if ( r_icache_inval_tlb_rsp ) r_icache_inval_tlb_rsp = false;
+        	    break;
+            }
+        
+            if ( r_icache_inval_tlb_rsp ) // Miss read response and tlb invalidation
+            {
+                r_icache_inval_tlb_rsp = false;
+                r_icache_fsm = ICACHE_IDLE;
+        	    break;
+            }
+
+            // Miss read response and no invalidation
+            r_icache_fsm = ICACHE_IDLE;
+        }	
+        break;
+    }
+    //////////////////////
+    case ICACHE_MISS_UPDT:
+    {
+        if ( ireq.valid ) m_cost_ins_miss_frz++;
+
+        // external cache invalidate request
+        if ( r_tgt_icache_req )   
+        {
+            r_icache_fsm = ICACHE_CC_INVAL;
+            r_icache_fsm_save = r_icache_fsm;
+            break;
+        }
+
+        if ( r_icache_inval_tlb_rsp ) // tlb invalidation
+        {
+            if ( r_icache_cleanup_req ) break;
+            r_icache_cleanup_req = true;
+            r_icache_cleanup_line = r_icache_paddr_save.read() >> (uint32_log2(m_icache_words) + 2);
+            r_icache_cleanup_type = CACHE_CLEANUP;
+            r_icache_inval_tlb_rsp = false;
+            if ( r_icache_inval_rsp ) r_icache_inval_rsp = false;
+            r_icache_fsm = ICACHE_IDLE;
+            break;
+        }
+
+        if ( !r_icache_cleanup_req ) // Miss update and no invalidation
+        {
+            if ( r_icache_inval_rsp )   // invalidation
+            {
+                r_icache_cleanup_req = true;
+                r_icache_cleanup_line = r_icache_paddr_save.read() >> (uint32_log2(m_icache_words) + 2);
+                r_icache_cleanup_type = CACHE_CLEANUP;
+                r_icache_inval_rsp = false;
+                r_icache_fsm = ICACHE_IDLE;
+            }
+            else
+            {
+                data_t* buf = r_icache_miss_buf;
+                paddr_t  victim_index = 0;
+                m_cpt_icache_dir_write++;
+                m_cpt_icache_data_write++;
+
+                r_icache_cleanup_req = r_icache.update(r_icache_paddr_save.read(), buf, &victim_index);
+                r_icache_cleanup_line = victim_index;         
+                r_icache_cleanup_type = CACHE_CLEANUP;            
+                r_icache_fsm = ICACHE_IDLE;
+            }
+        }
+        break;
+    }
+    ///////////////////
+    case ICACHE_ERROR:
+    {
+        r_vci_rsp_ins_error = false;
+        irsp.valid = true;
+        irsp.error = true;
+        irsp.instruction = 0; 
+        r_icache_fsm = ICACHE_IDLE;
+        break;
+    }
+    /////////////////////
+    case ICACHE_CC_INVAL:  
+    {                       
+        if ( ireq.valid ) m_cost_ins_miss_frz++;
+        m_cpt_icache_dir_read += m_icache_ways;
+
+        // invalidate cache
+        if( (( r_icache_fsm_save == ICACHE_MISS_WAIT ) || ( r_icache_fsm_save == ICACHE_MISS_UPDT ) ) && 
+            ((r_icache_paddr_save.read() & ~((m_icache_words<<2)-1)) == (r_tgt_addr.read() & ~((m_icache_words<<2)-1))) ) 
+        {
+            r_icache_inval_rsp = true;
+            r_tgt_icache_rsp = false; 
+        } 
+        else 
+        {
+            r_tgt_icache_rsp = r_icache.inval(r_tgt_addr.read());
+        }
+
+        if ( r_tgt_broadcast )
+        {
+		    // ins tlb invalidate verification    
+            r_icache_tlb_inval_req = true;
+            r_icache_fsm = ICACHE_TLB_CC_INVAL;
+        }
+        else
+        {
+            r_tgt_icache_req = false;        
+            r_icache_fsm = r_icache_fsm_save;
+        }    
+        break;
+    }
+    /////////////////////////
+    case ICACHE_TLB_CC_INVAL:
+    {
+        if ( ireq.valid ) m_cost_ins_miss_frz++;     
+
+	    if ( r_icache_tlb_inval_req ) break;
+
+        // invalidate cache
+        if( (( r_icache_fsm_save == ICACHE_TLB1_READ )   || ( r_icache_fsm_save == ICACHE_TLB2_READ )    ||
+             ( r_icache_fsm_save == ICACHE_TLB1_LL_WAIT )|| ( r_icache_fsm_save == ICACHE_TLB2_LL_WAIT ) ||
+             ( r_icache_fsm_save == ICACHE_TLB1_SC_WAIT )|| ( r_icache_fsm_save == ICACHE_TLB2_SC_WAIT ) || 
+             ( r_icache_fsm_save == ICACHE_TLB1_UPDT )   || ( r_icache_fsm_save == ICACHE_TLB2_UPDT ))   && 
+            ((r_icache_paddr_save.read() & ~((m_icache_words<<2)-1)) == r_tgt_addr.read()) ) 
+        {
+            r_icache_inval_tlb_rsp = true;
+        } 
+        else if (((r_icache_fsm_save == ICACHE_BIS)||(r_icache_fsm_save == ICACHE_MISS_WAIT) ||
+           /*  (r_icache_fsm_save == ICACHE_UNC_WAIT)|| */(r_icache_fsm_save == ICACHE_MISS_UPDT)) && 
+            (r_icache_tlb_nline == (paddr_t)(r_tgt_addr.read() >> (uint32_log2(m_icache_words)+2))))
+        {
+            r_icache_inval_tlb_rsp = true;
+        }
+
+        if( (( r_icache_fsm_save == ICACHE_TLB1_LL_WAIT )|| ( r_icache_fsm_save == ICACHE_TLB2_LL_WAIT ) ||
+             ( r_icache_fsm_save == ICACHE_TLB1_SC_WAIT )|| ( r_icache_fsm_save == ICACHE_TLB2_SC_WAIT ) || 
+             ( r_icache_fsm_save == ICACHE_TLB1_UPDT )   || ( r_icache_fsm_save == ICACHE_TLB2_UPDT ))   && 
+            ((r_icache_paddr_save.read() & ~((m_icache_words<<2)-1)) == r_tgt_addr.read()) ) 
+        {
+            if ( !r_icache_cc_hit_t ) r_ccinval_itlb_cpt = r_ccinval_itlb_cpt + 1;
+        } 
+
+        r_tgt_icache_req = false;
+	    r_itlb_translation_valid = false;
+        r_icache_ptba_ok = false;        
+        r_icache_fsm = r_icache_fsm_save;
+        break;
+    }
+    } // end switch r_icache_fsm
+
+#ifdef SOCLIB_MODULE_DEBUG
+    std::cout << name() << " Instruction Response: " << irsp << std::endl;
+#endif
+
+    ////////////////////////////////////////////////////////////////////////////////////
+    //      INVAL ITLB CHECK FSM 
+    ////////////////////////////////////////////////////////////////////////////////////////
+    switch(r_inval_itlb_fsm) {
+    ///////////////////// 
+    case INVAL_ITLB_IDLE:
+    {
+        if ( r_icache_tlb_inval_req )
+        {
+            paddr_t ipaddr;
+            r_ccinval_itlb_way = 0; 
+            r_ccinval_itlb_set = 0;
+            r_ccinval_itlb_cpt = 0;
+            r_icache_cc_hit_t = icache_tlb.translate(ireq.addr, &ipaddr);
+            r_inval_itlb_fsm = INVAL_ITLB_CHECK;    
+        }   
+        break;
+    }
+    ////////////////////////////
+    case INVAL_ITLB_CHECK:
+    {
+        size_t way = r_ccinval_itlb_way; 
+        size_t set = r_ccinval_itlb_set;
+        bool end = false;  
+      
+        // r_tgt_addr is number of line
+        bool tlb_hit = icache_tlb.cccheck((r_tgt_addr.read() >> (uint32_log2(m_icache_words)+2)),way, set, &way, &set, &end); 
+    
+        if ( tlb_hit )
+        {
+            r_ccinval_itlb_way = way; 
+            r_ccinval_itlb_set = set;
+            r_itlb_cc_check_end = end;
+            r_ccinval_itlb_cpt = r_ccinval_itlb_cpt + 1;
+            r_inval_itlb_fsm = INVAL_ITLB_INVAL;    
+        }        
+        else
+        {
+            r_inval_itlb_fsm = INVAL_ITLB_CLEAR;    
+        }
+        break;
+    }
+    /////////////////////////
+    case INVAL_ITLB_INVAL:
+    {
+        //m_cost_ins_tlb_inval_frz++;
+ 
+        icache_tlb.ccinval(r_ccinval_itlb_way, r_ccinval_itlb_set);
+
+        if ( !r_itlb_cc_check_end )
+        {
+            r_inval_itlb_fsm = INVAL_ITLB_CHECK; 
+        }
+        else
+        {
+            r_inval_itlb_fsm = INVAL_ITLB_CLEAR;    
+        }
+        break;
+    }
+    ////////////////////
+    case INVAL_ITLB_CLEAR:
+    {
+        r_icache_tlb_inval_req = false;
+        r_itlb_cc_check_end = false;
+        r_ccinval_itlb_way = 0; 
+        r_ccinval_itlb_set = 0; 
+        r_inval_itlb_fsm = INVAL_ITLB_IDLE;    
+        break;
+    }
+    } // end switch r_inval_itlb_fsm
+
+    ////////////////////////////////////////////////////////////////////////////////////
+    //      DCACHE FSM 
+    //
+    // Both the Cacheability Table, and the MMU cached bit are used to define
+    // the cacheability.
+    // 
+    // There is 14 mutually exclusive conditions to exit the IDLE state.
+    // Seven configurations corresponding to an XTN request from processor:
+    // - Context switch => CTXT_SWITCH state
+    // - Flush dcache => DCACHE_FLUSH state 
+    // - Flush icache => ICACHE_FLUSH state 
+    // - Invalidate a dtlb entry => DTLB_INVAL state
+    // - Invalidate a itlb entry => ITLB_INVAL state
+    // - Invalidate a dcache line => DCACHE_INVAL state
+    // - Invalidate a icache line => ICACHE_INVAL state
+    // Seven configurations corresponding to various read miss or write requests: 
+    // - TLB miss(in case hit_p miss) => TLB1_READ state
+    // - TLB miss(in case hit_p hit) => TLB2_READ state
+    // - Hit in TLB but VPN changed => BIS state
+    // - Cached read miss => MISS_REQ state
+    // - Uncache read miss => UNC_REQ state
+    // - Write hit => WRITE_UPDT state
+    // - Write miss => WRITE_REQ
+    //
+    // The r_vci_rsp_data_error flip-flop is set by the VCI_RSP controller and reset 
+    // by DCACHE-FSM when its state is in DCACHE_ERROR. 
+    //--------------------------------------------------------------------- 
+    // Data TLB: 
+    //  
+    // - int        ET          (00: unmapped; 01: unused or PTD)
+    //                          (10: PTE new;  11: PTE old      )
+    // - bool       cachable    (cached bit)
+    // - bool       writable    (writable bit) 
+    // - bool       executable  (** not used alwayse false)
+    // - bool       user        (access in user mode allowed)
+    // - bool       global      (PTE not invalidated by a TLB flush)
+    // - bool       dirty       (page has been modified) 
+    // - uint32_t   vpn         (virtual page number)
+    // - uint32_t   ppn         (physical page number)
+    ////////////////////////////////////////////////////////////////////////////////////////
+
+    switch (r_dcache_fsm) {
+
+    //////////////////////
+    case DCACHE_WRITE_REQ:
+    {
+        if ( r_tgt_dcache_req ) // external request
+        {
+            r_dcache_fsm = DCACHE_CC_CHECK;
+            r_dcache_fsm_save = r_dcache_fsm;
+            break;
+        }
+
+        if ( !r_wbuf.wok(r_dcache_paddr_save) )
+        {
+            m_cost_write_frz++;
+            drsp.valid = false;
+            drsp.rdata = 0;
+            break;
+        }     
+        // The next state and the processor request parameters are computed 
+        // as in the DCACHE_IDLE state (see below ...)
+    }
+    /////////////////
+    case DCACHE_IDLE:
+    {
+        // external cache invalidate request
+        if ( r_tgt_dcache_req )   
+        {
+            r_dcache_fsm = DCACHE_CC_CHECK;
+            r_dcache_fsm_save = DCACHE_IDLE;
+            if ( dreq.valid ) m_cost_data_miss_frz++;
+            break;
+        }        
+
+        if (dreq.valid) 
+        {
+            pte_info_t  dcache_pte_info;
+            int         xtn_opcod      = (int)dreq.addr/4;
+            paddr_t     tlb_dpaddr     = 0;        // physical address obtained from TLB
+            paddr_t     spc_dpaddr     = 0;        // physical adress obtained from PPN_save (speculative)
+            bool        dcache_hit_t   = false;    // hit on 4Kilo TLB
+            bool        dcache_hit_x   = false;    // VPN unmodified (can use spc_dpaddr)
+            bool        dcache_hit_p   = false;    // PTP unmodified (can skip first level page table walk)
+            bool        dcache_hit_c   = false;    // Cache hit
+            size_t      dcache_tlb_way = 0;        // selected way (in case of cache hit)
+            size_t      dcache_tlb_set = 0;        // selected set (Y field in address)
+            data_t      dcache_rdata   = 0;        // read data
+            bool        dcache_cached  = false;    // cacheable access (read or write)
+            paddr_t     dcache_tlb_nline = 0;       // TLB NLINE
+
+            m_cpt_dcache_data_read += m_dcache_ways;
+            m_cpt_dcache_dir_read += m_dcache_ways;
+
+            // Decoding READ XTN requests from processor
+            // They are executed in this DCACHE_IDLE state
+
+            if (dreq.type == iss_t::XTN_READ) 
+            {
+                switch(xtn_opcod) {
+                case iss_t::XTN_INS_ERROR_TYPE:
+                    drsp.rdata = (uint32_t)r_icache_error_type;
+                    r_icache_error_type = MMU_NONE;
+                    drsp.valid = true;
+                    drsp.error = false;
+                    break;
+                case iss_t::XTN_DATA_ERROR_TYPE:
+                    drsp.rdata = (uint32_t)r_dcache_error_type;
+                    r_dcache_error_type = MMU_NONE;
+                    drsp.valid = true;
+                    drsp.error = false;
+                    break;
+                case iss_t::XTN_INS_BAD_VADDR:
+                    drsp.rdata = (uint32_t)r_icache_bad_vaddr;       
+                    drsp.valid = true;
+                    drsp.error = false;
+                    break;
+                case iss_t::XTN_DATA_BAD_VADDR:
+                    drsp.rdata = (uint32_t)r_dcache_bad_vaddr;        
+                    drsp.valid = true;
+                    drsp.error = false;
+                    break;
+                case iss_t::XTN_PTPR:
+                    drsp.rdata = (uint32_t)r_mmu_ptpr;
+                    drsp.valid = true;
+                    drsp.error = false;
+                    break;
+                case iss_t::XTN_TLB_MODE:
+                    drsp.rdata = (uint32_t)r_mmu_mode;
+                    drsp.valid = true;
+                    drsp.error = false;
+                    break;
+                case iss_t::XTN_MMU_PARAMS:
+                    drsp.rdata = (uint32_t)r_mmu_params;
+                    drsp.valid = true;
+                    drsp.error = false;
+                    break;
+                case iss_t::XTN_MMU_RELEASE:
+                    drsp.rdata = (uint32_t)r_mmu_release;
+                    drsp.valid = true;
+                    drsp.error = false;
+                    break;
+                case iss_t::XTN_MMU_WORD_LO:
+                    drsp.rdata = (uint32_t)r_mmu_word_lo;
+                    drsp.valid = true;
+                    drsp.error = false;
+                    break;
+                case iss_t::XTN_MMU_WORD_HI:
+                    drsp.rdata = (uint32_t)r_mmu_word_hi;
+                    drsp.valid = true;
+                    drsp.error = false;
+                    break;
+                default:
+                    r_dcache_error_type = MMU_READ_UNDEFINED_XTN; 
+                    r_dcache_bad_vaddr  = dreq.addr;
+                    drsp.valid = true;
+                    drsp.error = true;
+                    break;
+                }
+                r_dcache_fsm = DCACHE_IDLE;
+                break;
+            }
+
+            // Decoding WRITE XTN requests from processor
+            // If there is no privilege violation, they are not executed in this DCACHE_IDLE state,
+            // but in the next state, because they generally require access to the caches or the TLBs 
+
+            if (dreq.type == iss_t::XTN_WRITE) 
+            {
+                drsp.valid = false;
+                drsp.error = false;
+                drsp.rdata = 0;
+                r_dcache_wdata_save = dreq.wdata;   
+                switch(xtn_opcod) {     
+
+                case iss_t::XTN_PTPR:       // context switch : checking the kernel mode
+                                            // both instruction & data TLBs must be flushed
+                    if ((dreq.mode == iss_t::MODE_HYPER) || (dreq.mode == iss_t::MODE_KERNEL)) 
+                    {
+                        r_mmu_ptpr = dreq.wdata;
+                        r_icache_error_type = MMU_NONE;
+                        r_dcache_error_type = MMU_NONE;
+                        r_dcache_type_save = dreq.addr/4; 
+                        r_dcache_xtn_req = true;
+                        r_dcache_fsm = DCACHE_CTXT_SWITCH;
+                    } 
+                    else 
+                    { 
+                        r_dcache_error_type = MMU_WRITE_PRIVILEGE_VIOLATION; 
+                        r_dcache_bad_vaddr  = dreq.addr;
+                        drsp.valid = true;
+                        drsp.error = true;
+                        r_dcache_fsm = DCACHE_IDLE;
+                    }
+                    break;
+
+                case iss_t::XTN_TLB_MODE:     // modifying TLBs mode : checking the kernel mode
+                    if ((dreq.mode == iss_t::MODE_HYPER) || (dreq.mode == iss_t::MODE_KERNEL)) 
+                    {
+                        r_mmu_mode = (int)dreq.wdata;
+                        drsp.valid = true;
+                    } 
+                    else 
+                    {
+                        r_dcache_error_type = MMU_WRITE_PRIVILEGE_VIOLATION; 
+                        r_dcache_bad_vaddr  = dreq.addr;
+                        drsp.valid = true;
+                        drsp.error = true;
+                    }
+                    r_dcache_fsm = DCACHE_IDLE;
+                    break;
+
+                case iss_t::XTN_DTLB_INVAL:     //  checking the kernel mode
+                    if ((dreq.mode == iss_t::MODE_HYPER) || (dreq.mode == iss_t::MODE_KERNEL)) 
+                    {
+                        r_dcache_fsm = DCACHE_DTLB_INVAL;  
+                    } 
+                    else 
+                    {
+                        r_dcache_error_type = MMU_WRITE_PRIVILEGE_VIOLATION; 
+                        r_dcache_bad_vaddr  = dreq.addr;
+                        drsp.valid = true;
+                        drsp.error = true;
+                        r_dcache_fsm = DCACHE_IDLE;
+                    }
+                    break;
+
+                case iss_t::XTN_ITLB_INVAL:     //  checking the kernel mode
+                    if ((dreq.mode == iss_t::MODE_HYPER) || (dreq.mode == iss_t::MODE_KERNEL)) 
+                    {
+                        r_dcache_xtn_req = true;
+                        r_dcache_type_save = dreq.addr/4;
+                        r_dcache_fsm = DCACHE_ITLB_INVAL;  
+                    } 
+                    else 
+                    {
+                        r_dcache_error_type = MMU_WRITE_PRIVILEGE_VIOLATION; 
+                        r_dcache_bad_vaddr  = dreq.addr;
+                        drsp.valid = true;
+                        drsp.error = true;
+                        r_dcache_fsm = DCACHE_IDLE;
+                    }
+                    break;
+
+                case iss_t::XTN_DCACHE_INVAL:   // cache inval can be executed in user mode.
+                    r_dcache_fsm = DCACHE_DCACHE_INVAL;
+                    break;
+
+                case iss_t::XTN_MMU_DCACHE_PA_INV:   // cache inval can be executed in user mode.
+                    r_dcache_fsm = DCACHE_DCACHE_INVAL_PA;
+                    break;
+
+                case iss_t::XTN_DCACHE_FLUSH:   // cache flush can be executed in user mode.
+                    r_dcache_way = 0;
+                    r_dcache_set = 0;
+                    r_dcache_fsm = DCACHE_DCACHE_FLUSH; 
+                    break;
+
+                case iss_t::XTN_ICACHE_INVAL:   // cache inval can be executed in user mode.
+                    r_dcache_type_save = dreq.addr/4; 
+                    r_dcache_xtn_req = true;
+                    r_dcache_fsm = DCACHE_ICACHE_INVAL; 
+                    break;
+
+                case iss_t::XTN_MMU_ICACHE_PA_INV:   // cache inval can be executed in user mode.
+                    r_dcache_type_save = dreq.addr/4; 
+                    r_dcache_xtn_req = true;
+                    r_dcache_fsm = DCACHE_ICACHE_INVAL_PA; 
+                    break;
+
+                case iss_t::XTN_ICACHE_FLUSH:   // cache flush can be executed in user mode.
+                    r_dcache_type_save = dreq.addr/4; 
+                    r_dcache_xtn_req = true; 
+                    r_dcache_fsm = DCACHE_ICACHE_FLUSH;
+                    break;
+
+                case iss_t::XTN_SYNC:           // cache synchronization can be executed in user mode.
+                    if (r_wbuf.rok())
+                    {
+                        r_dcache_fsm = DCACHE_DCACHE_SYNC; 
+                    }
+                    else
+                    {
+                        drsp.valid = true;
+                        r_dcache_fsm = DCACHE_IDLE;
+                    }
+		            break;
+
+                case iss_t::XTN_MMU_WORD_LO: // modifying MMU misc registers
+                    if ((dreq.mode == iss_t::MODE_HYPER) || (dreq.mode == iss_t::MODE_KERNEL)) 
+                    {
+                        r_mmu_word_lo = (int)dreq.wdata;
+                        drsp.valid = true;
+                    } 
+                    else 
+                    {
+                        r_dcache_error_type = MMU_WRITE_PRIVILEGE_VIOLATION; 
+                        r_dcache_bad_vaddr  = dreq.addr;
+                        drsp.valid = true;
+                        drsp.error = true;
+                    }
+                    r_dcache_fsm = DCACHE_IDLE;
+                    break;
+
+                case iss_t::XTN_MMU_WORD_HI: // modifying MMU misc registers
+                    if ((dreq.mode == iss_t::MODE_HYPER) || (dreq.mode == iss_t::MODE_KERNEL)) 
+                    {
+                        r_mmu_word_hi = (int)dreq.wdata;
+                        drsp.valid = true;
+                    } 
+                    else 
+                    {
+                        r_dcache_error_type = MMU_WRITE_PRIVILEGE_VIOLATION; 
+                        r_dcache_bad_vaddr  = dreq.addr;
+                        drsp.valid = true;
+                        drsp.error = true;
+                    }
+                    r_dcache_fsm = DCACHE_IDLE;
+                    break;
+
+                default:
+                    r_dcache_error_type = MMU_WRITE_UNDEFINED_XTN; 
+                    r_dcache_bad_vaddr  = dreq.addr;
+                    drsp.valid = true;
+                    drsp.error = true;
+                    r_dcache_fsm = DCACHE_IDLE;
+                    break;
+                } // end switch xtn_opcod
+
+                break;
+            } // end if XTN_WRITE
+
+            // Evaluating dcache_hit_t, dcache_hit_x, dcache_hit_p, dcache_hit_c,
+            // dcache_pte_info, dcache_tlb_way, dcache_tlb_set & dpaddr & cacheability 
+            // - If MMU activated : cacheability is defined by the cachable bit in the TLB
+            // - If MMU not activated : cacheability is defined by the segment table.
+
+            if ( !(r_mmu_mode.read() & DATA_TLB_MASK) ) // MMU not activated
+            {
+                dcache_hit_t  = true;       
+                dcache_hit_x  = true;   
+                dcache_hit_p  = true;  
+                tlb_dpaddr    = dreq.addr; 
+                spc_dpaddr    = dreq.addr;    
+                dcache_cached = m_cacheability_table[dreq.addr] && 
+                                ((dreq.type != iss_t::DATA_LL)  && (dreq.type != iss_t::DATA_SC) &&
+                                 (dreq.type != iss_t::XTN_READ) && (dreq.type != iss_t::XTN_WRITE));     
+            } 
+            else                                                            // MMU activated
+            {
+                m_cpt_data_tlb_read++;
+                dcache_hit_t  = dcache_tlb.cctranslate(dreq.addr, &tlb_dpaddr, &dcache_pte_info, &dcache_tlb_nline, 
+                                                       &dcache_tlb_way, &dcache_tlb_set);
+                dcache_hit_x  = (((vaddr_t)r_dcache_vpn_save << PAGE_K_NBITS) == (dreq.addr & ~PAGE_K_MASK)) && r_dtlb_translation_valid; 
+                dcache_hit_p  = (((dreq.addr >> PAGE_M_NBITS) == r_dcache_id1_save) && r_dcache_ptba_ok );
+                spc_dpaddr    = ((paddr_t)r_dcache_ppn_save << PAGE_K_NBITS) | (paddr_t)((dreq.addr & PAGE_K_MASK));
+                dcache_cached = dcache_pte_info.c &&
+                                 ((dreq.type != iss_t::DATA_LL)  && (dreq.type != iss_t::DATA_SC) &&
+                                  (dreq.type != iss_t::XTN_READ) && (dreq.type != iss_t::XTN_WRITE));     
+            }
+
+            if ( !(r_mmu_mode.read() & DATA_CACHE_MASK) )   // cache not actived
+            {
+                dcache_cached = false;
+            }
+
+            // dcache_hit_c & dcache_rdata
+            if ( dcache_cached )    // using speculative physical address for cached access
+            {
+                dcache_hit_c = r_dcache.read(spc_dpaddr, &dcache_rdata);
+            } 
+            else                    // using actual physical address for uncached access
+            {
+                dcache_hit_c = ((tlb_dpaddr == (paddr_t)r_dcache_paddr_save) && r_vci_rsp_data_ok ); 
+                dcache_rdata = r_dcache_miss_buf[0];
+            }
+
+            if ( r_mmu_mode.read() & DATA_TLB_MASK ) 
+            {
+                // Checking access rights
+                if ( dcache_hit_t ) 
+                {
+                    if (!dcache_pte_info.u && (dreq.mode == iss_t::MODE_USER)) 
+                    {
+                        if ((dreq.type == iss_t::DATA_READ)||(dreq.type == iss_t::DATA_LL))
+                        {
+                            r_dcache_error_type = MMU_READ_PRIVILEGE_VIOLATION;
+                        }
+                        else /*if ((dreq.type == iss_t::DATA_WRITE)||(dreq.type == iss_t::DATA_SC))*/
+                        {
+                            r_dcache_error_type = MMU_WRITE_PRIVILEGE_VIOLATION;
+                        }  
+                        r_dcache_bad_vaddr = dreq.addr;
+                        drsp.valid = true;
+                        drsp.error = true;
+                        drsp.rdata = 0;
+                        r_dcache_fsm = DCACHE_IDLE;
+                        break;
+                    }
+                    if (!dcache_pte_info.w && ((dreq.type == iss_t::DATA_WRITE)||(dreq.type == iss_t::DATA_SC))) 
+                    {
+                        r_dcache_error_type = MMU_WRITE_ACCES_VIOLATION;  
+                        r_dcache_bad_vaddr = dreq.addr;
+                        drsp.valid = true;
+                        drsp.error = true;
+                        drsp.rdata = 0;
+                        r_dcache_fsm = DCACHE_IDLE;
+                        break;
+                    }
+                }
+
+                // update LRU, save ppn, vpn and page type
+                if ( dcache_hit_t ) 
+                {
+                    dcache_tlb.setlru(dcache_tlb_way,dcache_tlb_set); 
+                    r_dcache_ppn_save = tlb_dpaddr >> PAGE_K_NBITS;
+                    r_dcache_vpn_save = dreq.addr >> PAGE_K_NBITS;
+                    r_dcache_tlb_nline = dcache_tlb_nline;
+                    r_dtlb_translation_valid = true;
+                }
+                else
+                {
+                    r_dtlb_translation_valid = false;
+                }
+
+            } // end if MMU activated
+
+            // compute next state 
+            if ( !dcache_hit_p && !dcache_hit_t )  // TLB miss
+            {
+                // walk page table level 1
+                r_dcache_tlb_paddr = (paddr_t)r_mmu_ptpr << (INDEX1_NBITS+2) | (paddr_t)((dreq.addr>>PAGE_M_NBITS)<<2);
+                r_dcache_tlb_read_req = true;
+                r_dcache_tlb_first_req = true;
+                r_vci_rsp_data_ok = false;
+                r_dcache_fsm = DCACHE_TLB1_READ;
+                m_cpt_data_tlb_miss++;
+                m_cost_data_tlb_miss_frz++;
+            }
+            else if ( dcache_hit_p && !dcache_hit_t )  // TLB Miss with possibility of bypass first level page
+            {
+                // walk page table level 2
+                r_dcache_tlb_paddr = (paddr_t)r_dcache_ptba_save | 
+                                     (paddr_t)(((dreq.addr&PTD_ID2_MASK)>>PAGE_K_NBITS) << 3); 
+                r_dcache_tlb_read_req = true;
+                r_dcache_tlb_first_req = false;
+                r_vci_rsp_data_ok = false;
+                r_dcache_fsm = DCACHE_TLB2_READ;
+                m_cpt_data_tlb_miss++;
+                m_cost_data_tlb_miss_frz++;
+            }
+            else if ( dcache_hit_t && !dcache_hit_x && dcache_cached )// cached access with an ucorrect speculative physical address
+            {
+                r_dcache_hit_p_save = dcache_hit_p;
+                r_dcache_fsm = DCACHE_BIS;
+                m_cost_data_miss_frz++;
+            }
+            else  // cached or uncached access with a correct speculative physical address
+            {
+                switch( dreq.type ) {
+                    case iss_t::DATA_READ:
+                    case iss_t::DATA_LL:
+                    case iss_t::DATA_SC:
+                        m_cpt_read++;
+                        if ( dcache_hit_c ) 
+                        {
+                            r_vci_rsp_data_ok = false;
+                            r_dcache_fsm = DCACHE_IDLE;
+                            drsp.valid = true;
+                            drsp.rdata = dcache_rdata;
+                        } 
+                        else 
+                        {
+                            if ( dcache_cached ) 
+                            {
+                                r_dcache_miss_req = true;
+                                r_vci_rsp_data_ok = false;
+                                r_dcache_fsm = DCACHE_MISS_WAIT;
+                                m_cpt_data_miss++;
+                                m_cost_data_miss_frz++;
+                            } 
+                            else 
+                            {
+                                r_dcache_unc_req = true;
+                                r_vci_rsp_data_ok = false;
+                                r_dcache_fsm = DCACHE_UNC_WAIT;
+                                m_cpt_unc_read++;
+                                m_cost_unc_read_frz++;
+                            }
+                        }
+                        break;
+                    case iss_t::DATA_WRITE:
+                        m_cpt_write++;
+                        if ( dcache_cached ) m_cpt_write_cached++;
+
+                        if ( dcache_hit_c && dcache_cached )    // cache update required
+                        {
+                            r_dcache_fsm = DCACHE_WRITE_UPDT;
+
+                        } 
+                        else if ( !dcache_pte_info.d && (r_mmu_mode.read() & DATA_TLB_MASK) )   // dirty bit update required
+                        {
+                            if (dcache_tlb.getpagesize(dcache_tlb_way, dcache_tlb_set)) 
+                            {
+                                r_dcache_pte_update = dcache_tlb.getpte(dcache_tlb_way, dcache_tlb_set) | PTE_D_MASK;
+                                r_dcache_tlb_paddr = (paddr_t)r_mmu_ptpr << (INDEX1_NBITS+2) | (paddr_t)((dreq.addr>>PAGE_M_NBITS)<<2);
+                                r_dcache_tlb_ll_dirty_req = true;
+                                r_vci_rsp_data_ok = false;
+                                r_dcache_fsm = DCACHE_LL_DIRTY_WAIT;
+                                m_cpt_data_tlb_write_dirty++;
+                            }
+                            else
+                            {   
+                                if (dcache_hit_p) 
+                                {
+                                    r_dcache_pte_update = dcache_tlb.getpte(dcache_tlb_way, dcache_tlb_set) | PTE_D_MASK;
+                                    r_dcache_tlb_paddr = (paddr_t)r_dcache_ptba_save | (paddr_t)(((dreq.addr&PTD_ID2_MASK)>>PAGE_K_NBITS) << 3);
+                                    r_dcache_tlb_ll_dirty_req = true;
+                                    r_vci_rsp_data_ok = false;
+                                    r_dcache_fsm = DCACHE_LL_DIRTY_WAIT;
+                                    m_cpt_data_tlb_write_dirty++;
+                                }
+                                else    // get PTBA to calculate the physical address of PTE
+                                {
+                                    r_dcache_pte_update = dcache_tlb.getpte(dcache_tlb_way, dcache_tlb_set) | PTE_D_MASK;
+                                    r_dcache_tlb_paddr = (paddr_t)r_mmu_ptpr << (INDEX1_NBITS+2) | (paddr_t)((dreq.addr>>PAGE_M_NBITS)<<2);
+                                    r_dcache_tlb_read_req = true;
+                                    r_dcache_tlb_first_req = true;
+                                    r_dcache_tlb_ptba_read = true;
+                                    r_vci_rsp_data_ok = false;
+                                    r_dcache_fsm = DCACHE_TLB1_READ;
+                                }
+                            }
+                            m_cost_data_tlb_miss_frz++;
+                        }
+                        else                                    // no cache update, not dirty bit update
+                        {
+                            r_dcache_fsm = DCACHE_WRITE_REQ;
+                            drsp.valid = true;
+                            drsp.rdata = 0;
+                        }
+                        break;
+                    default:
+                        break;
+                } // end switch dreq.type
+            } // end if next states
+
+            // save values for the next states
+            r_dcache_paddr_save   = tlb_dpaddr;
+            r_dcache_type_save    = dreq.type;
+            r_dcache_wdata_save   = dreq.wdata;
+            r_dcache_be_save      = dreq.be;
+            r_dcache_rdata_save   = dcache_rdata;
+            r_dcache_cached_save  = dcache_cached;
+            r_dcache_dirty_save   = dcache_pte_info.d;
+            r_dcache_tlb_set_save = dcache_tlb_set;
+            r_dcache_tlb_way_save = dcache_tlb_way;
+
+        } // end if dreq.valid
+        else 
+        {   
+            r_dcache_fsm = DCACHE_IDLE;
+        }
+        break;
+    }
+    /////////////////
+    case DCACHE_BIS:
+    {
+        // external cache invalidate request
+        if ( r_tgt_dcache_req )   
+        {
+            r_dcache_fsm = DCACHE_CC_CHECK;
+            r_dcache_fsm_save = r_dcache_fsm;
+            if ( dreq.valid ) m_cost_data_miss_frz++;
+            break;
+        }
+
+        if ( r_dcache_inval_tlb_rsp )
+        {
+            r_dcache_inval_tlb_rsp = false;
+            r_dcache_fsm = DCACHE_IDLE;
+            if ( dreq.valid ) m_cost_data_miss_frz++;
+            break;
+        }
+
+        data_t      dcache_rdata = 0;
+        bool        dcache_hit_c = false;
+        bool        dcache_hit_t = false;
+        paddr_t     tlb_dpaddr   = 0;  
+
+        // processor address translation
+        dcache_hit_t = dcache_tlb.translate(dreq.addr, &tlb_dpaddr);
+
+        if ( (tlb_dpaddr == r_dcache_paddr_save.read()) && dreq.valid && dcache_hit_t )     // unmodified & valid
+        {
+            // acces always cached in this state
+            dcache_hit_c = r_dcache.read(r_dcache_paddr_save, &dcache_rdata);
+            
+            if ( dreq.type == iss_t::DATA_READ )  // cached read
+            {
+                m_cpt_read++;
+                if ( !dcache_hit_c ) 
+                {
+                    r_dcache_miss_req = true;
+                    r_vci_rsp_data_ok = false;
+                    r_dcache_fsm = DCACHE_MISS_WAIT;
+                    m_cpt_data_miss++;
+                    m_cost_data_miss_frz++;
+                }
+                else
+                {
+                    r_dcache_fsm = DCACHE_IDLE;
+                }
+                drsp.valid = dcache_hit_c;
+                drsp.error = false;
+                drsp.rdata = dcache_rdata;
+            }
+            else    // cached write
+            {
+                m_cpt_write++;
+                m_cpt_write_cached++;
+                if ( dcache_hit_c )    // cache update required
+                {
+                	r_dcache_rdata_save = dcache_rdata;
+                    r_dcache_fsm = DCACHE_WRITE_UPDT;
+            
+                } 
+                else if ( !r_dcache_dirty_save && (r_mmu_mode.read() & DATA_TLB_MASK) )   // dirty bit update required
+                {
+                    if (dcache_tlb.getpagesize(r_dcache_tlb_way_save, r_dcache_tlb_set_save)) 
+                    {
+                        r_dcache_pte_update = dcache_tlb.getpte(r_dcache_tlb_way_save, r_dcache_tlb_set_save) | PTE_D_MASK;
+                        r_dcache_tlb_paddr = (paddr_t)r_mmu_ptpr << (INDEX1_NBITS+2) | (paddr_t)((dreq.addr>>PAGE_M_NBITS)<<2);
+                        r_dcache_tlb_ll_dirty_req = true;
+                        r_vci_rsp_data_ok = false;
+                        r_dcache_fsm = DCACHE_LL_DIRTY_WAIT;
+                        m_cpt_data_tlb_write_dirty++;
+                    }
+                    else
+                    {   
+                        if (r_dcache_hit_p_save) 
+                        {
+                            r_dcache_pte_update = dcache_tlb.getpte(r_dcache_tlb_way_save, r_dcache_tlb_set_save) | PTE_D_MASK;
+                            r_dcache_tlb_paddr = (paddr_t)r_dcache_ptba_save|(paddr_t)(((dreq.addr&PTD_ID2_MASK)>>PAGE_K_NBITS) << 3);
+                            r_dcache_tlb_ll_dirty_req = true;
+                            r_vci_rsp_data_ok = false;
+                            r_dcache_fsm = DCACHE_LL_DIRTY_WAIT;
+                            m_cpt_data_tlb_write_dirty++;
+                        }
+                        else
+                        {
+                            r_dcache_pte_update = dcache_tlb.getpte(r_dcache_tlb_way_save, r_dcache_tlb_set_save) | PTE_D_MASK;
+                            r_dcache_tlb_paddr = (paddr_t)r_mmu_ptpr << (INDEX1_NBITS+2) | (paddr_t)((dreq.addr>>PAGE_M_NBITS)<<2);
+                            r_dcache_tlb_read_req = true;
+                            r_dcache_tlb_first_req = true;
+                            r_dcache_tlb_ptba_read = true;
+                            r_vci_rsp_data_ok = false;
+                            r_dcache_fsm = DCACHE_TLB1_READ;
+                        }
+                    }
+                    m_cost_data_tlb_miss_frz++;
+                }
+                else                                    // no cache update, not dirty bit update
+                {
+                    r_dcache_fsm = DCACHE_WRITE_REQ;
+                    drsp.valid = true;
+                    drsp.rdata = 0;
+                }
+            }
+        }
+        else
+        {
+            drsp.valid = false;
+            drsp.error = false;
+            drsp.rdata = 0;
+            r_dcache_fsm = DCACHE_IDLE;
+        }
+        break;
+    }
+    //////////////////////////
+    case DCACHE_LL_DIRTY_WAIT:
+    {
+        // external cache invalidate request
+        if ( r_tgt_dcache_req )   
+        {
+            r_dcache_fsm = DCACHE_CC_CHECK;
+            r_dcache_fsm_save = r_dcache_fsm;
+            //m_cost_data_waste_wait_frz++;
+            break;
+        }
+
+        if ( r_vci_rsp_data_ok )
+        {
+            if ( r_vci_rsp_data_error ) // VCI response ko
+            {
+                if (dcache_tlb.getpagesize(r_dcache_tlb_way_save, r_dcache_tlb_set_save)) 
+                {
+                    r_dcache_error_type = MMU_WRITE_PT1_ILLEGAL_ACCESS;     
+                }
+                else
+                {
+                    r_dcache_error_type = MMU_WRITE_PT2_ILLEGAL_ACCESS;     
+                }
+                r_dcache_bad_vaddr = dreq.addr;
+                r_dcache_fsm = DCACHE_ERROR;
+ 
+		        if (r_dcache_inval_tlb_rsp) r_dcache_inval_tlb_rsp = false;
+		        if (r_dcache_inval_rsp) r_dcache_inval_rsp = false;
+            }
+            else
+            {
+                if ( !(r_dcache_miss_buf[0] >> PTE_V_SHIFT) )	// unmapped
+                {
+        	        if (dcache_tlb.getpagesize(r_dcache_tlb_way_save, r_dcache_tlb_set_save))
+        	        { 
+        	            r_dcache_error_type = MMU_WRITE_PT1_UNMAPPED;       
+        	        }
+        	        else
+        	        {
+        	            r_dcache_error_type = MMU_WRITE_PT2_UNMAPPED;       
+          	        }
+                    r_dcache_bad_vaddr = dreq.addr;
+                    r_dcache_fsm = DCACHE_ERROR;
+
+		            if (r_dcache_inval_tlb_rsp) r_dcache_inval_tlb_rsp = false;
+		            if (r_dcache_inval_rsp) r_dcache_inval_rsp = false;
+                }
+                else if ( r_dcache_inval_tlb_rsp )
+                {
+                    r_dcache_inval_tlb_rsp = false;
+                    r_dcache_fsm = DCACHE_IDLE;
+                    m_cost_data_tlb_miss_frz++;
+                }
+	            else if ( r_dcache_inval_rsp )
+	            {
+                	r_dcache_inval_rsp = false;
+	                r_dcache_fsm = DCACHE_IDLE;
+	            }
+        	    else
+        	    {
+        	        r_dcache_tlb_sc_dirty_req = true;
+                    r_vci_rsp_data_ok = false;
+                    r_dcache_pte_update = r_dcache_miss_buf[0] | r_dcache_pte_update.read();
+                    r_dcache_fsm = DCACHE_SC_DIRTY_WAIT; 
+        	    }
+            }
+        }
+        break;
+    }
+    //////////////////////////
+    case DCACHE_SC_DIRTY_WAIT:
+    {
+        // external cache invalidate request
+        if ( r_tgt_dcache_req )   
+        {
+            r_dcache_fsm = DCACHE_CC_CHECK;
+            r_dcache_fsm_save = r_dcache_fsm;
+            //m_cost_data_waste_wait_frz++;
+            break;
+        }
+
+        if ( r_vci_rsp_data_ok ) // VCI response 
+        {
+            if ( r_vci_rsp_data_error ) // VCI response ko
+	        {
+	            if (dcache_tlb.getpagesize(r_dcache_tlb_way_save, r_dcache_tlb_set_save))
+	            {
+	                r_dcache_error_type = MMU_WRITE_PT1_ILLEGAL_ACCESS;    
+	            }
+	            else
+	            {
+	                r_dcache_error_type = MMU_WRITE_PT2_ILLEGAL_ACCESS;    
+ 	            }
+	            r_dcache_bad_vaddr = dreq.addr;
+	            r_dcache_fsm = DCACHE_ERROR; 
+
+		        if (r_dcache_inval_tlb_rsp) r_dcache_inval_tlb_rsp = false;
+		        if (r_dcache_inval_rsp) r_dcache_inval_rsp = false;
+            }
+            else
+            {
+                // Using tlb entry is invalidated 
+                if ( r_dcache_inval_tlb_rsp )
+                {
+                    r_dcache_inval_tlb_rsp = false;
+                    if (r_dcache_tlb_sc_fail) r_dcache_tlb_sc_fail = false;
+                    r_dcache_fsm = DCACHE_IDLE;
+                    m_cost_data_tlb_miss_frz++;
+                }
+	            else if ( r_dcache_inval_rsp )
+	            {
+                	r_dcache_inval_rsp = false;
+                    if (r_dcache_tlb_sc_fail) r_dcache_tlb_sc_fail = false;
+	                r_dcache_fsm = DCACHE_IDLE;
+	            }
+	            else if ( r_dcache_tlb_sc_fail )
+	            {
+                    r_dcache_tlb_ll_dirty_req = true;
+                    r_dcache_tlb_sc_fail = false;
+                    r_vci_rsp_data_ok = false;
+	                r_dcache_fsm = DCACHE_LL_DIRTY_WAIT; 
+	            }
+                else 
+                {
+                    r_vci_rsp_data_ok = false;
+                    r_dcache_fsm = DCACHE_WRITE_DIRTY; 
+                }
+            }
+        }
+        break;
+    }
+    //////////////////////
+    case DCACHE_TLB1_READ:
+    {
+        if ( dreq.valid ) m_cost_data_tlb_miss_frz++;
+
+        // external cache invalidate request
+        if ( r_tgt_dcache_req )   
+        {
+            r_dcache_fsm = DCACHE_CC_CHECK;
+            r_dcache_fsm_save = r_dcache_fsm;
+            break;
+        }        
+
+        if ( r_dcache_cleanup_req ) break;
+
+        if ( r_vci_rsp_data_ok ) // VCI response ok
+        {
+            if ( r_vci_rsp_data_error )
+            {    
+                if ((r_dcache_type_save == iss_t::DATA_READ)||(r_dcache_type_save == iss_t::DATA_LL))
+                {
+                    r_dcache_error_type = MMU_READ_PT1_ILLEGAL_ACCESS;
+                }
+                else /*if ((dreq.type == iss_t::DATA_WRITE)||(dreq.type == iss_t::DATA_SC))*/
+                {
+                    r_dcache_error_type = MMU_WRITE_PT1_ILLEGAL_ACCESS;
+                } 
+                r_dcache_bad_vaddr = dreq.addr;
+                r_dcache_fsm = DCACHE_ERROR; 
+                
+		        if (r_dcache_inval_tlb_rsp) r_dcache_inval_tlb_rsp = false;
+		        if (r_dcache_inval_rsp) r_dcache_inval_rsp = false;	
+		        break;
+            }
+
+            if ( r_dcache_inval_tlb_rsp )  // TLB miss response and invalidation
+            {
+                r_dcache_fsm = DCACHE_IDLE;
+                r_dcache_cleanup_req = true;
+                r_dcache_cleanup_line = r_dcache_tlb_paddr.read() >> (uint32_log2(m_dcache_words) + 2);  
+                r_dcache_cleanup_type = TLB_CLEANUP;
+            	r_dcache_inval_tlb_rsp = false;
+		        break;
+            }
+
+	        if ( !(r_dcache_miss_buf[0] >> PTE_V_SHIFT) )	// unmapped
+	        {
+                r_dcache_ptba_ok    = false;
+                if ((r_dcache_type_save == iss_t::DATA_READ)||(r_dcache_type_save == iss_t::DATA_LL))
+                {
+                    r_dcache_error_type = MMU_READ_PT1_UNMAPPED;
+                }
+                else /*if ((dreq.type == iss_t::DATA_WRITE)||(dreq.type == iss_t::DATA_SC))*/
+                {
+                    r_dcache_error_type = MMU_WRITE_PT1_UNMAPPED;
+                }  
+                r_dcache_bad_vaddr  = dreq.addr;
+                r_dcache_fsm        = DCACHE_ERROR;
+	        }
+	        else if ( (r_dcache_miss_buf[0] & PTE_T_MASK) >> PTE_T_SHIFT ) // PTD
+	        {
+                r_dcache_ptba_ok   = true;
+                r_dcache_ptba_save = (paddr_t)(r_dcache_miss_buf[0] & ((1<<(m_paddr_nbits - PAGE_K_NBITS))-1)) << PAGE_K_NBITS;  
+                r_dcache_id1_save  = dreq.addr >> PAGE_M_NBITS;
+                r_dcache_tlb_paddr = (paddr_t)(r_dcache_miss_buf[0] & ((1<<(m_paddr_nbits - PAGE_K_NBITS))-1)) << PAGE_K_NBITS | 
+                                     (paddr_t)(((dreq.addr & PTD_ID2_MASK) >> PAGE_K_NBITS) << 3);
+                r_vci_rsp_data_ok = false;
+                if ( r_dcache_tlb_ptba_read )
+                {
+                    r_dcache_tlb_ptba_read = false;
+                    r_dcache_tlb_ll_dirty_req = true;
+                    r_dcache_fsm = DCACHE_LL_DIRTY_WAIT;
+                    m_cpt_data_tlb_write_dirty++;
+                }
+                else
+                {
+                    r_dcache_tlb_read_req = true;
+                    r_dcache_tlb_first_req = false;
+                    r_dcache_fsm = DCACHE_TLB2_READ;
+                }
+
+                // cleanup PTD in L2, because it's not keep in L1
+                r_dcache_cleanup_req = true;
+                r_dcache_cleanup_line = r_dcache_tlb_paddr.read() >> (uint32_log2(m_dcache_words) + 2);  
+                r_dcache_cleanup_type = TLB_CLEANUP;
+
+	        }
+	        else	// PTE
+	        {
+                r_dcache_ptba_ok = false;
+	            if ( (m_srcid_rw >> 4) == ((r_dcache_tlb_paddr.read() & ((1<<(m_paddr_nbits - PAGE_M_NBITS))-1)) >> (m_paddr_nbits - PAGE_M_NBITS -10)) ) // local
+	            {
+	                if ( (r_dcache_miss_buf[0] & PTE_L_MASK ) >> PTE_L_SHIFT ) // L bit is set
+	                {
+                        r_dcache_pte_update = r_dcache_miss_buf[0];
+                        r_vci_rsp_data_ok   = false;
+                        r_dcache_fsm        = DCACHE_TLB1_UPDT;
+	                }
+	                else
+	                {
+                        r_dcache_pte_update = r_dcache_miss_buf[0] | PTE_L_MASK;
+                        r_dcache_tlb_ll_acc_req = true;
+                        r_vci_rsp_data_ok = false;
+                        r_dcache_fsm        = DCACHE_TLB1_LL_WAIT;
+                        m_cpt_ins_tlb_write_et++;
+	                }
+                }
+	            else // remotely
+	            {
+	                if ( (r_dcache_miss_buf[0] & PTE_R_MASK ) >> PTE_R_SHIFT ) // R bit is set
+	                {
+                        r_dcache_pte_update = r_dcache_miss_buf[0];
+                        r_vci_rsp_data_ok   = false;
+                        r_dcache_fsm        = DCACHE_TLB1_UPDT;
+	                }
+	                else
+	                {
+                        r_dcache_pte_update = r_dcache_miss_buf[0] | PTE_R_MASK;
+                        r_dcache_tlb_ll_acc_req = true;
+                        r_vci_rsp_data_ok = false;
+                        r_dcache_fsm        = DCACHE_TLB1_LL_WAIT;
+                        m_cpt_ins_tlb_write_et++;
+	                }
+	            }
+	        }
+        }
+        break;
+    }
+    ///////////////////////
+    case DCACHE_TLB1_LL_WAIT:
+    {
+        // external cache invalidate request
+        if ( r_tgt_dcache_req )   
+        {
+            r_dcache_fsm = DCACHE_CC_CHECK;
+            r_dcache_fsm_save = r_dcache_fsm;
+            break;
+        }    
+
+	    if ( r_vci_rsp_data_ok )
+	    {
+            if ( r_vci_rsp_data_error ) // VCI response ko
+            {
+                if ((r_dcache_type_save == iss_t::DATA_READ)||(r_dcache_type_save == iss_t::DATA_LL))
+                {
+                    r_dcache_error_type = MMU_READ_PT1_ILLEGAL_ACCESS;
+                }
+                else /*if ((dreq.type == iss_t::DATA_WRITE)||(dreq.type == iss_t::DATA_SC))*/
+                {
+                    r_dcache_error_type = MMU_WRITE_PT1_ILLEGAL_ACCESS;
+                } 
+                r_dcache_bad_vaddr = dreq.addr;
+                r_dcache_fsm = DCACHE_ERROR; 
+
+		        if (r_dcache_inval_tlb_rsp) r_dcache_inval_tlb_rsp = false;
+            }
+	        else
+	        {
+	            if ( !(r_dcache_miss_buf[0] >> PTE_V_SHIFT) )	// unmapped
+	            {
+                    if ((r_dcache_type_save == iss_t::DATA_READ)||(r_dcache_type_save == iss_t::DATA_LL))
+                    {
+                        r_dcache_error_type = MMU_READ_PT1_UNMAPPED;
+                    }
+                    else /*if ((dreq.type == iss_t::DATA_WRITE)||(dreq.type == iss_t::DATA_SC))*/
+                    {
+                        r_dcache_error_type = MMU_WRITE_PT1_UNMAPPED;
+                    }  
+                    r_dcache_bad_vaddr  = dreq.addr;
+                    r_dcache_fsm        = DCACHE_ERROR;
+
+		            if (r_dcache_inval_tlb_rsp) r_dcache_inval_tlb_rsp = false;
+	            }
+       	        else if ( r_dcache_inval_tlb_rsp )
+       	        {
+       	            r_dcache_inval_tlb_rsp = false;
+       	            r_dcache_fsm = DCACHE_IDLE;
+       	            m_cost_data_tlb_miss_frz++;
+       	        }
+		        else
+		        {
+		            r_dcache_tlb_sc_acc_req = true;
+                    r_vci_rsp_data_ok = false;
+                    r_dcache_pte_update = r_dcache_miss_buf[0] | r_dcache_pte_update.read();
+                    r_dcache_fsm = DCACHE_TLB1_SC_WAIT; 
+		        }
+	        }
+	    }
+	    break;
+    }
+    ///////////////////////
+    case DCACHE_TLB1_SC_WAIT:
+    {
+        // external cache invalidate request
+        if ( r_tgt_dcache_req )   
+        {
+            r_dcache_fsm = DCACHE_CC_CHECK;
+            r_dcache_fsm_save = r_dcache_fsm;
+            break;
+        }    
+
+        if ( r_vci_rsp_data_ok ) // VCI response ko
+        {
+            if ( r_vci_rsp_data_error ) // VCI response ko
+	        {
+                if ((r_dcache_type_save == iss_t::DATA_READ)||(r_dcache_type_save == iss_t::DATA_LL))
+                {
+                    r_dcache_error_type = MMU_READ_PT1_ILLEGAL_ACCESS;
+                }
+                else /*if ((dreq.type == iss_t::DATA_WRITE)||(dreq.type == iss_t::DATA_SC))*/
+                {
+                    r_dcache_error_type = MMU_WRITE_PT1_ILLEGAL_ACCESS;
+                } 
+	            r_dcache_bad_vaddr = dreq.addr;
+	            r_dcache_fsm = DCACHE_ERROR; 
+
+		        if (r_dcache_inval_tlb_rsp) r_dcache_inval_tlb_rsp = false;
+	        }
+            else
+            {
+                // Using tlb entry is invalidated 
+                if ( r_dcache_inval_tlb_rsp )
+                {
+                    r_dcache_inval_tlb_rsp = false;
+                    if (r_dcache_tlb_sc_fail) r_dcache_tlb_sc_fail = false;
+                    r_dcache_fsm = DCACHE_IDLE;
+                    m_cost_data_tlb_miss_frz++;
+                }
+	            else if ( r_dcache_tlb_sc_fail )
+	            {
+                    r_dcache_tlb_ll_acc_req = true;
+                    r_dcache_tlb_sc_fail = false;
+                    r_vci_rsp_data_ok = false;
+	                r_dcache_fsm = DCACHE_TLB1_LL_WAIT; 
+	            }
+	            else
+	            {
+                    r_vci_rsp_data_ok = false;
+	                r_dcache_fsm = DCACHE_TLB1_UPDT; 
+	            }
+            }
+        }
+	    break;
+    }
+    //////////////////////
+    case DCACHE_TLB1_UPDT: 
+    {
+        if ( dreq.valid ) m_cost_data_tlb_miss_frz++;
+
+        // external cache invalidate request
+        if ( r_tgt_dcache_req )   
+        {
+            r_dcache_fsm = DCACHE_CC_CHECK;
+            r_dcache_fsm_save = r_dcache_fsm;
+            //m_cost_data_waste_wait_frz++;
+            break;
+        }
+        
+        // TLB update and invalidate different PTE
+        if ( !r_dcache_inval_tlb_rsp && !r_dcache_cleanup_req)
+        {
+            paddr_t victim_index = 0;
+            r_dcache_cleanup_req = dcache_tlb.update1(r_dcache_pte_update,dreq.addr,(r_dcache_tlb_paddr.read() >> (uint32_log2(m_dcache_words)+2)),&victim_index);
+            r_dcache_cleanup_line = victim_index;
+            r_dcache_cleanup_type = TLB_CLEANUP; 
+            r_dcache_fsm = DCACHE_IDLE;
+        }
+
+        // TLB update and invalidate same PTE
+        if ( r_dcache_inval_tlb_rsp )                                 
+        {
+            r_dcache_inval_tlb_rsp = false;
+            r_dcache_fsm = DCACHE_IDLE;
+        }
+        break;
+    }
+    /////////////////////
+    case DCACHE_TLB2_READ:
+    {
+        if ( dreq.valid ) m_cost_data_tlb_miss_frz++;
+
+        // external cache invalidate request
+        if ( r_tgt_dcache_req )   
+        {
+            r_dcache_fsm = DCACHE_CC_CHECK;
+            r_dcache_fsm_save = r_dcache_fsm;
+            break;
+        }        
+
+        if ( r_vci_rsp_data_ok ) // VCI response ok
+        {
+            if ( r_vci_rsp_data_error )
+            {
+                if ((r_dcache_type_save == iss_t::DATA_READ)||(r_dcache_type_save == iss_t::DATA_LL))
+                {
+                    r_dcache_error_type = MMU_READ_PT2_ILLEGAL_ACCESS;
+                }
+                else /*if ((dreq.type == iss_t::DATA_WRITE)||(dreq.type == iss_t::DATA_SC))*/
+                {
+                    r_dcache_error_type = MMU_WRITE_PT2_ILLEGAL_ACCESS;
+                } 
+                r_dcache_bad_vaddr = dreq.addr;
+                r_dcache_fsm = DCACHE_ERROR;
+
+                if (r_dcache_inval_tlb_rsp) r_dcache_inval_tlb_rsp = false;
+		        if (r_dcache_inval_rsp) r_dcache_inval_rsp = false;	
+		        break;
+            }    
+
+            if ( r_dcache_inval_tlb_rsp )  // TLB miss response and invalidation
+            {
+                if (r_dcache_cleanup_req) break;
+                r_dcache_fsm = DCACHE_IDLE; 
+                r_dcache_cleanup_req = true;
+                r_dcache_cleanup_line = r_dcache_tlb_paddr.read() >> (uint32_log2(m_dcache_words) + 2);  
+                r_dcache_cleanup_type = TLB_CLEANUP;
+            	r_dcache_inval_tlb_rsp = false;
+		        break;
+            }
+
+	        if ( !(r_dcache_miss_buf[0] >> PTE_V_SHIFT) )	// unmapped
+	        {
+                if ((r_dcache_type_save == iss_t::DATA_READ)||(r_dcache_type_save == iss_t::DATA_LL))
+                {
+                    r_dcache_error_type = MMU_READ_PT2_UNMAPPED;
+                }
+                else /*if ((dreq.type == iss_t::DATA_WRITE)||(dreq.type == iss_t::DATA_SC))*/
+                {
+                    r_dcache_error_type = MMU_WRITE_PT2_UNMAPPED;
+                }  
+                r_dcache_bad_vaddr  = dreq.addr;
+                r_dcache_fsm        = DCACHE_ERROR;
+	        }
+	        else if ( (r_dcache_miss_buf[0] & PTE_T_MASK) >> PTE_T_SHIFT ) // PTD
+	        {
+                r_dcache_pte_update = r_dcache_miss_buf[0];
+                r_vci_rsp_data_ok = false;
+	            r_dcache_fsm = DCACHE_TLB2_UPDT;
+	        }
+            else
+            {
+	            if ( (m_srcid_rw >> 4) == ((r_dcache_tlb_paddr.read() & ((1<<(m_paddr_nbits - PAGE_M_NBITS))-1)) >> (m_paddr_nbits - PAGE_M_NBITS -10)) ) // local
+	            {
+	                if ( (r_dcache_miss_buf[0] & PTE_L_MASK ) >> PTE_L_SHIFT ) // L bit is set
+	                {
+                        r_dcache_pte_update = r_dcache_miss_buf[0];
+                        r_vci_rsp_data_ok   = false;
+                        r_dcache_fsm        = DCACHE_TLB2_UPDT;
+	                }
+	                else
+	                {
+                        r_dcache_pte_update = r_dcache_miss_buf[0] | PTE_L_MASK;
+                        r_dcache_tlb_ll_acc_req = true;
+                        r_vci_rsp_data_ok = false; 
+                        r_dcache_fsm = DCACHE_TLB2_LL_WAIT;
+                        m_cpt_ins_tlb_write_et++;
+	                }
+                }
+	            else // remotely
+	            {
+	                if ( (r_dcache_miss_buf[0] & PTE_R_MASK ) >> PTE_R_SHIFT ) // R bit is set
+	                {
+                        r_dcache_pte_update = r_dcache_miss_buf[0];
+                        r_vci_rsp_data_ok   = false;
+                        r_dcache_fsm        = DCACHE_TLB2_UPDT;
+	                }
+	                else
+	                {
+                        r_dcache_pte_update = r_dcache_miss_buf[0] | PTE_R_MASK;
+                        r_dcache_tlb_ll_acc_req = true;
+                        r_vci_rsp_data_ok = false;
+                        r_dcache_fsm = DCACHE_TLB2_LL_WAIT;
+                        m_cpt_ins_tlb_write_et++;
+	                }
+	            }
+            }
+        }  
+        break;
+    }
+    ///////////////////////
+    case DCACHE_TLB2_LL_WAIT:
+    {
+        // external cache invalidate request
+        if ( r_tgt_dcache_req )   
+        {
+            r_dcache_fsm = DCACHE_CC_CHECK;
+            r_dcache_fsm_save = r_dcache_fsm;
+            break;
+        }    
+
+	    if ( r_vci_rsp_data_ok )
+	    {
+            if ( r_vci_rsp_data_error ) // VCI response ko
+            {
+                if ((r_dcache_type_save == iss_t::DATA_READ)||(r_dcache_type_save == iss_t::DATA_LL))
+                {
+                    r_dcache_error_type = MMU_READ_PT2_ILLEGAL_ACCESS;
+                }
+                else /*if ((dreq.type == iss_t::DATA_WRITE)||(dreq.type == iss_t::DATA_SC))*/
+                {
+                    r_dcache_error_type = MMU_WRITE_PT2_ILLEGAL_ACCESS;
+                } 
+                r_dcache_bad_vaddr = dreq.addr;
+                r_dcache_fsm = DCACHE_ERROR; 
+                
+                if (r_dcache_inval_tlb_rsp) r_dcache_inval_tlb_rsp = false;
+            }
+	        else
+	        {
+	            if ( !(r_dcache_miss_buf[0] >> PTE_V_SHIFT) )	// unmapped
+	            {
+                    if ((r_dcache_type_save == iss_t::DATA_READ)||(r_dcache_type_save == iss_t::DATA_LL))
+                    {
+                        r_dcache_error_type = MMU_READ_PT2_UNMAPPED;
+                    }
+                    else /*if ((dreq.type == iss_t::DATA_WRITE)||(dreq.type == iss_t::DATA_SC))*/
+                    {
+                        r_dcache_error_type = MMU_WRITE_PT2_UNMAPPED;
+                    }  
+                    r_dcache_bad_vaddr = dreq.addr;
+                    r_dcache_fsm = DCACHE_ERROR;
+
+                    if (r_dcache_inval_tlb_rsp) r_dcache_inval_tlb_rsp = false;
+	            }
+       	        else if ( r_dcache_inval_tlb_rsp )
+       	        {
+       	            r_dcache_inval_tlb_rsp = false;
+       	            r_dcache_fsm = DCACHE_IDLE;
+       	            m_cost_data_tlb_miss_frz++;
+       	        }
+		        else
+		        {
+		            r_dcache_tlb_sc_acc_req = true;
+                    r_vci_rsp_data_ok = false;
+                    r_dcache_pte_update = r_dcache_miss_buf[0] | r_dcache_pte_update.read();
+                    r_dcache_fsm = DCACHE_TLB2_SC_WAIT; 
+		        }
+	        }
+	    }
+	    break;
+    }
+    ///////////////////////
+    case DCACHE_TLB2_SC_WAIT:
+    {
+        // external cache invalidate request
+        if ( r_tgt_dcache_req )   
+        {
+            r_dcache_fsm = DCACHE_CC_CHECK;
+            r_dcache_fsm_save = r_dcache_fsm;
+            break;
+        }  
+
+        if ( r_vci_rsp_data_ok ) // VCI response 
+        {
+            if ( r_vci_rsp_data_error ) // VCI response ko
+	        {
+                if ((r_dcache_type_save == iss_t::DATA_READ)||(r_dcache_type_save == iss_t::DATA_LL))
+                {
+                    r_dcache_error_type = MMU_READ_PT2_ILLEGAL_ACCESS;
+                }
+                else /*if ((dreq.type == iss_t::DATA_WRITE)||(dreq.type == iss_t::DATA_SC))*/
+                {
+                    r_dcache_error_type = MMU_WRITE_PT2_ILLEGAL_ACCESS;
+                } 
+	            r_dcache_bad_vaddr = dreq.addr;
+	            r_dcache_fsm = DCACHE_ERROR; 
+
+                if (r_dcache_inval_tlb_rsp) r_dcache_inval_tlb_rsp = false;
+	        }
+            else
+            {
+                // Using tlb entry is invalidated 
+                if ( r_dcache_inval_tlb_rsp )
+                {
+                    r_dcache_inval_tlb_rsp = false;
+                    if (r_dcache_tlb_sc_fail) r_dcache_tlb_sc_fail = false;
+                    r_dcache_fsm = DCACHE_IDLE;
+                    m_cost_data_tlb_miss_frz++;
+                }
+	            else if ( r_dcache_tlb_sc_fail )
+	            {
+                    r_dcache_tlb_ll_acc_req = true;
+                    r_dcache_tlb_sc_fail = false;
+                    r_vci_rsp_data_ok = false;
+	                r_dcache_fsm = DCACHE_TLB2_LL_WAIT; 
+	            }
+	            else 
+	            {
+                    r_vci_rsp_data_ok = false;
+	                r_dcache_fsm = DCACHE_TLB2_UPDT; 
+	            }
+            }
+        }
+	    break;
+    }
+    //////////////////////
+    case DCACHE_TLB2_UPDT:  
+    {
+        if ( dreq.valid ) m_cost_data_tlb_miss_frz++;
+
+        // external cache invalidate request
+        if ( r_tgt_dcache_req )   
+        {
+            r_dcache_fsm = DCACHE_CC_CHECK;
+            r_dcache_fsm_save = r_dcache_fsm;
+            break;
+        }        
+
+        // TLB update and invalidate different PTE
+        if ( !r_dcache_inval_tlb_rsp && !r_dcache_cleanup_req)
+        {
+            paddr_t victim_index = 0;
+            r_dcache_cleanup_req = dcache_tlb.update1(r_dcache_pte_update,r_dcache_miss_buf[1],dreq.addr,(r_dcache_tlb_paddr.read() >> (uint32_log2(m_dcache_words)+2)),&victim_index);
+            r_dcache_cleanup_line = victim_index;
+            r_dcache_cleanup_type = TLB_CLEANUP; 
+            r_dcache_fsm = DCACHE_IDLE;
+        }
+
+        // TLB update and invalidate same PTE
+        if ( r_dcache_inval_tlb_rsp )                                 
+        {
+            r_dcache_inval_tlb_rsp = false;
+            r_dcache_fsm = DCACHE_IDLE;
+        }
+        break;
+    }
+    //////////////////////////
+    case DCACHE_CTXT_SWITCH:
+    {
+        size_t way = r_dcache_way;
+        size_t set = r_dcache_set;
+        bool clean = false;
+
+        m_cost_data_tlb_flush_frz++
+;
+        // 4K page size TLB flush leads to cleanup req  
+        if ( !r_dcache_cleanup_req )    // last cleanup finish
+        {
+            paddr_t victim_index = 0;
+            for ( ; way < m_dtlb_ways; way++)
+            {
+                for ( ; set < m_dtlb_sets; set++)
+                {
+                    if(dcache_tlb.checkcleanup1(way, set, &victim_index))
+                    {
+                        clean = true;
+                        r_dcache_cleanup_req = true;
+                        r_dcache_cleanup_line = victim_index;
+                        r_dcache_cleanup_type = TLB_CLEANUP;
+                        r_dcache_way = way + ((set+1)/m_dtlb_sets);
+                        r_dcache_set = (set+1) % m_dtlb_sets;
+                        break;
+                    }
+                }
+                if (clean) break;
+            }
+
+            if ((way == m_dtlb_ways) && (!r_dcache_xtn_req))
+            {
+                r_dcache_fsm = DCACHE_IDLE;
+                r_dtlb_translation_valid = false;
+                r_dcache_ptba_ok = false;
+                drsp.valid = true;
+                break;
+            }
+        }
+        break;
+    }
+    ////////////////////////
+    case DCACHE_ICACHE_FLUSH:
+    case DCACHE_ICACHE_INVAL:
+    case DCACHE_ITLB_INVAL:
+    {
+        if ( !r_dcache_xtn_req ) 
+        {
+            r_dcache_fsm = DCACHE_IDLE;
+            drsp.valid = true;
+        }
+        break;
+    }
+    ////////////////////////
+    case DCACHE_DCACHE_FLUSH:
+    {
+        m_cost_data_cache_flush_frz++;
+
+        // external cache invalidate request
+        if ( r_tgt_dcache_req )   
+        {
+            r_dcache_fsm = DCACHE_CC_CHECK;
+            r_dcache_fsm_save = r_dcache_fsm;
+            m_cost_data_waste_wait_frz++;
+            break;
+        }  
+        size_t way = r_dcache_way;
+        size_t set = r_dcache_set;
+        bool clean = false;
+        
+        // cache flush and send cleanup to external
+        if ( !r_dcache_cleanup_req )
+        {
+            paddr_t victim_index = 0;
+            for ( ; way < m_dcache_ways; way++ )
+            {    
+                for ( ; set < m_dcache_sets; set++ )
+                {  
+                    if ( r_dcache.flush(way, set, &victim_index) )
+                    {
+                        clean = true;
+                        r_dcache_cleanup_req = true;
+                        r_dcache_cleanup_line = victim_index;
+                        r_dcache_cleanup_type = CACHE_CLEANUP;
+                        r_dcache_way = way + ((set+1)/m_dcache_sets);
+                        r_dcache_set = (set+1) % m_dcache_sets;
+                        break;
+                    }
+                }
+                if (clean) break;
+            }
+
+            if ( way == m_dcache_ways )  
+            {
+                r_dcache_fsm = DCACHE_IDLE;
+                drsp.valid = true;
+                break;
+            }
+        }
+        break;
+    }
+    //////////////////////
+    case DCACHE_DTLB_INVAL: 
+    {
+        paddr_t victim_index = 0;
+
+        if ( !r_dcache_cleanup_req )
+        {
+            r_dcache_cleanup_req = dcache_tlb.inval1(r_dcache_wdata_save, &victim_index);
+            r_dcache_cleanup_type = TLB_CLEANUP;
+            r_dcache_cleanup_line = victim_index;
+            r_dtlb_translation_valid = false;
+            r_dcache_ptba_ok = false;
+            r_dcache_fsm = DCACHE_IDLE;
+            drsp.valid = true;
+        }
+        break;
+    }
+    ////////////////////////
+    case DCACHE_DCACHE_INVAL:
+    {
+        // external cache invalidate request
+        if ( r_tgt_dcache_req )   
+        {
+            r_dcache_fsm = DCACHE_CC_CHECK;
+            r_dcache_fsm_save = r_dcache_fsm;
+            m_cost_data_waste_wait_frz++;
+            break;
+        }  
+
+        m_cpt_dcache_dir_read += m_dcache_ways;
+        vaddr_t invadr = dreq.wdata;
+        paddr_t dpaddr = 0;
+        bool dcache_hit_t = false; 
+
+        if ( !r_dcache_cleanup_req )
+        {
+            if ( r_mmu_mode.read() & DATA_TLB_MASK ) 
+            {
+                dcache_hit_t = dcache_tlb.translate(invadr, &dpaddr); 
+            } 
+            else 
+            {
+                dpaddr = invadr;  
+                dcache_hit_t = true;
+            }
+
+            if ( dcache_hit_t )
+            {
+                r_dcache_cleanup_req = r_dcache.inval(dpaddr);
+                r_dcache_cleanup_type = CACHE_CLEANUP;
+                r_dcache_cleanup_line = dpaddr >> (uint32_log2(m_dcache_words)+2);
+            }
+            r_dcache_fsm = DCACHE_IDLE;
+            drsp.valid = true;
+        }
+        break;
+    }
+    ////////////////////////
+    case DCACHE_DCACHE_INVAL_PA:
+    {
+        // external cache invalidate request
+        if ( r_tgt_dcache_req )   
+        {
+            r_dcache_fsm = DCACHE_CC_CHECK;
+            r_dcache_fsm_save = r_dcache_fsm;
+            m_cost_data_waste_wait_frz++;
+            break;
+        }  
+
+        m_cpt_dcache_dir_read += m_dcache_ways;
+        paddr_t dpaddr = (paddr_t)r_mmu_word_hi.read() << 32 | r_mmu_word_lo.read();
+
+        if ( !r_dcache_cleanup_req )
+        {
+            r_dcache_cleanup_req = r_dcache.inval(dpaddr);
+            r_dcache_cleanup_type = CACHE_CLEANUP;
+            r_dcache_cleanup_line = dpaddr >> (uint32_log2(m_dcache_words)+2);
+            r_dcache_fsm = DCACHE_IDLE;
+            drsp.valid = true;
+        }
+        break;
+    }
+    /////////////////////////
+    case DCACHE_DCACHE_SYNC:
+    {
+        if ( r_wbuf.empty() ) 
+        {
+            drsp.valid = true;
+            r_dcache_fsm = DCACHE_IDLE;
+        }    
+        break;
+    }
+    /////////////////////
+    case DCACHE_MISS_WAIT:
+    {
+        // external cache invalidate request
+        if ( r_tgt_dcache_req ) 
+        {
+            r_dcache_fsm = DCACHE_CC_CHECK;
+            r_dcache_fsm_save = r_dcache_fsm;
+            m_cost_cc_wait_frz++;
+            break;
+        }
+
+        if ( r_vci_rsp_data_ok )
+        {
+            if ( r_vci_rsp_data_error ) 
+            {
+                r_dcache_error_type = MMU_READ_DATA_ILLEGAL_ACCESS; 
+                r_dcache_bad_vaddr = dreq.addr;
+                r_dcache_fsm = DCACHE_ERROR;
+
+		        if (r_dcache_inval_tlb_rsp) r_dcache_inval_tlb_rsp = false;
+		        if (r_dcache_inval_rsp) r_dcache_inval_rsp = false;
+		        break;
+            }        
+
+            if ( r_dcache_inval_tlb_rsp ) // Miss read response and tlb invalidation
+            {
+                if ( r_dcache_cleanup_req ) break;
+                r_dcache_cleanup_req = true;
+                r_dcache_cleanup_type = CACHE_CLEANUP;
+                r_dcache_cleanup_line = r_dcache_paddr_save.read() >> (uint32_log2(m_dcache_words) + 2);  
+                r_dcache_fsm = DCACHE_IDLE;
+                r_dcache_inval_tlb_rsp = false;
+                if ( r_dcache_inval_rsp ) r_dcache_inval_rsp = false;
+		        break;
+            }	
+
+	        if ( r_dcache_inval_rsp ) // TLB miss response and cache invalidation
+	        {
+                if ( r_dcache_cleanup_req ) break;
+                r_dcache_cleanup_req = true;
+                r_dcache_cleanup_type = CACHE_CLEANUP;
+                r_dcache_cleanup_line = r_dcache_paddr_save.read() >> (uint32_log2(m_dcache_words) + 2);  
+                r_dcache_fsm = DCACHE_IDLE;
+                r_dcache_inval_rsp = false;
+		        break;	    
+            }
+	        // Miss read response and no tlb invalidation   
+            r_dcache_fsm = DCACHE_MISS_UPDT;
+        }
+        break;
+    }
+    /////////////////////
+    case DCACHE_MISS_UPDT:
+    {
+        // external cache invalidate request
+        if ( r_tgt_dcache_req ) 
+        {
+            r_dcache_fsm = DCACHE_CC_CHECK;
+            r_dcache_fsm_save = r_dcache_fsm;
+            break;
+        }
+
+        if ( r_dcache_inval_tlb_rsp ) // tlb invalidation
+        {
+            if ( r_dcache_cleanup_req ) break;
+            r_dcache_cleanup_req = true;
+            r_dcache_cleanup_type = CACHE_CLEANUP;            
+            r_dcache_cleanup_line = r_dcache_paddr_save.read() >> (uint32_log2(m_dcache_words) + 2);  
+            r_dcache_inval_tlb_rsp = false;
+            r_dcache_inval_rsp = false;
+            r_dcache_fsm = DCACHE_IDLE;
+            break;
+        }
+
+        // Using tlb entry is in the invalidated cache line  
+        if ( r_dcache_inval_rsp )
+        {
+            if ( r_dcache_cleanup_req ) break;
+            r_dcache_cleanup_req = true;
+            r_dcache_cleanup_type = CACHE_CLEANUP;            
+            r_dcache_cleanup_line = r_dcache_paddr_save.read() >> (uint32_log2(m_dcache_words) + 2);  
+            r_dcache_inval_rsp = false;
+            r_dcache_fsm = DCACHE_IDLE;
+            m_cost_data_tlb_miss_frz++;
+            break;
+        }
+
+        if ( !r_dcache_cleanup_req ) // Miss update and no invalidation
+        {
+            paddr_t  victim_index = 0;
+            r_dcache_cleanup_req = r_dcache.update(r_dcache_paddr_save.read(), r_dcache_miss_buf, &victim_index);
+            r_dcache_cleanup_line = victim_index;
+            r_dcache_cleanup_type = CACHE_CLEANUP;
+            r_dcache_fsm = DCACHE_IDLE;
+        }
+        break;
+    }
+    //////////////////////
+    case DCACHE_UNC_WAIT:
+    {
+        // external cache invalidate request
+        if ( r_tgt_dcache_req ) 
+        {
+            r_dcache_fsm = DCACHE_CC_CHECK;
+            r_dcache_fsm_save = r_dcache_fsm;
+            break;
+        }
+
+        if ( r_vci_rsp_data_ok )
+        {
+            if ( r_vci_rsp_data_error ) 
+            {
+                r_dcache_error_type = MMU_READ_DATA_ILLEGAL_ACCESS; 
+                r_dcache_bad_vaddr = dreq.addr;
+                r_dcache_fsm = DCACHE_ERROR;
+
+                if (r_dcache_inval_tlb_rsp) r_dcache_inval_tlb_rsp = false;
+		        break;
+            }
+
+            if ( r_dcache_inval_tlb_rsp ) // Miss read response and tlb invalidation
+            {
+                r_dcache_inval_tlb_rsp = false;
+            }
+
+            if (dreq.type == iss_t::DATA_SC) 
+	        {
+                // Simulate an invalidate request
+		        r_dcache_cleanup_req = r_dcache.inval(r_dcache_paddr_save);
+                r_dcache_cleanup_type = CACHE_CLEANUP;
+		        r_dcache_cleanup_line = r_dcache_paddr_save.read() >> (uint32_log2(m_dcache_words)+2);
+            }		
+	        r_dcache_fsm = DCACHE_IDLE;        
+        }
+        break;
+    }
+    ///////////////////////
+    case DCACHE_WRITE_UPDT:
+    {
+        bool write_hit = false;
+        data_t mask = vci_param::be2mask(r_dcache_be_save.read());
+        data_t wdata = (mask & r_dcache_wdata_save) | (~mask & r_dcache_rdata_save);
+        write_hit = r_dcache.write(r_dcache_paddr_save, wdata);
+        assert(write_hit && "Write on miss ignores data");
+
+        if ( !r_dcache_dirty_save && (r_mmu_mode.read() & DATA_TLB_MASK) )   
+        {
+            if ( dcache_tlb.getpagesize(r_dcache_tlb_way_save, r_dcache_tlb_set_save) )	// 2M page size, one level page table 
+            {
+                r_dcache_pte_update = dcache_tlb.getpte(r_dcache_tlb_way_save, r_dcache_tlb_set_save) | PTE_D_MASK;
+                r_dcache_tlb_paddr = (paddr_t)r_mmu_ptpr << (INDEX1_NBITS+2) | (paddr_t)((dreq.addr>>PAGE_M_NBITS)<<2);
+                r_dcache_tlb_ll_dirty_req = true;
+                r_vci_rsp_data_ok = false;
+                r_dcache_fsm = DCACHE_LL_DIRTY_WAIT;
+                m_cpt_data_tlb_write_dirty++;
+            }
+            else
+            {   
+                if (r_dcache_hit_p_save) 
+                {
+                    r_dcache_pte_update = dcache_tlb.getpte(r_dcache_tlb_way_save, r_dcache_tlb_set_save) | PTE_D_MASK;
+                    r_dcache_tlb_paddr = (paddr_t)r_dcache_ptba_save|(paddr_t)(((dreq.addr&PTD_ID2_MASK)>>PAGE_K_NBITS) << 3);
+                    r_dcache_tlb_ll_dirty_req = true;
+                    r_vci_rsp_data_ok = false;
+                    r_dcache_fsm = DCACHE_LL_DIRTY_WAIT;
+                    m_cpt_data_tlb_write_dirty++;
+                }
+                else
+                {
+                    r_dcache_pte_update = dcache_tlb.getpte(r_dcache_tlb_way_save, r_dcache_tlb_set_save) | PTE_D_MASK;
+                    r_dcache_tlb_paddr = (paddr_t)r_mmu_ptpr << (INDEX1_NBITS+2) | (paddr_t)((dreq.addr>>PAGE_M_NBITS)<<2);
+                    r_dcache_tlb_ptba_read = true;
+                    r_dcache_tlb_read_req = true;
+                    r_dcache_tlb_first_req = true;
+                    r_vci_rsp_data_ok = false;
+                    r_dcache_fsm = DCACHE_TLB1_READ;
+                }
+            }        
+        }
+        else
+        {
+            r_dcache_fsm = DCACHE_WRITE_REQ;
+            drsp.valid = true;
+            drsp.rdata = 0;
+        }
+        break;
+    }
+    ////////////////////////
+    case DCACHE_WRITE_DIRTY:
+    {
+        m_cost_data_tlb_miss_frz++;
+
+        // external cache invalidate request
+        if ( r_tgt_dcache_req ) 
+        {
+            r_dcache_fsm = DCACHE_CC_CHECK;
+            r_dcache_fsm_save = r_dcache_fsm;
+            //m_cost_data_waste_wait_frz++;
+            break;
+        }
+
+        if ( r_dcache_inval_tlb_rsp ) // Miss read response and tlb invalidation
+        {
+            r_dcache_fsm = DCACHE_IDLE;
+            r_dcache_inval_tlb_rsp = false;
+	        break;
+        }
+        dcache_tlb.setdirty(r_dcache_tlb_way_save, r_dcache_tlb_set_save);
+        r_dcache_fsm = DCACHE_WRITE_REQ;
+        drsp.valid = true;
+        drsp.rdata = 0;
+        break;
+    }
+    /////////////////
+    case DCACHE_ERROR:
+    {
+        r_vci_rsp_data_error = false;
+        drsp.valid = true;
+        drsp.error = true;
+        drsp.rdata = 0;
+        r_dcache_fsm = DCACHE_IDLE;
+        break;
+    }   
+    /////////////////////
+    case DCACHE_CC_CHECK:   // read directory in case of invalidate or update request
+    {
+        m_cpt_dcache_dir_read += m_dcache_ways;
+        m_cpt_dcache_data_read += m_dcache_ways;
+
+        m_cost_cc_wait_frz++;
+
+        if (( /*( r_dcache_fsm_save == DCACHE_UNC_WAIT ) ||*/
+	         ( r_dcache_fsm_save == DCACHE_MISS_WAIT ) || ( r_dcache_fsm_save == DCACHE_MISS_UPDT ) ) && 
+           ( (r_dcache_paddr_save.read() & ~((m_dcache_words<<2)-1)) == (r_tgt_addr.read() & ~((m_dcache_words<<2)-1)))) 
+        {
+            r_dcache_inval_rsp = true;
+            r_tgt_dcache_rsp = r_tgt_update;
+
+            if ( r_tgt_broadcast )
+            {
+                r_dcache_tlb_inval_req = true;
+                r_dcache_fsm = DCACHE_TLB_CC_INVAL;        
+            }
+            else
+            {
+                r_tgt_dcache_req = false;
+                r_dcache_fsm = r_dcache_fsm_save;        
+            }    
+        } 
+        else
+        { 
+            data_t dcache_rdata = 0;
+            bool dcache_hit = r_dcache.read(r_tgt_addr.read(), &dcache_rdata);   
+
+            if ( dcache_hit )
+            {
+                if ( r_tgt_update ) // update 
+                {
+                    r_dcache_fsm = DCACHE_CC_UPDT;
+                } 
+                else                // invalidate 
+                {
+                    r_dcache_fsm = DCACHE_CC_INVAL;
+                }
+            }
+            else                    // nothing
+            {
+                r_dcache_fsm = DCACHE_CC_NOP;
+            }
+        }
+        break;
+    }
+    ///////////////////
+    case DCACHE_CC_UPDT:    // update directory and data cache        
+    {
+        m_cpt_dcache_dir_write++;
+        m_cpt_dcache_data_write++;
+        m_cost_cc_wait_frz++;
+
+        data_t* buf = r_tgt_buf;
+        for( size_t i = 0; i < m_dcache_words; i++ )
+        {
+            if( r_tgt_val[i] ) r_dcache.write( r_tgt_addr.read() + i*4, buf[i] );
+        }
+        r_tgt_dcache_req = false;
+        r_tgt_dcache_rsp = true;
+        r_dcache_fsm = r_dcache_fsm_save;
+        break;
+    }
+    /////////////////////
+    case DCACHE_CC_INVAL:   // invalidate a cache line
+    {
+        m_cost_cc_wait_frz++;
+        r_tgt_dcache_rsp = r_dcache.inval(r_tgt_addr.read());
+        if ( r_tgt_broadcast )
+        {
+            r_dcache_tlb_inval_req = true;
+            r_dcache_fsm = DCACHE_TLB_CC_INVAL;        
+        }
+        else
+        {
+            r_tgt_dcache_req = false;
+            r_dcache_fsm = r_dcache_fsm_save;        
+        }    
+        break;
+    }
+    ///////////////////
+    case DCACHE_CC_NOP:     // no external hit
+    {
+        m_cost_cc_wait_frz++;
+        r_tgt_dcache_rsp = r_tgt_update;
+        if ( r_tgt_broadcast )
+        {
+            r_dcache_tlb_inval_req = true;
+            r_dcache_fsm = DCACHE_TLB_CC_INVAL;        
+        }
+        else
+        {
+            r_tgt_dcache_req = false;
+            r_dcache_fsm = r_dcache_fsm_save;        
+        }    
+        break;
+    }   
+    /////////////////////////
+    case DCACHE_TLB_CC_INVAL:
+    {
+        paddr_t dcache_tlb_nline = 0;
+        if ( dreq.valid ) m_cost_data_tlb_miss_frz++;        
+
+	    if ( r_dcache_tlb_inval_req ) break;
+
+        if( (( r_dcache_fsm_save == DCACHE_TLB1_READ )     || ( r_dcache_fsm_save == DCACHE_TLB2_READ )        ||
+             ( r_dcache_fsm_save == DCACHE_TLB1_LL_WAIT )  || ( r_dcache_fsm_save == DCACHE_TLB2_LL_WAIT )     ||
+             ( r_dcache_fsm_save == DCACHE_TLB1_SC_WAIT )  || ( r_dcache_fsm_save == DCACHE_TLB2_SC_WAIT )     ||
+             ( r_dcache_fsm_save == DCACHE_TLB1_UPDT )     || ( r_dcache_fsm_save == DCACHE_TLB2_UPDT )        ||
+             ( r_dcache_fsm_save == DCACHE_LL_DIRTY_WAIT ) || ( r_dcache_fsm_save == DCACHE_SC_DIRTY_WAIT )    ||
+	         ( r_dcache_fsm_save == DCACHE_WRITE_DIRTY )) && 
+           ((r_dcache_tlb_paddr.read() & ~((m_dcache_words<<2)-1)) == r_tgt_addr.read()) ) 
+        {
+            r_dcache_inval_tlb_rsp = true;
+        } 
+
+        if (((r_dcache_fsm_save == DCACHE_BIS)||(r_dcache_fsm_save == DCACHE_MISS_WAIT) ||
+             (r_dcache_fsm_save == DCACHE_UNC_WAIT)||(r_dcache_fsm_save == DCACHE_MISS_UPDT)) && 
+             (r_dcache_tlb_nline == (paddr_t)(r_tgt_addr.read() & ~((m_dcache_words<<2)-1))))
+        {
+            r_dcache_inval_tlb_rsp = true;
+        }
+
+        if( (( r_dcache_fsm_save == DCACHE_TLB1_LL_WAIT )  || ( r_dcache_fsm_save == DCACHE_TLB2_LL_WAIT )     ||
+             ( r_dcache_fsm_save == DCACHE_TLB1_SC_WAIT )  || ( r_dcache_fsm_save == DCACHE_TLB2_SC_WAIT )     ||
+             ( r_dcache_fsm_save == DCACHE_TLB1_UPDT )     || ( r_dcache_fsm_save == DCACHE_TLB2_UPDT )        ||
+             ( r_dcache_fsm_save == DCACHE_LL_DIRTY_WAIT ) || ( r_dcache_fsm_save == DCACHE_SC_DIRTY_WAIT )    ||
+	         ( r_dcache_fsm_save == DCACHE_WRITE_DIRTY )) && 
+           ((r_dcache_tlb_paddr.read() & ~((m_dcache_words<<2)-1)) == r_tgt_addr.read()) ) 
+        {
+            if ( !r_dcache_cc_hit_t ) 
+            {
+                r_ccinval_dtlb_cpt = r_ccinval_dtlb_cpt + 1;
+            }
+        } 
+
+        r_tgt_dcache_req = false;
+	    r_dtlb_translation_valid = false;
+        r_dcache_ptba_ok = false;        
+        r_dcache_fsm = r_dcache_fsm_save;
+        break;
+    }
+    } // end switch r_dcache_fsm
+
+#ifdef SOCLIB_MODULE_DEBUG
+    std::cout << name() << " Data Response: " << drsp << std::endl;
+#endif
+
+    ////////////////////////////////////////////////////////////////////////////////////
+    //      INVAL DTLB CHECK FSM 
+    ////////////////////////////////////////////////////////////////////////////////////////
+    switch(r_inval_dtlb_fsm) {
+    /////////////////////
+    case INVAL_DTLB_IDLE:
+    {    
+        if ( r_dcache_tlb_inval_req )
+        {
+            paddr_t dpaddr;
+            r_ccinval_dtlb_way = 0;
+            r_ccinval_dtlb_set = 0;
+            r_ccinval_dtlb_cpt = 0;
+            r_dcache_cc_hit_t = dcache_tlb.translate(dreq.addr, &dpaddr);
+            r_inval_dtlb_fsm = INVAL_DTLB_CHECK;    
+        }   
+        break;
+    }    
+    //////////////////////
+    case INVAL_DTLB_CHECK:
+    {
+        size_t way = r_ccinval_dtlb_way; 
+        size_t set = r_ccinval_dtlb_set;
+        bool end = false;
+
+        bool tlb_hit = dcache_tlb.cccheck((r_tgt_addr.read() >> (uint32_log2(m_dcache_words)+2)), way, set, &way, &set, &end);
+    
+        if ( tlb_hit )
+        {
+            r_ccinval_dtlb_way = way; 
+            r_ccinval_dtlb_set = set;
+            r_dtlb_cc_check_end = end;
+            r_ccinval_dtlb_cpt = r_ccinval_dtlb_cpt + 1;
+            r_inval_dtlb_fsm = INVAL_DTLB_INVAL;    
+        }        
+        else
+        {
+            r_inval_dtlb_fsm = INVAL_DTLB_CLEAR;    
+        }
+        break;
+    }
+    /////////////////////////
+    case INVAL_DTLB_INVAL:
+    {
+        dcache_tlb.ccinval(r_ccinval_dtlb_way, r_ccinval_dtlb_set);
+        if ( !r_dtlb_cc_check_end )
+        {
+            r_inval_dtlb_fsm = INVAL_DTLB_CHECK; 
+        }
+        else
+        {
+            r_inval_dtlb_fsm = INVAL_DTLB_CLEAR;    
+        }
+        break;
+    }
+    ////////////////////
+    case INVAL_DTLB_CLEAR:
+    {
+        r_dcache_tlb_inval_req = false;
+        r_dtlb_cc_check_end = false;
+        r_ccinval_dtlb_way = 0; 
+        r_ccinval_dtlb_set = 0; 
+        r_inval_dtlb_fsm = INVAL_DTLB_IDLE;    
+        break;
+    }    
+    } // end switch r_inval_itlb_fsm
+
+    if ( r_dcache_fsm == DCACHE_WRITE_REQ )
+    {
+        r_wbuf.write(true, r_dcache_paddr_save.read(), r_dcache_be_save.read(), r_dcache_wdata_save); 
+    }
+    else
+    {
+        r_wbuf.write(false, 0, 0, 0);
+    }
+
+    /////////// execute one iss cycle /////////////////////////////////
+    {
+    uint32_t it = 0;
+    for (size_t i=0; i<(size_t)iss_t::n_irq; i++) if(p_irq[i].read()) it |= (1<<i);
+    m_iss.executeNCycles(1, irsp, drsp, it);
+    }
+
+    ////////////// number of frozen cycles //////////////////////////
+    if ( (ireq.valid && !irsp.valid) || (dreq.valid && !drsp.valid) )
+    {
+        m_cpt_frz_cycles++;
+    }
+
+    ////////////////////////////////////////////////////////////////////////////
+    // This CLEANUP FSM controls the transmission of the cleanup transactions
+    // on the coherence network. It controls the following ressources:
+    // - r_cleanup_fsm
+    // - r_dcache_cleanup_req reset
+    // - r_icache_cleanup_req reset
+    // 
+    // This FSM handles cleanup requests from both the DCACHE FSM & ICACHE FSM
+    // 1 - Instruction Cleanup  : r_icache_cleanup_req 
+    // 2 - Data Cleanup         : r_dcache_cleanup_req 
+    // In case of simultaneous requests, the data request have highest priority.
+    // There is only one cleanup transaction at a given time (sequencial behavior)
+    // because the same FSM controls both command & response. 
+    // The the r_icache_cleanup_req & r_dcache_cleanup_req are reset only
+    // when the response packet is received.
+    // Error handling :
+    // As the coherence trafic is controled by hardware, errors are not reported
+    // to software : In case of errors, the simulation stops.
+    ////////////////////////////////////////////////////////////////////////////
+
+    switch (r_cleanup_fsm) {
+    //////////////////	
+    case CLEANUP_CMD:
+    {
+        if ( p_vci_ini_c.cmdack.read() )
+        {
+            if ( r_icache_cleanup_req ) 
+	        {
+	            r_cleanup_fsm = CLEANUP_ICACHE_RSP;
+	        }	
+            else if ( r_dcache_cleanup_req ) 
+	        {
+	            r_cleanup_fsm = CLEANUP_DCACHE_RSP;
+	        }
+	    }   
+        break;
+    }
+    ////////////////////////
+    case CLEANUP_ICACHE_RSP:
+    {
+        if ( ! p_vci_ini_c.rspval.read() )
+            break;
+        assert( p_vci_ini_c.reop.read() && ((p_vci_ini_c.rtrdid.read() == 1)||(p_vci_ini_c.rtrdid.read() == 3)) &&
+                "illegal VCI response packet for icache cleanup");
+        assert( (p_vci_ini_c.rerror.read() == vci_param::ERR_NORMAL) &&
+                "error in response packet for icache cleanup");
+
+        r_icache_cleanup_req = false;
+        r_cleanup_fsm = CLEANUP_CMD;
+        break;
+    }
+    /////////////////////////		
+    case CLEANUP_DCACHE_RSP:
+    {
+        if ( ! p_vci_ini_c.rspval.read() )
+            break;
+        assert( p_vci_ini_c.reop.read() && ((p_vci_ini_c.rtrdid.read() == 0)||(p_vci_ini_c.rtrdid.read() == 2)) &&
+                "illegal VCI response packet for dcache cleanup");
+        assert( (p_vci_ini_c.rerror.read() == vci_param::ERR_NORMAL) &&
+                "error in response packet for dcache cleanup");
+
+        r_dcache_cleanup_req = false;
+        r_cleanup_fsm = CLEANUP_CMD;
+        break;
+    }
+    } // end switch r_cleanup_fsm
+
+    ////////////////////////////////////////////////////////////////////////////
+    //     VCI_CMD FSM 
+    //
+    // This FSM handles requests from both the DCACHE controler
+    // (request registers) and the ICACHE controler (request registers).
+    // There is 10 VCI transaction types :
+    // - INS_TLB_READ
+    // - INS_TLB_WRITE
+    // - INS_MISS
+    // - INS_UNC_MISS
+    // - DATA_TLB_READ
+    // - DATA_TLB_WRITE
+    // - DATA_TLB_DIRTY
+    // - DATA_MISS
+    // - DATA_UNC 
+    // - DATA_WRITE
+    // The ICACHE requests have the highest priority.
+    // There is at most one (CMD/RSP) VCI transaction, as both CMD_FSM and RSP_FSM
+    // exit simultaneously the IDLE state.
+    //////////////////////////////////////////////////////////////////////////////
+
+    switch (r_vci_cmd_fsm) {
+    
+    case CMD_IDLE:
+        if (r_icache_tlb_read_req && r_wbuf.miss( r_icache_paddr_save ))           
+        {            
+            r_vci_cmd_fsm = CMD_ITLB_READ;
+            r_icache_tlb_read_req = false;
+            m_cpt_itlbmiss_transaction++; 
+        } 
+        else if (r_icache_tlb_ll_req && r_wbuf.miss( r_icache_paddr_save ))      
+        {  
+            r_vci_cmd_fsm = CMD_ITLB_ACC_LL;
+            r_icache_tlb_ll_req = false;
+            //m_cpt_itlb_write_transaction++; 
+        } 
+        else if (r_icache_tlb_sc_req && r_wbuf.miss( r_icache_paddr_save ))      
+        {  
+            r_vci_cmd_fsm = CMD_ITLB_ACC_SC;
+            r_icache_tlb_sc_req = false;
+            //m_cpt_itlb_write_transaction++; 
+        } 
+        else if (r_icache_miss_req && r_wbuf.miss( r_icache_paddr_save )) 
+        {    
+            r_vci_cmd_fsm = CMD_INS_MISS;
+            r_icache_miss_req = false;
+            m_cpt_imiss_transaction++; 
+        }
+        else if (r_icache_unc_req && r_wbuf.miss( r_icache_paddr_save )) 
+        {    
+            r_vci_cmd_fsm = CMD_INS_UNC;
+            r_icache_unc_req = false;
+            m_cpt_imiss_transaction++; 
+        }  
+        else if (r_dcache_tlb_read_req && r_wbuf.miss( r_dcache_tlb_paddr )) 
+        {            
+            r_vci_cmd_fsm = CMD_DTLB_READ;
+            r_dcache_tlb_read_req = false;
+            m_cpt_dtlbmiss_transaction++; 
+        } 
+        else if (r_dcache_tlb_ll_acc_req && r_wbuf.miss( r_dcache_tlb_paddr )) 
+        {  
+            r_vci_cmd_fsm = CMD_DTLB_ACC_LL;
+            r_dcache_tlb_ll_acc_req = false;
+            m_cpt_dtlb_write_transaction++; 
+        } 
+        else if (r_dcache_tlb_sc_acc_req && r_wbuf.miss( r_dcache_tlb_paddr )) 
+        {  
+            r_vci_cmd_fsm = CMD_DTLB_ACC_SC;
+            r_dcache_tlb_sc_acc_req = false;
+            m_cpt_dtlb_write_transaction++; 
+        } 
+        else if (r_dcache_tlb_ll_dirty_req && r_wbuf.miss( r_dcache_tlb_paddr )) 
+        {  
+            r_vci_cmd_fsm = CMD_DTLB_DIRTY_LL;
+            r_dcache_tlb_ll_dirty_req = false;
+            m_cpt_dtlb_write_transaction++; 
+        } 
+        else if (r_dcache_tlb_sc_dirty_req && r_wbuf.miss( r_dcache_tlb_paddr )) 
+        {  
+            r_vci_cmd_fsm = CMD_DTLB_DIRTY_SC;
+            r_dcache_tlb_sc_dirty_req = false;
+            m_cpt_dtlb_write_transaction++; 
+        } 
+        else if (r_dcache_miss_req && r_wbuf.miss( r_dcache_paddr_save ))  
+        {
+            r_vci_cmd_fsm = CMD_DATA_MISS;
+            r_dcache_miss_req = false;
+            m_cpt_dmiss_transaction++; 
+        }
+        else if (r_dcache_unc_req && r_wbuf.miss( r_dcache_paddr_save ))  
+        {
+            r_vci_cmd_fsm = CMD_DATA_UNC;
+            r_dcache_unc_req = false;
+            m_cpt_unc_transaction++; 
+        }        
+        else if ( r_wbuf.rok() )
+        {
+            r_vci_cmd_fsm = CMD_DATA_WRITE;
+            r_vci_cmd_cpt = r_wbuf.getMin();
+            r_vci_cmd_min = r_wbuf.getMin();
+            r_vci_cmd_max = r_wbuf.getMax(); 
+            m_cpt_write_transaction++; 
+            m_length_write_transaction += (r_wbuf.getMax() - r_wbuf.getMin() + 1);
+        }
+
+        break;
+
+    case CMD_DATA_WRITE:
+        if ( p_vci_ini_rw.cmdack.read() ) 
+        {
+            r_vci_cmd_cpt = r_vci_cmd_cpt + 1;
+            if (r_vci_cmd_cpt == r_vci_cmd_max) 
+            {
+                r_vci_cmd_fsm = CMD_IDLE;
+                r_wbuf.sent();
+            }
+        }
+        break;
+
+    default:
+        if ( p_vci_ini_rw.cmdack.read() )
+        {  
+            r_vci_cmd_fsm = CMD_IDLE;
+        }
+        break;
+
+    } // end  switch r_vci_cmd_fsm
+
+    //////////////////////////////////////////////////////////////////////////
+    //      VCI_RSP FSM 
+    //
+    // This FSM is synchronized with the VCI_CMD FSM, as both FSMs exit the
+    // IDLE state simultaneously.
+    //////////////////////////////////////////////////////////////////////////
+
+    switch (r_vci_rsp_fsm) {
+
+    case RSP_IDLE:
+	    if ( p_vci_ini_rw.rspval.read() )
+	    {	
+            r_vci_rsp_cpt = 0;
+	        if ( (p_vci_ini_rw.rtrdid.read() & 0x30) == 0x30 )         // DCACHE write response
+            {
+                r_vci_rsp_fsm = RSP_DATA_WRITE;
+            }            
+            else if (( p_vci_ini_rw.rtrdid.read() == TYPE_INS_TLB_1 ) || 
+                     ( p_vci_ini_rw.rtrdid.read() == TYPE_INS_TLB_2 ))         // ITLB miss response
+            {            
+                r_vci_rsp_fsm = RSP_ITLB_READ;
+            } 
+            else if ( p_vci_ini_rw.rtrdid.read() == TYPE_INS_LL_ACC )       // ITLB linked load response
+            {   
+                r_vci_rsp_fsm = RSP_ITLB_ACC_LL;
+            } 
+            else if ( p_vci_ini_rw.rtrdid.read() == TYPE_INS_SC_ACC )       // ITLB linked load response
+            {   
+                r_vci_rsp_fsm = RSP_ITLB_ACC_SC;
+            }         
+            else if ( p_vci_ini_rw.rtrdid.read() == TYPE_INS_MISS )         // ICACHE cached miss response
+            {   
+                r_vci_rsp_fsm = RSP_INS_MISS;
+            }
+            else if ( p_vci_ini_rw.rtrdid.read() == TYPE_INS_UNC )          // ICACHE uncached miss response
+            {   
+                r_vci_rsp_fsm = RSP_INS_UNC;
+            }  
+            else if (( p_vci_ini_rw.rtrdid.read() == TYPE_DATA_TLB_1 ) || 
+                     ( p_vci_ini_rw.rtrdid.read() == TYPE_DATA_TLB_2 ))     // ITLB miss response
+            {
+                r_vci_rsp_fsm = RSP_DTLB_READ; 
+            }
+            else if ( p_vci_ini_rw.rtrdid.read() == TYPE_DATA_LL_ACC )    // DTLB access bits linked load response
+            {
+                r_vci_rsp_fsm = RSP_DTLB_ACC_LL; 
+            }
+            else if ( p_vci_ini_rw.rtrdid.read() == TYPE_DATA_SC_ACC )    // DTLB access bits store conditional response
+            {
+                r_vci_rsp_fsm = RSP_DTLB_ACC_SC; 
+            }
+            else if ( p_vci_ini_rw.rtrdid.read() == TYPE_DATA_LL_D )  // DTLB dirty bit linked load response
+            {
+                r_vci_rsp_fsm = RSP_DTLB_DIRTY_LL; 
+            }
+            else if ( p_vci_ini_rw.rtrdid.read() == TYPE_DATA_SC_D )  // DTLB dirty bit store conditional response
+            {
+                r_vci_rsp_fsm = RSP_DTLB_DIRTY_SC; 
+            }
+            else if ( p_vci_ini_rw.rtrdid.read() == TYPE_DATA_MISS )         // DCACHE read request
+            {
+                r_vci_rsp_fsm = RSP_DATA_MISS;
+            }
+            else if ( p_vci_ini_rw.rtrdid.read() == TYPE_DATA_UNC )          // DCACHE uncached read request
+            {
+                r_vci_rsp_fsm = RSP_DATA_UNC;
+            }
+        }
+        break;
+
+    case RSP_ITLB_READ:
+        m_cost_itlbmiss_transaction++;
+        if ( ! p_vci_ini_rw.rspval.read() )
+            break;
+
+        r_vci_rsp_cpt = r_vci_rsp_cpt + 1;
+        r_icache_miss_buf[r_vci_rsp_cpt] = (data_t)p_vci_ini_rw.rdata.read();
+        if ( p_vci_ini_rw.reop.read() ) 
+        {
+            if ( r_icache_tlb_first_req )
+            {
+                r_icache_tlb_first_req = false; 
+                assert( (r_vci_rsp_cpt == 0)  &&
+                    "illegal VCI response packet for data read uncached");
+            }
+/*
+            else
+            {
+                assert( (r_vci_rsp_cpt == 1)  &&
+                       "The VCI response packet for instruction miss is too short");
+            }
+*/
+            r_vci_rsp_ins_ok = true;
+            r_vci_rsp_fsm = RSP_IDLE;
+        } 
+        if ( p_vci_ini_rw.rerror.read() != vci_param::ERR_NORMAL )
+        {
+            r_vci_rsp_ins_error = true;
+        }
+        break;
+
+    case RSP_ITLB_ACC_LL:
+        if ( ! p_vci_ini_rw.rspval.read() )
+            break;
+
+        assert(p_vci_ini_rw.reop.read() &&
+               "illegal VCI response packet for ll tlb");
+
+        if ( p_vci_ini_rw.rerror.read() != vci_param::ERR_NORMAL ) 
+        {
+            r_vci_rsp_ins_error = true;
+        }
+	    else
+	    {
+	        r_icache_miss_buf[0] = (data_t)p_vci_ini_rw.rdata.read();
+	    }
+        r_vci_rsp_ins_ok = true;
+        r_vci_rsp_fsm = RSP_IDLE;
+	    break;
+
+    case RSP_ITLB_ACC_SC:
+        if ( ! p_vci_ini_rw.rspval.read() )
+            break;
+
+        assert(p_vci_ini_rw.reop.read() &&
+               "illegal VCI response packet for sc tlb");
+
+        if ( p_vci_ini_rw.rerror.read() != vci_param::ERR_NORMAL ) 
+        {
+            r_vci_rsp_ins_error = true;
+        }
+	    else if ( p_vci_ini_rw.rdata.read() == 1 ) // store conditional is not successful
+	    {
+            r_icache_tlb_sc_fail = true;
+	    }
+        r_vci_rsp_ins_ok = true;
+        r_vci_rsp_fsm = RSP_IDLE;
+	    break;
+
+    case RSP_INS_MISS:
+        m_cost_imiss_transaction++;
+        if ( ! p_vci_ini_rw.rspval.read() )
+            break;
+
+        assert( (r_vci_rsp_cpt < m_icache_words) && 
+               "The VCI response packet for instruction miss is too long");
+        r_vci_rsp_cpt = r_vci_rsp_cpt + 1;
+        r_icache_miss_buf[r_vci_rsp_cpt] = (data_t)p_vci_ini_rw.rdata.read();
+
+        if ( p_vci_ini_rw.reop.read() ) 
+        {
+            assert( (r_vci_rsp_cpt == m_icache_words - 1) &&
+                       "The VCI response packet for instruction miss is too short");
+            r_vci_rsp_ins_ok = true;
+            r_vci_rsp_fsm = RSP_IDLE;
+        } 
+        if ( p_vci_ini_rw.rerror.read() != vci_param::ERR_NORMAL )
+        {
+            r_vci_rsp_ins_error = true;
+        }
+        break;
+
+    case RSP_INS_UNC:
+        m_cost_imiss_transaction++;
+        if ( ! p_vci_ini_rw.rspval.read() )
+            break;
+
+        assert(p_vci_ini_rw.reop.read() &&
+               "illegal VCI response packet for uncached instruction");
+
+        r_icache_miss_buf[0] = (data_t)p_vci_ini_rw.rdata.read();
+        r_vci_rsp_ins_ok = true;
+        r_vci_rsp_fsm = RSP_IDLE;
+
+        if ( p_vci_ini_rw.rerror.read() != vci_param::ERR_NORMAL )
+        {
+            r_vci_rsp_ins_error = true;
+        }
+        break;
+
+    case RSP_DTLB_READ:
+        m_cost_dtlbmiss_transaction++;
+        if ( ! p_vci_ini_rw.rspval.read() )
+            break;
+
+        r_vci_rsp_cpt = r_vci_rsp_cpt + 1;
+        r_dcache_miss_buf[r_vci_rsp_cpt] = (data_t)p_vci_ini_rw.rdata.read();
+        if ( p_vci_ini_rw.reop.read() ) 
+        {
+            if ( r_dcache_tlb_first_req )
+            {
+                r_dcache_tlb_first_req = false;
+                assert( (r_vci_rsp_cpt == 0)  &&
+                    "illegal VCI response packet for data read uncached");
+            }
+/* 
+            else
+            {
+                assert( (r_vci_rsp_cpt == 1)  &&
+                       "The VCI response packet for instruction miss is too short");
+            }
+*/
+            r_vci_rsp_data_ok = true;
+            r_vci_rsp_fsm = RSP_IDLE;
+        } 
+        if ( p_vci_ini_rw.rerror.read() != vci_param::ERR_NORMAL )
+        {
+            r_vci_rsp_data_error = true;
+        }
+        break;
+
+    case RSP_DTLB_ACC_LL:
+        if ( ! p_vci_ini_rw.rspval.read() )
+            break;
+
+        assert(p_vci_ini_rw.reop.read() &&
+               "illegal VCI response packet for ll tlb");
+
+        if ( p_vci_ini_rw.rerror.read() != vci_param::ERR_NORMAL ) 
+        {
+            r_vci_rsp_data_error = true;
+        }
+	    else
+	    {
+	        r_dcache_miss_buf[0] = (data_t)p_vci_ini_rw.rdata.read();
+	    }
+        r_vci_rsp_data_ok = true;
+        r_vci_rsp_fsm = RSP_IDLE;
+	    break;
+
+    case RSP_DTLB_ACC_SC:
+        if ( ! p_vci_ini_rw.rspval.read() )
+            break;
+
+        assert(p_vci_ini_rw.reop.read() &&
+               "illegal VCI response packet for sc tlb");
+
+        if ( p_vci_ini_rw.rerror.read() != vci_param::ERR_NORMAL ) 
+        {
+            r_vci_rsp_data_error = true;
+        }
+	    else if ( p_vci_ini_rw.rdata.read() == 1 ) // store conditional is not successful
+	    {
+            r_dcache_tlb_sc_fail = true;
+	    }
+        r_vci_rsp_data_ok = true;
+        r_vci_rsp_fsm = RSP_IDLE;
+	    break;
+
+    case RSP_DTLB_DIRTY_LL:
+        if ( ! p_vci_ini_rw.rspval.read() )
+            break;
+
+        assert(p_vci_ini_rw.reop.read() &&
+               "illegal VCI response packet for ll tlb");
+
+        if ( p_vci_ini_rw.rerror.read() != vci_param::ERR_NORMAL ) 
+        {
+            r_vci_rsp_data_error = true;
+        }
+	    else
+	    {
+	        r_dcache_miss_buf[0] = (data_t)p_vci_ini_rw.rdata.read();
+	    }
+        r_vci_rsp_data_ok = true;
+        r_vci_rsp_fsm = RSP_IDLE;
+	    break;
+
+    case RSP_DTLB_DIRTY_SC:
+        if ( ! p_vci_ini_rw.rspval.read() )
+            break;
+
+        assert(p_vci_ini_rw.reop.read() &&
+               "illegal VCI response packet for sc tlb");
+
+        if ( p_vci_ini_rw.rerror.read() != vci_param::ERR_NORMAL ) 
+        {
+            r_vci_rsp_data_error = true;
+        }
+	    else if ( p_vci_ini_rw.rdata.read() == 1 ) // store conditional is not successful
+	    {
+            r_dcache_tlb_sc_fail = true;
+	    }
+        r_vci_rsp_data_ok = true;
+        r_vci_rsp_fsm = RSP_IDLE;
+	    break;
+
+    case RSP_DATA_UNC:
+        m_cost_unc_transaction++;
+        if ( ! p_vci_ini_rw.rspval.read() ) 
+            break;
+
+        assert(p_vci_ini_rw.reop.read() &&
+               "illegal VCI response packet for data read uncached");
+
+        if ( p_vci_ini_rw.rerror.read() != vci_param::ERR_NORMAL ) 
+        {
+            r_vci_rsp_data_error = true;
+        }
+        else
+        {
+            r_dcache_miss_buf[0] = (data_t)p_vci_ini_rw.rdata.read();
+            r_vci_rsp_data_ok = true;
+        }
+        r_vci_rsp_fsm = RSP_IDLE;
+        break;
+
+    case RSP_DATA_MISS:
+        m_cost_dmiss_transaction++;
+        if ( ! p_vci_ini_rw.rspval.read() )
+            break;
+
+        assert(r_vci_rsp_cpt != m_dcache_words &&
+               "illegal VCI response packet for data read miss");
+
+        r_vci_rsp_cpt = r_vci_rsp_cpt + 1;
+        r_dcache_miss_buf[r_vci_rsp_cpt] = (data_t)p_vci_ini_rw.rdata.read();
+        if ( p_vci_ini_rw.reop.read() ) 
+        {
+            assert(r_vci_rsp_cpt == m_dcache_words - 1 &&
+                    "illegal VCI response packet for data read miss");
+            r_vci_rsp_data_ok = true;
+            r_vci_rsp_fsm = RSP_IDLE;
+        } 
+        if ( p_vci_ini_rw.rerror.read() != vci_param::ERR_NORMAL )
+        {
+            r_vci_rsp_data_error = true;
+        }
+        break;
+
+    case RSP_DATA_WRITE:
+        m_cost_write_transaction++;
+        if ( ! p_vci_ini_rw.rspval.read() )
+            break;
+
+        if ( p_vci_ini_rw.reop.read() ) 
+        {
+            r_vci_rsp_fsm = RSP_IDLE;
+	        r_wbuf.completed( p_vci_ini_rw.rtrdid.read() & 0x0f );            
+        }
+        if ( p_vci_ini_rw.rerror.read() != vci_param::ERR_NORMAL ) 
+        {
+            m_iss.setWriteBerr();
+        }
+        break; 
+    } // end switch r_vci_rsp_fsm
+} // end transition()
+
+///////////////////////
+tmpl(void)::genMoore()
+///////////////////////
+{
+    switch ( r_cleanup_fsm.read() ) {
+
+    case CLEANUP_CMD:
+	    p_vci_ini_c.rspack  = false;
+        p_vci_ini_c.cmdval  = r_icache_cleanup_req || r_dcache_cleanup_req;
+        if ( r_icache_cleanup_req ) 
+	    {
+	        p_vci_ini_c.address = r_icache_cleanup_line.read() * (m_icache_words<<2);
+            if ( r_icache_cleanup_type == TLB_CLEANUP )
+            {    
+                p_vci_ini_c.trdid  = 3; // ins TLB cleanup 
+            }
+            else
+            {
+                p_vci_ini_c.trdid  = 1; // ins cleanup       
+            }                
+	    }
+        else 
+	    {                                    
+	        p_vci_ini_c.address = r_dcache_cleanup_line.read() * (m_dcache_words<<2);
+            if ( r_dcache_cleanup_type == TLB_CLEANUP )
+            {    
+                p_vci_ini_c.trdid  = 2; // data TLB cleanup 
+            }
+            else
+            {
+                p_vci_ini_c.trdid  = 0; // data cleanup       
+            }                
+	    }
+        p_vci_ini_c.wdata  = 0;
+        p_vci_ini_c.be     = 0xF;
+        p_vci_ini_c.plen   = 4;
+        p_vci_ini_c.cmd    = vci_param::CMD_WRITE;
+        p_vci_ini_c.pktid  = 0;
+        p_vci_ini_c.srcid  = m_srcid_c;
+        p_vci_ini_c.cons   = false;
+        p_vci_ini_c.wrap   = false;
+        p_vci_ini_c.contig = false;
+        p_vci_ini_c.clen   = 0;
+        p_vci_ini_c.cfixed = false;
+        p_vci_ini_c.eop = true;
+        break;
+
+    case CLEANUP_ICACHE_RSP:
+    case CLEANUP_DCACHE_RSP:
+        p_vci_ini_c.rspack  = true;
+        p_vci_ini_c.cmdval  = false;
+        p_vci_ini_c.address = 0;
+        p_vci_ini_c.wdata   = 0;
+        p_vci_ini_c.be      = 0;
+        p_vci_ini_c.plen    = 0;
+        p_vci_ini_c.cmd     = vci_param::CMD_NOP;
+        p_vci_ini_c.trdid   = 0;
+        p_vci_ini_c.pktid   = 0;
+        p_vci_ini_c.srcid   = m_srcid_c;
+        p_vci_ini_c.cons    = false;
+        p_vci_ini_c.wrap    = false;
+        p_vci_ini_c.contig  = false;
+        p_vci_ini_c.clen    = 0;
+        p_vci_ini_c.cfixed  = false;
+        p_vci_ini_c.eop     = false;
+	break;
+    } // end switch r_cleanup_fsm
+
+    // VCI initiator response
+    p_vci_ini_rw.rspack = ( r_vci_rsp_fsm != RSP_IDLE );
+
+    // VCI initiator command
+    p_vci_ini_rw.pktid  = 0;
+    p_vci_ini_rw.srcid  = m_srcid_rw;
+    p_vci_ini_rw.cons   = false;
+    p_vci_ini_rw.wrap   = false;
+    p_vci_ini_rw.contig = true;
+    p_vci_ini_rw.clen   = 0;
+    p_vci_ini_rw.cfixed = false;
+    
+    switch (r_vci_cmd_fsm) {
+
+    case CMD_IDLE:
+        p_vci_ini_rw.cmdval  = false;
+        p_vci_ini_rw.address = 0;
+        p_vci_ini_rw.wdata   = 0;
+        p_vci_ini_rw.be      = 0;
+        p_vci_ini_rw.trdid   = 0;
+        p_vci_ini_rw.plen    = 0;
+        p_vci_ini_rw.cmd     = vci_param::CMD_NOP;
+        p_vci_ini_rw.eop     = false;
+        break;
+
+    case CMD_ITLB_READ:     
+        p_vci_ini_rw.cmdval  = true;
+        p_vci_ini_rw.wdata   = 0;
+        p_vci_ini_rw.be      = 0xF;
+        if ( r_icache_tlb_first_req )
+        { 
+            p_vci_ini_rw.address = r_icache_paddr_save.read() & ~0x3;
+            p_vci_ini_rw.trdid = TYPE_INS_TLB_1; // ins TLB uncached read
+            p_vci_ini_rw.plen  = 4;
+        }
+        else
+        { 
+            p_vci_ini_rw.address = r_icache_paddr_save.read() & ~0x3;
+            p_vci_ini_rw.trdid = TYPE_INS_TLB_2; // ins TLB cached read 2 words
+            p_vci_ini_rw.plen  = 8; 
+        }
+        p_vci_ini_rw.cmd     = vci_param::CMD_READ;
+        p_vci_ini_rw.eop     = true;
+        break;
+
+    case CMD_ITLB_ACC_LL:
+        p_vci_ini_rw.cmdval  = true;
+        p_vci_ini_rw.address = r_icache_paddr_save.read() & ~0x3;
+        p_vci_ini_rw.wdata   = 0;
+        p_vci_ini_rw.be      = 0xF;
+        p_vci_ini_rw.trdid   = TYPE_INS_LL_ACC; // ins TLB uncached read
+        p_vci_ini_rw.plen    = 4;
+        p_vci_ini_rw.cmd     = vci_param::CMD_LOCKED_READ;
+        p_vci_ini_rw.eop     = true;
+	break;
+
+    case CMD_ITLB_ACC_SC:
+        p_vci_ini_rw.cmdval  = true;
+        p_vci_ini_rw.address = r_icache_paddr_save.read() & ~0x3;
+        p_vci_ini_rw.wdata   = r_icache_pte_update.read();
+        p_vci_ini_rw.be      = 0xF;
+        p_vci_ini_rw.trdid   = TYPE_INS_SC_ACC; // ins TLB uncached read
+        p_vci_ini_rw.plen    = 4;
+        p_vci_ini_rw.cmd     = vci_param::CMD_STORE_COND;
+        p_vci_ini_rw.eop     = true;
+	break;	
+
+    case CMD_INS_MISS:
+        p_vci_ini_rw.cmdval  = true;
+        p_vci_ini_rw.address = r_icache_paddr_save.read() & m_icache_yzmask;
+        p_vci_ini_rw.wdata   = 0;
+        p_vci_ini_rw.be      = 0xF;
+        p_vci_ini_rw.trdid   = TYPE_INS_MISS;
+        p_vci_ini_rw.plen    = m_icache_words << 2;
+        p_vci_ini_rw.cmd     = vci_param::CMD_READ;
+        p_vci_ini_rw.eop     = true;
+        break;
+
+    case CMD_INS_UNC:
+        p_vci_ini_rw.cmdval  = true;
+        p_vci_ini_rw.address = r_icache_paddr_save.read() & ~0x3;
+        p_vci_ini_rw.wdata   = 0;
+        p_vci_ini_rw.be      = 0xF;
+        p_vci_ini_rw.trdid   = TYPE_INS_UNC;
+        p_vci_ini_rw.plen    = 4;
+        p_vci_ini_rw.cmd     = vci_param::CMD_READ;
+        p_vci_ini_rw.eop     = true;
+        break;
+
+    case CMD_DTLB_READ:     
+        p_vci_ini_rw.cmdval  = true;
+        p_vci_ini_rw.wdata   = 0;
+        p_vci_ini_rw.be      = 0xF;
+        if ( r_dcache_tlb_first_req ) 
+        {
+            p_vci_ini_rw.address = r_dcache_tlb_paddr.read() & ~0x3;
+            p_vci_ini_rw.trdid = TYPE_DATA_TLB_1; // data TLB uncached read
+            p_vci_ini_rw.plen  = 4;
+        }
+        else
+        { 
+            p_vci_ini_rw.address = r_dcache_tlb_paddr.read() & ~0x3;
+            p_vci_ini_rw.trdid = TYPE_DATA_TLB_2; // data TLB cached read 2 words
+            p_vci_ini_rw.plen  = 8; 
+        }
+        p_vci_ini_rw.cmd     = vci_param::CMD_READ;
+        p_vci_ini_rw.eop     = true;
+        break;
+
+    case CMD_DTLB_ACC_LL:
+        p_vci_ini_rw.cmdval  = true;
+        p_vci_ini_rw.address = r_dcache_tlb_paddr.read() & ~0x3;
+        p_vci_ini_rw.wdata   = 0;
+        p_vci_ini_rw.be      = 0xF;
+        p_vci_ini_rw.trdid   = TYPE_DATA_LL_ACC; // data TLB uncached read
+        p_vci_ini_rw.plen    = 4;
+        p_vci_ini_rw.cmd     = vci_param::CMD_LOCKED_READ;
+        p_vci_ini_rw.eop     = true;
+	break;
+
+    case CMD_DTLB_ACC_SC:
+        p_vci_ini_rw.cmdval  = true;
+        p_vci_ini_rw.address = r_dcache_tlb_paddr.read() & ~0x3;
+        p_vci_ini_rw.wdata   = r_dcache_pte_update.read();
+        p_vci_ini_rw.be      = 0xF;
+        p_vci_ini_rw.trdid   = TYPE_DATA_SC_ACC; // data TLB uncached read
+        p_vci_ini_rw.plen    = 4;
+        p_vci_ini_rw.cmd     = vci_param::CMD_STORE_COND;
+        p_vci_ini_rw.eop     = true;
+	break;	
+
+    case CMD_DTLB_DIRTY_LL:
+        p_vci_ini_rw.cmdval  = true;
+        p_vci_ini_rw.address = r_dcache_tlb_paddr.read() & ~0x3;
+        p_vci_ini_rw.wdata   = 0;
+        p_vci_ini_rw.be      = 0xF;
+        p_vci_ini_rw.trdid   = TYPE_DATA_LL_D; // data TLB uncached read
+        p_vci_ini_rw.plen    = 4;
+        p_vci_ini_rw.cmd     = vci_param::CMD_LOCKED_READ;
+        p_vci_ini_rw.eop     = true;
+	break;
+
+    case CMD_DTLB_DIRTY_SC:
+        p_vci_ini_rw.cmdval  = true;
+        p_vci_ini_rw.address = r_dcache_tlb_paddr.read() & ~0x3;
+        p_vci_ini_rw.wdata   = r_dcache_pte_update.read();
+        p_vci_ini_rw.be      = 0xF;
+        p_vci_ini_rw.trdid   = TYPE_DATA_SC_D; // data TLB uncached read
+        p_vci_ini_rw.plen    = 4;
+        p_vci_ini_rw.cmd     = vci_param::CMD_STORE_COND;
+        p_vci_ini_rw.eop     = true;
+	break;	
+
+    case CMD_DATA_UNC:
+        p_vci_ini_rw.cmdval  = true;
+        p_vci_ini_rw.address = r_dcache_paddr_save.read() & ~0x3;
+        p_vci_ini_rw.trdid   = TYPE_DATA_UNC;
+        p_vci_ini_rw.plen    = 4;
+        p_vci_ini_rw.eop     = true;
+        switch(r_dcache_type_save) {
+        case iss_t::DATA_READ:
+            p_vci_ini_rw.wdata = 0;
+            p_vci_ini_rw.be    = r_dcache_be_save.read();
+            p_vci_ini_rw.cmd   = vci_param::CMD_READ;
+            break;
+        case iss_t::DATA_LL:
+            p_vci_ini_rw.wdata = 0;
+            p_vci_ini_rw.be    = 0xF;
+            p_vci_ini_rw.cmd   = vci_param::CMD_LOCKED_READ;
+            break;
+        case iss_t::DATA_SC:
+            p_vci_ini_rw.wdata = r_dcache_wdata_save.read();
+            p_vci_ini_rw.be    = 0xF;
+            p_vci_ini_rw.cmd   = vci_param::CMD_STORE_COND;
+            break;
+        default:
+            assert("this should not happen");
+        }
+        break;
+
+    case CMD_DATA_WRITE:
+        p_vci_ini_rw.cmdval  = true;
+        p_vci_ini_rw.address = r_wbuf.getAddress(r_vci_cmd_cpt);
+        p_vci_ini_rw.wdata   = r_wbuf.getData(r_vci_cmd_cpt);
+        p_vci_ini_rw.be      = r_wbuf.getBe(r_vci_cmd_cpt);
+        p_vci_ini_rw.trdid   = (r_wbuf.getIndex() | 0x30); // data cache write
+        p_vci_ini_rw.plen    = (r_vci_cmd_max - r_vci_cmd_min + 1)<<2;
+        p_vci_ini_rw.cmd     = vci_param::CMD_WRITE;
+        p_vci_ini_rw.eop     = (r_vci_cmd_cpt == r_vci_cmd_max);
+        break;
+
+    case CMD_DATA_MISS:
+        p_vci_ini_rw.cmdval  = true;
+        p_vci_ini_rw.address = r_dcache_paddr_save.read() & m_dcache_yzmask;
+        p_vci_ini_rw.wdata   = 0;
+        p_vci_ini_rw.be      = 0xF;
+        p_vci_ini_rw.trdid   = TYPE_DATA_MISS;
+        p_vci_ini_rw.plen    = m_dcache_words << 2;
+        p_vci_ini_rw.cmd     = vci_param::CMD_READ;
+        p_vci_ini_rw.eop     = true;
+        break;
+    } // end switch r_vci_cmd_fsm
+
+    // VCI_TGT
+    switch ( r_vci_tgt_fsm.read() ) {
+
+    case TGT_IDLE:
+    case TGT_UPDT_WORD:
+    case TGT_UPDT_DATA:
+        p_vci_tgt.cmdack  = true;
+        p_vci_tgt.rspval  = false;
+        break;
+
+    case TGT_RSP_BROADCAST:
+        p_vci_tgt.cmdack  = false;
+        p_vci_tgt.rspval  = !r_tgt_icache_req.read() && !r_tgt_dcache_req.read() && 
+                            ( r_tgt_icache_rsp | r_tgt_dcache_rsp | r_ccinval_itlb_cpt | r_ccinval_dtlb_cpt );
+        p_vci_tgt.rsrcid  = r_tgt_srcid.read();
+        p_vci_tgt.rpktid  = r_tgt_pktid.read();
+        p_vci_tgt.rtrdid  = r_tgt_trdid.read();
+        p_vci_tgt.rdata   = 0;
+        p_vci_tgt.rerror  = 0;
+        p_vci_tgt.reop    = true;
+        break;
+
+    case TGT_RSP_ICACHE:
+        p_vci_tgt.cmdack  = false;
+        p_vci_tgt.rspval  = !r_tgt_icache_req.read() && r_tgt_icache_rsp.read();
+        p_vci_tgt.rsrcid  = r_tgt_srcid.read();
+        p_vci_tgt.rpktid  = r_tgt_pktid.read();
+        p_vci_tgt.rtrdid  = r_tgt_trdid.read();
+        p_vci_tgt.rdata   = 0;
+        p_vci_tgt.rerror  = 0;
+        p_vci_tgt.reop    = true;
+        break;
+
+    case TGT_RSP_DCACHE:
+        p_vci_tgt.cmdack  = false;
+        p_vci_tgt.rspval  = !r_tgt_dcache_req.read() && r_tgt_dcache_rsp.read();
+        p_vci_tgt.rsrcid  = r_tgt_srcid.read();
+        p_vci_tgt.rpktid  = r_tgt_pktid.read();
+        p_vci_tgt.rtrdid  = r_tgt_trdid.read();
+        p_vci_tgt.rdata   = 0;
+        p_vci_tgt.rerror  = 0;
+        p_vci_tgt.reop    = true;
+        break;
+
+    case TGT_REQ_BROADCAST:
+    case TGT_REQ_ICACHE:
+    case TGT_REQ_DCACHE:
+        p_vci_tgt.cmdack  = false;
+        p_vci_tgt.rspval  = false;
+        break;
+
+    } // end switch TGT_FSM
+
+#ifdef SOCLIB_MODULE_DEBUG 
+   std::cout << name()  
+             << "Moore:" << std::hex
+             << "p_vci_ini_rw.cmdval:" << p_vci_ini_rw.cmdval
+             << "p_vci_ini_rw.address:" << p_vci_ini_rw.address
+             << "p_vci_ini_rw.wdata:" << p_vci_ini_rw.wdata
+             << "p_vci_ini_rw.cmd:" << p_vci_ini_rw.cmd
+             << "p_vci_ini_rw.eop:" << p_vci_ini_rw.eop
+             << std::endl;
+
+   std::cout << name()  
+             << "Moore:" << std::hex
+             << "p_vci_ini_c.cmdval:" << p_vci_ini_c.cmdval
+             << "p_vci_ini_c.address:" << p_vci_ini_c.address
+             << "p_vci_ini_c.cmd:" << p_vci_ini_c.cmd
+             << "p_vci_ini_c.eop:" << p_vci_ini_c.eop
+             << std::endl;
+
+   std::cout << name()  
+             << "Moore:" << std::hex
+             << "p_vci_tgt.cmdack:" << p_vci_tgt.cmdack
+             << "p_vci_tgt.rspval:" << p_vci_tgt.rspval
+             << "p_vci_tgt.rsrcid:" << p_vci_tgt.rsrcid
+             << "p_vci_tgt.rtrdid:" << p_vci_tgt.rtrdid
+             << "p_vci_tgt.reop:" << p_vci_tgt.reop
+             << std::endl;
+
+#endif
+}
+
+}}
+
+// Local Variables:
+// tab-width: 4
+// c-basic-offset: 4
+// c-file-offsets:((innamespace . 0)(inline-open . 0))
+// indent-tabs-mode: nil
+// End:
+
+// vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4
+
+
Index: branches/v4/modules/vci_cc_vcache_wrapper_v1/caba/metadata/vci_cc_vcache_wrapper_v1.sd
===================================================================
--- branches/v4/modules/vci_cc_vcache_wrapper_v1/caba/metadata/vci_cc_vcache_wrapper_v1.sd	(revision 371)
+++ branches/v4/modules/vci_cc_vcache_wrapper_v1/caba/metadata/vci_cc_vcache_wrapper_v1.sd	(revision 371)
@@ -0,0 +1,61 @@
+
+# -*- python -*-
+
+__id__ = "$Id: vci_cc_vcache_wrapper_v1.sd 917 2009-03-12 10:10:06Z nipo $"
+__version__ = "$Revision: 917 $"
+
+Module('caba:vci_cc_vcache_wrapper_v1',
+	classname = 'soclib::caba::VciCcVCacheWrapperV1',
+	   tmpl_parameters = [
+	parameter.Module('vci_param', default = 'caba:vci_param'),
+	parameter.Module('iss_t'),
+	],
+	header_files = [
+	'../source/include/vci_cc_vcache_wrapper_v1.h',
+	],
+	implementation_files = [
+	'../source/src/vci_cc_vcache_wrapper_v1.cpp',
+	],
+	uses = [
+	Uses('caba:base_module'),
+	Uses('caba:write_buffer'),
+	Uses('caba:generic_tlb', addr_t = parameter.StringExt('sc_dt::sc_uint<%d> ', parameter.Reference('addr_size'))),
+	Uses('caba:generic_cache', addr_t = parameter.StringExt('sc_dt::sc_uint<%d> ', parameter.Reference('addr_size'))),
+	Uses('common:address_masking_table', data_t = parameter.StringExt('sc_dt::sc_uint<%d> ', parameter.Reference('addr_size'))),
+	Uses('common:iss2'),
+	Uses('common:mapping_table'),
+	],
+	ports = [
+	Port('caba:vci_initiator', 'p_vci_ini_rw'),
+	Port('caba:vci_initiator', 'p_vci_ini_c'),
+	Port('caba:vci_target', 'p_vci_tgt'),
+	Port('caba:bit_in','p_irq', parameter.Constant('n_irq')),
+	Port('caba:bit_in', 'p_resetn', auto = 'resetn'),
+	Port('caba:clock_in', 'p_clk', auto = 'clock'),
+	],
+	instance_parameters = [
+	parameter.Int('proc_id'),
+	parameter.Module('mt', 'common:mapping_table', auto='env:mapping_table'),
+	parameter.Module('mc', 'common:mapping_table', auto='env:mapping_table'),
+	parameter.IntTab('initiator_rw_index'),
+	parameter.IntTab('initiator_c_index'),
+	parameter.IntTab('target_index'),
+    	parameter.Int('itlb_ways'),
+    	parameter.Int('itlb_sets'),
+    	parameter.Int('dtlb_ways'),
+    	parameter.Int('dtlb_sets'),
+    	parameter.Int('icache_ways'),
+    	parameter.Int('icache_sets'),
+    	parameter.Int('icache_words'),
+    	parameter.Int('dcache_ways'),
+    	parameter.Int('dcache_sets'),
+    	parameter.Int('dcache_words'),
+    	parameter.Int('write_buf_size'),
+	],
+	   extensions = [
+	'dsx:get_ident=initiator_index:p_vci_ini_rw',
+	'dsx:cpu=wrapper:iss_t',
+	'dsx:mapping_type=processor:proc_id',
+   ],
+)
+
Index: branches/v4/modules/vci_cc_vcache_wrapper_v1/caba/source/include/vci_cc_vcache_wrapper_v1.h
===================================================================
--- branches/v4/modules/vci_cc_vcache_wrapper_v1/caba/source/include/vci_cc_vcache_wrapper_v1.h	(revision 371)
+++ branches/v4/modules/vci_cc_vcache_wrapper_v1/caba/source/include/vci_cc_vcache_wrapper_v1.h	(revision 371)
@@ -0,0 +1,551 @@
+/* -*- c++ -*-
+ * File : vci_cc_vcache_wrapper_v1.h
+ * Copyright (c) UPMC, Lip6, SoC
+ * Authors : Alain GREINER, Yang GAO
+ *
+ * SOCLIB_LGPL_HEADER_BEGIN
+ * 
+ * This file is part of SoCLib, GNU LGPLv2.1.
+ * 
+ * SoCLib is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU Lesser General Public License as published
+ * by the Free Software Foundation; version 2.1 of the License.
+ * 
+ * SoCLib is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * Lesser General Public License for more details.
+ * 
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with SoCLib; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301 USA
+ * 
+ * SOCLIB_LGPL_HEADER_END
+ */
+ 
+#ifndef SOCLIB_CABA_VCI_CC_VCACHE_WRAPPER_V1_H
+#define SOCLIB_CABA_VCI_CC_VCACHE_WRAPPER_V1_H
+
+#include <inttypes.h>
+#include <systemc>
+#include "caba_base_module.h"
+#include "write_buffer.h"
+#include "generic_cache.h"
+#include "vci_initiator.h"
+#include "vci_target.h"
+#include "mapping_table.h"
+#include "generic_tlb.h"
+#include "static_assert.h"
+
+namespace soclib {
+namespace caba {
+
+using namespace sc_core;
+
+////////////////////////////////////////////
+template<typename vci_param, typename iss_t>
+class VciCcVCacheWrapperV1
+////////////////////////////////////////////
+    : public soclib::caba::BaseModule
+{
+    typedef uint32_t vaddr_t;
+    typedef uint32_t data_t;
+    typedef uint32_t tag_t;
+    typedef uint32_t type_t;
+    typedef typename iss_t::DataOperationType data_op_t;
+
+    typedef typename vci_param::addr_t  paddr_t;
+    typedef typename vci_param::be_t    vci_be_t;
+	typedef typename vci_param::srcid_t vci_srcid_t;
+	typedef typename vci_param::trdid_t vci_trdid_t;
+	typedef typename vci_param::pktid_t vci_pktid_t;
+	typedef typename vci_param::plen_t  vci_plen_t;
+
+    enum icache_fsm_state_e {  
+        ICACHE_IDLE,                // 00
+        ICACHE_BIS,                 // 01
+        ICACHE_TLB1_READ,           // 02
+        ICACHE_TLB1_LL_WAIT,        // 03
+        ICACHE_TLB1_SC_WAIT,        // 04
+        ICACHE_TLB1_UPDT_SEL,       // 05
+        ICACHE_TLB1_UPDT,           // 06
+        ICACHE_TLB2_READ,           // 07
+        ICACHE_TLB2_LL_WAIT,        // 08
+        ICACHE_TLB2_SC_WAIT,        // 09
+        ICACHE_TLB2_UPDT_SEL,       // 0a
+        ICACHE_TLB2_UPDT,           // 0b
+        ICACHE_TLB_FLUSH,           // 0c
+        ICACHE_CACHE_FLUSH,         // 0d
+        ICACHE_TLB_INVAL,           // 0e
+        ICACHE_CACHE_INVAL,         // 0f
+        ICACHE_CACHE_INVAL_PA,      // 10
+        ICACHE_MISS_WAIT,           // 11
+        ICACHE_UNC_WAIT,            // 12
+        ICACHE_MISS_UPDT,           // 13
+        ICACHE_ERROR,               // 14
+        ICACHE_CC_INVAL,            // 15
+        ICACHE_TLB_CC_INVAL,        // 16
+    };
+
+    enum dcache_fsm_state_e {  
+        DCACHE_IDLE,                // 00
+        DCACHE_BIS,                 // 01
+        DCACHE_TLB1_READ,           // 02
+        DCACHE_TLB1_LL_WAIT,        // 03
+        DCACHE_TLB1_SC_WAIT,        // 04
+        DCACHE_TLB1_UPDT_SEL,       // 05
+        DCACHE_TLB1_UPDT,           // 06
+        DCACHE_TLB2_READ,           // 07
+        DCACHE_TLB2_LL_WAIT,        // 08
+        DCACHE_TLB2_SC_WAIT,        // 09
+        DCACHE_TLB2_UPDT_SEL,       // 0a
+        DCACHE_TLB2_UPDT,           // 0b
+        DCACHE_CTXT_SWITCH,         // 0c
+        DCACHE_ICACHE_FLUSH,        // 0d
+        DCACHE_DCACHE_FLUSH,        // 0e
+        DCACHE_ITLB_INVAL,          // 0f
+        DCACHE_DTLB_INVAL,          // 10
+        DCACHE_ICACHE_INVAL,        // 11
+        DCACHE_DCACHE_INVAL,        // 12
+        DCACHE_ICACHE_INVAL_PA,     // 13
+        DCACHE_DCACHE_INVAL_PA,     // 14
+        DCACHE_DCACHE_SYNC,         // 15
+        DCACHE_LL_DIRTY_WAIT,       // 16
+        DCACHE_SC_DIRTY_WAIT,       // 17
+        DCACHE_WRITE_UPDT,          // 18
+        DCACHE_WRITE_DIRTY,         // 19
+        DCACHE_WRITE_REQ,           // 1a
+        DCACHE_MISS_WAIT,           // 1b
+        DCACHE_MISS_UPDT,           // 1c
+        DCACHE_UNC_WAIT,            // 1d
+        DCACHE_ERROR,               // 1e
+        DCACHE_CC_CHECK,            // 1f 
+        DCACHE_CC_INVAL,            // 20
+        DCACHE_CC_UPDT,             // 21
+        DCACHE_CC_NOP,              // 22
+        DCACHE_TLB_CC_INVAL,        // 23
+    };
+
+    enum cmd_fsm_state_e {      
+        CMD_IDLE,           // 00
+        CMD_ITLB_READ,      // 01
+        CMD_ITLB_ACC_LL,    // 02
+        CMD_ITLB_ACC_SC,    // 03
+        CMD_INS_MISS,       // 04
+        CMD_INS_UNC,        // 05
+        CMD_DTLB_READ,      // 06
+        CMD_DTLB_ACC_LL,    // 07
+        CMD_DTLB_ACC_SC,    // 08
+        CMD_DTLB_DIRTY_LL,  // 09
+        CMD_DTLB_DIRTY_SC,  // 0a
+        CMD_DATA_UNC,       // 0b
+        CMD_DATA_MISS,      // 0c
+        CMD_DATA_WRITE,     // 0d
+        CMD_INS_CLEANUP,    // 0e
+        CMD_DATA_CLEANUP,   // 0f
+    };
+
+    enum rsp_fsm_state_e {       
+        RSP_IDLE,           // 00
+        RSP_ITLB_READ,      // 01
+        RSP_ITLB_ACC_LL,    // 02
+        RSP_ITLB_ACC_SC,    // 03
+        RSP_INS_MISS,       // 04
+        RSP_INS_UNC,        // 05
+        RSP_DTLB_READ,      // 06
+        RSP_DTLB_ACC_LL,    // 07
+        RSP_DTLB_ACC_SC,    // 08
+        RSP_DTLB_DIRTY_LL,  // 09
+        RSP_DTLB_DIRTY_SC,  // 0a
+        RSP_DATA_MISS,      // 0b
+        RSP_DATA_UNC,       // 0c
+        RSP_DATA_WRITE,     // 0d
+        RSP_INS_CLEANUP,    // 0e
+        RSP_DATA_CLEANUP,   // 0f
+    };
+
+    enum tgt_fsm_state_e {  
+        TGT_IDLE,                   // 00
+        TGT_UPDT_WORD,              // 01
+        TGT_UPDT_DATA,              // 02
+        TGT_REQ_BROADCAST,          // 03
+        TGT_REQ_ICACHE,             // 04
+        TGT_REQ_DCACHE,             // 05
+        TGT_RSP_BROADCAST,          // 06
+        TGT_RSP_ICACHE,             // 07
+        TGT_RSP_DCACHE,             // 08
+    };
+
+    enum inval_itlb_fsm_state_e {
+        INVAL_ITLB_IDLE,        // 00
+        INVAL_ITLB_CHECK,       // 01
+        INVAL_ITLB_INVAL,       // 02
+        INVAL_ITLB_CLEAR,       // 03
+    };
+
+    enum inval_dtlb_fsm_state_e {
+        INVAL_DTLB_IDLE,        // 00
+        INVAL_DTLB_CHECK,       // 01
+        INVAL_DTLB_INVAL,       // 02
+        INVAL_DTLB_CLEAR,       // 03
+    };
+
+    // TLB Mode ITLB / DTLB / ICACHE / DCACHE
+    enum {          
+        ALL_DEACTIVE = 0x0000,   // TLBs disactive caches disactive
+        INS_TLB_MASK    = 0x8,
+        DATA_TLB_MASK   = 0x4,
+        INS_CACHE_MASK  = 0x2,
+        DATA_CACHE_MASK = 0x1,
+    };
+
+    // Error Type
+    enum mmu_error_type_e {
+        MMU_NONE                      = 0x0000, // None
+        MMU_WRITE_PT1_UNMAPPED 	      = 0x0001, // Write access of Page fault on Page Table 1          (non fatal error)
+        MMU_WRITE_PT2_UNMAPPED 	      = 0x0002, // Write access of Page fault on Page Table 2          (non fatal error)
+        MMU_WRITE_PRIVILEGE_VIOLATION = 0x0004, // Write access of Protected access in user mode       (user error)
+        MMU_WRITE_ACCES_VIOLATION 	  = 0x0008, // Write access of write access to a non writable page (user error)
+        MMU_WRITE_UNDEFINED_XTN 	  = 0x0020, // Write access of undefined external access address   (user error)
+        MMU_WRITE_PT1_ILLEGAL_ACCESS  = 0x0040, // Write access of Bus Error accessing Table 1         (kernel error)
+        MMU_WRITE_PT2_ILLEGAL_ACCESS  = 0x0080, // Write access of Bus Error accessing Table 2         (kernel error)
+        MMU_WRITE_DATA_ILLEGAL_ACCESS = 0x0100, // Write access of Bus Error in cache access           (kernel error)
+        MMU_READ_PT1_UNMAPPED 	      = 0x1001, // Read access of Page fault on Page Table 1  	       (non fatal error)
+        MMU_READ_PT2_UNMAPPED 	      = 0x1002, // Read access of Page fault on Page Table 2  	       (non fatal error)
+        MMU_READ_PRIVILEGE_VIOLATION  = 0x1004, // Read access of Protected access in user mode 	   (user error)
+        MMU_READ_EXEC_VIOLATION 	  = 0x1010, // Exec access to a non exec page                      (user error)
+        MMU_READ_UNDEFINED_XTN 	      = 0x1020, // Read access of Undefined external access address    (user error)
+        MMU_READ_PT1_ILLEGAL_ACCESS   = 0x1040, // Read access of Bus Error in Table1 access           (kernel error)
+        MMU_READ_PT2_ILLEGAL_ACCESS   = 0x1080, // Read access of Bus Error in Table2 access 	       (kernel error)
+        MMU_READ_DATA_ILLEGAL_ACCESS  = 0x1100, // Read access of Bus Error in cache access 	       (kernel error)
+    };
+
+    // Cleanup Type
+    enum {
+        NONE,           // reset 
+        CACHE_CLEANUP,  // cache cleanup
+        TLB_CLEANUP,    // TLB cleanup
+    };
+
+public:
+    sc_in<bool>                             p_clk;
+    sc_in<bool>                             p_resetn;
+    sc_in<bool>                             p_irq[iss_t::n_irq];
+    soclib::caba::VciInitiator<vci_param>   p_vci_ini_rw;
+    soclib::caba::VciInitiator<vci_param>   p_vci_ini_c;
+    soclib::caba::VciTarget<vci_param>      p_vci_tgt;
+
+private:
+    // STRUCTURAL PARAMETERS
+    soclib::common::AddressDecodingTable<uint32_t, bool>    m_cacheability_table;
+    const soclib::common::Segment                           m_segment;
+    iss_t                                                   m_iss;   
+    const vci_srcid_t                                       m_srcid_rw;
+    const vci_srcid_t                                       m_srcid_c;
+
+    const size_t  m_itlb_ways;
+    const size_t  m_itlb_sets;
+
+    const size_t  m_dtlb_ways;
+    const size_t  m_dtlb_sets;
+
+    const size_t  m_icache_ways;
+    const size_t  m_icache_sets;
+    const size_t  m_icache_yzmask;
+    const size_t  m_icache_words;
+
+    const size_t  m_dcache_ways;
+    const size_t  m_dcache_sets;
+    const size_t  m_dcache_yzmask;
+    const size_t  m_dcache_words;
+
+    const size_t  m_write_buf_size;  
+    const size_t  m_paddr_nbits;  
+
+    // instruction and data vcache tlb instances 
+    soclib::caba::GenericCcTlb<paddr_t>    icache_tlb;
+    soclib::caba::GenericCcTlb<paddr_t>    dcache_tlb;
+
+    sc_signal<vaddr_t>      r_mmu_ptpr;             // page table pointer register
+    sc_signal<int>          r_mmu_mode;             // tlb mode register
+    sc_signal<int>          r_mmu_params;           // mmu parameters register
+    sc_signal<int>          r_mmu_release;          // mmu release register
+    sc_signal<int>          r_mmu_word_lo;          // mmu misc data low
+    sc_signal<int>          r_mmu_word_hi;          // mmu mmu misc data hight
+
+    // DCACHE FSM REGISTERS
+    sc_signal<int>          r_dcache_fsm;               // state register
+    sc_signal<paddr_t>      r_dcache_paddr_save;        // physical address
+    sc_signal<data_t>       r_dcache_wdata_save;        // write data
+    sc_signal<data_t>       r_dcache_rdata_save;        // read data
+    sc_signal<type_t>       r_dcache_type_save;         // access type
+    sc_signal<vci_be_t>     r_dcache_be_save;           // byte enable
+    sc_signal<bool>         r_dcache_cached_save;       // used by the write buffer
+    sc_signal<paddr_t>      r_dcache_tlb_paddr;         // physical address of tlb miss
+    sc_signal<bool>         r_dcache_dirty_save;        // used for TLB dirty bit update
+    sc_signal<size_t>       r_dcache_tlb_set_save;      // used for TLB dirty bit update
+    sc_signal<size_t>       r_dcache_tlb_way_save;      // used for TLB dirty bit update
+    sc_signal<vaddr_t>      r_dcache_id1_save;          // used by the PT1 bypass
+    sc_signal<paddr_t>      r_dcache_ptba_save;         // used by the PT1 bypass
+    sc_signal<bool>         r_dcache_ptba_ok;           // used by the PT1 bypass
+    sc_signal<data_t>       r_dcache_pte_update;        // used for page table update
+    sc_signal<tag_t>        r_dcache_ppn_save;          // used for speculative cache access
+    sc_signal<tag_t>        r_dcache_vpn_save;          // used for speculative cache access
+    sc_signal<bool>         r_dtlb_translation_valid;   // used for speculative address
+    sc_signal<bool>         r_dcache_buf_unc_valid;     // used for uncached read
+    sc_signal<bool>         r_dcache_hit_p_save;        // used to save hit_p in case BIS
+
+    sc_signal<data_t>       r_dcache_error_type;        // software visible register
+    sc_signal<vaddr_t>      r_dcache_bad_vaddr;         // software visible register 
+
+    sc_signal<bool>         r_dcache_miss_req;          // used for cached read miss
+    sc_signal<bool>         r_dcache_unc_req;           // used for uncached read miss
+    sc_signal<bool>         r_dcache_write_req;         // used for write 
+    sc_signal<bool>         r_dcache_tlb_read_req;      // used for tlb ptba or pte read 
+    sc_signal<bool>         r_dcache_tlb_first_req;     // used for tlb ptba or pte read    
+    sc_signal<bool>         r_dcache_tlb_ll_acc_req;    // used for tlb entry type update
+    sc_signal<bool>         r_dcache_tlb_sc_acc_req;    // used for tlb entry type update
+    sc_signal<bool>         r_dcache_tlb_ll_dirty_req;  // used for tlb dirty bit update 
+    sc_signal<bool>         r_dcache_tlb_sc_dirty_req;  // used for tlb dirty bit update
+    sc_signal<bool>         r_dcache_sc_updt_dirty;     // used for tlb dirty bit update  
+    sc_signal<bool>         r_dcache_tlb_sc_fail;       // used for tlb entry sc failed
+    sc_signal<bool>         r_dcache_tlb_ptba_read;     // used for tlb ptba read when write dirty bit 
+    sc_signal<bool>         r_dcache_xtn_req;           // used for xtn write for ICACHE
+    
+    // coherence registers
+    sc_signal<int>          r_dcache_fsm_save;          // state save register
+    sc_signal<size_t>       r_dcache_way;
+    sc_signal<size_t>       r_dcache_set;
+    sc_signal<bool>         r_dcache_cleanup_req;
+    sc_signal<data_t>       r_dcache_cleanup_line;
+    sc_signal<int>          r_dcache_cleanup_type;       
+    sc_signal<bool>         r_dcache_inval_rsp;
+
+    // ICACHE FSM REGISTERS
+    sc_signal<int>          r_icache_fsm;               // state register
+    sc_signal<paddr_t>      r_icache_paddr_save;        // physical address
+    sc_signal<vaddr_t>      r_icache_id1_save;          // used by the PT1 bypass
+    sc_signal<paddr_t>      r_icache_ptba_save;         // used by the PT1 bypass
+    sc_signal<bool>         r_icache_ptba_ok;           // used by the PT1 bypass
+    sc_signal<data_t>       r_icache_pte_update;        // used for page table update
+    sc_signal<tag_t>        r_icache_ppn_save;          // used for speculative cache access
+    sc_signal<tag_t>        r_icache_vpn_save;          // used for speculative cache access
+    sc_signal<bool>         r_itlb_translation_valid;   // used for speculative physical address
+    sc_signal<bool>         r_icache_buf_unc_valid;     // used for uncached read
+    sc_signal<vaddr_t>      r_icache_vaddr_req;         // used by the PT1 bypass
+
+    sc_signal<data_t>       r_icache_error_type;        // software visible registers
+    sc_signal<vaddr_t>      r_icache_bad_vaddr;         // software visible registers
+
+    sc_signal<bool>         r_icache_miss_req;          // used for cached read miss
+    sc_signal<bool>         r_icache_unc_req;           // used for uncached read miss
+    sc_signal<bool>         r_icache_tlb_read_req;      // used for tlb ptba or pte read
+    sc_signal<bool>         r_icache_tlb_first_req;     // used for tlb ptba or pte read    
+    sc_signal<bool>         r_icache_tlb_ll_req;        // used for tlb entry type update
+    sc_signal<bool>         r_icache_tlb_sc_req;        // used for tlb entry type update
+    sc_signal<bool>         r_icache_tlb_sc_fail;       // used for tlb entry sc failed
+
+    // coherence registers
+    sc_signal<int>          r_icache_fsm_save;
+    sc_signal<size_t>       r_icache_way;
+    sc_signal<size_t>       r_icache_set;
+    sc_signal<bool>         r_icache_cleanup_req;
+    sc_signal<data_t>       r_icache_cleanup_line;
+    sc_signal<int>          r_icache_cleanup_type;          
+    sc_signal<bool>         r_icache_inval_rsp;
+
+    // VCI_CMD FSM REGISTERS
+    sc_signal<int>          r_vci_cmd_fsm;
+    sc_signal<size_t>       r_vci_cmd_min;       
+    sc_signal<size_t>       r_vci_cmd_max;       
+    sc_signal<size_t>       r_vci_cmd_cpt;     
+
+    // VCI_RSP FSM REGISTERS
+    sc_signal<int>          r_vci_rsp_fsm;
+    sc_signal<size_t>       r_vci_rsp_cpt;
+    sc_signal<bool>         r_vci_rsp_ins_error;
+    sc_signal<bool>         r_vci_rsp_data_error;
+
+    data_t                  *r_icache_miss_buf;    
+    data_t                  *r_dcache_miss_buf;  
+
+    // VCI_TGT FSM REGISTERS
+    data_t                  *r_tgt_buf;
+    bool                    *r_tgt_val;
+
+    sc_signal<int>          r_vci_tgt_fsm;
+    sc_signal<paddr_t>      r_tgt_addr;
+    sc_signal<size_t>       r_tgt_word;
+    sc_signal<bool>         r_tgt_update;
+    sc_signal<bool>         r_tgt_broadcast;
+    sc_signal<vci_srcid_t>  r_tgt_srcid;
+    sc_signal<vci_pktid_t>  r_tgt_pktid;
+    sc_signal<vci_trdid_t>  r_tgt_trdid;
+    sc_signal<vci_plen_t>   r_tgt_plen;
+    sc_signal<bool>         r_tgt_icache_req;
+    sc_signal<bool>         r_tgt_dcache_req;
+    sc_signal<bool>         r_tgt_icache_rsp;
+    sc_signal<bool>         r_tgt_dcache_rsp;
+    sc_signal<size_t>       r_ccinval_itlb_cpt;
+    sc_signal<size_t>       r_ccinval_dtlb_cpt;
+
+    // INVAL CHECK FSM
+    sc_signal<int>          r_inval_itlb_fsm;          
+    sc_signal<bool>         r_icache_tlb_inval_req;    
+    sc_signal<bool>         r_itlb_cc_check_end;
+    sc_signal<size_t>       r_ccinval_itlb_way; 
+    sc_signal<size_t>       r_ccinval_itlb_set; 
+    sc_signal<bool>         r_icache_inval_tlb_rsp;
+    sc_signal<paddr_t>      r_icache_tlb_nline;
+    sc_signal<bool>         r_icache_cc_hit_t;
+
+    sc_signal<int>          r_inval_dtlb_fsm;  
+    sc_signal<bool>         r_dcache_tlb_inval_req;    
+    sc_signal<bool>         r_dtlb_cc_check_end;
+    sc_signal<size_t>       r_ccinval_dtlb_way; 
+    sc_signal<size_t>       r_ccinval_dtlb_set; 
+    sc_signal<bool>         r_dcache_inval_tlb_rsp;
+    sc_signal<paddr_t>      r_dcache_tlb_nline;
+    sc_signal<bool>         r_dcache_cc_hit_t;
+
+    WriteBuffer<paddr_t>     r_wbuf;
+    GenericCache<paddr_t>    r_icache;
+    GenericCache<paddr_t>    r_dcache;
+
+    // Activity counters
+    uint32_t m_cpt_dcache_data_read;        // DCACHE DATA READ
+    uint32_t m_cpt_dcache_data_write;       // DCACHE DATA WRITE
+    uint32_t m_cpt_dcache_dir_read;         // DCACHE DIR READ
+    uint32_t m_cpt_dcache_dir_write;        // DCACHE DIR WRITE
+
+    uint32_t m_cpt_icache_data_read;        // ICACHE DATA READ
+    uint32_t m_cpt_icache_data_write;       // ICACHE DATA WRITE
+    uint32_t m_cpt_icache_dir_read;         // ICACHE DIR READ
+    uint32_t m_cpt_icache_dir_write;        // ICACHE DIR WRITE
+
+    uint32_t m_cpt_frz_cycles;	            // number of cycles where the cpu is frozen
+    uint32_t m_cpt_total_cycles;	        // total number of cycles 
+
+    // Cache activity counters
+    uint32_t m_cpt_read;                    // total number of read data
+    uint32_t m_cpt_write;                   // total number of write data
+    uint32_t m_cpt_data_miss;               // number of read miss
+    uint32_t m_cpt_ins_miss;                // number of instruction miss
+    uint32_t m_cpt_unc_read;                // number of read uncached
+    uint32_t m_cpt_write_cached;            // number of cached write
+    uint32_t m_cpt_ins_read;                // number of instruction read    
+
+    uint32_t m_cost_write_frz;              // number of frozen cycles related to write buffer of cache         
+    uint32_t m_cost_data_miss_frz;          // number of frozen cycles related to data miss of cache
+    uint32_t m_cost_unc_read_frz;           // number of frozen cycles related to uncached read of cache
+    uint32_t m_cost_ins_miss_frz;           // number of frozen cycles related to ins miss of cache
+
+    uint32_t m_cpt_imiss_transaction;       // number of VCI instruction miss transactions
+    uint32_t m_cpt_dmiss_transaction;       // number of VCI data miss transactions
+    uint32_t m_cpt_unc_transaction;         // number of VCI uncached read transactions
+    uint32_t m_cpt_write_transaction;       // number of VCI write transactions
+    uint32_t m_cpt_icache_unc_transaction;  // number of VCI instruction uncached transactions
+
+    uint32_t m_cost_imiss_transaction;      // cumulated duration for VCI IMISS transactions
+    uint32_t m_cost_dmiss_transaction;      // cumulated duration for VCI DMISS transactions
+    uint32_t m_cost_unc_transaction;        // cumulated duration for VCI UNC transactions
+    uint32_t m_cost_icache_unc_transaction; // cumulated duration for VCI IUNC transactions    
+    uint32_t m_cost_write_transaction;      // cumulated duration for VCI WRITE transactions
+    uint32_t m_length_write_transaction;    // cumulated length for VCI WRITE transactions
+
+    // TLB activity counters
+    uint32_t m_cpt_ins_tlb_read;            // number of instruction tlb read
+    uint32_t m_cpt_ins_tlb_miss;            // number of instruction tlb miss
+    uint32_t m_cpt_ins_tlb_update_acc;      // number of instruction tlb update acc
+    uint32_t m_cpt_data_tlb_read;           // number of data tlb read
+    uint32_t m_cpt_data_tlb_miss;           // number of data tlb miss
+    uint32_t m_cpt_data_tlb_update_acc;     // number of data tlb update acc
+    uint32_t m_cpt_data_tlb_update_dirty;   // number of data tlb update dirty
+    
+    uint32_t m_cost_ins_tlb_miss_frz;       // number of frozen cycles related to instruction tlb miss
+    uint32_t m_cost_data_tlb_miss_frz;      // number of frozen cycles related to data tlb miss
+    uint32_t m_cost_ins_tlb_update_acc_frz;      // number of cycles for instruction tlb flush 
+    uint32_t m_cost_data_tlb_update_acc_frz;     // number of cycles for data tlb flush
+    uint32_t m_cost_data_tlb_update_dirty_frz;    // number of cycles for instruction cache flush 
+
+    uint32_t m_cpt_itlbmiss_transaction;    // number of itlb miss transactions
+    uint32_t m_cpt_itlb_ll_transaction;        // number of itlb ll acc transactions
+    uint32_t m_cpt_itlb_sc_transaction;        // number of itlb sc acc transactions
+    uint32_t m_cpt_dtlbmiss_transaction;    // number of dtlb miss transactions
+    uint32_t m_cpt_dtlb_ll_transaction;        // number of dtlb ll acc transactions
+    uint32_t m_cpt_dtlb_sc_transaction;        // number of dtlb sc acc transactions
+    uint32_t m_cpt_dtlb_ll_dirty_transaction;  // number of dtlb ll dirty transactions
+    uint32_t m_cpt_dtlb_sc_dirty_transaction;  // number of dtlb sc dirty transactions    
+
+    uint32_t m_cost_itlbmiss_transaction;   // cumulated duration for VCI instruction TLB miss transactions
+    uint32_t m_cost_itlb_ll_transaction;      // cumulated duration for VCI instruction TLB ll acc transactions
+    uint32_t m_cost_itlb_sc_transaction;      // cumulated duration for VCI instruction TLB sc acc transactions
+    uint32_t m_cost_dtlbmiss_transaction;   // cumulated duration for VCI data TLB miss transactions
+    uint32_t m_cost_dtlb_ll_transaction;      // cumulated duration for VCI data TLB ll acc transactions
+    uint32_t m_cost_dtlb_sc_transaction;      // cumulated duration for VCI data TLB sc acc transactions
+    uint32_t m_cost_dtlb_ll_dirty_transaction;// cumulated duration for VCI data TLB ll dirty transactions
+    uint32_t m_cost_dtlb_sc_dirty_transaction;// cumulated duration for VCI data TLB sc dirty transactions
+
+    uint32_t m_cpt_cc_cleanup_ins;
+    uint32_t m_cpt_cc_cleanup_data;
+    uint32_t m_cpt_icleanup_transaction;
+    uint32_t m_cpt_dcleanup_transaction;
+    uint32_t m_cost_icleanup_transaction;
+    uint32_t m_cost_dcleanup_transaction;
+
+    uint32_t m_cpt_cc_update_data;              // number of coherence update data packets 
+    uint32_t m_cpt_cc_inval_ins;                // number of coherence inval instruction packets
+    uint32_t m_cpt_cc_inval_data;               // number of coherence inval data packets
+    uint32_t m_cpt_cc_broadcast;                // number of coherence broadcast packets
+
+protected:
+    SC_HAS_PROCESS(VciCcVCacheWrapperV1);
+
+public:
+    VciCcVCacheWrapperV1(
+        sc_module_name insname,
+        int proc_id,
+        const soclib::common::MappingTable &mtp,
+        const soclib::common::MappingTable &mtc,
+        const soclib::common::IntTab &initiator_index_rw,
+        const soclib::common::IntTab &initiator_index_c,
+        const soclib::common::IntTab &target_index,
+        size_t itlb_ways,
+        size_t itlb_sets,
+        size_t dtlb_ways,
+        size_t dtlb_sets,
+        size_t icache_ways,
+        size_t icache_sets,
+        size_t icache_words,
+        size_t dcache_ways,
+        size_t dcache_sets,
+        size_t dcache_words,
+        size_t write_buf_size );
+
+    ~VciCcVCacheWrapperV1();
+
+    void print_cpi();
+    void print_stats();
+
+private:
+    void transition();
+    void genMoore();
+
+    soclib_static_assert((int)iss_t::SC_ATOMIC == (int)vci_param::STORE_COND_ATOMIC);
+    soclib_static_assert((int)iss_t::SC_NOT_ATOMIC == (int)vci_param::STORE_COND_NOT_ATOMIC);
+};
+
+}}
+
+#endif /* SOCLIB_CABA_VCI_CC_VCACHE_WRAPPER_V1_H */
+
+// Local Variables:
+// tab-width: 4
+// c-basic-offset: 4
+// c-file-offsets:((innamespace . 0)(inline-open . 0))
+// indent-tabs-mode: nil
+// End:
+
+// vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4
+
Index: branches/v4/modules/vci_cc_vcache_wrapper_v1/caba/source/src/vci_cc_vcache_wrapper_v1.cpp
===================================================================
--- branches/v4/modules/vci_cc_vcache_wrapper_v1/caba/source/src/vci_cc_vcache_wrapper_v1.cpp	(revision 371)
+++ branches/v4/modules/vci_cc_vcache_wrapper_v1/caba/source/src/vci_cc_vcache_wrapper_v1.cpp	(revision 371)
@@ -0,0 +1,5290 @@
+/* -*- c++ -*-
+ * File : vci_cc_vcache_wrapper_v1.cpp
+ * Copyright (c) UPMC, Lip6, SoC
+ * Authors : Alain GREINER, Yang GAO
+ *
+ * SOCLIB_LGPL_HEADER_BEGIN
+ * 
+ * This file is part of SoCLib, GNU LGPLv2.1.
+ * 
+ * SoCLib is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU Lesser General Public License as published
+ * by the Free Software Foundation; version 2.1 of the License.
+ * 
+ * SoCLib is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * Lesser General Public License for more details.
+ * 
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with SoCLib; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301 USA
+ * 
+ * SOCLIB_LGPL_HEADER_END
+ */
+
+#include <cassert>
+#include "arithmetics.h"
+#include "../include/vci_cc_vcache_wrapper_v1.h"
+
+namespace soclib { 
+namespace caba {
+
+//#define SOCLIB_MODULE_DEBUG
+#ifdef SOCLIB_MODULE_DEBUG
+namespace {
+const char *icache_fsm_state_str[] = {
+        "ICACHE_IDLE",
+        "ICACHE_BIS",       
+        "ICACHE_TLB1_READ",  
+        "ICACHE_TLB1_LL_WAIT",        
+        "ICACHE_TLB1_SC_WAIT",     
+        "ICACHE_TLB1_UPDT_SEL",  
+        "ICACHE_TLB1_UPDT",  
+        "ICACHE_TLB2_READ",  
+        "ICACHE_TLB2_LL_WAIT",        
+        "ICACHE_TLB2_SC_WAIT",     
+        "ICACHE_TLB2_UPDT_SEL",  
+        "ICACHE_TLB2_UPDT",  
+        "ICACHE_TLB_FLUSH", 
+        "ICACHE_CACHE_FLUSH", 
+        "ICACHE_TLB_INVAL",  
+        "ICACHE_CACHE_INVAL",
+	    "ICACHE_CACHE_INVAL_PA",
+        "ICACHE_MISS_WAIT",
+        "ICACHE_UNC_WAIT",  
+        "ICACHE_MISS_UPDT",  
+        "ICACHE_ERROR", 
+        "ICACHE_CC_INVAL",
+        "ICACHE_TLB_CC_INVAL",
+    };
+const char *dcache_fsm_state_str[] = {
+        "DCACHE_IDLE",       
+        "DCACHE_BIS",     
+        "DCACHE_TLB1_READ",  
+        "DCACHE_TLB1_LL_WAIT",
+        "DCACHE_TLB1_SC_WAIT",
+        "DCACHE_TLB1_UPDT_SEL",  
+        "DCACHE_TLB1_UPDT",  
+        "DCACHE_TLB2_READ",  
+        "DCACHE_TLB2_LL_WAIT",
+        "DCACHE_TLB2_SC_WAIT", 
+        "DCACHE_TLB2_UPDT_SEL",   
+        "DCACHE_TLB2_UPDT",   
+        "DCACHE_CTXT_SWITCH",   
+        "DCACHE_ICACHE_FLUSH", 
+        "DCACHE_DCACHE_FLUSH", 
+        "DCACHE_ITLB_INVAL",
+        "DCACHE_DTLB_INVAL",
+        "DCACHE_ICACHE_INVAL",
+        "DCACHE_DCACHE_INVAL",
+    	"DCACHE_ICACHE_INVAL_PA",
+	    "DCACHE_DCACHE_INVAL_PA",
+        "DCACHE_DCACHE_SYNC",
+        "DCACHE_LL_DIRTY_WAIT",
+        "DCACHE_SC_DIRTY_WAIT",  
+        "DCACHE_WRITE_UPDT", 
+        "DCACHE_WRITE_DIRTY",
+        "DCACHE_WRITE_REQ",  
+        "DCACHE_MISS_WAIT",  
+        "DCACHE_MISS_UPDT",  
+        "DCACHE_UNC_WAIT",   
+        "DCACHE_ERROR",  
+        "DCACHE_CC_CHECK",
+        "DCACHE_CC_INVAL",
+        "DCACHE_CC_UPDT",
+        "DCACHE_CC_NOP",
+        "DCACHE_TLB_CC_INVAL",
+    };
+const char *cmd_fsm_state_str[] = {
+        "CMD_IDLE",           
+        "CMD_ITLB_READ",      
+        "CMD_ITLB_ACC_LL",
+        "CMD_ITLB_ACC_SC",      
+        "CMD_INS_MISS",     
+        "CMD_INS_UNC",     
+        "CMD_DTLB_READ",  
+        "CMD_DTLB_ACC_LL",
+        "CMD_DTLB_ACC_SC",
+        "CMD_DTLB_DIRTY_LL",
+        "CMD_DTLB_DIRTY_SC",
+        "CMD_DATA_UNC",     
+        "CMD_DATA_MISS",    
+        "CMD_DATA_WRITE",    
+        "CMD_INS_CLEANUP",    
+        "CMD_DATA_CLEANUP",   
+    };
+const char *rsp_fsm_state_str[] = {
+        "RSP_IDLE",                  
+        "RSP_ITLB_READ",             
+        "RSP_ITLB_ACC_LL",
+        "RSP_ITLB_ACC_SC",               
+        "RSP_INS_MISS",   
+        "RSP_INS_UNC",           
+        "RSP_DTLB_READ", 
+        "RSP_DTLB_ACC_LL",
+        "RSP_DTLB_ACC_SC",          
+        "RSP_DTLB_DIRTY_LL",
+        "RSP_DTLB_DIRTY_SC",
+        "RSP_DATA_MISS",             
+        "RSP_DATA_UNC",              
+        "RSP_DATA_WRITE",   
+        "RSP_INS_CLEANUP",    
+        "RSP_DATA_CLEANUP",   
+    };
+const char *tgt_fsm_state_str[] = {
+        "TGT_IDLE",
+        "TGT_UPDT_WORD",
+        "TGT_UPDT_DATA",
+        "TGT_REQ_BROADCAST",
+        "TGT_REQ_ICACHE",
+        "TGT_REQ_DCACHE",
+        "TGT_RSP_BROADCAST",
+        "TGT_RSP_ICACHE",
+        "TGT_RSP_DCACHE",
+    };	
+const char *inval_itlb_fsm_state_str[] = {
+        "INVAL_ITLB_IDLE",        
+        "INVAL_ITLB_CHECK"  , 
+        "INVAL_ITLB_INVAL",      
+        "INVAL_ITLB_CLEAR",           
+    };
+const char *inval_dtlb_fsm_state_str[] = {
+        "INVAL_DTLB_IDLE",        
+        "INVAL_DTLB_CHECK", 
+        "INVAL_DTLB_INVAL",    
+        "INVAL_DTLB_CLEAR",         
+    };
+}
+#endif
+
+#define tmpl(...)  template<typename vci_param, typename iss_t> __VA_ARGS__ VciCcVCacheWrapperV1<vci_param, iss_t>
+
+using soclib::common::uint32_log2;
+
+/***********************************************/
+tmpl(/**/)::VciCcVCacheWrapperV1(
+    sc_module_name name,
+    int proc_id,
+    const soclib::common::MappingTable &mtp,
+    const soclib::common::MappingTable &mtc,
+    const soclib::common::IntTab &initiator_index_rw,
+    const soclib::common::IntTab &initiator_index_c,
+    const soclib::common::IntTab &target_index,
+    size_t itlb_ways,
+    size_t itlb_sets,
+    size_t dtlb_ways,
+    size_t dtlb_sets,
+    size_t icache_ways,
+    size_t icache_sets,
+    size_t icache_words,
+    size_t dcache_ways,
+    size_t dcache_sets,
+    size_t dcache_words,
+    size_t write_buf_size )
+/***********************************************/
+    : soclib::caba::BaseModule(name),
+
+      p_clk("clk"),
+      p_resetn("resetn"),
+      p_vci_ini_rw("vci_ini_rw"),
+      p_vci_ini_c("vci_ini_c"),
+      p_vci_tgt("vci_tgt"),
+
+      m_cacheability_table(mtp.getCacheabilityTable()),
+      m_segment(mtc.getSegment(target_index)),
+      m_iss(this->name(), proc_id),
+      m_srcid_rw(mtp.indexForId(initiator_index_rw)),
+      m_srcid_c(mtp.indexForId(initiator_index_c)),
+
+      m_itlb_ways(itlb_ways),
+      m_itlb_sets(itlb_sets),
+
+      m_dtlb_ways(dtlb_ways),
+      m_dtlb_sets(dtlb_sets),
+
+      m_icache_ways(icache_ways),
+      m_icache_sets(icache_sets),
+      m_icache_yzmask((~0)<<(uint32_log2(icache_words) + 2)),
+      m_icache_words(icache_words),
+
+      m_dcache_ways(dcache_ways),
+      m_dcache_sets(dcache_sets),
+      m_dcache_yzmask((~0)<<(uint32_log2(dcache_words) + 2)),
+      m_dcache_words(dcache_words),
+
+      m_write_buf_size(write_buf_size),	
+      m_paddr_nbits(vci_param::N),
+
+      icache_tlb(itlb_ways,itlb_sets,vci_param::N),
+      dcache_tlb(dtlb_ways,dtlb_sets,vci_param::N),
+
+      r_dcache_fsm("r_dcache_fsm"),
+      r_dcache_paddr_save("r_dcache_paddr_save"),
+      r_dcache_wdata_save("r_dcache_wdata_save"),
+      r_dcache_rdata_save("r_dcache_rdata_save"),
+      r_dcache_type_save("r_dcache_type_save"),
+      r_dcache_be_save("r_dcache_be_save"),
+      r_dcache_cached_save("r_dcache_cached_save"),
+      r_dcache_tlb_paddr("r_dcache_tlb_paddr"),
+      r_dcache_miss_req("r_dcache_miss_req"),
+      r_dcache_unc_req("r_dcache_unc_req"),
+      r_dcache_write_req("r_dcache_write_req"),
+      r_dcache_tlb_read_req("r_dcache_tlb_read_req"),
+      r_dcache_tlb_ll_acc_req("r_dcache_tlb_ll_acc_req"),
+      r_dcache_tlb_sc_acc_req("r_dcache_tlb_sc_acc_req"),
+      r_dcache_tlb_ll_dirty_req("r_dcache_tlb_ll_dirty_req"),
+      r_dcache_tlb_sc_dirty_req("r_dcache_tlb_sc_dirty_req"),
+      r_dcache_tlb_ptba_read("r_dcache_tlb_ptba_read"),
+      r_dcache_xtn_req("r_dcache_xtn_req"),
+
+      r_icache_fsm("r_icache_fsm"),
+      r_icache_paddr_save("r_icache_paddr_save"),
+      r_icache_miss_req("r_icache_miss_req"),
+      r_icache_unc_req("r_icache_unc_req"),
+      r_icache_tlb_read_req("r_icache_tlb_read_req"),
+      r_icache_tlb_ll_req("r_icache_tlb_ll_req"),
+      r_icache_tlb_sc_req("r_icache_tlb_sc_req"),
+
+      r_vci_cmd_fsm("r_vci_cmd_fsm"),
+      r_vci_cmd_min("r_vci_cmd_min"),
+      r_vci_cmd_max("r_vci_cmd_max"),
+      r_vci_cmd_cpt("r_vci_cmd_cpt"),
+
+      r_vci_rsp_fsm("r_vci_rsp_fsm"),
+      r_vci_rsp_cpt("r_vci_rsp_cpt"),
+      r_vci_rsp_ins_error("r_vci_rsp_ins_error"),
+      r_vci_rsp_data_error("r_vci_rsp_data_error"),
+
+      r_vci_tgt_fsm("r_vci_tgt_fsm"),
+      r_tgt_addr("r_tgt_addr"),
+      r_tgt_word("r_tgt_word"),
+      r_tgt_update("r_tgt_update"),
+      r_tgt_broadcast("r_tgt_broadcast"),
+      r_tgt_srcid("r_tgt_srcid"),
+      r_tgt_pktid("r_tgt_pktid"),
+      r_tgt_trdid("r_tgt_trdid"),
+      r_tgt_icache_req("r_tgt_icache_req"),
+      r_tgt_dcache_req("r_tgt_dcache_req"),
+
+      r_wbuf("wbuf", write_buf_size ),
+      r_icache("icache", icache_ways, icache_sets, icache_words),
+      r_dcache("dcache", dcache_ways, dcache_sets, dcache_words)
+{
+    r_icache_miss_buf = new data_t[icache_words];
+    r_dcache_miss_buf = new data_t[dcache_words];
+    r_tgt_buf         = new data_t[dcache_words];
+    r_tgt_val         = new bool[dcache_words];
+
+    SC_METHOD(transition);
+    dont_initialize();
+    sensitive << p_clk.pos();
+  
+    SC_METHOD(genMoore);
+    dont_initialize();
+    sensitive << p_clk.neg();
+
+    typename iss_t::CacheInfo cache_info;
+    cache_info.has_mmu = true;
+    cache_info.icache_line_size = icache_words*sizeof(data_t);
+    cache_info.icache_assoc = icache_ways;
+    cache_info.icache_n_lines = icache_sets;
+    cache_info.dcache_line_size = dcache_words*sizeof(data_t);
+    cache_info.dcache_assoc = dcache_ways;
+    cache_info.dcache_n_lines = dcache_sets;
+    m_iss.setCacheInfo(cache_info);
+}
+
+/////////////////////////////////////
+tmpl(/**/)::~VciCcVCacheWrapperV1()
+/////////////////////////////////////
+{
+    delete [] r_icache_miss_buf;
+    delete [] r_dcache_miss_buf;
+    delete [] r_tgt_val;
+    delete [] r_tgt_buf;
+}
+
+////////////////////////
+tmpl(void)::print_cpi()
+////////////////////////
+{
+    std::cout << name() << " CPI = " 
+        << (float)m_cpt_total_cycles/(m_cpt_total_cycles - m_cpt_frz_cycles) << std::endl ;
+}
+
+////////////////////////
+tmpl(void)::print_stats()
+////////////////////////
+{
+    float run_cycles = (float)(m_cpt_total_cycles - m_cpt_frz_cycles);
+    std::cout << name() << std::endl
+              << "- CPI                    = " << (float)m_cpt_total_cycles/run_cycles << std::endl 
+              << "- READ RATE              = " << (float)m_cpt_read/run_cycles << std::endl 
+              << "- WRITE RATE             = " << (float)m_cpt_write/run_cycles << std::endl
+              << "- IMISS_RATE             = " << (float)m_cpt_ins_miss/m_cpt_ins_read << std::endl    
+              << "- DMISS RATE             = " << (float)m_cpt_data_miss/(m_cpt_read-m_cpt_unc_read) << std::endl 
+              << "- INS MISS COST          = " << (float)m_cost_ins_miss_frz/m_cpt_ins_miss << std::endl
+              << "- DATA MISS COST             = " << (float)m_cost_data_miss_frz/m_cpt_data_miss << std::endl
+              << "- WRITE COST             = " << (float)m_cost_write_frz/m_cpt_write << std::endl
+              << "- UNC COST               = " << (float)m_cost_unc_read_frz/m_cpt_unc_read << std::endl
+              << "- UNCACHED READ RATE     = " << (float)m_cpt_unc_read/m_cpt_read << std::endl 
+              << "- CACHED WRITE RATE      = " << (float)m_cpt_write_cached/m_cpt_write << std::endl
+              << "- INS TLB MISS RATE      = " << (float)m_cpt_ins_tlb_miss/m_cpt_ins_tlb_read << std::endl
+              << "- DATA TLB MISS RATE     = " << (float)m_cpt_data_tlb_miss/m_cpt_data_tlb_read << std::endl
+              << "- ITLB MISS COST         = " << (float)m_cost_ins_tlb_miss_frz/m_cpt_ins_tlb_miss << std::endl
+              << "- DTLB MISS COST         = " << (float)m_cost_data_tlb_miss_frz/m_cpt_data_tlb_miss << std::endl      
+              << "- ITLB UPDATE ACC COST   = " << (float)m_cost_ins_tlb_update_acc_frz/m_cpt_ins_tlb_update_acc << std::endl
+              << "- DTLB UPDATE ACC COST   = " << (float)m_cost_data_tlb_update_acc_frz/m_cpt_data_tlb_update_acc << std::endl
+              << "- DTLB UPDATE DIRTY COST = " << (float)m_cost_data_tlb_update_dirty_frz/m_cpt_data_tlb_update_dirty << std::endl 
+              << "- NB CC BROADCAST        = " << m_cpt_cc_broadcast << std::endl
+              << "- NB CC UPDATE DATA      = " << m_cpt_cc_update_data << std::endl
+              << "- NB CC INVAL DATA       = " << m_cpt_cc_inval_data << std::endl
+              << "- NB CC INVAL INS        = " << m_cpt_cc_inval_ins << std::endl
+              << "- NB CC CLEANUP DATA     = " << m_cpt_cc_cleanup_data << std::endl
+              << "- NB CC CLEANUP INS      = " << m_cpt_cc_cleanup_ins << std::endl
+              << "- ITLB MISS TRANSACTION  = " << (float)m_cost_itlbmiss_transaction/m_cpt_itlbmiss_transaction << std::endl
+              << "- DTLB MISS TRANSACTION  = " << (float)m_cost_dtlbmiss_transaction/m_cpt_dtlbmiss_transaction << std::endl;
+}
+
+/*************************************************/
+tmpl(void)::transition()
+/*************************************************/
+{
+    if ( ! p_resetn.read() ) 
+    {
+        m_iss.reset();
+
+        r_dcache_fsm = DCACHE_IDLE;
+        r_icache_fsm = ICACHE_IDLE;
+        r_vci_cmd_fsm = CMD_IDLE;
+        r_vci_rsp_fsm = RSP_IDLE;
+        r_vci_tgt_fsm = TGT_IDLE;
+        r_inval_itlb_fsm = INVAL_ITLB_IDLE;          
+        r_inval_dtlb_fsm = INVAL_DTLB_IDLE;     
+
+        // write buffer & caches
+        r_wbuf.reset();
+        r_icache.reset();
+        r_dcache.reset();
+
+        icache_tlb.reset();    
+        dcache_tlb.reset();    
+
+        //r_mmu_mode = ALL_DEACTIVE;
+        r_mmu_mode = 0x3;
+        r_mmu_params = (uint32_log2(m_dtlb_ways) << 29)   | (uint32_log2(m_dtlb_sets) << 25)   |
+                       (uint32_log2(m_dcache_ways) << 22) | (uint32_log2(m_dcache_sets) << 18) |
+                       (uint32_log2(m_itlb_ways) << 15)   | (uint32_log2(m_itlb_sets) << 11)   |
+                       (uint32_log2(m_icache_ways) << 8)  | (uint32_log2(m_icache_sets) << 4)  |
+                       (uint32_log2(m_icache_words * 4));
+        r_mmu_release = (uint32_t)(1 << 16) | 0x1;
+
+        r_icache_miss_req          = false;
+        r_icache_unc_req           = false;
+        r_icache_tlb_read_req      = false;
+        r_icache_tlb_first_req     = false;
+        r_icache_tlb_ll_req        = false;
+        r_icache_tlb_sc_req        = false;
+        r_icache_tlb_sc_fail       = false;
+
+        r_dcache_miss_req          = false;
+        r_dcache_unc_req           = false;
+        r_dcache_write_req         = false;
+        r_dcache_tlb_read_req      = false;
+        r_dcache_tlb_first_req     = false;
+        r_dcache_tlb_ll_acc_req    = false;
+        r_dcache_tlb_sc_acc_req    = false;
+        r_dcache_tlb_ll_dirty_req  = false;
+        r_dcache_tlb_sc_dirty_req  = false;
+        r_dcache_sc_updt_dirty     = false;	
+        r_dcache_tlb_sc_fail       = false;
+        r_dcache_tlb_ptba_read     = false;
+        r_dcache_xtn_req           = false;
+
+        r_dcache_dirty_save      = false;
+        r_dcache_hit_p_save      = false;
+        r_dcache_cached_save      = false;
+
+        r_icache_buf_unc_valid   = false;
+        r_dcache_buf_unc_valid   = false;
+
+        r_vci_rsp_ins_error      = false;
+        r_vci_rsp_data_error     = false;
+
+        r_icache_id1_save        = 0;
+        r_icache_ppn_save        = 0;
+        r_icache_vpn_save        = 0;
+        r_itlb_translation_valid = false;
+
+        r_dcache_id1_save        = 0;
+        r_dcache_ppn_save        = 0;
+        r_dcache_vpn_save        = 0;
+        r_dtlb_translation_valid = false;
+
+        r_icache_ptba_ok         = false;
+        r_dcache_ptba_ok         = false;
+
+        r_icache_error_type      = MMU_NONE;
+        r_dcache_error_type      = MMU_NONE;
+
+        r_icache_cleanup_req       = false;
+        r_icache_cleanup_type      = NONE;
+    
+        r_dcache_cleanup_req       = false;
+        r_dcache_cleanup_type      = NONE; 
+ 
+        r_tgt_icache_req           = false;
+        r_tgt_dcache_req           = false;
+        r_tgt_icache_rsp           = false;
+        r_tgt_dcache_rsp           = false;
+        r_ccinval_itlb_cpt         = 0; 
+        r_ccinval_dtlb_cpt         = 0; 
+
+        r_icache_cc_hit_t          = false;
+        r_dcache_cc_hit_t          = false;
+
+        r_tgt_broadcast            = false;
+        r_tgt_update               = false; 
+ 
+        r_icache_inval_rsp         = false;
+        r_dcache_inval_rsp         = false;
+
+        r_icache_tlb_inval_req     = false;    
+        r_itlb_cc_check_end        = false;
+        r_icache_inval_tlb_rsp     = false;
+        
+        r_dcache_tlb_inval_req     = false;    
+        r_dtlb_cc_check_end        = false;
+        r_dcache_inval_tlb_rsp     = false;
+
+        // activity counters
+        m_cpt_dcache_data_read  = 0;
+        m_cpt_dcache_data_write = 0;
+        m_cpt_dcache_dir_read   = 0;
+        m_cpt_dcache_dir_write  = 0;
+        m_cpt_icache_data_read  = 0;
+        m_cpt_icache_data_write = 0;
+        m_cpt_icache_dir_read   = 0;
+        m_cpt_icache_dir_write  = 0;
+
+	    m_cpt_frz_cycles   = 0;
+        m_cpt_total_cycles = 0;
+
+        m_cpt_read         = 0;
+        m_cpt_write        = 0;
+        m_cpt_data_miss    = 0;
+        m_cpt_ins_miss     = 0;
+        m_cpt_unc_read     = 0;
+        m_cpt_write_cached = 0;
+        m_cpt_ins_read     = 0;  
+
+        m_cost_write_frz     = 0;
+        m_cost_data_miss_frz = 0;
+        m_cost_unc_read_frz  = 0;
+        m_cost_ins_miss_frz  = 0;
+
+        m_cpt_imiss_transaction      = 0;
+        m_cpt_dmiss_transaction      = 0;
+        m_cpt_unc_transaction        = 0;
+        m_cpt_write_transaction      = 0; 
+        m_cpt_icache_unc_transaction = 0;
+
+        m_cost_imiss_transaction      = 0;
+        m_cost_dmiss_transaction      = 0;
+        m_cost_unc_transaction        = 0;
+        m_cost_write_transaction      = 0;
+        m_cost_icache_unc_transaction = 0;
+        m_length_write_transaction    = 0;
+
+        m_cpt_ins_tlb_read         = 0;             
+        m_cpt_ins_tlb_miss         = 0;             
+        m_cpt_ins_tlb_update_acc   = 0;         
+
+        m_cpt_data_tlb_read         = 0;           
+        m_cpt_data_tlb_miss         = 0;           
+        m_cpt_data_tlb_update_acc   = 0;       
+        m_cpt_data_tlb_update_dirty = 0;    
+
+        m_cost_ins_tlb_miss_frz          = 0;      
+        m_cost_data_tlb_miss_frz         = 0;      
+        m_cost_ins_tlb_update_acc_frz    = 0;
+        m_cost_data_tlb_update_acc_frz   = 0;
+        m_cost_data_tlb_update_dirty_frz = 0; 
+
+        m_cpt_itlbmiss_transaction      = 0;    
+        m_cpt_itlb_ll_transaction       = 0;  
+        m_cpt_itlb_sc_transaction       = 0;  
+        m_cpt_dtlbmiss_transaction      = 0;  
+        m_cpt_dtlb_ll_transaction       = 0;  
+        m_cpt_dtlb_sc_transaction       = 0;  
+        m_cpt_dtlb_ll_dirty_transaction = 0;  
+        m_cpt_dtlb_sc_dirty_transaction = 0;  
+ 
+        m_cost_itlbmiss_transaction      = 0;   
+        m_cost_itlb_ll_transaction       = 0;  
+        m_cost_itlb_sc_transaction       = 0;  
+        m_cost_dtlbmiss_transaction      = 0;   
+        m_cost_dtlb_ll_transaction       = 0;   
+        m_cost_dtlb_sc_transaction       = 0;   
+        m_cost_dtlb_ll_dirty_transaction = 0;   
+        m_cost_dtlb_sc_dirty_transaction = 0;   
+
+        m_cpt_cc_cleanup_ins        = 0;
+        m_cpt_cc_cleanup_data       = 0;
+        m_cpt_icleanup_transaction  = 0;
+        m_cpt_dcleanup_transaction  = 0;
+        m_cost_icleanup_transaction = 0;
+        m_cost_dcleanup_transaction = 0;
+
+        m_cpt_cc_update_data = 0;                
+        m_cpt_cc_inval_ins   = 0;               
+        m_cpt_cc_inval_data  = 0;               
+        m_cpt_cc_broadcast   = 0; 
+        return;
+    }
+
+#ifdef SOCLIB_MODULE_DEBUG
+std::cout << name() << "cycle = " << m_cpt_total_cycles  
+          << " tgt fsm: " << tgt_fsm_state_str[r_vci_tgt_fsm]
+          << " dcache fsm: " << dcache_fsm_state_str[r_dcache_fsm]
+          << " icache fsm: " << icache_fsm_state_str[r_icache_fsm]
+          << " cmd fsm: " << cmd_fsm_state_str[r_vci_cmd_fsm]
+          << " rsp fsm: " << rsp_fsm_state_str[r_vci_rsp_fsm] 
+          << " itlb inval fsm: " << inval_itlb_fsm_state_str[r_inval_itlb_fsm]
+          << " dtlb inval fsm: " << inval_dtlb_fsm_state_str[r_inval_dtlb_fsm] << std::endl;
+#endif
+
+    m_cpt_total_cycles++;
+
+    typename iss_t::InstructionRequest ireq = ISS_IREQ_INITIALIZER;
+    typename iss_t::InstructionResponse irsp = ISS_IRSP_INITIALIZER;
+
+    typename iss_t::DataRequest dreq = ISS_DREQ_INITIALIZER;
+    typename iss_t::DataResponse drsp = ISS_DRSP_INITIALIZER;
+
+    m_iss.getRequests( ireq, dreq );
+
+#ifdef SOCLIB_MODULE_DEBUG
+    std::cout << name() << " Instruction Request: " << ireq << std::endl;
+    std::cout << name() << " Data Request: " << dreq << std::endl;
+#endif
+
+    /////////////////////////////////////////////////////////////////////
+    // The TGT_FSM controls the following ressources:
+    // - r_vci_tgt_fsm
+    // - r_tgt_buf[nwords]
+    // - r_tgt_val[nwords]
+    // - r_tgt_update
+    // - r_tgt_word
+    // - r_tgt_addr
+    // - r_tgt_srcid
+    // - r_tgt_trdid
+    // - r_tgt_pktid
+    // All VCI commands must be CMD_WRITE.
+    // If the VCI address offset is null, the command is an invalidate 
+    // request. It is an update request otherwise.
+    // The VCI_TGT FSM stores the external request arguments in the
+    // IDLE, UPDT_WORD & UPDT_DATA states. It sets the r_tgt_icache_req 
+    // & r_tgt_dcache_req flip-flops to signal the external request to 
+    // the ICACHE & DCACHE FSMs in the REQ state. It waits the completion
+    // of the update or invalidate request in the RSP state.
+    // -  for an invalidate request the VCI packet length is 1 word.
+    // The WDATA field contains the line index (i.e. the Z & Y fields).
+    // -  for an update request the VCI packet length is (n+2) words.
+    // The WDATA field of the first VCI word contains the line number.
+    // The WDATA field of the second VCI word contains the word index.
+    // The WDATA field of the n following words contains the values.
+    // -  for both invalidate & update requests, the VCI response
+    // is one single word.
+    // In case of errors in the VCI command packet, the simulation
+    // is stopped with an error message.
+    /////////////////////////////////////////////////////////////////////
+    
+    switch(r_vci_tgt_fsm) {
+    //////////////
+    case TGT_IDLE:
+    {
+        if ( p_vci_tgt.cmdval.read() ) 
+        {
+            paddr_t address = p_vci_tgt.address.read();
+
+            if ( p_vci_tgt.cmd.read() != vci_param::CMD_WRITE) 
+            {
+                std::cout << "error in component VCI_CC_VCACHE_WRAPPER " << name() << std::endl;
+                std::cout << "the received VCI command is not a write" << std::endl;
+                exit(0);
+            }
+
+            // multi-update or multi-invalidate for data type
+            if ( ( (address&0x3) != 0x3 ) && ( ! m_segment.contains(address)) ) 
+            {
+                std::cout << "error in component VCI_CC_VCACHE_WRAPPER " << name() << std::endl;
+                std::cout << "out of segment VCI command received for a multi-updt or multi-inval request" << std::endl;
+                exit(0);
+            }
+
+            r_tgt_srcid = p_vci_tgt.srcid.read();
+            r_tgt_trdid = p_vci_tgt.trdid.read();
+            r_tgt_pktid = p_vci_tgt.pktid.read();
+            r_tgt_plen  = p_vci_tgt.plen.read(); 
+            r_tgt_addr  = (paddr_t)(p_vci_tgt.be.read() & 0x3) << 32 |
+			  (paddr_t)p_vci_tgt.wdata.read() * m_dcache_words * 4; 
+
+            if ( (address&0x3) == 0x3 ) // broadcast invalidate for data or instruction type
+            {
+                if ( ! p_vci_tgt.eop.read() ) 
+                {
+                    std::cout << "error in component VCI_CC_VCACHE_WRAPPER " << name() << std::endl;
+                    std::cout << "the BROADCAST INVALIDATE command length must be one word" << std::endl;
+                    exit(0);
+                }
+                r_tgt_update = false; 
+                r_tgt_broadcast = true; 
+                r_vci_tgt_fsm = TGT_REQ_BROADCAST;
+                m_cpt_cc_broadcast++;
+            }
+            else                // multi-update or multi-invalidate for data type
+            {
+                r_tgt_broadcast = false; 
+                paddr_t cell = address - m_segment.baseAddress();   
+
+                if (cell == 0)                      // invalidate   
+                {                         
+                    if ( ! p_vci_tgt.eop.read() ) 
+                    {
+                        std::cout << "error in component VCI_CC_VCACHE_WRAPPER " << name() << std::endl;
+                        std::cout << "the MULTI-INVALIDATE command length must be one word" << std::endl;
+                        exit(0);
+                    }
+                    r_tgt_update = false; 
+                    r_vci_tgt_fsm = TGT_REQ_DCACHE;
+                    m_cpt_cc_inval_data++ ;
+                }
+                else if (cell == 4)                // update 
+                {                                
+                    if ( p_vci_tgt.eop.read() ) 
+                    {
+                        std::cout << "error in component VCI_CC_VCACHE_WRAPPER " << name() << std::endl;
+                        std::cout << "the MULTI-UPDATE command length must be N+2 words" << std::endl;
+                        exit(0);
+                    }
+                    r_tgt_update = true; 
+                    r_vci_tgt_fsm = TGT_UPDT_WORD;
+                    m_cpt_cc_update_data++ ;
+                }     
+		        else if (cell == 8)
+		        {
+                    if ( ! p_vci_tgt.eop.read() ) 
+                    {
+                        std::cout << "error in component VCI_CC_VCACHE_WRAPPER " << name() << std::endl;
+                        std::cout << "the MULTI-INVALIDATE command length must be one word" << std::endl;
+                        exit(0);
+                    }
+                    r_tgt_update = false; 
+                    r_vci_tgt_fsm = TGT_REQ_ICACHE;
+                    m_cpt_cc_inval_ins++ ;
+		        }
+            } // end if address    
+        } // end if cmdval
+        break;
+    }
+    ///////////////////
+    case TGT_UPDT_WORD:
+    {
+        if (p_vci_tgt.cmdval.read()) 
+        {
+            if ( p_vci_tgt.eop.read() ) 
+            {
+                std::cout << "error in component VCI_CC_VCACHE_WRAPPER " << name() << std::endl;
+                std::cout << "the MULTI-UPDATE command length must be N+2 words" << std::endl;
+                exit(0);
+            }
+            for ( size_t i=0 ; i<m_dcache_words ; i++ ) r_tgt_val[i] = false;
+            r_tgt_word = p_vci_tgt.wdata.read(); // the first modified word index
+            r_vci_tgt_fsm = TGT_UPDT_DATA;
+        }
+        break;
+    }
+    ///////////////////
+    case TGT_UPDT_DATA:
+    {
+        if (p_vci_tgt.cmdval.read()) 
+        {
+            size_t word = r_tgt_word.read();
+            if (word >= m_dcache_words) 
+            {
+                std::cout << "error in component VCI_CC_VCACHE_WRAPPER " << name() << std::endl;
+                std::cout << "the reveived MULTI-UPDATE command length is wrong" << std::endl;
+                exit(0);
+            }
+            r_tgt_buf[word] = p_vci_tgt.wdata.read();
+            if(p_vci_tgt.be.read())    r_tgt_val[word] = true;
+            r_tgt_word = word + 1;
+            if (p_vci_tgt.eop.read())  r_vci_tgt_fsm = TGT_REQ_DCACHE;
+        }
+        break;
+    }
+    ////////////////////////
+    case TGT_REQ_BROADCAST:
+    {
+        if ( !r_tgt_icache_req.read() && !r_tgt_dcache_req.read() ) 
+        {
+            r_vci_tgt_fsm = TGT_RSP_BROADCAST; 
+            r_tgt_icache_req = true;
+            r_tgt_dcache_req = true;
+        }
+        break;
+    }
+    /////////////////////
+    case TGT_REQ_ICACHE:
+    {
+        if ( !r_tgt_icache_req.read() ) 
+        {
+            r_vci_tgt_fsm = TGT_RSP_ICACHE; 
+            r_tgt_icache_req = true;
+        }
+        break;
+    }
+    /////////////////////
+    case TGT_REQ_DCACHE:
+    {
+        if ( !r_tgt_dcache_req.read() ) 
+        {
+            r_vci_tgt_fsm = TGT_RSP_DCACHE; 
+            r_tgt_dcache_req = true;
+        }
+        break;
+    }
+    ///////////////////////
+    case TGT_RSP_BROADCAST:
+    {
+        // no response
+        if ( !r_tgt_icache_rsp.read() && !r_tgt_dcache_rsp.read() 
+          && !r_ccinval_itlb_cpt.read() && !r_ccinval_dtlb_cpt.read() 
+          && !r_tgt_icache_req.read() && !r_tgt_dcache_req.read() )
+        {
+            r_vci_tgt_fsm = TGT_IDLE;
+            break;
+        }
+
+        if ( p_vci_tgt.rspack.read() && !r_tgt_icache_req.read() && !r_tgt_dcache_req.read() ) 
+        {
+            if ( r_tgt_icache_rsp )
+            {
+                r_tgt_icache_rsp = false;
+                break;
+            }
+            if ( r_tgt_dcache_rsp )
+            {
+                r_tgt_dcache_rsp = false;
+                break;
+            }
+            if ( r_ccinval_itlb_cpt )
+            {
+                r_ccinval_itlb_cpt = r_ccinval_itlb_cpt - 1;
+                break;
+            }
+            if ( r_ccinval_dtlb_cpt )
+            {
+                r_ccinval_dtlb_cpt = r_ccinval_dtlb_cpt - 1;
+                break;
+            }
+        }        
+        break;
+    }
+    /////////////////////
+    case TGT_RSP_ICACHE:
+    {
+	    if ( (p_vci_tgt.rspack.read() || !r_tgt_icache_rsp.read()) && !r_tgt_icache_req.read() ) 
+        {
+            r_vci_tgt_fsm = TGT_IDLE;
+            r_tgt_icache_rsp = false; 
+        }
+        break;
+    }
+    /////////////////////
+    case TGT_RSP_DCACHE:
+    {
+	    if ( (p_vci_tgt.rspack.read() || !r_tgt_dcache_rsp.read()) && !r_tgt_dcache_req.read() )
+        {
+            r_vci_tgt_fsm = TGT_IDLE;
+            r_tgt_dcache_rsp = false; 
+        }
+        break;
+    }
+    } // end switch TGT_FSM
+
+    ////////////////////////////////////////////////////////////////////////////////////////
+    //      ICACHE_FSM
+    //
+    // There is 9 mutually exclusive conditions to exit the IDLE state.
+    // Four configurations corresponding to an XTN request from processor,
+    // - Flush TLB (in case of Context switch) => TLB_FLUSH state 
+    // - Flush cache => CACHE_FLUSH state 
+    // - Invalidate a TLB entry => TLB_INVAL state
+    // - Invalidate a cache line => CACHE_INVAL state
+    // Five configurations corresponding to various TLB or cache MISS :
+    // - TLB miss(in case hit_p miss) => TLB1_READ state
+    // - TLB miss(in case hit_p hit) => TLB2_READ state
+    // - Hit in TLB but VPN changed => BIS state
+    // - Cached read miss => MISS_REQ state
+    // - Uncache read miss => UNC_REQ state
+    // 
+    // In case of MISS, the controller writes a request in the r_icache_paddr_save register 
+    // and sets the corresponding request flip-flop : r_icache_tlb_read_req, r_icache_miss_req 
+    // or r_icache_unc_req. These request flip-flops are reset by the VCI_RSP controller 
+    // when the response is ready in the ICACHE buffer.
+    //
+    // The DCACHE FSM signals XTN processor requests using the r_dcache_xtn_req flip-flop. 
+    // The request opcod and the address to be invalidated are transmitted
+    // in the r_dcache_paddr_save & r_dcache_wdata_save registers respectively.
+    // The request flip-flop is reset by the ICACHE_FSM when the operation is completed.
+    //
+    // The r_vci_rsp_ins_error flip-flop is set by the VCI_RSP FSM and reset
+    // by the ICACHE-FSM in the ICACHE_ERROR state.
+    //
+    //----------------------------------------------------------------------------------- 
+    // Instruction TLB: 
+    //  
+    // - int        ET          (00: unmapped; 01: unused or PTD)
+    //                          (10: PTE new;  11: PTE old      )
+    // - bool       cachable    (cached bit)
+    // - bool       writable    (** not used alwayse false) 
+    // - bool       executable  (executable bit)
+    // - bool       user        (access in user mode allowed)
+    // - bool       global      (PTE not invalidated by a TLB flush)
+    // - bool       dirty       (** not used alwayse false) 
+    // - uint32_t   vpn         (virtual page number)
+    // - uint32_t   ppn         (physical page number)
+    ////////////////////////////////////////////////////////////////////////////////////////
+
+    switch(r_icache_fsm) {
+
+    ////////////////
+    case ICACHE_IDLE:
+    {
+        pte_info_t  icache_pte_info;
+        paddr_t     tlb_ipaddr     = 0;        // physical address obtained from TLB                                
+        paddr_t     spc_ipaddr     = 0;        // physical adress obtained from PPN_save (speculative)                         
+        data_t      icache_ins     = 0;        // read instruction
+        bool        icache_hit_c   = false;    // Cache hit
+        bool        icache_cached  = false;    // cacheable access (read)
+        bool        icache_hit_t   = false;    // hit on 4Kilo TLB
+        bool        icache_hit_x   = false;    // VPN unmodified (can use spc_dpaddr)
+        bool        icache_hit_p   = false;    // PTP unmodified (can skip first level page table walk)
+        size_t      icache_tlb_way = 0;        // selected way (in case of cache hit)
+        size_t      icache_tlb_set = 0;        // selected set (Y field in address)
+        paddr_t     icache_tlb_nline = 0;      // TLB NLINE
+
+        // Decoding processor XTN requests
+        // They are sent by DCACHE FSM  
+
+        if (r_dcache_xtn_req)
+        {
+            if ((int)r_dcache_type_save == (int)iss_t::XTN_PTPR)  
+            {
+                r_icache_way = 0;
+                r_icache_set = 0;
+                r_icache_fsm = ICACHE_TLB_FLUSH;   
+                break;
+            }
+            if ((int)r_dcache_type_save == (int)iss_t::XTN_ICACHE_FLUSH)
+            {
+                r_icache_way = 0;
+                r_icache_set = 0;
+                r_icache_fsm = ICACHE_CACHE_FLUSH;   
+                break;
+            }
+            if ((int)r_dcache_type_save == (int)iss_t::XTN_ITLB_INVAL) 
+            {
+                r_icache_fsm = ICACHE_TLB_INVAL;   
+                break;
+            }
+            if ((int)r_dcache_type_save == (int)iss_t::XTN_ICACHE_INVAL) 
+            {
+                r_icache_fsm = ICACHE_CACHE_INVAL;   
+                break;
+            }
+            if ((int)r_dcache_type_save == (int)iss_t::XTN_MMU_ICACHE_PA_INV) 
+            {
+                r_icache_fsm = ICACHE_CACHE_INVAL_PA;   
+                break;
+            }
+        } // end if xtn_req
+
+        // external request from broadcast
+        if ( r_tgt_icache_req )
+        {
+            r_icache_fsm = ICACHE_CC_INVAL;
+            r_icache_fsm_save = r_icache_fsm;
+            break;
+        }
+
+        // icache_hit_t, icache_hit_x, icache_hit_p 
+        // icache_pte_info, icache_tlb_way, icache_tlb_set & ipaddr & cacheability 
+        // - If MMU activated : cacheability is defined by the cachable bit in the TLB
+        // - If MMU not activated : cacheability is defined by the segment table.
+
+        if ( !(r_mmu_mode.read() & INS_TLB_MASK) )   // MMU not activated 
+        {
+            icache_hit_t  = true;         
+            icache_hit_x  = true;         
+            icache_hit_p  = true;         
+            tlb_ipaddr    = ireq.addr;
+            spc_ipaddr    = ireq.addr;
+            icache_cached = m_cacheability_table[ireq.addr];
+        } 
+        else                                                                // MMU activated
+        { 
+            m_cpt_ins_tlb_read++;
+            icache_hit_t = icache_tlb.cctranslate(ireq.addr, &tlb_ipaddr, &icache_pte_info, 
+                                                  &icache_tlb_nline, &icache_tlb_way, &icache_tlb_set); 
+            icache_hit_x   = (((vaddr_t)r_icache_vpn_save << PAGE_K_NBITS) == (ireq.addr & ~PAGE_K_MASK)) && r_itlb_translation_valid;
+            icache_hit_p   = (((ireq.addr >> PAGE_M_NBITS) == r_icache_id1_save) && r_icache_ptba_ok); 
+            spc_ipaddr     = ((paddr_t)r_icache_ppn_save << PAGE_K_NBITS) | (paddr_t)(ireq.addr & PAGE_K_MASK);
+            icache_cached  = icache_pte_info.c; 
+        }
+
+        if ( !(r_mmu_mode.read() & INS_CACHE_MASK) )   // cache not actived
+        {
+            icache_cached = false;
+        }
+
+        if ( ireq.valid ) 
+        {
+            m_cpt_icache_dir_read += m_icache_ways;
+            m_cpt_icache_data_read += m_icache_ways;
+
+            // icache_hit_c & icache_ins
+            if ( icache_cached )    // using speculative physical address for cached access
+            {
+                icache_hit_c = r_icache.read(spc_ipaddr, &icache_ins);
+            }
+            else                    // using actual physical address for uncached access
+            {
+                icache_hit_c = ( r_icache_buf_unc_valid && (tlb_ipaddr == (paddr_t)r_icache_paddr_save) );
+                icache_ins = r_icache_miss_buf[0];
+            }
+
+            if ( r_mmu_mode.read() & INS_TLB_MASK ) 
+            {
+                if ( icache_hit_t ) 
+                {
+                    // check access rights
+                    if ( !icache_pte_info.u && (ireq.mode == iss_t::MODE_USER)) 
+                    {
+                        r_icache_error_type = MMU_READ_PRIVILEGE_VIOLATION;  
+                        r_icache_bad_vaddr = ireq.addr;
+                        irsp.valid = true;
+                        irsp.error = true;
+                        irsp.instruction = 0;
+                        break;
+                    }
+                    if ( !icache_pte_info.x ) 
+                    {
+                        r_icache_error_type = MMU_READ_EXEC_VIOLATION;  
+                        r_icache_bad_vaddr = ireq.addr;
+                        irsp.valid = true;
+                        irsp.error = true;
+                        irsp.instruction = 0;
+                        break;
+                    }
+                }
+
+                // update LRU, save ppn, vpn and page type
+                if ( icache_hit_t )
+                {  
+                    icache_tlb.setlru(icache_tlb_way,icache_tlb_set);     
+                    r_icache_ppn_save = tlb_ipaddr >> PAGE_K_NBITS;
+                    r_icache_vpn_save = ireq.addr >> PAGE_K_NBITS;
+                    r_icache_tlb_nline = icache_tlb_nline;
+                    r_itlb_translation_valid = true;
+                }
+                else
+                {
+                    r_itlb_translation_valid = false;
+                }
+
+            } // end if MMU activated
+
+            // compute next state 
+            if ( !icache_hit_t && !icache_hit_p )      // TLB miss
+            {
+                // walk page table  level 1
+                r_icache_paddr_save = (paddr_t)r_mmu_ptpr << (INDEX1_NBITS+2) | (paddr_t)((ireq.addr>>PAGE_M_NBITS)<<2);
+                r_icache_tlb_read_req = true;
+                r_icache_tlb_first_req = true;
+                r_icache_vaddr_req = ireq.addr;
+                r_icache_fsm = ICACHE_TLB1_READ;
+                m_cpt_ins_tlb_miss++;
+                m_cost_ins_tlb_miss_frz++;
+            }
+            else if ( !icache_hit_t && icache_hit_p )  // TLB Miss with possibility of bypass first level page
+            {
+                // walk page table level 2
+                r_icache_paddr_save = (paddr_t)r_icache_ptba_save | 
+                                      (paddr_t)(((ireq.addr&PTD_ID2_MASK)>>PAGE_K_NBITS) << 3);
+                r_icache_tlb_read_req = true;
+                r_icache_tlb_first_req = false;
+                r_icache_vaddr_req = ireq.addr;
+                r_icache_fsm = ICACHE_TLB2_READ;
+                m_cpt_ins_tlb_miss++;
+                m_cost_ins_tlb_miss_frz++;
+            }
+            else if ( icache_hit_t && !icache_hit_x && icache_cached ) // cached access with an ucorrect speculative physical address
+            {
+                r_icache_paddr_save = tlb_ipaddr;   // save actual physical address for BIS
+                r_icache_vaddr_req = ireq.addr;
+                r_icache_fsm = ICACHE_BIS;
+                m_cost_ins_tlb_miss_frz++;
+            }
+            else    // cached or uncached access with a correct speculative physical address 
+            {   
+                m_cpt_ins_read++;      
+                if ( !icache_hit_c ) 
+                {
+                    m_cpt_ins_miss++;
+                    m_cost_ins_miss_frz++;
+                    if ( icache_cached ) 
+                    {
+                        r_icache_miss_req = true;
+                        r_icache_paddr_save = spc_ipaddr; 
+                        r_icache_vaddr_req = ireq.addr;
+                        r_icache_fsm = ICACHE_MISS_WAIT;
+                    } 
+                    else 
+                    {
+                        r_icache_unc_req = true;
+                        r_icache_buf_unc_valid = false;
+                        r_icache_paddr_save = tlb_ipaddr;
+                        r_icache_vaddr_req = ireq.addr; 
+                        r_icache_fsm = ICACHE_UNC_WAIT;
+                    } 
+                } 
+                else 
+                {
+                    r_icache_buf_unc_valid = false;
+                    r_icache_fsm = ICACHE_IDLE;
+                }
+                irsp.valid = icache_hit_c;
+                irsp.instruction = icache_ins;
+            } // end if next states
+            
+        } // end if ireq.valid
+        break;
+    }
+    ////////////////
+    case ICACHE_BIS: 
+    {
+        // external cache invalidate request
+        if ( r_tgt_icache_req )
+        {
+            if ( ireq.valid ) m_cost_ins_miss_frz++;
+            r_icache_fsm = ICACHE_CC_INVAL;
+            r_icache_fsm_save = r_icache_fsm;
+            break;
+        }
+
+        // using page is invalidated
+        if ( r_icache_inval_tlb_rsp )
+        {
+            if ( ireq.valid ) m_cost_ins_miss_frz++;
+            r_icache_inval_tlb_rsp = false;
+            r_icache_fsm = ICACHE_IDLE;
+            break;
+        }
+
+        data_t      icache_ins   = 0;
+        bool        icache_hit_c = false;
+        bool        icache_hit_t = false;
+        paddr_t     tlb_ipaddr   = 0;
+
+        // processor address translation
+        icache_hit_t = icache_tlb.translate(ireq.addr, &tlb_ipaddr);
+
+        // test if processor request modified
+        if ( (tlb_ipaddr == r_icache_paddr_save.read()) && ireq.valid && icache_hit_t ) // unmodified & valid
+        {
+            // acces is always cached in this state
+            icache_hit_c = r_icache.read(r_icache_paddr_save, &icache_ins);
+            m_cpt_ins_read++;
+      
+            if ( !icache_hit_c )
+            {
+                r_icache_miss_req = true;
+                r_icache_fsm = ICACHE_MISS_WAIT;
+                m_cpt_ins_miss++;
+            } 
+            else
+            {
+                r_icache_fsm = ICACHE_IDLE; 
+            }
+
+            irsp.valid = icache_hit_c;
+	        if (irsp.valid)
+	            assert((r_icache_vaddr_req.read() == ireq.addr) &&
+		        "vaddress should not be modified while ICACHE_BIS");
+            irsp.error = false;
+            irsp.instruction = icache_ins;
+        }
+        else
+        {
+            irsp.valid = false;
+            irsp.error = false;
+            irsp.instruction = 0;
+            r_icache_fsm = ICACHE_IDLE;
+        }
+        break;
+    }
+    //////////////////////
+    case ICACHE_TLB1_READ:
+    {
+        if ( ireq.valid ) m_cost_ins_tlb_miss_frz++;
+        // external cache invalidate request
+        if ( r_tgt_icache_req )
+        {
+            r_icache_fsm = ICACHE_CC_INVAL;
+            r_icache_fsm_save = r_icache_fsm;
+            break;
+        }
+
+        // cleanup PTD in L2, because it's not keep in L1
+		if ( r_icache_cleanup_req ) break;
+
+        if ( !r_icache_tlb_read_req ) // vci response 
+        {
+	        if (r_icache_vaddr_req.read() != ireq.addr || !ireq.valid) 
+	        {
+	            /* request modified, drop response and restart */
+	            r_icache_ptba_ok = false;
+                if ( r_icache_inval_tlb_rsp )	r_icache_inval_tlb_rsp = false;
+                if ( r_vci_rsp_ins_error )	r_vci_rsp_ins_error = false;
+	            r_icache_fsm = ICACHE_IDLE;
+
+                r_icache_cleanup_req = true;
+                r_icache_cleanup_line = r_icache_paddr_save.read() >> (uint32_log2(m_icache_words) + 2);  
+                r_icache_cleanup_type = TLB_CLEANUP;
+                m_cpt_cc_cleanup_ins++;
+	            break;
+	        }
+
+            if ( !r_icache_inval_tlb_rsp ) // vci response 
+            {  
+                if ( !r_vci_rsp_ins_error ) // vci response ok
+                { 
+                    if ( !(r_icache_miss_buf[0] >> PTE_V_SHIFT) ) // unmapped
+                    {
+                	    r_icache_ptba_ok    = false;	
+                        r_icache_error_type = MMU_READ_PT1_UNMAPPED;  
+                        r_icache_bad_vaddr  = r_icache_vaddr_req.read();
+                        r_icache_fsm        = ICACHE_ERROR;
+
+                        r_icache_cleanup_req = true;
+                        r_icache_cleanup_line = r_icache_paddr_save.read() >> (uint32_log2(m_icache_words) + 2);  
+                        r_icache_cleanup_type = TLB_CLEANUP;
+                        m_cpt_cc_cleanup_ins++;
+                    }
+	                else if ( (r_icache_miss_buf[0] & PTE_T_MASK ) >> PTE_T_SHIFT ) // PTD
+	                {
+                        r_icache_ptba_ok       = true;	
+                        r_icache_ptba_save     = (paddr_t)(r_icache_miss_buf[0] & ((1<<(m_paddr_nbits - PAGE_K_NBITS))-1)) << PAGE_K_NBITS; 
+                        r_icache_id1_save      = r_icache_vaddr_req.read() >> PAGE_M_NBITS;
+                        r_icache_paddr_save    = (paddr_t)(r_icache_miss_buf[0] & ((1<<(m_paddr_nbits - PAGE_K_NBITS))-1)) << PAGE_K_NBITS |
+                                                 (paddr_t)(((r_icache_vaddr_req.read() & PTD_ID2_MASK) >> PAGE_K_NBITS) << 3); 
+                        r_icache_tlb_read_req  = true;
+                        r_icache_tlb_first_req = false;
+                        r_icache_fsm           = ICACHE_TLB2_READ;
+
+                        // cleanup PTD in L2, because it's not keep in L1
+                        r_icache_cleanup_req = true;
+                        r_icache_cleanup_line = r_icache_paddr_save.read() >> (uint32_log2(m_icache_words) + 2);  
+                        r_icache_cleanup_type = TLB_CLEANUP;
+                        m_cpt_cc_cleanup_ins++;
+	                }	
+	                else        // PTE
+	                {
+                        r_icache_ptba_ok = false;
+	                
+	                    if ( (m_srcid_rw >> 4) == ((r_icache_miss_buf[0] & ((1<<(m_paddr_nbits - PAGE_M_NBITS))-1)) >> (m_paddr_nbits - PAGE_M_NBITS -10)) ) // local
+	                    {
+	                        if ( (r_icache_miss_buf[0] & PTE_L_MASK ) >> PTE_L_SHIFT ) // L bit is set
+	                        {
+                                r_icache_pte_update = r_icache_miss_buf[0];
+                                r_icache_fsm        = ICACHE_TLB1_UPDT_SEL;
+	                        }
+	                        else
+	                        {
+                                r_icache_pte_update = r_icache_miss_buf[0] | PTE_L_MASK;
+                                r_icache_tlb_ll_req = true;
+                                r_icache_fsm        = ICACHE_TLB1_LL_WAIT;
+                                m_cpt_ins_tlb_update_acc++;
+                                m_cost_ins_tlb_update_acc_frz++;
+	                        }
+                        }
+	                    else // remotely
+	                    {
+	                        if ( (r_icache_miss_buf[0] & PTE_R_MASK ) >> PTE_R_SHIFT ) // R bit is set
+	                        {
+                                r_icache_pte_update = r_icache_miss_buf[0];
+                                r_icache_fsm        = ICACHE_TLB1_UPDT_SEL;
+	                        }
+	                        else
+	                        {
+                                r_icache_pte_update = r_icache_miss_buf[0] | PTE_R_MASK;
+                                r_icache_tlb_ll_req = true;
+                                r_icache_fsm        = ICACHE_TLB1_LL_WAIT;
+                                m_cpt_ins_tlb_update_acc++;
+                                m_cost_ins_tlb_update_acc_frz++;
+	                        }
+	                    }
+	                }
+                }
+                else        // vci response error
+                {
+                    r_icache_fsm = ICACHE_ERROR;
+                    r_icache_error_type = MMU_READ_PT1_ILLEGAL_ACCESS;    
+                    r_icache_bad_vaddr = ireq.addr;
+                }
+            }
+
+            if ( r_icache_inval_tlb_rsp ) // TLB miss read response and invalidation
+            {
+                if ( r_vci_rsp_ins_error ) 
+                {
+                    r_icache_inval_tlb_rsp = false;
+                    r_icache_error_type = MMU_READ_PT1_UNMAPPED;    
+                    r_icache_bad_vaddr = r_icache_vaddr_req.read();
+                    r_icache_fsm = ICACHE_ERROR;
+                } 
+                else 
+                {
+                    r_icache_inval_tlb_rsp = false;
+                    r_icache_cleanup_req = true;
+                    r_icache_cleanup_line = r_icache_paddr_save.read() >> (uint32_log2(m_icache_words) + 2);  
+                    r_icache_cleanup_type = TLB_CLEANUP;
+                    m_cpt_cc_cleanup_ins++;
+                    r_icache_fsm = ICACHE_IDLE;  
+                } 
+            }
+        }
+        break;
+    }
+    ///////////////////////
+    case ICACHE_TLB1_LL_WAIT:
+    {
+        if ( ireq.valid ) m_cost_ins_tlb_miss_frz++;
+        m_cost_ins_tlb_update_acc_frz++;            
+
+        // external cache invalidate request
+        if ( r_tgt_icache_req )
+        {
+            r_icache_fsm = ICACHE_CC_INVAL;
+            r_icache_fsm_save = r_icache_fsm;
+            break;
+        }
+
+	    if ( !r_icache_tlb_ll_req )
+	    {
+            if ( r_vci_rsp_ins_error ) // VCI response ko
+            {
+                r_icache_error_type = MMU_READ_PT1_ILLEGAL_ACCESS;    
+                r_icache_bad_vaddr = ireq.addr;
+                r_icache_fsm = ICACHE_ERROR;
+
+		        if (r_icache_inval_tlb_rsp) r_icache_inval_tlb_rsp = false;
+            }
+	        else
+	        {
+	            if ( !(r_icache_miss_buf[0] >> PTE_V_SHIFT) )	// unmapped
+	            {
+                    r_icache_error_type = MMU_READ_PT1_UNMAPPED;       
+                    r_icache_bad_vaddr  = ireq.addr;
+                    r_icache_fsm        = ICACHE_ERROR;
+
+		            if (r_icache_inval_tlb_rsp) r_icache_inval_tlb_rsp = false;
+	            }
+                else if ( r_icache_inval_tlb_rsp )
+                {
+       		        r_icache_inval_tlb_rsp = false;
+       		        r_icache_fsm = ICACHE_IDLE;
+                }
+		        else
+		        {
+		            r_icache_tlb_sc_req = true;
+                    r_icache_pte_update = r_icache_miss_buf[0] | r_icache_pte_update.read();
+                    r_icache_fsm        = ICACHE_TLB1_SC_WAIT; 
+		        }
+	        }
+	    }
+	    break;
+    }
+    ///////////////////////
+    case ICACHE_TLB1_SC_WAIT:
+    {
+       if ( ireq.valid ) m_cost_ins_tlb_miss_frz++;
+        m_cost_ins_tlb_update_acc_frz++;
+
+        // external cache invalidate request
+        if ( r_tgt_icache_req )
+        {
+            r_icache_fsm = ICACHE_CC_INVAL;
+            r_icache_fsm_save = r_icache_fsm;
+            break;
+        }
+
+        if ( !r_icache_tlb_sc_req ) // VCI response ko
+        {
+            if ( r_vci_rsp_ins_error ) // VCI response ko
+	        {
+                r_icache_error_type = MMU_READ_PT1_ILLEGAL_ACCESS;    
+                r_icache_bad_vaddr  = ireq.addr; 
+                r_icache_fsm        = ICACHE_ERROR;
+
+		        if (r_icache_inval_tlb_rsp) r_icache_inval_tlb_rsp = false;
+	        }
+            else
+            {
+                if ( r_icache_inval_tlb_rsp )
+                {
+       		        r_icache_inval_tlb_rsp = false;
+                    if (r_icache_tlb_sc_fail) r_icache_tlb_sc_fail = false;
+       		        r_icache_fsm = ICACHE_IDLE;
+                }
+	            else if ( r_icache_tlb_sc_fail )
+	            {
+                    r_icache_tlb_ll_req = true;
+                    r_icache_tlb_sc_fail = false;
+	                r_icache_fsm = ICACHE_TLB1_LL_WAIT; 
+	            }
+	            else 
+	            {
+	                r_icache_fsm = ICACHE_TLB1_UPDT_SEL; 
+	            }
+            }
+        }
+	    break;
+    }
+    //////////////////////////
+    case ICACHE_TLB1_UPDT_SEL:
+    {
+        if ( ireq.valid ) m_cost_ins_tlb_miss_frz++;
+
+        // external cache invalidate request
+        if ( r_tgt_icache_req )
+        {
+            r_icache_fsm = ICACHE_CC_INVAL;
+            r_icache_fsm_save = r_icache_fsm;
+            break;
+        }
+
+        // TLB update and invalidate same PTE
+        if ( r_icache_inval_tlb_rsp )                                 
+        {
+            r_icache_inval_tlb_rsp = false;
+            r_icache_fsm = ICACHE_IDLE;
+        }
+
+        // TLB update and invalidate different PTE
+        if ( !r_icache_cleanup_req )
+        {
+            size_t way = 0;
+            size_t set = 0;
+            paddr_t victim_index = 0;
+
+            bool cleanup = icache_tlb.select1((r_icache_vaddr_req.read()>> PAGE_M_NBITS),&victim_index,&way,&set);
+            r_icache_way = way;
+            r_icache_set = set;
+            if (cleanup)
+            {
+                r_icache_cleanup_req = true;
+                r_icache_cleanup_line = victim_index;
+                r_icache_cleanup_type = TLB_CLEANUP; 
+                m_cpt_cc_cleanup_ins++;
+            }
+            r_icache_fsm = ICACHE_TLB1_UPDT;
+        }
+        break;
+    }
+    /////////////////////
+    case ICACHE_TLB1_UPDT:
+    {
+        if ( ireq.valid ) m_cost_ins_tlb_miss_frz++;
+
+	    icache_tlb.update(r_icache_pte_update,r_icache_vaddr_req.read(),r_icache_way.read(),r_icache_set.read(),(r_icache_paddr_save.read() >> (uint32_log2(m_dcache_words)+2)));
+        r_icache_fsm = ICACHE_IDLE;
+        break;
+    }
+    /////////////////////
+    case ICACHE_TLB2_READ:
+    {
+        if ( ireq.valid ) m_cost_ins_tlb_miss_frz++;
+
+        // external cache invalidate request
+        if ( r_tgt_icache_req )
+        {
+            r_icache_fsm = ICACHE_CC_INVAL;
+            r_icache_fsm_save = r_icache_fsm;
+            break;
+        }
+
+        if ( !r_icache_tlb_read_req ) // vci response 
+        {
+	        if (r_icache_vaddr_req.read() != ireq.addr || !ireq.valid) 
+	        {
+	            /* request modified, drop response and restart */
+	            r_icache_ptba_ok = false;
+                if ( r_icache_inval_tlb_rsp )	r_icache_inval_tlb_rsp = false;
+                if ( r_vci_rsp_ins_error )	r_vci_rsp_ins_error = false;
+	            r_icache_fsm = ICACHE_IDLE;
+
+                r_icache_cleanup_req = true;
+                r_icache_cleanup_line = r_icache_paddr_save.read() >> (uint32_log2(m_icache_words) + 2);  
+                r_icache_cleanup_type = TLB_CLEANUP;
+                m_cpt_cc_cleanup_ins++;
+	            break;
+	        }
+
+            if ( !r_icache_inval_tlb_rsp ) // vci response 
+            {
+                if ( !r_vci_rsp_ins_error ) // VCI response ok        
+                {
+	                if ( !(r_icache_miss_buf[0] >> PTE_V_SHIFT) ) // unmapped
+	                {
+                        r_icache_error_type = MMU_READ_PT2_UNMAPPED;  
+                        r_icache_bad_vaddr  = r_icache_vaddr_req.read();
+                        r_icache_fsm = ICACHE_ERROR;
+
+                        r_icache_cleanup_req = true;
+                        r_icache_cleanup_line = r_icache_paddr_save.read() >> (uint32_log2(m_icache_words) + 2);  
+                        r_icache_cleanup_type = TLB_CLEANUP;
+                        m_cpt_cc_cleanup_ins++;
+	                }
+	                else
+	                {
+	                    if ( (m_srcid_rw >> 4) == ((r_icache_miss_buf[0] & ((1<<(m_paddr_nbits - PAGE_M_NBITS))-1)) >> (m_paddr_nbits - PAGE_M_NBITS -10)) ) // local
+	                    {
+	                        if ( (r_icache_miss_buf[0] & PTE_L_MASK ) >> PTE_L_SHIFT ) // L bit is set
+	                        {
+                                r_icache_fsm        = ICACHE_TLB2_UPDT_SEL;
+                                r_icache_pte_update = r_icache_miss_buf[0];
+	                        }
+	                        else
+	                        {
+                                r_icache_pte_update = r_icache_miss_buf[0] | PTE_L_MASK;
+                                r_icache_tlb_ll_req = true;
+                                r_icache_fsm        = ICACHE_TLB2_LL_WAIT;
+                                m_cpt_ins_tlb_update_acc++;
+                                m_cost_ins_tlb_update_acc_frz++;
+	                        }
+                        }
+	                    else // remotely
+	                    {
+	                        if ( (r_icache_miss_buf[0] & PTE_R_MASK ) >> PTE_R_SHIFT ) // R bit is set
+	                        {
+                                r_icache_fsm        = ICACHE_TLB2_UPDT_SEL;
+                                r_icache_pte_update = r_icache_miss_buf[0];
+	                        }
+	                        else
+	                        {
+                                r_icache_pte_update = r_icache_miss_buf[0] | PTE_R_MASK;
+                                r_icache_tlb_ll_req = true;
+                                r_icache_fsm        = ICACHE_TLB2_LL_WAIT;
+                                m_cpt_ins_tlb_update_acc++;
+                                m_cost_ins_tlb_update_acc_frz++;
+	                        }
+	                    }
+	                }
+                }
+                else    // VCI response error
+                {
+                    r_icache_error_type = MMU_READ_PT2_ILLEGAL_ACCESS;
+                    r_icache_bad_vaddr = ireq.addr;
+                    r_icache_fsm = ICACHE_ERROR;
+                }
+            }
+
+            if ( r_icache_inval_tlb_rsp ) // TLB miss read response and invalidation
+            {
+                if ( r_vci_rsp_ins_error ) 
+                {
+                    r_icache_inval_tlb_rsp = false;
+                    r_icache_error_type = MMU_READ_PT2_UNMAPPED;    
+                    r_icache_bad_vaddr = ireq.addr;
+                    r_icache_fsm = ICACHE_ERROR;
+                } 
+                else 
+                {
+                    if (r_icache_cleanup_req) break;
+                    r_icache_inval_tlb_rsp = false;
+                    r_icache_cleanup_req = true;
+                    r_icache_cleanup_line = r_icache_paddr_save.read() >> (uint32_log2(m_icache_words) + 2);  
+                    r_icache_cleanup_type = TLB_CLEANUP;
+                    m_cpt_cc_cleanup_ins++;
+                    r_icache_fsm = ICACHE_IDLE;  
+                } 
+            }
+        }
+        break;
+    }
+    ///////////////////////
+    case ICACHE_TLB2_LL_WAIT:
+    {
+        if ( ireq.valid ) m_cost_ins_tlb_miss_frz++;
+        m_cost_ins_tlb_update_acc_frz++;
+
+        // external cache invalidate request
+        if ( r_tgt_icache_req )
+        {
+            r_icache_fsm = ICACHE_CC_INVAL;
+            r_icache_fsm_save = r_icache_fsm;
+            break;
+        }
+
+	    if ( !r_icache_tlb_ll_req )
+	    {
+            if ( r_vci_rsp_ins_error ) // VCI response ko
+            {
+                r_icache_error_type = MMU_READ_PT2_ILLEGAL_ACCESS;    
+                r_icache_bad_vaddr = ireq.addr;
+                r_icache_fsm = ICACHE_ERROR;
+
+                if (r_icache_inval_tlb_rsp) r_icache_inval_tlb_rsp = false;
+            }
+	        else
+	        {
+	            if ( !(r_icache_miss_buf[0] >> PTE_V_SHIFT) )	// unmapped
+	            {
+                    r_icache_error_type = MMU_READ_PT2_UNMAPPED;       
+                    r_icache_bad_vaddr  = ireq.addr;
+                    r_icache_fsm        = ICACHE_ERROR;
+
+                    if (r_icache_inval_tlb_rsp) r_icache_inval_tlb_rsp = false;
+	            }
+                else if ( r_icache_inval_tlb_rsp )
+                {
+       		        r_icache_inval_tlb_rsp = false;
+       		        r_icache_fsm = ICACHE_IDLE;
+                }
+		        else
+		        {
+		            r_icache_tlb_sc_req = true;
+                    r_icache_pte_update = r_icache_miss_buf[0] | r_icache_pte_update.read();
+                    r_icache_fsm        = ICACHE_TLB2_SC_WAIT; 
+		        }
+	        }
+	    }
+	    break;
+    }
+    ///////////////////////
+    case ICACHE_TLB2_SC_WAIT:
+    {
+        if ( ireq.valid ) m_cost_ins_tlb_miss_frz++;
+        m_cost_ins_tlb_update_acc_frz++;
+
+        // external cache invalidate request
+        if ( r_tgt_icache_req )
+        {
+            r_icache_fsm = ICACHE_CC_INVAL;
+            r_icache_fsm_save = r_icache_fsm;
+            break;
+        }
+
+        if ( !r_icache_tlb_sc_req ) // VCI response 
+        {
+            if ( r_vci_rsp_ins_error ) // VCI response ko
+	        {
+                r_icache_error_type = MMU_READ_PT2_ILLEGAL_ACCESS;    
+                r_icache_bad_vaddr  = ireq.addr; 
+                r_icache_fsm        = ICACHE_ERROR;
+
+                if (r_icache_inval_tlb_rsp) r_icache_inval_tlb_rsp = false;
+	        }
+            else
+            {
+                if ( r_icache_inval_tlb_rsp )
+                {
+       		        r_icache_inval_tlb_rsp = false;
+                    if (r_icache_tlb_sc_fail) r_icache_tlb_sc_fail = false;
+       		        r_icache_fsm = ICACHE_IDLE;
+                }
+	            else if ( r_icache_tlb_sc_fail )
+	            {
+                    r_icache_tlb_ll_req = true;
+                    r_icache_tlb_sc_fail = false;
+	                r_icache_fsm = ICACHE_TLB2_LL_WAIT; 
+	            }
+	            else 
+	            {
+	                r_icache_fsm = ICACHE_TLB2_UPDT_SEL; 
+	            }
+            }
+        }
+	    break;
+    }
+    //////////////////////////
+    case ICACHE_TLB2_UPDT_SEL: 
+    {
+        if ( ireq.valid ) m_cost_ins_tlb_miss_frz++;
+
+        // external cache invalidate request
+        if ( r_tgt_icache_req )
+        {
+            r_icache_fsm = ICACHE_CC_INVAL;
+            r_icache_fsm_save = r_icache_fsm;
+            break;
+        }
+
+        // TLB update and invalidate same PTE
+        if ( r_icache_inval_tlb_rsp )                            
+        {
+            r_icache_inval_tlb_rsp = false;
+            r_icache_fsm = ICACHE_IDLE;
+        }
+
+        // TLB update and invalidate different PTE
+        if ( !r_icache_cleanup_req )
+        {
+            size_t way = 0;
+            size_t set = 0;
+            paddr_t victim_index = 0;
+
+            bool cleanup = icache_tlb.select1((r_icache_vaddr_req.read()>> PAGE_K_NBITS),&victim_index,&way,&set);
+            r_icache_way = way;
+            r_icache_set = set;
+            if (cleanup)
+            {
+                r_icache_cleanup_req = true;
+                r_icache_cleanup_line = victim_index;
+                r_icache_cleanup_type = TLB_CLEANUP; 
+                m_cpt_cc_cleanup_ins++;
+            }
+            r_icache_fsm = ICACHE_TLB2_UPDT;
+        }
+
+        break;
+    }
+    /////////////////////
+    case ICACHE_TLB2_UPDT: 
+    {
+        icache_tlb.update(r_icache_pte_update,r_icache_miss_buf[1],r_icache_vaddr_req.read(),r_icache_way.read(),r_icache_set.read(),(r_icache_paddr_save.read() >> (uint32_log2(m_icache_words)+2)));
+        r_icache_fsm = ICACHE_IDLE;
+        break;
+    }
+    /////////////////////////////
+    case ICACHE_TLB_FLUSH:
+    {
+        size_t way = r_icache_way;
+        size_t set = r_icache_set;
+        bool clean = false;
+
+        // 4K page size TLB flush leads to cleanup req to data cache 
+        if ( !r_icache_cleanup_req )    // last cleanup finish
+        {
+            paddr_t victim_index = 0;
+            for ( ; way < m_itlb_ways; way++)
+            {
+                for ( ; set < m_itlb_sets; set++)
+                {
+                    if(icache_tlb.checkcleanup1(way, set, &victim_index))
+                    {
+                        clean = true;
+                        r_icache_cleanup_req = true;
+                        r_icache_cleanup_line = victim_index;
+                        r_icache_cleanup_type = TLB_CLEANUP;
+                        m_cpt_cc_cleanup_ins++;
+                        r_icache_way = way + ((set+1)/m_itlb_sets);
+                        r_icache_set = (set+1) % m_itlb_sets;
+                        break;
+                    }
+                }
+                if (clean) break;
+                set = 0;
+            }
+
+            if (way == m_itlb_ways)
+            {
+                r_dcache_xtn_req = false;
+                r_itlb_translation_valid = false;
+                r_icache_ptba_ok = false;
+                r_icache_fsm = ICACHE_IDLE;
+                break;
+            }
+        }
+        break;
+    }
+    ////////////////////////
+    case ICACHE_CACHE_FLUSH:
+    {
+        // external cache invalidate request
+        if ( r_tgt_icache_req )
+        {
+            r_icache_fsm = ICACHE_CC_INVAL;
+            r_icache_fsm_save = r_icache_fsm;
+            break;
+        }
+
+        size_t way = r_icache_way;
+        size_t set = r_icache_set;
+        bool clean = false;
+
+        // cache flush and send cleanup to external
+        if ( !r_icache_cleanup_req )
+        {
+            paddr_t victim_index = 0;
+            for ( ; way < m_icache_ways; way++ )
+            {    
+                for ( ; set < m_icache_sets; set++ )
+                {    
+                    if ( r_icache.flush(way, set, &victim_index) )
+                    {
+                        clean = true;
+                        r_icache_cleanup_req = true;
+                        r_icache_cleanup_line = victim_index;
+                        r_icache_cleanup_type = CACHE_CLEANUP;
+                        m_cpt_cc_cleanup_ins++;
+                        r_icache_way = way + ((set+1)/m_icache_sets);
+                        r_icache_set = (set+1) % m_icache_sets;
+                        break;
+                    }
+                }
+                if (clean) break;
+                set = 0;
+            }
+            if (way == m_icache_ways)
+            {
+                r_dcache_xtn_req = false;
+                r_icache_fsm = ICACHE_IDLE;
+                break;
+            }
+        }
+        break;
+    }
+    /////////////////////
+    case ICACHE_TLB_INVAL:  
+    {
+        paddr_t victim_index = 0;
+
+        if ( !r_icache_cleanup_req )
+        {
+            r_icache_cleanup_req = icache_tlb.inval1(r_dcache_wdata_save,&victim_index);
+            r_icache_cleanup_type = TLB_CLEANUP;
+            r_icache_cleanup_line = victim_index;
+            m_cpt_cc_cleanup_ins++;
+            r_dcache_xtn_req = false;
+            r_itlb_translation_valid = false;
+            r_icache_ptba_ok = false;
+            r_icache_fsm = ICACHE_IDLE;
+        }
+        break;
+	}
+    ////////////////////////
+    case ICACHE_CACHE_INVAL:
+    {
+        // external cache invalidate request
+        if ( r_tgt_icache_req )
+        {
+            r_icache_fsm = ICACHE_CC_INVAL;
+            r_icache_fsm_save = r_icache_fsm;
+            break;
+        }
+	
+        paddr_t ipaddr = 0;                     
+        bool    icache_hit_t = false;
+
+        if ( !r_icache_cleanup_req )
+        {
+            if ( r_mmu_mode.read() & INS_TLB_MASK ) 
+            {
+                icache_hit_t = icache_tlb.translate(r_dcache_wdata_save, &ipaddr); 
+            } 
+            else 
+            {
+                ipaddr = (paddr_t)r_dcache_wdata_save;
+                icache_hit_t = true;
+            }
+            if ( icache_hit_t )
+            {
+                // invalidate and cleanup if necessary
+                r_icache_cleanup_req = r_icache.inval(ipaddr);
+                r_icache_cleanup_line = ipaddr >> (uint32_log2(m_icache_words) + 2);
+                r_icache_cleanup_type = CACHE_CLEANUP;
+                m_cpt_cc_cleanup_ins++;
+            }
+            r_dcache_xtn_req = false; 
+            r_icache_fsm = ICACHE_IDLE;
+        }
+        break;
+    }
+    ////////////////////////
+    case ICACHE_CACHE_INVAL_PA:
+    {
+        // external cache invalidate request
+        if ( r_tgt_icache_req )
+        {
+            r_icache_fsm = ICACHE_CC_INVAL;
+            r_icache_fsm_save = r_icache_fsm;
+            break;
+        }
+	
+        paddr_t ipaddr = (paddr_t)r_mmu_word_hi.read() << 32 | r_mmu_word_lo.read();
+
+        if ( !r_icache_cleanup_req )
+        {    
+            // invalidate and cleanup if necessary
+            r_icache_cleanup_req = r_icache.inval(ipaddr);
+            r_icache_cleanup_line = ipaddr >> (uint32_log2(m_icache_words) + 2);   
+            r_icache_cleanup_type = CACHE_CLEANUP; 
+            m_cpt_cc_cleanup_ins++;
+            r_dcache_xtn_req = false; 
+            r_icache_fsm = ICACHE_IDLE;
+        }
+        break;
+    }
+    ///////////////////////
+    case ICACHE_MISS_WAIT:
+    {
+        m_cost_ins_miss_frz++;
+
+        // external cache invalidate request
+        if ( r_tgt_icache_req )     
+        {
+            r_icache_fsm = ICACHE_CC_INVAL;
+            r_icache_fsm_save = r_icache_fsm;
+            break;
+        }
+
+        if ( !r_icache_miss_req )
+        {
+            if ( r_vci_rsp_ins_error ) 
+            {
+                r_icache_error_type = MMU_READ_DATA_ILLEGAL_ACCESS; 
+                r_icache_bad_vaddr = ireq.addr;
+                r_icache_fsm = ICACHE_ERROR;
+        
+            	if ( r_icache_inval_tlb_rsp ) r_icache_inval_tlb_rsp = false;
+            	if ( r_icache_inval_rsp ) r_icache_inval_rsp = false;
+        	    break;
+            }
+        
+            if ( r_icache_inval_tlb_rsp ) // Miss read response and tlb invalidation
+            {
+		        if ( r_icache_cleanup_req ) break;
+                r_icache_cleanup_req = true;
+                r_icache_cleanup_line = r_icache_paddr_save.read() >> (uint32_log2(m_icache_words) + 2);  
+                r_icache_cleanup_type = CACHE_CLEANUP; 
+                m_cpt_cc_cleanup_ins++;
+                r_icache_fsm = ICACHE_IDLE;
+                r_icache_inval_tlb_rsp = false;
+                if ( r_icache_inval_rsp ) r_icache_inval_rsp = false;
+                break;
+            }
+        
+            if ( r_icache_inval_rsp ) // Miss read response and tlb invalidation
+            {
+		        if ( r_icache_cleanup_req ) break;
+                r_icache_cleanup_req = true;
+                r_icache_cleanup_line = r_icache_paddr_save.read() >> (uint32_log2(m_icache_words) + 2);  
+                r_icache_cleanup_type = CACHE_CLEANUP; 
+                m_cpt_cc_cleanup_ins++;
+                r_icache_fsm = ICACHE_IDLE;
+                r_icache_inval_rsp = false;
+                break;
+            }
+            r_icache_fsm = ICACHE_MISS_UPDT;  
+        }	
+        break;
+    }
+    ////////////////////
+    case ICACHE_UNC_WAIT:
+    {
+        // external cache invalidate request
+        if ( r_tgt_icache_req ) 
+        {
+            r_icache_fsm = ICACHE_CC_INVAL;
+            r_icache_fsm_save = r_icache_fsm;
+            break;
+        }
+
+        if ( !r_icache_unc_req )
+        {
+            if ( r_vci_rsp_ins_error ) 
+            {
+                r_icache_error_type = MMU_READ_DATA_ILLEGAL_ACCESS;    
+                r_icache_bad_vaddr = ireq.addr;
+                r_icache_fsm = ICACHE_ERROR;
+        
+            	if ( r_icache_inval_tlb_rsp ) r_icache_inval_tlb_rsp = false;
+        	    break;
+            }
+        
+            if ( r_icache_inval_tlb_rsp ) // Miss read response and tlb invalidation
+            {
+                r_icache_inval_tlb_rsp = false;
+                r_icache_fsm = ICACHE_IDLE;
+        	    break;
+            }
+            // Miss read response and no invalidation
+            r_icache_buf_unc_valid = true;
+            r_icache_fsm = ICACHE_IDLE;
+        }	
+        break;
+    }
+    //////////////////////
+    case ICACHE_MISS_UPDT:
+    {
+        if ( ireq.valid ) m_cost_ins_miss_frz++;
+
+        // external cache invalidate request
+        if ( r_tgt_icache_req )   
+        {
+            r_icache_fsm = ICACHE_CC_INVAL;
+            r_icache_fsm_save = r_icache_fsm;
+            break;
+        }
+
+        if ( r_icache_inval_tlb_rsp ) // tlb invalidation
+        {
+            if ( r_icache_cleanup_req ) break;
+            r_icache_cleanup_req = true;
+            r_icache_cleanup_line = r_icache_paddr_save.read() >> (uint32_log2(m_icache_words) + 2);
+            r_icache_cleanup_type = CACHE_CLEANUP;
+            m_cpt_cc_cleanup_ins++;
+            r_icache_inval_tlb_rsp = false;
+            if ( r_icache_inval_rsp ) r_icache_inval_rsp = false;
+            r_icache_fsm = ICACHE_IDLE;
+            break;
+        }
+
+        if ( !r_icache_cleanup_req ) // Miss update and no invalidation
+        {
+            if ( r_icache_inval_rsp )   // invalidation
+            {
+                r_icache_cleanup_req = true;
+                r_icache_cleanup_line = r_icache_paddr_save.read() >> (uint32_log2(m_icache_words) + 2);
+                r_icache_cleanup_type = CACHE_CLEANUP;
+                m_cpt_cc_cleanup_ins++;
+                r_icache_inval_rsp = false;
+                r_icache_fsm = ICACHE_IDLE;
+            }
+            else
+            {
+                data_t* buf = r_icache_miss_buf;
+                paddr_t  victim_index = 0;
+                m_cpt_icache_dir_write++;
+                m_cpt_icache_data_write++;
+
+                r_icache_cleanup_req = r_icache.update(r_icache_paddr_save.read(), buf, &victim_index);
+                r_icache_cleanup_line = victim_index;         
+                r_icache_cleanup_type = CACHE_CLEANUP;         
+                m_cpt_cc_cleanup_ins++;
+                r_icache_fsm = ICACHE_IDLE;
+            }
+        }
+        break;
+    }
+    ///////////////////
+    case ICACHE_ERROR:
+    {
+        r_vci_rsp_ins_error = false;
+        irsp.valid = true;
+        irsp.error = true;
+        irsp.instruction = 0; 
+        r_icache_fsm = ICACHE_IDLE;
+        break;
+    }
+    /////////////////////
+    case ICACHE_CC_INVAL:  
+    {                       
+        m_cpt_icache_dir_read += m_icache_ways;
+
+        /* activity counter */
+        if ( (( r_icache_fsm_save.read() == ICACHE_BIS ) ||( r_icache_fsm_save.read() == ICACHE_MISS_WAIT ) || ( r_icache_fsm_save.read() == ICACHE_MISS_UPDT ) ) && ( ireq.valid ) )        
+        {
+            m_cost_ins_miss_frz++; 
+        }
+        if( (( r_icache_fsm_save.read() == ICACHE_TLB1_READ )   || ( r_icache_fsm_save.read() == ICACHE_TLB2_READ )    ||
+             ( r_icache_fsm_save.read() == ICACHE_TLB1_LL_WAIT )|| ( r_icache_fsm_save.read() == ICACHE_TLB2_LL_WAIT ) ||
+             ( r_icache_fsm_save.read() == ICACHE_TLB1_SC_WAIT )|| ( r_icache_fsm_save.read() == ICACHE_TLB2_SC_WAIT ) || 
+             ( r_icache_fsm_save.read() == ICACHE_TLB1_UPDT )   || ( r_icache_fsm_save.read() == ICACHE_TLB2_UPDT ))   && (ireq.valid) )
+        {
+            m_cost_ins_tlb_miss_frz++;
+        }
+
+        if( (( r_icache_fsm_save.read() == ICACHE_MISS_WAIT ) || ( r_icache_fsm_save.read() == ICACHE_MISS_UPDT ) ) && 
+            ((r_icache_paddr_save.read() & ~((m_icache_words<<2)-1)) == (r_tgt_addr.read() & ~((m_icache_words<<2)-1))) ) 
+        {
+            r_icache_inval_rsp = true;
+            r_tgt_icache_rsp = false; 
+        } 
+        else 
+        {
+            r_tgt_icache_rsp = r_icache.inval(r_tgt_addr.read());
+        }
+
+        if ( r_tgt_broadcast )
+        {
+		    // ins tlb invalidate verification    
+            r_icache_tlb_inval_req = true;
+            r_icache_fsm = ICACHE_TLB_CC_INVAL;
+        }
+        else
+        {
+            r_tgt_icache_req = false;        
+            r_icache_fsm = r_icache_fsm_save;
+        }    
+        break;
+    }
+    /////////////////////////
+    case ICACHE_TLB_CC_INVAL:
+    {
+         /* activity counter */
+        if ( (( r_icache_fsm_save.read() == ICACHE_BIS ) ||( r_icache_fsm_save.read() == ICACHE_MISS_WAIT ) || ( r_icache_fsm_save.read() == ICACHE_MISS_UPDT ) ) && ( ireq.valid ) )        
+        {
+            m_cost_ins_miss_frz++;
+        }   
+
+        if( (( r_icache_fsm_save.read() == ICACHE_TLB1_READ )   || ( r_icache_fsm_save.read() == ICACHE_TLB2_READ )    ||
+             ( r_icache_fsm_save.read() == ICACHE_TLB1_LL_WAIT )|| ( r_icache_fsm_save.read() == ICACHE_TLB2_LL_WAIT ) ||
+             ( r_icache_fsm_save.read() == ICACHE_TLB1_SC_WAIT )|| ( r_icache_fsm_save.read() == ICACHE_TLB2_SC_WAIT ) || 
+             ( r_icache_fsm_save.read() == ICACHE_TLB1_UPDT )   || ( r_icache_fsm_save.read() == ICACHE_TLB2_UPDT ))   && (ireq.valid) )
+        {
+            m_cost_ins_tlb_miss_frz++;
+        }
+
+	    if ( r_icache_tlb_inval_req ) break;
+
+        // invalidate cache
+        if( (( r_icache_fsm_save.read() == ICACHE_TLB1_READ )     || ( r_icache_fsm_save.read() == ICACHE_TLB2_READ )    ||
+             ( r_icache_fsm_save.read() == ICACHE_TLB1_LL_WAIT )  || ( r_icache_fsm_save.read() == ICACHE_TLB2_LL_WAIT ) ||
+             ( r_icache_fsm_save.read() == ICACHE_TLB1_SC_WAIT )  || ( r_icache_fsm_save.read() == ICACHE_TLB2_SC_WAIT ) || 
+             ( r_icache_fsm_save.read() == ICACHE_TLB1_UPDT_SEL ) || ( r_icache_fsm_save.read() == ICACHE_TLB2_UPDT_SEL ))   && 
+            ((r_icache_paddr_save.read() & ~((m_icache_words<<2)-1)) == r_tgt_addr.read()) ) 
+        {
+            r_icache_inval_tlb_rsp = true;
+        } 
+        else if (((r_icache_fsm_save.read() == ICACHE_BIS)||(r_icache_fsm_save.read() == ICACHE_MISS_WAIT) ||
+           /*  (r_icache_fsm_save.read() == ICACHE_UNC_WAIT)|| */(r_icache_fsm_save.read() == ICACHE_MISS_UPDT)) && 
+            (r_icache_tlb_nline.read() == (paddr_t)(r_tgt_addr.read() >> (uint32_log2(m_icache_words)+2))))
+        {
+            r_icache_inval_tlb_rsp = true;
+        }
+
+        if( (/*( r_icache_fsm_save == ICACHE_TLB1_READ )   || ( r_icache_fsm_save == ICACHE_TLB2_READ ) ||*/
+             ( r_icache_fsm_save.read() == ICACHE_TLB1_LL_WAIT )  || ( r_icache_fsm_save.read() == ICACHE_TLB2_LL_WAIT ) ||
+             ( r_icache_fsm_save.read() == ICACHE_TLB1_SC_WAIT )  || ( r_icache_fsm_save.read() == ICACHE_TLB2_SC_WAIT ) || 
+             ( r_icache_fsm_save.read() == ICACHE_TLB1_UPDT_SEL ) || ( r_icache_fsm_save.read() == ICACHE_TLB2_UPDT_SEL ))   && 
+            ((r_icache_paddr_save.read() & ~((m_icache_words<<2)-1)) == r_tgt_addr.read()) ) 
+        {
+            if ( !r_icache_cc_hit_t ) r_ccinval_itlb_cpt = r_ccinval_itlb_cpt + 1;
+        } 
+
+        r_tgt_icache_req = false;
+	    r_itlb_translation_valid = false;
+        r_icache_ptba_ok = false;        
+        r_icache_fsm = r_icache_fsm_save;
+        break;
+    }
+    } // end switch r_icache_fsm
+
+#ifdef SOCLIB_MODULE_DEBUG
+    std::cout << name() << " Instruction Response: " << irsp << std::endl;
+#endif
+
+    ////////////////////////////////////////////////////////////////////////////////////
+    //      INVAL ITLB CHECK FSM 
+    ////////////////////////////////////////////////////////////////////////////////////////
+    switch(r_inval_itlb_fsm) {
+    ///////////////////// 
+    case INVAL_ITLB_IDLE:
+    {
+        if ( r_icache_tlb_inval_req )
+        {
+            paddr_t ipaddr;
+            r_icache_cc_hit_t = icache_tlb.translate(ireq.addr, &ipaddr);
+            r_ccinval_itlb_way = 0; 
+            r_ccinval_itlb_set = 0;
+            r_ccinval_itlb_cpt = 0;
+            r_inval_itlb_fsm = INVAL_ITLB_CHECK;    
+        }   
+        break;
+    }
+    ////////////////////////////
+    case INVAL_ITLB_CHECK:
+    {
+        size_t way = r_ccinval_itlb_way; 
+        size_t set = r_ccinval_itlb_set;
+        bool end = false;  
+      
+        // r_tgt_addr is number of line
+        bool tlb_hit = icache_tlb.cccheck((r_tgt_addr.read() >> (uint32_log2(m_icache_words)+2)),way, set, &way, &set, &end);     
+        if ( tlb_hit )
+        {
+            r_ccinval_itlb_way = way; 
+            r_ccinval_itlb_set = set;
+            r_itlb_cc_check_end = end;
+            r_ccinval_itlb_cpt = r_ccinval_itlb_cpt + 1;
+            r_inval_itlb_fsm = INVAL_ITLB_INVAL;    
+        }        
+        else
+        {
+            r_inval_itlb_fsm = INVAL_ITLB_CLEAR;    
+        }
+        break;
+    }
+    /////////////////////////
+    case INVAL_ITLB_INVAL:
+    {
+        icache_tlb.ccinval(r_ccinval_itlb_way, r_ccinval_itlb_set);
+
+        if ( !r_itlb_cc_check_end )
+        {
+            r_inval_itlb_fsm = INVAL_ITLB_CHECK; 
+        }
+        else
+        {
+            r_inval_itlb_fsm = INVAL_ITLB_CLEAR;    
+        }
+        break;
+    }
+    ////////////////////
+    case INVAL_ITLB_CLEAR:
+    {
+        r_icache_tlb_inval_req = false;
+        r_itlb_cc_check_end = false;
+        r_ccinval_itlb_way = 0; 
+        r_ccinval_itlb_set = 0; 
+        r_inval_itlb_fsm = INVAL_ITLB_IDLE;    
+        break;
+    }
+    } // end switch r_inval_itlb_fsm
+
+    ////////////////////////////////////////////////////////////////////////////////////
+    //      DCACHE FSM 
+    //
+    // Both the Cacheability Table, and the MMU cached bit are used to define
+    // the cacheability.
+    // 
+    // There is 14 mutually exclusive conditions to exit the IDLE state.
+    // Seven configurations corresponding to an XTN request from processor:
+    // - Context switch => CTXT_SWITCH state
+    // - Flush dcache => DCACHE_FLUSH state 
+    // - Flush icache => ICACHE_FLUSH state 
+    // - Invalidate a dtlb entry => DTLB_INVAL state
+    // - Invalidate a itlb entry => ITLB_INVAL state
+    // - Invalidate a dcache line => DCACHE_INVAL state
+    // - Invalidate a icache line => ICACHE_INVAL state
+    // Seven configurations corresponding to various read miss or write requests: 
+    // - TLB miss(in case hit_p miss) => TLB1_READ state
+    // - TLB miss(in case hit_p hit) => TLB2_READ state
+    // - Hit in TLB but VPN changed => BIS state
+    // - Cached read miss => MISS_REQ state
+    // - Uncache read miss => UNC_REQ state
+    // - Write hit => WRITE_UPDT state
+    // - Write miss => WRITE_REQ
+    //
+    // The r_vci_rsp_data_error flip-flop is set by the VCI_RSP controller and reset 
+    // by DCACHE-FSM when its state is in DCACHE_ERROR. 
+    //--------------------------------------------------------------------- 
+    // Data TLB: 
+    //  
+    // - int        ET          (00: unmapped; 01: unused or PTD)
+    //                          (10: PTE new;  11: PTE old      )
+    // - bool       cachable    (cached bit)
+    // - bool       writable    (writable bit) 
+    // - bool       executable  (** not used alwayse false)
+    // - bool       user        (access in user mode allowed)
+    // - bool       global      (PTE not invalidated by a TLB flush)
+    // - bool       dirty       (page has been modified) 
+    // - uint32_t   vpn         (virtual page number)
+    // - uint32_t   ppn         (physical page number)
+    ////////////////////////////////////////////////////////////////////////////////////////
+
+    switch (r_dcache_fsm) {
+
+    //////////////////////
+    case DCACHE_WRITE_REQ:
+    {
+        if ( r_tgt_dcache_req ) // external request
+        {
+            r_dcache_fsm = DCACHE_CC_CHECK;
+            r_dcache_fsm_save = r_dcache_fsm;
+            break;
+        }
+
+        // try to post the write request in the write buffer
+        if ( !r_dcache_write_req )     // no previous write transaction     
+        {
+            if ( r_wbuf.wok(r_dcache_paddr_save) )   // write request in the same cache line 
+            {    
+                r_wbuf.write(r_dcache_paddr_save.read(), r_dcache_be_save.read(), r_dcache_wdata_save);
+                // closing the write packet if uncached
+                if ( !r_dcache_cached_save )
+                { 
+                    r_dcache_write_req = true;
+                }
+            } 
+            else 
+            {    // close the write packet if write request not in the same cache line
+                r_dcache_write_req = true;
+                m_cost_write_frz++;
+                break;  //  posting not possible : stay in DCACHE_WRITEREQ state
+            }
+        } 
+        else     //  previous write transaction not completed
+        {
+            m_cost_write_frz++;
+            break;  //  posting not possible : stay in DCACHE_WRITEREQ state
+        }
+
+        // close the write packet if the next processor request is not a write 
+        if ( !dreq.valid || (dreq.type != iss_t::DATA_WRITE)) 
+        {
+            r_dcache_write_req = true;
+        }
+        
+        // The next state and the processor request parameters are computed 
+        // as in the DCACHE_IDLE state (see below ...)
+    }
+    /////////////////
+    case DCACHE_IDLE:
+    {
+        // external cache invalidate request
+        if ( r_tgt_dcache_req )   
+        {
+            r_dcache_fsm = DCACHE_CC_CHECK;
+            r_dcache_fsm_save = DCACHE_IDLE;
+            break;
+        }        
+
+        if (dreq.valid) 
+        {
+            pte_info_t  dcache_pte_info;
+            int         xtn_opcod      = (int)dreq.addr/4;
+            paddr_t     tlb_dpaddr     = 0;        // physical address obtained from TLB
+            paddr_t     spc_dpaddr     = 0;        // physical adress obtained from PPN_save (speculative)
+            bool        dcache_hit_t   = false;    // hit on 4Kilo TLB
+            bool        dcache_hit_x   = false;    // VPN unmodified (can use spc_dpaddr)
+            bool        dcache_hit_p   = false;    // PTP unmodified (can skip first level page table walk)
+            bool        dcache_hit_c   = false;    // Cache hit
+            size_t      dcache_tlb_way = 0;        // selected way (in case of cache hit)
+            size_t      dcache_tlb_set = 0;        // selected set (Y field in address)
+            data_t      dcache_rdata   = 0;        // read data
+            bool        dcache_cached  = false;    // cacheable access (read or write)
+            paddr_t     dcache_tlb_nline = 0;       // TLB NLINE
+
+            m_cpt_dcache_data_read += m_dcache_ways;
+            m_cpt_dcache_dir_read += m_dcache_ways;
+
+            // Decoding READ XTN requests from processor
+            // They are executed in this DCACHE_IDLE state
+
+            if (dreq.type == iss_t::XTN_READ) 
+            {
+                switch(xtn_opcod) {
+                case iss_t::XTN_INS_ERROR_TYPE:
+                    drsp.rdata = (uint32_t)r_icache_error_type;
+                    r_icache_error_type = MMU_NONE;
+                    drsp.valid = true;
+                    drsp.error = false;
+                    break;
+                case iss_t::XTN_DATA_ERROR_TYPE:
+                    drsp.rdata = (uint32_t)r_dcache_error_type;
+                    r_dcache_error_type = MMU_NONE;
+                    drsp.valid = true;
+                    drsp.error = false;
+                    break;
+                case iss_t::XTN_INS_BAD_VADDR:
+                    drsp.rdata = (uint32_t)r_icache_bad_vaddr;       
+                    drsp.valid = true;
+                    drsp.error = false;
+                    break;
+                case iss_t::XTN_DATA_BAD_VADDR:
+                    drsp.rdata = (uint32_t)r_dcache_bad_vaddr;        
+                    drsp.valid = true;
+                    drsp.error = false;
+                    break;
+                case iss_t::XTN_PTPR:
+                    drsp.rdata = (uint32_t)r_mmu_ptpr;
+                    drsp.valid = true;
+                    drsp.error = false;
+                    break;
+                case iss_t::XTN_TLB_MODE:
+                    drsp.rdata = (uint32_t)r_mmu_mode;
+                    drsp.valid = true;
+                    drsp.error = false;
+                    break;
+                case iss_t::XTN_MMU_PARAMS:
+                    drsp.rdata = (uint32_t)r_mmu_params;
+                    drsp.valid = true;
+                    drsp.error = false;
+                    break;
+                case iss_t::XTN_MMU_RELEASE:
+                    drsp.rdata = (uint32_t)r_mmu_release;
+                    drsp.valid = true;
+                    drsp.error = false;
+                    break;
+                case iss_t::XTN_MMU_WORD_LO:
+                    drsp.rdata = (uint32_t)r_mmu_word_lo;
+                    drsp.valid = true;
+                    drsp.error = false;
+                    break;
+                case iss_t::XTN_MMU_WORD_HI:
+                    drsp.rdata = (uint32_t)r_mmu_word_hi;
+                    drsp.valid = true;
+                    drsp.error = false;
+                    break;
+                default:
+                    r_dcache_error_type = MMU_READ_UNDEFINED_XTN; 
+                    r_dcache_bad_vaddr  = dreq.addr;
+                    drsp.valid = true;
+                    drsp.error = true;
+                    break;
+                }
+                r_dcache_fsm = DCACHE_IDLE;
+                break;
+            }
+
+            // Decoding WRITE XTN requests from processor
+            // If there is no privilege violation, they are not executed in this DCACHE_IDLE state,
+            // but in the next state, because they generally require access to the caches or the TLBs 
+
+            if (dreq.type == iss_t::XTN_WRITE) 
+            {
+                drsp.valid = false;
+                drsp.error = false;
+                drsp.rdata = 0;
+                r_dcache_wdata_save = dreq.wdata;   
+                switch(xtn_opcod) {     
+
+                case iss_t::XTN_PTPR:       // context switch : checking the kernel mode
+                                            // both instruction & data TLBs must be flushed
+                    if ((dreq.mode == iss_t::MODE_HYPER) || (dreq.mode == iss_t::MODE_KERNEL)) 
+                    {
+                        r_mmu_ptpr = dreq.wdata;
+                        r_icache_error_type = MMU_NONE;
+                        r_dcache_error_type = MMU_NONE;
+                        r_dcache_type_save = dreq.addr/4; 
+                        r_dcache_xtn_req = true;
+                        r_dcache_fsm = DCACHE_CTXT_SWITCH;
+                    } 
+                    else 
+                    { 
+                        r_dcache_error_type = MMU_WRITE_PRIVILEGE_VIOLATION; 
+                        r_dcache_bad_vaddr  = dreq.addr;
+                        drsp.valid = true;
+                        drsp.error = true;
+                        r_dcache_fsm = DCACHE_IDLE;
+                    }
+                    break;
+
+                case iss_t::XTN_TLB_MODE:     // modifying TLBs mode : checking the kernel mode
+                    if ((dreq.mode == iss_t::MODE_HYPER) || (dreq.mode == iss_t::MODE_KERNEL)) 
+                    {
+                        r_mmu_mode = (int)dreq.wdata;
+                        drsp.valid = true;
+                    } 
+                    else 
+                    {
+                        r_dcache_error_type = MMU_WRITE_PRIVILEGE_VIOLATION; 
+                        r_dcache_bad_vaddr  = dreq.addr;
+                        drsp.valid = true;
+                        drsp.error = true;
+                    }
+                    r_dcache_fsm = DCACHE_IDLE;
+                    break;
+
+                case iss_t::XTN_DTLB_INVAL:     //  checking the kernel mode
+                    if ((dreq.mode == iss_t::MODE_HYPER) || (dreq.mode == iss_t::MODE_KERNEL)) 
+                    {
+                        r_dcache_fsm = DCACHE_DTLB_INVAL;  
+                    } 
+                    else 
+                    {
+                        r_dcache_error_type = MMU_WRITE_PRIVILEGE_VIOLATION; 
+                        r_dcache_bad_vaddr  = dreq.addr;
+                        drsp.valid = true;
+                        drsp.error = true;
+                        r_dcache_fsm = DCACHE_IDLE;
+                    }
+                    break;
+
+                case iss_t::XTN_ITLB_INVAL:     //  checking the kernel mode
+                    if ((dreq.mode == iss_t::MODE_HYPER) || (dreq.mode == iss_t::MODE_KERNEL)) 
+                    {
+                        r_dcache_xtn_req = true;
+                        r_dcache_type_save = dreq.addr/4;
+                        r_dcache_fsm = DCACHE_ITLB_INVAL;  
+                    } 
+                    else 
+                    {
+                        r_dcache_error_type = MMU_WRITE_PRIVILEGE_VIOLATION; 
+                        r_dcache_bad_vaddr  = dreq.addr;
+                        drsp.valid = true;
+                        drsp.error = true;
+                        r_dcache_fsm = DCACHE_IDLE;
+                    }
+                    break;
+
+                case iss_t::XTN_DCACHE_INVAL:   // cache inval can be executed in user mode.
+                    r_dcache_fsm = DCACHE_DCACHE_INVAL;
+                    break;
+
+                case iss_t::XTN_MMU_DCACHE_PA_INV:   // cache inval can be executed in user mode.
+                    r_dcache_fsm = DCACHE_DCACHE_INVAL_PA;
+                    break;
+
+                case iss_t::XTN_DCACHE_FLUSH:   // cache flush can be executed in user mode.
+                    r_dcache_way = 0;
+                    r_dcache_set = 0;
+                    r_dcache_fsm = DCACHE_DCACHE_FLUSH; 
+                    break;
+
+                case iss_t::XTN_ICACHE_INVAL:   // cache inval can be executed in user mode.
+                    r_dcache_type_save = dreq.addr/4; 
+                    r_dcache_xtn_req = true;
+                    r_dcache_fsm = DCACHE_ICACHE_INVAL; 
+                    break;
+
+                case iss_t::XTN_MMU_ICACHE_PA_INV:   // cache inval can be executed in user mode.
+                    r_dcache_type_save = dreq.addr/4; 
+                    r_dcache_xtn_req = true;
+                    r_dcache_fsm = DCACHE_ICACHE_INVAL_PA; 
+                    break;
+
+                case iss_t::XTN_ICACHE_FLUSH:   // cache flush can be executed in user mode.
+                    r_dcache_type_save = dreq.addr/4; 
+                    r_dcache_xtn_req = true; 
+                    r_dcache_fsm = DCACHE_ICACHE_FLUSH;
+                    break;
+
+                case iss_t::XTN_SYNC:           // cache synchronization can be executed in user mode.
+                    if (r_wbuf.rok())
+                    {
+                        r_dcache_fsm = DCACHE_DCACHE_SYNC; 
+                    }
+                    else
+                    {
+                        drsp.valid = true;
+                        r_dcache_fsm = DCACHE_IDLE;
+                    }
+		            break;
+
+                case iss_t::XTN_MMU_WORD_LO: // modifying MMU misc registers
+                    if ((dreq.mode == iss_t::MODE_HYPER) || (dreq.mode == iss_t::MODE_KERNEL)) 
+                    {
+                        r_mmu_word_lo = (int)dreq.wdata;
+                        drsp.valid = true;
+                    } 
+                    else 
+                    {
+                        r_dcache_error_type = MMU_WRITE_PRIVILEGE_VIOLATION; 
+                        r_dcache_bad_vaddr  = dreq.addr;
+                        drsp.valid = true;
+                        drsp.error = true;
+                    }
+                    r_dcache_fsm = DCACHE_IDLE;
+                    break;
+
+                case iss_t::XTN_MMU_WORD_HI: // modifying MMU misc registers
+                    if ((dreq.mode == iss_t::MODE_HYPER) || (dreq.mode == iss_t::MODE_KERNEL)) 
+                    {
+                        r_mmu_word_hi = (int)dreq.wdata;
+                        drsp.valid = true;
+                    } 
+                    else 
+                    {
+                        r_dcache_error_type = MMU_WRITE_PRIVILEGE_VIOLATION; 
+                        r_dcache_bad_vaddr  = dreq.addr;
+                        drsp.valid = true;
+                        drsp.error = true;
+                    }
+                    r_dcache_fsm = DCACHE_IDLE;
+                    break;
+
+                default:
+                    r_dcache_error_type = MMU_WRITE_UNDEFINED_XTN; 
+                    r_dcache_bad_vaddr  = dreq.addr;
+                    drsp.valid = true;
+                    drsp.error = true;
+                    r_dcache_fsm = DCACHE_IDLE;
+                    break;
+                } // end switch xtn_opcod
+
+                break;
+            } // end if XTN_WRITE
+
+            // Evaluating dcache_hit_t, dcache_hit_x, dcache_hit_p, dcache_hit_c,
+            // dcache_pte_info, dcache_tlb_way, dcache_tlb_set & dpaddr & cacheability 
+            // - If MMU activated : cacheability is defined by the cachable bit in the TLB
+            // - If MMU not activated : cacheability is defined by the segment table.
+
+            if ( !(r_mmu_mode.read() & DATA_TLB_MASK) ) // MMU not activated
+            {
+                dcache_hit_t  = true;       
+                dcache_hit_x  = true;   
+                dcache_hit_p  = true;  
+                tlb_dpaddr    = dreq.addr; 
+                spc_dpaddr    = dreq.addr;    
+                dcache_cached = m_cacheability_table[dreq.addr] && 
+                                ((dreq.type != iss_t::DATA_LL)  && (dreq.type != iss_t::DATA_SC) &&
+                                 (dreq.type != iss_t::XTN_READ) && (dreq.type != iss_t::XTN_WRITE));     
+            } 
+            else                                                            // MMU activated
+            {
+                m_cpt_data_tlb_read++;
+                dcache_hit_t  = dcache_tlb.cctranslate(dreq.addr, &tlb_dpaddr, &dcache_pte_info, &dcache_tlb_nline, 
+                                                       &dcache_tlb_way, &dcache_tlb_set);
+                dcache_hit_x  = (((vaddr_t)r_dcache_vpn_save << PAGE_K_NBITS) == (dreq.addr & ~PAGE_K_MASK)) && r_dtlb_translation_valid; 
+                dcache_hit_p  = (((dreq.addr >> PAGE_M_NBITS) == r_dcache_id1_save) && r_dcache_ptba_ok );
+                spc_dpaddr    = ((paddr_t)r_dcache_ppn_save << PAGE_K_NBITS) | (paddr_t)((dreq.addr & PAGE_K_MASK));
+                dcache_cached = dcache_pte_info.c &&
+                                 ((dreq.type != iss_t::DATA_LL)  && (dreq.type != iss_t::DATA_SC) &&
+                                  (dreq.type != iss_t::XTN_READ) && (dreq.type != iss_t::XTN_WRITE));     
+            }
+
+            if ( !(r_mmu_mode.read() & DATA_CACHE_MASK) )   // cache not actived
+            {
+                dcache_cached = false;
+            }
+
+            // dcache_hit_c & dcache_rdata
+            if ( dcache_cached )    // using speculative physical address for cached access
+            {
+                dcache_hit_c = r_dcache.read(spc_dpaddr, &dcache_rdata);
+            } 
+            else                    // using actual physical address for uncached access
+            {
+                dcache_hit_c = false;
+            }
+
+            if ( r_mmu_mode.read() & DATA_TLB_MASK ) 
+            {
+                // Checking access rights
+                if ( dcache_hit_t ) 
+                {
+                    if (!dcache_pte_info.u && (dreq.mode == iss_t::MODE_USER)) 
+                    {
+                        if ((dreq.type == iss_t::DATA_READ)||(dreq.type == iss_t::DATA_LL))
+                        {
+                            r_dcache_error_type = MMU_READ_PRIVILEGE_VIOLATION;
+                        }
+                        else /*if ((dreq.type == iss_t::DATA_WRITE)||(dreq.type == iss_t::DATA_SC))*/
+                        {
+                            r_dcache_error_type = MMU_WRITE_PRIVILEGE_VIOLATION;
+                        }  
+                        r_dcache_bad_vaddr = dreq.addr;
+                        drsp.valid = true;
+                        drsp.error = true;
+                        drsp.rdata = 0;
+                        r_dcache_fsm = DCACHE_IDLE;
+                        break;
+                    }
+                    if (!dcache_pte_info.w && ((dreq.type == iss_t::DATA_WRITE)||(dreq.type == iss_t::DATA_SC))) 
+                    {
+                        r_dcache_error_type = MMU_WRITE_ACCES_VIOLATION;  
+                        r_dcache_bad_vaddr = dreq.addr;
+                        drsp.valid = true;
+                        drsp.error = true;
+                        drsp.rdata = 0;
+                        r_dcache_fsm = DCACHE_IDLE;
+                        break;
+                    }
+                }
+
+                // update LRU, save ppn, vpn and page type
+                if ( dcache_hit_t ) 
+                {
+                    dcache_tlb.setlru(dcache_tlb_way,dcache_tlb_set); 
+                    r_dcache_ppn_save = tlb_dpaddr >> PAGE_K_NBITS;
+                    r_dcache_vpn_save = dreq.addr >> PAGE_K_NBITS;
+                    r_dcache_tlb_nline = dcache_tlb_nline;
+                    r_dtlb_translation_valid = true;
+                }
+                else
+                {
+                    r_dtlb_translation_valid = false;
+                }
+
+            } // end if MMU activated
+
+            // compute next state 
+            if ( !dcache_hit_p && !dcache_hit_t )  // TLB miss
+            {
+                // walk page table level 1
+                r_dcache_tlb_paddr = (paddr_t)r_mmu_ptpr << (INDEX1_NBITS+2) | (paddr_t)((dreq.addr>>PAGE_M_NBITS)<<2);
+                r_dcache_tlb_read_req = true;
+                r_dcache_tlb_first_req = true;
+                r_dcache_fsm = DCACHE_TLB1_READ;
+                m_cpt_data_tlb_miss++;
+                m_cost_data_tlb_miss_frz++;
+            }
+            else if ( dcache_hit_p && !dcache_hit_t )  // TLB Miss with possibility of bypass first level page
+            {
+                // walk page table level 2
+                r_dcache_tlb_paddr = (paddr_t)r_dcache_ptba_save | 
+                                     (paddr_t)(((dreq.addr&PTD_ID2_MASK)>>PAGE_K_NBITS) << 3); 
+                r_dcache_tlb_read_req = true;
+                r_dcache_tlb_first_req = false;
+                r_dcache_fsm = DCACHE_TLB2_READ;
+                m_cpt_data_tlb_miss++;
+                m_cost_data_tlb_miss_frz++;
+            }
+            else if ( dcache_hit_t && !dcache_hit_x && dcache_cached )// cached access with an ucorrect speculative physical address
+            {
+                r_dcache_hit_p_save = dcache_hit_p;
+                r_dcache_fsm = DCACHE_BIS;
+                m_cost_data_tlb_miss_frz++;
+            }
+            else  // cached or uncached access with a correct speculative physical address
+            {
+                switch( dreq.type ) {
+                    case iss_t::DATA_READ:
+                    case iss_t::DATA_LL:
+                    case iss_t::DATA_SC:
+                        m_cpt_read++;
+                        if ( dcache_hit_c ) 
+                        {
+                            r_dcache_fsm = DCACHE_IDLE;
+                            drsp.valid = true;
+                            drsp.rdata = dcache_rdata;
+                        } 
+                        else 
+                        {
+                            if ( dcache_cached ) 
+                            {
+                                r_dcache_miss_req = true;
+                                r_dcache_fsm = DCACHE_MISS_WAIT;
+                                m_cpt_data_miss++;
+                                m_cost_data_miss_frz++;
+                            } 
+                            else 
+                            {
+                                if ( (dreq.type == iss_t::DATA_SC) && !dcache_pte_info.d && (r_mmu_mode.read() & DATA_TLB_MASK) )   // dirty bit update required
+                                {
+                                    m_cpt_data_tlb_update_dirty++;
+                                    m_cost_data_tlb_update_dirty_frz++;     
+                                    r_dcache_sc_updt_dirty = true;                       
+                                    if (dcache_tlb.getpagesize(dcache_tlb_way, dcache_tlb_set)) 
+                                    {
+                                        r_dcache_pte_update = dcache_tlb.getpte(dcache_tlb_way, dcache_tlb_set) | PTE_D_MASK;
+                                        r_dcache_tlb_paddr = (paddr_t)r_mmu_ptpr << (INDEX1_NBITS+2) | (paddr_t)((dreq.addr>>PAGE_M_NBITS)<<2);
+                                        r_dcache_tlb_ll_dirty_req = true;
+                                        r_dcache_fsm = DCACHE_LL_DIRTY_WAIT;
+                                    }
+                                    else
+                                    {   
+                                        if (dcache_hit_p) 
+                                        {
+                                            r_dcache_pte_update = dcache_tlb.getpte(dcache_tlb_way, dcache_tlb_set) | PTE_D_MASK;
+                                            r_dcache_tlb_paddr = (paddr_t)r_dcache_ptba_save | (paddr_t)(((dreq.addr&PTD_ID2_MASK)>>PAGE_K_NBITS) << 3);
+                                            r_dcache_tlb_ll_dirty_req = true;
+                                            r_dcache_fsm = DCACHE_LL_DIRTY_WAIT;
+                                        }
+                                        else    // get PTBA to calculate the physical address of PTE
+                                        {
+                                            data_t ptba;
+                                            if (r_dcache.read((paddr_t)r_mmu_ptpr << (INDEX1_NBITS+2) | (paddr_t)((dreq.addr>>PAGE_M_NBITS)<<2), &ptba))
+                                            {
+                                                r_dcache_pte_update = dcache_tlb.getpte(dcache_tlb_way, dcache_tlb_set) | PTE_D_MASK;
+                				                r_dcache_tlb_paddr = (paddr_t)(ptba & ((1<<(m_paddr_nbits - PAGE_K_NBITS))-1)) << PAGE_K_NBITS | 
+                                     (paddr_t)(((dreq.addr & PTD_ID2_MASK) >> PAGE_K_NBITS) << 3);
+                                            	r_dcache_tlb_ll_dirty_req = true;
+                                            	r_dcache_fsm = DCACHE_LL_DIRTY_WAIT;                                               
+                                            }    
+                                            else
+                                            {    
+                                                r_dcache_pte_update = dcache_tlb.getpte(dcache_tlb_way, dcache_tlb_set) | PTE_D_MASK;
+                                                r_dcache_tlb_paddr = (paddr_t)r_mmu_ptpr << (INDEX1_NBITS+2) | (paddr_t)((dreq.addr>>PAGE_M_NBITS)<<2);
+                                                r_dcache_tlb_read_req = true;
+                                                r_dcache_tlb_first_req = true;
+                                                r_dcache_tlb_ptba_read = true;
+                                                r_dcache_fsm = DCACHE_TLB1_READ;
+                                            }
+                                        }
+                                    }
+                                }
+                                else
+                                {
+                                    r_dcache_unc_req = true;
+                                    r_dcache_fsm = DCACHE_UNC_WAIT;
+                                    m_cpt_unc_read++;
+                                }
+                                m_cost_unc_read_frz++;
+                            }
+                        }
+                        break;
+                    case iss_t::DATA_WRITE:
+                        m_cpt_write++;
+                        if ( dcache_cached ) m_cpt_write_cached++;
+                        m_cost_write_frz++;
+
+                        if ( dcache_hit_c && dcache_cached )    // cache update required
+                        {
+                            r_dcache_fsm = DCACHE_WRITE_UPDT;
+
+                        } 
+                        else if ( !dcache_pte_info.d && (r_mmu_mode.read() & DATA_TLB_MASK) )   // dirty bit update required
+                        {
+                            m_cpt_data_tlb_update_dirty++;
+                            m_cost_data_tlb_update_dirty_frz++;                            
+                            if (dcache_tlb.getpagesize(dcache_tlb_way, dcache_tlb_set)) 
+                            {
+                                r_dcache_pte_update = dcache_tlb.getpte(dcache_tlb_way, dcache_tlb_set) | PTE_D_MASK;
+                                r_dcache_tlb_paddr = (paddr_t)r_mmu_ptpr << (INDEX1_NBITS+2) | (paddr_t)((dreq.addr>>PAGE_M_NBITS)<<2);
+                                r_dcache_tlb_ll_dirty_req = true;
+                                r_dcache_fsm = DCACHE_LL_DIRTY_WAIT;
+                            }
+                            else
+                            {   
+                                if (dcache_hit_p) 
+                                {
+                                    r_dcache_pte_update = dcache_tlb.getpte(dcache_tlb_way, dcache_tlb_set) | PTE_D_MASK;
+                                    r_dcache_tlb_paddr = (paddr_t)r_dcache_ptba_save | (paddr_t)(((dreq.addr&PTD_ID2_MASK)>>PAGE_K_NBITS) << 3);
+                                    r_dcache_tlb_ll_dirty_req = true;
+                                    r_dcache_fsm = DCACHE_LL_DIRTY_WAIT;
+                                }
+                                else    // get PTBA to calculate the physical address of PTE
+                                {
+                                    r_dcache_pte_update = dcache_tlb.getpte(dcache_tlb_way, dcache_tlb_set) | PTE_D_MASK;
+			                        data_t ptba;
+            		                if (r_dcache.read((paddr_t)r_mmu_ptpr << (INDEX1_NBITS+2) | (paddr_t)((dreq.addr>>PAGE_M_NBITS)<<2), &ptba))
+			                        {
+                			            r_dcache_tlb_paddr = (paddr_t)(ptba & ((1<<(m_paddr_nbits - PAGE_K_NBITS))-1)) << PAGE_K_NBITS | (paddr_t)(((dreq.addr & PTD_ID2_MASK) >> PAGE_K_NBITS) << 3);
+                                        r_dcache_tlb_ll_dirty_req = true;
+                                        r_dcache_fsm = DCACHE_LL_DIRTY_WAIT;
+			                        }
+				                    else
+				                    {
+                                        r_dcache_tlb_paddr = (paddr_t)r_mmu_ptpr << (INDEX1_NBITS+2) | (paddr_t)((dreq.addr>>PAGE_M_NBITS)<<2);
+                                        r_dcache_tlb_read_req = true;
+                                        r_dcache_tlb_first_req = true;
+                                        r_dcache_tlb_ptba_read = true;
+                                        r_dcache_fsm = DCACHE_TLB1_READ;
+				                    }
+                                }
+                            }
+                        }
+                        else                                    // no cache update, not dirty bit update
+                        {
+                            r_dcache_fsm = DCACHE_WRITE_REQ;
+                            drsp.valid = true;
+                            drsp.rdata = 0;
+                        }
+                        break;
+                    default:
+                        break;
+                } // end switch dreq.type
+            } // end if next states
+
+            // save values for the next states
+            r_dcache_paddr_save   = tlb_dpaddr;
+            r_dcache_type_save    = dreq.type;
+            r_dcache_wdata_save   = dreq.wdata;
+            r_dcache_be_save      = dreq.be;
+            r_dcache_rdata_save   = dcache_rdata;
+            r_dcache_cached_save  = dcache_cached;
+            r_dcache_dirty_save   = dcache_pte_info.d;
+            r_dcache_tlb_set_save = dcache_tlb_set;
+            r_dcache_tlb_way_save = dcache_tlb_way;
+
+        } // end if dreq.valid
+        else 
+        {   
+            r_dcache_fsm = DCACHE_IDLE;
+        }
+
+        // processor request are not accepted in the WRITE_REQ state 
+        // when the write buffer is not writeable
+
+        if ((r_dcache_fsm == DCACHE_WRITE_REQ) && 
+            (r_dcache_write_req || !r_wbuf.wok(r_dcache_paddr_save))) 
+        {
+            drsp.valid = false;
+        }
+        break;
+    }
+    /////////////////
+    case DCACHE_BIS:
+    {
+        // external cache invalidate request
+        if ( r_tgt_dcache_req )   
+        {
+            r_dcache_fsm = DCACHE_CC_CHECK;
+            r_dcache_fsm_save = r_dcache_fsm;
+            if ( dreq.valid ) m_cost_data_miss_frz++;
+            break;
+        }
+
+        if ( r_dcache_inval_tlb_rsp )
+        {
+            r_dcache_inval_tlb_rsp = false;
+            r_dcache_fsm = DCACHE_IDLE;
+            if ( dreq.valid ) m_cost_data_miss_frz++;
+            break;
+        }
+
+        data_t      dcache_rdata = 0;
+        bool        dcache_hit_c   = false;
+        bool        dcache_hit_t   = false;
+        paddr_t     tlb_dpaddr   = 0;  
+
+        // processor address translation
+        dcache_hit_t = dcache_tlb.translate(dreq.addr, &tlb_dpaddr);
+
+        if ( (tlb_dpaddr == r_dcache_paddr_save.read()) && dreq.valid && dcache_hit_t )     // unmodified & valid
+        {
+            // acces always cached in this state
+            dcache_hit_c = r_dcache.read(r_dcache_paddr_save, &dcache_rdata);
+            
+            if ( dreq.type == iss_t::DATA_READ )  // cached read
+            {
+                m_cpt_read++;
+                if ( !dcache_hit_c ) 
+                {
+                    r_dcache_miss_req = true;
+                    r_dcache_fsm = DCACHE_MISS_WAIT;
+                    m_cpt_data_miss++;
+                    m_cost_data_miss_frz++;
+                }
+                else
+                {
+                    r_dcache_fsm = DCACHE_IDLE;
+                }
+                drsp.valid = dcache_hit_c;
+                drsp.error = false;
+                drsp.rdata = dcache_rdata;
+            }
+            else    // cached write
+            {
+                m_cpt_write++;
+                m_cpt_write_cached++;
+                if ( dcache_hit_c )    // cache update required
+                {
+                	r_dcache_rdata_save = dcache_rdata;
+                    r_dcache_fsm = DCACHE_WRITE_UPDT;
+            
+                } 
+                else if ( !r_dcache_dirty_save && (r_mmu_mode.read() & DATA_TLB_MASK) )   // dirty bit update required
+                {
+                    m_cpt_data_tlb_update_dirty++;
+                    m_cost_data_tlb_update_dirty_frz++;                      
+                    if (dcache_tlb.getpagesize(r_dcache_tlb_way_save, r_dcache_tlb_set_save)) 
+                    {
+                        r_dcache_pte_update = dcache_tlb.getpte(r_dcache_tlb_way_save, r_dcache_tlb_set_save) | PTE_D_MASK;
+                        r_dcache_tlb_paddr = (paddr_t)r_mmu_ptpr << (INDEX1_NBITS+2) | (paddr_t)((dreq.addr>>PAGE_M_NBITS)<<2);
+                        r_dcache_tlb_ll_dirty_req = true;
+                        r_dcache_fsm = DCACHE_LL_DIRTY_WAIT;
+                    }
+                    else
+                    {   
+                        if (r_dcache_hit_p_save) 
+                        {
+                            r_dcache_pte_update = dcache_tlb.getpte(r_dcache_tlb_way_save, r_dcache_tlb_set_save) | PTE_D_MASK;
+                            r_dcache_tlb_paddr = (paddr_t)r_dcache_ptba_save|(paddr_t)(((dreq.addr&PTD_ID2_MASK)>>PAGE_K_NBITS) << 3);
+                            r_dcache_tlb_ll_dirty_req = true;
+                            r_dcache_fsm = DCACHE_LL_DIRTY_WAIT;
+                        }
+                        else
+                        {
+	                        r_dcache_pte_update = dcache_tlb.getpte(r_dcache_tlb_way_save, r_dcache_tlb_set_save) | PTE_D_MASK;
+			                data_t ptba;
+            		        if (r_dcache.read((paddr_t)r_mmu_ptpr << (INDEX1_NBITS+2) | (paddr_t)((dreq.addr>>PAGE_M_NBITS)<<2), &ptba))
+			                {
+                	            r_dcache_tlb_paddr = (paddr_t)(ptba & ((1<<(m_paddr_nbits - PAGE_K_NBITS))-1)) << PAGE_K_NBITS | (paddr_t)(((dreq.addr & PTD_ID2_MASK) >> PAGE_K_NBITS) << 3);
+                                r_dcache_tlb_ll_dirty_req = true;
+                                r_dcache_fsm = DCACHE_LL_DIRTY_WAIT;
+			                }
+			                else
+			                {
+                                r_dcache_tlb_paddr = (paddr_t)r_mmu_ptpr << (INDEX1_NBITS+2) | (paddr_t)((dreq.addr>>PAGE_M_NBITS)<<2);
+                                r_dcache_tlb_read_req = true;
+                                r_dcache_tlb_first_req = true;
+                                r_dcache_tlb_ptba_read = true;
+                                r_dcache_fsm = DCACHE_TLB1_READ;
+			                }
+                        }
+                    }
+                }
+                else                                    // no cache update, not dirty bit update
+                {
+                    r_dcache_fsm = DCACHE_WRITE_REQ;
+                    drsp.valid = true;
+                    drsp.rdata = 0;
+                }
+            }
+        }
+        else
+        {
+            drsp.valid = false;
+            drsp.error = false;
+            drsp.rdata = 0;
+            r_dcache_fsm = DCACHE_IDLE;
+        }
+        break;
+    }
+    //////////////////////////
+    case DCACHE_LL_DIRTY_WAIT:
+    {
+        m_cost_data_tlb_update_dirty_frz++;
+
+        // external cache invalidate request
+        if ( r_tgt_dcache_req )   
+        {
+            r_dcache_fsm = DCACHE_CC_CHECK;
+            r_dcache_fsm_save = r_dcache_fsm;
+            break;
+        }
+
+        if (!r_dcache_tlb_ll_dirty_req)
+        {
+            if ( r_vci_rsp_data_error ) // VCI response ko
+            {
+                if (dcache_tlb.getpagesize(r_dcache_tlb_way_save, r_dcache_tlb_set_save)) 
+                {
+                    r_dcache_error_type = MMU_WRITE_PT1_ILLEGAL_ACCESS;     
+                }
+                else
+                {
+                    r_dcache_error_type = MMU_WRITE_PT2_ILLEGAL_ACCESS;     
+                }
+                r_dcache_bad_vaddr = dreq.addr;
+                r_dcache_fsm = DCACHE_ERROR;
+ 
+		        if (r_dcache_inval_tlb_rsp) r_dcache_inval_tlb_rsp = false;
+		        if (r_dcache_inval_rsp) r_dcache_inval_rsp = false;
+		        if (r_dcache_sc_updt_dirty) r_dcache_sc_updt_dirty = false;
+            }
+            else
+            {
+                if ( !(r_dcache_miss_buf[0] >> PTE_V_SHIFT) )	// unmapped
+                {
+        	        if (dcache_tlb.getpagesize(r_dcache_tlb_way_save, r_dcache_tlb_set_save))
+        	        { 
+        	            r_dcache_error_type = MMU_WRITE_PT1_UNMAPPED;       
+        	        }
+        	        else
+        	        {
+        	            r_dcache_error_type = MMU_WRITE_PT2_UNMAPPED;       
+          	        }
+                    r_dcache_bad_vaddr = dreq.addr;
+                    r_dcache_fsm = DCACHE_ERROR;
+
+		            if (r_dcache_inval_tlb_rsp) r_dcache_inval_tlb_rsp = false;
+		            if (r_dcache_inval_rsp) r_dcache_inval_rsp = false;
+                    if (r_dcache_sc_updt_dirty) r_dcache_sc_updt_dirty = false;
+                }
+                else if ( r_dcache_inval_tlb_rsp )
+                {
+                    r_dcache_inval_tlb_rsp = false;
+                    r_dcache_fsm = DCACHE_IDLE;
+		            if (r_dcache_sc_updt_dirty) r_dcache_sc_updt_dirty = false;
+                }
+	            else if ( r_dcache_inval_rsp )
+	            {
+                	r_dcache_inval_rsp = false;
+	                r_dcache_fsm = DCACHE_IDLE;
+		            if (r_dcache_sc_updt_dirty) r_dcache_sc_updt_dirty = false;
+	            }
+        	    else
+        	    {
+        	        r_dcache_tlb_sc_dirty_req = true;
+                    r_dcache_pte_update = r_dcache_miss_buf[0] | r_dcache_pte_update.read();
+                    r_dcache_fsm = DCACHE_SC_DIRTY_WAIT; 
+        	    }
+            }
+        }
+        break;
+    }
+    //////////////////////////
+    case DCACHE_SC_DIRTY_WAIT:
+    {
+        m_cost_data_tlb_update_dirty_frz++;
+        // external cache invalidate request
+        if ( r_tgt_dcache_req )   
+        {
+            r_dcache_fsm = DCACHE_CC_CHECK;
+            r_dcache_fsm_save = r_dcache_fsm;
+            break;
+        }
+
+        if ( !r_dcache_tlb_sc_dirty_req ) // VCI response 
+        {
+            if ( r_vci_rsp_data_error ) // VCI response ko
+	        {
+	            if (dcache_tlb.getpagesize(r_dcache_tlb_way_save, r_dcache_tlb_set_save))
+	            {
+	                r_dcache_error_type = MMU_WRITE_PT1_ILLEGAL_ACCESS;    
+	            }
+	            else
+	            {
+	                r_dcache_error_type = MMU_WRITE_PT2_ILLEGAL_ACCESS;    
+ 	            }
+	            r_dcache_bad_vaddr = dreq.addr;
+	            r_dcache_fsm = DCACHE_ERROR; 
+
+		        if (r_dcache_inval_tlb_rsp) r_dcache_inval_tlb_rsp = false;
+		        if (r_dcache_inval_rsp) r_dcache_inval_rsp = false;
+		        if (r_dcache_sc_updt_dirty) r_dcache_sc_updt_dirty = false;
+            }
+            else
+            {
+                // Using tlb entry is invalidated 
+                if ( r_dcache_inval_tlb_rsp )
+                {
+                    r_dcache_inval_tlb_rsp = false;
+                    if (r_dcache_tlb_sc_fail) r_dcache_tlb_sc_fail = false;
+		            if (r_dcache_sc_updt_dirty) r_dcache_sc_updt_dirty = false;
+                    r_dcache_fsm = DCACHE_IDLE;
+                }
+	            else if ( r_dcache_inval_rsp )
+	            {
+                	r_dcache_inval_rsp = false;
+                    if (r_dcache_tlb_sc_fail) r_dcache_tlb_sc_fail = false;
+		            if (r_dcache_sc_updt_dirty) r_dcache_sc_updt_dirty = false;
+	                r_dcache_fsm = DCACHE_IDLE;
+	            }
+	            else if ( r_dcache_tlb_sc_fail )
+	            {
+                    r_dcache_tlb_ll_dirty_req = true;
+                    r_dcache_tlb_sc_fail = false;
+	                r_dcache_fsm = DCACHE_LL_DIRTY_WAIT; 
+	            }
+                else 
+                {
+                    r_dcache_fsm = DCACHE_WRITE_DIRTY; 
+                }
+            }
+        }
+        break;
+    }
+    //////////////////////
+    case DCACHE_TLB1_READ:
+    {
+        if ( dreq.valid ) m_cost_data_tlb_miss_frz++;
+
+        // external cache invalidate request
+        if ( r_tgt_dcache_req )   
+        {
+            r_dcache_fsm = DCACHE_CC_CHECK;
+            r_dcache_fsm_save = r_dcache_fsm;
+            break;
+        }        
+
+        if ( r_dcache_cleanup_req ) break;
+
+        if ( !r_dcache_tlb_read_req ) // VCI response ok
+        {
+            if ( r_vci_rsp_data_error )
+            {    
+                if ((r_dcache_type_save == iss_t::DATA_READ)||(r_dcache_type_save == iss_t::DATA_LL))
+                {
+                    r_dcache_error_type = MMU_READ_PT1_ILLEGAL_ACCESS;
+                }
+                else /*if ((dreq.type == iss_t::DATA_WRITE)||(dreq.type == iss_t::DATA_SC))*/
+                {
+                    r_dcache_error_type = MMU_WRITE_PT1_ILLEGAL_ACCESS;
+                } 
+                r_dcache_bad_vaddr = dreq.addr;
+                r_dcache_fsm = DCACHE_ERROR; 
+                
+		        if (r_dcache_inval_tlb_rsp) r_dcache_inval_tlb_rsp = false;
+		        if (r_dcache_inval_rsp) r_dcache_inval_rsp = false;	
+                if ( r_dcache_tlb_ptba_read ) r_dcache_tlb_ptba_read = false;
+		        break;
+            }
+
+            if ( r_dcache_inval_tlb_rsp )  // TLB miss response and invalidation
+            {
+                r_dcache_fsm = DCACHE_IDLE;
+                r_dcache_cleanup_req = true;
+                r_dcache_cleanup_line = r_dcache_tlb_paddr.read() >> (uint32_log2(m_dcache_words) + 2);  
+                r_dcache_cleanup_type = TLB_CLEANUP;
+                m_cpt_cc_cleanup_data++;
+            	r_dcache_inval_tlb_rsp = false;
+                if ( r_dcache_tlb_ptba_read ) r_dcache_tlb_ptba_read = false;
+		        break;
+            }
+
+	        if ( !(r_dcache_miss_buf[0] >> PTE_V_SHIFT) )	// unmapped
+	        {
+                r_dcache_ptba_ok    = false;
+                if ((r_dcache_type_save == iss_t::DATA_READ)||(r_dcache_type_save == iss_t::DATA_LL))
+                {
+                    r_dcache_error_type = MMU_READ_PT1_UNMAPPED;
+                }
+                else /*if ((dreq.type == iss_t::DATA_WRITE)||(dreq.type == iss_t::DATA_SC))*/
+                {
+                    r_dcache_error_type = MMU_WRITE_PT1_UNMAPPED;
+                }  
+                r_dcache_bad_vaddr  = dreq.addr;
+                r_dcache_fsm        = DCACHE_ERROR;
+
+                // unmapped cleanup in L2
+                r_dcache_cleanup_req = true;
+                r_dcache_cleanup_line = r_dcache_tlb_paddr.read() >> (uint32_log2(m_dcache_words)+2);
+                r_dcache_cleanup_type = TLB_CLEANUP;
+                m_cpt_cc_cleanup_data++;
+	        }
+	        else if ( (r_dcache_miss_buf[0] & PTE_T_MASK) >> PTE_T_SHIFT ) // PTD
+	        {
+                r_dcache_ptba_ok   = true;
+                r_dcache_ptba_save = (paddr_t)(r_dcache_miss_buf[0] & ((1<<(m_paddr_nbits - PAGE_K_NBITS))-1)) << PAGE_K_NBITS;  
+                r_dcache_id1_save  = dreq.addr >> PAGE_M_NBITS;
+                r_dcache_tlb_paddr = (paddr_t)(r_dcache_miss_buf[0] & ((1<<(m_paddr_nbits - PAGE_K_NBITS))-1)) << PAGE_K_NBITS | 
+                                     (paddr_t)(((dreq.addr & PTD_ID2_MASK) >> PAGE_K_NBITS) << 3);
+                if ( r_dcache_tlb_ptba_read )
+                {
+                    r_dcache_tlb_ptba_read = false;
+                    r_dcache_tlb_ll_dirty_req = true;
+                    r_dcache_fsm = DCACHE_LL_DIRTY_WAIT;
+                    m_cost_data_tlb_update_dirty_frz++; 
+                }
+                else
+                {
+                    r_dcache_tlb_read_req = true;
+                    r_dcache_tlb_first_req = false;
+                    r_dcache_fsm = DCACHE_TLB2_READ;
+                }
+
+                // cleanup PTD in L2, because it's not keep in L1
+                r_dcache_cleanup_req = true;
+                r_dcache_cleanup_line = r_dcache_tlb_paddr.read() >> (uint32_log2(m_dcache_words) + 2);  
+                r_dcache_cleanup_type = TLB_CLEANUP;
+                m_cpt_cc_cleanup_data++;
+
+	        }
+	        else	// PTE
+	        {
+                r_dcache_ptba_ok = false;
+	            if ( (m_srcid_rw >> 4) == ((r_dcache_tlb_paddr.read() & ((1<<(m_paddr_nbits - PAGE_M_NBITS))-1)) >> (m_paddr_nbits - PAGE_M_NBITS -10)) ) // local
+	            {
+	                if ( (r_dcache_miss_buf[0] & PTE_L_MASK ) >> PTE_L_SHIFT ) // L bit is set
+	                {
+                        r_dcache_pte_update = r_dcache_miss_buf[0];
+                        r_dcache_fsm        = DCACHE_TLB1_UPDT_SEL;
+	                }
+	                else
+	                {
+                        r_dcache_pte_update = r_dcache_miss_buf[0] | PTE_L_MASK;
+                        r_dcache_tlb_ll_acc_req = true;
+                        r_dcache_fsm        = DCACHE_TLB1_LL_WAIT;
+                        m_cpt_data_tlb_update_acc++;
+                        m_cost_data_tlb_update_acc_frz++;
+	                }
+                }
+	            else // remotely
+	            {
+	                if ( (r_dcache_miss_buf[0] & PTE_R_MASK ) >> PTE_R_SHIFT ) // R bit is set
+	                {
+                        r_dcache_pte_update = r_dcache_miss_buf[0];
+                        r_dcache_fsm        = DCACHE_TLB1_UPDT_SEL;
+	                }
+	                else
+	                {
+                        r_dcache_pte_update = r_dcache_miss_buf[0] | PTE_R_MASK;
+                        r_dcache_tlb_ll_acc_req = true;
+                        r_dcache_fsm        = DCACHE_TLB1_LL_WAIT;
+                        m_cpt_data_tlb_update_acc++;
+                        m_cost_data_tlb_update_acc_frz++;
+	                }
+	            }
+	        }
+        }
+        break;
+    }
+    ///////////////////////
+    case DCACHE_TLB1_LL_WAIT:
+    {
+        if ( dreq.valid ) m_cost_data_tlb_miss_frz++;
+        m_cost_data_tlb_update_acc_frz++;
+        
+        // external cache invalidate request
+        if ( r_tgt_dcache_req )   
+        {
+            r_dcache_fsm = DCACHE_CC_CHECK;
+            r_dcache_fsm_save = r_dcache_fsm;
+            break;
+        }    
+
+	    if (!r_dcache_tlb_ll_acc_req)
+	    {
+            if ( r_vci_rsp_data_error ) // VCI response ko
+            {
+                if ((r_dcache_type_save == iss_t::DATA_READ)||(r_dcache_type_save == iss_t::DATA_LL))
+                {
+                    r_dcache_error_type = MMU_READ_PT1_ILLEGAL_ACCESS;
+                }
+                else /*if ((dreq.type == iss_t::DATA_WRITE)||(dreq.type == iss_t::DATA_SC))*/
+                {
+                    r_dcache_error_type = MMU_WRITE_PT1_ILLEGAL_ACCESS;
+                } 
+                r_dcache_bad_vaddr = dreq.addr;
+                r_dcache_fsm = DCACHE_ERROR; 
+
+		        if (r_dcache_inval_tlb_rsp) r_dcache_inval_tlb_rsp = false;
+            }
+	        else
+	        {
+	            if ( !(r_dcache_miss_buf[0] >> PTE_V_SHIFT) )	// unmapped
+	            {
+                    if ((r_dcache_type_save == iss_t::DATA_READ)||(r_dcache_type_save == iss_t::DATA_LL))
+                    {
+                        r_dcache_error_type = MMU_READ_PT1_UNMAPPED;
+                    }
+                    else /*if ((dreq.type == iss_t::DATA_WRITE)||(dreq.type == iss_t::DATA_SC))*/
+                    {
+                        r_dcache_error_type = MMU_WRITE_PT1_UNMAPPED;
+                    }  
+                    r_dcache_bad_vaddr  = dreq.addr;
+                    r_dcache_fsm        = DCACHE_ERROR;
+
+		            if (r_dcache_inval_tlb_rsp) r_dcache_inval_tlb_rsp = false;
+	            }
+       	        else if ( r_dcache_inval_tlb_rsp )
+       	        {
+       	            r_dcache_inval_tlb_rsp = false;
+       	            r_dcache_fsm = DCACHE_IDLE;
+       	        }
+		        else
+		        {
+		            r_dcache_tlb_sc_acc_req = true;
+                    r_dcache_pte_update = r_dcache_miss_buf[0] | r_dcache_pte_update.read();
+                    r_dcache_fsm = DCACHE_TLB1_SC_WAIT; 
+		        }
+	        }
+	    }
+	    break;
+    }
+    ///////////////////////
+    case DCACHE_TLB1_SC_WAIT:
+    {
+        if ( dreq.valid ) m_cost_data_tlb_miss_frz++;
+        m_cost_data_tlb_update_acc_frz++;
+
+        // external cache invalidate request
+        if ( r_tgt_dcache_req )   
+        {
+            r_dcache_fsm = DCACHE_CC_CHECK;
+            r_dcache_fsm_save = r_dcache_fsm;
+            break;
+        }    
+
+        if ( !r_dcache_tlb_sc_acc_req ) // VCI response ko
+        {
+            if ( r_vci_rsp_data_error ) // VCI response ko
+	        {
+                if ((r_dcache_type_save == iss_t::DATA_READ)||(r_dcache_type_save == iss_t::DATA_LL))
+                {
+                    r_dcache_error_type = MMU_READ_PT1_ILLEGAL_ACCESS;
+                }
+                else /*if ((dreq.type == iss_t::DATA_WRITE)||(dreq.type == iss_t::DATA_SC))*/
+                {
+                    r_dcache_error_type = MMU_WRITE_PT1_ILLEGAL_ACCESS;
+                } 
+	            r_dcache_bad_vaddr = dreq.addr;
+	            r_dcache_fsm = DCACHE_ERROR; 
+
+		        if (r_dcache_inval_tlb_rsp) r_dcache_inval_tlb_rsp = false;
+	        }
+            else
+            {
+                // Using tlb entry is invalidated 
+                if ( r_dcache_inval_tlb_rsp )
+                {
+                    r_dcache_inval_tlb_rsp = false;
+                    if (r_dcache_tlb_sc_fail) r_dcache_tlb_sc_fail = false;
+                    r_dcache_fsm = DCACHE_IDLE;
+                }
+	            else if ( r_dcache_tlb_sc_fail )
+	            {
+                    r_dcache_tlb_ll_acc_req = true;
+                    r_dcache_tlb_sc_fail = false;
+	                r_dcache_fsm = DCACHE_TLB1_LL_WAIT; 
+	            }
+	            else
+	            {
+	                r_dcache_fsm = DCACHE_TLB1_UPDT_SEL; 
+	            }
+            }
+        }
+	    break;
+    }
+    //////////////////////
+    case DCACHE_TLB1_UPDT_SEL: 
+    {
+        if ( dreq.valid ) m_cost_data_tlb_miss_frz++;
+
+        // external cache invalidate request
+        if ( r_tgt_dcache_req )   
+        {
+            r_dcache_fsm = DCACHE_CC_CHECK;
+            r_dcache_fsm_save = r_dcache_fsm;
+            break;
+        }
+        
+        // TLB update and invalidate same PTE
+        if ( r_dcache_inval_tlb_rsp )                                 
+        {
+            r_dcache_inval_tlb_rsp = false;
+            r_dcache_fsm = DCACHE_IDLE;
+        }
+
+        // TLB update and invalidate different PTE
+        if ( !r_dcache_cleanup_req )
+        {
+            size_t way = 0;
+            size_t set = 0;
+            paddr_t victim_index = 0;
+            bool cleanup = dcache_tlb.select1((dreq.addr >> PAGE_M_NBITS),&victim_index,&way,&set);
+            r_dcache_way = way;
+            r_dcache_set = set;
+            if (cleanup)
+            {
+                r_dcache_cleanup_req = true;
+                r_dcache_cleanup_line = victim_index;
+                r_dcache_cleanup_type = TLB_CLEANUP; 
+                m_cpt_cc_cleanup_data++;
+            }
+            r_dcache_fsm = DCACHE_TLB1_UPDT;
+        }
+        break;
+    }
+    //////////////////////
+    case DCACHE_TLB1_UPDT: 
+    {
+        if ( dreq.valid ) m_cost_data_tlb_miss_frz++;
+
+        dcache_tlb.update(r_dcache_pte_update,dreq.addr,r_dcache_way.read(),r_dcache_set.read(),(r_dcache_tlb_paddr.read() >> (uint32_log2(m_dcache_words)+2)));
+        r_dcache_fsm = DCACHE_IDLE;
+        break;
+    }
+    /////////////////////
+    case DCACHE_TLB2_READ:
+    {
+        if ( dreq.valid ) m_cost_data_tlb_miss_frz++;
+
+        // external cache invalidate request
+        if ( r_tgt_dcache_req )   
+        {
+            r_dcache_fsm = DCACHE_CC_CHECK;
+            r_dcache_fsm_save = r_dcache_fsm;
+            break;
+        }        
+
+        if ( !r_dcache_tlb_read_req ) // VCI response ok
+        {
+            if ( r_vci_rsp_data_error )
+            {
+                if ((r_dcache_type_save == iss_t::DATA_READ)||(r_dcache_type_save == iss_t::DATA_LL))
+                {
+                    r_dcache_error_type = MMU_READ_PT2_ILLEGAL_ACCESS;
+                }
+                else /*if ((dreq.type == iss_t::DATA_WRITE)||(dreq.type == iss_t::DATA_SC))*/
+                {
+                    r_dcache_error_type = MMU_WRITE_PT2_ILLEGAL_ACCESS;
+                } 
+                r_dcache_bad_vaddr = dreq.addr;
+                r_dcache_fsm = DCACHE_ERROR;
+
+                if (r_dcache_inval_tlb_rsp) r_dcache_inval_tlb_rsp = false;
+		        if (r_dcache_inval_rsp) r_dcache_inval_rsp = false;	
+		        break;
+            }    
+
+            if ( r_dcache_inval_tlb_rsp )  // TLB miss response and invalidation
+            {
+                if (r_dcache_cleanup_req) break;
+                r_dcache_fsm = DCACHE_IDLE; 
+                r_dcache_cleanup_req = true;
+                r_dcache_cleanup_line = r_dcache_tlb_paddr.read() >> (uint32_log2(m_dcache_words) + 2);  
+                r_dcache_cleanup_type = TLB_CLEANUP;
+                m_cpt_cc_cleanup_data++;
+            	r_dcache_inval_tlb_rsp = false;
+		        break;
+            }
+
+	        if ( !(r_dcache_miss_buf[0] >> PTE_V_SHIFT) )	// unmapped
+	        {
+                if ((r_dcache_type_save == iss_t::DATA_READ)||(r_dcache_type_save == iss_t::DATA_LL))
+                {
+                    r_dcache_error_type = MMU_READ_PT2_UNMAPPED;
+                }
+                else /*if ((dreq.type == iss_t::DATA_WRITE)||(dreq.type == iss_t::DATA_SC))*/
+                {
+                    r_dcache_error_type = MMU_WRITE_PT2_UNMAPPED;
+                }  
+                r_dcache_bad_vaddr  = dreq.addr;
+                r_dcache_fsm        = DCACHE_ERROR;
+
+                r_dcache_cleanup_req = true;
+                r_dcache_cleanup_line = r_dcache_tlb_paddr.read() >> (uint32_log2(m_dcache_words) + 2);  
+                r_dcache_cleanup_type = TLB_CLEANUP;
+                m_cpt_cc_cleanup_data++;
+	        }
+	        else if ( (r_dcache_miss_buf[0] & PTE_T_MASK) >> PTE_T_SHIFT ) // PTD
+	        {
+                r_dcache_pte_update = r_dcache_miss_buf[0];
+	            r_dcache_fsm = DCACHE_TLB2_UPDT_SEL;
+	        }
+            else
+            {
+	            if ( (m_srcid_rw >> 4) == ((r_dcache_tlb_paddr.read() & ((1<<(m_paddr_nbits - PAGE_M_NBITS))-1)) >> (m_paddr_nbits - PAGE_M_NBITS -10)) ) // local
+	            {
+	                if ( (r_dcache_miss_buf[0] & PTE_L_MASK ) >> PTE_L_SHIFT ) // L bit is set
+	                {
+                        r_dcache_pte_update = r_dcache_miss_buf[0];
+                        r_dcache_fsm        = DCACHE_TLB2_UPDT_SEL;
+	                }
+	                else
+	                {
+                        r_dcache_pte_update = r_dcache_miss_buf[0] | PTE_L_MASK;
+                        r_dcache_tlb_ll_acc_req = true; 
+                        r_dcache_fsm = DCACHE_TLB2_LL_WAIT;
+                        m_cpt_data_tlb_update_acc++;
+                        m_cost_data_tlb_update_acc_frz++;
+	                }
+                }
+	            else // remotely
+	            {
+	                if ( (r_dcache_miss_buf[0] & PTE_R_MASK ) >> PTE_R_SHIFT ) // R bit is set
+	                {
+                        r_dcache_pte_update = r_dcache_miss_buf[0];
+                        r_dcache_fsm        = DCACHE_TLB2_UPDT_SEL;
+	                }
+	                else
+	                {
+                        r_dcache_pte_update = r_dcache_miss_buf[0] | PTE_R_MASK;
+                        r_dcache_tlb_ll_acc_req = true;
+                        r_dcache_fsm = DCACHE_TLB2_LL_WAIT;
+                        m_cpt_data_tlb_update_acc++;
+                        m_cost_data_tlb_update_acc_frz++;
+	                }
+	            }
+            }
+        }  
+        break;
+    }
+    ///////////////////////
+    case DCACHE_TLB2_LL_WAIT:
+    {
+        if ( dreq.valid ) m_cost_data_tlb_miss_frz++;
+        m_cost_data_tlb_update_acc_frz++;
+        
+        // external cache invalidate request
+        if ( r_tgt_dcache_req )   
+        {
+            r_dcache_fsm = DCACHE_CC_CHECK;
+            r_dcache_fsm_save = r_dcache_fsm;
+            break;
+        }    
+
+	    if (!r_dcache_tlb_ll_acc_req)
+	    {
+            if ( r_vci_rsp_data_error ) // VCI response ko
+            {
+                if ((r_dcache_type_save == iss_t::DATA_READ)||(r_dcache_type_save == iss_t::DATA_LL))
+                {
+                    r_dcache_error_type = MMU_READ_PT2_ILLEGAL_ACCESS;
+                }
+                else /*if ((dreq.type == iss_t::DATA_WRITE)||(dreq.type == iss_t::DATA_SC))*/
+                {
+                    r_dcache_error_type = MMU_WRITE_PT2_ILLEGAL_ACCESS;
+                } 
+                r_dcache_bad_vaddr = dreq.addr;
+                r_dcache_fsm = DCACHE_ERROR; 
+                
+                if (r_dcache_inval_tlb_rsp) r_dcache_inval_tlb_rsp = false;
+            }
+	        else
+	        {
+	            if ( !(r_dcache_miss_buf[0] >> PTE_V_SHIFT) )	// unmapped
+	            {
+                    if ((r_dcache_type_save == iss_t::DATA_READ)||(r_dcache_type_save == iss_t::DATA_LL))
+                    {
+                        r_dcache_error_type = MMU_READ_PT2_UNMAPPED;
+                    }
+                    else /*if ((dreq.type == iss_t::DATA_WRITE)||(dreq.type == iss_t::DATA_SC))*/
+                    {
+                        r_dcache_error_type = MMU_WRITE_PT2_UNMAPPED;
+                    }  
+                    r_dcache_bad_vaddr = dreq.addr;
+                    r_dcache_fsm = DCACHE_ERROR;
+
+                    if (r_dcache_inval_tlb_rsp) r_dcache_inval_tlb_rsp = false;
+	            }
+       	        else if ( r_dcache_inval_tlb_rsp )
+       	        {
+       	            r_dcache_inval_tlb_rsp = false;
+       	            r_dcache_fsm = DCACHE_IDLE;
+       	        }
+		        else
+		        {
+		            r_dcache_tlb_sc_acc_req = true;
+                    r_dcache_pte_update = r_dcache_miss_buf[0] | r_dcache_pte_update.read();
+                    r_dcache_fsm = DCACHE_TLB2_SC_WAIT; 
+		        }
+	        }
+	    }
+	    break;
+    }
+    ///////////////////////
+    case DCACHE_TLB2_SC_WAIT:
+    {
+        if ( dreq.valid ) m_cost_data_tlb_miss_frz++;
+        m_cost_data_tlb_update_acc_frz++;
+        
+        // external cache invalidate request
+        if ( r_tgt_dcache_req )   
+        {
+            r_dcache_fsm = DCACHE_CC_CHECK;
+            r_dcache_fsm_save = r_dcache_fsm;
+            break;
+        }  
+
+        if ( !r_dcache_tlb_sc_acc_req ) // VCI response 
+        {
+            if ( r_vci_rsp_data_error ) // VCI response ko
+	        {
+                if ((r_dcache_type_save == iss_t::DATA_READ)||(r_dcache_type_save == iss_t::DATA_LL))
+                {
+                    r_dcache_error_type = MMU_READ_PT2_ILLEGAL_ACCESS;
+                }
+                else /*if ((dreq.type == iss_t::DATA_WRITE)||(dreq.type == iss_t::DATA_SC))*/
+                {
+                    r_dcache_error_type = MMU_WRITE_PT2_ILLEGAL_ACCESS;
+                } 
+	            r_dcache_bad_vaddr = dreq.addr;
+	            r_dcache_fsm = DCACHE_ERROR; 
+
+                if (r_dcache_inval_tlb_rsp) r_dcache_inval_tlb_rsp = false;
+	        }
+            else
+            {
+                // Using tlb entry is invalidated 
+                if ( r_dcache_inval_tlb_rsp )
+                {
+                    r_dcache_inval_tlb_rsp = false;
+                    if (r_dcache_tlb_sc_fail) r_dcache_tlb_sc_fail = false;
+                    r_dcache_fsm = DCACHE_IDLE;
+                }
+	            else if ( r_dcache_tlb_sc_fail )
+	            {
+                    r_dcache_tlb_ll_acc_req = true;
+                    r_dcache_tlb_sc_fail = false;
+	                r_dcache_fsm = DCACHE_TLB2_LL_WAIT; 
+	            }
+	            else 
+	            {
+	                r_dcache_fsm = DCACHE_TLB2_UPDT_SEL; 
+	            }
+            }
+        }
+	    break;
+    }
+    //////////////////////////
+    case DCACHE_TLB2_UPDT_SEL:  
+    {
+        if ( dreq.valid ) m_cost_data_tlb_miss_frz++;
+
+        // external cache invalidate request
+        if ( r_tgt_dcache_req )   
+        {
+            r_dcache_fsm = DCACHE_CC_CHECK;
+            r_dcache_fsm_save = r_dcache_fsm;
+            break;
+        }   
+     
+        // TLB update and invalidate same PTE
+        if ( r_dcache_inval_tlb_rsp )                                 
+        {
+            r_dcache_inval_tlb_rsp = false;
+            r_dcache_fsm = DCACHE_IDLE;
+        }
+
+        // TLB update and invalidate different PTE
+        if ( !r_dcache_cleanup_req )
+        {
+            size_t way = 0;
+            size_t set = 0;
+            paddr_t victim_index = 0;
+            bool cleanup = dcache_tlb.select1((dreq.addr >> PAGE_K_NBITS),&victim_index,&way,&set);            
+            r_dcache_way = way;
+            r_dcache_set = set;
+            if (cleanup)
+            {
+                r_dcache_cleanup_req = true;
+                r_dcache_cleanup_line = victim_index;
+                r_dcache_cleanup_type = TLB_CLEANUP; 
+                m_cpt_cc_cleanup_data++;
+            }
+            r_dcache_fsm = DCACHE_TLB2_UPDT;
+        }
+        break;
+    }
+    //////////////////////
+    case DCACHE_TLB2_UPDT:  
+    {
+        if ( dreq.valid ) m_cost_data_tlb_miss_frz++;
+
+        dcache_tlb.update(r_dcache_pte_update,r_dcache_miss_buf[1],dreq.addr,r_dcache_way.read(),r_dcache_set.read(),(r_dcache_tlb_paddr.read() >> (uint32_log2(m_dcache_words)+2)));
+        r_dcache_fsm = DCACHE_IDLE;
+        break;
+    }
+    //////////////////////////
+    case DCACHE_CTXT_SWITCH:
+    {
+        size_t way = r_dcache_way;
+        size_t set = r_dcache_set;
+        bool clean = false;
+
+        // 4K page size TLB flush leads to cleanup req  
+        if ( !r_dcache_cleanup_req )    // last cleanup finish
+        {
+            paddr_t victim_index = 0;
+            for ( ; way < m_dtlb_ways; way++)
+            {
+                for ( ; set < m_dtlb_sets; set++)
+                {
+                    if(dcache_tlb.checkcleanup1(way, set, &victim_index))
+                    {
+                        clean = true;
+                        r_dcache_cleanup_req = true;
+                        r_dcache_cleanup_line = victim_index;
+                        r_dcache_cleanup_type = TLB_CLEANUP;
+                        m_cpt_cc_cleanup_data++;
+                        r_dcache_way = way + ((set+1)/m_dtlb_sets);
+                        r_dcache_set = (set+1) % m_dtlb_sets;
+                        break;
+                    }
+                }
+                if (clean) break;
+                set = 0;
+            }
+
+            if ((way == m_dtlb_ways) && (!r_dcache_xtn_req))
+            {
+                r_dcache_fsm = DCACHE_IDLE;
+                r_dtlb_translation_valid = false;
+                r_dcache_ptba_ok = false;
+                drsp.valid = true;
+                break;
+            }
+        }
+        break;
+    }
+    ////////////////////////
+    case DCACHE_ICACHE_FLUSH:
+    case DCACHE_ICACHE_INVAL:
+    case DCACHE_ICACHE_INVAL_PA:
+    case DCACHE_ITLB_INVAL:
+    {
+        // external cache invalidate request
+        if ( r_tgt_dcache_req )   
+        {
+            r_dcache_fsm = DCACHE_CC_CHECK;
+            r_dcache_fsm_save = r_dcache_fsm;
+            break;
+        }  
+
+        if ( !r_dcache_xtn_req ) 
+        {
+            r_dcache_fsm = DCACHE_IDLE;
+            drsp.valid = true;
+        }
+        break;
+    }
+    ////////////////////////
+    case DCACHE_DCACHE_FLUSH:
+    {
+        // external cache invalidate request
+        if ( r_tgt_dcache_req )   
+        {
+            r_dcache_fsm = DCACHE_CC_CHECK;
+            r_dcache_fsm_save = r_dcache_fsm;
+            break;
+        }  
+        size_t way = r_dcache_way;
+        size_t set = r_dcache_set;
+        bool clean = false;
+        
+        // cache flush and send cleanup to external
+        if ( !r_dcache_cleanup_req )
+        {
+            paddr_t victim_index = 0;
+            for ( ; way < m_dcache_ways; way++ )
+            {    
+                for ( ; set < m_dcache_sets; set++ )
+                {  
+                    if ( r_dcache.flush(way, set, &victim_index) )
+                    {
+                        clean = true;
+                        r_dcache_cleanup_req = true;
+                        r_dcache_cleanup_line = victim_index;
+                        r_dcache_cleanup_type = CACHE_CLEANUP;
+                        m_cpt_cc_cleanup_data++;
+                        r_dcache_way = way + ((set+1)/m_dcache_sets);
+                        r_dcache_set = (set+1) % m_dcache_sets;
+                        break;
+                    }
+                }
+                if (clean) break;
+                set = 0;
+            }
+
+            if ( way == m_dcache_ways )  
+            {
+                r_dcache_fsm = DCACHE_IDLE;
+                drsp.valid = true;
+                break;
+            }
+        }
+        break;
+    }
+    //////////////////////
+    case DCACHE_DTLB_INVAL: 
+    {
+        paddr_t victim_index = 0;
+
+        if ( !r_dcache_cleanup_req )
+        {
+            r_dcache_cleanup_req = dcache_tlb.inval1(r_dcache_wdata_save, &victim_index);
+            r_dcache_cleanup_type = TLB_CLEANUP;
+            m_cpt_cc_cleanup_data++;
+            r_dcache_cleanup_line = victim_index;
+            r_dtlb_translation_valid = false;
+            r_dcache_ptba_ok = false;
+            r_dcache_fsm = DCACHE_IDLE;
+            drsp.valid = true;
+        }
+        break;
+    }
+    ////////////////////////
+    case DCACHE_DCACHE_INVAL:
+    {
+        // external cache invalidate request
+        if ( r_tgt_dcache_req )   
+        {
+            r_dcache_fsm = DCACHE_CC_CHECK;
+            r_dcache_fsm_save = r_dcache_fsm;
+            break;
+        }  
+
+        m_cpt_dcache_dir_read += m_dcache_ways;
+        vaddr_t invadr = dreq.wdata;
+        paddr_t dpaddr = 0;
+        bool dcache_hit_t = false; 
+
+        if ( !r_dcache_cleanup_req )
+        {
+            if ( r_mmu_mode.read() & DATA_TLB_MASK ) 
+            {
+                dcache_hit_t = dcache_tlb.translate(invadr, &dpaddr); 
+            } 
+            else 
+            {
+                dpaddr = invadr;  
+                dcache_hit_t = true;
+            }
+
+            if ( dcache_hit_t )
+            {
+                r_dcache_cleanup_req = r_dcache.inval(dpaddr);
+                r_dcache_cleanup_type = CACHE_CLEANUP;
+                m_cpt_cc_cleanup_data++;
+                r_dcache_cleanup_line = dpaddr >> (uint32_log2(m_dcache_words)+2);
+            }
+            r_dcache_fsm = DCACHE_IDLE;
+            drsp.valid = true;
+        }
+        break;
+    }
+    ////////////////////////
+    case DCACHE_DCACHE_INVAL_PA:
+    {
+        // external cache invalidate request
+        if ( r_tgt_dcache_req )   
+        {
+            r_dcache_fsm = DCACHE_CC_CHECK;
+            r_dcache_fsm_save = r_dcache_fsm;
+            break;
+        }  
+
+        m_cpt_dcache_dir_read += m_dcache_ways;
+        paddr_t dpaddr = (paddr_t)r_mmu_word_hi.read() << 32 | r_mmu_word_lo.read();
+
+        if ( !r_dcache_cleanup_req )
+        {
+            r_dcache_cleanup_req = r_dcache.inval(dpaddr);
+            r_dcache_cleanup_type = CACHE_CLEANUP;
+            m_cpt_cc_cleanup_data++;
+            r_dcache_cleanup_line = dpaddr >> (uint32_log2(m_dcache_words)+2);
+            r_dcache_fsm = DCACHE_IDLE;
+            drsp.valid = true;
+        }
+        break;
+    }
+    /////////////////////////
+    case DCACHE_DCACHE_SYNC:
+    {
+        // external cache invalidate request
+        if ( r_tgt_dcache_req )   
+        {
+            r_dcache_fsm = DCACHE_CC_CHECK;
+            r_dcache_fsm_save = r_dcache_fsm;
+            break;
+        }  
+
+        if ( !r_dcache_write_req ) 
+        {
+            r_dcache_write_req = r_wbuf.rok();
+            drsp.valid = true;
+            r_dcache_fsm = DCACHE_IDLE;
+        }    
+        break;
+    }
+    /////////////////////
+    case DCACHE_MISS_WAIT:
+    {
+        if (dreq.valid) m_cost_data_miss_frz++;
+        // external cache invalidate request
+        if ( r_tgt_dcache_req ) 
+        {
+            r_dcache_fsm = DCACHE_CC_CHECK;
+            r_dcache_fsm_save = r_dcache_fsm;
+            break;
+        }
+
+        if ( !r_dcache_miss_req )
+        {
+            if ( r_vci_rsp_data_error ) 
+            {
+                r_dcache_error_type = MMU_READ_DATA_ILLEGAL_ACCESS; 
+                r_dcache_bad_vaddr = dreq.addr;
+                r_dcache_fsm = DCACHE_ERROR;
+
+		        if (r_dcache_inval_tlb_rsp) r_dcache_inval_tlb_rsp = false;
+		        if (r_dcache_inval_rsp) r_dcache_inval_rsp = false;
+		        break;
+            }        
+
+            if ( r_dcache_inval_tlb_rsp ) // Miss read response and tlb invalidation
+            {
+                if ( r_dcache_cleanup_req ) break;
+                r_dcache_cleanup_req = true;
+                r_dcache_cleanup_type = CACHE_CLEANUP;
+                m_cpt_cc_cleanup_data++;
+                r_dcache_cleanup_line = r_dcache_paddr_save.read() >> (uint32_log2(m_dcache_words) + 2);  
+                r_dcache_fsm = DCACHE_IDLE;
+                r_dcache_inval_tlb_rsp = false;
+                if ( r_dcache_inval_rsp ) r_dcache_inval_rsp = false;
+		        break;
+            }	
+
+	        if ( r_dcache_inval_rsp ) // TLB miss response and cache invalidation
+	        {
+                if ( r_dcache_cleanup_req ) break;
+                r_dcache_cleanup_req = true;
+                r_dcache_cleanup_type = CACHE_CLEANUP;
+                m_cpt_cc_cleanup_data++;
+                r_dcache_cleanup_line = r_dcache_paddr_save.read() >> (uint32_log2(m_dcache_words) + 2);  
+                r_dcache_fsm = DCACHE_IDLE;
+                r_dcache_inval_rsp = false;
+		        break;	    
+            }
+	        // Miss read response and no tlb invalidation   
+            r_dcache_fsm = DCACHE_MISS_UPDT;
+        }
+        break;
+    }
+    /////////////////////
+    case DCACHE_MISS_UPDT:
+    {
+        if (dreq.valid) m_cost_data_miss_frz++;
+        // external cache invalidate request
+        if ( r_tgt_dcache_req ) 
+        {
+            r_dcache_fsm = DCACHE_CC_CHECK;
+            r_dcache_fsm_save = r_dcache_fsm;
+            break;
+        }
+
+        if ( r_dcache_inval_tlb_rsp ) // tlb invalidation
+        {
+            if ( r_dcache_cleanup_req ) break;
+            r_dcache_cleanup_req = true;
+            r_dcache_cleanup_type = CACHE_CLEANUP;            
+            m_cpt_cc_cleanup_data++;
+            r_dcache_cleanup_line = r_dcache_paddr_save.read() >> (uint32_log2(m_dcache_words) + 2);  
+            r_dcache_inval_tlb_rsp = false;
+            r_dcache_inval_rsp = false;
+            r_dcache_fsm = DCACHE_IDLE;
+            break;
+        }
+
+        // Using tlb entry is in the invalidated cache line  
+        if ( r_dcache_inval_rsp )
+        {
+            if ( r_dcache_cleanup_req ) break;
+            r_dcache_cleanup_req = true;
+            r_dcache_cleanup_type = CACHE_CLEANUP;            
+            m_cpt_cc_cleanup_data++;
+            r_dcache_cleanup_line = r_dcache_paddr_save.read() >> (uint32_log2(m_dcache_words) + 2);  
+            r_dcache_inval_rsp = false;
+            r_dcache_fsm = DCACHE_IDLE;
+            break;
+        }
+
+        if ( !r_dcache_cleanup_req ) // Miss update and no invalidation
+        {
+            paddr_t  victim_index = 0;
+            m_cpt_dcache_data_write++;
+            m_cpt_dcache_dir_write++;
+            r_dcache_cleanup_req = r_dcache.update(r_dcache_paddr_save.read(), r_dcache_miss_buf, &victim_index);
+            r_dcache_cleanup_line = victim_index;
+            r_dcache_cleanup_type = CACHE_CLEANUP;
+            m_cpt_cc_cleanup_data++;
+            r_dcache_fsm = DCACHE_IDLE;
+        }
+        break;
+    }
+    //////////////////////
+    case DCACHE_UNC_WAIT:
+    {
+        if ( dreq.valid ) m_cost_unc_read_frz++;
+        // external cache invalidate request
+        if ( r_tgt_dcache_req ) 
+        {
+            r_dcache_fsm = DCACHE_CC_CHECK;
+            r_dcache_fsm_save = r_dcache_fsm;
+            break;
+        }
+
+        if ( !r_dcache_unc_req )
+        {
+            if ( r_vci_rsp_data_error ) 
+            {
+                r_dcache_error_type = MMU_READ_DATA_ILLEGAL_ACCESS; 
+                r_dcache_bad_vaddr = dreq.addr;
+                r_dcache_fsm = DCACHE_ERROR;
+
+                if (r_dcache_inval_tlb_rsp) r_dcache_inval_tlb_rsp = false;
+		        break;
+            }
+
+            if ( r_dcache_inval_tlb_rsp ) // Miss read response and tlb invalidation
+            {
+                r_dcache_inval_tlb_rsp = false;
+            }
+/*  
+            if (dreq.type == iss_t::DATA_SC) 
+	        {
+                // Simulate an invalidate request
+		        r_dcache_cleanup_req = r_dcache.inval(r_dcache_paddr_save);
+                r_dcache_cleanup_type = CACHE_CLEANUP;
+                m_cpt_cc_cleanup_data++;
+		        r_dcache_cleanup_line = r_dcache_paddr_save.read() >> (uint32_log2(m_dcache_words)+2);
+            }	
+*/	
+            drsp.valid = true;
+	        drsp.rdata = r_dcache_miss_buf[0];
+	        r_dcache_fsm = DCACHE_IDLE;        
+        }
+        break;
+    }
+    ///////////////////////
+    case DCACHE_WRITE_UPDT:
+    {
+        m_cpt_dcache_data_write++;
+        bool write_hit = false;
+        data_t mask = vci_param::be2mask(r_dcache_be_save.read());
+        data_t wdata = (mask & r_dcache_wdata_save) | (~mask & r_dcache_rdata_save);
+        write_hit = r_dcache.write(r_dcache_paddr_save, wdata);
+        assert(write_hit && "Write on miss ignores data");
+
+        if ( !r_dcache_dirty_save && (r_mmu_mode.read() & DATA_TLB_MASK) )   
+        {
+            m_cpt_data_tlb_update_dirty++;
+            m_cost_data_tlb_update_dirty_frz++;               
+            if ( dcache_tlb.getpagesize(r_dcache_tlb_way_save, r_dcache_tlb_set_save) )	// 2M page size, one level page table 
+            {
+                r_dcache_pte_update = dcache_tlb.getpte(r_dcache_tlb_way_save, r_dcache_tlb_set_save) | PTE_D_MASK;
+                r_dcache_tlb_paddr = (paddr_t)r_mmu_ptpr << (INDEX1_NBITS+2) | (paddr_t)((dreq.addr>>PAGE_M_NBITS)<<2);
+                r_dcache_tlb_ll_dirty_req = true;
+                r_dcache_fsm = DCACHE_LL_DIRTY_WAIT;
+            }
+            else
+            {   
+                if (r_dcache_hit_p_save) 
+                {
+                    r_dcache_pte_update = dcache_tlb.getpte(r_dcache_tlb_way_save, r_dcache_tlb_set_save) | PTE_D_MASK;
+                    r_dcache_tlb_paddr = (paddr_t)r_dcache_ptba_save|(paddr_t)(((dreq.addr&PTD_ID2_MASK)>>PAGE_K_NBITS) << 3);
+                    r_dcache_tlb_ll_dirty_req = true;
+                    r_dcache_fsm = DCACHE_LL_DIRTY_WAIT;
+                }
+                else
+                {
+                    r_dcache_pte_update = dcache_tlb.getpte(r_dcache_tlb_way_save, r_dcache_tlb_set_save) | PTE_D_MASK;
+		            data_t ptba;
+            	    if (r_dcache.read((paddr_t)r_mmu_ptpr << (INDEX1_NBITS+2) | (paddr_t)((dreq.addr>>PAGE_M_NBITS)<<2), &ptba))
+		            {
+                        r_dcache_tlb_paddr = (paddr_t)(ptba & ((1<<(m_paddr_nbits - PAGE_K_NBITS))-1)) << PAGE_K_NBITS | (paddr_t)(((dreq.addr & PTD_ID2_MASK) >> PAGE_K_NBITS) << 3);
+                    	r_dcache_tlb_ll_dirty_req = true;
+                    	r_dcache_fsm = DCACHE_LL_DIRTY_WAIT;
+		        
+		            }
+		            else
+		            {
+                        r_dcache_tlb_paddr = (paddr_t)r_mmu_ptpr << (INDEX1_NBITS+2) | (paddr_t)((dreq.addr>>PAGE_M_NBITS)<<2);
+                        r_dcache_tlb_ptba_read = true;
+                        r_dcache_tlb_read_req = true;
+                        r_dcache_tlb_first_req = true;
+                        r_dcache_fsm = DCACHE_TLB1_READ;
+		            }
+                }
+            }        
+        }
+        else
+        {
+            r_dcache_fsm = DCACHE_WRITE_REQ;
+            drsp.valid = true;
+            drsp.rdata = 0;
+        }
+        break;
+    }
+    ////////////////////////
+    case DCACHE_WRITE_DIRTY:
+    {
+        m_cost_data_tlb_update_dirty_frz++;
+
+        // external cache invalidate request
+        if ( r_tgt_dcache_req ) 
+        {
+            r_dcache_fsm = DCACHE_CC_CHECK;
+            r_dcache_fsm_save = r_dcache_fsm;
+            break;
+        }
+
+        if ( r_dcache_inval_tlb_rsp ) // Miss read response and tlb invalidation
+        {
+            r_dcache_fsm = DCACHE_IDLE;
+	        if ( r_dcache_sc_updt_dirty ) r_dcache_sc_updt_dirty = false;
+            r_dcache_inval_tlb_rsp = false;
+	        break;
+        }
+        dcache_tlb.setdirty(r_dcache_tlb_way_save, r_dcache_tlb_set_save);
+	    if (  r_dcache_sc_updt_dirty )
+	    {
+	        r_dcache_sc_updt_dirty = false;
+            r_dcache_unc_req = true;
+            r_dcache_fsm = DCACHE_UNC_WAIT;
+            m_cpt_unc_read++;
+	    }
+	    else
+	    {
+            r_dcache_fsm = DCACHE_WRITE_REQ;
+            drsp.valid = true;
+            drsp.rdata = 0;	
+	    }	
+        break;
+    }
+    /////////////////
+    case DCACHE_ERROR:
+    {
+        r_vci_rsp_data_error = false;
+        drsp.valid = true;
+        drsp.error = true;
+        drsp.rdata = 0;
+        r_dcache_fsm = DCACHE_IDLE;
+        break;
+    }   
+    /////////////////////
+    case DCACHE_CC_CHECK:   // read directory in case of invalidate or update request
+    {
+        m_cpt_dcache_dir_read += m_dcache_ways;
+        m_cpt_dcache_data_read += m_dcache_ways;
+
+        /* activity counter */
+        if ( (( r_dcache_fsm_save.read() == DCACHE_BIS ) ||( r_dcache_fsm_save.read() == DCACHE_MISS_WAIT ) || ( r_dcache_fsm_save.read() == DCACHE_MISS_UPDT ) ) && ( dreq.valid ) )        
+        {
+            m_cost_data_miss_frz++;
+        }
+        if( (( r_dcache_fsm_save.read() == DCACHE_TLB1_READ )   || ( r_dcache_fsm_save.read() == DCACHE_TLB2_READ )    ||
+             ( r_dcache_fsm_save.read() == DCACHE_TLB1_LL_WAIT )|| ( r_dcache_fsm_save.read() == DCACHE_TLB2_LL_WAIT ) ||
+             ( r_dcache_fsm_save.read() == DCACHE_TLB1_SC_WAIT )|| ( r_dcache_fsm_save.read() == DCACHE_TLB2_SC_WAIT ) || 
+             ( r_dcache_fsm_save.read() == DCACHE_TLB1_UPDT )   || ( r_dcache_fsm_save.read() == DCACHE_TLB2_UPDT ))   && (dreq.valid) )
+        {
+            m_cost_data_tlb_miss_frz++;
+        }
+
+        if(( /*( r_dcache_fsm_save == DCACHE_UNC_WAIT ) ||*/
+	         ( r_dcache_fsm_save.read() == DCACHE_MISS_WAIT ) || ( r_dcache_fsm_save.read() == DCACHE_MISS_UPDT ) ) && 
+           ( (r_dcache_paddr_save.read() & ~((m_dcache_words<<2)-1)) == (r_tgt_addr.read() & ~((m_dcache_words<<2)-1)))) 
+        {
+            r_dcache_inval_rsp = true;
+            r_tgt_dcache_rsp = r_tgt_update;
+
+            if ( r_tgt_broadcast )
+            {
+                r_dcache_tlb_inval_req = true;
+                r_dcache_fsm = DCACHE_TLB_CC_INVAL;        
+            }
+            else
+            {
+                r_tgt_dcache_req = false;
+                r_dcache_fsm = r_dcache_fsm_save;        
+            }    
+        } 
+        else
+        { 
+            data_t dcache_rdata = 0;
+            bool dcache_hit = r_dcache.read(r_tgt_addr.read(), &dcache_rdata);   
+
+            if ( dcache_hit )
+            {
+                if ( r_tgt_update ) // update 
+                {
+                    r_dcache_fsm = DCACHE_CC_UPDT;
+                } 
+                else                // invalidate 
+                {
+                    r_dcache_fsm = DCACHE_CC_INVAL;
+                }
+            }
+            else                    // nothing
+            {
+                r_dcache_fsm = DCACHE_CC_NOP;
+            }
+        }
+        break;
+    }
+    ///////////////////
+    case DCACHE_CC_UPDT:    // update directory and data cache        
+    {
+        /* activity counter */
+        if ( (( r_dcache_fsm_save.read() == DCACHE_BIS ) ||( r_dcache_fsm_save.read() == DCACHE_MISS_WAIT ) || ( r_dcache_fsm_save.read() == DCACHE_MISS_UPDT ) ) && ( dreq.valid ) )        
+        {
+            m_cost_data_miss_frz++;
+        }
+        if( (( r_dcache_fsm_save.read() == DCACHE_TLB1_READ )   || ( r_dcache_fsm_save.read() == DCACHE_TLB2_READ )    ||
+             ( r_dcache_fsm_save.read() == DCACHE_TLB1_LL_WAIT )|| ( r_dcache_fsm_save.read() == DCACHE_TLB2_LL_WAIT ) ||
+             ( r_dcache_fsm_save.read() == DCACHE_TLB1_SC_WAIT )|| ( r_dcache_fsm_save.read() == DCACHE_TLB2_SC_WAIT ) || 
+             ( r_dcache_fsm_save.read() == DCACHE_TLB1_UPDT )   || ( r_dcache_fsm_save.read() == DCACHE_TLB2_UPDT ))   && (dreq.valid) )
+        {
+            m_cost_data_tlb_miss_frz++;
+        }
+
+        m_cpt_dcache_dir_write++;
+        m_cpt_dcache_data_write++;
+
+        data_t* buf = r_tgt_buf;
+        for( size_t i = 0; i < m_dcache_words; i++ )
+        {
+            if( r_tgt_val[i] ) r_dcache.write( r_tgt_addr.read() + i*4, buf[i] );
+        }
+        r_tgt_dcache_req = false;
+        r_tgt_dcache_rsp = true;
+        r_dcache_fsm = r_dcache_fsm_save;
+        break;
+    }
+    /////////////////////
+    case DCACHE_CC_INVAL:   // invalidate a cache line
+    {
+        /* activity counter */
+        if ( (( r_dcache_fsm_save.read() == DCACHE_BIS ) ||( r_dcache_fsm_save.read() == DCACHE_MISS_WAIT ) || ( r_dcache_fsm_save.read() == DCACHE_MISS_UPDT ) ) && ( dreq.valid ) )        
+        {
+            m_cost_data_miss_frz++;
+        }
+        if( (( r_dcache_fsm_save.read() == DCACHE_TLB1_READ )   || ( r_dcache_fsm_save.read() == DCACHE_TLB2_READ )    ||
+             ( r_dcache_fsm_save.read() == DCACHE_TLB1_LL_WAIT )|| ( r_dcache_fsm_save.read() == DCACHE_TLB2_LL_WAIT ) ||
+             ( r_dcache_fsm_save.read() == DCACHE_TLB1_SC_WAIT )|| ( r_dcache_fsm_save.read() == DCACHE_TLB2_SC_WAIT ) || 
+             ( r_dcache_fsm_save.read() == DCACHE_TLB1_UPDT )   || ( r_dcache_fsm_save.read() == DCACHE_TLB2_UPDT ))   && (dreq.valid) )
+        {
+            m_cost_data_tlb_miss_frz++;
+        }
+
+        r_tgt_dcache_rsp = r_dcache.inval(r_tgt_addr.read());
+        if ( r_tgt_broadcast )
+        {
+            r_dcache_tlb_inval_req = true;
+            r_dcache_fsm = DCACHE_TLB_CC_INVAL;        
+        }
+        else
+        {
+            r_tgt_dcache_req = false;
+            r_dcache_fsm = r_dcache_fsm_save;        
+        }    
+        break;
+    }
+    ///////////////////
+    case DCACHE_CC_NOP:     // no external hit
+    {
+        /* activity counter */
+        if ( (( r_dcache_fsm_save.read() == DCACHE_BIS ) ||( r_dcache_fsm_save.read() == DCACHE_MISS_WAIT ) || ( r_dcache_fsm_save.read() == DCACHE_MISS_UPDT ) ) && ( dreq.valid ) )        
+        {
+            m_cost_data_miss_frz++;
+        }
+        if( (( r_dcache_fsm_save.read() == DCACHE_TLB1_READ )   || ( r_dcache_fsm_save.read() == DCACHE_TLB2_READ )    ||
+             ( r_dcache_fsm_save.read() == DCACHE_TLB1_LL_WAIT )|| ( r_dcache_fsm_save.read() == DCACHE_TLB2_LL_WAIT ) ||
+             ( r_dcache_fsm_save.read() == DCACHE_TLB1_SC_WAIT )|| ( r_dcache_fsm_save.read() == DCACHE_TLB2_SC_WAIT ) || 
+             ( r_dcache_fsm_save.read() == DCACHE_TLB1_UPDT )   || ( r_dcache_fsm_save.read() == DCACHE_TLB2_UPDT ))   && (dreq.valid) )
+        {
+            m_cost_data_tlb_miss_frz++;
+        }
+
+        r_tgt_dcache_rsp = r_tgt_update;
+        if ( r_tgt_broadcast )
+        {
+            r_dcache_tlb_inval_req = true;
+            r_dcache_fsm = DCACHE_TLB_CC_INVAL;        
+        }
+        else
+        {
+            r_tgt_dcache_req = false;
+            r_dcache_fsm = r_dcache_fsm_save;        
+        }    
+        break;
+    }   
+    /////////////////////////
+    case DCACHE_TLB_CC_INVAL:
+    {
+        /* activity counter */
+        if ( (( r_dcache_fsm_save.read() == DCACHE_BIS ) ||( r_dcache_fsm_save.read() == DCACHE_MISS_WAIT ) || ( r_dcache_fsm_save.read() == DCACHE_MISS_UPDT ) ) && ( dreq.valid ) )        
+        {
+            m_cost_data_miss_frz++;
+        }
+        if( (( r_dcache_fsm_save.read() == DCACHE_TLB1_READ )   || ( r_dcache_fsm_save.read() == DCACHE_TLB2_READ )    ||
+             ( r_dcache_fsm_save.read() == DCACHE_TLB1_LL_WAIT )|| ( r_dcache_fsm_save.read() == DCACHE_TLB2_LL_WAIT ) ||
+             ( r_dcache_fsm_save.read() == DCACHE_TLB1_SC_WAIT )|| ( r_dcache_fsm_save.read() == DCACHE_TLB2_SC_WAIT ) || 
+             ( r_dcache_fsm_save.read() == DCACHE_TLB1_UPDT )   || ( r_dcache_fsm_save.read() == DCACHE_TLB2_UPDT ))   && (dreq.valid) )
+        {
+            m_cost_data_tlb_miss_frz++;
+        }
+
+	    if ( r_dcache_tlb_inval_req ) break;
+
+        if( (( r_dcache_fsm_save.read() == DCACHE_TLB1_READ )     || ( r_dcache_fsm_save.read() == DCACHE_TLB2_READ )        ||
+             ( r_dcache_fsm_save.read() == DCACHE_TLB1_LL_WAIT )  || ( r_dcache_fsm_save.read() == DCACHE_TLB2_LL_WAIT )     ||
+             ( r_dcache_fsm_save.read() == DCACHE_TLB1_SC_WAIT )  || ( r_dcache_fsm_save.read() == DCACHE_TLB2_SC_WAIT )     ||
+             ( r_dcache_fsm_save.read() == DCACHE_TLB1_UPDT_SEL ) || ( r_dcache_fsm_save.read() == DCACHE_TLB2_UPDT_SEL )    ||
+             ( r_dcache_fsm_save.read() == DCACHE_LL_DIRTY_WAIT ) || ( r_dcache_fsm_save.read() == DCACHE_SC_DIRTY_WAIT )    ||
+	         ( r_dcache_fsm_save.read() == DCACHE_WRITE_DIRTY )) && 
+           ((r_dcache_tlb_paddr.read() & ~((m_dcache_words<<2)-1)) == r_tgt_addr.read()) ) 
+        {
+            r_dcache_inval_tlb_rsp = true;
+        } 
+
+        if (((r_dcache_fsm_save.read() == DCACHE_BIS)||(r_dcache_fsm_save.read() == DCACHE_MISS_WAIT) ||
+             (r_dcache_fsm_save.read() == DCACHE_UNC_WAIT)||(r_dcache_fsm_save.read() == DCACHE_MISS_UPDT)) && 
+             (r_dcache_tlb_nline.read() == (paddr_t)(r_tgt_addr.read() & ~((m_dcache_words<<2)-1))))
+        {
+            r_dcache_inval_tlb_rsp = true;
+        }
+
+        if( (/*( r_dcache_fsm_save == DCACHE_TLB1_READ )        || ( r_dcache_fsm_save == DCACHE_TLB2_READ )       ||*/
+             ( r_dcache_fsm_save.read() == DCACHE_TLB1_LL_WAIT )     || ( r_dcache_fsm_save.read() == DCACHE_TLB2_LL_WAIT )     ||
+             ( r_dcache_fsm_save.read() == DCACHE_TLB1_SC_WAIT )     || ( r_dcache_fsm_save.read() == DCACHE_TLB2_SC_WAIT )     ||
+             ( r_dcache_fsm_save.read() == DCACHE_TLB1_UPDT_SEL )    || ( r_dcache_fsm_save.read() == DCACHE_TLB2_UPDT_SEL )    ||
+             ( r_dcache_fsm_save.read() == DCACHE_LL_DIRTY_WAIT )    || ( r_dcache_fsm_save.read() == DCACHE_SC_DIRTY_WAIT )    ||
+	         ( r_dcache_fsm_save.read() == DCACHE_WRITE_DIRTY )) && 
+           ((r_dcache_tlb_paddr.read() & ~((m_dcache_words<<2)-1)) == r_tgt_addr.read()) ) 
+        {
+            if ( !r_dcache_cc_hit_t ) 
+            {
+                r_ccinval_dtlb_cpt = r_ccinval_dtlb_cpt + 1;
+            }
+        } 
+
+        r_tgt_dcache_req = false;
+	    r_dtlb_translation_valid = false;
+        r_dcache_ptba_ok = false;        
+        r_dcache_fsm = r_dcache_fsm_save;
+        break;
+    }
+    } // end switch r_dcache_fsm
+
+#ifdef SOCLIB_MODULE_DEBUG
+    std::cout << name() << " Data Response: " << drsp << std::endl;
+#endif
+
+    ////////////////////////////////////////////////////////////////////////////////////
+    //      INVAL DTLB CHECK FSM 
+    ////////////////////////////////////////////////////////////////////////////////////////
+    switch(r_inval_dtlb_fsm) {
+    /////////////////////
+    case INVAL_DTLB_IDLE:
+    {    
+        if ( r_dcache_tlb_inval_req )
+        {
+            paddr_t dpaddr;
+            r_dcache_cc_hit_t = dcache_tlb.translate(dreq.addr, &dpaddr);
+            r_ccinval_dtlb_way = 0;
+            r_ccinval_dtlb_set = 0;
+            r_ccinval_dtlb_cpt = 0;
+            r_inval_dtlb_fsm = INVAL_DTLB_CHECK;    
+        }   
+        break;
+    }    
+    //////////////////////
+    case INVAL_DTLB_CHECK:
+    {
+        size_t way = r_ccinval_dtlb_way; 
+        size_t set = r_ccinval_dtlb_set;
+        bool end = false;
+        bool tlb_hit = dcache_tlb.cccheck((r_tgt_addr.read() >> (uint32_log2(m_dcache_words)+2)), way, set, &way, &set, &end);
+    
+        if ( tlb_hit )
+        {
+            r_ccinval_dtlb_way = way; 
+            r_ccinval_dtlb_set = set;
+            r_dtlb_cc_check_end = end;
+            r_ccinval_dtlb_cpt = r_ccinval_dtlb_cpt + 1;
+            r_inval_dtlb_fsm = INVAL_DTLB_INVAL;    
+        }        
+        else
+        {
+            r_inval_dtlb_fsm = INVAL_DTLB_CLEAR;    
+        }
+        break;
+    }
+    /////////////////////////
+    case INVAL_DTLB_INVAL:
+    {
+        dcache_tlb.ccinval(r_ccinval_dtlb_way, r_ccinval_dtlb_set);
+        if ( !r_dtlb_cc_check_end )
+        {
+            r_inval_dtlb_fsm = INVAL_DTLB_CHECK; 
+        }
+        else
+        {
+            r_inval_dtlb_fsm = INVAL_DTLB_CLEAR;    
+        }
+        break;
+    }
+    ////////////////////
+    case INVAL_DTLB_CLEAR:
+    {
+        r_dcache_tlb_inval_req = false;
+        r_dtlb_cc_check_end = false;
+        r_ccinval_dtlb_way = 0; 
+        r_ccinval_dtlb_set = 0; 
+        r_inval_dtlb_fsm = INVAL_DTLB_IDLE;    
+        break;
+    }    
+    } // end switch r_inval_itlb_fsm
+
+    /////////// execute one iss cycle /////////////////////////////////
+    {
+    uint32_t it = 0;
+    for (size_t i=0; i<(size_t)iss_t::n_irq; i++) if(p_irq[i].read()) it |= (1<<i);
+    m_iss.executeNCycles(1, irsp, drsp, it);
+    }
+
+    ////////////// number of frozen cycles //////////////////////////
+    if ( (ireq.valid && !irsp.valid) || (dreq.valid && !drsp.valid) )
+    {
+        m_cpt_frz_cycles++;
+    }
+
+    ////////////////////////////////////////////////////////////////////////////
+    //     VCI_CMD FSM 
+    //
+    // This FSM handles requests from both the DCACHE controler
+    // (request registers) and the ICACHE controler (request registers).
+    // There is 10 VCI transaction types :
+    // - INS_TLB_READ
+    // - INS_TLB_WRITE
+    // - INS_MISS
+    // - INS_UNC_MISS
+    // - DATA_TLB_READ
+    // - DATA_TLB_WRITE
+    // - DATA_TLB_DIRTY
+    // - DATA_MISS
+    // - DATA_UNC 
+    // - DATA_WRITE
+    // The ICACHE requests have the highest priority.
+    // There is at most one (CMD/RSP) VCI transaction, as both CMD_FSM and RSP_FSM
+    // exit simultaneously the IDLE state.
+    //////////////////////////////////////////////////////////////////////////////
+
+    switch (r_vci_cmd_fsm) {
+    
+    case CMD_IDLE:
+        if (r_vci_rsp_fsm != RSP_IDLE)
+            break;
+
+        r_vci_cmd_cpt = 0;
+
+        if (r_icache_cleanup_req)
+        {
+            r_vci_cmd_fsm = CMD_INS_CLEANUP;
+            m_cpt_icleanup_transaction++;
+        }
+        else if (r_dcache_cleanup_req)
+        {
+            r_vci_cmd_fsm = CMD_DATA_CLEANUP;
+            m_cpt_dcleanup_transaction++;
+        }        
+        else if (r_icache_tlb_read_req)           
+        {            
+            r_vci_cmd_fsm = CMD_ITLB_READ;
+            m_cpt_itlbmiss_transaction++; 
+        } 
+        else if (r_icache_tlb_ll_req)      
+        {  
+            r_vci_cmd_fsm = CMD_ITLB_ACC_LL;
+            m_cpt_itlb_ll_transaction++; 
+        } 
+        else if (r_icache_tlb_sc_req)      
+        {  
+            r_vci_cmd_fsm = CMD_ITLB_ACC_SC;
+            m_cpt_itlb_sc_transaction++; 
+        } 
+        else if (r_icache_miss_req) 
+        {    
+            r_vci_cmd_fsm = CMD_INS_MISS;
+            m_cpt_imiss_transaction++; 
+        }
+        else if (r_icache_unc_req) 
+        {    
+            r_vci_cmd_fsm = CMD_INS_UNC;
+            m_cpt_icache_unc_transaction++; 
+        }  
+        else if (r_dcache_tlb_read_req) 
+        {            
+            r_vci_cmd_fsm = CMD_DTLB_READ;
+            m_cpt_dtlbmiss_transaction++; 
+        } 
+        else if (r_dcache_tlb_ll_acc_req) 
+        {  
+            r_vci_cmd_fsm = CMD_DTLB_ACC_LL;
+            m_cpt_dtlb_ll_transaction++; 
+        } 
+        else if (r_dcache_tlb_sc_acc_req) 
+        {  
+            r_vci_cmd_fsm = CMD_DTLB_ACC_SC;
+            m_cpt_dtlb_sc_transaction++; 
+        } 
+        else if (r_dcache_tlb_ll_dirty_req) 
+        {  
+            r_vci_cmd_fsm = CMD_DTLB_DIRTY_LL;
+            m_cpt_dtlb_ll_dirty_transaction++; 
+        } 
+        else if (r_dcache_tlb_sc_dirty_req) 
+        {  
+            r_vci_cmd_fsm = CMD_DTLB_DIRTY_SC;
+            m_cpt_dtlb_sc_dirty_transaction++; 
+        } 
+        else if (r_dcache_write_req)
+        {
+            r_vci_cmd_fsm = CMD_DATA_WRITE;
+            r_vci_cmd_cpt = r_wbuf.getMin();
+            r_vci_cmd_min = r_wbuf.getMin();
+            r_vci_cmd_max = r_wbuf.getMax(); 
+            m_cpt_write_transaction++; 
+            m_length_write_transaction += (r_wbuf.getMax() - r_wbuf.getMin() + 1);
+        }
+        else if (r_dcache_miss_req)  
+        {
+            r_vci_cmd_fsm = CMD_DATA_MISS;
+            m_cpt_dmiss_transaction++; 
+        }
+        else if (r_dcache_unc_req)  
+        {
+            r_vci_cmd_fsm = CMD_DATA_UNC;
+            m_cpt_unc_transaction++; 
+        }
+        break;
+
+    case CMD_DATA_WRITE:
+        if ( p_vci_ini_rw.cmdack.read() ) 
+        {
+            r_vci_cmd_cpt = r_vci_cmd_cpt + 1;
+            if (r_vci_cmd_cpt == r_vci_cmd_max) 
+            {
+                r_vci_cmd_fsm = CMD_IDLE;
+                r_wbuf.reset();
+            }
+        }
+        break;
+
+    case CMD_INS_CLEANUP:
+    case CMD_DATA_CLEANUP:
+        if ( p_vci_ini_c.cmdack.read() ) 
+	    {
+            r_vci_cmd_fsm = CMD_IDLE;
+        }
+        break;
+
+    default:
+        if ( p_vci_ini_rw.cmdack.read() )
+        {  
+            r_vci_cmd_fsm = CMD_IDLE;
+        }
+        break;
+
+    } // end  switch r_vci_cmd_fsm
+
+    //////////////////////////////////////////////////////////////////////////
+    //      VCI_RSP FSM 
+    //
+    // This FSM is synchronized with the VCI_CMD FSM, as both FSMs exit the
+    // IDLE state simultaneously.
+    //////////////////////////////////////////////////////////////////////////
+
+    switch (r_vci_rsp_fsm) {
+
+    case RSP_IDLE:
+        assert( !p_vci_ini_rw.rspval.read() && !p_vci_ini_c.rspval.read() && "Unexpected response" );
+
+        if (r_vci_cmd_fsm != CMD_IDLE)
+            break;
+
+        r_vci_rsp_cpt = 0;
+        if (r_icache_cleanup_req)	     // ICACHE cleanup response 
+        {
+            r_vci_rsp_fsm = RSP_INS_CLEANUP;
+        }
+        else if (r_dcache_cleanup_req)	     // DCACHE cleanup response
+        {
+            r_vci_rsp_fsm = RSP_DATA_CLEANUP;
+        }        
+        else if (r_icache_tlb_read_req)          // ITLB miss response
+        {            
+            r_vci_rsp_fsm = RSP_ITLB_READ;
+        } 
+        else if (r_icache_tlb_ll_req)       // ITLB linked load response
+        {   
+            r_vci_rsp_fsm = RSP_ITLB_ACC_LL;
+        } 
+        else if (r_icache_tlb_sc_req)       // ITLB linked load response
+        {   
+            r_vci_rsp_fsm = RSP_ITLB_ACC_SC;
+        }         
+        else if (r_icache_miss_req)         // ICACHE cached miss response
+        {   
+            r_vci_rsp_fsm = RSP_INS_MISS;
+        }
+        else if (r_icache_unc_req)          // ICACHE uncached miss response
+        {   
+            r_vci_rsp_fsm = RSP_INS_UNC;
+        }  
+        else if (r_dcache_tlb_read_req)     // ITLB miss response
+        {
+            r_vci_rsp_fsm = RSP_DTLB_READ; 
+        }
+        else if (r_dcache_tlb_ll_acc_req)    // DTLB access bits linked load response
+        {
+            r_vci_rsp_fsm = RSP_DTLB_ACC_LL; 
+        }
+        else if (r_dcache_tlb_sc_acc_req)    // DTLB access bits store conditional response
+        {
+            r_vci_rsp_fsm = RSP_DTLB_ACC_SC; 
+        }
+        else if (r_dcache_tlb_ll_dirty_req)  // DTLB dirty bit linked load response
+        {
+            r_vci_rsp_fsm = RSP_DTLB_DIRTY_LL; 
+        }
+        else if (r_dcache_tlb_sc_dirty_req)  // DTLB dirty bit store conditional response
+        {
+            r_vci_rsp_fsm = RSP_DTLB_DIRTY_SC; 
+        }
+        else if (r_dcache_write_req)        // DCACHE write request
+        {
+            r_vci_rsp_fsm = RSP_DATA_WRITE;
+        }
+        else if (r_dcache_miss_req)         // DCACHE read request
+        {
+            r_vci_rsp_fsm = RSP_DATA_MISS;
+        }
+        else if (r_dcache_unc_req)          // DCACHE uncached read request
+        {
+            r_vci_rsp_fsm = RSP_DATA_UNC;
+        }
+        break;
+
+    case RSP_ITLB_READ:
+        m_cost_itlbmiss_transaction++;
+        if ( ! p_vci_ini_rw.rspval.read() )
+            break;
+
+        r_vci_rsp_cpt = r_vci_rsp_cpt + 1;
+        r_icache_miss_buf[r_vci_rsp_cpt] = (data_t)p_vci_ini_rw.rdata.read();
+        if ( p_vci_ini_rw.reop.read() ) 
+        {
+            if ( r_icache_tlb_first_req )
+            {
+                assert( (r_vci_rsp_cpt == 0)  &&
+                    "illegal VCI response packet for data read uncached");
+            }
+            else
+            {
+                assert( (r_vci_rsp_cpt == 1)  &&
+                       "The VCI response packet for instruction miss is too short");
+            }
+
+            r_icache_tlb_read_req = false;
+            r_icache_tlb_first_req = false;
+            r_vci_rsp_fsm = RSP_IDLE;
+        } 
+        if ( p_vci_ini_rw.rerror.read() != vci_param::ERR_NORMAL )
+        {
+            r_vci_rsp_ins_error = true;
+        }
+        break;
+
+    case RSP_ITLB_ACC_LL:
+        m_cost_itlb_ll_transaction++;
+        if ( ! p_vci_ini_rw.rspval.read() )
+            break;
+
+        assert(p_vci_ini_rw.reop.read() &&
+               "illegal VCI response packet for ll tlb");
+
+        if ( p_vci_ini_rw.rerror.read() != vci_param::ERR_NORMAL ) 
+        {
+            r_vci_rsp_ins_error = true;
+        }
+	    else
+	    {
+	        r_icache_miss_buf[0] = (data_t)p_vci_ini_rw.rdata.read();
+	    }
+        r_icache_tlb_ll_req = false;
+        r_vci_rsp_fsm = RSP_IDLE;
+	    break;
+
+    case RSP_ITLB_ACC_SC:
+        m_cost_itlb_sc_transaction++;
+        if ( ! p_vci_ini_rw.rspval.read() )
+            break;
+
+        assert(p_vci_ini_rw.reop.read() &&
+               "illegal VCI response packet for sc tlb");
+
+        if ( p_vci_ini_rw.rerror.read() != vci_param::ERR_NORMAL ) 
+        {
+            r_vci_rsp_ins_error = true;
+        }
+	    else if ( p_vci_ini_rw.rdata.read() == 1 ) // store conditional is not successful
+	    {
+            r_icache_tlb_sc_fail = true;
+	    }
+        r_icache_tlb_sc_req = false;
+        r_vci_rsp_fsm = RSP_IDLE;
+	    break;
+
+    case RSP_INS_MISS:
+        m_cost_imiss_transaction++;
+        if ( ! p_vci_ini_rw.rspval.read() )
+            break;
+
+        assert( (r_vci_rsp_cpt < m_icache_words) && 
+               "The VCI response packet for instruction miss is too long");
+        r_vci_rsp_cpt = r_vci_rsp_cpt + 1;
+        r_icache_miss_buf[r_vci_rsp_cpt] = (data_t)p_vci_ini_rw.rdata.read();
+
+        if ( p_vci_ini_rw.reop.read() ) 
+        {
+            assert( (r_vci_rsp_cpt == m_icache_words - 1) &&
+                       "The VCI response packet for instruction miss is too short");
+            r_icache_miss_req = false;
+            r_vci_rsp_fsm = RSP_IDLE;
+        } 
+        if ( p_vci_ini_rw.rerror.read() != vci_param::ERR_NORMAL )
+        {
+            r_vci_rsp_ins_error = true;
+        }
+        break;
+
+    case RSP_INS_UNC:
+        m_cost_icache_unc_transaction++;
+        if ( ! p_vci_ini_rw.rspval.read() )
+            break;
+
+        assert(p_vci_ini_rw.reop.read() &&
+               "illegal VCI response packet for uncached instruction");
+
+        r_icache_miss_buf[0] = (data_t)p_vci_ini_rw.rdata.read();
+        r_icache_buf_unc_valid = true;
+        r_icache_unc_req = false;
+        r_vci_rsp_fsm = RSP_IDLE;
+
+        if ( p_vci_ini_rw.rerror.read() != vci_param::ERR_NORMAL )
+        {
+            r_vci_rsp_ins_error = true;
+        }
+        break;
+
+    case RSP_DTLB_READ:
+        m_cost_dtlbmiss_transaction++;
+        if ( ! p_vci_ini_rw.rspval.read() )
+            break;
+
+        r_vci_rsp_cpt = r_vci_rsp_cpt + 1;
+        r_dcache_miss_buf[r_vci_rsp_cpt] = (data_t)p_vci_ini_rw.rdata.read();
+        if ( p_vci_ini_rw.reop.read() ) 
+        {
+            if ( r_dcache_tlb_first_req )
+            {
+                assert( (r_vci_rsp_cpt == 0)  &&
+                    "illegal VCI response packet for data read uncached");
+            }
+            else
+            {
+                assert( (r_vci_rsp_cpt == 1)  &&
+                       "The VCI response packet for instruction miss is too short");
+            }
+
+            r_dcache_tlb_read_req = false;
+            r_dcache_tlb_first_req = false;
+            r_vci_rsp_fsm = RSP_IDLE;
+        } 
+        if ( p_vci_ini_rw.rerror.read() != vci_param::ERR_NORMAL )
+        {
+            r_vci_rsp_data_error = true;
+        }
+        break;
+
+    case RSP_DTLB_ACC_LL:
+        m_cost_dtlb_ll_transaction++;
+        if ( ! p_vci_ini_rw.rspval.read() )
+            break;
+
+        assert(p_vci_ini_rw.reop.read() &&
+               "illegal VCI response packet for ll tlb");
+
+        if ( p_vci_ini_rw.rerror.read() != vci_param::ERR_NORMAL ) 
+        {
+            r_vci_rsp_data_error = true;
+        }
+	    else
+	    {
+	        r_dcache_miss_buf[0] = (data_t)p_vci_ini_rw.rdata.read();
+	    }
+        r_dcache_tlb_ll_acc_req = false;
+        r_vci_rsp_fsm = RSP_IDLE;
+	    break;
+
+    case RSP_DTLB_ACC_SC:
+        m_cost_dtlb_sc_transaction++; 
+        if ( ! p_vci_ini_rw.rspval.read() )
+            break;
+
+        assert(p_vci_ini_rw.reop.read() &&
+               "illegal VCI response packet for sc tlb");
+
+        if ( p_vci_ini_rw.rerror.read() != vci_param::ERR_NORMAL ) 
+        {
+            r_vci_rsp_data_error = true;
+        }
+	    else if ( p_vci_ini_rw.rdata.read() == 1 ) // store conditional is not successful
+	    {
+            r_dcache_tlb_sc_fail = true;
+	    }
+        r_dcache_tlb_sc_acc_req = false;
+        r_vci_rsp_fsm = RSP_IDLE;
+	    break;
+
+    case RSP_DTLB_DIRTY_LL:
+        m_cost_dtlb_ll_dirty_transaction++; 
+        if ( ! p_vci_ini_rw.rspval.read() )
+            break;
+
+        assert(p_vci_ini_rw.reop.read() &&
+               "illegal VCI response packet for ll tlb");
+
+        if ( p_vci_ini_rw.rerror.read() != vci_param::ERR_NORMAL ) 
+        {
+            r_vci_rsp_data_error = true;
+        }
+	    else
+	    {
+	        r_dcache_miss_buf[0] = (data_t)p_vci_ini_rw.rdata.read();
+	    }
+        r_dcache_tlb_ll_dirty_req = false;
+        r_vci_rsp_fsm = RSP_IDLE;
+	    break;
+
+    case RSP_DTLB_DIRTY_SC:
+        m_cost_dtlb_sc_dirty_transaction++; 
+        if ( ! p_vci_ini_rw.rspval.read() )
+            break;
+
+        assert(p_vci_ini_rw.reop.read() &&
+               "illegal VCI response packet for sc tlb");
+
+        if ( p_vci_ini_rw.rerror.read() != vci_param::ERR_NORMAL ) 
+        {
+            r_vci_rsp_data_error = true;
+        }
+	    else if ( p_vci_ini_rw.rdata.read() == 1 ) // store conditional is not successful
+	    {
+            r_dcache_tlb_sc_fail = true;
+	    }
+        r_dcache_tlb_sc_dirty_req = false;
+        r_vci_rsp_fsm = RSP_IDLE;
+	    break;
+
+    case RSP_DATA_UNC:
+        m_cost_unc_transaction++;
+        if ( ! p_vci_ini_rw.rspval.read() ) 
+            break;
+
+        assert(p_vci_ini_rw.reop.read() &&
+               "illegal VCI response packet for data read uncached");
+
+        if ( p_vci_ini_rw.rerror.read() != vci_param::ERR_NORMAL ) 
+        {
+            r_vci_rsp_data_error = true;
+        }
+        else
+        {
+            r_dcache_miss_buf[0] = (data_t)p_vci_ini_rw.rdata.read();
+            r_dcache_buf_unc_valid = true;
+        }
+        r_dcache_unc_req = false;
+        r_vci_rsp_fsm = RSP_IDLE;
+        break;
+
+    case RSP_DATA_MISS:
+        m_cost_dmiss_transaction++;
+        if ( ! p_vci_ini_rw.rspval.read() )
+            break;
+
+        assert(r_vci_rsp_cpt != m_dcache_words &&
+               "illegal VCI response packet for data read miss");
+
+        r_vci_rsp_cpt = r_vci_rsp_cpt + 1;
+        r_dcache_miss_buf[r_vci_rsp_cpt] = (data_t)p_vci_ini_rw.rdata.read();
+        if ( p_vci_ini_rw.reop.read() ) 
+        {
+            assert(r_vci_rsp_cpt == m_dcache_words - 1 &&
+                    "illegal VCI response packet for data read miss");
+            r_dcache_miss_req = false;
+            r_vci_rsp_fsm = RSP_IDLE;
+        } 
+        if ( p_vci_ini_rw.rerror.read() != vci_param::ERR_NORMAL )
+        {
+            r_vci_rsp_data_error = true;
+        }
+        break;
+
+    case RSP_DATA_WRITE:
+        m_cost_write_transaction++;
+        if ( ! p_vci_ini_rw.rspval.read() )
+            break;
+
+        if ( p_vci_ini_rw.reop.read() ) 
+        {
+            r_vci_rsp_fsm = RSP_IDLE;
+            r_dcache_write_req = false;
+        }
+        if ( p_vci_ini_rw.rerror.read() != vci_param::ERR_NORMAL ) 
+        {
+            m_iss.setWriteBerr();
+        }
+        break; 
+
+    case RSP_INS_CLEANUP:
+    case RSP_DATA_CLEANUP:
+        if ( r_vci_rsp_fsm == RSP_INS_CLEANUP ) 
+        {
+            m_cost_icleanup_transaction++;
+        }
+        else
+        {                                    
+            m_cost_dcleanup_transaction++;
+        }
+
+        if ( ! p_vci_ini_c.rspval.read() )
+            break;
+        assert( p_vci_ini_c.reop.read() &&
+                "illegal VCI response packet for icache cleanup");
+        assert( (p_vci_ini_c.rerror.read() == vci_param::ERR_NORMAL) &&
+                "error in response packet for icache cleanup");
+
+        if ( r_vci_rsp_fsm == RSP_INS_CLEANUP ) 
+        {
+            r_icache_cleanup_req = false;
+        }
+        else
+        {                                    
+            r_dcache_cleanup_req = false;
+        }
+        r_vci_rsp_fsm = RSP_IDLE;
+        break;
+    } // end switch r_vci_rsp_fsm
+} // end transition()
+
+///////////////////////
+tmpl(void)::genMoore()
+///////////////////////
+{
+    // VCI initiator response
+
+    p_vci_ini_rw.rspack = true;
+    p_vci_ini_c.rspack = true;
+
+    // VCI initiator command
+
+    p_vci_ini_rw.pktid  = 0;
+    p_vci_ini_rw.srcid  = m_srcid_rw;
+    p_vci_ini_rw.cons   = false;
+    p_vci_ini_rw.wrap   = false;
+    p_vci_ini_rw.contig = true;
+    p_vci_ini_rw.clen   = 0;
+    p_vci_ini_rw.cfixed = false;
+
+    p_vci_ini_c.cmdval  = false;
+    p_vci_ini_c.address = 0;
+    p_vci_ini_c.wdata   = 0;
+    p_vci_ini_c.be      = 0;
+    p_vci_ini_c.plen    = 0;
+    p_vci_ini_c.cmd     = vci_param::CMD_NOP;
+    p_vci_ini_c.trdid   = 0;
+    p_vci_ini_c.pktid   = 0;
+    p_vci_ini_c.srcid   = 0;
+    p_vci_ini_c.cons    = false;
+    p_vci_ini_c.wrap    = false;
+    p_vci_ini_c.contig  = false;
+    p_vci_ini_c.clen    = 0;
+    p_vci_ini_c.cfixed  = false;
+    p_vci_ini_c.eop     = false;
+    
+    switch (r_vci_cmd_fsm) {
+
+    case CMD_IDLE:
+        p_vci_ini_rw.cmdval  = false;
+        p_vci_ini_rw.address = 0;
+        p_vci_ini_rw.wdata   = 0;
+        p_vci_ini_rw.be      = 0;
+        p_vci_ini_rw.trdid   = 0;
+        p_vci_ini_rw.plen    = 0;
+        p_vci_ini_rw.cmd     = vci_param::CMD_NOP;
+        p_vci_ini_rw.eop     = false;
+        break;
+
+    case CMD_ITLB_READ:     
+        p_vci_ini_rw.cmdval  = true;
+        p_vci_ini_rw.wdata   = 0;
+        p_vci_ini_rw.be      = 0xF;
+        if ( r_icache_tlb_first_req )
+        { 
+            p_vci_ini_rw.address = r_icache_paddr_save.read() & ~0x3;
+            p_vci_ini_rw.trdid = 6; // ins TLB uncached read
+            p_vci_ini_rw.plen  = 4;
+        }
+        else
+        { 
+            p_vci_ini_rw.address = r_icache_paddr_save.read() & ~0x3;
+            p_vci_ini_rw.trdid = 7; // ins TLB cached read 2 words
+            p_vci_ini_rw.plen  = 8; 
+        }
+        p_vci_ini_rw.cmd     = vci_param::CMD_READ;
+        p_vci_ini_rw.eop     = true;
+        break;
+
+    case CMD_ITLB_ACC_LL:
+        p_vci_ini_rw.cmdval  = true;
+        p_vci_ini_rw.address = r_icache_paddr_save.read() & ~0x3;
+        p_vci_ini_rw.wdata   = 0;
+        p_vci_ini_rw.be      = 0xF;
+        p_vci_ini_rw.trdid   = 6; // ins TLB uncached read
+        p_vci_ini_rw.plen    = 4;
+        p_vci_ini_rw.cmd     = vci_param::CMD_LOCKED_READ;
+        p_vci_ini_rw.eop     = true;
+	break;
+
+    case CMD_ITLB_ACC_SC:
+        p_vci_ini_rw.cmdval  = true;
+        p_vci_ini_rw.address = r_icache_paddr_save.read() & ~0x3;
+        p_vci_ini_rw.wdata   = r_icache_pte_update.read();
+        p_vci_ini_rw.be      = 0xF;
+        p_vci_ini_rw.trdid   = 6; // ins TLB uncached read
+        p_vci_ini_rw.plen    = 4;
+        p_vci_ini_rw.cmd     = vci_param::CMD_STORE_COND;
+        p_vci_ini_rw.eop     = true;
+	break;	
+
+    case CMD_INS_MISS:
+        p_vci_ini_rw.cmdval  = true;
+        p_vci_ini_rw.address = r_icache_paddr_save.read() & m_icache_yzmask;
+        p_vci_ini_rw.wdata   = 0;
+        p_vci_ini_rw.be      = 0xF;
+        p_vci_ini_rw.trdid   = 3;
+        p_vci_ini_rw.plen    = m_icache_words << 2;
+        p_vci_ini_rw.cmd     = vci_param::CMD_READ;
+        p_vci_ini_rw.eop     = true;
+        break;
+
+    case CMD_INS_UNC:
+        p_vci_ini_rw.cmdval  = true;
+        p_vci_ini_rw.address = r_icache_paddr_save.read() & ~0x3;
+        p_vci_ini_rw.wdata   = 0;
+        p_vci_ini_rw.be      = 0xF;
+        p_vci_ini_rw.trdid   = 2;
+        p_vci_ini_rw.plen    = 4;
+        p_vci_ini_rw.cmd     = vci_param::CMD_READ;
+        p_vci_ini_rw.eop     = true;
+        break;
+
+    case CMD_DTLB_READ:     
+        p_vci_ini_rw.cmdval  = true;
+        p_vci_ini_rw.wdata   = 0;
+        p_vci_ini_rw.be      = 0xF;
+        if ( r_dcache_tlb_first_req ) 
+        {
+            p_vci_ini_rw.address = r_dcache_tlb_paddr.read() & ~0x3;
+            p_vci_ini_rw.trdid = 4; // data TLB uncached read
+            p_vci_ini_rw.plen  = 4;
+        }
+        else
+        { 
+            p_vci_ini_rw.address = r_dcache_tlb_paddr.read() & ~0x3;
+            p_vci_ini_rw.trdid = 5; // data TLB cached read 2 words
+            p_vci_ini_rw.plen  = 8; 
+        }
+        p_vci_ini_rw.cmd     = vci_param::CMD_READ;
+        p_vci_ini_rw.eop     = true;
+        break;
+
+    case CMD_DTLB_ACC_LL:
+        p_vci_ini_rw.cmdval  = true;
+        p_vci_ini_rw.address = r_dcache_tlb_paddr.read() & ~0x3;
+        p_vci_ini_rw.wdata   = 0;
+        p_vci_ini_rw.be      = 0xF;
+        p_vci_ini_rw.trdid   = 4; // data TLB uncached read
+        p_vci_ini_rw.plen    = 4;
+        p_vci_ini_rw.cmd     = vci_param::CMD_LOCKED_READ;
+        p_vci_ini_rw.eop     = true;
+	break;
+
+    case CMD_DTLB_ACC_SC:
+        p_vci_ini_rw.cmdval  = true;
+        p_vci_ini_rw.address = r_dcache_tlb_paddr.read() & ~0x3;
+        p_vci_ini_rw.wdata   = r_dcache_pte_update.read();
+        p_vci_ini_rw.be      = 0xF;
+        p_vci_ini_rw.trdid   = 4; // data TLB uncached read
+        p_vci_ini_rw.plen    = 4;
+        p_vci_ini_rw.cmd     = vci_param::CMD_STORE_COND;
+        p_vci_ini_rw.eop     = true;
+	break;	
+
+    case CMD_DTLB_DIRTY_LL:
+        p_vci_ini_rw.cmdval  = true;
+        p_vci_ini_rw.address = r_dcache_tlb_paddr.read() & ~0x3;
+        p_vci_ini_rw.wdata   = 0;
+        p_vci_ini_rw.be      = 0xF;
+        p_vci_ini_rw.trdid   = 4; // data TLB uncached read
+        p_vci_ini_rw.plen    = 4;
+        p_vci_ini_rw.cmd     = vci_param::CMD_LOCKED_READ;
+        p_vci_ini_rw.eop     = true;
+	break;
+
+    case CMD_DTLB_DIRTY_SC:
+        p_vci_ini_rw.cmdval  = true;
+        p_vci_ini_rw.address = r_dcache_tlb_paddr.read() & ~0x3;
+        p_vci_ini_rw.wdata   = r_dcache_pte_update.read();
+        p_vci_ini_rw.be      = 0xF;
+        p_vci_ini_rw.trdid   = 4; // data TLB uncached read
+        p_vci_ini_rw.plen    = 4;
+        p_vci_ini_rw.cmd     = vci_param::CMD_STORE_COND;
+        p_vci_ini_rw.eop     = true;
+	break;	
+
+    case CMD_DATA_UNC:
+        p_vci_ini_rw.cmdval  = true;
+        p_vci_ini_rw.address = r_dcache_paddr_save.read() & ~0x3;
+        p_vci_ini_rw.trdid   = 0;
+        p_vci_ini_rw.plen    = 4;
+        p_vci_ini_rw.eop     = true;
+        switch(r_dcache_type_save) {
+        case iss_t::DATA_READ:
+            p_vci_ini_rw.wdata = 0;
+            p_vci_ini_rw.be    = r_dcache_be_save.read();
+            p_vci_ini_rw.cmd   = vci_param::CMD_READ;
+            break;
+        case iss_t::DATA_LL:
+            p_vci_ini_rw.wdata = 0;
+            p_vci_ini_rw.be    = 0xF;
+            p_vci_ini_rw.cmd   = vci_param::CMD_LOCKED_READ;
+            break;
+        case iss_t::DATA_SC:
+            p_vci_ini_rw.wdata = r_dcache_wdata_save.read();
+            p_vci_ini_rw.be    = 0xF;
+            p_vci_ini_rw.cmd   = vci_param::CMD_STORE_COND;
+            break;
+        default:
+            assert("this should not happen");
+        }
+        break;
+
+    case CMD_DATA_WRITE:
+        p_vci_ini_rw.cmdval  = true;
+        p_vci_ini_rw.address = r_wbuf.getAddress(r_vci_cmd_cpt);
+        p_vci_ini_rw.wdata   = r_wbuf.getData(r_vci_cmd_cpt);
+        p_vci_ini_rw.be      = r_wbuf.getBe(r_vci_cmd_cpt);
+        p_vci_ini_rw.trdid   = 0;
+        p_vci_ini_rw.plen    = (r_vci_cmd_max - r_vci_cmd_min + 1)<<2;
+        p_vci_ini_rw.cmd     = vci_param::CMD_WRITE;
+        p_vci_ini_rw.eop     = (r_vci_cmd_cpt == r_vci_cmd_max);
+        break;
+
+    case CMD_DATA_MISS:
+        p_vci_ini_rw.cmdval  = true;
+        p_vci_ini_rw.address = r_dcache_paddr_save.read() & m_dcache_yzmask;
+        p_vci_ini_rw.wdata   = 0;
+        p_vci_ini_rw.be      = 0xF;
+        p_vci_ini_rw.trdid   = 1;
+        p_vci_ini_rw.plen    = m_dcache_words << 2;
+        p_vci_ini_rw.cmd     = vci_param::CMD_READ;
+        p_vci_ini_rw.eop     = true;
+        break;
+
+    case CMD_INS_CLEANUP:
+    case CMD_DATA_CLEANUP:
+        p_vci_ini_rw.cmdval = false;
+        p_vci_ini_rw.address = 0;
+        p_vci_ini_rw.wdata  = 0;
+        p_vci_ini_rw.be     = 0;
+        p_vci_ini_rw.trdid  = 0;
+        p_vci_ini_rw.plen   = 0;
+        p_vci_ini_rw.cmd    = vci_param::CMD_NOP;
+        p_vci_ini_rw.eop    = false;
+
+        p_vci_ini_c.cmdval = true;
+        if ( r_vci_cmd_fsm == CMD_INS_CLEANUP ) 
+        {    
+            p_vci_ini_c.address = r_icache_cleanup_line.read() * (m_icache_words<<2);
+            if ( r_icache_cleanup_type == TLB_CLEANUP )
+            {    
+                p_vci_ini_c.trdid  = 3; // ins TLB cleanup 
+            }
+            else
+            {
+                p_vci_ini_c.trdid  = 1; // ins cleanup       
+            }    
+        }    
+        else
+        {    
+            p_vci_ini_c.address = r_dcache_cleanup_line.read() * (m_dcache_words<<2);
+            if ( r_dcache_cleanup_type == TLB_CLEANUP )
+            {    
+                p_vci_ini_c.trdid  = 2; // data TLB cleanup 
+            }
+            else
+            {
+                p_vci_ini_c.trdid  = 0; // data cleanup       
+            }    
+        }   
+        p_vci_ini_c.wdata  = 0;
+        p_vci_ini_c.be     = 0;
+        p_vci_ini_c.plen   = 4;
+        p_vci_ini_c.cmd    = vci_param::CMD_WRITE;
+        p_vci_ini_c.pktid  = 0;
+        p_vci_ini_c.srcid  = m_srcid_c;
+        p_vci_ini_c.cons   = false;
+        p_vci_ini_c.wrap   = false;
+        p_vci_ini_c.contig = false;
+        p_vci_ini_c.clen   = 0;
+        p_vci_ini_c.cfixed = false;
+        p_vci_ini_c.eop = true;
+        break;
+
+    } // end switch r_vci_cmd_fsm
+
+    // VCI_TGT
+    switch ( r_vci_tgt_fsm.read() ) {
+
+    case TGT_IDLE:
+    case TGT_UPDT_WORD:
+    case TGT_UPDT_DATA:
+        p_vci_tgt.cmdack  = true;
+        p_vci_tgt.rspval  = false;
+        break;
+
+    case TGT_RSP_BROADCAST:
+        p_vci_tgt.cmdack  = false;
+        p_vci_tgt.rspval  = !r_tgt_icache_req.read() && !r_tgt_dcache_req.read() && 
+                            ( r_tgt_icache_rsp | r_tgt_dcache_rsp | r_ccinval_itlb_cpt | r_ccinval_dtlb_cpt );
+        p_vci_tgt.rsrcid  = r_tgt_srcid.read();
+        p_vci_tgt.rpktid  = r_tgt_pktid.read();
+        p_vci_tgt.rtrdid  = r_tgt_trdid.read();
+        p_vci_tgt.rdata   = 0;
+        p_vci_tgt.rerror  = 0;
+        p_vci_tgt.reop    = true;
+        break;
+
+    case TGT_RSP_ICACHE:
+        p_vci_tgt.cmdack  = false;
+        p_vci_tgt.rspval  = !r_tgt_icache_req.read() && r_tgt_icache_rsp.read();
+        p_vci_tgt.rsrcid  = r_tgt_srcid.read();
+        p_vci_tgt.rpktid  = r_tgt_pktid.read();
+        p_vci_tgt.rtrdid  = r_tgt_trdid.read();
+        p_vci_tgt.rdata   = 0;
+        p_vci_tgt.rerror  = 0;
+        p_vci_tgt.reop    = true;
+        break;
+
+    case TGT_RSP_DCACHE:
+        p_vci_tgt.cmdack  = false;
+        p_vci_tgt.rspval  = !r_tgt_dcache_req.read() && r_tgt_dcache_rsp.read();
+        p_vci_tgt.rsrcid  = r_tgt_srcid.read();
+        p_vci_tgt.rpktid  = r_tgt_pktid.read();
+        p_vci_tgt.rtrdid  = r_tgt_trdid.read();
+        p_vci_tgt.rdata   = 0;
+        p_vci_tgt.rerror  = 0;
+        p_vci_tgt.reop    = true;
+        break;
+
+    case TGT_REQ_BROADCAST:
+    case TGT_REQ_ICACHE:
+    case TGT_REQ_DCACHE:
+        p_vci_tgt.cmdack  = false;
+        p_vci_tgt.rspval  = false;
+        break;
+
+    } // end switch TGT_FSM
+
+#ifdef SOCLIB_MODULE_DEBUG 
+   std::cout << name()  
+             << "Moore:" << std::hex
+             << "p_vci_ini_rw.cmdval:" << p_vci_ini_rw.cmdval
+             << "p_vci_ini_rw.address:" << p_vci_ini_rw.address
+             << "p_vci_ini_rw.wdata:" << p_vci_ini_rw.wdata
+             << "p_vci_ini_rw.cmd:" << p_vci_ini_rw.cmd
+             << "p_vci_ini_rw.eop:" << p_vci_ini_rw.eop
+             << std::endl;
+
+   std::cout << name()  
+             << "Moore:" << std::hex
+             << "p_vci_ini_c.cmdval:" << p_vci_ini_c.cmdval
+             << "p_vci_ini_c.address:" << p_vci_ini_c.address
+             << "p_vci_ini_c.cmd:" << p_vci_ini_c.cmd
+             << "p_vci_ini_c.eop:" << p_vci_ini_c.eop
+             << std::endl;
+
+   std::cout << name()  
+             << "Moore:" << std::hex
+             << "p_vci_tgt.cmdack:" << p_vci_tgt.cmdack
+             << "p_vci_tgt.rspval:" << p_vci_tgt.rspval
+             << "p_vci_tgt.rsrcid:" << p_vci_tgt.rsrcid
+             << "p_vci_tgt.rtrdid:" << p_vci_tgt.rtrdid
+             << "p_vci_tgt.reop:" << p_vci_tgt.reop
+             << std::endl;
+#endif
+}
+
+}}
+
+// Local Variables:
+// tab-width: 4
+// c-basic-offset: 4
+// c-file-offsets:((innamespace . 0)(inline-open . 0))
+// indent-tabs-mode: nil
+// End:
+
+// vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4
+
+
Index: branches/v4/modules/vci_cc_vcache_wrapper_v4/caba/metadata/vci_cc_vcache_wrapper_v4.sd
===================================================================
--- branches/v4/modules/vci_cc_vcache_wrapper_v4/caba/metadata/vci_cc_vcache_wrapper_v4.sd	(revision 371)
+++ branches/v4/modules/vci_cc_vcache_wrapper_v4/caba/metadata/vci_cc_vcache_wrapper_v4.sd	(revision 371)
@@ -0,0 +1,63 @@
+
+# -*- python -*-
+
+__id__ = "$Id: vci_cc_vcache_wrapper_v4.sd 20 2011-10-13  alain $"
+
+Module('caba:vci_cc_vcache_wrapper_v4',
+	classname = 'soclib::caba::VciCcVCacheWrapperV4',
+	tmpl_parameters = [ parameter.Module('vci_param', default = 'caba:vci_param'),
+	                    parameter.Module('iss_t') ],
+	header_files =         [ '../source/include/vci_cc_vcache_wrapper_v4.h' ],
+	implementation_files = [ '../source/src/vci_cc_vcache_wrapper_v4.cpp' ],
+	uses = [ Uses('caba:base_module'),
+	         Uses('common:mapping_table'),
+	         Uses('common:iss2'),
+	         Uses('caba:multi_write_buffer'),
+	         Uses('caba:generic_fifo'),
+	         Uses('caba:generic_cam'),
+	         Uses('caba:generic_llsc_local_table'),
+	         Uses('caba:generic_cache', 
+                       addr_t = parameter.StringExt('sc_dt::sc_uint<%d> ', 
+                       parameter.Reference('addr_size'))),
+	         Uses('caba:generic_tlb', 
+                       addr_t = parameter.StringExt('sc_dt::sc_uint<%d> ', 
+                       parameter.Reference('addr_size'))),
+	         Uses('common:address_masking_table', 
+                       data_t = parameter.StringExt('sc_dt::sc_uint<%d> ', 
+                       parameter.Reference('addr_size'))) ],
+	ports = [ Port('caba:vci_initiator', 'p_vci_ini_d'),
+	          Port('caba:vci_initiator', 'p_vci_ini_c'),
+	          Port('caba:vci_target', 'p_vci_tgt_d'),
+	          Port('caba:bit_in','p_irq', parameter.Constant('n_irq')),
+	          Port('caba:bit_in', 'p_resetn', auto = 'resetn'),
+	          Port('caba:clock_in', 'p_clk', auto = 'clock'), ],
+	instance_parameters = [ parameter.Int('proc_id'),
+	                        parameter.Module('mt', 'common:mapping_table'),
+	                        parameter.Module('mc', 'common:mapping_table'),
+	                        parameter.IntTab('initiator_rw_index'),
+	                        parameter.IntTab('initiator_c_index'),
+	                        parameter.IntTab('target_index'),
+    	                        parameter.Int('itlb_ways'),
+    	                        parameter.Int('itlb_sets'),
+    	                        parameter.Int('dtlb_ways'),
+    	                        parameter.Int('dtlb_sets'),
+    	                        parameter.Int('icache_ways'),
+    	                        parameter.Int('icache_sets'),
+    	                        parameter.Int('icache_words'),
+    	                        parameter.Int('dcache_ways'),
+    	                        parameter.Int('dcache_sets'),
+    	                        parameter.Int('dcache_words'),
+    	                        parameter.Int('wbuf_nlines'),
+    	                        parameter.Int('wbuf_nwords'),
+    	                        parameter.Int('max_frozen_cycles'), ],
+	extensions = [ 'dsx:get_ident='
+                       'initiator_d_index:p_vci_ini_d:mt,'
+                       'initiator_c_index:p_vci_ini_c:mc,'
+                       'target_index:p_vci_tgti_d:mc',
+	               'dsx:cpu=wrapper:iss_t',
+	               'dsx:addressable=target_index',
+                       'dsx:on_segment=mc:add_index:initiator_rw_index',
+	               'dsx:mapping_type=processor:proc_id', ],
+)
+
+
Index: branches/v4/modules/vci_cc_vcache_wrapper_v4/caba/source/include/vci_cc_vcache_wrapper_v4.h
===================================================================
--- branches/v4/modules/vci_cc_vcache_wrapper_v4/caba/source/include/vci_cc_vcache_wrapper_v4.h	(revision 371)
+++ branches/v4/modules/vci_cc_vcache_wrapper_v4/caba/source/include/vci_cc_vcache_wrapper_v4.h	(revision 371)
@@ -0,0 +1,729 @@
+/* -*- c++ -*-
+ * File : vci_cc_vcache_wrapper_v4.h
+ * Copyright (c) UPMC, Lip6, SoC
+ * Authors : Alain GREINER, Yang GAO
+ * Date : 27/11/2011
+ *
+ * SOCLIB_LGPL_HEADER_BEGIN
+ * 
+ * This file is part of SoCLib, GNU LGPLv2.1.
+ * 
+ * SoCLib is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU Lesser General Public License as published
+ * by the Free Software Foundation; version 2.1 of the License.
+ * 
+ * SoCLib is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * Lesser General Public License for more details.
+ * 
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with SoCLib; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301 USA
+ * 
+ * SOCLIB_LGPL_HEADER_END
+ */
+ 
+#ifndef SOCLIB_CABA_VCI_CC_VCACHE_WRAPPER_V4_H
+#define SOCLIB_CABA_VCI_CC_VCACHE_WRAPPER_V4_H
+
+#include <inttypes.h>
+#include <systemc>
+#include "caba_base_module.h"
+#include "multi_write_buffer.h"
+#include "generic_fifo.h"
+#include "generic_tlb.h"
+#include "generic_cache.h"
+#include "generic_cam.h"
+#include "generic_llsc_local_table.h"
+#include "vci_initiator.h"
+#include "vci_target.h"
+#include "mapping_table.h"
+#include "static_assert.h"
+#include "iss2.h"
+
+namespace soclib {
+namespace caba {
+
+using namespace sc_core;
+
+////////////////////////////////////////////
+template<typename vci_param, typename iss_t>
+class VciCcVCacheWrapperV4
+////////////////////////////////////////////
+    : public soclib::caba::BaseModule
+{
+    typedef uint32_t vaddr_t;
+    typedef uint32_t tag_t;
+    typedef uint32_t type_t;
+    typedef typename iss_t::DataOperationType data_op_t;
+
+    typedef typename vci_param::addr_t  paddr_t;
+    typedef typename vci_param::data_t  vci_data_t;
+    typedef typename vci_param::be_t    vci_be_t;
+    typedef typename vci_param::srcid_t vci_srcid_t;
+    typedef typename vci_param::trdid_t vci_trdid_t;
+    typedef typename vci_param::pktid_t vci_pktid_t;
+    typedef typename vci_param::plen_t  vci_plen_t;
+
+    enum icache_fsm_state_e {  
+        ICACHE_IDLE,             
+        // handling XTN processor requests
+        ICACHE_XTN_TLB_FLUSH,
+        ICACHE_XTN_CACHE_FLUSH, 
+        ICACHE_XTN_TLB_INVAL,  
+        ICACHE_XTN_CACHE_INVAL_VA,
+        ICACHE_XTN_CACHE_INVAL_PA,  
+        ICACHE_XTN_CACHE_INVAL_GO,
+        // handling tlb miss
+        ICACHE_TLB_WAIT,
+        // handling cache miss
+        ICACHE_MISS_VICTIM,   
+        ICACHE_MISS_INVAL,   
+        ICACHE_MISS_WAIT,   
+        ICACHE_MISS_UPDT, 
+        // handling unc read
+        ICACHE_UNC_WAIT,  
+        // handling coherence requests
+        ICACHE_CC_CHECK, 
+        ICACHE_CC_INVAL, 
+        ICACHE_CC_UPDT, 
+    };
+
+    enum dcache_fsm_state_e {  
+        DCACHE_IDLE,                
+        // handling itlb & dtlb miss
+        DCACHE_TLB_MISS,
+        DCACHE_TLB_PTE1_GET,           
+        DCACHE_TLB_PTE1_SELECT,      
+        DCACHE_TLB_PTE1_UPDT,       
+        DCACHE_TLB_PTE2_GET,    
+        DCACHE_TLB_PTE2_SELECT,       
+        DCACHE_TLB_PTE2_UPDT,           
+        DCACHE_TLB_LR_UPDT,           
+        DCACHE_TLB_LR_WAIT,           
+        DCACHE_TLB_RETURN,         
+	    // handling processor XTN requests
+        DCACHE_XTN_SWITCH,
+        DCACHE_XTN_SYNC,
+        DCACHE_XTN_IC_INVAL_VA,        
+        DCACHE_XTN_IC_FLUSH,        
+        DCACHE_XTN_IC_INVAL_PA,     
+        DCACHE_XTN_IT_INVAL,          
+        DCACHE_XTN_DC_FLUSH,        
+        DCACHE_XTN_DC_INVAL_VA,        
+        DCACHE_XTN_DC_INVAL_PA,     
+        DCACHE_XTN_DC_INVAL_END,
+        DCACHE_XTN_DC_INVAL_GO,          
+        DCACHE_XTN_DT_INVAL,          
+        //handling dirty bit update
+        DCACHE_DIRTY_GET_PTE,
+        DCACHE_DIRTY_WAIT,           
+	    // handling processor miss requests
+        DCACHE_MISS_VICTIM,
+        DCACHE_MISS_INVAL,
+        DCACHE_MISS_WAIT,           
+        DCACHE_MISS_UPDT,           
+        // handling processor unc, ll and sc requests
+        DCACHE_UNC_WAIT,            
+        DCACHE_LL_WAIT,            
+        DCACHE_SC_WAIT,            
+        // handling coherence requests
+        DCACHE_CC_CHECK,            
+        DCACHE_CC_INVAL,            
+        DCACHE_CC_UPDT,             
+        // handling TLB inval (after a coherence or XTN request)
+        DCACHE_INVAL_TLB_SCAN,             
+    };
+
+    enum cmd_fsm_state_e {      
+        CMD_IDLE,
+        CMD_INS_MISS,
+        CMD_INS_UNC,
+        CMD_DATA_MISS,
+        CMD_DATA_UNC,
+        CMD_DATA_WRITE,
+        CMD_DATA_LL,
+        CMD_DATA_SC,
+        CMD_DATA_CAS, 
+    };
+
+    enum rsp_fsm_state_e {       
+        RSP_IDLE,
+        RSP_INS_MISS,
+        RSP_INS_UNC,
+        RSP_DATA_MISS,
+        RSP_DATA_UNC,
+        RSP_DATA_LL,
+        RSP_DATA_WRITE,
+    };
+
+    enum cleanup_cmd_fsm_state_e {
+        CLEANUP_DATA_IDLE,
+        CLEANUP_DATA_GO,
+        CLEANUP_INS_IDLE,
+        CLEANUP_INS_GO,
+    };
+
+    enum tgt_fsm_state_e {  
+        TGT_IDLE,
+        TGT_UPDT_WORD,
+        TGT_UPDT_DATA,
+        TGT_REQ_BROADCAST,
+        TGT_REQ_ICACHE,
+        TGT_REQ_DCACHE,
+        TGT_RSP_BROADCAST,
+        TGT_RSP_ICACHE, 
+        TGT_RSP_DCACHE,
+    };
+
+    /* transaction type, pktid field */
+    enum transaction_type_e
+    {
+        // b3 unused
+        // b2 READ / NOT READ
+        // Si READ
+        //  b1 DATA / INS
+        //  b0 UNC / MISS
+        // Si NOT READ
+        //  b1 accÃšs table llsc type SW / other
+        //  b2 WRITE/CAS/LL/SC
+        TYPE_READ_DATA_UNC          = 0x0,
+        TYPE_READ_DATA_MISS         = 0x1,
+        TYPE_READ_INS_UNC           = 0x2,
+        TYPE_READ_INS_MISS          = 0x3,
+        TYPE_WRITE                  = 0x4,
+        TYPE_CAS                    = 0x5,
+        TYPE_LL                     = 0x6,
+        TYPE_SC                     = 0x7
+    };
+    
+    /* SC return values */
+    enum sc_status_type_e
+    {
+        SC_SUCCESS  =   0x00000000,
+        SC_FAIL     =   0x00000001
+    };
+    /*
+    this is already in vci_param.h
+    enum {
+        STORE_COND_ATOMIC = 0,
+        STORE_COND_NOT_ATOMIC = 1,
+    };
+    */
+
+    // TLB Mode : ITLB / DTLB / ICACHE / DCACHE
+    enum {          
+        INS_TLB_MASK    = 0x8,
+        DATA_TLB_MASK   = 0x4,
+        INS_CACHE_MASK  = 0x2,
+        DATA_CACHE_MASK = 0x1,
+    };
+
+    // Error Type
+    enum mmu_error_type_e 
+    {
+        MMU_NONE                      = 0x0000, // None
+        MMU_WRITE_PT1_UNMAPPED 	      = 0x0001, // Write access of Page fault on Page Table 1          
+        MMU_WRITE_PT2_UNMAPPED 	      = 0x0002, // Write access of Page fault on Page Table 2          
+        MMU_WRITE_PRIVILEGE_VIOLATION = 0x0004, // Write access of Protected access in user mode      
+        MMU_WRITE_ACCES_VIOLATION     = 0x0008, // Write access of write access to a non writable page
+        MMU_WRITE_UNDEFINED_XTN       = 0x0020, // Write access of undefined external access address  
+        MMU_WRITE_PT1_ILLEGAL_ACCESS  = 0x0040, // Write access of Bus Error accessing Table 1       
+        MMU_WRITE_PT2_ILLEGAL_ACCESS  = 0x0080, // Write access of Bus Error accessing Table 2      
+        MMU_WRITE_DATA_ILLEGAL_ACCESS = 0x0100, // Write access of Bus Error in cache access     
+        MMU_READ_PT1_UNMAPPED 	      = 0x1001, // Read access of Page fault on Page Table 1  	
+        MMU_READ_PT2_UNMAPPED 	      = 0x1002, // Read access of Page fault on Page Table 2  
+        MMU_READ_PRIVILEGE_VIOLATION  = 0x1004, // Read access of Protected access in user mode 
+        MMU_READ_EXEC_VIOLATION       = 0x1010, // Exec access to a non exec page              
+        MMU_READ_UNDEFINED_XTN 	      = 0x1020, // Read access of Undefined external access address 
+        MMU_READ_PT1_ILLEGAL_ACCESS   = 0x1040, // Read access of Bus Error in Table1 access      
+        MMU_READ_PT2_ILLEGAL_ACCESS   = 0x1080, // Read access of Bus Error in Table2 access 	
+        MMU_READ_DATA_ILLEGAL_ACCESS  = 0x1100, // Read access of Bus Error in cache access 
+    };
+
+    // miss types for data cache
+    enum dcache_miss_type_e
+    {
+        PTE1_MISS, 
+        PTE2_MISS,
+        PROC_MISS,  
+    };
+
+    enum transaction_type_d_e
+    {
+        // b0 : 1 if cached
+        // b1 : 1 if instruction
+        TYPE_DATA_UNC     = 0x0,
+        TYPE_DATA_MISS    = 0x1,
+        TYPE_INS_UNC      = 0x2,
+        TYPE_INS_MISS     = 0x3,
+    };
+
+public:
+    sc_in<bool>                             p_clk;
+    sc_in<bool>                             p_resetn;
+    sc_in<bool>                             p_irq[iss_t::n_irq];
+    soclib::caba::VciInitiator<vci_param>   p_vci_ini_d;
+    soclib::caba::VciInitiator<vci_param>   p_vci_ini_c;
+    soclib::caba::VciTarget<vci_param>      p_vci_tgt_c;
+
+private:
+
+    // STRUCTURAL PARAMETERS
+    soclib::common::AddressDecodingTable<uint32_t, bool>    	m_cacheability_table;
+    const soclib::common::Segment                           	m_segment;
+    const vci_srcid_t                                       	m_srcid_d;
+    const vci_srcid_t                                       	m_srcid_c;
+
+    const size_t  						m_itlb_ways;
+    const size_t  						m_itlb_sets;
+
+    const size_t  						m_dtlb_ways;
+    const size_t  						m_dtlb_sets;
+
+    const size_t  						m_icache_ways;
+    const size_t  						m_icache_sets;
+    const paddr_t 						m_icache_yzmask;
+    const size_t  						m_icache_words;
+
+    const size_t  						m_dcache_ways;
+    const size_t  						m_dcache_sets;
+    const paddr_t 						m_dcache_yzmask;
+    const size_t  						m_dcache_words;
+
+    const size_t                        m_x_width;
+    const size_t                        m_y_width;
+
+    const size_t                        m_memory_cache_local_id;
+
+    const size_t                        m_proc_id;
+
+    const uint32_t						m_max_frozen_cycles;
+
+    const size_t  						m_paddr_nbits;  
+
+    ////////////////////////////////////////
+    // Communication with processor ISS
+    ////////////////////////////////////////
+    typename iss_t::InstructionRequest  m_ireq;
+    typename iss_t::InstructionResponse m_irsp;
+    typename iss_t::DataRequest         m_dreq;
+    typename iss_t::DataResponse        m_drsp;
+
+    /////////////////////////////////////////////
+    // debug variables (for each FSM)
+    /////////////////////////////////////////////
+    uint32_t                            m_debug_start_cycle;
+    bool                                m_debug_ok;
+    bool                                m_debug_previous_hit;
+    bool                                m_idebug_previous_hit;
+    bool                                m_debug_dcache_fsm;
+    bool                                m_debug_icache_fsm;
+    bool                                m_debug_cleanup_fsm;
+    bool                                m_debug_inval_itlb_fsm;
+    bool                                m_debug_inval_dtlb_fsm;
+
+    ///////////////////////////////
+    // Software visible REGISTERS
+    ///////////////////////////////
+    sc_signal<uint32_t>     r_mmu_ptpr;             	// page table pointer register
+    sc_signal<uint32_t>     r_mmu_mode;             	// mmu mode register
+    sc_signal<uint32_t>     r_mmu_word_lo;          	// mmu misc data low
+    sc_signal<uint32_t>     r_mmu_word_hi;          	// mmu misc data hight
+    sc_signal<uint32_t>     r_mmu_ibvar;      	    	// mmu bad instruction address
+    sc_signal<uint32_t>     r_mmu_dbvar;              	// mmu bad data address
+    sc_signal<uint32_t>     r_mmu_ietr;                 // mmu instruction error type
+    sc_signal<uint32_t>     r_mmu_detr;                 // mmu data error type
+    uint32_t	            r_mmu_params;		        // read-only
+    uint32_t	            r_mmu_release;		        // read_only
+
+
+    //////////////////////////////
+    // ICACHE FSM REGISTERS
+    //////////////////////////////
+    sc_signal<int>          r_icache_fsm;               // state register
+    sc_signal<int>          r_icache_fsm_save;          // return state for coherence operation
+    sc_signal<paddr_t>      r_icache_vci_paddr;      	// physical address 
+    sc_signal<uint32_t>     r_icache_vaddr_save;        // virtual address requested by the processor
+
+    // icache miss handling
+    sc_signal<size_t>       r_icache_miss_way;		    // selected way for cache update
+    sc_signal<size_t>       r_icache_miss_set;		    // selected set for cache update         
+    sc_signal<size_t>       r_icache_miss_word;		    // word index for sequencial cache update
+    sc_signal<bool>         r_icache_miss_inval;        // coherence request matching a pending miss
+
+    // coherence request handling
+    sc_signal<size_t>       r_icache_cc_way;		    // selected way for cc update/inval
+    sc_signal<size_t>       r_icache_cc_set;		    // selected set for cc update/inval
+    sc_signal<size_t>       r_icache_cc_word;		    // word counter for cc update
+
+    // icache flush handling
+    sc_signal<size_t>       r_icache_flush_count;	    // slot counter used for cache flush
+
+    // communication between ICACHE FSM and VCI_CMD FSM
+    sc_signal<bool>         r_icache_miss_req;           // cached read miss
+    sc_signal<bool>         r_icache_unc_req;            // uncached read miss
+
+    // communication between ICACHE FSM and DCACHE FSM
+    sc_signal<bool>	        r_icache_tlb_miss_req;       // itlb miss request (set icache/reset dcache)
+    sc_signal<bool>         r_icache_tlb_rsp_error;      // itlb miss response error (written by dcache)
+
+    // communication between ICACHE FSM and CLEANUP FSMs
+    sc_signal<bool>         r_icache_cleanup_req;        // ins cleanup request
+    sc_signal<paddr_t>      r_icache_cleanup_line;       // ins cleanup NLINE
+
+    ///////////////////////////////
+    // DCACHE FSM REGISTERS
+    ///////////////////////////////
+    sc_signal<int>          r_dcache_fsm;               // state register
+    sc_signal<int>          r_dcache_fsm_cc_save;       // return state for coherence operation
+    sc_signal<int>          r_dcache_fsm_scan_save;     // return state for tlb scan operation
+    // registers written in P0 stage (used in P1 stage)
+    sc_signal<bool>         r_dcache_p0_valid;		    // P1 pipeline stage must be executed
+    sc_signal<uint32_t>     r_dcache_p0_vaddr;          // virtual address (from proc)
+    sc_signal<uint32_t>     r_dcache_p0_wdata;          // write data (from proc)
+    sc_signal<vci_be_t>     r_dcache_p0_be;             // byte enable (from proc)
+    sc_signal<paddr_t>      r_dcache_p0_paddr;          // physical address 
+    sc_signal<bool>         r_dcache_p0_cacheable;	    // address cacheable 
+    // registers written in P1 stage (used in P2 stage)
+    sc_signal<bool>         r_dcache_p1_valid;		    // P2 pipeline stage must be executed
+    sc_signal<uint32_t>     r_dcache_p1_wdata;          // write data (from proc)
+    sc_signal<vci_be_t>     r_dcache_p1_be;             // byte enable (from proc)
+    sc_signal<paddr_t>      r_dcache_p1_paddr;          // physical address 
+    sc_signal<size_t>       r_dcache_p1_cache_way;	    // selected way (from dcache) 
+    sc_signal<size_t>       r_dcache_p1_cache_set;	    // selected set (from dcache)    
+    sc_signal<size_t>       r_dcache_p1_cache_word;	    // selected word (from dcache)    
+    // registers used by the Dirty bit sub-fsm
+    sc_signal<paddr_t>      r_dcache_dirty_paddr;       // PTE physical address 
+    sc_signal<size_t>       r_dcache_dirty_way;	        // way to invalidate in dcache
+    sc_signal<size_t>       r_dcache_dirty_set;	        // set to invalidate in dcache
+
+    // communication between DCACHE FSM and VCI_CMD FSM
+    sc_signal<paddr_t>      r_dcache_vci_paddr;		    // physical address for VCI command
+    sc_signal<bool>         r_dcache_vci_miss_req;      // read miss request
+    sc_signal<bool>         r_dcache_vci_unc_req;       // uncacheable read request
+    sc_signal<bool>         r_dcache_vci_unc_be;        // uncacheable read byte enable
+    sc_signal<bool>         r_dcache_vci_cas_req;       // atomic write request CAS
+    sc_signal<uint32_t>     r_dcache_vci_cas_old;       // previous data value for an atomic write CAS
+    sc_signal<uint32_t>     r_dcache_vci_cas_new;       // new data value for an atomic write CAS
+    sc_signal<bool>         r_dcache_vci_ll_req;        // atomic read request LL
+    sc_signal<bool>         r_dcache_vci_sc_req;        // atomic write request SC
+    sc_signal<vci_data_t>   r_dcache_vci_sc_data;       // SC data (command)
+
+    // register used for XTN inval
+    sc_signal<size_t>       r_dcache_xtn_way;		    // selected way (from dcache) 
+    sc_signal<size_t>       r_dcache_xtn_set;		    // selected set (from dcache)    
+
+    // write buffer state extension
+    sc_signal<bool>         r_dcache_pending_unc_write; // pending uncacheable write in WBUF
+
+    // handling dcache miss
+    sc_signal<int>	        r_dcache_miss_type;		    // type of miss depending on the requester
+    sc_signal<size_t>       r_dcache_miss_word;		    // word index for sequencial cache update
+    sc_signal<size_t>       r_dcache_miss_way;		    // selected way for cache update
+    sc_signal<size_t>       r_dcache_miss_set;		    // selected set for cache update
+    sc_signal<bool>         r_dcache_miss_inval;        // coherence request matching a pending miss
+
+    // handling coherence requests
+    sc_signal<size_t>       r_dcache_cc_way;		    // selected way for cc update/inval
+    sc_signal<size_t>       r_dcache_cc_set;		    // selected set for cc update/inval
+    sc_signal<size_t>       r_dcache_cc_word;		    // word counter for cc update
+
+    // dcache flush handling
+    sc_signal<size_t>       r_dcache_flush_count;	    // slot counter used for cache flush
+
+    // ll rsp handling
+    sc_signal<size_t>       r_dcache_ll_rsp_count;	    // flit counter used for ll rsp
+
+    // sc cmd handling
+    sc_signal<vci_data_t>   r_sc_key;                   // SC key returned by local table
+
+    // used by the TLB miss sub-fsm
+    sc_signal<uint32_t>     r_dcache_tlb_vaddr;		    // virtual address for a tlb miss
+    sc_signal<bool>         r_dcache_tlb_ins;		    // target tlb (itlb if true)
+    sc_signal<paddr_t>      r_dcache_tlb_paddr;		    // physical address of pte
+    sc_signal<uint32_t>     r_dcache_tlb_pte_flags;	    // pte1 or first word of pte2
+    sc_signal<uint32_t>     r_dcache_tlb_pte_ppn;	    // second word of pte2
+    sc_signal<size_t>       r_dcache_tlb_cache_way;	    // selected way in dcache 
+    sc_signal<size_t>       r_dcache_tlb_cache_set;	    // selected set in dcache 
+    sc_signal<size_t>       r_dcache_tlb_cache_word;	// selected word in dcache
+    sc_signal<size_t>       r_dcache_tlb_way;		    // selected way in tlb    
+    sc_signal<size_t>       r_dcache_tlb_set;		    // selected set in tlb    
+
+    // ITLB and DTLB invalidation
+    sc_signal<paddr_t>      r_dcache_tlb_inval_line;	// line index 
+    sc_signal<size_t>       r_dcache_tlb_inval_count;   // tlb entry counter
+
+    // communication between DCACHE FSM and ICACHE FSM
+    sc_signal<bool>         r_dcache_xtn_req;           // xtn request (caused by processor)
+    sc_signal<int>          r_dcache_xtn_opcode;        // xtn request type
+
+    // communication between DCACHE FSM and CLEANUP FSMs
+    sc_signal<bool>         r_dcache_cleanup_req;       // data cleanup request
+    sc_signal<paddr_t>      r_dcache_cleanup_line;      // data cleanup NLINE
+
+    // dcache directory extension
+    bool                    *r_dcache_in_tlb;           // copy exist in dtlb or itlb
+    bool                    *r_dcache_contains_ptd;     // cache line contains a PTD
+
+    ///////////////////////////////////
+    // VCI_CMD FSM REGISTERS
+    ///////////////////////////////////
+    sc_signal<int>          r_vci_cmd_fsm;
+    sc_signal<size_t>       r_vci_cmd_min;      	    // used for write bursts 
+    sc_signal<size_t>       r_vci_cmd_max;      	    // used for write bursts 
+    sc_signal<size_t>       r_vci_cmd_cpt;    		    // used for write bursts 
+    sc_signal<bool>         r_vci_cmd_imiss_prio;	    // round-robin between imiss & dmiss
+
+    ///////////////////////////////////
+    // VCI_RSP FSM REGISTERS
+    ///////////////////////////////////
+    sc_signal<int>          r_vci_rsp_fsm;
+    sc_signal<size_t>       r_vci_rsp_cpt;
+    sc_signal<bool>         r_vci_rsp_ins_error;
+    sc_signal<bool>         r_vci_rsp_data_error;
+    GenericFifo<uint32_t>   r_vci_rsp_fifo_icache;	    // response FIFO to ICACHE FSM
+    GenericFifo<uint32_t>   r_vci_rsp_fifo_dcache;	    // response FIFO to DCACHE FSM
+
+    ///////////////////////////////////
+    //  CLEANUP FSM REGISTER
+    ///////////////////////////////////
+    sc_signal<int>          r_cleanup_fsm;              // state register
+    sc_signal<size_t>       r_cleanup_trdid;            // to clear the registration buffer
+    GenericCam<paddr_t>     r_cleanup_buffer;           // Registration buffer for cleanups
+
+    ///////////////////////////////////
+    //  TGT FSM REGISTERS
+    ///////////////////////////////////
+    sc_signal<int>          r_tgt_fsm;			        // state register
+    sc_signal<paddr_t>      r_tgt_paddr;		        // cache line physical address
+    sc_signal<size_t>       r_tgt_word_count;		    // word index
+    sc_signal<size_t>       r_tgt_word_min;		        // index of the first word to be updated
+    sc_signal<size_t>       r_tgt_word_max;		        // index of the last word to be updated
+    sc_signal<bool>         r_tgt_update;		        // update request
+    sc_signal<bool>         r_tgt_update_data;		    // update data request
+    sc_signal<vci_srcid_t>  r_tgt_srcid;
+    sc_signal<vci_pktid_t>  r_tgt_pktid;
+    sc_signal<vci_trdid_t>  r_tgt_trdid;
+
+    // communications between TGT FSM and DCACHE/ICACHE FSMs
+    sc_signal<bool>         r_tgt_icache_req;		    // coherence request (set by tgt)
+    sc_signal<bool>         r_tgt_dcache_req;		    // coherence request (set by tgt)
+    sc_signal<bool>         r_tgt_icache_rsp;		    // coherence response (set by icache)
+    sc_signal<bool>         r_tgt_dcache_rsp;		    // coherence response (set by dcache)
+
+    uint32_t                *r_tgt_buf;			        // cache line word buffer 
+    vci_be_t                *r_tgt_be;			        // cache line be buffer 
+
+    //////////////////////////////////////////////////////////////////
+    // processor, write buffer, caches , TLBs and CAM for cleanups 
+    //////////////////////////////////////////////////////////////////
+    iss_t                       r_iss;   
+    MultiWriteBuffer<paddr_t>	r_wbuf;
+    GenericCache<paddr_t>   	r_icache;
+    GenericCache<paddr_t>    	r_dcache;
+    GenericTlb<paddr_t>       	r_itlb;
+    GenericTlb<paddr_t>     	r_dtlb;
+
+    //////////////////////////////////////////////////////////////////
+    // llsc local registration table
+    //////////////////////////////////////////////////////////////////
+
+    #define LLSCLocalTable GenericLLSCLocalTable<8000, 1, paddr_t, vci_trdid_t, vci_data_t>
+    LLSCLocalTable r_llsc_table;                    // The llsc local registration table
+
+    typename LLSCLocalTable::in_t   table_in    ;   // llsc local table input signals
+    typename LLSCLocalTable::out_t  table_out   ;   // llsc local table output signals
+
+    #undef LLSCLocalTable
+
+    ////////////////////////////////
+    // Activity counters
+    ////////////////////////////////
+    uint32_t m_cpt_dcache_data_read;        // DCACHE DATA READ
+    uint32_t m_cpt_dcache_data_write;       // DCACHE DATA WRITE
+    uint32_t m_cpt_dcache_dir_read;         // DCACHE DIR READ
+    uint32_t m_cpt_dcache_dir_write;        // DCACHE DIR WRITE
+
+    uint32_t m_cpt_icache_data_read;        // ICACHE DATA READ
+    uint32_t m_cpt_icache_data_write;       // ICACHE DATA WRITE
+    uint32_t m_cpt_icache_dir_read;         // ICACHE DIR READ
+    uint32_t m_cpt_icache_dir_write;        // ICACHE DIR WRITE
+
+    uint32_t m_cpt_frz_cycles;	            // number of cycles where the cpu is frozen
+    uint32_t m_cpt_total_cycles;	        // total number of cycles
+
+    // Cache activity counters
+    uint32_t m_cpt_data_read;               // total number of read data
+    uint32_t m_cpt_data_write;              // total number of write data
+    uint32_t m_cpt_data_miss;               // number of read miss
+    uint32_t m_cpt_ins_miss;                // number of instruction miss
+    uint32_t m_cpt_unc_read;                // number of read uncached
+    uint32_t m_cpt_write_cached;            // number of cached write
+    uint32_t m_cpt_ins_read;                // number of instruction read
+    uint32_t m_cpt_ins_spc_miss;            // number of speculative instruction miss
+
+    uint32_t m_cost_write_frz;              // number of frozen cycles related to write buffer         
+    uint32_t m_cost_data_miss_frz;          // number of frozen cycles related to data miss
+    uint32_t m_cost_unc_read_frz;           // number of frozen cycles related to uncached read
+    uint32_t m_cost_ins_miss_frz;           // number of frozen cycles related to ins miss
+
+    uint32_t m_cpt_imiss_transaction;       // number of VCI instruction miss transactions
+    uint32_t m_cpt_dmiss_transaction;       // number of VCI data miss transactions
+    uint32_t m_cpt_unc_transaction;         // number of VCI uncached read transactions
+    uint32_t m_cpt_write_transaction;       // number of VCI write transactions
+    uint32_t m_cpt_icache_unc_transaction;
+
+    uint32_t m_cost_imiss_transaction;      // cumulated duration for VCI IMISS transactions
+    uint32_t m_cost_dmiss_transaction;      // cumulated duration for VCI DMISS transactions
+    uint32_t m_cost_unc_transaction;        // cumulated duration for VCI UNC transactions
+    uint32_t m_cost_write_transaction;      // cumulated duration for VCI WRITE transactions
+    uint32_t m_cost_icache_unc_transaction; // cumulated duration for VCI IUNC transactions    
+    uint32_t m_length_write_transaction;    // cumulated length for VCI WRITE transactions
+
+    // TLB activity counters
+    uint32_t m_cpt_ins_tlb_read;            // number of instruction tlb read
+    uint32_t m_cpt_ins_tlb_miss;            // number of instruction tlb miss
+    uint32_t m_cpt_ins_tlb_update_acc;      // number of instruction tlb update 
+    uint32_t m_cpt_ins_tlb_occup_cache;     // number of instruction tlb occupy data cache line 
+    uint32_t m_cpt_ins_tlb_hit_dcache;      // number of instruction tlb hit in data cache
+
+    uint32_t m_cpt_data_tlb_read;           // number of data tlb read
+    uint32_t m_cpt_data_tlb_miss;           // number of data tlb miss
+    uint32_t m_cpt_data_tlb_update_acc;     // number of data tlb update 
+    uint32_t m_cpt_data_tlb_update_dirty;   // number of data tlb update dirty
+    uint32_t m_cpt_data_tlb_hit_dcache;     // number of data tlb hit in data cache
+    uint32_t m_cpt_data_tlb_occup_cache;    // number of data tlb occupy data cache line
+    uint32_t m_cpt_tlb_occup_dcache;
+    
+    uint32_t m_cost_ins_tlb_miss_frz;       // number of frozen cycles related to instruction tlb miss
+    uint32_t m_cost_data_tlb_miss_frz;      // number of frozen cycles related to data tlb miss
+    uint32_t m_cost_ins_tlb_update_acc_frz;    // number of frozen cycles related to instruction tlb update acc
+    uint32_t m_cost_data_tlb_update_acc_frz;   // number of frozen cycles related to data tlb update acc
+    uint32_t m_cost_data_tlb_update_dirty_frz; // number of frozen cycles related to data tlb update dirty
+    uint32_t m_cost_ins_tlb_occup_cache_frz;   // number of frozen cycles related to instruction tlb miss operate in dcache
+    uint32_t m_cost_data_tlb_occup_cache_frz;  // number of frozen cycles related to data tlb miss operate in dcache
+
+    uint32_t m_cpt_itlbmiss_transaction;       // number of itlb miss transactions
+    uint32_t m_cpt_itlb_ll_transaction;        // number of itlb ll acc transactions
+    uint32_t m_cpt_itlb_sc_transaction;        // number of itlb sc acc transactions
+    uint32_t m_cpt_dtlbmiss_transaction;       // number of dtlb miss transactions
+    uint32_t m_cpt_dtlb_ll_transaction;        // number of dtlb ll acc transactions
+    uint32_t m_cpt_dtlb_sc_transaction;        // number of dtlb sc acc transactions
+    uint32_t m_cpt_dtlb_ll_dirty_transaction;  // number of dtlb ll dirty transactions
+    uint32_t m_cpt_dtlb_sc_dirty_transaction;  // number of dtlb sc dirty transactions
+
+    uint32_t m_cost_itlbmiss_transaction;       // cumulated duration for VCI instruction TLB miss transactions
+    uint32_t m_cost_itlb_ll_transaction;        // cumulated duration for VCI instruction TLB ll acc transactions
+    uint32_t m_cost_itlb_sc_transaction;        // cumulated duration for VCI instruction TLB sc acc transactions
+    uint32_t m_cost_dtlbmiss_transaction;       // cumulated duration for VCI data TLB miss transactions
+    uint32_t m_cost_dtlb_ll_transaction;        // cumulated duration for VCI data TLB ll acc transactions
+    uint32_t m_cost_dtlb_sc_transaction;        // cumulated duration for VCI data TLB sc acc transactions
+    uint32_t m_cost_dtlb_ll_dirty_transaction;  // cumulated duration for VCI data TLB ll dirty transactions
+    uint32_t m_cost_dtlb_sc_dirty_transaction;  // cumulated duration for VCI data TLB sc dirty transactions
+
+    // coherence activity counters
+    uint32_t m_cpt_cc_update_icache;            // number of coherence update instruction commands
+    uint32_t m_cpt_cc_update_dcache;            // number of coherence update data commands
+    uint32_t m_cpt_cc_inval_icache;             // number of coherence inval instruction commands
+    uint32_t m_cpt_cc_inval_dcache;             // number of coherence inval data commands
+    uint32_t m_cpt_cc_broadcast;                // number of coherence broadcast commands
+    
+    uint32_t m_cost_updt_data_frz;              // number of frozen cycles related to coherence update data packets
+    uint32_t m_cost_inval_ins_frz;              // number of frozen cycles related to coherence inval instruction packets
+    uint32_t m_cost_inval_data_frz;             // number of frozen cycles related to coherence inval data packets
+    uint32_t m_cost_broadcast_frz;              // number of frozen cycles related to coherence broadcast packets
+
+    uint32_t m_cpt_cc_cleanup_ins;              // number of coherence cleanup packets
+    uint32_t m_cpt_cc_cleanup_data;             // number of coherence cleanup packets
+
+    uint32_t m_cpt_icleanup_transaction;        // number of instruction cleanup transactions
+    uint32_t m_cpt_dcleanup_transaction;        // number of instructinumber of data cleanup transactions
+    uint32_t m_cost_icleanup_transaction;       // cumulated duration for VCI instruction cleanup transactions
+    uint32_t m_cost_dcleanup_transaction;       // cumulated duration for VCI data cleanup transactions
+
+    uint32_t m_cost_ins_tlb_inval_frz;      // number of frozen cycles related to checking ins tlb invalidate
+    uint32_t m_cpt_ins_tlb_inval;           // number of ins tlb invalidate
+
+    uint32_t m_cost_data_tlb_inval_frz;     // number of frozen cycles related to checking data tlb invalidate    
+    uint32_t m_cpt_data_tlb_inval;          // number of data tlb invalidate
+
+    // FSM activity counters
+    uint32_t m_cpt_fsm_icache     [64];
+    uint32_t m_cpt_fsm_dcache     [64];
+    uint32_t m_cpt_fsm_cmd        [64];
+    uint32_t m_cpt_fsm_rsp        [64];
+    uint32_t m_cpt_fsm_tgt        [64];
+    uint32_t m_cpt_fsm_cmd_cleanup[64];
+    uint32_t m_cpt_fsm_rsp_cleanup[64];
+
+    uint32_t m_cpt_stop_simulation;		// used to stop simulation if frozen
+
+protected:
+    SC_HAS_PROCESS(VciCcVCacheWrapperV4);
+
+public:
+    VciCcVCacheWrapperV4(
+        sc_module_name insname,
+        int proc_id,
+        const soclib::common::MappingTable &mtp,
+        const soclib::common::MappingTable &mtc,
+        const soclib::common::IntTab &initiator_index_d,
+        const soclib::common::IntTab &initiator_index_c,
+        const soclib::common::IntTab &target_index_d,
+        size_t   itlb_ways,
+        size_t   itlb_sets,
+        size_t   dtlb_ways,
+        size_t   dtlb_sets,
+        size_t   icache_ways,
+        size_t   icache_sets,
+        size_t   icache_words,
+        size_t   dcache_ways,
+        size_t   dcache_sets,
+        size_t   dcache_words,
+        size_t   wbuf_nlines, 
+        size_t   wbuf_nwords, 
+        size_t   x_width,
+        size_t   y_width,
+        uint32_t memory_cache_local_id,
+        uint32_t max_frozen_cycles,
+        uint32_t debug_start_cycle,
+        bool     debug_ok);
+
+    ~VciCcVCacheWrapperV4();
+
+    void print_cpi();
+    void print_stats();
+    void clear_stats();
+    void print_trace(size_t mode = 0);
+    void cache_monitor(paddr_t addr);
+    inline void iss_set_debug_mask(uint v) {
+	r_iss.set_debug_mask(v);
+    }
+
+private:
+    void transition();
+    void genMoore();
+
+    soclib_static_assert((int)iss_t::SC_ATOMIC == (int)vci_param::STORE_COND_ATOMIC);
+    soclib_static_assert((int)iss_t::SC_NOT_ATOMIC == (int)vci_param::STORE_COND_NOT_ATOMIC);
+};
+
+}}
+
+#endif /* SOCLIB_CABA_VCI_CC_VCACHE_WRAPPER_V4_H */
+
+// Local Variables:
+// tab-width: 4
+// c-basic-offset: 4
+// c-file-offsets:((innamespace . 0)(inline-open . 0))
+// indent-tabs-mode: nil
+// End:
+
+// vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4
+
+
+
+
Index: branches/v4/modules/vci_cc_vcache_wrapper_v4/caba/source/src/vci_cc_vcache_wrapper_v4.cpp
===================================================================
--- branches/v4/modules/vci_cc_vcache_wrapper_v4/caba/source/src/vci_cc_vcache_wrapper_v4.cpp	(revision 371)
+++ branches/v4/modules/vci_cc_vcache_wrapper_v4/caba/source/src/vci_cc_vcache_wrapper_v4.cpp	(revision 371)
@@ -0,0 +1,5258 @@
+/* i*- c++ -*-C
+ * File : vci_cc_vcache_wrapper_v4.cpp
+ * Copyright (c) UPMC, Lip6, SoC
+ * Authors : Alain GREINER, Yang GAO
+ *
+ * SOCLIB_LGPL_HEADER_BEGIN
+ * 
+ * This file is part of SoCLib, GNU LGPLv2.1.
+ * 
+ * SoCLib is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU Lesser General Public License as published
+ * by the Free Software Foundation; version 2.1 of the License.
+ * 
+ * SoCLib is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * Lesser General Public License for more details.
+ * 
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with SoCLib; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301 USA
+ * 
+ * SOCLIB_LGPL_HEADER_END
+ */
+
+#include <cassert>
+#include "arithmetics.h"
+#include "../include/vci_cc_vcache_wrapper_v4.h"
+
+#define DEBUG_DCACHE		1
+#define DEBUG_ICACHE		1
+#define DEBUG_CLEANUP		0
+
+namespace soclib { 
+namespace caba {
+
+namespace {
+const char *icache_fsm_state_str[] = {
+        "ICACHE_IDLE",
+     
+        "ICACHE_XTN_TLB_FLUSH", 
+        "ICACHE_XTN_CACHE_FLUSH", 
+        "ICACHE_XTN_TLB_INVAL",  
+        "ICACHE_XTN_CACHE_INVAL_VA",
+        "ICACHE_XTN_CACHE_INVAL_PA",
+        "ICACHE_XTN_CACHE_INVAL_GO",
+
+        "ICACHE_TLB_WAIT",
+
+        "ICACHE_MISS_VICTIM",
+        "ICACHE_MISS_INVAL",
+        "ICACHE_MISS_WAIT",
+        "ICACHE_MISS_UPDT",  
+
+        "ICACHE_UNC_WAIT",  
+
+        "ICACHE_CC_CHECK", 
+        "ICACHE_CC_INVAL", 
+        "ICACHE_CC_UPDT", 
+        
+    };
+const char *dcache_fsm_state_str[] = {
+        "DCACHE_IDLE",       
+
+        "DCACHE_TLB_MISS",
+        "DCACHE_TLB_PTE1_GET",
+        "DCACHE_TLB_PTE1_SELECT",  
+        "DCACHE_TLB_PTE1_UPDT", 
+        "DCACHE_TLB_PTE2_GET", 
+        "DCACHE_TLB_PTE2_SELECT",
+        "DCACHE_TLB_PTE2_UPDT",   
+        "DCACHE_TLB_LR_UPDT",
+        "DCACHE_TLB_LR_WAIT",
+        "DCACHE_TLB_RETURN",
+
+        "DCACHE_XTN_SWITCH", 
+        "DCACHE_XTN_SYNC", 
+        "DCACHE_XTN_IC_INVAL_VA",
+        "DCACHE_XTN_IC_FLUSH", 
+        "DCACHE_XTN_IC_INVAL_PA",
+        "DCACHE_XTN_IT_INVAL",
+        "DCACHE_XTN_DC_FLUSH", 
+        "DCACHE_XTN_DC_INVAL_VA",
+        "DCACHE_XTN_DC_INVAL_PA",
+        "DCACHE_XTN_DC_INVAL_END",
+        "DCACHE_XTN_DC_INVAL_GO",
+        "DCACHE_XTN_DT_INVAL",
+
+        "DCACHE_DIRTY_PTE_GET",
+        "DCACHE_DIRTY_WAIT",  
+
+        "DCACHE_MISS_VICTIM",
+        "DCACHE_MISS_INVAL",
+        "DCACHE_MISS_WAIT",  
+        "DCACHE_MISS_UPDT",  
+
+        "DCACHE_UNC_WAIT",   
+        "DCACHE_LL_WAIT",   
+        "DCACHE_SC_WAIT",   
+
+        "DCACHE_CC_CHECK",
+        "DCACHE_CC_INVAL",
+        "DCACHE_CC_UPDT",
+
+        "DCACHE_INVAL_TLB_SCAN",
+    };
+const char *cmd_fsm_state_str[] = {
+        "CMD_IDLE",           
+        "CMD_INS_MISS",     
+        "CMD_INS_UNC",     
+        "CMD_DATA_MISS",    
+        "CMD_DATA_UNC",     
+        "CMD_DATA_WRITE", 
+        "CMD_DATA_LL",
+        "CMD_DATA_SC",
+        "CMD_DATA_CAS", 
+    };
+const char *rsp_fsm_state_str[] = {
+        "RSP_IDLE",                  
+        "RSP_INS_MISS",   
+        "RSP_INS_UNC",           
+        "RSP_DATA_MISS",             
+        "RSP_DATA_UNC",              
+        "RSP_DATA_LL",
+        "RSP_DATA_WRITE",     
+    };
+const char *cleanup_fsm_state_str[] = {
+        "CLEANUP_DATA_IDLE",           
+        "CLEANUP_DATA_GO",    
+        "CLEANUP_INS_IDLE",      
+        "CLEANUP_INS_GO",      
+    };
+const char *tgt_fsm_state_str[] = {
+        "TGT_IDLE",
+        "TGT_UPDT_WORD",
+        "TGT_UPDT_DATA",
+        "TGT_REQ_BROADCAST",
+        "TGT_REQ_ICACHE",
+        "TGT_REQ_DCACHE",
+        "TGT_RSP_BROADCAST",
+        "TGT_RSP_ICACHE",
+        "TGT_RSP_DCACHE",
+    };	
+}
+
+#define tmpl(...)  template<typename vci_param, typename iss_t> __VA_ARGS__ VciCcVCacheWrapperV4<vci_param, iss_t>
+
+using soclib::common::uint32_log2;
+
+/////////////////////////////////
+tmpl(/**/)::VciCcVCacheWrapperV4(
+    sc_module_name 			name,
+    int 				proc_id,
+    const soclib::common::MappingTable 	&mtd,
+    const soclib::common::MappingTable 	&mtc,
+    const soclib::common::IntTab 	&initiator_index_d,
+    const soclib::common::IntTab 	&initiator_index_c,
+    const soclib::common::IntTab 	&target_index_c,
+    size_t 				itlb_ways,
+    size_t 				itlb_sets,
+    size_t 				dtlb_ways,
+    size_t 				dtlb_sets,
+    size_t 				icache_ways,
+    size_t 				icache_sets,
+    size_t 				icache_words,
+    size_t 				dcache_ways,
+    size_t 				dcache_sets,
+    size_t 				dcache_words,
+    size_t 				wbuf_nlines, 
+    size_t 				wbuf_nwords, 
+    size_t				x_width,
+    size_t				y_width,
+    uint32_t			memory_cache_local_id,
+    uint32_t			max_frozen_cycles,
+    uint32_t			debug_start_cycle,
+    bool				debug_ok)
+    : soclib::caba::BaseModule(name),
+
+      p_clk("clk"),
+      p_resetn("resetn"),
+      p_vci_ini_d("vci_ini_d"),
+      p_vci_ini_c("vci_ini_c"),
+      p_vci_tgt_c("vci_tgt_d"),
+
+      m_cacheability_table(mtd.getCacheabilityTable()),
+      m_segment(mtc.getSegment(target_index_c)),
+      m_srcid_d(mtd.indexForId(initiator_index_d)),
+      m_srcid_c(mtc.indexForId(initiator_index_c)),
+
+      m_itlb_ways(itlb_ways),
+      m_itlb_sets(itlb_sets),
+
+      m_dtlb_ways(dtlb_ways),
+      m_dtlb_sets(dtlb_sets),
+
+      m_icache_ways(icache_ways),
+      m_icache_sets(icache_sets),
+      m_icache_yzmask((~0)<<(uint32_log2(icache_words) + 2)),
+      m_icache_words(icache_words),
+
+      m_dcache_ways(dcache_ways),
+      m_dcache_sets(dcache_sets),
+      m_dcache_yzmask((~0)<<(uint32_log2(dcache_words) + 2)),
+      m_dcache_words(dcache_words),
+
+      m_x_width(x_width),
+      m_y_width(y_width),
+
+      m_memory_cache_local_id(memory_cache_local_id),      
+
+      m_proc_id(proc_id),
+
+      m_max_frozen_cycles(max_frozen_cycles),
+
+      m_paddr_nbits(vci_param::N),
+
+      m_debug_start_cycle(debug_start_cycle),
+      m_debug_ok(debug_ok),
+
+      r_mmu_ptpr("r_mmu_ptpr"),
+      r_mmu_mode("r_mmu_mode"),
+      r_mmu_word_lo("r_mmu_word_lo"),
+      r_mmu_word_hi("r_mmu_word_hi"),
+      r_mmu_ibvar("r_mmu_ibvar"),
+      r_mmu_dbvar("r_mmu_dbvar"),
+      r_mmu_ietr("r_mmu_ietr"),
+      r_mmu_detr("r_mmu_detr"),
+
+      r_icache_fsm("r_icache_fsm"),
+      r_icache_fsm_save("r_icache_fsm_save"),
+
+      r_icache_vci_paddr("r_icache_vci_paddr"),
+      r_icache_vaddr_save("r_icache_vaddr_save"),
+
+      r_icache_miss_way("r_icache_miss_way"),
+      r_icache_miss_set("r_icache_miss_set"),
+      r_icache_miss_word("r_icache_miss_word"),
+      r_icache_miss_inval("r_icache_miss_inval"),
+
+      r_icache_cc_way("r_icache_cc_way"),
+      r_icache_cc_set("r_icache_cc_set"),
+      r_icache_cc_word("r_icache_cc_word"),
+
+      r_icache_flush_count("r_icache_flush_count"),
+
+      r_icache_miss_req("r_icache_miss_req"),
+      r_icache_unc_req("r_icache_unc_req"),
+
+      r_icache_tlb_miss_req("r_icache_tlb_read_req"),
+      r_icache_tlb_rsp_error("r_icache_tlb_rsp_error"),
+
+      r_icache_cleanup_req("r_icache_cleanup_req"),
+      r_icache_cleanup_line("r_icache_cleanup_line"),
+
+      r_dcache_fsm("r_dcache_fsm"),
+      r_dcache_fsm_cc_save("r_dcache_fsm_cc_save"),
+      r_dcache_fsm_scan_save("r_dcache_fsm_scan_save"),
+
+      r_dcache_p0_valid("r_dcache_p0_valid"),
+      r_dcache_p0_vaddr("r_dcache_p0_vaddr"),
+      r_dcache_p0_wdata("r_dcache_p0_wdata"),
+      r_dcache_p0_be("r_dcache_p0_be"),
+      r_dcache_p0_paddr("r_dcache_p0_paddr"),
+      r_dcache_p0_cacheable("r_dcache_p0_cacheable"), 
+
+      r_dcache_p1_valid("r_dcache_p1_valid"),
+      r_dcache_p1_wdata("r_dcache_p1_wdata"),
+      r_dcache_p1_be("r_dcache_p1_be"),
+      r_dcache_p1_paddr("r_dcache_p1_paddr"),
+      r_dcache_p1_cache_way("r_dcache_p1_cache_way"),
+      r_dcache_p1_cache_set("r_dcache_p1_cache_set"),
+      r_dcache_p1_cache_word("r_dcache_p1_word_save"),
+
+      r_dcache_dirty_paddr("r_dcache_dirty_paddr"),
+      r_dcache_dirty_way("r_dcache_dirty_way"),
+      r_dcache_dirty_set("r_dcache_dirty_set"),
+
+      r_dcache_vci_paddr("r_dcache_vci_paddr"),
+      r_dcache_vci_miss_req("r_dcache_vci_miss_req"),
+      r_dcache_vci_unc_req("r_dcache_vci_unc_req"),
+      r_dcache_vci_unc_be("r_dcache_vci_unc_be"),
+      r_dcache_vci_cas_req("r_dcache_vci_cas_req"),
+      r_dcache_vci_cas_old("r_dcache_vci_cas_old"),
+      r_dcache_vci_cas_new("r_dcache_vci_cas_new"),
+      r_dcache_vci_ll_req("r_dcache_vci_ll_req"),
+      r_dcache_vci_sc_req("r_dcache_vci_sc_req"),
+      r_dcache_vci_sc_data("r_dcache_vci_sc_data"),
+
+      r_dcache_xtn_way("r_dcache_xtn_way"),
+      r_dcache_xtn_set("r_dcache_xtn_set"),
+
+      r_dcache_pending_unc_write("r_dcache_pending_unc_write"),
+
+      r_dcache_miss_type("r_dcache_miss_type"),
+      r_dcache_miss_word("r_dcache_miss_word"),
+      r_dcache_miss_way("r_dcache_miss_way"),
+      r_dcache_miss_set("r_dcache_miss_set"),
+      r_dcache_miss_inval("r_dcache_miss_inval"),
+
+      r_dcache_cc_way("r_dcache_cc_way"),
+      r_dcache_cc_set("r_dcache_cc_set"),
+      r_dcache_cc_word("r_dcache_cc_word"),
+
+      r_dcache_flush_count("r_dcache_flush_count"),
+
+      r_dcache_tlb_vaddr("r_dcache_tlb_vaddr"),
+      r_dcache_tlb_ins("r_dcache_tlb_ins"),
+      r_dcache_tlb_pte_flags("r_dcache_tlb_pte_flags"),
+      r_dcache_tlb_pte_ppn("r_dcache_tlb_pte_ppn"),
+      r_dcache_tlb_cache_way("r_dcache_tlb_cache_way"),
+      r_dcache_tlb_cache_set("r_dcache_tlb_cache_set"),
+      r_dcache_tlb_cache_word("r_dcache_tlb_cache_word"),
+      r_dcache_tlb_way("r_dcache_tlb_way"),
+      r_dcache_tlb_set("r_dcache_tlb_set"),
+
+      r_dcache_tlb_inval_line("r_dcache_tlb_inval_line"),
+      r_dcache_tlb_inval_count("r_dcache_tlb_inval_count"),
+
+      r_dcache_xtn_req("r_dcache_xtn_req"),
+      r_dcache_xtn_opcode("r_dcache_xtn_opcode"),
+
+      r_dcache_cleanup_req("r_dcache_cleanup_req"),
+      r_dcache_cleanup_line("r_dcache_cleanup_line"),
+
+      r_vci_cmd_fsm("r_vci_cmd_fsm"),
+      r_vci_cmd_min("r_vci_cmd_min"),
+      r_vci_cmd_max("r_vci_cmd_max"),
+      r_vci_cmd_cpt("r_vci_cmd_cpt"),
+      r_vci_cmd_imiss_prio("r_vci_cmd_imiss_prio"),
+
+      r_vci_rsp_fsm("r_vci_rsp_fsm"),
+      r_vci_rsp_cpt("r_vci_rsp_cpt"),
+      r_vci_rsp_ins_error("r_vci_rsp_ins_error"),
+      r_vci_rsp_data_error("r_vci_rsp_data_error"),
+      r_vci_rsp_fifo_icache("r_vci_rsp_fifo_icache", 2),	// 2 words depth
+      r_vci_rsp_fifo_dcache("r_vci_rsp_fifo_dcache", 2),	// 2 words depth
+
+      r_cleanup_fsm("r_cleanup_fsm"),
+      r_cleanup_trdid("r_cleanup_trdid"),
+      r_cleanup_buffer(4),			// up to 4 simultaneous cleanups
+
+      r_tgt_fsm("r_tgt_fsm"),
+      r_tgt_paddr("r_tgt_paddr"),
+      r_tgt_word_count("r_tgt_word_count"),
+      r_tgt_word_min("r_tgt_word_min"),
+      r_tgt_word_max("r_tgt_word_max"),
+      r_tgt_update("r_tgt_update"),
+      r_tgt_update_data("r_tgt_update_data"),
+      r_tgt_srcid("r_tgt_srcid"),
+      r_tgt_pktid("r_tgt_pktid"),
+      r_tgt_trdid("r_tgt_trdid"),
+
+      r_tgt_icache_req("r_tgt_icache_req"),
+      r_tgt_dcache_req("r_tgt_dcache_req"),
+      r_tgt_icache_rsp("r_tgt_icache_rsp"),
+      r_tgt_dcache_rsp("r_tgt_dcache_rsp"),
+
+      r_iss(this->name(), proc_id),
+      r_wbuf("wbuf", wbuf_nwords, wbuf_nlines, dcache_words ),
+      r_icache("icache", icache_ways, icache_sets, icache_words),
+      r_dcache("dcache", dcache_ways, dcache_sets, dcache_words),
+      r_itlb("itlb", proc_id, itlb_ways,itlb_sets,vci_param::N),
+      r_dtlb("dtlb", proc_id, dtlb_ways,dtlb_sets,vci_param::N)
+{
+    assert( ((icache_words*vci_param::B) < (1<<vci_param::K)) and
+             "Need more PLEN bits.");
+
+    assert( (vci_param::T > 2) and ((1<<(vci_param::T-1)) >= (wbuf_nlines)) and
+             "Need more TRDID bits.");
+
+    assert( (icache_words == dcache_words) and
+             "icache_words and dcache_words parameters must be equal");
+
+    assert( (itlb_sets == dtlb_sets) and
+             "itlb_sets and dtlb_sets parameters must be etqual");
+
+    assert( (itlb_ways == dtlb_ways) and
+             "itlb_ways and dtlb_ways parameters must be etqual");
+
+    r_mmu_params = (uint32_log2(m_dtlb_ways)   << 29)   | (uint32_log2(m_dtlb_sets)   << 25) |
+                   (uint32_log2(m_dcache_ways) << 22)   | (uint32_log2(m_dcache_sets) << 18) |
+                   (uint32_log2(m_itlb_ways)   << 15)   | (uint32_log2(m_itlb_sets)   << 11) |
+                   (uint32_log2(m_icache_ways) << 8)    | (uint32_log2(m_icache_sets) << 4)  |
+                   (uint32_log2(m_icache_words<<2));
+
+    r_mmu_release = (uint32_t)(1 << 16) | 0x1;
+
+    r_tgt_buf             = new uint32_t[dcache_words];
+    r_tgt_be              = new vci_be_t[dcache_words];
+    r_dcache_in_tlb       = new bool[dcache_ways*dcache_sets];          
+    r_dcache_contains_ptd = new bool[dcache_ways*dcache_sets];          
+
+    SC_METHOD(transition);
+    dont_initialize();
+    sensitive << p_clk.pos();
+  
+    SC_METHOD(genMoore);
+    dont_initialize();
+    sensitive << p_clk.neg();
+
+    typename iss_t::CacheInfo cache_info;
+    cache_info.has_mmu = true;
+    cache_info.icache_line_size = icache_words*sizeof(uint32_t);
+    cache_info.icache_assoc = icache_ways;
+    cache_info.icache_n_lines = icache_sets;
+    cache_info.dcache_line_size = dcache_words*sizeof(uint32_t);
+    cache_info.dcache_assoc = dcache_ways;
+    cache_info.dcache_n_lines = dcache_sets;
+    r_iss.setCacheInfo(cache_info);
+}
+
+/////////////////////////////////////
+tmpl(/**/)::~VciCcVCacheWrapperV4()
+/////////////////////////////////////
+{
+    delete [] r_tgt_be;
+    delete [] r_tgt_buf;
+    delete [] r_dcache_in_tlb;          
+    delete [] r_dcache_contains_ptd;     
+}
+
+////////////////////////
+tmpl(void)::print_cpi()
+////////////////////////
+{
+    std::cout << name() << " CPI = " 
+        << (float)m_cpt_total_cycles/(m_cpt_total_cycles - m_cpt_frz_cycles) << std::endl ;
+}
+
+////////////////////////////////////
+tmpl(void)::print_trace(size_t mode)
+////////////////////////////////////
+{
+    // b0 : write buffer trace
+    // b1 : write buffer verbose
+    // b2 : dcache trace
+    // b3 : icache trace
+    // b4 : dtlb trace
+    // b5 : itlb trace
+
+    std::cout << std::dec << "PROC " << name() << std::endl;
+
+    std::cout << "  " << m_ireq << std::endl;
+    std::cout << "  " << m_irsp << std::endl;
+    std::cout << "  " << m_dreq << std::endl;
+    std::cout << "  " << m_drsp << std::endl;
+
+    std::cout << "  " << icache_fsm_state_str[r_icache_fsm.read()]
+              << " | " << dcache_fsm_state_str[r_dcache_fsm.read()]
+              << " | " << cmd_fsm_state_str[r_vci_cmd_fsm.read()]
+              << " | " << rsp_fsm_state_str[r_vci_rsp_fsm.read()]
+              << " | " << tgt_fsm_state_str[r_tgt_fsm.read()] 
+              << " | " << cleanup_fsm_state_str[r_cleanup_fsm.read()];
+    if (r_dcache_p0_valid.read() ) std::cout << " | P1_WRITE";
+    if (r_dcache_p1_valid.read() ) std::cout << " | P2_WRITE";
+    std::cout << std::endl;
+
+    if(mode & 0x01)
+    {
+        r_wbuf.printTrace((mode>>1)&1);
+    }
+    if(mode & 0x04)
+    {
+        std::cout << "  Data Cache" << std::endl;
+        r_dcache.printTrace();
+    }
+    if(mode & 0x08)
+    {
+        std::cout << "  Instruction Cache" << std::endl;
+        r_icache.printTrace();
+    }
+    if(mode & 0x10)
+    {
+        std::cout << "  Data TLB" << std::endl;
+        r_dtlb.printTrace();
+    }
+    if(mode & 0x20)
+    {
+        std::cout << "  Instruction TLB" << std::endl;
+        r_itlb.printTrace();
+    }
+}
+
+//////////////////////////////////////////
+tmpl(void)::cache_monitor( paddr_t addr )
+//////////////////////////////////////////
+{ 
+    size_t	cache_way;
+    size_t	cache_set;
+    size_t	cache_word;
+    uint32_t	cache_rdata;
+    bool	cache_hit = r_dcache.read_neutral( addr,
+                                           &cache_rdata,
+                                           &cache_way,
+                                           &cache_set,
+                                           &cache_word );
+    bool	icache_hit = r_icache.read_neutral( addr,
+                                           &cache_rdata,
+                                           &cache_way,
+                                           &cache_set,
+                                           &cache_word );
+    if ( cache_hit != m_debug_previous_hit )
+    {
+        std::cout << "PROC " << name() 
+                  << " dcache change at cycle " << std::dec << m_cpt_total_cycles
+                  << " for adresse " << std::hex << addr
+                  << " / HIT = " << std::dec << cache_hit << std::endl;
+	m_debug_previous_hit = cache_hit;
+    }
+    if ( icache_hit != m_idebug_previous_hit )
+    {
+        std::cout << "PROC " << name() 
+                  << " icache change at cycle " << std::dec << m_cpt_total_cycles
+                  << " for adresse " << std::hex << addr
+                  << " / HIT = " << icache_hit << std::endl;
+	m_idebug_previous_hit = icache_hit;
+    }
+}
+
+/*
+////////////////////////
+tmpl(void)::print_stats()
+////////////////////////
+{
+    float run_cycles = (float)(m_cpt_total_cycles - m_cpt_frz_cycles);
+    std::cout << name() << std::endl
+        << "- CPI                    = " << (float)m_cpt_total_cycles/run_cycles << std::endl 
+        << "- READ RATE              = " << (float)m_cpt_read/run_cycles << std::endl 
+        << "- WRITE RATE             = " << (float)m_cpt_write/run_cycles << std::endl
+        << "- IMISS_RATE             = " << (float)m_cpt_ins_miss/m_cpt_ins_read << std::endl
+        << "- DMISS RATE             = " << (float)m_cpt_data_miss/(m_cpt_read-m_cpt_unc_read) << std::endl  
+        << "- INS MISS COST          = " << (float)m_cost_ins_miss_frz/m_cpt_ins_miss << std::endl     
+        << "- DATA MISS COST         = " << (float)m_cost_data_miss_frz/m_cpt_data_miss << std::endl 
+        << "- WRITE COST             = " << (float)m_cost_write_frz/m_cpt_write << std::endl        
+        << "- UNC COST               = " << (float)m_cost_unc_read_frz/m_cpt_unc_read << std::endl
+        << "- UNCACHED READ RATE     = " << (float)m_cpt_unc_read/m_cpt_read << std::endl 
+        << "- CACHED WRITE RATE      = " << (float)m_cpt_write_cached/m_cpt_write << std::endl 
+        << "- INS TLB MISS RATE      = " << (float)m_cpt_ins_tlb_miss/m_cpt_ins_tlb_read << std::endl
+        << "- DATA TLB MISS RATE     = " << (float)m_cpt_data_tlb_miss/m_cpt_data_tlb_read << std::endl
+        << "- ITLB MISS COST         = " << (float)m_cost_ins_tlb_miss_frz/m_cpt_ins_tlb_miss << std::endl
+        << "- DTLB MISS COST         = " << (float)m_cost_data_tlb_miss_frz/m_cpt_data_tlb_miss << std::endl   
+        << "- ITLB UPDATE ACC COST   = " << (float)m_cost_ins_tlb_update_acc_frz/m_cpt_ins_tlb_update_acc << std::endl
+        << "- DTLB UPDATE ACC COST   = " << (float)m_cost_data_tlb_update_acc_frz/m_cpt_data_tlb_update_acc << std::endl
+        << "- DTLB UPDATE DIRTY COST = " << (float)m_cost_data_tlb_update_dirty_frz/m_cpt_data_tlb_update_dirty << std::endl
+        << "- ITLB HIT IN DCACHE RATE= " << (float)m_cpt_ins_tlb_hit_dcache/m_cpt_ins_tlb_miss << std::endl
+        << "- DTLB HIT IN DCACHE RATE= " << (float)m_cpt_data_tlb_hit_dcache/m_cpt_data_tlb_miss << std::endl
+        << "- DCACHE FROZEN BY ITLB  = " << (float)m_cost_ins_tlb_occup_cache_frz/m_cpt_dcache_frz_cycles << std::endl
+        << "- DCACHE FOR TLB %       = " << (float)m_cpt_tlb_occup_dcache/(m_dcache_ways*m_dcache_sets) << std::endl
+        << "- NB CC BROADCAST        = " << m_cpt_cc_broadcast << std::endl
+        << "- NB CC UPDATE DATA      = " << m_cpt_cc_update_data << std::endl
+        << "- NB CC INVAL DATA       = " << m_cpt_cc_inval_data << std::endl
+        << "- NB CC INVAL INS        = " << m_cpt_cc_inval_ins << std::endl
+        << "- CC BROADCAST COST      = " << (float)m_cost_broadcast_frz/m_cpt_cc_broadcast << std::endl
+        << "- CC UPDATE DATA COST    = " << (float)m_cost_updt_data_frz/m_cpt_cc_update_data << std::endl
+        << "- CC INVAL DATA COST     = " << (float)m_cost_inval_data_frz/m_cpt_cc_inval_data << std::endl
+        << "- CC INVAL INS COST      = " << (float)m_cost_inval_ins_frz/m_cpt_cc_inval_ins << std::endl
+        << "- NB CC CLEANUP DATA     = " << m_cpt_cc_cleanup_data << std::endl
+        << "- NB CC CLEANUP INS      = " << m_cpt_cc_cleanup_ins << std::endl
+        << "- IMISS TRANSACTION      = " << (float)m_cost_imiss_transaction/m_cpt_imiss_transaction << std::endl
+        << "- DMISS TRANSACTION      = " << (float)m_cost_dmiss_transaction/m_cpt_dmiss_transaction << std::endl
+        << "- UNC TRANSACTION        = " << (float)m_cost_unc_transaction/m_cpt_unc_transaction << std::endl
+        << "- WRITE TRANSACTION      = " << (float)m_cost_write_transaction/m_cpt_write_transaction << std::endl
+        << "- WRITE LENGTH           = " << (float)m_length_write_transaction/m_cpt_write_transaction << std::endl
+        << "- ITLB MISS TRANSACTION  = " << (float)m_cost_itlbmiss_transaction/m_cpt_itlbmiss_transaction << std::endl
+        << "- DTLB MISS TRANSACTION  = " << (float)m_cost_dtlbmiss_transaction/m_cpt_dtlbmiss_transaction << std::endl;
+}
+
+////////////////////////
+tmpl(void)::clear_stats()
+////////////////////////
+{
+    m_cpt_dcache_data_read  = 0;
+    m_cpt_dcache_data_write = 0;
+    m_cpt_dcache_dir_read   = 0;
+    m_cpt_dcache_dir_write  = 0;
+    m_cpt_icache_data_read  = 0;
+    m_cpt_icache_data_write = 0;
+    m_cpt_icache_dir_read   = 0;
+    m_cpt_icache_dir_write  = 0;
+    
+    m_cpt_frz_cycles        = 0;
+    m_cpt_dcache_frz_cycles = 0;
+    m_cpt_total_cycles      = 0;
+    
+    m_cpt_read         = 0;
+    m_cpt_write        = 0;
+    m_cpt_data_miss    = 0;
+    m_cpt_ins_miss     = 0;
+    m_cpt_unc_read     = 0;
+    m_cpt_write_cached = 0;
+    m_cpt_ins_read     = 0;
+    
+    m_cost_write_frz     = 0;
+    m_cost_data_miss_frz = 0;
+    m_cost_unc_read_frz  = 0;
+    m_cost_ins_miss_frz  = 0;
+    
+    m_cpt_imiss_transaction      = 0;
+    m_cpt_dmiss_transaction      = 0;
+    m_cpt_unc_transaction        = 0;
+    m_cpt_write_transaction      = 0;
+    m_cpt_icache_unc_transaction = 0;	
+    
+    m_cost_imiss_transaction      = 0;
+    m_cost_dmiss_transaction      = 0;
+    m_cost_unc_transaction        = 0;
+    m_cost_write_transaction      = 0;
+    m_cost_icache_unc_transaction = 0;
+    m_length_write_transaction    = 0;
+    
+    m_cpt_ins_tlb_read       = 0;             
+    m_cpt_ins_tlb_miss       = 0;             
+    m_cpt_ins_tlb_update_acc = 0;         
+    
+    m_cpt_data_tlb_read         = 0;           
+    m_cpt_data_tlb_miss         = 0;           
+    m_cpt_data_tlb_update_acc   = 0;       
+    m_cpt_data_tlb_update_dirty = 0;    
+    m_cpt_ins_tlb_hit_dcache    = 0;
+    m_cpt_data_tlb_hit_dcache   = 0;
+    m_cpt_ins_tlb_occup_cache   = 0;
+    m_cpt_data_tlb_occup_cache  = 0;
+    
+    m_cost_ins_tlb_miss_frz          = 0;      
+    m_cost_data_tlb_miss_frz         = 0;      
+    m_cost_ins_tlb_update_acc_frz    = 0;
+    m_cost_data_tlb_update_acc_frz   = 0;
+    m_cost_data_tlb_update_dirty_frz = 0;
+    m_cost_ins_tlb_occup_cache_frz   = 0;
+    m_cost_data_tlb_occup_cache_frz  = 0;
+    
+    m_cpt_itlbmiss_transaction      = 0;    
+    m_cpt_itlb_ll_transaction       = 0;  
+    m_cpt_itlb_sc_transaction       = 0;  
+    m_cpt_dtlbmiss_transaction      = 0;  
+    m_cpt_dtlb_ll_transaction       = 0;  
+    m_cpt_dtlb_sc_transaction       = 0;  
+    m_cpt_dtlb_ll_dirty_transaction = 0;  
+    m_cpt_dtlb_sc_dirty_transaction = 0;  
+    
+    m_cost_itlbmiss_transaction      = 0;   
+    m_cost_itlb_ll_transaction       = 0;  
+    m_cost_itlb_sc_transaction       = 0;  
+    m_cost_dtlbmiss_transaction      = 0;   
+    m_cost_dtlb_ll_transaction       = 0;   
+    m_cost_dtlb_sc_transaction       = 0;   
+    m_cost_dtlb_ll_dirty_transaction = 0;   
+    m_cost_dtlb_sc_dirty_transaction = 0;
+
+    m_cpt_cc_update_data = 0;
+    m_cpt_cc_inval_ins   = 0;
+    m_cpt_cc_inval_data  = 0;
+    m_cpt_cc_broadcast   = 0;
+
+    m_cost_updt_data_frz  = 0;
+    m_cost_inval_ins_frz  = 0;
+    m_cost_inval_data_frz = 0;
+    m_cost_broadcast_frz  = 0;
+
+    m_cpt_cc_cleanup_data = 0;
+    m_cpt_cc_cleanup_ins  = 0;
+}
+
+*/
+
+/////////////////////////
+tmpl(void)::transition()
+/////////////////////////
+{
+    #define LLSCLocalTable GenericLLSCLocalTable<8000, 1, paddr_t, vci_trdid_t, vci_data_t>
+    if ( not p_resetn.read() ) 
+    {
+        r_iss.reset();
+        r_wbuf.reset();
+        r_icache.reset();
+        r_dcache.reset();
+        r_itlb.reset();    
+        r_dtlb.reset();    
+
+        r_dcache_fsm      = DCACHE_IDLE;
+        r_icache_fsm      = ICACHE_IDLE;
+        r_vci_cmd_fsm     = CMD_IDLE;
+        r_vci_rsp_fsm     = RSP_IDLE;
+        r_tgt_fsm         = TGT_IDLE;
+        r_cleanup_fsm     = CLEANUP_DATA_IDLE;
+
+        // reset dcache directory extension
+        for (size_t i=0 ; i< m_dcache_ways*m_dcache_sets ; i++)
+        {
+            r_dcache_in_tlb[i]       = false;
+            r_dcache_contains_ptd[i] = false;
+        } 
+
+        // Response FIFOs and cleanup buffer
+        r_vci_rsp_fifo_icache.init();
+        r_vci_rsp_fifo_dcache.init();
+        r_cleanup_buffer.reset();
+
+        // ICACHE & DCACHE activated
+        r_mmu_mode = 0x3;
+
+	    // No request from ICACHE FSM to CMD FSM
+        r_icache_miss_req          = false;
+        r_icache_unc_req           = false;
+
+        // No request from ICACHE_FSM to DCACHE FSM
+        r_icache_tlb_miss_req      = false;      
+ 
+        // No request from ICACHE_FSM to CLEANUP FSMs
+        r_icache_cleanup_req       = false;      
+        
+        // No pending write in pipeline
+        r_dcache_p0_valid          = false;
+        r_dcache_p1_valid          = false;
+
+        // No request from DCACHE_FSM to CMD_FSM
+        r_dcache_vci_miss_req      = false;
+        r_dcache_vci_unc_req       = false;
+        r_dcache_vci_cas_req       = false;
+        r_dcache_vci_ll_req        = false;
+        r_dcache_vci_sc_req        = false;
+
+        // No uncacheable write pending
+        r_dcache_pending_unc_write = false;
+
+        // No processor XTN request pending
+        r_dcache_xtn_req           = false;
+
+        // No request from DCACHE FSM to CLEANUP FSMs
+        r_dcache_cleanup_req      = false;
+
+        // No request from TGT FSM to ICACHE/DCACHE FSMs
+        r_tgt_icache_req          = false;
+        r_tgt_dcache_req          = false;
+
+        // No signalisation of a coherence request matching a pending miss
+        r_icache_miss_inval       = false;
+        r_dcache_miss_inval       = false;
+
+        // No signalisation  of errors
+        r_vci_rsp_ins_error       = false;
+        r_vci_rsp_data_error      = false;
+
+        // Debug variables
+        m_debug_previous_hit      = false;
+        m_idebug_previous_hit     = false;
+        m_debug_dcache_fsm	      = false;
+        m_debug_icache_fsm	      = false;
+        m_debug_cleanup_fsm  	  = false;
+
+        // activity counters
+        m_cpt_dcache_data_read  = 0;
+        m_cpt_dcache_data_write = 0;
+        m_cpt_dcache_dir_read   = 0;
+        m_cpt_dcache_dir_write  = 0;
+        m_cpt_icache_data_read  = 0;
+        m_cpt_icache_data_write = 0;
+        m_cpt_icache_dir_read   = 0;
+        m_cpt_icache_dir_write  = 0;
+
+        m_cpt_frz_cycles        = 0;
+        m_cpt_total_cycles      = 0;
+        m_cpt_stop_simulation   = 0;
+
+        m_cpt_data_miss         = 0;
+        m_cpt_ins_miss          = 0;
+        m_cpt_unc_read          = 0;
+        m_cpt_write_cached      = 0;
+        m_cpt_ins_read          = 0;
+
+        m_cost_write_frz        = 0;
+        m_cost_data_miss_frz    = 0;
+        m_cost_unc_read_frz     = 0;
+        m_cost_ins_miss_frz     = 0;
+
+        m_cpt_imiss_transaction = 0;
+        m_cpt_dmiss_transaction = 0;
+        m_cpt_unc_transaction   = 0;
+        m_cpt_write_transaction = 0;
+        m_cpt_icache_unc_transaction = 0;	
+
+        m_cost_imiss_transaction      = 0;
+        m_cost_dmiss_transaction      = 0;
+        m_cost_unc_transaction        = 0;
+        m_cost_write_transaction      = 0;
+        m_cost_icache_unc_transaction = 0;
+        m_length_write_transaction    = 0;
+
+        m_cpt_ins_tlb_read       = 0;             
+        m_cpt_ins_tlb_miss       = 0;             
+        m_cpt_ins_tlb_update_acc = 0;         
+
+        m_cpt_data_tlb_read         = 0;           
+        m_cpt_data_tlb_miss         = 0;           
+        m_cpt_data_tlb_update_acc   = 0;       
+        m_cpt_data_tlb_update_dirty = 0;    
+        m_cpt_ins_tlb_hit_dcache    = 0;
+        m_cpt_data_tlb_hit_dcache   = 0;
+        m_cpt_ins_tlb_occup_cache   = 0;
+        m_cpt_data_tlb_occup_cache  = 0;
+
+        m_cost_ins_tlb_miss_frz          = 0;      
+        m_cost_data_tlb_miss_frz         = 0;      
+        m_cost_ins_tlb_update_acc_frz    = 0;
+        m_cost_data_tlb_update_acc_frz   = 0;
+        m_cost_data_tlb_update_dirty_frz = 0;
+        m_cost_ins_tlb_occup_cache_frz   = 0;
+        m_cost_data_tlb_occup_cache_frz  = 0;
+
+    	m_cpt_ins_tlb_inval       = 0;           
+    	m_cpt_data_tlb_inval      = 0;          
+    	m_cost_ins_tlb_inval_frz  = 0;     
+    	m_cost_data_tlb_inval_frz = 0;         
+
+        m_cpt_cc_broadcast   = 0;
+
+   	    m_cost_updt_data_frz  = 0;
+   	    m_cost_inval_ins_frz  = 0;
+   	    m_cost_inval_data_frz = 0;
+   	    m_cost_broadcast_frz  = 0;
+
+   	    m_cpt_cc_cleanup_data = 0;
+   	    m_cpt_cc_cleanup_ins  = 0;
+
+        m_cpt_itlbmiss_transaction      = 0;    
+        m_cpt_itlb_ll_transaction       = 0;  
+        m_cpt_itlb_sc_transaction       = 0;  
+        m_cpt_dtlbmiss_transaction      = 0;  
+        m_cpt_dtlb_ll_transaction       = 0;  
+        m_cpt_dtlb_sc_transaction       = 0;  
+        m_cpt_dtlb_ll_dirty_transaction = 0;  
+        m_cpt_dtlb_sc_dirty_transaction = 0;  
+ 
+        m_cost_itlbmiss_transaction      = 0;   
+        m_cost_itlb_ll_transaction       = 0;  
+        m_cost_itlb_sc_transaction       = 0;  
+        m_cost_dtlbmiss_transaction      = 0;   
+        m_cost_dtlb_ll_transaction       = 0;   
+        m_cost_dtlb_sc_transaction       = 0;   
+        m_cost_dtlb_ll_dirty_transaction = 0;   
+        m_cost_dtlb_sc_dirty_transaction = 0;    
+/* 
+        m_cpt_dcache_frz_cycles = 0;
+        m_cpt_read              = 0;
+        m_cpt_write             = 0;
+   	m_cpt_cc_update_data = 0;
+   	m_cpt_cc_inval_ins   = 0;
+   	m_cpt_cc_inval_data  = 0;
+  */
+
+        for (uint32_t i=0; i<32 ; ++i) m_cpt_fsm_icache      [i]   = 0;
+        for (uint32_t i=0; i<32 ; ++i) m_cpt_fsm_dcache      [i]   = 0;
+        for (uint32_t i=0; i<32 ; ++i) m_cpt_fsm_cmd         [i]   = 0;
+        for (uint32_t i=0; i<32 ; ++i) m_cpt_fsm_rsp         [i]   = 0;
+        for (uint32_t i=0; i<32 ; ++i) m_cpt_fsm_tgt         [i]   = 0;
+        for (uint32_t i=0; i<32 ; ++i) m_cpt_fsm_cmd_cleanup [i]   = 0;
+        for (uint32_t i=0; i<32 ; ++i) m_cpt_fsm_rsp_cleanup [i]   = 0;
+
+        // init the llsc local registration table
+        r_llsc_table.init();
+
+        return;
+    }
+
+    // Response FIFOs default values
+    bool       vci_rsp_fifo_icache_get       = false;
+    bool       vci_rsp_fifo_icache_put       = false;
+    uint32_t   vci_rsp_fifo_icache_data      = 0;
+
+    bool       vci_rsp_fifo_dcache_get       = false;
+    bool       vci_rsp_fifo_dcache_put       = false;
+    uint32_t   vci_rsp_fifo_dcache_data      = 0;
+
+#ifdef INSTRUMENTATION
+    m_cpt_fsm_dcache  [r_dcache_fsm.read() ] ++;
+    m_cpt_fsm_icache  [r_icache_fsm.read() ] ++;
+    m_cpt_fsm_cmd     [r_vci_cmd_fsm.read()] ++;
+    m_cpt_fsm_rsp     [r_vci_rsp_fsm.read()] ++;
+    m_cpt_fsm_tgt     [r_tgt_fsm.read()    ] ++;
+    m_cpt_fsm_cleanup [r_cleanup_fsm.read()] ++;
+#endif
+
+    m_cpt_total_cycles++;
+
+    m_debug_cleanup_fsm    = (m_cpt_total_cycles > m_debug_start_cycle) and m_debug_ok;
+    m_debug_icache_fsm     = (m_cpt_total_cycles > m_debug_start_cycle) and m_debug_ok;
+    m_debug_dcache_fsm     = (m_cpt_total_cycles > m_debug_start_cycle) and m_debug_ok;
+
+    /////////////////////////////////////////////////////////////////////
+    // The TGT_FSM controls the following ressources:
+    // - r_tgt_fsm
+    // - r_tgt_buf[nwords]
+    // - r_tgt_be[nwords]
+    // - r_tgt_update
+    // - r_tgt_word_min
+    // - r_tgt_word_max
+    // - r_tgt_word_count
+    // - r_tgt_paddr
+    // - r_tgt_srcid
+    // - r_tgt_trdid
+    // - r_tgt_pktid
+    // - r_tgt_icache_req (set)
+    // - r_tgt_dcache_req (set)
+    //
+    // All VCI commands must be CMD_WRITE.
+    // - If the 2 LSB bits of the VCI address are 11, it is a broadcast request.
+    //   It is a multicast request otherwise.
+    // - For multicast requests, the ADDRESS[2] bit distinguishes DATA/INS
+    //   (0 for data / 1 for instruction), and the ADDRESS[3] bit distinguishes
+    //   INVAL/UPDATE (0 for invalidate / 1 for UPDATE).
+    //
+    // For all types of coherence request, the line index (i.e. the Z & Y fields) 
+    // is coded on 34 bits, and is contained in the WDATA and BE fields 
+    // of the first VCI flit.
+    // -  for a multicast invalidate or for a broadcast invalidate request
+    //    the VCI packet length is 1 word. 
+    // -  for an update request the VCI packet length is (n+2) words.
+    //    The WDATA field of the second VCI word contains the word index.
+    //    The WDATA field of the n following words contains the values.
+    // -  for all transaction types, the VCI response is one single word.
+    // In case of errors in the VCI command packet, the simulation
+    // is stopped with an error message.
+    //
+    // This FSM is NOT pipelined : It consumes a new coherence request 
+    // on the VCI port only when the previous request is completed.
+    //
+    // The VCI_TGT FSM stores the external request arguments in the
+    // IDLE, UPDT_WORD & UPDT_DATA states. It sets the r_tgt_icache_req 
+    // and/or the r_tgt_dcache_req flip-flops to signal the coherence request 
+    // to the ICACHE & DCACHE FSMs in the REQ_ICACHE, REQ_DCACHE & REQ_BROADCAST
+    // states. It waits the completion of the coherence request  by polling the
+    // r_tgt_*cache_req flip-flops in the RSP_ICACHE, RSP_DCACHE & RSP_BROADCAST
+    // states. These flip-flops are reset by the ICACHE and DCACHE FSMs. 
+    // These two FSMs signal if a VCI answer must be send by setting
+    // the r_tgt_icache_rsp and/or the r_tgt_dcache_rsp flip_flops.
+    ///////////////////////////////////////////////////////////////////////////////
+
+    switch( r_tgt_fsm.read() ) 
+    {
+    //////////////
+    case TGT_IDLE:
+    {
+        if ( p_vci_tgt_c.cmdval.read() ) 
+        {
+            paddr_t address = p_vci_tgt_c.address.read();
+
+            // command checking
+            if ( p_vci_tgt_c.cmd.read() != vci_param::CMD_WRITE) 
+            {
+                std::cout << "error in component VCI_CC_VCACHE_WRAPPER " << name() << std::endl;
+                std::cout << "the received VCI coherence command is not a write" << std::endl;
+                exit(0);
+            }
+
+            // address checking
+            if ( ( (address & 0x3) != 0x3 ) && ( not m_segment.contains(address)) ) 
+            {
+                std::cout << "error in component VCI_CC_VCACHE_WRAPPER " << name() << std::endl;
+                std::cout << "out of segment VCI coherence command received" << std::endl;
+                exit(0);
+            }
+
+            r_tgt_srcid = p_vci_tgt_c.srcid.read();
+            r_tgt_trdid = p_vci_tgt_c.trdid.read();
+            r_tgt_pktid = p_vci_tgt_c.pktid.read();
+
+	    if (sizeof(paddr_t) <= 32) 
+        {
+		     assert(p_vci_tgt_c.be.read() == 0 
+             && "byte enable should be 0 for 32bits paddr");
+             r_tgt_paddr  = (paddr_t)p_vci_tgt_c.wdata.read() * m_dcache_words * 4; 
+	    }
+        else 
+        {
+             r_tgt_paddr  = (paddr_t)(p_vci_tgt_c.be.read() & 0x3) << 32 |
+			                (paddr_t)p_vci_tgt_c.wdata.read() * m_dcache_words * 4; 
+	    }
+
+            if ( (address&0x3) == 0x3 ) // broadcast invalidate for data or instruction type
+            {
+                if ( not p_vci_tgt_c.eop.read() ) 
+                {
+                    std::cout << "error in component VCI_CC_VCACHE_WRAPPER " << name() << std::endl;
+                    std::cout << "the BROADCAST INVALIDATE command must be one flit" << std::endl;
+                    exit(0);
+                }
+                r_tgt_update = false; 
+                r_tgt_fsm = TGT_REQ_BROADCAST;
+
+#ifdef INSTRUMENTATION
+m_cpt_cc_broadcast++;
+#endif
+            }
+            else                // multi-update or multi-invalidate for data type
+            {
+                paddr_t cell = address - m_segment.baseAddress();   
+
+                if (cell == 0)                      // invalidate data
+                {                         
+                    if ( not p_vci_tgt_c.eop.read() ) 
+                    {
+                        std::cout << "error in VCI_CC_VCACHE_WRAPPER " << name() << std::endl;
+                        std::cout << "the MULTI-INVALIDATE command must be one flit" << std::endl;
+                        exit(0);
+                    }
+                    r_tgt_update = false; 
+                    r_tgt_fsm    = TGT_REQ_DCACHE;
+
+#ifdef INSTRUMENTATION
+m_cpt_cc_inval_dcache++;
+#endif
+                }
+                else if (cell == 4)                // invalidate instruction
+                {                                
+                    if ( not p_vci_tgt_c.eop.read() ) 
+                    {
+                        std::cout << "error in VCI_CC_VCACHE_WRAPPER " << name() << std::endl;
+                        std::cout << "the MULTI-INVALIDATE command must be one flit" << std::endl;
+                        exit(0);
+                    }
+                    r_tgt_update = false; 
+                    r_tgt_fsm    = TGT_REQ_ICACHE;
+
+#ifdef INSTRUMENTATION
+m_cpt_cc_inval_icache++;
+#endif
+                }     
+		else if (cell == 8)		// update data
+		{
+                    if ( p_vci_tgt_c.eop.read() ) 
+                    {
+                        std::cout << "error in VCI_CC_VCACHE_WRAPPER " << name() << std::endl;
+                        std::cout << "the MULTI-UPDATE command must be N+2 flits" << std::endl;
+                        exit(0);
+                    }
+                    r_tgt_update      = true; 
+                    r_tgt_update_data = true;
+                    r_tgt_fsm         = TGT_UPDT_WORD;
+
+#ifdef INSTRUMENTATION
+m_cpt_cc_update_dcache++;
+#endif
+		}
+                else				// update instruction
+                {
+                    if ( p_vci_tgt_c.eop.read() ) 
+                    {
+                        std::cout << "error in VCI_CC_VCACHE_WRAPPER " << name() << std::endl;
+                        std::cout << "the MULTI-UPDATE command must be N+2 flits" << std::endl;
+                        exit(0);
+                    }
+                    r_tgt_update      = true; 
+                    r_tgt_update_data = false;
+                    r_tgt_fsm         = TGT_UPDT_WORD;
+
+#ifdef INSTRUMENTATION
+m_cpt_cc_update_icache++;
+#endif
+                }
+            } // end if multi      
+        } // end if cmdval
+        break;
+    }
+    ///////////////////
+    case TGT_UPDT_WORD:		// first word index acquisition
+    {
+        if (p_vci_tgt_c.cmdval.read()) 
+        {
+            if ( p_vci_tgt_c.eop.read() ) 
+            {
+                std::cout << "error in component VCI_CC_VCACHE_WRAPPER " << name() << std::endl;
+                std::cout << "the MULTI-UPDATE command must be N+2 flits" << std::endl;
+                exit(0);
+            }
+            for ( size_t i=0 ; i<m_dcache_words ; i++ ) r_tgt_be[i] = false;
+
+            r_tgt_word_min   = p_vci_tgt_c.wdata.read(); // first modifid word index
+            r_tgt_word_count = p_vci_tgt_c.wdata.read(); // initializing word index
+            r_tgt_fsm = TGT_UPDT_DATA;
+        }
+        break;
+    }
+    ///////////////////
+    case TGT_UPDT_DATA:
+    {
+        if (p_vci_tgt_c.cmdval.read()) 
+        {
+            size_t word = r_tgt_word_count.read();
+            if (word >= m_dcache_words) 
+            {
+                std::cout << "error in component VCI_CC_VCACHE_WRAPPER " << name() << std::endl;
+                std::cout << "the reveived MULTI-UPDATE command is wrong" << std::endl;
+                exit(0);
+            }
+            r_tgt_buf[word]  = p_vci_tgt_c.wdata.read();
+            r_tgt_be[word]   = p_vci_tgt_c.be.read();
+            r_tgt_word_count = word + 1;	
+
+            if (p_vci_tgt_c.eop.read()) 	// last word
+            {
+                 r_tgt_word_max = word;
+                 if ( r_tgt_update_data.read() )	r_tgt_fsm = TGT_REQ_DCACHE;
+                 else					r_tgt_fsm = TGT_REQ_ICACHE;
+            }
+        }
+        break;
+    }
+    ///////////////////////
+    case TGT_REQ_BROADCAST:	// set requests to DCACHE & ICACHE FSMs 
+    {
+        if ( not r_tgt_icache_req.read() and not r_tgt_dcache_req.read() ) 
+        {
+            r_tgt_fsm = TGT_RSP_BROADCAST; 
+            r_tgt_icache_req = true;
+            r_tgt_dcache_req = true;
+        }
+        break;
+    }
+    /////////////////////
+    case TGT_REQ_ICACHE:	// set request to ICACHE FSM (if no previous request pending)
+    {
+        if ( not r_tgt_icache_req.read() ) 
+        {
+            r_tgt_fsm = TGT_RSP_ICACHE; 
+            r_tgt_icache_req = true;
+        }
+        break;
+    }
+    ////////////////////
+    case TGT_REQ_DCACHE:	// set request to DCACHE FSM (if no previous request pending)
+    {
+        if ( not r_tgt_dcache_req.read() ) 
+        {
+            r_tgt_fsm = TGT_RSP_DCACHE; 
+            r_tgt_dcache_req = true;
+        }
+        break;
+    }
+    ///////////////////////
+    case TGT_RSP_BROADCAST:	// waiting acknowledge from both DCACHE & ICACHE FSMs
+        			// no response when r_tgt_*cache_rsp is false
+    {
+        if ( not r_tgt_icache_req.read() and not r_tgt_dcache_req.read() ) // both completed
+        {
+            if ( r_tgt_icache_rsp.read() or r_tgt_dcache_rsp.read() )	// at least one response
+            {
+                if ( p_vci_tgt_c.rspack.read() )
+                {
+                    // reset dcache first if activated
+                    if (r_tgt_dcache_rsp)   r_tgt_dcache_rsp = false;
+                    else                    r_tgt_icache_rsp = false;
+                }
+            }
+            else
+            {
+                r_tgt_fsm = TGT_IDLE;
+            }
+        }
+        break;
+    }
+    ////////////////////
+    case TGT_RSP_ICACHE:	// waiting acknowledge from ICACHE FSM
+    {
+        // no response when r_tgt_icache_rsp is false
+        if ( not r_tgt_icache_req.read() and (p_vci_tgt_c.rspack.read() or not r_tgt_icache_rsp.read()))
+        {
+            r_tgt_fsm        = TGT_IDLE;
+            r_tgt_icache_rsp = false;
+        }
+        break;
+    }
+    ////////////////////
+    case TGT_RSP_DCACHE:
+    {
+        // no response when r_tgt_dcache_rsp is false
+        if ( not r_tgt_dcache_req.read() and (p_vci_tgt_c.rspack.read() or not r_tgt_dcache_rsp.read()))
+        {
+            r_tgt_fsm        = TGT_IDLE;
+            r_tgt_dcache_rsp = false;
+        }
+        break;
+    }
+    } // end switch TGT_FSM
+
+    /////////////////////////////////////////////////////////////////////
+    // Get data and instruction requests from processor
+    ///////////////////////////////////////////////////////////////////////
+
+    r_iss.getRequests(m_ireq, m_dreq);
+
+    ////////////////////////////////////////////////////////////////////////////////////
+    //      ICACHE_FSM
+    //
+    // There is 9 conditions to exit the IDLE state:
+    // One condition is a coherence request from TGT FSM :
+    // - Coherence operation				=> ICACHE_CC_CHEK
+    // Five configurations corresponding to XTN processor requests sent by DCACHE FSM :
+    // - Flush TLB 					=> ICACHE_XTN_TLB_FLUSH 
+    // - Flush cache 					=> ICACHE_XTN_CACHE_FLUSH 
+    // - Invalidate a TLB entry 			=> ICACHE_XTN_TLB_INVAL
+    // - Invalidate a cache line 			=> ICACHE_XTN_CACHE_INVAL_VA@
+    // - Invalidate a cache line using physical address	=> ICACHE_XTN_CACHE_INVAL_PA
+    // three configurations corresponding to instruction processor requests :
+    // - tlb miss 					=> ICACHE_TLB_WAIT 
+    // - cacheable read miss 				=> ICACHE_MISS_VICTIM
+    // - uncacheable read miss 				=> ICACHE_UNC_REQ 
+    // 
+    // In case of cache miss, the ICACHE FSM request a VCI transaction to CMD FSM
+    // using the r_icache_tlb_miss_req flip-flop, that reset this flip-flop when the
+    // transaction starts. Then the ICACHE FSM  goes to the ICACHE_MISS VICTIM
+    // state to select a slot and request a VCI transaction to the CLEANUP FSM. 
+    // It goes next to the ICACHE_MISS_WAIT state waiting a response from RSP FSM. 
+    // The availability of the missing cache line is signaled by the response fifo,
+    // and the cache update is done (one word per cycle) in the ICACHE_MISS_UPDT state.
+    // 
+    // In case of uncacheable address, the ICACHE FSM request an uncached VCI transaction
+    // to CMD FSM using the r_icache_unc_req flip-flop, that reset this flip-flop
+    // when the transaction starts. The ICACHE FSM goes to ICACHE_UNC_WAIT to wait
+    // the response from the RSP FSM, through the response fifo. The missing instruction
+    // is directly returned to processor in this state.
+    // 
+    // In case of tlb miss, the ICACHE FSM request to the DCACHE FSM to update the tlb
+    // using the r_icache_tlb_miss_req flip-flop and the r_icache_tlb_miss_vaddr register,
+    // and goes to the ICACHE_TLB_WAIT state.
+    // The tlb update is entirely done by the DCACHE FSM (who becomes the owner of dtlb until
+    // the update is completed, and reset r_icache_tlb_miss_req to signal the completion.
+    //
+    // The DCACHE FSM signals XTN processor requests to ICACHE_FSM
+    // using the r_dcache_xtn_req flip-flop. 
+    // The request opcode and the address to be invalidated are transmitted
+    // in the r_dcache_xtn_opcode and r_dcache_p0_wdata registers respectively.
+    // The r_dcache_xtn_req flip-flop is reset by the ICACHE_FSM when the operation 
+    // is completed.
+    //
+    // The r_vci_rsp_ins_error flip-flop is set by the RSP FSM in case of bus error
+    // in a cache miss or uncacheable read VCI transaction. Nothing is written 
+    // in the response fifo. This flip-flop is reset by the ICACHE-FSM.
+    ////////////////////////////////////////////////////////////////////////////////////////
+
+    // default value for m_irsp
+    m_irsp.valid       = false;
+    m_irsp.error       = false;
+    m_irsp.instruction = 0;
+
+    switch( r_icache_fsm.read() ) 
+    {
+    /////////////////
+    case ICACHE_IDLE:	// In this state, we handle processor requests, XTN requests sent
+                        // by DCACHE FSM, and coherence requests with a fixed priority:
+                        //         coherence > XTN > instruction
+                        // We access the itlb and dcache in parallel with the virtual address
+                        // for itlb, and with a speculative physical address for icache,
+                        // computed during the previous cycle.
+    {
+        // coherence request from the target FSM
+        if ( r_tgt_icache_req.read() )
+        {
+            r_icache_fsm = ICACHE_CC_CHECK;
+            r_icache_fsm_save = r_icache_fsm.read();
+            break;
+        }
+
+        // Decoding processor XTN requests sent by DCACHE FSM  
+        // These request are not executed in this IDLE state, because
+        // they require access to icache or itlb, that are already accessed
+        if ( r_dcache_xtn_req.read() )
+        {
+            if ( (int)r_dcache_xtn_opcode.read() == (int)iss_t::XTN_PTPR ) 
+            {
+                r_icache_fsm         = ICACHE_XTN_TLB_FLUSH;   
+                break;
+            }
+            if ( (int)r_dcache_xtn_opcode.read() == (int)iss_t::XTN_ICACHE_FLUSH)
+            {
+                r_icache_flush_count = 0;
+                r_icache_fsm         = ICACHE_XTN_CACHE_FLUSH;   
+                break;
+            }
+            if ( (int)r_dcache_xtn_opcode.read() == (int)iss_t::XTN_ITLB_INVAL) 
+            {
+                r_icache_fsm         = ICACHE_XTN_TLB_INVAL;   
+                break;
+            }
+            if ( (int)r_dcache_xtn_opcode.read() == (int)iss_t::XTN_ICACHE_INVAL) 
+            {
+                r_icache_fsm         = ICACHE_XTN_CACHE_INVAL_VA;   
+                break;
+            }
+            if ( (int)r_dcache_xtn_opcode.read() == (int)iss_t::XTN_MMU_ICACHE_PA_INV) 
+            {
+		if (sizeof(paddr_t) <= 32) {
+			assert(r_mmu_word_hi.read() == 0 &&
+			    "high bits should be 0 for 32bit paddr");
+			r_icache_vci_paddr = (paddr_t)r_mmu_word_lo.read();
+		} else {
+			r_icache_vci_paddr =
+				(paddr_t)r_mmu_word_hi.read() << 32 | 
+				(paddr_t)r_mmu_word_lo.read();
+		}
+                r_icache_fsm         = ICACHE_XTN_CACHE_INVAL_PA;   
+                break;
+            }
+        } // end if xtn_req
+
+        // processor request
+        if ( m_ireq.valid )
+        {
+            bool	cacheable;
+            paddr_t	paddr;
+
+            // We register processor request
+            r_icache_vaddr_save = m_ireq.addr;
+
+            // speculative icache access (if cache activated)
+            // we use the speculative PPN computed during the previous cycle
+            
+            uint32_t 	cache_inst = 0;
+            bool	cache_hit  = false;
+
+            if ( r_mmu_mode.read() & INS_CACHE_MASK )
+            {
+                paddr_t   spc_paddr = (r_icache_vci_paddr.read() & ~PAGE_K_MASK) |
+                                      ((paddr_t)m_ireq.addr & PAGE_K_MASK);
+
+#ifdef INSTRUMENTATION
+m_cpt_icache_data_read++;
+m_cpt_icache_dir_read++;
+#endif
+                cache_hit = r_icache.read( spc_paddr,
+                                           &cache_inst );
+            }
+
+            // systematic itlb access (if tlb activated)
+            // we use the virtual address
+
+            paddr_t	tlb_paddr;
+            pte_info_t  tlb_flags; 
+            size_t      tlb_way;  
+            size_t      tlb_set;
+            paddr_t     tlb_nline;
+            bool	tlb_hit   = false;;  
+
+            if ( r_mmu_mode.read() & INS_TLB_MASK )
+            {
+
+#ifdef INSTRUMENTATION
+m_cpt_itlb_read++;
+#endif
+                tlb_hit = r_itlb.translate( m_ireq.addr,
+                                            &tlb_paddr,
+                                            &tlb_flags,
+                                            &tlb_nline,	// unused
+                                            &tlb_way,	// unused
+                                            &tlb_set );	// unused
+            }
+
+            // We compute cacheability, physical address and check access rights:
+            // - If MMU activated : cacheability is defined by the C bit in the PTE,
+            //   the physical address is obtained from the TLB, and the access rights are
+            //   defined by the U and X bits in the PTE.
+            // - If MMU not activated : cacheability is defined by the segment table,
+            //   the physical address is equal to the virtual address (identity mapping)
+            //   and there is no access rights checking
+
+            if ( not (r_mmu_mode.read() & INS_TLB_MASK) ) 	// tlb not activated: 
+            {
+                // cacheability
+                if ( not (r_mmu_mode.read() & INS_CACHE_MASK) ) cacheable = false;
+                else     cacheable = m_cacheability_table[m_ireq.addr];
+
+                // physical address
+                paddr = (paddr_t)m_ireq.addr;
+            }
+            else						// itlb activated
+            {
+                if ( tlb_hit )	// tlb hit
+                {  
+                    // cacheability
+                    if ( not (r_mmu_mode.read() & INS_CACHE_MASK) ) cacheable = false;
+                    else  cacheable = tlb_flags.c;
+
+                    // physical address 
+                    paddr       = tlb_paddr;
+
+                    // access rights checking 
+                    if ( not tlb_flags.u && (m_ireq.mode == iss_t::MODE_USER) )
+                    {
+                        r_mmu_ietr        = MMU_READ_PRIVILEGE_VIOLATION;
+                        r_mmu_ibvar       = m_ireq.addr;
+                        m_irsp.valid        = true;
+                        m_irsp.error        = true;
+                        m_irsp.instruction  = 0;
+                        break;
+                    }
+                    else if ( not tlb_flags.x )
+                    {
+                        r_mmu_ietr        = MMU_READ_EXEC_VIOLATION;
+                        r_mmu_ibvar       = m_ireq.addr;
+                        m_irsp.valid        = true;
+                        m_irsp.error        = true;
+                        m_irsp.instruction  = 0;
+                        break;
+                    }
+                }
+                // in case of TLB miss we send an itlb miss request to DCACHE FSM and break
+                else
+                {
+
+#ifdef INSTRUMENTATION
+m_cpt_itlb_miss++;
+#endif
+                    r_icache_fsm          = ICACHE_TLB_WAIT;
+                    r_icache_tlb_miss_req = true;
+                    break;
+                } 
+            } // end if itlb activated
+
+            // physical address registration (for next cycle)
+            r_icache_vci_paddr   = paddr;
+
+            // We enter this section only in case of TLB hit:
+            // Finally, we get the instruction depending on cacheability,
+            // we send the response to processor, and compute next state
+            if ( cacheable )  	// cacheable read
+            {
+                if ( (r_icache_vci_paddr.read() & ~PAGE_K_MASK) 
+                      != (paddr & ~PAGE_K_MASK) ) 	// speculative access KO 
+                {
+
+#ifdef INSTRUMENTATION
+m_cpt_icache_spc_miss++;
+#endif
+                    // we return an invalid response and stay in IDLE state
+                    // the cache access will cost one extra cycle.
+                    break;
+                }
+                
+                if ( not cache_hit )	// cache miss
+                {
+
+#ifdef INSTRUMENTATION
+m_cpt_icache_miss++;
+#endif
+                    r_icache_fsm      = ICACHE_MISS_VICTIM;
+                    r_icache_miss_req = true;
+                }
+                else			// cache hit
+                {
+      
+#ifdef INSTRUMENTATION
+m_cpt_ins_read++; 
+#endif
+                    m_irsp.valid       = true;
+                    m_irsp.instruction = cache_inst;
+                }
+            }
+            else             	// non cacheable read
+            {
+                r_icache_unc_req  = true;
+                r_icache_fsm      = ICACHE_UNC_WAIT;
+            }
+        }    // end if m_ireq.valid
+        break;
+    }
+    /////////////////////
+    case ICACHE_TLB_WAIT:	// Waiting the itlb update by the DCACHE FSM after a tlb miss
+                                // the itlb is udated by the DCACHE FSM, as well as the 
+                                // r_mmu_ietr and r_mmu_ibvar registers in case of error.
+                                // the itlb is not accessed by ICACHE FSM until DCACHE FSM
+                                // reset the r_icache_tlb_miss_req flip-flop
+                                // external coherence request are accepted in this state.
+    {
+        // external coherence request
+        if ( r_tgt_icache_req.read() )
+        {
+            r_icache_fsm = ICACHE_CC_CHECK;
+            r_icache_fsm_save = r_icache_fsm.read();
+            break;
+        }
+
+        if ( m_ireq.valid ) m_cost_ins_tlb_miss_frz++;
+
+        // DCACHE FSM signals response by reseting the request flip-flop
+        if ( not r_icache_tlb_miss_req.read() )
+        {
+            if ( r_icache_tlb_rsp_error.read() ) // error reported : tlb not updated
+            {
+                r_icache_tlb_rsp_error = false;
+                m_irsp.error             = true;
+                m_irsp.valid             = true;
+                r_icache_fsm           = ICACHE_IDLE;
+            }
+            else				// tlb updated : return to IDLE state
+            {
+                r_icache_fsm  = ICACHE_IDLE;
+            }
+        }
+        break;
+    }
+    //////////////////////////
+    case ICACHE_XTN_TLB_FLUSH:   	// invalidate in one cycle all non global TLB entries
+    {   
+        r_itlb.flush();   
+        r_dcache_xtn_req     = false;
+        r_icache_fsm         = ICACHE_IDLE;
+        break;
+    }
+    ////////////////////////////
+    case ICACHE_XTN_CACHE_FLUSH:	// Invalidate sequencially all cache lines using
+                                        // the r_icache_flush_count register as a slot counter.
+                                	// We loop in this state until all slots have been visited.
+                       		        // A cleanup request is generated for each valid line 
+                                	// and we are blocked until the previous cleanup is completed
+    {
+        if ( not r_icache_cleanup_req.read() )
+        {
+            size_t	way = r_icache_flush_count.read()/m_icache_sets;
+            size_t	set = r_icache_flush_count.read()%m_icache_sets;
+            paddr_t 	nline;
+            bool 	cleanup_req = r_icache.inval( way, 
+                                                      set, 
+                                                      &nline );
+            if ( cleanup_req )
+            {
+                r_icache_cleanup_req  = true;
+                r_icache_cleanup_line = nline;
+            }
+            r_icache_flush_count = r_icache_flush_count.read() + 1;
+        
+		
+            if ( r_icache_flush_count.read() == (m_icache_sets*m_icache_ways - 1) )
+            {
+            	r_dcache_xtn_req 	= false;
+            	r_icache_fsm 	= ICACHE_IDLE;
+            }
+        }
+       
+        break;
+    }
+    //////////////////////////
+    case ICACHE_XTN_TLB_INVAL: 		// invalidate one TLB entry selected by the virtual address 
+        				// stored in the r_dcache_p0_wdata register
+    {
+        r_itlb.inval(r_dcache_p0_wdata.read());
+        r_dcache_xtn_req     = false;
+        r_icache_fsm         = ICACHE_IDLE;
+        break;
+    }
+    ///////////////////////////////
+    case ICACHE_XTN_CACHE_INVAL_VA:	// Selective cache line invalidate with virtual address
+                                        // requires 3 cycles (in case of hit on itlb and icache).
+					// In this state, we access TLB to translate virtual address 
+        				// stored in the r_dcache_p0_wdata register.
+    {
+        paddr_t 	paddr;                     
+        bool    	hit;
+
+        // read physical address in TLB when MMU activated
+        if ( r_mmu_mode.read() & INS_TLB_MASK ) 	// itlb activated
+        {
+
+#ifdef INSTRUMENTATION
+m_cpt_itlb_read++;
+#endif
+            hit = r_itlb.translate(r_dcache_p0_wdata.read(), 
+                                   &paddr); 
+        } 
+        else 						// itlb not activated
+        {
+            paddr 	= (paddr_t)r_dcache_p0_wdata.read();
+            hit 	= true;
+        }
+
+        if ( hit )		// continue the selective inval process
+        {
+            r_icache_vci_paddr    = paddr;                
+            r_icache_fsm          = ICACHE_XTN_CACHE_INVAL_PA;
+        }
+        else			// miss : send a request to DCACHE FSM
+        {
+
+#ifdef INSTRUMENTATION
+m_cpt_itlb_miss++;
+#endif
+            r_icache_tlb_miss_req = true;
+	    r_icache_vaddr_save   = r_dcache_p0_wdata.read();
+            r_icache_fsm          = ICACHE_TLB_WAIT;
+        }
+        break;
+    }
+    ///////////////////////////////
+    case ICACHE_XTN_CACHE_INVAL_PA:	// selective invalidate cache line with physical address 
+                                        // require 2 cycles. In this state, we read dcache,
+                                        // with address stored in r_icache_vci_paddr register.
+    {
+        uint32_t	data;
+        size_t		way;
+        size_t		set;
+        size_t		word;
+        bool 		hit = r_icache.read(r_icache_vci_paddr.read(),
+                                            &data,
+                                            &way,
+                                            &set,
+                                            &word);
+        if ( hit )	// inval to be done
+        {
+                r_icache_miss_way = way;
+                r_icache_miss_set = set;
+                r_icache_fsm      = ICACHE_XTN_CACHE_INVAL_GO;
+        }
+        else		// miss : acknowlege the XTN request and return
+        {
+            r_dcache_xtn_req = false; 
+            r_icache_fsm     = ICACHE_IDLE;
+        }
+        break;
+    }
+    ///////////////////////////////
+    case ICACHE_XTN_CACHE_INVAL_GO: 	// In this state, we invalidate the cache line & cleanup.
+                                        // We are blocked if the previous cleanup is not completed
+    {
+        paddr_t nline;
+
+        if ( not r_icache_cleanup_req.read() )
+        {
+	    bool hit;
+            hit = r_icache.inval( r_icache_miss_way.read(),
+                                  r_icache_miss_set.read(),
+                                  &nline );
+	    assert(hit && "XTN_ICACHE_INVAL way/set should still be in icache");
+  
+            // request cleanup 
+            r_icache_cleanup_req  = true;
+            r_icache_cleanup_line = nline;
+            // acknowledge the XTN request and return
+            r_dcache_xtn_req      = false; 
+            r_icache_fsm          = ICACHE_IDLE;
+        }
+        break;
+    }
+
+    ////////////////////////
+    case ICACHE_MISS_VICTIM:               // Selects a victim line
+                                           // Set the r_icache_cleanup_req flip-flop 
+                                           // when the selected slot is not empty
+    {
+        m_cost_ins_miss_frz++;
+
+        size_t index; 	// unused
+        bool hit = r_cleanup_buffer.hit( r_icache_vci_paddr.read()>>(uint32_log2(m_icache_words)+2), &index );
+        if ( not hit and not r_icache_cleanup_req.read() )
+        {
+            bool	valid;
+            size_t  	way;
+            size_t  	set;
+            paddr_t 	victim;
+
+            valid = r_icache.victim_select(r_icache_vci_paddr.read(),
+                                           &victim, 
+                                           &way, 
+                                           &set);
+            r_icache_miss_way     = way;
+            r_icache_miss_set     = set;
+
+            if ( valid )
+            {
+                r_icache_cleanup_req  = true;
+                r_icache_cleanup_line = victim;
+                r_icache_fsm          = ICACHE_MISS_INVAL;
+            }
+            else
+            {
+                r_icache_fsm          = ICACHE_MISS_WAIT;
+            }
+        }
+        break;
+    }
+    ///////////////////////
+    case ICACHE_MISS_INVAL:	// invalidate the victim line
+    {
+        paddr_t	nline;
+	bool hit;
+
+        hit = r_icache.inval( r_icache_miss_way.read(),
+                        r_icache_miss_set.read(),
+                        &nline );	// unused
+	assert(hit && "selected way/set line should be in icache");
+
+        r_icache_fsm = ICACHE_MISS_WAIT;
+        break;
+    }
+    //////////////////////
+    case ICACHE_MISS_WAIT:	// waiting a response to a miss request from VCI_RSP FSM
+    {
+        if ( m_ireq.valid ) m_cost_ins_miss_frz++;
+
+        // external coherence request
+        if ( r_tgt_icache_req.read() )     
+        {
+            r_icache_fsm = ICACHE_CC_CHECK;
+            r_icache_fsm_save = r_icache_fsm.read();
+            break;
+        }
+
+	if ( r_vci_rsp_ins_error.read() ) // bus error 
+	{
+            r_mmu_ietr = MMU_READ_DATA_ILLEGAL_ACCESS; 
+            r_mmu_ibvar  = r_icache_vaddr_save.read();
+            m_irsp.valid           = true;
+            m_irsp.error           = true;
+            r_vci_rsp_ins_error  = false;
+            r_icache_fsm = ICACHE_IDLE;
+        }
+        else if ( r_vci_rsp_fifo_icache.rok() ) // response available
+        {
+            r_icache_miss_word = 0;
+            r_icache_fsm       = ICACHE_MISS_UPDT;  
+	}	
+        break;
+    }
+    //////////////////////
+    case ICACHE_MISS_UPDT:	// update the cache (one word per cycle)
+    {
+        if ( m_ireq.valid ) m_cost_ins_miss_frz++;
+
+        if ( r_vci_rsp_fifo_icache.rok() )	// response available
+        {
+            if ( r_icache_miss_inval )  // Matching coherence request
+                                        // We pop the response FIFO, without updating the cache
+                                        // We send a cleanup for the missing line at the last word
+                                        // Blocked if the previous cleanup is not completed
+            {
+                if ( r_icache_miss_word.read() < m_icache_words-1 ) 	// not the last word
+                {
+                    vci_rsp_fifo_icache_get = true;
+                    r_icache_miss_word = r_icache_miss_word.read() + 1;
+                }
+                else							// last word
+                {
+                    if ( not r_icache_cleanup_req.read() )	// no pending cleanup
+                    {
+                        vci_rsp_fifo_icache_get = true;
+                        r_icache_cleanup_req    = true;
+                        r_icache_cleanup_line   = r_icache_vci_paddr.read() >> (uint32_log2(m_icache_words<<2));
+                        r_icache_miss_inval     = false;
+                        r_icache_fsm            = ICACHE_IDLE;
+                    }
+                }
+            }
+            else			// No matching coherence request
+                                        // We pop the FIFO and update the cache 
+                                        // We update the directory at the last word
+            {
+
+#ifdef INSTRUMENTATION
+m_cpt_icache_data_write++;
+#endif
+                r_icache.write( r_icache_miss_way.read(),
+                                r_icache_miss_set.read(),
+                                r_icache_miss_word.read(),
+                                r_vci_rsp_fifo_icache.read() );
+                vci_rsp_fifo_icache_get = true;
+                r_icache_miss_word = r_icache_miss_word.read() + 1;
+                if ( r_icache_miss_word.read() == m_icache_words-1 )  // last word
+                {
+
+#ifdef INSTRUMENTATION
+m_cpt_icache_dir_write++;
+#endif
+                    r_icache.victim_update_tag( r_icache_vci_paddr.read(),
+                                                r_icache_miss_way.read(),
+                                                r_icache_miss_set.read() );
+                    r_icache_fsm = ICACHE_IDLE;
+                }
+            }
+        }
+        break;
+    }
+    ////////////////////
+    case ICACHE_UNC_WAIT:	// waiting a response to an uncacheable read from VCI_RSP FSM
+                                // 
+    {
+        // external coherence request
+        if ( r_tgt_icache_req.read() ) 
+        {
+            r_icache_fsm      = ICACHE_CC_CHECK;
+            r_icache_fsm_save = r_icache_fsm.read();
+            break;
+        }
+
+	if ( r_vci_rsp_ins_error.read() ) // bus error
+        {
+            r_mmu_ietr          = MMU_READ_DATA_ILLEGAL_ACCESS;    
+            r_mmu_ibvar         = m_ireq.addr;
+            r_vci_rsp_ins_error = false;
+            m_irsp.valid        = true;
+            m_irsp.error        = true;
+            r_icache_fsm        = ICACHE_IDLE;
+        }
+        else if (r_vci_rsp_fifo_icache.rok() ) // instruction available
+        {
+            vci_rsp_fifo_icache_get = true;
+            r_icache_fsm            = ICACHE_IDLE;
+            if ( m_ireq.valid and (m_ireq.addr == r_icache_vaddr_save.read()) )  // request not modified
+            {
+                m_irsp.valid       = true;
+                m_irsp.instruction = r_vci_rsp_fifo_icache.read();
+            }
+	}	
+        break;
+    }
+    /////////////////////
+    case ICACHE_CC_CHECK:   	// This state is the entry point of a sub-fsm
+                                // handling coherence requests.
+                                // the return state is defined in r_icache_fsm_save.
+    {
+        paddr_t  paddr = r_tgt_paddr.read();
+        paddr_t  mask  = ~((m_icache_words<<2)-1);
+
+        if( (r_icache_fsm_save.read() == ICACHE_MISS_WAIT) and
+                ((r_icache_vci_paddr.read() & mask) == (paddr & mask))) 	// matching a pending miss
+        {
+            r_icache_miss_inval = true;				// signaling the matching
+            r_tgt_icache_req    = false;			// coherence request completed
+            r_tgt_icache_rsp    = r_tgt_update.read(); 		// response required if update
+            r_icache_fsm        = r_icache_fsm_save.read();
+        }
+        else  								// no match
+        {
+
+#ifdef INSTRUMENTATION
+m_cpt_icache_dir_read++;
+#endif
+            uint32_t	inst;
+            size_t 	way;
+            size_t 	set;
+            size_t 	word;
+            bool   	hit = r_icache.read(paddr, 
+                                            &inst,
+                                            &way, 
+                                            &set, 
+                                            &word);
+            r_icache_cc_way = way;
+            r_icache_cc_set = set;
+
+            if ( hit and r_tgt_update.read() )           // hit update
+            {
+                r_icache_fsm         = ICACHE_CC_UPDT;
+                r_icache_cc_word     = r_tgt_word_min.read();
+            }
+            else if ( hit and not r_tgt_update.read() )  // hit inval
+            {
+                r_icache_fsm           = ICACHE_CC_INVAL;
+            }
+            else                                         // miss can happen
+            {
+                r_tgt_icache_req = false;
+                r_tgt_icache_rsp = r_tgt_update.read();
+                r_icache_fsm     = r_icache_fsm_save.read();
+            }
+        }
+        break;
+    }
+
+    /////////////////////
+    case ICACHE_CC_INVAL:  	// invalidate a cache line
+    {                       
+        paddr_t	nline;
+	bool hit;
+        hit = r_icache.inval( r_icache_cc_way.read(),
+                              r_icache_cc_set.read(), 
+                              &nline );
+	assert (hit && "ICACHE_CC_INVAL way/set should still be in icache");
+        r_tgt_icache_req = false;
+        r_tgt_icache_rsp = true;
+        r_icache_fsm     = r_icache_fsm_save.read();
+        break;
+    }
+    ////////////////////
+    case ICACHE_CC_UPDT:	// write one word per cycle (from word_min to word_max)
+    {
+        size_t  word  = r_icache_cc_word.read();
+        size_t  way   = r_icache_cc_way.read();
+        size_t  set   = r_icache_cc_set.read();
+
+        r_icache.write( way,
+                        set,
+                        word,
+                        r_tgt_buf[word],
+                        r_tgt_be[word] );
+
+        r_icache_cc_word = word+1;
+
+        if ( word == r_tgt_word_max.read() )	// last word
+        {
+            r_tgt_icache_req = false;
+            r_tgt_icache_rsp = true;
+            r_icache_fsm     = r_icache_fsm_save.read();
+        }
+        break;
+    }
+
+    } // end switch r_icache_fsm
+
+    ////////////////////////////////////////////////////////////////////////////////////
+    //      DCACHE FSM 
+    //
+    // Both the Cacheability Table, and the MMU cacheable bit are used to define
+    // the cacheability, depending on the MMU mode.
+    // 
+    // 1/ Coherence requests : 
+    //    There is a coherence request when the tgt_dcache_req flip-flop is set,
+    //    requesting a line invalidation or a line update. 
+    //    Coherence requests are taken into account in IDLE, UNC_WAIT, MISS_WAIT states.
+    //    The actions associated to the pre-empted state are not executed, the DCACHE FSM
+    //    goes to the CC_CHECK state to execute the requested action, and returns to the
+    //    pre-empted state.
+    //
+    // 2/ TLB miss
+    //    The page tables can be cacheable.
+    //    In case of miss in itlb or dtlb, the tlb miss is handled by a dedicated
+    //    sub-fsm (DCACHE_TLB_MISS state), that handle possible miss in DCACHE,
+    //    this sub-fsm implement the table-walk...
+    //
+    // 3/ processor requests : 
+    //    Processor READ, WRITE, LL or SC requests are taken in IDLE state only.
+    //    The IDLE state implements a three stages pipe-line to handle write bursts:
+    //    - The physical address is computed by dtlb in stage P0.
+    //    - The registration in wbuf and the dcache hit are computed in stage P1. 
+    //    - The dcache update is done in stage P2.  
+    //    WRITE or SC requests can require a PTE Dirty bit update (in memory), 
+    //    that is done (before handling the processor request) by a dedicated sub-fsm 
+    //    (DCACHE_DIRTY_TLB_SET state).
+    //    If a PTE is modified, both the itlb and dtlb are selectively, but sequencially
+    //    cleared by a dedicated sub_fsm (DCACHE_INVAL_TLB_SCAN state).
+    //    If there is no write in the pipe, dcache and dtlb are accessed in parallel,
+    //    (virtual address for itlb, and speculative physical address computed during 
+    //    previous cycle for dcache) in order to return the data in one cycle for a READ
+    //    request. We just pay an extra cycle when the speculative access is failing.
+    //
+    // 4/ Atomic instructions LL/SC
+    //    The LL/SC address can be cacheable or non cacheable.
+    //    The llsc_local_table holds a registration for an active LL/SC
+    //    operation (with an address, a registration key, an aging counter and a
+    //    valid bit).
+    //    - LL requests from the processor are transmitted as a one flit VCI
+    //      CMD_LOCKED_READ transaction with TYPE_LL as PKTID value. PLEN must
+    //      be 8 as the response is 2 flits long (data and registration key) 
+    //    - SC requests from the processor are systematically transmitted to the 
+    //      memory cache as 2 flits VCI CMD_NOP (or CMD_STORE_COND)
+    //      transactions, with TYPE_SC as PKTID value (the first flit contains
+    //      the registration key, the second flit contains the data to write in
+    //      case of success).
+    //      The cache is not updated, as this is done in case of success by the
+    //      coherence transaction.
+    //
+    // 5/ Non cacheable access:
+    //    This component implement a strong order between non cacheable access
+    //    (read or write) : A new non cacheable VCI transaction starts only when
+    //    the previous non cacheable transaction is completed. Both cacheable and
+    //    non cacheable transactions use the write buffer, but the DCACHE FSM registers
+    //    a non cacheable write transaction posted in the write buffer by setting the
+    //    r_dcache_pending_unc_write flip_flop. All other non cacheable requests
+    //    are stalled until this flip-flop is reset by the VCI_RSP_FSM (when the 
+    //    pending non cacheable write transaction completes).
+    //
+    // 6/ Error handling:  
+    //    When the MMU is not activated, Read Bus Errors are synchronous events, 
+    //    but Write Bus Errors are asynchronous events (processor is not frozen).
+    //    - If a Read Bus Error is detected, the VCI_RSP FSM sets the
+    //      r_vci_rsp_data_error flip-flop, without writing any data in the
+    //      r_vci_rsp_fifo_dcache FIFO, and the synchronous error is signaled
+    //      by the DCACHE FSM.
+    //    - If a Write Bus Error is detected, the VCI_RSP FSM  signals
+    //      the asynchronous error using the setWriteBerr() method.
+    //    When the MMU is activated bus error are rare events, as the MMU
+    //    checks the physical address before the VCI transaction starts.
+    ////////////////////////////////////////////////////////////////////////////////////////
+
+    // default value for m_drsp 
+    m_drsp.valid = false;
+    m_drsp.error = false;
+    m_drsp.rdata = 0;
+    
+    // keep track of the local llsc table access and perform a NOP access if
+    // necessary at the end of the DCACHE transition function
+    bool llsc_local_table_access_done = false;
+
+    switch ( r_dcache_fsm.read() ) 
+    {
+    case DCACHE_IDLE:	// There are 9 conditions to exit the IDLE state :
+						// 1) Dirty bit update (processor)    => DCACHE_DIRTY_GET_PTE
+						// 2) Coherence request (TGT FSM)     => DCACHE_CC_CHECK 
+						// 3) ITLB miss request (ICACHE FSM)  => DCACHE_TLB_MISS
+						// 4) XTN request (processor)         => DCACHE_XTN_*
+						// 5) DTLB miss (processor)           => DCACHE_TLB_MISS
+						// 6) Cacheable read miss (processor) => DCACHE_MISS_VICTIM
+						// 7) Uncacheable read (processor)    => DCACHE_UNC_WAIT 
+						// 8) LL access (processor)           => DCACHE_LL_WAIT
+						// 9) SC access (processor)           => DCACHE_SC_WAIT
+                        //
+                        // The dtlb is unconditionally accessed to translate the
+                        // virtual adress from processor.
+                        //
+                        // There is 4 configurations to access the cache, 
+                        // depending on the pipe-line state, defined 
+                        // by the r_dcache_p0_valid (V0) flip-flop : P1 stage activated
+                        // and    r_dcache_p1_valid (V1) flip-flop : P2 stage activated
+                        //  V0 / V1 / Data      / Directory / comment                    
+                        //  0  / 0  / read(A0)  / read(A0)  / read speculative access  
+                        //  0  / 1  / write(A2) / nop       / read request delayed
+                        //  1  / 0  / nop       / read(A1)  / read request delayed
+                        //  1  / 1  / write(A2) / read(A1)  / read request delayed
+    { 
+        bool tlb_inval_required = false;
+        bool write_pipe_frozen  = false;
+
+        ////////////////////////////////////////////////////////////////////////////////
+        // Handling P2 pipe-line stage 
+        // Inputs are r_dcache_p1_* registers.
+        // If r_dcache_p1_valid is true, we update the local copy in dcache.
+        // If the modified cache line has copies in TLBs, we launch a TLB invalidate
+        // operation, going to DCACHE_INVAL_TLB_SCAN state.
+
+        if ( r_dcache_p1_valid.read() )		// P2 stage activated
+        {
+            size_t   way        = r_dcache_p1_cache_way.read();
+            size_t   set        = r_dcache_p1_cache_set.read();
+            size_t   word       = r_dcache_p1_cache_word.read();
+            uint32_t wdata      = r_dcache_p1_wdata.read();
+            vci_be_t be         = r_dcache_p1_be.read();
+
+            r_dcache.write( way,
+                            set,
+                            word,
+                            wdata,
+                            be );
+#ifdef INSTRUMENTATION
+m_cpt_dcache_data_write++; 
+#endif
+            // cache update after a WRITE hit can require itlb & dtlb inval or flush
+            if ( r_dcache_in_tlb[way*m_dcache_sets+set] )
+            {
+                tlb_inval_required       = true;
+	            r_dcache_tlb_inval_count = 0;
+	            r_dcache_tlb_inval_line  = r_dcache_p1_paddr.read()>>
+                                             (uint32_log2(m_dcache_words<<2)); 
+	            r_dcache_in_tlb[way*m_dcache_sets+set] = false;
+            }
+            else if ( r_dcache_contains_ptd[way*m_dcache_sets+set] )
+            {
+                r_itlb.reset();
+                r_dtlb.reset();
+	            r_dcache_contains_ptd[way*m_dcache_sets+set] = false;
+            }
+
+#if DEBUG_DCACHE
+if ( m_debug_dcache_fsm )
+{
+    std::cout << "  <PROC " << name() << ".DCACHE_IDLE> Cache update in P2 stage" << std::dec
+              << " / WAY = " << way 
+              << " / SET = " << set 
+              << " / WORD = " << word << std::hex
+              << " / DATA = " << wdata
+              << " / BE = " << be << std::endl;
+}
+#endif
+        } // end P2 stage
+
+        ///////////////////////////////////////////////////////////////////////////
+        // Handling P1 pipe-line stage 
+        // Inputs are r_dcache_p0_* registers.
+        // We must write into wbuf and test the hit in dcache.
+        // If the write request is non cacheable, and there is a pending
+        // non cacheable write, or if the write buffer is full, the P0 and P1 stages 
+        // are frozen until the write request registration is possible, 
+        // while the P2 stage is not frozen.
+        // The r_dcache_p1_valid bit must be computed at all cycles, and 
+        // the P2 stage must be activated if there is a local copy in dcache. 
+
+        if ( r_dcache_p0_valid.read() )  // P1 stage activated
+        {
+            // frozen if write not cacheable, and previous non cacheable write registered
+            if ( not r_dcache_p0_cacheable.read() and r_dcache_pending_unc_write.read() ) 
+            {
+                r_dcache_p1_valid = false;
+                write_pipe_frozen = true;
+            }
+            else		// try a registration into write buffer
+            {
+
+                bool wok = r_wbuf.write( r_dcache_p0_paddr.read(),
+                                         r_dcache_p0_be.read(),
+                                         r_dcache_p0_wdata.read(),
+                                         r_dcache_p0_cacheable.read() );
+#ifdef INSTRUMENTATION 
+m_cpt_wbuf_write++;
+#endif
+                if ( not wok ) // frozen if write buffer full
+                {
+                    r_dcache_p1_valid = false;
+                    write_pipe_frozen = true;
+                }
+                else          // update the write_buffer state extension
+                {
+                    if(not r_dcache_pending_unc_write.read())
+                        r_dcache_pending_unc_write = not r_dcache_p0_cacheable.read();
+
+                    // read directory to check local copy
+                    size_t  cache_way;
+                    size_t  cache_set;
+                    size_t  cache_word;
+                    bool    local_copy;
+                    if ( r_mmu_mode.read() & DATA_CACHE_MASK) 	// cache activated
+                    {
+                        local_copy = r_dcache.hit( r_dcache_p0_paddr.read(),
+                                                   &cache_way,
+                                                   &cache_set,
+                                                   &cache_word );
+#ifdef INSTRUMENTATION
+m_cpt_dcache_dir_read++; 
+#endif
+                    }
+                    else
+                    {
+                        local_copy = false;
+                    }
+
+                    // store values for P2 pipe stage
+                    if ( local_copy )
+                    {
+                        r_dcache_p1_valid       = true;
+                        r_dcache_p1_wdata       = r_dcache_p0_wdata.read();
+                        r_dcache_p1_be          = r_dcache_p0_be.read();
+                        r_dcache_p1_paddr       = r_dcache_p0_paddr.read();
+                        r_dcache_p1_cache_way   = cache_way;
+                        r_dcache_p1_cache_set   = cache_set;
+                        r_dcache_p1_cache_word  = cache_word;
+                    }
+                    else
+                    {
+                        r_dcache_p1_valid       = false;
+                    }
+                }
+            }
+        }
+        else  // P1 stage not activated 
+        {
+            r_dcache_p1_valid = false; 
+        } // end P1 stage
+
+        /////////////////////////////////////////////////////////////////////////////////
+        // handling P0 pipe-line stage
+        // This stage is controlling r_dcache_fsm and r_dcache_p0_* registers. 
+        // The r_dcache_p0_valid flip-flop is only set in case of a WRITE request.
+        // - the TLB invalidate requests have the highest priority,
+        // - then the external coherence requests,
+        // - then the itlb miss requests,
+        // - and finally the processor requests. 
+        // If dtlb is activated, there is an unconditionnal access to dtlb, 
+        // for address translation.
+        // 1) A processor WRITE request is blocked if the Dirty bit mus be set, or if 
+        //    dtlb miss. If dtlb is OK, It enters the three stage pipe-line (fully 
+        //    handled by the IDLE state), and the processor request is acknowledged.
+        // 2) A processor READ request generate a simultaneouss access to
+        //    both dcache data and dcache directoty, using speculative PPN, but
+        //    is delayed if the write pipe-line is not empty.
+        //    In case of miss, we wait the VCI response in DCACHE_UNC_WAIT or 
+        //    DCACHE_MISS_WAIT states.
+        // 3) A processor LL request generate a VCI LL transaction. We wait for
+        //    the response in DCACHE_LL_WAIT state.
+        // 4) A processor SC request is delayed until the write pipe-line is empty.
+        //    A VCI SC transaction is launched, and we wait the VCI response in
+        //    DCACHE_SC_WAIT state. It can be completed by a "long write" if the 
+        //    PTE dirty bit must be updated in dtlb, dcache, and RAM.
+        //    The data is not modified in dcache, as it will be done by the
+        //    coherence transaction.   
+
+        // TLB inval required after a write hit
+        if ( tlb_inval_required )
+        {
+            r_dcache_fsm_scan_save = r_dcache_fsm.read();
+            r_dcache_fsm           = DCACHE_INVAL_TLB_SCAN;
+            r_dcache_p0_valid      = r_dcache_p0_valid.read() and write_pipe_frozen;
+        }
+        // external coherence request 
+        else if ( r_tgt_dcache_req.read() )   
+        {
+            r_dcache_fsm_cc_save = r_dcache_fsm.read();
+            r_dcache_fsm         = DCACHE_CC_CHECK;
+            r_dcache_p0_valid    = r_dcache_p0_valid.read() and write_pipe_frozen;
+        }        
+
+        // processor request
+        else if ( m_dreq.valid and not write_pipe_frozen )
+        {
+            // dcache access using speculative PPN only if pipe-line empty
+            paddr_t		cache_paddr;
+            size_t		cache_way;
+            size_t		cache_set;
+            size_t		cache_word;
+            uint32_t	cache_rdata;
+            bool	    cache_hit;
+
+            if ( (r_mmu_mode.read() & DATA_CACHE_MASK) and 	// cache activated
+                 not r_dcache_p0_valid.read() and 
+                 not r_dcache_p1_valid.read() )			// pipe-line empty
+            {
+                cache_paddr = (r_dcache_p0_paddr.read() & ~PAGE_K_MASK) | 
+                              ((paddr_t)m_dreq.addr & PAGE_K_MASK);
+
+                cache_hit = r_dcache.read( cache_paddr,
+                                           &cache_rdata,
+                                           &cache_way,
+                                           &cache_set,
+                                           &cache_word );
+#ifdef INSTRUMENTATION
+m_cpt_dcache_dir_read++;
+m_cpt_dcache_data_read++;
+#endif
+            }
+            else
+            {
+                cache_hit = false;
+            } // end dcache access    
+
+            // systematic dtlb access using virtual address
+            paddr_t	tlb_paddr;
+            pte_info_t 	tlb_flags; 
+            size_t     	tlb_way; 
+            size_t     	tlb_set; 
+            paddr_t    	tlb_nline; 
+            bool	tlb_hit;    	
+
+            if ( r_mmu_mode.read() & DATA_TLB_MASK )	// DTLB activated
+            {
+                tlb_hit = r_dtlb.translate( m_dreq.addr,
+                                            &tlb_paddr,
+                                            &tlb_flags,
+                                            &tlb_nline,
+                                            &tlb_way,	
+                                            &tlb_set );	
+#ifdef INSTRUMENTATION
+m_cpt_dtlb_read++;
+#endif
+            }
+            else
+            {
+                tlb_hit = false;
+            } // end dtlb access
+
+            // register the processor request
+            r_dcache_p0_vaddr = m_dreq.addr;
+            r_dcache_p0_be    = m_dreq.be;
+            r_dcache_p0_wdata = m_dreq.wdata;
+
+            // Handling READ XTN requests from processor
+            // They are executed in this DCACHE_IDLE state.
+            // The processor must not be in user mode
+            if (m_dreq.type == iss_t::XTN_READ) 
+            {
+                int xtn_opcode = (int)m_dreq.addr/4;
+
+                // checking processor mode:
+                if (m_dreq.mode  == iss_t::MODE_USER)
+                {
+                    r_mmu_detr = MMU_READ_PRIVILEGE_VIOLATION; 
+                    r_mmu_dbvar  = m_dreq.addr;
+                    m_drsp.valid            = true;
+                    m_drsp.error            = true;
+                    r_dcache_fsm          = DCACHE_IDLE;
+                }
+                else 
+                {
+                    switch( xtn_opcode ) 
+                    {
+                    case iss_t::XTN_INS_ERROR_TYPE:
+                        m_drsp.rdata = r_mmu_ietr.read();
+                        m_drsp.valid = true;
+                        break;
+
+                    case iss_t::XTN_DATA_ERROR_TYPE:
+                        m_drsp.rdata = r_mmu_detr.read();
+                        m_drsp.valid = true;
+                        break;
+
+                    case iss_t::XTN_INS_BAD_VADDR:
+                        m_drsp.rdata = r_mmu_ibvar.read();       
+                        m_drsp.valid = true;
+                        break;
+
+                    case iss_t::XTN_DATA_BAD_VADDR:
+                        m_drsp.rdata = r_mmu_dbvar.read();        
+                        m_drsp.valid = true;
+                        break;
+
+                    case iss_t::XTN_PTPR:
+                        m_drsp.rdata = r_mmu_ptpr.read();
+                        m_drsp.valid = true;
+                        break;
+
+                    case iss_t::XTN_TLB_MODE:
+                        m_drsp.rdata = r_mmu_mode.read();
+                        m_drsp.valid = true;
+                        break;
+
+                    case iss_t::XTN_MMU_PARAMS:
+                        m_drsp.rdata = r_mmu_params;
+                        m_drsp.valid = true;
+                        break;
+
+                    case iss_t::XTN_MMU_RELEASE:
+                        m_drsp.rdata = r_mmu_release;
+                        m_drsp.valid = true;
+                        break;
+
+                    case iss_t::XTN_MMU_WORD_LO:
+                        m_drsp.rdata = r_mmu_word_lo.read();
+                        m_drsp.valid = true;
+                        break;
+
+                    case iss_t::XTN_MMU_WORD_HI:
+                        m_drsp.rdata = r_mmu_word_hi.read();
+                        m_drsp.valid = true;
+                        break;
+
+                    default:
+                        r_mmu_detr = MMU_READ_UNDEFINED_XTN; 
+                        r_mmu_dbvar  = m_dreq.addr;
+                        m_drsp.valid = true;
+                        m_drsp.error = true;
+                        break;
+                    } // end switch xtn_opcode
+                } // end else
+                r_dcache_p0_valid = false;
+            } // end if XTN_READ
+
+            // Handling WRITE XTN requests from processor.
+            // They are not executed in this DCACHE_IDLE state,
+            // if they require access to the caches or the TLBs
+            // that are already accessed for speculative read.
+            // Caches can be invalidated or flushed in user mode,
+            // and the sync instruction can be executed in user mode
+            else if (m_dreq.type == iss_t::XTN_WRITE) 
+            {
+                int xtn_opcode      = (int)m_dreq.addr/4;
+                r_dcache_xtn_opcode = xtn_opcode;
+
+                // checking processor mode:
+                if ( (m_dreq.mode  == iss_t::MODE_USER) &&
+                     (xtn_opcode != iss_t:: XTN_SYNC) &&
+                     (xtn_opcode != iss_t::XTN_DCACHE_INVAL) &&
+                     (xtn_opcode != iss_t::XTN_DCACHE_FLUSH) &&
+                     (xtn_opcode != iss_t::XTN_ICACHE_INVAL) &&
+                     (xtn_opcode != iss_t::XTN_ICACHE_FLUSH) )
+                {
+                    r_mmu_detr = MMU_WRITE_PRIVILEGE_VIOLATION; 
+                    r_mmu_dbvar  = m_dreq.addr;
+                    m_drsp.valid          = true;
+                    m_drsp.error          = true;
+                    r_dcache_fsm        = DCACHE_IDLE;
+                }
+                else
+                {
+                    switch( xtn_opcode ) 
+                    {     
+                    case iss_t::XTN_PTPR:   			// itlb & dtlb must be flushed
+                        r_dcache_xtn_req = true;
+                        r_dcache_fsm     = DCACHE_XTN_SWITCH;
+                        break;
+
+                    case iss_t::XTN_TLB_MODE:			// no cache or tlb access 
+                        r_mmu_mode = m_dreq.wdata;
+                        m_drsp.valid = true;
+                        r_dcache_fsm = DCACHE_IDLE;
+                        break;
+
+                    case iss_t::XTN_DTLB_INVAL:     		// dtlb access
+                        r_dcache_fsm = DCACHE_XTN_DT_INVAL;  
+                        break;
+
+                    case iss_t::XTN_ITLB_INVAL:     		// itlb access
+                        r_dcache_xtn_req = true;
+                        r_dcache_fsm = DCACHE_XTN_IT_INVAL;  
+                        break;
+
+                    case iss_t::XTN_DCACHE_INVAL:   		// dcache, dtlb & itlb access
+                        r_dcache_fsm = DCACHE_XTN_DC_INVAL_VA;
+                        break;
+
+                    case iss_t::XTN_MMU_DCACHE_PA_INV:  	// dcache, dtlb & itlb access
+                        r_dcache_fsm   = DCACHE_XTN_DC_INVAL_PA;
+			if (sizeof(paddr_t) <= 32) {
+				assert(r_mmu_word_hi.read() == 0 &&
+				    "high bits should be 0 for 32bit paddr");
+				r_dcache_p0_paddr =
+					(paddr_t)r_mmu_word_lo.read();
+			} else {
+				r_dcache_p0_paddr =
+					(paddr_t)r_mmu_word_hi.read() << 32 | 
+					(paddr_t)r_mmu_word_lo.read();
+			}
+                        break;
+
+                    case iss_t::XTN_DCACHE_FLUSH:   	       // itlb and dtlb must be reset  
+                        r_dcache_flush_count = 0;
+                        r_dcache_fsm         = DCACHE_XTN_DC_FLUSH; 
+                        break;
+
+                    case iss_t::XTN_ICACHE_INVAL:   		// icache and itlb access
+                        r_dcache_xtn_req = true;
+                        r_dcache_fsm     = DCACHE_XTN_IC_INVAL_VA; 
+                        break;
+
+                    case iss_t::XTN_MMU_ICACHE_PA_INV:		// icache access 
+                        r_dcache_xtn_req = true;
+                        r_dcache_fsm     = DCACHE_XTN_IC_INVAL_PA; 
+                        break;
+
+                    case iss_t::XTN_ICACHE_FLUSH:   		// icache access
+                        r_dcache_xtn_req = true; 
+                        r_dcache_fsm     = DCACHE_XTN_IC_FLUSH;
+                        break;
+
+                    case iss_t::XTN_SYNC:           		// wait until write buffer empty
+                        r_dcache_fsm     = DCACHE_XTN_SYNC;
+                        break;
+
+                    case iss_t::XTN_MMU_WORD_LO: 		// no cache or tlb access
+                        r_mmu_word_lo = m_dreq.wdata;
+                        m_drsp.valid    = true;
+                        r_dcache_fsm  = DCACHE_IDLE;
+                        break;
+
+                    case iss_t::XTN_MMU_WORD_HI: 		// no cache or tlb access
+                        r_mmu_word_hi = m_dreq.wdata;
+                        m_drsp.valid    = true;
+                        r_dcache_fsm  = DCACHE_IDLE;
+                        break;
+
+	            case iss_t::XTN_ICACHE_PREFETCH:		// not implemented : no action
+	            case iss_t::XTN_DCACHE_PREFETCH:		// not implemented : no action
+                        m_drsp.valid   = true;
+                        r_dcache_fsm = DCACHE_IDLE;
+		        break;
+	
+                    default:
+                        r_mmu_detr = MMU_WRITE_UNDEFINED_XTN; 
+                        r_mmu_dbvar  = m_dreq.addr;
+                        m_drsp.valid = true;
+                        m_drsp.error = true;
+                        r_dcache_fsm = DCACHE_IDLE;
+                        break;
+                    } // end switch xtn_opcode
+                } // end else 
+                r_dcache_p0_valid = false;
+            } // end if XTN_WRITE
+
+            // Handling read/write/ll/sc processor requests.
+            // The dtlb and dcache can be activated or not.
+            // We compute the physical address, the cacheability, and check processor request.
+            // - If DTLB not activated : cacheability is defined by the segment table,
+            //   the physical address is equal to the virtual address (identity mapping)
+            // - If DTLB activated : cacheability is defined by the C bit in the PTE,
+            //   the physical address is obtained from the TLB, and the U & W bits
+            //   of the PTE are checked. 
+            // The processor request is decoded only if the TLB is not activated or if
+            // the virtual address hits in tLB and access rights are OK.
+            // We call the TLB_MISS sub-fsm in case of dtlb miss.
+            else
+            {
+                bool	valid_req = false;
+                bool	cacheable = false;
+                paddr_t	paddr     = 0;
+
+                if ( not (r_mmu_mode.read() & DATA_TLB_MASK) )		// dtlb not activated 
+                {
+                    valid_req     = true;
+
+                    // cacheability
+                    if ( not (r_mmu_mode.read() & DATA_CACHE_MASK) ) cacheable = false;
+                    else cacheable = m_cacheability_table[m_dreq.addr];
+
+                    // physical address
+                    paddr       = (paddr_t)m_dreq.addr;
+                }
+                else 							// dtlb activated
+                {
+                    if ( tlb_hit )					// tlb hit
+                    {
+                        // cacheability
+                        if ( not (r_mmu_mode.read() & DATA_CACHE_MASK) ) cacheable = false;
+                        else cacheable = tlb_flags.c;
+
+                        // access rights checking 
+                        if ( not tlb_flags.u and (m_dreq.mode == iss_t::MODE_USER)) 
+                        {
+                            if ( (m_dreq.type == iss_t::DATA_READ) or (m_dreq.type == iss_t::DATA_LL) )
+                                r_mmu_detr = MMU_READ_PRIVILEGE_VIOLATION;
+                            else 
+                                r_mmu_detr = MMU_WRITE_PRIVILEGE_VIOLATION;
+
+                            r_mmu_dbvar  = m_dreq.addr;
+                            m_drsp.valid   = true;
+                            m_drsp.error   = true;
+                            m_drsp.rdata   = 0;
+#if DEBUG_DCACHE
+if ( m_debug_dcache_fsm )
+{
+    std::cout << "  <PROC " << name() << ".DCACHE_IDLE> HIT in dtlb, but privilege violation" << std::endl;
+}
+#endif
+                        }
+                        else if ( not tlb_flags.w and 
+                                  ((m_dreq.type == iss_t::DATA_WRITE) or 
+                                   (m_dreq.type == iss_t::DATA_SC)) ) 
+                        {
+                            r_mmu_detr   = MMU_WRITE_ACCES_VIOLATION;  
+                            r_mmu_dbvar  = m_dreq.addr;
+                            m_drsp.valid   = true;
+                            m_drsp.error   = true;
+                            m_drsp.rdata   = 0;
+#if DEBUG_DCACHE
+if ( m_debug_dcache_fsm )
+{
+    std::cout << "  <PROC " << name() << ".DCACHE_IDLE> HIT in dtlb, but writable violation" << std::endl;
+}
+#endif
+                        }
+                        else
+                        {
+                            valid_req    = true;
+                        }
+
+                        // physical address
+                        paddr = tlb_paddr;
+                    }
+                    else						// tlb miss
+                    {
+                        r_dcache_tlb_vaddr   = m_dreq.addr;
+                        r_dcache_tlb_ins     = false; 
+                        r_dcache_fsm         = DCACHE_TLB_MISS;
+                    }
+                }    // end DTLB activated
+
+                if ( valid_req ) 	// processor request is valid after TLB check
+                {
+                    // physical address and cacheability registration 
+                    r_dcache_p0_paddr          = paddr;
+                    r_dcache_p0_cacheable      = cacheable;
+
+                    // READ request
+                    // The read requests are taken only if the write pipe-line is empty.
+                    // If dcache hit, dtlb hit, and speculative PPN OK, data in one cycle.
+                    // If speculative access is KO we just pay one extra cycle.
+                    // If dcache miss, we go to DCACHE_MISS_VICTIM state.
+                    // If uncacheable, we go to DCACHE_UNC_WAIT state.
+                    if ( ((m_dreq.type == iss_t::DATA_READ)) 
+                        and not r_dcache_p0_valid.read() and not r_dcache_p1_valid.read() )
+                    { 
+                        if ( cacheable )            		// cacheable read
+                        {
+                            // if the speculative access is illegal, we pay an extra cycle
+                            if ( (r_dcache_p0_paddr.read() & ~PAGE_K_MASK) 
+                                 != (paddr & ~PAGE_K_MASK))
+                            {
+#ifdef INSTRUMENTATION
+m_cpt_dcache_spec_miss++;
+#endif
+#if DEBUG_DCACHE
+if ( m_debug_dcache_fsm )
+{
+    std::cout << "  <PROC " << name() << ".DCACHE_IDLE> Speculative access miss" << std::endl;
+}
+#endif
+                            }
+                            // if cache miss, try to get the missing line
+                            else if ( not cache_hit )
+                            {
+#ifdef INSTRUMENTATION
+m_cpt_dcache_miss++;
+#endif
+                                r_dcache_vci_paddr    = paddr;
+                                r_dcache_vci_miss_req = true;
+                                r_dcache_miss_type    = PROC_MISS;
+                                r_dcache_fsm          = DCACHE_MISS_VICTIM;
+                            }
+                            // if cache hit return the data
+                            else                    
+                            {
+#ifdef INSTRUMENTATION
+m_cpt_data_read++;
+#endif
+                                m_drsp.valid   = true;
+                                m_drsp.rdata   = cache_rdata;
+#if DEBUG_DCACHE
+if ( m_debug_dcache_fsm )
+{
+    std::cout << "  <PROC " << name() << ".DCACHE_IDLE> HIT in dcache" << std::endl;
+}
+#endif
+                            }
+                        }
+                        else					// uncacheable read
+                        {
+                            r_dcache_vci_paddr    = paddr;
+                            r_dcache_vci_unc_be   = m_dreq.be;
+                            r_dcache_vci_unc_req  = true;
+                            r_dcache_fsm          = DCACHE_UNC_WAIT;
+                        }
+
+                        r_dcache_p0_valid = false;
+                    } // end READ
+
+                    // LL request
+                    // The LL requests are taken only if the write pipe-line is empty.
+                    // We request an LL transaction to CMD FSM and go to
+                    // DCACHE_LL_WAIT state, that will return the response to
+                    // the processor.
+                    else if ( ((m_dreq.type == iss_t::DATA_LL))
+                        and not r_dcache_p0_valid.read() and not r_dcache_p1_valid.read() )
+                    {
+                        // prepare llsc local table access
+                        table_in.cmd       = LLSCLocalTable::LL_CMD ;
+                        table_in.address   = paddr;
+                        // access the table
+                        r_llsc_table.exec(table_in, table_out);
+                        llsc_local_table_access_done = true;
+                        // test if the table is done
+                        if(!table_out.done)
+                        {
+                            r_dcache_p0_valid     = false;
+                            break;
+                        }
+                        // request an LL CMD and go to DCACHE_LL_WAIT state
+                        r_dcache_vci_ll_req   = true;
+                        r_dcache_ll_rsp_count = 0;
+                        r_dcache_p0_valid     = false;
+                        r_dcache_vci_paddr    = paddr;
+                        r_dcache_fsm          = DCACHE_LL_WAIT;
+                    }// end LL
+
+                    // WRITE request:
+                    // If the TLB is activated and the PTE Dirty bit is not set, we stall 
+                    // the processor and set the Dirty bit before handling the write request. 
+                    // If we don't need to set the Dirty bit, we can acknowledge
+                    // the processor request, as the write arguments (including the
+                    // physical address) are registered in r_dcache_p0 registers:
+                    // We simply activate the P1 pipeline stage.
+                    else if ( m_dreq.type == iss_t::DATA_WRITE )
+                    {
+                        if ( (r_mmu_mode.read() & DATA_TLB_MASK ) 
+                              and not tlb_flags.d )		// Dirty bit must be set
+                        {
+                            // The PTE physical address is obtained from the nline value (dtlb),
+                            // and the word index (proper bits of the virtual address)
+                            if ( tlb_flags.b )	// PTE1
+                            {
+                                r_dcache_dirty_paddr = (paddr_t)(tlb_nline*(m_dcache_words<<2)) |
+                                                       (paddr_t)((m_dreq.addr>>19) & 0x3c);
+                            }
+                            else		// PTE2
+                            {
+                                r_dcache_dirty_paddr = (paddr_t)(tlb_nline*(m_dcache_words<<2)) |
+                                                       (paddr_t)((m_dreq.addr>>9) & 0x38);
+                            }
+                            r_dcache_fsm      = DCACHE_DIRTY_GET_PTE;
+                            r_dcache_p0_valid = false;
+                        }
+                        else					// Write request accepted
+                        {
+#ifdef INSTRUMENTATION
+m_cpt_data_write++;
+#endif
+                            table_in.cmd       = LLSCLocalTable::SW_CMD ;
+                            table_in.address   = paddr;
+                            r_llsc_table.exec(table_in, table_out)  ;
+                            llsc_local_table_access_done = true;
+                            if(!table_out.done)
+                            {
+                                r_dcache_p0_valid     = false;
+                                break;
+                            }
+                            m_drsp.valid      = true;
+                            m_drsp.rdata      = 0;
+                            r_dcache_p0_valid = true;
+                        }
+                    } // end WRITE
+ 
+                    // SC request:
+                    // The SC requests are taken only if the write pipe-line is empty.
+                    //  We test if a DIRTY bit update is required.
+                    //  If the TLB is activated and the PTE Dirty bit is not set, we stall 
+                    //  the processor and set the Dirty bit before handling the write request. 
+                    //  If we don't need to set the Dirty bit, we request a SC transaction 
+                    //  to CMD FSM and go to DCACHE_SC_WAIT state, that will return 
+                    //  the response to the processor. 
+                    //  We don't check a possible write hit in dcache, as the cache update 
+                    //  is done by the coherence transaction induced by the SC...
+                    else if ( ( m_dreq.type == iss_t::DATA_SC )
+                        and not r_dcache_p0_valid.read() and not r_dcache_p1_valid.read() )
+                    {
+                        if ( (r_mmu_mode.read() & DATA_TLB_MASK ) 
+                              and not tlb_flags.d )			// Dirty bit must be set
+                        {
+                            // The PTE physical address is obtained from the nline value (dtlb),
+                            // and the word index (virtual address)
+                            if ( tlb_flags.b )	// PTE1
+                            {
+                                r_dcache_dirty_paddr = (paddr_t)(tlb_nline*(m_dcache_words<<2)) |
+                                                       (paddr_t)((m_dreq.addr>>19) & 0x3c);
+                            }
+                            else			// PTE2
+                            {
+                                r_dcache_dirty_paddr = (paddr_t)(tlb_nline*(m_dcache_words<<2)) |
+                                                       (paddr_t)((m_dreq.addr>>9) & 0x38);
+                            }
+                            r_dcache_fsm           = DCACHE_DIRTY_GET_PTE;
+                        }
+                        else					// SC request accepted
+                        {
+#ifdef INSTRUMENTATION
+m_cpt_data_sc++;
+#endif
+                            // prepare llsc local table access
+                            table_in.cmd       = LLSCLocalTable::SC_CMD ;
+                            table_in.address   = paddr;
+                            // access the table
+                            r_llsc_table.exec(table_in, table_out)  ;
+                            llsc_local_table_access_done = true;
+                            // test if the table is done
+                            if(!table_out.done)
+                            {
+                                r_dcache_p0_valid     = false;
+                                break;
+                            }
+                            // test for a local fail
+                            if(table_out.hit)
+                            {
+                                // request an SC CMD and go to DCACHE_SC_WAIT state
+                                r_sc_key             = table_out.key;
+                                r_dcache_vci_paddr   = paddr;
+                                r_dcache_vci_sc_req  = true;
+                                r_dcache_vci_sc_data = m_dreq.wdata;
+                                r_dcache_fsm         = DCACHE_SC_WAIT;
+                            }
+                            else // local fail
+                            {
+	                            m_drsp.valid = true;
+	                            m_drsp.rdata = 0x1;
+                            }
+                        }
+                        r_dcache_p0_valid = false;
+                    } // end SC
+                    else
+                    {
+                        r_dcache_p0_valid = false;
+                    }
+                } // end valid_req
+                else
+                {
+                    r_dcache_p0_valid = false;
+                }
+            }  // end if read/write/ll/sc request	
+        } // end dreq.valid
+        
+        // itlb miss request 
+    	else if ( r_icache_tlb_miss_req.read() )
+        {
+            r_dcache_tlb_ins    = true;
+            r_dcache_tlb_vaddr  = r_icache_vaddr_save.read();
+            r_dcache_fsm        = DCACHE_TLB_MISS;
+            r_dcache_p0_valid   = r_dcache_p0_valid.read() and write_pipe_frozen;
+        }
+        else
+        {
+            r_dcache_p0_valid = r_dcache_p0_valid.read() and write_pipe_frozen;
+        } // end P0 pipe stage
+        break;
+    } 
+    /////////////////////
+    case DCACHE_TLB_MISS: // This is the entry point for the sub-fsm handling all tlb miss.
+                          // Input arguments are:
+                          // - r_dcache_tlb_vaddr
+                          // - r_dcache_tlb_ins (true when itlb miss) 
+                          // The sub-fsm access the dcache to find the missing TLB entry,
+                          // and activates the cache miss procedure in case of miss.
+                          // It bypass the first level page table access if possible.
+                          // It uses atomic access to update the R/L access bits
+                          // in the page table if required.
+                          // It directly updates the itlb or dtlb, and writes into the 
+                          // r_mmu_ins_* or r_mmu_data* error reporting registers.
+    {
+        uint32_t	ptba = 0;
+        bool		bypass;
+        paddr_t		pte_paddr;
+
+        // evaluate bypass in order to skip first level page table access
+        if ( r_dcache_tlb_ins.read() )				// itlb miss
+        {
+            bypass = r_itlb.get_bypass(r_dcache_tlb_vaddr.read(), &ptba);
+        }
+        else							// dtlb miss
+        {
+            bypass = r_dtlb.get_bypass(r_dcache_tlb_vaddr.read(), &ptba);
+        }
+
+        if ( not bypass )     // Try to read PTE1/PTD1 in dcache
+        {
+            pte_paddr = (paddr_t)r_mmu_ptpr.read() << (INDEX1_NBITS+2) |
+                        (paddr_t)((r_dcache_tlb_vaddr.read() >> PAGE_M_NBITS) << 2);
+            r_dcache_tlb_paddr = pte_paddr;
+            r_dcache_fsm       = DCACHE_TLB_PTE1_GET;
+        }
+        else                  // Try to read PTE2 in dcache
+        {
+            pte_paddr = (paddr_t)ptba << PAGE_K_NBITS |
+                        (paddr_t)(r_dcache_tlb_vaddr.read()&PTD_ID2_MASK)>>(PAGE_K_NBITS-3);
+            r_dcache_tlb_paddr = pte_paddr;
+            r_dcache_fsm       = DCACHE_TLB_PTE2_GET;
+        }
+
+#if DEBUG_DCACHE
+if ( m_debug_dcache_fsm )
+{
+    if ( r_dcache_tlb_ins.read() ) 
+    {
+        std::cout << "  <PROC " << name() << ".DCACHE_TLB_MISS> ITLB miss";
+    }
+    else
+    {                           
+        std::cout << "  <PROC " << name() << ".DCACHE_TLB_MISS> DTLB miss";
+    }
+    std::cout << " / VADDR = " << std::hex << r_dcache_tlb_vaddr.read()
+              << " / BYPASS = " << bypass 
+              << " / PTE_ADR = " << pte_paddr << std::endl;
+}
+#endif
+  
+        break;
+    }
+    /////////////////////////  
+    case DCACHE_TLB_PTE1_GET:	// try to read a PT1 entry in dcache
+    {
+        uint32_t 	entry;
+        size_t		way;
+        size_t		set;
+        size_t		word;
+
+        bool     hit = r_dcache.read( r_dcache_tlb_paddr.read(),
+                                      &entry,
+                                      &way,
+                                      &set,
+                                      &word );
+#ifdef INSTRUMENTATION
+m_cpt_dcache_data_read++;
+m_cpt_dcache_dir_read++;
+#endif
+        if ( hit )	//  hit in dcache 
+        {
+            if ( not (entry & PTE_V_MASK) )	// unmapped
+            {
+                if ( r_dcache_tlb_ins.read() ) 
+                {
+                    r_mmu_ietr             = MMU_READ_PT1_UNMAPPED;
+                    r_mmu_ibvar            = r_dcache_tlb_vaddr.read();
+                    r_icache_tlb_miss_req  = false;
+                    r_icache_tlb_rsp_error = true;
+                }
+                else
+                {
+                    r_mmu_detr             = MMU_READ_PT1_UNMAPPED;
+                    r_mmu_dbvar            = r_dcache_tlb_vaddr.read();
+                    m_drsp.valid             = true;
+                    m_drsp.error             = true;
+                }
+                r_dcache_fsm          = DCACHE_IDLE;
+
+#if DEBUG_DCACHE
+if ( m_debug_dcache_fsm )
+{
+    std::cout << "  <PROC " << name() << ".DCACHE_TLB_PTE1_GET> HIT in dcache, but unmapped"
+              << std::hex << " / paddr = " << r_dcache_tlb_paddr.read()
+              << std::dec << " / way = " << way
+              << std::dec << " / set = " << set
+              << std::dec << " / word = " << word
+              << std::hex << " / PTE1 = " << entry << std::endl;
+}
+#endif
+  
+            }
+            else if( entry & PTE_T_MASK ) 	//  PTD : me must access PT2
+            {
+                // mark the cache line ac containing a PTD
+                r_dcache_contains_ptd[m_dcache_sets*way+set] = true;
+
+                // register bypass
+                if ( r_dcache_tlb_ins.read() )		// itlb
+                {
+                    r_itlb.set_bypass(r_dcache_tlb_vaddr.read(),
+                                      entry & ((1 << (m_paddr_nbits-PAGE_K_NBITS)) - 1), 
+                                      r_dcache_tlb_paddr.read() >> (uint32_log2(m_icache_words<<2))); 
+                }
+                else					// dtlb
+                {
+                    r_dtlb.set_bypass(r_dcache_tlb_vaddr.read(),
+                                      entry & ((1 << (m_paddr_nbits-PAGE_K_NBITS)) - 1),
+                                      r_dcache_tlb_paddr.read() >> (uint32_log2(m_dcache_words)+2));
+                }
+                r_dcache_tlb_paddr = (paddr_t)(entry & ((1<<(m_paddr_nbits-PAGE_K_NBITS))-1)) << PAGE_K_NBITS |
+                                     (paddr_t)(((r_dcache_tlb_vaddr.read() & PTD_ID2_MASK) >> PAGE_K_NBITS) << 3);
+                r_dcache_fsm       = DCACHE_TLB_PTE2_GET;
+
+#if DEBUG_DCACHE
+if ( m_debug_dcache_fsm )
+{
+    std::cout << "  <PROC " << name() << ".DCACHE_TLB_PTE1_GET> HIT in dcache"
+              << std::hex << " / paddr = " << r_dcache_tlb_paddr.read()
+              << std::dec << " / way = " << way
+              << std::dec << " / set = " << set
+              << std::dec << " / word = " << word
+              << std::hex << " / PTD = " << entry << std::endl;
+}
+#endif
+            }
+            else			//  PTE1 :  we must update the TLB
+            {
+                r_dcache_in_tlb[m_icache_sets*way+set] = true;
+                r_dcache_tlb_pte_flags  = entry;
+                r_dcache_tlb_cache_way  = way;
+                r_dcache_tlb_cache_set  = set;
+                r_dcache_tlb_cache_word = word;
+                r_dcache_fsm            = DCACHE_TLB_PTE1_SELECT;
+
+#if DEBUG_DCACHE
+if ( m_debug_dcache_fsm )
+{
+    std::cout << "  <PROC " << name() << ".DCACHE_TLB_PTE1_GET> HIT in dcache"
+              << std::hex << " / paddr = " << r_dcache_tlb_paddr.read()
+              << std::dec << " / way = " << way
+              << std::dec << " / set = " << set
+              << std::dec << " / word = " << word
+              << std::hex << " / PTE1 = " << entry << std::endl;
+}
+#endif
+            }
+        }
+        else		// we must load the missing cache line in dcache
+        {
+            r_dcache_vci_miss_req  = true;		
+            r_dcache_vci_paddr     = r_dcache_tlb_paddr.read(); 
+            r_dcache_miss_type     = PTE1_MISS;
+            r_dcache_fsm           = DCACHE_MISS_VICTIM;	 
+
+#if DEBUG_DCACHE
+if ( m_debug_dcache_fsm )
+{
+    std::cout << "  <PROC " << name() << ".DCACHE_TLB_PTE1_GET> MISS in dcache:"
+              << " PTE1 address = " << std::hex << r_dcache_tlb_paddr.read() << std::endl;
+}
+#endif
+        }
+        break;
+    }
+    ////////////////////////////
+    case DCACHE_TLB_PTE1_SELECT:	// select a slot for PTE1 
+    {
+        size_t 	way;
+        size_t 	set;
+
+        if ( r_dcache_tlb_ins.read() )
+        {
+            r_itlb.select( r_dcache_tlb_vaddr.read(),
+                           true,  // PTE1 
+                           &way,
+                           &set );
+#ifdef INSTRUMENTATION
+m_cpt_itlb_read++;
+#endif
+        }
+        else
+        {
+            r_dtlb.select( r_dcache_tlb_vaddr.read(),
+                           true,  // PTE1 
+                           &way,
+                           &set );
+#ifdef INSTRUMENTATION
+m_cpt_dtlb_read++;
+#endif
+        }
+        r_dcache_tlb_way = way;
+        r_dcache_tlb_set = set;
+        r_dcache_fsm     = DCACHE_TLB_PTE1_UPDT;
+
+#if DEBUG_DCACHE
+if ( m_debug_dcache_fsm )
+{
+    if ( r_dcache_tlb_ins.read() ) 
+        std::cout << "  <PROC " << name() << ".DCACHE_TLB_PTE1_SELECT> Select a slot in ITLB:";
+    else                           
+        std::cout << "  <PROC " << name() << ".DCACHE_TLB_PTE1_SELECT> Select a slot in DTLB:";
+        std::cout << " way = " << std::dec << way
+                  << " / set = " << set << std::endl;
+}
+#endif
+        break;
+    }
+    //////////////////////////
+    case DCACHE_TLB_PTE1_UPDT:	// write a new PTE1 in tlb after testing the L/R bit
+                                // - if L/R bit already set, exit the sub-fsm.
+                                // - if not, we update the page table but we dont write
+                                //   neither in DCACHE, nor in TLB, as this will be done by
+                                //   the coherence mechanism.
+    {
+        paddr_t	  nline    = r_dcache_tlb_paddr.read() >> (uint32_log2(m_dcache_words)+2);   
+        uint32_t  pte      = r_dcache_tlb_pte_flags.read();
+        bool	  pt_updt  = false;
+        bool	  local    = true;
+
+        // We should compute the access locality: 
+        // The PPN MSB bits define the destination cluster index.
+        // The m_srcid_d MSB bits define the source cluster index.
+        // The number of bits to compare depends on the number of clusters, 
+        // and can be obtained in the mapping table.
+        // As long as this computation is not done, all access are local.
+
+        if ( local )						// local access
+        {
+            if ( not ((pte & PTE_L_MASK) == PTE_L_MASK) ) // we must set the L bit
+            {
+                pt_updt                = true;
+                r_dcache_vci_cas_old    = pte;
+                r_dcache_vci_cas_new    = pte | PTE_L_MASK;
+                pte                    = pte | PTE_L_MASK;
+                r_dcache_tlb_pte_flags = pte;
+            }
+        }
+        else 							// remote access
+        {
+            if ( not ((pte & PTE_R_MASK) == PTE_R_MASK) ) // we must set the R bit
+            {
+                pt_updt                = true;
+                r_dcache_vci_cas_old    = pte;
+                r_dcache_vci_cas_new    = pte | PTE_R_MASK;
+                pte                    = pte | PTE_R_MASK;
+                r_dcache_tlb_pte_flags = pte;
+            }
+        }
+
+        if ( not pt_updt )					// update TLB and return
+        {
+            if ( r_dcache_tlb_ins.read() )  
+            {
+                r_itlb.write( true,		// 2M page
+                              pte,
+                              0,		// argument unused for a PTE1
+                              r_dcache_tlb_vaddr.read(),    
+                              r_dcache_tlb_way.read(), 
+                              r_dcache_tlb_set.read(),
+                              nline );
+#ifdef INSTRUMENTATION
+m_cpt_itlb_write++;
+#endif
+
+#if DEBUG_DCACHE
+if ( m_debug_dcache_fsm )
+{
+    std::cout << "  <PROC " << name() << ".DCACHE_TLB_PTE1_UPDT> write PTE1 in ITLB";
+    std::cout << " / set = " << std::dec << r_dcache_tlb_set.read()
+              << " / way = " << r_dcache_tlb_way.read() << std::endl;
+    r_itlb.printTrace();
+}
+#endif
+            }
+            else
+            {
+                r_dtlb.write( true,		// 2M page
+                              pte,
+                              0,		// argument unused for a PTE1
+                              r_dcache_tlb_vaddr.read(),    
+                              r_dcache_tlb_way.read(), 
+                              r_dcache_tlb_set.read(),
+                              nline );
+#ifdef INSTRUMENTATION
+m_cpt_dtlb_write++;
+#endif
+
+#if DEBUG_DCACHE
+if ( m_debug_dcache_fsm )
+{
+    std::cout << "  <PROC " << name() << ".DCACHE_TLB_PTE1_UPDT> write PTE1 in DTLB";
+    std::cout << " / set = " << std::dec << r_dcache_tlb_set.read()
+              << " / way = " << r_dcache_tlb_way.read() << std::endl;
+    r_dtlb.printTrace();
+}
+#endif
+            }
+            r_dcache_fsm = DCACHE_TLB_RETURN;
+        }
+        else                            // update page table but not TLB
+        {
+            r_dcache_fsm = DCACHE_TLB_LR_UPDT; 
+
+#if DEBUG_DCACHE
+if ( m_debug_dcache_fsm )
+{
+    std::cout << "  <PROC " << name() << ".DCACHE_TLB_PTE1_UPDT> L/R bit update required"
+              << std::endl;
+}
+#endif
+        }
+        break;
+    }
+    /////////////////////////
+    case DCACHE_TLB_PTE2_GET:	// Try to get a PTE2 (64 bits) in the dcache
+    {
+        uint32_t 	pte_flags;
+        uint32_t 	pte_ppn;
+        size_t   	way;
+        size_t   	set;
+        size_t		word; 
+ 
+        bool     hit = r_dcache.read( r_dcache_tlb_paddr.read(),
+                                      &pte_flags,
+                                      &pte_ppn,
+                                      &way,
+                                      &set,
+                                      &word );
+#ifdef INSTRUMENTATION
+m_cpt_dcache_data_read++;
+m_cpt_dcache_dir_read++;
+#endif
+        if ( hit )      // request hits in dcache 
+        {
+            if ( not (pte_flags & PTE_V_MASK) )	// unmapped
+            {
+                if ( r_dcache_tlb_ins.read() ) 
+                {
+                    r_mmu_ietr             = MMU_READ_PT2_UNMAPPED;
+                    r_mmu_ibvar            = r_dcache_tlb_vaddr.read();
+                    r_icache_tlb_miss_req  = false;
+                    r_icache_tlb_rsp_error = true;
+                }
+                else
+                {
+                    r_mmu_detr             = MMU_READ_PT2_UNMAPPED;
+                    r_mmu_dbvar            = r_dcache_tlb_vaddr.read();
+                    m_drsp.valid             = true;
+                    m_drsp.error             = true;
+                }
+                r_dcache_fsm          = DCACHE_IDLE;
+
+#if DEBUG_DCACHE
+if ( m_debug_dcache_fsm )
+{
+    std::cout << "  <PROC " << name() << ".DCACHE_TLB_PTE2_GET> HIT in dcache, but PTE is unmapped"
+              << " PTE_FLAGS = " << std::hex << pte_flags 
+              << " PTE_PPN = " << std::hex << pte_ppn << std::endl;
+}
+#endif
+            }
+            else				// mapped : we must update the TLB
+            {
+                r_dcache_in_tlb[m_dcache_sets*way+set] = true;
+                r_dcache_tlb_pte_flags  = pte_flags;
+                r_dcache_tlb_pte_ppn    = pte_ppn;
+                r_dcache_tlb_cache_way  = way;
+                r_dcache_tlb_cache_set  = set;
+                r_dcache_tlb_cache_word = word;
+                r_dcache_fsm            = DCACHE_TLB_PTE2_SELECT;
+
+#if DEBUG_DCACHE
+if ( m_debug_dcache_fsm )
+{
+    std::cout << "  <PROC " << name() << ".DCACHE_TLB_PTE2_GET> HIT in dcache:"
+              << " PTE_FLAGS = " << std::hex << pte_flags 
+              << " PTE_PPN = " << std::hex << pte_ppn << std::endl;
+}
+#endif
+             }
+        }
+        else            // we must load the missing cache line in dcache
+        {
+            r_dcache_fsm          = DCACHE_MISS_VICTIM; 
+            r_dcache_vci_miss_req = true;
+            r_dcache_vci_paddr    = r_dcache_tlb_paddr.read();
+            r_dcache_miss_type    = PTE2_MISS;
+
+#if DEBUG_DCACHE
+if ( m_debug_dcache_fsm )
+{
+    std::cout << "  <PROC " << name() << ".DCACHE_TLB_PTE2_GET> MISS in dcache:"
+              << " PTE address = " << std::hex << r_dcache_tlb_paddr.read() << std::endl;
+}
+#endif
+        }
+        break;
+    }
+    ////////////////////////////
+    case DCACHE_TLB_PTE2_SELECT:    // select a slot for PTE2
+    {
+        size_t way;
+        size_t set;
+
+        if ( r_dcache_tlb_ins.read() )
+        {
+            r_itlb.select( r_dcache_tlb_vaddr.read(),
+                           false,	// PTE2 
+                           &way,
+                           &set );
+#ifdef INSTRUMENTATION
+m_cpt_itlb_read++;
+#endif
+        }
+        else
+        {
+            r_dtlb.select( r_dcache_tlb_vaddr.read(),
+                           false,	// PTE2 
+                           &way,
+                           &set );
+#ifdef INSTRUMENTATION
+m_cpt_dtlb_read++;
+#endif
+        }
+
+#if DEBUG_DCACHE
+if ( m_debug_dcache_fsm )
+{
+    if ( r_dcache_tlb_ins.read() ) 
+        std::cout << "  <PROC " << name() << ".DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB:";
+    else                           
+        std::cout << "  <PROC " << name() << ".DCACHE_TLB_PTE2_SELECT> Select a slot in DTLB:";
+        std::cout << " way = " << std::dec << way
+                  << " / set = " << set << std::endl;
+}
+#endif
+        r_dcache_tlb_way = way;
+        r_dcache_tlb_set = set;
+        r_dcache_fsm     = DCACHE_TLB_PTE2_UPDT;
+        break;
+    }
+    //////////////////////////
+    case DCACHE_TLB_PTE2_UPDT:	// write a new PTE2 in tlb after testing the L/R bit
+                                // - if L/R bit already set, exit the sub-fsm.
+                                // - if not, we update the page table but we dont write
+                                //   neither in DCACHE, nor in TLB, as this will be done by
+                                //   the coherence mechanism.
+    {
+        paddr_t	        nline     = r_dcache_tlb_paddr.read() >> (uint32_log2(m_dcache_words)+2);   
+        uint32_t        pte_flags = r_dcache_tlb_pte_flags.read();
+        uint32_t        pte_ppn   = r_dcache_tlb_pte_ppn.read();
+        bool            pt_updt   = false;
+        bool            local     = true;
+
+        // We should compute the access locality: 
+        // The PPN MSB bits define the destination cluster index.
+        // The m_srcid_d MSB bits define the source cluster index.
+        // The number of bits to compare depends on the number of clusters, 
+        // and can be obtained in the mapping table.
+        // As long as this computation is not done, all access are local.
+
+        if ( local )						// local access
+        {
+            if ( not ((pte_flags & PTE_L_MASK) == PTE_L_MASK) ) // we must set the L bit
+            {
+                pt_updt                = true;
+                r_dcache_vci_cas_old    = pte_flags;
+                r_dcache_vci_cas_new    = pte_flags | PTE_L_MASK;
+                pte_flags              = pte_flags | PTE_L_MASK;
+		        r_dcache_tlb_pte_flags = pte_flags;
+            }
+        }
+        else                                                    // remote access
+        {
+            if ( not ((pte_flags & PTE_R_MASK) == PTE_R_MASK) ) // we must set the R bit
+            {
+                pt_updt                = true;
+                r_dcache_vci_cas_old    = pte_flags;
+                r_dcache_vci_cas_new    = pte_flags | PTE_R_MASK;
+                pte_flags              = pte_flags | PTE_R_MASK;
+		        r_dcache_tlb_pte_flags = pte_flags;
+            }
+        }
+        
+        if ( not pt_updt )                       // update TLB 
+        {
+            if ( r_dcache_tlb_ins.read() )  
+            {
+                r_itlb.write( false,	// 4K page
+                              pte_flags,
+                              pte_ppn,
+                              r_dcache_tlb_vaddr.read(),    
+                              r_dcache_tlb_way.read(), 
+                              r_dcache_tlb_set.read(),
+                              nline );
+#ifdef INSTRUMENTATION
+m_cpt_itlb_write++;
+#endif
+
+#if DEBUG_DCACHE
+if ( m_debug_dcache_fsm )
+{
+    std::cout << "  <PROC " << name() << ".DCACHE_TLB_PTE2_UPDT> write PTE2 in ITLB";
+    std::cout << " / set = " << std::dec << r_dcache_tlb_set.read()
+              << " / way = " << r_dcache_tlb_way.read() << std::endl;
+    r_itlb.printTrace();
+}
+#endif
+            }
+            else
+            {
+                r_dtlb.write( false,	// 4K page
+                              pte_flags,
+                              pte_ppn,
+                              r_dcache_tlb_vaddr.read(),    
+                              r_dcache_tlb_way.read(), 
+                              r_dcache_tlb_set.read(),
+                              nline );
+#ifdef INSTRUMENTATION
+m_cpt_dtlb_write++;
+#endif
+
+#if DEBUG_DCACHE
+if ( m_debug_dcache_fsm )
+{
+    std::cout << "  <PROC " << name() << ".DCACHE_TLB_PTE2_UPDT> write PTE2 in DTLB";
+    std::cout << " / set = " << std::dec << r_dcache_tlb_set.read()
+              << " / way = " << r_dcache_tlb_way.read() << std::endl;
+    r_dtlb.printTrace();
+}
+#endif
+
+            }
+            r_dcache_fsm = DCACHE_TLB_RETURN;
+        }
+        else                                   // update page table but not TLB
+        {
+            r_dcache_fsm = DCACHE_TLB_LR_UPDT; 	// dcache and page table update
+
+#if DEBUG_DCACHE
+if ( m_debug_dcache_fsm )
+{
+    std::cout << "  <PROC " << name() << ".DCACHE_TLB_PTE2_UPDT> L/R bit update required"
+              << std::endl;
+}
+#endif
+        }
+        break;
+    }
+    ////////////////////////
+    case DCACHE_TLB_LR_UPDT:        // request a SC transaction to update L/R bit
+    {
+#if DEBUG_DCACHE
+if ( m_debug_dcache_fsm )
+{
+    std::cout << "  <PROC " << name() << ".DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit" << std::endl;
+}
+#endif
+        // r_dcache_vci_cas_old & r_dcache_vci_cas_new registers are already set
+        r_dcache_vci_paddr = r_dcache_tlb_paddr.read();
+        // prepare llsc local table access
+        table_in.cmd       = LLSCLocalTable::SW_CMD;
+        table_in.address   = r_dcache_tlb_paddr.read();
+        // access the table
+        r_llsc_table.exec(table_in, table_out);
+        llsc_local_table_access_done = true;
+        // test if the table is done
+        if(!table_out.done)
+            break;
+        // request a CAS CMD and go to DCACHE_TLB_LR_WAIT state
+        r_dcache_vci_cas_req = true;
+        r_dcache_fsm         = DCACHE_TLB_LR_WAIT;
+        break;
+    }
+    ////////////////////////
+    case DCACHE_TLB_LR_WAIT:		// Waiting the response to SC transaction for DIRTY bit.
+                                    // We consume the response in rsp FIFO, 
+                                    // and exit the sub-fsm, but we don't
+                                    // analyse the response, because we don't
+                                    // care if the L/R bit update is not done.
+                                    // We must take the coherence requests because
+                                    // there is a risk of dead-lock
+
+    {
+        // external coherence request
+        if ( r_tgt_dcache_req )
+        {
+            r_dcache_fsm         = DCACHE_CC_CHECK;
+            r_dcache_fsm_cc_save = r_dcache_fsm.read();
+            break;
+        }
+
+        if ( r_vci_rsp_data_error.read() ) 	// bus error
+        {
+            std::cout << "BUS ERROR in DCACHE_TLB_LR_WAIT state" << std::endl;
+            std::cout << "This should not happen in this state" << std::endl;
+            exit(0);
+        }
+	else if ( r_vci_rsp_fifo_dcache.rok() ) // response available
+	{
+#if DEBUG_DCACHE
+if ( m_debug_dcache_fsm )
+{
+    std::cout << "  <PROC " << name() << ".DCACHE_TLB_LR_WAIT> SC response received" << std::endl;
+}
+#endif
+            vci_rsp_fifo_dcache_get = true;     
+            r_dcache_fsm            = DCACHE_TLB_RETURN;
+        }
+        break;
+    }
+    ///////////////////////
+    case DCACHE_TLB_RETURN:		// return to caller depending on tlb miss type
+    {
+#if DEBUG_DCACHE
+if ( m_debug_dcache_fsm )
+{
+    std::cout << "  <PROC " << name() << ".DCACHE_TLB_RETURN> TLB MISS completed" << std::endl;
+}
+#endif
+        if ( r_dcache_tlb_ins.read() ) r_icache_tlb_miss_req = false;
+        r_dcache_fsm = DCACHE_IDLE;
+        break;
+    }
+    ///////////////////////
+    case DCACHE_XTN_SWITCH:		// The r_ptpr registers must be written,
+                                // and both itlb and dtlb must be flushed.
+                                // Caution : the itlb miss requests must be taken 
+                                // to avoid dead-lock in case of simultaneous ITLB miss
+    {
+        // itlb miss request
+        if ( r_icache_tlb_miss_req.read() )
+        {
+            r_dcache_tlb_ins    = true;
+            r_dcache_tlb_vaddr  = r_icache_vaddr_save.read();
+            r_dcache_fsm        = DCACHE_TLB_MISS;
+            break;
+        }
+
+        if ( not r_dcache_xtn_req.read() )
+        {
+            r_dtlb.flush();
+            r_mmu_ptpr   = m_dreq.wdata;
+            r_dcache_fsm = DCACHE_IDLE;
+            m_drsp.valid = true;
+        }
+        break;
+    }
+    /////////////////////
+    case DCACHE_XTN_SYNC:		// waiting until write buffer empty
+                                // The coherence request must be taken
+                                // as there is a risk of dead-lock
+    {
+        // external coherence request 
+        if ( r_tgt_dcache_req.read() )   
+        {
+            r_dcache_fsm_cc_save = r_dcache_fsm.read();
+            r_dcache_fsm         = DCACHE_CC_CHECK;
+        }        
+
+        if ( r_wbuf.empty() )
+        {
+            m_drsp.valid   = true;
+            r_dcache_fsm = DCACHE_IDLE;
+        }
+        break;
+    }
+    ////////////////////////
+    case DCACHE_XTN_IC_FLUSH:		// Waiting completion of an XTN request to the ICACHE FSM
+    case DCACHE_XTN_IC_INVAL_VA:	// Caution : the itlb miss requests must be taken 
+    case DCACHE_XTN_IC_INVAL_PA:	// because the XTN_ICACHE_INVAL request to icache
+    case DCACHE_XTN_IT_INVAL:		// can generate an itlb miss,
+                                    // and because it can exist a simultaneous ITLB miss
+    {
+        // external coherence request
+        if ( r_tgt_dcache_req )   
+        {
+            r_dcache_fsm_cc_save = r_dcache_fsm.read();
+            r_dcache_fsm         = DCACHE_CC_CHECK;
+            break;
+        }  
+
+        // itlb miss request
+        if ( r_icache_tlb_miss_req.read() )
+        {
+            r_dcache_tlb_ins    = true;
+            r_dcache_tlb_vaddr  = r_icache_vaddr_save.read();
+            r_dcache_fsm        = DCACHE_TLB_MISS;
+            break;
+        }
+
+        // test if XTN request to icache completed
+        if ( not r_dcache_xtn_req.read() ) 
+        {
+            r_dcache_fsm = DCACHE_IDLE;
+            m_drsp.valid = true;
+        }
+        break;
+    }
+    /////////////////////////
+    case DCACHE_XTN_DC_FLUSH:	// Invalidate sequencially all cache lines, using
+                                // the r_dcache_flush counter as a slot counter.
+                                // We loop in this state until all slots have been visited.
+                                // A cleanup request is generated for each valid line 
+                                // and we are blocked until the previous cleanup is completed
+				                // Finally, both the itlb and dtlb are flushed
+                                // (including global entries) 
+    {
+        if ( not r_dcache_cleanup_req )
+        {
+            paddr_t 	nline;
+            size_t	way = r_dcache_flush_count.read()/m_icache_sets;
+            size_t	set = r_dcache_flush_count.read()%m_icache_sets;
+
+            bool	cleanup_req = r_dcache.inval( way,
+                                                      set,
+                                                      &nline );
+            if ( cleanup_req ) 
+            {
+                r_dcache_cleanup_req  = true;
+                r_dcache_cleanup_line = nline;
+            }
+
+            r_dcache_in_tlb[m_dcache_sets*way+set]       = false;
+            r_dcache_contains_ptd[m_dcache_sets*way+set] = false;
+
+            r_dcache_flush_count = r_dcache_flush_count.read() + 1;
+
+            if ( r_dcache_flush_count.read() == (m_dcache_sets*m_dcache_ways - 1) ) // last 
+            {
+                r_dtlb.reset();    
+                r_itlb.reset(); 
+                r_dcache_fsm = DCACHE_IDLE;
+                m_drsp.valid = true;
+            }
+        }
+	break;
+    }
+    /////////////////////////
+    case DCACHE_XTN_DT_INVAL: 	// handling processor XTN_DTLB_INVAL request
+    {
+        r_dtlb.inval(r_dcache_p0_wdata.read());
+        r_dcache_fsm        = DCACHE_IDLE;
+        m_drsp.valid          = true;
+        break;
+    }
+    ////////////////////////////
+    case DCACHE_XTN_DC_INVAL_VA:  // selective cache line invalidate with virtual address
+                                  // requires 3 cycles: access tlb, read cache, inval cache
+                               	  // we compute the physical address in this state 
+    {
+        paddr_t paddr;
+        bool    hit;
+
+        if ( r_mmu_mode.read() & DATA_TLB_MASK ) 	// dtlb activated
+        {
+#ifdef INSTRUMENTATION
+m_cpt_dtlb_read++;
+#endif
+            hit = r_dtlb.translate( r_dcache_p0_wdata.read(),
+                                    &paddr ); 
+        }
+        else 						// dtlb not activated
+        {
+            paddr = (paddr_t)r_dcache_p0_wdata.read();
+            hit   = true;
+        }
+
+        if ( hit )		// tlb hit
+        {
+            r_dcache_p0_paddr = paddr;
+            r_dcache_fsm      = DCACHE_XTN_DC_INVAL_PA;
+        }
+        else			// tlb miss
+       	{
+#ifdef INSTRUMENTATION
+m_cpt_dtlb_miss++;
+#endif
+            r_dcache_tlb_ins    = false;		// dtlb
+            r_dcache_tlb_vaddr  = r_dcache_p0_wdata.read();
+            r_dcache_fsm        = DCACHE_TLB_MISS; 
+        } 
+  
+#if DEBUG_DCACHE
+if ( m_debug_dcache_fsm )
+{
+    std::cout << "  <PROC " << name() << ".DCACHE_XTN_DC_INVAL_VA> Compute physical address" << std::hex
+              << " / VADDR = " << r_dcache_p0_wdata.read()
+              << " / PADDR = " << paddr << std::endl;
+}
+#endif
+
+        break;
+    }
+    ////////////////////////////
+    case DCACHE_XTN_DC_INVAL_PA:  // selective cache line invalidate with physical address
+                                  // requires 2 cycles: read cache / inval cache
+                                  // In this state we read dcache.
+    {
+        uint32_t	data;
+        size_t		way;
+        size_t		set;
+        size_t		word;
+        bool		hit = r_dcache.read( r_dcache_p0_paddr.read(),
+                                             &data,
+                                             &way,
+                                             &set,
+                                             &word );
+#ifdef INSTRUMENTATION
+m_cpt_dcache_data_read++;
+m_cpt_dcache_dir_read++;
+#endif
+        if ( hit )	// inval to be done
+        {
+            r_dcache_xtn_way = way;
+            r_dcache_xtn_set = set;
+            r_dcache_fsm      = DCACHE_XTN_DC_INVAL_GO;
+        }
+        else		// miss : nothing to do
+        {
+            r_dcache_fsm      = DCACHE_IDLE;
+            m_drsp.valid        = true;
+        }
+
+#if DEBUG_DCACHE
+if ( m_debug_dcache_fsm )
+{
+    std::cout << "  <PROC " << name() << ".DCACHE_XTN_DC_INVAL_PA> Test hit in dcache" << std::hex
+              << " / PADDR = " << r_dcache_p0_paddr.read() << std::dec
+              << " / HIT = " << hit
+              << " / SET = " << set
+              << " / WAY = " << way << std::endl;
+}
+#endif
+        break;
+    }
+    ////////////////////////////
+    case DCACHE_XTN_DC_INVAL_GO:  // In this state, we invalidate the cache line 
+        			              // Blocked if previous cleanup not completed
+                                  // Test if itlb or dtlb inval is required    
+    {
+        if ( not r_dcache_cleanup_req.read() )
+        {
+            paddr_t	nline;
+            size_t	way        = r_dcache_xtn_way.read();
+            size_t	set        = r_dcache_xtn_set.read();
+            bool    hit;
+   
+            hit = r_dcache.inval( way,
+                                  set,
+                                  &nline );
+            assert(hit && "XTN_DC_INVAL way/set should still be in cache");
+
+            // request cleanup
+            r_dcache_cleanup_req  = true;
+            r_dcache_cleanup_line = nline;
+	    
+            // possible itlb & dtlb invalidate 
+            if ( r_dcache_in_tlb[way*m_dcache_sets+set] ) 
+            {
+                r_dcache_tlb_inval_line  = nline;
+                r_dcache_tlb_inval_count = 0;
+                r_dcache_fsm_scan_save   = DCACHE_XTN_DC_INVAL_END;
+                r_dcache_fsm             = DCACHE_INVAL_TLB_SCAN;
+                r_dcache_in_tlb[way*m_dcache_sets+set] = false;
+            }
+            else if ( r_dcache_contains_ptd[way*m_dcache_sets+set] ) 
+            {
+                r_itlb.reset();
+                r_dtlb.reset();
+                r_dcache_contains_ptd[way*m_dcache_sets+set] = false;
+                r_dcache_fsm = DCACHE_IDLE;
+                m_drsp.valid = true;
+            }
+            else
+            {
+                r_dcache_fsm = DCACHE_IDLE;
+                m_drsp.valid = true;
+            }
+
+#if DEBUG_DCACHE
+if ( m_debug_dcache_fsm )
+{
+    std::cout << "  <PROC " << name() << ".DCACHE_XTN_DC_INVAL_GO> Actual dcache inval" << std::hex
+              << " / NLINE = " << nline << std::endl;
+}
+#endif
+	}
+        break;
+    }
+    //////////////////////////////
+    case DCACHE_XTN_DC_INVAL_END:  	// send response to processor XTN request
+    {
+        r_dcache_fsm = DCACHE_IDLE;
+        m_drsp.valid = true;
+        break;
+    }
+    ////////////////////////
+    case DCACHE_MISS_VICTIM:		// Selects a victim line if there is no pending cleanup 
+                                        // on the missing line, and if a new cleanup can be posted.
+                                	// Set the r_dcache_cleanup_req flip-flop if required
+    {
+        size_t index; 	// unused
+        bool hit = r_cleanup_buffer.hit( r_dcache_vci_paddr.read()>>(uint32_log2(m_dcache_words)+2), &index );
+        if ( not hit and not r_dcache_cleanup_req.read() )
+        {
+            bool      valid;
+            size_t    way;
+            size_t    set;
+            paddr_t   victim;
+
+            valid = r_dcache.victim_select( r_dcache_vci_paddr.read(),
+                                            &victim,
+                                            &way,
+                                            &set );
+            r_dcache_miss_way = way;
+            r_dcache_miss_set = set;
+
+            if ( valid )
+            {
+                r_dcache_cleanup_req  = true;
+                r_dcache_cleanup_line = victim;
+                r_dcache_fsm          = DCACHE_MISS_INVAL;
+            }
+            else
+            {
+                r_dcache_fsm          = DCACHE_MISS_WAIT;
+            }
+
+#if DEBUG_DCACHE
+if ( m_debug_dcache_fsm )
+{
+    std::cout << "  <PROC " << name() << ".DCACHE_MISS_VICTIM> Select a slot:" << std::dec
+              << " / WAY = "   << way 
+              << " / SET = "   << set
+              << " / VALID = "  << valid
+              << " / LINE = " << std::hex << victim << std::endl; 
+}
+#endif
+        }
+        break;
+    }
+    ///////////////////////
+    case DCACHE_MISS_INVAL:		// invalidate the victim line
+                                	// and possibly request itlb or dtlb invalidate
+    {
+        paddr_t	nline;
+        size_t	way        = r_dcache_miss_way.read();
+        size_t	set        = r_dcache_miss_set.read();
+        bool    hit;
+
+        hit = r_dcache.inval( way, 
+                        set,
+                        &nline );
+
+        assert(hit && "selected way/set line should be in dcache");
+
+#if DEBUG_DCACHE
+if ( m_debug_dcache_fsm )
+{
+    std::cout << "  <PROC " << name() << ".DCACHE_MISS_INVAL> inval line:" << std::dec
+              << " / way = "   << way 
+              << " / set = "   << set
+              << " / nline = "  << std::hex << nline << std::endl; 
+}
+#endif
+        // if selective itlb & dtlb invalidate are required 
+        // the miss response is not handled before invalidate completed
+        if ( r_dcache_in_tlb[way*m_dcache_sets+set] ) 
+        {
+            r_dcache_in_tlb[way*m_dcache_sets+set] = false;
+            r_dcache_tlb_inval_line  = nline;
+            r_dcache_tlb_inval_count = 0;
+            r_dcache_fsm_scan_save   = DCACHE_MISS_WAIT;
+            r_dcache_fsm             = DCACHE_INVAL_TLB_SCAN;
+        }
+        else if ( r_dcache_contains_ptd[way*m_dcache_sets+set] ) 
+        {
+            r_itlb.reset();
+            r_dtlb.reset();
+            r_dcache_contains_ptd[way*m_dcache_sets+set] = false;
+            r_dcache_fsm = DCACHE_MISS_WAIT;
+        }
+        else
+        {
+            r_dcache_fsm = DCACHE_MISS_WAIT;
+        }
+        break;
+    }
+    //////////////////////
+    case DCACHE_MISS_WAIT:	// waiting the response to a miss request from VCI_RSP FSM
+                                // This state is in charge of error signaling
+                                // There is 5 types of error depending on the requester
+    {
+        // external coherence request
+        if ( r_tgt_dcache_req ) 
+        {
+            r_dcache_fsm_cc_save = r_dcache_fsm;
+            r_dcache_fsm         = DCACHE_CC_CHECK;
+            break;
+        }
+
+        if ( r_vci_rsp_data_error.read() ) 			// bus error
+        {
+            switch ( r_dcache_miss_type.read() )
+            {
+                case PROC_MISS:  
+                {
+                    r_mmu_detr            = MMU_READ_DATA_ILLEGAL_ACCESS; 
+                    r_mmu_dbvar           = r_dcache_p0_vaddr.read();
+                    m_drsp.valid            = true;
+                    m_drsp.error            = true;
+                    r_dcache_fsm          = DCACHE_IDLE;
+                    break;
+                }
+                case PTE1_MISS:
+                {
+                    if ( r_dcache_tlb_ins.read() )
+                    {
+                        r_mmu_ietr              = MMU_READ_PT1_ILLEGAL_ACCESS;
+                        r_mmu_ibvar             = r_dcache_tlb_vaddr.read();
+                        r_icache_tlb_miss_req   = false;
+                        r_icache_tlb_rsp_error  = true;
+                    }
+                    else
+                    {
+                        r_mmu_detr              = MMU_READ_PT1_ILLEGAL_ACCESS;
+                        r_mmu_dbvar             = r_dcache_tlb_vaddr.read();
+                        m_drsp.valid              = true;
+                        m_drsp.error              = true;
+                    }
+                    r_dcache_fsm                = DCACHE_IDLE;
+                    break;
+                }
+                case PTE2_MISS: 
+                {
+                    if ( r_dcache_tlb_ins.read() )
+                    {
+                        r_mmu_ietr              = MMU_READ_PT2_ILLEGAL_ACCESS;
+                        r_mmu_ibvar             = r_dcache_tlb_vaddr.read();
+                        r_icache_tlb_miss_req   = false;
+                        r_icache_tlb_rsp_error  = true;
+                    }
+                    else
+                    {
+                        r_mmu_detr              = MMU_READ_PT2_ILLEGAL_ACCESS;
+                        r_mmu_dbvar             = r_dcache_tlb_vaddr.read();
+                        m_drsp.valid              = true;
+                        m_drsp.error              = true;
+                    }
+                    r_dcache_fsm                = DCACHE_IDLE;
+                    break;
+                }
+            } // end switch type
+            r_vci_rsp_data_error = false;
+        }
+        else if ( r_vci_rsp_fifo_dcache.rok() )		// valid response available
+        {
+            r_dcache_miss_word = 0;
+	    r_dcache_fsm       = DCACHE_MISS_UPDT;
+        }	
+        break;
+    }
+    //////////////////////
+    case DCACHE_MISS_UPDT:	// update the dcache (one word per cycle)
+                                // returns the response depending on the miss type
+    {
+        if ( r_vci_rsp_fifo_dcache.rok() )	// one word available
+        {
+            if ( r_dcache_miss_inval.read() )	// Matching coherence request
+                                                // pop the FIFO, without cache update
+                                                // send a cleanup for the missing line
+                                                // if the previous cleanup is completed
+            {
+                if ( r_dcache_miss_word.read() < (m_dcache_words - 1) )     // not the last
+                {
+                    vci_rsp_fifo_dcache_get = true;
+                    r_dcache_miss_word = r_dcache_miss_word.read() + 1;
+                }
+                else                                                    // last word
+                {
+                    if ( not r_dcache_cleanup_req.read() )      // no pending cleanup
+                    {
+                        vci_rsp_fifo_dcache_get = true;
+                        r_dcache_cleanup_req    = true;
+                        r_dcache_cleanup_line   = r_dcache_vci_paddr.read() >> 
+                                                     (uint32_log2(m_dcache_words)+2);
+                        r_dcache_miss_inval     = false;
+                        r_dcache_fsm            = DCACHE_IDLE;
+                    }
+                }
+            }
+            else                                // No matching coherence request
+                                                // pop the FIFO and update the cache 
+                                                // update the directory at the last word
+            {
+                 size_t	way  = r_dcache_miss_way.read();
+                 size_t	set  = r_dcache_miss_set.read();
+                 size_t word = r_dcache_miss_word.read();
+
+#ifdef INSTRUMENTATION
+m_cpt_dcache_data_write++;
+#endif
+                r_dcache.write( way,
+                                set,
+                                word,
+                                r_vci_rsp_fifo_dcache.read());
+
+                vci_rsp_fifo_dcache_get = true;
+                r_dcache_miss_word = r_dcache_miss_word.read() + 1;
+               
+                // if last word, update directory, set in_tlb & contains_ptd bits
+                if ( r_dcache_miss_word.read() == (m_dcache_words - 1) ) 
+                {
+
+#ifdef INSTRUMENTATION
+m_cpt_dcache_dir_write++;
+#endif
+                    r_dcache.victim_update_tag( r_dcache_vci_paddr.read(),
+                                                r_dcache_miss_way.read(),
+                                                r_dcache_miss_set.read() );
+
+                    r_dcache_in_tlb[way*m_dcache_sets+set] = false;
+                    r_dcache_contains_ptd[way*m_dcache_sets+set] = false;
+                    
+                    if      (r_dcache_miss_type.read()==PTE1_MISS) r_dcache_fsm = DCACHE_TLB_PTE1_GET; 
+                    else if (r_dcache_miss_type.read()==PTE2_MISS) r_dcache_fsm = DCACHE_TLB_PTE2_GET;
+                    else	                                   r_dcache_fsm = DCACHE_IDLE;
+                }
+            }
+
+#if DEBUG_DCACHE
+if ( m_debug_dcache_fsm )
+{
+    if ( r_dcache_miss_inval.read() )
+    {
+        if ( r_dcache_miss_word.read() < m_dcache_words-1 ) 
+        {
+            std::cout << "  <PROC " << name() << ".DCACHE_MISS_UPDT> Matching coherence request:"
+                      << "  pop the FIFO, don't update the cache" << std::endl;
+        }
+        else
+        {
+            std::cout << "  <PROC " << name() << ".DCACHE_MISS_UPDT> Matching coherence request:"
+                      << " last word : send a cleanup request " << std::endl;
+        }
+    }
+    else
+    {
+        std::cout << "  <PROC " << name() << ".DCACHE_MISS_UPDT> Write one word:"
+                  << " address = " << std::hex << r_dcache_vci_paddr.read() 
+                  << " / data = "  << r_vci_rsp_fifo_dcache.read()
+                  << " / way = "   << std::dec << r_dcache_miss_way.read() 
+                  << " / set = "   << r_dcache_miss_set.read()
+                  << " / word = "  << r_dcache_miss_word.read() << std::endl; 
+    }
+}
+#endif
+  
+        } // end if rok
+        break;
+    }
+    /////////////////////
+    case DCACHE_UNC_WAIT:
+    {
+        // external coherence request
+        if ( r_tgt_dcache_req.read() ) 
+        {
+            r_dcache_fsm_cc_save = r_dcache_fsm;
+            r_dcache_fsm         = DCACHE_CC_CHECK;
+            break;
+        }
+
+        if ( r_vci_rsp_data_error.read() ) 	// bus error
+        {
+            r_mmu_detr           = MMU_READ_DATA_ILLEGAL_ACCESS; 
+            r_mmu_dbvar          = m_dreq.addr;
+            r_vci_rsp_data_error = false;
+            m_drsp.error         = true;
+            m_drsp.valid         = true;
+            r_dcache_fsm         = DCACHE_IDLE;
+            break;
+        }
+	    else if ( r_vci_rsp_fifo_dcache.rok() )     // data available
+	    {
+            // consume data 
+            vci_rsp_fifo_dcache_get = true;     
+            r_dcache_fsm            = DCACHE_IDLE;
+
+            // acknowledge the processor request if it has not been modified
+            if ( m_dreq.valid and (m_dreq.addr == r_dcache_p0_vaddr.read()) )
+            {
+	            m_drsp.valid        = true;
+	            m_drsp.rdata        = r_vci_rsp_fifo_dcache.read();
+            }
+	    }	
+        break;
+    }
+    /////////////////////
+    case DCACHE_LL_WAIT:
+    {
+        // external coherence request
+        if ( r_tgt_dcache_req.read() ) 
+        {
+            r_dcache_fsm_cc_save = r_dcache_fsm;
+            r_dcache_fsm         = DCACHE_CC_CHECK;
+            break;
+        }
+
+        if ( r_vci_rsp_data_error.read() ) 	// bus error
+        {
+            r_mmu_detr           = MMU_READ_DATA_ILLEGAL_ACCESS; 
+            r_mmu_dbvar          = m_dreq.addr;
+            r_vci_rsp_data_error = false;
+            m_drsp.error         = true;
+            m_drsp.valid         = true;
+            r_dcache_fsm         = DCACHE_IDLE;
+            break;
+        }
+	    else if ( r_vci_rsp_fifo_dcache.rok() )     // data available
+	    {
+            // consume data 
+            vci_rsp_fifo_dcache_get = true;
+            if(r_dcache_ll_rsp_count.read() == 0) //first flit
+            {
+                //access table
+                table_in.cmd    = LLSCLocalTable::LL_RSP    ;
+                table_in.index  = 0;//p_vci_ini_d.rtrdid.read() ; // TODO use this ?
+                table_in.key    = r_vci_rsp_fifo_dcache.read();
+                r_llsc_table.exec(table_in, table_out);
+                llsc_local_table_access_done = true;
+                r_dcache_ll_rsp_count = r_dcache_ll_rsp_count.read() + 1 ;
+            }
+            else //last flit
+            {
+                // acknowledge the processor request if it has not been modified
+                if ( m_dreq.valid and (m_dreq.addr == r_dcache_p0_vaddr.read()) )
+                {
+                    m_drsp.valid        = true;
+                    m_drsp.rdata        = r_vci_rsp_fifo_dcache.read();
+                }
+                r_dcache_fsm = DCACHE_IDLE;
+            }
+	    }
+        break;
+    }
+    ////////////////////
+    case DCACHE_SC_WAIT:	// waiting VCI response after a processor SC request
+    {
+        // external coherence request
+        if ( r_tgt_dcache_req.read() ) 
+        {
+            r_dcache_fsm_cc_save = r_dcache_fsm;
+            r_dcache_fsm         = DCACHE_CC_CHECK;
+            break;
+        }
+
+        if ( r_vci_rsp_data_error.read() ) 		// bus error
+        {
+            r_mmu_detr           = MMU_READ_DATA_ILLEGAL_ACCESS; 
+            r_mmu_dbvar          = m_dreq.addr;
+            r_vci_rsp_data_error = false;
+            m_drsp.error         = true;
+            m_drsp.valid         = true;
+            r_dcache_fsm         = DCACHE_IDLE;
+            break;
+        }
+	    else if ( r_vci_rsp_fifo_dcache.rok() ) // response available
+	    {
+            // consume response 
+            vci_rsp_fifo_dcache_get = true;
+            m_drsp.valid            = true;
+            m_drsp.rdata            = r_vci_rsp_fifo_dcache.read();
+            r_dcache_fsm            = DCACHE_IDLE;
+	    }	
+        break;
+    }
+    //////////////////////////
+    case DCACHE_DIRTY_GET_PTE:		// This sub_fsm set the PTE Dirty bit in memory 
+                                    // before handling a processor WRITE or SC request  
+                                    // Input argument is r_dcache_dirty_paddr
+                                    // In this first state, we get PTE value in dcache
+                                    // and post a SC request to CMD FSM
+    {
+        // get PTE in dcache
+        uint32_t pte;
+        size_t   way;
+        size_t   set;
+        size_t   word;	// unused
+        bool     hit = r_dcache.read( r_dcache_dirty_paddr.read(),
+                                      &pte,
+                                      &way,
+                                      &set,
+                                      &word );
+#ifdef INSTRUMENTATION
+m_cpt_dcache_data_read++;
+m_cpt_dcache_dir_read++;
+#endif
+        assert( hit and "error in DCACHE_DIRTY_TLB_SET: the PTE should be in dcache" );
+
+        // request CAS transaction to CMD_FSM
+        r_dcache_dirty_way  = way; 
+        r_dcache_dirty_set  = set; 
+        // prepare llsc local table access
+        table_in.cmd       = LLSCLocalTable::SW_CMD;
+        table_in.address   = r_dcache_dirty_paddr.read();
+        // access the table
+        r_llsc_table.exec(table_in, table_out);
+        llsc_local_table_access_done = true;
+        // test if the table is done
+        if(!table_out.done)
+            break;
+        // request a CAS CMD and go to DCACHE_DIRTY_WAIT state
+        r_dcache_vci_cas_req = true;
+        r_dcache_vci_paddr  = r_dcache_dirty_paddr.read();
+        r_dcache_vci_cas_old = pte;
+        r_dcache_vci_cas_new = pte | PTE_D_MASK;
+        r_dcache_fsm        = DCACHE_DIRTY_WAIT;
+
+#if DEBUG_DCACHE
+if ( m_debug_dcache_fsm )
+{
+    std::cout << "  <PROC " << name() << ".DCACHE_DIRTY_GET_PTE> Get PTE in dcache" << std::hex
+              << " / PTE_PADDR = " << r_dcache_dirty_paddr.read() 
+              << " / PTE_VALUE = " << pte << std::dec 
+              << " / CACHE_SET = " << set
+              << " / CACHE_WAY = " << way << std::endl;
+}
+#endif
+        break;
+    }
+    //////////////////////////
+    case DCACHE_DIRTY_WAIT:         // wait completion of CAS for PTE Dirty bit,
+                                    // and return to IDLE state when response is received.
+                                    // we don't care if the CAS is a failure:
+                                    // - if the CAS is a success, the coherence mechanism
+                                    //   updates the local copy.
+                                    // - if the CAS is a failure, we just retry the write.
+    {
+        // external coherence request
+        if ( r_tgt_dcache_req ) 
+        {
+            r_dcache_fsm_cc_save = r_dcache_fsm;
+            r_dcache_fsm         = DCACHE_CC_CHECK;
+            break;
+        }
+
+        if ( r_vci_rsp_data_error.read() )	// bus error
+        {
+            std::cout << "BUS ERROR in DCACHE_DIRTY_WAIT state" << std::endl;
+            std::cout << "This should not happen in this state" << std::endl;
+            exit(0);
+        }
+        else if ( r_vci_rsp_fifo_dcache.rok() )	// response available
+        {
+            vci_rsp_fifo_dcache_get = true;
+            r_dcache_fsm            = DCACHE_IDLE;
+
+#if DEBUG_DCACHE
+if ( m_debug_dcache_fsm )
+{
+    std::cout << "  <PROC " << name() << ".DCACHE_DIRTY_WAIT> SC completed" << std::endl;
+}
+#endif
+        }
+        break;
+    }
+    /////////////////////
+    case DCACHE_CC_CHECK:   // This state is the entry point for the sub-FSM
+                            // handling coherence requests.
+                            // If there is a matching pending miss on the modified cache 
+                            // line this is signaled in the r_dcache_miss inval flip-flop.
+                            // If the updated (or invalidated) cache line has copies in TLBs
+                            // these TLB copies are invalidated.
+                            // The return state is defined in r_dcache_fsm_cc_save
+    {
+        paddr_t  paddr = r_tgt_paddr.read();
+        paddr_t  mask = ~((m_dcache_words<<2)-1);
+
+
+        if( (r_dcache_fsm_cc_save == DCACHE_MISS_WAIT) and
+            ((r_dcache_vci_paddr.read() & mask) == (paddr & mask)) ) // matching pending miss
+        {
+            r_dcache_miss_inval = true;			// signaling the match
+            r_tgt_dcache_req    = false;		// coherence request completed
+            r_tgt_dcache_rsp    = r_tgt_update.read();	// response required if update
+            r_dcache_fsm        = r_dcache_fsm_cc_save.read();
+
+#if DEBUG_DCACHE
+if ( m_debug_dcache_fsm )
+{
+    std::cout << "  <PROC " << name() << ".DCACHE_CC_CHECK> Coherence request matching a pending miss:"
+              << " address = " << std::hex << paddr << std::endl;
+}
+#endif
+  
+        }
+        else                                                    // no match for a pending miss
+	    {
+            uint32_t   rdata;
+            size_t 	   way;
+            size_t 	   set;
+            size_t	   word;
+
+            bool 	   hit = r_dcache.read( paddr,
+                                            &rdata,	// unused
+                                            &way, 
+                                            &set,
+                                            &word);	// unused
+#ifdef INSTRUMENTATION
+m_cpt_dcache_data_read++;
+m_cpt_dcache_dir_read++;
+#endif
+            r_dcache_cc_way = way;
+            r_dcache_cc_set = set;
+
+            if ( hit and r_tgt_update.read() )		// hit update
+            {
+                r_dcache_fsm     = DCACHE_CC_UPDT;
+                r_dcache_cc_word = r_tgt_word_min.read();
+            }
+            else if ( hit and not r_tgt_update.read() )	// hit inval
+            {
+                r_dcache_fsm     = DCACHE_CC_INVAL;
+            }
+            else					// miss can happen
+            {
+                r_tgt_dcache_req = false;
+                r_tgt_dcache_rsp = r_tgt_update.read();
+                r_dcache_fsm     = r_dcache_fsm_cc_save.read();
+            }
+
+#if DEBUG_DCACHE
+if ( m_debug_dcache_fsm )
+{
+    
+    std::cout << "  <PROC " << name() << ".DCACHE_CC_CHECK> Coherence request received :"
+              << " address = " << std::hex << paddr << std::dec;
+    if ( hit ) 
+    {
+        std::cout << " / HIT" << " / way = " << way << " / set = " << set << std::endl;
+    }
+    else
+    {
+        std::cout << " / MISS" << std::endl;
+    }
+}
+#endif
+  
+        }
+        break;
+    }
+    /////////////////////
+    case DCACHE_CC_INVAL:   	// invalidate one cache line after
+                                // invalidation of copies in TLBs
+    {
+        paddr_t  nline;
+        size_t	 way    = r_dcache_cc_way.read();
+        size_t	 set    = r_dcache_cc_set.read();
+        bool     hit;
+
+        if ( r_dcache_in_tlb[way*m_dcache_sets+set] ) 			// selective TLB inval
+        {
+            r_dcache_in_tlb[way*m_dcache_sets+set] = false;
+            r_dcache_tlb_inval_line  = r_tgt_paddr.read() >> (uint32_log2(m_dcache_words)+2);
+            r_dcache_tlb_inval_count = 0;
+            r_dcache_fsm_scan_save   = r_dcache_fsm.read();
+            r_dcache_fsm             = DCACHE_INVAL_TLB_SCAN;
+        }
+        else 								                  // actual cache line inval
+        {
+            if ( r_dcache_contains_ptd[way*m_dcache_sets+set] ) 	// TLB flush
+            {
+                r_itlb.reset();
+                r_dtlb.reset();
+                r_dcache_contains_ptd[way*m_dcache_sets+set] = false;
+            }
+            r_tgt_dcache_rsp = true;
+            r_tgt_dcache_req = false;
+            r_dcache_fsm     = r_dcache_fsm_cc_save.read();
+ 
+            hit = r_dcache.inval( way, 
+                                  set,
+                                  &nline );
+#if DEBUG_DCACHE
+if ( m_debug_dcache_fsm )
+{
+    std::cout << "  <PROC " << name() << ".DCACHE_CC_INVAL> Invalidate cache line" << std::dec
+	      << " / WAY = " << way
+	      << " / SET = " << set << std::endl;
+}
+#endif
+  
+	    assert(hit && "CC_INVAL way/set should be in dcache");
+        }
+        break;
+    }
+    ///////////////////
+    case DCACHE_CC_UPDT:    	// write one word per cycle (from word_min to word_max)
+                                // and test possible copies in TLBs
+    {
+        size_t	 word       = r_dcache_cc_word.read();
+        size_t	 way        = r_dcache_cc_way.read();
+        size_t	 set        = r_dcache_cc_set.read();
+        paddr_t  nline	    = r_tgt_paddr.read() >> (uint32_log2(m_dcache_words)+2);
+
+        if ( r_dcache_in_tlb[way*m_dcache_sets+set] ) 			// selective TLB inval
+        {
+            r_dcache_in_tlb[way*m_dcache_sets+set] = false;
+            r_dcache_tlb_inval_line  = nline;
+            r_dcache_tlb_inval_count = 0;
+            r_dcache_fsm_scan_save   = r_dcache_fsm.read();
+            r_dcache_fsm             = DCACHE_INVAL_TLB_SCAN;
+        }
+        else 								// cache update
+        {
+            if ( r_dcache_contains_ptd[way*m_dcache_sets+set] ) 	// TLB flush
+            {
+                r_itlb.reset();
+                r_dtlb.reset();
+                r_dcache_contains_ptd[way*m_dcache_sets+set] = false;
+            } 
+
+            r_dcache.write( way,
+                            set,
+                            word,
+                            r_tgt_buf[word],
+                            r_tgt_be[word] );
+#ifdef INSTRUMENTATION
+m_cpt_dcache_data_write++;
+#endif
+            r_dcache_cc_word = word + 1;
+
+#if DEBUG_DCACHE
+if ( m_debug_dcache_fsm )
+{
+    std::cout << "  <PROC " << name() << ".DCACHE_CC_UPDT> Update one word" << std::dec
+	      << " / WAY = " << way
+	      << " / SET = " << set 
+              << " / WORD = " << word
+              << " / VALUE = " << std::hex << r_tgt_buf[word] << std::endl;
+}
+#endif
+            if ( word == r_tgt_word_max.read() )	// last word
+            {
+                r_tgt_dcache_rsp = true;
+                r_tgt_dcache_req = false;
+                r_dcache_fsm     = r_dcache_fsm_cc_save.read();
+            }
+        }
+
+        break;
+    }
+    ///////////////////////////
+    case DCACHE_INVAL_TLB_SCAN:     	// Scan sequencially all TLB entries for both ITLB & DTLB
+                                        // It makes the assumption that (m_itlb_sets == m_dtlb_sets)
+                                        // and (m_itlb_ways == m_dtlb_ways)
+                                        // We enter this state when a DCACHE line is modified,
+                                        // and there is a copy in itlb or dtlb.
+                                        // It can be caused by: 
+                                        // - a coherence inval or updt transaction, 
+                                        // - a line inval caused by a cache miss
+                                        // - a processor XTN inval request, 
+                                        // - a WRITE hit,
+                                        // - a Dirty bit update failure
+                                        // Input arguments are:
+                                        // - r_dcache_tlb_inval_line
+                                        // - r_dcache_tlb_inval_count
+                                        // - r_dcache_fsm_cc_save
+    {
+        paddr_t	line = r_dcache_tlb_inval_line.read(); 		        // nline
+        size_t	way  = r_dcache_tlb_inval_count.read()/m_itlb_sets;	// way
+        size_t  set  = r_dcache_tlb_inval_count.read()%m_itlb_sets;	// set
+        bool    ok;
+
+        ok = r_itlb.inval( line,
+                            way,
+                            set );
+#if DEBUG_DCACHE
+if ( m_debug_dcache_fsm and ok )
+{
+    std::cout << "  <PROC " << name() << ".DCACHE_INVAL_TLB_SCAN> Invalidate ITLB entry:" << std::hex 
+              << " line = " << line << std::dec
+              << " / set = " << set 
+              << " / way = " << way << std::endl;
+    r_itlb.printTrace();
+}
+#endif
+        ok = r_dtlb.inval( line,
+                           way,
+                           set );
+#if DEBUG_DCACHE
+if ( m_debug_dcache_fsm and ok )
+{
+    std::cout << "  <PROC " << name() << ".DCACHE_INVAL_TLB_SCAN> Invalidate DTLB entry:" << std::hex 
+              << " line = " << line << std::dec
+              << " / set = " << set 
+              << " / way = " << way << std::endl;
+    r_dtlb.printTrace();
+}
+#endif
+
+        // return to the calling state when TLB inval completed
+        if ( r_dcache_tlb_inval_count.read() == ((m_dtlb_sets*m_dtlb_ways)-1) )
+        {
+            r_dcache_fsm = r_dcache_fsm_scan_save.read();
+        }
+        r_dcache_tlb_inval_count = r_dcache_tlb_inval_count.read() + 1;
+        break;
+    }   
+    } // end switch r_dcache_fsm
+    // perform a NOP access the the local llsc table if necessary
+    if(llsc_local_table_access_done == false)
+    {
+        table_in.cmd = LLSCLocalTable::NOP;
+        r_llsc_table.exec(table_in, table_out);
+    }
+
+    ///////////////// wbuf update //////////////////////////////////////////////////////
+    r_wbuf.update();
+
+    //////////////// test processor frozen /////////////////////////////////////////////
+    // The simulation exit if the number of consecutive frozen cycles
+    // is larger than the m_max_frozen_cycles (constructor parameter)
+    if ( (m_ireq.valid and not m_irsp.valid) or (m_dreq.valid and not m_drsp.valid) )       
+    {
+        m_cpt_frz_cycles++; 		// used for instrumentation
+        m_cpt_stop_simulation++;	// used for debug
+        if ( m_cpt_stop_simulation > m_max_frozen_cycles )
+        {
+            std::cout << std::dec << "ERROR in CC_VCACHE_WRAPPER " << name() << std::endl
+                      << " stop at cycle " << m_cpt_total_cycles << std::endl
+                      << " frozen since cycle " << m_cpt_total_cycles - m_max_frozen_cycles << std::endl;
+                      r_iss.dump();
+            exit(1);
+        }
+    }
+    else
+    {
+        m_cpt_stop_simulation = 0;
+    }
+
+    /////////// execute one iss cycle /////////////////////////////////
+    {
+    uint32_t it = 0;
+    for (size_t i=0; i<(size_t)iss_t::n_irq; i++) if(p_irq[i].read()) it |= (1<<i);
+    r_iss.executeNCycles(1, m_irsp, m_drsp, it);
+    }
+
+    ////////////////////////////////////////////////////////////////////////////
+    // The VCI_CMD FSM controls the following ressources:
+    // - r_vci_cmd_fsm
+    // - r_vci_cmd_min
+    // - r_vci_cmd_max
+    // - r_vci_cmd_cpt
+    // - r_vci_cmd_imiss_prio
+    // - wbuf (reset)
+    // - r_icache_miss_req (reset)
+    // - r_icache_unc_req (reset)
+    // - r_dcache_vci_miss_req (reset)
+    // - r_dcache_vci_unc_req (reset)
+    // - r_dcache_vci_ll_req (reset)
+    // - r_dcache_vci_sc_req (reset in case of local sc fail)
+    // - r_dcache_vci_cas_req (reset)
+    //
+    // This FSM handles requests from both the DCACHE FSM & the ICACHE FSM.
+    // There are 8 request types, with the following priorities : 
+    // 1 - Data Read Miss         : r_dcache_vci_miss_req and miss in the write buffer
+    // 2 - Data Read Uncachable   : r_dcache_vci_unc_req  
+    // 3 - Instruction Miss       : r_icache_miss_req and miss in the write buffer
+    // 4 - Instruction Uncachable : r_icache_unc_req 
+    // 5 - Data Write             : r_wbuf.rok()      
+    // 6 - Data Linked Load       : r_dcache_vci_ll_req
+    // 7 - Data Store Conditionnal: r_dcache_vci_sc_req
+    // 8 - Compare And Swap       : r_dcache_vci_cas_req
+    //
+    // As we want to support several simultaneous VCI transactions, the VCI_CMD_FSM 
+    // and the VCI_RSP_FSM are fully desynchronized.
+    //
+    // VCI formats:
+    // According to the VCI advanced specification, all read requests packets 
+    // (data Uncached, Miss data, instruction Uncached, Miss instruction) 
+    // are one word packets.
+    // For write burst packets, all words are in the same cache line,
+    // and addresses must be contiguous (the BE field is 0 in case of "holes").
+    // The sc command packet implements actually a compare-and-swap mechanism
+    // and the packet contains two flits.
+    ////////////////////////////////////////////////////////////////////////////////////
+
+    switch ( r_vci_cmd_fsm.read() ) 
+    {
+        //////////////
+        case CMD_IDLE:
+        {
+            // r_dcache_vci_miss_req and r_icache_miss_req require both a write_buffer access 
+            // to check a possible pending write on the same cache line. 
+            // As there is only one possible access per cycle to write buffer, we implement 
+            // a round-robin priority for this access, using the r_vci_cmd_imiss_prio flip-flop.
+
+            size_t      wbuf_min;
+            size_t      wbuf_max;
+
+            bool dcache_miss_req = r_dcache_vci_miss_req.read()
+                 and ( not r_icache_miss_req.read() or not r_vci_cmd_imiss_prio.read() );
+
+            bool icache_miss_req = r_icache_miss_req.read()
+                 and ( not r_dcache_vci_miss_req.read() or r_vci_cmd_imiss_prio.read() );
+
+            // 1 - Data Read Miss
+            if ( dcache_miss_req and r_wbuf.miss(r_dcache_vci_paddr.read()) )
+            {
+                r_vci_cmd_fsm         = CMD_DATA_MISS;
+                r_dcache_vci_miss_req = false;
+                r_vci_cmd_imiss_prio  = true;
+//                m_cpt_dmiss_transaction++;
+            }
+            // 2 - Data Read Uncachable
+            else if ( r_dcache_vci_unc_req.read() )
+            {
+                r_vci_cmd_fsm        = CMD_DATA_UNC;
+                r_dcache_vci_unc_req = false;
+//                m_cpt_dunc_transaction++;
+            }
+            // 3 - Instruction Miss
+            else if ( icache_miss_req and r_wbuf.miss(r_icache_vci_paddr.read()) )
+            {
+                r_vci_cmd_fsm        = CMD_INS_MISS;
+                r_icache_miss_req    = false;
+                r_vci_cmd_imiss_prio = false;
+//                m_cpt_imiss_transaction++;
+            }
+            // 4 - Instruction Uncachable
+            else if ( r_icache_unc_req.read() )
+            {
+                r_vci_cmd_fsm    = CMD_INS_UNC;
+                r_icache_unc_req = false;
+//                m_cpt_iunc_transaction++;
+            }
+            // 5 - Data Write
+            else if ( r_wbuf.rok(&wbuf_min, &wbuf_max) )
+            {
+                r_vci_cmd_fsm       = CMD_DATA_WRITE;
+                r_vci_cmd_cpt       = wbuf_min;
+                r_vci_cmd_min       = wbuf_min;
+                r_vci_cmd_max       = wbuf_max;
+//                m_cpt_write_transaction++;
+//                m_length_write_transaction += (wbuf_max-wbuf_min+1);
+            }
+            // 6 - Data Linked Load
+            // must check that all write transaction are completed
+            else if ( r_dcache_vci_ll_req.read() && r_wbuf.miss(r_dcache_vci_paddr.read()))
+            {
+                r_dcache_vci_ll_req = false;
+                r_vci_cmd_fsm       = CMD_DATA_LL;
+//              r_vci_cmd_cpt       = 0;
+//              m_cpt_sc_transaction++;
+            }
+            // 7 - Data Store Conditionnal
+            // should check that all write transaction are completed ?
+            else if ( r_dcache_vci_sc_req.read() )
+            {
+                r_dcache_vci_sc_req = false;
+                r_vci_cmd_cpt  = 0;
+                r_vci_cmd_fsm  = CMD_DATA_SC;
+//              m_cpt_sc_transaction++;
+            }
+            // 8 - Compare And Swap
+            // should check that all write transaction are completed ?
+            else if ( r_dcache_vci_cas_req.read() )
+            {
+                r_vci_cmd_fsm        = CMD_DATA_CAS;
+                r_dcache_vci_cas_req = false;
+                r_vci_cmd_cpt        = 0;
+//              m_cpt_sc_transaction++;
+            }
+            break;
+        }
+        ////////////////////
+        case CMD_DATA_WRITE:
+        {
+            if ( p_vci_ini_d.cmdack.read() )
+            {
+//                m_conso_wbuf_read++;
+                r_vci_cmd_cpt = r_vci_cmd_cpt + 1;
+                if (r_vci_cmd_cpt == r_vci_cmd_max) // last flit sent
+                {
+                    r_vci_cmd_fsm = CMD_IDLE ;
+                    r_wbuf.sent() ;
+                }
+            }
+            break;
+        }
+        /////////////////
+        case CMD_DATA_SC:
+        case CMD_DATA_CAS:
+        {
+            // The CAS and SC VCI commands contain two flits
+            if ( p_vci_ini_d.cmdack.read() )
+            {
+               r_vci_cmd_cpt = r_vci_cmd_cpt + 1;
+               if (r_vci_cmd_cpt == 1) r_vci_cmd_fsm = CMD_IDLE ;
+            }
+            break;
+        }
+        //////////////////
+        case CMD_INS_MISS:
+        case CMD_INS_UNC:
+        case CMD_DATA_MISS:
+        case CMD_DATA_UNC:
+        case CMD_DATA_LL:
+        {
+            // all read VCI commands contain one single flit
+            if ( p_vci_ini_d.cmdack.read() )  r_vci_cmd_fsm = CMD_IDLE;
+            break;
+        }
+
+    } // end  switch r_vci_cmd_fsm
+
+    //////////////////////////////////////////////////////////////////////////
+    // The VCI_RSP FSM controls the following ressources:
+    // - r_vci_rsp_fsm:
+    // - r_vci_rsp_fifo_icache (push)
+    // - r_vci_rsp_fifo_dcache (push)
+    // - r_vci_rsp_data_error (set)
+    // - r_vci_rsp_ins_error (set)
+    // - r_vci_rsp_cpt
+    // - r_dcache_vci_sc_req (reset when SC response recieved)
+    //
+    // As the VCI_RSP and VCI_CMD are fully desynchronized to support several
+    // simultaneous VCI transactions, this FSM uses the VCI RPKTID field 
+    // to identify the transactions.
+    //
+    // VCI vormat:
+    // This component checks the response packet length and accepts only
+    // single word packets for write response packets. 
+    //
+    // Error handling:
+    // This FSM analyzes the VCI error code and signals directly the Write Bus Error. 
+    // In case of Read Data Error, the VCI_RSP FSM sets the r_vci_rsp_data_error 
+    // flip_flop and the error is signaled by the DCACHE FSM.  
+    // In case of Instruction Error, the VCI_RSP FSM sets the r_vci_rsp_ins_error 
+    // flip_flop and the error is signaled by the ICACHE FSM.  
+    // In case of Cleanup Error, the simulation stops with an error message...
+    //////////////////////////////////////////////////////////////////////////
+
+    switch ( r_vci_rsp_fsm.read() ) 
+    {
+    //////////////
+    case RSP_IDLE:
+    {
+        if ( p_vci_ini_d.rspval.read() )
+        {
+            r_vci_rsp_cpt = 0;
+
+            if      ( (p_vci_ini_d.rpktid.read() & 0x7) ==  TYPE_READ_DATA_UNC  ) 
+            {
+                r_vci_rsp_fsm = RSP_DATA_UNC;
+            }
+            else if ( (p_vci_ini_d.rpktid.read() & 0x7) ==  TYPE_READ_DATA_MISS ) 
+            {
+                r_vci_rsp_fsm = RSP_DATA_MISS;
+            }
+            else if ( (p_vci_ini_d.rpktid.read() & 0x7) ==  TYPE_READ_INS_UNC   ) 
+            {
+                r_vci_rsp_fsm = RSP_INS_UNC;
+            }
+            else if ( (p_vci_ini_d.rpktid.read() & 0x7) ==  TYPE_READ_INS_MISS  ) 
+            {
+                r_vci_rsp_fsm = RSP_INS_MISS;
+            }
+            else if ( (p_vci_ini_d.rpktid.read() & 0x7) ==  TYPE_WRITE          )
+            {
+                r_vci_rsp_fsm = RSP_DATA_WRITE; 
+            }
+            else if ( (p_vci_ini_d.rpktid.read() & 0x7) ==  TYPE_CAS            ) 
+            {
+                r_vci_rsp_fsm = RSP_DATA_UNC;
+            }
+            else if ( (p_vci_ini_d.rpktid.read() & 0x7) ==  TYPE_LL             ) 
+            {
+                r_vci_rsp_fsm = RSP_DATA_LL;
+            }
+            else if ( (p_vci_ini_d.rpktid.read() & 0x7) == TYPE_SC             ) 
+            {
+                r_vci_rsp_fsm = RSP_DATA_UNC;
+            }
+            else
+            {
+                assert(false and "Unexpected VCI response");
+            }
+        }
+        break;
+    }
+        //////////////////
+        case RSP_INS_MISS:
+        {
+            if ( p_vci_ini_d.rspval.read() )
+            {
+                if ( (p_vci_ini_d.rerror.read()&0x1) != 0 )  // error reported
+                {
+                    r_vci_rsp_ins_error = true;
+                    if ( p_vci_ini_d.reop.read() ) r_vci_rsp_fsm = RSP_IDLE;
+                }
+                else                                        // no error reported
+                {
+                    if ( r_vci_rsp_fifo_icache.wok() )
+                    {
+                        assert( (r_vci_rsp_cpt.read() < m_icache_words) and
+                        "The VCI response packet for instruction miss is too long" );
+
+                        r_vci_rsp_cpt                 = r_vci_rsp_cpt.read() + 1;
+                        vci_rsp_fifo_icache_put       = true,
+                        vci_rsp_fifo_icache_data      = p_vci_ini_d.rdata.read();
+                        if ( p_vci_ini_d.reop.read() )
+                        {
+                            assert( (r_vci_rsp_cpt.read() == m_icache_words - 1) and
+                            "The VCI response packet for instruction miss is too short");
+
+                            r_vci_rsp_fsm    = RSP_IDLE;
+                        }
+                    }
+                }
+            }
+            break;
+        }
+        /////////////////
+        case RSP_INS_UNC:
+        {
+            if (p_vci_ini_d.rspval.read() )
+            {
+                assert( p_vci_ini_d.reop.read() and
+                "illegal VCI response packet for uncachable instruction");
+
+                if ( (p_vci_ini_d.rerror.read()&0x1) != 0 )  // error reported
+                {
+                    r_vci_rsp_ins_error = true;
+                    r_vci_rsp_fsm = RSP_IDLE;
+                }
+                else                                         // no error reported
+                {
+                    if ( r_vci_rsp_fifo_icache.wok())
+                    {
+                        vci_rsp_fifo_icache_put       = true;
+                        vci_rsp_fifo_icache_data      = p_vci_ini_d.rdata.read();
+                        r_vci_rsp_fsm = RSP_IDLE;
+                    }
+                }
+            }
+            break;
+        }
+        ///////////////////
+        case RSP_DATA_MISS:
+        {
+            if ( p_vci_ini_d.rspval.read() )
+            {
+                if ( (p_vci_ini_d.rerror.read()&0x1) != 0 )  // error reported
+                {
+                    r_vci_rsp_data_error = true;
+                    if ( p_vci_ini_d.reop.read() ) r_vci_rsp_fsm = RSP_IDLE;
+                }
+                else                                        // no error reported
+                {
+                    if ( r_vci_rsp_fifo_dcache.wok() )
+                    {
+                        assert( (r_vci_rsp_cpt.read() < m_dcache_words) and
+                        "The VCI response packet for data miss is too long");
+
+                        r_vci_rsp_cpt                 = r_vci_rsp_cpt.read() + 1;
+                        vci_rsp_fifo_dcache_put       = true,
+                        vci_rsp_fifo_dcache_data      = p_vci_ini_d.rdata.read();
+                        if ( p_vci_ini_d.reop.read() )
+                        {
+                            assert( (r_vci_rsp_cpt.read() == m_dcache_words - 1) and
+                            "The VCI response packet for data miss is too short");
+
+                            r_vci_rsp_fsm     = RSP_IDLE;
+                        }
+                    }
+                }
+            }
+            break;
+        }
+        //////////////////
+        case RSP_DATA_UNC:
+        {
+            if (p_vci_ini_d.rspval.read() )
+            {
+                assert( p_vci_ini_d.reop.read() and
+                "illegal VCI response packet for uncachable read data");
+
+                if ( (p_vci_ini_d.rerror.read()&0x1) != 0 )  // error reported
+                {
+                    r_vci_rsp_data_error = true;
+                    r_vci_rsp_fsm = RSP_IDLE;
+                }
+                else                                         // no error reported
+                {
+                    if ( r_vci_rsp_fifo_dcache.wok())
+                    {
+                        vci_rsp_fifo_dcache_put       = true;
+                        vci_rsp_fifo_dcache_data      = p_vci_ini_d.rdata.read();
+                        r_vci_rsp_fsm = RSP_IDLE;
+                    }
+                }
+            }
+            break;
+        }
+        ////////////////////
+        case RSP_DATA_LL:
+        {
+            if ( p_vci_ini_d.rspval.read() )
+            {
+                if ( (p_vci_ini_d.rerror.read()&0x1) != 0 )  // error reported
+                {
+                    r_vci_rsp_data_error = true;
+                    r_vci_rsp_fsm = RSP_IDLE;
+                }
+                if (r_vci_rsp_cpt.read() == 0) //first flit
+                {
+                    if(r_vci_rsp_fifo_dcache.wok())
+                    {
+                        assert(!p_vci_ini_d.reop.read() &&
+                            "illegal VCI response packet for LL");
+                        vci_rsp_fifo_dcache_put  = true;
+                        vci_rsp_fifo_dcache_data = p_vci_ini_d.rdata.read();
+                        r_vci_rsp_cpt            = r_vci_rsp_cpt.read() + 1;
+                    }
+                    break;
+                }
+                else // last flit
+                {
+                    if(r_vci_rsp_fifo_dcache.wok())
+                    {
+                        assert(p_vci_ini_d.reop.read() &&
+                            "illegal VCI response packet for LL");
+                        vci_rsp_fifo_dcache_put  = true;
+                        vci_rsp_fifo_dcache_data = p_vci_ini_d.rdata.read();
+                        r_vci_rsp_fsm            = RSP_IDLE;
+                    }
+                    break;
+                }
+            }
+            break;
+        }
+        ////////////////////
+        case RSP_DATA_WRITE:
+        {
+            if (p_vci_ini_d.rspval.read())
+            {
+                assert( p_vci_ini_d.reop.read() and
+                "a VCI response packet must contain one flit for a write transaction");
+
+                r_vci_rsp_fsm = RSP_IDLE;
+                uint32_t   wbuf_index = p_vci_ini_d.rtrdid.read();
+                bool       cacheable  = r_wbuf.completed(wbuf_index);
+                if ( not cacheable ) r_dcache_pending_unc_write = false;
+                if ( (p_vci_ini_d.rerror.read()&0x1) != 0 ) r_iss.setWriteBerr();
+            }
+            break;
+        }
+    } // end switch r_vci_rsp_fsm
+
+    /////////////////////////////////////////////////////////////////////////////////////
+    // The CLEANUP FSM is in charge to send the cleanup commands on the coherence 
+    // network. It has two clients (DCACHE FSM and ICACHE FSM) that are served
+    // with a round-robin priority. All cleanup commands are registered in the 
+    // r_cleanup_buffer, because we must avoid to send a Read Miss command 
+    // for line (X) if there is a pending cleanup for line (X): the r_cleanup_buffer 
+    // is tested by the ICACHE FSM and DCACHE FSM before posting a miss request.
+    // The CLEANUP FSM resets the r_*cache_cleanup request flip-flops as soon as 
+    // the request has been sent and registered in the buffer.
+    // The buffer itself is cleared when the cleanup response is received.
+    // We use an assocative registration buffer (CAM) in order to support several
+    // simultaneous cleanup transactions (up to 4 simultaneous clenups).
+    // The VCI TRDID field is used to distinguish data/instruction cleanups:
+    // - if data cleanup        : TRDID = 2*index + 0
+    // - if instruction cleanup : TRDID = 2*index + 1
+    /////////////////////////////////////////////////////////////////////////////////////
+
+    switch ( r_cleanup_fsm.read() ) 
+    {
+        ///////////////////////
+        case CLEANUP_DATA_IDLE:     // dcache has highest priority
+        {
+            size_t  index = 0;
+            bool    ok;
+            if ( r_dcache_cleanup_req.read() )      // dcache request
+            {
+                ok = r_cleanup_buffer.write( r_dcache_cleanup_line.read(), 
+                                             &index );   
+                if ( ok )   // successful registration
+                {
+                    r_cleanup_fsm   = CLEANUP_DATA_GO; 
+                    r_cleanup_trdid = index<<1;
+                }
+            }
+            else if ( r_icache_cleanup_req.read() ) // icache request
+            {
+                ok = r_cleanup_buffer.write( r_icache_cleanup_line.read(), 
+                                             &index );   
+                if ( ok )   // successful registration
+                {
+                    r_cleanup_fsm   = CLEANUP_INS_GO; 
+                    r_cleanup_trdid = (index<<1) + 1;
+                }
+            }
+            break;
+        }
+        //////////////////////
+        case CLEANUP_INS_IDLE:     // icache has highest priority
+        {
+            size_t  index = 0;
+            bool    ok;
+            if ( r_icache_cleanup_req.read() )      // icache request
+            {
+                ok = r_cleanup_buffer.write( r_icache_cleanup_line.read(),
+                                             &index );   
+                if ( ok )   // successful registration
+                {
+                    r_cleanup_fsm   = CLEANUP_INS_GO;
+                    r_cleanup_trdid = (index<<1) + 1;
+                }
+            }
+            else if ( r_dcache_cleanup_req.read() ) // dcache request
+            {
+                ok = r_cleanup_buffer.write( r_dcache_cleanup_line.read(),
+                                             &index );   
+                if ( ok )   // successful registration
+                {
+                    r_cleanup_fsm   = CLEANUP_DATA_GO;
+                    r_cleanup_trdid = index<<1;
+                }
+            }
+            break;
+        }
+        /////////////////////
+        case CLEANUP_DATA_GO:
+        {
+            if ( p_vci_ini_c.cmdack.read() )
+            {
+                r_cleanup_fsm        = CLEANUP_INS_IDLE;
+                r_dcache_cleanup_req = false;
+
+#if DEBUG_CLEANUP
+if ( m_debug_cleanup_fsm )
+{
+    std::cout << "  <PROC " << name() << ".CLEANUP_DATA_GO> Cleanup request for icache:" << std::hex
+              << " address = " << (r_dcache_cleanup_line.read()*m_dcache_words*4)
+              << " / trdid = " << std::dec << r_cleanup_trdid.read() << std::endl;
+}
+#endif
+            }
+            break;
+        }
+        ////////////////////
+        case CLEANUP_INS_GO:
+        {
+            if ( p_vci_ini_c.cmdack.read() )
+            {
+                r_cleanup_fsm        = CLEANUP_DATA_IDLE;
+                r_icache_cleanup_req = false;
+
+#if DEBUG_CLEANUP
+if ( m_debug_cleanup_fsm )
+{
+    std::cout << "  <PROC " << name() << ".CLEANUP_INS_GO> Cleanup request for dcache:" << std::hex
+              << " address = " << (r_icache_cleanup_line.read()*m_icache_words*4)
+              << " / trdid = " << std::dec << r_cleanup_trdid.read() << std::endl;
+}
+#endif
+            }
+            break;
+        }
+    } // end switch CLEANUP FSM
+
+    //////////////// Handling  cleanup responses //////////////////
+    if ( p_vci_ini_c.rspval.read() )   
+    {
+        r_cleanup_buffer.inval( p_vci_ini_c.rtrdid.read() >> 1);
+    }
+
+    ///////////////// Response FIFOs update  //////////////////////
+    r_vci_rsp_fifo_icache.update(vci_rsp_fifo_icache_get,
+                                 vci_rsp_fifo_icache_put,
+                                 vci_rsp_fifo_icache_data);
+
+    r_vci_rsp_fifo_dcache.update(vci_rsp_fifo_dcache_get,
+                                 vci_rsp_fifo_dcache_put,
+                                 vci_rsp_fifo_dcache_data);
+
+    #undef LLSCLocalTable
+} // end transition()
+
+///////////////////////
+tmpl(void)::genMoore()
+///////////////////////
+{
+    ////////////////////////////////////////////////////////////////
+    // VCI initiator command on the coherence network (cleanup)
+    // it depends on the CLEANUP FSM state
+
+    paddr_t  cleanup_nline;
+    paddr_t  address;
+
+    if ( r_cleanup_fsm.read() == CLEANUP_DATA_GO )
+    {
+        cleanup_nline = r_dcache_cleanup_line.read();
+        address       = (m_x_width + m_y_width) ? (cleanup_nline * m_dcache_words * 4    ) >>
+                                                  (vci_param::N  - m_x_width - m_y_width ) : 0;
+    }
+    else if ( r_cleanup_fsm.read() == CLEANUP_INS_GO )
+    {
+        cleanup_nline = r_icache_cleanup_line.read();
+        address       = (m_x_width + m_y_width) ? (cleanup_nline * m_icache_words * 4    ) >>
+                                                  (vci_param::N  - m_x_width - m_y_width ) : 0;
+    }
+    else
+    {
+        cleanup_nline = 0;
+        address       = 0;
+    }
+
+    address           <<= vci_param::S - m_x_width - m_y_width;
+    address            |= m_memory_cache_local_id;
+    address           <<= vci_param::N - vci_param::S;
+
+    p_vci_ini_c.cmdval  = ((r_cleanup_fsm.read() == CLEANUP_DATA_GO) or
+                           (r_cleanup_fsm.read() == CLEANUP_INS_GO) );
+    p_vci_ini_c.address = address;
+    p_vci_ini_c.wdata   = (uint32_t) cleanup_nline;
+    p_vci_ini_c.be      = (cleanup_nline >> 32) & 0x3;
+    p_vci_ini_c.plen    = 4;
+    p_vci_ini_c.cmd     = vci_param::CMD_WRITE;
+    p_vci_ini_c.trdid   = r_cleanup_trdid.read();
+    p_vci_ini_c.pktid   = 0;
+    p_vci_ini_c.srcid   = m_srcid_c;
+    p_vci_ini_c.cons    = false;
+    p_vci_ini_c.wrap    = false;
+    p_vci_ini_c.contig  = false;
+    p_vci_ini_c.clen    = 0;
+    p_vci_ini_c.cfixed  = false;
+    p_vci_ini_c.eop     = true;
+
+    /////////////////////////////////////////////////////////////////
+    // VCI initiator response on the coherence network (cleanup)
+    // We always consume the response, and we don't use it.
+
+    p_vci_ini_c.rspack  = true;
+
+    /////////////////////////////////////////////////////////////////
+    // VCI initiator command on the direct network
+    // it depends on the CMD FSM state
+
+    bool is_sc_or_cas  = (r_vci_cmd_fsm.read() == CMD_DATA_CAS) or
+                         (r_vci_cmd_fsm.read() == CMD_DATA_SC );
+
+    p_vci_ini_d.pktid  = 0;
+    p_vci_ini_d.srcid  = m_srcid_d;
+    p_vci_ini_d.cons   = is_sc_or_cas; 
+    p_vci_ini_d.contig = not is_sc_or_cas; 
+    p_vci_ini_d.wrap   = false;
+    p_vci_ini_d.clen   = 0;
+    p_vci_ini_d.cfixed = false;
+
+    switch ( r_vci_cmd_fsm.read() ) {
+
+    case CMD_IDLE:
+        p_vci_ini_d.cmdval  = false;
+        p_vci_ini_d.address = 0;
+        p_vci_ini_d.wdata   = 0;
+        p_vci_ini_d.be      = 0;
+        p_vci_ini_d.trdid   = 0;
+        p_vci_ini_d.pktid   = 0;
+        p_vci_ini_d.plen    = 0;
+        p_vci_ini_d.cmd     = vci_param::CMD_NOP;
+        p_vci_ini_d.eop     = false;
+        break;
+
+    case CMD_INS_MISS:
+        p_vci_ini_d.cmdval  = true;
+        p_vci_ini_d.address = r_icache_vci_paddr.read() & m_icache_yzmask;
+        p_vci_ini_d.wdata   = 0;
+        p_vci_ini_d.be      = 0xF;
+        p_vci_ini_d.trdid   = 0;
+        p_vci_ini_d.pktid   = TYPE_READ_INS_MISS;
+        p_vci_ini_d.plen    = m_icache_words<<2;
+        p_vci_ini_d.cmd     = vci_param::CMD_READ;
+        p_vci_ini_d.eop     = true;
+        break;
+
+    case CMD_INS_UNC:
+        p_vci_ini_d.cmdval  = true;
+        p_vci_ini_d.address = r_icache_vci_paddr.read() & ~0x3;
+        p_vci_ini_d.wdata   = 0;
+        p_vci_ini_d.be      = 0xF;
+        p_vci_ini_d.trdid   = 0;
+        p_vci_ini_d.pktid   = TYPE_READ_INS_UNC;
+        p_vci_ini_d.plen    = 4;
+        p_vci_ini_d.cmd     = vci_param::CMD_READ;
+        p_vci_ini_d.eop     = true;
+        break;
+
+    case CMD_DATA_MISS:
+        p_vci_ini_d.cmdval  = true;
+        p_vci_ini_d.address = r_dcache_vci_paddr.read() & m_dcache_yzmask;
+        p_vci_ini_d.wdata   = 0;
+        p_vci_ini_d.be      = 0xF;
+        p_vci_ini_d.trdid   = 0;
+        p_vci_ini_d.pktid   = TYPE_READ_DATA_MISS;
+        p_vci_ini_d.plen    = m_dcache_words << 2;
+        p_vci_ini_d.cmd     = vci_param::CMD_READ;
+        p_vci_ini_d.eop     = true;
+        break;
+
+    case CMD_DATA_UNC:
+        p_vci_ini_d.cmdval  = true;
+        p_vci_ini_d.address = r_dcache_vci_paddr.read() & ~0x3;
+        p_vci_ini_d.wdata   = 0;
+        p_vci_ini_d.be      = r_dcache_vci_unc_be.read();
+        p_vci_ini_d.trdid   = 0;
+        p_vci_ini_d.pktid   = TYPE_READ_DATA_UNC;
+        p_vci_ini_d.plen    = 4;
+        p_vci_ini_d.cmd     = vci_param::CMD_READ;
+        p_vci_ini_d.eop     = true;
+        break;
+
+    case CMD_DATA_WRITE:
+        p_vci_ini_d.cmdval  = true;
+        p_vci_ini_d.address = r_wbuf.getAddress(r_vci_cmd_cpt.read()) & ~0x3;
+        p_vci_ini_d.wdata   = r_wbuf.getData(r_vci_cmd_cpt.read());
+        p_vci_ini_d.be      = r_wbuf.getBe(r_vci_cmd_cpt.read());
+        p_vci_ini_d.trdid   = r_wbuf.getIndex();
+        p_vci_ini_d.pktid   = TYPE_WRITE;
+        p_vci_ini_d.plen    = (r_vci_cmd_max.read() - r_vci_cmd_min.read() + 1) << 2;
+        p_vci_ini_d.cmd     = vci_param::CMD_WRITE;
+        p_vci_ini_d.eop     = (r_vci_cmd_cpt.read() == r_vci_cmd_max.read());
+        break;
+
+    case CMD_DATA_LL:
+        p_vci_ini_d.cmdval  = true;
+        p_vci_ini_d.address = r_dcache_vci_paddr.read() & ~0x3;
+        p_vci_ini_d.wdata   = 0;
+        p_vci_ini_d.be      = 0xF;
+        p_vci_ini_d.trdid   = 0;    //TODO local table index
+        p_vci_ini_d.pktid   = TYPE_LL;
+        p_vci_ini_d.plen    = 8;
+        p_vci_ini_d.cmd     = vci_param::CMD_LOCKED_READ;
+        p_vci_ini_d.eop     = true;
+        break;
+
+    case CMD_DATA_SC:
+        p_vci_ini_d.cmdval  = true;
+        p_vci_ini_d.address = r_dcache_vci_paddr.read() & ~0x3;
+        if ( r_vci_cmd_cpt.read() == 0 ) p_vci_ini_d.wdata = r_sc_key.read();
+        else                             p_vci_ini_d.wdata = r_dcache_vci_sc_data.read();
+        p_vci_ini_d.be      = 0xF;
+        p_vci_ini_d.trdid   = 0;
+        p_vci_ini_d.pktid   = TYPE_SC;
+        p_vci_ini_d.plen    = 8;
+        p_vci_ini_d.cmd     = vci_param::CMD_NOP;
+        p_vci_ini_d.eop     = (r_vci_cmd_cpt.read() == 1);
+        break;      
+
+    case CMD_DATA_CAS:
+        p_vci_ini_d.cmdval  = true;
+        p_vci_ini_d.address = r_dcache_vci_paddr.read() & ~0x3;
+        if ( r_vci_cmd_cpt.read() == 0 ) p_vci_ini_d.wdata = r_dcache_vci_cas_old.read();
+        else                             p_vci_ini_d.wdata = r_dcache_vci_cas_new.read();
+        p_vci_ini_d.be      = 0xF;
+        p_vci_ini_d.trdid   = 0;
+        p_vci_ini_d.pktid   = TYPE_CAS;
+        p_vci_ini_d.plen    = 8;
+        p_vci_ini_d.cmd     = vci_param::CMD_NOP;
+        p_vci_ini_d.eop     = (r_vci_cmd_cpt.read() == 1);
+        break;      
+    } // end switch r_vci_cmd_fsm
+
+    //////////////////////////////////////////////////////////
+    // VCI initiator response on the direct network
+    // it depends on the VCI RSP state
+
+    switch (r_vci_rsp_fsm.read() )
+    {
+        case RSP_DATA_WRITE : p_vci_ini_d.rspack = true; break;
+        case RSP_INS_MISS   : p_vci_ini_d.rspack = r_vci_rsp_fifo_icache.wok(); break;
+        case RSP_INS_UNC    : p_vci_ini_d.rspack = r_vci_rsp_fifo_icache.wok(); break;
+        case RSP_DATA_MISS  : p_vci_ini_d.rspack = r_vci_rsp_fifo_dcache.wok(); break;
+        case RSP_DATA_UNC   : p_vci_ini_d.rspack = r_vci_rsp_fifo_dcache.wok(); break;
+        case RSP_DATA_LL    : p_vci_ini_d.rspack = r_vci_rsp_fifo_dcache.wok(); break;
+        case RSP_IDLE       : p_vci_ini_d.rspack = false; break;
+    } // end switch r_vci_rsp_fsm
+
+    ////////////////////////////////////////////////////////////////
+    // VCI target command and response on the coherence network
+    switch ( r_tgt_fsm.read() ) 
+    {
+    case TGT_IDLE:
+    case TGT_UPDT_WORD:
+    case TGT_UPDT_DATA:
+        p_vci_tgt_c.cmdack  = true;
+        p_vci_tgt_c.rspval  = false;
+        break;
+
+    case TGT_RSP_BROADCAST:
+        p_vci_tgt_c.cmdack  = false;
+        p_vci_tgt_c.rspval  = not r_tgt_icache_req.read() and not r_tgt_dcache_req.read()
+                              and ( r_tgt_icache_rsp.read() or r_tgt_dcache_rsp.read() );
+        p_vci_tgt_c.rsrcid  = r_tgt_srcid.read();
+        p_vci_tgt_c.rpktid  = r_tgt_pktid.read();
+        p_vci_tgt_c.rtrdid  = r_tgt_trdid.read();
+        p_vci_tgt_c.rdata   = 0;
+        p_vci_tgt_c.rerror  = 0;
+        p_vci_tgt_c.reop    = true;
+        break;
+
+    case TGT_RSP_ICACHE:
+        p_vci_tgt_c.cmdack  = false;
+        p_vci_tgt_c.rspval  = not r_tgt_icache_req.read() and r_tgt_icache_rsp.read();
+        p_vci_tgt_c.rsrcid  = r_tgt_srcid.read();
+        p_vci_tgt_c.rpktid  = r_tgt_pktid.read();
+        p_vci_tgt_c.rtrdid  = r_tgt_trdid.read();
+        p_vci_tgt_c.rdata   = 0;
+        p_vci_tgt_c.rerror  = 0;
+        p_vci_tgt_c.reop    = true;
+        break;
+
+    case TGT_RSP_DCACHE:
+        p_vci_tgt_c.cmdack  = false;
+        p_vci_tgt_c.rspval  = not r_tgt_dcache_req.read() and r_tgt_dcache_rsp.read();
+        p_vci_tgt_c.rsrcid  = r_tgt_srcid.read();
+        p_vci_tgt_c.rpktid  = r_tgt_pktid.read();
+        p_vci_tgt_c.rtrdid  = r_tgt_trdid.read();
+        p_vci_tgt_c.rdata   = 0;
+        p_vci_tgt_c.rerror  = 0;
+        p_vci_tgt_c.reop    = true;
+        break;
+
+    case TGT_REQ_BROADCAST:
+    case TGT_REQ_ICACHE:
+    case TGT_REQ_DCACHE:
+        p_vci_tgt_c.cmdack  = false;
+        p_vci_tgt_c.rspval  = false;
+        break;
+
+    } // end switch TGT_FSM
+} // end genMoore
+
+}}
+
+// Local Variables:
+// tab-width: 4
+// c-basic-offset: 4
+// c-file-offsets:((innamespace . 0)(inline-open . 0))
+// indent-tabs-mode: nil
+// End:
+
+// vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4
Index: branches/v4/modules/vci_cc_xcache_wrapper/caba/metadata/vci_cc_xcache_wrapper.sd
===================================================================
--- branches/v4/modules/vci_cc_xcache_wrapper/caba/metadata/vci_cc_xcache_wrapper.sd	(revision 371)
+++ branches/v4/modules/vci_cc_xcache_wrapper/caba/metadata/vci_cc_xcache_wrapper.sd	(revision 371)
@@ -0,0 +1,56 @@
+
+# -*- python -*-
+
+__id__ = "$Id$"
+__version__ = "$Revision$"
+
+Module('caba:vci_cc_xcache_wrapper',
+	classname = 'soclib::caba::VciCcXcacheWrapper',
+	tmpl_parameters = [
+		parameter.Module('vci_param', default = 'caba:vci_param'),
+		parameter.Module('iss_t'),
+		],
+	header_files = [
+		'../source/include/vci_cc_xcache_wrapper.h',
+		],
+	implementation_files = [
+		'../source/src/vci_cc_xcache_wrapper.cpp',
+		],
+	uses = [
+		Uses('caba:base_module'),
+		Uses('common:mapping_table'),
+		Uses('common:iss2'),
+		Uses('caba:write_buffer'),
+		Uses('caba:generic_cache', addr_t = 'uint32_t'),
+		],
+	ports = [
+		Port('caba:vci_initiator', 'p_vci_ini'),
+		Port('caba:vci_target', 'p_vci_tgt'),
+		Port('caba:bit_in', 'p_irq', parameter.Constant('n_irq')),
+		Port('caba:bit_in', 'p_resetn', auto = 'resetn'),
+		Port('caba:clock_in', 'p_clk', auto = 'clock'),
+		],
+	instance_parameters = [
+		parameter.Int('proc_id'),
+		parameter.Module('mt', 'common:mapping_table'),
+		parameter.IntTab('initiator_index'),
+		parameter.IntTab('target_index'),
+		parameter.Int('icache_ways'),
+		parameter.Int('icache_sets'),
+		parameter.Int('icache_words'),
+		parameter.Int('dcache_ways'),
+		parameter.Int('dcache_sets'),
+		parameter.Int('dcache_words'),
+		],
+	   extensions = [
+	'dsx:get_ident='
+        'initiator_index:p_vci_ini:mc,'
+        'target_index:p_vci_tgt:mc',
+	'dsx:cpu=wrapper:iss_t',
+	'dsx:addressable=target_index',
+    'dsx:on_segment=mc:add_index:initiator_index',
+	'dsx:mapping_type=processor:proc_id',
+   ],
+)
+
+
Index: branches/v4/modules/vci_cc_xcache_wrapper/caba/source/include/vci_cc_xcache_wrapper.h
===================================================================
--- branches/v4/modules/vci_cc_xcache_wrapper/caba/source/include/vci_cc_xcache_wrapper.h	(revision 371)
+++ branches/v4/modules/vci_cc_xcache_wrapper/caba/source/include/vci_cc_xcache_wrapper.h	(revision 371)
@@ -0,0 +1,287 @@
+/* -*- c++ -*-
+ *
+ * SOCLIB_LGPL_HEADER_BEGIN
+ * 
+ * This file is part of SoCLib, GNU LGPLv2.1.
+ * 
+ * SoCLib is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU Lesser General Public License as published
+ * by the Free Software Foundation; version 2.1 of the License.
+ * 
+ * SoCLib is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * Lesser General Public License for more details.
+ * 
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with SoCLib; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301 USA
+ * 
+ * SOCLIB_LGPL_HEADER_END
+ *
+ * Copyright (c) UPMC, Lip6, SoC
+ *         Alain Greiner <alain.greiner@lip6.fr>, 2008
+ *
+ * Maintainers: alain
+ */
+ 
+#ifndef SOCLIB_CABA_VCI_CC_XCACHE_WRAPPER_H
+#define SOCLIB_CABA_VCI_CC_XCACHE_WRAPPER_H
+
+#include <inttypes.h>
+#include <systemc>
+#include "caba_base_module.h"
+#include "write_buffer.h"
+#include "generic_cache.h"
+#include "vci_initiator.h"
+#include "vci_target.h"
+#include "mapping_table.h"
+#include "static_assert.h"
+
+namespace soclib {
+namespace caba {
+
+using namespace sc_core;
+
+////////////////////////////////////////////
+template<typename vci_param, typename iss_t>
+class VciCcXcacheWrapper
+///////////////////////////////////////////
+    : public soclib::caba::BaseModule
+{
+    typedef uint32_t    addr_t;
+    typedef uint32_t    data_t;
+    typedef uint32_t    tag_t;
+    typedef uint32_t    be_t;
+
+    enum dcache_fsm_state_e {
+        DCACHE_IDLE,
+        DCACHE_WRITE_UPDT,
+        DCACHE_WRITE_REQ,
+        DCACHE_MISS_WAIT,
+        DCACHE_MISS_UPDT,
+        DCACHE_UNC_WAIT,
+        DCACHE_INVAL,
+        DCACHE_ERROR,
+        DCACHE_CC_CHECK,
+        DCACHE_CC_INVAL,
+        DCACHE_CC_UPDT,
+        DCACHE_CC_NOP,
+    };
+
+    enum icache_fsm_state_e {
+        ICACHE_IDLE,
+        ICACHE_MISS_WAIT,
+        ICACHE_MISS_UPDT,
+        ICACHE_UNC_WAIT,
+        ICACHE_ERROR,
+        ICACHE_CC_INVAL,
+    };
+
+    enum cmd_fsm_state_e {
+        CMD_IDLE,
+        CMD_INS_MISS,
+        CMD_INS_UNC,
+        CMD_DATA_MISS,
+        CMD_DATA_UNC,
+        CMD_DATA_WRITE,
+        CMD_INS_CLEANUP,
+        CMD_DATA_CLEANUP,
+    };
+
+    enum rsp_fsm_state_e {
+        RSP_IDLE,
+        RSP_INS_MISS,
+        RSP_INS_UNC,
+        RSP_DATA_MISS,
+        RSP_DATA_UNC,
+        RSP_DATA_WRITE,
+        RSP_INS_CLEANUP,
+        RSP_DATA_CLEANUP,
+    };
+
+    enum tgt_fsm_state_e {
+        TGT_IDLE,
+        TGT_UPDT_WORD,
+        TGT_UPDT_DATA,
+        TGT_REQ_BROADCAST,
+        TGT_REQ_DCACHE,
+        TGT_RSP_BROADCAST,
+        TGT_RSP_DCACHE,
+    };
+
+public:
+
+    // PORTS
+    sc_in<bool>                             p_clk;
+    sc_in<bool>                             p_resetn;
+    sc_in<bool>                             p_irq[iss_t::n_irq];
+    soclib::caba::VciInitiator<vci_param>   p_vci_ini;
+    soclib::caba::VciTarget<vci_param>      p_vci_tgt;
+
+private:
+
+    // STRUCTURAL PARAMETERS
+    const soclib::common::AddressDecodingTable<uint32_t, bool>  m_cacheability_table;
+    const soclib::common::Segment                               m_segment;
+    iss_t                                                       m_iss;
+    const uint32_t                                              m_srcid;   
+    addr_t                                                      m_cleanup_address;
+    
+    const size_t                                                m_dcache_ways;
+    const size_t                                                m_dcache_words;
+    const size_t                                                m_dcache_yzmask;
+    const size_t                                                m_icache_ways;
+    const size_t                                                m_icache_words;
+    const size_t                                                m_icache_yzmask;
+
+    // REGISTERS
+    sc_signal<int>          r_dcache_fsm;
+    sc_signal<int>          r_dcache_fsm_save;
+    sc_signal<addr_t>       r_dcache_addr_save;
+    sc_signal<data_t>       r_dcache_wdata_save;
+    sc_signal<data_t>       r_dcache_rdata_save;
+    sc_signal<int>          r_dcache_type_save;
+    sc_signal<be_t>         r_dcache_be_save;
+    sc_signal<bool>         r_dcache_cached_save;
+    sc_signal<bool>         r_dcache_cleanup_req;
+    sc_signal<data_t>       r_dcache_cleanup_line;
+    sc_signal<bool>         r_dcache_miss_req;
+    sc_signal<bool>         r_dcache_unc_req;
+    sc_signal<bool>         r_dcache_write_req;
+    sc_signal<bool>         r_dcache_inval_rsp;
+
+    sc_signal<int>          r_icache_fsm;
+    sc_signal<int>          r_icache_fsm_save;
+    sc_signal<addr_t>       r_icache_addr_save;
+    sc_signal<bool>         r_icache_miss_req;
+    sc_signal<bool>         r_icache_unc_req;
+    sc_signal<bool>         r_icache_cleanup_req;
+    sc_signal<data_t>       r_icache_cleanup_line;
+    sc_signal<bool>         r_icache_inval_rsp;
+
+    sc_signal<int>          r_vci_cmd_fsm;
+    sc_signal<size_t>       r_vci_cmd_min;       
+    sc_signal<size_t>       r_vci_cmd_max;       
+    sc_signal<size_t>       r_vci_cmd_cpt;       
+      
+    sc_signal<int>          r_vci_rsp_fsm;
+    sc_signal<bool>         r_vci_rsp_ins_error;    
+    sc_signal<bool>         r_vci_rsp_data_error;    
+    sc_signal<size_t>       r_vci_rsp_cpt;  
+
+    data_t                  *r_icache_miss_buf;    
+    data_t                  *r_dcache_miss_buf;    
+    sc_signal<bool>         r_icache_buf_unc_valid;
+    sc_signal<bool>         r_dcache_buf_unc_valid;
+
+    data_t                  *r_tgt_buf;
+    bool                    *r_tgt_val;
+
+    sc_signal<int>          r_vci_tgt_fsm;
+    sc_signal<size_t>       r_tgt_addr;
+    sc_signal<size_t>       r_tgt_word;
+    sc_signal<bool>         r_tgt_update;
+    sc_signal<size_t>       r_tgt_srcid;
+    sc_signal<size_t>       r_tgt_pktid;
+    sc_signal<size_t>       r_tgt_trdid;
+    sc_signal<size_t>       r_tgt_plen;
+    sc_signal<bool>         r_tgt_icache_req;
+    sc_signal<bool>         r_tgt_dcache_req;
+    sc_signal<bool>         r_tgt_icache_rsp;
+    sc_signal<bool>         r_tgt_dcache_rsp;
+
+    WriteBuffer<addr_t>     r_wbuf;
+    GenericCache<addr_t>    r_icache;
+    GenericCache<addr_t>    r_dcache;
+
+    // Activity counters
+    uint32_t m_cpt_dcache_data_read;        // DCACHE DATA READ
+    uint32_t m_cpt_dcache_data_write;       // DCACHE DATA WRITE
+    uint32_t m_cpt_dcache_dir_read;         // DCACHE DIR READ
+    uint32_t m_cpt_dcache_dir_write;        // DCACHE DIR WRITE
+
+    uint32_t m_cpt_icache_data_read;        // ICACHE DATA READ
+    uint32_t m_cpt_icache_data_write;       // ICACHE DATA WRITE
+    uint32_t m_cpt_icache_dir_read;         // ICACHE DIR READ
+    uint32_t m_cpt_icache_dir_write;        // ICACHE DIR WRITE
+
+    uint32_t m_cpt_cc_update;               // number of coherence update packets 
+    uint32_t m_cpt_cc_inval;                // number of coherence inval packets
+
+    uint32_t m_cpt_frz_cycles;	            // number of cycles where the cpu is frozen
+    uint32_t m_cpt_total_cycles;	        // total number of cycles 
+
+    uint32_t m_cpt_read;                    // total number of read instructions
+    uint32_t m_cpt_write;                   // total number of write instructions
+    uint32_t m_cpt_data_miss;               // number of read miss
+    uint32_t m_cpt_ins_miss;                // number of instruction miss
+    uint32_t m_cpt_unc_read;                // number of read uncached
+    uint32_t m_cpt_write_cached;            // number of cached write
+
+    uint32_t m_cost_write_frz;              // number of frozen cycles related to write buffer         
+    uint32_t m_cost_data_miss_frz;          // number of frozen cycles related to data miss
+    uint32_t m_cost_unc_read_frz;           // number of frozen cycles related to uncached read
+    uint32_t m_cost_ins_miss_frz;           // number of frozen cycles related to ins miss
+
+    uint32_t m_cpt_imiss_transaction;       // number of VCI instruction miss transactions
+    uint32_t m_cpt_dmiss_transaction;       // number of VCI data miss transactions
+    uint32_t m_cpt_unc_transaction;         // number of VCI uncached read transactions
+    uint32_t m_cpt_write_transaction;       // number of VCI write transactions
+
+    uint32_t m_cost_imiss_transaction;      // cumulated duration for VCI IMISS transactions
+    uint32_t m_cost_dmiss_transaction;      // cumulated duration for VCI DMISS transactions
+    uint32_t m_cost_unc_transaction;        // cumulated duration for VCI UNC transactions
+    uint32_t m_cost_write_transaction;      // cumulated duration for VCI WRITE transactions
+    uint32_t m_length_write_transaction;    // cumulated length for VCI WRITE transactions
+
+protected:
+    SC_HAS_PROCESS(VciCcXcacheWrapper);
+
+public:
+
+    VciCcXcacheWrapper(
+                       sc_module_name insname,
+                       int proc_id,
+                       const soclib::common::MappingTable &mtp,
+                       const soclib::common::MappingTable &mtc,
+                       const soclib::common::IntTab &initiator_index,
+                       const soclib::common::IntTab &target_index,
+                       size_t icache_ways,
+                       size_t icache_sets,
+                       size_t icache_words,
+                       size_t dcache_ways,
+                       size_t dcache_sets,
+                       size_t dcache_words,
+                       addr_t cleanup_offset );
+
+    ~VciCcXcacheWrapper();
+
+    void print_cpi();
+    void print_stats();
+
+private:
+
+    void transition();
+    void genMoore();
+
+    soclib_static_assert((int)iss_t::SC_ATOMIC == (int)vci_param::STORE_COND_ATOMIC);
+    soclib_static_assert((int)iss_t::SC_NOT_ATOMIC == (int)vci_param::STORE_COND_NOT_ATOMIC);
+};
+
+}}
+
+#endif /* SOCLIB_CABA_VCI_CC_XCACHE_WRAPPER_H */
+
+// Local Variables:
+// tab-width: 4
+// c-basic-offset: 4
+// c-file-offsets:((innamespace . 0)(inline-open . 0))
+// indent-tabs-mode: nil
+// End:
+
+// vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4
+
+
+
Index: branches/v4/modules/vci_cc_xcache_wrapper/caba/source/src/vci_cc_xcache_wrapper.cpp
===================================================================
--- branches/v4/modules/vci_cc_xcache_wrapper/caba/source/src/vci_cc_xcache_wrapper.cpp	(revision 371)
+++ branches/v4/modules/vci_cc_xcache_wrapper/caba/source/src/vci_cc_xcache_wrapper.cpp	(revision 371)
@@ -0,0 +1,1564 @@
+/* -*- c++ -*-
+ *
+ * SOCLIB_LGPL_HEADER_BEGIN
+ * 
+ * This file is part of SoCLib, GNU LGPLv2.1.
+ * 
+ * SoCLib is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU Lesser General Public License as published
+ * by the Free Software Foundation; version 2.1 of the License.
+ * 
+ * SoCLib is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * Lesser General Public License for more details.
+ * 
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with SoCLib; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301 USA
+ * 
+ * SOCLIB_LGPL_HEADER_END
+ *
+ * Copyright (c) UPMC, Lip6, SoC
+ *         Alain Greiner <alain.greiner@lip6.fr>, 2008
+ *
+ * Maintainers: alain eric.guthmuller@polytechnique.edu nipo
+ */
+
+/////////////////////////////////////////////////////////////////////////////
+// History
+// - 25/04/2008
+//   The existing vci_xcache component has been extended to include 
+//   a VCI target port to support a directory based coherence protocol.
+//   Two types of packets can be send by the L2 cache to the L1 cache
+//   * INVALIDATE packets : length = 1
+//   * UPDATE packets : length = n + 2   
+//   The CLEANUP packets are sent by the L1 cache to the L2 cache, 
+//   to signal a replaced cache line.
+// - 12/08/2008
+//   The vci_cc_xcache_wrapper component instanciates directly the processsor 
+//   iss, in order to supress the processor/cache interface.
+//   According to the VCI advanced specification, this component uses one 
+//   word VCI CMD packets for MISS transactions, and accept one word VCI RSP
+//   packets for Write burst  transactions.
+//   The write buffer has been modified to use the WriteBuffer object. 
+//   A VCI write burst is constructed when two conditions are satisfied :
+//   The processor make strictly successive write requests, and they are
+//   in the same cache line. The write buffer performs re-ordering, to
+//   respect the contiguous addresses VCI constraint. In case of several
+//   WRITE_WORD requests in the same word, only the last request is conserved.
+//   In case of several WRITE_HALF or WRITE_WORD requests in the same word,
+//   the requests are merged in the same word. In case of uncached write
+//   requests, each request is transmited as a single VCI transaction.
+//   Both the data & instruction caches can be flushed in one single cycle.
+///////////////////////////////////////////////////////////////////////////////
+
+#include <cassert>
+#include "arithmetics.h"
+#include "../include/vci_cc_xcache_wrapper.h"
+
+#define DEBUG_CC_XCACHE_WRAPPER 0
+
+namespace soclib { 
+namespace caba {
+
+#if DEBUG_CC_XCACHE_WRAPPER
+namespace {
+const char *dcache_fsm_state_str[] = {
+    "DCACHE_IDLE",
+    "DCACHE_WRITE_UPDT",
+    "DCACHE_WRITE_REQ",
+    "DCACHE_MISS_WAIT",
+    "DCACHE_MISS_UPDT",
+    "DCACHE_UNC_WAIT",
+    "DCACHE_INVAL",
+    "DCACHE_ERROR",
+    "DCACHE_CC_CHECK",
+    "DCACHE_CC_INVAL",
+    "DCACHE_CC_UPDT",
+    "DCACHE_CC_NOP",
+};
+const char *icache_fsm_state_str[] = {
+    "ICACHE_IDLE",
+    "ICACHE_MISS_WAIT",
+    "ICACHE_MISS_UPDT",
+    "ICACHE_UNC_WAIT",
+    "ICACHE_ERROR",
+    "ICACHE_CC_INVAL",
+};
+const char *cmd_fsm_state_str[] = {
+    "CMD_IDLE",
+    "CMD_INS_MISS",
+    "CMD_INS_UNC",
+    "CMD_DATA_MISS",
+    "CMD_DATA_UNC",
+    "CMD_DATA_WRITE",
+};
+const char *rsp_fsm_state_str[] = {
+    "RSP_IDLE",
+    "RSP_INS_MISS",
+    "RSP_INS_UNC",
+    "RSP_DATA_MISS",
+    "RSP_DATA_UNC",
+    "RSP_DATA_WRITE",
+};
+const char *tgt_fsm_state_str[] = {
+    "TGT_IDLE",
+    "TGT_UPDT_WORD",
+    "TGT_UPDT_DATA",
+    "TGT_REQ_BROADCAST",
+    "TGT_REQ_DCACHE",
+    "TGT_RSP_BROADCAST",
+    "TGT_RSP_DCACHE",
+};
+}
+#endif
+
+#define tmpl(...)  template<typename vci_param, typename iss_t> __VA_ARGS__ VciCcXcacheWrapper<vci_param, iss_t>
+
+using soclib::common::uint32_log2;
+
+/////////////////////////////////
+tmpl(/**/)::VciCcXcacheWrapper(
+                               /////////////////////////////////
+                               sc_module_name name,
+                               int proc_id,
+                               const soclib::common::MappingTable &mtp,
+                               const soclib::common::MappingTable &mtc,
+                               const soclib::common::IntTab &initiator_index,
+                               const soclib::common::IntTab &target_index,
+                               size_t icache_ways,
+                               size_t icache_sets,
+                               size_t icache_words,
+                               size_t dcache_ways,
+                               size_t dcache_sets,
+                               size_t dcache_words,
+                               addr_t cleanup_offset )
+           : 
+           soclib::caba::BaseModule(name),
+
+           p_clk("clk"),
+           p_resetn("resetn"),
+           p_vci_ini("vci_ini"),
+           p_vci_tgt("vci_tgt"),
+
+           m_cacheability_table(mtp.getCacheabilityTable()),
+           m_segment(mtc.getSegment(target_index)),
+           m_iss(this->name(), proc_id),
+           m_srcid(mtp.indexForId(initiator_index)),
+           m_cleanup_address(cleanup_offset),
+
+           m_dcache_ways(dcache_ways),
+           m_dcache_words(dcache_words),
+           m_dcache_yzmask((~0)<<(uint32_log2(dcache_words) + 2)),
+           m_icache_ways(icache_ways),
+           m_icache_words(icache_words),
+           m_icache_yzmask((~0)<<(uint32_log2(icache_words) + 2)),
+
+           r_dcache_fsm("r_dcache_fsm"),
+           r_dcache_fsm_save("r_dcache_fsm_save"),
+           r_dcache_addr_save("r_dcache_addr_save"),
+           r_dcache_wdata_save("r_dcache_wdata_save"),
+           r_dcache_rdata_save("r_dcache_rdata_save"),
+           r_dcache_type_save("r_dcache_type_save"),
+           r_dcache_be_save("r_dcache_be_save"),
+           r_dcache_cached_save("r_dcache_cached_save"),
+           r_dcache_cleanup_req("r_dcache_cleanup_req"),
+           r_dcache_cleanup_line("r_dcache_cleanup_line"),
+           r_dcache_miss_req("r_dcache_miss_req"),
+           r_dcache_unc_req("r_dcache_unc_req"),
+           r_dcache_write_req("r_dcache_write_req"),
+
+           r_icache_fsm("r_icache_fsm"),
+           r_icache_fsm_save("r_icache_fsm_save"),
+           r_icache_addr_save("r_icache_addr_save"),
+           r_icache_miss_req("r_icache_miss_req"),
+           r_icache_cleanup_req("r_icache_cleanup_req"),
+           r_icache_cleanup_line("r_icache_cleanup_line"),
+
+           r_vci_cmd_fsm("r_vci_cmd_fsm"),
+           r_vci_cmd_min("r_vci_cmd_min"),
+           r_vci_cmd_max("r_vci_cmd_max"),
+           r_vci_cmd_cpt("r_vci_cmd_cpt"),
+
+           r_vci_rsp_fsm("r_vci_rsp_fsm"),
+           r_vci_rsp_ins_error("r_vci_rsp_ins_error"),
+           r_vci_rsp_data_error("r_vci_rsp_data_error"),
+           r_vci_rsp_cpt("r_vci_rsp_cpt"),
+
+           r_dcache_buf_unc_valid("r_dcache_buf_unc_valid"),
+           r_icache_buf_unc_valid("r_icache_buf_unc_valid"),
+
+           r_vci_tgt_fsm("r_vci_tgt_fsm"),
+           r_tgt_addr("r_tgt_addr"),
+           r_tgt_word("r_tgt_word"),
+           r_tgt_update("r_tgt_update"),
+           r_tgt_srcid("r_tgt_srcid"),
+           r_tgt_pktid("r_tgt_pktid"),
+           r_tgt_trdid("r_tgt_trdid"),
+           r_tgt_icache_req("r_tgt_icache_req"),
+           r_tgt_dcache_req("r_tgt_dcache_req"),
+
+           r_wbuf("r_wbuf", dcache_words ),
+           r_icache("icache", icache_ways, icache_sets, icache_words),
+           r_dcache("dcache", dcache_ways, dcache_sets, dcache_words)
+
+{
+    r_icache_miss_buf = new data_t[icache_words];
+    r_dcache_miss_buf = new data_t[dcache_words];
+    r_tgt_buf         = new data_t[dcache_words];
+    r_tgt_val         = new bool[dcache_words];
+
+    SC_METHOD(transition);
+    dont_initialize();
+    sensitive << p_clk.pos();
+  
+    SC_METHOD(genMoore);
+    dont_initialize();
+    sensitive << p_clk.neg();
+
+    typename iss_t::CacheInfo cache_info;
+    cache_info.has_mmu = false;
+    cache_info.icache_line_size = icache_words*sizeof(data_t);
+    cache_info.icache_assoc = icache_ways;
+    cache_info.icache_n_lines = icache_sets;
+    cache_info.dcache_line_size = dcache_words*sizeof(data_t);
+    cache_info.dcache_assoc = dcache_ways;
+    cache_info.dcache_n_lines = dcache_sets;
+    m_iss.setCacheInfo(cache_info);
+} // end constructor
+
+///////////////////////////////////
+tmpl(/**/)::~VciCcXcacheWrapper()
+           ///////////////////////////////////
+{
+    delete [] r_icache_miss_buf;
+    delete [] r_dcache_miss_buf;
+    delete [] r_tgt_val;
+    delete [] r_tgt_buf;
+}
+
+////////////////////////
+tmpl(void)::print_cpi()
+           ////////////////////////
+{
+    std::cout << "CPU " << m_srcid << " : CPI = " 
+              << (float)m_cpt_total_cycles/(m_cpt_total_cycles - m_cpt_frz_cycles) << std::endl ;
+}
+////////////////////////
+tmpl(void)::print_stats()
+           ////////////////////////
+{
+    float run_cycles = (float)(m_cpt_total_cycles - m_cpt_frz_cycles);
+    std::cout << "------------------------------------" << std:: dec << std::endl;
+    std::cout << "CPU " << m_srcid << " / Time = " << m_cpt_total_cycles << std::endl;
+    std::cout << "- CPI                = " << (float)m_cpt_total_cycles/run_cycles << std::endl ;
+    std::cout << "- READ RATE          = " << (float)m_cpt_read/run_cycles << std::endl ;
+    std::cout << "- WRITE RATE         = " << (float)m_cpt_write/run_cycles << std::endl;
+    std::cout << "- UNCACHED READ RATE = " << (float)m_cpt_unc_read/m_cpt_read << std::endl ;
+    std::cout << "- CACHED WRITE RATE  = " << (float)m_cpt_write_cached/m_cpt_write << std::endl ;
+    std::cout << "- IMISS_RATE         = " << (float)m_cpt_ins_miss/run_cycles << std::endl;
+    std::cout << "- DMISS RATE         = " << (float)m_cpt_data_miss/(m_cpt_read-m_cpt_unc_read) << std::endl ;
+    std::cout << "- INS MISS COST      = " << (float)m_cost_ins_miss_frz/m_cpt_ins_miss << std::endl;
+    std::cout << "- IMISS TRANSACTION  = " << (float)m_cost_imiss_transaction/m_cpt_imiss_transaction << std::endl;
+    std::cout << "- DMISS COST         = " << (float)m_cost_data_miss_frz/m_cpt_data_miss << std::endl;
+    std::cout << "- DMISS TRANSACTION  = " << (float)m_cost_dmiss_transaction/m_cpt_dmiss_transaction << std::endl;
+    std::cout << "- UNC COST           = " << (float)m_cost_unc_read_frz/m_cpt_unc_read << std::endl;
+    std::cout << "- UNC TRANSACTION    = " << (float)m_cost_unc_transaction/m_cpt_unc_transaction << std::endl;
+    std::cout << "- WRITE COST         = " << (float)m_cost_write_frz/m_cpt_write << std::endl;
+    std::cout << "- WRITE TRANSACTION  = " << (float)m_cost_write_transaction/m_cpt_write_transaction << std::endl;
+    std::cout << "- WRITE LENGTH       = " << (float)m_length_write_transaction/m_cpt_write_transaction << std::endl;
+}
+
+//////////////////////////
+tmpl(void)::transition()
+           //////////////////////////
+{
+    if ( ! p_resetn.read() ) {
+
+        m_iss.reset();
+
+        // FSM states
+        r_dcache_fsm = DCACHE_IDLE;
+        r_icache_fsm = ICACHE_IDLE;
+        r_vci_cmd_fsm = CMD_IDLE;
+        r_vci_rsp_fsm = RSP_IDLE;
+        r_vci_tgt_fsm = TGT_IDLE;
+
+        // write buffer & caches
+        r_wbuf.reset();
+        r_icache.reset();
+        r_dcache.reset();
+
+        // synchronisation flip-flops from ICACHE & DCACHE FSMs to VCI  FSMs
+        r_icache_miss_req    = false;
+        r_icache_unc_req     = false;
+        r_icache_cleanup_req = false;
+        r_dcache_miss_req    = false;
+        r_dcache_unc_req     = false;
+        r_dcache_write_req   = false;
+        r_dcache_cleanup_req = false;
+
+        // synchronisation flip-flops from TGT FSM to ICACHE & DCACHE FSMs
+        r_tgt_icache_req     = false;
+        r_tgt_dcache_req     = false;
+
+        // internal messages in DCACHE et ICACHE FSMs
+        r_icache_inval_rsp   = false;
+        r_dcache_inval_rsp   = false;
+
+        // error signals from the VCI RSP FSM to the ICACHE or DCACHE FSMs
+        r_dcache_buf_unc_valid = false;
+        r_icache_buf_unc_valid = false;
+        r_vci_rsp_data_error   = false;
+        r_vci_rsp_ins_error    = false;
+
+        // activity counters
+        m_cpt_dcache_data_read  = 0;
+        m_cpt_dcache_data_write = 0;
+        m_cpt_dcache_dir_read  = 0;
+        m_cpt_dcache_dir_write = 0;
+        m_cpt_icache_data_read  = 0;
+        m_cpt_icache_data_write = 0;
+        m_cpt_icache_dir_read  = 0;
+        m_cpt_icache_dir_write = 0;
+
+        m_cpt_cc_update = 0;
+        m_cpt_cc_inval = 0;
+
+        m_cpt_frz_cycles = 0;
+        m_cpt_total_cycles = 0;
+
+        m_cpt_read = 0;
+        m_cpt_write = 0;
+        m_cpt_data_miss = 0;
+        m_cpt_ins_miss = 0;
+        m_cpt_unc_read = 0;
+        m_cpt_write_cached = 0;
+
+        m_cost_write_frz = 0;
+        m_cost_data_miss_frz = 0;
+        m_cost_unc_read_frz = 0;
+        m_cost_ins_miss_frz = 0;
+
+        m_cpt_imiss_transaction = 0;
+        m_cpt_dmiss_transaction = 0;
+        m_cpt_unc_transaction = 0;
+        m_cpt_write_transaction = 0;
+
+        m_cost_imiss_transaction = 0;
+        m_cost_dmiss_transaction = 0;
+        m_cost_unc_transaction = 0;
+        m_cost_write_transaction = 0;
+        m_length_write_transaction = 0;
+
+        return;
+    }
+
+#if DEBUG_CC_XCACHE_WRAPPER
+    std::cout << "--------------------------------------------" << std::endl;
+    std::cout << std::dec << "CC_XCACHE_WRAPPER " << m_srcid << " / Time = " << m_cpt_total_cycles << std::endl;
+    std::cout             << " tgt fsm    = " << tgt_fsm_state_str[r_vci_tgt_fsm] << std::endl
+                          << " dcache fsm = " << dcache_fsm_state_str[r_dcache_fsm] << std::endl
+                          << " icache fsm = " << icache_fsm_state_str[r_icache_fsm] << std::endl
+                          << " cmd fsm    = " << cmd_fsm_state_str[r_vci_cmd_fsm] << std::endl
+                          << " rsp fsm    = " << rsp_fsm_state_str[r_vci_rsp_fsm] << std::endl;
+#endif
+
+    m_cpt_total_cycles++;
+
+    /////////////////////////////////////////////////////////////////////
+    // The TGT_FSM controls the following ressources:
+    // - r_vci_tgt_fsm
+    // - r_tgt_buf[nwords]
+    // - r_tgt_val[nwords]
+    // - r_tgt_update
+    // - r_tgt_word
+    // - r_tgt_addr
+    // - r_tgt_srcid
+    // - r_tgt_trdid
+    // - r_tgt_pktid
+    // All VCI commands must be CMD_WRITE.
+    // If the VCI address offset is null, the command is an invalidate 
+    // request. It is an update request otherwise.
+    // The VCI_TGT FSM stores the external request arguments in the
+    // IDLE, UPDT_WORD & UPDT_DATA states. It sets the r_tgt_icache_req 
+    // & r_tgt_dcache_req flip-flops to signal the external request to 
+    // the ICACHE & DCACHE FSMs in the REQ state. It waits the completion
+    // of the update or invalidate request in the RSP state.
+    // -  for an invalidate request the VCI packet length is 1 word.
+    // The WDATA field contains the line index (i.e. the Z & Y fields).
+    // -  for an update request the VCI packet length is (n+2) words.
+    // The WDATA field of the first VCI word contains the line number.
+    // The WDATA field of the second VCI word contains the word index.
+    // The WDATA field of the n following words contains the values.
+    // -  for both invalidate & update requests, the VCI response
+    // is one single word.
+    // In case of errors in the VCI command packet, the simulation
+    // is stopped with an error message.
+    /////////////////////////////////////////////////////////////////////
+    
+    switch(r_vci_tgt_fsm) {
+
+    case TGT_IDLE:
+        if ( p_vci_tgt.cmdval.read() ) 
+        {
+            addr_t address = p_vci_tgt.address.read();
+
+            if ( p_vci_tgt.cmd.read() != vci_param::CMD_WRITE) 
+            {
+                std::cout << "error in component VCI_CC_XCACHE_WRAPPER " << name() << std::endl;
+                std::cout << "the received VCI command is not a write" << std::endl;
+                exit(0);
+            }
+
+            // multi-update or multi-invalidate for data type
+            if ( (address != 0x3) && (! m_segment.contains(address)) ) 
+            {
+                std::cout << "error in component VCI_CC_XCACHE_WRAPPER " << name() << std::endl;
+                std::cout << "out of segment VCI command received for a multi-updt or multi-inval request" << std::endl;
+                exit(0);
+            }
+
+            r_tgt_srcid = p_vci_tgt.srcid.read();
+            r_tgt_trdid = p_vci_tgt.trdid.read();
+            r_tgt_pktid = p_vci_tgt.pktid.read();
+            r_tgt_plen  = p_vci_tgt.plen.read();    // todo: wait L2 modification
+            r_tgt_addr = (addr_t)p_vci_tgt.wdata.read() * m_dcache_words * 4;
+            
+            if ( address == 0x3 )   // broadcast invalidate for data or instruction type
+            {
+                if ( ! p_vci_tgt.eop.read() ) 
+                {
+                    std::cout << "error in component VCI_CC_XCACHE_WRAPPER " << name() << std::endl;
+                    std::cout << "the BROADCAST INVALIDATE command length must be one word" << std::endl;
+                    exit(0);
+                }
+                r_tgt_update = false; 
+                r_vci_tgt_fsm = TGT_REQ_BROADCAST;
+                m_cpt_cc_inval++ ;
+            }
+            else                    // multi-update or multi-invalidate for data type
+            { 
+                addr_t cell = address - m_segment.baseAddress();
+                if (cell == 0) 
+                {                               // invalidate 
+                    if ( ! p_vci_tgt.eop.read() ) 
+                    {
+                        std::cout << "error in component VCI_CC_XCACHE_WRAPPER " << name() << std::endl;
+                        std::cout << "the MULTI-INVALIDATE command length must be one word" << std::endl;
+                        exit(0);
+                    }
+                    r_tgt_update = false; 
+                    r_vci_tgt_fsm = TGT_REQ_DCACHE;
+                    m_cpt_cc_inval++ ;
+                } 
+                else 
+                {                                // update
+                    if ( p_vci_tgt.eop.read() ) 
+                    {
+                        std::cout << "error in component VCI_CC_XCACHE_WRAPPER " << name() << std::endl;
+                        std::cout << "the MULTI-UPDATE command length must be N+2 words" << std::endl;
+                        exit(0);
+                    }
+                    r_tgt_update = true; 
+                    r_vci_tgt_fsm = TGT_UPDT_WORD;
+                    m_cpt_cc_update++ ;
+                }
+            } // end if address
+        } // end if cmdval
+        break;
+
+    case TGT_UPDT_WORD:
+        if (p_vci_tgt.cmdval.read()) 
+        {
+            if ( p_vci_tgt.eop.read() ) 
+            {
+                std::cout << "error in component VCI_CC_XCACHE_WRAPPER " << name() << std::endl;
+                std::cout << "the MULTI-UPDATE command length must be N+2 words" << std::endl;
+                exit(0);
+            }
+            for ( size_t i=0 ; i<m_dcache_words ; i++ ) r_tgt_val[i] = false;
+            r_tgt_word = p_vci_tgt.wdata.read(); // the first modified word index
+            r_vci_tgt_fsm = TGT_UPDT_DATA;
+        }
+        break;
+
+    case TGT_UPDT_DATA:
+        if (p_vci_tgt.cmdval.read()) 
+        {
+            size_t word = r_tgt_word.read();
+            if ( word >= m_dcache_words ) 
+            {
+                std::cout << "error in component VCI_CC_XCACHE_WRAPPER " << name() << std::endl;
+                std::cout << "the reveived MULTI-UPDATE command length is wrong" << std::endl;
+                exit(0);
+            }
+            r_tgt_buf[word] = p_vci_tgt.wdata.read();
+            if(p_vci_tgt.be.read())    r_tgt_val[word] = true;
+            r_tgt_word = word + 1;
+            if (p_vci_tgt.eop.read())  r_vci_tgt_fsm = TGT_REQ_DCACHE;
+        }
+        break;
+
+    case TGT_REQ_BROADCAST:
+        if ( !r_tgt_icache_req.read() && !r_tgt_dcache_req.read() ) 
+        {
+            r_vci_tgt_fsm = TGT_RSP_BROADCAST; 
+            r_tgt_icache_req = true;
+            r_tgt_dcache_req = true;
+        }
+        break;
+
+    case TGT_REQ_DCACHE:
+        if ( !r_tgt_dcache_req.read() ) 
+        {
+            r_vci_tgt_fsm = TGT_RSP_DCACHE; 
+            r_tgt_dcache_req = true;
+        }
+        break;
+
+    case TGT_RSP_BROADCAST:
+        if ( p_vci_tgt.rspack.read() && !r_tgt_icache_req.read() && !r_tgt_dcache_req.read() ) 
+        {
+            // one response
+            if ( !r_tgt_icache_rsp || !r_tgt_dcache_rsp )
+            {
+                r_vci_tgt_fsm = TGT_IDLE; 
+                r_tgt_icache_rsp = false;
+                r_tgt_dcache_rsp = false;
+            }
+
+            // if data and instruction have the inval line, need two responses  
+            if ( r_tgt_icache_rsp && r_tgt_dcache_rsp )
+            {
+                r_tgt_icache_rsp = false; // only reset one for respond the second time 
+            }
+        }
+        break;
+
+    case TGT_RSP_DCACHE:
+        if ( p_vci_tgt.rspack.read() && !r_tgt_dcache_req.read() ) 
+        {
+            r_vci_tgt_fsm = TGT_IDLE;
+            r_tgt_dcache_rsp = false; 
+        }
+        break;
+
+    } // end switch TGT_FSM
+
+    /////////////////////////////////////////////////////////////////////
+    // The ICACHE FSM controls the following ressources:
+    // - r_icache_fsm
+    // - r_icache_fsm_save
+    // - r_icache instruction cache access
+    // - r_icache_addr_save
+    // - r_icache_miss_req set
+    // - r_icache_unc_req set
+    // - r_icache_buf_unc_valid set
+    // - r_vci_rsp_ins_error reset
+    // - r_tgt_icache_req reset
+    // - ireq & irsp structures for communication with the processor
+    //
+    // 1/ External requests (update or invalidate) have highest priority.
+    //    They are taken into account in the IDLE and WAIT states.
+    //    As external hit should be extremly rare on the ICACHE,
+    //    all external requests are handled as invalidate...
+    //    In case of external request the ICACHE FSM goes to the CC_CHECK
+    //    state to test the external hit, and returns in the
+    //    pre-empted state after completion.
+    // 2/ Processor requests are taken into account only in the IDLE state.
+    //    In case of MISS, or in case of uncached instruction, the FSM 
+    //    writes the missing address line in the  r_icache_addr_save register 
+    //    and sets the r_icache_miss_req or the r_icache_unc_req flip-flops.
+    //    These request flip-flops are reset by the VCI_RSP FSM
+    //    when the VCI transaction is completed and the r_icache_buf_unc_valid
+    //    is set in case of uncached access.
+    //    In case of bus error, the VCI_RSP FSM sets the r_vci_rsp_ins_error 
+    //    flip-flop. It is reset by the ICACHE FSM.
+    ///////////////////////////////////////////////////////////////////////
+
+    typename iss_t::InstructionRequest  ireq = ISS_IREQ_INITIALIZER;
+    typename iss_t::InstructionResponse irsp = ISS_IRSP_INITIALIZER;
+
+    typename iss_t::DataRequest  dreq = ISS_DREQ_INITIALIZER;
+    typename iss_t::DataResponse drsp = ISS_DRSP_INITIALIZER;
+
+    m_iss.getRequests( ireq, dreq );
+
+#if DEBUG_CC_XCACHE_WRAPPER
+    std::cout << " Instruction Request: " << ireq << std::endl;
+#endif
+
+    switch(r_icache_fsm) {
+        /////////////////
+    case ICACHE_IDLE:
+        {
+            if ( r_tgt_icache_req ) {   // external request
+                if ( ireq.valid ) m_cost_ins_miss_frz++;
+                r_icache_fsm = ICACHE_CC_INVAL;
+                r_icache_fsm_save = r_icache_fsm;
+                break;
+            } 
+            if ( ireq.valid ) {
+                data_t  icache_ins = 0;
+                bool    icache_hit = false;
+                bool    icache_cached = m_cacheability_table[ireq.addr];
+                // icache_hit & icache_ins evaluation
+                if ( icache_cached ) {
+                    icache_hit = r_icache.read(ireq.addr, &icache_ins);
+                } else {
+                    icache_hit = ( r_icache_buf_unc_valid && (ireq.addr == r_icache_addr_save) );
+                    icache_ins = r_icache_miss_buf[0];
+                }
+                if ( ! icache_hit ) {
+                    m_cpt_ins_miss++;
+                    m_cost_ins_miss_frz++;
+                    r_icache_addr_save = ireq.addr;
+                    if ( icache_cached ) {
+                        r_icache_fsm = ICACHE_MISS_WAIT;
+                        r_icache_miss_req = true;
+                    } else {
+                        r_icache_fsm = ICACHE_UNC_WAIT;
+                        r_icache_unc_req = true;
+                    }
+                } else {
+                    r_icache_buf_unc_valid = false;
+                }
+                m_cpt_icache_dir_read += m_icache_ways;
+                m_cpt_icache_data_read += m_icache_ways;
+                irsp.valid          = icache_hit;
+                irsp.instruction    = icache_ins;
+            }
+            break;
+        }
+        //////////////////////
+    case ICACHE_MISS_WAIT:
+        {
+            m_cost_ins_miss_frz++;
+            if ( r_tgt_icache_req ) {   // external request
+                r_icache_fsm = ICACHE_CC_INVAL;
+                r_icache_fsm_save = r_icache_fsm;
+                break;
+            } 
+            if ( !r_icache_miss_req && !r_icache_inval_rsp ) { // Miss read response and no invalidation
+                if ( r_vci_rsp_ins_error ) {
+                    r_icache_fsm = ICACHE_ERROR;
+                } else {
+                    r_icache_fsm = ICACHE_MISS_UPDT;
+                }
+            }
+            if ( !r_icache_miss_req && r_icache_inval_rsp ) { // Miss read response and invalidation
+                if ( r_vci_rsp_ins_error ) {
+                    r_icache_inval_rsp = false;
+                    r_icache_fsm = ICACHE_ERROR;
+                } else {
+                    r_icache_inval_rsp = false;
+                    r_icache_fsm = ICACHE_IDLE;
+                }
+            }
+            break;
+        }
+        /////////////////////
+    case ICACHE_UNC_WAIT:
+        {
+            m_cost_ins_miss_frz++;
+            if ( r_tgt_icache_req ) {   // external request
+                r_icache_fsm = ICACHE_CC_INVAL;
+                r_icache_fsm_save = r_icache_fsm;
+                break;
+            } 
+            if ( !r_icache_unc_req ) {
+                if ( r_vci_rsp_ins_error ) {
+                    r_icache_fsm = ICACHE_ERROR;
+                } else {
+                    r_icache_fsm = ICACHE_IDLE;
+                    r_icache_buf_unc_valid = true;
+                }
+            }
+            break;
+        }
+        //////////////////
+    case ICACHE_ERROR:
+        {
+            r_icache_fsm = ICACHE_IDLE;
+            r_vci_rsp_ins_error = false;
+            irsp.error          = true;
+            irsp.valid          = true;
+            break;
+        }
+        //////////////////////
+    case ICACHE_MISS_UPDT: 
+        {
+            if ( r_tgt_icache_req ) {   // external request
+                r_icache_fsm = ICACHE_CC_INVAL;
+                r_icache_fsm_save = r_icache_fsm;
+                break;
+            } 
+            if(!r_icache_cleanup_req.read() && !r_icache_inval_rsp){
+                addr_t    ad  = r_icache_addr_save;
+                data_t*   buf = r_icache_miss_buf;
+                data_t    victim_index = 0;
+                m_cpt_icache_dir_write++;
+                m_cpt_icache_data_write++;
+                if ( ireq.valid ) m_cost_ins_miss_frz++;
+
+                r_icache_cleanup_req = r_icache.update(ad, buf, &victim_index);
+                r_icache_cleanup_line = victim_index;
+
+                r_icache_fsm        = ICACHE_IDLE;
+                break;
+            }
+            if(r_icache_inval_rsp){
+                if ( ireq.valid ) m_cost_ins_miss_frz++;
+                r_icache_inval_rsp  = false;
+                r_icache_fsm        = ICACHE_IDLE;
+                break;
+            }
+            if ( ireq.valid ) m_cost_ins_miss_frz++;
+        }
+        /////////////////////
+    case ICACHE_CC_INVAL:  
+        {                       
+            addr_t    ad  = r_tgt_addr;
+            if ( ireq.valid ) m_cost_ins_miss_frz++;
+            m_cpt_icache_dir_read += m_icache_ways;
+            if( (( r_icache_fsm_save == ICACHE_MISS_WAIT ) || ( r_icache_fsm_save == ICACHE_MISS_UPDT )) && 
+                ((r_icache_addr_save.read() & ~((m_icache_words<<2)-1)) == (ad & ~((m_icache_words<<2)-1))) ) {
+                r_icache_inval_rsp = true;
+            } else {
+                r_tgt_icache_rsp = r_icache.inval(ad);
+            }
+            r_tgt_icache_req = false;
+            r_icache_fsm = r_icache_fsm_save;
+            break;
+        }
+
+    } // end switch r_icache_fsm
+
+#if DEBUG_CC_XCACHE_WRAPPER
+    std::cout << " Instruction Response: " << irsp << std::endl;
+#endif
+
+    //////////////////////////////////////////////////////////////////////://///////////
+    // The DCACHE FSM controls the following ressources:
+    // - r_dcache_fsm
+    // - r_dcache_fsm_save
+    // - r_dcache (data cache access)
+    // - r_dcache_addr_save
+    // - r_dcache_wdata_save
+    // - r_dcache_rdata_save
+    // - r_dcache_type_save
+    // - r_dcache_be_save
+    // - r_dcache_cached_save
+    // - r_dcache_miss_req set
+    // - r_dcache_unc_req set
+    // - r_dcache_write_req set
+    // - r_dcache_cleanup_req set
+    // - r_vci_rsp_data_error reset
+    // - r_tgt_dcache_req reset
+    // - r_wbuf write
+    // - dreq & drsp structures for communication with the processor
+    //
+    // 1/ EXTERNAL REQUEST : 
+    //    There is an external request when the tgt_dcache req flip-flop is set,
+    //    requesting a line invalidation or a line update. 
+    //    External requests are taken into account in the states  IDLE, WRITE_REQ,  
+    //    UNC_WAIT, MISS_WAIT, and have the highest priority :
+    //    The actions associated to the pre-empted state are not executed, the DCACHE FSM
+    //    goes to the CC_CHECK state to execute the requested action, and returns to the
+    //    pre-empted state.
+    //  2/ PROCESSOR REQUEST : 
+    //   In order to support VCI write burst, the processor requests are taken into account
+    //   in the WRITE_REQ state as well as in the IDLE state.
+    //   - In the IDLE state, the processor request cannot be satisfied if
+    //   there is a cached read miss, or an uncached read.
+    //   - In the WRITE_REQ state, the request cannot be satisfied if
+    //   there is a cached read miss, or an uncached read,
+    //   or when the write buffer is full.
+    //   - In all other states, the processor request is not satisfied.
+    //
+    //   The cache access takes into account the cacheability_table.
+    //   In case of processor request, there is five conditions to exit the IDLE state:
+    //   - CACHED READ MISS => to the MISS_WAIT state (waiting the r_miss_ok signal), 
+    //     then to the MISS_UPDT state, and finally to the IDLE state.
+    //   - UNCACHED READ  => to the UNC_WAIT state (waiting the r_miss_ok signal), 
+    //     and to the IDLE state.
+    //   - CACHE INVALIDATE HIT => to the INVAL state for one cycle, then to IDLE state.
+    //   - WRITE MISS => directly to the WRITE_REQ state to access the write buffer.
+    //   - WRITE HIT => to the WRITE_UPDT state, then to the WRITE_REQ state.
+    //
+    // Error handling :  Read Bus Errors are synchronous events, but
+    // Write Bus Errors are asynchronous events (processor is not frozen).
+    // - If a Read Bus Error is detected, the VCI_RSP FSM sets the
+    //   r_vci_rsp_data_error flip-flop, and the synchronous error is signaled
+    //   by the DCACHE FSM.
+    // - If a Write Bus Error is detected, the VCI_RSP FSM  signals
+    //   the asynchronous error using the setWriteBerr() method.
+    ///////////////////////////////////////////////////////////////////////////////////
+
+#if DEBUG_CC_XCACHE_WRAPPER
+    std::cout << " Data Request: " << dreq << std::endl;
+#endif
+
+    //if( (m_cpt_total_cycles % 10000) ==0 ) std::cout << std::dec << "Proc " << m_srcid << " Data Request: " << dreq << std::endl;
+
+    switch ( r_dcache_fsm ) {
+
+        /////////////////////
+    case DCACHE_WRITE_REQ:
+        { 
+            if ( r_tgt_dcache_req ) {   // external request
+                r_dcache_fsm = DCACHE_CC_CHECK;
+                r_dcache_fsm_save = r_dcache_fsm;
+                break;
+            }
+
+            // try to post the write request in the write buffer
+            if ( !r_dcache_write_req ) {    // no previous write transaction     
+                if ( r_wbuf.wok(r_dcache_addr_save) ) {   // write request in the same cache line 
+                    r_wbuf.write(r_dcache_addr_save, r_dcache_be_save, r_dcache_wdata_save);
+                    // close the write packet if uncached
+                    if ( !r_dcache_cached_save ) r_dcache_write_req = true ;
+                } else {    
+                    // close the write packet if write request not in the same cache line
+                    r_dcache_write_req = true;  
+                    m_cost_write_frz++;
+                    break;  // posting request not possible : stay in DCACHE_WRITEREQ state
+                }
+            } else {    //  previous write transaction not completed
+                m_cost_write_frz++;
+                break;  // posting request not possible : stay in DCACHE_WRITEREQ state  
+            }
+
+            // close the write packet if the next processor request is not a write 
+            if ( !dreq.valid || (dreq.type != iss_t::DATA_WRITE) ) r_dcache_write_req = true ;
+
+            // The next state and the processor request parameters are computed 
+            // as in the DCACHE_IDLE state (see below ...)
+        }
+        /////////////////
+    case DCACHE_IDLE:
+        {
+            if ( r_tgt_dcache_req ) {   // external request
+                r_dcache_fsm = DCACHE_CC_CHECK;
+                r_dcache_fsm_save = r_dcache_fsm;
+                break;
+            } 
+
+            if ( dreq.valid ) {              
+                bool        dcache_hit     = false;
+                data_t      dcache_rdata   = 0;
+                bool        dcache_cached;
+                m_cpt_dcache_data_read += m_dcache_ways;
+                m_cpt_dcache_dir_read += m_dcache_ways;
+
+                // dcache_cached evaluation
+                switch (dreq.type) {
+                case iss_t::DATA_LL:
+                case iss_t::DATA_SC:
+                case iss_t::XTN_READ:
+                case iss_t::XTN_WRITE:
+                    dcache_cached = false;
+                    break;
+                default:
+                    dcache_cached = m_cacheability_table[dreq.addr];
+                }
+
+                // dcache_hit & dcache_rdata evaluation
+                if ( dcache_cached ) {
+                    dcache_hit = r_dcache.read(dreq.addr, &dcache_rdata);
+                } else {
+                    dcache_hit = ( !r_dcache_unc_req && (dreq.addr == r_dcache_addr_save) );
+                    dcache_rdata = r_dcache_miss_buf[0];
+                }
+
+                switch( dreq.type ) {
+                case iss_t::DATA_READ:
+                case iss_t::DATA_LL:
+                case iss_t::DATA_SC:
+                    m_cpt_read++;
+                    if ( dcache_hit ) {
+                        r_dcache_fsm = DCACHE_IDLE;
+                        drsp.valid = true;
+                        drsp.rdata = dcache_rdata;
+                        r_dcache_buf_unc_valid = false;
+                    } else {
+                        if ( dcache_cached ) {
+                            m_cpt_data_miss++;
+                            m_cost_data_miss_frz++;
+                            r_dcache_miss_req = true;
+                            r_dcache_fsm = DCACHE_MISS_WAIT;
+                        } else {
+                            m_cpt_unc_read++;
+                            m_cost_unc_read_frz++;
+                            r_dcache_unc_req = true;
+                            r_dcache_fsm = DCACHE_UNC_WAIT;
+                        }
+                    }
+                    break;
+                case iss_t::XTN_READ:
+                case iss_t::XTN_WRITE:
+                    // only DCACHE INVALIDATE request are supported
+                    if ( dreq.addr/4 == iss_t::XTN_DCACHE_INVAL )
+                        r_dcache_fsm = DCACHE_INVAL;
+                    drsp.valid = true;
+                    drsp.rdata = 0;
+                    break;
+                case iss_t::DATA_WRITE:
+                    m_cpt_write++;
+                    if ( dcache_hit && dcache_cached ) {
+                        r_dcache_fsm = DCACHE_WRITE_UPDT;
+                        m_cpt_write_cached++;
+                    } else {
+                        r_dcache_fsm = DCACHE_WRITE_REQ;
+                    }
+                    drsp.valid = true;
+                    drsp.rdata = 0;
+                    break;
+                } // end switch dreq.type
+
+                r_dcache_addr_save      = dreq.addr;
+                r_dcache_type_save      = dreq.type;
+                r_dcache_wdata_save     = dreq.wdata;
+                r_dcache_be_save        = dreq.be;
+                r_dcache_rdata_save     = dcache_rdata;
+                r_dcache_cached_save    = dcache_cached;
+
+            } else {    // end if dreq.valid
+                r_dcache_fsm = DCACHE_IDLE;
+            }
+            // processor request are not accepted in the WRITE_REQUEST state
+            // when the write buffer is not writeable
+            if ( (r_dcache_fsm == DCACHE_WRITE_REQ) &&
+                 (r_dcache_write_req || !r_wbuf.wok(r_dcache_addr_save)) ) {
+                drsp.valid = false;
+                drsp.rdata = 0;
+            }
+            break;
+        }
+        ///////////////////////
+    case DCACHE_WRITE_UPDT:
+        {
+            m_cpt_dcache_data_write++;
+            data_t mask = vci_param::be2mask(r_dcache_be_save);
+            data_t wdata = (mask & r_dcache_wdata_save) | (~mask & r_dcache_rdata_save);
+            r_dcache.write(r_dcache_addr_save, wdata);
+            r_dcache_fsm = DCACHE_WRITE_REQ;
+            break;
+        }
+        //////////////////////
+    case DCACHE_MISS_WAIT:
+        {
+            if ( dreq.valid ) m_cost_data_miss_frz++;
+            if ( r_tgt_dcache_req.read() ) {   // external request
+                r_dcache_fsm = DCACHE_CC_CHECK;
+                r_dcache_fsm_save = r_dcache_fsm;
+                break;
+            }
+            if ( !r_dcache_miss_req && !r_dcache_inval_rsp ) { // Miss read response and no invalidation
+                if ( r_vci_rsp_data_error ) {
+                    r_dcache_fsm = DCACHE_ERROR;
+                } else {
+                    r_dcache_fsm = DCACHE_MISS_UPDT;
+                }
+                break;
+            }
+            if ( !r_dcache_miss_req && r_dcache_inval_rsp ) { // Miss read response and invalidation
+                if ( r_vci_rsp_data_error ) {
+                    r_dcache_inval_rsp  = false;
+                    r_dcache_fsm = DCACHE_ERROR;
+                } else {
+                    r_dcache_inval_rsp  = false;
+                    r_dcache_fsm = DCACHE_IDLE;
+                }
+                break;
+            }
+            break;
+        }
+        //////////////////////
+    case DCACHE_MISS_UPDT:
+        {
+            if ( r_tgt_dcache_req.read() ) {   // external request
+                r_dcache_fsm = DCACHE_CC_CHECK;
+                r_dcache_fsm_save = r_dcache_fsm;
+                break;
+            }
+            if( !r_dcache_cleanup_req.read() && !r_dcache_inval_rsp ){
+                addr_t  ad  = r_dcache_addr_save;
+                data_t* buf = new data_t[m_dcache_words];
+                for(size_t i=0; i<m_dcache_words; i++) {
+                    buf[i] = r_dcache_miss_buf[i];
+                }
+                data_t  victim_index = 0;
+                if ( dreq.valid ) m_cost_data_miss_frz++;
+                m_cpt_dcache_data_write++;
+                m_cpt_dcache_dir_write++;
+
+                r_dcache_cleanup_req = r_dcache.update(ad, buf, &victim_index);
+                r_dcache_cleanup_line = victim_index;
+            
+                r_dcache_fsm = DCACHE_IDLE;
+                delete [] buf;
+                break;
+            }
+            if( r_dcache_inval_rsp ){
+                r_dcache_inval_rsp  = false;
+                r_dcache_fsm = DCACHE_IDLE;
+                break;
+            }
+            break;
+        }
+        ////////////////////
+    case DCACHE_UNC_WAIT:
+        {
+            if ( dreq.valid ) m_cost_unc_read_frz++;
+            if ( r_tgt_dcache_req ) {   // external request
+                r_dcache_fsm = DCACHE_CC_CHECK;
+                r_dcache_fsm_save = r_dcache_fsm;
+                break;
+            } 
+            if ( !r_dcache_unc_req ) {
+                if ( r_vci_rsp_data_error ) {
+                    r_dcache_fsm = DCACHE_ERROR;
+                } else {
+                    r_dcache_fsm = DCACHE_IDLE;
+	                // If request was a DATA_SC we need to invalidate the corresponding cache line,
+	                // so that subsequent access to this line are read from RAM
+	                if (dreq.type == iss_t::DATA_SC) {
+	                    r_dcache_fsm = DCACHE_INVAL;
+	                    r_dcache_wdata_save = r_dcache_addr_save;
+	                }
+                    r_dcache_buf_unc_valid = true;
+                }
+            }
+            break;
+        }
+        //////////////////
+    case DCACHE_ERROR:
+        {
+            r_dcache_fsm = DCACHE_IDLE;
+            r_vci_rsp_data_error = false;
+            drsp.error = true;
+            drsp.valid = true;
+            break;
+        }
+        /////////////////    
+    case DCACHE_INVAL:
+        {
+            m_cpt_dcache_dir_read += m_dcache_ways;
+            r_dcache.inval(r_dcache_addr_save);
+            r_dcache_fsm = DCACHE_IDLE;
+            break;
+        }
+        /////////////////////
+    case DCACHE_CC_CHECK:   // read directory in case of invalidate or update request
+        {
+            m_cpt_dcache_dir_read += m_dcache_ways;
+            m_cpt_dcache_data_read += m_dcache_ways;
+            addr_t  ad           = r_tgt_addr;
+            data_t  dcache_rdata = 0;
+
+            if(( ( r_dcache_fsm_save == DCACHE_MISS_WAIT ) || ( r_dcache_fsm_save == DCACHE_MISS_UPDT ) ) && 
+               ( (r_dcache_addr_save.read() & ~((m_dcache_words<<2)-1)) == (ad & ~((m_dcache_words<<2)-1)))) {
+                r_dcache_inval_rsp = true;
+                r_tgt_dcache_req = false;
+                r_dcache_fsm = r_dcache_fsm_save;
+            } else {
+                bool    dcache_hit   = r_dcache.read(ad, &dcache_rdata);
+                if ( dcache_hit && r_tgt_update ) {
+                    r_dcache_fsm = DCACHE_CC_UPDT;
+                    // complete the line buffer in case of update
+                    for ( size_t word = 0 ; word < m_dcache_words ; word++ ) {
+                        if ( !r_tgt_val[word] ) {
+                            addr_t  ad = r_tgt_addr + (addr_t)word;
+                            r_dcache.read(ad, &dcache_rdata);
+                            r_tgt_buf[word] = dcache_rdata;
+                        }
+                    }
+                } else if ( dcache_hit && !r_tgt_update ) {
+                    r_dcache_fsm = DCACHE_CC_INVAL;
+                } else {
+                    r_dcache_fsm = DCACHE_CC_NOP;
+                }
+            }
+            break;
+        }
+        ///////////////////
+    case DCACHE_CC_UPDT:    // update directory and data cache        
+        {
+            m_cpt_dcache_dir_write++;
+            m_cpt_dcache_data_write++;
+            addr_t  ad      = r_tgt_addr;
+            data_t* buf     = r_tgt_buf;
+            for(size_t i=0; i<m_dcache_words; i++){
+                if(r_tgt_val[i]) r_dcache.write( ad + i*4, buf[i]);
+            }
+            r_tgt_dcache_req = false;
+            r_dcache_fsm = r_dcache_fsm_save;
+            break;
+        }
+        /////////////////////
+    case DCACHE_CC_INVAL:   // invalidate a cache line
+        {
+            addr_t  ad      = r_tgt_addr;
+            r_tgt_dcache_rsp = r_dcache.inval(ad);
+            r_tgt_dcache_req = false;
+            r_dcache_fsm = r_dcache_fsm_save;
+            break;
+        }
+        ///////////////////
+    case DCACHE_CC_NOP:     // no external hit
+        {
+            r_tgt_dcache_req = false;
+            r_dcache_fsm = r_dcache_fsm_save;
+            break;
+        }    
+    } // end switch r_dcache_fsm
+
+#if DEBUG_CC_XCACHE_WRAPPER
+    std::cout << " Data Response: " << drsp << std::endl;
+#endif
+
+    /////////// execute one iss cycle /////////////////////////////////////////////
+    {
+        uint32_t it = 0;
+        for (size_t i=0; i<(size_t)iss_t::n_irq; i++) 
+            if(p_irq[i].read()) it |= (1<<i);
+        m_iss.executeNCycles(1, irsp, drsp, it);
+    }
+
+    if ( (ireq.valid && !irsp.valid) || (dreq.valid && !drsp.valid) ) m_cpt_frz_cycles++;
+    
+
+    ////////////////////////////////////////////////////////////////////////////
+    // The VCI_CMD FSM controls the following ressources:
+    // - r_vci_cmd_fsm
+    // - r_vci_cmd_min
+    // - r_vci_cmd_max
+    // - r_vci_cmd_cpt
+    // - wbuf reset
+    //
+    // This FSM handles requests from both the DCACHE FSM & the ICACHE FSM.
+    // There is 7 request types, with the following priorities : 
+    // 1 - Instruction Miss     : r_icache_miss_req
+    // 2 - Data Write           : r_dcache_write_req
+    // 3 - Data Read Miss       : r_dcache_miss_req 
+    // 4 - Data Read Uncached   : r_dcache_unc_req 
+    // 5 - Instruction Cleanup  : r_icache_cleanup_req 
+    // 6 - Data Cleanup         : r_dcache_cleanup_req 
+    // There is at most one (CMD/RSP) VCI transaction, as both CMD_FSM 
+    // and RSP_FSM exit simultaneously the IDLE state.
+    //
+    // VCI formats:
+    // According to the VCI advanced specification, all read requests packets 
+    // (read Uncached, Miss data, Miss instruction) are one word packets.
+    // For write burst packets, all words must be in the same cache line,
+    // and addresses must be contiguous (the BE field is 0 in case of "holes").
+    //////////////////////////////////////////////////////////////////////////////
+
+    switch (r_vci_cmd_fsm) {
+    
+    case CMD_IDLE:
+        if (r_vci_rsp_fsm != RSP_IDLE) break;
+
+        r_vci_cmd_cpt = 0;
+        if ( r_icache_miss_req ) { 
+            r_vci_cmd_fsm = CMD_INS_MISS; 
+            m_cpt_imiss_transaction++;
+        } else if ( r_icache_unc_req ) { 
+            r_vci_cmd_fsm = CMD_INS_UNC; 
+            m_cpt_imiss_transaction++;
+        } else if ( r_dcache_write_req ) { 
+            r_vci_cmd_fsm = CMD_DATA_WRITE;
+            r_vci_cmd_cpt = r_wbuf.getMin();
+            r_vci_cmd_min = r_wbuf.getMin();
+            r_vci_cmd_max = r_wbuf.getMax(); 
+            m_cpt_write_transaction++; 
+            m_length_write_transaction += (r_wbuf.getMax() - r_wbuf.getMin() + 1); 
+        } else if ( r_dcache_miss_req ) { 
+            r_vci_cmd_fsm = CMD_DATA_MISS;
+            m_cpt_dmiss_transaction++; 
+        } else if ( r_dcache_unc_req ) { 
+            r_vci_cmd_fsm = CMD_DATA_UNC;
+            m_cpt_unc_transaction++; 
+        } else if ( r_icache_cleanup_req ) { 
+            r_vci_cmd_fsm = CMD_INS_CLEANUP; 
+        } else if ( r_dcache_cleanup_req ) { 
+            r_vci_cmd_fsm = CMD_DATA_CLEANUP;
+        }
+        break;
+            
+    case CMD_DATA_WRITE:
+        if ( p_vci_ini.cmdack.read() ) {
+            r_vci_cmd_cpt = r_vci_cmd_cpt + 1;
+            if (r_vci_cmd_cpt == r_vci_cmd_max) {
+                r_vci_cmd_fsm = CMD_IDLE ;
+                r_wbuf.reset() ;
+            }
+        }
+        break;
+
+    case CMD_INS_MISS:
+    case CMD_INS_UNC:
+    case CMD_DATA_MISS:
+    case CMD_DATA_UNC:
+    case CMD_INS_CLEANUP:
+    case CMD_DATA_CLEANUP:
+        if ( p_vci_ini.cmdack.read() ) {
+            r_vci_cmd_fsm = CMD_IDLE;
+        }
+        break;
+
+    } // end  switch r_vci_cmd_fsm
+
+    //////////////////////////////////////////////////////////////////////////
+    // The VCI_RSP FSM controls the following ressources:
+    // - r_vci_rsp_fsm:
+    // - r_icache_miss_buf[m_icache_words]
+    // - r_dcache_miss_buf[m_dcache_words]
+    // - r_icache_miss_req reset
+    // - r_icache_unc_req reset
+    // - r_dcache_miss_req reset
+    // - r_icache_cleanup_req reset
+    // - r_dcache_cleanup_req reset
+    // - r_vci_rsp_data_error set
+    // - r_vci_rsp_ins_error set
+    // - r_vci_rsp_cpt
+    // In order to have only one active VCI transaction, this VCI_RSP_FSM 
+    // is synchronized with the VCI_CMD FSM, and both FSMs exit the
+    // IDLE state simultaneously.
+    // 
+    // VCI formats:
+    // This component accepts single word or multi-word response packets for
+    // write response packets. 
+    //
+    // Error handling:
+    // This FSM analyzes the VCI error code and signals directly the
+    // Write Bus Error. 
+    // In case of Read Data Error, the VCI_RSP FSM sets the r_vci_rsp_data_error 
+    // flip_flop and the error is signaled by the DCACHE FSM.  
+    // In case of Instruction Error, the VCI_RSP FSM sets the r_vci_rsp_ins_error 
+    // flip_flop and the error is signaled by the DCACHE FSM.  
+    // In case of Cleanup Error, the simulation stops with an error message...
+    //////////////////////////////////////////////////////////////////////////
+
+    switch (r_vci_rsp_fsm) {
+
+    case RSP_IDLE:
+        if(p_vci_ini.rspval.read())
+            {
+                std::cout << "CC_XCache " << m_srcid << " Unexpected response" << std::endl;
+            }
+        assert( ! p_vci_ini.rspval.read() && "Unexpected response" );
+        if (r_vci_cmd_fsm != CMD_IDLE) break;
+
+        r_vci_rsp_cpt = 0;
+        if      ( r_icache_miss_req )       r_vci_rsp_fsm = RSP_INS_MISS;
+        else if ( r_icache_unc_req )        r_vci_rsp_fsm = RSP_DATA_WRITE;
+        else if ( r_dcache_write_req )      r_vci_rsp_fsm = RSP_DATA_WRITE;
+        else if ( r_dcache_miss_req )       r_vci_rsp_fsm = RSP_DATA_MISS;
+        else if ( r_dcache_unc_req )        r_vci_rsp_fsm = RSP_DATA_UNC;
+        else if ( r_icache_cleanup_req )    r_vci_rsp_fsm = RSP_INS_CLEANUP;
+        else if ( r_dcache_cleanup_req )    r_vci_rsp_fsm = RSP_DATA_CLEANUP;
+        break;
+
+    case RSP_INS_MISS:
+        m_cost_imiss_transaction++;
+        if ( ! p_vci_ini.rspval.read() )
+            break;
+        assert( (r_vci_rsp_cpt < m_icache_words) &&
+                "The VCI response packet for instruction miss is too long" );
+        r_vci_rsp_cpt = r_vci_rsp_cpt + 1;
+        r_icache_miss_buf[r_vci_rsp_cpt] = (data_t)p_vci_ini.rdata.read();
+
+        if ( p_vci_ini.reop.read() ) {
+            assert( (r_vci_rsp_cpt == m_icache_words - 1) &&
+                    "The VCI response packet for instruction miss is too short");
+            r_icache_miss_req = false;
+            r_vci_rsp_fsm = RSP_IDLE;
+        }
+        if ( p_vci_ini.rerror.read() != vci_param::ERR_NORMAL ) r_vci_rsp_ins_error = true;
+        break;
+
+    case RSP_INS_UNC:
+        m_cost_imiss_transaction++;
+        if ( ! p_vci_ini.rspval.read() )
+            break;
+        assert(p_vci_ini.reop.read() &&
+               "illegal VCI response packet for uncached instruction");
+        r_icache_miss_buf[0] = (data_t)p_vci_ini.rdata.read();
+        r_vci_rsp_fsm = RSP_IDLE;
+        r_icache_unc_req = false;
+        if ( p_vci_ini.rerror.read() != vci_param::ERR_NORMAL ) r_vci_rsp_ins_error = true;
+        break;
+
+    case RSP_DATA_MISS:
+        m_cost_dmiss_transaction++;
+        if ( ! p_vci_ini.rspval.read() )
+            break;
+        assert(r_vci_rsp_cpt != m_dcache_words &&
+               "illegal VCI response packet for data read miss");
+        r_vci_rsp_cpt = r_vci_rsp_cpt + 1;
+        r_dcache_miss_buf[r_vci_rsp_cpt] = (data_t)p_vci_ini.rdata.read();
+        if ( p_vci_ini.reop.read() ) {
+            assert(r_vci_rsp_cpt == m_dcache_words - 1 &&
+                   "illegal VCI response packet for data read miss");
+            r_dcache_miss_req = false;
+            r_vci_rsp_fsm = RSP_IDLE;
+        }
+        if ( p_vci_ini.rerror.read() != vci_param::ERR_NORMAL ) r_vci_rsp_data_error = true;
+        break;
+
+    case RSP_DATA_WRITE:
+        m_cost_write_transaction++;
+        if ( ! p_vci_ini.rspval.read() )
+            break;
+        if ( p_vci_ini.reop.read() ) {
+            r_vci_rsp_fsm = RSP_IDLE;
+            r_dcache_write_req = false;
+        }
+        if ( p_vci_ini.rerror.read() != vci_param::ERR_NORMAL ) m_iss.setWriteBerr();
+        break;
+
+    case RSP_DATA_UNC:
+        m_cost_unc_transaction++;
+        if ( ! p_vci_ini.rspval.read() )
+            break;
+        assert(p_vci_ini.reop.read() &&
+               "illegal VCI response packet for data read uncached");
+        r_dcache_miss_buf[0] = (data_t)p_vci_ini.rdata.read();
+        r_vci_rsp_fsm = RSP_IDLE;
+        r_dcache_unc_req = false;
+        if ( p_vci_ini.rerror.read() != vci_param::ERR_NORMAL ) r_vci_rsp_data_error = true;
+        break;
+
+    case RSP_INS_CLEANUP:
+    case RSP_DATA_CLEANUP:
+        if ( ! p_vci_ini.rspval.read() )
+            break;
+        assert( p_vci_ini.reop.read() &&
+                "illegal VCI response packet for icache cleanup");
+        assert( (p_vci_ini.rerror.read() == vci_param::ERR_NORMAL) &&
+                "error in response packet for icache cleanup");
+        if ( r_vci_rsp_fsm == RSP_INS_CLEANUP ) r_icache_cleanup_req = false;
+        else                                    r_dcache_cleanup_req = false;
+        r_vci_rsp_fsm = RSP_IDLE;
+        break;
+        
+    } // end switch r_vci_rsp_fsm
+
+} // end transition()
+
+//////////////////////////////////////////////////////////////////////////////////
+tmpl(void)::genMoore()
+           //////////////////////////////////////////////////////////////////////////////////
+{
+    // VCI initiator response
+
+    p_vci_ini.rspack = true;
+
+    // VCI initiator command
+
+    switch (r_vci_cmd_fsm.read() ) {
+
+    case CMD_IDLE:
+        p_vci_ini.cmdval  = false;
+        p_vci_ini.address = 0;
+        p_vci_ini.wdata   = 0;
+        p_vci_ini.be      = 0;
+        p_vci_ini.plen    = 0;
+        p_vci_ini.cmd     = vci_param::CMD_NOP;
+        p_vci_ini.trdid   = 0;
+        p_vci_ini.pktid   = 0;
+        p_vci_ini.srcid   = 0;
+        p_vci_ini.cons    = false;
+        p_vci_ini.wrap    = false;
+        p_vci_ini.contig  = false;
+        p_vci_ini.clen    = 0;
+        p_vci_ini.cfixed  = false;
+        p_vci_ini.eop     = false;
+        break;
+
+    case CMD_DATA_UNC:
+        p_vci_ini.cmdval = true;
+        p_vci_ini.address = r_dcache_addr_save & ~0x3;
+        switch( r_dcache_type_save ) {
+        case iss_t::DATA_READ:
+            p_vci_ini.wdata = 0;
+            p_vci_ini.be  = r_dcache_be_save.read();
+            p_vci_ini.cmd = vci_param::CMD_READ;
+            break;
+        case iss_t::DATA_LL:
+            p_vci_ini.wdata = 0;
+            p_vci_ini.be  = 0xF;
+            p_vci_ini.cmd = vci_param::CMD_LOCKED_READ;
+            break;
+        case iss_t::DATA_SC:
+            p_vci_ini.wdata = r_dcache_wdata_save.read();
+            p_vci_ini.be  = 0xF;
+            p_vci_ini.cmd = vci_param::CMD_STORE_COND;
+            break;
+        default:
+            assert("this should not happen");
+        }
+        p_vci_ini.plen = 4;
+        p_vci_ini.trdid  = 0;   // data cache uncached read
+        p_vci_ini.pktid  = 0;
+        p_vci_ini.srcid  = m_srcid;
+        p_vci_ini.cons   = false;
+        p_vci_ini.wrap   = false;
+        p_vci_ini.contig = true;
+        p_vci_ini.clen   = 0;
+        p_vci_ini.cfixed = false;
+        p_vci_ini.eop    = true;
+        break;
+
+    case CMD_DATA_WRITE:
+        p_vci_ini.cmdval  = true;
+        p_vci_ini.address = r_wbuf.getAddress(r_vci_cmd_cpt);
+        p_vci_ini.wdata   = r_wbuf.getData(r_vci_cmd_cpt);
+        p_vci_ini.be      = r_wbuf.getBe(r_vci_cmd_cpt);
+        p_vci_ini.plen    = (r_vci_cmd_max - r_vci_cmd_min + 1)<<2;
+        p_vci_ini.cmd     = vci_param::CMD_WRITE;
+        p_vci_ini.trdid   = 0;  // data cache write
+        p_vci_ini.pktid   = 0;
+        p_vci_ini.srcid   = m_srcid;
+        p_vci_ini.cons    = false;
+        p_vci_ini.wrap    = false;
+        p_vci_ini.contig  = true;
+        p_vci_ini.clen    = 0;
+        p_vci_ini.cfixed  = false;
+        p_vci_ini.eop     = (r_vci_cmd_cpt == r_vci_cmd_max);
+        break;
+
+    case CMD_DATA_MISS:
+        p_vci_ini.cmdval = true;
+        p_vci_ini.address = r_dcache_addr_save & m_dcache_yzmask;
+        p_vci_ini.be     = 0xF;
+        p_vci_ini.plen   = m_dcache_words << 2;
+        p_vci_ini.cmd    = vci_param::CMD_READ;
+        p_vci_ini.trdid  = 1;   // data cache cached read
+        p_vci_ini.pktid  = 0;
+        p_vci_ini.srcid  = m_srcid;
+        p_vci_ini.cons   = false;
+        p_vci_ini.wrap   = false;
+        p_vci_ini.contig = true;
+        p_vci_ini.clen   = 0;
+        p_vci_ini.cfixed = false;
+        p_vci_ini.eop = true;
+        break;
+
+    case CMD_INS_MISS:
+        p_vci_ini.cmdval = true;
+        p_vci_ini.address = r_icache_addr_save & m_icache_yzmask;
+        p_vci_ini.be     = 0xF;
+        p_vci_ini.plen   = m_icache_words << 2;
+        p_vci_ini.cmd    = vci_param::CMD_READ;
+        p_vci_ini.trdid  = 3;   // ins cache cached read
+        p_vci_ini.pktid  = 0;
+        p_vci_ini.srcid  = m_srcid;
+        p_vci_ini.cons   = false;
+        p_vci_ini.wrap   = false;
+        p_vci_ini.contig = true;
+        p_vci_ini.clen   = 0;
+        p_vci_ini.cfixed = false;
+        p_vci_ini.eop = true;
+        break;
+
+    case CMD_INS_UNC:
+        p_vci_ini.cmdval = true;
+        p_vci_ini.address = r_icache_addr_save & ~0x3;
+        p_vci_ini.be     = 0xF;
+        p_vci_ini.plen   = 4;
+        p_vci_ini.cmd    = vci_param::CMD_READ;
+        p_vci_ini.trdid  = 2;   // ins cache uncached read
+        p_vci_ini.pktid  = 0;
+        p_vci_ini.srcid  = m_srcid;
+        p_vci_ini.cons   = false;
+        p_vci_ini.wrap   = false;
+        p_vci_ini.contig = true;
+        p_vci_ini.clen   = 0;
+        p_vci_ini.cfixed = false;
+        p_vci_ini.eop = true;
+        break;
+
+    case CMD_INS_CLEANUP:
+    case CMD_DATA_CLEANUP:
+        p_vci_ini.cmdval = true;
+        if ( r_vci_cmd_fsm == CMD_INS_CLEANUP ) p_vci_ini.address = r_icache_cleanup_line.read() * (m_icache_words<<2);
+        else                                    p_vci_ini.address = r_dcache_cleanup_line.read() * (m_icache_words<<2);
+        p_vci_ini.wdata  = 0;
+        p_vci_ini.be     = 0;
+        p_vci_ini.plen   = 4;
+        p_vci_ini.cmd    = vci_param::CMD_WRITE;
+        p_vci_ini.trdid  = 1; // cleanup for distinguish from a write
+        p_vci_ini.pktid  = 0;
+        p_vci_ini.srcid  = m_srcid;
+        p_vci_ini.cons   = false;
+        p_vci_ini.wrap   = false;
+        p_vci_ini.contig = false;
+        p_vci_ini.clen   = 0;
+        p_vci_ini.cfixed = false;
+        p_vci_ini.eop = true;
+        break;
+
+    } // end switch r_vci_cmd_fsm
+
+    // VCI_TGT
+
+    switch ( r_vci_tgt_fsm.read() ) {
+
+    case TGT_IDLE:
+    case TGT_UPDT_WORD:
+    case TGT_UPDT_DATA:
+        p_vci_tgt.cmdack  = true;
+        p_vci_tgt.rspval  = false;
+        break;
+
+    case TGT_RSP_BROADCAST:
+        p_vci_tgt.cmdack  = false;
+        p_vci_tgt.rspval  = !r_tgt_icache_req.read() && !r_tgt_dcache_req.read() && ( r_tgt_icache_rsp | r_tgt_dcache_rsp );
+        p_vci_tgt.rsrcid  = r_tgt_srcid.read();
+        p_vci_tgt.rpktid  = r_tgt_pktid.read();
+        p_vci_tgt.rtrdid  = r_tgt_trdid.read();
+        p_vci_tgt.rdata   = 0;
+        p_vci_tgt.rerror  = 0;
+        p_vci_tgt.reop    = true;
+        break;
+
+    case TGT_RSP_DCACHE:
+        p_vci_tgt.cmdack  = false;
+        p_vci_tgt.rspval  = !r_tgt_dcache_req.read();
+        p_vci_tgt.rsrcid  = r_tgt_srcid.read();
+        p_vci_tgt.rpktid  = r_tgt_pktid.read();
+        p_vci_tgt.rtrdid  = r_tgt_trdid.read();
+        p_vci_tgt.rdata   = 0;
+        p_vci_tgt.rerror  = 0;
+        p_vci_tgt.reop    = true;
+        break;
+
+    case TGT_REQ_BROADCAST:
+    case TGT_REQ_DCACHE:
+        p_vci_tgt.cmdack  = false;
+        p_vci_tgt.rspval  = false;
+        break;
+
+    } // end switch TGT_FSM
+} // end genMoore()
+
+}} // end namespace
+
+// Local Variables:
+// tab-width: 4
+// c-basic-offset: 4
+// c-file-offsets:((innamespace . 0)(inline-open . 0))
+// indent-tabs-mode: nil
+// End:
+
+// vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4
+
+
+
+
Index: branches/v4/modules/vci_cc_xcache_wrapper_multi/caba/metadata/vci_cc_xcache_wrapper_multi.sd
===================================================================
--- branches/v4/modules/vci_cc_xcache_wrapper_multi/caba/metadata/vci_cc_xcache_wrapper_multi.sd	(revision 371)
+++ branches/v4/modules/vci_cc_xcache_wrapper_multi/caba/metadata/vci_cc_xcache_wrapper_multi.sd	(revision 371)
@@ -0,0 +1,62 @@
+
+# -*- python -*-
+
+__id__ = "$Id$"
+__version__ = "$Revision$"
+
+Module('caba:vci_cc_xcache_wrapper_multi',
+	classname = 'soclib::caba::VciCcXCacheWrapperMulti',
+	tmpl_parameters = [
+		parameter.Module('vci_param', default = 'caba:vci_param'),
+		parameter.Module('iss_t'),
+		],
+	header_files = [
+		'../source/include/vci_cc_xcache_wrapper_multi.h',
+		],
+	implementation_files = [
+		'../source/src/vci_cc_xcache_wrapper_multi.cpp',
+		],
+	uses = [
+		Uses('caba:base_module'),
+		Uses('common:mapping_table'),
+		Uses('common:iss2'),
+		Uses('caba:multi_write_buffer'),
+		Uses('caba:generic_cache', addr_t = 'uint32_t'),
+		],
+	ports = [
+		Port('caba:vci_initiator', 'p_vci_ini_d'),
+        Port('caba:vci_initiator', 'p_vci_ini_c'),
+		Port('caba:vci_target', 'p_vci_tgt'),
+		Port('caba:bit_in', 'p_irq', parameter.Constant('n_irq')),
+		Port('caba:bit_in', 'p_resetn', auto = 'resetn'),
+		Port('caba:clock_in', 'p_clk', auto = 'clock'),
+		],
+	instance_parameters = [
+		parameter.Int('proc_id'),
+		parameter.Module('mtp', 'common:mapping_table'),
+		parameter.Module('mtc', 'common:mapping_table'),
+		parameter.IntTab('initiator_rw_index'),
+		parameter.IntTab('initiator_c_index'),
+		parameter.IntTab('target_index'),
+		parameter.Int('icache_ways'),
+		parameter.Int('icache_sets'),
+		parameter.Int('icache_words'),
+		parameter.Int('dcache_ways'),
+		parameter.Int('dcache_sets'),
+		parameter.Int('dcache_words'),
+		parameter.Int('wbuf_nwords'),
+		parameter.Int('wbuf_nlines'),
+		],
+	   extensions = [
+	'dsx:get_ident='
+        'initiator_rw_index:p_vci_ini_d:mt,'
+        'initiator_c_index:p_vci_ini_c:mc,'
+        'target_index:p_vci_tgt:mc',
+	'dsx:cpu=wrapper:iss_t',
+	'dsx:addressable=target_index',
+    'dsx:on_segment=mc:add_index:initiator_rw_index',
+	'dsx:mapping_type=processor:proc_id',
+   ],
+)
+
+
Index: branches/v4/modules/vci_cc_xcache_wrapper_multi/caba/source/include/vci_cc_xcache_wrapper_multi.h
===================================================================
--- branches/v4/modules/vci_cc_xcache_wrapper_multi/caba/source/include/vci_cc_xcache_wrapper_multi.h	(revision 371)
+++ branches/v4/modules/vci_cc_xcache_wrapper_multi/caba/source/include/vci_cc_xcache_wrapper_multi.h	(revision 371)
@@ -0,0 +1,321 @@
+/* -*- c++ -*-
+ *
+ * SOCLIB_LGPL_HEADER_BEGIN
+ * 
+ * This file is part of SoCLib, GNU LGPLv2.1.
+ * 
+ * SoCLib is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU Lesser General Public License as published
+ * by the Free Software Foundation; version 2.1 of the License.
+ * 
+ * SoCLib is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * Lesser General Public License for more details.
+ * 
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with SoCLib; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301 USA
+ * 
+ * SOCLIB_LGPL_HEADER_END
+ *
+ * Copyright (c) UPMC, Lip6, SoC
+ *         Alain Greiner <alain.greiner@lip6.fr>, 2008
+ *
+ * Maintainers: alain
+ */
+ 
+#ifndef SOCLIB_CABA_VCI_CC_XCACHE_WRAPPER_MULTI_H
+#define SOCLIB_CABA_VCI_CC_XCACHE_WRAPPER_MULTI_H
+
+#include <inttypes.h>
+#include <systemc>
+#include "caba_base_module.h"
+#include "multi_write_buffer.h"
+#include "generic_cache.h"
+#include "vci_initiator.h"
+#include "vci_target.h"
+#include "mapping_table.h"
+#include "static_assert.h"
+
+
+namespace soclib {
+namespace caba {
+
+using namespace sc_core;
+
+////////////////////////////////////////////
+template<typename vci_param, typename iss_t>
+class VciCcXCacheWrapperMulti
+///////////////////////////////////////////
+    : public soclib::caba::BaseModule
+{
+    typedef 		uint32_t    		data_t;
+    typedef 		uint32_t    		be_t;
+    typedef typename 	vci_param::fast_addr_t 	addr_t;
+
+    enum dcache_fsm_state_e {
+        DCACHE_IDLE,
+        DCACHE_WRITE_UPDT,
+        DCACHE_WRITE_REQ,
+        DCACHE_MISS_SELECT,
+        DCACHE_MISS_CLEANUP,
+        DCACHE_MISS_WAIT,
+        DCACHE_MISS_UPDT,
+        DCACHE_UNC_WAIT,
+        DCACHE_UNC_GO,
+        DCACHE_INVAL,
+        DCACHE_SYNC,
+        DCACHE_ERROR,
+        DCACHE_CC_CHECK,
+        DCACHE_CC_INVAL,
+        DCACHE_CC_UPDT,
+    };
+
+    enum icache_fsm_state_e {
+        ICACHE_IDLE,
+        ICACHE_MISS_SELECT,
+        ICACHE_MISS_CLEANUP,
+        ICACHE_MISS_WAIT,
+        ICACHE_MISS_UPDT,
+        ICACHE_UNC_WAIT,
+        ICACHE_UNC_GO,
+        ICACHE_ERROR,
+        ICACHE_CC_CHECK,
+        ICACHE_CC_INVAL,
+        ICACHE_CC_UPDT,
+    };
+
+    enum cmd_fsm_state_e {
+        CMD_IDLE,
+        CMD_INS_MISS,
+        CMD_INS_UNC,
+        CMD_DATA_MISS,
+        CMD_DATA_UNC,
+        CMD_DATA_WRITE,
+    };
+
+    enum rsp_fsm_state_e {
+        RSP_IDLE,
+        RSP_INS_MISS,
+        RSP_INS_UNC,
+        RSP_DATA_MISS,
+        RSP_DATA_UNC,
+        RSP_DATA_WRITE,
+    };
+
+    enum tgt_fsm_state_e {
+        TGT_IDLE,
+        TGT_UPDT_WORD,
+        TGT_UPDT_DATA,
+        TGT_REQ_BROADCAST,
+        TGT_REQ_ICACHE,
+        TGT_REQ_DCACHE,
+        TGT_RSP_BROADCAST,
+        TGT_RSP_ICACHE,
+        TGT_RSP_DCACHE,
+    };
+
+    enum cleanup_fsm_state_e {
+        CLEANUP_IDLE,
+        CLEANUP_DCACHE,
+        CLEANUP_ICACHE,
+    };
+
+    enum transaction_type_e {
+        TYPE_DATA_UNC = 0,
+        TYPE_DATA_MISS = 1,
+        TYPE_INS_UNC = 2,
+        TYPE_INS_MISS = 3,
+    };
+
+public:
+
+    // PORTS
+    sc_in<bool>                             p_clk;
+    sc_in<bool>                             p_resetn;
+    sc_in<bool>                             p_irq[iss_t::n_irq];
+    soclib::caba::VciInitiator<vci_param>   p_vci_ini_d;
+    soclib::caba::VciInitiator<vci_param>   p_vci_ini_c;
+    soclib::caba::VciTarget<vci_param>      p_vci_tgt_c;
+
+private:
+
+    // STRUCTURAL PARAMETERS
+    const soclib::common::AddressDecodingTable<addr_t, bool>    	m_cacheability_table;
+    const soclib::common::Segment                                   	m_segment;
+    iss_t               						m_iss;
+    const uint32_t      						m_srcid_d;   
+    const uint32_t      						m_srcid_c;   
+   
+    const size_t        						m_dcache_ways;
+    const size_t        						m_dcache_words;
+    const size_t        						m_dcache_yzmask;
+    const size_t        						m_icache_ways;
+    const size_t        						m_icache_words;
+    const size_t        						m_icache_yzmask;
+
+    // REGISTERS
+    sc_signal<int>          r_dcache_fsm;		// controls the data cache interface
+    sc_signal<int>          r_dcache_fsm_save;
+    sc_signal<addr_t>       r_dcache_addr_save;
+    sc_signal<data_t>       r_dcache_wdata_save;
+    sc_signal<data_t>       r_dcache_rdata_save;
+    sc_signal<int>          r_dcache_type_save;
+    sc_signal<be_t>         r_dcache_be_save;
+    sc_signal<addr_t>       r_dcache_cleanup_save;	// victim line index for cleanup
+    sc_signal<size_t>       r_dcache_way_save;		// selected slot for the replacement
+    sc_signal<bool>         r_dcache_cleanup_req;	// send a cleanup request to CLEANUP FSM
+    sc_signal<addr_t>       r_dcache_cleanup_line;	// define the victim line index
+    sc_signal<bool>         r_dcache_miss_req;          // send a miss request to CMD FSM
+    sc_signal<bool>         r_dcache_unc_req;		// send a uncached request to CMD FSM
+    sc_signal<bool>         r_dcache_inval_pending;	// external inval or update request pending
+
+    sc_signal<int>          r_icache_fsm;		// controls the instruction cache interface
+    sc_signal<int>          r_icache_fsm_save;
+    sc_signal<addr_t>       r_icache_addr_save;
+    sc_signal<addr_t>       r_icache_cleanup_save;	// victim line index for cleanup
+    sc_signal<size_t>       r_icache_way_save;		// selected slot for the replacement
+    sc_signal<bool>         r_icache_miss_req;          // send a miss request to to CMD FSM
+    sc_signal<bool>         r_icache_unc_req;		// send an uncached request to CMD FSM
+    sc_signal<bool>         r_icache_cleanup_req;	// send a cleanup request to CLEANUP FSM
+    sc_signal<addr_t>       r_icache_cleanup_line;      // define the victim line index
+    sc_signal<bool>         r_icache_inval_pending;	// external inval or update request pending
+
+    sc_signal<int>          r_cmd_fsm;			// controls the command on the direct network
+    sc_signal<size_t>       r_cmd_min;       
+    sc_signal<size_t>       r_cmd_max;       
+    sc_signal<size_t>       r_cmd_cpt;       
+      
+    sc_signal<int>          r_rsp_fsm;			// controls the response on the direct network
+    sc_signal<bool>         r_rsp_ins_error;    	// signals an error to the ICACHE FSM
+    sc_signal<bool>         r_rsp_data_error;    	// signals an error to the DCACHE FSM
+    sc_signal<size_t>       r_rsp_cpt;  
+    sc_signal<bool>         r_rsp_ins_ok;		// signals an available data to the ICACHE FSM
+    sc_signal<bool>         r_rsp_data_ok;		// signals an available data to the DCACHE FSM;
+
+    data_t                  *r_icache_miss_buf;    
+    data_t                  *r_dcache_miss_buf;    
+
+    data_t                  *r_tgt_buf;
+    bool                    *r_tgt_val;
+
+    sc_signal<int>          r_tgt_fsm;			// controls the target port of the coherence network
+    sc_signal<addr_t>       r_tgt_addr;
+    sc_signal<size_t>       r_tgt_word;
+    sc_signal<bool>         r_tgt_update;
+    sc_signal<bool>         r_tgt_data;
+    sc_signal<bool>         r_tgt_brdcast;
+    sc_signal<size_t>       r_tgt_srcid;
+    sc_signal<size_t>       r_tgt_pktid;
+    sc_signal<size_t>       r_tgt_trdid;
+    sc_signal<size_t>       r_tgt_plen;
+    sc_signal<bool>         r_tgt_icache_req;		// coherence request from TGT FSM to ICACHE FSM
+    sc_signal<bool>         r_tgt_dcache_req;		// coherence request from TGT FSM to DCACHE FSM
+    sc_signal<bool>         r_tgt_icache_rsp;   	// response from ICACHE FSM to TGT FSM : true == hit
+    sc_signal<bool>         r_tgt_dcache_rsp;   	// response from DCACHE FSM to TGT FSM : true == hit
+
+    sc_signal<int>          r_cleanup_fsm;		// controls initiator port of the coherence network
+
+    MultiWriteBuffer<addr_t>	r_wbuf;
+    GenericCache<addr_t>    	r_icache;
+    GenericCache<addr_t>    	r_dcache;
+
+    // Activity counters
+    uint32_t m_cpt_dcache_data_read;        // DCACHE DATA READ
+    uint32_t m_cpt_dcache_data_write;       // DCACHE DATA WRITE
+    uint32_t m_cpt_dcache_dir_read;         // DCACHE DIR READ
+    uint32_t m_cpt_dcache_dir_write;        // DCACHE DIR WRITE
+
+    uint32_t m_cpt_icache_data_read;        // ICACHE DATA READ
+    uint32_t m_cpt_icache_data_write;       // ICACHE DATA WRITE
+    uint32_t m_cpt_icache_dir_read;         // ICACHE DIR READ
+    uint32_t m_cpt_icache_dir_write;        // ICACHE DIR WRITE
+
+    uint32_t m_cpt_cc_broadcast;            // number of coherence broadcast packets 
+    uint32_t m_cpt_cc_update_data;          // number of coherence data update packets 
+    uint32_t m_cpt_cc_update_ins;           // number of coherence instruction update packets 
+    uint32_t m_cpt_cc_inval_data;           // number of coherence data inval packets
+    uint32_t m_cpt_cc_inval_ins;            // number of coherence instruction inval packets
+    uint32_t m_cpt_cc_cleanup_data;         // number of coherence data cleanup packets
+    uint32_t m_cpt_cc_cleanup_ins;          // number of coherence instruction cleanup packets
+
+    uint32_t m_cpt_frz_cycles;	            // number of cycles where the cpu is frozen
+    uint32_t m_cpt_total_cycles;	    // total number of cycles 
+
+    uint32_t m_cpt_read;                    // total number of read requests
+    uint32_t m_cpt_write;                   // total number of write requests
+    uint32_t m_cpt_write_cached;            // number of cached write requests
+    uint32_t m_cpt_data_unc;                // number of uncachable data requests
+    uint32_t m_cpt_ins_unc;                 // number of uncachable instruction requests
+    uint32_t m_cpt_ll;                      // number of ll requests
+    uint32_t m_cpt_sc;                      // number of sc requests
+    uint32_t m_cpt_data_miss;               // number of read miss
+    uint32_t m_cpt_ins_miss;                // number of instruction miss
+
+    uint32_t m_cost_write_frz;              // number of frozen cycles related to write buffer         
+    uint32_t m_cost_data_miss_frz;          // number of frozen cycles related to data miss
+    uint32_t m_cost_unc_frz;                // number of frozen cycles related to uncached read
+    uint32_t m_cost_ins_miss_frz;           // number of frozen cycles related to ins miss
+
+    uint32_t m_cpt_imiss_transaction;       // number of VCI instruction miss transactions
+    uint32_t m_cpt_dmiss_transaction;       // number of VCI data miss transactions
+    uint32_t m_cpt_data_unc_transaction;    // number of VCI instruction uncached transactions
+    uint32_t m_cpt_ins_unc_transaction;     // number of VCI data uncached transactions
+    uint32_t m_cpt_write_transaction;       // number of VCI write transactions
+
+    uint32_t m_length_write_transaction;    // cumulated length for VCI WRITE transactions
+
+protected:
+    SC_HAS_PROCESS(VciCcXCacheWrapperMulti);
+
+public:
+
+    VciCcXCacheWrapperMulti(
+                       sc_module_name insname,
+                       int proc_id,
+                       const soclib::common::MappingTable &mtp,
+                       const soclib::common::MappingTable &mtc,
+                       const soclib::common::IntTab &initiator_index_p,
+                       const soclib::common::IntTab &initiator_index_c,
+                       const soclib::common::IntTab &target_index_c,
+                       size_t icache_ways,
+                       size_t icache_sets,
+                       size_t icache_words,
+                       size_t dcache_ways,
+                       size_t dcache_sets,
+                       size_t dcache_words,
+                       size_t wbuf_nwords,
+                       size_t wbuf_nlines,
+                       size_t wbuf_timeout);
+
+    ~VciCcXCacheWrapperMulti();
+
+    void printTrace(size_t mode);
+    void printStatistics();
+
+private:
+
+    void transition();
+    void genMoore();
+
+    static_assert((int)iss_t::SC_ATOMIC == (int)vci_param::STORE_COND_ATOMIC);
+    static_assert((int)iss_t::SC_NOT_ATOMIC == (int)vci_param::STORE_COND_NOT_ATOMIC);
+};
+
+}}
+
+#endif /* SOCLIB_CABA_VCI_CC_XCACHE_WRAPPER_MULTI_H */
+
+// Local Variables:
+// tab-width: 4
+// c-basic-offset: 4
+// c-file-offsets:((innamespace . 0)(inline-open . 0))
+// indent-tabs-mode: nil
+// End:
+
+// vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4
+
+
+
Index: branches/v4/modules/vci_cc_xcache_wrapper_multi/caba/source/src/vci_cc_xcache_wrapper_multi.cpp
===================================================================
--- branches/v4/modules/vci_cc_xcache_wrapper_multi/caba/source/src/vci_cc_xcache_wrapper_multi.cpp	(revision 371)
+++ branches/v4/modules/vci_cc_xcache_wrapper_multi/caba/source/src/vci_cc_xcache_wrapper_multi.cpp	(revision 371)
@@ -0,0 +1,2023 @@
+/* -*- c++ -*-
+ *
+ * SOCLIB_LGPL_HEADER_BEGIN
+ * 
+ * This file is part of SoCLib, GNU LGPLv2.1.
+ * 
+ * SoCLib is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU Lesser General Public License as published
+ * by the Free Software Foundation; version 2.1 of the License.
+ * 
+ * SoCLib is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * Lesser General Public License for more details.
+ * 
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with SoCLib; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301 USA
+ * 
+ * SOCLIB_LGPL_HEADER_END
+ *
+ * Copyright (c) UPMC, Lip6, SoC
+ *         Alain Greiner <alain.greiner@lip6.fr>, 2008
+ *
+ * Maintainers: alain 
+ *              eric.guthmuller@polytechnique.edu 
+ *              nipo
+ *              malek <abdelmalek.si-merabet@lip6.fr> 
+ */
+
+/////////////////////////////////////////////////////////////////////////////
+// History
+// - 25/04/2008
+//   The existing vci_xcache component has been extended to include 
+//   a VCI target port to support a directory based coherence protocol.
+//   Three types of packets can be send by the L2 cache to the L1 cache
+//   * MULTICAST INVALIDATE packets : length = 1
+//   * MULTICAST UPDATE packets : length = n + 2   
+//   * BROADCAST INVALIDATE packets : length = 1
+//   The CLEANUP packets are sent by the L1 cache to the L2 cache, 
+//   to signal a replaced cache line.
+// - 12/08/2008
+//   The vci_cc_xcache_wrapper component instanciates directly the processsor 
+//   iss, in order to supress the processor/cache interface.
+//   According to the VCI advanced specification, this component uses one 
+//   word VCI CMD packets for MISS transactions, and accept one word VCI RSP
+//   packets for Write burst  transactions.
+//   The write buffer has been modified to use the WriteBuffer object. 
+//   A VCI write burst is constructed when two conditions are satisfied :
+//   The processor make strictly successive write requests, and they are
+//   in the same cache line. The write buffer performs re-ordering, to
+//   respect the contiguous addresses VCI constraint. In case of several
+//   WRITE_WORD requests in the same word, only the last request is conserved.
+//   In case of several WRITE_HALF or WRITE_WORD requests in the same word,
+//   the requests are merged in the same word. In case of uncachable write
+//   requests, each request is transmited as a single VCI transaction.
+//   Both the data & instruction caches can be flushed in one single cycle.
+// - 08/12/2009
+//   The update instruction coherence request (code 0XC) are supported. 
+// - 26/12/2009
+//   The VCI_CC_XCACHE_WRAPPER_MULTI is derived from the VCI_CC_XCACHE_WRAPPER_V1
+//   to support several concurrent VCI transactions, in order to improve the CPI.
+//   A new write buffer supporting simultaneous write transactions has been 
+//   introduced. The VCI command & response FSMs are not synchronized anymore:
+//   The read requests can be transmitted before previous write requests
+//   (if the missing address does not match a pending write in the write buffer)
+//   and several read & write requests can be simultaneously transmitted.
+//   The transactions can complete in any order, depending on the network.
+//   Two new flip-flops have been introduced to signal completion of the
+//   read transactions from the RSP FSM to the DCACHE & ICACHE FSMs: 
+//   r_rsp_data_ok, r_rsp_ins_ok
+//   As simultaneous VCI transactions are supported, the TRDID & RTRDID fields
+//   are used to transport the transaction index.
+//   The transaction index has an odd value for a write transaction, depending
+//   on the line index in the write buffer: PKTID = 2*wbuf_index + 1
+//   The transaction index has an even value for a read transaction, with only
+//   only four possible values, depending on cachable/uncachable & data/instruction.
+//   A new CLEANUP FSM has been introduced to transmit the cleanups 
+//   request from the DCACHE & ICACHE FSM on the coherence network.
+//   The LL/SC requests are still uncachable.
+// - 07/06/2010
+//   The DCACHE FSM has been modified to enforce a well defined consistency model:
+//   1) All uncachable acces (both read and write) are now blocking
+//      the processor until the VCI response is received.
+//      Uncachable access are considered as I/O access and must respect
+//      a strict sequencial policy.
+//   2) For cachable access, the write buffer supports the "read after write"
+//      rule, and the "write after write" rule : registered write requests
+//      are tested before handling a read miss, and before locking a buffer line.
+//   The MultiWriteBuffer component has been modified, to support
+//   these rules, and to have an associative behavior: it can exist several
+//   open lines, with a private time-out for each open line.
+//   A printTrace() method has been defined.
+///////////////////////////////////////////////////////////////////////////////
+
+#include <cassert>
+#include "arithmetics.h"
+#include "../include/vci_cc_xcache_wrapper_multi.h"
+
+namespace soclib { 
+namespace caba {
+
+    namespace {
+        const char *dcache_fsm_state_str[] = {
+            "DCACHE_IDLE        ",
+            "DCACHE_WRITE_UPDT  ",
+            "DCACHE_WRITE_REQ   ",
+            "DCACHE_MISS_SELECT ",
+            "DCACHE_MISS_CLEANUP",
+            "DCACHE_MISS_WAIT   ",
+            "DCACHE_MISS_UPDT   ",
+            "DCACHE_UNC_WAIT    ",
+            "DCACHE_UNC_GO      ",
+            "DCACHE_INVAL       ",
+            "DCACHE_SYNC        ",
+            "DCACHE_ERROR       ",
+            "DCACHE_CC_CHECK    ",
+            "DCACHE_CC_INVAL    ",
+            "DCACHE_CC_UPDT     ",
+        };
+        const char *icache_fsm_state_str[] = {
+            "ICACHE_IDLE        ",
+            "ICACHE_MISS_SELECT ",
+            "ICACHE_MISS_CLEANUP",
+            "ICACHE_MISS_WAIT   ",
+            "ICACHE_MISS_UPDT   ",
+            "ICACHE_UNC_WAIT    ",
+            "ICACHE_UNC_GO      ",
+            "ICACHE_ERROR       ",
+            "ICACHE_CC_CHECK    ",
+            "ICACHE_CC_INVAL    ",
+            "ICACHE_CC_UPDT     ",
+        };
+        const char *cmd_fsm_state_str[] = {
+            "CMD_IDLE      ",
+            "CMD_INS_MISS  ",
+            "CMD_INS_UNC   ",
+            "CMD_DATA_MISS ",
+            "CMD_DATA_UNC  ",
+            "CMD_DATA_WRITE",
+        };
+        const char *rsp_fsm_state_str[] = {
+            "RSP_IDLE      ",
+            "RSP_INS_MISS  ",
+            "RSP_INS_UNC   ",
+            "RSP_DATA_MISS ",
+            "RSP_DATA_UNC  ",
+            "RSP_DATA_WRITE",
+        };
+        const char *tgt_fsm_state_str[] = {
+            "TGT_IDLE         ",
+            "TGT_UPDT_WORD    ",
+            "TGT_UPDT_DATA    ",
+            "TGT_REQ_BROADCAST",
+            "TGT_REQ_ICACHE   ",
+            "TGT_REQ_DCACHE   ",
+            "TGT_RSP_BROADCAST",
+            "TGT_RSP_ICACHE   ",
+            "TGT_RSP_DCACHE   ",
+        };
+        const char *cleanup_fsm_state_str[] = {
+            "CLEANUP_IDLE",
+            "CLEANUP_DCACHE",
+            "CLEANUP_ICACHE",
+        };
+    }
+
+#define tmpl(...)  template<typename vci_param, typename iss_t> __VA_ARGS__ VciCcXCacheWrapperMulti<vci_param, iss_t>
+
+    using soclib::common::uint32_log2;
+
+    /////////////////////////////////////
+    tmpl(/**/)::VciCcXCacheWrapperMulti(
+            sc_module_name name,
+            int proc_id,
+            const soclib::common::MappingTable &mtp,
+            const soclib::common::MappingTable &mtc,
+            const soclib::common::IntTab &initiator_index_p,
+            const soclib::common::IntTab &initiator_index_c,
+            const soclib::common::IntTab &target_index_c,
+            size_t icache_ways,
+            size_t icache_sets,
+            size_t icache_words,
+            size_t dcache_ways,
+            size_t dcache_sets,
+            size_t dcache_words,
+            size_t wbuf_nwords,
+            size_t wbuf_nlines,
+            size_t wbuf_timeout)
+        : 
+            soclib::caba::BaseModule(name),
+
+            p_clk("clk"),
+            p_resetn("resetn"),
+            p_vci_ini_d("vci_ini_p"),
+            p_vci_ini_c("vci_ini_c"),
+            p_vci_tgt_c("vci_tgt_c"),
+
+            m_cacheability_table(mtp.getCacheabilityTable<addr_t>()),
+            m_segment(mtc.getSegment(target_index_c)),
+            m_iss(this->name(), proc_id),
+            m_srcid_d(mtp.indexForId(initiator_index_p)),
+            m_srcid_c(mtc.indexForId(initiator_index_c)),
+            
+            m_dcache_ways(dcache_ways),
+            m_dcache_words(dcache_words),
+            m_dcache_yzmask((~0)<<(uint32_log2(dcache_words) + 2)),
+            m_icache_ways(icache_ways),
+            m_icache_words(icache_words),
+            m_icache_yzmask((~0)<<(uint32_log2(icache_words) + 2)),
+
+            r_dcache_fsm("r_dcache_fsm"),
+            r_dcache_fsm_save("r_dcache_fsm_save"),
+            r_dcache_addr_save("r_dcache_addr_save"),
+            r_dcache_wdata_save("r_dcache_wdata_save"),
+            r_dcache_rdata_save("r_dcache_rdata_save"),
+            r_dcache_type_save("r_dcache_type_save"),
+            r_dcache_be_save("r_dcache_be_save"),
+            r_dcache_cleanup_save("r_dcache_cleanup_save"),
+            r_dcache_way_save("r_dcache_way_save"),
+            r_dcache_cleanup_req("r_dcache_cleanup_req"),
+            r_dcache_cleanup_line("r_dcache_cleanup_line"),
+            r_dcache_miss_req("r_dcache_miss_req"),
+            r_dcache_unc_req("r_dcache_unc_req"),
+            r_dcache_inval_pending("r_dcache_inval_pending"),
+
+            r_icache_fsm("r_icache_fsm"),
+            r_icache_fsm_save("r_icache_fsm_save"),
+            r_icache_addr_save("r_icache_addr_save"),
+            r_icache_cleanup_save("r_icache_cleanup_save"),
+            r_icache_way_save("r_icache_way_save"),
+            r_icache_miss_req("r_icache_miss_req"),
+            r_icache_cleanup_req("r_icache_cleanup_req"),
+            r_icache_cleanup_line("r_icache_cleanup_line"),
+            r_icache_inval_pending("r_icache_inval_pending"),
+
+            r_cmd_fsm("r_cmd_fsm"),
+            r_cmd_min("r_cmd_min"),
+            r_cmd_max("r_cmd_max"),
+            r_cmd_cpt("r_cmd_cpt"),
+
+            r_rsp_fsm("r_rsp_fsm"),
+            r_rsp_ins_error("r_rsp_ins_error"),
+            r_rsp_data_error("r_rsp_data_error"),
+            r_rsp_cpt("r_rsp_cpt"),
+            r_rsp_ins_ok("r_rsp_ins_ok"),
+            r_rsp_data_ok("r_rsp_data_ok"),
+
+            r_tgt_fsm("r_tgt_fsm"),
+            r_tgt_addr("r_tgt_addr"),
+            r_tgt_word("r_tgt_word"),
+            r_tgt_update("r_tgt_update"),
+            r_tgt_data("r_tgt_data"),
+            r_tgt_srcid("r_tgt_srcid"),
+            r_tgt_pktid("r_tgt_pktid"),
+            r_tgt_trdid("r_tgt_trdid"),
+            r_tgt_icache_req("r_tgt_icache_req"),
+            r_tgt_dcache_req("r_tgt_dcache_req"),
+            r_tgt_icache_rsp("r_tgt_icache_rsp"),
+            r_tgt_dcache_rsp("r_tgt_dcache_rsp"),
+
+            r_cleanup_fsm("r_cleanup_fsm"),
+
+            r_wbuf("r_wbuf", wbuf_nwords, wbuf_nlines, wbuf_timeout, dcache_words),
+            r_icache("icache", icache_ways, icache_sets, icache_words),
+            r_dcache("dcache", dcache_ways, dcache_sets, dcache_words)
+
+            {
+                assert( (icache_words*vci_param::B) < (1<<vci_param::K) &&
+                        "I need more PLEN bits");
+
+                assert( (vci_param::T > 2) && ((1<<(vci_param::T-1)) >= wbuf_nlines) &&
+                        "I need more TRDID bits");
+
+                r_icache_miss_buf = new data_t[icache_words];
+                r_dcache_miss_buf = new data_t[dcache_words];
+                r_tgt_buf         = new data_t[dcache_words];
+                r_tgt_val         = new bool[dcache_words];
+
+                SC_METHOD(transition);
+                dont_initialize();
+                sensitive << p_clk.pos();
+
+                SC_METHOD(genMoore);
+                dont_initialize();
+                sensitive << p_clk.neg();
+
+                typename iss_t::CacheInfo cache_info;
+                cache_info.has_mmu = false;
+                cache_info.icache_line_size = icache_words*sizeof(data_t);
+                cache_info.icache_assoc = icache_ways;
+                cache_info.icache_n_lines = icache_sets;
+                cache_info.dcache_line_size = dcache_words*sizeof(data_t);
+                cache_info.dcache_assoc = dcache_ways;
+                cache_info.dcache_n_lines = dcache_sets;
+                m_iss.setCacheInfo(cache_info);
+
+            } // end constructor
+
+    //////////////////////////////////////
+    tmpl(/**/)::~VciCcXCacheWrapperMulti()
+    {
+        delete [] r_icache_miss_buf;
+        delete [] r_dcache_miss_buf;
+        delete [] r_tgt_val;
+        delete [] r_tgt_buf;
+    }
+
+    ///////////////////////////////////
+    tmpl(void)::printTrace(size_t mode)
+    {
+        typename iss_t::InstructionRequest  ireq;
+        typename iss_t::DataRequest         dreq;
+
+        m_iss.getRequests( ireq, dreq );
+        std::cout << std::dec << "Proc " << m_srcid_d << std::endl;
+        std::cout << ireq << std::endl;
+        std::cout << dreq << std::endl;
+        std::cout << "  " << dcache_fsm_state_str[r_dcache_fsm]
+                  << "  " << icache_fsm_state_str[r_icache_fsm]
+                  << "  " << cmd_fsm_state_str[r_cmd_fsm]
+                  << "  " << rsp_fsm_state_str[r_rsp_fsm]
+                  << "  " << tgt_fsm_state_str[r_tgt_fsm] 
+                  << "  " << cleanup_fsm_state_str[r_cleanup_fsm] << std::endl;
+        if(mode & 0x1)
+        {
+            r_wbuf.printTrace();
+        }
+        if(mode & 0x2)
+        {
+            std::cout << "  Data cache" << std::endl;
+            r_dcache.printTrace();
+        }
+        if(mode & 0x4)
+        {
+            std::cout << "  Instruction cache" << std::endl;
+            r_icache.printTrace();
+        }
+    }
+    /////////////////////////////
+    tmpl(void)::printStatistics()
+    {
+        float run_cycles = (float)(m_cpt_total_cycles - m_cpt_frz_cycles);
+        std::cout << "------------------------------------" << std:: dec << std::endl
+        << "CPU " << m_srcid_d << " / cycles = " << m_cpt_total_cycles << std::endl
+        << "- CPI               = " << (float)m_cpt_total_cycles/run_cycles << std::endl
+        << "- READ RATE         = " << (float)m_cpt_read/run_cycles << std::endl
+        << "- WRITE RATE        = " << (float)m_cpt_write/run_cycles << std::endl
+        << "- CACHED WRITE RATE = " << (float)m_cpt_write_cached/m_cpt_write << std::endl
+        << "- UNC RATE          = " << (float)m_cpt_data_unc/run_cycles << std::endl
+        << "- LL RATE           = " << (float)m_cpt_ll/run_cycles << std::endl
+        << "- SC RATE           = " << (float)m_cpt_sc/run_cycles << std::endl
+        << "- IMISS_RATE        = " << (float)m_cpt_ins_miss/run_cycles << std::endl
+        << "- IMISS COST        = " << (float)m_cost_ins_miss_frz/m_cpt_ins_miss << std::endl
+        << "- DMISS RATE        = " << (float)m_cpt_data_miss/m_cpt_read << std::endl
+        << "- DMISS COST        = " << (float)m_cost_data_miss_frz/m_cpt_data_miss << std::endl
+        << "- UNC COST          = " << (float)m_cost_unc_frz/m_cpt_data_unc << std::endl
+        << "- WRITE COST        = " << (float)m_cost_write_frz/m_cpt_write << std::endl
+        << "- WRITE LENGTH      = " << (float)m_length_write_transaction/m_cpt_write_transaction << std::endl
+        << "- CC_BROADCAST      = " << m_cpt_cc_broadcast << std::endl
+        << "- CC_UPDATE_DATA    = " << m_cpt_cc_update_data << std::endl
+        << "- CC_UPDATE_INS     = " << m_cpt_cc_update_ins << std::endl
+        << "- CC_INVAL_DATA     = " << m_cpt_cc_inval_data << std::endl
+        << "- CC_INVAL_INS      = " << m_cpt_cc_inval_ins << std::endl
+        << "- CC_CLEANUP_DATA   = " << m_cpt_cc_cleanup_data << std::endl
+        << "- CC_CLEANUP_INS    = " << m_cpt_cc_cleanup_ins << std::endl;
+    }
+
+    //////////////////////////
+    tmpl(void)::transition()
+    {
+        if ( ! p_resetn.read() ) {
+
+            m_iss.reset();
+
+            // FSM states
+            r_dcache_fsm 	= DCACHE_IDLE;
+            r_icache_fsm 	= ICACHE_IDLE;
+            r_cmd_fsm 		= CMD_IDLE;
+            r_rsp_fsm 		= RSP_IDLE;
+            r_tgt_fsm 		= TGT_IDLE;
+            r_cleanup_fsm 	= CLEANUP_IDLE;
+
+            // write buffer & caches
+            r_wbuf.reset();
+            r_icache.reset();
+            r_dcache.reset();
+
+            // synchronisation flip-flops from ICACHE & DCACHE FSMs to CMD  FSM
+            r_icache_miss_req    = false;
+            r_icache_unc_req     = false;
+            r_dcache_miss_req    = false;
+            r_dcache_unc_req     = false;
+
+            // synchronisation flip-flops from ICACHE & DCACHE FSMs to CLEANUP FSM
+            r_icache_cleanup_req = false;
+            r_dcache_cleanup_req = false;
+
+            // synchronisation flip-flops from TGT FSM to ICACHE & DCACHE FSMs
+            r_tgt_icache_req     = false;
+            r_tgt_dcache_req     = false;
+            r_tgt_icache_rsp     = false;
+            r_tgt_dcache_rsp     = false;
+
+            // internal messages in DCACHE et ICACHE FSMs
+            r_icache_inval_pending   = false;
+            r_dcache_inval_pending   = false;
+
+            // synchronisation flip-flops from the RSP FSM to the ICACHE or DCACHE FSMs
+            r_rsp_data_ok 	= false;
+            r_rsp_ins_ok	= false;
+            r_rsp_data_error   	= false;
+            r_rsp_ins_error    	= false;
+
+            // activity counters
+            m_cpt_dcache_data_read  = 0;
+            m_cpt_dcache_data_write = 0;
+            m_cpt_dcache_dir_read  = 0;
+            m_cpt_dcache_dir_write = 0;
+
+            m_cpt_icache_data_read  = 0;
+            m_cpt_icache_data_write = 0;
+            m_cpt_icache_dir_read  = 0;
+            m_cpt_icache_dir_write = 0;
+
+            m_cpt_cc_broadcast = 0;
+            m_cpt_cc_update_data = 0;
+            m_cpt_cc_inval_data = 0;
+            m_cpt_cc_cleanup_data = 0;
+            m_cpt_cc_update_ins = 0;
+            m_cpt_cc_inval_ins = 0;
+            m_cpt_cc_cleanup_ins = 0;
+
+            m_cpt_frz_cycles = 0;
+            m_cpt_total_cycles = 0;
+
+            m_cpt_read = 0;
+            m_cpt_write = 0;
+            m_cpt_write_cached = 0;
+            m_cpt_data_unc = 0;
+            m_cpt_ins_unc = 0;
+            m_cpt_ll = 0;
+            m_cpt_sc = 0;
+            m_cpt_data_miss = 0;
+            m_cpt_ins_miss = 0;
+
+            m_cost_write_frz = 0;
+            m_cost_data_miss_frz = 0;
+            m_cost_unc_frz = 0;
+            m_cost_ins_miss_frz = 0;
+
+            m_cpt_imiss_transaction = 0;
+            m_cpt_dmiss_transaction = 0;
+            m_cpt_data_unc_transaction = 0;
+            m_cpt_ins_unc_transaction = 0;
+            m_cpt_write_transaction = 0;
+
+            return;
+        }
+
+#if SOCLIB_MODULE_DEBUG
+if ( m_srcid_d == 0 )
+{
+std::cout << std::dec << "CcXcache " << m_srcid_d << " / Time = " << m_cpt_total_cycles << std::endl
+          << "  " << dcache_fsm_state_str[r_dcache_fsm] 
+          << "  " << icache_fsm_state_str[r_icache_fsm]
+          << "  " << cmd_fsm_state_str[r_cmd_fsm] 
+          << "  " << rsp_fsm_state_str[r_rsp_fsm]
+          << "  " << cleanup_fsm_state_str[r_cleanup_fsm]
+          << "  " << tgt_fsm_state_str[r_tgt_fsm] << std::endl;
+}
+#endif
+
+        m_cpt_total_cycles++;
+
+        /////////////////////////////////////////////////////////////////////
+        // The TGT_FSM controls the following ressources:
+        // - r_tgt_fsm
+        // - r_tgt_buf[nwords]
+        // - r_tgt_val[nwords]
+        // - r_tgt_update
+        // - r_tgt_data
+        // - r_tgt_word
+        // - r_tgt_addr
+        // - r_tgt_srcid
+        // - r_tgt_trdid
+        // - r_tgt_pktid
+        // All VCI commands must be CMD_WRITE.
+        // If the VCI address offset is null, the command is an invalidate 
+        // request. It is an update request otherwise.
+        // The VCI_TGT FSM stores the external request arguments in the
+        // IDLE, UPDT_WORD & UPDT_DATA states. It sets the r_tgt_icache_req 
+        // & r_tgt_dcache_req flip-flops to signal the external request to 
+        // the ICACHE & DCACHE FSMs in the REQ states. It waits the completion
+        // of the update or invalidate request in the RSP states.
+        // -  for an invalidate request the VCI packet length is 1 word.
+        // The WDATA field contains the line index (i.e. the Z & Y fields).
+        // -  for an update request the VCI packet length is (n+2) words.
+        // The WDATA field of the first VCI word contains the line index.
+        // The WDATA field of the second VCI word contains the word index.
+        // The WDATA field of the n following words contains the values.
+        // -  for both invalidate & update requests, the VCI response
+        // is one single word.
+        // In case of errors in the VCI command packet, the simulation
+        // is stopped with an error message.
+        /////////////////////////////////////////////////////////////////////
+
+        switch( r_tgt_fsm ) {
+
+            case TGT_IDLE:
+            {
+                if ( p_vci_tgt_c.cmdval.read() ) 
+                {
+                    addr_t address = p_vci_tgt_c.address.read();
+
+                    if ( p_vci_tgt_c.cmd.read() != vci_param::CMD_WRITE) 
+                    {
+                        std::cout << "error in VCI_CC_XCACHE_WRAPPER " << name() << std::endl;
+                        std::cout << "the received coherence request from " << p_vci_tgt_c.srcid.read() 
+                                  << " is not a write" << std::endl;
+                        exit(0);
+                    }
+
+                    if ( (address != 0x3) && (! m_segment.contains(address)) ) 
+                    {
+                        std::cout << "error in VCI_CC_XCACHE_WRAPPER " << name() << std::endl;
+                        std::cout << "out of segment coherence request" << std::endl;
+                        exit(0);
+                    }
+
+                    r_tgt_addr = (((addr_t) ((p_vci_tgt_c.be.read() & 0x3) << 32)) | 
+                                 ((addr_t) (p_vci_tgt_c.wdata.read()))) * m_dcache_words * 4;      
+                    r_tgt_srcid = p_vci_tgt_c.srcid.read();
+                    r_tgt_trdid = p_vci_tgt_c.trdid.read();
+                    r_tgt_pktid = p_vci_tgt_c.pktid.read();
+                    r_tgt_plen  = p_vci_tgt_c.plen.read();
+                    
+                    if ( address == 0x3 ) // broadcast invalidate 
+                    {
+                        if ( ! p_vci_tgt_c.eop.read() ) 
+                        {
+                            std::cout << "error in VCI_CC_XCACHE_WRAPPER " << name() << std::endl;
+                            std::cout << "a broascast request must be one word" << std::endl;
+                            exit(0);
+                        }
+                        r_tgt_update = false; 
+                        r_tgt_brdcast= true;
+                        r_tgt_fsm = TGT_REQ_BROADCAST;
+                        m_cpt_cc_broadcast++;
+                    }
+                    else                    // multicast-update or multicast-invalidate
+                    { 
+                        uint32_t cell = address - m_segment.baseAddress(); 
+                        if (cell == 0)                  // invalidate data
+                        {
+                            if ( ! p_vci_tgt_c.eop.read() ) 
+                            {
+                                std::cout << "error in VCI_CC_XCACHE_WRAPPER " << name() << std::endl;
+                                std::cout << "an invalidate requestn must be one word" << std::endl;
+                                exit(0);
+                            }
+                            r_tgt_brdcast = false;
+                            r_tgt_update  = false; 
+                            r_tgt_data    = true;
+                            r_tgt_fsm = TGT_REQ_DCACHE;
+                            m_cpt_cc_inval_data++;
+                        } 
+                        else if (cell == 4)             // update data
+                        {                                
+                            if ( p_vci_tgt_c.eop.read() ) 
+                            {
+                                std::cout << "error in VCI_CC_VCACHE_WRAPPER " << name() << std::endl;
+                                std::cout << "an update request must be N+2 words" << std::endl;
+                                exit(0);
+                            }
+                            r_tgt_brdcast  = false;
+                            r_tgt_update   = true; 
+                            r_tgt_data     = true;
+                            r_tgt_fsm  = TGT_UPDT_WORD;
+                            m_cpt_cc_update_data++;
+                        } 
+                        else if (cell == 8)              // invalidate instruction
+                        {                         
+                            if ( ! p_vci_tgt_c.eop.read() ) 
+                            {
+                                std::cout << "error in VCI_CC_VCACHE_WRAPPER " << name() << std::endl;
+                                std::cout << "an invalidate request must be one word" << std::endl;
+                                exit(0);
+                            }
+                            r_tgt_brdcast = false;
+                            r_tgt_data    = false;
+                            r_tgt_update  = false; 
+                            r_tgt_fsm = TGT_REQ_ICACHE;
+                            m_cpt_cc_inval_ins++;
+                        } 
+                        else if (cell == 12)             // update ins
+                        {                                
+                            if ( p_vci_tgt_c.eop.read() ) 
+                            {
+                                std::cout << "error in VCI_CC_VCACHE_WRAPPER " << name() << std::endl;
+                                std::cout << "an update request must be N+2 words" << std::endl;
+                                exit(0);
+                            }
+                            r_tgt_brdcast = false;
+                            r_tgt_update  = true; 
+                            r_tgt_data    = false;
+                            r_tgt_fsm = TGT_UPDT_WORD;
+                            m_cpt_cc_update_ins++;
+                        } 
+
+                    } // end if address
+                } // end if cmdval
+                break;
+            }
+            case TGT_UPDT_WORD:
+            {
+                if (p_vci_tgt_c.cmdval.read()) 
+                {
+                    if ( p_vci_tgt_c.eop.read() ) 
+                    {
+                        std::cout << "error in VCI_CC_XCACHE_WRAPPER " << name() << std::endl;
+                        std::cout << "an update command length must be N+2 words" << std::endl;
+                        exit(0);
+                    }
+                    for ( size_t i=0 ; i<m_dcache_words ; i++ ) r_tgt_val[i] = false;
+                    r_tgt_word = p_vci_tgt_c.wdata.read(); // the first modified word index
+                    r_tgt_fsm = TGT_UPDT_DATA;
+                }
+                break;
+            }
+            case TGT_UPDT_DATA:
+            {
+                if (p_vci_tgt_c.cmdval.read()) 
+                {
+                    size_t word = r_tgt_word.read();
+                    if ( word >= m_dcache_words ) 
+                    {
+                        std::cout << "error in VCI_CC_XCACHE_WRAPPER " << name() << std::endl;
+                        std::cout << "the word index in an update request is wrong" << std::endl;
+                        exit(0);
+                    }
+                    r_tgt_buf[word] = p_vci_tgt_c.wdata.read();
+                    if(p_vci_tgt_c.be.read())    r_tgt_val[word] = true;
+                    r_tgt_word = word + 1;
+                    if (p_vci_tgt_c.eop.read()) {
+                        if (r_tgt_data.read())  r_tgt_fsm = TGT_REQ_DCACHE;
+                        else                    r_tgt_fsm = TGT_REQ_ICACHE;
+                    }
+                }
+                break;
+            }
+            case TGT_REQ_ICACHE:
+            {
+                if ( !r_tgt_icache_req.read() ) 
+                {
+                    r_tgt_fsm = TGT_RSP_ICACHE; 
+                    r_tgt_icache_req = true;
+                }
+                break;
+            }
+            case TGT_REQ_DCACHE:
+            {
+                if ( !r_tgt_dcache_req.read() ) 
+                {
+                    r_tgt_fsm = TGT_RSP_DCACHE; 
+                    r_tgt_dcache_req = true;
+                }
+                break;
+            }
+            case TGT_REQ_BROADCAST:
+            {
+                if ( !r_tgt_icache_req.read() && !r_tgt_dcache_req.read() ) 
+                {
+                    r_tgt_fsm = TGT_RSP_BROADCAST; 
+                    r_tgt_icache_req = true;
+                    r_tgt_dcache_req = true;
+                }
+                break;
+            }
+            case TGT_RSP_BROADCAST:
+            {
+                if ( !r_tgt_icache_req.read() && !r_tgt_dcache_req.read() ) 
+                {
+                    // one response
+                    if ( !r_tgt_icache_rsp || !r_tgt_dcache_rsp )
+                    {
+                        if ( p_vci_tgt_c.rspack.read() )
+                        {
+                            r_tgt_fsm = TGT_IDLE; 
+                            r_tgt_icache_rsp = false;
+                            r_tgt_dcache_rsp = false;
+                        }
+                    }
+                    //  two responses  
+                    if ( r_tgt_icache_rsp && r_tgt_dcache_rsp )
+                    {
+                        if ( p_vci_tgt_c.rspack.read() )
+                        {
+                            r_tgt_icache_rsp = false; // reset one to prepare the second response
+                        }
+                    }
+                    // no need for a response
+                    if ( !r_tgt_icache_rsp && !r_tgt_dcache_rsp )
+                    {
+                        r_tgt_fsm = TGT_IDLE;
+                    }
+                }
+                break;
+            }
+            case TGT_RSP_ICACHE:
+            {
+                if ( (p_vci_tgt_c.rspack.read() || !r_tgt_icache_rsp.read()) && !r_tgt_icache_req.read() ) 
+                {
+                    r_tgt_fsm = TGT_IDLE;
+                    r_tgt_icache_rsp = false; 
+                }
+                break;
+            }
+            case TGT_RSP_DCACHE:
+            {
+                if ( (p_vci_tgt_c.rspack.read() || !r_tgt_dcache_rsp.read()) && !r_tgt_dcache_req.read() ) 
+                {
+                    r_tgt_fsm = TGT_IDLE;
+                    r_tgt_dcache_rsp = false; 
+                }
+                break;
+            }
+        } // end switch TGT_FSM
+
+        typename iss_t::InstructionRequest  	ireq;
+        typename iss_t::InstructionResponse 	irsp;
+
+        typename iss_t::DataRequest  		dreq;
+        typename iss_t::DataResponse 		drsp;
+
+        ireq.valid = false;
+        dreq.valid = false;
+        irsp.valid = false;
+        irsp.error = false;
+        drsp.valid = false;
+        drsp.error = false;
+
+        m_iss.getRequests( ireq, dreq );
+
+        //////////////////////////////////////////////////////////////////////////////
+        // The ICACHE FSM controls the following ressources:
+        // - r_icache_fsm
+        // - r_icache_fsm_save
+        // - r_icache (read & write)
+        // - r_icache_addr_save
+        // - r_icache_miss_req (set)
+        // - r_icache_unc_req (set)
+        // - r_rsp_ins_ok (reset)
+        // - r_rsp_ins_error (reset)
+        // - r_tgt_icache_req (reset)
+        // - r_tgt_icache_rsp
+        // - r_icache_cleanup_req (set)
+        // - r_icache_cleanup_line
+        // - ireq & irsp structures (communication with the processor)
+        //
+        // 1/ External coherence requests (update or invalidate) 
+        //    There is an external request when the r_tgt_icache_req flip-flop is set,
+        //    These requests are taken into account in the IDLE and WAIT states.
+        //    In case of external request the ICACHE FSM goes to the CC_CHECK
+        //    state to test the external hit, and returns in the
+        //    pre-empted state after this external request is completed.
+        //
+        // 2/ Processor requests are taken into account only in the IDLE state.
+        //    The cache access takes into account the cacheability_table.
+        //    In case of MISS, or in case of uncachable instruction, the FSM 
+        //    writes the missing address line in the  r_icache_addr_save register 
+        //    and sets the r_icache_miss_req or the r_icache_unc_req flip-flops.
+        //    These request flip-flops are reset by the CMD FSM.
+        //    The r_rsp_ins_ok flip-flop is set by the RSP FSM when the 
+        //    transaction is completed. In case of bus error, the RSP FSM sets 
+        //    the r_rsp_ins_error flip-flop. They must be reset by the ICACHE FSM.
+        //   - CACHED READ MISS => to the MISS_WAIT state, waiting the r_rsp_ins_ok signal.
+        //     It can be delayed in the MISS_DELAY state in case of matching pending
+        //     cleanup request.  Then it goes to the MISS_UPDT state, then to the CLEANUP_REQ
+        //     state (if necessary), and finally to the IDLE state.
+        //   - UNCACHED READ  => to the UNC_WAIT state (waiting the r_rsp_ins_ok signal), 
+        //     and back to the IDLE state. 
+        ////////////////////////////////////////////////////////////////////////////////////
+
+        switch(r_icache_fsm) {
+ 
+        case ICACHE_IDLE:
+        {
+            if ( r_tgt_icache_req )    // external request
+            {
+                if ( ireq.valid ) m_cost_ins_miss_frz++;
+                r_icache_fsm = ICACHE_CC_CHECK;
+                r_icache_fsm_save = r_icache_fsm;
+                break;
+            } 
+            if ( ireq.valid ) 
+            {
+                data_t  icache_ins;
+                bool    icache_cachable = m_cacheability_table[(addr_t)ireq.addr];
+                m_cpt_icache_dir_read += m_icache_ways;
+                m_cpt_icache_data_read += m_icache_ways;
+                if ( icache_cachable ) 
+                {
+                    if ( r_icache.read((addr_t)ireq.addr, &icache_ins) ) 	// hit
+                    {
+                        r_icache_fsm        = ICACHE_IDLE;
+                        irsp.valid          = true;
+                        irsp.instruction    = icache_ins;
+                    }
+                    else                                           		// miss
+                    {
+                        m_cpt_ins_miss++;
+                        m_cost_ins_miss_frz++;
+                        // if the missing line corresponds to a pending cleanup
+                        // the miss request to the CMD FSM must be delayed
+                        if ( r_icache_cleanup_req && 
+                           ((addr_t)r_icache_cleanup_line == (addr_t)(ireq.addr/(m_icache_words*4))) ) 
+                        {
+                            break;
+                        }
+                        else
+                        {
+                            r_icache_fsm 	= ICACHE_MISS_SELECT;
+                            r_icache_addr_save  = ireq.addr;
+                            r_icache_miss_req 	= true;
+                            r_rsp_ins_ok	= false;
+                        }
+                    }
+                }
+                else                        // uncachable instruction
+                {
+                    m_cpt_ins_unc++;
+                    m_cost_ins_miss_frz++;
+                    r_icache_addr_save      = ireq.addr;
+                    r_icache_fsm            = ICACHE_UNC_WAIT;
+                    r_icache_unc_req        = true;
+                    r_rsp_ins_ok            = false;
+                }
+            }
+            break;
+        }
+        case ICACHE_MISS_SELECT: // select a victim 
+        {
+            m_cost_ins_miss_frz++;
+            size_t	way;
+            addr_t	index;
+            addr_t  ad = r_icache_addr_save;
+            if ( r_icache.select_before_update( ad, &way, &index) )
+            {
+                r_icache_fsm          = ICACHE_MISS_CLEANUP; 
+                r_icache_cleanup_save = index;
+                r_icache_way_save     = way;
+            }
+            else
+            {
+                r_icache_way_save     = way;
+                r_icache_fsm          = ICACHE_MISS_WAIT;
+            }
+            break;
+        }
+        case ICACHE_MISS_CLEANUP: // try to post a cleanup request to the CLEANUP FSM
+        {
+            m_cost_ins_miss_frz++;
+            if ( r_tgt_icache_req )    // coherence request 
+            {
+                r_icache_fsm = ICACHE_CC_CHECK;
+                r_icache_fsm_save = r_icache_fsm;
+                break;
+            } 
+            if ( !r_icache_cleanup_req )	// no pending cleanup
+            {
+                r_icache_cleanup_req 	= true;
+                r_icache_cleanup_line   = r_icache_cleanup_save;
+                r_icache_fsm	    	= ICACHE_MISS_WAIT;
+            }
+            break;                
+        }
+        case ICACHE_MISS_WAIT:  // waiting the response from the RSP FSM
+        {
+            m_cost_ins_miss_frz++;
+            if ( r_tgt_icache_req )    // coherence request
+            {
+                r_icache_fsm = ICACHE_CC_CHECK;
+                r_icache_fsm_save = r_icache_fsm;
+                break;
+            } 
+            if ( r_rsp_ins_ok )  // there is a response
+            {
+                if      ( r_rsp_ins_error )		r_icache_fsm = ICACHE_ERROR;
+                else if ( !r_icache_inval_pending )	r_icache_fsm = ICACHE_MISS_UPDT;
+                else
+                {
+                    if ( r_icache_cleanup_req ) 
+                    {
+                        break;
+                    }
+                    else
+                    {
+                        // the cache is not updated in case of pending inval 
+                        r_icache_cleanup_req = true;
+                        r_icache_cleanup_line = r_icache_addr_save.read() >> (uint32_log2(m_icache_words) + 2);
+                        r_icache_fsm = ICACHE_IDLE;
+                        r_icache_inval_pending = false;
+                    }
+                }
+            }
+            break;
+        }
+        case ICACHE_MISS_UPDT:  // update the cache 
+        {
+            m_cost_ins_miss_frz++;
+            m_cpt_icache_dir_write++;
+            m_cpt_icache_data_write++;
+            addr_t 	ad   	= (addr_t) r_icache_addr_save;
+            data_t*   	buf   	= (data_t*) r_icache_miss_buf;
+            size_t	way	= (size_t) r_icache_way_save;
+            r_icache.update_after_select( buf, way, ad );
+            r_icache_fsm = ICACHE_IDLE;
+            break;
+        }
+        case ICACHE_UNC_WAIT:
+        {
+            m_cost_ins_miss_frz++;
+            if ( r_tgt_icache_req )    // external request
+            {
+                r_icache_fsm = ICACHE_CC_CHECK;
+                r_icache_fsm_save = r_icache_fsm;
+                break;
+            } 
+            if ( r_rsp_ins_ok ) 
+            {
+                if ( r_rsp_ins_error ) 	r_icache_fsm = ICACHE_ERROR;
+                else 			r_icache_fsm = ICACHE_UNC_GO;
+            }
+            break;
+        }
+        case ICACHE_UNC_GO:
+        {
+            r_icache_fsm    = ICACHE_IDLE;
+            if( ireq.addr == r_icache_addr_save )
+            {
+                irsp.valid          = true;
+                irsp.instruction    = r_icache_miss_buf[0];
+            }
+        }
+        case ICACHE_ERROR:
+        {
+            r_icache_fsm 	= ICACHE_IDLE;
+            r_rsp_ins_error     = false;
+            irsp.error          = true;
+            irsp.valid          = true;
+            break;
+        } 
+        case ICACHE_CC_CHECK:   // read directory in case of external request
+        {
+            m_cpt_icache_dir_read += m_icache_ways;
+            m_cpt_icache_data_read += m_icache_ways;
+            if ( ( (r_icache_fsm_save == ICACHE_MISS_WAIT) || (r_icache_fsm_save == ICACHE_MISS_CLEANUP) ) && 
+                ((r_icache_addr_save & ~((m_icache_words<<2)-1))==(r_tgt_addr & ~((m_icache_words<<2)-1))))
+                 // the external request matches a miss
+            {
+                r_icache_inval_pending 	= true;
+                r_tgt_icache_req       	= false;
+                r_tgt_icache_rsp       	= r_tgt_update;  // always a response in case of update 
+                r_icache_fsm 		= r_icache_fsm_save;
+            } 
+            else  // the external request is not matching a pending miss
+            {
+                data_t  data;
+                bool    icache_hit   	= r_icache.read(r_tgt_addr, &data);
+                if ( icache_hit && r_tgt_update )  // hit update
+                {
+                    r_icache_fsm = ICACHE_CC_UPDT;
+                } 
+                else if ( icache_hit && !r_tgt_update ) // hit inval
+                {
+                    r_icache_fsm = ICACHE_CC_INVAL;
+                } 
+                else	// miss 
+                { 
+                    r_tgt_icache_req 	= false;
+                    r_tgt_icache_rsp 	= r_tgt_update; // alaways a response in case of update
+                    r_icache_fsm 	= r_icache_fsm_save;
+                }
+            }
+            break;
+        }
+        case ICACHE_CC_UPDT:    // update the cache line        
+        {
+            m_cpt_icache_dir_write++;
+            m_cpt_icache_data_write++;
+            for(size_t i=0; i<m_icache_words; i++)
+            {
+                if(r_tgt_val[i]) r_icache.write( (r_tgt_addr + i*4), r_tgt_buf[i] );
+            }
+            r_tgt_icache_rsp = true;
+            r_tgt_icache_req = false;
+            r_icache_fsm = r_icache_fsm_save;
+            break;
+        }
+        case ICACHE_CC_INVAL:   // invalidate a cache line
+        {
+            r_icache.inval(r_tgt_addr);
+            r_tgt_icache_rsp = true;
+            r_tgt_icache_req = false;
+            r_icache_fsm = r_icache_fsm_save;
+            break;
+        }
+        } // end switch r_icache_fsm
+
+        //////////////////////////////////////////////////////////////////////://///////////
+        // The DCACHE FSM controls the following ressources:
+        // - r_dcache_fsm
+        // - r_dcache_fsm_save
+        // - r_dcache (read and write)
+        // - r_dcache_addr_save
+        // - r_dcache_wdata_save
+        // - r_dcache_rdata_save
+        // - r_dcache_type_save
+        // - r_dcache_be_save
+        // - r_dcache_miss_req (set)
+        // - r_dcache_unc_req (set)
+        // - r_rsp_data_ok (reset)
+        // - r_rsp_data_error (reset)
+        // - r_dcache_cleanup_req (set)
+        // - r_dcache_cleanup_ine
+        // - r_tgt_dcache_req (reset)
+        // - r_tgt_dcache_rsp
+        // - r_wbuf (write)
+        // - dreq & drsp structures (communication with the processor)
+        //
+        // 1/ external request (invalidate or update)
+        //    There is an external request when the r_tgt_dcache_req flip-flop is set.
+        //    External requests are taken into account in the states  IDLE, WRITE_REQ,  
+        //    UNC_WAIT, MISS_WAIT, and have the highest priority :
+        //    The actions associated to the pre-empted state are not executed, the DCACHE FSM
+        //    goes to the CC_CHECK state to execute the requested action, and returns to the
+        //    pre-empted state.
+        //
+        //  2/ processor request  
+        //   In order to support VCI write burst, the processor requests are taken into account
+        //   in the WRITE_REQ state as well as in the IDLE state.
+        // - In IDLE state, the request is satisfied if it is a cachable read hit, 
+        //   an XTN request, or a cachable write. 
+        // - In WRITE_REQ state, the request is satisfied if it is a cachable read hit,
+        //   an XTN request, or a write when the write buffer is not full.
+        // - Both the uncachable read and the uncachable write requests block the processor
+        //   until the corresponding VCI transaction is completed.
+        //
+        //   The cache access takes into account the cacheability_table.
+        //   In case of processor request, there is six conditions to exit the IDLE state:
+        //   - CACHED READ MISS => to the MISS_WAIT state (waiting r_rsp_data_ok),
+        //     then to the MISS_UPDT state, and finally to the IDLE state.
+        //   - UNCACHED READ or WRITE => to the UNC_WAIT state (waiting r_rsp_data_ok),
+        //     then to the UNC_GO state, and finally to the IDLE state.
+        //   - XTN_INVAL => to the INVAL state for one cycle, then to IDLE state.
+        //   - XTN_SYNC  => to the SYNC state until write buffer empty, then to IDLE state.
+        //   - WRITE MISS => directly to the WRITE_REQ state to access the write buffer.
+        //   - WRITE HIT => to the WRITE_UPDT state, then to the WRITE_REQ state.
+        //
+        //   All LL or SC requests are handled as uncachable.
+        //
+        // Error handling :  Read Bus Errors are synchronous events, but
+        // Write Bus Errors are asynchronous events (processor is not frozen).
+        // - If a Read Bus Error is detected, the VCI_RSP FSM sets the
+        //   r_rsp_data_error flip-flop, and the synchronous error is signaled
+        //   by the DCACHE FSM.
+        // - If a Write Bus Error is detected, the VCI_RSP FSM  signals
+        //   the asynchronous error using the setWriteBerr() method.
+        ///////////////////////////////////////////////////////////////////////////////////
+
+        switch ( r_dcache_fsm ) {
+
+        case DCACHE_WRITE_REQ:
+	{
+            if ( r_tgt_dcache_req )    // coherence request
+            {
+                r_dcache_fsm = DCACHE_CC_CHECK;
+                r_dcache_fsm_save = r_dcache_fsm;
+                break;
+            }
+            if( !r_wbuf.write(r_dcache_addr_save, r_dcache_be_save, r_dcache_wdata_save) ) 
+            {
+                // stay in DCACHE_WRITEREQ state if the write request is not accepted 
+                m_cost_write_frz++;
+                break;
+            }
+                // If the write request is accepted by the write buffer
+                // the next state and the response to processor request are evaluated
+                // as in the DCACHE_IDLE state  below ...
+        }     
+        case DCACHE_IDLE:
+        {
+            if ( r_tgt_dcache_req )   // coherence request
+            {
+                r_dcache_fsm = DCACHE_CC_CHECK;
+                r_dcache_fsm_save = r_dcache_fsm;
+                break;
+            } 
+            if ( dreq.valid ) 
+            {              
+                bool        dcache_hit;
+                data_t      dcache_rdata;
+                bool        dcache_cachable;
+
+                // dcache_cachable, dcache_hit & dcache_rdata evaluation
+                m_cpt_dcache_data_read += m_dcache_ways;
+                m_cpt_dcache_dir_read += m_dcache_ways;
+                dcache_cachable     = m_cacheability_table[dreq.addr];
+                dcache_hit          = r_dcache.read(dreq.addr, &dcache_rdata);
+
+                // Save data request 
+                r_dcache_addr_save      = dreq.addr;
+                r_dcache_type_save      = dreq.type;
+                r_dcache_wdata_save     = dreq.wdata;
+                r_dcache_be_save        = dreq.be;
+                r_dcache_rdata_save     = dcache_rdata;
+
+                // reset r_rsp_data_ok
+                r_rsp_data_ok               = false;
+
+                // next FSM state, request to VCI, and processor response 
+                if(dreq.type  == iss_t::DATA_READ)
+                {
+                    if(!dcache_cachable)                              // uncachable read 
+                    {
+                        m_cpt_data_unc++;
+                        m_cost_unc_frz++;
+                        r_dcache_unc_req            = true;
+                        r_dcache_fsm                = DCACHE_UNC_WAIT;
+                    }
+                    else
+                    {
+                        m_cpt_read++;
+                        if(dcache_hit)                               // cachable read hit
+                        {
+                            drsp.valid         	= true;
+                            drsp.rdata          = dcache_rdata;
+                            r_dcache_fsm  	= DCACHE_IDLE;
+                        }
+                        else                                         // cachable read miss
+                        {
+                            m_cost_data_miss_frz++;
+                            // if the missing line corresponds to a pending cleanup
+                            // the miss request to the CMD FSM must be delayed
+                            if ( r_dcache_cleanup_req &&
+                               ((addr_t)r_dcache_cleanup_line == (addr_t)(dreq.addr/(m_dcache_words*4))) )
+                            {
+                                break;
+                            }
+                            else
+                            {
+                                m_cpt_data_miss++;
+                                r_dcache_miss_req       = true;
+                                r_dcache_fsm 		= DCACHE_MISS_SELECT;
+                            }
+                        }
+                    }
+                }
+                else if(dreq.type == iss_t::DATA_WRITE)
+                {
+                    if(!dcache_cachable)                              // uncachable write
+                    {
+                        m_cpt_data_unc++;
+                        m_cost_unc_frz++;
+                        r_dcache_unc_req       	= true;
+                        r_dcache_fsm           	= DCACHE_UNC_WAIT;
+                    }
+                    else
+                    {
+                        m_cpt_write++;
+                        if(!dcache_hit)                              // cachable write miss 
+                        {
+                            drsp.rdata         	= 0;
+                            drsp.valid         	= true;
+                            r_dcache_fsm       	= DCACHE_WRITE_REQ;
+                        }
+                        else                                         // cachable write hit 
+                        {
+                            m_cpt_write_cached++;
+                            drsp.rdata         	= 0;
+                            drsp.valid         	= true;
+                            r_dcache_fsm       	= DCACHE_WRITE_UPDT;
+                        }
+                    }
+                }
+                else if(dreq.type == iss_t::DATA_LL)                        // linked read
+                //  all LL  requests are handled as uncachable  
+                {
+                    m_cpt_ll++;
+                    m_cost_unc_frz++;
+                    r_dcache_unc_req           	= true;
+                    r_dcache_fsm               	= DCACHE_UNC_WAIT;
+                }
+                else if(dreq.type == iss_t::DATA_SC)                        // conditional write
+                //  all SC requests are handled as uncachable   
+                {
+                    m_cpt_sc++;
+                    m_cost_unc_frz++;
+                    r_dcache_unc_req           	= true;
+                    r_dcache_fsm               	= DCACHE_UNC_WAIT;
+                }
+                else if((dreq.type == iss_t::XTN_WRITE) || (dreq.type == iss_t::XTN_READ))  // XTN access
+                // only INVAL & SYNC requests are supported
+                {
+                    drsp.valid = true;
+                    drsp.rdata = 0;
+                    if ( dreq.addr/4 == iss_t::XTN_DCACHE_INVAL )
+                    {
+                        r_dcache_fsm = DCACHE_INVAL;
+                    }
+                    else if ( dreq.addr/4 == iss_t::XTN_SYNC )
+                    {
+                        r_dcache_fsm = DCACHE_SYNC;
+                    }
+                    else if ( dreq.addr/4 == iss_t::XTN_TLB_MODE )
+                    {
+                        r_dcache_fsm = DCACHE_IDLE;
+                    }
+                    else
+                    {
+                        std::cout << "warning in VCI_CC_XCACHE_WRAPPER " << name() << std::endl;
+                        std::cout << "unsupported  external access : " << dreq.addr/4 << std::endl;
+                        std::cout << "only TLB_MODE, DCACHE_INVAL & SYNC are supported" << std::endl;
+                    }
+                }
+            }
+            else // no dreq.valid
+            {
+                r_dcache_fsm = DCACHE_IDLE;
+                drsp.valid = true;
+                drsp.rdata = 0;
+            }
+            break;
+        }
+        case DCACHE_WRITE_UPDT:
+        {
+            m_cpt_dcache_data_write++;
+            data_t mask = vci_param::be2mask(r_dcache_be_save);
+            data_t wdata = (mask & r_dcache_wdata_save) | (~mask & r_dcache_rdata_save);
+            r_dcache.write( r_dcache_addr_save, wdata );
+            r_dcache_fsm = DCACHE_WRITE_REQ;
+            break;
+        }
+        case DCACHE_MISS_SELECT: // select a victim
+        {
+            m_cost_data_miss_frz++;
+            size_t	way;
+            addr_t	index;
+            addr_t    	addr = r_dcache_addr_save;
+            if ( r_dcache.select_before_update( addr, &way, &index) )
+            {
+                r_dcache_fsm          = DCACHE_MISS_CLEANUP; 
+                r_dcache_cleanup_save = index;
+                r_dcache_way_save     = way;
+            }
+            else
+            {
+                r_dcache_way_save     = way;
+                r_dcache_fsm          = DCACHE_MISS_WAIT;
+            }
+            break;
+        }
+        case DCACHE_MISS_CLEANUP: // try to post a cleanup request to the CLEANUP FSM
+        {
+            m_cost_data_miss_frz++;
+            if ( r_tgt_dcache_req )    // coherence request 
+            {
+                r_dcache_fsm = DCACHE_CC_CHECK;
+                r_dcache_fsm_save = r_dcache_fsm;
+                break;
+            } 
+            if ( !r_dcache_cleanup_req )	// no pending cleanup
+            {
+                r_dcache_cleanup_req 	= true;
+                r_dcache_cleanup_line   = r_dcache_cleanup_save;
+                r_dcache_fsm		= DCACHE_MISS_WAIT;
+            }
+            break;                
+        }
+        case DCACHE_MISS_WAIT:  // waiting the response from the RSP FSM
+        {
+            m_cost_data_miss_frz++;
+            if ( r_tgt_dcache_req )    // coherence request
+            {
+                r_dcache_fsm = DCACHE_CC_CHECK;
+                r_dcache_fsm_save = r_dcache_fsm;
+                break;
+            } 
+            if ( r_rsp_data_ok )  // there is a response
+            {
+                if      ( r_rsp_data_error )		r_dcache_fsm = DCACHE_ERROR;
+                else if ( !r_dcache_inval_pending )	r_dcache_fsm = DCACHE_MISS_UPDT;
+                else
+                {
+                    if ( r_dcache_cleanup_req ) 
+                    {
+                        break;
+                    }
+                    else
+                    {
+                        // the cache is not updated in case of pending inval
+                        r_dcache_cleanup_req = true;
+                        r_dcache_cleanup_line = r_dcache_addr_save >> (uint32_log2(m_icache_words) + 2);
+                        r_dcache_fsm = DCACHE_IDLE;
+                        r_dcache_inval_pending = false;
+                    }
+                }
+            }
+            break;
+        }
+        case DCACHE_MISS_UPDT:  // update the cache 
+        {
+            m_cost_data_miss_frz++;
+            m_cpt_dcache_dir_write++;
+            m_cpt_dcache_data_write++;
+            addr_t 	ad   	= (addr_t) r_dcache_addr_save;
+            data_t*   	buf   	= (data_t*) r_dcache_miss_buf;
+            size_t	way	= (size_t) r_dcache_way_save;
+            r_dcache.update_after_select( buf, way, ad );
+            r_dcache_fsm = DCACHE_IDLE;
+            break;
+        }
+        case DCACHE_UNC_WAIT:
+        {
+            if ( dreq.valid ) m_cost_unc_frz++;
+            if ( r_tgt_dcache_req )    // external request
+            {
+                r_dcache_fsm = DCACHE_CC_CHECK;
+                r_dcache_fsm_save = r_dcache_fsm;
+                break;
+            } 
+            if ( r_rsp_data_ok ) 
+            {
+                if ( r_rsp_data_error ) 	r_dcache_fsm = DCACHE_ERROR;
+                else 				r_dcache_fsm = DCACHE_UNC_GO;
+            }
+            break;
+        }
+        case DCACHE_UNC_GO:
+        {
+            r_dcache_fsm = DCACHE_IDLE;
+            drsp.valid = true;
+            drsp.rdata = r_dcache_miss_buf[0];
+            break;
+        }
+        case DCACHE_ERROR:
+        {
+            r_dcache_fsm = DCACHE_IDLE;
+            r_rsp_data_error = false;
+            drsp.error = true;
+            drsp.valid = true;
+            break;
+        }
+        case DCACHE_INVAL:  // local inval requiring a cleanup in case of hit
+        {
+            if( !r_dcache_cleanup_req )
+            {
+                m_cpt_dcache_dir_read += m_dcache_ways;
+                r_dcache_cleanup_req = r_dcache.inval( r_dcache_addr_save );
+                r_dcache_cleanup_line = r_dcache_addr_save.read() >> (uint32_log2(m_dcache_words)+2);
+                r_dcache_fsm = DCACHE_IDLE;
+            }
+            break;
+        }
+        case DCACHE_SYNC:
+        {
+            if ( r_wbuf.empty() ) r_dcache_fsm = DCACHE_IDLE; 
+            break;
+        }
+        case DCACHE_CC_CHECK:   // read directory in case of external request
+        {
+            m_cpt_dcache_dir_read += m_dcache_ways;
+            m_cpt_dcache_data_read += m_dcache_ways;
+            if ( ( (r_dcache_fsm_save == DCACHE_MISS_WAIT) || (r_dcache_fsm_save == DCACHE_MISS_CLEANUP) ) && 
+            ((r_dcache_addr_save & ~((m_dcache_words<<2)-1))==(r_tgt_addr & ~((m_dcache_words<<2)-1))))
+                    // external request matches a miss
+            {
+                r_dcache_inval_pending 	= true;
+                r_tgt_dcache_req       	= false;
+                r_tgt_dcache_rsp       	= r_tgt_update; // always a response to an update
+                r_dcache_fsm 		= r_dcache_fsm_save;
+            } 
+            else  // the external request is not matching a pending miss
+            {
+                data_t  data;
+                bool    dcache_hit   	= r_dcache.read(r_tgt_addr, &data);
+                if ( dcache_hit && r_tgt_update )  // hit update
+                {
+                    r_dcache_fsm = DCACHE_CC_UPDT;
+                } 
+                else if ( dcache_hit && !r_tgt_update ) // hit inval
+                {
+                    r_dcache_fsm = DCACHE_CC_INVAL;
+                } 
+                else	// miss 
+                { 
+                    r_tgt_dcache_req = false;
+                    r_tgt_dcache_rsp = r_tgt_update;  // always a respons in case of update
+                    r_dcache_fsm = r_dcache_fsm_save;
+                }
+            }
+            break;
+        }   
+        case DCACHE_CC_UPDT:    // update the cache line        
+        {
+            m_cpt_dcache_dir_write++;
+            m_cpt_dcache_data_write++;
+            for(size_t i=0; i<m_dcache_words; i++)
+            {
+                if(r_tgt_val[i]) r_dcache.write( (r_tgt_addr + i*4), r_tgt_buf[i] );
+            }
+            r_tgt_dcache_rsp = true;
+            r_tgt_dcache_req = false;
+            r_dcache_fsm = r_dcache_fsm_save;
+            break;
+        }
+        case DCACHE_CC_INVAL:   // invalidate a cache line
+        {        
+                r_dcache.inval(r_tgt_addr);
+                r_tgt_dcache_rsp = true;
+                r_tgt_dcache_req = false;
+                r_dcache_fsm = r_dcache_fsm_save;
+                break;
+        }
+        } // end switch r_dcache_fsm
+
+        ////////// write buffer state update  /////////////
+        // The update() method must be called at each cycle to update the internal state.
+        // All pending write requests must be locked in case of SYNC or in case of MISS.
+        if( (r_dcache_fsm == DCACHE_SYNC) || (r_dcache_fsm == DCACHE_MISS_WAIT) )
+        {
+            r_wbuf.update(true);
+        }
+        else
+        {
+            r_wbuf.update(false);
+        }
+
+#if SOCLIB_MODULE_DEBUG
+std::cout << ireq << std::endl << irsp << std::endl << dreq << std::endl << drsp << std::endl;
+#endif
+
+        /////////// execute one iss cycle /////////////////////////////////////////////
+        {
+            uint32_t it = 0;
+            for (size_t i=0; i<(size_t)iss_t::n_irq; i++) 
+                if(p_irq[i].read()) it |= (1<<i);
+            m_iss.executeNCycles(1, irsp, drsp, it);
+        }
+
+        if ( (ireq.valid && !irsp.valid) || (dreq.valid && !drsp.valid) ) m_cpt_frz_cycles++;
+
+        ////////////////////////////////////////////////////////////////////////////
+        // This CLEANUP FSM controls the transmission of the cleanup transactions
+        // on the coherence network. It controls the following ressources:
+        // - r_cleanup_fsm
+        // - r_dcache_cleanup_req (reset)
+        // - r_icache_cleanup_req (reset)
+        // 
+        // This FSM handles cleanup requests from both the DCACHE FSM & ICACHE FSM
+        // - Instruction Cleanup  : r_icache_cleanup_req 
+        // - Data Cleanup         : r_dcache_cleanup_req 
+        // In case of simultaneous requests, the data request have highest priority.
+        // There is only one cleanup transaction at a given time (sequencial behavior)
+        // because the same FSM controls both command & response. 
+        // The the r_icache_cleanup_req & r_dcache_cleanup_req are reset only
+        // when the response packet is received.
+        // Error handling :
+        // As the coherence trafic is controled by hardware, errors are not reported
+        // to software : In case of errors, the simulation stops.
+        ////////////////////////////////////////////////////////////////////////////
+
+        switch (r_cleanup_fsm) {
+
+            case CLEANUP_IDLE:
+            {    
+                if ( p_vci_ini_c.cmdack )
+                {
+                    if      (r_dcache_cleanup_req) 	r_cleanup_fsm = CLEANUP_DCACHE;
+                    else if (r_icache_cleanup_req) 	r_cleanup_fsm = CLEANUP_ICACHE;
+                }
+                break;
+            }
+            case CLEANUP_DCACHE:
+            {
+                if ( p_vci_ini_c.rspval )
+                {
+                    assert( p_vci_ini_c.reop && (p_vci_ini_c.rtrdid.read() == 0) &&
+                      "illegal response packet received for a cleanup transaction");
+                    assert( (p_vci_ini_c.rerror.read() == vci_param::ERR_NORMAL) && 
+                      "error signaled in a cleanup response" );
+                    
+                    r_cleanup_fsm = CLEANUP_IDLE;
+                    r_dcache_cleanup_req = false;
+                    m_cpt_cc_cleanup_data++;
+                }
+                break;
+            }
+            case CLEANUP_ICACHE:
+            {
+                if ( p_vci_ini_c.rspval )
+                {
+                    assert( p_vci_ini_c.reop && (p_vci_ini_c.rtrdid.read() == 1) &&
+                      "illegal response packet received for a cleanup transaction");
+                    assert( (p_vci_ini_c.rerror.read() == vci_param::ERR_NORMAL) && 
+                      "error signaled in a cleanup response" );
+                    
+                    r_cleanup_fsm = CLEANUP_IDLE;
+                    r_icache_cleanup_req = false;
+                    m_cpt_cc_cleanup_ins++;
+                }
+                break;
+            }
+        } // end switch r_cleanup_fsm    
+        
+        ////////////////////////////////////////////////////////////////////////////
+        // The CMD FSM controls the transmission of read & write requests
+        // on the direct network. It controls the following ressources:
+        // - r_cmd_fsm
+        // - r_cmd_min
+        // - r_cmd_max
+        // - r_cmd_cpt
+        // - r_dcache_miss_req reset
+        // - r_dcache_unc_req reset
+        // - r_icache_miss_req reset
+        // - r_icache_unc_req reset
+        // - wbuf sent()
+        //
+        // This FSM handles requests from both the DCACHE FSM & the ICACHE FSM.
+        // There is 5 request types, with the following priorities : 
+        // 1 - Data Read Miss       : r_dcache_miss_req (if no hit in the write buffer)
+        // 2 - Data Read Uncachable   : r_dcache_unc_req (if no hit in the write buffer)
+        // 3 - Instruction Miss     : r_icache_miss_req (if no hit in the write buffer)
+        // 4 - Instruction Uncachable : r_icache_unc_req (if no hit in the write buffer)
+        // 5 - Data Write           : r_wbuf.rok()      
+        // The read requests have highest priority, because the processor is blocked.
+        //
+        // VCI formats:
+        // According to the VCI advanced specification, all read requests packets 
+        // (read Uncachable, Miss data, Miss instruction) are one word packets.
+        // For write burst packets, all words must be in the same cache line,
+        // and addresses must be contiguous (the BE field is 0 in case of "holes").
+        // The PLEN VCI field is always documented.
+        // As simultaneous VCI transactions are supported, the TRDID field is used:
+        // - Write transactions : TRDID = wbuf_index + (1<<(trdid_size-1))
+        // - Read transactions  : TRDID = 2*cachable + instruction  
+        ///////////////////////////////////////////////////////////////////////////////////
+
+        switch (r_cmd_fsm) {
+
+            case CMD_IDLE:
+            {
+                size_t	min;
+                size_t	max;
+                if ( r_dcache_miss_req & r_wbuf.miss( r_dcache_addr_save ) )
+                { 
+                    r_cmd_fsm = CMD_DATA_MISS;
+                    r_dcache_miss_req = false;
+                    m_cpt_dmiss_transaction++; 
+                } 
+                else if ( r_icache_miss_req & r_wbuf.miss( r_icache_addr_save ) )
+                { 
+                    r_cmd_fsm = CMD_INS_MISS; 
+                    r_icache_miss_req = false;
+                    m_cpt_imiss_transaction++;
+                } 
+                else if ( r_wbuf.rok(&min, &max) ) 
+                { 
+                    r_cmd_fsm = CMD_DATA_WRITE;
+                    r_cmd_cpt = min;
+                    r_cmd_min = min;
+                    r_cmd_max = max;
+                    m_cpt_write_transaction++; 
+                    m_length_write_transaction += (max-min+1); 
+                } 
+                else if ( r_dcache_unc_req )
+                { 
+                    r_cmd_fsm = CMD_DATA_UNC;
+                    r_dcache_unc_req = false;
+                    m_cpt_data_unc_transaction++; 
+                }
+                else if ( r_icache_unc_req )
+                { 
+                    r_cmd_fsm = CMD_INS_UNC; 
+                    r_icache_unc_req = false;
+                    m_cpt_ins_unc_transaction++;
+                }
+                break;
+            }
+            case CMD_DATA_WRITE:
+            {
+                if ( p_vci_ini_d.cmdack.read() ) 
+                {
+                    r_cmd_cpt = r_cmd_cpt + 1;
+                    if (r_cmd_cpt == r_cmd_max) 
+                    {
+                        r_cmd_fsm = CMD_IDLE ;
+                        r_wbuf.sent() ;
+                    }
+                }
+                break;
+            }
+            case CMD_INS_MISS:
+            case CMD_INS_UNC:
+            case CMD_DATA_MISS:
+            case CMD_DATA_UNC:
+            {
+                if ( p_vci_ini_d.cmdack.read() )  r_cmd_fsm = CMD_IDLE;
+                break;
+            }
+        } // end  switch r_cmd_fsm
+
+        //////////////////////////////////////////////////////////////////////////
+        // The RSP FSM receive the response packets on the direct network.
+        // It controls the following ressources:
+        // - r_rsp_fsm:
+        // - r_icache_miss_buf[m_icache_words]
+        // - r_dcache_miss_buf[m_dcache_words]
+        // - r_icache_miss_req reset
+        // - r_icache_unc_req reset
+        // - r_dcache_miss_req reset
+        // - r_dcache_unc_req reset
+        // - r_icache_cleanup_req reset
+        // - r_dcache_cleanup_req reset
+        // - r_rsp_data_ok set
+        // - r_rsp_ins_ok set
+        // - r_rsp_data_error set
+        // - r_rsp_ins_error set
+        // - r_rsp_cpt
+        // 
+        // VCI formats:
+        // This component accepts only single word write response packets. 
+        // As simultaneous VCI transactions are supported, the TRDID field is used:
+        // - Write transactions : TRDID = wbuf_index + (1<<(trdid_size-1))
+        // - Read transactions  : TRDID = 2*cachable + instruction  
+        //
+        // Error handling:
+        // - In case of Write error, the error is directly signaled by the RSP FSM.
+        // - In case of Read Data Error, the VCI_RSP FSM sets the r_rsp_data_error 
+        //   flip_flop and the error is signaled by the DCACHE FSM.  
+        // - In case of Instruction Error, the VCI_RSP FSM sets the r_rsp_ins_error 
+        //   flip_flop and the error is signaled by the ICACHE FSM.  
+        //////////////////////////////////////////////////////////////////////////
+        // Implementation note
+        // It should be possible to save one cycle on the MISS cost by a simple
+        // modification of this RSP FSM : The first flit of a valid response
+        // could be decoded and handled directly in the IDLE state.
+        // The computation of the RSPACK condition become more complex... 
+        //////////////////////////////////////////////////////////////////////////: 
+
+        switch (r_rsp_fsm) {
+
+        case RSP_IDLE:
+        {
+            if( p_vci_ini_d.rspval.read() )
+            {
+                r_rsp_cpt = 0;
+                if ( (p_vci_ini_d.rtrdid.read()>>(vci_param::T-1)) != 0 )	r_rsp_fsm = RSP_DATA_WRITE;
+                else if ( p_vci_ini_d.rtrdid.read() == TYPE_DATA_MISS ) 	r_rsp_fsm = RSP_DATA_MISS;
+                else if ( p_vci_ini_d.rtrdid.read() == TYPE_DATA_UNC ) 		r_rsp_fsm = RSP_DATA_UNC;
+                else if ( p_vci_ini_d.rtrdid.read() == TYPE_INS_MISS ) 		r_rsp_fsm = RSP_INS_MISS;
+                else if ( p_vci_ini_d.rtrdid.read() == TYPE_INS_UNC ) 		r_rsp_fsm = RSP_INS_UNC;
+            }
+            break;
+        }
+        case RSP_DATA_WRITE:
+        {
+            if ( p_vci_ini_d.rspval.read() )
+            {
+                assert(p_vci_ini_d.reop.read() &&
+                   "A VCI response packet must contain one flit for a write transaction");
+                r_rsp_fsm = RSP_IDLE;
+                r_wbuf.completed( p_vci_ini_d.rtrdid.read() - (1<<(vci_param::T-1)) );
+                if ( p_vci_ini_d.rerror.read() != vci_param::ERR_NORMAL ) m_iss.setWriteBerr();
+            }
+            break;
+        }
+        case RSP_INS_MISS:
+        {
+            if ( p_vci_ini_d.rspval.read() )
+            {  
+                assert( (r_rsp_cpt < m_icache_words) &&
+                        "The VCI response packet for instruction miss is too long" );
+                r_rsp_cpt = r_rsp_cpt + 1;
+                r_icache_miss_buf[r_rsp_cpt] = (data_t)p_vci_ini_d.rdata.read();
+                if ( p_vci_ini_d.reop.read() ) {
+                    assert( (r_rsp_cpt == m_icache_words - 1) &&
+                            "The VCI response packet for instruction miss is too short");
+                    r_rsp_ins_ok = true;
+                    r_rsp_fsm = RSP_IDLE;
+                }
+                if ( p_vci_ini_d.rerror.read() != vci_param::ERR_NORMAL ) r_rsp_ins_error = true;
+            }
+            break;
+        }
+        case RSP_INS_UNC:
+        {
+            if ( p_vci_ini_d.rspval.read() )
+            {
+                assert(p_vci_ini_d.reop.read() &&
+                   "illegal VCI response packet for uncachable instruction");
+                r_icache_miss_buf[0] = (data_t)p_vci_ini_d.rdata.read();
+                r_rsp_ins_ok = true;
+                r_rsp_fsm = RSP_IDLE;
+                if ( p_vci_ini_d.rerror.read() != vci_param::ERR_NORMAL ) r_rsp_ins_error = true;
+            }
+            break;
+        }
+        case RSP_DATA_MISS:
+        {
+            if ( p_vci_ini_d.rspval.read() )
+            {
+                assert( (r_rsp_cpt < m_dcache_words) &&
+                        "The VCI response packet for data miss is too long" );
+                r_rsp_cpt = r_rsp_cpt + 1;
+                r_dcache_miss_buf[r_rsp_cpt] = (data_t)p_vci_ini_d.rdata.read();
+                if ( p_vci_ini_d.reop.read() )
+                {
+                    assert(r_rsp_cpt == m_dcache_words - 1 &&
+                        "The VCI response packet for data miss is too short" );
+                    r_rsp_data_ok = true;
+                    r_rsp_fsm = RSP_IDLE;
+                }
+                if ( p_vci_ini_d.rerror.read() != vci_param::ERR_NORMAL ) r_rsp_data_error = true;
+            }
+            break;
+        }
+        case RSP_DATA_UNC:
+        {
+            if ( p_vci_ini_d.rspval.read() )
+            {
+                assert(p_vci_ini_d.reop.read() &&
+                   "illegal VCI response packet for uncachable data");
+                r_dcache_miss_buf[0] = (data_t)p_vci_ini_d.rdata.read();
+                r_rsp_data_ok = true;
+                r_rsp_fsm = RSP_IDLE;
+                if ( p_vci_ini_d.rerror.read() != vci_param::ERR_NORMAL ) r_rsp_data_error = true;
+            }
+            break;
+        }
+        } // end switch r_rsp_fsm
+
+    } // end transition()
+
+    //////////////////////
+    tmpl(void)::genMoore()
+    {
+        // Coherence network (initiator port)
+
+        switch ( r_cleanup_fsm.read() ) {
+
+            case CLEANUP_IDLE:
+                p_vci_ini_c.rspack  = false;
+                p_vci_ini_c.cmdval  = r_icache_cleanup_req || r_dcache_cleanup_req;
+                if ( r_dcache_cleanup_req )
+                {
+                    p_vci_ini_c.address =  r_dcache_cleanup_line.read() * (m_dcache_words << 2);
+                    p_vci_ini_c.trdid   = 0;
+                }
+                else
+                {
+                    p_vci_ini_c.address =  r_icache_cleanup_line.read() * (m_icache_words << 2); 
+                    p_vci_ini_c.trdid   = 1;
+                }
+                p_vci_ini_c.wdata  = 0;
+                p_vci_ini_c.be     = 0xF;
+                p_vci_ini_c.plen   = 4;
+                p_vci_ini_c.cmd    = vci_param::CMD_WRITE;
+                p_vci_ini_c.pktid  = 0;
+                p_vci_ini_c.srcid  = m_srcid_c;
+                p_vci_ini_c.cons   = false;
+                p_vci_ini_c.wrap   = false;
+                p_vci_ini_c.contig = false;
+                p_vci_ini_c.clen   = 0;
+                p_vci_ini_c.cfixed = false;
+                p_vci_ini_c.eop = true;
+                break;
+
+           case CLEANUP_DCACHE:
+                p_vci_ini_c.rspack  = true;
+                p_vci_ini_c.cmdval  = false;
+                p_vci_ini_c.address = 0;
+                p_vci_ini_c.wdata  = 0;
+                p_vci_ini_c.be     = 0;
+                p_vci_ini_c.plen   = 0;
+                p_vci_ini_c.cmd    = vci_param::CMD_WRITE;
+                p_vci_ini_c.trdid  = 0; 
+                p_vci_ini_c.pktid  = 0;
+                p_vci_ini_c.srcid  = 0;
+                p_vci_ini_c.cons   = false;
+                p_vci_ini_c.wrap   = false;
+                p_vci_ini_c.contig = false;
+                p_vci_ini_c.clen   = 0;
+                p_vci_ini_c.cfixed = false;
+                p_vci_ini_c.eop = false;
+                break;
+
+           case CLEANUP_ICACHE:
+                p_vci_ini_c.rspack  = true;
+                p_vci_ini_c.cmdval  = false;
+                p_vci_ini_c.address = 0;
+                p_vci_ini_c.wdata  = 0;
+                p_vci_ini_c.be     = 0;
+                p_vci_ini_c.plen   = 0;
+                p_vci_ini_c.cmd    = vci_param::CMD_WRITE;
+                p_vci_ini_c.trdid  = 0; 
+                p_vci_ini_c.pktid  = 0;
+                p_vci_ini_c.srcid  = 0;
+                p_vci_ini_c.cons   = false;
+                p_vci_ini_c.wrap   = false;
+                p_vci_ini_c.contig = false;
+                p_vci_ini_c.clen   = 0;
+                p_vci_ini_c.cfixed = false;
+                p_vci_ini_c.eop = false;
+                break;
+           } // end switch r_cleanup_fsm
+
+        // Direct network initiator response
+
+        p_vci_ini_d.rspack = ( r_rsp_fsm != RSP_IDLE );
+
+        // Direct network initiator command
+
+        switch ( r_cmd_fsm ) {
+
+            case CMD_IDLE:
+                p_vci_ini_d.cmdval  = false;
+                p_vci_ini_d.address = 0;
+                p_vci_ini_d.wdata   = 0;
+                p_vci_ini_d.be      = 0;
+                p_vci_ini_d.plen    = 0;
+                p_vci_ini_d.cmd     = vci_param::CMD_WRITE;
+                p_vci_ini_d.trdid   = 0;
+                p_vci_ini_d.pktid   = 0;
+                p_vci_ini_d.srcid   = 0;
+                p_vci_ini_d.cons    = false;
+                p_vci_ini_d.wrap    = false;
+                p_vci_ini_d.contig  = false;
+                p_vci_ini_d.clen    = 0;
+                p_vci_ini_d.cfixed  = false;
+                p_vci_ini_d.eop     = false;
+                break;
+
+            case CMD_DATA_WRITE:
+                p_vci_ini_d.cmdval  = true;
+                p_vci_ini_d.address = r_wbuf.getAddress(r_cmd_cpt);
+                p_vci_ini_d.wdata   = r_wbuf.getData(r_cmd_cpt);
+                p_vci_ini_d.be      = r_wbuf.getBe(r_cmd_cpt);
+                p_vci_ini_d.plen    = (r_cmd_max - r_cmd_min + 1)<<2;
+                p_vci_ini_d.cmd     = vci_param::CMD_WRITE;
+                p_vci_ini_d.trdid   = r_wbuf.getIndex() + (1<<(vci_param::T-1));
+                p_vci_ini_d.pktid   = 0;
+                p_vci_ini_d.srcid   = m_srcid_d;
+                p_vci_ini_d.cons    = false;
+                p_vci_ini_d.wrap    = false;
+                p_vci_ini_d.contig  = true;
+                p_vci_ini_d.clen    = 0;
+                p_vci_ini_d.cfixed  = false;
+                p_vci_ini_d.eop     = (r_cmd_cpt == r_cmd_max);
+                break;
+
+            case CMD_DATA_MISS:
+                p_vci_ini_d.cmdval = true;
+                p_vci_ini_d.address = r_dcache_addr_save & (addr_t)m_dcache_yzmask;
+                p_vci_ini_d.be     = 0xF;
+                p_vci_ini_d.plen   = m_dcache_words << 2;
+                p_vci_ini_d.cmd    = vci_param::CMD_READ;
+                p_vci_ini_d.trdid  = TYPE_DATA_MISS;
+                p_vci_ini_d.pktid  = 0;
+                p_vci_ini_d.srcid  = m_srcid_d;
+                p_vci_ini_d.cons   = false;
+                p_vci_ini_d.wrap   = false;
+                p_vci_ini_d.contig = true;
+                p_vci_ini_d.clen   = 0;
+                p_vci_ini_d.cfixed = false;
+                p_vci_ini_d.eop    = true;
+                break;
+
+            case CMD_DATA_UNC:
+                p_vci_ini_d.cmdval = true;
+                p_vci_ini_d.address = r_dcache_addr_save & ~0x3;
+                switch( r_dcache_type_save ) {
+                    case iss_t::DATA_WRITE:
+                        p_vci_ini_d.wdata = r_dcache_wdata_save.read();
+                        p_vci_ini_d.be  = r_dcache_be_save.read();
+                        p_vci_ini_d.cmd = vci_param::CMD_WRITE;
+                        break;
+                    case iss_t::DATA_READ:
+                        p_vci_ini_d.wdata = 0;
+                        p_vci_ini_d.be  = r_dcache_be_save.read();
+                        p_vci_ini_d.cmd = vci_param::CMD_READ;
+                        break;
+                    case iss_t::DATA_LL:
+                        p_vci_ini_d.wdata = 0;
+                        p_vci_ini_d.be  = 0xF;
+                        p_vci_ini_d.cmd = vci_param::CMD_LOCKED_READ;
+                        break;
+                    case iss_t::DATA_SC:
+                        p_vci_ini_d.wdata = r_dcache_wdata_save.read();
+                        p_vci_ini_d.be  = 0xF;
+                        p_vci_ini_d.cmd = vci_param::CMD_STORE_COND;
+                        break;
+                    default:
+                        assert("this should not happen");
+                }
+                p_vci_ini_d.plen   = 4;
+                p_vci_ini_d.trdid  = TYPE_DATA_UNC;
+                p_vci_ini_d.pktid  = 0;
+                p_vci_ini_d.srcid  = m_srcid_d;
+                p_vci_ini_d.cons   = false;
+                p_vci_ini_d.wrap   = false;
+                p_vci_ini_d.contig = true;
+                p_vci_ini_d.clen   = 0;
+                p_vci_ini_d.cfixed = false;
+                p_vci_ini_d.eop    = true;
+                break;
+
+            case CMD_INS_MISS:
+                p_vci_ini_d.cmdval = true;
+                p_vci_ini_d.address = r_icache_addr_save & (addr_t)m_icache_yzmask;
+                p_vci_ini_d.be     = 0xF;
+                p_vci_ini_d.plen   = m_icache_words << 2;
+                p_vci_ini_d.cmd    = vci_param::CMD_READ;
+                p_vci_ini_d.trdid  = TYPE_INS_MISS;
+                p_vci_ini_d.pktid  = 0;
+                p_vci_ini_d.srcid  = m_srcid_d;
+                p_vci_ini_d.cons   = false;
+                p_vci_ini_d.wrap   = false;
+                p_vci_ini_d.contig = true;
+                p_vci_ini_d.clen   = 0;
+                p_vci_ini_d.cfixed = false;
+                p_vci_ini_d.eop    = true;
+                break;
+
+            case CMD_INS_UNC:
+                p_vci_ini_d.cmdval = true;
+                p_vci_ini_d.address = r_icache_addr_save.read() & ~0x3;
+                p_vci_ini_d.be     = 0xF;
+                p_vci_ini_d.plen   = 4;
+                p_vci_ini_d.cmd    = vci_param::CMD_READ;
+                p_vci_ini_d.trdid  = TYPE_INS_UNC;
+                p_vci_ini_d.pktid  = 0;
+                p_vci_ini_d.srcid  = m_srcid_d;
+                p_vci_ini_d.cons   = false;
+                p_vci_ini_d.wrap   = false;
+                p_vci_ini_d.contig = true;
+                p_vci_ini_d.clen   = 0;
+                p_vci_ini_d.cfixed = false;
+                p_vci_ini_d.eop    = true;
+                break;
+        } // end switch r_cmd_fsm
+
+        // coherence network : target port
+
+        switch ( r_tgt_fsm.read() ) {
+
+            case TGT_IDLE:
+            case TGT_UPDT_WORD:
+            case TGT_UPDT_DATA:
+                p_vci_tgt_c.cmdack  = true;
+                p_vci_tgt_c.rspval  = false;
+                break;
+
+            case TGT_RSP_BROADCAST:
+                p_vci_tgt_c.cmdack  = false;
+                p_vci_tgt_c.rspval  = !r_tgt_icache_req.read() && !r_tgt_dcache_req.read() 
+                                       &&  ( r_tgt_icache_rsp | r_tgt_dcache_rsp );
+                p_vci_tgt_c.rsrcid  = r_tgt_srcid.read();
+                p_vci_tgt_c.rpktid  = r_tgt_pktid.read();
+                p_vci_tgt_c.rtrdid  = r_tgt_trdid.read();
+                p_vci_tgt_c.rdata   = 0;
+                p_vci_tgt_c.rerror  = 0;
+                p_vci_tgt_c.reop    = true;
+                break;
+
+            case TGT_RSP_ICACHE:
+                p_vci_tgt_c.cmdack  = false;
+                p_vci_tgt_c.rspval  = !r_tgt_icache_req.read() && r_tgt_icache_rsp.read();
+                p_vci_tgt_c.rsrcid  = r_tgt_srcid.read();
+                p_vci_tgt_c.rpktid  = r_tgt_pktid.read();
+                p_vci_tgt_c.rtrdid  = r_tgt_trdid.read();
+                p_vci_tgt_c.rdata   = 0;
+                p_vci_tgt_c.rerror  = 0;
+                p_vci_tgt_c.reop    = true;
+                break;
+
+            case TGT_RSP_DCACHE:
+                p_vci_tgt_c.cmdack  = false;
+                p_vci_tgt_c.rspval  = !r_tgt_dcache_req.read() && r_tgt_dcache_rsp.read();
+                p_vci_tgt_c.rsrcid  = r_tgt_srcid.read();
+                p_vci_tgt_c.rpktid  = r_tgt_pktid.read();
+                p_vci_tgt_c.rtrdid  = r_tgt_trdid.read();
+                p_vci_tgt_c.rdata   = 0;
+                p_vci_tgt_c.rerror  = 0;
+                p_vci_tgt_c.reop    = true;
+                break;
+
+            case TGT_REQ_BROADCAST:
+            case TGT_REQ_ICACHE:
+            case TGT_REQ_DCACHE:
+                p_vci_tgt_c.cmdack  = false;
+                p_vci_tgt_c.rspval  = false;
+                break;
+
+        } // end switch TGT_FSM
+    } // end genMoore()
+
+}} // end namespace
+
+// Local Variables:
+// tab-width: 4
+// c-basic-offset: 4
+// c-file-offsets:((innamespace . 0)(inline-open . 0))
+// indent-tabs-mode: nil
+// End:
+
+// vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4
+
+
+
+
Index: branches/v4/modules/vci_cc_xcache_wrapper_v1/caba/metadata/vci_cc_xcache_wrapper_v1.sd
===================================================================
--- branches/v4/modules/vci_cc_xcache_wrapper_v1/caba/metadata/vci_cc_xcache_wrapper_v1.sd	(revision 371)
+++ branches/v4/modules/vci_cc_xcache_wrapper_v1/caba/metadata/vci_cc_xcache_wrapper_v1.sd	(revision 371)
@@ -0,0 +1,60 @@
+
+# -*- python -*-
+
+__id__ = "$Id$"
+__version__ = "$Revision$"
+
+Module('caba:vci_cc_xcache_wrapper_v1',
+	classname = 'soclib::caba::VciCcXCacheWrapperV1',
+	tmpl_parameters = [
+		parameter.Module('vci_param', default = 'caba:vci_param'),
+		parameter.Module('iss_t'),
+		],
+	header_files = [
+		'../source/include/vci_cc_xcache_wrapper_v1.h',
+		],
+	implementation_files = [
+		'../source/src/vci_cc_xcache_wrapper_v1.cpp',
+		],
+	uses = [
+		Uses('caba:base_module'),
+		Uses('common:mapping_table'),
+		Uses('common:iss2'),
+		Uses('caba:write_buffer'),
+		Uses('caba:generic_cache', addr_t = 'uint32_t'),
+		],
+	ports = [
+		Port('caba:vci_initiator', 'p_vci_ini_rw'),
+    Port('caba:vci_initiator', 'p_vci_ini_c'),
+		Port('caba:vci_target', 'p_vci_tgt'),
+		Port('caba:bit_in', 'p_irq', parameter.Constant('n_irq')),
+		Port('caba:bit_in', 'p_resetn', auto = 'resetn'),
+		Port('caba:clock_in', 'p_clk', auto = 'clock'),
+		],
+	instance_parameters = [
+		parameter.Int('proc_id'),
+		parameter.Module('mtp'),
+		parameter.Module('mtc'),
+		parameter.IntTab('initiator_rw_index'),
+		parameter.IntTab('initiator_c_index'),
+		parameter.IntTab('target_index'),
+		parameter.Int('icache_ways'),
+		parameter.Int('icache_sets'),
+		parameter.Int('icache_words'),
+		parameter.Int('dcache_ways'),
+		parameter.Int('dcache_sets'),
+		parameter.Int('dcache_words'),
+		],
+	   extensions = [
+	'dsx:get_ident='
+        'initiator_rw_index:p_vci_ini_rw:mtp,'
+        'initiator_c_index:p_vci_ini_c:mtc,'
+        'target_index:p_vci_tgt:mtc',
+	'dsx:cpu=wrapper:iss_t',
+	'dsx:addressable=target_index',
+	'dsx:on_segment=mtc:add_index:initiator_rw_index',
+	'dsx:mapping_type=processor:proc_id',
+   ],
+)
+
+
Index: branches/v4/modules/vci_cc_xcache_wrapper_v1/caba/source/include/vci_cc_xcache_wrapper_v1.h
===================================================================
--- branches/v4/modules/vci_cc_xcache_wrapper_v1/caba/source/include/vci_cc_xcache_wrapper_v1.h	(revision 371)
+++ branches/v4/modules/vci_cc_xcache_wrapper_v1/caba/source/include/vci_cc_xcache_wrapper_v1.h	(revision 371)
@@ -0,0 +1,304 @@
+/* -*- c++ -*-
+ *
+ * SOCLIB_LGPL_HEADER_BEGIN
+ * 
+ * This file is part of SoCLib, GNU LGPLv2.1.
+ * 
+ * SoCLib is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU Lesser General Public License as published
+ * by the Free Software Foundation; version 2.1 of the License.
+ * 
+ * SoCLib is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * Lesser General Public License for more details.
+ * 
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with SoCLib; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301 USA
+ * 
+ * SOCLIB_LGPL_HEADER_END
+ *
+ * Copyright (c) UPMC, Lip6, SoC
+ *         Alain Greiner <alain.greiner@lip6.fr>, 2008
+ *
+ * Maintainers: alain
+ */
+ 
+#ifndef SOCLIB_CABA_VCI_CC_XCACHE_WRAPPER_V1_H
+#define SOCLIB_CABA_VCI_CC_XCACHE_WRAPPER_V1_H
+
+#include <inttypes.h>
+#include <systemc>
+#include "caba_base_module.h"
+#include "write_buffer.h"
+#include "generic_cache.h"
+#include "vci_initiator.h"
+#include "vci_target.h"
+#include "mapping_table.h"
+#include "static_assert.h"
+
+
+namespace soclib {
+namespace caba {
+
+using namespace sc_core;
+
+////////////////////////////////////////////
+template<typename vci_param, typename iss_t>
+class VciCcXCacheWrapperV1
+///////////////////////////////////////////
+    : public soclib::caba::BaseModule
+{
+    typedef sc_dt::sc_uint<40> addr_40;
+    typedef uint32_t    data_t;
+    typedef uint32_t    tag_t;
+    typedef uint32_t    be_t;
+    typedef typename vci_param::fast_addr_t vci_addr_t;
+    enum dcache_fsm_state_e {
+        DCACHE_IDLE,
+        DCACHE_WRITE_UPDT,
+        DCACHE_WRITE_REQ,
+        DCACHE_MISS_WAIT,
+        DCACHE_MISS_UPDT,
+        DCACHE_UNC_WAIT,
+        DCACHE_INVAL,
+        DCACHE_ERROR,
+        DCACHE_CC_CHECK,
+        DCACHE_CC_INVAL,
+        DCACHE_CC_UPDT,
+        DCACHE_CC_CLEANUP,
+    };
+
+    enum icache_fsm_state_e {
+        ICACHE_IDLE,
+        ICACHE_MISS_WAIT,
+        ICACHE_MISS_UPDT,
+        ICACHE_UNC_WAIT,
+        ICACHE_ERROR,
+        ICACHE_CC_CHECK,
+        ICACHE_CC_INVAL,
+        ICACHE_CC_UPDT,
+        ICACHE_CC_CLEANUP 
+    };
+
+    enum cmd_fsm_state_e {
+        CMD_IDLE,
+        CMD_INS_MISS,
+        CMD_INS_UNC,
+        CMD_DATA_MISS,
+        CMD_DATA_UNC,
+        CMD_DATA_WRITE,
+        CMD_INS_CLEANUP,
+        CMD_DATA_CLEANUP,
+    };
+
+    enum rsp_fsm_state_e {
+        RSP_IDLE,
+        RSP_INS_MISS,
+        RSP_INS_UNC,
+        RSP_DATA_MISS,
+        RSP_DATA_UNC,
+        RSP_DATA_WRITE,
+        RSP_INS_CLEANUP,
+        RSP_DATA_CLEANUP,
+    };
+
+    enum tgt_fsm_state_e {
+        TGT_IDLE,
+        TGT_UPDT_WORD,
+        TGT_UPDT_DATA,
+        TGT_REQ_BROADCAST,
+        TGT_REQ_ICACHE,
+        TGT_REQ_DCACHE,
+        TGT_RSP_BROADCAST,
+        TGT_RSP_ICACHE,
+        TGT_RSP_DCACHE,
+    };
+
+public:
+
+    // PORTS
+    sc_in<bool>                             p_clk;
+    sc_in<bool>                             p_resetn;
+    sc_in<bool>                             p_irq[iss_t::n_irq];
+    soclib::caba::VciInitiator<vci_param>   p_vci_ini_rw;
+    soclib::caba::VciInitiator<vci_param>   p_vci_ini_c;
+    soclib::caba::VciTarget<vci_param>      p_vci_tgt;
+
+private:
+
+    // STRUCTURAL PARAMETERS
+    const soclib::common::AddressDecodingTable<vci_addr_t, bool>    m_cacheability_table;
+    const soclib::common::Segment                                   m_segment;
+    iss_t               m_iss;
+    const uint32_t      m_srcid_rw;   
+    const uint32_t      m_srcid_c;   
+    
+    const size_t        m_dcache_ways;
+    const size_t        m_dcache_words;
+    const size_t        m_dcache_yzmask;
+    const size_t        m_icache_ways;
+    const size_t        m_icache_words;
+    const size_t        m_icache_yzmask;
+
+    const size_t	m_x_width;   
+    const size_t	m_y_width;   
+    const size_t	m_memc_id;   
+    addr_40		m_srcid_mask;
+
+    // REGISTERS
+    sc_signal<int>          r_dcache_fsm;
+    sc_signal<int>          r_dcache_fsm_save;
+    sc_signal<addr_40>      r_dcache_addr_save;
+    sc_signal<data_t>       r_dcache_wdata_save;
+    sc_signal<data_t>       r_dcache_rdata_save;
+    sc_signal<int>          r_dcache_type_save;
+    sc_signal<be_t>         r_dcache_be_save;
+    sc_signal<bool>         r_dcache_cached_save;
+    sc_signal<bool>         r_dcache_cleanup_req;
+    sc_signal<addr_40>      r_dcache_cleanup_line;
+    sc_signal<bool>         r_dcache_miss_req;
+    sc_signal<bool>         r_dcache_unc_req;
+    sc_signal<bool>         r_dcache_write_req;
+    sc_signal<bool>         r_dcache_inval_rsp;
+
+    sc_signal<int>          r_icache_fsm;
+    sc_signal<int>          r_icache_fsm_save;
+    sc_signal<addr_40>      r_icache_addr_save;
+    sc_signal<bool>         r_icache_miss_req;
+    sc_signal<bool>         r_icache_unc_req;
+    sc_signal<bool>         r_icache_cleanup_req;
+    sc_signal<addr_40>      r_icache_cleanup_line;
+    sc_signal<bool>         r_icache_inval_rsp;
+
+    sc_signal<int>          r_vci_cmd_fsm;
+    sc_signal<size_t>       r_vci_cmd_min;       
+    sc_signal<size_t>       r_vci_cmd_max;       
+    sc_signal<size_t>       r_vci_cmd_cpt;       
+      
+    sc_signal<int>          r_vci_rsp_fsm;
+    sc_signal<bool>         r_vci_rsp_ins_error;    
+    sc_signal<bool>         r_vci_rsp_data_error;    
+    sc_signal<size_t>       r_vci_rsp_cpt;  
+
+    data_t                  *r_icache_miss_buf;    
+    data_t                  *r_dcache_miss_buf;    
+    sc_signal<bool>         r_icache_buf_unc_valid;
+    sc_signal<bool>         r_dcache_buf_unc_valid;
+
+    data_t                  *r_tgt_buf;
+    be_t                    *r_tgt_be;
+
+    sc_signal<int>          r_vci_tgt_fsm;
+    sc_signal<addr_40>       r_tgt_addr;
+    sc_signal<size_t>       r_tgt_word;
+    sc_signal<bool>         r_tgt_update;
+    sc_signal<bool>         r_data_update; // 0 : update ins; 1 : update data
+    sc_signal<bool>         r_tgt_brdcast;
+    sc_signal<size_t>       r_tgt_srcid;
+    sc_signal<size_t>       r_tgt_pktid;
+    sc_signal<size_t>       r_tgt_trdid;
+    sc_signal<size_t>       r_tgt_plen;
+    sc_signal<bool>         r_tgt_icache_req;
+    sc_signal<bool>         r_tgt_dcache_req;
+    sc_signal<bool>         r_tgt_icache_rsp;
+    sc_signal<bool>         r_tgt_dcache_rsp;
+
+    WriteBuffer<addr_40>        r_wbuf;
+    GenericCache<vci_addr_t>    r_icache;
+    GenericCache<vci_addr_t>    r_dcache;
+
+    // Activity counters
+    uint32_t m_cpt_dcache_data_read;        // DCACHE DATA READ
+    uint32_t m_cpt_dcache_data_write;       // DCACHE DATA WRITE
+    uint32_t m_cpt_dcache_dir_read;         // DCACHE DIR READ
+    uint32_t m_cpt_dcache_dir_write;        // DCACHE DIR WRITE
+
+    uint32_t m_cpt_icache_data_read;        // ICACHE DATA READ
+    uint32_t m_cpt_icache_data_write;       // ICACHE DATA WRITE
+    uint32_t m_cpt_icache_dir_read;         // ICACHE DIR READ
+    uint32_t m_cpt_icache_dir_write;        // ICACHE DIR WRITE
+
+    uint32_t m_cpt_cc_update;               // number of coherence update packets 
+    uint32_t m_cpt_cc_inval;                // number of coherence inval packets
+
+    uint32_t m_cpt_frz_cycles;	            // number of cycles where the cpu is frozen
+    uint32_t m_cpt_total_cycles;	        // total number of cycles 
+
+    uint32_t m_cpt_read;                    // total number of read instructions
+    uint32_t m_cpt_write;                   // total number of write instructions
+    uint32_t m_cpt_data_miss;               // number of read miss
+    uint32_t m_cpt_ins_miss;                // number of instruction miss
+    uint32_t m_cpt_unc_read;                // number of read uncached
+    uint32_t m_cpt_write_cached;            // number of cached write
+
+    uint32_t m_cost_write_frz;              // number of frozen cycles related to write buffer         
+    uint32_t m_cost_data_miss_frz;          // number of frozen cycles related to data miss
+    uint32_t m_cost_unc_read_frz;           // number of frozen cycles related to uncached read
+    uint32_t m_cost_ins_miss_frz;           // number of frozen cycles related to ins miss
+
+    uint32_t m_cpt_imiss_transaction;       // number of VCI instruction miss transactions
+    uint32_t m_cpt_dmiss_transaction;       // number of VCI data miss transactions
+    uint32_t m_cpt_unc_transaction;         // number of VCI uncached read transactions
+    uint32_t m_cpt_write_transaction;       // number of VCI write transactions
+
+    uint32_t m_cost_imiss_transaction;      // cumulated duration for VCI IMISS transactions
+    uint32_t m_cost_dmiss_transaction;      // cumulated duration for VCI DMISS transactions
+    uint32_t m_cost_unc_transaction;        // cumulated duration for VCI UNC transactions
+    uint32_t m_cost_write_transaction;      // cumulated duration for VCI WRITE transactions
+    uint32_t m_length_write_transaction;    // cumulated length for VCI WRITE transactions
+
+protected:
+    SC_HAS_PROCESS(VciCcXCacheWrapperV1);
+
+public:
+
+    VciCcXCacheWrapperV1(
+                       sc_module_name insname,
+                       int proc_id,
+                       const soclib::common::MappingTable &mtp,
+                       const soclib::common::MappingTable &mtc,
+                       const soclib::common::IntTab &initiator_index_rw,
+                       const soclib::common::IntTab &initiator_index_c,
+                       const soclib::common::IntTab &target_index,
+                       size_t icache_ways,
+                       size_t icache_sets,
+                       size_t icache_words,
+                       size_t dcache_ways,
+                       size_t dcache_sets,
+                       size_t dcache_words,
+		       size_t x_width,
+		       size_t y_width,
+		       size_t memc_id );
+
+    ~VciCcXCacheWrapperV1();
+
+    void print_cpi();
+    void print_stats();
+
+private:
+
+    void transition();
+    void genMoore();
+
+    soclib_static_assert((int)iss_t::SC_ATOMIC == (int)vci_param::STORE_COND_ATOMIC);
+    soclib_static_assert((int)iss_t::SC_NOT_ATOMIC == (int)vci_param::STORE_COND_NOT_ATOMIC);
+};
+
+}}
+
+#endif /* SOCLIB_CABA_VCI_CC_XCACHE_WRAPPER_V1_H */
+
+// Local Variables:
+// tab-width: 4
+// c-basic-offset: 4
+// c-file-offsets:((innamespace . 0)(inline-open . 0))
+// indent-tabs-mode: nil
+// End:
+
+// vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4
+
+
+
Index: branches/v4/modules/vci_cc_xcache_wrapper_v1/caba/source/src/vci_cc_xcache_wrapper_v1.cpp
===================================================================
--- branches/v4/modules/vci_cc_xcache_wrapper_v1/caba/source/src/vci_cc_xcache_wrapper_v1.cpp	(revision 371)
+++ branches/v4/modules/vci_cc_xcache_wrapper_v1/caba/source/src/vci_cc_xcache_wrapper_v1.cpp	(revision 371)
@@ -0,0 +1,1980 @@
+/* -*- c++ -*-
+ *
+ * SOCLIB_LGPL_HEADER_BEGIN
+ * 
+ * This file is part of SoCLib, GNU LGPLv2.1.
+ * 
+ * SoCLib is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU Lesser General Public License as published
+ * by the Free Software Foundation; version 2.1 of the License.
+ * 
+ * SoCLib is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * Lesser General Public License for more details.
+ * 
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with SoCLib; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301 USA
+ * 
+ * SOCLIB_LGPL_HEADER_END
+ *
+ * Copyright (c) UPMC, Lip6, SoC
+ *         Alain Greiner <alain.greiner@lip6.fr>, 2008
+ *
+ * Maintainers: alain 
+ *              eric.guthmuller@polytechnique.edu 
+ *              nipo
+ *              malek <abdelmalek.si-merabet@lip6.fr> 
+ *              cfuguet <c.sarfuguet@gmail.com>
+ */
+
+/////////////////////////////////////////////////////////////////////////////
+// History
+// - 25/04/2008
+//   The existing vci_xcache component has been extended to include 
+//   a VCI target port to support a directory based coherence protocol.
+//   Two types of packets can be send by the L2 cache to the L1 cache
+//   * INVALIDATE packets : length = 1
+//   * UPDATE packets : length = n + 2   
+//   The CLEANUP packets are sent by the L1 cache to the L2 cache, 
+//   to signal a replaced cache line.
+// - 12/08/2008
+//   The vci_cc_xcache_wrapper component instanciates directly the processsor 
+//   iss, in order to supress the processor/cache interface.
+//   According to the VCI advanced specification, this component uses one 
+//   word VCI CMD packets for MISS transactions, and accept one word VCI RSP
+//   packets for Write burst  transactions.
+//   The write buffer has been modified to use the WriteBuffer object. 
+//   A VCI write burst is constructed when two conditions are satisfied :
+//   The processor make strictly successive write requests, and they are
+//   in the same cache line. The write buffer performs re-ordering, to
+//   respect the contiguous addresses VCI constraint. In case of several
+//   WRITE_WORD requests in the same word, only the last request is conserved.
+//   In case of several WRITE_HALF or WRITE_WORD requests in the same word,
+//   the requests are merged in the same word. In case of uncached write
+//   requests, each request is transmited as a single VCI transaction.
+//   Both the data & instruction caches can be flushed in one single cycle.
+// 08/12/2009
+//   adding update instruction (code X"C")  
+///////////////////////////////////////////////////////////////////////////////
+
+#include <cassert>
+#include "arithmetics.h"
+#include "../include/vci_cc_xcache_wrapper_v1.h"
+
+//#define DEBUG_CC_XCACHE_WRAPPER 1
+//#define DEBUG_CLEANUP
+
+namespace soclib { 
+namespace caba {
+
+#if DEBUG_CC_XCACHE_WRAPPER
+    namespace {
+        const char *dcache_fsm_state_str[] = {
+            "DCACHE_IDLE",
+            "DCACHE_WRITE_UPDT",
+            "DCACHE_WRITE_REQ",
+            "DCACHE_MISS_WAIT",
+            "DCACHE_MISS_UPDT",
+            "DCACHE_UNC_WAIT",
+            "DCACHE_INVAL",
+            "DCACHE_ERROR",
+            "DCACHE_CC_CHECK",
+            "DCACHE_CC_INVAL",
+            "DCACHE_CC_UPDT",
+            "DCACHE_CC_NOP",
+            "DCACHE_CC_CLEANUP",
+        };
+        const char *icache_fsm_state_str[] = {
+            "ICACHE_IDLE",
+            "ICACHE_MISS_WAIT",
+            "ICACHE_MISS_UPDT",
+            "ICACHE_UNC_WAIT",
+            "ICACHE_ERROR",
+            "ICACHE_CC_CHECK",
+            "ICACHE_CC_INVAL",
+            "ICACHE_CC_UPDT",
+            "ICACHE_CC_CLEANUP", 
+        };
+        const char *cmd_fsm_state_str[] = {
+            "CMD_IDLE",
+            "CMD_INS_MISS",
+            "CMD_INS_UNC",
+            "CMD_DATA_MISS",
+            "CMD_DATA_UNC",
+            "CMD_DATA_WRITE",
+            "CMD_INS_CLEANUP",
+            "CMD_DATA_CLEANUP",
+        };
+        const char *rsp_fsm_state_str[] = {
+            "RSP_IDLE",
+            "RSP_INS_MISS",
+            "RSP_INS_UNC",
+            "RSP_DATA_MISS",
+            "RSP_DATA_UNC",
+            "RSP_DATA_WRITE",
+            "RSP_INS_CLEANUP",
+            "RSP_DATA_CLEANUP",
+        };
+        const char *tgt_fsm_state_str[] = {
+            "TGT_IDLE",
+            "TGT_UPDT_WORD",
+            "TGT_UPDT_DATA",
+            "TGT_REQ_BROADCAST",
+            "TGT_REQ_ICACHE",
+            "TGT_REQ_DCACHE",
+            "TGT_RSP_BROADCAST",
+            "TGT_RSP_ICACHE",
+            "TGT_RSP_DCACHE",
+        };
+    }
+#endif
+
+#define tmpl(...)  template<typename vci_param, typename iss_t> __VA_ARGS__ VciCcXCacheWrapperV1<vci_param, iss_t>
+
+    using soclib::common::uint32_log2;
+
+    /////////////////////////////////
+    tmpl(/**/)::VciCcXCacheWrapperV1(
+            /////////////////////////////////
+            sc_module_name name,
+            int proc_id,
+            const soclib::common::MappingTable &mtp,
+            const soclib::common::MappingTable &mtc,
+            const soclib::common::IntTab &initiator_index_rw,
+            const soclib::common::IntTab &initiator_index_c,
+            const soclib::common::IntTab &target_index,
+            size_t icache_ways,
+            size_t icache_sets,
+            size_t icache_words,
+            size_t dcache_ways,
+            size_t dcache_sets,
+            size_t dcache_words,
+            // Parameters for the CLEANUP transaction
+            size_t x_width,
+            size_t y_width,
+            size_t memc_id )
+        : 
+            soclib::caba::BaseModule(name),
+
+            p_clk("clk"),
+            p_resetn("resetn"),
+            p_vci_ini_rw("vci_ini_rw"),
+            p_vci_ini_c("vci_ini_c"),
+            p_vci_tgt("vci_tgt"),
+
+            m_cacheability_table(mtp.getCacheabilityTable<vci_addr_t>()),
+            m_segment(mtc.getSegment(target_index)),
+            m_iss(this->name(), proc_id),
+            m_srcid_rw(mtp.indexForId(initiator_index_rw)),
+            m_srcid_c(mtc.indexForId(initiator_index_c)),
+
+            m_dcache_ways(dcache_ways),
+            m_dcache_words(dcache_words),
+            m_dcache_yzmask((~0)<<(uint32_log2(dcache_words) + 2)),
+            m_icache_ways(icache_ways),
+            m_icache_words(icache_words),
+            m_icache_yzmask((~0)<<(uint32_log2(icache_words) + 2)),
+
+            m_x_width(x_width),
+            m_y_width(y_width),
+
+            m_memc_id(memc_id),
+
+            m_srcid_mask(~((0x1 << (vci_param::N - vci_param::S)) - 1)),
+
+            r_dcache_fsm("r_dcache_fsm"),
+            r_dcache_fsm_save("r_dcache_fsm_save"),
+            r_dcache_addr_save("r_dcache_addr_save"),
+            r_dcache_wdata_save("r_dcache_wdata_save"),
+            r_dcache_rdata_save("r_dcache_rdata_save"),
+            r_dcache_type_save("r_dcache_type_save"),
+            r_dcache_be_save("r_dcache_be_save"),
+            r_dcache_cached_save("r_dcache_cached_save"),
+            r_dcache_cleanup_req("r_dcache_cleanup_req"),
+            r_dcache_cleanup_line("r_dcache_cleanup_line"),
+            r_dcache_miss_req("r_dcache_miss_req"),
+            r_dcache_unc_req("r_dcache_unc_req"),
+            r_dcache_write_req("r_dcache_write_req"),
+
+            r_icache_fsm("r_icache_fsm"),
+            r_icache_fsm_save("r_icache_fsm_save"),
+            r_icache_addr_save("r_icache_addr_save"),
+            r_icache_miss_req("r_icache_miss_req"),
+            r_icache_cleanup_req("r_icache_cleanup_req"),
+            r_icache_cleanup_line("r_icache_cleanup_line"),
+
+            r_vci_cmd_fsm("r_vci_cmd_fsm"),
+            r_vci_cmd_min("r_vci_cmd_min"),
+            r_vci_cmd_max("r_vci_cmd_max"),
+            r_vci_cmd_cpt("r_vci_cmd_cpt"),
+
+            r_vci_rsp_fsm("r_vci_rsp_fsm"),
+            r_vci_rsp_ins_error("r_vci_rsp_ins_error"),
+            r_vci_rsp_data_error("r_vci_rsp_data_error"),
+            r_vci_rsp_cpt("r_vci_rsp_cpt"),
+
+            r_icache_buf_unc_valid("r_icache_buf_unc_valid"),
+            r_dcache_buf_unc_valid("r_dcache_buf_unc_valid"),
+
+            r_vci_tgt_fsm("r_vci_tgt_fsm"),
+            r_tgt_addr("r_tgt_addr"),
+            r_tgt_word("r_tgt_word"),
+            r_tgt_update("r_tgt_update"),
+            r_data_update("r_data_update"),
+            r_tgt_srcid("r_tgt_srcid"),
+            r_tgt_pktid("r_tgt_pktid"),
+            r_tgt_trdid("r_tgt_trdid"),
+            r_tgt_icache_req("r_tgt_icache_req"),
+            r_tgt_dcache_req("r_tgt_dcache_req"),
+
+            r_wbuf("r_wbuf", dcache_words ),
+            r_icache("icache", icache_ways, icache_sets, icache_words),
+            r_dcache("dcache", dcache_ways, dcache_sets, dcache_words)
+
+            {
+                r_icache_miss_buf = new data_t[icache_words];
+                r_dcache_miss_buf = new data_t[dcache_words];
+                r_tgt_buf         = new data_t[dcache_words];
+                r_tgt_be          = new be_t[dcache_words];
+
+                SC_METHOD(transition);
+                dont_initialize();
+                sensitive << p_clk.pos();
+
+                SC_METHOD(genMoore);
+                dont_initialize();
+                sensitive << p_clk.neg();
+
+                typename iss_t::CacheInfo cache_info;
+                cache_info.has_mmu = false;
+                cache_info.icache_line_size = icache_words*sizeof(data_t);
+                cache_info.icache_assoc = icache_ways;
+                cache_info.icache_n_lines = icache_sets;
+                cache_info.dcache_line_size = dcache_words*sizeof(data_t);
+                cache_info.dcache_assoc = dcache_ways;
+                cache_info.dcache_n_lines = dcache_sets;
+                m_iss.setCacheInfo(cache_info);
+
+            } // end constructor
+
+    ///////////////////////////////////
+    tmpl(/**/)::~VciCcXCacheWrapperV1()
+        ///////////////////////////////////
+    {
+        delete [] r_icache_miss_buf;
+        delete [] r_dcache_miss_buf;
+        delete [] r_tgt_be;
+        delete [] r_tgt_buf;
+    }
+
+    ////////////////////////
+    tmpl(void)::print_cpi()
+        ////////////////////////
+    {
+        std::cout << "CPU " << m_srcid_rw << " : CPI = " 
+            << (float)m_cpt_total_cycles/(m_cpt_total_cycles - m_cpt_frz_cycles) << std::endl ;
+    }
+    ////////////////////////
+    tmpl(void)::print_stats()
+        ////////////////////////
+    {
+        float run_cycles = (float)(m_cpt_total_cycles - m_cpt_frz_cycles);
+        std::cout << "------------------------------------" << std:: dec << std::endl;
+        std::cout << "CPU " << m_srcid_rw << " / Time = " << m_cpt_total_cycles << std::endl;
+        std::cout << "- CPI                = " << (float)m_cpt_total_cycles/run_cycles << std::endl ;
+        std::cout << "- READ RATE          = " << (float)m_cpt_read/run_cycles << std::endl ;
+        std::cout << "- WRITE RATE         = " << (float)m_cpt_write/run_cycles << std::endl;
+        std::cout << "- UNCACHED READ RATE = " << (float)m_cpt_unc_read/m_cpt_read << std::endl ;
+        std::cout << "- CACHED WRITE RATE  = " << (float)m_cpt_write_cached/m_cpt_write << std::endl ;
+        std::cout << "- IMISS_RATE         = " << (float)m_cpt_ins_miss/run_cycles << std::endl;
+        std::cout << "- DMISS RATE         = " << (float)m_cpt_data_miss/(m_cpt_read-m_cpt_unc_read) << std::endl ;
+        std::cout << "- INS MISS COST      = " << (float)m_cost_ins_miss_frz/m_cpt_ins_miss << std::endl;
+        std::cout << "- IMISS TRANSACTION  = " << (float)m_cost_imiss_transaction/m_cpt_imiss_transaction << std::endl;
+        std::cout << "- DMISS COST         = " << (float)m_cost_data_miss_frz/m_cpt_data_miss << std::endl;
+        std::cout << "- DMISS TRANSACTION  = " << (float)m_cost_dmiss_transaction/m_cpt_dmiss_transaction << std::endl;
+        std::cout << "- UNC COST           = " << (float)m_cost_unc_read_frz/m_cpt_unc_read << std::endl;
+        std::cout << "- UNC TRANSACTION    = " << (float)m_cost_unc_transaction/m_cpt_unc_transaction << std::endl;
+        std::cout << "- WRITE COST         = " << (float)m_cost_write_frz/m_cpt_write << std::endl;
+        std::cout << "- WRITE TRANSACTION  = " << (float)m_cost_write_transaction/m_cpt_write_transaction << std::endl;
+        std::cout << "- WRITE LENGTH       = " << (float)m_length_write_transaction/m_cpt_write_transaction << std::endl;
+    }
+
+    //////////////////////////
+    tmpl(void)::transition()
+        //////////////////////////
+    {
+        if ( ! p_resetn.read() ) {
+
+            m_iss.reset();
+
+            // FSM states
+            r_dcache_fsm = DCACHE_IDLE;
+            r_icache_fsm = ICACHE_IDLE;
+            r_vci_cmd_fsm = CMD_IDLE;
+            r_vci_rsp_fsm = RSP_IDLE;
+            r_vci_tgt_fsm = TGT_IDLE;
+
+            // write buffer & caches
+            r_wbuf.reset();
+            r_icache.reset();
+            r_dcache.reset();
+
+            // synchronisation flip-flops from ICACHE & DCACHE FSMs to VCI  FSMs
+            r_icache_miss_req    = false;
+            r_icache_unc_req     = false;
+            r_icache_cleanup_req = false;
+            r_dcache_miss_req    = false;
+            r_dcache_unc_req     = false;
+            r_dcache_write_req   = false;
+            r_dcache_cleanup_req = false;
+
+            // synchronisation flip-flops from TGT FSM to ICACHE & DCACHE FSMs
+            r_tgt_icache_req     = false;
+            r_tgt_dcache_req     = false;
+
+            // internal messages in DCACHE et ICACHE FSMs
+            r_icache_inval_rsp   = false;
+            r_dcache_inval_rsp   = false;
+
+            // error signals from the VCI RSP FSM to the ICACHE or DCACHE FSMs
+            r_dcache_buf_unc_valid = false;
+            r_icache_buf_unc_valid = false;
+            r_vci_rsp_data_error   = false;
+            r_vci_rsp_ins_error    = false;
+
+            // activity counters
+            m_cpt_dcache_data_read  = 0;
+            m_cpt_dcache_data_write = 0;
+            m_cpt_dcache_dir_read  = 0;
+            m_cpt_dcache_dir_write = 0;
+            m_cpt_icache_data_read  = 0;
+            m_cpt_icache_data_write = 0;
+            m_cpt_icache_dir_read  = 0;
+            m_cpt_icache_dir_write = 0;
+
+            m_cpt_cc_update = 0;
+            m_cpt_cc_inval = 0;
+
+            m_cpt_frz_cycles = 0;
+            m_cpt_total_cycles = 0;
+
+            m_cpt_read = 0;
+            m_cpt_write = 0;
+            m_cpt_data_miss = 0;
+            m_cpt_ins_miss = 0;
+            m_cpt_unc_read = 0;
+            m_cpt_write_cached = 0;
+
+            m_cost_write_frz = 0;
+            m_cost_data_miss_frz = 0;
+            m_cost_unc_read_frz = 0;
+            m_cost_ins_miss_frz = 0;
+
+            m_cpt_imiss_transaction = 0;
+            m_cpt_dmiss_transaction = 0;
+            m_cpt_unc_transaction = 0;
+            m_cpt_write_transaction = 0;
+
+            m_cost_imiss_transaction = 0;
+            m_cost_dmiss_transaction = 0;
+            m_cost_unc_transaction = 0;
+            m_cost_write_transaction = 0;
+            m_length_write_transaction = 0;
+
+            return;
+        }
+
+#if DEBUG_CC_XCACHE_WRAPPER
+        std::cout << "--------------------------------------------" << std::endl;
+        std::cout << std::dec << "CC_XCACHE_WRAPPER " << m_srcid_rw << " / Time = " << m_cpt_total_cycles << std::endl;
+        std::cout             << " tgt fsm    = " << tgt_fsm_state_str[r_vci_tgt_fsm] << std::endl
+            << " dcache fsm = " << dcache_fsm_state_str[r_dcache_fsm] << std::endl
+            << " icache fsm = " << icache_fsm_state_str[r_icache_fsm] << std::endl
+            << " cmd fsm    = " << cmd_fsm_state_str[r_vci_cmd_fsm] << std::endl
+            << " rsp fsm    = " << rsp_fsm_state_str[r_vci_rsp_fsm] << std::endl;
+#endif
+
+        m_cpt_total_cycles++;
+
+        /////////////////////////////////////////////////////////////////////
+        // The TGT_FSM controls the following ressources:
+        // - r_vci_tgt_fsm
+        // - r_tgt_buf[nwords]
+        // - r_tgt_be[nwords]
+        // - r_tgt_update
+        // - r_data_update
+        // - r_tgt_word
+        // - r_tgt_addr
+        // - r_tgt_srcid
+        // - r_tgt_trdid
+        // - r_tgt_pktid
+        // All VCI commands must be CMD_WRITE.
+        // If the VCI address offset is null, the command is an invalidate 
+        // request. It is an update request otherwise.
+        // The VCI_TGT FSM stores the external request arguments in the
+        // IDLE, UPDT_WORD & UPDT_DATA states. It sets the r_tgt_icache_req 
+        // & r_tgt_dcache_req flip-flops to signal the external request to 
+        // the ICACHE & DCACHE FSMs in the REQ state. It waits the completion
+        // of the update or invalidate request in the RSP state.
+        // -  for an invalidate request the VCI packet length is 1 word.
+        // The WDATA field contains the line index (i.e. the Z & Y fields).
+        // -  for an update request the VCI packet length is (n+2) words.
+        // The WDATA field of the first VCI word contains the line number.
+        // The WDATA field of the second VCI word contains the word index.
+        // The WDATA field of the n following words contains the values.
+        // -  for both invalidate & update requests, the VCI response
+        // is one single word.
+        // In case of errors in the VCI command packet, the simulation
+        // is stopped with an error message.
+        /////////////////////////////////////////////////////////////////////
+
+        switch(r_vci_tgt_fsm) {
+
+            case TGT_IDLE:
+                if ( p_vci_tgt.cmdval.read() ) 
+                {
+                    addr_40 address = p_vci_tgt.address.read();
+
+                    if ( p_vci_tgt.cmd.read() != vci_param::CMD_WRITE) 
+                    {
+                        std::cout << "error in component VCI_CC_XCACHE_WRAPPER " << name() << std::endl;
+                        std::cout << " for the vci_address : " << std::hex << p_vci_tgt.address << std::endl;
+                        std::cout << "the received VCI command from " << std::hex << p_vci_tgt.srcid.read() << " is not a write" << std::endl;
+                        exit(0);
+                    }
+
+                    // multi-update or multi-invalidate for data type
+                    if ( ((address&0x3) != 0x3) && (! m_segment.contains(address)) ) 
+                    {
+                        std::cout << "error in component VCI_CC_XCACHE_WRAPPER " << name() << std::endl;
+                        std::cout << "out of segment VCI command received for a multi-updt or multi-inval request" << std::endl;
+                        exit(0);
+                    }
+
+                    r_tgt_addr = (((addr_40) ((p_vci_tgt.be.read() & 0x3) << 32)) | 
+                                 ((addr_40) (p_vci_tgt.wdata.read()))) * m_dcache_words * 4;      
+                    r_tgt_srcid = p_vci_tgt.srcid.read();
+                    r_tgt_trdid = p_vci_tgt.trdid.read();
+                    r_tgt_pktid = p_vci_tgt.pktid.read();
+                    r_tgt_plen  = p_vci_tgt.plen.read();
+                    
+                    if ( (address&0x3) == 0x3 )   // broadcast invalidate for data or instruction type
+                    {
+                        if ( ! p_vci_tgt.eop.read() ) 
+                        {
+                            std::cout << "error in component VCI_CC_XCACHE_WRAPPER " << name() << std::endl;
+                            std::cout << "the BROADCAST INVALIDATE command length must be one word" << std::endl;
+                            exit(0);
+                        }
+                        r_tgt_update = false; 
+                        r_tgt_brdcast= true;
+                        r_vci_tgt_fsm = TGT_REQ_BROADCAST;
+                        m_cpt_cc_inval++ ;
+                    }
+                    else                    // multi-update or multi-invalidate for data type
+                    { 
+                        uint32_t cell = address - m_segment.baseAddress(); // addr_40
+                        r_tgt_brdcast = false;
+                        if (cell == 0) 
+                        {                               // invalidate 
+                            if ( ! p_vci_tgt.eop.read() ) 
+                            {
+                                std::cout << "error in component VCI_CC_XCACHE_WRAPPER " << name() << std::endl;
+                                std::cout << "the MULTI-INVALIDATE command length must be one word" << std::endl;
+                                exit(0);
+                            }
+                            r_tgt_update = false; 
+                            r_vci_tgt_fsm = TGT_REQ_DCACHE;
+                            m_cpt_cc_inval++ ;
+                        } 
+                        else if (cell == 4)                  // update data
+                        {                                
+                            if ( p_vci_tgt.eop.read() ) 
+                            {
+                                std::cout << "error in component VCI_CC_VCACHE_WRAPPER " << name() << std::endl;
+                                std::cout << "the MULTI-UPDATE command length must be N+2 words" << std::endl;
+                                exit(0);
+                            }
+                            r_data_update  = true;
+                            r_tgt_update   = true; 
+                            r_vci_tgt_fsm  = TGT_UPDT_WORD;
+                            m_cpt_cc_update++ ;
+                        } 
+                        else if (cell == 8)                  // invalidate instruction
+                        {                         
+                            if ( ! p_vci_tgt.eop.read() ) 
+                            {
+                                std::cout << "error in component VCI_CC_VCACHE_WRAPPER " << name() << std::endl;
+                                std::cout << "the MULTI-INVALIDATE command length must be one word" << std::endl;
+                                exit(0);
+                            }
+                            r_tgt_update = false; 
+                            r_vci_tgt_fsm = TGT_REQ_ICACHE;
+                            m_cpt_cc_inval++ ;
+                        } 
+                        else if (cell == 12)                  // update ins
+                        {                                
+                            if ( p_vci_tgt.eop.read() ) 
+                            {
+                                std::cout << "error in component VCI_CC_VCACHE_WRAPPER " << name() << std::endl;
+                                std::cout << "the MULTI-UPDATE command length must be N+2 words" << std::endl;
+                                exit(0);
+                            }
+                            r_data_update = false;
+                            r_tgt_update  = true; 
+                            r_vci_tgt_fsm = TGT_UPDT_WORD;
+                            m_cpt_cc_update++ ;
+                        } 
+
+                    } // end if address
+                } // end if cmdval
+                break;
+
+            case TGT_UPDT_WORD:
+                if (p_vci_tgt.cmdval.read()) 
+                {
+                    if ( p_vci_tgt.eop.read() ) 
+                    {
+                        std::cout << "error in component VCI_CC_XCACHE_WRAPPER " << name() << std::endl;
+                        std::cout << "the MULTI-UPDATE command length must be N+2 words" << std::endl;
+                        exit(0);
+                    }
+                    for ( size_t i=0 ; i<m_dcache_words ; i++ ) r_tgt_be[i] = 0;
+                    r_tgt_word = p_vci_tgt.wdata.read(); // the first modified word index
+                    r_vci_tgt_fsm = TGT_UPDT_DATA;
+                }
+                break;
+
+            case TGT_UPDT_DATA:
+                if (p_vci_tgt.cmdval.read()) 
+                {
+                    size_t word = r_tgt_word.read();
+                    if ( word >= m_dcache_words ) 
+                    {
+                        std::cout << "error in component VCI_CC_XCACHE_WRAPPER " << name() << std::endl;
+                        std::cout << "the received MULTI-UPDATE command length is wrong" << std::endl;
+                        exit(0);
+                    }
+                    r_tgt_buf[word] = p_vci_tgt.wdata.read();
+                    r_tgt_be[word] = p_vci_tgt.be.read();
+                    r_tgt_word = word + 1;
+                    if (p_vci_tgt.eop.read()) {
+                        if (r_data_update.read())  r_vci_tgt_fsm = TGT_REQ_DCACHE;
+                        else r_vci_tgt_fsm = TGT_REQ_ICACHE;
+                    }
+                }
+                break;
+
+            case TGT_REQ_BROADCAST:
+                if ( !r_tgt_icache_req.read() && !r_tgt_dcache_req.read() ) 
+                {
+                    r_vci_tgt_fsm = TGT_RSP_BROADCAST; 
+                    r_tgt_icache_req = true;
+                    r_tgt_dcache_req = true;
+                }
+                break;
+                ////////////////////
+            case TGT_REQ_ICACHE:
+                {
+                    if ( !r_tgt_icache_req.read() ) 
+                    {
+                        r_vci_tgt_fsm = TGT_RSP_ICACHE; 
+                        r_tgt_icache_req = true;
+                    }
+                    break;
+                }
+
+            case TGT_REQ_DCACHE:
+                if ( !r_tgt_dcache_req.read() ) 
+                {
+                    r_vci_tgt_fsm = TGT_RSP_DCACHE; 
+                    r_tgt_dcache_req = true;
+                }
+                break;
+
+            case TGT_RSP_BROADCAST:
+                if ( !r_tgt_icache_req.read() && !r_tgt_dcache_req.read() ) 
+                {
+                    // one response
+                    if ( !r_tgt_icache_rsp || !r_tgt_dcache_rsp )
+                    {
+                        if ( p_vci_tgt.rspack.read() )
+                        {
+                            r_vci_tgt_fsm = TGT_IDLE; 
+                            r_tgt_icache_rsp = false;
+                            r_tgt_dcache_rsp = false;
+                        }
+                    }
+
+                    // if data and instruction have the inval line, need two responses  
+                    if ( r_tgt_icache_rsp && r_tgt_dcache_rsp )
+                    {
+                        if ( p_vci_tgt.rspack.read() )
+                        {
+                            r_tgt_icache_rsp = false; // only reset one for respond the second time 
+                        }
+                    }
+
+                    // if there is no need for a response
+                    if ( !r_tgt_icache_rsp && !r_tgt_dcache_rsp )
+                    {
+                        r_vci_tgt_fsm = TGT_IDLE;
+                    }
+
+                }
+                break;
+                ////////////////////
+            case TGT_RSP_ICACHE:
+                {
+                    if ( (p_vci_tgt.rspack.read() || !r_tgt_icache_rsp.read()) && !r_tgt_icache_req.read() ) 
+                    {
+                        r_vci_tgt_fsm = TGT_IDLE;
+                        r_tgt_icache_rsp = false; 
+                    }
+                    break;
+                }
+
+            case TGT_RSP_DCACHE:
+                {
+                    if ( (p_vci_tgt.rspack.read() || !r_tgt_dcache_rsp.read()) && !r_tgt_dcache_req.read() ) 
+                    {
+                        r_vci_tgt_fsm = TGT_IDLE;
+                        r_tgt_dcache_rsp = false; 
+                    }
+                    break;
+                }
+        } // end switch TGT_FSM
+
+        /////////////////////////////////////////////////////////////////////
+        // The ICACHE FSM controls the following ressources:
+        // - r_icache_fsm
+        // - r_icache_fsm_save
+        // - r_icache instruction cache access
+        // - r_icache_addr_save
+        // - r_icache_miss_req set
+        // - r_icache_unc_req set
+        // - r_icache_buf_unc_valid set
+        // - r_vci_rsp_ins_error reset
+        // - r_tgt_icache_req reset
+        // - ireq & irsp structures for communication with the processor
+        //
+        // 1/ External requests (update or invalidate) have highest priority.
+        //    They are taken into account in the IDLE and WAIT states.
+        //    As external hit should be extremly rare on the ICACHE,
+        //    all external requests are handled as invalidate...
+        //    In case of external request the ICACHE FSM goes to the CC_CHECK
+        //    state to test the external hit, and returns in the
+        //    pre-empted state after completion.
+        // 2/ Processor requests are taken into account only in the IDLE state.
+        //    In case of MISS, or in case of uncached instruction, the FSM 
+        //    writes the missing address line in the  r_icache_addr_save register 
+        //    and sets the r_icache_miss_req or the r_icache_unc_req flip-flops.
+        //    These request flip-flops are reset by the VCI_RSP FSM
+        //    when the VCI transaction is completed and the r_icache_buf_unc_valid
+        //    is set in case of uncached access.
+        //    In case of bus error, the VCI_RSP FSM sets the r_vci_rsp_ins_error 
+        //    flip-flop. It is reset by the ICACHE FSM.
+        ///////////////////////////////////////////////////////////////////////
+
+        typename iss_t::InstructionRequest  ireq = ISS_IREQ_INITIALIZER;
+        typename iss_t::InstructionResponse irsp = ISS_IRSP_INITIALIZER;
+
+        typename iss_t::DataRequest  dreq = ISS_DREQ_INITIALIZER;
+        typename iss_t::DataResponse drsp = ISS_DRSP_INITIALIZER;
+
+        m_iss.getRequests( ireq, dreq );
+
+#if DEBUG_CC_XCACHE_WRAPPER
+        std::cout << " Instruction Request: " << ireq << std::endl;
+#endif
+
+        switch(r_icache_fsm) {
+            /////////////////
+            case ICACHE_IDLE:
+                {
+                    if ( r_tgt_icache_req ) {   // external request
+                        if ( ireq.valid ) m_cost_ins_miss_frz++;
+                        r_icache_fsm = ICACHE_CC_CHECK;
+                        r_icache_fsm_save = r_icache_fsm;
+                        break;
+                    } 
+                    if ( ireq.valid ) {
+                        data_t  icache_ins = 0;
+                        bool    icache_hit = false;
+                        bool    icache_cached = m_cacheability_table[(vci_addr_t)ireq.addr];
+                        // icache_hit & icache_ins evaluation
+                        if ( icache_cached ) {
+                            icache_hit = r_icache.read((vci_addr_t) ireq.addr, &icache_ins);
+                        } else {
+                            icache_hit = ( r_icache_buf_unc_valid && ((addr_40) ireq.addr == (addr_40)r_icache_addr_save) );
+                            icache_ins = r_icache_miss_buf[0];
+                        }
+                        if ( ! icache_hit ) {
+                            m_cpt_ins_miss++;
+                            m_cost_ins_miss_frz++;
+                            r_icache_addr_save = (addr_40) ireq.addr;
+                            if ( icache_cached ) {
+                                r_icache_fsm = ICACHE_MISS_WAIT;
+                                r_icache_miss_req = true;
+                            } else {
+                                r_icache_fsm = ICACHE_UNC_WAIT;
+                                r_icache_unc_req = true;
+                            }
+                        } else {
+                            r_icache_buf_unc_valid = false;
+                        }
+                        m_cpt_icache_dir_read += m_icache_ways;
+                        m_cpt_icache_data_read += m_icache_ways;
+                        irsp.valid          = icache_hit;
+                        irsp.instruction    = icache_ins;
+                    }
+                    break;
+                }
+                //////////////////////
+            case ICACHE_MISS_WAIT:
+                {
+                    m_cost_ins_miss_frz++;
+                    if ( r_tgt_icache_req ) {   // external request
+                        r_icache_fsm = ICACHE_CC_CHECK;
+                        r_icache_fsm_save = r_icache_fsm;
+                        break;
+                    } 
+                    if ( !r_icache_miss_req && !r_icache_inval_rsp ) { // Miss read response and no invalidation
+                        if ( r_vci_rsp_ins_error ) {
+                            r_icache_fsm = ICACHE_ERROR;
+                        } else {
+                            r_icache_fsm = ICACHE_MISS_UPDT;
+                        }
+                    }
+                    if ( !r_icache_miss_req && r_icache_inval_rsp ) { // Miss read response and invalidation
+                        if ( r_vci_rsp_ins_error ) {
+                            r_icache_inval_rsp = false;
+                            r_icache_fsm = ICACHE_ERROR;
+                        } else {
+                            r_icache_inval_rsp = false;
+                            r_icache_fsm = ICACHE_CC_CLEANUP;
+                        }
+                    }
+                    break;
+                }
+                /////////////////////
+            case ICACHE_UNC_WAIT:
+                {
+                    m_cost_ins_miss_frz++;
+                    if ( r_tgt_icache_req ) {   // external request
+                        r_icache_fsm = ICACHE_CC_CHECK;
+                        r_icache_fsm_save = r_icache_fsm;
+                        break;
+                    } 
+                    if ( !r_icache_unc_req ) {
+                        if ( r_vci_rsp_ins_error ) {
+                            r_icache_fsm = ICACHE_ERROR;
+                        } else {
+                            r_icache_fsm = ICACHE_IDLE;
+                            r_icache_buf_unc_valid = true;
+                        }
+                    }
+                    break;
+                }
+                //////////////////
+            case ICACHE_ERROR:
+                {
+                    r_icache_fsm = ICACHE_IDLE;
+                    r_vci_rsp_ins_error = false;
+                    irsp.error          = true;
+                    irsp.valid          = true;
+                    break;
+                }
+                //////////////////////
+            case ICACHE_MISS_UPDT: 
+                {
+                    if ( r_tgt_icache_req ) {   // external request
+                        r_icache_fsm = ICACHE_CC_CHECK;
+                        r_icache_fsm_save = r_icache_fsm;
+                        break;
+                    } 
+                    if(!r_icache_cleanup_req.read() && !r_icache_inval_rsp){
+                        vci_addr_t ad   = 0;
+                        ad              = (vci_addr_t) r_icache_addr_save.read();
+                        data_t*   buf   = r_icache_miss_buf;
+                        vci_addr_t victim_index = 0;
+                        m_cpt_icache_dir_write++;
+                        m_cpt_icache_data_write++;
+                        if ( ireq.valid ) m_cost_ins_miss_frz++;
+
+                        r_icache_cleanup_req  = r_icache.update(ad, buf, &victim_index);
+                        r_icache_cleanup_line = (addr_40) victim_index;
+
+                        r_icache_fsm        = ICACHE_IDLE;
+                        break;
+                    }
+                    if(r_icache_inval_rsp){
+                        if ( ireq.valid ) m_cost_ins_miss_frz++;
+                        r_icache_inval_rsp  = false;
+                        r_icache_fsm = ICACHE_CC_CLEANUP;
+                        break;
+                    }
+                    if ( ireq.valid ) m_cost_ins_miss_frz++;
+                }
+                ////////////////////
+            case ICACHE_CC_CLEANUP:
+                {
+                    // external cache invalidate request
+                    if ( r_tgt_icache_req )     
+                    {
+                        r_icache_fsm = ICACHE_CC_CHECK;
+                        r_icache_fsm_save = r_icache_fsm;
+                        break;
+                    }
+                    // cleanup
+                    if(!r_icache_cleanup_req){
+                        r_icache_cleanup_req = true;
+                        r_icache_cleanup_line = r_icache_addr_save.read() >> (uint32_log2(m_icache_words) + 2);   
+                        r_icache_fsm = ICACHE_IDLE;
+                    }
+                    break;
+                }
+            case ICACHE_CC_CHECK:   // read directory in case of invalidate or update request
+                {
+
+                    m_cpt_icache_dir_read += m_icache_ways;
+                    m_cpt_icache_data_read += m_icache_ways;
+                    addr_40  ad           = r_tgt_addr;
+                    data_t  icache_rdata = 0;
+
+                    if(( ( r_icache_fsm_save == ICACHE_MISS_WAIT ) || ( r_icache_fsm_save == ICACHE_MISS_UPDT ) ) && 
+                            ( (r_icache_addr_save.read() & ~((m_icache_words<<2)-1)) == (ad & ~((m_icache_words<<2)-1)))) {
+                        r_icache_inval_rsp = true;
+                        r_tgt_icache_req = false;
+                        if(r_tgt_update){    // Also send a cleanup and answer
+                            r_tgt_icache_rsp     = true;
+                        } else {            // Also send a cleanup but don't answer
+                            r_tgt_icache_rsp     = false;
+                        }
+                        r_icache_fsm = r_icache_fsm_save;
+                    } else {
+                        bool    icache_hit   = r_icache.read(ad, &icache_rdata);
+                        if ( icache_hit && r_tgt_update ) {
+                            r_icache_fsm = ICACHE_CC_UPDT;
+                            // complete the line buffer in case of update
+                            for ( size_t word = 0 ; word < m_icache_words ; word++ ) {
+                                data_t mask = vci_param::be2mask(r_tgt_be[word]);
+                                addr_40  ad = addr_40 (r_tgt_addr.read() + word*4); //(addr_40)word;
+                                r_icache.read(ad, &icache_rdata);
+                                r_tgt_buf[word] = (mask & r_tgt_buf[word]) | (~mask & icache_rdata);
+                            }
+                        } else if ( icache_hit && !r_tgt_update ) {
+                            r_icache_fsm = ICACHE_CC_INVAL;
+                        } else { // instruction not found (can happen)
+                            r_tgt_icache_req = false;
+                            if(r_tgt_update){
+                                r_tgt_icache_rsp = true;
+                            } else {
+                                r_tgt_icache_rsp = false;
+                            }
+                            r_icache_fsm = r_icache_fsm_save;
+                        }
+                    }
+                    break;
+                }
+                ///////////////////
+            case ICACHE_CC_UPDT:    // update directory and data cache        
+                {
+                    m_cpt_icache_dir_write++;
+                    m_cpt_icache_data_write++;
+                    addr_40  ad     = r_tgt_addr;
+                    data_t* buf     = r_tgt_buf;
+                    for(size_t i=0; i<m_icache_words; i++){
+                        if(r_tgt_be[i]) r_icache.write( ad + i*4, buf[i]);
+                    }
+                    r_tgt_icache_req = false;
+                    r_tgt_icache_rsp = true;
+                    r_icache_fsm = r_icache_fsm_save;
+                    break;
+                }
+
+                /////////////////////
+            case ICACHE_CC_INVAL:   // invalidate a cache line
+                {
+                    addr_40  ad      = r_tgt_addr;
+                    r_tgt_icache_rsp = r_icache.inval(ad);
+                    r_tgt_icache_req = false;
+                    r_icache_fsm = r_icache_fsm_save;
+                    break;
+                }
+
+        } // end switch r_icache_fsm
+
+#if DEBUG_CC_XCACHE_WRAPPER
+        std::cout << " Instruction Response: " << irsp << std::endl;
+#endif
+
+        //////////////////////////////////////////////////////////////////////://///////////
+        // The DCACHE FSM controls the following ressources:
+        // - r_dcache_fsm
+        // - r_dcache_fsm_save
+        // - r_dcache (data cache access)
+        // - r_dcache_addr_save
+        // - r_dcache_wdata_save
+        // - r_dcache_rdata_save
+        // - r_dcache_type_save
+        // - r_dcache_be_save
+        // - r_dcache_cached_save
+        // - r_dcache_miss_req set
+        // - r_dcache_unc_req set
+        // - r_dcache_write_req set
+        // - r_dcache_cleanup_req set
+        // - r_vci_rsp_data_error reset
+        // - r_tgt_dcache_req reset
+        // - r_wbuf write
+        // - dreq & drsp structures for communication with the processor
+        //
+        // 1/ EXTERNAL REQUEST : 
+        //    There is an external request when the tgt_dcache req flip-flop is set,
+        //    requesting a line invalidation or a line update. 
+        //    External requests are taken into account in the states  IDLE, WRITE_REQ,  
+        //    UNC_WAIT, MISS_WAIT, and have the highest priority :
+        //    The actions associated to the pre-empted state are not executed, the DCACHE FSM
+        //    goes to the CC_CHECK state to execute the requested action, and returns to the
+        //    pre-empted state.
+        //  2/ PROCESSOR REQUEST : 
+        //   In order to support VCI write burst, the processor requests are taken into account
+        //   in the WRITE_REQ state as well as in the IDLE state.
+        //   - In the IDLE state, the processor request cannot be satisfied if
+        //   there is a cached read miss, or an uncached read.
+        //   - In the WRITE_REQ state, the request cannot be satisfied if
+        //   there is a cached read miss, or an uncached read,
+        //   or when the write buffer is full.
+        //   - In all other states, the processor request is not satisfied.
+        //
+        //   The cache access takes into account the cacheability_table.
+        //   In case of processor request, there is five conditions to exit the IDLE state:
+        //   - CACHED READ MISS => to the MISS_WAIT state (waiting the r_miss_ok signal), 
+        //     then to the MISS_UPDT state, and finally to the IDLE state.
+        //   - UNCACHED READ  => to the UNC_WAIT state (waiting the r_miss_ok signal), 
+        //     and to the IDLE state.
+        //   - CACHE INVALIDATE HIT => to the INVAL state for one cycle, then to IDLE state.
+        //   - WRITE MISS => directly to the WRITE_REQ state to access the write buffer.
+        //   - WRITE HIT => to the WRITE_UPDT state, then to the WRITE_REQ state.
+        //
+        // Error handling :  Read Bus Errors are synchronous events, but
+        // Write Bus Errors are asynchronous events (processor is not frozen).
+        // - If a Read Bus Error is detected, the VCI_RSP FSM sets the
+        //   r_vci_rsp_data_error flip-flop, and the synchronous error is signaled
+        //   by the DCACHE FSM.
+        // - If a Write Bus Error is detected, the VCI_RSP FSM  signals
+        //   the asynchronous error using the setWriteBerr() method.
+        ///////////////////////////////////////////////////////////////////////////////////
+
+#if DEBUG_CC_XCACHE_WRAPPER
+        std::cout << " Data Request: " << dreq << std::endl;
+#endif
+
+        //if( (m_cpt_total_cycles % 10000) ==0 ) std::cout << std::dec << "Proc " << m_srcid << " Data Request: " << dreq << std::endl;
+
+        switch ( r_dcache_fsm ) {
+
+            /////////////////////
+            case DCACHE_WRITE_REQ:
+                { 
+                    if ( r_tgt_dcache_req ) {   // external request
+                        r_dcache_fsm = DCACHE_CC_CHECK;
+                        r_dcache_fsm_save = r_dcache_fsm;
+                        break;
+                    }
+                    // try to post the write request in the write buffer
+                    if ( !r_dcache_write_req ) {    // no previous write transaction     
+                        if ( r_wbuf.wok(r_dcache_addr_save) ) {   // write request in the same cache line
+                            r_wbuf.write(r_dcache_addr_save, r_dcache_be_save, r_dcache_wdata_save);
+                            // close the write packet if uncached
+                            if ( !r_dcache_cached_save ){
+                                r_dcache_write_req = true ;
+                            }
+                        } else {    
+                            // close the write packet if write request not in the same cache line
+                            r_dcache_write_req = true;  
+                            if(!m_srcid_rw) {
+                            }
+                            m_cost_write_frz++;
+                            break;  // posting request not possible : stay in DCACHE_WRITEREQ state
+                        }
+                    } else {    //  previous write transaction not completed
+                        m_cost_write_frz++;
+                        break;  // posting request not possible : stay in DCACHE_WRITEREQ state  
+                    }
+
+                    // close the write packet if the next processor request is not a write 
+                    if ( !dreq.valid || (dreq.type != iss_t::DATA_WRITE) ) {
+                        r_dcache_write_req = true ;
+                    }
+
+                    // The next state and the processor request parameters are computed 
+                    // as in the DCACHE_IDLE state (see below ...)
+                }
+                /////////////////
+            case DCACHE_IDLE:
+                {
+                    if ( r_tgt_dcache_req ) {   // external request
+                        r_dcache_fsm = DCACHE_CC_CHECK;
+                        r_dcache_fsm_save = r_dcache_fsm;
+                        break;
+                    } 
+
+                    if ( dreq.valid ) {              
+                        bool        dcache_hit     = false;
+                        data_t      dcache_rdata   = 0;
+                        bool        dcache_cached;
+                        m_cpt_dcache_data_read += m_dcache_ways;
+                        m_cpt_dcache_dir_read += m_dcache_ways;
+
+                        // dcache_cached evaluation
+                        switch (dreq.type) {
+                            case iss_t::DATA_LL:
+                            case iss_t::DATA_SC:
+                            case iss_t::XTN_READ:
+                            case iss_t::XTN_WRITE:
+                                dcache_cached = false;
+                                break;
+                            default:
+                                dcache_cached = m_cacheability_table[(vci_addr_t)dreq.addr];
+                        }
+
+                        // dcache_hit & dcache_rdata evaluation
+                        if ( dcache_cached ) {
+                            dcache_hit = r_dcache.read((vci_addr_t) dreq.addr, &dcache_rdata);
+                        } else {
+                            dcache_hit = ( r_dcache_buf_unc_valid.read() && ((addr_40) dreq.addr == (addr_40)r_dcache_addr_save) );
+                            dcache_rdata = r_dcache_miss_buf[0];
+                        }
+
+                        switch( dreq.type ) {
+                            case iss_t::DATA_READ:
+                            case iss_t::DATA_LL:
+                            case iss_t::DATA_SC:
+                                m_cpt_read++;
+                                if ( dcache_hit ) {
+                                    r_dcache_fsm = DCACHE_IDLE;
+                                    drsp.valid = true;
+                                    drsp.rdata = dcache_rdata;
+                                    r_dcache_buf_unc_valid = false;
+                                } else {
+                                    if ( dcache_cached ) {
+                                        m_cpt_data_miss++;
+                                        m_cost_data_miss_frz++;
+                                        r_dcache_miss_req = true;
+                                        r_dcache_fsm = DCACHE_MISS_WAIT;
+                                    } else {
+                                        m_cpt_unc_read++;
+                                        m_cost_unc_read_frz++;
+                                        r_dcache_unc_req = true;
+                                        r_dcache_fsm = DCACHE_UNC_WAIT;
+                                    }
+                                }
+                                break;
+                            case iss_t::XTN_READ:
+                            case iss_t::XTN_WRITE:
+                                // only DCACHE INVALIDATE request are supported
+                                if ( dreq.addr/4 == iss_t::XTN_DCACHE_INVAL ){
+                                    r_dcache_fsm = DCACHE_INVAL;
+                                } else {
+                                    r_dcache_fsm = DCACHE_IDLE;
+                                }
+                                drsp.valid = true;
+                                drsp.rdata = 0;
+                                break;
+                            case iss_t::DATA_WRITE:
+                                m_cpt_write++;
+                                if ( dcache_hit && dcache_cached ) {
+                                    r_dcache_fsm = DCACHE_WRITE_UPDT;
+                                    m_cpt_write_cached++;
+                                } else {
+                                    r_dcache_fsm = DCACHE_WRITE_REQ;
+                                }
+                                drsp.valid = true;
+                                drsp.rdata = 0;
+                                break;
+                        } // end switch dreq.type
+
+                        r_dcache_addr_save      = (addr_40) dreq.addr;
+                        r_dcache_type_save      = dreq.type;
+                        r_dcache_wdata_save     = dreq.wdata;
+                        r_dcache_be_save        = dreq.be;
+                        r_dcache_rdata_save     = dcache_rdata;
+                        r_dcache_cached_save    = dcache_cached;
+
+                    } else {    // end if dreq.valid
+                        r_dcache_fsm = DCACHE_IDLE;
+                    }
+                    // processor request are not accepted in the WRITE_REQUEST state
+                    // when the write buffer is not writeable
+                    if ( (r_dcache_fsm == DCACHE_WRITE_REQ) &&
+                            (r_dcache_write_req || !r_wbuf.wok(r_dcache_addr_save)) ) {
+                        drsp.valid = false;
+                        drsp.rdata = 0;
+                    }
+                    break;
+                }
+                ///////////////////////
+            case DCACHE_WRITE_UPDT:
+                {
+                    m_cpt_dcache_data_write++;
+                    data_t mask = vci_param::be2mask(r_dcache_be_save);
+                    data_t wdata = (mask & r_dcache_wdata_save) | (~mask & r_dcache_rdata_save);
+                    vci_addr_t ad = r_dcache_addr_save.read();
+                    r_dcache.write(ad, wdata);
+                    r_dcache_fsm = DCACHE_WRITE_REQ;
+                    break;
+                }
+                //////////////////////
+            case DCACHE_MISS_WAIT:
+                {
+
+                    if ( dreq.valid ) m_cost_data_miss_frz++;
+                    if ( r_tgt_dcache_req.read() ) {   // external request
+                        r_dcache_fsm = DCACHE_CC_CHECK;
+                        r_dcache_fsm_save = r_dcache_fsm;
+                        break;
+                    }
+                    if ( !r_dcache_miss_req && !r_dcache_inval_rsp ) { // Miss read response and no invalidation
+                        if ( r_vci_rsp_data_error ) {
+                            r_dcache_fsm = DCACHE_ERROR;
+                        } else {
+                            r_dcache_fsm = DCACHE_MISS_UPDT;
+                        }
+                        break;
+                    }
+                    if ( !r_dcache_miss_req && r_dcache_inval_rsp ) { // Miss read response and invalidation
+                        if ( r_vci_rsp_data_error ) {
+                            r_dcache_inval_rsp  = false;
+                            r_dcache_fsm = DCACHE_ERROR;
+                        } else {
+                            r_dcache_inval_rsp  = false;
+                            r_dcache_fsm = DCACHE_CC_CLEANUP;
+                        }
+                        break;
+                    }
+                    break;
+                }
+                //////////////////////
+            case DCACHE_MISS_UPDT:
+
+                {
+                        if ( r_tgt_dcache_req.read() ) {   // external request
+                        r_dcache_fsm = DCACHE_CC_CHECK;
+                        r_dcache_fsm_save = r_dcache_fsm;
+                        break;
+                    }
+                    if( !r_dcache_cleanup_req.read() && !r_dcache_inval_rsp ){
+                        vci_addr_t  ad  = 0;
+                        ad = (vci_addr_t) r_dcache_addr_save.read();
+                        data_t* buf = new data_t[m_dcache_words];
+                        for(size_t i=0; i<m_dcache_words; i++) {
+                            buf[i] = r_dcache_miss_buf[i];
+                        }
+                        vci_addr_t  victim_index = 0;
+                        if ( dreq.valid ) m_cost_data_miss_frz++;
+                        m_cpt_dcache_data_write++;
+                        m_cpt_dcache_dir_write++;
+
+                        r_dcache_cleanup_req = r_dcache.update(ad, buf, &victim_index);
+                        r_dcache_cleanup_line = (addr_40) victim_index;
+
+                        r_dcache_fsm = DCACHE_IDLE;
+                        delete [] buf;
+                        break;
+                    }
+                    if( r_dcache_inval_rsp ){
+                        r_dcache_inval_rsp  = false;
+                        r_dcache_fsm = DCACHE_CC_CLEANUP;
+                        break;
+                    }
+                    break;
+                }
+                ////////////////////
+            case DCACHE_UNC_WAIT:
+                {
+                    if ( dreq.valid ) m_cost_unc_read_frz++;
+                    if ( r_tgt_dcache_req ) {   // external request
+                        r_dcache_fsm = DCACHE_CC_CHECK;
+                        r_dcache_fsm_save = r_dcache_fsm;
+                        break;
+                    } 
+                    if ( !r_dcache_unc_req ) {
+                        if ( r_vci_rsp_data_error ) {
+                            r_dcache_fsm = DCACHE_ERROR;
+                        } else {
+                            r_dcache_fsm = DCACHE_IDLE;
+                            // If request was a DATA_SC we need to invalidate the corresponding cache line,
+                            // so that subsequent access to this line are read from RAM
+                            if (dreq.type == iss_t::DATA_SC) {
+                                r_dcache_fsm = DCACHE_INVAL;
+                            }
+                            r_dcache_buf_unc_valid = true;
+                        }
+                    }
+                    break;
+                }
+                //////////////////
+            case DCACHE_ERROR:
+                {
+                    r_dcache_fsm = DCACHE_IDLE;
+                    r_vci_rsp_data_error = false;
+                    drsp.error = true;
+                    drsp.valid = true;
+                    break;
+                }
+                /////////////////    
+            case DCACHE_INVAL:
+                {
+                    if ( r_tgt_dcache_req.read() ) {   // external request
+                        r_dcache_fsm = DCACHE_CC_CHECK;
+                        r_dcache_fsm_save = r_dcache_fsm;
+                        break;
+                    }
+                    if( !r_dcache_cleanup_req.read() ){
+                        m_cpt_dcache_dir_read += m_dcache_ways;
+                        vci_addr_t  ad  = r_dcache_addr_save.read();
+                        r_dcache_cleanup_req = r_dcache.inval(ad);
+                        r_dcache_cleanup_line = r_dcache_addr_save.read() >> (uint32_log2(m_dcache_words)+2);
+
+                        r_dcache_fsm = DCACHE_IDLE;
+                    }
+                    break;
+                }
+                /////////////////////
+            case DCACHE_CC_CHECK:   // read directory in case of invalidate or update request
+                {
+
+                    m_cpt_dcache_dir_read += m_dcache_ways;
+                    m_cpt_dcache_data_read += m_dcache_ways;
+                    addr_40  ad           = r_tgt_addr;
+                    data_t  dcache_rdata = 0;
+
+                    if(( ( r_dcache_fsm_save == DCACHE_MISS_WAIT ) || ( r_dcache_fsm_save == DCACHE_MISS_UPDT ) ) && 
+                            ( (r_dcache_addr_save.read() & ~((m_dcache_words<<2)-1)) == (ad & ~((m_dcache_words<<2)-1)))) {
+                        r_dcache_inval_rsp = true;
+                        r_tgt_dcache_req = false;
+                        if(r_tgt_update){    // Also send a cleanup and answer
+                            r_tgt_dcache_rsp     = true;
+                        } else {            // Also send a cleanup but don't answer
+                            r_tgt_dcache_rsp     = false;
+                        }
+                        r_dcache_fsm = r_dcache_fsm_save;
+                    } else {
+                        bool    dcache_hit   = r_dcache.read(ad, &dcache_rdata);
+                        if ( dcache_hit && r_tgt_update ) {
+                            r_dcache_fsm = DCACHE_CC_UPDT;
+                            // complete the line buffer in case of update
+                            for ( size_t word = 0 ; word < m_dcache_words ; word++ ) {
+                                addr_40  ad = addr_40 (r_tgt_addr.read() + word*4); //(addr_40)word;
+                                data_t mask = vci_param::be2mask(r_tgt_be[word]);
+                                r_dcache.read(ad, &dcache_rdata);
+                                r_tgt_buf[word] = (mask & r_tgt_buf[word]) | (~mask & dcache_rdata);
+                            }
+                        } else if ( dcache_hit && !r_tgt_update ) {
+                            r_dcache_fsm = DCACHE_CC_INVAL;
+                        } else { // data not found (can happen) 
+                            if(r_tgt_update){
+                                r_tgt_dcache_rsp = true;
+                            } else {
+                                r_tgt_dcache_rsp = false;
+                            }
+                            r_tgt_dcache_req = false;
+                            r_dcache_fsm = r_dcache_fsm_save;
+                        }
+                    }
+                    break;
+                }
+                ///////////////////
+            case DCACHE_CC_UPDT:    // update directory and data cache        
+                {
+                    m_cpt_dcache_dir_write++;
+                    m_cpt_dcache_data_write++;
+                    addr_40  ad      = r_tgt_addr;
+                    data_t* buf     = r_tgt_buf;
+                    for(size_t i=0; i<m_dcache_words; i++){
+                        if(r_tgt_be[i]) r_dcache.write( ad + i*4, buf[i]);
+                    }
+                    r_tgt_dcache_req = false;
+                    r_tgt_dcache_rsp = true;
+                    r_dcache_fsm = r_dcache_fsm_save;
+                    break;
+                }
+                /////////////////////
+            case DCACHE_CC_INVAL:   // invalidate a cache line
+                {
+                    addr_40  ad      = r_tgt_addr;
+                    r_tgt_dcache_rsp = r_dcache.inval(ad);
+                    r_tgt_dcache_req = false;
+                    r_dcache_fsm = r_dcache_fsm_save;
+                    break;
+                }
+             ///////////////////
+            case DCACHE_CC_CLEANUP:   
+                {
+                    // external cache invalidate request
+                    if ( r_tgt_dcache_req )   
+                    {
+                        r_dcache_fsm = DCACHE_CC_CHECK;
+                        r_dcache_fsm_save = r_dcache_fsm;
+                        break;
+                    }        
+                    // cleanup
+                    if(!r_dcache_cleanup_req){
+                        r_dcache_cleanup_req = true;
+                        r_dcache_cleanup_line = r_dcache_addr_save.read() >> (uint32_log2(m_dcache_words) + 2);
+                        r_dcache_fsm = DCACHE_IDLE;
+                    }
+                    break;
+                }    
+
+        } // end switch r_dcache_fsm
+
+#if DEBUG_CC_XCACHE_WRAPPER
+        std::cout << " Data Response: " << drsp << std::endl;
+#endif
+
+        /////////// execute one iss cycle /////////////////////////////////////////////
+        {
+            uint32_t it = 0;
+            for (size_t i=0; i<(size_t)iss_t::n_irq; i++) 
+                if(p_irq[i].read()) it |= (1<<i);
+            m_iss.executeNCycles(1, irsp, drsp, it);
+        }
+
+        if ( (ireq.valid && !irsp.valid) || (dreq.valid && !drsp.valid) ) m_cpt_frz_cycles++;
+
+
+        ////////////////////////////////////////////////////////////////////////////
+        // The VCI_CMD FSM controls the following ressources:
+        // - r_vci_cmd_fsm
+        // - r_vci_cmd_min
+        // - r_vci_cmd_max
+        // - r_vci_cmd_cpt
+        // - wbuf reset
+        //
+        // This FSM handles requests from both the DCACHE FSM & the ICACHE FSM.
+        // There is 7 request types, with the following priorities : 
+        // 1 - Instruction Miss     : r_icache_miss_req
+        // 2 - Data Write           : r_dcache_write_req
+        // 3 - Data Read Miss       : r_dcache_miss_req 
+        // 4 - Data Read Uncached   : r_dcache_unc_req 
+        // 5 - Instruction Cleanup  : r_icache_cleanup_req 
+        // 6 - Data Cleanup         : r_dcache_cleanup_req 
+        // There is at most one (CMD/RSP) VCI transaction, as both CMD_FSM 
+        // and RSP_FSM exit simultaneously the IDLE state.
+        //
+        // VCI formats:
+        // According to the VCI advanced specification, all read requests packets 
+        // (read Uncached, Miss data, Miss instruction) are one word packets.
+        // For write burst packets, all words must be in the same cache line,
+        // and addresses must be contiguous (the BE field is 0 in case of "holes").
+        //////////////////////////////////////////////////////////////////////////////
+
+        switch (r_vci_cmd_fsm) {
+
+            case CMD_IDLE:
+                if (r_vci_rsp_fsm != RSP_IDLE) break;
+
+                r_vci_cmd_cpt = 0;
+                if ( r_icache_cleanup_req ) { 
+                    r_vci_cmd_fsm = CMD_INS_CLEANUP; 
+                } else if ( r_dcache_cleanup_req ) { 
+                    r_vci_cmd_fsm = CMD_DATA_CLEANUP;
+                } else if ( r_icache_miss_req ) { 
+                    r_vci_cmd_fsm = CMD_INS_MISS; 
+                    m_cpt_imiss_transaction++;
+                } else if ( r_icache_unc_req ) { 
+                    r_vci_cmd_fsm = CMD_INS_UNC; 
+                    m_cpt_imiss_transaction++;
+                } else if ( r_dcache_write_req ) { 
+                    r_vci_cmd_fsm = CMD_DATA_WRITE;
+                    r_vci_cmd_cpt = r_wbuf.getMin();
+                    r_vci_cmd_min = r_wbuf.getMin();
+                    r_vci_cmd_max = r_wbuf.getMax(); 
+                    m_cpt_write_transaction++; 
+                    m_length_write_transaction += (r_wbuf.getMax() - r_wbuf.getMin() + 1); 
+                } else if ( r_dcache_miss_req ) { 
+                    r_vci_cmd_fsm = CMD_DATA_MISS;
+                    m_cpt_dmiss_transaction++; 
+                } else if ( r_dcache_unc_req ) { 
+                    r_vci_cmd_fsm = CMD_DATA_UNC;
+                    m_cpt_unc_transaction++; 
+                }
+                break;
+
+            case CMD_DATA_WRITE:
+                if ( p_vci_ini_rw.cmdack.read() ) {
+                    r_vci_cmd_cpt = r_vci_cmd_cpt + 1;
+                    if (r_vci_cmd_cpt == r_vci_cmd_max) {
+                        r_vci_cmd_fsm = CMD_IDLE ;
+                        r_wbuf.reset() ;
+                    }
+                }
+                break;
+
+            case CMD_INS_MISS:
+            case CMD_INS_UNC:
+            case CMD_DATA_MISS:
+            case CMD_DATA_UNC:
+                if ( p_vci_ini_rw.cmdack.read() ) {
+                    r_vci_cmd_fsm = CMD_IDLE;
+                }
+                break;
+            case CMD_INS_CLEANUP:
+            case CMD_DATA_CLEANUP:
+                if ( p_vci_ini_c.cmdack.read() ) {
+                    r_vci_cmd_fsm = CMD_IDLE;
+                }
+                break;
+
+        } // end  switch r_vci_cmd_fsm
+
+        //////////////////////////////////////////////////////////////////////////
+        // The VCI_RSP FSM controls the following ressources:
+        // - r_vci_rsp_fsm:
+        // - r_icache_miss_buf[m_icache_words]
+        // - r_dcache_miss_buf[m_dcache_words]
+        // - r_icache_miss_req reset
+        // - r_icache_unc_req reset
+        // - r_dcache_miss_req reset
+        // - r_icache_cleanup_req reset
+        // - r_dcache_cleanup_req reset
+        // - r_vci_rsp_data_error set
+        // - r_vci_rsp_ins_error set
+        // - r_vci_rsp_cpt
+        // In order to have only one active VCI transaction, this VCI_RSP_FSM 
+        // is synchronized with the VCI_CMD FSM, and both FSMs exit the
+        // IDLE state simultaneously.
+        // 
+        // VCI formats:
+        // This component accepts single word or multi-word response packets for
+        // write response packets. 
+        //
+        // Error handling:
+        // This FSM analyzes the VCI error code and signals directly the
+        // Write Bus Error. 
+        // In case of Read Data Error, the VCI_RSP FSM sets the r_vci_rsp_data_error 
+        // flip_flop and the error is signaled by the DCACHE FSM.  
+        // In case of Instruction Error, the VCI_RSP FSM sets the r_vci_rsp_ins_error 
+        // flip_flop and the error is signaled by the DCACHE FSM.  
+        // In case of Cleanup Error, the simulation stops with an error message...
+        //////////////////////////////////////////////////////////////////////////
+
+        switch (r_vci_rsp_fsm) {
+
+            case RSP_IDLE:
+                if(p_vci_ini_rw.rspval.read()||
+                        p_vci_ini_c.rspval.read())
+                {
+                    std::cout << "CC_XCache " << m_srcid_rw << " Unexpected response" << std::endl;
+                }
+                assert( ! p_vci_ini_rw.rspval.read() && ! p_vci_ini_c.rspval.read() && "Unexpected response" );
+                if (r_vci_cmd_fsm != CMD_IDLE) break;
+
+                r_vci_rsp_cpt = 0;
+                if      ( r_icache_cleanup_req )    r_vci_rsp_fsm = RSP_INS_CLEANUP;
+                else if ( r_dcache_cleanup_req )    r_vci_rsp_fsm = RSP_DATA_CLEANUP;
+                else if ( r_icache_miss_req )       r_vci_rsp_fsm = RSP_INS_MISS;
+                else if ( r_icache_unc_req )        r_vci_rsp_fsm = RSP_INS_UNC;
+                else if ( r_dcache_write_req )      r_vci_rsp_fsm = RSP_DATA_WRITE;
+                else if ( r_dcache_miss_req )       r_vci_rsp_fsm = RSP_DATA_MISS;
+                else if ( r_dcache_unc_req )        r_vci_rsp_fsm = RSP_DATA_UNC;
+                break;
+
+            case RSP_INS_MISS:
+                m_cost_imiss_transaction++;
+                if ( ! p_vci_ini_rw.rspval.read() )
+                    break;
+                assert( (r_vci_rsp_cpt < m_icache_words) &&
+                        "The VCI response packet for instruction miss is too long" );
+                r_vci_rsp_cpt = r_vci_rsp_cpt + 1;
+                r_icache_miss_buf[r_vci_rsp_cpt] = (data_t)p_vci_ini_rw.rdata.read();
+
+                if ( p_vci_ini_rw.reop.read() ) {
+                    assert( (r_vci_rsp_cpt == m_icache_words - 1) &&
+                            "The VCI response packet for instruction miss is too short");
+                    r_icache_miss_req = false;
+                    r_vci_rsp_fsm = RSP_IDLE;
+                }
+                if ( (p_vci_ini_rw.rerror.read()&0x1) != vci_param::ERR_NORMAL ) r_vci_rsp_ins_error = true;
+                break;
+
+            case RSP_INS_UNC:
+                m_cost_imiss_transaction++;
+                if ( ! p_vci_ini_rw.rspval.read() )
+                    break;
+                assert(p_vci_ini_rw.reop.read() &&
+                        "illegal VCI response packet for uncached instruction");
+                r_icache_miss_buf[0] = (data_t)p_vci_ini_rw.rdata.read();
+                r_vci_rsp_fsm = RSP_IDLE;
+                r_icache_unc_req = false;
+                if ( (p_vci_ini_rw.rerror.read()&0x1) != vci_param::ERR_NORMAL ) r_vci_rsp_ins_error = true;
+                break;
+
+            case RSP_DATA_MISS:
+                m_cost_dmiss_transaction++;
+                if ( ! p_vci_ini_rw.rspval.read() )
+                    break;
+                assert(r_vci_rsp_cpt != m_dcache_words &&
+                        "illegal VCI response packet for data read miss");
+                r_vci_rsp_cpt = r_vci_rsp_cpt + 1;
+                r_dcache_miss_buf[r_vci_rsp_cpt] = (data_t)p_vci_ini_rw.rdata.read();
+                if ( p_vci_ini_rw.reop.read() ) {
+                    assert(r_vci_rsp_cpt == m_dcache_words - 1 &&
+                            "illegal VCI response packet for data read miss");
+                    r_dcache_miss_req = false;
+                    r_vci_rsp_fsm = RSP_IDLE;
+                }
+                if ( (p_vci_ini_rw.rerror.read()&0x1) != vci_param::ERR_NORMAL ) r_vci_rsp_data_error = true;
+                break;
+
+            case RSP_DATA_WRITE:
+                m_cost_write_transaction++;
+                if ( ! p_vci_ini_rw.rspval.read() )
+                    break;
+                if ( p_vci_ini_rw.reop.read() ) {
+                    r_vci_rsp_fsm = RSP_IDLE;
+                    r_dcache_write_req = false;
+                }
+                if ( (p_vci_ini_rw.rerror.read()&0x1) != vci_param::ERR_NORMAL ) m_iss.setWriteBerr();
+                break;
+
+            case RSP_DATA_UNC:
+                m_cost_unc_transaction++;
+                if ( ! p_vci_ini_rw.rspval.read() )
+                    break;
+                assert(p_vci_ini_rw.reop.read() &&
+                        "illegal VCI response packet for data read uncached");
+                r_dcache_miss_buf[0] = (data_t)p_vci_ini_rw.rdata.read();
+                r_vci_rsp_fsm = RSP_IDLE;
+                r_dcache_unc_req = false;
+                if ( (p_vci_ini_rw.rerror.read()&0x1) != vci_param::ERR_NORMAL ) r_vci_rsp_data_error = true;
+                break;
+
+            case RSP_INS_CLEANUP:
+            case RSP_DATA_CLEANUP:
+                if ( ! p_vci_ini_c.rspval.read() )
+                    break;
+                assert( p_vci_ini_c.reop.read() &&
+                        "illegal VCI response packet for icache cleanup");
+                assert( ((p_vci_ini_c.rerror.read()&0x1) == vci_param::ERR_NORMAL) &&
+                        "error in response packet for icache cleanup");
+                if ( r_vci_rsp_fsm == RSP_INS_CLEANUP ) r_icache_cleanup_req = false;
+                else                                    r_dcache_cleanup_req = false;
+                r_vci_rsp_fsm = RSP_IDLE;
+                break;
+
+        } // end switch r_vci_rsp_fsm
+
+    } // end transition()
+
+    //////////////////////////////////////////////////////////////////////////////////
+    tmpl(void)::genMoore()
+        //////////////////////////////////////////////////////////////////////////////////
+    {
+        // VCI initiator response
+
+        p_vci_ini_rw.rspack = true;
+        p_vci_ini_c.rspack = true;
+
+        // VCI initiator command
+
+        addr_40 memc_addr = 0;
+        switch (r_vci_cmd_fsm.read() ) {
+
+            case CMD_IDLE:
+                p_vci_ini_rw.cmdval  = false;
+                p_vci_ini_rw.address = 0;
+                p_vci_ini_rw.wdata   = 0;
+                p_vci_ini_rw.be      = 0;
+                p_vci_ini_rw.plen    = 0;
+                p_vci_ini_rw.cmd     = vci_param::CMD_NOP;
+                p_vci_ini_rw.trdid   = 0;
+                p_vci_ini_rw.pktid   = 0;
+                p_vci_ini_rw.srcid   = 0;
+                p_vci_ini_rw.cons    = false;
+                p_vci_ini_rw.wrap    = false;
+                p_vci_ini_rw.contig  = false;
+                p_vci_ini_rw.clen    = 0;
+                p_vci_ini_rw.cfixed  = false;
+                p_vci_ini_rw.eop     = false;
+
+                p_vci_ini_c.cmdval  = false;
+                p_vci_ini_c.address = 0;
+                p_vci_ini_c.wdata  = 0;
+                p_vci_ini_c.be     = 0;
+                p_vci_ini_c.plen   = 0;
+                p_vci_ini_c.cmd    = vci_param::CMD_NOP;
+                p_vci_ini_c.trdid  = 0;
+                p_vci_ini_c.pktid  = 0;
+                p_vci_ini_c.srcid  = 0;
+                p_vci_ini_c.cons   = false;
+                p_vci_ini_c.wrap   = false;
+                p_vci_ini_c.contig = false;
+                p_vci_ini_c.clen   = 0;
+                p_vci_ini_c.cfixed = false;
+                p_vci_ini_c.eop = false;
+
+                break;
+
+            case CMD_DATA_UNC:
+                p_vci_ini_rw.cmdval = true;
+                p_vci_ini_rw.address = (addr_40) r_dcache_addr_save.read() & ~0x3;
+                switch( r_dcache_type_save ) {
+                    case iss_t::DATA_READ:
+                        p_vci_ini_rw.wdata = 0;
+                        p_vci_ini_rw.be  = r_dcache_be_save.read();
+                        p_vci_ini_rw.cmd = vci_param::CMD_READ;
+                        break;
+                    case iss_t::DATA_LL:
+                        p_vci_ini_rw.wdata = 0;
+                        p_vci_ini_rw.be  = 0xF;
+                        p_vci_ini_rw.cmd = vci_param::CMD_LOCKED_READ;
+                        break;
+                    case iss_t::DATA_SC:
+                        p_vci_ini_rw.wdata = r_dcache_wdata_save.read();
+                        p_vci_ini_rw.be  = 0xF;
+                        p_vci_ini_rw.cmd = vci_param::CMD_STORE_COND;
+                        break;
+                    default:
+                        assert("this should not happen");
+                }
+                p_vci_ini_rw.plen = 4;
+                p_vci_ini_rw.trdid  = 0;   // data cache uncached read
+                p_vci_ini_rw.pktid  = 0;
+                p_vci_ini_rw.srcid  = m_srcid_rw;
+                p_vci_ini_rw.cons   = false;
+                p_vci_ini_rw.wrap   = false;
+                p_vci_ini_rw.contig = true;
+                p_vci_ini_rw.clen   = 0;
+                p_vci_ini_rw.cfixed = false;
+                p_vci_ini_rw.eop    = true;
+
+                p_vci_ini_c.cmdval  = false;
+                p_vci_ini_c.address = 0;
+                p_vci_ini_c.wdata  = 0;
+                p_vci_ini_c.be     = 0;
+                p_vci_ini_c.plen   = 0;
+                p_vci_ini_c.cmd    = vci_param::CMD_NOP;
+                p_vci_ini_c.trdid  = 0;
+                p_vci_ini_c.pktid  = 0;
+                p_vci_ini_c.srcid  = 0;
+                p_vci_ini_c.cons   = false;
+                p_vci_ini_c.wrap   = false;
+                p_vci_ini_c.contig = false;
+                p_vci_ini_c.clen   = 0;
+                p_vci_ini_c.cfixed = false;
+                p_vci_ini_c.eop = false;
+
+                break;
+
+            case CMD_DATA_WRITE:
+                p_vci_ini_rw.cmdval  = true;
+                p_vci_ini_rw.address = r_wbuf.getAddress(r_vci_cmd_cpt)&~0x3;
+                p_vci_ini_rw.wdata   = r_wbuf.getData(r_vci_cmd_cpt);
+                p_vci_ini_rw.be      = r_wbuf.getBe(r_vci_cmd_cpt);
+                p_vci_ini_rw.plen    = (r_vci_cmd_max - r_vci_cmd_min + 1)<<2;
+                p_vci_ini_rw.cmd     = vci_param::CMD_WRITE;
+                p_vci_ini_rw.trdid   = 0;  // data cache write
+                p_vci_ini_rw.pktid   = 0;
+                p_vci_ini_rw.srcid   = m_srcid_rw;
+                p_vci_ini_rw.cons    = false;
+                p_vci_ini_rw.wrap    = false;
+                p_vci_ini_rw.contig  = true;
+                p_vci_ini_rw.clen    = 0;
+                p_vci_ini_rw.cfixed  = false;
+                p_vci_ini_rw.eop     = (r_vci_cmd_cpt == r_vci_cmd_max);
+
+                p_vci_ini_c.cmdval  = false;
+                p_vci_ini_c.address = 0;
+                p_vci_ini_c.wdata  = 0;
+                p_vci_ini_c.be     = 0;
+                p_vci_ini_c.plen   = 0;
+                p_vci_ini_c.cmd    = vci_param::CMD_NOP;
+                p_vci_ini_c.trdid  = 0;
+                p_vci_ini_c.pktid  = 0;
+                p_vci_ini_c.srcid  = 0;
+                p_vci_ini_c.cons   = false;
+                p_vci_ini_c.wrap   = false;
+                p_vci_ini_c.contig = false;
+                p_vci_ini_c.clen   = 0;
+                p_vci_ini_c.cfixed = false;
+                p_vci_ini_c.eop = false;
+
+                break;
+
+            case CMD_DATA_MISS:
+                p_vci_ini_rw.cmdval = true;
+                p_vci_ini_rw.address = r_dcache_addr_save.read() & (addr_40) m_dcache_yzmask;
+                p_vci_ini_rw.be     = 0xF;
+                p_vci_ini_rw.plen   = m_dcache_words << 2;
+                p_vci_ini_rw.cmd    = vci_param::CMD_READ;
+                p_vci_ini_rw.trdid  = 1;   // data cache cached read
+                p_vci_ini_rw.pktid  = 0;
+                p_vci_ini_rw.srcid  = m_srcid_rw;
+                p_vci_ini_rw.cons   = false;
+                p_vci_ini_rw.wrap   = false;
+                p_vci_ini_rw.contig = true;
+                p_vci_ini_rw.clen   = 0;
+                p_vci_ini_rw.cfixed = false;
+                p_vci_ini_rw.eop = true;
+
+                p_vci_ini_c.cmdval  = false;
+                p_vci_ini_c.address = 0;
+                p_vci_ini_c.wdata  = 0;
+                p_vci_ini_c.be     = 0;
+                p_vci_ini_c.plen   = 0;
+                p_vci_ini_c.cmd    = vci_param::CMD_NOP;
+                p_vci_ini_c.trdid  = 0;
+                p_vci_ini_c.pktid  = 0;
+                p_vci_ini_c.srcid  = 0;
+                p_vci_ini_c.cons   = false;
+                p_vci_ini_c.wrap   = false;
+                p_vci_ini_c.contig = false;
+                p_vci_ini_c.clen   = 0;
+                p_vci_ini_c.cfixed = false;
+                p_vci_ini_c.eop = false;
+
+                break;
+
+            case CMD_INS_MISS:
+                p_vci_ini_rw.cmdval = true;
+                p_vci_ini_rw.address = r_icache_addr_save.read() & (addr_40) m_icache_yzmask;
+                p_vci_ini_rw.be     = 0xF;
+                p_vci_ini_rw.plen   = m_icache_words << 2;
+                p_vci_ini_rw.cmd    = vci_param::CMD_READ;
+                p_vci_ini_rw.trdid  = 3;   // ins cache cached read
+                p_vci_ini_rw.pktid  = 0;
+                p_vci_ini_rw.srcid  = m_srcid_rw;
+                p_vci_ini_rw.cons   = false;
+                p_vci_ini_rw.wrap   = false;
+                p_vci_ini_rw.contig = true;
+                p_vci_ini_rw.clen   = 0;
+                p_vci_ini_rw.cfixed = false;
+                p_vci_ini_rw.eop = true;
+
+                p_vci_ini_c.cmdval  = false;
+                p_vci_ini_c.address = 0;
+                p_vci_ini_c.wdata  = 0;
+                p_vci_ini_c.be     = 0;
+                p_vci_ini_c.plen   = 0;
+                p_vci_ini_c.cmd    = vci_param::CMD_NOP;
+                p_vci_ini_c.trdid  = 0;
+                p_vci_ini_c.pktid  = 0;
+                p_vci_ini_c.srcid  = 0;
+                p_vci_ini_c.cons   = false;
+                p_vci_ini_c.wrap   = false;
+                p_vci_ini_c.contig = false;
+                p_vci_ini_c.clen   = 0;
+                p_vci_ini_c.cfixed = false;
+                p_vci_ini_c.eop = false;
+
+                break;
+
+            case CMD_INS_UNC:
+                p_vci_ini_rw.cmdval = true;
+                p_vci_ini_rw.address = r_icache_addr_save.read() & ~0x3;
+                p_vci_ini_rw.be     = 0xF;
+                p_vci_ini_rw.plen   = 4;
+                p_vci_ini_rw.cmd    = vci_param::CMD_READ;
+                p_vci_ini_rw.trdid  = 2;   // ins cache uncached read
+                p_vci_ini_rw.pktid  = 0;
+                p_vci_ini_rw.srcid  = m_srcid_rw;
+                p_vci_ini_rw.cons   = false;
+                p_vci_ini_rw.wrap   = false;
+                p_vci_ini_rw.contig = true;
+                p_vci_ini_rw.clen   = 0;
+                p_vci_ini_rw.cfixed = false;
+                p_vci_ini_rw.eop = true;
+
+                p_vci_ini_c.cmdval  = false;
+                p_vci_ini_c.address = 0;
+                p_vci_ini_c.wdata  = 0;
+                p_vci_ini_c.be     = 0;
+                p_vci_ini_c.plen   = 0;
+                p_vci_ini_c.cmd    = vci_param::CMD_NOP;
+                p_vci_ini_c.trdid  = 0;
+                p_vci_ini_c.pktid  = 0;
+                p_vci_ini_c.srcid  = 0;
+                p_vci_ini_c.cons   = false;
+                p_vci_ini_c.wrap   = false;
+                p_vci_ini_c.contig = false;
+                p_vci_ini_c.clen   = 0;
+                p_vci_ini_c.cfixed = false;
+                p_vci_ini_c.eop = false;
+
+
+                break;
+
+            case CMD_INS_CLEANUP:
+            {
+                p_vci_ini_rw.cmdval = false;
+                p_vci_ini_rw.address = 0;
+                p_vci_ini_rw.wdata  = 0;
+                p_vci_ini_rw.be     = 0;
+                p_vci_ini_rw.plen   = 0;
+                p_vci_ini_rw.cmd    = vci_param::CMD_NOP;
+                p_vci_ini_rw.trdid  = 0;
+                p_vci_ini_rw.pktid  = 0;
+                p_vci_ini_rw.srcid  = 0;
+                p_vci_ini_rw.cons   = false;
+                p_vci_ini_rw.wrap   = false;
+                p_vci_ini_rw.contig = false;
+                p_vci_ini_rw.clen   = 0;
+                p_vci_ini_rw.cfixed = false;
+                p_vci_ini_rw.eop    = false;
+
+                memc_addr = r_icache_cleanup_line.read() * (m_icache_words<<2);
+                memc_addr.range(vci_param::N-1 - m_x_width - m_y_width, vci_param::N - vci_param::S) 
+                  = m_memc_id;
+
+                memc_addr &= m_srcid_mask;
+
+                p_vci_ini_c.cmdval  = true;
+                p_vci_ini_c.address = memc_addr; 
+                p_vci_ini_c.wdata   = r_icache_cleanup_line.read().range(31, 0);
+                p_vci_ini_c.be      = r_icache_cleanup_line.read().range(33, 32);
+                p_vci_ini_c.plen    = 4;
+                p_vci_ini_c.cmd     = vci_param::CMD_WRITE;
+                p_vci_ini_c.trdid   = 1; // cleanup instruction
+                p_vci_ini_c.pktid   = 0;
+                p_vci_ini_c.srcid   = m_srcid_c;
+                p_vci_ini_c.cons    = false;
+                p_vci_ini_c.wrap    = false;
+                p_vci_ini_c.contig  = false;
+                p_vci_ini_c.clen    = 0;
+                p_vci_ini_c.cfixed  = false;
+                p_vci_ini_c.eop     = true;
+
+#ifdef DEBUG_CLEANUP
+                std::cout << "Initiating Instruction Cleanup Transaction..." << std::endl;
+                std::cout << "MemoryCache Address: " << std::hex << memc_addr << std::endl;
+                std::cout << "Cache Line Address to cleanup: " << std::hex << r_icache_cleanup_line.read()
+                          << std::endl;
+#endif
+            }
+                break;
+
+            case CMD_DATA_CLEANUP:
+            {
+                p_vci_ini_rw.cmdval = false;
+                p_vci_ini_rw.address = 0;
+                p_vci_ini_rw.wdata  = 0;
+                p_vci_ini_rw.be     = 0;
+                p_vci_ini_rw.plen   = 0;
+                p_vci_ini_rw.cmd    = vci_param::CMD_NOP;
+                p_vci_ini_rw.trdid  = 0;
+                p_vci_ini_rw.pktid  = 0;
+                p_vci_ini_rw.srcid  = 0;
+                p_vci_ini_rw.cons   = false;
+                p_vci_ini_rw.wrap   = false;
+                p_vci_ini_rw.contig = false;
+                p_vci_ini_rw.clen   = 0;
+                p_vci_ini_rw.cfixed = false;
+                p_vci_ini_rw.eop    = false;
+
+                memc_addr = r_dcache_cleanup_line.read() * (m_dcache_words<<2);
+                memc_addr.range(vci_param::N-1 - m_x_width - m_y_width, vci_param::N - vci_param::S) 
+                  = m_memc_id;
+
+                memc_addr &= m_srcid_mask;
+
+                p_vci_ini_c.cmdval  = true;
+                p_vci_ini_c.address = memc_addr; 
+                p_vci_ini_c.wdata   = r_dcache_cleanup_line.read().range(31, 0);
+                p_vci_ini_c.be      = r_dcache_cleanup_line.read().range(33, 32);
+                p_vci_ini_c.plen    = 4;
+                p_vci_ini_c.cmd     = vci_param::CMD_WRITE;
+                p_vci_ini_c.trdid   = 0; // cleanup data
+                p_vci_ini_c.pktid   = 0;
+                p_vci_ini_c.srcid   = m_srcid_c;
+                p_vci_ini_c.cons    = false;
+                p_vci_ini_c.wrap    = false;
+                p_vci_ini_c.contig  = false;
+                p_vci_ini_c.clen    = 0;
+                p_vci_ini_c.cfixed  = false;
+                p_vci_ini_c.eop     = true;
+
+#ifdef DEBUG_CLEANUP
+                std::cout << "Initiating Data Cleanup Transaction..." << std::endl;
+                std::cout << "MemoryCache Address: " << std::hex << memc_addr << std::endl; 
+                std::cout << "Cache Line Address to cleanup: " << std::hex << r_dcache_cleanup_line.read()
+                          << std::endl;
+#endif
+		    }
+                break;
+
+        } // end switch r_vci_cmd_fsm
+
+        // VCI_TGT
+
+        switch ( r_vci_tgt_fsm.read() ) {
+
+            case TGT_IDLE:
+            case TGT_UPDT_WORD:
+            case TGT_UPDT_DATA:
+                p_vci_tgt.cmdack  = true;
+                p_vci_tgt.rspval  = false;
+                break;
+
+            case TGT_RSP_BROADCAST:
+                p_vci_tgt.cmdack  = false;
+                p_vci_tgt.rspval  = !r_tgt_icache_req.read() && !r_tgt_dcache_req.read() && ( r_tgt_icache_rsp | r_tgt_dcache_rsp );
+                p_vci_tgt.rsrcid  = r_tgt_srcid.read();
+                p_vci_tgt.rpktid  = r_tgt_pktid.read();
+                p_vci_tgt.rtrdid  = r_tgt_trdid.read();
+                p_vci_tgt.rdata   = 0;
+                p_vci_tgt.rerror  = 0x2 & ( (1 << vci_param::E) - 1); // Write OK
+                p_vci_tgt.reop    = true;
+                break;
+
+            case TGT_RSP_ICACHE:
+                p_vci_tgt.cmdack  = false;
+                p_vci_tgt.rspval  = !r_tgt_icache_req.read() && r_tgt_icache_rsp.read();
+                p_vci_tgt.rsrcid  = r_tgt_srcid.read();
+                p_vci_tgt.rpktid  = r_tgt_pktid.read();
+                p_vci_tgt.rtrdid  = r_tgt_trdid.read();
+                p_vci_tgt.rdata   = 0;
+                p_vci_tgt.rerror  = 0x2 & ( (1 << vci_param::E) - 1); // Write OK
+                p_vci_tgt.reop    = true;
+                break;
+
+            case TGT_RSP_DCACHE:
+                p_vci_tgt.cmdack  = false;
+                p_vci_tgt.rspval  = !r_tgt_dcache_req.read() && r_tgt_dcache_rsp.read();
+                p_vci_tgt.rsrcid  = r_tgt_srcid.read();
+                p_vci_tgt.rpktid  = r_tgt_pktid.read();
+                p_vci_tgt.rtrdid  = r_tgt_trdid.read();
+                p_vci_tgt.rdata   = 0;
+                p_vci_tgt.rerror  = 0x2 & ( (1 << vci_param::E) - 1); // Write OK
+                p_vci_tgt.reop    = true;
+                break;
+
+            case TGT_REQ_BROADCAST:
+            case TGT_REQ_ICACHE:
+            case TGT_REQ_DCACHE:
+                p_vci_tgt.cmdack  = false;
+                p_vci_tgt.rspval  = false;
+                break;
+
+        } // end switch TGT_FSM
+    } // end genMoore()
+
+}} // end namespace
+
+// Local Variables:
+// tab-width: 4
+// c-basic-offset: 4
+// c-file-offsets:((innamespace . 0)(inline-open . 0))
+// indent-tabs-mode: nil
+// End:
+
+// vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4
+
+
+
+
Index: branches/v4/modules/vci_cc_xcache_wrapper_v4/caba/metadata/vci_cc_xcache_wrapper_v4.sd
===================================================================
--- branches/v4/modules/vci_cc_xcache_wrapper_v4/caba/metadata/vci_cc_xcache_wrapper_v4.sd	(revision 371)
+++ branches/v4/modules/vci_cc_xcache_wrapper_v4/caba/metadata/vci_cc_xcache_wrapper_v4.sd	(revision 371)
@@ -0,0 +1,63 @@
+
+# -*- python -*-
+
+__id__ = "$Id$"
+__version__ = "$Revision$"
+
+Module('caba:vci_cc_xcache_wrapper_v4',
+	classname = 'soclib::caba::VciCcXCacheWrapperV4',
+	tmpl_parameters = [
+		parameter.Module('vci_param', default = 'caba:vci_param'),
+		parameter.Module('iss_t'),
+		],
+	header_files = [
+		'../source/include/vci_cc_xcache_wrapper_v4.h',
+		],
+	implementation_files = [
+		'../source/src/vci_cc_xcache_wrapper_v4.cpp',
+		],
+	uses = [
+		Uses('caba:base_module'),
+		Uses('common:mapping_table'),
+		Uses('common:iss2'),
+		Uses('caba:multi_write_buffer'),
+		Uses('caba:generic_fifo'),
+                Uses('caba:generic_cam'),
+		Uses('caba:generic_cache', addr_t = 'uint32_t'),
+		],
+	ports = [
+		Port('caba:vci_initiator', 'p_vci_ini_d'),
+		Port('caba:vci_initiator', 'p_vci_ini_c'),
+		Port('caba:vci_target', 'p_vci_tgt_c'),
+		Port('caba:bit_in', 'p_irq', parameter.Constant('n_irq')),
+		Port('caba:bit_in', 'p_resetn', auto = 'resetn'),
+		Port('caba:clock_in', 'p_clk', auto = 'clock'),
+		],
+	instance_parameters = [
+		parameter.Int('proc_id'),
+		parameter.Module('mtd', 'common:mapping_table'),
+		parameter.Module('mtc', 'common:mapping_table'),
+		parameter.IntTab('initiator_index_d'),
+		parameter.IntTab('initiator_index_c'),
+		parameter.IntTab('target_index_c'),
+		parameter.Int('icache_ways'),
+		parameter.Int('icache_sets'),
+		parameter.Int('icache_words'),
+		parameter.Int('dcache_ways'),
+		parameter.Int('dcache_sets'),
+		parameter.Int('dcache_words'),
+		parameter.Int('wbuf_nwords'),
+		parameter.Int('wbuf_nlines'),
+		parameter.Int('max_frozen_cycles'),
+		],
+	extensions = [
+		'dsx:get_ident='
+		'initiator_index_d:p_vci_ini_d:mtd,'
+		'initiator_index_c:p_vci_ini_c:mtc'
+		'target_index_c:p_vci_tgt_c:mtc',
+		'dsx:cpu=wrapper:iss_t',
+		'dsx:addressable=target_index_c',
+		'dsx:on_segment=mtc:add_index:initiator_index_d',
+		'dsx:mapping_type=processor:proc_id',
+		],
+)
Index: branches/v4/modules/vci_cc_xcache_wrapper_v4/caba/source/include/vci_cc_xcache_wrapper_v4.h
===================================================================
--- branches/v4/modules/vci_cc_xcache_wrapper_v4/caba/source/include/vci_cc_xcache_wrapper_v4.h	(revision 371)
+++ branches/v4/modules/vci_cc_xcache_wrapper_v4/caba/source/include/vci_cc_xcache_wrapper_v4.h	(revision 371)
@@ -0,0 +1,391 @@
+/* -*- c++ -*-
+ * File : vci_cc_xcache_wrapper_v4.h
+ * Copyright (c) UPMC, Lip6, SoC
+ * Authors : Alain GREINER
+ * Date : 27/11/2011
+ *
+ * SOCLIB_LGPL_HEADER_BEGIN
+ * 
+ * This file is part of SoCLib, GNU LGPLv2.1.
+ * 
+ * SoCLib is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU Lesser General Public License as published
+ * by the Free Software Foundation; version 2.1 of the License.
+ * 
+ * SoCLib is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * Lesser General Public License for more details.
+ * 
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with SoCLib; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301 USA
+ * 
+ * SOCLIB_LGPL_HEADER_END
+ */
+ 
+#ifndef SOCLIB_CABA_VCI_CC_XCACHE_WRAPPER_V4_H
+#define SOCLIB_CABA_VCI_CC_XCACHE_WRAPPER_V4_H
+
+#include <inttypes.h>
+#include <fstream>
+#include <systemc>
+#include <queue>
+#include "caba_base_module.h"
+#include "multi_write_buffer.h"
+#include "generic_cache.h"
+#include "generic_fifo.h"
+#include "generic_cam.h"
+#include "vci_initiator.h"
+#include "vci_target.h"
+#include "mapping_table.h"
+#include "static_assert.h"
+#include "iss2.h"
+
+namespace soclib {
+namespace caba {
+
+using namespace sc_core;
+
+////////////////////////////////////////////
+template<typename vci_param, typename iss_t>
+class VciCcXCacheWrapperV4
+///////////////////////////////////////////
+    : public soclib::caba::BaseModule
+{
+    typedef uint32_t    			            data_t;
+    typedef uint32_t    			            tag_t;
+    typedef uint32_t    			            be_t;
+    typedef typename vci_param::fast_addr_t 	vci_addr_t;
+    
+    enum dcache_fsm_state_e 
+    {
+        DCACHE_IDLE,
+        DCACHE_WRITE_UPDT,
+        DCACHE_MISS_VICTIM,
+        DCACHE_MISS_WAIT,
+        DCACHE_MISS_UPDT,
+        DCACHE_UNC_WAIT,
+        DCACHE_INVAL,
+        DCACHE_INVAL_GO,
+        DCACHE_SYNC,
+        DCACHE_ERROR,
+        DCACHE_CC_CHECK,
+        DCACHE_CC_INVAL,
+        DCACHE_CC_UPDT,
+    };
+
+    enum icache_fsm_state_e 
+    {
+        ICACHE_IDLE,
+        ICACHE_MISS_VICTIM,
+        ICACHE_MISS_WAIT,
+        ICACHE_MISS_UPDT,
+        ICACHE_UNC_WAIT,
+        ICACHE_ERROR,
+        ICACHE_CC_CHECK,
+        ICACHE_CC_INVAL,
+        ICACHE_CC_UPDT,
+    };
+
+    enum cmd_fsm_state_e 
+    {
+        CMD_IDLE,
+        CMD_INS_MISS,
+        CMD_INS_UNC,
+        CMD_DATA_MISS,
+        CMD_DATA_UNC,
+        CMD_DATA_WRITE,
+        CMD_DATA_SC,
+    };
+
+    enum rsp_fsm_state_e 
+    {
+        RSP_IDLE,
+        RSP_INS_MISS,
+        RSP_INS_UNC,
+        RSP_DATA_MISS,
+        RSP_DATA_UNC,
+        RSP_DATA_WRITE,
+        RSP_DATA_SC,
+    };
+
+    enum tgt_fsm_state_e 
+    {
+        TGT_IDLE,
+        TGT_UPDT_WORD,
+        TGT_UPDT_DATA,
+        TGT_REQ_BROADCAST,
+        TGT_REQ_ICACHE,
+        TGT_REQ_DCACHE,
+        TGT_RSP_BROADCAST,
+        TGT_RSP_ICACHE,
+        TGT_RSP_DCACHE,
+    };
+
+    enum cleanup_cmd_fsm_state_e 
+    {
+        CLEANUP_DATA_IDLE,
+        CLEANUP_INS_IDLE,
+        CLEANUP_DATA_GO,
+        CLEANUP_INS_GO,
+    };
+
+    enum transaction_type_d_e 
+    {
+        // convention with memcache
+        // b0 : 1 if cached
+        // b1 : 1 if instruction
+        // b2 : 1 if sc
+        TYPE_DATA_UNC     = 0x0,
+        TYPE_DATA_MISS    = 0x1,
+        TYPE_INS_UNC      = 0x2,
+        TYPE_INS_MISS     = 0x3,
+    };
+
+public:
+
+    // PORTS
+    sc_in<bool>                             p_clk;
+    sc_in<bool>                             p_resetn;
+    sc_in<bool>                           * p_irq;		// [iss_t::n_irq];
+    soclib::caba::VciInitiator<vci_param>   p_vci_ini_d;
+    soclib::caba::VciInitiator<vci_param>   p_vci_ini_c;
+    soclib::caba::VciTarget<vci_param>      p_vci_tgt_c;
+
+private:
+
+    // STRUCTURAL PARAMETERS
+    const soclib::common::AddressDecodingTable<vci_addr_t, bool>    	m_cacheability_table;
+    const soclib::common::Segment                                   	m_segment;
+
+    const uint32_t       						m_srcid_d;   
+    const uint32_t       						m_srcid_c;   
+    
+    const size_t         						m_dcache_ways;
+    const size_t         						m_icache_ways;
+
+    const size_t         						m_cache_words;
+    const size_t         						m_cache_words_shift;
+    const vci_addr_t     						m_cache_yzmask;
+
+    const uint32_t							    m_max_frozen_cycles;
+
+    iss_t              			    * r_iss; 
+    MultiWriteBuffer<vci_addr_t>	* r_wbuf;
+    GenericCache<vci_addr_t> 		* r_icache;
+    GenericCache<vci_addr_t> 		* r_dcache;
+
+    sc_signal<int>          r_icache_fsm; 
+    sc_signal<int>          r_icache_fsm_save;		// return state for coherence request
+    sc_signal<vci_addr_t>   r_icache_addr_save;		// address requested by proc
+    sc_signal<bool>         r_icache_miss_req;		// set by icache_fsm / reset by cmd_fsm
+    sc_signal<bool>         r_icache_unc_req;		// set by icache_fsm / reset by cmd_fsm
+    sc_signal<bool>         r_icache_cleanup_req;	// a victim line must be evicted   
+    sc_signal<vci_addr_t>   r_icache_cleanup_line;	// address of the selected victim line
+    sc_signal<size_t>       r_icache_cleanup_way;	// way of the selected victim line
+    sc_signal<size_t>       r_icache_cleanup_set;	// set of the selected victim line
+    sc_signal<bool>         r_icache_miss_inval;	// cancellation request for pending miss 
+    sc_signal<size_t>       r_icache_update_word;	// word index for update (intern/extern)
+    sc_signal<data_t>       r_icache_unc_buf;       // Non cacheable read buffer (one word) 
+    sc_signal<bool>	        r_icache_unc_valid;     // Non cacheable read buffer valid
+    sc_signal<size_t>       r_icache_cc_way;        // way index for coherence request
+    sc_signal<size_t>       r_icache_cc_set;        // set index for coherence request
+
+    sc_signal<int>          r_dcache_fsm;
+    sc_signal<int>          r_dcache_fsm_save;		// return state when coherence request
+    sc_signal<vci_addr_t>   r_dcache_addr_save;		// address requested by proc
+    sc_signal<data_t>       r_dcache_wdata_save;	// data written (for dcache update)
+    sc_signal<be_t>         r_dcache_be_save;		// byte enable (for dcache update)
+    sc_signal<be_t>         r_dcache_way_save;		// selected way (in case of hit)
+    sc_signal<be_t>         r_dcache_set_save;		// selected set (in case of hit)
+    sc_signal<be_t>         r_dcache_word_save;		// selected word (in case of hit)
+    sc_signal<bool>         r_dcache_cleanup_req;	// a victim line must be evicted
+    sc_signal<vci_addr_t>   r_dcache_cleanup_line;	// address of the selected victim line
+    sc_signal<size_t>       r_dcache_cleanup_way;	// way of the selected victim line
+    sc_signal<size_t>       r_dcache_cleanup_set;	// set of the selected victim line
+    sc_signal<bool>         r_dcache_miss_req;		// set by dcache_fsm / reset by cmd_fsm
+    sc_signal<bool>         r_dcache_unc_req;		// set by dcache_fsm / reset by cmd_fsm
+    sc_signal<bool>         r_dcache_sc_req;		// set by dcache_fsm / reset by cmd_fsm
+    sc_signal<bool>         r_dcache_miss_inval;	// cancellation of a pending miss     
+    sc_signal<size_t>       r_dcache_update_word;	// word index for update (intern/extern)
+    sc_signal<data_t>       r_dcache_ll_data;		// LL reservation data
+    sc_signal<vci_addr_t>   r_dcache_ll_addr;		// ll reservation address
+    sc_signal<bool>         r_dcache_ll_valid;		// ll reservation valid
+    sc_signal<bool>	        r_dcache_pending_unc_write; // Non cacheable write pending
+    sc_signal<data_t>       r_dcache_unc_buf;       // Non cacheable read buffer (one word)
+    sc_signal<bool>	        r_dcache_unc_valid;     // Non cacheable read buffer valid 
+    sc_signal<size_t>       r_dcache_cc_way;        // way index for coherence request
+    sc_signal<size_t>       r_dcache_cc_set;        // set index for coherence request
+                                                   
+    sc_signal<int>          r_vci_cmd_fsm;
+    sc_signal<size_t>       r_vci_cmd_min;       	// min word index for a write burst
+    sc_signal<size_t>       r_vci_cmd_max;       	// max word index for a write burst
+    sc_signal<size_t>       r_vci_cmd_cpt;       
+    sc_signal<bool>         r_vci_cmd_imiss_prio;	// round-robin flip-flop to access wbuf
+
+    sc_signal<int>          r_vci_rsp_fsm;
+    sc_signal<size_t>       r_vci_rsp_cpt;  
+    sc_signal<bool>         r_vci_rsp_ins_error;	// set by rsp_fsm / reset by icache_fsm
+    sc_signal<bool>         r_vci_rsp_data_error;	// set by rsp_fsm / reset by dcache_fsm
+    GenericFifo<data_t>     r_vci_rsp_fifo_icache;	// response fifo to ICACHE FSM
+    GenericFifo<data_t>     r_vci_rsp_fifo_dcache;	// response FIFO to DCACHE FSM
+
+    sc_signal<int>          r_tgt_fsm;			    // target port on coherence network
+    sc_signal<bool>         r_tgt_icache_rsp;		// VCI response required when true
+    sc_signal<bool>         r_tgt_dcache_rsp;		// VCI response required when true
+    sc_signal<vci_addr_t>   r_tgt_addr;			    // address of the target line
+    sc_signal<size_t>       r_tgt_word_min;		    // index of the first word to be updated
+    sc_signal<size_t>       r_tgt_word_max;		    // index of the last word to be updated
+    sc_signal<size_t>       r_tgt_word_count;		// word counter to fill the tgt_buf
+    sc_signal<bool>         r_tgt_update;		    // update request when true
+    sc_signal<bool>         r_tgt_update_data;  	// update_data request when true
+    sc_signal<size_t>       r_tgt_srcid;
+    sc_signal<size_t>       r_tgt_pktid;
+    sc_signal<size_t>       r_tgt_trdid;
+    sc_signal<bool>         r_tgt_icache_req; 		// coherence request to ICACHE
+    sc_signal<bool>         r_tgt_dcache_req;		// coherence request to DCACHE
+    sc_signal<data_t>     * r_tgt_buf;          	// [m_cache_words]
+    sc_signal<be_t>       * r_tgt_be;           	// [m_cache_words]
+
+    sc_signal<int>          r_cleanup_fsm;	        // send cleanup commands
+    sc_signal<size_t>       r_cleanup_trdid;        // index for trdid
+    GenericCam<vci_addr_t>  r_cleanup_buffer;       // registration buffer for cleanups
+
+    // ISS interface variables (used for communication 
+    // between transition() and print_trace() functions
+    bool					                m_ireq_valid;
+    uint32_t				                m_ireq_addr;
+    soclib::common::Iss2::ExecMode		    m_ireq_mode;
+	
+    bool					                m_irsp_valid;
+    uint32_t				                m_irsp_instruction;
+    bool					                m_irsp_error;
+	
+    bool					                m_dreq_valid;
+    uint32_t				                m_dreq_addr;
+    soclib::common::Iss2::ExecMode		    m_dreq_mode;
+    soclib::common::Iss2::DataOperationType	m_dreq_type;
+    uint32_t					            m_dreq_wdata;
+    uint8_t					                m_dreq_be;
+
+    bool					                m_drsp_valid;
+    uint32_t					            m_drsp_rdata;
+    bool					                m_drsp_error;
+
+    // Activity counters (for power consumption evaluation)
+    uint32_t   m_conso_dcache_data_read;           // DCACHE DATA READ activity
+    uint32_t   m_conso_dcache_data_write;          // DCACHE DATA WRITE activity
+    uint32_t   m_conso_dcache_dir_read;            // DCACHE DIR READ activity
+    uint32_t   m_conso_dcache_dir_write;           // DCACHE DIR WRITE activity
+                                                  
+    uint32_t   m_conso_icache_data_read;           // ICACHE DATA READ activity
+    uint32_t   m_conso_icache_data_write;          // ICACHE DATA WRITE activity
+    uint32_t   m_conso_icache_dir_read;            // ICACHE DIR READ activity
+    uint32_t   m_conso_icache_dir_write;           // ICACHE DIR WRITE activity
+               
+    uint32_t   m_conso_wbuf_read;		           // WBUF READ activity
+    uint32_t   m_conso_wbuf_write;		           // WBUF WRITE activity
+
+    uint32_t   m_cpt_cc_update_icache;             // number of coherence update packets for icache
+    uint32_t   m_cpt_cc_update_dcache;             // number of coherence update packets for dcache
+    uint32_t   m_cpt_cc_inval_icache;              // number of coherence inval packets	for icache
+    uint32_t   m_cpt_cc_inval_dcache;              // number of coherence inval packets for dcache
+    uint32_t   m_cpt_cc_inval_broadcast;           // number of coherence broadcast packets
+               
+    uint32_t   m_cpt_frz_cycles;	               // total number of cpu frozen cycles
+    uint32_t   m_cpt_total_cycles;	               // total number of cycles from reset
+    uint32_t   m_cpt_stop_simulation;	   	       // consecutive frozen cycles counter 
+               
+    uint32_t   m_cpt_ins_cacheable;                // number of cacheable instructions 
+    uint32_t   m_cpt_ins_uncacheable;              // number of non cacheable instructions
+    uint32_t   m_cpt_ins_miss;                     // number of cacheable instruction miss
+               
+    uint32_t   m_cpt_data_read_cacheable;          // number of cacheable data read
+    uint32_t   m_cpt_data_read_miss;               // number of cacheable data read miss
+    uint32_t   m_cpt_data_read_uncacheable;        // number of non cacheable data read 
+    uint32_t   m_cpt_data_write_cacheable;         // number of cacheable write
+    uint32_t   m_cpt_data_write_uncacheable;       // number of non cacheable write
+    uint32_t   m_cpt_data_write_hit;               // number of cacheable write making hit
+    uint32_t   m_cpt_data_ll;			           // number of LL requests
+    uint32_t   m_cpt_data_sc;			           // number of SC requests
+
+    uint32_t   m_cpt_xtn_dcache_inval;		       // dcache line invalidation request
+    uint32_t   m_cpt_xtn_sync;		               // write buffer flush request
+
+    uint32_t   m_cost_write_frz;                   // number of frozen cycles related to write buffer 
+    uint32_t   m_cost_data_miss_frz;               // number of frozen cycles related to data miss
+    uint32_t   m_cost_ins_miss_frz;                // number of frozen cycles related to ins miss
+               
+    uint32_t   m_cpt_imiss_transaction;            // number of VCI inst read miss transactions
+    uint32_t   m_cpt_dmiss_transaction;            // number of VCI data read miss transactions
+    uint32_t   m_cpt_iunc_transaction;             // number of VCI uncacheable inst read transactions
+    uint32_t   m_cpt_dunc_transaction;             // number of VCI uncacheable data read transactions
+    uint32_t   m_cpt_write_transaction;            // number of VCI write transactions
+    uint32_t   m_cpt_sc_transaction;               // number of VCI sc transactions
+               
+    uint32_t   m_cost_imiss_transaction;           // cumulated duration for VCI IMISS transactions
+    uint32_t   m_cost_dmiss_transaction;           // cumulated duration for VCI DMISS transactions
+    uint32_t   m_cost_unc_transaction;             // cumulated duration for VCI UNC transactions
+    uint32_t   m_cost_write_transaction;           // cumulated duration for VCI WRITE transactions
+    uint32_t   m_length_write_transaction;         // cumulated length for VCI WRITE transactions
+
+
+    uint32_t * m_cpt_fsm_dcache;  		   // array of number of cycles per state
+    uint32_t * m_cpt_fsm_icache; 		   // array of number of cycles per state
+    uint32_t * m_cpt_fsm_cmd;			   // array of number of cycles per state
+    uint32_t * m_cpt_fsm_rsp;			   // array of number of cycles per state
+    uint32_t * m_cpt_fsm_tgt;			   // array of number of cycles per state
+    uint32_t * m_cpt_fsm_cleanup;		   // array of number of cycles per state
+
+protected:
+    SC_HAS_PROCESS(VciCcXCacheWrapperV4);
+
+public:
+
+    VciCcXCacheWrapperV4(
+                       sc_module_name 				insname,
+                       int 					proc_id,
+                       const soclib::common::MappingTable 	&mtd,
+                       const soclib::common::MappingTable 	&mtc,
+                       const soclib::common::IntTab 		&initiator_index_d,
+                       const soclib::common::IntTab 		&initiator_index_c,
+                       const soclib::common::IntTab 		&target_index_c,
+                       size_t 					icache_ways,
+                       size_t 					icache_sets,
+                       size_t 					icache_words,
+                       size_t 					dcache_ways,
+                       size_t 					dcache_sets,
+                       size_t 					dcache_words,
+                       size_t 					wbuf_nwords,
+                       size_t 					wbuf_nlines,
+                       uint32_t					max_frozen_cycles = 1000);
+
+    ~VciCcXCacheWrapperV4();
+
+    void print_trace(size_t mode = 0);
+    void print_cpi();
+    void print_stats(bool print_wbuf=true, bool print_fsm=true);
+
+private:
+
+    void transition();
+    void genMoore();
+
+    soclib_static_assert((int)iss_t::SC_ATOMIC     == (int)vci_param::STORE_COND_ATOMIC);
+    soclib_static_assert((int)iss_t::SC_NOT_ATOMIC == (int)vci_param::STORE_COND_NOT_ATOMIC);
+};
+
+}}
+
+#endif /* SOCLIB_CABA_VCI_CC_VCACHE_WRAPPER_V4_H */
+
+// Local Variables:
+// tab-width: 4
+// c-basic-offset: 4
+// c-file-offsets:((innamespace . 0)(inline-open . 0))
+// indent-tabs-mode: nil
+// End:
+
+// vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4
Index: branches/v4/modules/vci_cc_xcache_wrapper_v4/caba/source/src/vci_cc_xcache_wrapper_v4.cpp
===================================================================
--- branches/v4/modules/vci_cc_xcache_wrapper_v4/caba/source/src/vci_cc_xcache_wrapper_v4.cpp	(revision 371)
+++ branches/v4/modules/vci_cc_xcache_wrapper_v4/caba/source/src/vci_cc_xcache_wrapper_v4.cpp	(revision 371)
@@ -0,0 +1,2694 @@
+/* -*- c++ -*-
+ * File         : vci_cc_xcache_wrapper_v4.cpp
+ * Date         : 26/11/2011
+ * Copyright    : UPMC / LIP6
+ * Authors      : Alain Greiner 
+ *
+ * SOCLIB_LGPL_HEADER_BEGIN
+ * 
+ * This file is part of SoCLib, GNU LGPLv2.1.
+ * 
+ * SoCLib is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU Lesser General Public License as published
+ * by the Free Software Foundation; version 2.1 of the License.
+ * 
+ * SoCLib is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * Lesser General Public License for more details.
+ * 
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with SoCLib; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301 USA
+ * 
+ * SOCLIB_LGPL_HEADER_END
+ *
+ * Copyright (c) UPMC, Lip6
+ *         Alain Greiner <alain.greiner@lip6.fr>, 2011
+ *
+ * Maintainers: alain 
+ */
+
+#include "../include/vci_cc_xcache_wrapper_v4.h"
+
+#define DEBUG_GLOBAL		0
+#define DEBUG_DCACHE		0
+#define DEBUG_ICACHE		0
+
+#define DEBUG_START_CYCLE	0
+#define DEBUG_ID		    0
+
+namespace soclib { namespace caba {
+
+    namespace {
+      const char *dcache_fsm_state_str[] = 
+      {
+        "DCACHE_IDLE",
+        "DCACHE_WRITE_UPDT",
+        "DCACHE_MISS_VICTIM",
+        "DCACHE_MISS_WAIT",
+        "DCACHE_MISS_UPDT",
+        "DCACHE_UNC_WAIT",
+        "DCACHE_INVAL",
+        "DCACHE_INVAL_GO",
+        "DCACHE_SYNC",
+        "DCACHE_ERROR",
+        "DCACHE_CC_CHECK",
+        "DCACHE_CC_INVAL",
+        "DCACHE_CC_UPDT",
+      };
+      const char *icache_fsm_state_str[] = 
+      {
+        "ICACHE_IDLE",
+        "ICACHE_MISS_VICTIM",
+        "ICACHE_MISS_WAIT",
+        "ICACHE_MISS_UPDT",
+        "ICACHE_UNC_WAIT",
+        "ICACHE_ERROR",
+        "ICACHE_CC_CHECK",
+        "ICACHE_CC_INVAL",
+        "ICACHE_CC_UPDT",
+      };
+      const char *cmd_fsm_state_str[] = 
+      {
+        "CMD_IDLE",
+        "CMD_INS_MISS",
+        "CMD_INS_UNC",
+        "CMD_DATA_MISS",
+        "CMD_DATA_UNC",
+        "CMD_DATA_WRITE",
+        "CMD_DATA_SC",
+      };
+      const char *rsp_fsm_state_str[] = 
+      {
+        "RSP_IDLE",
+        "RSP_INS_MISS",
+        "RSP_INS_UNC",
+        "RSP_DATA_MISS",
+        "RSP_DATA_UNC",
+        "RSP_DATA_WRITE",
+        "RSP_DATA_SC",
+      };
+      const char *tgt_fsm_state_str[] = 
+      {
+        "TGT_IDLE",
+        "TGT_UPDT_WORD",
+        "TGT_UPDT_DATA",
+        "TGT_REQ_BROADCAST",
+        "TGT_REQ_ICACHE",
+        "TGT_REQ_DCACHE",
+        "TGT_RSP_BROADCAST",
+        "TGT_RSP_ICACHE",
+        "TGT_RSP_DCACHE",
+      };
+
+      const char *cleanup_fsm_state_str[] = 
+      {
+        "CLEANUP_DATA_IDLE",
+        "CLEANUP_DATA_GO",
+        "CLEANUP_INS_IDLE",
+        "CLEANUP_INS_GO",
+      };
+    }
+
+#define tmpl(...) template<typename vci_param, typename iss_t> __VA_ARGS__ VciCcXCacheWrapperV4<vci_param, iss_t>
+
+using soclib::common::uint32_log2;
+
+/////////////////////////////////
+tmpl(/**/)::VciCcXCacheWrapperV4(
+    sc_module_name                      name,
+    int                                 proc_id,
+    const soclib::common::MappingTable  &mtp,
+    const soclib::common::MappingTable  &mtc,
+    const soclib::common::IntTab        &initiator_index_d,
+    const soclib::common::IntTab        &initiator_index_c,
+    const soclib::common::IntTab        &target_index_c,
+    size_t                              icache_ways,
+    size_t                              icache_sets,
+    size_t                              icache_words,
+    size_t                              dcache_ways,
+    size_t                              dcache_sets,
+    size_t                              dcache_words,
+    size_t                              wbuf_nwords,
+    size_t                              wbuf_nlines,
+    uint32_t				            max_frozen_cycles)
+     : 
+     soclib::caba::BaseModule(name),
+
+     p_clk       ("clk"),
+     p_resetn    ("resetn"),
+     p_vci_ini_d ("vci_ini_d"),
+     p_vci_ini_c ("vci_ini_c"),
+     p_vci_tgt_c ("vci_tgt_c"),
+
+     m_cacheability_table(mtp.getCacheabilityTable<vci_addr_t>()),
+     m_segment(mtc.getSegment(target_index_c)),
+     m_srcid_d(mtp.indexForId(initiator_index_d)),
+     m_srcid_c(mtc.indexForId(initiator_index_c)),
+
+     m_dcache_ways(dcache_ways),
+     m_icache_ways(icache_ways),
+
+     m_cache_words(icache_words),
+     m_cache_words_shift(uint32_log2(icache_words)+uint32_log2(sizeof(data_t))),
+     m_cache_yzmask((~0)<<m_cache_words_shift),
+
+     m_max_frozen_cycles(max_frozen_cycles),
+
+     r_icache_fsm("r_icache_fsm"),
+     r_icache_fsm_save("r_icache_fsm_save"),
+     r_icache_addr_save("r_icache_addr_save"),
+     r_icache_miss_req("r_icache_miss_req"),
+     r_icache_unc_req("r_icache_unc_req"),
+     r_icache_cleanup_req("r_icache_cleanup_req"),
+     r_icache_cleanup_line("r_icache_cleanup_line"),
+     r_icache_cleanup_way("r_icache_cleanup_way"),
+     r_icache_cleanup_set("r_icache_cleanup_set"),
+     r_icache_miss_inval("r_icache_miss_inval"),
+     r_icache_update_word("r_icache_update_word"),
+
+     r_dcache_fsm("r_dcache_fsm"),
+     r_dcache_fsm_save("r_dcache_fsm_save"),
+     r_dcache_addr_save("r_dcache_addr_save"),
+     r_dcache_wdata_save("r_dcache_wdata_save"),
+     r_dcache_be_save("r_dcache_be_save"),
+     r_dcache_way_save("r_dcache_way_save"),
+     r_dcache_set_save("r_dcache_set_save"),
+     r_dcache_word_save("r_dcache_word_save"),
+     r_dcache_cleanup_req("r_dcache_cleanup_req"),
+     r_dcache_cleanup_line("r_dcache_cleanup_line"),
+     r_dcache_cleanup_way("r_dcache_cleanup_way"),
+     r_dcache_cleanup_set("r_dcache_cleanup_set"),
+     r_dcache_miss_req("r_dcache_miss_req"),
+     r_dcache_unc_req("r_dcache_unc_req"),
+     r_dcache_sc_req("r_dcache_sc_req"),
+     r_dcache_miss_inval("r_dcache_miss_inval"),
+     r_dcache_update_word("r_dcache_update_word"),
+     r_dcache_ll_data("r_dcache_ll_data"),
+     r_dcache_ll_addr("r_dcache_ll_addr"),
+     r_dcache_ll_valid("r_dcache_ll_valid"),
+
+     r_vci_cmd_fsm("r_vci_cmd_fsm"),
+     r_vci_cmd_min("r_vci_cmd_min"),
+     r_vci_cmd_max("r_vci_cmd_max"),
+     r_vci_cmd_cpt("r_vci_cmd_cpt"),
+     r_vci_cmd_imiss_prio("r_vci_cmd_imiss_prio"),
+
+     r_vci_rsp_fsm("r_vci_rsp_fsm"),
+     r_vci_rsp_cpt("r_vci_rsp_cpt"),
+     r_vci_rsp_ins_error("r_vci_rsp_ins_error"),
+     r_vci_rsp_data_error("r_vci_rsp_data_error"),
+     r_vci_rsp_fifo_icache("r_vci_rsp_fifo_icache" ,2),     // two words depth
+     r_vci_rsp_fifo_dcache("r_vci_rsp_fifo_dcache" ,2),     // two words depth
+
+     r_tgt_fsm("r_tgt_fsm"),
+     r_tgt_icache_rsp("r_tgt_icache_rsp"),
+     r_tgt_dcache_rsp("r_tgt_dcache_rsp"),
+     r_tgt_addr("r_tgt_daddr"),
+     r_tgt_word_min("r_tgt_word_min"),
+     r_tgt_word_max("r_tgt_word_max"),
+     r_tgt_word_count("r_tgt_word_count"),
+     r_tgt_update("r_tgt_update"),
+     r_tgt_update_data("r_tgt_update_data"),
+     r_tgt_srcid("r_tgt_srcid"),
+     r_tgt_pktid("r_tgt_pktid"),
+     r_tgt_trdid("r_tgt_trdid"),
+     r_tgt_icache_req("r_tgt_icache_req"),
+     r_tgt_dcache_req("r_tgt_dcache_req"),
+
+     r_cleanup_fsm("r_cleanup_fsm"),
+     r_cleanup_trdid("r_cleanup_trdid"),
+     r_cleanup_buffer(16)                   // up to 16 simultaneous cleanup transactions
+{
+    assert( ((icache_words*vci_param::B) < (1<<vci_param::K)) and
+             "Need more PLEN bits.");
+
+    assert( (vci_param::T > 2) and ((1<<(vci_param::T-1)) >= (wbuf_nlines)) and
+             "Need more TRDID bits.");
+
+    assert( (icache_words == dcache_words) and
+             "icache_words must be equal at dcache_words.");
+
+    p_irq  = new sc_in<bool> [iss_t::n_irq];
+
+    r_iss     = new iss_t (this->name() , proc_id);
+    r_icache  = new GenericCache<vci_addr_t>("icache", icache_ways, icache_sets, icache_words);
+    r_dcache  = new GenericCache<vci_addr_t>("dcache", dcache_ways, dcache_sets, dcache_words);
+    r_wbuf    = new MultiWriteBuffer<vci_addr_t>("wbuf", wbuf_nwords, wbuf_nlines, dcache_words);
+                
+    r_tgt_buf = new sc_signal<data_t> [m_cache_words];
+    r_tgt_be  = new sc_signal<be_t>   [m_cache_words];
+
+    m_cpt_fsm_dcache  = new uint32_t [32];
+    m_cpt_fsm_icache  = new uint32_t [32];
+    m_cpt_fsm_cmd     = new uint32_t [32];
+    m_cpt_fsm_rsp     = new uint32_t [32];
+    m_cpt_fsm_tgt     = new uint32_t [32];
+    m_cpt_fsm_cleanup = new uint32_t [32];
+
+    SC_METHOD(transition);
+    dont_initialize();
+    sensitive << p_clk.pos();
+
+    SC_METHOD(genMoore);
+    dont_initialize();
+    sensitive << p_clk.neg();
+
+    typename iss_t::CacheInfo cache_info;
+    cache_info.has_mmu          = false;
+    cache_info.icache_line_size = icache_words*sizeof(data_t);
+    cache_info.icache_assoc     = icache_ways;
+    cache_info.icache_n_lines   = icache_sets;
+    cache_info.dcache_line_size = dcache_words*sizeof(data_t);
+    cache_info.dcache_assoc     = dcache_ways;
+    cache_info.dcache_n_lines   = dcache_sets;
+
+    r_iss->setCacheInfo(cache_info);
+    
+} // end constructor
+
+///////////////////////////////////
+tmpl(/**/)::~VciCcXCacheWrapperV4()
+{
+    delete r_icache ;
+    delete r_wbuf   ;
+    delete r_dcache ;
+    delete r_iss;
+    delete [] p_irq;
+    delete [] r_tgt_buf;
+    delete [] r_tgt_be;
+}
+
+////////////////////////
+tmpl(void)::print_cpi()
+{
+    std::cout << "CPU " << m_srcid_d << " : CPI = " 
+              << (float)m_cpt_total_cycles/(m_cpt_total_cycles - m_cpt_frz_cycles) 
+              << std::endl ;
+}
+
+/*
+
+////////////////////////////////////////////////////////
+tmpl(void)::print_stats(bool print_wbuf, bool print_fsm)
+{
+    std::cout << "------------------------------------" << std:: dec << std::endl;
+    std::cout << "CPU " << m_srcid_d << " / Time = " << m_cpt_total_cycles << std::endl;
+
+    float run_cycles = (float)(m_cpt_total_cycles - m_cpt_frz_cycles);
+
+    std::cout << "- CPI                            : " 
+              << (float)m_cpt_total_cycles/run_cycles << std::endl ;
+
+    std::cout << "- CACHABLE INSTRUCTIONS          : " 
+              << m_cpt_ins_cacheable << std::endl ;
+
+    std::cout << "- INSTRUCTION CACHE MISS RATE    : "
+              << (float)m_cpt_ins_miss*100.0/(float)m_cpt_ins_cacheable 
+              << " %" << std::endl ;
+
+    std::cout << "- NON CACHABLE INSTRUCTIONS      : " 
+              << m_cpt_ins_uncacheable << std::endl ;
+
+    std::cout << "- CACHABLE DATA READ             : " 
+              << m_cpt_data_read_cacheable << std::endl;
+
+    std::cout << "- DATA CACHE MISS RATE           : "
+              << (float)m_cpt_data_read_miss*100.0/(float)m_cpt_data_read_cacheable 
+              << " %" << std::endl;
+
+    std::cout << "- CACHABLE DATA WRITE            : " 
+              << m_cpt_data_write_cacheable << std::endl ;
+
+    std::cout << "- CACHED WRITE RATE              : "
+              << (float)m_cpt_data_write_hit*100.0/(float)m_cpt_data_write_cacheable 
+              << " %" << std::endl;
+
+    std::cout << "- NON CACHABLE DATA READ         : " 
+              << m_cpt_data_read_uncacheable << std::endl;
+
+    std::cout << "- NON CACHABLE DATA WRITE        : " 
+              << m_cpt_data_write_uncacheable << std::endl;
+
+    std::cout << "- WRITE RATE                     : " 
+              << (float)m_cpt_data_write_cacheable*100.0/(float)m_cpt_ins_cacheable
+              << " %" << std::endl;
+
+    std::cout << "- READ RATE                      : " 
+              << (float)m_cpt_data_read_cacheable*100.0/(float)m_cpt_ins_cacheable
+              << " %" << std::endl;
+
+    std::cout << "- AVERAGE INSTRUCTION MISS COST  : " 
+              << (float)m_cost_ins_miss_frz/(float)m_cpt_ins_miss << std::endl;
+
+    std::cout << "- AVERAGE DATA MISS COST         : " 
+              << (float)m_cost_data_miss_frz/m_cpt_data_read_miss << std::endl;
+
+    std::cout << "- AVERAGE WRITE COST             : " 
+              << (float)m_cost_write_frz/m_cpt_data_write_cacheable << std::endl;
+
+    std::cout << "- CC_UPDATE_ICACHE               : " 
+              << m_cpt_cc_update_icache  << std::endl;
+
+    std::cout << "- CC_UPDATE_DCACHE               : " 
+              << m_cpt_cc_update_dcache  << std::endl;
+
+    std::cout << "- CC_INVAL_ICACHE                : " 
+              << m_cpt_cc_inval_icache << std::endl;
+
+    std::cout << "- CC_INVAL_ICACHE                : " 
+              << m_cpt_cc_inval_icache << std::endl;
+
+    std::cout << "-CC_BROADCAST                    : " 
+              << m_cpt_cc_inval_broadcast << std::endl;
+
+//  this part is removed because soclib::common::size() not found ...
+
+    if (print_fsm)
+    {
+        std::cout << "- DCACHE FSM" << std::endl;
+        for (uint32_t i=0; i<soclib::common::size(dcache_fsm_state_str ); ++i)
+            std::cout << "  + "  << dcache_fsm_state_str[i] << " : "
+                      << m_cpt_fsm_dcache [i] << std::endl; 
+
+        std::cout << "- ICACHE FSM" << std::endl;
+        for (uint32_t i=0; i<soclib::common::size(icache_fsm_state_str ); ++i)
+            std::cout << "  + "  << icache_fsm_state_str[i] << " : "
+                      << m_cpt_fsm_icache [i] << std::endl; 
+
+        std::cout << "- CMD FSM" << std::endl;
+        for (uint32_t i=0; i<soclib::common::size(cmd_fsm_state_str ); ++i)
+            std::cout << "  + " << cmd_fsm_state_str[i] << " : " 
+                      << m_cpt_fsm_cmd [i] << std::endl;
+
+        std::cout << "- RSP FSM" << std::endl;
+        for (uint32_t i=0; i<soclib::common::size(rsp_fsm_state_str ); ++i)
+            std::cout << "  + " << rsp_fsm_state_str[i] << " : "
+                      << m_cpt_fsm_rsp [i] << std::endl;
+
+        std::cout << "- TGT FSM" << std::endl;
+        for (uint32_t i=0; i<soclib::common::size(tgt_fsm_state_str ); ++i)
+            std::cout << "  + "  << tgt_fsm_state_str[i] << " : " 
+                      << m_cpt_fsm_tgt [i] << std::endl;
+
+        std::cout << "- CLEANUP FSM" << std::endl;
+        for (uint32_t i=0; i<soclib::common::size(cleanup_fsm_state_str ); ++i)
+            std::cout << "  + "  << cleanup_fsm_state_str[i] << " : " 
+                      << m_cpt_fsm_cleanup [i] << std::endl;
+    }
+
+    if (print_wbuf) r_wbuf->printStatistics();
+}
+
+*/
+////////////////////////////////////
+tmpl(void)::print_trace(size_t mode)
+{
+    // b0 : write buffer print trace
+    // b1 : write buffer verbose
+    // b2 : dcache print trace
+    // b3 : icache print trace
+
+    typename iss_t::InstructionRequest  ireq;
+    typename iss_t::InstructionResponse irsp;
+    typename iss_t::DataRequest         dreq;
+    typename iss_t::DataResponse        drsp;
+
+    ireq.valid       = m_ireq_valid;
+    ireq.addr        = m_ireq_addr;
+    ireq.mode        = m_ireq_mode;
+
+    irsp.valid       = m_irsp_valid;
+    irsp.instruction = m_irsp_instruction;
+    irsp.error       = m_irsp_error;
+
+    dreq.valid       = m_dreq_valid;
+    dreq.addr        = m_dreq_addr;
+    dreq.mode        = m_dreq_mode;
+    dreq.type        = m_dreq_type;
+    dreq.wdata       = m_dreq_wdata;
+    dreq.be          = m_dreq_be;
+
+    drsp.valid       = m_drsp_valid;
+    drsp.rdata       = m_drsp_rdata;
+    drsp.error       = m_drsp_error;
+
+    std::cout << std::dec << "Proc " << name() << std::endl;
+
+    std::cout << "  " << ireq << std::endl;
+    std::cout << "  " << irsp << std::endl;
+    std::cout << "  " << dreq << std::endl;
+    std::cout << "  " << drsp << std::endl;
+ 
+    std::cout << "  " << icache_fsm_state_str[r_icache_fsm.read()]
+              << " | " << dcache_fsm_state_str[r_dcache_fsm.read()]
+              << " | " << cmd_fsm_state_str[r_vci_cmd_fsm.read()]
+              << " | " << rsp_fsm_state_str[r_vci_rsp_fsm.read()]
+              << " | " << tgt_fsm_state_str[r_tgt_fsm.read()]
+              << " | " << cleanup_fsm_state_str[r_cleanup_fsm.read()] << std::endl;
+
+    if(mode & 0x1)
+    {
+        std::cout << "  Write Buffer" << std::endl;
+        r_wbuf->printTrace((mode>>1)&1);
+    }
+    if(mode & 0x4)
+    {
+        std::cout << "  Data cache" << std::endl;
+        r_dcache->printTrace();
+    }
+    if(mode & 0x8)
+    {
+        std::cout << "  Instruction cache" << std::endl;
+        r_icache->printTrace();
+    }
+}
+
+//////////////////////////
+tmpl(void)::transition()
+//////////////////////////
+{
+    // Reset
+    if ( not p_resetn.read() ) 
+    {
+        // iss, write buffer & caches
+        r_iss->reset();
+        r_wbuf->reset();
+        r_dcache->reset();
+        r_icache->reset();
+        r_cleanup_buffer.reset();
+
+        // FSM states
+        r_icache_fsm                = ICACHE_IDLE;
+        r_dcache_fsm                = DCACHE_IDLE;
+        r_vci_cmd_fsm               = CMD_IDLE;
+        r_vci_rsp_fsm               = RSP_IDLE;
+        r_tgt_fsm                   = TGT_IDLE;
+        r_cleanup_fsm               = CLEANUP_DATA_IDLE;
+
+        // synchronisation flip-flops between TGT FSM and ICACHE/DCACHE FSMs
+        r_tgt_icache_req            = false;
+        r_tgt_dcache_req            = false;
+
+        // synchronisation flip-flops between ICACHE/DCACHE FSMs and CLEANUP FSM
+        r_icache_cleanup_req        = false;
+        r_dcache_cleanup_req        = false;
+
+        // synchronisation flip-flops between ICACHE FSMs and VCI FSMs
+        r_icache_miss_req           = false;
+        r_icache_unc_req            = false;
+        r_icache_miss_inval         = false;
+        r_vci_rsp_ins_error         = false;
+
+        // synchronisation flip-flops between DCACHE FSMs and VCI FSMs
+        r_dcache_miss_req           = false;
+        r_dcache_unc_req            = false;
+        r_dcache_sc_req             = false;
+        r_dcache_miss_inval         = false;
+        r_vci_rsp_data_error        = false;
+
+        // pending non cacheable write
+        r_dcache_pending_unc_write  = false;
+
+        // linked load reservation flip-flop
+        r_dcache_ll_valid           = false;
+
+        // uncacheable read buffers
+        r_icache_unc_valid          = false;
+        r_dcache_unc_valid          = false;
+
+        // response FIFOs 
+        r_vci_rsp_fifo_icache.init();
+        r_vci_rsp_fifo_dcache.init();
+      
+        // activity counters (consommation)
+        m_conso_dcache_data_read     = 0;
+        m_conso_dcache_data_write    = 0;
+        m_conso_dcache_dir_read      = 0;
+        m_conso_dcache_dir_write     = 0;
+
+        m_conso_icache_data_read     = 0;
+        m_conso_icache_data_write    = 0;
+        m_conso_icache_dir_read      = 0;
+        m_conso_icache_dir_write     = 0;
+
+        m_conso_wbuf_read            = 0;
+        m_conso_wbuf_write           = 0;
+
+        // coherence request counters
+        m_cpt_cc_update_icache       = 0;
+        m_cpt_cc_update_dcache       = 0;
+        m_cpt_cc_inval_icache        = 0;
+        m_cpt_cc_inval_dcache        = 0;
+        m_cpt_cc_inval_broadcast     = 0;
+
+        // CPI computation
+        m_cpt_frz_cycles             = 0;
+        m_cpt_total_cycles           = 0;
+        m_cpt_stop_simulation        = 0;
+
+        // number of executed instructions
+        m_cpt_ins_cacheable          = 0;
+        m_cpt_ins_uncacheable        = 0;
+        m_cpt_ins_miss               = 0;
+
+        // number of data requests
+        m_cpt_data_read_cacheable    = 0;
+        m_cpt_data_read_miss         = 0;
+        m_cpt_data_read_uncacheable  = 0;
+        m_cpt_data_write_cacheable   = 0;
+        m_cpt_data_write_uncacheable = 0;
+        m_cpt_data_write_hit         = 0;
+        m_cpt_data_ll                = 0;
+        m_cpt_data_sc                = 0;
+
+        // number of external register requests
+        m_cpt_xtn_dcache_inval       = 0;
+        m_cpt_xtn_sync               = 0;
+
+        // cumulated cost (frozen cycles) for write and miss
+        m_cost_write_frz             = 0;
+        m_cost_data_miss_frz         = 0;
+        m_cost_ins_miss_frz          = 0;
+
+        m_cpt_imiss_transaction      = 0;
+        m_cpt_dmiss_transaction      = 0;
+        m_cpt_iunc_transaction       = 0;
+        m_cpt_dunc_transaction       = 0;
+        m_cpt_write_transaction      = 0;
+        m_cpt_sc_transaction         = 0;
+
+        m_cost_imiss_transaction    = 0;
+        m_cost_dmiss_transaction    = 0;
+        m_cost_unc_transaction      = 0;
+        m_cost_write_transaction    = 0;
+        m_length_write_transaction  = 0;
+
+        for (uint32_t i=0; i<32 ; ++i) 
+            m_cpt_fsm_icache  [i]   = 0;
+        for (uint32_t i=0; i<32 ; ++i) 
+            m_cpt_fsm_dcache  [i]   = 0;
+        for (uint32_t i=0; i<32 ; ++i) 
+            m_cpt_fsm_cmd     [i]   = 0;
+        for (uint32_t i=0; i<32 ; ++i) 
+            m_cpt_fsm_rsp     [i]   = 0;
+        for (uint32_t i=0; i<32 ; ++i) 
+            m_cpt_fsm_tgt     [i]   = 0;
+        for (uint32_t i=0; i<32 ; ++i) 
+            m_cpt_fsm_cleanup [i]   = 0;
+
+        return; 
+    }
+
+    // Response FIFOs default values
+    bool     vci_rsp_fifo_icache_get       = false;
+    bool     vci_rsp_fifo_icache_put       = false;
+    data_t   vci_rsp_fifo_icache_data      = 0;
+
+    bool     vci_rsp_fifo_dcache_get       = false;
+    bool     vci_rsp_fifo_dcache_put       = false;
+    data_t   vci_rsp_fifo_dcache_data      = 0;
+
+    // FSMs activity
+    m_cpt_fsm_dcache  [r_dcache_fsm.read() ] ++;
+    m_cpt_fsm_icache  [r_icache_fsm.read() ] ++;
+    m_cpt_fsm_cmd     [r_vci_cmd_fsm.read()] ++;
+    m_cpt_fsm_rsp     [r_vci_rsp_fsm.read()] ++;
+    m_cpt_fsm_tgt     [r_tgt_fsm.read()    ] ++;
+    m_cpt_fsm_cleanup [r_cleanup_fsm.read()] ++;
+
+    m_cpt_total_cycles++;
+
+    //////////////////////////////////////////////////////////////////////////////
+    // The TGT_FSM receives the coherence requests.
+    // It controls the following ressources:
+    // - r_tgt_fsm
+    // - r_tgt_buf[nwords]
+    // - r_tgt_be[nwords]
+    // - r_tgt_update
+    // - r_tgt_word_min
+    // - r_tgt_word_max
+    // - r_tgt_word_count
+    // - r_tgt_addr
+    // - r_tgt_srcid
+    // - r_tgt_trdid
+    // - r_tgt_pktid
+    // - r_tgt_icache_req (set)
+    // - r_tgt_dcache_req (set)
+    //
+    // All VCI commands must be CMD_WRITE.
+    // - If the 2 LSB bits of the VCI address are 11, it is a broadcast request.
+    //   It is a multicast request otherwise.
+    // - For multicast requests, the ADDRESS[2] bit distinguishes DATA/INS
+    //   (0 for data / 1 for instruction), and the ADDRESS[3] bit distinguishes
+    //   INVAL/UPDATE (0 for invalidate / 1 for UPDATE).
+    //
+    // For all types of coherence resqests, the line index (i.e. the Z & Y fields) 
+    // is coded on 34 bits, and is contained in the WDATA and BE fields 
+    // of the first VCI flit.
+    // -  for a multicast invalidate or for a broadcast invalidate request
+    //    the VCI packet length is 1 word. 
+    // -  for an update request the VCI packet length is (n+2) words.
+    //    The WDATA field of the second VCI word contains the word index.
+    //    The WDATA field of the n following words contains the values.
+    // -  for all transaction types, the VCI response is one single word.
+    // In case of errors in the VCI command packet, the simulation
+    // is stopped with an error message.
+    //
+    // This FSM is NOT pipelined : It consumes a new request on the VCI port
+    // only when the previous request is completed.
+    //
+    // The VCI_TGT FSM stores the external request arguments in the
+    // IDLE, UPDT_WORD & UPDT_DATA states. It sets the r_tgt_icache_req 
+    // and/or the r_tgt_dcache_req flip-flops to signal the coherence request 
+    // to the ICACHE & DCACHE FSMs in the REQ_ICACHE, REQ_DCACHE & REQ_BROADCAST
+    // states. It waits the completion of the coherence request  by polling the
+    // r_tgt_*cache_req flip-flops in the RSP_ICACHE, RSP_DCACHE & RSP_BROADCAST
+    // states. These flip-flops are reset by the ICACHE_FSM and/or DCACHE_FSM. 
+    // These two FSMs signal if a VCI answer must be send by setting
+    // the r_tgt_icache_rsp and/or the r_tgt_dcache_rsp flip_flops.
+    ///////////////////////////////////////////////////////////////////////////////
+
+    switch( r_tgt_fsm.read() ) 
+    {
+        //////////////
+        case TGT_IDLE:
+        {
+            vci_addr_t tgt_addr; 
+            
+            if ( p_vci_tgt_c.cmdval.read() ) 
+            {
+                vci_addr_t address = p_vci_tgt_c.address.read();
+
+                if ( p_vci_tgt_c.cmd.read() != vci_param::CMD_WRITE) 
+                {
+                    std::cout << "error in component VCI_CC_XCACHE_WRAPPER " 
+                              << name() << std::endl;
+                    std::cout << "coherence request is not a write" 
+                              << std::endl;
+                    exit(0);
+                }
+
+                // address checking for multi-update or multi-invalidate 
+                if ( ((address&0x3) != 0x3) and (not m_segment.contains(address)) ) 
+                {
+                    std::cout << "error in component VCI_CC_XCACHE_WRAPPER "
+                              << name() << std::endl;
+                    std::cout << "out of segment coherence request"
+                              << std::endl;
+                    exit(0);
+                }
+            
+                // address of the target cache line = nline * m_cache_words * 4
+                tgt_addr  = (vci_addr_t)(((((uint64_t)p_vci_tgt_c.be.read() & 0x3) << 32) | 
+                                  (uint64_t)p_vci_tgt_c.wdata.read() ) << m_cache_words_shift);
+
+                r_tgt_srcid    	= p_vci_tgt_c.srcid.read();
+                r_tgt_trdid    	= p_vci_tgt_c.trdid.read();
+                r_tgt_pktid    	= p_vci_tgt_c.pktid.read();
+                r_tgt_addr 	= tgt_addr;             // target line (for *CACHE FSMs)
+                    
+                if ( (address&0x3) == 0x3 )   // broadcast invalidate 
+                {
+                    if ( not p_vci_tgt_c.eop.read() ) 
+                    {
+                        std::cout << "error in component VCI_CC_XCACHE_WRAPPER " 
+                                  << name() << std::endl;
+                        std::cout << "the BROADCAST INVALIDATE command length must be one word"
+                                  << std::endl;
+                        exit(0);
+                    }
+                    r_tgt_update = false; 
+                    r_tgt_fsm = TGT_REQ_BROADCAST;
+
+                    m_cpt_cc_inval_broadcast++ ;
+                }
+                else                    // multi-update or multi-invalidate
+                { 
+                    uint32_t cell = address - m_segment.baseAddress(); 
+                    if (cell == 0)                           // invalidate data
+                    {
+                        if ( not p_vci_tgt_c.eop.read() ) 
+                        {
+                            std::cout << "error in component VCI_CC_XCACHE_WRAPPER " 
+                                      << name() << std::endl;
+                            std::cout << "the MULTI-INVALIDATE command length must be one word"
+                                      << std::endl;
+                            exit(0);
+                        }
+                        r_tgt_update 		= false; 
+                        r_tgt_fsm 		= TGT_REQ_DCACHE;
+
+                        m_cpt_cc_inval_dcache++ ;
+                    } 
+                    else if (cell == 4)                     // invalidate instruction
+                    {                         
+                        if ( not p_vci_tgt_c.eop.read() ) 
+                        {
+                            std::cout << "error in component VCI_CC_VCACHE_WRAPPER " 
+                                      << name() << std::endl;
+                            std::cout << "the MULTI-INVALIDATE command length must be one word"
+                                      << std::endl;
+                            exit(0);
+                        }
+                        r_tgt_update 		= false; 
+                        r_tgt_fsm 		= TGT_REQ_ICACHE;
+
+                        m_cpt_cc_inval_icache++ ;
+                    } 
+                    else if (cell == 8)    			// update data 
+                    {                                
+                        if ( p_vci_tgt_c.eop.read() ) 
+                        {
+                            std::cout << "error in component VCI_CC_VCACHE_WRAPPER " 
+                                      << name() << std::endl;
+                            std::cout << "the MULTI-UPDATE command length must be N+2 words" 
+                                      << std::endl;
+                            exit(0);
+                        }
+                        r_tgt_update      	= true;
+                        r_tgt_update_data 	= true;
+                        r_tgt_fsm 		= TGT_UPDT_WORD;
+
+                        m_cpt_cc_update_dcache++;
+                    }
+                    else					// update instruction
+                    {
+
+
+                        if ( p_vci_tgt_c.eop.read() ) 
+                        {
+                            std::cout << "error in component VCI_CC_VCACHE_WRAPPER " 
+                                      << name() << std::endl;
+                            std::cout << "the MULTI-UPDATE command length must be N+2 words" 
+                                      << std::endl;
+                            exit(0);
+                        }
+                        r_tgt_update      	= true;
+                        r_tgt_update_data 	= false;
+                        r_tgt_fsm 		= TGT_UPDT_WORD;
+
+                        m_cpt_cc_update_icache++;
+                    }
+                } // end if multi
+            } // end if cmdval
+            break;
+        }
+        //////////////////
+        case TGT_UPDT_WORD:	 // first word index acquisition fo update requests
+
+        {
+            if (p_vci_tgt_c.cmdval.read()) 
+            {
+                if ( p_vci_tgt_c.eop.read() ) 
+                {
+                    std::cout << "error in component VCI_CC_XCACHE_WRAPPER " 
+                              << name() << std::endl;
+                    std::cout << "the MULTI-UPDATE command length must be N+2 words" 
+                              << std::endl;
+                    exit(0);
+                }
+
+                for ( size_t i=0 ; i<m_cache_words ; i++ ) r_tgt_be[i] = 0;
+
+                r_tgt_word_min   = p_vci_tgt_c.wdata.read();  // first modified word 
+                r_tgt_word_count = p_vci_tgt_c.wdata.read();  // initializes the word counter
+                r_tgt_fsm   = TGT_UPDT_DATA;
+            }
+            break;
+        }
+        ///////////////////
+        case TGT_UPDT_DATA:  // data acquisition for update requests
+        {
+            if (p_vci_tgt_c.cmdval.read()) 
+            {
+                size_t word = r_tgt_word_count.read();
+                if ( word >= m_cache_words ) 
+                {
+                    std::cout << "error in component VCI_CC_XCACHE_WRAPPER " 
+                              << name() << std::endl;
+                    std::cout << "the reveived MULTI-UPDATE command length is wrong" 
+                              << std::endl;
+                    exit(0);
+                }
+
+                r_tgt_buf[word] = p_vci_tgt_c.wdata.read();
+                r_tgt_be [word] = p_vci_tgt_c.be.read();
+
+                r_tgt_word_count = word + 1;
+                if (p_vci_tgt_c.eop.read())  // last word 
+                {
+                    r_tgt_word_max = word;          // last modified word 
+              	    if(r_tgt_update_data.read()) 	r_tgt_fsm = TGT_REQ_DCACHE;
+                    else 			        r_tgt_fsm = TGT_REQ_ICACHE;
+                }
+            }
+            break;
+        }
+        ///////////////////////
+        case TGT_REQ_BROADCAST: // set the requests (if no previous request pending)
+        {
+            if (not r_tgt_icache_req.read() and not r_tgt_dcache_req.read()) 
+            {
+                r_tgt_fsm = TGT_RSP_BROADCAST; 
+                r_tgt_icache_req = true;
+                r_tgt_dcache_req = true;
+            }
+            break;
+        }
+        ////////////////////
+        case TGT_REQ_ICACHE: // set the request (if no previous request pending)
+        {
+            if ( not r_tgt_icache_req.read() ) 
+            {
+                r_tgt_fsm = TGT_RSP_ICACHE; 
+                r_tgt_icache_req = true;
+            }
+            break;
+        }
+        ////////////////////
+        case TGT_REQ_DCACHE: // set the request (if no previous request pending)
+        {
+            if ( not r_tgt_dcache_req.read() ) 
+            {
+                r_tgt_fsm = TGT_RSP_DCACHE; 
+                r_tgt_dcache_req = true;
+            }
+            break;
+        }
+        ///////////////////////
+        case TGT_RSP_BROADCAST:  // waiting acknowlege from both dcache fsm and icache fsm
+                                 // no VCI response when the r_tgt_*cache_rsp flip_flop is false
+        {
+            if ( not r_tgt_icache_req.read() and not r_tgt_dcache_req.read() )
+            {
+                if ( r_tgt_icache_rsp.read() or r_tgt_dcache_rsp.read() )  // at least one response
+                {
+                    if ( p_vci_tgt_c.rspack.read())
+                    {
+                        // reset dcache first if activated
+                        if (r_tgt_dcache_rsp) 	r_tgt_dcache_rsp = false;
+                        else 		        r_tgt_icache_rsp = false;
+                    }
+                }
+                else
+                {
+                    r_tgt_fsm = TGT_IDLE;
+                }
+            }
+            break;
+        }
+        ////////////////////
+        case TGT_RSP_ICACHE:  // waiting acknowledge from the icache fsm
+        {
+            // no VCI response when the r_tgt_icache_rsp flip_flop is false
+            if ( not r_tgt_icache_req.read() and p_vci_tgt_c.rspack.read() )
+            {
+                r_tgt_fsm = TGT_IDLE;
+                r_tgt_icache_rsp = false; 
+            }
+            break;
+        }
+        ////////////////////
+        case TGT_RSP_DCACHE:  // waiting acknowledge from the dcache fsm
+        {
+            // no VCI response when the r_tgt_dcache_rsp flip_flop is false
+            if ( not r_tgt_dcache_req.read() and p_vci_tgt_c.rspack.read() )
+            {
+                r_tgt_fsm = TGT_IDLE;
+                r_tgt_dcache_rsp = false; 
+            }
+            break;
+        }
+    } // end switch TGT_FSM
+
+    /////////////////////////////////////////////////////////////////////
+    // Get data and instruction requests from processor
+    ///////////////////////////////////////////////////////////////////////
+
+    typename iss_t::InstructionRequest  ireq = ISS_IREQ_INITIALIZER;
+    typename iss_t::DataRequest         dreq = ISS_DREQ_INITIALIZER;
+
+    r_iss->getRequests(ireq, dreq);
+
+    ///////////////////////////////////////////////////////////////////////////////
+    // The ICACHE FSM controls the following ressources:
+    // - r_icache_fsm
+    // - r_icache_fsm_save
+    // - r_icache_addr_save
+    // - r_icache_miss_req (set)
+    // - r_icache_unc_req (set)
+    // - r_icache_cleanup_req (set)
+    // - r_icache_cleanup_line
+    // - r_icache_cleanup_set
+    // - r_icache_cleanup_way
+    // - r_icache_miss_inval
+    // - r_icache (instruction cache access)
+    // - r_vci_rsp_ins_error (reset)
+    // - r_tgt_icache_req (reset)
+    // - r_tgt_icache_rsp
+    // - ireq & irsp structures for communication with the processor
+    //
+    // 1/ Coherence requests (update or invalidate) have highest priority.
+    //    They are taken into account in IDLE, UNC_WAIT, and MISS_WAIT states.
+    //    In case of coherence request the ICACHE FSM goes to the CC_CHECK
+    //    state to test the cache hit, and then to the CC_INVAL or
+    //    CC_UPDATE states to execute the request. It reset the r_tgt_icache_req 
+    //    flip_flop to signal completion, writes in the r_tgt_icache_rsp
+    //    to allow the VCI response, and returns in the pre-empted state.
+    //    
+    // 2/ Processor requests are taken into account only in the IDLE state.
+    //    In case of miss, or in case of uncached instruction, the FSM 
+    //    writes the missing address line in the r_icache_addr_save register 
+    //    and sets the r_icache_miss_req or the r_icache_unc_req flip-flops.
+    //    These request flip-flops are reset by the VCI_RSP FSM
+    //    when the VCI transaction is completed.
+    //
+    // 3/ In case of uncacheable instruction, the VCI_RSP FSM writes the
+    //    requested instruction in the r_icache_unc_buf register, and
+    //    sets the r_icache_unc_valid flip_flop. This flip_flop is reset
+    //    by the ICACHE FSM.
+    //
+    // 4/ In case of bus error, the VCI_RSP FSM sets the r_vci_rsp_ins_error 
+    //    flip-flop, and does not write any data in the response FIFO.
+    //    The r_vci_rsp_ins_error flip-flop is reset by the ICACHE FSM.
+    ////////////////////////////////////////////////////////////////////////////////
+        
+    // The default value for irsp.valid is false
+    typename iss_t::InstructionResponse irsp = ISS_IRSP_INITIALIZER;
+
+    switch( r_icache_fsm.read() ) 
+    {
+        /////////////////
+        case ICACHE_IDLE:
+        {
+            if ( r_tgt_icache_req.read() )    // coherence request
+            {
+                r_icache_fsm = ICACHE_CC_CHECK;
+                r_icache_fsm_save = r_icache_fsm.read();
+                break;
+            } 
+            if ( ireq.valid )  // processor request
+            {
+                bool     cacheable = m_cacheability_table[ireq.addr];
+                vci_addr_t addr     = (vci_addr_t)ireq.addr;
+
+                if ( cacheable )	 // cacheable
+                {
+                    data_t   inst;
+                    bool     hit = r_icache->read(addr, &inst);
+                    m_conso_icache_dir_read++;
+                    m_conso_icache_data_read++;
+                    if ( !hit )     // cacheable miss
+                    {
+                        // in order to avoid a dead-lock with the mem_cache
+                        // (in case of simultaneous broadcast for example),
+                        // we check that the previous cleanup request is completed
+                        // and the ICACHE FSM is blocked in IDLE state until completion
+                        if ( not r_icache_cleanup_req.read() )
+                        {
+                            r_icache_fsm       = ICACHE_MISS_VICTIM;
+                            r_icache_miss_req  = true;
+                            r_icache_addr_save = addr;
+                            m_cpt_ins_miss++;
+                            m_cost_ins_miss_frz++;
+                        }
+                    }
+                    else            // cacheable hit
+                    {
+                        irsp.valid          = true;
+                        irsp.instruction    = inst;
+                        m_cpt_ins_cacheable++;
+                    }
+                } 
+                else 		    // non cacheable
+                {
+                    if ( r_icache_unc_valid.read() and (addr == r_icache_addr_save.read()) )
+                    {
+                        r_icache_unc_valid  = false;
+                        irsp.valid          = true;
+                        irsp.instruction    = r_icache_unc_buf.read();
+                        m_cpt_ins_uncacheable++;
+                    }
+                    else
+                    {
+                        r_icache_unc_valid  = false;
+                        r_icache_fsm       = ICACHE_UNC_WAIT;
+                        r_icache_unc_req   = true;
+                        r_icache_addr_save = addr;
+                    }
+                }
+            }
+            break;
+        }
+        ////////////////////////
+        case ICACHE_MISS_VICTIM:           // Selects (and invalidates) a victim line
+        {                                  // Set the r_icache_cleanup_req flip-flop 
+                                           // when the selected slot is not empty
+            m_cost_ins_miss_frz++;
+
+            size_t       way;
+            size_t       set;
+            vci_addr_t   victim;
+                        
+            r_icache_cleanup_req  = r_icache->victim_select( r_icache_addr_save.read(), 
+                                                             &victim, 
+                                                             &way, 
+                                                             &set );
+            r_icache_cleanup_line = victim;
+            r_icache_cleanup_way  = way;
+            r_icache_cleanup_set  = set;
+            r_icache_fsm = ICACHE_MISS_WAIT;
+            break;
+        }
+        //////////////////////
+        case ICACHE_MISS_WAIT:            // waiting the response to a miss request
+        {                                 // to test a bus error
+            m_cost_ins_miss_frz++;
+
+            if ( r_tgt_icache_req.read() )    // coherence request
+            {
+                r_icache_fsm      = ICACHE_CC_CHECK;
+                r_icache_fsm_save = r_icache_fsm.read();
+                break;
+            }
+
+            if ( r_vci_rsp_ins_error.read() ) 
+            {
+                r_icache_fsm = ICACHE_ERROR;
+            } 
+            else if ( r_vci_rsp_fifo_icache.rok() )
+            {
+                r_icache_update_word = 0;
+                r_icache_fsm = ICACHE_MISS_UPDT;
+            }
+            break;
+        }
+        //////////////////////
+        case ICACHE_MISS_UPDT:          // Update the cache (one word per cycle) 
+        {
+            m_cost_ins_miss_frz++;
+            if ( r_vci_rsp_fifo_icache.rok() )
+            {
+                size_t      word = r_icache_update_word.read();
+                vci_addr_t  addr = r_icache_addr_save.read();
+                size_t      way  = r_icache_cleanup_way.read();
+                size_t      set  = r_icache_cleanup_set.read();
+
+                m_conso_icache_data_write++;
+                // if the pending miss is cancelled by a matching coherence request
+                // we pop the FIFO, but we don't update the cache
+                if ( not r_icache_miss_inval.read() )
+                      r_icache->write( way, 
+                                       set, 
+                                       word, 
+                                       r_vci_rsp_fifo_icache.read() );
+
+                vci_rsp_fifo_icache_get = true;
+                r_icache_update_word = word+1;
+
+                // if last word, finish the update
+                if ( word == m_cache_words-1 )
+                {
+                    if ( not r_icache_miss_inval.read() )
+                    {
+                        m_conso_icache_dir_write++;
+                        r_icache->victim_update_tag(addr, way, set);
+                    }
+                    r_icache_miss_inval = false;
+                    r_icache_fsm = ICACHE_IDLE;
+                }
+            }
+            break;
+        }
+        /////////////////////
+        case ICACHE_UNC_WAIT:           // waiting the response to an uncached request
+        {
+            if ( r_tgt_icache_req.read() )   // coherence request
+            {
+                r_icache_fsm      = ICACHE_CC_CHECK;
+                r_icache_fsm_save = r_icache_fsm.read();
+                break;
+            }
+            if ( r_vci_rsp_ins_error ) 	
+            {
+                r_icache_fsm = ICACHE_ERROR;
+            }
+            else if ( r_vci_rsp_fifo_icache.rok() )
+            {
+                vci_rsp_fifo_icache_get = true;
+                r_icache_unc_buf        = r_vci_rsp_fifo_icache.read();
+                r_icache_unc_valid      = true;                
+                r_icache_fsm            = ICACHE_IDLE;
+            }
+            break;
+        }
+        //////////////////
+        case ICACHE_ERROR:
+        {
+            irsp.error          = true;
+            irsp.valid          = true;
+            r_icache_fsm        = ICACHE_IDLE;
+            r_vci_rsp_ins_error = false;
+            break;
+        }
+        /////////////////////
+        case ICACHE_CC_CHECK:   // check directory in case of coherence request
+        {
+            vci_addr_t 	addr = r_tgt_addr.read();
+            vci_addr_t 	mask = ~((m_cache_words<<2)-1);
+
+            if( (r_icache_fsm_save.read() == ICACHE_MISS_WAIT) and 
+                ((r_icache_addr_save.read() & mask) == (addr & mask))) 
+                // The coherence request matches a pending miss
+            {
+                r_icache_miss_inval = true;
+                r_tgt_icache_req    = false;
+                r_tgt_icache_rsp    = r_tgt_update.read();
+                r_icache_fsm        = r_icache_fsm_save.read();  
+            } 
+            else  // no match for a pending miss
+            {
+                size_t way;
+                size_t set;
+                size_t word;
+                bool   hit = r_icache->hit(addr, 
+                                           &way, 
+                                           &set, 
+                                           &word);
+                r_icache_cc_way = way;
+                r_icache_cc_set = set;
+
+                m_conso_icache_dir_read++;
+
+                if ( hit and r_tgt_update.read() )           // hit update
+                {
+                      r_icache_fsm         = ICACHE_CC_UPDT;
+                      r_icache_update_word = r_tgt_word_min.read();
+                } 
+                else if ( hit and not r_tgt_update.read() )  // hit inval
+                {
+                    r_icache_fsm = ICACHE_CC_INVAL;
+                } 
+                else  				                        // miss can happen
+                {
+                    r_tgt_icache_req = false;
+                    r_tgt_icache_rsp = r_tgt_update.read(); 
+                    r_icache_fsm     = r_icache_fsm_save.read();
+                }
+            }
+            break;
+        }
+        /////////////////////
+        case ICACHE_CC_INVAL:  
+        {                      
+              vci_addr_t nline; 
+              r_icache->inval( r_icache_cc_way.read(),
+                               r_icache_cc_way.read(),
+                               &nline );
+              r_tgt_icache_req = false;
+              r_tgt_icache_rsp = true;
+              r_icache_fsm     = r_icache_fsm_save.read();
+              break;
+        }    
+        /////////////////////
+        case ICACHE_CC_UPDT:
+        {                       
+            size_t  word = r_icache_update_word.read();
+            r_icache->write( r_icache_cc_way.read(),
+                             r_icache_cc_set.read(),
+                             word,
+                             r_tgt_buf[word].read(),
+                             r_tgt_be[word].read() );
+            r_icache_update_word = word+1;
+
+            if ( word == r_tgt_word_max.read() )  // last word
+            {
+                r_tgt_icache_req = false;
+                r_tgt_icache_rsp = true;
+                r_icache_fsm     = r_icache_fsm_save.read();
+            }
+            break;
+        }    
+    } // end switch r_icache_fsm
+
+    // save the IREQ and IRSP fields for the print_trace() function
+    m_ireq_valid        = ireq.valid;
+    m_ireq_addr         = ireq.addr;
+    m_ireq_mode         = ireq.mode;
+    
+    m_irsp_valid        = irsp.valid;
+    m_irsp_instruction  = irsp.instruction;
+    m_irsp_error        = irsp.error;
+
+    //////////////////////////////////////////////////////////////////////://///////////
+    // The DCACHE FSM controls the following ressources:
+    // - r_dcache_fsm
+    // - r_dcache_fsm_save
+    // - r_dcache (data cache access)
+    // - r_dcache_addr_save
+    // - r_dcache_wdata_save
+    // - r_dcache_be_save
+    // - r_dcache_way_save
+    // - r_dcache_set_save
+    // - r_dcache_word_save
+    // - r_dcache_miss_req (set)
+    // - r_dcache_unc_req (set)
+    // - r_dcache_sc_req (set)
+    // - r_dcache_cleanup_req (set)
+    // - r_vci_rsp_data_error (reset)
+    // - r_tgt_dcache_req (reset)
+    // - r_wbuf write
+    // - drsp structure 
+    //
+    // 1/ Coherence requests : 
+    //    There is a coherence request when the tgt_dcache_req flip-flop is set,
+    //    requesting a line invalidation or a line update. 
+    //    Coherence requests are taken into account in IDLE, UNC_WAIT, MISS_WAIT states, 
+    //    and have the highest priority.
+    //    The actions associated to the pre-empted state are not executed, the DCACHE FSM
+    //    goes to the CC_CHECK state to execute the requested action, and returns to the
+    //    pre-empted state.
+    //
+    // 2/ processor requests : 
+    //    Processor READ requests are taken into account in IDLE state only.
+    //    In order to support WRITE bursts, write requests are taken into account 
+    //    in the WRITE_UPDT state as well as in the IDLE state.
+    //    - The processor read requests cannot be satisfied if
+    //    there is a cached read miss, or an uncached read.
+    //    - The processor write requests cannot be satisfied when the write buffer is full.
+    //
+    // 3/ Atomic instructions LL/SC
+    //    The reservation registers (r_dcache_ll_valid, r_dcache_ll_addr and
+    //    r_dcache_ll_data are stored in the L1 cache controller, and not in the 
+    //    memory controller. 
+    //    - LL requests from the processor and are transmitted as standard 
+    //      VCI read transactions (one word / one line, depending on the cacheability).
+    //    - SC requests from the processor are systematically transmitted to the 
+    //      memory cache as compare&swap requests (both the data value stored in the
+    //      r_dcache_ll_data register and the new value). 
+    //    The LL/SC address can be cacheable or not cacheable.
+    //
+    // 4/ Non cacheable access
+    //    This component implement a strong order between non cacheable access
+    //    (read or write) : A new non cacheable VCI transaction starts only when
+    //    the previous non cacheable transaction is completed. Both cacheable and
+    //    non cacheable transactions use the write buffer, but the DCACHE FSM registers
+    //    a non cacheable write transaction posted in the write buffer by setting the
+    //    r_dcache_pending_unc_write flip_flop. All other non cacheable requests
+    //    are stalled until this flip-flop is reset by the VCI_RSP_FSM (when the 
+    //    pending non cacheable write transaction completes).
+    //
+    // 5/ Error handling :  Read Bus Errors are synchronous events, but
+    //    Write Bus Errors are asynchronous events (processor is not frozen).
+    //    - If a Read Bus Error is detected, the VCI_RSP FSM sets the
+    //      r_vci_rsp_data_error flip-flop, without writing any data in the
+    //      r_vci_rsp_fifo_dcache FIFO, and the synchronous error is signaled
+    //      by the DCACHE FSM.
+    //    - If a Write Bus Error is detected, the VCI_RSP FSM  signals
+    //      the asynchronous error using the setWriteBerr() method.
+    ///////////////////////////////////////////////////////////////////////////////////
+
+    // The default value for drsp.valid is false
+    typename iss_t::DataResponse  drsp = ISS_DRSP_INITIALIZER;
+
+    switch ( r_dcache_fsm.read() ) 
+    {
+        /////////////////
+        case DCACHE_IDLE:       // waiting requests from processor
+        {
+            if ( r_tgt_dcache_req.read() )  // coherence request
+            { 
+                r_dcache_fsm      = DCACHE_CC_CHECK;
+                r_dcache_fsm_save = r_dcache_fsm.read();
+                break;
+            } 
+            if ( dreq.valid )  // processor request
+            {
+                bool     	cacheable      = m_cacheability_table[dreq.addr];
+                vci_addr_t	addr          = (vci_addr_t)dreq.addr;
+
+                switch( dreq.type ) 
+                {
+                    case iss_t::DATA_LL:
+                    case iss_t::DATA_READ:
+                    {
+                        if ( cacheable )	// cacheable read   
+                        {
+                            data_t   rdata;
+                            bool     hit = r_dcache->read(addr, &rdata);
+                            m_conso_dcache_dir_read++;
+                            m_conso_dcache_data_read++;
+                            if ( !hit )         // cacheable read miss
+                            {
+                                // in order to avoid a dead-lock with the mem_cache
+                                // (in case of simultaneous broadcast for example),
+                                // we check that the previous cleanup request is completed
+                                // if not the DCACHE_FSM is blocked in IDLE state until completion
+                                if ( not r_dcache_cleanup_req.read() )
+                                {
+                                    r_dcache_fsm       = DCACHE_MISS_VICTIM;
+                                    r_dcache_miss_req  = true;
+                                    r_dcache_addr_save = addr;
+                                    m_cpt_data_read_miss++;
+                                    m_cost_data_miss_frz++;
+                                }
+                            }
+                            else                // cacheable read hit
+                            {
+                                m_cpt_data_read_cacheable++;
+                                drsp.valid   = true;
+                                drsp.rdata   = rdata;
+
+                                // makes reservation in case of LL
+                                if( dreq.type == iss_t::DATA_LL )
+                                {
+                                    m_cpt_data_ll++;
+                                    r_dcache_ll_valid = true;
+                                    r_dcache_ll_data  = rdata;
+                                    r_dcache_ll_addr  = addr;
+                                }
+                            }
+                        }
+                        else            // non cacheable read   
+                        {
+                            // non cacheable accesses must be strongly ordered
+                            // A non cacheable read must be delayed if there is 
+                            // a pending uncacheable write in the write buffer 
+                            if ( not r_dcache_pending_unc_write.read() )
+                            {
+                                if ( r_dcache_unc_valid.read() and 			// hit
+                                           (addr == r_dcache_addr_save.read()) )
+                                {
+                                    r_dcache_unc_valid = false;
+                                    drsp.valid         = true;
+                                    drsp.rdata         = r_dcache_unc_buf.read();
+                                    m_cpt_data_read_uncacheable++;
+
+                                    // makes reservation in case of uncacheable LL
+                                    if( dreq.type == iss_t::DATA_LL )
+                                    {
+                                        m_cpt_data_ll++;
+                                        r_dcache_ll_valid = true;
+                                        r_dcache_ll_data  = r_dcache_unc_buf.read();
+                                        r_dcache_ll_addr  = addr;
+                                    }
+                                }
+                                else							// miss
+                                {
+                                    r_dcache_unc_valid = false;
+                                    r_dcache_unc_req   = true;
+                                    r_dcache_fsm       = DCACHE_UNC_WAIT;
+                                    r_dcache_addr_save = addr;
+                                }
+                            } // end if pending_unc_write
+                        }                        
+                        break;
+                    }
+                    case iss_t::DATA_SC:
+                    {
+                        // - if a previous LL (with the same address) is registered, 
+                        // we makes a SC transaction, that will store the response
+                        // in the r_dcache_unc_buf register (0 if success).
+                        // As for the non cacheable read, we must test the 
+                        // r_dcache_unc_valid flip-flop to detect the SC completion,
+                        // return the value stored in r_dcache_unc_buf, and invalidate
+                        // the LL reservation.
+                        // - if there is no registerd LL, we just stay in IDLE state 
+                        // and return 1 (atomic access failed)
+
+                        if( r_dcache_ll_valid.read() and (r_dcache_ll_addr.read() == addr))
+                        {
+                            if ( r_dcache_unc_valid.read() and 		// SC done
+                                    (addr == r_dcache_addr_save.read()) )
+                            {
+                                r_dcache_ll_valid  = false;
+                                r_dcache_unc_valid = false;
+                                drsp.valid         = true;
+                                drsp.rdata         = r_dcache_unc_buf.read();
+                                m_cpt_data_sc++;
+                            }
+                            else					// SC to be done
+                            {
+                                r_dcache_sc_req     = true;
+                                r_dcache_fsm        = DCACHE_UNC_WAIT;
+                                r_dcache_addr_save  = addr;
+                                r_dcache_wdata_save = dreq.wdata;
+                            }
+                        } 
+                        else 					// no registered LL
+                        {
+                            drsp.valid = true;
+                            drsp.rdata = 1; 
+                            r_dcache_ll_valid = false;
+                        }
+                        break;
+                    }
+                    case iss_t::XTN_READ:
+                    case iss_t::XTN_WRITE:
+                    {
+                        // only DCACHE INVALIDATE and SYNC requests are supported
+                        if ( dreq.addr>>2 == iss_t::XTN_DCACHE_INVAL ) 
+                        {
+                            m_cpt_xtn_dcache_inval++;
+                            r_dcache_fsm        = DCACHE_INVAL;
+                            r_dcache_wdata_save = dreq.wdata;
+                        } 
+                        else if ( dreq.addr>>2 == iss_t::XTN_SYNC )
+                        {
+                            m_cpt_xtn_sync++;
+                            // Test if write buffer is already empty
+                            if ( r_wbuf->empty() )
+                            {
+                                drsp.valid = true;
+                                r_dcache_fsm  = DCACHE_IDLE;
+                            }
+                            else
+                            {
+                                r_dcache_fsm  = DCACHE_SYNC;
+                            }
+                        }
+                        else
+                        {
+                            std::cout << "Warning in VCI_CC_XCACHE_WRAPPER " 
+                                      << name() << std::endl;
+                            std::cout << "Unsupported  external access : " 
+                                      << (dreq.addr>>2) << std::endl;
+                            drsp.valid = true;
+                            r_dcache_fsm  = DCACHE_IDLE;
+                        }
+                        break;
+                    }
+                    case iss_t::DATA_WRITE:
+                    {
+                        if ( cacheable )     // cacheable write
+                        {
+                            bool    hit;
+                            size_t  way		= 0;
+                            size_t  set		= 0;
+                            size_t  word	= 0;
+
+                            m_conso_dcache_dir_read++;
+                            hit = r_dcache->hit(addr, &way, &set, &word);
+                            m_conso_wbuf_write++;
+                            bool wok = r_wbuf->write(addr, dreq.be, dreq.wdata, cacheable);
+                            if ( wok )
+                            {
+                                m_cpt_data_write_cacheable++;
+                                drsp.valid = true;
+                                if (hit)    // cached write
+                                {
+                                    m_cpt_data_write_hit++;
+                                    r_dcache_fsm          = DCACHE_WRITE_UPDT; 
+                                    r_dcache_addr_save    = addr;
+                                    r_dcache_wdata_save   = dreq.wdata;
+                                    r_dcache_be_save      = dreq.be;
+                                    r_dcache_way_save     = way;
+                                    r_dcache_set_save     = set;
+                                    r_dcache_word_save    = word;
+                                }
+                                else	  // non cached
+                                {
+                                    r_dcache_fsm = DCACHE_IDLE;
+                                }
+                            }
+                            else  // write miss into write buffer
+                            {
+                                r_dcache_fsm = DCACHE_IDLE;
+                                m_cost_write_frz++;
+                            }
+                        }
+                        else                // non cacheable write 
+                        {
+                            // non cacheable accesses must be strongly ordered
+                            // A non cacahble write must be delayed if there is 
+                            // a pending uncacheable write in the write buffer 
+                            if ( not r_dcache_pending_unc_write.read() )
+                            {
+                                m_conso_wbuf_write++;
+                                bool wok = r_wbuf->write(addr, dreq.be, dreq.wdata, cacheable);
+                                if ( wok ) 
+                                {
+                                    m_cpt_data_write_uncacheable++;
+                                    drsp.valid = true;
+                                }
+                            }
+                            r_dcache_fsm = DCACHE_IDLE;
+                        }
+
+                        break;
+                    }
+                }   // end switch dreq.type
+            }   // end if dreq.valid
+            break;
+        }
+        ///////////////////////
+        case DCACHE_WRITE_UPDT:
+        {
+            // cache update (address, data & be from the previous cycle)
+            m_conso_dcache_data_write++;
+            r_dcache->write( r_dcache_way_save.read(),         
+                             r_dcache_set_save.read(),        
+                             r_dcache_word_save.read(),
+                             r_dcache_wdata_save.read(),  
+                             r_dcache_be_save.read() );  
+
+#if DEBUG_DCACHE
+if ( (m_cpt_total_cycles > DEBUG_START_CYCLE) and (m_srcid_d == DEBUG_ID) )
+{
+    std::cout << "  <PROC.DCACHE_WRITE_UPDT> Writing one word :" << std::hex
+              << " data = " << r_dcache_wdata_save.read()
+              << " / be = " << r_dcache_be_save.read()
+              << " / way = " << r_dcache_way_save.read()
+              << " / set = " << r_dcache_set_save.read()
+              << " / word = " << r_dcache_word_save.read() << std::endl;
+}
+#endif
+
+            // possible write after write
+            if ( dreq.valid and (dreq.type == iss_t::DATA_WRITE) )
+            {
+                bool     cacheable = m_cacheability_table[dreq.addr];
+                vci_addr_t addr     = (vci_addr_t)dreq.addr;
+
+                if ( cacheable ) // cacheable write
+                {
+                    bool    hit;
+                    size_t  way  = 0;
+                    size_t  set  = 0;
+                    size_t  word = 0;
+
+                    m_conso_dcache_dir_read++;
+                    hit = r_dcache->hit(addr, &way, &set, &word);
+                    m_conso_wbuf_write++;
+                    bool wok = r_wbuf->write(addr, dreq.be, dreq.wdata, cacheable);
+                    if (wok)   
+                    {
+                        m_cpt_data_write_cacheable++;
+                        drsp.valid = true;
+                        if (hit)        // cached write
+                        {
+                            m_cpt_data_write_hit++;
+                            r_dcache_fsm          = DCACHE_WRITE_UPDT; 
+                            r_dcache_addr_save    = addr;
+                            r_dcache_wdata_save   = dreq.wdata;
+                            r_dcache_be_save      = dreq.be;
+                            r_dcache_way_save     = way;
+                            r_dcache_set_save     = set;
+                            r_dcache_word_save    = word;
+                        }
+                        else   // uncached write
+                        {
+                            r_dcache_fsm = DCACHE_IDLE;
+                        }
+                    }
+                    else   // write miss into write buffer
+                    {
+                        m_cost_write_frz++;
+                        r_dcache_fsm = DCACHE_IDLE;
+                    }
+                }
+                else  // non cacheable write
+                {
+                    // non cacheable accesses must be strongly ordered 
+                    // A non cacahble write must be delayed if there is 
+                    // a pending uncacheable write in the write buffer 
+                    if ( not r_dcache_pending_unc_write.read() )
+                    {
+                        m_conso_wbuf_write++;
+                        bool wok = r_wbuf->write(addr, dreq.be, dreq.wdata, cacheable);
+                        if ( wok ) 
+                        {
+                            m_cpt_data_write_uncacheable++;
+                            drsp.valid = true;
+                        }
+                    }
+                    r_dcache_fsm = DCACHE_IDLE;
+                }
+            }
+            else    // no valid write request
+            {
+                r_dcache_fsm = DCACHE_IDLE;
+            }
+            break;
+        }
+        ////////////////////////
+        case DCACHE_MISS_VICTIM:           // Selects (and invalidates) a victim line
+        {                                  // Set the r_dcache_cleanup_req flip-flop 
+                                           // when the selected slot is not empty
+            m_cost_data_miss_frz++;
+
+            size_t     way;
+            size_t     set;
+            vci_addr_t   addr = r_dcache_addr_save.read();
+            vci_addr_t   victim;
+                        
+            bool cleanup_requested = r_dcache->victim_select( addr, &victim, &way, &set );
+
+            r_dcache_cleanup_line = victim;
+            r_dcache_cleanup_way  = way;
+            r_dcache_cleanup_set  = set;
+            r_dcache_cleanup_req  = cleanup_requested;
+            r_dcache_fsm = DCACHE_MISS_WAIT;
+            break;
+        }
+        //////////////////////
+        case DCACHE_MISS_WAIT:          // Waiting the response to a miss request
+        {                               // to test a bus error
+            m_cost_data_miss_frz++;
+
+            if ( r_tgt_dcache_req.read() )    // coherence request
+            {
+                r_dcache_fsm      = DCACHE_CC_CHECK;
+                r_dcache_fsm_save = r_dcache_fsm.read();
+                break;
+            }
+
+            if ( r_vci_rsp_data_error.read() ) 
+            {
+                r_dcache_fsm = DCACHE_ERROR;
+            } 
+            else if ( r_vci_rsp_fifo_dcache.rok() )
+            {
+                r_dcache_update_word = 0;
+                r_dcache_fsm = DCACHE_MISS_UPDT;
+            }
+            break;
+        }
+        //////////////////////
+        case DCACHE_MISS_UPDT:      // Update the cache (one word per cycle)
+        {
+            m_cost_data_miss_frz++;
+
+            size_t       word = r_dcache_update_word.read();
+            vci_addr_t   addr = r_dcache_addr_save.read();
+            size_t       way  = r_dcache_cleanup_way.read();
+            size_t       set  = r_dcache_cleanup_set.read();
+                    
+            if ( r_vci_rsp_fifo_dcache.rok() )
+            {
+                if ( not r_dcache_miss_inval.read() )  // no matching coherence request
+                {
+                    m_conso_dcache_data_write++;
+                    r_dcache->write( way, 
+                                     set, 
+                                     word, 
+                                     r_vci_rsp_fifo_dcache.read() );
+
+                    if ( word == m_cache_words-1 )	// last word
+                    {
+                        m_conso_dcache_dir_write++;
+                        r_dcache->victim_update_tag(addr, way, set);
+                        r_dcache_fsm = DCACHE_IDLE;
+                    }
+                    vci_rsp_fifo_dcache_get = true;
+                    r_dcache_update_word = word+1;
+                }
+                else	// if there is a matching coherence request :
+                        // we pop the response FIFO, but we don't update the cache
+                        // when we receive the last word, we send a cleanup for the
+                        // missing line and return to the IDLE state
+                {
+                    if ( word < m_cache_words-1 ) 
+                    {
+                        vci_rsp_fifo_dcache_get = true;
+                        r_dcache_update_word = word+1;
+                    }
+                    else	// last word
+                    {
+                        if ( not r_dcache_cleanup_req )
+                        {
+                            vci_rsp_fifo_dcache_get = true;
+                            r_dcache_cleanup_req  = true;
+                            r_dcache_cleanup_line = r_dcache_addr_save.read() >> m_cache_words_shift;
+                            r_dcache_miss_inval    = false;
+                            r_dcache_fsm          = DCACHE_IDLE;
+                        }
+                    }
+                }
+
+#if DEBUG_DCACHE
+if ( (m_cpt_total_cycles > DEBUG_START_CYCLE) and (m_srcid_d == DEBUG_ID) )
+{
+    if ( r_dcache_miss_inval.read() )
+    {
+        if ( word < m_cache_words-1 ) 
+        {
+            std::cout << "  <PROC.DCACHE_MISS_UPDT> Matching coherence request:"
+                      << "  pop the FIFO, don't update the cache" << std::endl;
+        }
+        else
+        {
+            std::cout << "  <PROC.DCACHE_MISS_UPDT> Matching coherence request:"
+                      << " last word : send a cleanup request " << std::endl;
+        }
+    }
+    else
+    {
+        std::cout << "  <PROC.DCACHE_MISS_UPDT> Write one word:"
+                  << " address = " << addr 
+                  << " / data = " << r_vci_rsp_fifo_dcache.read()
+                  << " / way = " << way 
+                  << " / set = " << set
+                  << " / word = " << word << std::endl; 
+    }
+}
+#endif
+            }
+            break;
+        }
+        /////////////////////
+        case DCACHE_UNC_WAIT:       // Waiting the response to an uncached request
+        {
+            if ( r_tgt_dcache_req )    // coherence request
+            {
+                r_dcache_fsm      = DCACHE_CC_CHECK;
+                r_dcache_fsm_save = r_dcache_fsm;
+                break;
+            } 
+
+            if ( r_vci_rsp_data_error ) 
+            {
+                r_dcache_fsm = DCACHE_ERROR;
+            }
+            else if ( r_vci_rsp_fifo_dcache.rok() )
+            {
+                vci_rsp_fifo_dcache_get = true;
+                r_dcache_unc_valid      = true;
+                r_dcache_unc_buf        = r_vci_rsp_fifo_dcache.read();
+                r_dcache_fsm            = DCACHE_IDLE;
+            }
+            break;
+        }
+        //////////////////
+        case DCACHE_ERROR:      // signal a read bus error to the processor
+        {
+            r_dcache_fsm         = DCACHE_IDLE;
+            r_vci_rsp_data_error = false;
+            drsp.error           = true;
+            drsp.valid           = true;
+            break;
+        }
+        //////////////////    
+        case DCACHE_INVAL:      // XTN inval is done in two cycles
+                                // In this state we test the cache hit
+        {                   
+            uint32_t    data;   // unused
+            size_t      word;   // unused
+            size_t      way;
+            size_t      set;
+            bool        hit = r_dcache->read( r_dcache_wdata_save.read(),
+                                              &data,
+                                              &way,
+                                              &set,
+                                              &word );
+            if ( hit )  // inval to be done
+            {
+                r_dcache_way_save = way;
+                r_dcache_set_save = set;
+                r_dcache_fsm      = DCACHE_INVAL_GO;
+            }
+            else        // nothing to do
+            {
+                drsp.valid        = true;
+                r_dcache_fsm      = DCACHE_IDLE;
+            }
+            break;
+        }
+        /////////////////////    
+        case DCACHE_INVAL_GO:   // XTN inval is done in two cycles
+                                // In this state we wait to post a cleanup request
+                                // and make the inval when cleanup is possible
+        {
+
+            if ( r_tgt_dcache_req )  // coherence request
+            {   
+                r_dcache_fsm      = DCACHE_CC_CHECK;
+                r_dcache_fsm_save = r_dcache_fsm;
+                break;
+            } 
+
+            if ( not r_dcache_cleanup_req .read() )
+            {
+                vci_addr_t  nline;
+                r_dcache_cleanup_req  = r_dcache->inval( r_dcache_way_save.read(),
+                                                         r_dcache_set_save.read(),
+                                                         &nline );
+
+                r_dcache_cleanup_line = r_dcache_wdata_save.read() >> m_cache_words_shift;
+                r_dcache_fsm          = DCACHE_IDLE;
+                drsp.valid            = true;      
+            }
+            break;
+        }
+        /////////////////
+        case DCACHE_SYNC:       // waiting until the write buffer is empty
+        {
+            if ( r_tgt_dcache_req )  // coherence request
+            {   
+                r_dcache_fsm      = DCACHE_CC_CHECK;
+                r_dcache_fsm_save = r_dcache_fsm;
+                break;
+            } 
+
+            if ( r_wbuf->empty() );
+            {
+                drsp.valid    = true;      
+                r_dcache_fsm  = DCACHE_IDLE;
+            }
+            break;
+        }
+        /////////////////////
+        case DCACHE_CC_CHECK:   // read directory in case of coherence request
+        {
+            vci_addr_t  addr  = r_tgt_addr.read();
+            vci_addr_t  mask  = ~((m_cache_words<<2)-1);
+
+            if( (r_dcache_fsm_save.read() == DCACHE_MISS_WAIT) and 
+                 ((r_dcache_addr_save.read() & mask) == (addr & mask)) )
+                 // The coherence request matches a pending miss
+            {
+                r_dcache_miss_inval = true;
+                r_tgt_dcache_req    = false;
+                r_tgt_dcache_rsp    = r_tgt_update.read();
+                r_dcache_fsm        = r_dcache_fsm_save.read();
+            }
+            else    // no match for a pending miss
+            {
+                size_t  way;
+                size_t  set;
+                size_t  word;
+                bool    hit   = r_dcache->hit( addr, 
+                                               &way, 
+                                               &set, 
+                                               &word );
+                r_dcache_cc_way = way;
+                r_dcache_cc_set = set;
+
+                m_conso_dcache_dir_read++;
+
+                if ( hit and r_tgt_update.read() )          // hit update
+                {
+                    r_dcache_fsm         = DCACHE_CC_UPDT;
+                    r_dcache_update_word = r_tgt_word_min.read();
+                }
+                else if (hit and not r_tgt_update.read() )  // hit inval
+                {
+                    r_dcache_fsm         = DCACHE_CC_INVAL;
+                }
+                else                                        // miss can happen
+                {
+                    r_tgt_dcache_req = false;
+                    r_tgt_dcache_rsp = r_tgt_update.read();
+                    r_dcache_fsm     = r_dcache_fsm_save.read();
+                }
+            }
+            break;
+        }
+        /////////////////////
+        case DCACHE_CC_INVAL:  
+        {
+            vci_addr_t  nline;
+            r_dcache->inval( r_dcache_cc_way.read(),
+                             r_dcache_cc_set.read(),
+                             &nline );
+            r_tgt_dcache_req = false;
+            r_tgt_dcache_rsp = true;
+            r_dcache_fsm     = r_dcache_fsm_save.read();
+            break;
+        }
+        ////////////////////
+        case DCACHE_CC_UPDT:   
+        {
+              size_t word = r_dcache_update_word.read();
+              r_dcache->write( r_dcache_cc_way.read(),
+                               r_dcache_cc_set.read(),
+                               word,
+                               r_tgt_buf[ word].read(),
+                               r_tgt_be[word].read() );
+
+              r_dcache_update_word = word+1;
+              if ( word == r_tgt_word_max.read() )      // last word
+              {
+                  r_tgt_dcache_req = false;
+                  r_tgt_dcache_rsp = true;
+                  r_dcache_fsm     = r_dcache_fsm_save.read();
+              }
+              break;
+          }
+    } // end switch r_dcache_fsm
+        
+    // save the DREQ and DRSP fields for the print_trace() function
+    m_dreq_valid = dreq.valid;
+    m_dreq_addr  = dreq.addr;
+    m_dreq_mode  = dreq.mode;
+    m_dreq_type  = dreq.type;
+    m_dreq_wdata = dreq.wdata;
+    m_dreq_be    = dreq.be;
+    
+    m_drsp_valid = drsp.valid;
+    m_drsp_rdata = drsp.rdata;
+    m_drsp_error = drsp.error;
+
+    ////////// write buffer state update  ////////////////////////////////////////////
+    // The update() method must be called at each cycle to update the internal state.
+
+    r_wbuf->update ();
+
+    /////////// test processor frozen /////////////////////////////////////////////
+    // The simulation exit if the number of consecutive frozen cycles
+    // is larger than the m_max_frozen_cycles (constructor parameter)
+    if ( (ireq.valid and not irsp.valid) or (dreq.valid and not drsp.valid) )       
+    {
+        m_cpt_frz_cycles++;         // used for instrumentation
+        m_cpt_stop_simulation++;    // used for processor stop if frozen
+        if ( m_cpt_stop_simulation > m_max_frozen_cycles )
+        {
+            std::cout << std::dec << "ERROR in CC_XCACHE_WRAPPER " << name()
+                      << " frozen since cycle " << m_cpt_total_cycles - m_max_frozen_cycles 
+                      << std::endl;
+            exit(1);
+        }
+    }
+    else
+    {
+        m_cpt_stop_simulation = 0;
+    }
+
+    /////////// execute one iss cycle /////////////////////////////////////////////
+
+    uint32_t it = 0;
+    for (size_t i=0; i<(size_t)iss_t::n_irq; i++) if ( p_irq[i].read() ) it |= (1<<i);
+                
+    r_iss->executeNCycles(1, irsp, drsp, it);
+
+    ////////////////////////////////////////////////////////////////////////////////
+    // The CLEANUP FSM send the cleanup commands on the coherence network,
+    // and supports simultaneous cleanup transactions, but two simultaneous
+    // transactions mut address different cache lines.
+    // Therefore, the line number is registered in an associative
+    // registration buffer (Content Adressable Memory) by the CLEANUP FSM,
+    // and the corresponding slot (identified by the VCI TRDID field) is cleared 
+    // when the cleanup transaction response is received.
+    // It handles cleanup requests from both the DCACHE FSM & ICACHE FSM
+    // with a round robin priority, and can support up to 16 simultaneous 
+    // cleanup transactions (16 slots in the registration buffer).
+    // The r_dcache_cleanup_req (or r_icache_cleanup_req) flip-flops are reset
+    // when the command has been sent.
+    // The VCI TRDID field is used to distinguish data/instruction cleanups:
+    // - if data cleanup        : TRDID = 2*index + 0
+    // - if instruction cleanup : TRDID = 2*index + 1
+    ////////////////////////////////////////////////////////////////////////////
+
+    switch ( r_cleanup_fsm.read() ) 
+    {
+        ///////////////////////
+        case CLEANUP_DATA_IDLE:     // dcache has highest priority
+        {
+            size_t  index = 0;
+            bool    ok;
+            if ( r_dcache_cleanup_req.read() )      // dcache request
+            {
+                ok = r_cleanup_buffer.register_value( r_dcache_cleanup_line.read(), 
+                                                      &index );   
+                if ( ok )   // successful registration
+                {
+                    r_cleanup_fsm   = CLEANUP_DATA_GO; 
+                    r_cleanup_trdid = index<<1;
+                }
+            }
+            else if ( r_icache_cleanup_req.read() ) // icache request
+            {
+                ok = r_cleanup_buffer.register_value( r_icache_cleanup_line.read(), 
+                                                      &index );   
+                if ( ok )   // successful registration
+                {
+                    r_cleanup_fsm   = CLEANUP_INS_GO; 
+                    r_cleanup_trdid = index<<1 + 1;
+                }
+            }
+            break;
+        }
+        //////////////////////
+        case CLEANUP_INS_IDLE:     // icache has highest priority
+        {
+            size_t  index = 0;
+            bool    ok;
+            if ( r_icache_cleanup_req.read() )      // icache request
+            {
+                ok = r_cleanup_buffer.register_value( r_icache_cleanup_line.read(),
+                                                      &index );   
+                if ( ok )   // successful registration
+                {
+                    r_cleanup_fsm   = CLEANUP_INS_GO;
+                    r_cleanup_trdid = index<<1 + 1;
+                }
+            }
+            else if ( r_dcache_cleanup_req.read() ) // dcache request
+            {
+                ok = r_cleanup_buffer.register_value( r_dcache_cleanup_line.read(),
+                                                      &index );   
+                if ( ok )   // successful registration
+                {
+                    r_cleanup_fsm   = CLEANUP_DATA_GO;
+                    r_cleanup_trdid = index<<1;
+                }
+            }
+            break;
+        }
+        /////////////////////
+        case CLEANUP_DATA_GO:
+        {
+            if ( p_vci_ini_c.cmdack.read() )
+            {
+                r_dcache_cleanup_req = false;
+                r_cleanup_fsm    = CLEANUP_INS_IDLE;
+            }
+        }
+        ////////////////////////
+        case CLEANUP_INS_GO:
+        {
+            if ( p_vci_ini_c.cmdack.read() )
+            {
+                r_icache_cleanup_req = false;
+                r_cleanup_fsm    = CLEANUP_DATA_IDLE;
+            }
+        }
+    } // end switch CLEANUP FSM
+
+    //////////////// Handling  cleanup responses //////////////////
+    if ( p_vci_ini_c.rspval.read() )    // valid response
+    {
+        r_cleanup_buffer.cancel_index( p_vci_ini_c.rtrdid.read() >> 1);
+    }
+
+    ////////////////////////////////////////////////////////////////////////////
+    // The VCI_CMD FSM controls the following ressources:
+    // - r_vci_cmd_fsm
+    // - r_vci_cmd_min
+    // - r_vci_cmd_max
+    // - r_vci_cmd_cpt
+    // - r_vci_cmd_imiss_prio
+    // - wbuf (reset)
+    // - r_icache_miss_req (reset)
+    // - r_icache_unc_req (reset)
+    // - r_dcache_miss_req (reset)
+    // - r_dcache_unc_req (reset)
+    // - r_dcache_sc_req (reset)
+    //
+    // This FSM handles requests from both the DCACHE FSM & the ICACHE FSM.
+    // There is 6 request types, with the following priorities : 
+    // 1 - Data Read Miss         : r_dcache_miss_req and miss in the write buffer
+    // 2 - Data Read Uncacheable   : r_dcache_unc_req  
+    // 3 - Instruction Miss       : r_icache_miss_req and miss in the write buffer
+    // 4 - Instruction Uncacheable : r_icache_unc_req 
+    // 5 - Data Write             : r_wbuf.rok()      
+    // 6 - Data Store Conditionnal: r_dcache_sc_req
+    //
+    // As we want to support several simultaneous VCI transactions, the VCI_CMD_FSM 
+    // and the VCI_RSP_FSM are fully desynchronized.
+    //
+    // VCI formats:
+    // According to the VCI advanced specification, all read requests packets 
+    // (data Uncached, Miss data, instruction Uncached, Miss instruction) 
+    // are one word packets.
+    // For write burst packets, all words are in the same cache line,
+    // and addresses must be contiguous (the BE field is 0 in case of "holes").
+    // The sc command packet implements actually a compare-and-swap mechanism
+    // and the packet contains two flits. 
+    //////////////////////////////////////////////////////////////////////////////
+
+    switch ( r_vci_cmd_fsm.read() ) 
+    {
+        //////////////
+        case CMD_IDLE:
+        {
+            // r_dcache_miss_req and r_icache_miss_req require both a write_buffer access 
+            // to check a possible pending write on the same cache line. 
+            // As there is only one possible access per cycle to write buffer, we implement 
+            // a round-robin priority for this access, using the r_vci_cmd_imiss_prio flip-flop.
+
+            size_t	wbuf_min;
+            size_t	wbuf_max;
+
+            bool dcache_miss_req = r_dcache_miss_req.read() 
+                 and ( not r_icache_miss_req.read() or not r_vci_cmd_imiss_prio.read() );
+            bool icache_miss_req = r_icache_miss_req.read() 
+                 and ( not r_dcache_miss_req.read() or r_vci_cmd_imiss_prio.read() );
+
+            // 1 - Data Read Miss
+            if ( dcache_miss_req and r_wbuf->miss(r_dcache_addr_save.read()) )
+            { 
+                r_vci_cmd_fsm        = CMD_DATA_MISS;
+                r_dcache_miss_req    = false;
+                r_vci_cmd_imiss_prio = true;
+                m_cpt_dmiss_transaction++; 
+            } 
+            // 2 - Data Read Uncacheable
+            else if ( r_dcache_unc_req.read() )
+            { 
+                r_vci_cmd_fsm    = CMD_DATA_UNC;
+                r_dcache_unc_req = false;
+                m_cpt_dunc_transaction++; 
+            }
+            // 3 - Instruction Miss
+            else if ( icache_miss_req and r_wbuf->miss(r_icache_addr_save.read()) )
+            {
+                r_vci_cmd_fsm        = CMD_INS_MISS; 
+                r_icache_miss_req    = false;
+                r_vci_cmd_imiss_prio = false;
+                m_cpt_imiss_transaction++;
+            } 
+            // 4 - Instruction Uncacheable
+            else if ( r_icache_unc_req.read() )
+            { 
+                r_vci_cmd_fsm    = CMD_INS_UNC; 
+                r_icache_unc_req = false;
+                m_cpt_iunc_transaction++;
+            }
+            // 5 - Data Write
+            else if ( r_wbuf->rok(&wbuf_min, &wbuf_max) )
+            { 
+                r_vci_cmd_fsm       = CMD_DATA_WRITE;
+                r_vci_cmd_cpt       = wbuf_min;
+                r_vci_cmd_min       = wbuf_min;
+                r_vci_cmd_max       = wbuf_max;
+                m_cpt_write_transaction++; 
+                m_length_write_transaction += (wbuf_max-wbuf_min+1); 
+            } 
+            // 6 - Data Store Conditionnal
+            else if ( r_dcache_sc_req.read() )
+            { 
+                r_vci_cmd_fsm       = CMD_DATA_SC;
+                r_dcache_sc_req = false;
+                r_vci_cmd_cpt       = 0;
+                m_cpt_sc_transaction++; 
+            }
+            break;
+        }
+        ////////////////////
+        case CMD_DATA_WRITE:
+        {
+            if ( p_vci_ini_d.cmdack.read() ) 
+            {
+                m_conso_wbuf_read++;
+                r_vci_cmd_cpt = r_vci_cmd_cpt + 1;
+                if (r_vci_cmd_cpt == r_vci_cmd_max) // last flit sent
+                {
+                    r_vci_cmd_fsm = CMD_IDLE ;
+                    r_wbuf->sent() ;
+                }
+            }
+            break;
+        }
+        /////////////////
+        case CMD_DATA_SC:
+        {
+            // The SC VCI command contains two flits
+            if ( p_vci_ini_d.cmdack.read() ) 
+            {
+               r_vci_cmd_cpt = r_vci_cmd_cpt + 1;
+               if (r_vci_cmd_cpt == 1) r_vci_cmd_fsm = CMD_IDLE ;
+            }
+            break;
+        }
+        //////////////////
+        case CMD_INS_MISS:
+        case CMD_INS_UNC:
+        case CMD_DATA_MISS:
+        case CMD_DATA_UNC:
+        {
+            // all read VCI commands contain one single flit
+            if ( p_vci_ini_d.cmdack.read() )  r_vci_cmd_fsm = CMD_IDLE; 
+            break;
+        }
+
+    } // end  switch r_vci_cmd_fsm
+
+    ///////////////////////////////////////////////////////////////////////////////
+    // The VCI_RSP FSM controls the following ressources:
+    // - r_vci_rsp_fsm:
+    // - r_vci_rsp_fifo_icache (push)
+    // - r_vci_rsp_fifo_dcache (push)
+    // - r_vci_rsp_data_error (set)
+    // - r_vci_rsp_ins_error (set)
+    // - r_vci_rsp_cpt
+    // 
+    // As we support several simultaneous transactions, this FSM uses
+    // the VCI TRDID field to identify the transactions.
+    //
+    // VCI vormat:
+    // This component Rcheks the response packet length and accepts only
+    // single word packets for write response packets. 
+    //
+    // Error handling:
+    // This FSM analyzes the VCI error code and signals directly the Write Bus Error. 
+    // In case of Read Data Error, the VCI_RSP FSM sets the r_vci_rsp_data_error 
+    // flip_flop and the error is signaled by the DCACHE FSM.  
+    // In case of Instruction Error, the VCI_RSP FSM sets the r_vci_rsp_ins_error 
+    // flip_flop and the error is signaled by the DCACHE FSM.  
+    // In case of Cleanup Error, the simulation stops with an error message...
+    /////////////////////////////////////////////////////////////////////////////////
+
+    switch ( r_vci_rsp_fsm.read() ) 
+    {
+        //////////////
+        case RSP_IDLE:
+        {
+            if( p_vci_ini_d.rspval.read() )
+            {
+                r_vci_rsp_cpt = 0;
+
+                if ( (p_vci_ini_d.rtrdid.read()>>(vci_param::T-1)) != 0 )
+                {
+                    r_vci_rsp_fsm = RSP_DATA_WRITE;
+                }
+                else if ( p_vci_ini_d.rtrdid.read() == TYPE_INS_MISS )
+                {
+                    r_vci_rsp_fsm = RSP_INS_MISS;
+                }
+                else if ( p_vci_ini_d.rtrdid.read() == TYPE_INS_UNC )
+                {
+                    r_vci_rsp_fsm = RSP_INS_UNC;
+                }
+                else if ( p_vci_ini_d.rtrdid.read() == TYPE_DATA_MISS )
+                {
+                    r_vci_rsp_fsm = RSP_DATA_MISS;
+                }
+                else if ( p_vci_ini_d.rtrdid.read() == TYPE_DATA_UNC )
+                {
+                    r_vci_rsp_fsm = RSP_DATA_UNC;
+                }
+                else
+                {
+                    assert(false and "Unexpected response");
+                }
+            }
+            break;
+        }
+        //////////////////
+        case RSP_INS_MISS:
+        {        
+            if ( p_vci_ini_d.rspval.read() )
+            {
+                if ( (p_vci_ini_d.rerror.read()&0x1) != 0 )  // error reported
+                {
+                    r_vci_rsp_ins_error = true;
+                    if ( p_vci_ini_d.reop.read() ) r_vci_rsp_fsm = RSP_IDLE;
+                }
+                else                                        // no error reported
+                {
+                    if ( r_vci_rsp_fifo_icache.wok() )
+                    {
+                        assert( (r_vci_rsp_cpt.read() < m_cache_words) and
+                        "The VCI response packet for instruction miss is too long" );
+
+                        r_vci_rsp_cpt                 = r_vci_rsp_cpt.read() + 1;
+                        vci_rsp_fifo_icache_put       = true,
+                        vci_rsp_fifo_icache_data      = p_vci_ini_d.rdata.read();
+                        if ( p_vci_ini_d.reop.read() ) 
+                        {
+                            assert( (r_vci_rsp_cpt.read() == m_cache_words - 1) and 
+                            "The VCI response packet for instruction miss is too short");
+
+                            r_vci_rsp_fsm    = RSP_IDLE;
+                        }
+                    }
+                }
+            }
+            break;
+        }
+        /////////////////
+        case RSP_INS_UNC:
+        {
+            if (p_vci_ini_d.rspval.read() )
+            {
+                assert( p_vci_ini_d.reop.read() and
+                "illegal VCI response packet for uncacheable instruction");
+
+                if ( (p_vci_ini_d.rerror.read()&0x1) != 0 )  // error reported
+                {
+                    r_vci_rsp_ins_error = true;
+                    r_vci_rsp_fsm = RSP_IDLE;
+                }
+                else                                         // no error reported
+                {   
+                    if ( r_vci_rsp_fifo_icache.wok())
+                    {
+                        vci_rsp_fifo_icache_put       = true;
+                        vci_rsp_fifo_icache_data      = p_vci_ini_d.rdata.read();
+                        r_vci_rsp_fsm = RSP_IDLE;
+                    }
+                }
+            }
+            break;
+        }
+        ///////////////////
+        case RSP_DATA_MISS:
+        {
+            if ( p_vci_ini_d.rspval.read() )
+            {
+                if ( (p_vci_ini_d.rerror.read()&0x1) != 0 )  // error reported
+                {
+                    r_vci_rsp_data_error = true;
+                    if ( p_vci_ini_d.reop.read() ) r_vci_rsp_fsm = RSP_IDLE;
+                }
+                else                                        // no error reported
+                {
+                    if ( r_vci_rsp_fifo_dcache.wok() )
+                    {
+                        assert( (r_vci_rsp_cpt.read() < m_cache_words) and
+                        "The VCI response packet for data miss is too long");
+
+                        r_vci_rsp_cpt                 = r_vci_rsp_cpt.read() + 1;
+                        vci_rsp_fifo_dcache_put       = true,
+                        vci_rsp_fifo_dcache_data      = p_vci_ini_d.rdata.read();
+                        if ( p_vci_ini_d.reop.read() ) 
+                        {
+                            assert( (r_vci_rsp_cpt.read() == m_cache_words - 1) and
+                            "The VCI response packet for data miss is too short");
+
+                            r_vci_rsp_fsm     = RSP_IDLE;
+                        }
+                    }
+                }
+            }
+            break;
+        }
+        //////////////////
+        case RSP_DATA_UNC:
+        {
+            if (p_vci_ini_d.rspval.read() )
+            {
+                assert( p_vci_ini_d.reop.read() and
+                "illegal VCI response packet for uncacheable read data");
+
+                if ( (p_vci_ini_d.rerror.read()&0x1) != 0 )  // error reported
+                {
+                    r_vci_rsp_data_error = true;
+                    r_vci_rsp_fsm = RSP_IDLE;
+                }
+                else                                         // no error reported
+                {   
+                    if ( r_vci_rsp_fifo_dcache.wok())
+                    {
+                        vci_rsp_fifo_dcache_put       = true;
+                        vci_rsp_fifo_dcache_data      = p_vci_ini_d.rdata.read();
+                        r_vci_rsp_fsm = RSP_IDLE;
+                    }
+                }
+            }
+            break;
+        }
+        ////////////////////
+        case RSP_DATA_WRITE:
+        {
+            if (p_vci_ini_d.rspval.read())
+            {
+                assert( p_vci_ini_d.reop.read() and
+                "a VCI response packet must contain one flit for a write transaction");
+
+                r_vci_rsp_fsm = RSP_IDLE;
+                uint32_t wbuf_index = p_vci_ini_d.rtrdid.read() - (1<<(vci_param::T-1));
+                bool     cacheable  = r_wbuf->completed(wbuf_index);
+                if ( not cacheable ) r_dcache_pending_unc_write = false;
+                if ( (p_vci_ini_d.rerror.read()&0x1) != 0 ) r_iss->setWriteBerr();
+            }
+            break;
+        }
+    } // end switch r_vci_rsp_fsm
+
+    // FIFO_RSP update
+
+    r_vci_rsp_fifo_icache.update(vci_rsp_fifo_icache_get, 
+                                 vci_rsp_fifo_icache_put, 
+                                 vci_rsp_fifo_icache_data);
+      
+    r_vci_rsp_fifo_dcache.update(vci_rsp_fifo_dcache_get, 
+                                 vci_rsp_fifo_dcache_put, 
+                                 vci_rsp_fifo_dcache_data);
+
+} // end transition()
+
+//////////////////////////
+tmpl(void)::genMoore()
+//////////////////////////
+{
+    ////////////////////////////////////////////////////////////////
+    // VCI initiator command on the coherence network (cleanup)
+
+    vci_addr_t  address;
+
+    if ( r_cleanup_fsm.read() == CLEANUP_DATA_GO )
+        address = (vci_addr_t)r_dcache_cleanup_line.read()<<m_cache_words_shift;
+    else if ( r_cleanup_fsm.read() == CLEANUP_INS_GO )
+        address = (vci_addr_t)r_icache_cleanup_line.read()<<m_cache_words_shift;
+    else
+        address = 0;
+
+    p_vci_ini_c.cmdval  = ((r_cleanup_fsm.read() == CLEANUP_DATA_GO) or
+                           (r_cleanup_fsm.read() == CLEANUP_INS_GO) );
+    p_vci_ini_c.address = address;
+    p_vci_ini_c.wdata   = 0;
+    p_vci_ini_c.be      = 0xF;
+    p_vci_ini_c.plen    = 4;
+    p_vci_ini_c.cmd     = vci_param::CMD_WRITE;
+    p_vci_ini_c.trdid   = r_cleanup_trdid.read();
+    p_vci_ini_c.pktid   = 0;
+    p_vci_ini_c.srcid   = m_srcid_c;
+    p_vci_ini_c.cons    = false;
+    p_vci_ini_c.wrap    = false;
+    p_vci_ini_c.contig  = false;
+    p_vci_ini_c.clen    = 0;
+    p_vci_ini_c.cfixed  = false;
+    p_vci_ini_c.eop     = true;
+
+    /////////////////////////////////////////////////////////////////
+    // VCI initiator response on the coherence network (cleanup)
+
+    p_vci_ini_c.rspack  = true;
+
+    //////////////////////////////////////////////
+    // VCI initiator command on the direct network
+    switch (r_vci_cmd_fsm.read() ) 
+    {
+        case CMD_IDLE:
+        {
+            p_vci_ini_d.cmdval  = false;
+            p_vci_ini_d.address = 0;
+            p_vci_ini_d.wdata   = 0;
+            p_vci_ini_d.be      = 0;
+            p_vci_ini_d.plen    = 0;
+            p_vci_ini_d.cmd     = vci_param::CMD_NOP;
+            p_vci_ini_d.trdid   = 0;
+            p_vci_ini_d.pktid   = 0;
+            p_vci_ini_d.srcid   = 0;
+            p_vci_ini_d.cons    = false;
+            p_vci_ini_d.wrap    = false;
+            p_vci_ini_d.contig  = false;
+            p_vci_ini_d.clen    = 0;
+            p_vci_ini_d.cfixed  = false;
+            p_vci_ini_d.eop     = false;
+            break;
+        }
+        case CMD_DATA_UNC:
+        {
+            p_vci_ini_d.cmdval  = true;
+            p_vci_ini_d.address = (vci_addr_t) r_dcache_addr_save.read() & ~0x3;
+            p_vci_ini_d.wdata   = 0;
+            p_vci_ini_d.be      = r_dcache_be_save.read();
+            p_vci_ini_d.cmd     = vci_param::CMD_READ;
+            p_vci_ini_d.plen    = 4;
+            p_vci_ini_d.trdid   = TYPE_DATA_UNC; 
+            p_vci_ini_d.pktid   = 0;
+            p_vci_ini_d.srcid   = m_srcid_d;
+            p_vci_ini_d.cons    = false;
+            p_vci_ini_d.wrap    = false;
+            p_vci_ini_d.contig  = true;
+            p_vci_ini_d.clen    = 0;
+            p_vci_ini_d.cfixed  = false;
+            p_vci_ini_d.eop     = true;
+            break;
+        }
+        case CMD_DATA_SC:
+        {
+            p_vci_ini_d.cmdval  = true;
+            p_vci_ini_d.address = (vci_addr_t)r_dcache_addr_save.read() & ~0x3;
+            if ( r_vci_cmd_cpt.read() == 0 ) p_vci_ini_d.wdata = r_dcache_ll_data.read();
+            else                             p_vci_ini_d.wdata = r_dcache_wdata_save.read();
+            p_vci_ini_d.be      = 0xF;
+            p_vci_ini_d.cmd     = vci_param::CMD_STORE_COND;
+            p_vci_ini_d.plen    = 8;
+            p_vci_ini_d.trdid   = TYPE_DATA_UNC; 
+            p_vci_ini_d.pktid   = 0;
+            p_vci_ini_d.srcid   = m_srcid_d;
+            p_vci_ini_d.cons    = true;
+            p_vci_ini_d.wrap    = false;
+            p_vci_ini_d.contig  = false;
+            p_vci_ini_d.clen    = 0;
+            p_vci_ini_d.cfixed  = false;
+            p_vci_ini_d.eop     = (r_vci_cmd_cpt.read() == 1);
+            break;
+        }
+        case CMD_DATA_WRITE:
+        {
+            p_vci_ini_d.cmdval  = true;
+            p_vci_ini_d.address = (vci_addr_t)r_wbuf->getAddress(r_vci_cmd_cpt.read())&~0x3;
+            p_vci_ini_d.wdata   = r_wbuf->getData(r_vci_cmd_cpt.read());
+            p_vci_ini_d.be      = r_wbuf->getBe(r_vci_cmd_cpt.read());
+            p_vci_ini_d.plen    = (r_vci_cmd_max - r_vci_cmd_min + 1)<<2;
+            p_vci_ini_d.cmd     = vci_param::CMD_WRITE;
+            p_vci_ini_d.trdid   = r_wbuf->getIndex() + (1<<(vci_param::T-1));
+            p_vci_ini_d.pktid   = 0;
+            p_vci_ini_d.srcid   = m_srcid_d;
+            p_vci_ini_d.cons    = false;
+            p_vci_ini_d.wrap    = false;
+            p_vci_ini_d.contig  = true;
+            p_vci_ini_d.clen    = 0;
+            p_vci_ini_d.cfixed  = false;
+            p_vci_ini_d.eop     = (r_vci_cmd_cpt.read() == r_vci_cmd_max.read());
+            break;
+        }
+        case CMD_DATA_MISS:
+        {
+            p_vci_ini_d.cmdval  = true;
+            p_vci_ini_d.address = (vci_addr_t)r_dcache_addr_save.read() & (vci_addr_t)m_cache_yzmask;
+            p_vci_ini_d.be      = 0xF;
+            p_vci_ini_d.plen    = m_cache_words << 2;
+            p_vci_ini_d.cmd     = vci_param::CMD_READ;
+            p_vci_ini_d.trdid   = TYPE_DATA_MISS; 
+            p_vci_ini_d.pktid   = 0;
+            p_vci_ini_d.srcid   = m_srcid_d;
+            p_vci_ini_d.cons    = false;
+            p_vci_ini_d.wrap    = false;
+            p_vci_ini_d.contig  = true;
+            p_vci_ini_d.clen    = 0;
+            p_vci_ini_d.cfixed  = false;
+            p_vci_ini_d.eop     = true;
+            break;
+        }
+        case CMD_INS_MISS:
+        {
+            p_vci_ini_d.cmdval  = true;
+            p_vci_ini_d.address = (vci_addr_t)r_icache_addr_save.read() & (vci_addr_t)m_cache_yzmask;
+            p_vci_ini_d.be      = 0xF;
+            p_vci_ini_d.plen    = m_cache_words << 2;
+            p_vci_ini_d.cmd     = vci_param::CMD_READ;
+            p_vci_ini_d.trdid   = TYPE_INS_MISS; 
+            p_vci_ini_d.pktid   = 0;
+            p_vci_ini_d.srcid   = m_srcid_d;
+            p_vci_ini_d.cons    = false;
+            p_vci_ini_d.wrap    = false;
+            p_vci_ini_d.contig  = true;
+            p_vci_ini_d.clen    = 0;
+            p_vci_ini_d.cfixed  = false;
+            p_vci_ini_d.eop     = true;
+            break;
+        }
+        case CMD_INS_UNC:
+        {
+            p_vci_ini_d.cmdval  = true;
+            p_vci_ini_d.address = (vci_addr_t)r_icache_addr_save.read() & ~0x3;
+            p_vci_ini_d.be      = 0xF;
+            p_vci_ini_d.plen    = 4;
+            p_vci_ini_d.cmd     = vci_param::CMD_READ;
+            p_vci_ini_d.trdid   = TYPE_INS_UNC;  
+            p_vci_ini_d.pktid   = 0;
+            p_vci_ini_d.srcid   = m_srcid_d;
+            p_vci_ini_d.cons    = false;
+            p_vci_ini_d.wrap    = false;
+            p_vci_ini_d.contig  = true;
+            p_vci_ini_d.clen    = 0;
+            p_vci_ini_d.cfixed  = false;
+            p_vci_ini_d.eop     = true;
+            break;
+        }
+    } // end switch r_vci_cmd_fsm
+
+    ///////////////////////////////////////////////
+    // VCI initiator response on the direct network
+    switch (r_vci_rsp_fsm.read() ) 
+    {
+        case RSP_DATA_WRITE : p_vci_ini_d.rspack = true; break;
+        case RSP_INS_MISS   :
+        case RSP_INS_UNC    : p_vci_ini_d.rspack = r_vci_rsp_fifo_icache.wok(); break;
+        case RSP_DATA_MISS  :
+        case RSP_DATA_UNC   :
+        case RSP_DATA_SC    : p_vci_ini_d.rspack = r_vci_rsp_fifo_dcache.wok(); break;
+        case RSP_IDLE       :
+        default             : p_vci_ini_d.rspack = false; break;
+    } // end switch r_vci_rsp_fsm
+
+    ////////////////////////////////////////////////////////////
+    // VCI target command and  response on the coherence network
+    switch ( r_tgt_fsm.read() ) 
+    {
+        case TGT_IDLE:
+        case TGT_UPDT_WORD:
+        case TGT_UPDT_DATA:
+        {
+            p_vci_tgt_c.cmdack  = true;
+            p_vci_tgt_c.rspval  = false;
+            break;
+        }
+        case TGT_RSP_BROADCAST:
+        {
+            p_vci_tgt_c.cmdack  = false;
+            p_vci_tgt_c.rspval  = (not r_tgt_icache_req.read() and not r_tgt_dcache_req.read()) 
+                                  and (r_tgt_icache_rsp.read() or r_tgt_dcache_rsp.read());
+            p_vci_tgt_c.rsrcid  = r_tgt_srcid.read();
+            p_vci_tgt_c.rpktid  = r_tgt_pktid.read();
+            p_vci_tgt_c.rtrdid  = r_tgt_trdid.read();
+            p_vci_tgt_c.rdata   = 0;
+            p_vci_tgt_c.rerror  = 0; 
+            p_vci_tgt_c.reop    = true;
+            break;
+        }
+        case TGT_RSP_ICACHE:
+        {
+            p_vci_tgt_c.cmdack  = false;
+            p_vci_tgt_c.rspval  = not r_tgt_icache_req.read() and r_tgt_icache_rsp.read();
+            p_vci_tgt_c.rsrcid  = r_tgt_srcid.read();
+            p_vci_tgt_c.rpktid  = r_tgt_pktid.read();
+            p_vci_tgt_c.rtrdid  = r_tgt_trdid.read();
+            p_vci_tgt_c.rdata   = 0;
+            p_vci_tgt_c.rerror  = 0; 
+            p_vci_tgt_c.reop    = true;
+            break;
+        }
+        case TGT_RSP_DCACHE:
+        {
+            p_vci_tgt_c.cmdack  = false;
+            p_vci_tgt_c.rspval  = not r_tgt_dcache_req.read() and r_tgt_dcache_rsp.read();
+            p_vci_tgt_c.rsrcid  = r_tgt_srcid.read();
+            p_vci_tgt_c.rpktid  = r_tgt_pktid.read();
+            p_vci_tgt_c.rtrdid  = r_tgt_trdid.read();
+            p_vci_tgt_c.rdata   = 0;
+            p_vci_tgt_c.rerror  = 0;
+            p_vci_tgt_c.reop    = true;
+            break;
+        }
+        case TGT_REQ_BROADCAST:
+        case TGT_REQ_ICACHE:
+        case TGT_REQ_DCACHE:
+        {
+            p_vci_tgt_c.cmdack  = false;
+            p_vci_tgt_c.rspval  = false;
+            break;
+        }
+    } // end switch TGT_FSM
+} // end genMoore()
+  
+
+}} // end namespace
+
+// Local Variables:
+// tab-width: 4
+// c-basic-offset: 4
+// c-file-offsets:((innamespace . 0)(inline-open . 0))
+// indent-tabs-mode: nil
+// End:
+
+// vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4
Index: branches/v4/modules/vci_dma_tsar/caba/metadata/vci_dma_tsar.sd
===================================================================
--- branches/v4/modules/vci_dma_tsar/caba/metadata/vci_dma_tsar.sd	(revision 371)
+++ branches/v4/modules/vci_dma_tsar/caba/metadata/vci_dma_tsar.sd	(revision 371)
@@ -0,0 +1,43 @@
+
+# -*- python -*-
+
+__id__ = "$Id$"
+__version__ = "$Revision$"
+
+Module('caba:vci_dma_tsar',
+	classname = 'soclib::caba::VciDmaTsar',
+	   tmpl_parameters = [
+	parameter.Module('vci_param',  default = 'caba:vci_param'),
+	],
+	header_files = ['../source/include/vci_dma_tsar.h',
+					],
+    interface_files = [
+					'../../include/soclib/dma_tsar.h',
+					],
+	implementation_files = ['../source/src/vci_dma_tsar.cpp',],
+			  ports = [
+	Port('caba:vci_target', 'p_vci_target'),
+	Port('caba:vci_initiator', 'p_vci_initiator'),
+	Port('caba:bit_out', 'p_irq'),
+	Port('caba:bit_in', 'p_resetn', auto = 'resetn'),
+	Port('caba:clock_in', 'p_clk', auto = 'clock'),
+	],
+	uses = [
+		Uses('caba:base_module'),
+		Uses('caba:vci_target_fsm', default_target = 'true', support_llsc = 'false'),
+		Uses('caba:vci_initiator_simple_read_req'),
+		Uses('caba:vci_initiator_simple_write_req'),
+		Uses('caba:vci_initiator_fsm'),
+		],
+	instance_parameters = [
+        parameter.Module('mt', typename = 'common:mapping_table', auto = 'env:mapping_table'),
+		parameter.IntTab('srcid'),
+		parameter.IntTab('tgtid'),
+        parameter.Int('burst_size'),
+	],
+	   extensions = [
+	'dsx:addressable=tgtid',
+	'dsx:max_segments=1',
+	'dsx:get_ident=tgtid:p_vci_target:mt,srcid:p_vci_initiator:mt',
+   ],
+)
Index: branches/v4/modules/vci_dma_tsar/caba/source/include/vci_dma_tsar.h
===================================================================
--- branches/v4/modules/vci_dma_tsar/caba/source/include/vci_dma_tsar.h	(revision 371)
+++ branches/v4/modules/vci_dma_tsar/caba/source/include/vci_dma_tsar.h	(revision 371)
@@ -0,0 +1,106 @@
+/* -*- c++ -*-
+ *
+ * SOCLIB_LGPL_HEADER_BEGIN
+ * 
+ * This file is part of SoCLib, GNU LGPLv2.1.
+ * 
+ * SoCLib is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU Lesser General Public License as published
+ * by the Free Software Foundation; version 2.1 of the License.
+ * 
+ * SoCLib is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * Lesser General Public License for more details.
+ * 
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with SoCLib; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301 USA
+ * 
+ * SOCLIB_LGPL_HEADER_END
+ *
+ * Copyright (c) UPMC, Lip6, Asim
+ *         Nicolas Pouillon <nipo@ssji.net>, 2007
+ *
+ * Maintainers: nipo
+ */
+#ifndef SOCLIB_VCI_DMA_TSAR_H
+#define SOCLIB_VCI_DMA_TSAR_H
+
+#include <stdint.h>
+#include <systemc>
+#include "vci_target_fsm.h"
+#include "vci_initiator_fsm.h"
+#include "caba_base_module.h"
+#include "mapping_table.h"
+
+namespace soclib {
+namespace caba {
+
+using namespace sc_core;
+
+template<typename vci_param>
+class VciDmaTsar
+	: public caba::BaseModule
+{
+private:
+    soclib::caba::VciTargetFsm<vci_param, true> m_vci_target_fsm;
+    soclib::caba::VciInitiatorFsm<vci_param> m_vci_init_fsm;
+    typedef typename soclib::caba::VciInitiatorReq<vci_param> req_t;
+
+    bool on_write(int seg, typename vci_param::addr_t addr, typename vci_param::data_t data, int be);
+    bool on_read(int seg, typename vci_param::addr_t addr, typename vci_param::data_t &data);
+    void read_done( req_t *req );
+    void write_finish( req_t *req );
+    void transition();
+    void genMoore();
+
+	uint32_t m_src;
+	uint32_t m_dst;
+	uint32_t m_len;
+	uint32_t m_offset;
+    uint32_t m_offset_buffer;
+    bool m_partial;
+    bool m_must_finish;
+	bool m_irq_enabled;
+	bool r_irq;
+
+	std::vector<uint8_t> m_data;
+
+	bool m_handling;
+
+	void next_req();
+	void ended();
+
+protected:
+    SC_HAS_PROCESS(VciDmaTsar);
+
+public:
+    sc_in<bool> p_clk;
+    sc_in<bool> p_resetn;
+    soclib::caba::VciTarget<vci_param> p_vci_target;
+    soclib::caba::VciInitiator<vci_param> p_vci_initiator;
+    sc_out<bool> p_irq;
+
+	VciDmaTsar(
+		sc_module_name name,
+		const soclib::common::MappingTable &mt,
+		const soclib::common::IntTab &srcid,
+		const soclib::common::IntTab &tgtid,
+		const size_t burst_size );
+};
+
+}}
+
+#endif /* SOCLIB_VCI_DMA_TSAR_H */
+
+// Local Variables:
+// tab-width: 4
+// c-basic-offset: 4
+// c-file-offsets:((innamespace . 0)(inline-open . 0))
+// indent-tabs-mode: nil
+// End:
+
+// vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4
+
Index: branches/v4/modules/vci_dma_tsar/caba/source/src/vci_dma_tsar.cpp
===================================================================
--- branches/v4/modules/vci_dma_tsar/caba/source/src/vci_dma_tsar.cpp	(revision 371)
+++ branches/v4/modules/vci_dma_tsar/caba/source/src/vci_dma_tsar.cpp	(revision 371)
@@ -0,0 +1,267 @@
+/* -*- c++ -*-
+ *
+ * SOCLIB_LGPL_HEADER_BEGIN
+ * 
+ * This file is part of SoCLib, GNU LGPLv2.1.
+ * 
+ * SoCLib is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU Lesser General Public License as published
+ * by the Free Software Foundation; version 2.1 of the License.
+ * 
+ * SoCLib is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * Lesser General Public License for more details.
+ * 
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with SoCLib; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301 USA
+ * 
+ * SOCLIB_LGPL_HEADER_END
+ *
+ * Copyright (c) UPMC, Lip6, Asim
+ *         Nicolas Pouillon <nipo@ssji.net>, 2007
+ */
+
+#include <stdint.h>
+#include "register.h"
+#include "../include/vci_dma_tsar.h"
+#include "dma_tsar.h"
+
+namespace soclib { namespace caba {
+
+#define tmpl(t) template<typename vci_param> t VciDmaTsar<vci_param>
+
+tmpl(bool)::on_write(int seg, typename vci_param::addr_t addr, typename vci_param::data_t data, int be)
+{
+    int cell = (int)addr / vci_param::B;
+
+	switch ((enum SoclibDmaRegisters)cell) {
+	case DMA_SRC:
+		m_src = data;
+		return true;
+    case DMA_DST:
+		m_dst = data;
+		return true;
+    case DMA_LEN:
+		m_len = data;
+		return true;
+    case DMA_RESET:
+        m_must_finish = true;
+        m_irq_enabled = false;
+		r_irq = false;
+        return true;
+    case DMA_IRQ_DISABLED:
+		m_irq_enabled = !data;
+		return true;
+	};
+	return false;
+}
+
+tmpl(void)::ended()
+{
+	if ( m_irq_enabled )
+		r_irq = true;
+	m_len = 0;
+    m_must_finish = false;
+	m_handling = false;
+}
+
+tmpl(bool)::on_read(int seg, typename vci_param::addr_t addr, typename vci_param::data_t &data)
+{
+    int cell = (int)addr / vci_param::B;
+
+	switch ((enum SoclibDmaRegisters)cell) {
+	case DMA_SRC:
+		data = m_src;
+		return true;
+    case DMA_DST:
+		data = m_dst;
+		return true;
+	case DMA_LEN:
+		data = m_len;
+		return true;
+    default:
+        return false;
+	}
+	return false;
+}
+
+tmpl(void)::read_done( req_t *req )
+{
+	if ( !req->failed() && !m_must_finish ) {
+		ssize_t remaining = (ssize_t)m_len-(size_t)m_offset;
+		ssize_t burst = m_offset_buffer;
+
+        if ( ( ( 0 < ( remaining-(size_t)m_offset_buffer ) ) 
+            && ( ( remaining-(size_t)m_offset_buffer ) < m_data.size()) ) && m_partial ){
+            VciInitSimpleReadReq<vci_param> *new_req =
+                new VciInitSimpleReadReq<vci_param>(
+                        &m_data[m_offset_buffer], m_src+m_offset+m_offset_buffer, 4 );
+            m_offset_buffer+=4;
+            new_req->setDone( this, ON_T(read_done) );
+            m_vci_init_fsm.doReq( new_req );
+            delete req;
+            return;
+        }
+        if ( (( m_src+m_offset+m_offset_buffer ) & ( m_data.size()-1 )) && m_partial ){
+            VciInitSimpleReadReq<vci_param> *new_req =
+                new VciInitSimpleReadReq<vci_param>(
+                        &m_data[m_offset_buffer], m_src+m_offset+m_offset_buffer, 4 );
+            m_offset_buffer+=4;
+            new_req->setDone( this, ON_T(read_done) );
+            m_vci_init_fsm.doReq( new_req );
+            delete req;
+            return;
+        }
+        m_partial = false;
+        if( (( m_dst+m_offset ) & ~( m_data.size()-1 )) !=
+            (( m_dst+m_offset+m_offset_buffer-4 ) & ~( m_data.size()-1 )) ){
+            burst = (((m_dst+m_offset) & ~( m_data.size()-1))+m_data.size()) - (m_dst+m_offset);
+            m_partial = true;
+        }
+		VciInitSimpleWriteReq<vci_param> *new_req =
+			new VciInitSimpleWriteReq<vci_param>( m_dst+m_offset, &m_data[0], burst );
+		new_req->setDone( this, ON_T(write_finish) );
+		m_vci_init_fsm.doReq( new_req );
+	} else {
+		ended();
+	}
+	delete req;
+}
+
+tmpl(void)::write_finish( req_t *req )
+{
+    ssize_t burst = 0;
+    uint32_t offset = 0;
+    if( m_partial ){
+        burst = m_dst + m_offset + m_offset_buffer - ((m_dst+m_offset+m_offset_buffer) & ~( m_data.size()-1));
+        offset = m_offset_buffer - burst;
+    } else {
+	    m_offset += m_offset_buffer;
+    }
+	if ( !req->failed() && !m_must_finish ){
+        if(m_partial){
+            VciInitSimpleWriteReq<vci_param> *new_req =
+                new VciInitSimpleWriteReq<vci_param>( m_dst+m_offset+offset, &m_data[offset], burst );
+            new_req->setDone( this, ON_T(write_finish) );
+            m_partial = false;
+            m_vci_init_fsm.doReq( new_req );
+            delete req;
+            return;
+        }
+		next_req();
+    }
+	else {
+		ended();
+	}
+	delete req;
+}
+
+tmpl(void)::next_req()
+{
+	ssize_t remaining = (ssize_t)m_len-(size_t)m_offset;
+	if ( remaining <= 0 ) {
+		ended();
+		return;
+	}
+
+	ssize_t burst = m_data.size();
+    m_partial = false;
+	if ( remaining < burst ){
+		burst = 4;
+        m_partial = true;
+    }
+    if ( ( m_src+m_offset ) & ( m_data.size()-1 ) ){
+        burst = 4;
+        m_partial = true;
+    }
+
+    m_offset_buffer = burst;
+	VciInitSimpleReadReq<vci_param> *req =
+		new VciInitSimpleReadReq<vci_param>(
+			&m_data[0], m_src+m_offset, burst );
+	req->setDone( this, ON_T(read_done) );
+	m_vci_init_fsm.doReq( req );
+}
+
+tmpl(void)::transition()
+{
+	if (!p_resetn) {
+		m_vci_target_fsm.reset();
+		m_vci_init_fsm.reset();
+		r_irq = false;
+		m_irq_enabled = false;
+		m_len = 0;
+        m_offset_buffer = 0;
+		m_handling = false;
+        m_must_finish = false;
+		return;
+	}
+
+
+	if ( m_len && !m_handling ) {
+		m_handling = true;
+		m_offset = 0;
+
+		next_req();
+	}
+    
+    if( !m_handling )
+        m_must_finish = false;
+
+	m_vci_target_fsm.transition();
+	m_vci_init_fsm.transition();
+}
+
+tmpl(void)::genMoore()
+{
+	m_vci_target_fsm.genMoore();
+	m_vci_init_fsm.genMoore();
+
+	p_irq = r_irq && m_irq_enabled;
+}
+
+tmpl(/**/)::VciDmaTsar(
+    sc_module_name name,
+    const MappingTable &mt,
+    const IntTab &srcid,
+    const IntTab &tgtid,
+	const size_t burst_size )
+	: caba::BaseModule(name),
+	  m_vci_target_fsm(p_vci_target, mt.getSegmentList(tgtid)),
+	  m_vci_init_fsm(p_vci_initiator, mt.indexForId(srcid)),
+	  m_len(0),
+	  m_data(burst_size, (uint8_t)0),
+      p_clk("clk"),
+      p_resetn("resetn"),
+      p_vci_target("vci_target"),
+      p_vci_initiator("vci_initiator"),
+      p_irq("irq")
+{
+	m_vci_target_fsm.on_read_write(on_read, on_write);
+    
+    assert(burst_size && "Useless DMA with no buffer");
+    assert(burst_size < (1<<vci_param::K) && "I will be unable to create requests that big");
+
+	SC_METHOD(transition);
+	dont_initialize();
+	sensitive << p_clk.pos();
+
+	SC_METHOD(genMoore);
+	dont_initialize();
+	sensitive << p_clk.neg();
+}
+
+}}
+
+// Local Variables:
+// tab-width: 4
+// c-basic-offset: 4
+// c-file-offsets:((innamespace . 0)(inline-open . 0))
+// indent-tabs-mode: nil
+// End:
+
+// vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4
+
Index: branches/v4/modules/vci_dma_tsar/include/soclib/dma_tsar.h
===================================================================
--- branches/v4/modules/vci_dma_tsar/include/soclib/dma_tsar.h	(revision 371)
+++ branches/v4/modules/vci_dma_tsar/include/soclib/dma_tsar.h	(revision 371)
@@ -0,0 +1,49 @@
+/*
+ * SOCLIB_LGPL_HEADER_BEGIN
+ * 
+ * This file is part of SoCLib, GNU LGPLv2.1.
+ * 
+ * SoCLib is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU Lesser General Public License as published
+ * by the Free Software Foundation; version 2.1 of the License.
+ * 
+ * SoCLib is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * Lesser General Public License for more details.
+ * 
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with SoCLib; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301 USA
+ * 
+ * SOCLIB_LGPL_HEADER_END
+ *
+ * Copyright (c) UPMC, Lip6, Asim
+ *         Nicolas Pouillon <nipo@ssji.net>, 2007
+ *         Eric Guthmuller  <eric.guthmuller@polytechnique.edu>, 2009
+ *
+ * Maintainers: nipo eric.guthmuller@polytechnique.edu
+ */
+#ifndef DMA_REGS_TSAR_H
+#define DMA_REGS_TSAR_H
+
+enum SoclibDmaRegisters {
+    DMA_SRC,
+    DMA_DST,
+    DMA_LEN,
+    DMA_RESET,
+    DMA_IRQ_DISABLED,
+};
+
+#endif /* DMA_REGS_TSAR_H */
+
+// Local Variables:
+// tab-width: 4
+// c-basic-offset: 4
+// c-file-offsets:((innamespace . 0)(inline-open . 0))
+// indent-tabs-mode: nil
+// End:
+
+// vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4
+
Index: branches/v4/modules/vci_dma_tsar_v2/caba/metadata/vci_dma_tsar_v2.sd
===================================================================
--- branches/v4/modules/vci_dma_tsar_v2/caba/metadata/vci_dma_tsar_v2.sd	(revision 371)
+++ branches/v4/modules/vci_dma_tsar_v2/caba/metadata/vci_dma_tsar_v2.sd	(revision 371)
@@ -0,0 +1,43 @@
+
+# -*- python -*-
+
+__id__ = "$Id$"
+__version__ = "$Revision$"
+
+Module('caba:vci_dma_tsar_v2',
+	classname = 'soclib::caba::VciDmaTsarV2',
+	   tmpl_parameters = [
+	parameter.Module('vci_param',  default = 'caba:vci_param'),
+	],
+	header_files = ['../source/include/vci_dma_tsar_v2.h',
+					],
+    interface_files = [
+					'../../include/soclib/dma_tsar_v2.h',
+					],
+	implementation_files = ['../source/src/vci_dma_tsar_v2.cpp',],
+			  ports = [
+	Port('caba:vci_target', 'p_vci_target'),
+	Port('caba:vci_initiator', 'p_vci_initiator'),
+	Port('caba:bit_out', 'p_irq'),
+	Port('caba:bit_in', 'p_resetn', auto = 'resetn'),
+	Port('caba:clock_in', 'p_clk', auto = 'clock'),
+	],
+	uses = [
+		Uses('caba:base_module'),
+		Uses('caba:vci_target_fsm', default_target = 'true', support_llsc = 'false'),
+		Uses('caba:vci_initiator_simple_read_req'),
+		Uses('caba:vci_initiator_simple_write_req'),
+		Uses('caba:vci_initiator_fsm'),
+		],
+	instance_parameters = [
+        parameter.Module('mt', typename = 'common:mapping_table', auto = 'env:mapping_table'),
+		parameter.IntTab('srcid'),
+		parameter.IntTab('tgtid'),
+        parameter.Int('burst_size'),
+	],
+	   extensions = [
+	'dsx:addressable=tgtid',
+	'dsx:max_segments=1',
+	'dsx:get_ident=tgtid:p_vci_target:mt,srcid:p_vci_initiator:mt',
+   ],
+)
Index: branches/v4/modules/vci_dma_tsar_v2/caba/source/include/vci_dma_tsar_v2.h
===================================================================
--- branches/v4/modules/vci_dma_tsar_v2/caba/source/include/vci_dma_tsar_v2.h	(revision 371)
+++ branches/v4/modules/vci_dma_tsar_v2/caba/source/include/vci_dma_tsar_v2.h	(revision 371)
@@ -0,0 +1,106 @@
+/* -*- c++ -*-
+ *
+ * SOCLIB_LGPL_HEADER_BEGIN
+ * 
+ * This file is part of SoCLib, GNU LGPLv2.1.
+ * 
+ * SoCLib is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU Lesser General Public License as published
+ * by the Free Software Foundation; version 2.1 of the License.
+ * 
+ * SoCLib is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * Lesser General Public License for more details.
+ * 
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with SoCLib; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301 USA
+ * 
+ * SOCLIB_LGPL_HEADER_END
+ *
+ * Copyright (c) UPMC, Lip6, Asim
+ *         Nicolas Pouillon <nipo@ssji.net>, 2007
+ *
+ * Maintainers: nipo
+ */
+#ifndef SOCLIB_VCI_DMA_TSAR_V2_H
+#define SOCLIB_VCI_DMA_TSAR_V2_H
+
+#include <stdint.h>
+#include <systemc>
+#include "vci_target_fsm.h"
+#include "vci_initiator_fsm.h"
+#include "caba_base_module.h"
+#include "mapping_table.h"
+
+namespace soclib {
+namespace caba {
+
+using namespace sc_core;
+
+template<typename vci_param>
+class VciDmaTsarV2
+	: public caba::BaseModule
+{
+private:
+    soclib::caba::VciTargetFsm<vci_param, true> m_vci_target_fsm;
+    soclib::caba::VciInitiatorFsm<vci_param> m_vci_init_fsm;
+    typedef typename soclib::caba::VciInitiatorReq<vci_param> req_t;
+
+    bool on_write(int seg, typename vci_param::addr_t addr, typename vci_param::data_t data, int be);
+    bool on_read(int seg, typename vci_param::addr_t addr, typename vci_param::data_t &data);
+    void read_done( req_t *req );
+    void write_finish( req_t *req );
+    void transition();
+    void genMoore();
+
+	uint32_t m_src;
+	uint32_t m_dst;
+	uint32_t m_len;
+	uint32_t m_offset;
+    uint32_t m_offset_buffer;
+    bool m_partial;
+    bool m_must_finish;
+	bool m_irq_enabled;
+	bool r_irq;
+
+	std::vector<uint8_t> m_data;
+
+	bool m_handling;
+
+	void next_req();
+	void ended();
+
+protected:
+    SC_HAS_PROCESS(VciDmaTsarV2);
+
+public:
+    sc_in<bool> p_clk;
+    sc_in<bool> p_resetn;
+    soclib::caba::VciTarget<vci_param> p_vci_target;
+    soclib::caba::VciInitiator<vci_param> p_vci_initiator;
+    sc_out<bool> p_irq;
+
+	VciDmaTsarV2(
+		sc_module_name name,
+		const soclib::common::MappingTable &mt,
+		const soclib::common::IntTab &srcid,
+		const soclib::common::IntTab &tgtid,
+		const size_t burst_size );
+};
+
+}}
+
+#endif /* SOCLIB_VCI_DMA_TSAR_V2_H */
+
+// Local Variables:
+// tab-width: 4
+// c-basic-offset: 4
+// c-file-offsets:((innamespace . 0)(inline-open . 0))
+// indent-tabs-mode: nil
+// End:
+
+// vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4
+
Index: branches/v4/modules/vci_dma_tsar_v2/caba/source/src/vci_dma_tsar_v2.cpp
===================================================================
--- branches/v4/modules/vci_dma_tsar_v2/caba/source/src/vci_dma_tsar_v2.cpp	(revision 371)
+++ branches/v4/modules/vci_dma_tsar_v2/caba/source/src/vci_dma_tsar_v2.cpp	(revision 371)
@@ -0,0 +1,246 @@
+/* -*- c++ -*-
+ *
+ * SOCLIB_LGPL_HEADER_BEGIN
+ * 
+ * This file is part of SoCLib, GNU LGPLv2.1.
+ * 
+ * SoCLib is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU Lesser General Public License as published
+ * by the Free Software Foundation; version 2.1 of the License.
+ * 
+ * SoCLib is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * Lesser General Public License for more details.
+ * 
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with SoCLib; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301 USA
+ * 
+ * SOCLIB_LGPL_HEADER_END
+ *
+ * Copyright (c) UPMC, Lip6, Asim
+ *         Nicolas Pouillon <nipo@ssji.net>, 2007
+ */
+
+#include <stdint.h>
+#include "register.h"
+#include "../include/vci_dma_tsar_v2.h"
+#include "dma_tsar_v2.h"
+
+namespace soclib { namespace caba {
+
+#define tmpl(t) template<typename vci_param> t VciDmaTsarV2<vci_param>
+
+tmpl(bool)::on_write(int seg, typename vci_param::addr_t addr, typename vci_param::data_t data, int be)
+{
+    int cell = (int)addr / vci_param::B;
+
+	switch ((enum SoclibDmaRegisters)cell) {
+	case DMA_SRC:
+		m_src = data;
+		return true;
+    case DMA_DST:
+		m_dst = data;
+		return true;
+    case DMA_LEN:
+		m_len = data;
+		return true;
+    case DMA_RESET:
+        m_must_finish = true;
+        m_irq_enabled = false;
+		r_irq = false;
+        return true;
+    case DMA_IRQ_DISABLED:
+		m_irq_enabled = !data;
+		return true;
+	};
+	return false;
+}
+
+tmpl(void)::ended()
+{
+	if ( m_irq_enabled )
+		r_irq = true;
+	m_len = 0;
+    m_must_finish = false;
+	m_handling = false;
+}
+
+tmpl(bool)::on_read(int seg, typename vci_param::addr_t addr, typename vci_param::data_t &data)
+{
+    int cell = (int)addr / vci_param::B;
+
+	switch ((enum SoclibDmaRegisters)cell) {
+	case DMA_SRC:
+		data = m_src;
+		return true;
+    case DMA_DST:
+		data = m_dst;
+		return true;
+	case DMA_LEN:
+		data = m_len;
+		return true;
+    default:
+        return false;
+	}
+	return false;
+}
+
+tmpl(void)::read_done( req_t *req )
+{
+	if ( !req->failed() && !m_must_finish ) {
+		ssize_t burst = m_offset_buffer;
+
+        m_partial = false;
+        if( (( m_dst+m_offset ) & ~( m_data.size()-1 )) !=
+            (( m_dst+m_offset+m_offset_buffer-1 ) & ~( m_data.size()-1 )) ){
+            burst = (((m_dst+m_offset) & ~( m_data.size()-1))+m_data.size()) - (m_dst+m_offset);
+            m_partial = true;
+        }
+		VciInitSimpleWriteReq<vci_param> *new_req =
+			new VciInitSimpleWriteReq<vci_param>( m_dst+m_offset, &m_data[0], burst );
+		new_req->setDone( this, ON_T(write_finish) );
+		m_vci_init_fsm.doReq( new_req );
+	} else {
+		ended();
+	}
+	delete req;
+}
+
+tmpl(void)::write_finish( req_t *req )
+{
+    ssize_t burst = 0;
+    uint32_t offset = 0;
+    if( m_partial ){
+        burst = m_dst + m_offset + m_offset_buffer - ((m_dst+m_offset+m_offset_buffer) & ~( m_data.size()-1));
+        offset = m_offset_buffer - burst ;
+    } else {
+	    m_offset += m_offset_buffer;
+    }
+	if ( !req->failed() && !m_must_finish ){
+        if(m_partial){
+            VciInitSimpleWriteReq<vci_param> *new_req =
+                new VciInitSimpleWriteReq<vci_param>( m_dst+m_offset+offset, &m_data[offset], burst );
+            new_req->setDone( this, ON_T(write_finish) );
+            m_partial = false;
+            m_vci_init_fsm.doReq( new_req );
+            delete req;
+            return;
+        }
+		next_req();
+    }
+	else {
+		ended();
+	}
+	delete req;
+}
+
+tmpl(void)::next_req()
+{
+	ssize_t remaining = (ssize_t)m_len-(size_t)m_offset;
+	if ( remaining <= 0 ) {
+		ended();
+		return;
+	}
+
+	ssize_t burst = m_data.size();
+    m_partial = false;
+    if ( ( m_src+m_offset ) & ( m_data.size()-1 ) ){
+        burst = m_data.size() - ( (m_src+m_offset) & (m_data.size()-1) );
+        m_partial = true;
+    }
+	if ( remaining < burst ){
+		burst = remaining;
+        m_partial = true;
+    }
+
+    m_offset_buffer = burst;
+
+	VciInitSimpleReadReq<vci_param> *req =
+		new VciInitSimpleReadReq<vci_param>(
+			&m_data[0], (m_src+m_offset), burst );
+	req->setDone( this, ON_T(read_done) );
+	m_vci_init_fsm.doReq( req );
+}
+
+tmpl(void)::transition()
+{
+	if (!p_resetn) {
+		m_vci_target_fsm.reset();
+		m_vci_init_fsm.reset();
+		r_irq = false;
+		m_irq_enabled = false;
+		m_len = 0;
+        m_offset_buffer = 0;
+		m_handling = false;
+        m_must_finish = false;
+		return;
+	}
+
+
+	if ( m_len && !m_handling ) {
+		m_handling = true;
+		m_offset = 0;
+
+		next_req();
+	}
+    
+    if( !m_handling )
+        m_must_finish = false;
+
+	m_vci_target_fsm.transition();
+	m_vci_init_fsm.transition();
+}
+
+tmpl(void)::genMoore()
+{
+	m_vci_target_fsm.genMoore();
+	m_vci_init_fsm.genMoore();
+
+	p_irq = r_irq && m_irq_enabled;
+}
+
+tmpl(/**/)::VciDmaTsarV2(
+    sc_module_name name,
+    const MappingTable &mt,
+    const IntTab &srcid,
+    const IntTab &tgtid,
+	const size_t burst_size )
+	: caba::BaseModule(name),
+	  m_vci_target_fsm(p_vci_target, mt.getSegmentList(tgtid)),
+	  m_vci_init_fsm(p_vci_initiator, mt.indexForId(srcid)),
+	  m_len(0),
+	  m_data(burst_size, (uint8_t)0),
+      p_clk("clk"),
+      p_resetn("resetn"),
+      p_vci_target("vci_target"),
+      p_vci_initiator("vci_initiator"),
+      p_irq("irq")
+{
+	m_vci_target_fsm.on_read_write(on_read, on_write);
+    
+    assert(burst_size && "Useless DMA with no buffer");
+    assert(burst_size < (1<<vci_param::K) && "I will be unable to create requests that big");
+
+	SC_METHOD(transition);
+	dont_initialize();
+	sensitive << p_clk.pos();
+
+	SC_METHOD(genMoore);
+	dont_initialize();
+	sensitive << p_clk.neg();
+}
+
+}}
+
+// Local Variables:
+// tab-width: 4
+// c-basic-offset: 4
+// c-file-offsets:((innamespace . 0)(inline-open . 0))
+// indent-tabs-mode: nil
+// End:
+
+// vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4
+
Index: branches/v4/modules/vci_dma_tsar_v2/include/soclib/dma_tsar_v2.h
===================================================================
--- branches/v4/modules/vci_dma_tsar_v2/include/soclib/dma_tsar_v2.h	(revision 371)
+++ branches/v4/modules/vci_dma_tsar_v2/include/soclib/dma_tsar_v2.h	(revision 371)
@@ -0,0 +1,49 @@
+/*
+ * SOCLIB_LGPL_HEADER_BEGIN
+ * 
+ * This file is part of SoCLib, GNU LGPLv2.1.
+ * 
+ * SoCLib is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU Lesser General Public License as published
+ * by the Free Software Foundation; version 2.1 of the License.
+ * 
+ * SoCLib is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * Lesser General Public License for more details.
+ * 
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with SoCLib; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301 USA
+ * 
+ * SOCLIB_LGPL_HEADER_END
+ *
+ * Copyright (c) UPMC, Lip6, Asim
+ *         Nicolas Pouillon <nipo@ssji.net>, 2007
+ *         Eric Guthmuller  <eric.guthmuller@polytechnique.edu>, 2009
+ *
+ * Maintainers: nipo eric.guthmuller@polytechnique.edu
+ */
+#ifndef DMA_REGS_TSAR_V2_H
+#define DMA_REGS_TSAR_V2_H
+
+enum SoclibDmaRegisters {
+    DMA_SRC,
+    DMA_DST,
+    DMA_LEN,
+    DMA_RESET,
+    DMA_IRQ_DISABLED,
+};
+
+#endif /* DMA_REGS_TSAR_V2_H */
+
+// Local Variables:
+// tab-width: 4
+// c-basic-offset: 4
+// c-file-offsets:((innamespace . 0)(inline-open . 0))
+// indent-tabs-mode: nil
+// End:
+
+// vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4
+
Index: branches/v4/modules/vci_io_bridge/caba/metadata/vci_io_bridge.sd
===================================================================
--- branches/v4/modules/vci_io_bridge/caba/metadata/vci_io_bridge.sd	(revision 371)
+++ branches/v4/modules/vci_io_bridge/caba/metadata/vci_io_bridge.sd	(revision 371)
@@ -0,0 +1,98 @@
+
+# -*- python -*-
+
+__id__ = "$Id: vci_io_bridge.sd 20 2012-6-11 $"
+
+Module('caba:vci_io_bridge',
+	classname = 'soclib::caba::VciIoBridge',
+	tmpl_parameters = [ 
+        parameter.Module('vci_param_d', default = 'caba:vci_param',
+                            cell_size   = parameter.Reference("cell_size_d"),
+                            plen_size   = parameter.Reference("plen_size_d"),
+                            addr_size   = parameter.Reference("addr_size_d"),
+                            rerror_size = parameter.Reference("rerror_size_d"),
+                            clen_size   = parameter.Reference("clen_size_d"),  
+                            rflag_size  = parameter.Reference("rflag_size_d"), 
+                            srcid_size  = parameter.Reference("srcid_size_d"),
+                            pktid_size  = parameter.Reference("pktid_size_d"),
+                            trdid_size  = parameter.Reference("trdid_size_d"),
+                            wrplen_size = parameter.Reference("wrplen_size_d")),
+	    parameter.Module('vci_param_x', default = 'caba:vci_param',
+                            cell_size   = parameter.Reference("cell_size_x"),
+                            plen_size   = parameter.Reference("plen_size_x"),
+                            addr_size   = parameter.Reference("addr_size_x"),
+                            rerror_size = parameter.Reference("rerror_size_x"),
+                            clen_size   = parameter.Reference("clen_size_x"),  
+                            rflag_size  = parameter.Reference("rflag_size_x"), 
+                            srcid_size  = parameter.Reference("srcid_size_x"),
+                            pktid_size  = parameter.Reference("pktid_size_x"),
+                            trdid_size  = parameter.Reference("trdid_size_x"),
+                            wrplen_size = parameter.Reference("wrplen_size_x")),
+        parameter.Module('vci_param_io', default = 'caba:vci_param', 
+                            cell_size   = parameter.Reference("cell_size_io"),
+                            plen_size   = parameter.Reference("plen_size_io"),
+                            addr_size   = parameter.Reference("addr_size_io"),
+                            rerror_size = parameter.Reference("rerror_size_io"),
+                            clen_size   = parameter.Reference("clen_size_io"),  
+                            rflag_size  = parameter.Reference("rflag_size_io"), 
+                            srcid_size  = parameter.Reference("srcid_size_io"),
+                            pktid_size  = parameter.Reference("pktid_size_io"),
+                            trdid_size  = parameter.Reference("trdid_size_io"),
+                            wrplen_size = parameter.Reference("wrplen_size_io")),
+    ],
+	header_files =         [ '../source/include/vci_io_bridge.h',
+	                         '../source/include/transaction_tab_io.h'],
+	implementation_files = [ '../source/src/vci_io_bridge.cpp' ],
+	uses = [ Uses('caba:base_module'),
+	         Uses('common:mapping_table'),
+	         Uses('caba:generic_fifo'),
+	         Uses('caba:generic_tlb', 
+                       addr_t = parameter.StringExt('sc_dt::sc_uint<%d> ', 
+                       parameter.Reference('addr_size'))),
+ 	         Uses('common:address_decoding_table', 
+                       input_t  = 'unsigned long',
+                       output_t = 'bool'),
+ 	         Uses('common:address_decoding_table', 
+                       input_t  = 'unsigned long',
+                       output_t = 'int'),
+#	         Uses('common:address_masking_table', 
+#                       data_t = parameter.StringExt('sc_dt::sc_uint<%d> ', 
+#                       parameter.Reference('addr_size'))),
+           ],
+	ports = [ Port('caba:vci_initiator', 'p_vci_ini_dma'),
+	          Port('caba:vci_target', 'p_vci_tgt_dma'),
+              Port('caba:vci_initiator', 'p_vci_ini_config'),
+	          Port('caba:vci_target', 'p_vci_tgt_config'),
+              Port('caba:vci_initiator', 'p_vci_ini_miss'),
+	          Port('caba:bit_in','p_irq', parameter.Reference('nb_periph')),
+	          Port('caba:bit_in', 'p_resetn', auto = 'resetn'),
+	          Port('caba:clock_in', 'p_clk', auto = 'clock'), ],
+	instance_parameters = [ parameter.Int('nd_periph'),
+	                        parameter.Module('mtx', 'common:mapping_table'),
+	                        parameter.Module('mtd', 'common:mapping_table'),
+	                        parameter.Module('mtio', 'common:mapping_table'),
+	                        parameter.Module('seg_config_iob', 'common:segment'), 
+                            parameter.IntTab('tgt_index_iocluster'),
+#	                        parameter.IntTab('tgt_index_config'),
+	                        parameter.IntTab('init_index_direct'),
+	                        parameter.IntTab('tgt_index_iospace'),
+	                        parameter.IntTab('init_index_iospace'),
+	                        parameter.IntTab('init_index_dma'),
+    	                        parameter.Int('dcache_words'),
+    	                        parameter.Int('iotlb_ways'),
+    	                        parameter.Int('iotlb_sets'),
+    	                        parameter.Int('max_frozen_cycles'), ],
+	extensions = [ 'dsx:get_ident='
+                       'tgt_index_config:p_vci_tgt_config:mtd,'
+                       'init_index_direct:p_vci_init_miss:mtd,'
+                       'tgt_index_iospace:p_vci_tgt_dma:mtio,'
+                       'init_index_iospace:p_vci_init_config:mtio,'
+                       'init_index_dma:p_vci_ini_dma:mtx,'
+	               'dsx:cpu=wrapper:iss_t',
+	               'dsx:addressable=tgt_index_config,tgt_index_iospace',
+#                       'dsx:on_segment=mc:add_index:initiator_rw_index',
+	               ],
+
+#       debug = True,
+)
+
Index: branches/v4/modules/vci_io_bridge/caba/source/include/transaction_tab_io.h
===================================================================
--- branches/v4/modules/vci_io_bridge/caba/source/include/transaction_tab_io.h	(revision 371)
+++ branches/v4/modules/vci_io_bridge/caba/source/include/transaction_tab_io.h	(revision 371)
@@ -0,0 +1,230 @@
+#ifndef IOB_TRANSACTION_H_
+#define IOB_TRANSACTION_H_
+ 
+#include <inttypes.h>
+#include <systemc>
+#include <cassert>
+#include "arithmetics.h"
+
+#define DEBUG_IOB_TRANSACTION 0
+
+// The index of Transaction Tab Entry corresponds to the trdid of the VCI packet on XRAM network
+
+////////////////////////////////////////////////////////////////////////
+//                  A transaction tab entry         
+////////////////////////////////////////////////////////////////////////
+
+class TransactionTabIOEntry {
+  typedef uint32_t              size_t;
+
+ public:
+  bool 		            valid;     	    // entry valid 
+  size_t 	            srcid;     	    // processor requesting the transaction
+  size_t 	            trdid;     	    // processor requesting the transaction
+
+  /////////////////////////////////////////////////////////////////////
+  // The init() function initializes the entry 
+  /////////////////////////////////////////////////////////////////////
+  void init()
+  {
+    valid		= false;
+  }
+
+  ////////////////////////////////////////////////////////////////////
+  // The copy() function copies an existing entry
+  // Its arguments are :
+  // - source : the transaction tab entry to copy
+  ////////////////////////////////////////////////////////////////////
+  void copy(const TransactionTabIOEntry &source)
+  {
+    valid	    = source.valid;
+    srcid	    = source.srcid;
+    trdid	    = source.trdid;
+  }
+
+  ////////////////////////////////////////////////////////////////////
+  // The print() function prints the entry 
+  ////////////////////////////////////////////////////////////////////
+  void print(){
+    std::cout << "valid       = " << valid        << std::endl;
+    std::cout << "srcid       = " << srcid        << std::endl;
+    std::cout << "trdid       = " << trdid        << std::endl;
+  }
+
+  /////////////////////////////////////////////////////////////////////
+  // 		Constructors
+  /////////////////////////////////////////////////////////////////////
+
+  TransactionTabIOEntry()
+    {
+      valid=false;
+    }
+
+  TransactionTabIOEntry(const TransactionTabIOEntry &source){
+    valid	    = source.valid;
+    srcid	    = source.srcid;
+    trdid	    = source.trdid;
+  }
+
+}; // end class TransactionTabIOEntry
+
+////////////////////////////////////////////////////////////////////////
+//                  The transaction tab                              
+////////////////////////////////////////////////////////////////////////
+class TransactionTabIO{
+//  typedef uint32_t size_t;
+
+ private:
+  size_t size_tab;                // The size of the tab
+
+ public:
+  TransactionTabIOEntry *tab;       // The transaction tab
+
+  ////////////////////////////////////////////////////////////////////
+  //		Constructors
+  ////////////////////////////////////////////////////////////////////
+  TransactionTabIO()
+    {
+      size_tab=0;
+      tab=NULL;
+    }
+
+  TransactionTabIO(size_t n_entries)
+    {
+      size_tab = n_entries;
+      tab = new TransactionTabIOEntry[size_tab];
+    }
+
+  ~TransactionTabIO()
+    {
+      delete [] tab;
+    }
+
+  /////////////////////////////////////////////////////////////////////
+  // The size() function returns the size of the tab
+  /////////////////////////////////////////////////////////////////////
+  size_t size()
+  {
+    return size_tab;
+  }
+
+  /////////////////////////////////////////////////////////////////////
+  // The init() function initializes the transaction tab entries
+  /////////////////////////////////////////////////////////////////////
+  void init()
+  {
+    for ( size_t i=0; i<size_tab; i++) {
+      tab[i].init();
+    }
+  }
+
+  /////////////////////////////////////////////////////////////////////
+  // The print() function prints a transaction tab entry
+  // Arguments :
+  // - index : the index of the entry to print
+  /////////////////////////////////////////////////////////////////////
+  void print(const size_t index)
+  {
+    assert( (index < size_tab) 
+	    && "Invalid Transaction Tab Entry");
+    tab[index].print();
+    return;
+  }
+
+  /////////////////////////////////////////////////////////////////////
+  // The read() function returns a transaction tab entry.
+  // Arguments :
+  // - index : the index of the entry to read
+  /////////////////////////////////////////////////////////////////////
+  TransactionTabIOEntry read(const size_t index)
+  {
+    assert( (index < size_tab) 
+	    && "Invalid Transaction Tab Entry");
+    return tab[index];
+  }
+  
+  /////////////////////////////////////////////////////////////////////
+  // The readSrcid() function returns the srcid field of a transaction tab entry.
+  // Arguments :
+  // - index : the index of the entry to read
+  /////////////////////////////////////////////////////////////////////
+  size_t readSrcid(const size_t index)
+  {
+    assert( (index < size_tab) 
+	    && "Invalid Transaction Tab Entry");
+    return tab[index].srcid;
+  }
+
+  /////////////////////////////////////////////////////////////////////
+  // The readTrdid() function returns the trdid field of a transaction tab entry.
+  // Arguments :
+  // - index : the index of the entry to read
+  /////////////////////////////////////////////////////////////////////
+  size_t readTrdid(const size_t index)
+  {
+    assert( (index < size_tab) 
+	    && "Invalid Transaction Tab Entry");
+    return tab[index].trdid;
+  }
+
+  /////////////////////////////////////////////////////////////////////
+  // The full() function returns the state of the transaction tab
+  // Arguments :
+  // - index : (return argument) the index of an empty entry 
+  // The function returns true if the transaction tab is full
+  /////////////////////////////////////////////////////////////////////
+  bool full(size_t &index)
+  {
+    for(size_t i=0; i<size_tab; i++){
+      if(!tab[i].valid){
+	    index=i;
+	    return false;	
+      }
+    }
+    return true;
+  }
+
+  /////////////////////////////////////////////////////////////////////
+  // The set() function registers a transaction (read or write)
+  // to the XRAM in the transaction tab.
+  // Arguments :
+  // - index : index in the transaction tab
+  // - srcid : srcid of the initiator that caused the transaction
+  // - trdid : trdid of the initiator that caused the transaction
+  /////////////////////////////////////////////////////////////////////
+  void set(const size_t index,
+	   const size_t srcid,
+	   const size_t trdid) 
+  {
+    assert( (index < size_tab) 
+	    && "The selected entry is out of range in set() Transaction Tab");
+
+    tab[index].valid	        = true;
+    tab[index].srcid	        = srcid;
+    tab[index].trdid	        = trdid;
+  }
+
+  /////////////////////////////////////////////////////////////////////
+  // The erase() function erases an entry in the transaction tab.
+  // Arguments :
+  // - index : the index of the request in the transaction tab
+  /////////////////////////////////////////////////////////////////////
+  void erase(const size_t index)
+  {
+    assert( (index < size_tab) 
+	    && "The selected entry is out of range in erase() Transaction Tab");
+    tab[index].valid	= false;
+  }
+}; // end class TransactionTabIO
+
+#endif
+
+// Local Variables:
+// tab-width: 4
+// c-basic-offset: 4
+// c-file-offsets:((innamespace . 0)(inline-open . 0))
+// indent-tabs-mode: nil
+// End:
+
+// vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4
+
Index: branches/v4/modules/vci_io_bridge/caba/source/include/vci_io_bridge.h
===================================================================
--- branches/v4/modules/vci_io_bridge/caba/source/include/vci_io_bridge.h	(revision 371)
+++ branches/v4/modules/vci_io_bridge/caba/source/include/vci_io_bridge.h	(revision 371)
@@ -0,0 +1,622 @@
+/* -*- c++ -*-
+ * File : vci_io_bridge.h
+ * Copyright (c) UPMC, Lip6, SoC
+ * Date : 16/04/2012
+ *
+ * SOCLIB_LGPL_HEADER_BEGIN
+ * 
+ * This file is part of SoCLib, GNU LGPLv2.1.
+ * 
+ * SoCLib is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU Lesser General Public License as published
+ * by the Free Software Foundation; version 2.1 of the License.
+ * 
+ * SoCLib is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * Lesser General Public License for more details.
+ * 
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with SoCLib; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301 USA
+ * 
+ * SOCLIB_LGPL_HEADER_END
+ */
+
+//////Utilisation Considerations////////////////////////////////////////////////
+//
+// - IOMMU PTPR pointer must fit in 32 bits (with a classical 2 level 4K page
+//   table in a 32 bit virtual space, it means a maximum of 45 bits in physical
+//   address)
+//
+// - Physical address must fit in two 32 bit words
+//
+// - Maximal number of flits in a write transaction cannot be bigger than (nÂ° of
+//   words in a chache line)/2
+//
+// - Page Tables must have the format used in TSAR (compatible with component
+//   generic_tlb)
+//
+// - IO's segment size must be the same in both networks
+//
+// - Write operations on IOMMU configuration registers (PTPR, ACTIVE) can only
+//   be done when DMA_TLB FSM is IDLE. It should, preferably, be done before
+//   starting any transfers. Pseudo register INVAL may be modified any time.
+//
+// - Similarly, write operations on the interruptions registers can only be done
+//   when the dedicated FSM is IDLE.                
+////////////////////////////////////////////////////////////////////////////////
+
+ 
+///////TODO List///////////////////////////////////////////////////////////////
+//
+// Tableau de correspondance d'adresses physique - IO (pour CONFIG_CMD)
+//
+// Conversion 32 (entree) Ã  64 (sortie) bits (champ data). Dans les deux senses (CMD et RSP)
+// 
+// Ne pas garder tous les champs WRITE CMD dans les FIFO a chaque flit
+// (seulement 'data' et 'be')
+///////////////////////////////////////////////////////////////////////////////
+
+#ifndef SOCLIB_CABA_VCI_IO_BRIDGE_H
+#define SOCLIB_CABA_VCI_IO_BRIDGE_H
+
+#include <inttypes.h>
+#include <systemc>
+#include "caba_base_module.h"
+#include "generic_fifo.h"
+#include "generic_tlb.h"
+#include "mapping_table.h"
+#include "address_decoding_table.h" 
+#include "static_assert.h"
+#include "transaction_tab_io.h"
+#include "vci_initiator.h"
+#include "vci_target.h"
+
+namespace soclib {
+namespace caba {
+
+using namespace soclib::common;
+
+////////////////////////////////////////////
+template<typename vci_param_d,typename vci_param_x, typename vci_param_io >
+class VciIoBridge
+////////////////////////////////////////////
+    : public soclib::caba::BaseModule
+{
+    typedef uint32_t tag_t;
+    typedef uint32_t type_t;
+    
+    // Address field may change between direct, extenal and IO network 
+    typedef typename vci_param_d::addr_t        paddr_t; 
+    typedef typename vci_param_x::addr_t        paddr_t_x; // Just the cache line, for example
+    typedef typename vci_param_io::addr_t       vaddr_t;
+    
+    // Data field may change for external network 
+    typedef typename vci_param_x::data_t      vci_data_t_x;
+    // Srcid field may change for external network 
+    typedef typename vci_param_x::srcid_t     vci_srcid_t_x;
+    
+    // Other fields must coincide   
+    typedef typename vci_param_d::srcid_t     vci_srcid_t;  
+    typedef typename vci_param_d::data_t      vci_data_t;   
+    typedef typename vci_param_d::be_t        vci_be_t;
+    typedef typename vci_param_d::trdid_t     vci_trdid_t;
+    typedef typename vci_param_d::pktid_t     vci_pktid_t;
+    typedef typename vci_param_d::plen_t      vci_plen_t;
+    typedef typename vci_param_d::cmd_t       vci_cmd_t;
+    typedef typename vci_param_d::contig_t    vci_contig_t;
+    typedef typename vci_param_d::eop_t       vci_eop_t;
+    typedef typename vci_param_d::const_t     vci_cons_t;
+    typedef typename vci_param_d::wrap_t      vci_wrap_t;
+    typedef typename vci_param_d::clen_t      vci_clen_t;
+    typedef typename vci_param_d::cfixed_t    vci_cfixed_t;
+
+    typedef typename vci_param_d::rerror_t    vci_rerror_t;
+
+    enum {
+        CACHE_LINE_MASK = 0xFFFFFFFFC0,  
+        PPN1_MASK = 0x0007FFFF,  
+        PPN2_MASK = 0x0FFFFFFF,  
+        K_PAGE_OFFSET_MASK = 0x00000FFF,  
+        M_PAGE_OFFSET_MASK = 0x001FFFFF,
+        PTE2_LINE_OFFSET   = 0x00007000, // bits 12,13,14.
+        PTE1_LINE_OFFSET   = 0x01E00000, // bits 21,22,23,24 
+    };
+ 
+    //DMA (from Peripherals to XRAM)
+    enum dma_cmd_fsm_state {  
+        DMA_CMD_IDLE,
+        DMA_CMD_TRT_LOCK,
+        DMA_CMD_TRT_WAIT,
+        DMA_CMD_TRT_SET,
+        DMA_CMD_FIFO_PUT,
+        DMA_CMD_FIFO_MISS_PUT,
+        DMA_CMD_TLB_MISS_WAIT,
+        DMA_CMD_TLB_MISS_STORE,
+        DMA_CMD_ERROR,
+    };
+   
+    enum dma_rsp_fsm_state {  
+        DMA_RSP_IDLE,
+        DMA_RSP_TRT_LOCK,
+        DMA_RSP_FIFO_PUT, 
+        DMA_RSP_FIFO_ERROR_PUT,
+    };
+    
+    // Allocates the transaction_tab_dma
+    enum alloc_trt_dma_fsm_state {
+        ALLOC_TRT_DMA_CMD,
+        ALLOC_TRT_DMA_RSP
+    };
+     
+
+    enum dma_tlb_fsm_state {   
+        DMA_TLB_IDLE,
+        DMA_TLB_MISS,
+        DMA_TLB_PTE1_GET,
+        DMA_TLB_PTE1_SELECT,
+        DMA_TLB_PTE1_UPDT,
+        DMA_TLB_PTE2_GET,                                                  
+        DMA_TLB_PTE2_SELECT,
+        DMA_TLB_PTE2_UPDT,
+        DMA_TLB_WAIT_TRANSACTION,
+        DMA_TLB_RETURN,
+        // Treatment of CONFIG FSM request
+        DMA_TLB_INVAL_CHECK,
+        DMA_TLB_INVAL_SCAN
+	};
+    
+    //CONFIG (from Direct Network to Peripherals)
+    enum config_cmd_fsm_state {  
+        CONFIG_CMD_IDLE,
+        CONFIG_CMD_TRT_LOCK,
+        CONFIG_CMD_TRT_WAIT,
+        CONFIG_CMD_TRT_SET,
+        CONFIG_CMD_FIFO_PUT,
+        
+        // IOB private configuration segment 
+        CONFIG_CMD_PTPR_WRITE,
+        CONFIG_CMD_PTPR_READ,
+        CONFIG_CMD_ACTIVE_WRITE,
+        CONFIG_CMD_ACTIVE_READ,
+        CONFIG_CMD_BVAR_READ,
+        CONFIG_CMD_ETR_READ,
+        CONFIG_CMD_BAD_ID_READ,
+        CONFIG_CMD_INVAL_REQ,
+        CONFIG_CMD_INVAL,
+        CONFIG_CMD_IT_ADDR_IOMMU_WRITE_1,
+        CONFIG_CMD_IT_ADDR_IOMMU_WRITE_2,
+        CONFIG_CMD_IT_ADDR_IOMMU_READ_1,
+        CONFIG_CMD_IT_ADDR_IOMMU_READ_2,
+        CONFIG_CMD_IT_ADDR_WRITE_1,
+        CONFIG_CMD_IT_ADDR_WRITE_2,
+        CONFIG_CMD_IT_ADDR_READ_1,
+        CONFIG_CMD_IT_ADDR_READ_2,
+        CONFIG_CMD_ERROR_WAIT,
+        CONFIG_CMD_ERROR_RSP
+	};
+    
+    enum config_rsp_fsm_state {  
+        CONFIG_RSP_IDLE,
+        CONFIG_RSP_TRT_LOCK,
+        CONFIG_RSP_FIFO_PUT 
+    };
+    
+    // Allocates the transaction_tab_dma
+    enum alloc_trt_config_fsm_state {
+        ALLOC_TRT_CONFIG_CMD,
+        ALLOC_TRT_CONFIG_RSP
+	};
+    
+    //MISS TRANSACTIONS (to Direct Network)
+    enum miss_init_fsm_state {  
+        MISS_INIT_IDLE_MISS,
+        MISS_INIT_IDLE_IRQ,
+        MISS_INIT_IRQ_CMD,
+        MISS_INIT_IRQ_RSP,
+        MISS_INIT_TLB_MISS_CMD,
+        MISS_INIT_TLB_MISS_RSP
+	};
+    
+    /////////////////////////////////////////////////////////////////
+
+    // Configuration Error Type  
+    enum config_error_type {
+        READ_OK     = 0, 
+        READ_ERROR  = 1, 
+        WRITE_OK    = 2,
+        WRITE_ERROR = 3
+	};
+ 
+    // Miss types for iotlb
+    enum tlb_miss_type_e
+    {
+        PTE1_MISS, 
+        PTE2_MISS
+	};
+    
+    // IOB Configuration registers
+    // Required segment size = (8 + 2*nb_periph) words
+    enum {
+        IOB_IOMMU_PTPR = 0,     // R/W  : Page Table Pointer Register
+        IOB_IOMMU_ACTIVE = 1,   // R/W  : IOMMU activated if not 0
+        IOB_IOMMU_BVAR = 2,     // R    : Bad Virtual Address
+        IOB_IOMMU_ETR = 3,      // R    : Error type
+        IOB_IOMMU_BAD_ID = 4,   // R    : Faulty peripheral Index
+        IOB_INVAL_PTE = 5,      //   W  : Invalidate PTE. Virtual Address
+        IOB_IT_ADDR_IOMMU_LO = 6,    // R/W
+        IOB_IT_ADDR_IOMMU_HI = 7,    // R/W
+        IOB_IT_ADDR_BEGIN = 8        // R/W : One register by IO
+                                     // Addressed by two 32-bit words each
+    };
+
+    
+    // Error Type
+    enum mmu_error_type_e 
+    {
+        MMU_NONE                      = 0x0000, // None
+        MMU_WRITE_ACCES_VIOLATION     = 0x0008, // Write access of write access to a non writable page (bit W in flags)
+        MMU_WRITE_PT1_ILLEGAL_ACCESS  = 0x0040, // Write access of Bus Error accessing Table 1       
+        MMU_READ_PT1_UNMAPPED 	      = 0x1001, // Read access of Page fault on Page Table 1  	
+        MMU_READ_PT2_UNMAPPED 	      = 0x1002, // Read access of Page fault on Page Table 2  
+        MMU_READ_PT1_ILLEGAL_ACCESS   = 0x1040, // Read access of Bus Error in Table1 access      
+        MMU_READ_PT2_ILLEGAL_ACCESS   = 0x1080, // Read access of Bus Error in Table2 access 	
+        MMU_READ_DATA_ILLEGAL_ACCESS  = 0x1100, // Read access of Bus Error in cache access 
+    };
+    
+
+public:
+    sc_in<bool>                             p_clk;
+    sc_in<bool>                             p_resetn;
+    sc_in<bool>                             *p_irq_in;      
+    
+    soclib::caba::VciInitiator<vci_param_x>     p_vci_ini_dma; // XRAM Noc
+    soclib::caba::VciTarget<vci_param_io>       p_vci_tgt_dma;
+    
+    soclib::caba::VciInitiator<vci_param_io>    p_vci_ini_config;
+    soclib::caba::VciTarget<vci_param_d>        p_vci_tgt_config;
+    
+    soclib::caba::VciInitiator<vci_param_d>     p_vci_ini_miss;
+
+private:
+    const size_t  	m_words;
+    const size_t    m_nb_periph;
+
+    // STRUCTURAL PARAMETERS
+    // soclib::common::AddressDecodingTable<unsigned long, bool>   m_locality_table_config;
+    // soclib::common::AddressDecodingTable<unsigned long, int>    m_routing_table_config;
+    //const soclib::common::MappingTable&                   m_mtio; 
+    
+    uint32_t                    		m_transaction_tab_dma_lines;
+    TransactionTabIO      		    	m_transaction_tab_dma;	// dma transaction table
+    
+    uint32_t                    		m_transaction_tab_config_lines;
+    TransactionTabIO      		    	m_transaction_tab_config;	// config transaction table
+    
+    // Direct Network
+    const soclib::common::Segment                          	m_segment_config;
+    const vci_srcid_t                                      	m_srcid_miss;
+    // XRAM Network 
+    const vci_srcid_t_x                                   	m_srcid_dma;
+    // IO Network
+    const soclib::common::Segment                          	m_segment_io;
+    const vci_srcid_t                                      	m_srcid_config;
+
+    const size_t  						m_iotlb_ways;
+    const size_t  						m_iotlb_sets;
+    const size_t  						m_paddr_nbits;  
+
+
+    /////////////////////////////////////////////
+    // debug variables (for each FSM)
+    /////////////////////////////////////////////
+    uint32_t                            m_debug_start_cycle;
+    bool                                m_debug_ok;
+    
+    bool                                m_debug_dma_cmd_fsm;
+    bool                                m_debug_dma_rsp_fsm;
+    bool                                m_debug_dma_tlb_fsm;
+    bool                                m_debug_config_cmd_fsm;
+    bool                                m_debug_config_rsp_fsm;
+    bool                                m_debug_miss_init_fsm;
+
+    ///////////////////////////////
+    // MEMORY MAPPED REGISTERS
+    ///////////////////////////////
+    sc_signal<uint32_t>     r_iommu_ptpr;       // page table pointer register
+    sc_signal<bool>         r_iommu_active;         // iotlb mode
+    sc_signal<uint32_t>     r_iommu_bvar;       // iommu bad address
+    sc_signal<uint32_t>     r_iommu_etr;        // iommu error type
+    sc_signal<uint32_t>     r_iommu_bad_id;     // ID of the peripheral that tried bad operation
+    
+    sc_signal<paddr_t>     r_it_addr_iommu;        // iommu error type
+    paddr_t                *r_it_addr;        // iommu error type
+ 
+	///////////////////////////////////
+    // DMA_CMD FSM REGISTERS
+    ///////////////////////////////////
+    sc_signal<int>          r_dma_cmd_fsm;			        // state register
+    sc_signal<int>          r_dma_cmd_fsm_save; //saves current state when miss interruption happens
+    sc_signal<bool>         r_miss_interrupt;
+    
+    sc_signal<int>          r_dma_cmd_count;
+    sc_signal<vci_trdid_t>  r_dma_cmd_trt_index; 
+    sc_signal<paddr_t>      r_dma_paddr;
+    
+    GenericFifo<paddr_t>        m_dma_cmd_addr_fifo;
+    //GenericFifo<size_t>       m_dma_cmd_length_fifo;
+    GenericFifo<vci_srcid_t>    m_dma_cmd_srcid_fifo;
+    GenericFifo<vci_trdid_t>    m_dma_cmd_trdid_fifo;
+    GenericFifo<vci_pktid_t>    m_dma_cmd_pktid_fifo;
+    GenericFifo<vci_be_t>       m_dma_cmd_be_fifo;
+    GenericFifo<vci_cmd_t>      m_dma_cmd_cmd_fifo;
+    GenericFifo<vci_contig_t>   m_dma_cmd_contig_fifo;
+    GenericFifo<vci_data_t>     m_dma_cmd_data_fifo;
+    GenericFifo<vci_eop_t>      m_dma_cmd_eop_fifo;
+    GenericFifo<vci_cons_t>     m_dma_cmd_cons_fifo;
+    GenericFifo<vci_plen_t>     m_dma_cmd_plen_fifo;
+    GenericFifo<vci_wrap_t>     m_dma_cmd_wrap_fifo;
+    GenericFifo<vci_cfixed_t>   m_dma_cmd_cfixed_fifo;
+    GenericFifo<vci_clen_t>     m_dma_cmd_clen_fifo;
+
+    // Command storage registers (in case of miss tlb)
+    sc_signal<paddr_t>              r_miss_paddr; 
+    sc_signal<vci_cmd_t>            r_miss_cmd ;
+    sc_signal<vci_contig_t>         r_miss_contig; 
+    sc_signal<vci_cons_t>           r_miss_cons ;
+    sc_signal<vci_plen_t>           r_miss_plen ;
+    sc_signal<vci_wrap_t>           r_miss_wrap ;
+    sc_signal<vci_cfixed_t>         r_miss_cfixed; 
+    sc_signal<vci_clen_t>           r_miss_clen ;
+    sc_signal<vci_srcid_t>          r_miss_srcid ;
+    sc_signal<vci_trdid_t>          r_miss_trdid ;
+    sc_signal<vci_pktid_t>          r_miss_pktid ;
+    vci_data_t                      *r_miss_data ;  
+    vci_be_t                        *r_miss_be;
+    
+    // Error registers 
+    sc_signal<int>          r_dma_error_type;   
+    sc_signal<vci_trdid_t>  r_dma_error_trdid;  
+    sc_signal<vci_pktid_t>  r_dma_error_pktid;  
+    
+    ///////////////////////////////////
+    // DMA_TLB FSM REGISTERS
+    ///////////////////////////////////
+    sc_signal<int>          r_dma_tlb_fsm;		    // state register 
+    sc_signal<bool>         r_waiting_transaction;  // Flag for returning from
+                                                    // invalidation interruptions
+    sc_signal<int>          r_tlb_miss_type;
+
+    sc_signal<vaddr_t>      r_iotlb_vaddr;	        // virtual address for a tlb miss
+    sc_signal<paddr_t>      r_iotlb_paddr;		    // physical address of pte
+    sc_signal<uint32_t>     r_iotlb_pte_flags;	    // pte1 or first word of pte2
+    sc_signal<uint32_t>     r_iotlb_pte_ppn;	    // second word of pte2
+    sc_signal<size_t>       r_iotlb_way;		    // selected way in tlb    
+    sc_signal<size_t>       r_iotlb_set;		    // selected set in tlb    
+   
+    //////////////////////////////////////////////////////////////////
+    // IOTLB  
+    //////////////////////////////////////////////////////////////////
+    GenericTlb<paddr_t>       	r_iotlb;
+	
+    ///////////////////////////////////
+    // DMA_RSP FSM REGISTERS
+    ///////////////////////////////////
+    sc_signal<int>          r_dma_rsp_fsm;
+
+	sc_signal<vci_trdid_t>	r_dma_rtrdid; 
+	sc_signal<vci_srcid_t>	r_dma_rsrcid;	
+    
+    GenericFifo<vci_data_t>     m_dma_rsp_data_fifo;
+    GenericFifo<vci_srcid_t>    m_dma_rsp_rsrcid_fifo;
+    GenericFifo<vci_trdid_t>    m_dma_rsp_rtrdid_fifo;
+    GenericFifo<vci_pktid_t>    m_dma_rsp_rpktid_fifo;
+    GenericFifo<vci_eop_t>      m_dma_rsp_reop_fifo;
+    GenericFifo<vci_rerror_t>   m_dma_rsp_rerror_fifo;
+	
+    //Communication between DMA_CMD and DMA_RSP
+    sc_signal<bool>     r_dma_cmd_rsp_erase_req;
+	sc_signal<bool>     r_dma_cmd_error_req; 
+    //Communication between DMA_CMD and TLB 
+    sc_signal<bool>     r_dma_tlb_req;
+    sc_signal<bool>     r_tlb_dma_untreated; 
+	sc_signal<bool>     r_dma_tlb_error_req; 
+    sc_signal<int>      r_tlb_error_type;   
+    //Communication betweeen TLB and CONFIG_CMD
+    sc_signal<bool>         r_config_tlb_req;
+    sc_signal<vaddr_t>      r_config_tlb_inval_vaddr;
+    
+    ///////////////////////////////////
+    // ALLOC_TRT_DMA FSM REGISTERS
+    ///////////////////////////////////
+    sc_signal<int>          r_alloc_trt_dma_fsm;			// state register 
+
+
+    ///////////////////////////////////
+    // CONFIG_CMD FSM REGISTERS
+    ///////////////////////////////////
+    sc_signal<int>          r_config_cmd_fsm;		        // state register
+    
+    sc_signal<vci_trdid_t>       r_config_cmd_trt_index; 
+    
+    GenericFifo<paddr_t>        m_config_cmd_addr_fifo;
+    //GenericFifo<size_t>       m_config_cmd_length_fifo;
+    GenericFifo<vci_srcid_t>    m_config_cmd_srcid_fifo;
+    GenericFifo<vci_trdid_t>    m_config_cmd_trdid_fifo;
+    GenericFifo<vci_pktid_t>    m_config_cmd_pktid_fifo;
+    GenericFifo<vci_be_t>       m_config_cmd_be_fifo;
+    GenericFifo<vci_cmd_t>      m_config_cmd_cmd_fifo;
+    GenericFifo<vci_contig_t>   m_config_cmd_contig_fifo;
+    GenericFifo<vci_data_t>     m_config_cmd_data_fifo;
+    GenericFifo<vci_eop_t>      m_config_cmd_eop_fifo;
+    GenericFifo<vci_cons_t>     m_config_cmd_cons_fifo;
+    GenericFifo<vci_plen_t>     m_config_cmd_plen_fifo;
+    GenericFifo<vci_wrap_t>     m_config_cmd_wrap_fifo;
+    GenericFifo<vci_cfixed_t>   m_config_cmd_cfixed_fifo;
+    GenericFifo<vci_clen_t>     m_config_cmd_clen_fifo;
+    
+    
+    // Private configuration registers
+    sc_signal<int>          r_config_error_type; // rerror field
+    sc_signal<vci_data_t>   r_config_first_word;    
+    sc_signal<int>          r_it_index;
+    
+    GenericFifo<vci_data_t>   m_config_local_data_fifo;
+    GenericFifo<vci_srcid_t>  m_config_local_rsrcid_fifo;
+    GenericFifo<vci_trdid_t>  m_config_local_rtrdid_fifo;
+    GenericFifo<vci_pktid_t>  m_config_local_rpktid_fifo;
+    GenericFifo<vci_eop_t>    m_config_local_reop_fifo;
+    GenericFifo<vci_rerror_t> m_config_local_rerror_fifo;
+    sc_signal<vaddr_t>      r_config_vaddr;
+    
+
+    ///////////////////////////////////
+    // CONFIG_RSP FSM REGISTERS
+    ///////////////////////////////////
+    sc_signal<int>          r_config_rsp_fsm;
+
+	sc_signal<vci_trdid_t>	r_config_rtrdid; 
+	sc_signal<vci_srcid_t>	r_config_rsrcid;
+    
+    GenericFifo<vci_data_t>   m_config_rsp_data_fifo;
+    GenericFifo<vci_srcid_t>  m_config_rsp_rsrcid_fifo;
+    GenericFifo<vci_trdid_t>  m_config_rsp_rtrdid_fifo;
+    GenericFifo<vci_pktid_t>  m_config_rsp_rpktid_fifo;
+    GenericFifo<vci_eop_t>    m_config_rsp_reop_fifo;
+    GenericFifo<vci_rerror_t> m_config_rsp_rerror_fifo;
+	
+    // Defines priority between the two response FIFOs (local and remote)
+    sc_signal<bool>         r_config_rsp_fifo_local_priority; 
+                                                            
+    //Communication between CONFIG_CMD and CONFIG_RSP
+    sc_signal<bool>     r_config_cmd_rsp_erase_req; // used to signal an erasing on TRT table
+    
+    ///////////////////////////////////
+    // ALLOC_TRT_CONFIG FSM REGISTERS
+    ///////////////////////////////////
+    sc_signal<int>          r_alloc_trt_config_fsm;			        // state register 
+
+    ///////////////////////////////////
+    // MISS_INIT FSM REGISTERS
+    ///////////////////////////////////
+    sc_signal<int>          r_miss_init_fsm;
+
+	sc_signal<vci_data_t>	r_miss_rdata;
+	sc_signal<vci_pktid_t>	r_miss_rpktid; 
+	sc_signal<vci_trdid_t>	r_miss_rtrdid; 
+	sc_signal<vci_rerror_t>	r_miss_rerror; 
+	sc_signal<vci_eop_t>	r_miss_reop;  
+	//sc_signal<vci_data_t>	r_miss_rsrcid;
+	
+    sc_signal<size_t>	r_miss_rsp_cpt;
+    
+    //IRQ
+	sc_signal<uint32_t>	r_irq_pending;  
+	sc_signal<uint32_t>	r_irq_mask;  
+	sc_signal<uint32_t>	r_irq_chosen;  
+
+
+    //Communication between TLB and MISS_INIT 
+    sc_signal<bool>         r_tlb_miss_init_req;
+    sc_signal<bool>         r_miss_init_error; 
+    
+    ////////////////////////////////////
+    // MISS PREFETCH BUFFER
+    ///////////////////////////////////
+    //DMA_TLB FSM is its owner. 
+    //CONFIG FSM must set a request in order to access the resource (invalidation)
+
+    // Proposition : Buffer with some lines (4, for example). It could be
+    // indexed from the bit 20.
+ 
+    vci_data_t                *r_miss_buf_data;     // cache line data buffer 
+    bool                    r_miss_buf_valid;       // For individual invalidation,
+                                                    // we could rather use the Valid bit at each PTE
+    sc_signal<paddr_t>      r_miss_buf_tag;         // chache line number  
+    sc_signal<paddr_t>      r_miss_buf_vaddr_begin; // Virtual address of the first PTE on the line 
+    
+    bool                    r_miss_buf_first_level; // useful only if using both types of pages
+    
+    ////////////////////////////////
+    // Activity counters
+    ////////////////////////////////
+    
+    uint32_t m_cpt_total_cycles;            // total number of cycles
+    
+    // TLB activity counters
+    uint32_t m_cpt_iotlb_read;              // number of iotlb read
+    uint32_t m_cpt_iotlb_miss;              // number of iotlb miss
+    uint32_t m_cost_iotlb_miss;             // number of blocking cycles (not the treatment cycles itself)
+    uint32_t m_cpt_iotlbmiss_transaction;   // number of iotlb miss transactions to Mem Cache
+    uint32_t m_cost_iotlbmiss_transaction;  // cumulated duration for iotlb miss transactions
+
+    //Transaction Tabs (TRTs) activity counters
+    uint32_t m_cpt_trt_dma_full;            // DMA TRT full when a new command arrives
+    uint32_t m_cpt_trt_dma_full_cost;       // total number of cycles blocked
+    uint32_t m_cpt_trt_config_full;         // Config TRT full when a new command arrives
+    uint32_t m_cpt_trt_config_full_cost;    // total number of cycles blocked
+
+    // FSM activity counters
+    // unused on print_stats
+    uint32_t m_cpt_fsm_dma_cmd          [32]; 
+    uint32_t m_cpt_fsm_dma_rsp          [32]; 
+    uint32_t m_cpt_fsm_dma_tlb          [32]; 
+    uint32_t m_cpt_fsm_alloc_trt_dma    [32]; 
+    uint32_t m_cpt_fsm_config_cmd       [32]; 
+    uint32_t m_cpt_fsm_config_rsp       [32]; 
+    uint32_t m_cpt_fsm_alloc_trt_config [32]; 
+    uint32_t m_cpt_fsm_miss_init        [32];
+ 
+protected:
+    SC_HAS_PROCESS(VciIoBridge);
+
+public:
+    VciIoBridge(
+        sc_module_name insname,
+        size_t nb_periph,                               // maximun is 32
+        const soclib::common::MappingTable  &mtx,       //external network
+        const soclib::common::MappingTable  &mtd,       //direct network
+        const soclib::common::MappingTable  &mtio,      //io network
+        const soclib::common::Segment       &seg_config_iob,
+        const soclib::common::IntTab &tgt_index_iocluster,
+//        const soclib::common::IntTab &tgt_index_config,     // Direct Noc
+        const soclib::common::IntTab &init_index_direct,    // Direct Noc 
+        const soclib::common::IntTab &tgt_index_iospace,    // IO Noc
+        const soclib::common::IntTab &init_index_iospace,   // IO Noc
+        const soclib::common::IntTab &init_index_dma,       // XRAM Noc
+        size_t dcache_words,
+        size_t   iotlb_ways,
+        size_t   iotlb_sets,
+        uint32_t debug_start_cycle,
+        bool     debug_ok);
+
+    ~VciIoBridge();
+
+    void print_stats();
+    void clear_stats();
+    void print_trace(size_t mode = 0);
+    
+
+private:
+    void transition();
+    void genMoore();
+};
+
+}}
+
+#endif /* SOCLIB_CABA_VCI_CC_VCACHE_WRAPPER_V4_H */
+
+// Local Variables:
+// tab-width: 4
+// c-basic-offset: 4
+// c-file-offsets:((innamespace . 0)(inline-open . 0))
+// indent-tabs-mode: nil
+// End:
+
+// vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4
+
+
+
+
Index: branches/v4/modules/vci_io_bridge/caba/source/src/vci_io_bridge.cpp
===================================================================
--- branches/v4/modules/vci_io_bridge/caba/source/src/vci_io_bridge.cpp	(revision 371)
+++ branches/v4/modules/vci_io_bridge/caba/source/src/vci_io_bridge.cpp	(revision 371)
@@ -0,0 +1,3320 @@
+/* i*- c++ -*-C
+ * File : vci_io_bridge.cpp
+ * Copyright (c) UPMC, Lip6, SoC
+ *
+ * SOCLIB_LGPL_HEADER_BEGIN
+ * 
+ * This file is part of SoCLib, GNU LGPLv2.1.
+ * 
+ * SoCLib is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU Lesser General Public License as published
+ * by the Free Software Foundation; version 2.1 of the License.
+ * 
+ * SoCLib is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * Lesser General Public License for more details.
+ * 
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with SoCLib; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301 USA
+ * 
+ * SOCLIB_LGPL_HEADER_END
+ */
+
+#include <cassert>
+#include "arithmetics.h"
+#include "alloc_elems.h"
+#include "../include/vci_io_bridge.h"
+
+//////   debug services   ///////////////////////////////////////////////////////
+// All debug messages are conditionned by two variables:
+// - compile time : DEBUG_*** : defined below
+// - execution time : m_debug_***  : defined by constructor arguments
+//    m_debug_* = (m_debug_ok) and (m_cpt_cycle > m_debug_start_cycle)
+/////////////////////////////////////////////////////////////////////////////////
+
+#define DEBUG_DMA_CMD	    	1
+#define DEBUG_DMA_RSP	    	1
+#define DEBUG_DMA_TLB	    	1
+#define DEBUG_CONFIG_CMD		1
+#define DEBUG_CONFIG_RSP		1
+#define DEBUG_MISS_INIT 		1
+
+#define NEW_XRAM_VCI            0
+    
+#define IOMMU_ID		4097
+
+namespace soclib { 
+namespace caba {
+
+namespace {
+
+//DMA 
+const char *dma_cmd_fsm_state_str[] = {
+        "DMA_CMD_IDLE",
+        "DMA_CMD_TRT_LOCK",
+        "DMA_CMD_TRT_WAIT",
+        "DMA_CMD_TRT_SET",
+        "DMA_CMD_FIFO_PUT",
+        "DMA_CMD_FIFO_MISS_PUT",
+        "DMA_CMD_TLB_MISS_WAIT",
+        "DMA_CMD_TLB_MISS_STORE",
+        "DMA_CMD_ERROR",
+    };
+
+const char *dma_rsp_fsm_state_str[] = {
+        "DMA_RSP_IDLE",
+        "DMA_RSP_TRT_LOCK",
+        "DMA_RSP_FIFO_PUT",
+        "DMA_RSP_FIFO_ERROR_PUT",
+ };
+
+const char *alloc_trt_dma_fsm_state_str[] = {
+        "ALLOC_TRT_DMA_CMD",
+        "ALLOC_TRT_DMA_RSP",
+    };
+
+const char *dma_tlb_fsm_state_str[] = {
+        "DMA_TLB_IDLE",
+        "DMA_TLB_MISS",
+        "DMA_TLB_PTE1_GET",
+        "DMA_TLB_PTE1_SELECT",
+        "DMA_TLB_PTE1_UPDT",
+        "DMA_TLB_PTE2_GET",                                                  
+        "DMA_TLB_PTE2_SELECT",
+        "DMA_TLB_PTE2_UPDT",
+        "DMA_TLB_WAIT_TRANSACTION",
+        "DMA_TLB_RETURN",
+        "DMA_TLB_INVAL_CHECK",
+        "DMA_TLB_INVAL_SCAN",
+    };
+
+//CONFIG 
+const char *config_cmd_fsm_state_str[] = {
+        "CONFIG_CMD_IDLE",
+        "CONFIG_CMD_TRT_LOCK",
+        "CONFIG_CMD_TRT_WAIT",
+        "CONFIG_CMD_TRT_SET",
+        "CONFIG_CMD_FIFO_PUT",
+         
+        // IOB private configuration segment 
+        "CONFIG_CMD_PTPR_WRITE",
+        "CONFIG_CMD_PTPR_READ",
+        "CONFIG_CMD_ACTIVE_WRITE",
+        "CONFIG_CMD_ACTIVE_READ",
+        "CONFIG_CMD_BVAR_READ",
+        "CONFIG_CMD_ETR_READ",
+        "CONFIG_CMD_BAD_ID_READ",
+        "CONFIG_CMD_INVAL_REQ",
+        "CONFIG_CMD_INVAL",
+        "CONFIG_CMD_IT_ADDR_IOMMU_WRITE_1",
+        "CONFIG_CMD_IT_ADDR_IOMMU_WRITE_2",
+        "CONFIG_CMD_IT_ADDR_IOMMU_READ_1",
+        "CONFIG_CMD_IT_ADDR_IOMMU_READ_2",
+        "CONFIG_CMD_IT_ADDR_WRITE_1",
+        "CONFIG_CMD_IT_ADDR_WRITE_2",
+        "CONFIG_CMD_IT_ADDR_READ_1",
+        "CONFIG_CMD_IT_ADDR_READ_2",
+        "CONFIG_CMD_ERROR_WAIT",
+        "CONFIG_CMD_ERROR_RSP",
+    };
+
+const char *config_rsp_fsm_state_str[] = {
+        "CONFIG_RSP_IDLE",
+        "CONFIG_RSP_TRT_LOCK",
+        "CONFIG_RSP_FIFO_PUT", 
+    };
+
+const char *alloc_trt_config_fsm_state_str[] = {
+        "ALLOC_TRT_CONFIG_CMD",
+        "ALLOC_TRT_CONFIG_RSP",
+    };
+
+//MISS TRANSACTIONS (to Direct Network) 
+const char *miss_init_fsm_state_str[] = {  
+        "MISS_INIT_IDLE_MISS",
+        "MISS_INIT_IDLE_IRQ",
+        "MISS_INIT_IRQ_CMD",
+        "MISS_INIT_IRQ_RSP",
+        "MISS_INIT_TLB_MISS_CMD",
+        "MISS_INIT_TLB_MISS_RSP",
+    };
+}
+
+#define tmpl(...)  template<typename vci_param_d,typename vci_param_x, typename vci_param_io> __VA_ARGS__ VciIoBridge<vci_param_d,vci_param_x,vci_param_io>
+
+/////////////////////////////////
+tmpl(/**/)::VciIoBridge(
+    sc_module_name 			            name,
+    size_t                              nb_periph,
+    const soclib::common::MappingTable 	&mtx,
+    const soclib::common::MappingTable 	&mtd,
+    const soclib::common::MappingTable 	&mtio,
+    const soclib::common::Segment       &seg_config_iob,
+    const soclib::common::IntTab 	    &tgt_index_iocluster,
+//    const soclib::common::IntTab 	    &tgt_index_config,
+    const soclib::common::IntTab 	    &init_index_direct,
+    const soclib::common::IntTab 	    &tgt_index_iospace,
+    const soclib::common::IntTab 	    &init_index_iospace,
+    const soclib::common::IntTab 	    &init_index_dma,
+    size_t                              dcache_words,
+    size_t 				                iotlb_ways,
+    size_t 				                iotlb_sets,
+    uint32_t				            debug_start_cycle,
+    bool				                debug_ok)
+    : soclib::caba::BaseModule(name),
+
+      p_clk("clk"),
+      p_resetn("resetn"),
+      p_irq_in(soclib::common::alloc_elems<sc_core::sc_in<bool> >("irq_in", nb_periph)),
+      p_vci_ini_dma("vci_ini_dma"),
+      p_vci_tgt_dma("vci_tgt_dma"),
+      p_vci_ini_config("vci_ini_config"),
+      p_vci_tgt_config("vci_tgt_config"),
+      p_vci_ini_miss("vci_ini_miss"),
+
+      m_words(dcache_words),
+      m_nb_periph(nb_periph),
+      
+      // m_locality_table_config(mtd.getLocalityTable<unsigned long>(tgt_index_iocluster)),
+      // These structures simulate what in hardware will be a correspondence table
+      // Between segments' base address on the direct space and on the IO space
+      // m_routing_table_config(mtd.getRoutingTable<unsigned long>(tgt_index_iocluster)), 
+      //m_mtio(mtio),
+      
+      m_transaction_tab_dma(2),
+      m_transaction_tab_config(1),
+      //Direct Network
+//      m_segment_config(mtd.getSegment(tgt_index_config)),
+      m_segment_config(seg_config_iob),
+      m_srcid_miss(mtx.indexForId(init_index_direct)), 
+      //XRAM Network
+      m_srcid_dma(mtx.indexForId(init_index_dma)),
+      //IO Network
+      m_segment_io(mtio.getSegment(tgt_index_iospace)),
+      m_srcid_config(mtio.indexForId(init_index_iospace)),
+
+      m_iotlb_ways(iotlb_ways),
+      m_iotlb_sets(iotlb_sets),
+      m_paddr_nbits(vci_param_d::N),
+
+      m_debug_start_cycle(debug_start_cycle),
+      m_debug_ok(debug_ok),
+
+      r_iommu_ptpr("r_iommu_ptpr"),
+      r_iommu_active("r_iommu_active"),
+      r_iommu_bvar("r_iommu_bvar"),
+      r_iommu_etr("r_iommu_etr"),
+      r_iommu_bad_id("r_iommu_bad_id"),
+      r_it_addr_iommu("r_it_addr_iommu"),
+
+      // DMA_CMD 
+      r_dma_cmd_fsm("r_dma_cmd_fsm"),
+      r_dma_cmd_fsm_save("r_dma_cmd_fsm_save"),      
+      r_miss_interrupt("r_miss_interrupt"),
+      r_dma_cmd_count("r_dma_cmd_count"),
+      r_dma_cmd_trt_index("r_dma_cmd_trt_index"),
+      r_dma_paddr("r_dma_paddr"),
+      // FIFOs
+      m_dma_cmd_addr_fifo("m_dma_cmd_addr_fifo",4),
+      //m_dma_cmd_length_fifo("m_dma_cmd_length_fifo",4),
+      m_dma_cmd_srcid_fifo("m_dma_cmd_srcid_fifo",4), 
+      m_dma_cmd_trdid_fifo("m_dma_cmd_trdid_fifo",4), 
+      m_dma_cmd_pktid_fifo("m_dma_cmd_pktid_fifo",4), 
+      m_dma_cmd_be_fifo("m_dma_cmd_be_fifo",4), 
+      m_dma_cmd_cmd_fifo("m_dma_cmd_cmd_fifo",4), 
+      m_dma_cmd_contig_fifo("m_dma_cmd_contig_fifo",4), 
+      m_dma_cmd_data_fifo("m_dma_cmd_data_fifo",4), 
+      m_dma_cmd_eop_fifo("m_dma_cmd_eop_fifo",4),
+      m_dma_cmd_cons_fifo("m_dma_cmd_cons_fifo",4), 
+      m_dma_cmd_plen_fifo("m_dma_cmd_plen_fifo",4), 
+      m_dma_cmd_wrap_fifo("m_dma_cmd_wrap_fifo",4), 
+      m_dma_cmd_cfixed_fifo("m_dma_cmd_cfixed_fifo",4),
+      m_dma_cmd_clen_fifo("m_dma_cmd_clen_fifo",4), 
+
+      r_miss_paddr       ("r_miss_paddr"), 
+      r_miss_cmd         ("r_miss_cmd"), 
+      r_miss_contig      ("r_miss_contig"),
+      r_miss_cons        ("r_miss_cons"),
+      r_miss_plen        ("r_miss_plen"),
+      r_miss_wrap        ("r_miss_wrap"),
+      r_miss_cfixed      ("r_miss_cfixed"),    
+      r_miss_clen        ("r_miss_clen"),
+      r_miss_srcid       ("r_miss_srcid"),
+      r_miss_trdid       ("r_miss_trdid"),
+      r_miss_pktid       ("r_miss_pktid"),
+
+      r_dma_error_type("r_dma_error_type"),      
+      r_dma_error_trdid("r_dma_error_trdid"), 
+      r_dma_error_pktid("r_dma_error_pktid"), 
+
+ 
+      r_dma_tlb_fsm("r_dma_tlb_fsm"),
+      r_waiting_transaction("r_waiting_transaction"),
+      r_tlb_miss_type("r_tlb_miss_type"),
+
+                     
+      r_iotlb_vaddr("r_iotlb_vaddr"),		 // virtual address for a tlb miss
+      r_iotlb_paddr("r_iotlb_paddr"),		 // physical address of pte
+      r_iotlb_pte_flags("r_iotlb_pte_flags"),// pte1 or first word of pte2
+      r_iotlb_pte_ppn("r_iotlb_pte_ppn"),	 // second word of pte2
+      r_iotlb_way("r_iotlb_way"),		     // selected way in tlb    
+      r_iotlb_set("r_iotlb_set"),		     // selected set in tlb    
+
+      r_iotlb("iotlb", IOMMU_ID, iotlb_ways,iotlb_sets,vci_param_d::N),
+      
+      //DMA_RSP
+      r_dma_rsp_fsm("r_dma_rsp_fsm"),
+      r_dma_rtrdid("r_dma_rtrdid"),
+      r_dma_rsrcid("r_dma_rsrcid"),
+      //Fifo's
+      m_dma_rsp_data_fifo("m_dma_rsp_data_fifo",4),
+      m_dma_rsp_rsrcid_fifo("m_dma_rsp_rsrcid_fifo",4),
+      m_dma_rsp_rtrdid_fifo("m_dma_rsp_rtrdid_fifo",4),
+      m_dma_rsp_rpktid_fifo("m_dma_rsp_rpktid_fifo",4),
+      m_dma_rsp_reop_fifo("m_dma_rsp_reop_fifo",4),
+      m_dma_rsp_rerror_fifo("m_dma_rsp_rerror_fifo",4),
+      
+      r_dma_cmd_rsp_erase_req("r_dma_cmd_rsp_erase_req"),
+      r_dma_cmd_error_req("r_dma_cmd_error_req"),
+      r_dma_tlb_req("r_dma_tlb_req"),
+      r_tlb_dma_untreated("r_tlb_dma_untreated"), 
+      r_dma_tlb_error_req("r_dma_tlb_error_req"),
+      r_config_tlb_req("r_config_tlb_req"),
+      r_config_tlb_inval_vaddr("r_config_tlb_inval_vaddr"), 
+      
+      // ALLOC TRT DMA
+      r_alloc_trt_dma_fsm("r_alloc_trt_dma_fsm"),
+      
+      // CONFIG CMD
+      r_config_cmd_fsm("r_config_cmd_fsm"),
+      r_config_cmd_trt_index("r_config_cmd_trt_index"),
+     
+      m_config_cmd_addr_fifo("m_config_cmd_addr_fifo",4),
+      //m_config_cmd_length_fifo("m_config_cmd_length_fifo",4),
+      m_config_cmd_srcid_fifo("m_config_cmd_srcid_fifo",4),
+      m_config_cmd_trdid_fifo("m_config_cmd_trdid_fifo",4),
+      m_config_cmd_pktid_fifo("m_config_cmd_pktid_fifo",4),
+      m_config_cmd_be_fifo("m_config_cmd_be_fifo",4),
+      m_config_cmd_cmd_fifo("m_config_cmd_cmd_fifo",4),
+      m_config_cmd_contig_fifo("m_config_cmd_contig_fifo",4),
+      m_config_cmd_data_fifo("m_config_cmd_data_fifo",4),
+      m_config_cmd_eop_fifo("m_config_cmd_eop_fifo",4),
+      m_config_cmd_cons_fifo("m_config_cmd_cons_fifo",4),
+      m_config_cmd_plen_fifo("m_config_cmd_plen_fifo",4),
+      m_config_cmd_wrap_fifo("m_config_cmd_wrap_fifo",4),
+      m_config_cmd_cfixed_fifo("m_config_cmd_cfixed_fifo",4),
+      m_config_cmd_clen_fifo("m_config_cmd_clen_fifo",4),
+      // Private configuration registers
+      r_config_error_type("r_config_error_type"),
+      r_config_first_word("r_config_first_word"),
+      r_it_index("r_it_index"),
+      //Fifo's
+      m_config_local_data_fifo("m_config_local_data_fifo",4),     
+      m_config_local_rsrcid_fifo("m_config_local_rsrcid_fifo",4),
+      m_config_local_rtrdid_fifo("m_config_local_rtrdid_fifo",4),
+      m_config_local_rpktid_fifo("m_config_local_rpktid_fifo",4),
+      m_config_local_reop_fifo("m_config_local_reop_fifo",4),
+      m_config_local_rerror_fifo("m_config_local_rerror_fifo",4),    
+      r_config_vaddr("r_config_vaddr"),
+    
+      // CONFIG RSP  
+      r_config_rsp_fsm("r_config_rsp_fsm"),
+      r_config_rtrdid("r_config_rtrdid"),
+      r_config_rsrcid("r_config_rsrcid"),
+      //Fifo's
+      m_config_rsp_data_fifo("m_config_rsp_data_fifo",4),     
+      m_config_rsp_rsrcid_fifo("m_config_rsp_rsrcid_fifo",4),
+      m_config_rsp_rtrdid_fifo("m_config_rsp_rtrdid_fifo",4),
+      m_config_rsp_rpktid_fifo("m_config_rsp_rpktid_fifo",4),
+      m_config_rsp_reop_fifo("m_config_rsp_reop_fifo",4),
+      m_config_rsp_rerror_fifo("m_config_rsp_rerror_fifo",4),    
+
+      // Communication between CONFIG CMD and CONFIG RSP
+      r_config_cmd_rsp_erase_req("r_config_cmd_rsp_erase_req"),      
+    
+      // ALLOC TRT CONFIG 
+      r_alloc_trt_config_fsm("r_alloc_trt_config_fsm"), 
+      // MISS INIT
+      r_miss_init_fsm("r_miss_init_fsm"), 
+      r_miss_rdata("r_miss_rdata"),
+      r_miss_rpktid("r_miss_rpktid"),
+      r_miss_rtrdid("r_miss_rtrdid"),
+      r_miss_rerror("r_miss_rerror"),
+      r_miss_reop("r_miss_reop"),
+      //r_miss_rsrcid("r_miss_rsrcid"),
+      r_miss_rsp_cpt("r_miss_rsp_cpt"),
+      //IRQ
+      r_irq_pending("r_irq_pending"),
+      r_irq_mask("r_irq_mask"),
+      r_irq_chosen("r_irq_chosen"),
+      
+      r_tlb_miss_init_req("r_tlb_miss_init_req"),
+      r_miss_init_error("r_miss_init_error"),
+      
+      r_miss_buf_valid("r_miss_buf_valid"),
+      r_miss_buf_tag("r_miss_buf_tag")
+{
+    assert( (vci_param_d::N <=  64) and
+            "ADDRESS cannot be bigger than 64 bits");
+    assert( (vci_param_d::B ==  vci_param_io::B) and
+            "DATA field must have the same size in Direct and IO Network");
+    assert ( (vci_param_d::B)*8 == 32 
+        and "Error: data field in Direct Noc must be 32 bits" );
+                    
+    
+    // Interruption Address vector, one entry for each IO
+    r_it_addr           = new paddr_t[nb_periph];
+    // One cache line buffer
+    r_miss_buf_data     = new vci_data_t[dcache_words];
+    // Command storage in case of miss TLB
+    // (dcache_words/2) => Maximal size of a write command 
+    r_miss_data     = new vci_data_t[dcache_words]; 
+    r_miss_be     = new vci_be_t[dcache_words];
+    
+    SC_METHOD(transition);
+    dont_initialize();
+    sensitive << p_clk.pos();
+  
+    SC_METHOD(genMoore);
+    dont_initialize();
+    sensitive << p_clk.neg();
+
+ }
+
+/////////////////////////////////////
+tmpl(/**/)::~VciIoBridge()
+/////////////////////////////////////
+{
+    delete [] r_it_addr;
+    delete [] r_miss_buf_data;
+    delete [] r_miss_data;
+    delete [] r_miss_be;
+    soclib::common::dealloc_elems(p_irq_in, m_nb_periph);
+}
+
+////////////////////////////////////
+tmpl(void)::print_trace(size_t mode)
+////////////////////////////////////
+{
+    // b0 : IOtlb trace
+
+    std::cout << std::dec << "IO_BRIDGE " << name() << std::endl;
+
+    std::cout << "  " << dma_cmd_fsm_state_str[r_dma_cmd_fsm.read()]
+              << " | " << dma_rsp_fsm_state_str[r_dma_rsp_fsm.read()]
+              << " | " << dma_tlb_fsm_state_str[r_dma_tlb_fsm.read()]
+              << " | " << alloc_trt_dma_fsm_state_str[r_alloc_trt_dma_fsm.read()]
+              << " | " << config_cmd_fsm_state_str[r_config_cmd_fsm.read()]
+              << " | " << config_rsp_fsm_state_str[r_config_rsp_fsm.read()]
+              << " | " << alloc_trt_config_fsm_state_str[r_alloc_trt_config_fsm.read()]
+              << " | " << miss_init_fsm_state_str[r_miss_init_fsm.read()];
+    std::cout << std::endl;
+
+    if(mode & 0x01)
+    {
+        std::cout << "  IOTLB" << std::endl;
+        r_iotlb.printTrace();
+    }
+    if(mode & 0x02)
+    {
+    	
+    }
+}
+
+
+
+////////////////////////
+tmpl(void)::print_stats()
+////////////////////////
+{
+    std::cout << name() << std::endl
+        << "- IOTLB MISS RATE      = " << (float)m_cpt_iotlb_miss/m_cpt_iotlb_read << std::endl
+        << "- IOTLB MISS COST         = " << (float)m_cost_iotlb_miss/m_cpt_iotlb_miss << std::endl
+        << "- IOTLB MISS TRANSACTION COST  = " << (float)m_cost_iotlbmiss_transaction/m_cpt_iotlbmiss_transaction << std::endl
+        << "- IOTLB MISS TRANSACTION RATE (OVER ALL MISSES)  = " << (float)m_cpt_iotlbmiss_transaction/m_cpt_iotlb_miss << std::endl;
+}
+
+////////////////////////
+tmpl(void)::clear_stats()
+////////////////////////
+{
+    m_cpt_iotlb_read                = 0;             
+    m_cpt_iotlb_miss                = 0;             
+    m_cost_iotlb_miss               = 0;
+    m_cpt_iotlbmiss_transaction     = 0;    
+    m_cost_iotlbmiss_transaction    = 0;   
+        
+    m_cpt_trt_dma_full          = 0;
+    m_cpt_trt_dma_full_cost     = 0;
+    m_cpt_trt_config_full          = 0;
+    m_cpt_trt_config_full_cost     = 0;
+}
+
+/////////////////////////
+tmpl(void)::transition()
+/////////////////////////
+{
+    if ( not p_resetn.read() ) 
+    {
+
+        r_dma_cmd_fsm		    = DMA_CMD_IDLE;
+        r_dma_rsp_fsm		    = DMA_RSP_IDLE;
+        r_alloc_trt_dma_fsm     = ALLOC_TRT_DMA_CMD;
+        r_dma_tlb_fsm	        = DMA_TLB_IDLE;
+        r_config_cmd_fsm	    = CONFIG_CMD_IDLE;
+        r_config_rsp_fsm	    = CONFIG_RSP_IDLE;
+        r_alloc_trt_config_fsm  = ALLOC_TRT_CONFIG_CMD;
+        r_miss_init_fsm		    = MISS_INIT_IDLE_MISS;
+
+        //miss buffer invalidation
+        r_miss_buf_valid = false; 
+        
+		r_iommu_active = false;
+
+        r_dma_cmd_count = 0;
+        
+        // initializing FIFOs
+        m_dma_cmd_addr_fifo.init();
+        m_dma_cmd_srcid_fifo.init();
+        m_dma_cmd_trdid_fifo.init();
+        m_dma_cmd_pktid_fifo.init();
+        m_dma_cmd_be_fifo.init();
+        m_dma_cmd_cmd_fifo.init();
+        m_dma_cmd_contig_fifo.init();
+        m_dma_cmd_data_fifo.init();
+        m_dma_cmd_eop_fifo.init();
+        m_dma_cmd_cons_fifo.init();
+        m_dma_cmd_plen_fifo.init();
+        m_dma_cmd_wrap_fifo.init();
+        m_dma_cmd_cfixed_fifo.init();
+        m_dma_cmd_clen_fifo.init();
+        
+        m_dma_rsp_rsrcid_fifo.init();
+        m_dma_rsp_rtrdid_fifo.init();
+        m_dma_rsp_rpktid_fifo.init();
+        m_dma_rsp_data_fifo.init();
+        m_dma_rsp_rerror_fifo.init();
+        m_dma_rsp_reop_fifo.init();
+        
+        m_config_cmd_addr_fifo.init();
+        m_config_cmd_srcid_fifo.init();
+        m_config_cmd_trdid_fifo.init();
+        m_config_cmd_pktid_fifo.init();
+        m_config_cmd_be_fifo.init();
+        m_config_cmd_cmd_fifo.init();
+        m_config_cmd_contig_fifo.init();
+        m_config_cmd_data_fifo.init();
+        m_config_cmd_eop_fifo.init();
+        m_config_cmd_cons_fifo.init();
+        m_config_cmd_plen_fifo.init();
+        m_config_cmd_wrap_fifo.init();
+        m_config_cmd_cfixed_fifo.init();
+        m_config_cmd_clen_fifo.init();
+        
+        m_config_rsp_rsrcid_fifo.init();
+        m_config_rsp_rtrdid_fifo.init();
+        m_config_rsp_rpktid_fifo.init();
+        m_config_rsp_data_fifo.init();
+        m_config_rsp_rerror_fifo.init();
+        m_config_rsp_reop_fifo.init();
+        
+        m_config_local_rsrcid_fifo.init();
+        m_config_local_rtrdid_fifo.init();
+        m_config_local_rpktid_fifo.init();
+        m_config_local_data_fifo.init();
+        m_config_local_rerror_fifo.init();
+        m_config_local_reop_fifo.init();
+
+        //Communication between DMA_CMD and DMA_RSP
+        r_dma_cmd_rsp_erase_req		=false;
+        r_dma_cmd_error_req         =false;
+        //Communication between DMA_CMD and TLB 
+        r_dma_tlb_req		        =false;
+        r_tlb_dma_untreated		    =false; 
+        //Communication betweeen TLB and CONFIG_CMD
+        r_config_tlb_req		    =false;
+        r_config_tlb_inval_vaddr	=false;
+	    r_dma_tlb_error_req         =false; 
+        r_tlb_error_type            =false;   
+        //Communication between CONFIG_CMD and CONFIG_RSP
+        r_config_cmd_rsp_erase_req  =false;
+        //Communication between TLB_MISS and MISS_INIT 
+        r_tlb_miss_init_req         =false;
+        r_miss_init_error           =false;
+        // Debug variables
+		m_debug_dma_rsp_fsm	        = false;
+		m_debug_dma_cmd_fsm         = false;
+        m_debug_dma_tlb_fsm         = false;
+        m_debug_config_cmd_fsm      = false;
+        m_debug_config_rsp_fsm      = false;
+        m_debug_miss_init_fsm       = false;
+        
+        r_irq_mask              = 0xFFFFFFFF;
+        r_irq_chosen            = 0;
+          
+	    // activity counters
+	    m_cpt_total_cycles      = 0;
+        m_cpt_iotlb_read       = 0;             
+        m_cpt_iotlb_miss       = 0;             
+        m_cpt_iotlbmiss_transaction      = 0;    
+        m_cost_iotlbmiss_transaction      = 0;   
+        
+        m_cpt_trt_dma_full          = 0;
+        m_cpt_trt_dma_full_cost     = 0;
+        m_cpt_trt_config_full          = 0;
+        m_cpt_trt_config_full_cost     = 0;
+
+        for (uint32_t i=0; i<32 ; ++i) m_cpt_fsm_dma_cmd            [i]   = 0;
+        for (uint32_t i=0; i<32 ; ++i) m_cpt_fsm_dma_rsp            [i]   = 0;
+        for (uint32_t i=0; i<32 ; ++i) m_cpt_fsm_dma_tlb            [i]   = 0;
+        for (uint32_t i=0; i<32 ; ++i) m_cpt_fsm_alloc_trt_dma      [i]   = 0;
+        for (uint32_t i=0; i<32 ; ++i) m_cpt_fsm_config_cmd         [i]   = 0;
+        for (uint32_t i=0; i<32 ; ++i) m_cpt_fsm_config_rsp         [i]   = 0;
+        for (uint32_t i=0; i<32 ; ++i) m_cpt_fsm_alloc_trt_config   [i]   = 0;
+        for (uint32_t i=0; i<32 ; ++i) m_cpt_fsm_miss_init          [i]   = 0;
+        return;
+    }
+
+    
+    //bool        miss_unposted      = false;
+    bool        dma_cmd_fifo_put    = false;
+    bool        dma_cmd_fifo_get    = false;
+    bool        dma_rsp_fifo_put    = false; 
+    bool        dma_rsp_fifo_get    = false; 
+    
+    bool        config_cmd_fifo_put = false;
+    bool        config_cmd_fifo_get = false;
+    bool        config_rsp_fifo_put = false;
+    bool        config_rsp_fifo_get = false;
+    bool        config_local_fifo_put = false;
+    bool        config_local_fifo_get = false;
+
+#ifdef INSTRUMENTATION
+    m_cpt_fsm_dma_cmd	        [r_dma_cmd_fsm.read()] ++;
+    m_cpt_fsm_dma_rsp	        [r_dma_rsp_fsm.read() ] ++;
+    m_cpt_fsm_dma_tlb   	    [r_dma_tlb_fsm.read() ] ++;
+    m_cpt_fsm_alloc_trt_dma  	[r_alloc_trt_dma_fsm.read() ] ++;
+    m_cpt_fsm_config_cmd	    [r_config_cmd_fsm.read() ] ++;
+    m_cpt_fsm_config_rsp	    [r_config_rsp_fsm.read() ] ++;
+    m_cpt_fsm_alloc_trt_config  [r_alloc_trt_config_fsm.read() ] ++;
+    m_cpt_fsm_miss_init	        [r_miss_init_fsm.read() ] ++;
+#endif
+
+    m_cpt_total_cycles++;
+
+    m_debug_dma_cmd_fsm        = (m_cpt_total_cycles > m_debug_start_cycle) and m_debug_ok;
+    m_debug_dma_rsp_fsm         = (m_cpt_total_cycles > m_debug_start_cycle) and m_debug_ok;
+    m_debug_dma_tlb_fsm    = (m_cpt_total_cycles > m_debug_start_cycle) and m_debug_ok;
+    m_debug_config_cmd_fsm      = (m_cpt_total_cycles > m_debug_start_cycle) and m_debug_ok;
+    m_debug_config_rsp_fsm     = (m_cpt_total_cycles > m_debug_start_cycle) and m_debug_ok;
+    m_debug_miss_init_fsm       = (m_cpt_total_cycles > m_debug_start_cycle) and m_debug_ok;
+
+    /////////////////////////////////////////////////////////////////////
+    // The DMA_CMD_FSM controls the following ressources:
+    // - r_dma_cmd_fsm
+    // - r_dma_srcid
+    // - r_dma_tlb_req (set)
+    // - r_tlb_dma_untreated (reset)
+    // - r_dma_cmd_rsp_erase_req (set)
+    ///////////////////////////////////////////////////////////////////////////////
+
+    switch( r_dma_cmd_fsm.read() ) 
+    {
+    //////////////
+    case DMA_CMD_IDLE:
+    {
+        // Treats an eventual request from TLB_MISS fsm 
+        // to send a command whose miss treatment is now finished
+        if ( r_tlb_dma_untreated.read() )
+        {
+            r_dma_cmd_fsm    = DMA_CMD_TRT_LOCK;//before posting we must update TRT
+            r_dma_cmd_fsm_save = DMA_CMD_IDLE;
+            r_miss_interrupt = true;
+            break;
+        }
+        // Error during miss treatment
+        else if (r_dma_tlb_error_req.read())
+        {
+            r_iommu_etr     = r_tlb_error_type.read(); 
+            r_iommu_bvar    = r_iotlb_vaddr.read();
+            r_iommu_bad_id  = r_miss_srcid.read();
+            // For DMA_RSP FSM
+            if(r_miss_cmd.read() == vci_param_io::CMD_WRITE) r_dma_error_type = WRITE_ERROR;
+            else r_dma_error_type = READ_ERROR;
+            r_dma_error_trdid   = r_miss_trdid.read(); 
+            r_dma_error_pktid   = r_miss_pktid.read(); 
+ 
+            r_dma_tlb_error_req = false; 
+            r_dma_cmd_fsm   = DMA_CMD_ERROR;
+        }
+
+        if ( p_vci_tgt_dma.cmdval.read() )
+        { 
+            if ( not r_iommu_active.read()) 	// iotlb not activated 
+            {
+                // physical address
+                r_dma_paddr = (paddr_t)p_vci_tgt_dma.address.read();
+                r_dma_cmd_fsm	= DMA_CMD_TRT_LOCK;
+            }
+            else if (r_dma_tlb_fsm.read() == DMA_TLB_IDLE ||
+                     r_dma_tlb_fsm.read() == DMA_TLB_WAIT_TRANSACTION )	  // iotlb activated
+            {
+                paddr_t	paddr;
+
+                
+                // We compute physical address and check access rights :
+                // - If MMU not activated :the physical address is equal to the virtual 
+                //address (identity mapping) and there is no access rights checking
+                // - If MMU activated : cacheability is defined by the C bit in the PTE,
+                //   the physical address is obtained from the TLB, and the access rights are
+                //   defined by the W bit in the PTE.
+
+                paddr_t		iotlb_paddr;
+                pte_info_t  iotlb_flags; 
+                size_t      iotlb_way;  
+                size_t      iotlb_set;
+                paddr_t     iotlb_nline;
+                bool		iotlb_hit   = false;;  
+
+
+#ifdef INSTRUMENTATION
+m_cpt_iotlb_read++;
+#endif
+
+                iotlb_hit = r_iotlb.translate(p_vci_tgt_dma.address.read(),
+                                            &iotlb_paddr,
+                                            &iotlb_flags,
+                                            &iotlb_nline,// unused
+                                            &iotlb_way,	 // unused
+                                            &iotlb_set );// unused
+            
+            
+                if ( iotlb_hit )	// tlb hit
+                { 
+                    paddr       = iotlb_paddr;
+					
+                    // access rights checking 
+                    if ( not iotlb_flags.w and 
+                        (p_vci_tgt_dma.cmd.read() == vci_param_io::CMD_WRITE) ) 
+                    {
+                        r_iommu_etr     = MMU_WRITE_ACCES_VIOLATION;  
+                        r_iommu_bvar    = p_vci_tgt_dma.address.read();
+                        r_iommu_bad_id  = p_vci_tgt_dma.srcid.read();
+                        r_dma_cmd_fsm   = DMA_CMD_ERROR;
+                        // For DMA_RSP
+                        r_dma_error_type    = WRITE_ERROR; 
+                        r_dma_error_trdid   = p_vci_tgt_dma.trdid.read(); 
+                        r_dma_error_pktid   = p_vci_tgt_dma.pktid.read(); 
+#if DEBUG_DMA_CMD
+if( m_debug_dma_cmd_fsm )
+{
+    std::cout << "  <IOB.DMA_CMD_IDLE> HIT in iotlb, but writable violation" << std::endl;
+}
+#endif
+                    break;
+                    }
+
+                    // Physical address registration 
+                    r_dma_paddr   = paddr;			
+                    r_dma_cmd_fsm	= DMA_CMD_TRT_LOCK;
+                }
+                // TLB miss: we enter TLB_MISS treatment sub-fsm
+                else 
+                {
+
+#ifdef INSTRUMENTATION
+m_cpt_iotlb_miss++;
+#endif
+                    if( r_dma_tlb_req.read() || r_tlb_dma_untreated.read() || r_dma_tlb_error_req.read() )
+                    {
+                        // There's already a ongoing request
+                        // or a completed request but not yet put on FIFO.
+                        // We stay blocked
+                        r_dma_cmd_fsm = DMA_CMD_TLB_MISS_WAIT;
+#if DEBUG_DMA_CMD
+if( m_debug_dma_cmd_fsm )
+{
+    std::cout << "  <IOB.DMA_CMD_IDLE> MISS in iotlb. There is a pending request." << std::endl;
+}
+#endif
+                    }
+                    else
+                    {
+                        // We register request virtual address, to be used by DMA_TLB_MISS FSM
+		                r_iotlb_vaddr = p_vci_tgt_dma.address.read();
+                        assert((r_dma_cmd_count.read() == 0)
+                                and "ERROR: TRT counter should be 0");
+                        r_dma_tlb_req   = true;
+                        r_dma_cmd_fsm   = DMA_CMD_TLB_MISS_STORE;
+#if DEBUG_DMA_CMD
+if( m_debug_dma_cmd_fsm )
+{
+    std::cout << "  <IOB.DMA_CMD_IDLE> MISS in iotlb. No pending request." << std::endl;
+}
+#endif
+                    }
+                } // end !hit 
+            } // end if tlb_activated
+        } // end if cmdval
+        break;
+    }
+    /////////////////////////
+    case DMA_CMD_TRT_LOCK:	// Waiting for the lock to modify Transaction Table
+    {
+        if ( r_alloc_trt_dma_fsm.read() == ALLOC_TRT_DMA_CMD ) 
+        {
+
+#if DEBUG_DMA_CMD
+if( m_debug_dma_cmd_fsm )
+{
+    std::cout << "  <IOB.DMA_CMD_TRT_LOCK> Check the TRT" << std::endl;
+}
+#endif
+            size_t 		wok_index = 0;
+            bool 		wok       = !m_transaction_tab_dma.full(wok_index);
+
+            if ( wok ) 	// TRT isn't full. Write the new transaction. 
+            {
+                r_dma_cmd_trt_index = (vci_trdid_t)wok_index;
+                r_dma_cmd_fsm       = DMA_CMD_TRT_SET;
+            } 
+            else 		// wait an empty entry in TRT
+            {
+                r_dma_cmd_rsp_erase_req = true;
+                r_dma_cmd_fsm       = DMA_CMD_TRT_WAIT;
+#if DEBUG_DMA_CMD
+if( m_debug_dma_cmd_fsm )
+{
+    std::cout << "  <IOB.DMA_CMD_TRT_LOCK> TRT is full. Going to TRT_WAIT state" << std::endl;
+}
+#endif
+            
+#ifdef INSTRUMENTATION        
+m_cpt_trt_dma_full++;
+#endif
+            }
+        }
+        break;
+    }
+    ////////////////
+    case DMA_CMD_TRT_WAIT:	// release the lock protecting the transaction tab
+                            // waits that RSP erases an entry 
+    { 
+#ifdef INSTRUMENTATION        
+m_cpt_trt_dma_full_cost++;
+#endif
+        // DMA_RSP will notify an erase action by reseting this register
+        if(!r_dma_cmd_rsp_erase_req.read())
+        {
+            r_dma_cmd_fsm = DMA_CMD_TRT_LOCK; // take the lock again
+        }
+        break;
+    }
+    ////////////////////////
+    case DMA_CMD_TRT_SET:	// register a new transaction in TRT
+    {  
+        if ( r_alloc_trt_dma_fsm.read() == ALLOC_TRT_DMA_CMD ) 
+        {
+            if(r_miss_interrupt.read())
+            {
+                m_transaction_tab_dma.set(r_dma_cmd_trt_index.read(),
+                                      r_miss_srcid.read(), 
+                                      r_miss_trdid.read() );
+                r_dma_cmd_fsm = DMA_CMD_FIFO_MISS_PUT;
+            }
+            else
+            {
+                m_transaction_tab_dma.set(r_dma_cmd_trt_index.read(),
+                                          p_vci_tgt_dma.srcid.read(), 
+                                          p_vci_tgt_dma.trdid.read() );
+                r_dma_cmd_fsm = DMA_CMD_FIFO_PUT;
+            }
+#if DEBUG_DMA_CMD
+if( m_debug_dma_cmd_fsm )
+{
+    std::cout << "  <IOB.DMA_CMD_TRT_SET> Set a new entry in TRT" << std::endl;
+    if(r_miss_interrupt.read()) std::cout << " From the Network " << std::endl;
+    else std::cout << " From miss interruption" << std::endl;
+}
+#endif
+        }
+        break;
+    }  
+    ///////////////////////
+    case DMA_CMD_FIFO_PUT:	 
+    {
+        if ( p_vci_tgt_dma.cmdval && m_dma_cmd_addr_fifo.wok() ) 
+        {
+            dma_cmd_fifo_put = true;
+            //miss_unposted = false;
+            if(  p_vci_tgt_dma.contig )    r_dma_paddr = r_dma_paddr.read() + 4;
+            if(  p_vci_tgt_dma.eop )    r_dma_cmd_fsm = DMA_CMD_IDLE;
+           
+#if DEBUG_DMA_CMD
+if( m_debug_dma_cmd_fsm ) 
+{
+    std::cout << "  <IOB.DMA_CMD_FIFO_PUT> Push into cmd_fifo:" 
+              << " address = " << std::hex << r_dma_paddr.read()
+              << " srcid = " << std::dec << m_srcid_dma
+              << " trdid = " << r_dma_cmd_trt_index.read()
+              << " wdata = " << std::hex << p_vci_tgt_dma.wdata.read()
+              << " be = " << p_vci_tgt_dma.be.read()
+              << " contig = " << p_vci_tgt_dma.contig.read()
+              << " eop = " << std::dec << p_vci_tgt_dma.eop.read() 
+              << " plen = " << std::dec << p_vci_tgt_dma.plen.read() << std::endl;
+}
+#endif
+        }
+        break;
+    }
+    ///////////////////////
+    case DMA_CMD_FIFO_MISS_PUT:	 
+    {
+        if ( m_dma_cmd_addr_fifo.wok() ) 
+        {
+            dma_cmd_fifo_put    = true;
+            //miss_unposted       = true;
+            if( r_miss_contig.read() )    r_miss_paddr = r_miss_paddr.read() + 4;
+            
+            if( r_dma_cmd_count.read() == 1 ) 
+            {
+                r_tlb_dma_untreated = false;
+                r_miss_interrupt = false;
+                r_dma_cmd_fsm = r_dma_cmd_fsm_save.read();
+            }
+            r_dma_cmd_count = r_dma_cmd_count.read() - 1;
+
+#if DEBUG_DMA_CMD
+if( m_debug_dma_cmd_fsm ) 
+{
+    std::cout << "  <IOB.DMA_CMD_FIFO_MISS_PUT> Push into cmd_fifo:" 
+              << " counter = " << std::hex << r_dma_cmd_count.read()
+              << " address = " << std::hex << r_miss_paddr.read()
+              << " srcid = " << std::dec << r_miss_srcid.read()
+              << " trdid = " << r_miss_trdid.read()
+              << " wdata = " << std::hex << r_miss_data
+              << " be = " << r_miss_be
+              << " plen = " << std::dec << r_miss_plen.read() << std::endl;
+}
+#endif
+        }
+        break;
+    }
+    ///////////////////
+    case DMA_CMD_TLB_MISS_WAIT: // to store the miss request there must be 
+                                // neither an ongoing request, nor a unposted finished request
+    {
+        // Treats an eventual request from TLB_MISS fsm 
+        // to send a command whose miss treatment is now finished
+        if ( r_tlb_dma_untreated.read() )
+        {
+            r_dma_cmd_fsm    = DMA_CMD_TRT_LOCK; //before posting we must update TRT
+            r_dma_cmd_fsm_save = DMA_CMD_TLB_MISS_WAIT;
+            r_miss_interrupt = true;
+            break;
+        }
+        // Error during miss treatment
+        else if (r_dma_tlb_error_req.read())
+        {
+            r_iommu_etr     = r_tlb_error_type.read(); 
+            r_iommu_bvar    = r_iotlb_vaddr.read();
+            r_iommu_bad_id  = r_miss_srcid.read();
+            // For DMA_RSP FSM
+            if(r_miss_cmd.read() == vci_param_io::CMD_WRITE) r_dma_error_type = WRITE_ERROR;
+            else r_dma_error_type = READ_ERROR;
+            r_dma_error_trdid   = r_miss_trdid.read(); 
+            r_dma_error_pktid   = r_miss_pktid.read(); 
+ 
+            r_dma_tlb_error_req = false; 
+            r_dma_cmd_fsm   = DMA_CMD_ERROR;
+        }
+
+#ifdef INSTRUMENTATION        
+m_cost_iotlb_miss++;  // Now it represents misses' total blocking cost (not the treatment cost itself)
+#endif
+        else if (not r_dma_tlb_req.read())
+        {
+            r_dma_cmd_fsm   = DMA_CMD_TLB_MISS_STORE;
+            assert((r_dma_cmd_count.read() == 0) and "ERROR: TRT counter should be 0");
+        }
+        break;
+    }
+    ///////////////////
+    case DMA_CMD_TLB_MISS_STORE:
+    {
+        if ( p_vci_tgt_dma.cmdval.read()) 
+        {
+            if(r_dma_cmd_count.read() == 0)
+            {
+                r_miss_cmd = p_vci_tgt_dma.cmd.read();
+                r_miss_contig = p_vci_tgt_dma.contig.read();
+                r_miss_cons = p_vci_tgt_dma.cons.read();
+                r_miss_plen = p_vci_tgt_dma.plen.read();
+                r_miss_wrap = p_vci_tgt_dma.wrap.read();
+                r_miss_cfixed = p_vci_tgt_dma.cfixed.read();
+                r_miss_clen = p_vci_tgt_dma.clen.read();
+                r_miss_srcid = p_vci_tgt_dma.srcid.read();
+                r_miss_trdid = p_vci_tgt_dma.trdid.read();
+                r_miss_pktid = p_vci_tgt_dma.pktid.read();
+                
+//                r_dma_tlb_req   = true;
+            }
+            
+            r_miss_data[r_dma_cmd_count.read()] = p_vci_tgt_dma.wdata.read();
+            r_miss_be[r_dma_cmd_count.read()] = p_vci_tgt_dma.be.read();
+            
+            r_dma_cmd_count = r_dma_cmd_count.read() + 1;
+            
+            if(  p_vci_tgt_dma.eop )  r_dma_cmd_fsm = DMA_CMD_IDLE;
+           
+#if DEBUG_DMA_CMD
+if( m_debug_dma_cmd_fsm ) 
+{
+    std::cout << "  <IOB.DMA_CMD_TLB_MISS_STORE> Storing VCI fields of command that originate the Miss:" 
+              << " counter = " << std::hex << r_dma_cmd_count.read()
+              << " address = " << std::hex << p_vci_tgt_dma.address.read()
+              << " srcid = " << std::dec << p_vci_tgt_dma.srcid.read()
+              << " trdid = " << p_vci_tgt_dma.trdid.read()
+              << " wdata = " << std::hex << p_vci_tgt_dma.wdata.read()
+              << " be = " << p_vci_tgt_dma.be.read()
+              << " plen = " << std::dec << p_vci_tgt_dma.plen.read() << std::endl;
+}
+#endif
+        }
+        break;
+    }
+    ///////////////////
+    case DMA_CMD_ERROR:
+    {
+        // Wait in case of pending request
+        // it isn't the case, generally
+        if(!r_dma_cmd_error_req.read())
+        { 
+            r_dma_cmd_error_req = true; 
+            r_dma_cmd_fsm       = DMA_CMD_IDLE;
+        }
+        break;
+    }
+    } // end switch DMA_CMD_FSM
+
+    /////////////////////////////////////////////////////////////////////
+    // The DMA_RSP_FSM controls the following ressources:
+    // - r_dma_rsp_fsm
+    // - r_dma_cmd_rsp_erase_req (reset) 
+    // - r_fma_error_req (reset)
+    // - 
+    //////////////////////////////////////////////////////////////////////////////
+    switch( r_dma_rsp_fsm.read() ) 
+    {
+    /////////////////////
+    case DMA_RSP_IDLE:
+    {    	
+        // Interruption from DMA_CMD following an error
+        if(r_dma_cmd_error_req.read()) r_dma_rsp_fsm = DMA_RSP_FIFO_ERROR_PUT;
+        
+        if(p_vci_ini_dma.rspval.read()) 
+		{
+			r_dma_rsp_fsm = DMA_RSP_TRT_LOCK;
+		}
+		break;
+    }
+    /////////////////////
+    case DMA_RSP_TRT_LOCK:
+    {    	
+        if ( r_alloc_trt_dma_fsm.read() == ALLOC_TRT_DMA_RSP ) 
+        {
+            
+#if DEBUG_DMA_RSP
+if( m_debug_dma_rsp_fsm )
+{
+    std::cout << "  <IOB.DMA_RSP_TRT_LOCK> Erase entry" << std::endl;
+}
+#endif
+            uint32_t trdid_xram = p_vci_ini_dma.rtrdid.read(); 
+            
+            r_dma_rsrcid = (vci_srcid_t)m_transaction_tab_dma.readSrcid(trdid_xram);
+            r_dma_rtrdid = (vci_trdid_t)m_transaction_tab_dma.readTrdid(trdid_xram);
+            m_transaction_tab_dma.erase(trdid_xram);
+            if (r_dma_cmd_rsp_erase_req.read()) r_dma_cmd_rsp_erase_req = false;
+            r_dma_rsp_fsm       = DMA_RSP_FIFO_PUT;
+        }        
+		break;
+    }
+    //////////////////
+    case DMA_RSP_FIFO_PUT:
+    {
+        if(p_vci_ini_dma.rspval.read() && m_dma_rsp_data_fifo.wok())
+    	{
+            dma_rsp_fifo_put = true;
+            if(p_vci_ini_dma.reop.read())   r_dma_rsp_fsm = DMA_RSP_IDLE;	
+
+#if DEBUG_DMA_RSP
+if( m_debug_dma_rsp_fsm ) 
+{
+    std::cout << "  <IOB.DMA_RSP_FIFO_PUT> Push into rsp_fifo:" 
+              << " rsrcid = " << std::dec << r_dma_rsrcid.read()
+              << " rtrdid = " << r_dma_rtrdid.read()
+              << " rdata = " << std::hex << p_vci_ini_dma.rdata.read()
+    << std::endl;
+}
+#endif
+    			
+    	}
+    	break;
+    }
+    //////////////////
+    case DMA_RSP_FIFO_ERROR_PUT:
+    {
+        if(m_dma_rsp_data_fifo.wok())
+    	{
+            dma_rsp_fifo_put = true;
+            r_dma_rsp_fsm = DMA_RSP_IDLE;	
+
+#if DEBUG_DMA_RSP
+if( m_debug_dma_rsp_fsm ) 
+{
+    std::cout << "  <IOB.DMA_RSP_FIFO_ERROR_PUT> Push into rsp_fifo:" 
+              << " rsrcid = " << std::dec << r_iommu_bad_id.read()
+              << " rtrdid = " << r_dma_error_trdid.read()
+              << " rerror = " << r_dma_error_type.read()
+              << " rdata = " << std::hex << 0
+    << std::endl;
+}
+#endif
+    			
+    	}
+    	break;
+    }
+    } // end switch DMA_RSP_FSM 
+
+    ////////////////////////////////////////////////////////////////////////////
+    // The ALLOC_TRT_DMA fsm allocates the access to the Transaction Table (m_transaction_tab_dma)
+    // with a round robin priority between 2 user FSMs :
+    // - DMA_CMD : to set a new entry
+    // - DMA_RSP : to read and erase an entry
+    // The ressource is always allocated.
+    ////////////////////////////////////////////////////////////////////////////
+    
+    switch ( r_alloc_trt_dma_fsm.read() ) 
+    {
+    ///////////////////
+    case ALLOC_TRT_DMA_CMD:
+    {
+        if ( r_dma_cmd_fsm.read() != DMA_CMD_TRT_LOCK ) 
+        {
+          if (r_dma_rsp_fsm.read() == DMA_RSP_TRT_LOCK) r_alloc_trt_dma_fsm = ALLOC_TRT_DMA_RSP;
+        }
+        break;
+    }
+    ///////////////////
+    case ALLOC_TRT_DMA_RSP:
+    {
+        if (r_dma_rsp_fsm.read() != DMA_RSP_TRT_LOCK) 
+        {
+            if (r_dma_cmd_fsm.read() == DMA_CMD_TRT_LOCK) r_alloc_trt_dma_fsm = ALLOC_TRT_DMA_CMD;
+        }
+        break;
+    }
+    } // end switch r_alloc_trt_dma_fsm
+    
+
+    ////////////////////////////////////////////////////////////////////////////
+    // The DMA_TLB_MISS FSM handles an IOTLB miss. It blocks the TGT_FSM.
+    // Input argument is:
+    // - r_iotlb_vaddr
+    // - r_dma_tlb_req (reset)
+    // - r_tlb_miss_init_req (set)
+    // - r_config_tlb_req (reset)
+    // - r_tlb_dma_untreated (set)
+    // 
+    // This fsm searchs the requested PTE on the  prefetch buffer.
+    // In case of miss,  it accesses the XRAM to find the missing TLB entry,
+    // It bypass the first level page table access if possible.
+    // It directly updates the iotlb, and writes into the 
+    // r_mmu_ins_* or r_mmu_data* error reporting registers.
+    ////////////////////////////////////////////////////////////////////////////////////
+    switch (r_dma_tlb_fsm.read())
+    {
+    case DMA_TLB_IDLE:
+    {
+        if(r_config_tlb_req)
+        {
+            r_config_tlb_req = false;
+            r_waiting_transaction = false;
+            r_dma_tlb_fsm = DMA_TLB_INVAL_CHECK;
+        // Request from CONFIG FSM following an PTE invalidation signal by OS
+        }
+        // Miss in IOTLB
+        else if(r_dma_tlb_req.read())   
+        {
+        // Checking prefetch buffer, by the virtual address
+        if(!r_miss_buf_first_level)
+        {
+            if( r_miss_buf_valid &&
+                (r_miss_buf_vaddr_begin.read() == 
+                (r_iotlb_vaddr.read()& ~PTE2_LINE_OFFSET & ~K_PAGE_OFFSET_MASK)))
+            {
+              // Hit
+                size_t pte_offset = (r_iotlb_vaddr.read()& PTE2_LINE_OFFSET)>>12; 
+              
+
+                uint32_t pte_flags = r_miss_buf_data[2*pte_offset];
+                uint32_t pte_ppn = r_miss_buf_data[2*pte_offset+1]; //because PTE2 is 2 words long
+                
+                // Bit valid checking
+                if ( not ( pte_flags & PTE_V_MASK) )	// unmapped
+                {
+                    //must not occur!
+                    std::cout << "IOMMU ERROR : " << name() << " DMA_TLB_IDLE state" << std::endl
+                                  << "The Page Table entry ins't valid (unmapped)" << std::endl;
+                       
+                    r_tlb_error_type          = MMU_READ_PT2_UNMAPPED;
+                    r_dma_tlb_error_req       = true;
+                    r_dma_tlb_req             = false;
+                        
+#if DEBUG_DMA_TLB
+if ( m_debug_dma_tlb_fsm )
+{
+    std::cout << "  <IOB.DMA_TLB_IDLE> PTE2 Unmapped"
+              << std::hex << " / paddr = " << r_iotlb_paddr.read()
+              << std::hex << " / PTE (first word) = " << pte_flags << std::endl;
+}
+#endif
+                    break; 
+                }
+
+                r_iotlb_pte_flags       = pte_flags; 
+                r_iotlb_pte_ppn         = pte_ppn;
+                r_dma_tlb_fsm           = DMA_TLB_PTE2_SELECT;
+                
+#if DEBUG_DMA_TLB
+if ( m_debug_dma_tlb_fsm )
+{
+    std::cout << "  <IOB.DMA_TLB_IDLE> Hit on the prefetch buffer for PTE2:"
+              << " PTE_FLAGS = " << std::hex << pte_flags 
+              << " PTE_PPN = " << std::hex << pte_ppn << std::endl;
+}
+#endif
+                break;    
+            }
+        }
+        else    // First level entries on buffer. Unused if only small pages
+        {
+           if( r_miss_buf_valid &&
+              (r_miss_buf_vaddr_begin.read() == 
+               (r_iotlb_vaddr.read()& ~PTE1_LINE_OFFSET & ~M_PAGE_OFFSET_MASK ))) 
+            // The virtual address corresponds to one entry on the buffer line
+            {
+              // Hit
+                size_t pte_offset = (r_iotlb_vaddr.read()& PTE1_LINE_OFFSET)>>21; 
+              
+                uint32_t pte_flags = r_miss_buf_data[pte_offset];
+                            
+                // Bit valid checking
+                if ( not ( pte_flags & PTE_V_MASK) )	// unmapped
+                {
+                    //must not occur!
+                    std::cout << "IOMMU ERROR " << name() << "DMA_TLB_IDLE state" << std::endl
+                                  << "The Page Table entry ins't valid (unmapped)" << std::endl;
+                       
+                    r_tlb_error_type          = MMU_READ_PT1_UNMAPPED;
+                    r_dma_tlb_error_req       = true;
+                    r_dma_tlb_req             = false;
+                        
+#if DEBUG_DMA_TLB
+if ( m_debug_dma_tlb_fsm )
+{
+    std::cout << "  <IOB.DMA_TLB_IDLE> First level entry Unmapped"
+              << std::hex << " / paddr = " << r_iotlb_paddr.read()
+              << std::hex << " / PTE = " << pte_flags << std::endl;
+}
+#endif
+                    break; 
+                }
+                
+                if( pte_flags & PTE_T_MASK ) 	//  PTD : me must access PT2
+                {
+                    // register bypass
+                    r_iotlb.set_bypass( r_iotlb_vaddr.read(),
+                                      pte_flags & ((1 << (m_paddr_nbits-PAGE_K_NBITS)) - 1), 
+                                     0); //nline, unused 
+
+                    //&PTE2 = PTBA + IX2 * 8
+                    // ps: PAGE_K_NBITS corresponds also to the size of a second level page table
+                    r_iotlb_paddr = (paddr_t)(pte_flags & ((1<<(m_paddr_nbits-PAGE_K_NBITS))-1)) << PAGE_K_NBITS |
+                                  (paddr_t)(((r_iotlb_vaddr.read() & PTD_ID2_MASK) >> PAGE_K_NBITS) << 3);
+                    r_tlb_miss_init_req     = true;
+                    r_tlb_miss_type         = PTE2_MISS;
+                    r_dma_tlb_fsm           = DMA_TLB_WAIT_TRANSACTION;
+#ifdef INSTRUMENTATION
+m_cpt_iotlbmiss_transaction++;
+#endif
+
+#if DEBUG_DMA_TLB
+if ( m_debug_dma_tlb_fsm )
+{
+    std::cout << "  <IOB.DMA_TLB_IDLE> Hit on prefetch, but it is a PTD.Search PTE2"
+              << std::hex << " / paddr = " << r_iotlb_paddr.read()
+              << std::hex << " / PTD = " << pte_flags << std::endl;
+}
+#endif
+                }
+                else			//  PTE1 :  we must update the TLB
+                            //  Should not occur if working only with small pages
+                {
+                    r_iotlb_pte_flags   = pte_flags;
+                    r_dma_tlb_fsm  = DMA_TLB_PTE1_SELECT;
+
+#if DEBUG_DMA_TLB
+if ( m_debug_dma_tlb_fsm )
+{
+    std::cout << "  <IOB.DMA_TLB_PTE1_GET> Success. Big page"
+              << std::hex << " / paddr = " << r_iotlb_paddr.read()
+              << std::hex << " / PTE1 = " << pte_flags << std::endl;
+}
+#endif
+                }
+                break;
+            }
+        }
+       
+        r_dma_tlb_fsm = DMA_TLB_MISS; 
+
+#if DEBUG_DMA_TLB
+if ( m_debug_dma_tlb_fsm )
+{
+    std::cout << "  <IOB.DMA_TLB_IDLE> Miss on prefetch."
+              << std::hex << " / vaddr = " << r_iotlb_vaddr.read() << std::endl;
+}
+#endif
+        }
+        break;
+    }
+    /////////////////////
+    case DMA_TLB_MISS: // handling all tlb miss
+    {
+        uint32_t	ptba = 0; //28 bits en TSAR
+        bool		bypass;
+        paddr_t		pte_paddr;
+
+        // evaluate bypass in order to skip first level page table access
+        bypass = r_iotlb.get_bypass(r_iotlb_vaddr.read(), &ptba);
+        
+        //Request to MISS_INIT_FSM to start transaction on Direct Network       
+        if ( not bypass )     // Read PTE1/PTD1 in XRAM
+        {
+        // VOIR CONVENTION >> 13
+            pte_paddr = (paddr_t)((r_iommu_ptpr.read()) << (INDEX1_NBITS+2)) |
+                        (paddr_t)((r_iotlb_vaddr.read() >> PAGE_M_NBITS) << 2);
+            r_iotlb_paddr = pte_paddr;
+            
+            r_tlb_miss_init_req     = true;
+            r_tlb_miss_type         = PTE1_MISS;
+            r_dma_tlb_fsm           = DMA_TLB_WAIT_TRANSACTION;
+#ifdef INSTRUMENTATION
+m_cpt_iotlbmiss_transaction++;
+#endif
+        }
+        else                  // Read PTE2 in XRAM
+        {
+            //&PTE2 = PTBA + IX2 * 8
+            pte_paddr = (paddr_t)ptba << PAGE_K_NBITS |
+                        (paddr_t)(r_iotlb_vaddr.read()&PTD_ID2_MASK)>>(PAGE_K_NBITS-3);
+            
+            r_iotlb_paddr = pte_paddr;
+            
+            r_tlb_miss_init_req     = true;
+            r_tlb_miss_type         = PTE2_MISS;
+            r_dma_tlb_fsm           = DMA_TLB_WAIT_TRANSACTION;
+#ifdef INSTRUMENTATION
+m_cpt_iotlbmiss_transaction++;
+#endif
+        }
+
+#if DEBUG_DMA_TLB
+if ( m_debug_dma_tlb_fsm )
+{
+    std::cout << "  <IOB.DMA_TLB_MISS> IOTLB miss";
+    std::cout << " / VADDR = " << std::hex << r_iotlb_vaddr.read()
+              << " / BYPASS = " << bypass 
+              << " / PTE_ADR = " << pte_paddr << std::endl;
+}
+#endif
+  
+        break;
+    }
+    /////////////////////////  
+    case DMA_TLB_PTE1_GET:	// Try to read a PT1 entry in the miss buffer
+    {
+        
+        uint32_t  entry;
+        
+        paddr_t line_number  = (paddr_t)((r_iotlb_paddr.read())&(CACHE_LINE_MASK));
+        size_t word_position = (size_t)( ((r_iotlb_paddr.read())&(~CACHE_LINE_MASK))>>2 );
+
+        // Hit test. Just to verify. 
+        // Hit must happen, since we've just finished its' miss transaction
+        bool hit = (r_miss_buf_valid && (r_miss_buf_tag.read()== line_number) ); 
+        assert(hit and "Error: No hit on prefetch buffer after Miss Transaction"); 
+        
+        entry = r_miss_buf_data[word_position];
+            
+        // Bit valid checking
+        if ( not ( entry & PTE_V_MASK) )	// unmapped
+        {
+            //must not occur!
+            std::cout << "IOMMU ERROR " << name() << "DMA_TLB_IDLE state" << std::endl
+                      << "The Page Table entry ins't valid (unmapped)" << std::endl;
+                       
+            r_tlb_error_type          = MMU_READ_PT1_UNMAPPED;
+            r_dma_tlb_error_req       = true;
+            r_dma_tlb_req             = false;
+            r_dma_tlb_fsm             = DMA_TLB_IDLE;            
+#if DEBUG_DMA_TLB
+if ( m_debug_dma_tlb_fsm )
+{
+    std::cout << "  <IOB.DMA_PTE1_GET> First level entry Unmapped"
+              << std::hex << " / paddr = " << r_iotlb_paddr.read()
+              << std::hex << " / PTE = " << entry << std::endl;
+}
+#endif
+                    break; 
+        }
+    
+        if( entry & PTE_T_MASK ) 	//  PTD : me must access PT2
+        {
+            // register bypass
+            r_iotlb.set_bypass( r_iotlb_vaddr.read(),
+                                entry & ((1 << (m_paddr_nbits-PAGE_K_NBITS)) - 1), 
+                                0); //nline, unused 
+
+            //&PTE2 = PTBA + IX2 * 8
+            // ps: PAGE_K_NBITS corresponds also to the size of a second level page table
+            r_iotlb_paddr = (paddr_t)(entry & ((1<<(m_paddr_nbits-PAGE_K_NBITS))-1)) << PAGE_K_NBITS |
+                                (paddr_t)(((r_iotlb_vaddr.read() & PTD_ID2_MASK) >> PAGE_K_NBITS) << 3);
+            r_tlb_miss_init_req     = true;
+            r_tlb_miss_type         = PTE2_MISS;
+            r_dma_tlb_fsm           = DMA_TLB_WAIT_TRANSACTION;
+#ifdef INSTRUMENTATION
+m_cpt_iotlbmiss_transaction++;
+#endif
+
+#if DEBUG_DMA_TLB
+if ( m_debug_dma_tlb_fsm )
+{
+    std::cout << "  <IOB.DMA_TLB_PTE1_GET> Success. Search PTE2"
+              << std::hex << " / paddr = " << r_iotlb_paddr.read()
+              << std::hex << " / PTD = " << entry << std::endl;
+}
+#endif
+        }
+        else			//  PTE1 :  we must update the IOTLB
+                        //  Should not occur if working only with small pages
+        {
+            r_iotlb_pte_flags   = entry;
+            r_dma_tlb_fsm  = DMA_TLB_PTE1_SELECT;
+
+#if DEBUG_DMA_TLB
+if ( m_debug_dma_tlb_fsm )
+{
+    std::cout << "  <IOB.DMA_TLB_PTE1_GET> Success. Big page"
+              << std::hex << " / paddr = " << r_iotlb_paddr.read()
+              << std::hex << " / PTE1 = " << entry << std::endl;
+}
+#endif
+        }
+        
+        break;
+    }
+    ////////////////////////////
+    case DMA_TLB_PTE1_SELECT:	// select a slot for PTE1 
+    {
+        size_t 	way;
+        size_t 	set;
+        
+        r_iotlb.select(  r_iotlb_vaddr.read(),
+                        true,  // PTE1 
+                        &way,
+                        &set );
+#ifdef INSTRUMENTATION
+m_cpt_iotlb_read++;
+#endif
+
+#if DEBUG_DMA_TLB
+if ( m_debug_dma_tlb_fsm )
+{
+    std::cout << "  <IOB.DMA_TLB_PTE1_SELECT> Select a slot in IOTLB:";
+    std::cout << " way = " << std::dec << way
+                  << " / set = " << set << std::endl;
+}
+#endif
+        r_iotlb_way = way;
+        r_iotlb_set = set;
+        r_dma_tlb_fsm     = DMA_TLB_PTE1_UPDT;
+        break;
+    }
+    //////////////////////////
+    case DMA_TLB_PTE1_UPDT:     // write a new PTE1 in tlb
+                                // not necessary to treat the L/R bit
+    {
+        //(OLD) paddr_t	  nline = r_dcache_tlb_paddr.read() >> (uint32_log2(m_dcache_words)+2);   
+        uint32_t  pte   = r_iotlb_pte_flags.read();
+        
+        r_miss_paddr = (paddr_t)( ((r_iotlb_pte_flags.read() & PPN1_MASK) << 21)
+                        | (r_iotlb_vaddr.read()& M_PAGE_OFFSET_MASK) );
+        
+        // update TLB
+        r_iotlb.write( true,		// 2M page
+                      pte,
+                      0,		// argument unused for a PTE1
+                      r_iotlb_vaddr.read(),    
+                      r_iotlb_way.read(), 
+                      r_iotlb_set.read(),
+                      0 );      //we set nline = 0
+#ifdef INSTRUMENTATION
+m_cpt_iotlb_write++;
+#endif
+
+#if DEBUG_DMA_TLB
+if ( m_debug_dma_tlb_fsm )
+{
+    std::cout   << "  <IOB.DMA_TLB_PTE1_UPDT> write PTE1 in IOTLB";
+    std::cout   << " / set = " << std::dec << r_iotlb_set.read()
+                << " / way = " << r_iotlb_way.read() << std::endl;
+    r_iotlb.printTrace();
+}
+#endif
+        // next state
+        r_dma_tlb_fsm = DMA_TLB_RETURN;	// exit sub-fsm
+        break;
+    }
+    /////////////////////////
+    case DMA_TLB_PTE2_GET:	// Try to read a PTE2 (64 bits) in the miss buffer
+    {    
+        uint32_t 	pte_flags;
+        uint32_t 	pte_ppn;
+        
+        paddr_t line_number  = (paddr_t)((r_iotlb_paddr.read())&(CACHE_LINE_MASK));
+        size_t word_position = (size_t)( ((r_iotlb_paddr.read())&(~CACHE_LINE_MASK))>>2 );
+        
+        
+        // Hit test. Just to verify.
+        bool hit = (r_miss_buf_valid && (r_miss_buf_tag.read()== line_number) ); 
+        assert(hit and "Error: No hit on prefetch buffer after Miss Transaction"); 
+        pte_flags= r_miss_buf_data[word_position];
+        pte_ppn= r_miss_buf_data[word_position+1]; //because PTE2 is 2 words long
+        // Bit valid checking
+        if ( not ( pte_flags & PTE_V_MASK) )	// unmapped
+        {
+            //must not occur!
+            std::cout << "IOMMU ERROR " << name() << "DMA_TLB_IDLE state" << std::endl
+                      << "The Page Table entry ins't valid (unmapped)" << std::endl;
+                       
+            r_tlb_error_type          = MMU_READ_PT2_UNMAPPED;
+            r_dma_tlb_error_req       = true;
+            r_dma_tlb_req             = false;
+            r_dma_tlb_fsm             = DMA_TLB_IDLE;            
+#if DEBUG_DMA_TLB
+if ( m_debug_dma_tlb_fsm )
+{
+    std::cout << "  <IOB.DMA_TLB_PTE2_GET> PTE2 Unmapped"
+              << std::hex << " / paddr = " << r_iotlb_paddr.read()
+              << std::hex << " / PTE = " << pte_flags << std::endl;
+}
+#endif
+                    break; 
+        }
+            
+        r_iotlb_pte_flags       = pte_flags; 
+        r_iotlb_pte_ppn         = pte_ppn;
+        r_dma_tlb_fsm           = DMA_TLB_PTE2_SELECT;
+                
+#if DEBUG_DMA_TLB
+if ( m_debug_dma_tlb_fsm )
+{
+    std::cout << "  <IOB.DMA_TLB_PTE2_GET> Mapped:"
+              << " PTE_FLAGS = " << std::hex << pte_flags 
+              << " PTE_PPN = " << std::hex << pte_ppn << std::endl;
+}
+#endif
+        break;
+    }
+    ////////////////////////////
+    case DMA_TLB_PTE2_SELECT:    // select a slot for PTE2
+    {
+        size_t way;
+        size_t set;
+
+        r_iotlb.select( r_iotlb_vaddr.read(),
+                        false,	// PTE2 
+                        &way,
+                        &set );
+#ifdef INSTRUMENTATION
+m_cpt_iotlb_read++;
+#endif
+
+#if DEBUG_DMA_TLB
+if ( m_debug_dma_tlb_fsm )
+{
+        std::cout << "  <IOB.DMA_TLB_PTE2_SELECT> Select a slot in IOTLB:";
+        std::cout << " way = " << std::dec << way
+                  << " / set = " << set << std::endl;
+}
+#endif
+        r_iotlb_way = way;
+        r_iotlb_set = set;
+        r_dma_tlb_fsm     = DMA_TLB_PTE2_UPDT;
+        break;
+    }
+    //////////////////////////
+    case DMA_TLB_PTE2_UPDT:      	// write a new PTE2 in tlb
+                                    // not necessary to treat the L/R bit
+    {
+        //(OLD) paddr_t	        nline     = r_dcache_tlb_paddr.read() >> (uint32_log2(m_dcache_words)+2);   
+        uint32_t        pte_flags = r_iotlb_pte_flags.read();
+        uint32_t        pte_ppn   = r_iotlb_pte_ppn.read();
+        
+        r_miss_paddr = (paddr_t)( ((r_iotlb_pte_ppn.read() & PPN2_MASK) << 12)
+                        | (r_iotlb_vaddr.read()& K_PAGE_OFFSET_MASK) );
+        
+        // update TLB for a PTE2
+        r_iotlb.write( false,	// 4K page
+                       pte_flags,
+                       pte_ppn,
+                       r_iotlb_vaddr.read(),    
+                       r_iotlb_way.read(), 
+                       r_iotlb_set.read(),
+                       0 );     // nline = 0
+#ifdef INSTRUMENTATION
+m_cpt_iotlb_write++;
+#endif
+
+#if DEBUG_DMA_TLB
+if ( m_debug_dma_tlb_fsm )
+{
+        std::cout << "  <IOB.DMA_TLB_PTE2_UPDT> write PTE2 in IOTLB";
+        std::cout << " / set = " << std::dec << r_iotlb_set.read()
+                  << " / way = " << r_iotlb_way.read() << std::endl;
+        r_iotlb.printTrace();
+}
+#endif
+        // next state
+        r_dma_tlb_fsm = DMA_TLB_RETURN;	// exit sub-fsm
+        break;
+    }
+    ///////////////////////
+    case DMA_TLB_WAIT_TRANSACTION:
+    {
+        // CONFIG FSM request following a invalidation signal sent by OS.
+        if(r_config_tlb_req)
+        {
+            r_config_tlb_req = false;
+            r_waiting_transaction = true;
+            r_dma_tlb_fsm = DMA_TLB_INVAL_CHECK;
+        }
+
+#ifdef INSTRUMENTATION
+m_cost_iotlbmiss_transaction++;
+#endif
+        if ( not r_tlb_miss_init_req )	//  Miss transaction is done 
+        { 
+	        if ( r_miss_init_error.read() ) // bus error 
+	        {
+                r_miss_init_error  = false;
+                r_tlb_error_type    = MMU_READ_DATA_ILLEGAL_ACCESS;
+                r_dma_tlb_error_req     = true;
+                r_dma_tlb_req           = false;
+                r_dma_tlb_fsm = DMA_TLB_IDLE;
+            }
+            else if(r_tlb_miss_type == PTE1_MISS)
+            {
+                r_dma_tlb_fsm = DMA_TLB_PTE1_GET; 
+        
+            }
+            else
+            {
+                r_dma_tlb_fsm = DMA_TLB_PTE2_GET;
+            }
+        }
+        break;
+    }
+    ///////////////////////
+    case DMA_TLB_RETURN:		// return to caller depending on tlb miss type
+    {
+#if DEBUG_DMA_TLB
+if ( m_debug_dma_tlb_fsm )
+{
+    std::cout << "  <IOB.DMA_TLB_RETURN> IOTLB MISS completed" << std::endl;
+}
+#endif
+        r_dma_tlb_req = false;
+        r_tlb_dma_untreated = true;
+        r_dma_tlb_fsm = DMA_TLB_IDLE;
+        break;
+    }
+    //////////////////////
+    case DMA_TLB_INVAL_CHECK:   // request from CONFIG FSM to invalidate all PTE on a given line
+                                // This state checks the necessity to invalidate prefetch buffer
+    {
+        // If a transaction is pending, no need to invalidate the prefetch
+        // We can ignore it, since we'll replace the line.
+        // The new line is necessarily up-to-date
+        if(!r_waiting_transaction.read() && r_miss_buf_valid)
+        {
+            if(!r_miss_buf_first_level)
+            {
+               if( r_miss_buf_vaddr_begin.read() == 
+                   (r_config_tlb_inval_vaddr.read()& ~PTE2_LINE_OFFSET) ) 
+                // The virtual address corresponds to one entry on the buffer line
+                {
+                    r_miss_buf_valid = false;   //change here for individual invalidation
+                }
+            }
+            else    // First level entries on buffer. Unused if only small pages
+            {
+               if( r_miss_buf_vaddr_begin.read() == 
+                   (r_config_tlb_inval_vaddr.read()& ~PTE1_LINE_OFFSET) ) 
+                // The virtual address corresponds to one entry on the buffer line
+                {
+                    r_miss_buf_valid = false;   //change here for individual invalidation
+                }
+            }
+        }
+        
+        // Invalidation on IOTLB
+        bool    ok;
+        ok = r_iotlb.inval(r_config_tlb_inval_vaddr.read());
+         
+        if(r_waiting_transaction.read()) r_dma_tlb_fsm =DMA_TLB_WAIT_TRANSACTION; 
+        else r_dma_tlb_fsm = DMA_TLB_IDLE;
+        break; 
+    }
+    } //end switch r_dma_tlb_fsm
+    
+    
+    /////////////////////////////////////////////////////////////////////
+    // The CONFIG_CMD_FSM is similar to the DMA_CMD_FSM, but without miss TLB treatmentcontrols the following ressources:
+    // - r_config_cmd_fsm
+    //
+    // - r_config_cmd_rsp_erase_req (set)
+    // - r_config_tlb_req (set)
+    /////////////////////////////////////////////////////////////////////
+
+    switch( r_config_cmd_fsm.read() ) 
+    {
+    //////////////
+    case CONFIG_CMD_IDLE:
+    {
+        if ( p_vci_tgt_config.cmdval.read() ) 
+        {
+#if DEBUG_CONFIG_CMD
+if( m_debug_config_cmd_fsm )
+{
+    std::cout << "  <IOB.CONFIG_CMD_IDLE> Configuration command received!" <<std::endl;
+    std::cout << " address = " << std::hex << p_vci_tgt_config.address.read()
+              << " srcid = " << std::dec << p_vci_tgt_config.srcid.read()
+              << " trdid = " << p_vci_tgt_config.trdid.read()
+              << " wdata = " << std::hex << p_vci_tgt_config.wdata.read()
+              << " be = " << p_vci_tgt_config.be.read()
+              << " plen = " << std::dec << p_vci_tgt_config.plen.read() << std::endl;
+}
+#endif
+            paddr_t config_paddr = p_vci_tgt_config.address.read();
+   
+//           // Just to verify 
+//           if(! m_locality_table_config[config_paddr] ) //cannot receive remote packets
+//           {
+//           std::cout << "IOB ERROR " << name() << " CONFIG_CMD_IDLE state" << std::endl
+//                         << "Received a remote packet" << std::endl;
+//               exit(0);
+//           }
+
+            bool read = (p_vci_tgt_config.cmd.read() == vci_param_d::CMD_READ);
+            
+            uint32_t              cell    = (uint32_t)((config_paddr & 0x1FF)>>2); 
+            
+            // Treatement of received command
+            // Verifies error, tests if the the command is for IOB itself 
+ 
+            // To IOB itself
+            if(m_segment_config.contains(config_paddr))
+            {
+                if(!read && (cell == IOB_IOMMU_PTPR)) 
+                    r_config_cmd_fsm = CONFIG_CMD_PTPR_WRITE;
+                else if(read && (cell == IOB_IOMMU_PTPR)) 
+                    r_config_cmd_fsm = CONFIG_CMD_PTPR_READ;
+                else if(!read && (cell == IOB_IOMMU_ACTIVE)) 
+                    r_config_cmd_fsm = CONFIG_CMD_ACTIVE_WRITE;
+                else if(read && (cell == IOB_IOMMU_ACTIVE)) 
+                    r_config_cmd_fsm = CONFIG_CMD_ACTIVE_READ;
+                else if(read && (cell == IOB_IOMMU_BVAR)) 
+                    r_config_cmd_fsm = CONFIG_CMD_BVAR_READ;
+                else if(read && (cell == IOB_IOMMU_ETR)) 
+                    r_config_cmd_fsm = CONFIG_CMD_ETR_READ;
+                else if(read && (cell == IOB_IOMMU_BAD_ID)) 
+                    r_config_cmd_fsm = CONFIG_CMD_BAD_ID_READ;
+                // PTE invalidation signaled by the OS
+                else if(!read && (cell == IOB_INVAL_PTE))
+                    r_config_cmd_fsm = CONFIG_CMD_INVAL_REQ;
+                else if(!read && (cell == IOB_IT_ADDR_IOMMU_LO)) 
+                    r_config_cmd_fsm = CONFIG_CMD_IT_ADDR_IOMMU_WRITE_1;
+                else if(read && (cell == IOB_IT_ADDR_IOMMU_LO)) 
+                    r_config_cmd_fsm = CONFIG_CMD_IT_ADDR_IOMMU_READ_1;
+                else if( !read && ((cell >= IOB_IT_ADDR_BEGIN)&&
+                        ( cell< (IOB_IT_ADDR_BEGIN +2*m_nb_periph-1) ) ) )
+                {
+                    // a factor two shows up because the registres come in couples
+                    r_it_index = (cell - IOB_IT_ADDR_BEGIN)/2;
+                    r_config_cmd_fsm = CONFIG_CMD_IT_ADDR_WRITE_1;
+                } 
+                else if( read && ((cell >= IOB_IT_ADDR_BEGIN)&&
+                        (cell< (IOB_IT_ADDR_BEGIN +2*m_nb_periph-1))) ) 
+                {
+                    r_it_index = (cell - IOB_IT_ADDR_BEGIN)/2;
+                    r_config_cmd_fsm = CONFIG_CMD_IT_ADDR_READ_1;
+                }
+                else
+                //Error. Wrong address, or invalid operation.
+                {
+                    if(read)    r_config_error_type = READ_ERROR;
+                    else        r_config_error_type = WRITE_ERROR;
+                    r_config_cmd_fsm = CONFIG_CMD_ERROR_WAIT; 
+                }
+            }
+            // Must route the command to the correct IO
+            else
+            {
+                if(!p_vci_tgt_config.eop.read())
+                {
+                    //Error
+                    if(read)    r_config_error_type = READ_ERROR;
+                    else        r_config_error_type = WRITE_ERROR;
+                    r_config_cmd_fsm = CONFIG_CMD_ERROR_WAIT; 
+                }
+                
+                // Find the corresponding address on IO Space
+//                int tgt_index = m_routing_table_config[config_paddr];
+//#if DEBUG_CONFIG_CMD
+//if( m_debug_config_cmd_fsm )
+//{
+//    std::cout << "  <IOB.CONFIG_CMD_IDLE> Routing a configuration packet" <<std::endl
+//            << "Target Index on Direct NoC: " << tgt_index << std::endl;
+//}
+//#endif
+//                soclib::common::Segment io_segment = m_mtio.getSegment(IntTab(tgt_index));
+//               #define L2 soclib::common::uint32_log2 
+//               paddr_t offset_mask = ( (1 << L2(io_segment.size())) - 1);
+//               #undef L2
+//               r_config_vaddr = (vaddr_t)( io_segment.baseAddress() | 
+//                               (vaddr_t)(config_paddr & offset_mask) ); 
+                
+                // TODO So far, it is in identity mapping
+                r_config_vaddr = (vaddr_t) config_paddr ; 
+                r_config_cmd_fsm	= CONFIG_CMD_TRT_LOCK;
+
+            }
+
+
+        } // end if cmdval
+        break;
+    }
+    /////////////////////////
+    case CONFIG_CMD_TRT_LOCK: // Waiting for the lock to modify Transaction Table
+    {
+        if ( r_alloc_trt_config_fsm.read() == ALLOC_TRT_CONFIG_CMD ) 
+        {
+
+#if DEBUG_CONFIG_CMD
+if( m_debug_config_cmd_fsm )
+{
+    std::cout << "  <IOB.CONFIG_CMD_TRT_LOCK> Check the TRT" << std::endl;
+}
+#endif
+            size_t 		wok_index = 0;
+            bool 		wok       = !m_transaction_tab_config.full(wok_index);
+
+            if ( wok ) 	// TRT isn't full. Write the new transaction. 
+            {
+                r_config_cmd_trt_index = (vci_trdid_t)wok_index;
+                r_config_cmd_fsm       = CONFIG_CMD_TRT_SET;
+            } 
+            else 		// wait an empty entry in TRT
+            {
+                r_config_cmd_fsm       = CONFIG_CMD_TRT_WAIT;
+                r_config_cmd_rsp_erase_req = true;
+#if DEBUG_CONFIG_CMD
+if( m_debug_config_cmd_fsm )
+{
+    std::cout << "  <IOB.CONFIG_CMD_TRT_LOCK> TRT is full. Going to TRT_WAIT state" << std::endl;
+}
+#endif
+            
+#ifdef INSTRUMENTATION        
+m_cpt_trt_config_full++;
+#endif
+            }
+        }
+        break;
+    }
+    ////////////////
+    case CONFIG_CMD_TRT_WAIT:	// release the lock protecting the transaction tab
+                                // waits that RSP erases an entry 
+    { 
+#ifdef INSTRUMENTATION        
+m_cpt_trt_config_full_cost++;
+#endif
+        // CONFIG_RSP will notify an erase action by reseting this register
+        if(!r_config_cmd_rsp_erase_req.read())
+        {
+            r_config_cmd_fsm = CONFIG_CMD_TRT_LOCK; // take the lock again
+        }
+        break;
+    }
+    ////////////////////////
+    case CONFIG_CMD_TRT_SET:	// register a new transaction in TRT
+    {  
+        if ( r_alloc_trt_config_fsm.read() == ALLOC_TRT_CONFIG_CMD ) 
+        {
+            m_transaction_tab_config.set(   r_config_cmd_trt_index.read(),
+                                            p_vci_tgt_config.srcid.read(), 
+                                            p_vci_tgt_config.trdid.read() );
+            
+            r_config_cmd_fsm = CONFIG_CMD_FIFO_PUT;
+#if DEBUG_CONFIG_CMD
+if( m_debug_config_cmd_fsm )
+{
+    std::cout << "  <IOB.CONFIG_CMD_TRT_SET> Set a new entry in TRT" << std::endl;
+}
+#endif
+        }
+        break;
+    }  
+    ///////////////////////
+    case CONFIG_CMD_FIFO_PUT:	 
+    {
+        if ( p_vci_tgt_config.cmdval && m_config_cmd_addr_fifo.wok() ) 
+        {
+            config_cmd_fifo_put = true;
+            if(  p_vci_tgt_config.eop )    r_config_cmd_fsm = CONFIG_CMD_IDLE;
+           
+#if DEBUG_CONFIG_CMD
+if( m_debug_config_cmd_fsm ) 
+{
+    std::cout << "  <IOB.CONFIG_CMD_FIFO_PUT> Push into config_cmd_fifo:" 
+              << " address = " << std::hex << r_config_vaddr.read()
+              << " srcid = " << std::dec << m_srcid_config
+              << " trdid = " << r_config_cmd_trt_index.read()
+              << " wdata = " << std::hex << p_vci_tgt_config.wdata.read()
+              << " be = " << p_vci_tgt_config.be.read()
+              << " plen = " << std::dec << p_vci_tgt_config.plen.read() << std::endl;
+}
+#endif
+        }
+        break;
+    }
+    
+    ///////////////////////////////
+    // Private Configuration States
+    ///////////////////////////////
+
+    //////////////////
+    case CONFIG_CMD_PTPR_WRITE: // Convention- The word received is in the format:
+                                // 00000 BASE_ADDRESS[39:13]
+                                // Same pattern as in iommu_ptpr register
+    {
+        if ( p_vci_tgt_config.cmdval.read() && m_config_local_data_fifo.wok()
+            && r_dma_tlb_fsm == DMA_TLB_IDLE )
+        {
+            // This verification could have been done on IDLE state
+            // It would save us one cycle 
+            if ( !p_vci_tgt_config.eop.read() )
+            {
+                std::cout << "CONFIG_CMD ERROR " << name() << " CONFIG_CMD_PTPR_WRITE state" << std::endl;
+                std::cout << " PTPR write command must contain one single flit" << std::endl;
+                r_config_error_type = WRITE_ERROR;
+                r_config_cmd_fsm = CONFIG_CMD_ERROR_WAIT; 
+                break;
+            }
+            
+            // Depends on the convention
+            r_iommu_ptpr = (uint32_t)(p_vci_tgt_config.wdata.read()); 
+            
+            config_local_fifo_put = true;
+            r_config_cmd_fsm = CONFIG_CMD_IDLE;
+
+#if DEBUG_CONFIG_CMD
+if( m_debug_config_cmd_fsm ) 
+{
+    std::cout << "  <IOB.CONFIG_CMD_PTPR_WRITE> PTPR received:" 
+              << "r_iommu_ptpr = " << std::hex << (p_vci_tgt_config.wdata.read())
+              <<std::endl;
+}
+#endif
+        } 
+        break;
+    }
+    /////////////////////
+    case CONFIG_CMD_ACTIVE_WRITE: 
+    {
+        if ( p_vci_tgt_config.cmdval.read() && m_config_local_data_fifo.wok() 
+            && r_dma_tlb_fsm == DMA_TLB_IDLE )
+        {
+            // This verification could have been done on IDLE state
+            // It would save us one cycle 
+            if ( !p_vci_tgt_config.eop.read() )
+            {
+                std::cout << "CONFIG_CMD ERROR " << name() << " CONFIG_CMD_ACTIVE_WRITE state" << std::endl;
+                std::cout << " ACTIVE write command must contain one single flit" << std::endl;
+                r_config_error_type = WRITE_ERROR;
+                r_config_cmd_fsm = CONFIG_CMD_ERROR_WAIT; 
+                break;
+            }
+            
+            r_iommu_active = (p_vci_tgt_config.wdata.read() != 0);
+            
+            config_local_fifo_put = true;
+            r_config_cmd_fsm = CONFIG_CMD_IDLE;
+        } 
+        break;
+    }
+    ///////////////////
+    case CONFIG_CMD_INVAL_REQ: // Blocks in case of untreated request
+    {   
+        if ( !r_config_tlb_req.read() )
+        {
+            r_config_tlb_req = true;     
+            r_config_cmd_fsm = CONFIG_CMD_INVAL;
+        } 
+        break;
+    }
+    ///////////////////
+    case CONFIG_CMD_INVAL: // Consuming the 32bit Virtual Address of the invalidated page
+    {
+        if ( p_vci_tgt_config.cmdval.read() && 
+                m_config_local_data_fifo.wok() ) 
+        {
+            
+            if ( !p_vci_tgt_config.eop.read() )
+            {
+                std::cout << "CONFIG_CMD ERROR " << name() << " CONFIG_CMD_INVAL state" << std::endl;
+                std::cout << " PTE invalidation commands must contain one single flit" << std::endl;
+                r_config_error_type = WRITE_ERROR;
+                r_config_cmd_fsm = CONFIG_CMD_ERROR_WAIT; 
+                break;
+            }
+            
+            assert( (p_vci_tgt_config.wdata.read()& K_PAGE_OFFSET_MASK) == 0 
+                    and " Error : Invalid format for Page Virtual Address. At least the 12 LSB bits must be zero");
+
+            r_config_tlb_inval_vaddr = (vaddr_t)(p_vci_tgt_config.wdata.read());
+             
+            config_local_fifo_put = true;
+            r_config_cmd_fsm = CONFIG_CMD_IDLE;
+        } 
+        break;
+    }
+    //////////////////
+    case CONFIG_CMD_IT_ADDR_IOMMU_WRITE_1: 
+    {
+        if ( p_vci_tgt_config.cmdval.read() && m_config_local_data_fifo.wok())
+        {
+            if(vci_param_d::N <= 32)
+            {
+            // address holds in one single flit
+                if (!p_vci_tgt_config.eop.read() )
+                {
+                    
+                    std::cout << "CONFIG_CMD ERROR " << name() << " CONFIG_CMD_IT_ADDR_IOMMU_WRITE_1 state" << std::endl;
+                    std::cout << " PTE invalidation command should contain just one flit" << std::endl;
+                    r_config_error_type = WRITE_ERROR;
+                    r_config_cmd_fsm = CONFIG_CMD_ERROR_WAIT;
+                }
+                else
+                {
+                    // If physical address holds on a single word
+                    r_it_addr[r_it_index.read()] = (paddr_t)(p_vci_tgt_config.wdata.read()); 
+                 
+                    config_local_fifo_put = true; 
+                    r_config_cmd_fsm = CONFIG_CMD_IDLE;
+                }
+        
+            }
+            else
+            {
+            // two flits are required to send address
+                if ( p_vci_tgt_config.eop.read() )
+                {
+                    
+                    std::cout << "CONFIG_CMD ERROR " << name() << " CONFIG_CMD_IT_ADDR_IOMMU_WRITE_1 state" << std::endl;
+                    std::cout << " PTE invalidation commands should contain two flits" << std::endl;
+                    r_config_error_type = WRITE_ERROR;
+                    r_config_cmd_fsm = CONFIG_CMD_ERROR_RSP;
+                }
+                else
+                {
+                    r_config_first_word = p_vci_tgt_config.wdata.read(); 
+                    r_config_cmd_fsm = CONFIG_CMD_IT_ADDR_IOMMU_WRITE_2;
+                }
+            }
+        } 
+        break;
+    }
+    /////////////////
+    case CONFIG_CMD_IT_ADDR_IOMMU_WRITE_2: 
+    {
+        if ( p_vci_tgt_config.cmdval.read() && m_config_local_data_fifo.wok() )
+        {
+            if ( !p_vci_tgt_config.eop.read() )
+            {
+                std::cout << "CONFIG_CMD ERROR " << name() << " CONFIG_CMD_IT_IOMMU_WRITE_2 state" << std::endl;
+                std::cout << " PTE invalidation commands must contain two flits" << std::endl;
+                r_config_error_type = WRITE_ERROR;
+                r_config_cmd_fsm = CONFIG_CMD_ERROR_WAIT; 
+                break;
+            }
+            
+            // Depends on the convention
+            size_t mask_msb = (1 << (vci_param_d::N - 32)) - 1 ;
+            r_it_addr_iommu = (paddr_t)(r_config_first_word.read() |
+                                   ((p_vci_tgt_config.wdata.read()& mask_msb)<<32)); 
+             
+            config_local_fifo_put = true;
+            r_config_cmd_fsm = CONFIG_CMD_IDLE;
+        } 
+    }
+    //////////////////
+    case CONFIG_CMD_IT_ADDR_WRITE_1: 
+    {
+        if ( p_vci_tgt_config.cmdval.read() && m_config_local_data_fifo.wok())
+        {
+            if(vci_param_d::N <= 32)
+            {
+            // address holds in one single flit
+                if (!p_vci_tgt_config.eop.read() )
+                {
+                    
+                    std::cout << "CONFIG_CMD ERROR " << name() << " CONFIG_CMD_IT_ADDR_WRITE_1 state" << std::endl;
+                    std::cout << " PTE invalidation command should contain just one flit" << std::endl;
+                    r_config_error_type = WRITE_ERROR;
+                    r_config_cmd_fsm = CONFIG_CMD_ERROR_WAIT;
+                    
+                   
+                }
+                else
+                {
+                    // If physical address holds on a single word
+                    r_it_addr[r_it_index.read()] = (paddr_t)(p_vci_tgt_config.wdata.read()); 
+                 
+                    config_local_fifo_put = true; 
+                    r_config_cmd_fsm = CONFIG_CMD_IDLE;
+                }
+        
+            }
+            else
+            {
+            // two flits are required to send address
+                if ( p_vci_tgt_config.eop.read() )
+                {
+                    
+                    std::cout << "CONFIG_CMD ERROR " << name() << " CONFIG_CMD_IT_ADDR_WRITE_1 state" << std::endl;
+                    std::cout << " PTE invalidation commands should contain two flits" << std::endl;
+                    r_config_error_type = WRITE_ERROR;
+                    r_config_cmd_fsm = CONFIG_CMD_ERROR_RSP;
+                }
+                else
+                {
+                    r_config_first_word = p_vci_tgt_config.wdata.read();
+                    r_config_cmd_fsm = CONFIG_CMD_IT_ADDR_WRITE_2;
+                }
+            } 
+        } 
+        break;
+    }
+    /////////////////
+    case CONFIG_CMD_IT_ADDR_WRITE_2: 
+    {
+        if ( p_vci_tgt_config.cmdval.read() && m_config_local_data_fifo.wok() )
+        {
+            if ( !p_vci_tgt_config.eop.read() )
+            {
+                std::cout << "CONFIG_CMD ERROR " << name() << " CONFIG_CMD_IT_ADDR_WRITE_2 state" << std::endl;
+                std::cout << " PTE invalidation commands must contain two flits" << std::endl;
+                r_config_error_type = WRITE_ERROR;
+                r_config_cmd_fsm = CONFIG_CMD_ERROR_WAIT; 
+                break;
+            }
+            
+            // Depends on the convention
+            size_t mask_msb = (1 << (vci_param_d::N - 32)) - 1 ;
+            r_it_addr[r_it_index.read()] = (paddr_t)(r_config_first_word.read() |
+                                ((p_vci_tgt_config.wdata.read()& mask_msb)<<32)); 
+             
+            config_local_fifo_put = true;
+            r_config_cmd_fsm = CONFIG_CMD_IDLE;
+        } 
+    }
+    //////////////////
+    case CONFIG_CMD_PTPR_READ: 
+    case CONFIG_CMD_ACTIVE_READ:
+    case CONFIG_CMD_BVAR_READ:
+    case CONFIG_CMD_ETR_READ:
+    case CONFIG_CMD_BAD_ID_READ:
+    case CONFIG_CMD_IT_ADDR_IOMMU_READ_1:
+    case CONFIG_CMD_IT_ADDR_READ_1:
+    {
+        if ( p_vci_tgt_config.cmdval.read() && m_config_local_data_fifo.wok() )
+        {
+            // This verification could have been done on IDLE state
+            // It would save us one cycle 
+            if ( !p_vci_tgt_config.eop.read() )
+            {
+                std::cout << "CONFIG_CMD ERROR " << name() << config_cmd_fsm_state_str[r_config_cmd_fsm.read()] << std::endl;
+                std::cout << " Read commands must contain one single flit" << std::endl;
+                r_config_error_type = READ_ERROR;
+                r_config_cmd_fsm = CONFIG_CMD_ERROR_WAIT; 
+                break;
+            }
+            
+            // fifo data receives the content of the corresponding register 
+            // (depending on the current state) 
+            config_local_fifo_put = true;
+            if(r_config_cmd_fsm.read()== CONFIG_CMD_IT_ADDR_READ_1)
+            r_config_cmd_fsm = CONFIG_CMD_IT_ADDR_READ_2;
+            else if(r_config_cmd_fsm.read()== CONFIG_CMD_IT_ADDR_IOMMU_READ_1)
+            r_config_cmd_fsm = CONFIG_CMD_IT_ADDR_IOMMU_READ_2;
+            else
+            r_config_cmd_fsm = CONFIG_CMD_IDLE;
+        } 
+        break;
+    }
+    //////////////////
+    case CONFIG_CMD_IT_ADDR_READ_2:
+    case CONFIG_CMD_IT_ADDR_IOMMU_READ_2:
+    {
+        if ( p_vci_tgt_config.cmdval.read() && m_config_local_data_fifo.wok() )
+        {
+            config_local_fifo_put = true;
+            r_config_cmd_fsm = CONFIG_CMD_IDLE;
+        } 
+    }
+    //////////////////
+    case CONFIG_CMD_ERROR_WAIT: //receives the other flits of the same transaction
+    {
+        if ( p_vci_tgt_config.cmdval.read() && p_vci_tgt_config.eop.read() ) 
+        r_config_cmd_fsm = CONFIG_CMD_ERROR_RSP; 
+    }
+    ///////////////////
+    case CONFIG_CMD_ERROR_RSP:
+    {
+        if ( m_config_local_data_fifo.wok() )
+        {
+            config_local_fifo_put = true;
+            r_config_cmd_fsm = CONFIG_CMD_IDLE;
+        }
+        break;
+    }
+
+    } // end switch CONFIG_CMD FSM
+
+    /////////////////////////////////////////////////////////////////////
+    // The CONFIG_RSP_FSM controls the following ressources:
+    // - r_config_rsp_fsm
+    // - r_config_cmd_rsp_erase_req (reset) 
+    // - 
+    // - 
+    //////////////////////////////////////////////////////////////////////////////
+    switch( r_config_rsp_fsm.read() ) 
+    {
+    /////////////////////
+    case CONFIG_RSP_IDLE:
+    {    	
+        if(p_vci_ini_config.rspval.read()) 
+		{
+            r_config_rsp_fsm = CONFIG_RSP_TRT_LOCK;
+		}
+		break;
+    }
+    /////////////////////
+    case CONFIG_RSP_TRT_LOCK:
+    {    	
+        if ( r_alloc_trt_config_fsm.read() == ALLOC_TRT_CONFIG_RSP ) 
+        {
+            
+#if DEBUG_CONFIG_RSP
+if( m_debug_config_rsp_fsm )
+{
+    std::cout << "  <IOB.CONFIG_RSP_TRT_LOCK> Read and erase entry" << std::endl;
+}
+#endif
+            uint32_t trdid_iospace = p_vci_ini_config.rtrdid.read(); 
+            
+            r_config_rsrcid = (vci_srcid_t)m_transaction_tab_config.readSrcid(trdid_iospace);
+            r_config_rtrdid = (vci_trdid_t)m_transaction_tab_config.readTrdid(trdid_iospace);
+            m_transaction_tab_config.erase(trdid_iospace);
+            if (r_config_cmd_rsp_erase_req.read()) r_config_cmd_rsp_erase_req = false;
+            r_config_rsp_fsm       = CONFIG_RSP_FIFO_PUT;
+        }        
+		break;
+    }
+    //////////////////
+    case CONFIG_RSP_FIFO_PUT:
+    {
+        if(p_vci_ini_config.rspval.read() && m_config_rsp_data_fifo.wok())
+    	{
+            config_rsp_fifo_put = true;
+            if(p_vci_ini_config.reop.read())   r_config_rsp_fsm = CONFIG_RSP_IDLE;	
+
+#if DEBUG_CONFIG_RSP
+if( m_debug_config_rsp_fsm ) 
+{
+    std::cout << "  <IOB.CONFIG_RSP_FIFO_PUT> Push into rsp_fifo:" 
+              << " rsrcid = " << std::dec << r_config_rsrcid.read()
+              << " rtrdid = " << r_config_rtrdid.read()
+              << " rdata = " << std::hex << p_vci_ini_config.rdata.read()
+    << std::endl;
+}
+#endif
+    			
+    	}
+    	break;
+    }
+    } // end switch CONFIG_RSP FSM
+
+
+    ////////////////////////////////////////////////////////////////////////////
+    // The ALLOC_TRT_CONFIG fsm allocates the access to the Transaction Table (m_transaction_tab_config)
+    // with a round robin priority between 2 user FSMs :
+    // - CONFIG_CMD : to set a new entry
+    // - CONFIG_RSP : to read and erase an entry
+    // The ressource is always allocated.
+    ////////////////////////////////////////////////////////////////////////////////////
+    
+    switch ( r_alloc_trt_config_fsm.read() ) 
+    {
+    ///////////////////
+    case ALLOC_TRT_CONFIG_CMD:
+    {
+        if ( r_config_cmd_fsm.read() != CONFIG_CMD_TRT_LOCK ) 
+        {
+          if (r_config_rsp_fsm.read() == CONFIG_RSP_TRT_LOCK) r_alloc_trt_config_fsm = ALLOC_TRT_CONFIG_RSP;
+        }
+    }
+    ///////////////////
+    case ALLOC_TRT_CONFIG_RSP:
+    {
+        if (r_config_rsp_fsm.read() != CONFIG_RSP_TRT_LOCK) 
+        {
+            if (r_config_cmd_fsm.read() == CONFIG_CMD_TRT_LOCK) r_alloc_trt_config_fsm = ALLOC_TRT_CONFIG_CMD;
+        }
+    }
+    } // end switch r_alloc_trt_config_fsm
+
+    ////////////////////////////////////////////////////////////////////////////
+    // The MISS_INIT FSM sends a page table entry miss request into Direct Noc
+    // It controls the following ressources:
+    // - r_miss_init_fsm
+    // - r_tlb_miss_init_req (reset)
+    // - r_miss_buf_data
+    // - r_miss_buf_valid
+    // - r_miss_buf_tag
+    ////////////////////////////////////////////////////////////////////////////////////
+
+    // Building the interruption vector (systematically)
+    uint32_t irq_demands = 0;
+    for ( size_t i = 0; i<m_nb_periph; ++i )
+        irq_demands |= (p_irq_in[i].read() ? 1 : 0) << i;
+    
+    // For next cycle:
+        // Afectation of the new pending vector. 
+        // Not useful, unless Irq choice is postponed to next cycle
+    r_irq_pending = irq_demands & r_irq_mask.read();
+        // Updating Mask
+    r_irq_mask = r_irq_mask.read()| ~irq_demands;  
+    
+ 
+    switch ( r_miss_init_fsm.read() ) 
+    {
+        //////////////
+        case MISS_INIT_IDLE_MISS:
+        {
+            if(r_tlb_miss_init_req.read())
+            {
+                r_miss_init_fsm = MISS_INIT_TLB_MISS_CMD;
+            }
+            else if (irq_demands & r_irq_mask.read()){
+                // Choosing one interruption to send            
+                // Find the first bit 1 
+                // starting by the bit just after the last chosen
+                size_t i = (r_irq_chosen.read() + 1)% m_nb_periph;
+                bool found = false;
+                do
+                {
+                    if(irq_demands & r_irq_mask.read() & (1<<i)) 
+                    {
+                        r_irq_chosen = i;
+                        found = true;
+                    }
+                    i = (i+1) % m_nb_periph;
+                }
+                while(i != r_irq_chosen.read()+1 && !found); 
+
+                r_miss_init_fsm = MISS_INIT_IRQ_CMD;
+            }
+			break;
+        }
+        //////////////
+        case MISS_INIT_IDLE_IRQ:
+        {
+            if (irq_demands & r_irq_mask.read()){
+                // Choosing one interruption to send            
+                // Find the first bit 1 
+                // starting by the bit just after the last chosen
+                size_t i = (r_irq_chosen.read() + 1)% m_nb_periph;
+                bool found = false;
+                do
+                {
+                    if(irq_demands & r_irq_mask.read() & (1<<i)) 
+                    {
+                        r_irq_chosen = i;
+                        found = true;
+                    }
+                    i = (i+1) % m_nb_periph;
+                }
+                while(i != r_irq_chosen.read()+1 && !found); 
+
+                r_miss_init_fsm = MISS_INIT_IRQ_CMD;
+            }
+            else if(r_tlb_miss_init_req.read())
+            {
+                r_miss_init_fsm = MISS_INIT_TLB_MISS_CMD;
+            }
+			break;
+        }
+        /////////////////////////       // send a read request to Direct Network
+        case MISS_INIT_IRQ_CMD: 
+        {
+        if ( p_vci_ini_miss.cmdack ) 
+        {
+            // Masking chosen interruption, until it is resolved 
+            r_irq_mask = r_irq_mask.read() & ~(1<<r_irq_chosen.read());
+            r_miss_init_fsm = MISS_INIT_IRQ_RSP;		
+
+#if DEBUG_MISS_INIT
+if( m_debug_miss_init_fsm )
+{
+    std::cout << "  <IOB.MISS_INIT_IRQ_CMD> Send write (irq) command to XICU"
+              << " irq ID = " << std::dec << r_irq_chosen.read()
+              << " new mask = " << std::hex << (r_irq_mask.read() & ~(1<<r_irq_chosen.read()))
+     << std::endl;
+}
+#endif
+        }
+            break;
+        }
+        //////////////////
+        case MISS_INIT_IRQ_RSP:	
+        {
+            if ( p_vci_ini_miss.rspval.read() ) 
+            {
+                // It is a WRITE command, response in one single flit long
+                assert( p_vci_ini_miss.reop.read() and "Write answer should have one single flit" ); 
+                bool error;
+                
+                if ( (p_vci_ini_miss.rerror.read()&0x1) != 0 )  // error reported
+                {
+                    // TODO traiter error
+                    error = true;
+                }
+                r_miss_init_fsm = MISS_INIT_IDLE_MISS;
+            }
+            break;
+        }
+        /////////////////////////       // send a read request to Direct Network
+        case MISS_INIT_TLB_MISS_CMD: 
+        {
+        if ( p_vci_ini_miss.cmdack ) 
+        {
+            r_miss_rsp_cpt  = 0;    //counter for the response flits
+            r_miss_buf_tag  = ( (r_iotlb_paddr.read()) & CACHE_LINE_MASK ); 
+            r_miss_buf_valid = true;
+            
+            if(r_tlb_miss_type.read()== PTE1_MISS)
+                r_miss_buf_vaddr_begin =(r_iotlb_vaddr.read() & ~M_PAGE_OFFSET_MASK & ~PTE1_LINE_OFFSET);
+            else
+                r_miss_buf_vaddr_begin =(r_iotlb_vaddr.read() & ~K_PAGE_OFFSET_MASK & ~PTE2_LINE_OFFSET);
+                
+            r_miss_init_fsm = MISS_INIT_TLB_MISS_RSP;		
+
+#if DEBUG_MISS_INIT
+if( m_debug_miss_init_fsm )
+{
+    std::cout << "  <IOB.MISS_INIT_TLB_MISS_CMD> Send read (tlb entry) request to MEM CACHE: "
+    << " | address :  "<< std::hex <<(paddr_t)((r_iotlb_paddr.read())& CACHE_LINE_MASK)
+    << std::endl;
+}
+#endif
+        }
+            break;
+        }
+        //////////////////
+        case MISS_INIT_TLB_MISS_RSP:	
+        {
+            if ( p_vci_ini_miss.rspval.read() ) 
+            {
+                if ( (p_vci_ini_miss.rerror.read()&0x1) != 0 )  // error reported
+                {
+                    r_miss_init_error = true;
+                    if ( p_vci_ini_miss.reop.read() ) 
+                    {    
+                        r_miss_init_fsm = MISS_INIT_IDLE_IRQ;
+                        r_tlb_miss_init_req = false; 
+                    }
+#if DEBUG_MISS_INIT
+if( m_debug_miss_init_fsm ) 
+{
+    std::cout << " <IOB.MISS_INIT_TLB_MISS_RSP> ERROR " << std::endl; 
+}
+#endif
+                }
+                else
+                { 
+                    bool   eop  	= p_vci_ini_miss.reop.read();
+
+
+#if DEBUG_MISS_INIT
+if( m_debug_miss_init_fsm ) 
+{
+    std::cout << "  <IOB.MISS_INIT_TLB_MISS_RSP> Response from Mem Cache to a read (tlb entry) transaction. Count = " << r_miss_rsp_cpt.read()
+    <<" | Data = " << std::hex << p_vci_ini_miss.rdata.read() << std::endl; 
+}
+#endif
+
+                    assert(((eop == (r_miss_rsp_cpt.read() == (m_words-1))) ) 
+                        and "Error : invalid length for a response from MEM CACHE");
+                    r_miss_buf_data[r_miss_rsp_cpt] =  (uint32_t)p_vci_ini_miss.rdata.read();
+                    
+                    r_miss_rsp_cpt = r_miss_rsp_cpt.read() + 1;
+                    
+                    if ( eop ) 
+                    {
+                        r_tlb_miss_init_req = false;     //reset the request flip-flop
+                        r_miss_init_fsm = MISS_INIT_IDLE_IRQ;		
+                    }
+
+                }
+            }
+            break;
+        }
+
+    } // end  switch r_miss_init_fsm
+    
+    //////////////////////////////////
+    // Fifo consumption arbitration //
+    //////////////////////////////////
+    
+    // Round Robin priority for CONFIG_RSP FIFO consumption
+    r_config_rsp_fifo_local_priority = ! r_config_rsp_fifo_local_priority.read(); 
+    
+    //DMA CMD
+    dma_cmd_fifo_get = (p_vci_ini_dma.cmdack.read() && m_dma_cmd_addr_fifo.rok());
+    // DMA RSP
+    dma_rsp_fifo_get = (p_vci_tgt_dma.rspack.read() && m_dma_rsp_data_fifo.rok());
+    // CONFIG CMD
+    config_cmd_fifo_get = (p_vci_ini_config.cmdack.read() && m_config_cmd_addr_fifo.rok() );
+    // CONFIG RSP, detemines wich fifo to consume 
+    if(r_config_rsp_fifo_local_priority)
+    {
+        if(m_config_local_data_fifo.rok()) config_local_fifo_get = p_vci_tgt_config.rspack.read();
+        else if (m_config_rsp_data_fifo.rok()) config_rsp_fifo_get = p_vci_tgt_config.rspack.read();
+            
+    }
+    else
+    {
+        if (m_config_rsp_data_fifo.rok()) config_rsp_fifo_get = p_vci_tgt_config.rspack.read();
+        else if(m_config_local_data_fifo.rok()) config_local_fifo_get = p_vci_tgt_config.rspack.read();
+    }
+    ///////////////
+    //DMA_CMD Fifo
+    ///////////////
+    if(r_miss_interrupt)
+    {
+        m_dma_cmd_addr_fifo.update( dma_cmd_fifo_get,
+                                    dma_cmd_fifo_put,
+                                    r_miss_paddr.read() );
+        m_dma_cmd_cmd_fifo.update( dma_cmd_fifo_get,
+                                    dma_cmd_fifo_put,
+                                    r_miss_cmd.read() );
+        m_dma_cmd_contig_fifo.update( dma_cmd_fifo_get,
+                                    dma_cmd_fifo_put,
+                                    r_miss_contig.read() );
+        m_dma_cmd_cons_fifo.update( dma_cmd_fifo_get,
+                                    dma_cmd_fifo_put,
+                                    r_miss_cons.read() );
+        m_dma_cmd_plen_fifo.update( dma_cmd_fifo_get,
+                                    dma_cmd_fifo_put,
+                                    r_miss_plen.read() );
+        m_dma_cmd_wrap_fifo.update( dma_cmd_fifo_get,
+                                    dma_cmd_fifo_put,
+                                    r_miss_wrap.read() );
+        m_dma_cmd_cfixed_fifo.update( dma_cmd_fifo_get,
+                                    dma_cmd_fifo_put,
+                                    r_miss_cfixed.read() );
+        m_dma_cmd_clen_fifo.update( dma_cmd_fifo_get,
+                                    dma_cmd_fifo_put,
+                                    r_miss_clen.read() );
+        m_dma_cmd_srcid_fifo.update( dma_cmd_fifo_get,
+                                    dma_cmd_fifo_put,
+                                    m_srcid_dma ); //r_miss_srcid.read()
+        m_dma_cmd_trdid_fifo.update( dma_cmd_fifo_get,
+                                    dma_cmd_fifo_put,
+                                    r_miss_trdid.read() );
+        m_dma_cmd_pktid_fifo.update( dma_cmd_fifo_get,
+                                    dma_cmd_fifo_put,
+                                    r_miss_pktid.read() );
+        m_dma_cmd_data_fifo.update( dma_cmd_fifo_get,
+                                    dma_cmd_fifo_put,
+                                    r_miss_data[r_dma_cmd_count.read()-1] );
+        m_dma_cmd_be_fifo.update( dma_cmd_fifo_get,
+                                    dma_cmd_fifo_put,
+                                    r_miss_be[r_dma_cmd_count.read()-1] );
+        m_dma_cmd_eop_fifo.update( dma_cmd_fifo_get,
+                                    dma_cmd_fifo_put,
+                                    (r_dma_cmd_count.read() == 1) );
+    }
+    else 
+    {
+        m_dma_cmd_addr_fifo.update( dma_cmd_fifo_get,
+                                    dma_cmd_fifo_put,
+                                    r_dma_paddr.read() ); 
+        m_dma_cmd_cmd_fifo.update( dma_cmd_fifo_get,
+                                    dma_cmd_fifo_put,
+                                    p_vci_tgt_dma.cmd.read() );
+        m_dma_cmd_contig_fifo.update( dma_cmd_fifo_get,
+                                    dma_cmd_fifo_put,
+                                    p_vci_tgt_dma.contig.read() );
+        m_dma_cmd_cons_fifo.update( dma_cmd_fifo_get,
+                                    dma_cmd_fifo_put,
+                                    p_vci_tgt_dma.cons.read() );
+        m_dma_cmd_plen_fifo.update( dma_cmd_fifo_get,
+                                    dma_cmd_fifo_put,
+                                    p_vci_tgt_dma.plen.read() );
+        m_dma_cmd_wrap_fifo.update( dma_cmd_fifo_get,
+                                    dma_cmd_fifo_put,
+                                    p_vci_tgt_dma.wrap.read() );
+        m_dma_cmd_cfixed_fifo.update( dma_cmd_fifo_get,
+                                    dma_cmd_fifo_put,
+                                    p_vci_tgt_dma.cfixed.read() );
+        m_dma_cmd_clen_fifo.update( dma_cmd_fifo_get,
+                                    dma_cmd_fifo_put,
+                                    p_vci_tgt_dma.clen.read() );
+        m_dma_cmd_srcid_fifo.update( dma_cmd_fifo_get,
+                                    dma_cmd_fifo_put,
+                                    m_srcid_dma );
+        m_dma_cmd_trdid_fifo.update( dma_cmd_fifo_get,
+                                    dma_cmd_fifo_put,
+                                    r_dma_cmd_trt_index.read() );
+        m_dma_cmd_pktid_fifo.update( dma_cmd_fifo_get,
+                                    dma_cmd_fifo_put,
+                                    p_vci_tgt_dma.pktid.read() );
+        m_dma_cmd_data_fifo.update( dma_cmd_fifo_get,
+                                    dma_cmd_fifo_put,
+                                    p_vci_tgt_dma.wdata.read() ); // TODO change
+                                                            // For 64bits XRAM
+        m_dma_cmd_be_fifo.update( dma_cmd_fifo_get,
+                                    dma_cmd_fifo_put,
+                                    p_vci_tgt_dma.be.read() ); 
+        m_dma_cmd_eop_fifo.update( dma_cmd_fifo_get,
+                                    dma_cmd_fifo_put,
+                                     p_vci_tgt_dma.eop.read() );
+    }
+
+    ///////////////
+    //DMA_RSP Fifo
+    ///////////////
+    if(r_dma_rsp_fsm.read() == DMA_RSP_FIFO_ERROR_PUT)
+    {
+        m_dma_rsp_data_fifo.update( dma_rsp_fifo_get,
+                                    dma_rsp_fifo_put,
+                                    0 );
+        m_dma_rsp_rsrcid_fifo.update( dma_rsp_fifo_get,
+                                    dma_rsp_fifo_put,
+                                    r_iommu_bad_id.read() ); 
+        m_dma_rsp_rtrdid_fifo.update( dma_rsp_fifo_get,
+                                    dma_rsp_fifo_put,
+                                    r_dma_error_trdid.read() ); 
+        m_dma_rsp_rpktid_fifo.update( dma_rsp_fifo_get,
+                                    dma_rsp_fifo_put,
+                                    r_dma_error_pktid.read() );
+        m_dma_rsp_reop_fifo.update( dma_rsp_fifo_get,
+                                   dma_rsp_fifo_put,
+                                   true );
+        m_dma_rsp_rerror_fifo.update( dma_rsp_fifo_get,
+                                      dma_rsp_fifo_put,
+                                      r_dma_error_type.read() );
+    }
+    else
+    {
+        m_dma_rsp_data_fifo.update( dma_rsp_fifo_get,
+                                    dma_rsp_fifo_put,
+                                    p_vci_ini_dma.rdata.read() );
+        m_dma_rsp_rsrcid_fifo.update( dma_rsp_fifo_get,
+                                    dma_rsp_fifo_put,
+                                    r_dma_rsrcid.read() ); 
+        m_dma_rsp_rtrdid_fifo.update( dma_rsp_fifo_get,
+                                    dma_rsp_fifo_put,
+                                    r_dma_rtrdid.read() ); 
+        m_dma_rsp_rpktid_fifo.update( dma_rsp_fifo_get,
+                                    dma_rsp_fifo_put,
+                                    p_vci_ini_dma.rpktid.read() );
+        m_dma_rsp_reop_fifo.update( dma_rsp_fifo_get,
+                                   dma_rsp_fifo_put,
+                                   p_vci_ini_dma.reop.read() );
+        m_dma_rsp_rerror_fifo.update( dma_rsp_fifo_get,
+                                      dma_rsp_fifo_put,
+                                      p_vci_ini_dma.rerror.read() );
+    }
+
+    //////////////////
+    //CONFIG_CMD Fifo
+    //////////////////
+    m_config_cmd_addr_fifo.update( config_cmd_fifo_get,
+                                config_cmd_fifo_put,
+                                r_config_vaddr.read() ); 
+    m_config_cmd_cmd_fifo.update( config_cmd_fifo_get,
+                                config_cmd_fifo_put,
+                                p_vci_tgt_config.cmd.read() );
+    m_config_cmd_contig_fifo.update( config_cmd_fifo_get,
+                                config_cmd_fifo_put,
+                                p_vci_tgt_config.contig.read() );
+    m_config_cmd_cons_fifo.update( config_cmd_fifo_get,
+                                config_cmd_fifo_put,
+                                p_vci_tgt_config.cons.read() );
+    m_config_cmd_plen_fifo.update( config_cmd_fifo_get,
+                                config_cmd_fifo_put,
+                                p_vci_tgt_config.plen.read() );
+    m_config_cmd_wrap_fifo.update( config_cmd_fifo_get,
+                                config_cmd_fifo_put,
+                                p_vci_tgt_config.wrap.read() );
+    m_config_cmd_cfixed_fifo.update( config_cmd_fifo_get,
+                                config_cmd_fifo_put,
+                                p_vci_tgt_config.cfixed.read() );
+    m_config_cmd_clen_fifo.update( config_cmd_fifo_get,
+                                config_cmd_fifo_put,
+                                p_vci_tgt_config.clen.read() );
+    m_config_cmd_srcid_fifo.update( config_cmd_fifo_get,
+                                config_cmd_fifo_put,
+                                m_srcid_config );
+    m_config_cmd_trdid_fifo.update( config_cmd_fifo_get,
+                                config_cmd_fifo_put,
+                                r_config_cmd_trt_index.read() ); 
+    m_config_cmd_pktid_fifo.update( config_cmd_fifo_get,
+                                config_cmd_fifo_put,
+                                p_vci_tgt_config.pktid.read() );
+    m_config_cmd_data_fifo.update( config_cmd_fifo_get,
+                                config_cmd_fifo_put,
+                                p_vci_tgt_config.wdata.read() );
+    m_config_cmd_be_fifo.update( config_cmd_fifo_get,
+                                config_cmd_fifo_put,
+                                p_vci_tgt_config.be.read() );
+    m_config_cmd_eop_fifo.update( config_cmd_fifo_get,
+                                    config_cmd_fifo_put,
+                                     p_vci_tgt_config.eop.read() );
+    
+    //////////////////
+    //CONFIG_RSP Fifo
+    //////////////////
+    m_config_rsp_data_fifo.update( config_rsp_fifo_get,
+                                config_rsp_fifo_put,
+                                p_vci_ini_config.rdata.read() );
+    m_config_rsp_rsrcid_fifo.update( config_rsp_fifo_get,
+                                config_rsp_fifo_put,
+                                r_config_rsrcid.read() );
+    m_config_rsp_rtrdid_fifo.update( config_rsp_fifo_get,
+                                config_rsp_fifo_put,
+                                r_config_rtrdid.read() );
+    m_config_rsp_rpktid_fifo.update( config_rsp_fifo_get,
+                                config_rsp_fifo_put,
+                                p_vci_ini_config.rpktid.read() );
+    m_config_rsp_reop_fifo.update( config_rsp_fifo_get,
+                               config_rsp_fifo_put,
+                               p_vci_ini_config.reop.read() );
+    m_config_rsp_rerror_fifo.update( config_rsp_fifo_get,
+                                  config_rsp_fifo_put,
+                                  p_vci_ini_config.rerror.read() );
+    
+    ///////////////////////
+    //CONFIG Local RSP Fifo
+    ///////////////////////
+    m_config_local_rsrcid_fifo.update( config_local_fifo_get,
+                                config_local_fifo_put,
+                                p_vci_tgt_config.srcid.read() );
+    m_config_local_rtrdid_fifo.update( config_local_fifo_get,
+                                config_local_fifo_put,
+                                p_vci_tgt_config.trdid.read() );
+    m_config_local_rpktid_fifo.update( config_local_fifo_get,
+                                config_local_fifo_put,
+                                p_vci_tgt_config.pktid.read() );
+    
+    switch( r_config_cmd_fsm.read() ) 
+    {
+    case CONFIG_CMD_PTPR_WRITE:
+    case CONFIG_CMD_ACTIVE_WRITE:
+    case CONFIG_CMD_IT_ADDR_IOMMU_WRITE_2:
+    case CONFIG_CMD_IT_ADDR_WRITE_2:
+    case CONFIG_CMD_INVAL:
+        m_config_local_data_fifo.update( config_local_fifo_get,
+                                config_local_fifo_put,
+                                0); 
+        m_config_local_rerror_fifo.update( config_local_fifo_get,
+                                        config_local_fifo_put,
+                                        WRITE_OK );
+        m_config_local_reop_fifo.update( config_local_fifo_get,
+                                        config_local_fifo_put,
+                                        true );
+        break;
+    case CONFIG_CMD_PTPR_READ:
+        m_config_local_data_fifo.update( config_local_fifo_get,
+                                config_local_fifo_put,
+                                r_iommu_ptpr.read()); 
+        m_config_local_rerror_fifo.update( config_local_fifo_get,
+                                        config_local_fifo_put,
+                                        READ_OK );
+        m_config_local_reop_fifo.update( config_local_fifo_get,
+                                        config_local_fifo_put,
+                                        true );
+        break;
+    case CONFIG_CMD_ACTIVE_READ:
+        m_config_local_data_fifo.update( config_local_fifo_get,
+                                config_local_fifo_put,
+                                r_iommu_active.read()); 
+        m_config_local_rerror_fifo.update( config_local_fifo_get,
+                                        config_local_fifo_put,
+                                        READ_OK );
+        m_config_local_reop_fifo.update( config_local_fifo_get,
+                                        config_local_fifo_put,
+                                        true );
+        break;
+    case CONFIG_CMD_BVAR_READ:
+        m_config_local_data_fifo.update( config_local_fifo_get,
+                                config_local_fifo_put,
+                                r_iommu_bvar.read()); 
+        m_config_local_rerror_fifo.update( config_local_fifo_get,
+                                        config_local_fifo_put,
+                                        READ_OK );
+        m_config_local_reop_fifo.update( config_local_fifo_get,
+                                        config_local_fifo_put,
+                                        true );
+        break;
+    case CONFIG_CMD_ETR_READ:
+        m_config_local_data_fifo.update( config_local_fifo_get,
+                                config_local_fifo_put,
+                                r_iommu_etr.read()); 
+        m_config_local_rerror_fifo.update( config_local_fifo_get,
+                                        config_local_fifo_put,
+                                        READ_OK );
+        m_config_local_reop_fifo.update( config_local_fifo_get,
+                                        config_local_fifo_put,
+                                        true );
+        break;
+    case CONFIG_CMD_BAD_ID_READ:
+        m_config_local_data_fifo.update( config_local_fifo_get,
+                                config_local_fifo_put,
+                                r_iommu_bad_id.read()); 
+        m_config_local_rerror_fifo.update( config_local_fifo_get,
+                                        config_local_fifo_put,
+                                        READ_OK );
+        m_config_local_reop_fifo.update( config_local_fifo_get,
+                                        config_local_fifo_put,
+                                        true );
+        break;
+    case CONFIG_CMD_IT_ADDR_IOMMU_READ_1:
+        m_config_local_data_fifo.update( config_local_fifo_get,
+                                config_local_fifo_put,
+                                (uint32_t)(r_it_addr_iommu.read() & 0xFFFFFFFF) ); 
+        m_config_local_rerror_fifo.update( config_local_fifo_get,
+                                        config_local_fifo_put,
+                                        READ_OK );
+        m_config_local_reop_fifo.update( config_local_fifo_get,
+                                        config_local_fifo_put,
+                                        false );
+        break;
+    case CONFIG_CMD_IT_ADDR_IOMMU_READ_2:
+        m_config_local_data_fifo.update( config_local_fifo_get,
+                                config_local_fifo_put,
+                               (uint32_t)((r_it_addr_iommu.read()>>32)&0xFF) ); 
+        m_config_local_rerror_fifo.update( config_local_fifo_get,
+                                        config_local_fifo_put,
+                                        READ_OK );
+        m_config_local_reop_fifo.update( config_local_fifo_get,
+                                        config_local_fifo_put,
+                                        true );
+        break;
+    case CONFIG_CMD_IT_ADDR_READ_1:
+        m_config_local_data_fifo.update( config_local_fifo_get,
+                                config_local_fifo_put,
+                               (uint32_t)(r_it_addr[r_it_index.read()] & 0xFFFFFFFF) ); 
+        m_config_local_rerror_fifo.update( config_local_fifo_get,
+                                        config_local_fifo_put,
+                                        READ_OK );
+        m_config_local_reop_fifo.update( config_local_fifo_get,
+                                        config_local_fifo_put,
+                                        false );
+        break;
+    case CONFIG_CMD_IT_ADDR_READ_2:
+        m_config_local_data_fifo.update( config_local_fifo_get,
+                                config_local_fifo_put,
+                                (uint32_t)((r_it_addr[r_it_index.read()]>>32)&0xFF) ); 
+        m_config_local_rerror_fifo.update( config_local_fifo_get,
+                                        config_local_fifo_put,
+                                        READ_OK );
+        m_config_local_reop_fifo.update( config_local_fifo_get,
+                                        config_local_fifo_put,
+                                        true );
+        break;
+    case CONFIG_CMD_ERROR_RSP:
+        m_config_local_data_fifo.update( config_local_fifo_get,
+                                        config_local_fifo_put,
+                                        0); 
+        m_config_local_rerror_fifo.update( config_local_fifo_get,
+                                        config_local_fifo_put,
+                                        r_config_error_type.read() );
+        m_config_local_reop_fifo.update( config_local_fifo_get,
+                                        config_local_fifo_put,
+                                        true );
+        break;
+    default:
+        m_config_local_data_fifo.update( config_local_fifo_get,
+                                config_local_fifo_put,
+                                0); 
+        m_config_local_rerror_fifo.update( config_local_fifo_get,
+                                        config_local_fifo_put,
+                                        0 );
+        m_config_local_reop_fifo.update( config_local_fifo_get,
+                               config_local_fifo_put,
+                               false );
+        break;
+    }
+
+} // end transition()
+
+///////////////////////
+tmpl(void)::genMoore()
+///////////////////////
+{
+    //////////////////
+    // DMA Commands //
+    //////////////////
+    
+    // VCI initiator command on the xram network
+    if(m_dma_cmd_addr_fifo.rok()) 
+    //&& p_vci_ini_dma.cmdack.read())
+    {
+        p_vci_ini_dma.cmdval  = true;
+        #if NEW_XRAM_VCI
+        p_vci_ini_dma.address = (paddr_t_x)(m_dma_cmd_addr_fifo.read() >> 6 )
+        #else
+        p_vci_ini_dma.address = m_dma_cmd_addr_fifo.read();
+        #endif
+        
+        p_vci_ini_dma.be      = m_dma_cmd_be_fifo.read();
+        p_vci_ini_dma.cmd     = m_dma_cmd_cmd_fifo.read();
+        p_vci_ini_dma.contig  = m_dma_cmd_contig_fifo.read();
+        #if NEW_XRAM_VCI
+        //TODO for 64 bits field
+        #else
+        p_vci_ini_dma.wdata   = m_dma_cmd_data_fifo.read(); // The first is in param_x
+                                                    // the second in param_io
+        #endif
+        p_vci_ini_dma.eop     = m_dma_cmd_eop_fifo.read();
+        p_vci_ini_dma.cons    = m_dma_cmd_cons_fifo.read();
+        p_vci_ini_dma.plen    = m_dma_cmd_plen_fifo.read();
+        p_vci_ini_dma.wrap    = m_dma_cmd_wrap_fifo.read();
+        p_vci_ini_dma.cfixed  = m_dma_cmd_cfixed_fifo.read();
+        p_vci_ini_dma.clen    = m_dma_cmd_clen_fifo.read();
+        p_vci_ini_dma.trdid   = m_dma_cmd_trdid_fifo.read();
+        p_vci_ini_dma.pktid   = m_dma_cmd_pktid_fifo.read();
+        p_vci_ini_dma.srcid   = m_dma_cmd_srcid_fifo.read();
+    }
+    else
+    {
+        p_vci_ini_dma.cmdval  = false;
+        p_vci_ini_dma.address = 0;
+        p_vci_ini_dma.be      = 0;
+        p_vci_ini_dma.cmd     = vci_param_x::CMD_NOP;
+        p_vci_ini_dma.contig  = false;
+        p_vci_ini_dma.wdata   = 0;
+        p_vci_ini_dma.eop     = false;
+        p_vci_ini_dma.cons    = true;
+        p_vci_ini_dma.plen    = 0;
+        p_vci_ini_dma.wrap    = false;
+        p_vci_ini_dma.cfixed  = false;
+        p_vci_ini_dma.clen    = 0;
+        p_vci_ini_dma.trdid   = 0;
+        p_vci_ini_dma.pktid   = 0; 
+    }
+    
+    // VCI target command on the IO network
+    // it depends on the DMA_CMD FSM state
+
+    switch ( r_dma_cmd_fsm.read() ) 
+    {
+    case DMA_CMD_IDLE:
+    case DMA_CMD_TRT_LOCK:	
+    case DMA_CMD_TRT_WAIT:	
+    case DMA_CMD_TRT_SET:	
+        p_vci_tgt_dma.cmdack  = false;
+        break;
+    case DMA_CMD_FIFO_PUT:
+    case DMA_CMD_FIFO_MISS_PUT:
+        p_vci_tgt_dma.cmdack  = m_dma_cmd_addr_fifo.wok();
+        break;
+    case DMA_CMD_TLB_MISS_WAIT:
+        p_vci_tgt_dma.cmdack  = false;
+        break;
+    case DMA_CMD_TLB_MISS_STORE:
+        p_vci_tgt_dma.cmdack  = true;
+        break;
+    case DMA_CMD_ERROR:
+        p_vci_tgt_dma.cmdack  = !r_dma_cmd_error_req.read();
+        break; 
+    }// end switch r_dma_cmd_fsm
+
+    //////////////////
+    // DMA Responses//
+    //////////////////
+    
+    // VCI target response on the IO network
+    if(m_dma_rsp_data_fifo.rok())
+    {
+        p_vci_tgt_dma.rspval  = true;
+		p_vci_tgt_dma.rsrcid  = m_dma_rsp_rsrcid_fifo.read();
+        p_vci_tgt_dma.rtrdid  = m_dma_rsp_rtrdid_fifo.read();
+        
+        p_vci_tgt_dma.rpktid  = m_dma_rsp_rpktid_fifo.read();
+    
+        #if NEW_XRAM_VCI
+        //TODO for 64 bit data field
+        #else 
+        p_vci_tgt_dma.rdata   = m_dma_rsp_data_fifo.read(); // The first is in param_io
+                                                    // the second in param_x
+        #endif 
+        
+        p_vci_tgt_dma.rerror  = m_dma_rsp_rerror_fifo.read();
+        p_vci_tgt_dma.reop    = m_dma_rsp_reop_fifo.read();
+    }
+    else
+    {
+        p_vci_tgt_dma.rspval  = false;
+        
+		p_vci_tgt_dma.rsrcid  = 0;
+		p_vci_tgt_dma.rdata   = 0;
+		p_vci_tgt_dma.rpktid  = 0;
+		p_vci_tgt_dma.rtrdid  = 0;
+		p_vci_tgt_dma.rerror  = 0;
+		p_vci_tgt_dma.reop    = false;
+
+    }
+
+    // VCI initiator response on the Xram Network
+    // it depends on the DMA_RSP FSM state
+    switch ( r_dma_rsp_fsm.read() ) 
+    {
+    case DMA_RSP_IDLE:
+    case DMA_RSP_TRT_LOCK:
+    case DMA_RSP_FIFO_ERROR_PUT:
+    {
+		p_vci_ini_dma.rspack = false;
+        break;
+    }
+    case DMA_RSP_FIFO_PUT:
+	{
+    	p_vci_ini_dma.rspack = m_dma_rsp_data_fifo.wok();
+        break;
+    }
+    }// end switch r_dma_rsp_fsm
+
+    /////////////////////
+    // CONFIG Commands //
+    /////////////////////
+
+    // VCI initiator command on the IO network
+    if(m_config_cmd_addr_fifo.rok())
+    {
+        p_vci_ini_config.cmdval  = true;
+        #if NEW_XRAM_VCI
+        p_vci_ini_config.address = (paddr_t_x)(m_config_cmd_addr_fifo.read() >> 6 )
+        #else
+        p_vci_ini_config.address = m_config_cmd_addr_fifo.read();
+        #endif
+        
+        p_vci_ini_config.be      = m_config_cmd_be_fifo.read();
+        p_vci_ini_config.cmd     = m_config_cmd_cmd_fifo.read();
+        p_vci_ini_config.contig  = m_config_cmd_contig_fifo.read();
+        #if NEW_XRAM_VCI
+        //TODO
+        #else
+        p_vci_ini_config.wdata   = m_config_cmd_data_fifo.read(); // The first is in param_x
+                                                    // the second in param_io
+        #endif
+        p_vci_ini_config.eop     = m_config_cmd_eop_fifo.read();
+        p_vci_ini_config.cons    = m_config_cmd_cons_fifo.read();
+        p_vci_ini_config.plen    = m_config_cmd_plen_fifo.read();
+        p_vci_ini_config.wrap    = m_config_cmd_wrap_fifo.read();
+        p_vci_ini_config.cfixed  = m_config_cmd_cfixed_fifo.read();
+        p_vci_ini_config.clen    = m_config_cmd_clen_fifo.read();
+        p_vci_ini_config.trdid   = m_config_cmd_trdid_fifo.read();
+        p_vci_ini_config.pktid   = m_config_cmd_pktid_fifo.read();
+    }
+    else
+    {
+        p_vci_ini_config.cmdval  = false;
+        p_vci_ini_config.address = 0;
+        p_vci_ini_config.be      = 0;
+        p_vci_ini_config.cmd     = vci_param_io::CMD_NOP;
+        p_vci_ini_config.contig  = false;
+        p_vci_ini_config.wdata   = 0;
+        p_vci_ini_config.eop     = false;
+        p_vci_ini_config.cons    = true;
+        p_vci_ini_config.plen    = 0;
+        p_vci_ini_config.wrap    = false;
+        p_vci_ini_config.cfixed  = false;
+        p_vci_ini_config.clen    = 0;
+        p_vci_ini_config.trdid   = 0;
+        p_vci_ini_config.pktid   = 0; 
+    }
+    
+    // VCI target command on the Direct network
+    // it depends on the CONFIG_CMD FSM state
+
+    switch ( r_config_cmd_fsm.read() ) 
+    {
+    case CONFIG_CMD_IDLE:
+    case CONFIG_CMD_TRT_LOCK:   
+    case CONFIG_CMD_TRT_WAIT: 
+    case CONFIG_CMD_TRT_SET: 
+    case CONFIG_CMD_IT_ADDR_IOMMU_READ_1:
+    case CONFIG_CMD_IT_ADDR_READ_1:
+    case CONFIG_CMD_ERROR_RSP:  
+    case CONFIG_CMD_INVAL_REQ:
+        p_vci_tgt_config.cmdack  = false;
+        break;
+    case CONFIG_CMD_FIFO_PUT:	  
+    case CONFIG_CMD_PTPR_WRITE:
+    case CONFIG_CMD_PTPR_READ:
+    case CONFIG_CMD_ACTIVE_WRITE:
+    case CONFIG_CMD_ACTIVE_READ:
+    case CONFIG_CMD_BVAR_READ:
+    case CONFIG_CMD_ETR_READ:
+    case CONFIG_CMD_BAD_ID_READ:
+    case CONFIG_CMD_IT_ADDR_IOMMU_WRITE_2:
+    case CONFIG_CMD_IT_ADDR_IOMMU_READ_2:
+    case CONFIG_CMD_IT_ADDR_WRITE_2:
+    case CONFIG_CMD_IT_ADDR_READ_2:
+    case CONFIG_CMD_INVAL: 
+        p_vci_tgt_config.cmdack  = m_config_cmd_addr_fifo.wok();
+        break;
+    case CONFIG_CMD_IT_ADDR_IOMMU_WRITE_1:
+    case CONFIG_CMD_IT_ADDR_WRITE_1:
+    case CONFIG_CMD_ERROR_WAIT: 
+        p_vci_tgt_config.cmdack = true; 
+        break;
+    default: 
+        p_vci_tgt_config.cmdack  = false;
+        break;
+    }// end switch r_config_cmd_fsm
+
+    /////////////////////
+    // CONFIG Responses//
+    /////////////////////
+    
+    // VCI target response on the Direct network
+    if(r_config_rsp_fifo_local_priority)
+    {
+    if( m_config_local_data_fifo.rok() )
+    {
+        p_vci_tgt_config.rspval  = true;
+		p_vci_tgt_config.rsrcid  = m_config_local_rsrcid_fifo.read();
+        p_vci_tgt_config.rtrdid  = m_config_local_rtrdid_fifo.read();
+        p_vci_tgt_config.rpktid  = m_config_local_rpktid_fifo.read();
+        p_vci_tgt_config.rdata   = m_config_local_data_fifo.read();
+        p_vci_tgt_config.rerror  = m_config_local_rerror_fifo.read();
+        p_vci_tgt_config.reop    = m_config_local_reop_fifo.read();
+    }
+    else if(m_config_rsp_data_fifo.rok() )
+    {
+        p_vci_tgt_config.rspval  = true;
+		p_vci_tgt_config.rsrcid  = m_config_rsp_rsrcid_fifo.read();
+        p_vci_tgt_config.rtrdid  = m_config_rsp_rtrdid_fifo.read();
+        
+        p_vci_tgt_config.rpktid  = m_config_rsp_rpktid_fifo.read();
+    
+        p_vci_tgt_config.rdata   = m_config_rsp_data_fifo.read(); // The first is in param_d
+                                                    // the second in param_io
+        p_vci_tgt_config.rerror  = m_config_rsp_rerror_fifo.read();
+        p_vci_tgt_config.reop    = m_config_rsp_reop_fifo.read();
+    }
+    else
+    {
+        p_vci_tgt_config.rspval  = false;
+        
+		p_vci_tgt_config.rsrcid  = 0;
+		p_vci_tgt_config.rdata   = 0;
+		p_vci_tgt_config.rpktid  = 0;
+		p_vci_tgt_config.rtrdid  = 0;
+		p_vci_tgt_config.rerror  = 0;
+		p_vci_tgt_config.reop    = false;
+
+    }
+    }
+    else
+    {
+    if(m_config_rsp_data_fifo.rok() )
+    {
+        p_vci_tgt_config.rspval  = true;
+		p_vci_tgt_config.rsrcid  = m_config_rsp_rsrcid_fifo.read();
+        p_vci_tgt_config.rtrdid  = m_config_rsp_rtrdid_fifo.read();
+        
+        p_vci_tgt_config.rpktid  = m_config_rsp_rpktid_fifo.read();
+    
+        p_vci_tgt_config.rdata   = m_config_rsp_data_fifo.read(); // The first is in param_d
+                                                    // the second in param_io
+        p_vci_tgt_config.rerror  = m_config_rsp_rerror_fifo.read();
+        p_vci_tgt_config.reop    = m_config_rsp_reop_fifo.read();
+    }
+    else if( m_config_local_data_fifo.rok() )
+    {
+        p_vci_tgt_config.rspval  = true;
+		p_vci_tgt_config.rsrcid  = m_config_local_rsrcid_fifo.read();
+        p_vci_tgt_config.rtrdid  = m_config_local_rtrdid_fifo.read();
+        p_vci_tgt_config.rpktid  = m_config_local_rpktid_fifo.read();
+        p_vci_tgt_config.rdata   = m_config_local_data_fifo.read();
+        p_vci_tgt_config.rerror  = m_config_local_rerror_fifo.read();
+        p_vci_tgt_config.reop    = m_config_local_reop_fifo.read();
+    }
+    else
+    {
+        p_vci_tgt_config.rspval  = false;
+        
+		p_vci_tgt_config.rsrcid  = 0;
+		p_vci_tgt_config.rdata   = 0;
+		p_vci_tgt_config.rpktid  = 0;
+		p_vci_tgt_config.rtrdid  = 0;
+		p_vci_tgt_config.rerror  = 0;
+		p_vci_tgt_config.reop    = false;
+
+    }
+    }
+    
+    // VCI initiator response on the IO Network
+    // it depends on the CONFIG_RSP FSM state
+    switch ( r_config_rsp_fsm.read() ) 
+    {
+    case CONFIG_RSP_IDLE:
+    case CONFIG_RSP_TRT_LOCK:
+	p_vci_ini_config.rspack = false;
+        break;
+    case CONFIG_RSP_FIFO_PUT:
+		p_vci_ini_config.rspack = m_config_rsp_data_fifo.wok();
+        break;
+    }// end switch r_config_rsp_fsm
+
+    ////////////////////////////////////////////////////////////////
+    // VCI initiator command and response on from the Direct network 
+    // for Miss Transactions
+    p_vci_ini_miss.srcid   = m_srcid_miss;
+    
+    switch ( r_miss_init_fsm.read() ) 
+    {   
+    case MISS_INIT_IDLE_MISS:
+    case MISS_INIT_IDLE_IRQ:
+		p_vci_ini_miss.cmdval  = false;
+        p_vci_ini_miss.address = 0;
+        p_vci_ini_miss.be      = 0;
+        p_vci_ini_miss.cmd     = vci_param_d::CMD_NOP;
+        p_vci_ini_miss.contig  = false;
+        p_vci_ini_miss.wdata   = 0;
+        p_vci_ini_miss.eop     = false;
+        p_vci_ini_miss.cons    = true;
+        p_vci_ini_miss.plen    = 0;
+        p_vci_ini_miss.wrap    = false;
+        p_vci_ini_miss.cfixed  = false;
+        p_vci_ini_miss.clen    = 0;
+        p_vci_ini_miss.trdid   = 0;
+        p_vci_ini_miss.pktid   = 0;
+
+		p_vci_ini_miss.rspack = false;
+        break;
+    
+    case MISS_INIT_IRQ_CMD:
+        p_vci_ini_miss.cmdval  = true;
+        p_vci_ini_miss.address = (paddr_t)r_it_addr[r_irq_chosen.read()]; 
+        p_vci_ini_miss.wdata   = 0;
+        p_vci_ini_miss.plen    = vci_param_d::B;
+        p_vci_ini_miss.trdid   = 0;  
+        p_vci_ini_miss.cmd     = vci_param_d::CMD_READ;
+        p_vci_ini_miss.eop     = true;
+        
+        p_vci_ini_miss.be      = 0xF;
+        p_vci_ini_miss.pktid   = 0;
+        p_vci_ini_miss.cons    = false;
+        p_vci_ini_miss.wrap    = false;
+        p_vci_ini_miss.contig  = true;
+        p_vci_ini_miss.clen    = 0;
+        p_vci_ini_miss.cfixed  = false;
+        break;
+    
+    case MISS_INIT_IRQ_RSP:
+    case MISS_INIT_TLB_MISS_RSP:
+        p_vci_ini_miss.cmdval  = false;
+        p_vci_ini_miss.address = 0;
+        p_vci_ini_miss.be      = 0;
+        p_vci_ini_miss.cmd     = vci_param_d::CMD_NOP;
+        p_vci_ini_miss.contig  = false;
+        p_vci_ini_miss.wdata   = 0;
+        p_vci_ini_miss.eop     = false;
+        p_vci_ini_miss.cons    = true;
+        p_vci_ini_miss.plen    = 0;
+        p_vci_ini_miss.wrap    = false;
+        p_vci_ini_miss.cfixed  = false;
+        p_vci_ini_miss.clen    = 0;
+        p_vci_ini_miss.trdid   = 0;
+        p_vci_ini_miss.pktid   = 0;
+        
+        p_vci_ini_miss.rspack = true;
+ 
+        break;
+   
+    case MISS_INIT_TLB_MISS_CMD:
+        p_vci_ini_miss.cmdval  = true;
+        p_vci_ini_miss.address = (paddr_t)((r_iotlb_paddr.read())& CACHE_LINE_MASK);
+        p_vci_ini_miss.wdata   = 0x00000000;
+        p_vci_ini_miss.plen    = m_words*(vci_param_d::B);
+        p_vci_ini_miss.trdid   = 0;  //could be used as the index on a miss transaction table
+        p_vci_ini_miss.cmd     = vci_param_d::CMD_READ;
+        p_vci_ini_miss.eop     = true;
+        
+        p_vci_ini_miss.be      = 0xF;
+        p_vci_ini_miss.pktid   = 0;
+        p_vci_ini_miss.cons    = false;
+        p_vci_ini_miss.wrap    = false;
+        p_vci_ini_miss.contig  = true;
+        p_vci_ini_miss.clen    = 0;
+        p_vci_ini_miss.cfixed  = false;
+        break;
+
+    } // end switch r_miss_init_fsm
+} // end genMoore
+
+}}
+
+// Local Variables:
+// tab-width: 4
+// c-basic-offset: 4
+// c-file-offsets:((innamespace . 0)(inline-open . 0))
+// indent-tabs-mode: nil
+// End:
+
+// vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4
Index: branches/v4/modules/vci_mem_cache/caba/metadata/vci_mem_cache.sd
===================================================================
--- branches/v4/modules/vci_mem_cache/caba/metadata/vci_mem_cache.sd	(revision 371)
+++ branches/v4/modules/vci_mem_cache/caba/metadata/vci_mem_cache.sd	(revision 371)
@@ -0,0 +1,25 @@
+
+# -*- python -*-
+
+__id__ = "$Id$"
+__version__ = "$Revision$"
+
+Module('caba:vci_mem_cache',
+       classname = 'soclib::caba::VciMemCache',
+       tmpl_parameters = [parameter.Module('vci_param', default = 'caba:vci_param'),],
+       header_files = ['../source/include/vci_mem_cache.h',
+                       '../source/include/xram_transaction.h',
+                       '../source/include/mem_cache_directory.h',
+                       '../source/include/atomic_tab.h',
+                       '../source/include/update_tab.h',],
+       implementation_files = ['../source/src/vci_mem_cache.cpp',],
+       uses = [Uses('caba:base_module'),
+               Uses('common:loader'),
+               Uses('common:mapping_table'),
+               Uses('caba:generic_fifo'),
+               ],
+       ports = [Port('caba:vci_target', 'p_vci_tgt'),
+                Port('caba:vci_initiator','p_vci_init'),
+                Port('caba:bit_in', 'p_resetn', auto = 'resetn'),
+                Port('caba:clock_in', 'p_clk', auto = 'clock'),],
+)
Index: branches/v4/modules/vci_mem_cache/caba/source/include/atomic_tab.h
===================================================================
--- branches/v4/modules/vci_mem_cache/caba/source/include/atomic_tab.h	(revision 371)
+++ branches/v4/modules/vci_mem_cache/caba/source/include/atomic_tab.h	(revision 371)
@@ -0,0 +1,112 @@
+#ifndef ATOMIC_TAB_H_
+#define ATOMIC_TAB_H_
+
+#include <inttypes.h>
+#include <systemc>
+#include <cassert>
+#include "arithmetics.h"
+
+
+
+////////////////////////////////////////////////////////////////////////
+////////////////////////////////////////////////////////////////////////
+/*                  The atomic access tab                             */
+////////////////////////////////////////////////////////////////////////
+////////////////////////////////////////////////////////////////////////
+
+class AtomicTab{
+    typedef uint32_t size_t;
+    typedef uint32_t addr_t;
+
+private:
+    size_t size_tab;                            // The size of the tab
+    std::vector<addr_t> addr_tab;               // Address entries
+    std::vector<bool>   valid_tab;              // Valid entries
+
+public:
+
+    AtomicTab()
+	: addr_tab(0),
+	  valid_tab(0)
+	{
+	size_tab=0;
+    }
+
+    AtomicTab(size_t size_tab_i)
+	: addr_tab(size_tab_i),
+	  valid_tab(size_tab_i)
+	{
+	size_tab=size_tab_i;
+    }
+
+
+    /////////////////////////////////////////////////////////////////////
+    /* The size() function returns the size of the tab */
+    /////////////////////////////////////////////////////////////////////
+    const size_t size(){
+	return size_tab;
+    }
+
+
+    /////////////////////////////////////////////////////////////////////
+    /* The init() function initializes the transaction tab entries */
+    /////////////////////////////////////////////////////////////////////
+    void init(){
+    	for ( size_t i=0; i<size_tab; i++) {
+		addr_tab[i]=0;
+		valid_tab[i]=false;
+    	}
+    }
+
+
+    /////////////////////////////////////////////////////////////////////
+    /* The set() function sets an entry 
+       Arguments :
+       - id : the id of the initiator (index of the entry)
+       - addr : the address of the lock
+     */
+    /////////////////////////////////////////////////////////////////////
+    void set(const size_t id, const addr_t addr){
+	assert( (id<size_tab) && "Atomic Tab Error : bad entry");
+	addr_tab[id]=addr;
+	valid_tab[id]=true;
+	return;
+    }
+
+
+    /////////////////////////////////////////////////////////////////////
+    /* The isatomic() function tests if the SC request corresponds to an entry
+       Arguments :
+       - id : the id of the initiator (index of the entry)
+       - addr : the address of the lock
+
+       This function return true if the request corresponds
+     */
+    /////////////////////////////////////////////////////////////////////
+    bool isatomic(const size_t id, const addr_t addr){
+	assert( (id<size_tab) && "Atomic Tab Error : bad entry");
+	bool test=valid_tab[id];
+	test=test && (addr == addr_tab[id]);
+	return test;
+    }
+
+
+    /////////////////////////////////////////////////////////////////////
+    /* The reset() function resets all the entries for this lock
+       Arguments :
+       - addr : the address of the lock
+     */
+    /////////////////////////////////////////////////////////////////////
+    void reset(const addr_t addr){
+	for(size_t i=0 ; i<size_tab ; i++){
+		if(addr == addr_tab[i]){
+			valid_tab[i]=false;
+		}
+	}
+	return;
+    }
+
+};
+ 
+#endif
+
Index: branches/v4/modules/vci_mem_cache/caba/source/include/mem_cache_directory.h
===================================================================
--- branches/v4/modules/vci_mem_cache/caba/source/include/mem_cache_directory.h	(revision 371)
+++ branches/v4/modules/vci_mem_cache/caba/source/include/mem_cache_directory.h	(revision 371)
@@ -0,0 +1,288 @@
+#ifndef SOCLIB_CABA_MEM_CACHE_DIRECTORY_H
+#define SOCLIB_CABA_MEM_CACHE_DIRECTORY_H 
+
+#include <inttypes.h>
+#include <systemc>
+#include <cassert>
+#include "arithmetics.h"
+
+namespace soclib { namespace caba {
+
+  using namespace sc_core;
+
+////////////////////////////////////////////////////////////////////////
+//                    A LRU entry 
+////////////////////////////////////////////////////////////////////////
+class LruEntry {
+
+public:
+
+    bool recent;            
+
+    void init()
+    {
+	recent=false;
+    }
+
+}; // end class LruEntry
+
+////////////////////////////////////////////////////////////////////////
+//                    A directory entry                               
+////////////////////////////////////////////////////////////////////////
+class DirectoryEntry {
+
+    typedef uint32_t tag_t;
+    typedef uint32_t size_t;
+    typedef uint32_t copy_t;
+
+public:
+
+    bool	 	valid;                  // entry valid
+    bool	 	dirty;                  // entry dirty
+    bool	 	lock;                   // entry locked
+    tag_t	 	tag;                    // tag of the entry
+    copy_t 		copies;              	// vector of copies 
+
+    DirectoryEntry()
+    {
+	valid   = false;
+	dirty   = false;
+	lock    = false;
+	tag     = 0;
+	copies	= 0;
+    }
+    
+    DirectoryEntry(const DirectoryEntry &source)
+    {
+	valid	= source.valid;
+	dirty	= source.dirty;
+	tag	= source.tag;
+	lock	= source.lock;
+	copies	= source.copies;
+    }
+    
+    /////////////////////////////////////////////////////////////////////
+    // The init() function initializes the entry 
+    /////////////////////////////////////////////////////////////////////
+    void init()
+    {
+	valid = false;
+	dirty = false;
+	lock  = false;
+    }
+    
+    /////////////////////////////////////////////////////////////////////
+    // The copy() function copies an existing source entry to a target 
+    /////////////////////////////////////////////////////////////////////
+    void copy(const DirectoryEntry &source)
+    {
+	valid	= source.valid;
+	dirty	= source.dirty;
+	tag	= source.tag;
+	lock	= source.lock;
+	copies	= source.copies;
+    }
+
+    ////////////////////////////////////////////////////////////////////
+    // The print() function prints the entry 
+    ////////////////////////////////////////////////////////////////////
+    void print()
+    {
+	std::cout << "Valid = " << valid << " ; Dirty = " << dirty << " ; Lock = " 
+  	   << lock << " ; Tag = " << std::hex << tag << " ; copies = " << copies << std::endl;
+    }
+
+}; // end class DirectoryEntry
+
+////////////////////////////////////////////////////////////////////////
+//                       The directory  
+////////////////////////////////////////////////////////////////////////
+class CacheDirectory {
+
+    typedef uint32_t addr_t;
+    typedef uint32_t data_t;
+    typedef uint32_t tag_t;
+    typedef uint32_t size_t;
+
+ private:
+
+// Directory constants
+    size_t					m_ways;
+    size_t					m_sets;
+    size_t					m_words;
+    size_t					m_width;
+
+// the directory & lru tables
+    DirectoryEntry 				**m_dir_tab;
+    LruEntry	 				**m_lru_tab;
+
+ public:
+
+    ////////////////////////
+    // Constructor
+    ////////////////////////
+    CacheDirectory( size_t ways, size_t sets, size_t words, size_t address_width)	 
+    {
+	m_ways 	= ways; 
+	m_sets 	= sets;
+	m_words = words;
+        m_width = address_width;
+
+        m_dir_tab = new DirectoryEntry*[sets];
+        for ( size_t i=0; i<sets; i++ ) {
+            m_dir_tab[i] = new DirectoryEntry[ways];
+            for ( size_t j=0 ; j<ways ; j++) m_dir_tab[i][j].init();
+        }
+        m_lru_tab = new LruEntry*[sets];
+        for ( size_t i=0; i<sets; i++ ) {
+	    m_lru_tab[i] = new LruEntry[ways];
+            for ( size_t j=0 ; j<ways ; j++) m_lru_tab[i][j].init();
+        }
+    } // end constructor
+
+    /////////////////
+    // Destructor
+    /////////////////
+    ~CacheDirectory()
+    {
+        for(size_t i=0 ; i<m_sets ; i++){
+	    delete [] m_dir_tab[i];
+    	    delete [] m_lru_tab[i];
+        }
+        delete [] m_dir_tab;
+        delete [] m_lru_tab;
+    } // end destructor
+
+    /////////////////////////////////////////////////////////////////////
+    // The read() function reads a directory entry. In case of hit, the
+    // LRU is updated.
+    // Arguments :
+    // - address : the address of the entry 
+    // - way : (return argument) the way of the entry in case of hit
+    // The function returns a copy of a (valid or invalid) entry  
+    /////////////////////////////////////////////////////////////////////
+    DirectoryEntry read(const addr_t &address,size_t &way)
+    {
+
+      #define L2 soclib::common::uint32_log2
+      const size_t set = (size_t)(address >> (L2(m_words) + 2)) & (m_sets - 1);
+      const tag_t  tag = (tag_t)(address >> (L2(m_sets) + L2(m_words) + 2));
+      #undef L2
+
+      bool hit       = false;
+      for ( size_t i=0 ; i<m_ways ; i++ ) {
+        bool equal = ( m_dir_tab[set][i].tag == tag );
+        bool valid = m_dir_tab[set][i].valid;
+        hit = equal && valid;
+        if ( hit ) {			
+          way = i;
+          break;
+        } 
+      }
+      if ( hit ) {
+        m_lru_tab[set][way].recent = true;
+        return DirectoryEntry(m_dir_tab[set][way]);
+      } else {
+        return DirectoryEntry();
+      }
+    } // end read()
+
+    /////////////////////////////////////////////////////////////////////
+    // The write function writes a new entry, 
+    // and updates the LRU bits if necessary.
+    // Arguments :
+    // - set : the set of the entry
+    // - way : the way of the entry
+    // - entry : the entry value
+    /////////////////////////////////////////////////////////////////////
+    void write(const size_t &set, const size_t &way, const DirectoryEntry &entry)
+    {
+      assert( (set<m_sets) 
+		&& "Cache Directory write : The set index is invalid");
+      assert( (way<m_ways) 
+		&& "Cache Directory write : The way index is invalid");
+
+      // update Directory
+      m_dir_tab[set][way].copy(entry);
+
+      // update LRU bits
+      bool all_recent = true;
+      for ( size_t i=0 ; i<m_ways ; i++ ) {
+        if ( i != way ) all_recent = m_lru_tab[set][i].recent && all_recent;
+      }
+      if ( all_recent ) {
+        for( size_t i=0 ; i<m_ways ; i++ ) m_lru_tab[set][i].recent = false;
+      } else {
+        m_lru_tab[set][way].recent = true;
+      }
+    } // end write()
+
+    /////////////////////////////////////////////////////////////////////
+    // The print() function prints a selected directory entry
+    // Arguments :
+    // - set : the set of the entry to print
+    // - way : the way of the entry to print
+    /////////////////////////////////////////////////////////////////////
+    void print(const size_t &set, const size_t &way)
+    {
+	std::cout << std::dec << " set : " << set << " ; way : " << way << " ; " ;
+	m_dir_tab[set][way].print();
+    } // end print()
+    
+    /////////////////////////////////////////////////////////////////////
+    // The select() function selects a directory entry to evince.
+    // Arguments :
+    // - set   : (input argument) the set to modify
+    // - way   : (return argument) the way to evince
+    /////////////////////////////////////////////////////////////////////
+    DirectoryEntry select(const size_t &set, size_t &way)
+    {
+	assert( (set < m_sets) 
+		&& "Cache Directory : (select) The set index is invalid");
+
+	for(size_t i=0; i<m_ways; i++){
+		if(!(m_lru_tab[set][i].recent) && !(m_dir_tab[set][i].lock)){
+			way=i;
+			return DirectoryEntry(m_dir_tab[set][way]);
+		}
+	}
+	for(size_t i=0; i<m_ways; i++){
+		if( !(m_lru_tab[set][i].recent) && (m_dir_tab[set][i].lock)){
+			way=i;
+			return DirectoryEntry(m_dir_tab[set][way]);
+		}
+	}
+	for(size_t i=0; i<m_ways; i++){
+		if( (m_lru_tab[set][i].recent) && !(m_dir_tab[set][i].lock)){
+			way=i;
+			return DirectoryEntry(m_dir_tab[set][way]);
+		}
+	}
+	for(size_t i=0; i<m_ways; i++){
+		if( (m_lru_tab[set][i].recent) && (m_dir_tab[set][i].lock)){
+			way=i;
+			return DirectoryEntry(m_dir_tab[set][way]);
+		}
+	}
+	way = 0;
+	return DirectoryEntry(m_dir_tab[set][0]);
+    } // end select()
+
+    /////////////////////////////////////////////////////////////////////
+    // 		Global initialisation function
+    /////////////////////////////////////////////////////////////////////
+    void init()
+    {
+        for ( size_t set=0 ; set<m_sets ; set++ ) {
+            for ( size_t way=0 ; way<m_ways ; way++ ) {
+                m_dir_tab[set][way].init();
+                m_lru_tab[set][way].init();
+            }
+        }
+    } // end init()
+ 
+}; // end class CacheDirectory
+ 
+}} // end namespaces
+
+#endif
Index: branches/v4/modules/vci_mem_cache/caba/source/include/update_tab.h
===================================================================
--- branches/v4/modules/vci_mem_cache/caba/source/include/update_tab.h	(revision 371)
+++ branches/v4/modules/vci_mem_cache/caba/source/include/update_tab.h	(revision 371)
@@ -0,0 +1,264 @@
+#ifndef UPDATE_TAB_H_
+#define UPDATE_TAB_H_
+
+#include <inttypes.h>
+#include <systemc>
+#include <cassert>
+#include "arithmetics.h"
+
+////////////////////////////////////////////////////////////////////////
+//                  An update tab entry    
+////////////////////////////////////////////////////////////////////////
+class UpdateTabEntry {
+  typedef uint32_t size_t;
+
+ public:
+  bool 	valid;                // It is a valid pending transaction
+  bool	update;               // It is an update transaction 
+  size_t 	srcid;                // The srcid of the initiator which wrote the data
+  size_t 	trdid;                // The trdid of the initiator which wrote the data
+  size_t 	pktid;                // The pktid of the initiator which wrote the data
+  size_t 	count;                // The number of acknowledge responses to receive
+
+  UpdateTabEntry(){
+    valid	= false;
+    update	= false;
+    srcid	= 0;
+    trdid	= 0;
+    pktid	= 0;
+    count	= 0;
+  }
+
+  UpdateTabEntry(bool   i_valid, 
+		 bool   i_update, 
+		 size_t i_srcid, 
+		 size_t i_trdid, 
+		 size_t i_pktid, 
+		 size_t i_count) 
+    {
+      valid		= i_valid;
+      update		= i_update;
+      srcid		= i_srcid;
+      trdid		= i_trdid;
+      pktid		= i_pktid;
+      count		= i_count;
+    }
+
+  UpdateTabEntry(const UpdateTabEntry &source)
+    {
+      valid		= source.valid;
+      update 		= source.update;
+      srcid		= source.srcid;
+      trdid		= source.trdid;
+      pktid		= source.pktid;
+      count  		= source.count;
+    }
+
+  ////////////////////////////////////////////////////
+  // The init() function initializes the entry 
+  ///////////////////////////////////////////////////
+  void init()
+  {
+    valid=false;
+    update=false;
+    srcid=0;
+    trdid=0;
+    pktid=0;
+    count=0;
+  }
+
+  ////////////////////////////////////////////////////////////////////
+  // The copy() function copies an existing entry
+  // Its arguments are :
+  // - source : the update tab entry to copy
+  ////////////////////////////////////////////////////////////////////
+  void copy(const UpdateTabEntry &source)
+  {
+    valid=source.valid;
+    update=source.update;
+    srcid=source.srcid;
+    trdid=source.trdid;
+    pktid=source.pktid;
+    count=source.count;
+  }
+
+  ////////////////////////////////////////////////////////////////////
+  // The print() function prints the entry  
+  ////////////////////////////////////////////////////////////////////
+  void print(){
+    std::cout << "valid = " << valid << std::endl;
+    std::cout << "update = " << update << std::endl;
+    std::cout << "srcid = " << srcid << std::endl; 
+    std::cout << "trdid = " << trdid << std::endl; 
+    std::cout << "pktid = " << pktid << std::endl; 
+    std::cout << "count = " << count << std::endl;
+  }
+};
+
+////////////////////////////////////////////////////////////////////////
+//                        The update tab             
+////////////////////////////////////////////////////////////////////////
+class UpdateTab{
+
+  typedef uint32_t size_t;
+
+ private:
+  size_t size_tab;
+  std::vector<UpdateTabEntry> tab;
+
+ public:
+
+ UpdateTab()
+   : tab(0)
+    {
+      size_tab=0;
+    }
+
+ UpdateTab(size_t size_tab_i)
+   : tab(size_tab_i)
+  {
+    size_tab=size_tab_i;
+  }
+
+  ////////////////////////////////////////////////////////////////////
+  // The size() function returns the size of the tab  
+  ////////////////////////////////////////////////////////////////////
+  const size_t size(){
+    return size_tab;
+  }
+
+
+  /////////////////////////////////////////////////////////////////////
+  // The init() function initializes the tab 
+  /////////////////////////////////////////////////////////////////////
+  void init(){
+    for ( size_t i=0; i<size_tab; i++) {
+      tab[i].init();
+    }
+  }
+
+
+  /////////////////////////////////////////////////////////////////////
+  // The reads() function reads an entry 
+  // Arguments :
+  // - entry : the entry to read
+  // This function returns a copy of the entry.
+  /////////////////////////////////////////////////////////////////////
+  UpdateTabEntry read (size_t entry)
+  {
+    assert(entry<size_tab && "Bad Update Tab Entry");
+    return UpdateTabEntry(tab[entry]);
+  }
+
+  ///////////////////////////////////////////////////////////////////////////
+  // The set() function writes an entry in the Update Table
+  // Arguments :
+  // - update : transaction type (bool)
+  // - srcid : srcid of the initiator
+  // - trdid : trdid of the initiator
+  // - pktid : pktid of the initiator
+  // - count : number of expected responses
+  // - index : (return argument) index of the selected entry
+  // This function returns true if the write successed (an entry was empty).
+  ///////////////////////////////////////////////////////////////////////////
+  bool set(const bool	update,
+	   const size_t srcid,
+	   const size_t trdid,
+	   const size_t pktid,
+	   const size_t count,
+	   size_t &index)
+  {
+    for ( size_t i=0 ; i<size_tab ; i++ ) {
+      if( !tab[i].valid ) {
+	tab[i].valid		= true;
+	tab[i].update		= update;
+	tab[i].srcid		= (size_t) srcid;
+	tab[i].trdid		= (size_t) trdid;
+	tab[i].pktid		= (size_t) pktid;
+	tab[i].count		= (size_t) count;
+	index			= i;
+	return true;
+      }
+    }
+    return false;
+  } // end set()
+
+    /////////////////////////////////////////////////////////////////////
+    // The decrement() function decrements the counter for a given entry.
+    // Arguments :
+    // - index   : the index of the entry
+    // - counter : (return argument) value of the counter after decrement
+    // This function returns true if the entry is valid.
+    /////////////////////////////////////////////////////////////////////
+  bool decrement( const size_t index,
+		  size_t &counter ) 
+  {
+    assert((index<size_tab) && "Bad Update Tab Entry");
+    if ( tab[index].valid ) {
+      tab[index].count--;
+      counter = tab[index].count;
+      return true;
+    } else {
+      return false;
+    }
+  }
+
+  /////////////////////////////////////////////////////////////////////
+  // The is_update() function returns the transaction type
+  // Arguments :
+  // - index : the index of the entry
+  /////////////////////////////////////////////////////////////////////
+  bool is_update(const size_t index)
+  {
+    assert(index<size_tab && "Bad Update Tab Entry");
+    return tab[index].update;	
+  }
+
+  /////////////////////////////////////////////////////////////////////
+  // The srcid() function returns the srcid value
+  // Arguments :
+  // - index : the index of the entry
+  /////////////////////////////////////////////////////////////////////
+  size_t srcid(const size_t index)
+  {
+    assert(index<size_tab && "Bad Update Tab Entry");
+    return tab[index].srcid;	
+  }
+
+  /////////////////////////////////////////////////////////////////////
+  // The trdid() function returns the trdid value
+  // Arguments :
+  // - index : the index of the entry
+  /////////////////////////////////////////////////////////////////////
+  size_t trdid(const size_t index)
+  {
+    assert(index<size_tab && "Bad Update Tab Entry");
+    return tab[index].trdid;	
+  }
+
+  /////////////////////////////////////////////////////////////////////
+  // The pktid() function returns the pktid value
+  // Arguments :
+  // - index : the index of the entry
+  /////////////////////////////////////////////////////////////////////
+  size_t pktid(const size_t index)
+  {
+    assert(index<size_tab && "Bad Update Tab Entry");
+    return tab[index].pktid;	
+  }
+
+  /////////////////////////////////////////////////////////////////////
+  // The clear() function erases an entry of the tab
+  // Arguments :
+  // - index : the index of the entry
+  /////////////////////////////////////////////////////////////////////       
+  void clear(const size_t index)
+  {
+    assert(index<size_tab && "Bad Update Tab Entry");
+    tab[index].valid=false;
+    return;	
+  }
+
+};
+
+#endif
Index: branches/v4/modules/vci_mem_cache/caba/source/include/vci_mem_cache.h
===================================================================
--- branches/v4/modules/vci_mem_cache/caba/source/include/vci_mem_cache.h	(revision 371)
+++ branches/v4/modules/vci_mem_cache/caba/source/include/vci_mem_cache.h	(revision 371)
@@ -0,0 +1,563 @@
+/* -*- c++ -*-
+ * File         : vci_mem_cache.h
+ * Date         : 26/10/2008
+ * Copyright    : UPMC / LIP6
+ * Authors      : Alain Greiner / Eric Guthmuller
+ *
+ * SOCLIB_LGPL_HEADER_BEGIN
+ *
+ * This file is part of SoCLib, GNU LGPLv2.1.
+ *
+ * SoCLib is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU Lesser General Public License as published
+ * by the Free Software Foundation; version 2.1 of the License.
+ *
+ * SoCLib is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with SoCLib; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301 USA
+ *
+ * SOCLIB_LGPL_HEADER_END
+ *
+ * Maintainers: alain eric.guthmuller@polytechnique.edu
+ */
+
+#ifndef SOCLIB_CABA_MEM_CACHE_H
+#define SOCLIB_CABA_MEM_CACHE_H
+
+#include <inttypes.h>
+#include <systemc>
+#include <list>
+#include <cassert>
+#include "arithmetics.h"
+#include "alloc_elems.h"
+#include "caba_base_module.h"
+#include "vci_target.h"
+#include "vci_initiator.h"
+#include "generic_fifo.h"
+#include "mapping_table.h"
+#include "int_tab.h"
+#include "mem_cache_directory.h"
+#include "xram_transaction.h"
+#include "update_tab.h"
+#include "atomic_tab.h"
+
+#define TRANSACTION_TAB_LINES 4     // Number of lines in the transaction tab
+#define UPDATE_TAB_LINES 4          // Number of lines in the update tab
+
+namespace soclib {  namespace caba {
+    using namespace sc_core;
+
+    template<typename vci_param>
+    class VciMemCache
+      : public soclib::caba::BaseModule
+    {
+      typedef uint32_t addr_t;
+      typedef uint32_t data_t;
+      typedef uint32_t tag_t;
+      typedef uint32_t size_t;
+      typedef uint32_t be_t;
+      typedef uint32_t copy_t;
+
+      /* States of the TGT_CMD fsm */
+      enum tgt_cmd_fsm_state_e{
+        TGT_CMD_IDLE,
+	TGT_CMD_READ,
+	TGT_CMD_READ_EOP,
+	TGT_CMD_WRITE,
+	TGT_CMD_ATOMIC,
+	TGT_CMD_CLEANUP,
+      };
+
+      /* States of the TGT_RSP fsm */
+      enum tgt_rsp_fsm_state_e{
+	TGT_RSP_READ_IDLE,
+	TGT_RSP_WRITE_IDLE,
+	TGT_RSP_LLSC_IDLE,
+        TGT_RSP_CLEANUP_IDLE,
+	TGT_RSP_XRAM_IDLE,
+	TGT_RSP_INIT_IDLE,
+        TGT_RSP_READ_TEST,
+	TGT_RSP_READ_WORD,
+	TGT_RSP_READ_LINE,
+	TGT_RSP_WRITE,
+	TGT_RSP_LLSC,
+	TGT_RSP_CLEANUP,
+        TGT_RSP_XRAM_TEST,
+	TGT_RSP_XRAM_WORD,
+	TGT_RSP_XRAM_LINE,
+        TGT_RSP_INIT,
+      };
+
+      /* States of the INIT_CMD fsm */
+      enum init_cmd_fsm_state_e{
+	INIT_CMD_INVAL_IDLE,
+	INIT_CMD_INVAL_SEL,
+	INIT_CMD_INVAL_NLINE,
+        INIT_CMD_UPDT_IDLE,
+	INIT_CMD_UPDT_SEL,
+	INIT_CMD_UPDT_NLINE,
+	INIT_CMD_UPDT_INDEX,
+	INIT_CMD_UPDT_DATA,
+      };
+
+      /* States of the INIT_RSP fsm */
+      enum init_rsp_fsm_state_e{
+        INIT_RSP_IDLE,
+	INIT_RSP_UPT_LOCK,
+	INIT_RSP_UPT_CLEAR,
+	INIT_RSP_END,
+      };
+
+      /* States of the READ fsm */
+      enum read_fsm_state_e{
+        READ_IDLE,
+	READ_DIR_LOCK,
+	READ_DIR_HIT,
+	READ_RSP,
+	READ_TRT_LOCK,
+        READ_TRT_SET,
+	READ_XRAM_REQ,
+      };
+
+      /* States of the WRITE fsm */
+      enum write_fsm_state_e{
+        WRITE_IDLE,
+        WRITE_NEXT,
+	WRITE_DIR_LOCK,
+	WRITE_DIR_HIT_READ,
+	WRITE_DIR_HIT,
+        WRITE_UPT_LOCK,
+        WRITE_WAIT_UPT,
+	WRITE_UPDATE,
+	WRITE_RSP,
+	WRITE_TRT_LOCK,
+	WRITE_TRT_DATA,
+	WRITE_TRT_SET,
+	WRITE_WAIT_TRT,
+	WRITE_XRAM_REQ,
+      };
+
+      /* States of the IXR_RSP fsm */
+      enum ixr_rsp_fsm_state_e{
+    	IXR_RSP_IDLE,
+        IXR_RSP_ACK,
+	IXR_RSP_TRT_ERASE,
+	IXR_RSP_TRT_READ,
+      };
+
+      /* States of the XRAM_RSP fsm */
+      enum xram_rsp_fsm_state_e{
+    	XRAM_RSP_IDLE,
+	XRAM_RSP_TRT_COPY,
+	XRAM_RSP_TRT_DIRTY,
+	XRAM_RSP_DIR_LOCK,
+	XRAM_RSP_DIR_UPDT,
+	XRAM_RSP_DIR_RSP,
+        XRAM_RSP_UPT_LOCK,
+        XRAM_RSP_WAIT,
+	XRAM_RSP_INVAL,
+        XRAM_RSP_WRITE_DIRTY,
+      };
+
+      /* States of the XRAM_CMD fsm */
+      enum xram_cmd_fsm_state_e{
+    	XRAM_CMD_READ_IDLE,
+    	XRAM_CMD_WRITE_IDLE,
+    	XRAM_CMD_LLSC_IDLE,
+    	XRAM_CMD_XRAM_IDLE,
+    	XRAM_CMD_READ_NLINE,
+    	XRAM_CMD_WRITE_NLINE,
+    	XRAM_CMD_LLSC_NLINE,
+    	XRAM_CMD_XRAM_DATA,
+      };
+
+      /* States of the LLSC fsm */
+      enum llsc_fsm_state_e{
+	LLSC_IDLE,
+	LL_DIR_LOCK,
+	LL_DIR_HIT,
+	LL_RSP,
+	SC_DIR_LOCK,
+	SC_DIR_HIT,
+	SC_RSP_FALSE,
+	SC_RSP_TRUE,
+	LLSC_TRT_LOCK,
+	LLSC_TRT_SET,
+	LLSC_XRAM_REQ,
+      };
+
+      /* States of the CLEANUP fsm */
+      enum cleanup_fsm_state_e{
+	CLEANUP_IDLE,
+	CLEANUP_DIR_LOCK,
+	CLEANUP_DIR_WRITE,
+	CLEANUP_RSP,
+      };
+
+      /* States of the ALLOC_DIR fsm */
+      enum alloc_dir_fsm_state_e{
+	ALLOC_DIR_READ,
+	ALLOC_DIR_WRITE,
+	ALLOC_DIR_LLSC,
+        ALLOC_DIR_CLEANUP,
+	ALLOC_DIR_XRAM_RSP,
+      };
+
+      /* States of the ALLOC_TRT fsm */
+      enum alloc_trt_fsm_state_e{
+	ALLOC_TRT_READ,
+	ALLOC_TRT_WRITE,
+	ALLOC_TRT_LLSC,
+	ALLOC_TRT_XRAM_RSP,
+	ALLOC_TRT_IXR_RSP,
+      };
+
+      /* States of the ALLOC_UPT fsm */
+      enum alloc_upt_fsm_state_e{
+	ALLOC_UPT_WRITE,
+	ALLOC_UPT_XRAM_RSP,
+	ALLOC_UPT_INIT_RSP,
+      };
+
+      uint32_t	   m_cpt_cycles;            // Counter of cycles 
+      uint32_t	   m_cpt_read;              // Number of READ transactions
+      uint32_t	   m_cpt_read_miss;         // Number of MISS READ 
+      uint32_t	   m_cpt_write;             // Number of WRITE transactions
+      uint32_t	   m_cpt_write_miss;        // Number of MISS WRITE
+      uint32_t       m_cpt_write_cells;	    // Cumulated length for WRITE transactions
+      uint32_t       m_cpt_write_dirty;	    // Cumulated length for WRITE transactions
+      uint32_t	   m_cpt_update;            // Number of UPDATE transactions
+      uint32_t	   m_cpt_update_mult;       // Number of targets for UPDATE
+      uint32_t	   m_cpt_inval;             // Number of INVAL  transactions
+      uint32_t	   m_cpt_inval_mult;        // Number of targets for INVAL  
+      uint32_t	   m_cpt_cleanup;           // Number of CLEANUP transactions
+      uint32_t	   m_cpt_ll;                // Number of LL transactions
+      uint32_t	   m_cpt_sc;                // Number of SC transactions
+
+    protected:
+
+      SC_HAS_PROCESS(VciMemCache);
+    
+    public:
+      sc_in<bool> 			  	p_clk;
+      sc_in<bool> 			  	p_resetn;
+      soclib::caba::VciTarget<vci_param>    	p_vci_tgt;
+      soclib::caba::VciInitiator<vci_param> 	p_vci_ini;	
+      soclib::caba::VciInitiator<vci_param> 	p_vci_ixr;
+
+      VciMemCache(
+		  sc_module_name name,                            // Instance Name 
+		  const soclib::common::MappingTable &mtp,        // Mapping table for primary requets
+		  const soclib::common::MappingTable &mtc,        // Mapping table for coherence requets
+		  const soclib::common::MappingTable &mtx,        // Mapping table for XRAM
+		  const soclib::common::IntTab &vci_ixr_index,  	// VCI port to XRAM (initiator)
+		  const soclib::common::IntTab &vci_ini_index,  	// VCI port to PROC (initiator)
+		  const soclib::common::IntTab &vci_tgt_index,    // VCI port to PROC (target)
+		  size_t nways,                                   // Number of ways per set 
+		  size_t nsets,                                   // Number of sets
+		  size_t nwords);                                 // Number of words per line
+
+      ~VciMemCache();
+
+      void transition();
+
+      void genMoore();
+
+      void print_stats();
+
+    private:
+
+      // Component attributes
+      const size_t   			  m_initiators;		// Number of initiators
+      const size_t			  m_ways;		// Number of ways in a set
+      const size_t			  m_sets;		// Number of cache sets
+      const size_t			  m_words;		// Number of words in a line
+      const size_t  		  	  m_srcid_ixr;		// Srcid for requests to XRAM 
+      const size_t  		  	  m_srcid_ini;		// Srcid for requests to processors
+      //soclib::common::Segment	  	  m_mem_segment;	// memory cached into the cache
+      std::list<soclib::common::Segment>	  	  m_seglist;	// memory cached into the cache
+      soclib::common::Segment	  	  m_reg_segment;	// memory cache mapped registers
+      addr_t	        		  *m_coherence_table; 	// address(srcid)
+      AtomicTab	   			  m_atomic_tab;		// atomic access table
+      TransactionTab      		  m_transaction_tab;	// xram transaction table
+      UpdateTab				  m_update_tab;		// pending update & invalidate 
+      CacheDirectory			  m_cache_directory;	// data cache directory
+
+      data_t	        	          ***m_cache_data;	// data array[set][way][word]
+
+      // adress masks
+      const soclib::common::AddressMaskingTable<addr_t>   m_x;
+      const soclib::common::AddressMaskingTable<addr_t>   m_y;
+      const soclib::common::AddressMaskingTable<addr_t>   m_z;
+      const soclib::common::AddressMaskingTable<addr_t>	m_nline; 
+
+      //////////////////////////////////////////////////
+      // Registers controlled by the TGT_CMD fsm
+      //////////////////////////////////////////////////
+
+      // Fifo between TGT_CMD fsm and READ fsm
+      GenericFifo<addr_t>    m_cmd_read_addr_fifo;
+      GenericFifo<bool>      m_cmd_read_word_fifo;
+      GenericFifo<size_t>    m_cmd_read_srcid_fifo;
+      GenericFifo<size_t>    m_cmd_read_trdid_fifo;
+      GenericFifo<size_t>    m_cmd_read_pktid_fifo;
+
+      // Fifo between TGT_CMD fsm and WRITE fsm    
+      GenericFifo<addr_t>    m_cmd_write_addr_fifo;
+      GenericFifo<bool>      m_cmd_write_eop_fifo;
+      GenericFifo<size_t>    m_cmd_write_srcid_fifo;
+      GenericFifo<size_t>    m_cmd_write_trdid_fifo;
+      GenericFifo<size_t>    m_cmd_write_pktid_fifo;
+      GenericFifo<data_t>	   m_cmd_write_data_fifo;
+      GenericFifo<be_t>	   m_cmd_write_be_fifo;
+
+      // Fifo between TGT_CMD fsm and LLSC fsm
+      GenericFifo<addr_t>    m_cmd_llsc_addr_fifo;
+      GenericFifo<bool>      m_cmd_llsc_sc_fifo;
+      GenericFifo<size_t>    m_cmd_llsc_srcid_fifo;
+      GenericFifo<size_t>    m_cmd_llsc_trdid_fifo;
+      GenericFifo<size_t>    m_cmd_llsc_pktid_fifo;
+      GenericFifo<data_t>	   m_cmd_llsc_wdata_fifo;
+
+      // Fifo between TGT_CMD fsm and CLEANUP fsm
+      GenericFifo<size_t>    m_cmd_cleanup_srcid_fifo;
+      GenericFifo<size_t>    m_cmd_cleanup_trdid_fifo;
+      GenericFifo<size_t>    m_cmd_cleanup_pktid_fifo;
+      GenericFifo<data_t>	   m_cmd_cleanup_nline_fifo;
+
+      sc_signal<int>         r_tgt_cmd_fsm;
+	
+      sc_signal<size_t>	     r_index;
+      size_t nseg;
+      soclib::common::Segment  **m_seg;
+      ///////////////////////////////////////////////////////
+      // Registers controlled by the READ fsm
+      ///////////////////////////////////////////////////////
+
+      sc_signal<int>         r_read_fsm;				// FSM state 
+      sc_signal<copy_t>      r_read_copies;			// bit-vector of copies 
+      sc_signal<tag_t>       r_read_tag;				// cache line tag (in directory)
+      sc_signal<bool>        r_read_lock;				// lock bit (in directory)
+      sc_signal<bool>        r_read_dirty;			// dirty bit (in directory)
+      sc_signal<data_t>     *r_read_data;				// data (one cache line)
+      sc_signal<bool>        r_read_word;				// single word read
+      sc_signal<size_t>      r_read_way;				// associative way (in cache)
+      sc_signal<size_t>      r_read_trt_index;			// Transaction Table index
+    
+      // Buffer between READ fsm and XRAM_CMD fsm (ask a missing cache line to XRAM)   
+      sc_signal<bool>        r_read_to_xram_cmd_req;		// valid request
+      sc_signal<data_t>      r_read_to_xram_cmd_nline;		// cache line index
+      sc_signal<size_t>      r_read_to_xram_cmd_trdid;		// index in Transaction Table
+
+      // Buffer between READ fsm and TGT_RSP fsm (send a hit read response to L1 cache)
+      sc_signal<bool>	   r_read_to_tgt_rsp_req;		// valid request
+      sc_signal<size_t>	   r_read_to_tgt_rsp_srcid;		// Transaction srcid
+      sc_signal<size_t>	   r_read_to_tgt_rsp_trdid;		// Transaction trdid
+      sc_signal<size_t>	   r_read_to_tgt_rsp_pktid;		// Transaction pktid
+      sc_signal<data_t> 	  *r_read_to_tgt_rsp_data;		// data (one cache line)
+      sc_signal<bool> 	  *r_read_to_tgt_rsp_val;		// valid bit (for single_word)
+
+      ///////////////////////////////////////////////////////////////
+      // Registers controlled by the WRITE fsm
+      ///////////////////////////////////////////////////////////////
+
+      sc_signal<int>         r_write_fsm;				// FSM state
+      sc_signal<addr_t>	   r_write_address;			// first word address
+      sc_signal<size_t>      r_write_word_index;			// first word index in line
+      sc_signal<size_t>      r_write_word_count;			// number of words in line
+      sc_signal<size_t>      r_write_srcid;			// transaction srcid
+      sc_signal<size_t>      r_write_trdid;			// transaction trdid
+      sc_signal<size_t>      r_write_pktid;			// transaction pktid
+      sc_signal<data_t>	  *r_write_data;			// data (one cache line)	
+      sc_signal<be_t>       *r_write_be;				// one byte enable per word
+      sc_signal<bool>        r_write_byte;			// is it a byte write
+      sc_signal<bool>        r_write_lock;			// lock bit (in directory)
+      sc_signal<tag_t>       r_write_tag;	  			// cache line tag (in directory)
+      sc_signal<copy_t>      r_write_copies;			// bit vector of copies
+      sc_signal<size_t>	   r_write_nb_copies;			// number of copies
+      sc_signal<size_t>	   r_write_way;				// way of the line
+      sc_signal<size_t>      r_write_trt_index;			// index in Transaction Table
+      sc_signal<size_t>      r_write_upt_index;			// index in Update Table
+
+      // Buffer between WRITE fsm and TGT_RSP fsm (acknowledge a write command from L1)
+      sc_signal<bool>        r_write_to_tgt_rsp_req;		// valid request
+      sc_signal<size_t>      r_write_to_tgt_rsp_srcid;		// transaction srcid
+      sc_signal<size_t>      r_write_to_tgt_rsp_trdid;		// transaction trdid
+      sc_signal<size_t>      r_write_to_tgt_rsp_pktid;		// transaction pktid
+
+      // Buffer between WRITE fsm and XRAM_CMD fsm (ask a missing cache line to XRAM) 
+      sc_signal<bool>	   r_write_to_xram_cmd_req;		// valid request
+      sc_signal<data_t>      r_write_to_xram_cmd_nline;		// cache line index
+      sc_signal<size_t>      r_write_to_xram_cmd_trdid;		// index in Transaction Table
+
+      // Buffer between WRITE fsm and INIT_CMD fsm (Update L1 caches)
+      sc_signal<bool>	   r_write_to_init_cmd_req;		// valid request
+      sc_signal<data_t>	   r_write_to_init_cmd_nline;		// cache line index
+      sc_signal<size_t>	   r_write_to_init_cmd_trdid;		// index in Update Table
+      sc_signal<copy_t>      r_write_to_init_cmd_copies;		// bit_vector of L1 to update
+      sc_signal<data_t>     *r_write_to_init_cmd_data;		// data (one cache line)
+      sc_signal<bool>       *r_write_to_init_cmd_we;		// word enable
+      sc_signal<size_t>	   r_write_to_init_cmd_count;		// number of words in line
+      sc_signal<size_t>	   r_write_to_init_cmd_index;		// index of first word in line
+
+      /////////////////////////////////////////////////////////
+      // Registers controlled by INIT_RSP fsm
+      //////////////////////////////////////////////////////////
+
+      sc_signal<int> 	   r_init_rsp_fsm;			// FSM state
+      sc_signal<size_t>	   r_init_rsp_upt_index;		// index in the Update Table
+      sc_signal<size_t>	   r_init_rsp_srcid;			// pending write srcid      
+      sc_signal<size_t>	   r_init_rsp_trdid;			// pending write trdid      
+      sc_signal<size_t>	   r_init_rsp_pktid;			// pending write pktid      
+
+      // Buffer between INIT_RSP fsm and TGT_RSP fsm (complete write/update transaction)
+      sc_signal<bool>	   r_init_rsp_to_tgt_rsp_req;   	// valid request
+      sc_signal<size_t>	   r_init_rsp_to_tgt_rsp_srcid;		// Transaction srcid
+      sc_signal<size_t>	   r_init_rsp_to_tgt_rsp_trdid;		// Transaction trdid
+      sc_signal<size_t>	   r_init_rsp_to_tgt_rsp_pktid;		// Transaction pktid
+
+      ///////////////////////////////////////////////////////
+      // Registers controlled by CLEANUP fsm
+      ///////////////////////////////////////////////////////
+
+      sc_signal<int> 	   r_cleanup_fsm;			// FSM state
+      sc_signal<size_t>      r_cleanup_srcid;			// transaction srcid
+      sc_signal<size_t>      r_cleanup_trdid;			// transaction trdid
+      sc_signal<size_t>      r_cleanup_pktid;			// transaction pktid
+      sc_signal<data_t>      r_cleanup_nline;			// cache line index
+
+      sc_signal<copy_t>      r_cleanup_copies;			// bit-vector of copies 
+      sc_signal<tag_t>       r_cleanup_tag;			// cache line tag (in directory)
+      sc_signal<bool>        r_cleanup_lock;			// lock bit (in directory)
+      sc_signal<bool>        r_cleanup_dirty;			// dirty bit (in directory)
+      sc_signal<size_t>      r_cleanup_way;			// associative way (in cache)
+
+      // Buffer between CLEANUP fsm and TGT_RSP fsm (acknowledge a cleanup command from L1)
+      sc_signal<bool>        r_cleanup_to_tgt_rsp_req;		// valid request
+      sc_signal<size_t>      r_cleanup_to_tgt_rsp_srcid;		// transaction srcid
+      sc_signal<size_t>      r_cleanup_to_tgt_rsp_trdid;		// transaction trdid
+      sc_signal<size_t>      r_cleanup_to_tgt_rsp_pktid;		// transaction pktid
+
+      ///////////////////////////////////////////////////////
+      // Registers controlled by LLSC fsm
+      ///////////////////////////////////////////////////////
+
+      sc_signal<int> 	   r_llsc_fsm;				// FSM state
+      sc_signal<data_t>	   r_llsc_data;				// read data word
+      sc_signal<copy_t>  	   r_llsc_copies;			// bit_vector of copies
+      sc_signal<bool>    	   r_llsc_dirty;			// dirty bit (in directory)
+      sc_signal<size_t>  	   r_llsc_way;				// way in directory
+      sc_signal<size_t>  	   r_llsc_set;				// set in directory
+      sc_signal<data_t>  	   r_llsc_tag;				// cache line tag (in directory)
+      sc_signal<size_t>  	   r_llsc_trt_index;    		// Transaction Table index
+
+      // Buffer between LLSC fsm and INIT_CMD fsm (XRAM read)	
+      sc_signal<bool>	   r_llsc_to_xram_cmd_req;		// valid request
+      sc_signal<data_t>	   r_llsc_to_xram_cmd_nline;		// cache line index
+      sc_signal<size_t>	   r_llsc_to_xram_cmd_trdid;		// index in Transaction Table
+
+      // Buffer between LLSC fsm and TGT_RSP fsm
+      sc_signal<bool>	   r_llsc_to_tgt_rsp_req;		// valid request
+      sc_signal<data_t> 	   r_llsc_to_tgt_rsp_data;		// read data word
+      sc_signal<size_t>	   r_llsc_to_tgt_rsp_srcid;		// Transaction srcid
+      sc_signal<size_t>	   r_llsc_to_tgt_rsp_trdid;		// Transaction trdid
+      sc_signal<size_t>	   r_llsc_to_tgt_rsp_pktid;		// Transaction pktid
+
+      ////////////////////////////////////////////////////
+      // Registers controlled by the IXR_RSP fsm
+      ////////////////////////////////////////////////////
+
+      sc_signal<int> 	   r_ixr_rsp_fsm;			// FSM state
+      sc_signal<size_t>	   r_ixr_rsp_trt_index;			// TRT entry index
+      sc_signal<size_t> 	   r_ixr_rsp_cpt;			// word counter
+
+      // Buffer between IXR_RSP fsm and XRAM_RSP fsm  (response from the XRAM)
+      sc_signal<bool>	  *r_ixr_rsp_to_xram_rsp_rok;		// A xram response is ready
+
+      ////////////////////////////////////////////////////
+      // Registers controlled by the XRAM_RSP fsm
+      ////////////////////////////////////////////////////
+
+      sc_signal<int> 	   r_xram_rsp_fsm;			// FSM state
+      sc_signal<size_t>	   r_xram_rsp_trt_index;		// TRT entry index
+      TransactionTabEntry    r_xram_rsp_trt_buf;			// TRT entry local buffer
+      sc_signal<bool>	   r_xram_rsp_victim_inval;		// victim line invalidate 
+      sc_signal<bool>	   r_xram_rsp_victim_dirty;		// victim line dirty bit
+      sc_signal<size_t> 	   r_xram_rsp_victim_way;		// victim line way
+      sc_signal<size_t> 	   r_xram_rsp_victim_set;		// victim line set
+      sc_signal<data_t> 	   r_xram_rsp_victim_nline;		// victim line index
+      sc_signal<copy_t>      r_xram_rsp_victim_copies;		// victim line copies
+      sc_signal<data_t>	  *r_xram_rsp_victim_data;		// victim line data
+      sc_signal<size_t>	   r_xram_rsp_upt_index;		// UPT entry index
+
+      // Buffer between XRAM_RSP fsm and TGT_RSP fsm  (response to L1 cache)
+      sc_signal<bool>	   r_xram_rsp_to_tgt_rsp_req;		// Valid request
+      sc_signal<size_t>      r_xram_rsp_to_tgt_rsp_srcid;		// Transaction srcid
+      sc_signal<size_t>      r_xram_rsp_to_tgt_rsp_trdid;		// Transaction trdid
+      sc_signal<size_t>      r_xram_rsp_to_tgt_rsp_pktid;		// Transaction pktid
+      sc_signal<data_t>     *r_xram_rsp_to_tgt_rsp_data;		// data (one cache line)
+      sc_signal<bool>       *r_xram_rsp_to_tgt_rsp_val;		// valid bit (for single word)
+
+      // Buffer between XRAM_RSP fsm and INIT_CMD fsm (Inval L1 Caches) 
+      sc_signal<bool>	   r_xram_rsp_to_init_cmd_req;		// Valid request
+      sc_signal<data_t>      r_xram_rsp_to_init_cmd_nline;	// cache line index;
+      sc_signal<size_t>	   r_xram_rsp_to_init_cmd_trdid;	// index of UPT entry
+      sc_signal<copy_t>      r_xram_rsp_to_init_cmd_copies;	// bit_vector of copies
+
+      // Buffer between XRAM_RSP fsm and XRAM_CMD fsm (XRAM write)
+      sc_signal<bool>	   r_xram_rsp_to_xram_cmd_req;		// Valid request
+      sc_signal<data_t>	   r_xram_rsp_to_xram_cmd_nline;	// cache line index
+      sc_signal<data_t>	  *r_xram_rsp_to_xram_cmd_data;		// cache line data
+      sc_signal<size_t>	   r_xram_rsp_to_xram_cmd_trdid;	// index in transaction table
+
+      ////////////////////////////////////////////////////
+      // Registers controlled by the XRAM_CMD fsm
+      ////////////////////////////////////////////////////
+
+      sc_signal<int> 		r_xram_cmd_fsm;
+      sc_signal<size_t>		r_xram_cmd_cpt;
+
+      ////////////////////////////////////////////////////
+      // Registers controlled by TGT_RSP fsm
+      ////////////////////////////////////////////////////
+
+      sc_signal<int> 		r_tgt_rsp_fsm;
+      sc_signal<size_t> 		r_tgt_rsp_cpt;
+
+      ////////////////////////////////////////////////////
+      // Registers controlled by INIT_CMD fsm
+      ////////////////////////////////////////////////////
+
+      sc_signal<int> 		r_init_cmd_fsm;
+      sc_signal<size_t>		r_init_cmd_cpt;
+      sc_signal<size_t>		r_init_cmd_target;
+
+      ////////////////////////////////////////////////////
+      // Registers controlled by ALLOC_DIR fsm
+      ////////////////////////////////////////////////////
+
+      sc_signal<int> 		r_alloc_dir_fsm;
+    
+      ////////////////////////////////////////////////////
+      // Registers controlled by ALLOC_TRT fsm
+      ////////////////////////////////////////////////////
+
+      sc_signal<int> 		r_alloc_trt_fsm;
+
+      ////////////////////////////////////////////////////
+      // Registers controlled by ALLOC_UPT fsm
+      ////////////////////////////////////////////////////
+
+      sc_signal<int> 		r_alloc_upt_fsm;
+
+    }; // end class VciMemCache
+ 
+  }}
+
+#endif
Index: branches/v4/modules/vci_mem_cache/caba/source/include/xram_transaction.h
===================================================================
--- branches/v4/modules/vci_mem_cache/caba/source/include/xram_transaction.h	(revision 371)
+++ branches/v4/modules/vci_mem_cache/caba/source/include/xram_transaction.h	(revision 371)
@@ -0,0 +1,392 @@
+#ifndef XRAM_TRANSACTION_H_
+#define XRAM_TRANSACTION_H_
+ 
+#include <inttypes.h>
+#include <systemc>
+#include <cassert>
+#include "arithmetics.h"
+
+#define DEBUG_XRAM_TRANSACTION 0
+
+////////////////////////////////////////////////////////////////////////
+//                  A transaction tab entry         
+////////////////////////////////////////////////////////////////////////
+
+class TransactionTabEntry {
+  typedef uint32_t size_t;
+  typedef uint32_t data_t;
+  typedef uint32_t be_t;
+
+ public:
+  bool 	valid;     		// entry valid 
+  bool 	xram_read; 		// read request to XRAM
+  data_t  	nline;    		// index (zy) of the requested line
+  size_t 	srcid;     		// processor requesting the transaction
+  size_t 	trdid;     		// processor requesting the transaction
+  size_t 	pktid;     		// processor requesting the transaction
+  bool 	proc_read;	 	// read request from processor
+  bool 	single_word;   		// single word in case of processor read 
+  size_t 	word_index;    		// word index in case of single word read
+  std::vector<data_t> wdata;        	// write buffer (one cache line)
+  std::vector<be_t> wdata_be;    	// be for each data in the write buffer
+
+  /////////////////////////////////////////////////////////////////////
+  // The init() function initializes the entry 
+  /////////////////////////////////////////////////////////////////////
+  void init()
+  {
+    valid		= false;
+  }
+
+  /////////////////////////////////////////////////////////////////////
+  // The alloc() function initializes the vectors of an entry
+  // Its arguments are :
+  // - n_words : number of words per line in the cache
+  /////////////////////////////////////////////////////////////////////
+  void alloc(size_t n_words)
+  {
+    wdata_be.reserve( (int)n_words );
+    wdata.reserve( (int)n_words );
+    for(size_t i=0; i<n_words; i++){
+      wdata_be.push_back(false);
+      wdata.push_back(0);
+    }
+  }
+
+  ////////////////////////////////////////////////////////////////////
+  // The copy() function copies an existing entry
+  // Its arguments are :
+  // - source : the transaction tab entry to copy
+  ////////////////////////////////////////////////////////////////////
+  void copy(const TransactionTabEntry &source)
+  {
+    valid		= source.valid;
+    xram_read 	= source.xram_read;
+    nline		= source.nline;
+    srcid		= source.srcid;
+    trdid		= source.trdid;
+    pktid		= source.pktid;
+    proc_read 	= source.proc_read;
+    single_word 	= source.single_word;
+    word_index	= source.word_index;
+    wdata_be.assign(source.wdata_be.begin(),source.wdata_be.end());
+    wdata.assign(source.wdata.begin(),source.wdata.end());	
+  }
+
+  ////////////////////////////////////////////////////////////////////
+  // The print() function prints the entry 
+  ////////////////////////////////////////////////////////////////////
+  void print(){
+    std::cout << "valid       = " << valid        << std::endl;
+    std::cout << "xram_read   = " << xram_read    << std::endl;
+    std::cout << "nline       = " << nline        << std::endl;
+    std::cout << "srcid       = " << srcid        << std::endl;
+    std::cout << "trdid       = " << trdid        << std::endl;
+    std::cout << "pktid       = " << pktid        << std::endl;
+    std::cout << "proc_read   = " << proc_read    << std::endl;
+    std::cout << "single_word = " << single_word  << std::endl;
+    std::cout << "word_index  = " << word_index   << std::endl; 
+    for(size_t i=0; i<wdata_be.size() ; i++){
+      std::cout << "wdata_be [" << i <<"] = " << wdata_be[i] << std::endl;
+    }
+    for(size_t i=0; i<wdata.size() ; i++){
+      std::cout << "wdata [" << i <<"] = " << wdata[i] << std::endl;
+    }
+    std::cout << std::endl;
+  }
+
+  /////////////////////////////////////////////////////////////////////
+  // 		Constructors
+  /////////////////////////////////////////////////////////////////////
+
+  TransactionTabEntry()
+    {
+      wdata_be.clear();
+      wdata.clear();
+      valid=false;
+    }
+
+  TransactionTabEntry(const TransactionTabEntry &source){
+    valid		= source.valid;
+    xram_read	= source.xram_read;
+    nline		= source.nline;
+    srcid		= source.srcid;
+    trdid		= source.trdid;
+    pktid		= source.pktid;
+    proc_read	= source.proc_read;
+    single_word 	= source.single_word;
+    word_index	= source.word_index;
+    wdata_be.assign(source.wdata_be.begin(),source.wdata_be.end());
+    wdata.assign(source.wdata.begin(),source.wdata.end());	
+  }
+
+}; // end class TransactionTabEntry
+
+////////////////////////////////////////////////////////////////////////
+//                  The transaction tab                              
+////////////////////////////////////////////////////////////////////////
+class TransactionTab{
+  typedef uint32_t size_t;
+  typedef uint32_t data_t;
+  typedef uint32_t be_t;
+
+ private:
+  size_t size_tab;                // The size of the tab
+
+  data_t be_to_mask(be_t be)
+  {
+    data_t ret = 0;
+    if ( be&0x1 ) {
+      ret = ret | 0x000000FF;
+    }
+    if ( be&0x2 ) {
+      ret = ret | 0x0000FF00;
+    }
+    if ( be&0x4 ) {
+      ret = ret | 0x00FF0000;
+    }
+    if ( be&0x8 ) {
+      ret = ret | 0xFF000000;
+    }
+    return ret;
+  }
+
+ public:
+  TransactionTabEntry *tab;       // The transaction tab
+
+  ////////////////////////////////////////////////////////////////////
+  //		Constructors
+  ////////////////////////////////////////////////////////////////////
+  TransactionTab()
+    {
+      size_tab=0;
+      tab=NULL;
+    }
+
+  TransactionTab(size_t n_entries, size_t n_words)
+    {
+      size_tab = n_entries;
+      tab = new TransactionTabEntry[size_tab];
+      for ( size_t i=0; i<size_tab; i++) {
+	tab[i].alloc(n_words);
+      }
+    }
+
+  ~TransactionTab()
+    {
+      delete [] tab;
+    }
+
+  /////////////////////////////////////////////////////////////////////
+  // The size() function returns the size of the tab
+  /////////////////////////////////////////////////////////////////////
+  size_t size()
+  {
+    return size_tab;
+  }
+
+  /////////////////////////////////////////////////////////////////////
+  // The init() function initializes the transaction tab entries
+  /////////////////////////////////////////////////////////////////////
+  void init()
+  {
+    for ( size_t i=0; i<size_tab; i++) {
+      tab[i].init();
+    }
+  }
+
+  /////////////////////////////////////////////////////////////////////
+  // The print() function prints a transaction tab entry
+  // Arguments :
+  // - index : the index of the entry to print
+  /////////////////////////////////////////////////////////////////////
+  void print(const size_t index)
+  {
+    assert( (index < size_tab) 
+	    && "Invalid Transaction Tab Entry");
+    tab[index].print();
+    return;
+  }
+
+  /////////////////////////////////////////////////////////////////////
+  // The read() function returns a transaction tab entry.
+  // Arguments :
+  // - index : the index of the entry to read
+  /////////////////////////////////////////////////////////////////////
+  TransactionTabEntry read(const size_t index)
+  {
+    assert( (index < size_tab) 
+	    && "Invalid Transaction Tab Entry");
+    return tab[index];
+  }
+
+  /////////////////////////////////////////////////////////////////////
+  // The full() function returns the state of the transaction tab
+  // Arguments :
+  // - index : (return argument) the index of an empty entry 
+  // The function returns true if the transaction tab is full
+  /////////////////////////////////////////////////////////////////////
+  bool full(size_t &index)
+  {
+    for(size_t i=0; i<size_tab; i++){
+      if(!tab[i].valid){
+	index=i;
+	return false;	
+      }
+    }
+    return true;
+  }
+
+  /////////////////////////////////////////////////////////////////////
+  // The hit_read() function checks if an XRAM read transaction exists 
+  // for a given cache line.
+  // Arguments :
+  // - index : (return argument) the index of the hit entry, if there is 
+  // - nline : the index (zy) of the requested line
+  // The function returns true if a read request has already been sent
+  //////////////////////////////////////////////////////////////////////
+  bool hit_read(const data_t nline,size_t &index)
+  {
+    for(size_t i=0; i<size_tab; i++){
+      if(tab[i].valid && (nline==tab[i].nline) && tab[i].xram_read) {
+	index=i;
+	return true;	
+      }
+    }
+    return false;
+  }
+
+  ///////////////////////////////////////////////////////////////////////
+  // The hit_write() function looks if an XRAM write transaction exists 
+  // for a given line.
+  // Arguments :
+  // - nline : the index (zy) of the requested line
+  // The function returns true if a write request has already been sent
+  ///////////////////////////////////////////////////////////////////////
+  bool hit_write(const data_t nline)
+  {
+    for(size_t i=0; i<size_tab; i++){
+      if(tab[i].valid && (nline==tab[i].nline) && !(tab[i].xram_read)) {
+	return true;	
+      }
+    }
+    return false;
+  }
+
+  /////////////////////////////////////////////////////////////////////
+  // The write_data_mask() function writes a vector of data (a line).
+  // The data is written only if the corresponding bits are set
+  // in the be vector. 
+  // Arguments :
+  // - index : the index of the request in the transaction tab
+  // - be   : vector of be 
+  // - data : vector of data
+  /////////////////////////////////////////////////////////////////////
+  void write_data_mask(const size_t index, 
+		       const std::vector<be_t> &be, 
+		       const std::vector<data_t> &data) 
+  {
+    assert( (index < size_tab) 
+	    && "Invalid Transaction Tab Entry");
+    assert(be.size()==tab[index].wdata_be.size() 
+	   && "Bad data mask in write_data_mask in TransactionTab");
+    assert(data.size()==tab[index].wdata.size() 
+	   && "Bad data in write_data_mask in TransactionTab");
+
+    for(size_t i=0; i<tab[index].wdata_be.size() ; i++) {
+      tab[index].wdata_be[i] = tab[index].wdata_be[i] | be[i];
+      data_t mask = be_to_mask(be[i]);
+      tab[index].wdata[i] = (tab[index].wdata[i] & ~mask) | (data[i] & mask);
+    }
+  }
+
+  /////////////////////////////////////////////////////////////////////
+  // The set() function registers a transaction (read or write)
+  // to the XRAM in the transaction tab.
+  // Arguments :
+  // - index : index in the transaction tab
+  // - xram_read : transaction type (read or write a cache line)
+  // - nline : the index (zy) of the cache line
+  // - srcid : srcid of the initiator that caused the transaction
+  // - trdid : trdid of the initiator that caused the transaction
+  // - pktid : pktid of the initiator that caused the transaction
+  // - proc_read : does the initiator want a copy
+  // - single_word : single word read (in case of processor read)
+  // - word_index : index in the line (in case of single word read)
+  // - data : the data to write (in case of write)
+  // - data_be : the mask of the data to write (in case of write)
+  /////////////////////////////////////////////////////////////////////
+  void set(const size_t index,
+	   const bool xram_read,
+	   const data_t nline,
+	   const size_t srcid,
+	   const size_t trdid,
+	   const size_t pktid,
+	   const bool proc_read,
+	   const bool single_word,
+	   const size_t word_index,
+	   const std::vector<be_t> &data_be,
+	   const std::vector<data_t> &data) 
+  {
+    assert( (index < size_tab) 
+	    && "The selected entry is out of range in set() Transaction Tab");
+    assert(data_be.size()==tab[index].wdata_be.size() 
+	   && "Bad data_be argument in set() TransactionTab");
+    assert(data.size()==tab[index].wdata.size() 
+	   && "Bad data argument in set() TransactionTab");
+
+    tab[index].valid	= true;
+    tab[index].xram_read	= xram_read;
+    tab[index].nline	= nline;
+    tab[index].srcid	= srcid;
+    tab[index].trdid	= trdid;
+    tab[index].pktid	= pktid;
+    tab[index].proc_read	= proc_read;
+    tab[index].single_word	= single_word;
+    tab[index].word_index	= word_index;
+    for(size_t i=0; i<tab[index].wdata.size(); i++) {
+      tab[index].wdata_be[i] = data_be[i];
+      tab[index].wdata[i]    = data[i];
+    }
+  }
+
+  /////////////////////////////////////////////////////////////////////
+  // The write_rsp() function writes a word of the response to an 
+  // XRAM read transaction.
+  // The data is only written when the corresponding BE field is Ox0.
+  // Arguments :
+  // - index : the index of the transaction in the transaction tab
+  // - word_index : the index of the data in the line
+  // - data : the data to write
+  /////////////////////////////////////////////////////////////////////
+  void write_rsp(const size_t index,
+		 const size_t word,
+		 const data_t data)
+  {
+    assert( (index < size_tab) 
+	    && "Selected entry  out of range in write_rsp() Transaction Tab");
+    assert( (word <= tab[index].wdata_be.size()) 
+	    && "Bad word_index in write_rsp() in TransactionTab");
+    assert( tab[index].valid 
+	    && "Transaction Tab Entry invalid in write_rsp()");
+    assert( tab[index].xram_read 
+	    && "Selected entry is not an XRAM read transaction in write_rsp()");
+
+    data_t mask = be_to_mask(tab[index].wdata_be[word]);
+    tab[index].wdata[word] = (tab[index].wdata[word] & mask) | (data & ~mask);
+  }
+
+  /////////////////////////////////////////////////////////////////////
+  // The erase() function erases an entry in the transaction tab.
+  // Arguments :
+  // - index : the index of the request in the transaction tab
+  /////////////////////////////////////////////////////////////////////
+  void erase(const size_t index)
+  {
+    assert( (index < size_tab) 
+	    && "The selected entry is out of range in erase() Transaction Tab");
+    tab[index].valid	= false;
+  }
+}; // end class TransactionTab
+
+#endif
Index: branches/v4/modules/vci_mem_cache/caba/source/src/vci_mem_cache.cpp
===================================================================
--- branches/v4/modules/vci_mem_cache/caba/source/src/vci_mem_cache.cpp	(revision 371)
+++ branches/v4/modules/vci_mem_cache/caba/source/src/vci_mem_cache.cpp	(revision 371)
@@ -0,0 +1,2790 @@
+/* -*- c++ -*-
+ * File 	: vci_mem_cache.cpp
+ * Date 	: 30/10/2008
+ * Copyright 	: UPMC / LIP6
+ * Authors 	: Alain Greiner / Eric Guthmuller
+ *
+ * SOCLIB_LGPL_HEADER_BEGIN
+ *
+ * This file is part of SoCLib, GNU LGPLv2.1.
+ *
+ * SoCLib is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU Lesser General Public License as published
+ * by the Free Software Foundation; version 2.1 of the License.
+ *
+ * SoCLib is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with SoCLib; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301 USA
+ *
+ * SOCLIB_LGPL_HEADER_END
+ *
+ * Maintainers: alain eric.guthmuller@polytechnique.edu
+ */
+
+#include "../include/vci_mem_cache.h"
+
+#define DEBUG_VCI_MEM_CACHE 0
+
+namespace soclib { namespace caba {
+
+#ifdef DEBUG_VCI_MEM_CACHE 
+  const char *tgt_cmd_fsm_str[] = {
+    "TGT_CMD_IDLE",
+    "TGT_CMD_READ",
+    "TGT_CMD_READ_EOP",
+    "TGT_CMD_WRITE",
+    "TGT_CMD_ATOMIC",
+    "TGT_CMD_CLEANUP",
+  };
+  const char *tgt_rsp_fsm_str[] = {
+    "TGT_RSP_READ_IDLE",
+    "TGT_RSP_WRITE_IDLE",
+    "TGT_RSP_LLSC_IDLE",
+    "TGT_RSP_CLEANUP_IDLE",
+    "TGT_RSP_XRAM_IDLE",
+    "TGT_RSP_INIT_IDLE",
+    "TGT_RSP_READ_TEST",
+    "TGT_RSP_READ_WORD",
+    "TGT_RSP_READ_LINE",
+    "TGT_RSP_WRITE",
+    "TGT_RSP_LLSC",
+    "TGT_RSP_CLEANUP",
+    "TGT_RSP_XRAM_TEST",
+    "TGT_RSP_XRAM_WORD",
+    "TGT_RSP_XRAM_LINE",
+    "TGT_RSP_INIT",
+  };
+  const char *init_cmd_fsm_str[] = {
+    "INIT_CMD_INVAL_IDLE",
+    "INIT_CMD_INVAL_SEL",
+    "INIT_CMD_INVAL_NLINE",
+    "INIT_CMD_UPDT_IDLE",
+    "INIT_CMD_UPDT_SEL",
+    "INIT_CMD_UPDT_NLINE",
+    "INIT_CMD_UPDT_INDEX",
+    "INIT_CMD_UPDT_DATA",
+  };
+  const char *init_rsp_fsm_str[] = {
+    "INIT_RSP_IDLE",
+    "INIT_RSP_UPT_LOCK",
+    "INIT_RSP_UPT_CLEAR",
+    "INIT_RSP_END",
+  };
+  const char *read_fsm_str[] = {
+    "READ_IDLE",
+    "READ_DIR_LOCK",
+    "READ_DIR_HIT",
+    "READ_RSP",
+    "READ_TRT_LOCK",
+    "READ_TRT_SET",
+    "READ_XRAM_REQ",
+  };
+  const char *write_fsm_str[] = {
+    "WRITE_IDLE",
+    "WRITE_NEXT"
+      "WRITE_DIR_LOCK",
+    "WRITE_DIR_HIT_READ",
+    "WRITE_DIR_HIT",
+    "WRITE_UPT_LOCK",
+    "WRITE_WAIT_UPT",
+    "WRITE_UPDATE",
+    "WRITE_RSP",
+    "WRITE_TRT_LOCK",
+    "WRITE_TRT_DATA",
+    "WRITE_TRT_SET",
+    "WRITE_WAIT_TRT",
+    "WRITE_XRAM_REQ",
+  };
+  const char *ixr_rsp_fsm_str[] = {
+    "IXR_RSP_IDLE",
+    "IXR_RSP_ACK",
+    "IXR_RSP_TRT_ERASE",
+    "IXR_RSP_TRT_READ",
+  };
+  const char *xram_rsp_fsm_str[] = {
+    "XRAM_RSP_IDLE",
+    "XRAM_RSP_TRT_COPY",
+    "XRAM_RSP_TRT_DIRTY",
+    "XRAM_RSP_DIR_LOCK",
+    "XRAM_RSP_DIR_UPDT",
+    "XRAM_RSP_DIR_RSP",
+    "XRAM_RSP_UPT_LOCK",
+    "XRAM_RSP_WAIT",
+    "XRAM_RSP_INVAL",
+    "XRAM_RSP_WRITE_DIRTY",
+  };
+  const char *xram_cmd_fsm_str[] = {
+    "XRAM_CMD_READ_IDLE",
+    "XRAM_CMD_WRITE_IDLE",
+    "XRAM_CMD_LLSC_IDLE",
+    "XRAM_CMD_XRAM_IDLE",
+    "XRAM_CMD_READ_NLINE",
+    "XRAM_CMD_WRITE_NLINE",
+    "XRAM_CMD_LLSC_NLINE",
+    "XRAM_CMD_XRAM_DATA",
+  };
+  const char *llsc_fsm_str[] = {
+    "LLSC_IDLE",
+    "LL_DIR_LOCK",
+    "LL_DIR_HIT",
+    "LL_RSP",
+    "SC_DIR_LOCK",
+    "SC_DIR_HIT",
+    "SC_RSP_FALSE",
+    "SC_RSP_TRUE",
+    "LLSC_TRT_LOCK",
+    "LLSC_TRT_SET",
+    "LLSC_XRAM_REQ",
+  };
+  const char *cleanup_fsm_str[] = {
+    "CLEANUP_IDLE",
+    "CLEANUP_DIR_LOCK",
+    "CLEANUP_DIR_WRITE",
+    "CLEANUP_RSP",
+  };
+  const char *alloc_dir_fsm_str[] = {
+    "ALLOC_DIR_READ",
+    "ALLOC_DIR_WRITE",
+    "ALLOC_DIR_LLSC",
+    "ALLOC_DIR_CLEANUP",
+    "ALLOC_DIR_XRAM_RSP",
+  };
+  const char *alloc_trt_fsm_str[] = {
+    "ALLOC_TRT_READ",
+    "ALLOC_TRT_WRITE",
+    "ALLOC_TRT_LLSC",
+    "ALLOC_TRT_XRAM_RSP",
+    "ALLOC_TRT_IXR_RSP",
+  };
+  const char *alloc_upt_fsm_str[] = {
+    "ALLOC_UPT_WRITE",
+    "ALLOC_UPT_XRAM_RSP",
+    "ALLOC_UPT_INIT_RSP",
+  };
+#endif
+
+#define tmpl(x) template<typename vci_param> x VciMemCache<vci_param>
+
+  using soclib::common::uint32_log2;
+
+  ////////////////////////////////
+  // 	Constructor 
+  ////////////////////////////////
+
+  tmpl(/**/)::VciMemCache( 
+      sc_module_name name,
+      const soclib::common::MappingTable &mtp,
+      const soclib::common::MappingTable &mtc,
+      const soclib::common::MappingTable &mtx,
+      const soclib::common::IntTab &vci_ixr_index,
+      const soclib::common::IntTab &vci_ini_index,
+      const soclib::common::IntTab &vci_tgt_index,
+      size_t nways,
+      size_t nsets,
+      size_t nwords)
+
+    : soclib::caba::BaseModule(name),
+
+    p_clk("clk"),
+    p_resetn("resetn"),
+    p_vci_tgt("vci_tgt"),
+    p_vci_ini("vci_ini"),
+
+    m_initiators( 32 ),
+    m_ways( nways ),
+    m_sets( nsets ),
+    m_words( nwords ),
+    m_srcid_ixr( mtx.indexForId(vci_ixr_index) ),
+    m_srcid_ini( mtc.indexForId(vci_ini_index) ),
+    //m_mem_segment("bidon",0,0,soclib::common::IntTab(),false),
+    m_seglist(mtp.getSegmentList(vci_tgt_index)),
+    m_reg_segment("bidon",0,0,soclib::common::IntTab(),false),
+    m_coherence_table( mtc.getCoherenceTable() ),
+    m_atomic_tab( m_initiators ),
+    m_transaction_tab( TRANSACTION_TAB_LINES, nwords ),
+    m_update_tab( UPDATE_TAB_LINES ),
+    m_cache_directory( nways, nsets, nwords, vci_param::N ),
+    nseg(0),	
+#define L2 soclib::common::uint32_log2
+    m_x( L2(m_words), 2),
+    m_y( L2(m_sets), L2(m_words) + 2),
+    m_z( vci_param::N - L2(m_sets) - L2(m_words) - 2, L2(m_sets) + L2(m_words) + 2),
+    m_nline( vci_param::N - L2(m_words) - 2, L2(m_words) + 2),
+#undef L2
+
+    //  FIFOs 
+    m_cmd_read_addr_fifo("m_cmd_read_addr_fifo", 4),
+    m_cmd_read_word_fifo("m_cmd_read_word_fifo", 4),
+    m_cmd_read_srcid_fifo("m_cmd_read_srcid_fifo", 4),
+    m_cmd_read_trdid_fifo("m_cmd_read_trdid_fifo", 4),
+    m_cmd_read_pktid_fifo("m_cmd_read_pktid_fifo", 4),
+
+    m_cmd_write_addr_fifo("m_cmd_write_addr_fifo",8),
+    m_cmd_write_eop_fifo("m_cmd_write_eop_fifo",8),
+    m_cmd_write_srcid_fifo("m_cmd_write_srcid_fifo",8),
+    m_cmd_write_trdid_fifo("m_cmd_write_trdid_fifo",8),
+    m_cmd_write_pktid_fifo("m_cmd_write_pktid_fifo",8),
+    m_cmd_write_data_fifo("m_cmd_write_data_fifo",8),
+    m_cmd_write_be_fifo("m_cmd_write_be_fifo",8),
+
+    m_cmd_llsc_addr_fifo("m_cmd_llsc_addr_fifo",4),
+    m_cmd_llsc_sc_fifo("m_cmd_llsc_sc_fifo",4),
+    m_cmd_llsc_srcid_fifo("m_cmd_llsc_srcid_fifo",4),
+    m_cmd_llsc_trdid_fifo("m_cmd_llsc_trdid_fifo",4),
+    m_cmd_llsc_pktid_fifo("m_cmd_llsc_pktid_fifo",4),
+    m_cmd_llsc_wdata_fifo("m_cmd_llsc_wdata_fifo",4),
+
+    m_cmd_cleanup_srcid_fifo("m_cmd_cleanup_srcid_fifo",4),
+    m_cmd_cleanup_trdid_fifo("m_cmd_cleanup_trdid_fifo",4),
+    m_cmd_cleanup_pktid_fifo("m_cmd_cleanup_pktid_fifo",4),
+    m_cmd_cleanup_nline_fifo("m_cmd_cleanup_nline_fifo",4),
+
+    r_tgt_cmd_fsm("r_tgt_cmd_fsm"),
+    r_read_fsm("r_read_fsm"),
+    r_write_fsm("r_write_fsm"),
+    r_init_rsp_fsm("r_init_rsp_fsm"),
+    r_cleanup_fsm("r_cleanup_fsm"),
+    r_llsc_fsm("r_llsc_fsm"),
+    r_ixr_rsp_fsm("r_ixr_rsp_fsm"),
+    r_xram_rsp_fsm("r_xram_rsp_fsm"),
+    r_xram_cmd_fsm("r_xram_cmd_fsm"),
+    r_tgt_rsp_fsm("r_tgt_rsp_fsm"),
+    r_init_cmd_fsm("r_init_cmd_fsm"),
+    r_alloc_dir_fsm("r_alloc_dir_fsm"),
+    r_alloc_trt_fsm("r_alloc_trt_fsm"),
+    r_alloc_upt_fsm("r_alloc_upt_fsm")
+    {
+      assert(IS_POW_OF_2(nsets));
+      assert(IS_POW_OF_2(nwords));
+      assert(IS_POW_OF_2(nways));
+      assert(nsets);
+      assert(nwords);
+      assert(nways);
+      assert(nsets <= 1024);
+      assert(nwords <= 32);
+      assert(nways <= 32);
+
+      // Get the segments associated to the MemCache 
+      //std::list<soclib::common::Segment> segList(mtp.getSegmentList(vci_tgt_index));
+      std::list<soclib::common::Segment>::iterator seg;
+      /*
+         for(seg = segList.begin(); seg != segList.end() ; seg++) {
+         if( seg->size() > 8 ) m_mem_segment = *seg; 
+         else                  m_reg_segment = *seg;
+         nseg++;
+         }
+         */
+
+      for(seg = m_seglist.begin(); seg != m_seglist.end() ; seg++) {
+        if( seg->size() > 8 ) nseg++;
+      }
+      //assert( (nseg == 2) && (m_reg_segment.size() == 8) );
+
+      m_seg = new soclib::common::Segment*[nseg];
+      size_t i = 0;
+      for ( seg = m_seglist.begin() ; seg != m_seglist.end() ; seg++ ) { 
+        if ( seg->size() > 8 ) 
+        {
+          m_seg[i] = &(*seg);
+          i++;
+        }
+        else
+        {
+          m_reg_segment = *seg;
+        }		
+      }
+
+      assert( (m_reg_segment.size() == 8) );
+
+      // Memory cache allocation & initialisation
+      m_cache_data = new data_t**[nways];
+      for ( size_t i=0 ; i<nways ; ++i ) {
+        m_cache_data[i] = new data_t*[nsets];
+      }
+      for ( size_t i=0; i<nways; ++i ) {
+        for ( size_t j=0; j<nsets; ++j ) {
+          m_cache_data[i][j] = new data_t[nwords];
+          for ( size_t k=0; k<nwords; k++){
+            m_cache_data[i][j][k]=0;
+          }	
+        }
+      }
+
+      // Allocation for IXR_RSP FSM
+      r_ixr_rsp_to_xram_rsp_rok	    	= new sc_signal<bool>[TRANSACTION_TAB_LINES];
+
+      // Allocation for XRAM_RSP FSM
+      r_xram_rsp_victim_data        	= new sc_signal<data_t>[nwords];
+      r_xram_rsp_to_tgt_rsp_data    	= new sc_signal<data_t>[nwords];
+      r_xram_rsp_to_tgt_rsp_val     	= new sc_signal<bool>[nwords];
+      r_xram_rsp_to_xram_cmd_data   	= new sc_signal<data_t>[nwords];
+
+      // Allocation for READ FSM
+      r_read_data 			= new sc_signal<data_t>[nwords];
+      r_read_to_tgt_rsp_data 		= new sc_signal<data_t>[nwords];
+      r_read_to_tgt_rsp_val 		= new sc_signal<bool>[nwords];
+
+      // Allocation for WRITE FSM
+      r_write_data 			= new sc_signal<data_t>[nwords];
+      r_write_be 			= new sc_signal<be_t>[nwords];
+      r_write_to_init_cmd_data 		= new sc_signal<data_t>[nwords];
+      r_write_to_init_cmd_we		= new sc_signal<bool>[nwords];
+
+      // Simulation
+
+      SC_METHOD(transition);
+      dont_initialize();
+      sensitive << p_clk.pos();
+
+      SC_METHOD(genMoore);
+      dont_initialize();
+      sensitive << p_clk.neg();
+
+    } // end constructor
+
+  /////////////////////////////////////////
+  // This function prints the statistics 
+  /////////////////////////////////////////
+
+  tmpl(void)::print_stats()
+  {
+    std::cout << "----------------------------------" << std::dec << std::endl;
+    std::cout << "MEM_CACHE " << m_srcid_ini << " / Time = " << m_cpt_cycles << std::endl
+      << "- READ RATE           = " << (float)m_cpt_read/m_cpt_cycles << std::endl
+      << "- READ MISS RATE      = " << (float)m_cpt_read_miss/m_cpt_read << std::endl
+      << "- WRITE RATE          = " << (float)m_cpt_write/m_cpt_cycles << std::endl
+      << "- WRITE MISS RATE     = " << (float)m_cpt_write_miss/m_cpt_write << std::endl
+      << "- WRITE BURST LENGTH  = " << (float)m_cpt_write_cells/m_cpt_write << std::endl
+      << "- UPDATE RATE         = " << (float)m_cpt_update/m_cpt_cycles << std::endl
+      << "- UPDATE ARITY        = " << (float)m_cpt_update_mult/m_cpt_update << std::endl
+      << "- INVAL RATE          = " << (float)m_cpt_inval/m_cpt_cycles << std::endl
+      << "- INVAL ARITY         = " << (float)m_cpt_inval_mult/m_cpt_inval << std::endl
+      << "- SAVE DIRTY RATE     = " << (float)m_cpt_write_dirty/m_cpt_cycles << std::endl
+      << "- CLEANUP RATE        = " << (float)m_cpt_cleanup/m_cpt_cycles << std::endl
+      << "- LL RATE             = " << (float)m_cpt_ll/m_cpt_cycles << std::endl
+      << "- SC RATE             = " << (float)m_cpt_sc/m_cpt_cycles << std::endl;
+  }
+
+  /////////////////////////////////
+  tmpl(/**/)::~VciMemCache()
+    /////////////////////////////////
+  {
+    for(size_t i=0; i<m_ways ; i++){
+      for(size_t j=0; j<m_sets ; j++){
+        delete [] m_cache_data[i][j];
+      }
+    }
+    for(size_t i=0; i<m_ways ; i++){
+      delete [] m_cache_data[i];
+    }
+    delete [] m_cache_data;
+    delete [] m_coherence_table;
+
+    delete [] r_ixr_rsp_to_xram_rsp_rok;
+
+    delete [] r_xram_rsp_victim_data;
+    delete [] r_xram_rsp_to_tgt_rsp_data;
+    delete [] r_xram_rsp_to_tgt_rsp_val;
+    delete [] r_xram_rsp_to_xram_cmd_data;
+
+    delete [] r_read_data;
+    delete [] r_read_to_tgt_rsp_data;
+    delete [] r_read_to_tgt_rsp_val;
+
+    delete [] r_write_data;
+    delete [] r_write_be;
+    delete [] r_write_to_init_cmd_data;
+  }
+
+  //////////////////////////////////
+  tmpl(void)::transition()
+    //////////////////////////////////
+  {
+    using soclib::common::uint32_log2;
+    //  RESET          
+    if ( ! p_resetn.read() ) {
+
+      //     Initializing FSMs
+      r_tgt_cmd_fsm 	= TGT_CMD_IDLE;
+      r_tgt_rsp_fsm 	= TGT_RSP_READ_IDLE;
+      r_init_cmd_fsm 	= INIT_CMD_INVAL_IDLE;
+      r_init_rsp_fsm 	= INIT_RSP_IDLE;
+      r_read_fsm 	= READ_IDLE;
+      r_write_fsm 	= WRITE_IDLE;
+      r_llsc_fsm 	= LLSC_IDLE;
+      r_cleanup_fsm 	= CLEANUP_IDLE;
+      r_alloc_dir_fsm = ALLOC_DIR_READ;
+      r_alloc_trt_fsm = ALLOC_TRT_READ;
+      r_alloc_upt_fsm = ALLOC_UPT_WRITE;
+      r_ixr_rsp_fsm 	= IXR_RSP_IDLE;
+      r_xram_rsp_fsm 	= XRAM_RSP_IDLE;
+      r_xram_cmd_fsm 	= XRAM_CMD_READ_IDLE;
+
+      //  Initializing Tables
+      m_cache_directory.init();
+      m_atomic_tab.init();	
+      m_transaction_tab.init();
+
+      // initializing FIFOs and communication Buffers
+
+      m_cmd_read_addr_fifo.init();
+      m_cmd_read_word_fifo.init();
+      m_cmd_read_srcid_fifo.init();
+      m_cmd_read_trdid_fifo.init();
+      m_cmd_read_pktid_fifo.init();
+
+      m_cmd_write_addr_fifo.init();
+      m_cmd_write_eop_fifo.init();
+      m_cmd_write_srcid_fifo.init();
+      m_cmd_write_trdid_fifo.init();
+      m_cmd_write_pktid_fifo.init();
+      m_cmd_write_data_fifo.init();
+
+      m_cmd_llsc_addr_fifo.init();
+      m_cmd_llsc_srcid_fifo.init();
+      m_cmd_llsc_trdid_fifo.init();
+      m_cmd_llsc_pktid_fifo.init();
+      m_cmd_llsc_wdata_fifo.init();
+      m_cmd_llsc_sc_fifo.init();
+
+      m_cmd_cleanup_srcid_fifo.init();
+      m_cmd_cleanup_trdid_fifo.init();
+      m_cmd_cleanup_pktid_fifo.init();
+      m_cmd_cleanup_nline_fifo.init();
+
+      r_read_to_tgt_rsp_req		= false;
+      r_read_to_xram_cmd_req		= false;
+
+      r_write_to_tgt_rsp_req		= false;
+      r_write_to_xram_cmd_req		= false;
+      r_write_to_init_cmd_req		= false;
+
+      r_init_rsp_to_tgt_rsp_req	= false;
+
+      r_cleanup_to_tgt_rsp_req	= false;
+
+      r_llsc_to_tgt_rsp_req		= false;
+      r_llsc_to_xram_cmd_req		= false;
+
+      for(size_t i=0; i<TRANSACTION_TAB_LINES ; i++){
+        r_ixr_rsp_to_xram_rsp_rok[i]= false;
+      }
+
+      r_xram_rsp_to_tgt_rsp_req	= false;
+      r_xram_rsp_to_init_cmd_req	= false;
+      r_xram_rsp_to_xram_cmd_req	= false;
+      r_xram_rsp_trt_index		= 0;
+
+      r_xram_cmd_cpt = 0;
+
+      // Activity counters
+      m_cpt_cycles		= 0;
+      m_cpt_read		= 0;
+      m_cpt_read_miss		= 0;
+      m_cpt_write		= 0;
+      m_cpt_write_miss	= 0;
+      m_cpt_write_cells	= 0;
+      m_cpt_write_dirty	= 0;
+      m_cpt_update		= 0;
+      m_cpt_update_mult 	= 0;
+      m_cpt_inval 		= 0;
+      m_cpt_inval_mult 	= 0;
+      m_cpt_cleanup		= 0;
+      m_cpt_ll     		= 0;
+      m_cpt_sc     		= 0;
+
+      return;
+    }
+
+    bool    cmd_read_fifo_put = false;
+    bool    cmd_read_fifo_get = false;
+
+    bool    cmd_write_fifo_put = false;
+    bool    cmd_write_fifo_get = false;
+
+    bool    cmd_llsc_fifo_put = false;
+    bool    cmd_llsc_fifo_get = false;
+
+    bool    cmd_cleanup_fifo_put = false;
+    bool    cmd_cleanup_fifo_get = false;
+
+#if DEBUG_VCI_MEM_CACHE 
+    std::cout << "---------------------------------------------" << std::dec << std::endl;
+    std::cout << "MEM_CACHE " << m_srcid_ini << " ; Time = " << m_cpt_cycles << std::endl
+      << " - TGT_CMD FSM   = " << tgt_cmd_fsm_str[r_tgt_cmd_fsm] << std::endl
+      << " - TGT_RSP FSM   = " << tgt_rsp_fsm_str[r_tgt_rsp_fsm] << std::endl
+      << " - INIT_CMD FSM  = " << init_cmd_fsm_str[r_init_cmd_fsm] << std::endl
+      << " - INIT_RSP FSM  = " << init_rsp_fsm_str[r_init_rsp_fsm] << std::endl
+      << " - READ FSM      = " << read_fsm_str[r_read_fsm] << std::endl
+      << " - WRITE FSM     = " << write_fsm_str[r_write_fsm] << std::endl
+      << " - LLSC FSM      = " << llsc_fsm_str[r_llsc_fsm] << std::endl
+      << " - CLEANUP FSM   = " << cleanup_fsm_str[r_cleanup_fsm] << std::endl
+      << " - XRAM_CMD FSM  = " << xram_cmd_fsm_str[r_xram_cmd_fsm] << std::endl
+      << " - IXR_RSP FSM   = " << ixr_rsp_fsm_str[r_ixr_rsp_fsm] << std::endl
+      << " - XRAM_RSP FSM  = " << xram_rsp_fsm_str[r_xram_rsp_fsm] << std::endl
+      << " - ALLOC_DIR FSM = " << alloc_dir_fsm_str[r_alloc_dir_fsm] << std::endl
+      << " - ALLOC_TRT FSM = " << alloc_trt_fsm_str[r_alloc_trt_fsm] << std::endl
+      << " - ALLOC_UPT FSM = " << alloc_upt_fsm_str[r_alloc_upt_fsm] << std::endl;
+#endif
+
+
+    ////////////////////////////////////////////////////////////////////////////////////
+    //		TGT_CMD FSM
+    ////////////////////////////////////////////////////////////////////////////////////
+    // The TGT_CMD_FSM controls the incoming VCI command pakets from the processors
+    //
+    // There is 4 types of packets for the m_mem_segment :
+    // - READ    : a READ request has a length of 1 VCI cell. It can be a single word 
+    //             or an entire cache line, depending on the PLEN value.
+    // - WRITE   : a WRITE request has a maximum length of 16 cells, and can only
+    //             concern words in a same line.
+    // - LL      : The LL request has a length of 1 cell.
+    // - SC      : The SC request has a length of 1 cell. 
+    //             The WDATA field contains the data to write.
+    //
+    // There is one type of packet for the m_reg_segment :
+    // - CLEANUP : it is a one cell VCI packet. The VCI CMD field is WRITE, and the
+    //             WDATA field contains the cache line number (z & y).
+    ////////////////////////////////////////////////////////////////////////////////////
+
+    switch ( r_tgt_cmd_fsm.read() ) {
+
+      //////////////////
+      case TGT_CMD_IDLE:
+        {
+          if ( p_vci_tgt.cmdval ) {
+            assert( (p_vci_tgt.srcid.read() < m_initiators)
+                && "error in VCI_MEM_CACHE : The received SRCID is larger than 31");
+
+            bool reached = false;
+            for ( size_t index = 0 ; index < nseg && !reached ; index++) 
+            {
+              if ( m_seg[index]->contains(p_vci_tgt.address.read()) ) {
+                reached = true;
+                r_index = index;
+              }
+            }
+
+            if ( !reached ) 
+            { 
+              std::cout << "Out of segment access in VCI_MEM_CACHE" << std::endl;
+              std::cout << "Faulty address = " << p_vci_tgt.address.read() << std::endl;
+              std::cout << "Faulty initiator = " << p_vci_tgt.srcid.read() << std::endl;
+              exit(0);
+            } 
+            else if ( p_vci_tgt.cmd.read() == vci_param::CMD_READ ) 
+            {
+              r_tgt_cmd_fsm = TGT_CMD_READ;
+            } 
+            else if (( p_vci_tgt.cmd.read() == vci_param::CMD_WRITE ) && ( p_vci_tgt.trdid.read() == 0x0 ) )
+            {  
+              r_tgt_cmd_fsm = TGT_CMD_WRITE;
+            } 
+            else if ((p_vci_tgt.cmd.read() == vci_param::CMD_LOCKED_READ) || 
+                (p_vci_tgt.cmd.read() == vci_param::CMD_STORE_COND) ) 
+            {
+              r_tgt_cmd_fsm = TGT_CMD_ATOMIC;
+            } 
+            else if (( p_vci_tgt.cmd.read() == vci_param::CMD_WRITE ) && ( p_vci_tgt.trdid.read() == 0x1 ))
+            {  
+              r_tgt_cmd_fsm = TGT_CMD_CLEANUP;
+            } 
+          }
+          break;
+        }
+        //////////////////
+      case TGT_CMD_READ:
+        {
+          assert(((p_vci_tgt.plen.read() == 4) || (p_vci_tgt.plen.read() == m_words*4))
+              && "All read request to the MemCache must have PLEN = 4 or PLEN = 4*nwords"); 
+
+          if ( p_vci_tgt.cmdval && m_cmd_read_addr_fifo.wok() ) {
+            cmd_read_fifo_put = true;
+            if ( p_vci_tgt.eop )  r_tgt_cmd_fsm = TGT_CMD_IDLE;
+            else                  r_tgt_cmd_fsm = TGT_CMD_READ_EOP;		
+          } 
+          break;
+        }
+        //////////////////////
+      case TGT_CMD_READ_EOP:
+        {
+          if ( p_vci_tgt.cmdval && p_vci_tgt.eop ){
+            r_tgt_cmd_fsm = TGT_CMD_IDLE;
+          }
+          break;
+        }
+        ///////////////////
+      case TGT_CMD_WRITE:
+        {
+          if ( p_vci_tgt.cmdval && m_cmd_write_addr_fifo.wok() ) {
+            cmd_write_fifo_put = true;
+            if(  p_vci_tgt.eop )  r_tgt_cmd_fsm = TGT_CMD_IDLE;
+          }
+          break;
+        }
+        ////////////////////
+      case TGT_CMD_ATOMIC:
+        {
+          assert(p_vci_tgt.eop && "Memory Cache Error: LL or SC command with length > 1 ");
+
+          if ( p_vci_tgt.cmdval && m_cmd_llsc_addr_fifo.wok() ) {
+            cmd_llsc_fifo_put = true;
+            r_tgt_cmd_fsm = TGT_CMD_IDLE;
+          }
+          break;
+        }
+        /////////////////////
+      case TGT_CMD_CLEANUP:
+        {
+          assert(p_vci_tgt.eop && "Memory Cache Error: CLEANUP request with length > 1 ");
+
+          if ( p_vci_tgt.cmdval && m_cmd_cleanup_nline_fifo.wok() ) {
+            cmd_cleanup_fifo_put = true;
+            r_tgt_cmd_fsm = TGT_CMD_IDLE;
+          }
+          break;
+        }
+    } // end switch tgt_cmd_fsm
+
+    /////////////////////////////////////////////////////////////////////////
+    //		INIT_RSP FSM
+    /////////////////////////////////////////////////////////////////////////
+    // This FSM controls the response to the update or invalidate requests
+    // sent by the memory cache to the L1 caches :
+    //
+    // - update request initiated by the WRITE FSM.  
+    //   The FSM decrements the proper entry in the Update/Inval Table.
+    //   It sends a request to the TGT_RSP FSM to complete the pending 
+    //   write transaction (acknowledge response to the writer processor), 
+    //   and clear the UPT entry when all responses have been received.  
+    // - invalidate request initiated by the XRAM_RSP FSM.
+    //   The FSM decrements the proper entry in the Update/Inval_Table,
+    //   and clear the entry when all responses have been received.
+    //
+    // All those response packets are one word, compact
+    // packets complying with the VCI advanced format. 
+    // The index in the Table is defined in the RTRDID field, and
+    // the Transaction type is defined in the Update/Inval Table.
+    /////////////////////////////////////////////////////////////////////
+
+    switch ( r_init_rsp_fsm.read() ) {
+
+      ///////////////////
+      case INIT_RSP_IDLE:
+        {
+          if ( p_vci_ini.rspval ) {
+            assert ( ( p_vci_ini.rtrdid.read() < m_update_tab.size() )
+                && "UPT index too large in VCI response paquet received by memory cache" );
+            assert ( p_vci_ini.reop 
+                && "All response packets to update/invalidate requests must be one cell" );
+            r_init_rsp_upt_index = p_vci_ini.rtrdid.read(); 
+            r_init_rsp_fsm = INIT_RSP_UPT_LOCK;
+          }
+          break;
+        }
+        ///////////////////////
+      case INIT_RSP_UPT_LOCK:	// decrement the number of expected responses
+        {
+          if ( r_alloc_upt_fsm.read() == ALLOC_UPT_INIT_RSP ) { 
+            size_t count = 0;
+            bool valid  = m_update_tab.decrement(r_init_rsp_upt_index.read(), count); 
+            assert ( valid 
+                && "Invalid UPT entry in VCI response paquet received by memory cache" );
+            if ( count == 0 ) r_init_rsp_fsm = INIT_RSP_UPT_CLEAR;
+            else              r_init_rsp_fsm = INIT_RSP_IDLE;
+          }
+          break;
+        }
+        ////////////////////////
+      case INIT_RSP_UPT_CLEAR:	// clear the UPT entry
+        {
+          if ( r_alloc_upt_fsm.read() == ALLOC_UPT_INIT_RSP ) { 
+            r_init_rsp_srcid = m_update_tab.srcid(r_init_rsp_upt_index.read());
+            r_init_rsp_trdid = m_update_tab.trdid(r_init_rsp_upt_index.read());
+            r_init_rsp_pktid = m_update_tab.pktid(r_init_rsp_upt_index.read());
+            bool update = m_update_tab.is_update(r_init_rsp_upt_index.read());
+            if ( update ) r_init_rsp_fsm = INIT_RSP_END;
+            else          r_init_rsp_fsm = INIT_RSP_IDLE;
+            m_update_tab.clear(r_init_rsp_upt_index.read());
+          }
+          break;
+        }
+        //////////////////
+      case INIT_RSP_END:
+        {
+          if ( !r_init_rsp_to_tgt_rsp_req ) {
+            r_init_rsp_to_tgt_rsp_req = true;
+            r_init_rsp_to_tgt_rsp_srcid = r_init_rsp_srcid.read();
+            r_init_rsp_to_tgt_rsp_trdid = r_init_rsp_trdid.read();
+            r_init_rsp_to_tgt_rsp_pktid = r_init_rsp_pktid.read();
+            r_init_rsp_fsm = INIT_RSP_IDLE;
+          }
+          break;
+        }
+    } // end switch r_init_rsp_fsm
+
+    ////////////////////////////////////////////////////////////////////////////////////
+    //		READ FSM
+    ////////////////////////////////////////////////////////////////////////////////////
+    // The READ FSM controls the read requests sent by processors.
+    // It takes the lock protecting the cache directory to check the cache line status:
+    // - In case of HIT, the fsm copies the data (one line, or one single word)
+    //   in the r_read_to_tgt_rsp buffer. It waits if this buffer is not empty.
+    //   The requesting initiator is registered in the cache directory.
+    // - In case of MISS, the READ fsm takes the lock protecting the transaction tab.
+    //   If a read transaction to the XRAM for this line already exists,
+    //   or if the transaction tab is full, the fsm is stalled.
+    //   If a transaction entry is free, the READ fsm sends a request to the XRAM.
+    ////////////////////////////////////////////////////////////////////////////////////
+
+    switch ( r_read_fsm.read() ) {
+
+      ///////////////
+      case READ_IDLE:
+        {
+          if (m_cmd_read_addr_fifo.rok()) {
+            m_cpt_read++;
+            r_read_fsm = READ_DIR_LOCK;
+          }
+          break;
+        }
+        ///////////////////
+      case READ_DIR_LOCK:	// check directory for hit / miss
+        {
+          if( r_alloc_dir_fsm.read() == ALLOC_DIR_READ ) {
+            size_t way = 0;
+            DirectoryEntry entry = m_cache_directory.read(m_cmd_read_addr_fifo.read(), way);
+
+            r_read_dirty	= entry.dirty;
+            r_read_tag	= entry.tag;
+            r_read_lock	= entry.lock;
+            r_read_way	= way;
+            r_read_word	= m_cmd_read_word_fifo.read();
+            r_read_copies = entry.copies | (0x1 << m_cmd_read_srcid_fifo.read());
+
+            // In case of hit, the read acces must be registered in the copies bit-vector
+            // for both a cache line read & a single word read (TLB coherence)
+
+            if( entry.valid )  { 
+              r_read_fsm = READ_DIR_HIT;
+            } else {
+              r_read_fsm = READ_TRT_LOCK;
+              m_cpt_read_miss++;
+            }
+          }
+          break;
+        }
+        //////////////////
+      case READ_DIR_HIT:	// read hit : update the memory cache
+        {
+          if( r_alloc_dir_fsm.read() == ALLOC_DIR_READ ) {
+
+            // read data in the cache
+            size_t set = m_y[m_cmd_read_addr_fifo.read()];
+            size_t way = r_read_way.read();
+            for ( size_t i=0 ; i<m_words ; i++ ) {
+              r_read_data[i] = m_cache_data[way][set][i];
+            }
+
+            // update the cache directory (for the copies)
+            DirectoryEntry entry;
+            entry.valid	= true;
+            entry.dirty	= r_read_dirty.read();
+            entry.tag	= r_read_tag.read();
+            entry.lock	= r_read_lock.read();
+            entry.copies  = r_read_copies.read();
+            m_cache_directory.write(set, way, entry);
+            r_read_fsm    = READ_RSP;
+          }
+          break;
+        }
+        //////////////
+      case READ_RSP: 		//  request the TGT_RSP FSM to return data
+        {
+          if( !r_read_to_tgt_rsp_req ) {	
+            for ( size_t i=0 ; i<m_words ; i++ ) {
+              r_read_to_tgt_rsp_data[i] = r_read_data[i];
+              if ( r_read_word ) {	// single word
+                r_read_to_tgt_rsp_val[i] = (i == m_x[m_cmd_read_addr_fifo.read()]);
+              } else {			// cache line
+                r_read_to_tgt_rsp_val[i] = true;
+              }
+            }
+            cmd_read_fifo_get 		= true;
+            r_read_to_tgt_rsp_req		= true;
+            r_read_to_tgt_rsp_srcid	= m_cmd_read_srcid_fifo.read();
+            r_read_to_tgt_rsp_trdid	= m_cmd_read_trdid_fifo.read();
+            r_read_to_tgt_rsp_pktid	= m_cmd_read_pktid_fifo.read();
+            r_read_fsm 			= READ_IDLE;  
+          }
+          break;
+        }
+        ///////////////////
+      case READ_TRT_LOCK:	// read miss : check the Transaction Table
+        {
+          if ( r_alloc_trt_fsm.read() == ALLOC_TRT_READ ) {
+            size_t index = 0;
+            bool   hit = m_transaction_tab.hit_read(m_nline[m_cmd_read_addr_fifo.read()], index);
+            bool   wok = !m_transaction_tab.full(index);
+            if( hit || !wok ) {  // missing line already requested or no space
+              r_read_fsm = READ_IDLE;
+            } else {			   // missing line is requested to the XRAM
+              r_read_trt_index = index;
+              r_read_fsm       = READ_TRT_SET;
+            }
+          }
+          break;
+        }
+        //////////////////
+      case READ_TRT_SET:
+        {
+          if ( r_alloc_trt_fsm.read() == ALLOC_TRT_READ ) {
+            m_transaction_tab.set(r_read_trt_index.read(),
+                true,
+                m_nline[m_cmd_read_addr_fifo.read()],
+                m_cmd_read_srcid_fifo.read(),
+                m_cmd_read_trdid_fifo.read(),
+                m_cmd_read_pktid_fifo.read(),
+                true,
+                m_cmd_read_word_fifo.read(),
+                m_x[m_cmd_read_addr_fifo.read()],
+                std::vector<be_t>(m_words,0),
+                std::vector<data_t>(m_words,0));
+            r_read_fsm 	 = READ_XRAM_REQ;
+          }
+          break;
+        }
+        /////////////////////
+      case READ_XRAM_REQ:
+        {
+          if( !r_read_to_xram_cmd_req ) {
+            cmd_read_fifo_get		= true;
+            r_read_to_xram_cmd_req  	= true;
+            r_read_to_xram_cmd_nline 	= m_nline[m_cmd_read_addr_fifo.read()];
+            r_read_to_xram_cmd_trdid 	= r_read_trt_index.read();
+            r_read_fsm 			= READ_IDLE;
+          }
+          break;
+        }
+    } // end switch read_fsm
+
+    ///////////////////////////////////////////////////////////////////////////////////
+    //		WRITE FSM
+    ///////////////////////////////////////////////////////////////////////////////////
+    // The WRITE FSM handles the write bursts sent by the processors.
+    // All addresses in a burst must be in the same cache line.
+    // A complete write burst is consumed in the FIFO & copied to a local buffer.
+    // Then the FSM takes the lock protecting the cache directory, to check
+    // if the line is in the cache.
+    //
+    // - In case of HIT, the cache is updated.
+    //   If there is no other copy, an acknowledge response is immediately
+    //   returned to the writing processor.
+    //   if the data is cached by other processoris, the FSM takes the lock
+    //   protecting the Update Table (UPT) to register this update transaction.
+    //   If the UPT is full, it releases the lock  and waits. Then, it sends 
+    //   a multi-update request to all owners of the line (but the writer), 
+    //   through the INIT_CMD FSM. In case of multi-update transaction, the WRITE FSM 
+    //   does not respond to the writing processor, as this response will be sent by 
+    //   the INIT_RSP FSM when all update responses have been received.
+    //
+    // - In case of MISS, the WRITE FSM takes the lock protecting the transaction
+    //   table (TRT). If a read transaction to the XRAM for this line already exists, 
+    //   it writes in the TRT (write buffer). Otherwise, if a TRT entry is free, 
+    //   the WRITE FSM register a new transaction in TRT, and sends a read line request 
+    //   to the XRAM. If the TRT is full, it releases the lock, and waits.
+    //   Finally, the WRITE FSM returns an aknowledge response to the writing processor.
+    /////////////////////////////////////////////////////////////////////////////////////
+
+    switch ( r_write_fsm.read() ) {
+
+      ////////////////
+      case WRITE_IDLE:	// copy first word of a write burst in local buffer	
+        {
+          if ( m_cmd_write_addr_fifo.rok()) {
+            m_cpt_write++;
+            m_cpt_write_cells++;
+            // consume a word in the FIFO & write it in the local buffer 
+            cmd_write_fifo_get	= true;
+            size_t index 		= m_x[m_cmd_write_addr_fifo.read()];
+            r_write_address	= m_cmd_write_addr_fifo.read();
+            r_write_word_index	= index;
+            r_write_word_count	= 1;
+            r_write_data[index]	= m_cmd_write_data_fifo.read();
+            r_write_srcid		= m_cmd_write_srcid_fifo.read();
+            r_write_trdid		= m_cmd_write_trdid_fifo.read();
+            r_write_pktid		= m_cmd_write_pktid_fifo.read();
+
+            // the be field must be set for all words 
+            for ( size_t i=0 ; i<m_words ; i++ ) {
+              if ( i == index ) 	r_write_be[i] = m_cmd_write_be_fifo.read();
+              else		r_write_be[i] = 0x0;
+            }
+            if( !((m_cmd_write_be_fifo.read()==0x0)||(m_cmd_write_be_fifo.read()==0xF)) )
+              r_write_byte=true;
+            else  r_write_byte=false;
+
+            if( m_cmd_write_eop_fifo.read() )
+            {  
+              r_write_fsm = WRITE_DIR_LOCK;
+            }
+            else
+            {
+              r_write_fsm = WRITE_NEXT;
+            }
+          }
+          break;
+        }
+        ////////////////
+      case WRITE_NEXT:	// copy next word of a write burst in local buffer
+        {
+          if ( m_cmd_write_addr_fifo.rok() ) {
+            m_cpt_write_cells++;
+
+            // check that the next word is in the same cache line
+            assert( (m_nline[r_write_address.read()] == m_nline[m_cmd_write_addr_fifo.read()])  
+                && "write error in vci_mem_cache : write burst over a line" );
+            // consume a word in the FIFO & write it in the local buffer 
+            cmd_write_fifo_get=true;
+            size_t index 		= r_write_word_index.read() + r_write_word_count.read();
+            r_write_be[index]   	= m_cmd_write_be_fifo.read();
+            r_write_data[index] 	= m_cmd_write_data_fifo.read();
+            r_write_word_count 	= r_write_word_count.read() + 1;
+            if( !((m_cmd_write_be_fifo.read()==0x0)||(m_cmd_write_be_fifo.read()==0xF)) )
+              r_write_byte=true;
+            if ( m_cmd_write_eop_fifo.read() )  r_write_fsm = WRITE_DIR_LOCK;
+          }
+          break;
+        }
+        ////////////////////
+      case WRITE_DIR_LOCK:	// access directory to check hit/miss
+        {
+          if ( r_alloc_dir_fsm.read() == ALLOC_DIR_WRITE ) {
+            size_t  way = 0;
+            DirectoryEntry entry(m_cache_directory.read(r_write_address.read(), way));
+
+            // copy directory entry in local buffers in case of hit
+            if ( entry.valid )  {	
+              r_write_lock	= entry.lock;
+              r_write_tag         = entry.tag;
+              r_write_copies      = entry.copies;
+              r_write_way  	= way;
+              if(r_write_byte.read())
+                r_write_fsm         = WRITE_DIR_HIT_READ;
+              else  r_write_fsm         = WRITE_DIR_HIT;
+            } else {
+              r_write_fsm		= WRITE_TRT_LOCK;
+              m_cpt_write_miss++;
+            }
+          }
+          break;
+        }
+        ///////////////////
+      case WRITE_DIR_HIT_READ:	// read the cache and complete the buffer (data, when be!=0xF)
+        {			
+          // update local buffer
+          size_t set	= m_y[r_write_address.read()];
+          size_t way	= r_write_way.read();
+          for(size_t i=0 ; i<m_words ; i++) {
+            data_t mask      = 0;
+            if  (r_write_be[i].read() & 0x1) mask = mask | 0x000000FF;
+            if  (r_write_be[i].read() & 0x2) mask = mask | 0x0000FF00;
+            if  (r_write_be[i].read() & 0x4) mask = mask | 0x00FF0000;
+            if  (r_write_be[i].read() & 0x8) mask = mask | 0xFF000000;
+            if(r_write_be[i].read()) { // complete only if mask is not null (for energy consumption)
+              r_write_data[i]  = (r_write_data[i].read() & mask) | 
+                (m_cache_data[way][set][i] & ~mask);
+              r_write_be[i]=0xF;
+            }
+          } // end for
+
+          r_write_fsm            = WRITE_DIR_HIT;
+          break;
+        }
+        ///////////////////
+      case WRITE_DIR_HIT:	// update the cache (data & dirty bit)
+        {			
+          // update directory with Dirty bit
+          DirectoryEntry entry;
+          entry.valid	= true;
+          entry.dirty	= true;
+          entry.tag	= r_write_tag.read();
+          entry.lock	= r_write_lock.read();
+          entry.copies    = r_write_copies.read();
+          size_t set	= m_y[r_write_address.read()];
+          size_t way	= r_write_way.read();
+          m_cache_directory.write(set, way, entry);
+
+          // write data in cache
+          for(size_t i=0 ; i<m_words ; i++) {
+            if  ( r_write_be[i].read() ) {
+              m_cache_data[way][set][i]  = r_write_data[i].read();
+            }
+          } // end for
+
+          // compute the actual number of copies & the modified bit vector
+          size_t	n	= 0;
+          copy_t  mask    = 0x1;
+          copy_t  copies  = r_write_copies.read();
+          for ( size_t i=0 ; i<32 ; i++) {
+            if ( i != r_write_srcid.read() ) {
+              if ( copies & mask ) n++;
+            } else {
+              copies = copies &  ~mask;
+            }
+            mask = (mask << 1);
+          }
+          r_write_nb_copies = n;
+          r_write_copies    = copies;
+
+          if ( n == 0 )   r_write_fsm = WRITE_RSP;
+          else  		r_write_fsm = WRITE_UPT_LOCK;
+          break;
+        }
+        /////////////////////
+      case WRITE_UPT_LOCK: 	// Try to register the request in Update Table
+        {			
+          if ( r_alloc_upt_fsm.read() == ALLOC_UPT_WRITE ) {
+            bool          wok=false;
+            size_t	index=0;
+            size_t        srcid=r_write_srcid.read();
+            size_t        trdid=r_write_trdid.read();
+            size_t        pktid=r_write_pktid.read();
+            size_t        nb_copies=r_write_nb_copies.read();
+            wok                =m_update_tab.set(true,	// it's an update transaction
+                srcid,
+                trdid,
+                pktid,
+                nb_copies,
+                index);
+            r_write_upt_index = index;
+            //  releases the lock protecting Update Table if no entry...
+            if ( wok ) r_write_fsm = WRITE_UPDATE;
+            else       r_write_fsm = WRITE_WAIT_UPT;
+          }
+          break;
+        }
+        ////////////////////
+      case WRITE_WAIT_UPT:	// release the lock protecting UPT
+        {
+          r_write_fsm = WRITE_UPT_LOCK;
+          break;
+        }
+        //////////////////
+      case WRITE_UPDATE:	// send a multi-update request to INIT_CMD fsm
+        {
+          if ( !r_write_to_init_cmd_req ) {
+            r_write_to_init_cmd_req    = true;
+            r_write_to_init_cmd_trdid  = r_write_upt_index.read();
+            r_write_to_init_cmd_nline  = m_nline[r_write_address.read()];
+            r_write_to_init_cmd_index  = r_write_word_index.read();
+            r_write_to_init_cmd_count  = r_write_word_count.read();
+            r_write_to_init_cmd_copies = r_write_copies;
+
+            for(size_t i=0; i<m_words ; i++){
+              assert( ((r_write_be[i].read()==0xF)||(r_write_be[i].read()==0x0)) &&
+                  "write error in vci_mem_cache : invalid BE");
+              if(r_write_be[i].read())  r_write_to_init_cmd_we[i]=true;
+              else                      r_write_to_init_cmd_we[i]=false;
+            }
+
+            size_t min = r_write_word_index.read();
+            size_t max = r_write_word_index.read() + r_write_word_count.read();
+            for (size_t i=min ; i<max ; i++) {
+              r_write_to_init_cmd_data[i] = r_write_data[i];
+            }
+            r_write_fsm = WRITE_IDLE;
+          }
+          break;
+        }
+        ///////////////
+      case WRITE_RSP:		// send a request to TGT_RSP FSM to acknowledge the write
+        {
+          if ( !r_write_to_tgt_rsp_req ) {
+            r_write_to_tgt_rsp_req	= true;
+            r_write_to_tgt_rsp_srcid	= r_write_srcid;
+            r_write_to_tgt_rsp_trdid	= r_write_trdid;
+            r_write_to_tgt_rsp_pktid	= r_write_pktid;
+            r_write_fsm 			= WRITE_IDLE;
+          }
+          break;
+        }
+        ////////////////////
+      case WRITE_TRT_LOCK:	// Miss : check Transaction Table
+        {
+          if ( r_alloc_trt_fsm.read() == ALLOC_TRT_WRITE ) {
+            size_t hit_index = 0;
+            size_t wok_index = 0;
+            bool hit = m_transaction_tab.hit_read(m_nline[r_write_address.read()],hit_index);
+            bool wok = !m_transaction_tab.full(wok_index);
+            if ( hit ) {		// register the modified data in TRT 
+              r_write_trt_index = hit_index;
+              r_write_fsm       = WRITE_TRT_DATA;
+            } else if ( wok ) {	// set a new entry in TRT
+              r_write_trt_index = wok_index;
+              r_write_fsm       = WRITE_TRT_SET;
+            } else {		// wait an empty entry in TRT
+              r_write_fsm       = WRITE_WAIT_TRT;
+            }
+          }
+          break;
+        }
+        ////////////////////
+      case WRITE_WAIT_TRT:	// release the lock protecting TRT
+        {  
+          r_write_fsm = WRITE_DIR_LOCK;
+          break;
+        }
+        ///////////////////
+      case WRITE_TRT_SET:	// register a new transaction in TRT (Write Buffer)
+        {  
+          if ( r_alloc_trt_fsm.read() == ALLOC_TRT_WRITE ) {
+            std::vector<be_t> be_vector;
+            std::vector<data_t> data_vector;
+            be_vector.clear();
+            data_vector.clear();
+            for ( size_t i=0; i<m_words; i++ ) {
+              be_vector.push_back(r_write_be[i]);
+              data_vector.push_back(r_write_data[i]);
+            }
+            m_transaction_tab.set(r_write_trt_index.read(),
+                true,				// read request to XRAM
+                m_nline[r_write_address.read()],
+                r_write_srcid.read(),
+                r_write_trdid.read(),
+                r_write_pktid.read(),
+                false,				// not a processor read
+                false,				// not a single word 
+                0,				// word index
+                be_vector,
+                data_vector);
+            r_write_fsm = WRITE_XRAM_REQ;
+          }
+          break;
+        }  
+        ///////////////////
+      case WRITE_TRT_DATA:	// update an entry in TRT (Write Buffer)
+        {  
+          if ( r_alloc_trt_fsm.read() == ALLOC_TRT_WRITE ) {
+            std::vector<be_t> be_vector;
+            std::vector<data_t> data_vector;
+            be_vector.clear();
+            data_vector.clear();
+            for ( size_t i=0; i<m_words; i++ ) {
+              be_vector.push_back(r_write_be[i]);
+              data_vector.push_back(r_write_data[i]);
+            }
+            m_transaction_tab.write_data_mask(r_write_trt_index.read(),
+                be_vector,
+                data_vector);
+            r_write_fsm = WRITE_RSP;
+          }
+          break;
+        }
+        ////////////////////
+      case WRITE_XRAM_REQ:	// send a request to XRAM_CMD FSM
+        {  
+          if ( !r_write_to_xram_cmd_req ) {
+            r_write_to_xram_cmd_req     = true;
+            r_write_to_xram_cmd_nline   = m_nline[r_write_address.read()];
+            r_write_to_xram_cmd_trdid   = r_write_trt_index.read();
+            r_write_fsm                 = WRITE_RSP;
+          }
+          break;
+        }
+    } // end switch r_write_fsm
+
+    ///////////////////////////////////////////////////////////////////////
+    //		XRAM_CMD FSM
+    ///////////////////////////////////////////////////////////////////////
+    // The XRAM_CMD fsm controls the command packets to the XRAM :
+    // - It sends a single cell VCI write in case of MISS request
+    // posted by the READ, WRITE or LLSC FSMs : the WDATA field
+    // contains the cache line index and the TRDID fiels contains 
+    // the Transaction Tab index.
+    // The VCI response is a multi-cell packet : the N cells contain
+    // the N data words.
+    // - It sends a multi-cell VCI write when the XRAM_RSP FSM request 
+    // to save a dirty line to the XRAM : The first cell contain the
+    // cache line index, the following cells contain the data.
+    // The VCI response is a single cell packet.
+    // This FSM handles requests from the READ, WRITE, LLSC & XRAM_RSP FSMs 
+    // with a round-robin priority.
+    ////////////////////////////////////////////////////////////////////////
+
+    switch ( r_xram_cmd_fsm.read() ) {
+
+      //////////////////////// 
+      case XRAM_CMD_READ_IDLE:
+        if      ( r_write_to_xram_cmd_req )     r_xram_cmd_fsm = XRAM_CMD_WRITE_NLINE;
+        else if ( r_llsc_to_xram_cmd_req  )     r_xram_cmd_fsm = XRAM_CMD_LLSC_NLINE;
+        else if ( r_xram_rsp_to_xram_cmd_req  ) r_xram_cmd_fsm = XRAM_CMD_XRAM_DATA;
+        else if ( r_read_to_xram_cmd_req  )     r_xram_cmd_fsm = XRAM_CMD_READ_NLINE;
+        break;
+        //////////////////////// 
+      case XRAM_CMD_WRITE_IDLE:
+        if      ( r_llsc_to_xram_cmd_req  )     r_xram_cmd_fsm = XRAM_CMD_LLSC_NLINE;
+        else if ( r_xram_rsp_to_xram_cmd_req  ) r_xram_cmd_fsm = XRAM_CMD_XRAM_DATA;
+        else if ( r_read_to_xram_cmd_req  )     r_xram_cmd_fsm = XRAM_CMD_READ_NLINE;
+        else if ( r_write_to_xram_cmd_req )     r_xram_cmd_fsm = XRAM_CMD_WRITE_NLINE;
+        break;
+        //////////////////////// 
+      case XRAM_CMD_LLSC_IDLE:
+        if      ( r_xram_rsp_to_xram_cmd_req  ) r_xram_cmd_fsm = XRAM_CMD_XRAM_DATA;
+        else if ( r_read_to_xram_cmd_req  )     r_xram_cmd_fsm = XRAM_CMD_READ_NLINE;
+        else if ( r_write_to_xram_cmd_req )     r_xram_cmd_fsm = XRAM_CMD_WRITE_NLINE;
+        else if ( r_llsc_to_xram_cmd_req  )     r_xram_cmd_fsm = XRAM_CMD_LLSC_NLINE;
+        break;
+        //////////////////////// 
+      case XRAM_CMD_XRAM_IDLE:
+        if      ( r_read_to_xram_cmd_req  )     r_xram_cmd_fsm = XRAM_CMD_READ_NLINE;
+        else if ( r_write_to_xram_cmd_req )     r_xram_cmd_fsm = XRAM_CMD_WRITE_NLINE;
+        else if ( r_llsc_to_xram_cmd_req  )     r_xram_cmd_fsm = XRAM_CMD_LLSC_NLINE;
+        else if ( r_xram_rsp_to_xram_cmd_req  ) r_xram_cmd_fsm = XRAM_CMD_XRAM_DATA;
+        break;
+        /////////////////////////
+      case XRAM_CMD_READ_NLINE:
+        if ( p_vci_ixr.cmdack ) {
+          r_xram_cmd_fsm = XRAM_CMD_READ_IDLE;		
+          r_read_to_xram_cmd_req = false;
+        }
+        break;
+        //////////////////////////
+      case XRAM_CMD_WRITE_NLINE:
+        if ( p_vci_ixr.cmdack ) {
+          r_xram_cmd_fsm = XRAM_CMD_WRITE_IDLE;		
+          r_write_to_xram_cmd_req = false;
+        }
+        break;
+        /////////////////////////
+      case XRAM_CMD_LLSC_NLINE:
+        if ( p_vci_ixr.cmdack ) {
+          r_xram_cmd_fsm = XRAM_CMD_LLSC_IDLE;		
+          r_llsc_to_xram_cmd_req = false;
+        }
+        break;
+        ////////////////////////
+      case XRAM_CMD_XRAM_DATA:
+        if ( p_vci_ixr.cmdack ) {
+          if ( r_xram_cmd_cpt.read() == (m_words - 1) ) {
+            r_xram_cmd_cpt = 0;
+            r_xram_cmd_fsm = XRAM_CMD_XRAM_IDLE;
+            r_xram_rsp_to_xram_cmd_req = false;
+          } else {
+            r_xram_cmd_cpt = r_xram_cmd_cpt + 1;
+          }
+        }
+        break;
+
+    } // end switch r_xram_cmd_fsm
+
+    ////////////////////////////////////////////////////////////////////////////
+    //                IXR_RSP FSM
+    ////////////////////////////////////////////////////////////////////////////
+    // The IXR_RSP FSM receives the response packets from the XRAM,
+    // for both write transaction, and read transaction.
+    //
+    // - A response to a write request is a single-cell VCI packet.
+    // The Transaction Tab index is contained in the RTRDID field.
+    // The FSM takes the lock protecting the TRT, and the corresponding
+    // entry is erased.
+    //	
+    // - A response to a read request is a multi-cell VCI packet.
+    // The Transaction Tab index is contained in the RTRDID field.
+    // The N cells contain the N words of the cache line in the RDATA field.
+    // The FSM takes the lock protecting the TRT to store the line in the TRT
+    // (taking into account the write requests already stored in the TRT).
+    // When the line is completely written, the corresponding rok signal is set.
+    ///////////////////////////////////////////////////////////////////////////////
+
+    switch ( r_ixr_rsp_fsm.read() ) {
+
+      ///////////////////
+      case IXR_RSP_IDLE:	// test if it's a read or a write transaction
+        {
+          if ( p_vci_ixr.rspval ) {
+            r_ixr_rsp_cpt   = 0;
+            r_ixr_rsp_trt_index = p_vci_ixr.rtrdid.read();
+            if ( p_vci_ixr.reop )  r_ixr_rsp_fsm = IXR_RSP_ACK;
+            else                   r_ixr_rsp_fsm = IXR_RSP_TRT_READ;
+          }
+          break;  
+        }
+        ////////////////////////
+      case IXR_RSP_ACK:        // Acknowledge the vci response
+        r_ixr_rsp_fsm = IXR_RSP_TRT_ERASE;
+        break;
+        ////////////////////////
+      case IXR_RSP_TRT_ERASE: 	// erase the entry in the TRT
+        {
+          if ( r_alloc_trt_fsm.read() == ALLOC_TRT_IXR_RSP ) {
+            m_transaction_tab.erase(r_ixr_rsp_trt_index.read());
+            r_ixr_rsp_fsm = IXR_RSP_IDLE;
+          }
+          break;
+        }
+        ///////////////////////
+      case IXR_RSP_TRT_READ:		// write data in the TRT
+        {
+          if ( (r_alloc_trt_fsm.read() == ALLOC_TRT_IXR_RSP) &&  p_vci_ixr.rspval ) {
+            bool   eop  	= p_vci_ixr.reop.read();
+            data_t data 	= p_vci_ixr.rdata.read();
+            size_t index        = r_ixr_rsp_trt_index.read();
+            assert( eop == (r_ixr_rsp_cpt.read() == (m_words-1)) 
+                && "Error in VCI_MEM_CACHE : invalid length for a response from XRAM");
+            m_transaction_tab.write_rsp(index, r_ixr_rsp_cpt.read(), data);
+            r_ixr_rsp_cpt = r_ixr_rsp_cpt.read() + 1;
+            if ( eop ) {
+              r_ixr_rsp_to_xram_rsp_rok[r_ixr_rsp_trt_index.read()]=true;
+              r_ixr_rsp_fsm = IXR_RSP_IDLE;
+            }
+          }
+          break;
+        }
+    } // end swich r_ixr_rsp_fsm
+
+
+    ////////////////////////////////////////////////////////////////////////////
+    //                XRAM_RSP FSM
+    ////////////////////////////////////////////////////////////////////////////
+    // The XRAM_RSP FSM handles the response packets from the XRAM,
+    // for read transactions.
+    //
+    // When a response is available, the corresponding TRT entry 
+    // is copied in a local buffer to be written in the cache. 
+    // Then, the FSM releases the lock protecting the TRT, and takes the lock 
+    // protecting the cache directory.
+    // It selects a cache slot and writes the line in the cache.
+    // If it was a read MISS, the XRAM_RSP FSM send a request to the TGT_RSP
+    // FSM to return the cache line to the registered processor.
+    // If there is no empty slot, a victim line is evicted, and
+    // invalidate requests are sent to the L1 caches containing copies.
+    // If this line is dirty, the XRAM_RSP FSM send a request to the XRAM_CMD 
+    // FSM to save the victim line to the XRAM, and register the write transaction
+    // in the TRT (using the entry previously used by the read transaction).
+    ///////////////////////////////////////////////////////////////////////////////
+
+    switch ( r_xram_rsp_fsm.read() ) {
+
+      ///////////////////
+      case XRAM_RSP_IDLE:	// test if there is a response with a round robin priority
+        {
+          size_t ptr   = r_xram_rsp_trt_index.read();
+          size_t lines = TRANSACTION_TAB_LINES;
+          for(size_t i=0; i<lines; i++){
+            size_t index=(i+ptr+1)%lines;
+            if(r_ixr_rsp_to_xram_rsp_rok[index]){
+              r_xram_rsp_trt_index=index;
+              r_ixr_rsp_to_xram_rsp_rok[index]=false;
+              r_xram_rsp_fsm           = XRAM_RSP_DIR_LOCK;
+              break;
+            }
+          }
+          break;  
+        }
+        ///////////////////////
+      case XRAM_RSP_DIR_LOCK: 	// Take the lock on the directory
+        {
+          if( r_alloc_dir_fsm.read() == ALLOC_DIR_XRAM_RSP ) {
+            r_xram_rsp_fsm           = XRAM_RSP_TRT_COPY;
+          }
+          break;
+        }
+        ///////////////////////
+      case XRAM_RSP_TRT_COPY:		// Copy the TRT entry in the local buffer and eviction of a cache line
+        {
+          if ( (r_alloc_trt_fsm.read() == ALLOC_TRT_XRAM_RSP) ) {
+            size_t index = r_xram_rsp_trt_index.read();
+            TransactionTabEntry    trt_entry(m_transaction_tab.read(index));	
+
+            r_xram_rsp_trt_buf.copy(trt_entry);  // TRT entry local buffer
+
+            // selects & extracts a victim line from cache
+            size_t way = 0;
+            size_t set = m_y[trt_entry.nline * m_words * 4];
+            DirectoryEntry victim(m_cache_directory.select(set, way));
+
+            for (size_t i=0 ; i<m_words ; i++) r_xram_rsp_victim_data[i] = m_cache_data[way][set][i];
+
+            r_xram_rsp_victim_copies = victim.copies;
+            r_xram_rsp_victim_way    = way;
+            r_xram_rsp_victim_set    = set;
+            r_xram_rsp_victim_nline  = victim.tag*m_sets + set;
+            r_xram_rsp_victim_inval  = victim.valid && (victim.copies != 0);
+            r_xram_rsp_victim_dirty  = victim.dirty;
+
+            r_xram_rsp_fsm = XRAM_RSP_DIR_UPDT;
+          }
+          break;
+        }
+        ///////////////////////
+      case XRAM_RSP_DIR_UPDT:		// updates the cache (both data & directory)
+        {
+          // update data
+          size_t set   = r_xram_rsp_victim_set.read();
+          size_t way   = r_xram_rsp_victim_way.read();
+          for(size_t i=0; i<m_words ; i++){
+            m_cache_data[way][set][i] = r_xram_rsp_trt_buf.wdata[i];
+          }
+          // update directory
+          bool dirty = false;
+          for(size_t i=0; i<m_words;i++){
+            dirty = dirty || (r_xram_rsp_trt_buf.wdata_be[i] != 0);
+          }
+          DirectoryEntry entry;
+          entry.valid	= true;
+          entry.lock	= false;
+          entry.dirty	= dirty;
+          entry.tag	= r_xram_rsp_trt_buf.nline / m_sets;
+          if(r_xram_rsp_trt_buf.proc_read) {
+            entry.copies    = 0x1 << r_xram_rsp_trt_buf.srcid;
+          } else {
+            entry.copies    = 0;
+          }
+          m_cache_directory.write(set, way, entry);
+          // If the victim is not dirty, we erase the entry in the TRT
+          if      (!r_xram_rsp_victim_dirty.read()) m_transaction_tab.erase(r_xram_rsp_trt_index.read());
+          // Next state
+          if      ( r_xram_rsp_victim_dirty.read())       r_xram_rsp_fsm = XRAM_RSP_TRT_DIRTY;
+          else if ( r_xram_rsp_trt_buf.proc_read  )       r_xram_rsp_fsm = XRAM_RSP_DIR_RSP;
+          else if ( r_xram_rsp_victim_inval.read())       r_xram_rsp_fsm = XRAM_RSP_UPT_LOCK;
+          else                                            r_xram_rsp_fsm = XRAM_RSP_IDLE;
+          break;
+        }
+        ////////////////////////
+      case XRAM_RSP_TRT_DIRTY:		// set the TRT entry (write line to XRAM) if the victim is dirty
+        {
+          if ( r_alloc_trt_fsm.read() == ALLOC_TRT_XRAM_RSP ) {
+            m_transaction_tab.set(r_xram_rsp_trt_index.read(),
+                false,				// write to XRAM
+                r_xram_rsp_victim_nline.read(), // line index
+                0,
+                0,
+                0,
+                false,
+                false,
+                0,
+                std::vector<be_t>(m_words,0),
+                std::vector<data_t>(m_words,0) );
+            if      ( r_xram_rsp_trt_buf.proc_read  )       r_xram_rsp_fsm = XRAM_RSP_DIR_RSP;
+            else if ( r_xram_rsp_victim_inval.read())       r_xram_rsp_fsm = XRAM_RSP_UPT_LOCK;
+            else                                            r_xram_rsp_fsm = XRAM_RSP_WRITE_DIRTY;
+          }
+          break;
+        }
+        //////////////////////
+      case XRAM_RSP_DIR_RSP:     // send a request to TGT_RSP FSM in case of read
+        {
+          if ( !r_xram_rsp_to_tgt_rsp_req ) {
+            r_xram_rsp_to_tgt_rsp_srcid = r_xram_rsp_trt_buf.srcid;
+            r_xram_rsp_to_tgt_rsp_trdid = r_xram_rsp_trt_buf.trdid;
+            r_xram_rsp_to_tgt_rsp_pktid = r_xram_rsp_trt_buf.pktid;
+            for (size_t i=0; i < m_words; i++) {
+              r_xram_rsp_to_tgt_rsp_data[i] = r_xram_rsp_trt_buf.wdata[i];
+              if( r_xram_rsp_trt_buf.single_word ) {
+                r_xram_rsp_to_tgt_rsp_val[i] = (r_xram_rsp_trt_buf.word_index == i);
+              } else {
+                r_xram_rsp_to_tgt_rsp_val[i] = true;
+              }
+            } 
+            r_xram_rsp_to_tgt_rsp_req   = true;
+            if      ( r_xram_rsp_victim_inval ) r_xram_rsp_fsm = XRAM_RSP_UPT_LOCK;
+            else if ( r_xram_rsp_victim_dirty ) r_xram_rsp_fsm = XRAM_RSP_WRITE_DIRTY; 
+            else                                r_xram_rsp_fsm = XRAM_RSP_IDLE;
+          }
+          break;
+        }
+        ///////////////////////
+      case XRAM_RSP_UPT_LOCK:	// Try to register the inval transaction in UPT
+        {
+          if ( r_alloc_upt_fsm == ALLOC_UPT_XRAM_RSP ) {
+            size_t index;
+            copy_t  copies  = r_xram_rsp_victim_copies.read();
+            copy_t  mask = 0x1;
+            size_t n=0;
+            for ( size_t i=0 ; i<32 ; i++) {
+              if ( copies & mask ) n++;
+              mask = (mask << 1);
+            }
+            bool	 wok = m_update_tab.set(false,	// it's an inval transaction
+                0,
+                0,
+                0,
+                n,
+                index);
+            if ( wok ) {
+              r_xram_rsp_upt_index = index;
+              r_xram_rsp_fsm       = XRAM_RSP_INVAL;
+            } else {
+              r_xram_rsp_fsm       = XRAM_RSP_WAIT;
+            }
+          }
+          break;
+        }
+        ///////////////////
+      case XRAM_RSP_WAIT:	// releases UPT lock for one cycle
+        {
+          r_xram_rsp_fsm = XRAM_RSP_UPT_LOCK;
+        }
+        ////////////////////
+      case XRAM_RSP_INVAL:	// send invalidate request to INIT_CMD FSM
+        {
+          if( !r_xram_rsp_to_init_cmd_req ) {	      
+            r_xram_rsp_to_init_cmd_req     = true; 
+            r_xram_rsp_to_init_cmd_nline   = r_xram_rsp_victim_nline.read();
+            r_xram_rsp_to_init_cmd_trdid   = r_xram_rsp_upt_index;
+            r_xram_rsp_to_init_cmd_copies  = r_xram_rsp_victim_copies;
+            if ( r_xram_rsp_victim_dirty ) r_xram_rsp_fsm = XRAM_RSP_WRITE_DIRTY;
+            else		                 r_xram_rsp_fsm = XRAM_RSP_IDLE;
+          }
+          break;
+        }
+        //////////////////////////
+      case XRAM_RSP_WRITE_DIRTY:	// send a write request to XRAM_CMD FSM
+        {
+          if ( !r_xram_rsp_to_xram_cmd_req ) {
+            r_xram_rsp_to_xram_cmd_req = true;
+            r_xram_rsp_to_xram_cmd_nline = r_xram_rsp_victim_nline.read();
+            r_xram_rsp_to_xram_cmd_trdid = r_xram_rsp_trt_index.read();
+            for(size_t i=0; i<m_words ; i++) {
+              r_xram_rsp_to_xram_cmd_data[i] = r_xram_rsp_victim_data[i];
+            }
+            m_cpt_write_dirty++;
+            r_xram_rsp_fsm = XRAM_RSP_IDLE;
+          }
+          break;
+        }
+    } // end swich r_xram_rsp_fsm
+
+    ////////////////////////////////////////////////////////////////////////////////////
+    //		CLEANUP FSM
+    ////////////////////////////////////////////////////////////////////////////////////
+    // The CLEANUP FSM handles the cleanup request from L1 caches.
+    // It accesses the cache directory to update the list of copies.
+    //
+    // !!!!!!!! The actual cleanup of the cache directory has to be done...
+    //
+    ////////////////////////////////////////////////////////////////////////////////////
+
+    switch ( r_cleanup_fsm.read() ) {
+
+      ///////////////////
+      case CLEANUP_IDLE:
+        {
+          if ( m_cmd_cleanup_nline_fifo.rok() ) {
+            m_cpt_cleanup++;
+            cmd_cleanup_fifo_get = true;
+            r_cleanup_nline      = m_cmd_cleanup_nline_fifo.read();
+            r_cleanup_srcid      = m_cmd_cleanup_srcid_fifo.read();
+            r_cleanup_trdid      = m_cmd_cleanup_trdid_fifo.read();
+            r_cleanup_pktid      = m_cmd_cleanup_pktid_fifo.read();
+
+            r_cleanup_fsm        = CLEANUP_DIR_LOCK;
+          }
+          break;
+        }
+        //////////////////////
+      case CLEANUP_DIR_LOCK:
+        {
+          if ( r_alloc_dir_fsm.read() == ALLOC_DIR_CLEANUP ) {
+
+            // Read the directory
+            size_t way = 0;
+            DirectoryEntry entry = m_cache_directory.read(r_cleanup_nline.read() << (m_words +2) , way);
+
+            r_cleanup_dirty	= entry.dirty;
+            r_cleanup_tag		= entry.tag;
+            r_cleanup_lock	= entry.lock;
+            r_cleanup_way		= way;
+            r_cleanup_copies	= entry.copies & ~(0x1 << r_cleanup_srcid.read());
+
+            // In case of hit, the copy must be cleaned in the copies bit-vector
+            if( entry.valid )  { 
+              r_cleanup_fsm = CLEANUP_DIR_WRITE;
+            } else {
+              r_cleanup_fsm = CLEANUP_RSP;
+            }
+          }
+          break;
+        }
+        ///////////////////////
+      case CLEANUP_DIR_WRITE:
+        {
+          size_t way      = r_cleanup_way.read();
+#define L2 soclib::common::uint32_log2
+          size_t set      = m_y[r_cleanup_nline.read() << (L2(m_words) +2)];
+#undef L2
+
+          // update the cache directory (for the copies)
+          DirectoryEntry entry;
+          entry.valid	= true;
+          entry.dirty	= r_cleanup_dirty.read();
+          entry.tag	= r_cleanup_tag.read();
+          entry.lock	= r_cleanup_lock.read();
+          entry.copies    = r_cleanup_copies.read();
+          m_cache_directory.write(set, way, entry);  
+
+          // response to the cache      
+          r_cleanup_fsm = CLEANUP_RSP;
+
+          break;
+        }
+        /////////////////
+      case CLEANUP_RSP:
+        {
+          if ( !r_cleanup_to_tgt_rsp_req ) {
+            r_cleanup_to_tgt_rsp_req   = true;
+            r_cleanup_to_tgt_rsp_srcid = r_cleanup_srcid.read();
+            r_cleanup_to_tgt_rsp_trdid = r_cleanup_trdid.read();
+            r_cleanup_to_tgt_rsp_pktid = r_cleanup_pktid.read();
+            r_cleanup_fsm = CLEANUP_IDLE;
+          }
+          break;
+        }
+    } // end switch cleanup fsm
+
+    ////////////////////////////////////////////////////////////////////////////////////
+    //		LLSC FSM
+    ////////////////////////////////////////////////////////////////////////////////////
+    // The LLSC FSM handles the LL & SC atomic access.
+    //
+    // For a LL :
+    // It access the directory to check hit / miss.
+    // - In case of hit, the LL request is registered in the Atomic Table and the
+    // response is sent to the requesting processor.
+    // - In case of miss, the LLSC FSM accesses the transaction table. 
+    // If a read transaction to the XRAM for this line already exists, 
+    // or if the transaction table is full, it returns to IDLE state.
+    // Otherwise, a new transaction to the XRAM is initiated.
+    // In both cases, the LL request is not consumed in the FIFO.
+    //
+    // For a SC :
+    // It access the directory to check hit / miss.
+    // - In case of hit, the Atomic Table is checked and the proper response
+    // (true or false is sent to the requesting processor.
+    // - In case of miss, the LLSC FSM accesses the transaction table. 
+    // If a read transaction to the XRAM for this line already exists, 
+    // or if the transaction table is full, it returns to IDLE state. 
+    // Otherwise, a new transaction to the XRAM is initiated.
+    // In both cases, the SC request is not consumed in the FIFO.
+    /////////////////////////////////////////////////////////////////////
+
+    switch ( r_llsc_fsm.read() ) {
+
+      ///////////////
+      case LLSC_IDLE:		// test LL / SC
+        {
+          if( m_cmd_llsc_addr_fifo.rok() ) {
+            if(m_cmd_llsc_sc_fifo.read()){
+              m_cpt_sc++;
+              r_llsc_fsm = SC_DIR_LOCK;
+            }
+            else{
+              m_cpt_ll++;
+              r_llsc_fsm = LL_DIR_LOCK;
+            }
+          }	
+          break;
+        }
+        /////////////////
+      case LL_DIR_LOCK:		// check directory for hit / miss
+        {
+          if( r_alloc_dir_fsm.read() == ALLOC_DIR_LLSC ) {
+            size_t way = 0;
+            DirectoryEntry entry(m_cache_directory.read(m_cmd_llsc_addr_fifo.read(), way));
+            r_llsc_dirty  = entry.dirty;
+            r_llsc_tag    = entry.tag;
+            r_llsc_way    = way;
+            r_llsc_copies = entry.copies | (0x1 << m_cmd_llsc_srcid_fifo.read());
+
+            if ( entry.valid )  r_llsc_fsm = LL_DIR_HIT;
+            else                r_llsc_fsm = LLSC_TRT_LOCK;
+          }
+          break;
+        }
+        ////////////////
+      case LL_DIR_HIT:		// read hit : update the memory cache
+        {
+          size_t way	= r_llsc_way.read();
+          size_t set	= m_y[m_cmd_llsc_addr_fifo.read()];
+          size_t word	= m_x[m_cmd_llsc_addr_fifo.read()];
+
+          // update directory (lock bit & copies)
+          DirectoryEntry entry;
+          entry.valid	= true;
+          entry.dirty	= r_llsc_dirty.read();
+          entry.lock	= true;
+          entry.tag	= r_llsc_tag.read();
+          entry.copies    = r_llsc_copies.read();
+          m_cache_directory.write(set, way, entry);
+
+          // read data in cache
+          r_llsc_data	= m_cache_data[way][set][word];
+
+          // set Atomic Table
+          m_atomic_tab.set(m_cmd_llsc_srcid_fifo.read(), m_cmd_llsc_addr_fifo.read());
+
+          r_llsc_fsm 	= LL_RSP;
+          break;
+        }
+        ////////////
+      case LL_RSP:		// request the TGT_RSP FSM to return data
+        {
+          if ( !r_llsc_to_tgt_rsp_req ) {
+            cmd_llsc_fifo_get		= true;
+            r_llsc_to_tgt_rsp_data	= r_llsc_data.read();
+            r_llsc_to_tgt_rsp_srcid	= m_cmd_llsc_srcid_fifo.read();
+            r_llsc_to_tgt_rsp_trdid	= m_cmd_llsc_trdid_fifo.read();
+            r_llsc_to_tgt_rsp_pktid	= m_cmd_llsc_pktid_fifo.read();
+            r_llsc_to_tgt_rsp_req		= true;
+            r_llsc_fsm = LLSC_IDLE;
+          }
+          break;
+        }
+        /////////////////
+      case SC_DIR_LOCK:
+        {
+          if( r_alloc_dir_fsm.read() == ALLOC_DIR_LLSC ) {
+            size_t way = 0;
+            DirectoryEntry entry(m_cache_directory.read(m_cmd_llsc_addr_fifo.read(), way));
+            bool ok = m_atomic_tab.isatomic(m_cmd_llsc_srcid_fifo.read(),m_cmd_llsc_addr_fifo.read());
+            if( ok ) {
+              r_llsc_dirty 	= entry.dirty;
+              r_llsc_tag		= entry.tag;
+              r_llsc_way		= way;
+              r_llsc_copies 	= entry.copies;
+              if ( entry.valid )  r_llsc_fsm = SC_DIR_HIT;
+              else                r_llsc_fsm = LLSC_TRT_LOCK;
+            } else {
+              r_llsc_fsm = SC_RSP_FALSE;
+            }
+          }
+          break;
+        }
+        ////////////////
+      case SC_DIR_HIT:
+        {
+          size_t way	= r_llsc_way.read();
+          size_t set	= m_y[m_cmd_llsc_addr_fifo.read()]; 
+          size_t word	= m_x[m_cmd_llsc_addr_fifo.read()]; 
+
+          // update directory (lock & dirty bits
+          DirectoryEntry entry;
+          entry.valid	= true;
+          entry.dirty	= true;
+          entry.lock	= true;
+          entry.tag	= r_llsc_tag.read();
+          entry.copies    = r_llsc_copies.read();
+          m_cache_directory.write(set, way, entry);
+
+          // write data in cache
+          m_cache_data[way][set][word] = m_cmd_llsc_wdata_fifo.read();
+
+          // reset Atomic Table
+          m_atomic_tab.reset(m_cmd_llsc_addr_fifo.read());
+
+          r_llsc_fsm = SC_RSP_TRUE;
+          break;
+        }
+        //////////////////
+      case SC_RSP_FALSE:
+        {
+          if( !r_llsc_to_tgt_rsp_req ) {
+            cmd_llsc_fifo_get		= true;
+            r_llsc_to_tgt_rsp_req		= true;
+            r_llsc_to_tgt_rsp_data	= 1;
+            r_llsc_to_tgt_rsp_srcid	= m_cmd_llsc_srcid_fifo.read();
+            r_llsc_to_tgt_rsp_trdid	= m_cmd_llsc_trdid_fifo.read();
+            r_llsc_to_tgt_rsp_pktid	= m_cmd_llsc_pktid_fifo.read();
+            r_llsc_fsm 			= LLSC_IDLE;
+          }
+          break;
+        }
+        /////////////////
+      case SC_RSP_TRUE:
+        {
+          if( !r_llsc_to_tgt_rsp_req ) {
+            cmd_llsc_fifo_get		= true;
+            r_llsc_to_tgt_rsp_req		= true;
+            r_llsc_to_tgt_rsp_data	= 0;
+            r_llsc_to_tgt_rsp_srcid	= m_cmd_llsc_srcid_fifo.read();
+            r_llsc_to_tgt_rsp_trdid	= m_cmd_llsc_trdid_fifo.read();
+            r_llsc_to_tgt_rsp_pktid	= m_cmd_llsc_pktid_fifo.read();
+            r_llsc_fsm 			= LLSC_IDLE;
+          }
+          break;
+        }
+        ///////////////////
+      case LLSC_TRT_LOCK:         // read or write miss : check the Transaction Table
+        {
+          if( r_alloc_trt_fsm.read() == ALLOC_TRT_LLSC ) {
+            size_t   index = 0;
+            bool hit = m_transaction_tab.hit_read(m_nline[m_cmd_llsc_addr_fifo.read()],index);
+            bool wok = !m_transaction_tab.full(index);
+
+            if ( hit || !wok ) {  // missing line already requested or no space in TRT
+              r_llsc_fsm = LLSC_IDLE;
+            } else {
+              r_llsc_trt_index = index;
+              r_llsc_fsm       = LLSC_TRT_SET;
+            }
+          }
+          break;
+        }
+        //////////////////
+      case LLSC_TRT_SET:	// register the XRAM transaction in Transaction Table
+        {
+          if( r_alloc_trt_fsm.read() == ALLOC_TRT_LLSC ) {
+            m_transaction_tab.set(r_llsc_trt_index.read(),
+                true,
+                m_nline[m_cmd_llsc_addr_fifo.read()],
+                m_cmd_llsc_srcid_fifo.read(),
+                m_cmd_llsc_trdid_fifo.read(),
+                m_cmd_llsc_pktid_fifo.read(),
+                false,
+                false,
+                0,
+                std::vector<be_t>(m_words,0),
+                std::vector<data_t>(m_words,0));
+            r_llsc_fsm = LLSC_XRAM_REQ;
+          }
+          break;
+        }
+        ///////////////////
+      case LLSC_XRAM_REQ:	// request the XRAM_CMD FSM to tetch the missing line
+        {
+          if ( !r_llsc_to_xram_cmd_req ) {
+            r_llsc_to_xram_cmd_req        = true;
+            r_llsc_to_xram_cmd_trdid      = r_llsc_trt_index.read();
+            r_llsc_to_xram_cmd_nline      = m_nline[m_cmd_llsc_addr_fifo.read()];
+            if( m_cmd_llsc_sc_fifo.read() ) {
+              r_llsc_fsm                    = SC_RSP_FALSE;
+            } else {
+              cmd_llsc_fifo_get             = true;
+              r_llsc_fsm                    = LLSC_IDLE;
+            }
+          }
+          break;
+        }
+    } // end switch r_llsc_fsm
+
+
+    //////////////////////////////////////////////////////////////////////////////
+    //		INIT_CMD FSM
+    //////////////////////////////////////////////////////////////////////////////
+    // The INIT_CMD fsm controls the VCI CMD initiator port, used to update
+    // or invalidate cache lines in L1 caches.
+    // It implements a round-robin priority between the two following requests:
+    // - r_write_to_init_cmd_req : update request from WRITE FSM 
+    // - r_xram_rsp_to_init_cmd_req : invalidate request from XRAM_RSP FSM 
+    // The inval request is a single cell VCI write command containing the 
+    // index of the line to be invalidated.
+    // The update request is a multi-cells VCI write command : The first cell 
+    // contains the index of the cache line to be updated. The second cell contains 
+    // the index of the first modified word in the line. The following cells
+    // contain the data.
+    ///////////////////////////////////////////////////////////////////////////////
+
+    switch ( r_init_cmd_fsm.read() ) {
+
+      //////////////////////// 
+      case INIT_CMD_UPDT_IDLE:	// Invalidate requests have highest priority
+        {
+          if ( r_xram_rsp_to_init_cmd_req ) {
+            r_init_cmd_fsm = INIT_CMD_INVAL_SEL;
+            m_cpt_inval++;
+          } else if ( r_write_to_init_cmd_req ) {
+            r_init_cmd_fsm = INIT_CMD_UPDT_SEL;
+            m_cpt_update++;
+          }
+          break;
+        }
+        /////////////////////////
+      case INIT_CMD_INVAL_IDLE:	// Update requests have highest priority
+        {
+          if ( r_write_to_init_cmd_req ) {
+            r_init_cmd_fsm = INIT_CMD_UPDT_SEL;
+            m_cpt_update++;
+          } else if ( r_xram_rsp_to_init_cmd_req ) {
+            r_init_cmd_fsm = INIT_CMD_INVAL_SEL;
+            m_cpt_inval++;
+          }
+          break;
+        }
+        ////////////////////////
+      case INIT_CMD_INVAL_SEL:	// selects the next L1 cache
+        {
+
+          if (r_xram_rsp_to_init_cmd_copies.read() == 0) {	// no more copies
+            r_xram_rsp_to_init_cmd_req = false;
+            r_init_cmd_fsm = INIT_CMD_INVAL_IDLE;
+          } else {						// select the first target
+            copy_t copies = r_xram_rsp_to_init_cmd_copies.read();
+            copy_t mask   = 0x1;
+            for ( size_t i=0 ; i<8*sizeof(copy_t) ; i++ ) {
+              if ( copies & mask ) {
+                r_init_cmd_target = i;
+                break;
+              }
+              mask = mask << 1;
+            } // end for 
+            m_cpt_inval_mult++;
+            r_init_cmd_fsm = INIT_CMD_INVAL_NLINE;
+            r_xram_rsp_to_init_cmd_copies = copies & ~mask;
+          }
+          break;
+        }
+        ////////////////////////
+      case INIT_CMD_INVAL_NLINE:	// send the cache line index
+        {
+          if ( p_vci_ini.cmdack ) r_init_cmd_fsm = INIT_CMD_INVAL_SEL;
+          break;
+        }
+        ///////////////////////
+      case INIT_CMD_UPDT_SEL:	// selects the next L1 cache
+        {
+          if (r_write_to_init_cmd_copies.read() == 0) {	// no more copies
+            r_write_to_init_cmd_req = false;
+            r_init_cmd_fsm    = INIT_CMD_UPDT_IDLE;
+          } else {						// select the first target
+            copy_t copies = r_write_to_init_cmd_copies.read();
+            copy_t mask   = 0x1;
+            for ( size_t i=0 ; i<8*sizeof(copy_t) ; i++ ) {
+              if ( copies & mask ) {
+                r_init_cmd_target = i;
+                break;
+              }
+              mask = mask << 1;
+            } // end for 
+            r_init_cmd_fsm    = INIT_CMD_UPDT_NLINE;
+            r_write_to_init_cmd_copies = copies & ~mask;
+            r_init_cmd_cpt    = 0;
+            m_cpt_update_mult++;
+          }
+          break;
+        }
+        /////////////////////////
+      case INIT_CMD_UPDT_NLINE:	// send the cache line index
+        {
+          if ( p_vci_ini.cmdack )  r_init_cmd_fsm = INIT_CMD_UPDT_INDEX;
+          break;
+        }
+        /////////////////////////
+      case INIT_CMD_UPDT_INDEX:	// send the first word index
+        {
+          if ( p_vci_ini.cmdack )  r_init_cmd_fsm = INIT_CMD_UPDT_DATA;
+          break;
+        }
+        ////////////////////////
+      case INIT_CMD_UPDT_DATA:	// send the data
+        {
+          if ( p_vci_ini.cmdack ) {
+            if ( r_init_cmd_cpt.read() == (r_write_to_init_cmd_count.read()-1) ) {
+              r_init_cmd_fsm = INIT_CMD_UPDT_SEL;
+            } else {
+              r_init_cmd_cpt = r_init_cmd_cpt.read() + 1;
+            }
+          }
+          break;
+        }
+    } // end switch r_init_cmd_fsm
+
+    /////////////////////////////////////////////////////////////////////
+    //		TGT_RSP FSM
+    /////////////////////////////////////////////////////////////////////
+    // The TGT_RSP fsm sends the responses on the VCI target port
+    // with a round robin priority between six requests :
+    // - r_read_to_tgt_rsp_req
+    // - r_write_to_tgt_rsp_req
+    // - r_llsc_to_tgt_rsp_req
+    // - r_cleanup_to_tgt_rsp_req
+    // - r_init_rsp_to_tgt_rsp_req
+    // - r_xram_rsp_to_tgt_rsp_req
+    // The  ordering is :  read > write > llsc > cleanup > xram > init
+    /////////////////////////////////////////////////////////////////////
+
+    switch ( r_tgt_rsp_fsm.read() ) {
+
+      ///////////////////////
+      case TGT_RSP_READ_IDLE:		// write requests have the highest priority
+        {
+          if      ( r_write_to_tgt_rsp_req    ) r_tgt_rsp_fsm = TGT_RSP_WRITE;
+          else if ( r_llsc_to_tgt_rsp_req     ) r_tgt_rsp_fsm = TGT_RSP_LLSC;
+          else if ( r_cleanup_to_tgt_rsp_req  ) r_tgt_rsp_fsm = TGT_RSP_CLEANUP;
+          else if ( r_xram_rsp_to_tgt_rsp_req ) r_tgt_rsp_fsm = TGT_RSP_XRAM_TEST;
+          else if ( r_init_rsp_to_tgt_rsp_req ) r_tgt_rsp_fsm = TGT_RSP_INIT;
+          else if ( r_read_to_tgt_rsp_req     ) r_tgt_rsp_fsm = TGT_RSP_READ_TEST;
+          break;
+        }
+        ////////////////////////
+      case TGT_RSP_WRITE_IDLE:		// llsc requests have the highest priority
+        {
+          if      ( r_llsc_to_tgt_rsp_req     ) r_tgt_rsp_fsm = TGT_RSP_LLSC;
+          else if ( r_cleanup_to_tgt_rsp_req  ) r_tgt_rsp_fsm = TGT_RSP_CLEANUP;
+          else if ( r_xram_rsp_to_tgt_rsp_req ) r_tgt_rsp_fsm = TGT_RSP_XRAM_TEST;
+          else if ( r_init_rsp_to_tgt_rsp_req ) r_tgt_rsp_fsm = TGT_RSP_INIT;
+          else if ( r_read_to_tgt_rsp_req     ) r_tgt_rsp_fsm = TGT_RSP_READ_TEST;
+          else if ( r_write_to_tgt_rsp_req    ) r_tgt_rsp_fsm = TGT_RSP_WRITE;
+          break;
+        }
+        ///////////////////////
+      case TGT_RSP_LLSC_IDLE:		// cleanup requests have the highest priority
+        {
+          if      ( r_cleanup_to_tgt_rsp_req  ) r_tgt_rsp_fsm = TGT_RSP_CLEANUP;
+          else if ( r_xram_rsp_to_tgt_rsp_req ) r_tgt_rsp_fsm = TGT_RSP_XRAM_TEST;
+          else if ( r_init_rsp_to_tgt_rsp_req ) r_tgt_rsp_fsm = TGT_RSP_INIT;
+          else if ( r_read_to_tgt_rsp_req     ) r_tgt_rsp_fsm = TGT_RSP_READ_TEST;
+          else if ( r_write_to_tgt_rsp_req    ) r_tgt_rsp_fsm = TGT_RSP_WRITE;
+          else if ( r_llsc_to_tgt_rsp_req     ) r_tgt_rsp_fsm = TGT_RSP_LLSC;
+          break;
+        }
+        //////////////////////////
+      case TGT_RSP_CLEANUP_IDLE:	// xram requests have the highest priority
+        {
+          if      ( r_xram_rsp_to_tgt_rsp_req ) r_tgt_rsp_fsm = TGT_RSP_XRAM_TEST;
+          else if ( r_init_rsp_to_tgt_rsp_req ) r_tgt_rsp_fsm = TGT_RSP_INIT;
+          else if ( r_read_to_tgt_rsp_req     ) r_tgt_rsp_fsm = TGT_RSP_READ_TEST;
+          else if ( r_write_to_tgt_rsp_req    ) r_tgt_rsp_fsm = TGT_RSP_WRITE;
+          else if ( r_llsc_to_tgt_rsp_req     ) r_tgt_rsp_fsm = TGT_RSP_LLSC;
+          else if ( r_cleanup_to_tgt_rsp_req  ) r_tgt_rsp_fsm = TGT_RSP_CLEANUP;
+          break;
+        }
+        ///////////////////////
+      case TGT_RSP_XRAM_IDLE:		// init requests have the highest priority
+        {
+          if      ( r_init_rsp_to_tgt_rsp_req ) r_tgt_rsp_fsm = TGT_RSP_INIT;
+          else if ( r_read_to_tgt_rsp_req     ) r_tgt_rsp_fsm = TGT_RSP_READ_TEST;
+          else if ( r_write_to_tgt_rsp_req    ) r_tgt_rsp_fsm = TGT_RSP_WRITE;
+          else if ( r_llsc_to_tgt_rsp_req     ) r_tgt_rsp_fsm = TGT_RSP_LLSC;
+          else if ( r_cleanup_to_tgt_rsp_req  ) r_tgt_rsp_fsm = TGT_RSP_CLEANUP;
+          else if ( r_xram_rsp_to_tgt_rsp_req ) r_tgt_rsp_fsm = TGT_RSP_XRAM_TEST;
+          break;
+        }
+        ///////////////////////
+      case TGT_RSP_INIT_IDLE:		// read requests have the highest priority
+        {
+          if      ( r_read_to_tgt_rsp_req     ) r_tgt_rsp_fsm = TGT_RSP_READ_TEST;
+          else if ( r_write_to_tgt_rsp_req    ) r_tgt_rsp_fsm = TGT_RSP_WRITE;
+          else if ( r_llsc_to_tgt_rsp_req     ) r_tgt_rsp_fsm = TGT_RSP_LLSC;
+          else if ( r_cleanup_to_tgt_rsp_req  ) r_tgt_rsp_fsm = TGT_RSP_CLEANUP;
+          else if ( r_xram_rsp_to_tgt_rsp_req ) r_tgt_rsp_fsm = TGT_RSP_XRAM_TEST;
+          else if ( r_init_rsp_to_tgt_rsp_req ) r_tgt_rsp_fsm = TGT_RSP_INIT;
+          break;
+        }
+        ///////////////////////
+      case TGT_RSP_READ_TEST:		// test if word or cache line
+        {
+          bool 		line = true;
+          size_t	index;
+          for ( size_t i=0; i< m_words ; i++ ) {
+            line = line && r_read_to_tgt_rsp_val[i];
+            if ( r_read_to_tgt_rsp_val[i] ) index = i;
+          }
+          if ( line ) {
+            r_tgt_rsp_cpt = 0;
+            r_tgt_rsp_fsm = TGT_RSP_READ_LINE;
+          } else {
+            r_tgt_rsp_cpt = index;
+            r_tgt_rsp_fsm = TGT_RSP_READ_WORD;
+          } 
+          break;
+        }
+        ///////////////////////
+      case TGT_RSP_READ_WORD:		// send one word response
+        {
+          if ( p_vci_tgt.rspack ) {
+            r_tgt_rsp_fsm = TGT_RSP_READ_IDLE;
+            r_read_to_tgt_rsp_req = false;
+          }
+          break;
+        }
+        ///////////////////////
+      case TGT_RSP_READ_LINE:		// send one complete cache line
+        {
+          if ( p_vci_tgt.rspack ) {
+            if ( r_tgt_rsp_cpt.read() == (m_words-1) ) {
+              r_tgt_rsp_fsm = TGT_RSP_READ_IDLE;
+              r_read_to_tgt_rsp_req = false;
+            } else {
+              r_tgt_rsp_cpt = r_tgt_rsp_cpt.read() + 1;
+            }
+          }
+          break;
+        }
+        ///////////////////
+      case TGT_RSP_WRITE:		// send the write acknowledge
+        {
+          if ( p_vci_tgt.rspack ) {
+            r_tgt_rsp_fsm = TGT_RSP_WRITE_IDLE;
+            r_write_to_tgt_rsp_req = false;
+          }
+          break;
+        }
+        //////////////////
+      case TGT_RSP_LLSC:		// send one atomic word response
+        {
+          if ( p_vci_tgt.rspack ) {
+            r_tgt_rsp_fsm = TGT_RSP_LLSC_IDLE;
+            r_llsc_to_tgt_rsp_req = false;
+          }
+          break;
+        }
+        /////////////////////
+      case TGT_RSP_CLEANUP:		// send the cleanup acknowledge
+        {
+          if ( p_vci_tgt.rspack ) {
+            r_tgt_rsp_fsm = TGT_RSP_CLEANUP_IDLE;
+            r_cleanup_to_tgt_rsp_req = false;
+          }
+          break;
+        }
+        ///////////////////////
+      case TGT_RSP_XRAM_TEST:		// test if word or cache line
+        {
+          bool 	line = true;
+          size_t	index;
+          for ( size_t i=0; i< m_words ; i++ ) {
+            line = line && r_xram_rsp_to_tgt_rsp_val[i];
+            if ( r_xram_rsp_to_tgt_rsp_val[i] ) index = i;
+          }
+          if ( line ) {
+            r_tgt_rsp_cpt = 0;
+            r_tgt_rsp_fsm = TGT_RSP_XRAM_LINE;
+          } else {
+            r_tgt_rsp_cpt = index;
+            r_tgt_rsp_fsm = TGT_RSP_XRAM_WORD;
+          } 
+          break;
+        }
+        ///////////////////////
+      case TGT_RSP_XRAM_WORD:		// send one word response
+        {
+          if ( p_vci_tgt.rspack ) {
+            r_tgt_rsp_fsm = TGT_RSP_XRAM_IDLE;
+            r_xram_rsp_to_tgt_rsp_req = false;
+          }
+          break;
+        }
+        ///////////////////////
+      case TGT_RSP_XRAM_LINE:		// send one complete cache line
+        {
+          if ( p_vci_tgt.rspack ) {
+            if ( r_tgt_rsp_cpt.read() == (m_words-1) ) {
+              r_tgt_rsp_fsm = TGT_RSP_XRAM_IDLE;
+              r_xram_rsp_to_tgt_rsp_req = false;
+            } else {
+              r_tgt_rsp_cpt = r_tgt_rsp_cpt.read() + 1;
+            }
+          }
+          break;
+        }
+        ///////////////////
+      case TGT_RSP_INIT:		// send the pending write acknowledge
+        {
+          if ( p_vci_tgt.rspack ) {
+            r_tgt_rsp_fsm = TGT_RSP_INIT_IDLE;
+            r_init_rsp_to_tgt_rsp_req = false;
+          }
+          break;
+        }
+    } // end switch tgt_rsp_fsm
+
+    ////////////////////////////////////////////////////////////////////////////////////
+    //		ALLOC_UPT FSM
+    ////////////////////////////////////////////////////////////////////////////////////
+    // The ALLOC_UPT FSM allocates the access to the Update/Inval Table (UPT).
+    // with a round robin priority between three FSMs : INIT_RSP > WRITE > XRAM_RSP 
+    // - The WRITE FSM initiates update transactions and sets  new entry in UPT.
+    // - The XRAM_RSP FSM initiates inval transactions and sets  new entry in UPT.
+    // - The INIT_RSP FSM complete those trasactions and erase the UPT entry.
+    // The ressource is always allocated.
+    /////////////////////////////////////////////////////////////////////////////////////
+
+    switch ( r_alloc_upt_fsm.read() ) {
+
+      ////////////////////////
+      case ALLOC_UPT_INIT_RSP:
+        if ( (r_init_rsp_fsm.read() != INIT_RSP_UPT_LOCK) && 
+            (r_init_rsp_fsm.read() != INIT_RSP_UPT_CLEAR) ) 
+        {
+          if      (r_write_fsm.read()==WRITE_UPT_LOCK)       r_alloc_upt_fsm = ALLOC_UPT_WRITE;
+          else if (r_xram_rsp_fsm.read()==XRAM_RSP_UPT_LOCK) r_alloc_upt_fsm = ALLOC_UPT_XRAM_RSP;
+        }
+        break;
+
+        /////////////////////
+      case ALLOC_UPT_WRITE:
+        if ( r_write_fsm.read() != WRITE_UPT_LOCK ) 
+        {
+          if      (r_xram_rsp_fsm.read()==XRAM_RSP_UPT_LOCK) r_alloc_upt_fsm = ALLOC_UPT_XRAM_RSP;
+          else if (r_init_rsp_fsm.read()==INIT_RSP_UPT_LOCK) r_alloc_upt_fsm = ALLOC_UPT_INIT_RSP;
+        }
+        break;
+
+        ////////////////////////
+      case ALLOC_UPT_XRAM_RSP:
+        if ( r_xram_rsp_fsm.read() != XRAM_RSP_UPT_LOCK ) 
+        { 
+          if      (r_init_rsp_fsm.read()==INIT_RSP_UPT_LOCK) r_alloc_upt_fsm = ALLOC_UPT_INIT_RSP;
+          else if (r_write_fsm.read()==WRITE_UPT_LOCK)       r_alloc_upt_fsm = ALLOC_UPT_WRITE;
+        }
+        break;
+
+    } // end switch r_alloc_upt_fsm
+
+    ////////////////////////////////////////////////////////////////////////////////////
+    //		ALLOC_DIR FSM
+    ////////////////////////////////////////////////////////////////////////////////////
+    // The ALLOC_DIR FSM allocates the access to the directory and
+    // the data cache with a round robin priority between 5 user FSMs :
+    // The cyclic ordering is READ > WRITE > LLSC > CLEANUP > XRAM_RSP
+    // The ressource is always allocated.
+    /////////////////////////////////////////////////////////////////////////////////////
+
+    switch ( r_alloc_dir_fsm.read() ) {
+
+      ////////////////////
+      case ALLOC_DIR_READ:
+        if ( ( (r_read_fsm.read() != READ_DIR_LOCK) &&
+              (r_read_fsm.read() != READ_TRT_LOCK)     )
+            ||
+            ( (r_read_fsm.read()      == READ_TRT_LOCK)  &&
+              (r_alloc_trt_fsm.read() == ALLOC_TRT_READ)    )  ) 
+        {
+          if      (r_write_fsm.read()==WRITE_DIR_LOCK)       r_alloc_dir_fsm = ALLOC_DIR_WRITE;
+          else if ((r_llsc_fsm.read()==LL_DIR_LOCK) || 
+              (r_llsc_fsm.read()==SC_DIR_LOCK))         r_alloc_dir_fsm = ALLOC_DIR_LLSC;
+          else if (r_cleanup_fsm.read()==CLEANUP_DIR_LOCK)   r_alloc_dir_fsm = ALLOC_DIR_CLEANUP;
+          else if (r_xram_rsp_fsm.read()==XRAM_RSP_DIR_LOCK) r_alloc_dir_fsm = ALLOC_DIR_XRAM_RSP;
+        }
+        break;
+
+        /////////////////////
+      case ALLOC_DIR_WRITE:
+        if ( ( (r_write_fsm.read() != WRITE_DIR_LOCK)     &&
+              (r_write_fsm.read() != WRITE_TRT_LOCK)     &&
+              (r_write_fsm.read() != WRITE_DIR_HIT_READ)      )
+            ||
+            ( (r_write_fsm.read()     == WRITE_TRT_LOCK) &&
+              (r_alloc_trt_fsm.read() == ALLOC_TRT_WRITE)   )   )
+        {
+          if      ((r_llsc_fsm.read()==LL_DIR_LOCK) || 
+              (r_llsc_fsm.read()==SC_DIR_LOCK))         r_alloc_dir_fsm = ALLOC_DIR_LLSC;
+          else if (r_cleanup_fsm.read()==CLEANUP_DIR_LOCK)   r_alloc_dir_fsm = ALLOC_DIR_CLEANUP;
+          else if (r_xram_rsp_fsm.read()==XRAM_RSP_DIR_LOCK) r_alloc_dir_fsm = ALLOC_DIR_XRAM_RSP;
+          else if (r_read_fsm.read()==READ_DIR_LOCK) 	     r_alloc_dir_fsm = ALLOC_DIR_READ;
+        }
+        break;
+
+        ////////////////////
+      case ALLOC_DIR_LLSC:
+        if ( ( (r_llsc_fsm.read() != LL_DIR_LOCK)    &&
+              (r_llsc_fsm.read() != LL_DIR_HIT )    &&
+              (r_llsc_fsm.read() != SC_DIR_LOCK)    &&
+              (r_llsc_fsm.read() != SC_DIR_HIT )    &&
+              (r_llsc_fsm.read() != LLSC_TRT_LOCK )    )
+            || 
+            ( (r_llsc_fsm.read()      == LLSC_TRT_LOCK ) &&
+              (r_alloc_trt_fsm.read() == ALLOC_TRT_LLSC)    ) )
+        {
+          if      (r_cleanup_fsm.read()==CLEANUP_DIR_LOCK)   r_alloc_dir_fsm = ALLOC_DIR_CLEANUP;
+          else if (r_xram_rsp_fsm.read()==XRAM_RSP_DIR_LOCK) r_alloc_dir_fsm = ALLOC_DIR_XRAM_RSP;
+          else if (r_read_fsm.read()==READ_DIR_LOCK) 	     r_alloc_dir_fsm = ALLOC_DIR_READ;
+          else if (r_write_fsm.read()==WRITE_DIR_LOCK)       r_alloc_dir_fsm = ALLOC_DIR_WRITE;
+        }
+        break;
+
+        ///////////////////////
+      case ALLOC_DIR_CLEANUP:
+        if ( (r_cleanup_fsm.read() != CLEANUP_DIR_LOCK) )
+        {
+          if      (r_xram_rsp_fsm.read()==XRAM_RSP_DIR_LOCK) r_alloc_dir_fsm = ALLOC_DIR_XRAM_RSP;
+          else if (r_read_fsm.read()==READ_DIR_LOCK) 	     r_alloc_dir_fsm = ALLOC_DIR_READ;
+          else if (r_write_fsm.read()==WRITE_DIR_LOCK)       r_alloc_dir_fsm = ALLOC_DIR_WRITE;
+          else if ((r_llsc_fsm.read()==LL_DIR_LOCK) || 
+              (r_llsc_fsm.read()==SC_DIR_LOCK))         r_alloc_dir_fsm = ALLOC_DIR_LLSC;
+        }
+        break;
+        ////////////////////////
+      case ALLOC_DIR_XRAM_RSP:
+        if ( (r_xram_rsp_fsm.read() != XRAM_RSP_DIR_LOCK)  &&
+            (r_xram_rsp_fsm.read() != XRAM_RSP_TRT_COPY) ) 
+        {
+          if      (r_read_fsm.read()==READ_DIR_LOCK) 	     r_alloc_dir_fsm = ALLOC_DIR_READ;
+          else if (r_write_fsm.read()==WRITE_DIR_LOCK)     r_alloc_dir_fsm = ALLOC_DIR_WRITE;
+          else if ((r_llsc_fsm.read()==LL_DIR_LOCK) || 
+              (r_llsc_fsm.read()==SC_DIR_LOCK))       r_alloc_dir_fsm = ALLOC_DIR_LLSC;
+          else if (r_cleanup_fsm.read()==CLEANUP_DIR_LOCK) r_alloc_dir_fsm = ALLOC_DIR_CLEANUP;
+        }
+        break;
+
+    } // end switch alloc_dir_fsm
+
+    ////////////////////////////////////////////////////////////////////////////////////
+    //		ALLOC_TRT FSM
+    ////////////////////////////////////////////////////////////////////////////////////
+    // The ALLOC_TRT fsm allocates the access to the Transaction Table (write buffer)
+    // with a round robin priority between 4 user FSMs :
+    // The cyclic priority is READ > WRITE > LLSC > XRAM_RSP
+    // The ressource is always allocated.
+    ///////////////////////////////////////////////////////////////////////////////////
+
+    switch (r_alloc_trt_fsm) {
+
+      ////////////////////
+      case ALLOC_TRT_READ:
+        if ( r_read_fsm.read() != READ_TRT_LOCK ) 
+        {
+          if      (r_write_fsm.read()==WRITE_TRT_LOCK)            r_alloc_trt_fsm = ALLOC_TRT_WRITE;
+          else if (r_llsc_fsm.read()==LLSC_TRT_LOCK)              r_alloc_trt_fsm = ALLOC_TRT_LLSC;
+          else if (r_xram_rsp_fsm.read()==XRAM_RSP_TRT_COPY)      r_alloc_trt_fsm = ALLOC_TRT_XRAM_RSP;
+          else if ((r_ixr_rsp_fsm.read()==IXR_RSP_TRT_ERASE) ||
+              (r_ixr_rsp_fsm.read()==IXR_RSP_TRT_READ))       r_alloc_trt_fsm = ALLOC_TRT_IXR_RSP;
+        }
+        break;
+        /////////////////////
+      case ALLOC_TRT_WRITE:
+        if ( r_write_fsm.read() != WRITE_TRT_LOCK ) 
+        {
+          if      (r_llsc_fsm.read()==LLSC_TRT_LOCK) 	          r_alloc_trt_fsm = ALLOC_TRT_LLSC;
+          else if (r_xram_rsp_fsm.read()==XRAM_RSP_TRT_COPY)      r_alloc_trt_fsm = ALLOC_TRT_XRAM_RSP;
+          else if ((r_ixr_rsp_fsm.read()==IXR_RSP_TRT_ERASE) ||
+              (r_ixr_rsp_fsm.read()==IXR_RSP_TRT_READ))       r_alloc_trt_fsm = ALLOC_TRT_IXR_RSP;
+          else if (r_read_fsm.read()==READ_TRT_LOCK) 	          r_alloc_trt_fsm = ALLOC_TRT_READ;
+        }
+        break;
+        ////////////////////
+      case ALLOC_TRT_LLSC:
+        if ( r_llsc_fsm.read() != LLSC_TRT_LOCK )
+        { 
+          if      (r_xram_rsp_fsm.read()==XRAM_RSP_TRT_COPY)      r_alloc_trt_fsm = ALLOC_TRT_XRAM_RSP;
+          else if ((r_ixr_rsp_fsm.read()==IXR_RSP_TRT_ERASE) ||
+              (r_ixr_rsp_fsm.read()==IXR_RSP_TRT_READ))       r_alloc_trt_fsm = ALLOC_TRT_IXR_RSP;
+          else if (r_read_fsm.read()==READ_TRT_LOCK) 	          r_alloc_trt_fsm = ALLOC_TRT_READ;
+          else if (r_write_fsm.read()==WRITE_TRT_LOCK)            r_alloc_trt_fsm = ALLOC_TRT_WRITE;
+        }
+        break;
+        ////////////////////////
+      case ALLOC_TRT_XRAM_RSP:
+        if ( (r_xram_rsp_fsm.read() != XRAM_RSP_TRT_COPY)  &&
+            (r_xram_rsp_fsm.read() != XRAM_RSP_DIR_UPDT) ) {
+          if      ((r_ixr_rsp_fsm.read()==IXR_RSP_TRT_ERASE) ||
+              (r_ixr_rsp_fsm.read()==IXR_RSP_TRT_READ))       r_alloc_trt_fsm = ALLOC_TRT_IXR_RSP;
+          else if (r_read_fsm.read()==READ_TRT_LOCK) 	          r_alloc_trt_fsm = ALLOC_TRT_READ;
+          else if (r_write_fsm.read()==WRITE_TRT_LOCK)            r_alloc_trt_fsm = ALLOC_TRT_WRITE;
+          else if (r_llsc_fsm.read()==LLSC_TRT_LOCK) 	          r_alloc_trt_fsm = ALLOC_TRT_LLSC;
+        }
+        break;
+        ////////////////////////
+      case ALLOC_TRT_IXR_RSP:
+        if ( (r_ixr_rsp_fsm.read() != IXR_RSP_TRT_ERASE) &&
+            (r_ixr_rsp_fsm.read() != IXR_RSP_TRT_READ) ) {
+          if      (r_read_fsm.read()==READ_TRT_LOCK) 	          r_alloc_trt_fsm = ALLOC_TRT_READ;
+          else if (r_write_fsm.read()==WRITE_TRT_LOCK)            r_alloc_trt_fsm = ALLOC_TRT_WRITE;
+          else if (r_llsc_fsm.read()==LLSC_TRT_LOCK) 	          r_alloc_trt_fsm = ALLOC_TRT_LLSC;
+          else if (r_xram_rsp_fsm.read()==XRAM_RSP_TRT_COPY)      r_alloc_trt_fsm = ALLOC_TRT_XRAM_RSP;
+        }
+        break;
+
+    } // end switch alloc_trt_fsm
+
+    ////////////////////////////////////////////////////////////////////////////////////
+    //		TGT_CMD to READ FIFO
+    ////////////////////////////////////////////////////////////////////////////////////
+
+    if ( cmd_read_fifo_put ) {
+      if ( cmd_read_fifo_get ) {
+        m_cmd_read_addr_fifo.put_and_get(p_vci_tgt.address.read());
+        m_cmd_read_word_fifo.put_and_get((p_vci_tgt.plen.read() == 4));
+        m_cmd_read_srcid_fifo.put_and_get(p_vci_tgt.srcid.read());
+        m_cmd_read_trdid_fifo.put_and_get(p_vci_tgt.trdid.read());
+        m_cmd_read_pktid_fifo.put_and_get(p_vci_tgt.pktid.read());
+      } else {
+        m_cmd_read_addr_fifo.simple_put(p_vci_tgt.address.read());
+        m_cmd_read_word_fifo.simple_put((p_vci_tgt.plen.read() == 4));
+        m_cmd_read_srcid_fifo.simple_put(p_vci_tgt.srcid.read());
+        m_cmd_read_trdid_fifo.simple_put(p_vci_tgt.trdid.read());
+        m_cmd_read_pktid_fifo.simple_put(p_vci_tgt.pktid.read());
+      }
+    } else {
+      if ( cmd_read_fifo_get ) {
+        m_cmd_read_addr_fifo.simple_get();
+        m_cmd_read_word_fifo.simple_get();
+        m_cmd_read_srcid_fifo.simple_get();
+        m_cmd_read_trdid_fifo.simple_get();
+        m_cmd_read_pktid_fifo.simple_get();
+      }
+    }
+    /////////////////////////////////////////////////////////////////////
+    //		TGT_CMD to WRITE FIFO
+    /////////////////////////////////////////////////////////////////////
+
+    if ( cmd_write_fifo_put ) {
+      if ( cmd_write_fifo_get ) {
+        m_cmd_write_addr_fifo.put_and_get(p_vci_tgt.address.read());
+        m_cmd_write_eop_fifo.put_and_get(p_vci_tgt.eop.read());
+        m_cmd_write_srcid_fifo.put_and_get(p_vci_tgt.srcid.read());
+        m_cmd_write_trdid_fifo.put_and_get(p_vci_tgt.trdid.read());
+        m_cmd_write_pktid_fifo.put_and_get(p_vci_tgt.pktid.read());
+        m_cmd_write_data_fifo.put_and_get(p_vci_tgt.wdata.read());
+        m_cmd_write_be_fifo.put_and_get(p_vci_tgt.be.read());
+      } else {
+        m_cmd_write_addr_fifo.simple_put(p_vci_tgt.address.read());
+        m_cmd_write_eop_fifo.simple_put(p_vci_tgt.eop.read());
+        m_cmd_write_srcid_fifo.simple_put(p_vci_tgt.srcid.read());
+        m_cmd_write_trdid_fifo.simple_put(p_vci_tgt.trdid.read());
+        m_cmd_write_pktid_fifo.simple_put(p_vci_tgt.pktid.read());
+        m_cmd_write_data_fifo.simple_put(p_vci_tgt.wdata.read());
+        m_cmd_write_be_fifo.simple_put(p_vci_tgt.be.read());
+      }
+    } else {
+      if ( cmd_write_fifo_get ) {
+        m_cmd_write_addr_fifo.simple_get();
+        m_cmd_write_eop_fifo.simple_get();
+        m_cmd_write_srcid_fifo.simple_get();
+        m_cmd_write_trdid_fifo.simple_get();
+        m_cmd_write_pktid_fifo.simple_get();
+        m_cmd_write_data_fifo.simple_get();
+        m_cmd_write_be_fifo.simple_get();
+      }
+    }
+    ////////////////////////////////////////////////////////////////////////////////////
+    //		TGT_CMD to LLSC FIFO
+    ////////////////////////////////////////////////////////////////////////////////////
+
+    if ( cmd_llsc_fifo_put ) {
+      if ( cmd_llsc_fifo_get ) {
+        m_cmd_llsc_addr_fifo.put_and_get(p_vci_tgt.address.read());
+        m_cmd_llsc_sc_fifo.put_and_get(p_vci_tgt.cmd.read() == vci_param::CMD_STORE_COND); 
+        m_cmd_llsc_srcid_fifo.put_and_get(p_vci_tgt.srcid.read());
+        m_cmd_llsc_trdid_fifo.put_and_get(p_vci_tgt.trdid.read());
+        m_cmd_llsc_pktid_fifo.put_and_get(p_vci_tgt.pktid.read());
+        m_cmd_llsc_wdata_fifo.put_and_get(p_vci_tgt.wdata.read());
+      } else {
+        m_cmd_llsc_addr_fifo.simple_put(p_vci_tgt.address.read());
+        m_cmd_llsc_sc_fifo.simple_put(p_vci_tgt.cmd.read() == vci_param::CMD_STORE_COND); 
+        m_cmd_llsc_srcid_fifo.simple_put(p_vci_tgt.srcid.read());
+        m_cmd_llsc_trdid_fifo.simple_put(p_vci_tgt.trdid.read());
+        m_cmd_llsc_pktid_fifo.simple_put(p_vci_tgt.pktid.read());
+        m_cmd_llsc_wdata_fifo.simple_put(p_vci_tgt.wdata.read());
+      }
+    } else {
+      if ( cmd_llsc_fifo_get ) {
+        m_cmd_llsc_addr_fifo.simple_get();
+        m_cmd_llsc_sc_fifo.simple_get();
+        m_cmd_llsc_srcid_fifo.simple_get();
+        m_cmd_llsc_trdid_fifo.simple_get();
+        m_cmd_llsc_pktid_fifo.simple_get();
+        m_cmd_llsc_wdata_fifo.simple_get();
+      }
+    }
+
+    ////////////////////////////////////////////////////////////////////////////////////
+    //		TGT_CMD to CLEANUP FIFO
+    ////////////////////////////////////////////////////////////////////////////////////
+
+    if ( cmd_cleanup_fifo_put ) {
+      if ( cmd_cleanup_fifo_get ) {
+        m_cmd_cleanup_srcid_fifo.put_and_get(p_vci_tgt.srcid.read());
+        m_cmd_cleanup_trdid_fifo.put_and_get(p_vci_tgt.trdid.read());
+        m_cmd_cleanup_pktid_fifo.put_and_get(p_vci_tgt.pktid.read());
+        m_cmd_cleanup_nline_fifo.put_and_get(p_vci_tgt.wdata.read());
+      } else {
+        m_cmd_cleanup_srcid_fifo.simple_put(p_vci_tgt.srcid.read());
+        m_cmd_cleanup_trdid_fifo.simple_put(p_vci_tgt.trdid.read());
+        m_cmd_cleanup_pktid_fifo.simple_put(p_vci_tgt.pktid.read());
+        m_cmd_cleanup_nline_fifo.simple_put(p_vci_tgt.wdata.read());
+      }
+    } else {
+      if ( cmd_cleanup_fifo_get ) {
+        m_cmd_cleanup_srcid_fifo.simple_get();
+        m_cmd_cleanup_trdid_fifo.simple_get();
+        m_cmd_cleanup_pktid_fifo.simple_get();
+        m_cmd_cleanup_nline_fifo.simple_get();
+      }
+    }
+
+    m_cpt_cycles++;
+
+  } // end transition()
+
+  /////////////////////////////
+  tmpl(void)::genMoore()
+    /////////////////////////////
+  {
+    ////////////////////////////////////////////////////////////
+    // Command signals on the p_vci_ixr port
+    ////////////////////////////////////////////////////////////
+
+
+    p_vci_ixr.be      = 0xF;
+    p_vci_ixr.pktid   = 0;
+    p_vci_ixr.srcid   = m_srcid_ixr;
+    p_vci_ixr.cons    = false;
+    p_vci_ixr.wrap    = false;
+    p_vci_ixr.contig  = true;
+    p_vci_ixr.clen    = 0;
+    p_vci_ixr.cfixed  = false;
+
+    if ( r_xram_cmd_fsm.read() == XRAM_CMD_READ_NLINE ) {
+      p_vci_ixr.cmd     = vci_param::CMD_READ;
+      p_vci_ixr.cmdval  = true;
+      p_vci_ixr.address = (r_read_to_xram_cmd_nline.read()*m_words*4);
+      p_vci_ixr.plen    = m_words*4;
+      p_vci_ixr.wdata   = 0x00000000;
+      p_vci_ixr.trdid   = r_read_to_xram_cmd_trdid.read();
+      p_vci_ixr.eop     = true;
+    } 
+    else if ( r_xram_cmd_fsm.read() == XRAM_CMD_LLSC_NLINE ) {
+      p_vci_ixr.cmd     = vci_param::CMD_READ;
+      p_vci_ixr.cmdval  = true;
+      p_vci_ixr.address = (r_llsc_to_xram_cmd_nline.read()*m_words*4);
+      p_vci_ixr.plen    = m_words*4;
+      p_vci_ixr.wdata   = 0x00000000;
+      p_vci_ixr.trdid   = r_llsc_to_xram_cmd_trdid.read();
+      p_vci_ixr.eop     = true;
+    } 
+    else if ( r_xram_cmd_fsm.read() == XRAM_CMD_WRITE_NLINE ) {
+      p_vci_ixr.cmd     = vci_param::CMD_READ;
+      p_vci_ixr.cmdval  = true;
+      p_vci_ixr.address = (r_write_to_xram_cmd_nline.read()*m_words*4);
+      p_vci_ixr.plen    = m_words*4;
+      p_vci_ixr.wdata   = 0x00000000;
+      p_vci_ixr.trdid   = r_write_to_xram_cmd_trdid.read();
+      p_vci_ixr.eop     = true;
+    } 
+    else if ( r_xram_cmd_fsm.read() == XRAM_CMD_XRAM_DATA ) {
+      p_vci_ixr.cmd     = vci_param::CMD_WRITE;
+      p_vci_ixr.cmdval  = true;
+      p_vci_ixr.address = ((r_xram_rsp_to_xram_cmd_nline.read()*m_words+r_xram_cmd_cpt.read())*4);
+      p_vci_ixr.plen    = m_words*4;
+      p_vci_ixr.wdata   = r_xram_rsp_to_xram_cmd_data[r_xram_cmd_cpt.read()].read();
+      p_vci_ixr.trdid   = r_xram_rsp_to_xram_cmd_trdid.read();
+      p_vci_ixr.eop     = (r_xram_cmd_cpt == (m_words-1));
+    } else {
+      p_vci_ixr.cmdval  = false;
+      p_vci_ixr.address = 0;
+      p_vci_ixr.plen    = 0;
+      p_vci_ixr.wdata   = 0;
+      p_vci_ixr.trdid   = 0;
+      p_vci_ixr.eop	  = false;
+    }
+
+    ////////////////////////////////////////////////////
+    // Response signals on the p_vci_ixr port
+    ////////////////////////////////////////////////////
+
+    if ( ((r_alloc_trt_fsm.read() == ALLOC_TRT_IXR_RSP) &&
+          (r_ixr_rsp_fsm.read() == IXR_RSP_TRT_READ)) || 
+        (r_ixr_rsp_fsm.read() == IXR_RSP_ACK) )           p_vci_ixr.rspack = true;
+    else                                                    p_vci_ixr.rspack = false;
+
+    ////////////////////////////////////////////////////
+    // Command signals on the p_vci_tgt port
+    ////////////////////////////////////////////////////
+
+    switch ((tgt_cmd_fsm_state_e)r_tgt_cmd_fsm.read()) {
+      case TGT_CMD_IDLE:
+        p_vci_tgt.cmdack  = false;
+        break;
+      case TGT_CMD_READ:
+        p_vci_tgt.cmdack  = m_cmd_read_addr_fifo.wok();
+        break;
+      case TGT_CMD_READ_EOP:
+        p_vci_tgt.cmdack  = true;
+        break;
+      case TGT_CMD_WRITE:
+        p_vci_tgt.cmdack  = m_cmd_write_addr_fifo.wok();
+        break;
+      case TGT_CMD_ATOMIC:
+        p_vci_tgt.cmdack  = m_cmd_llsc_addr_fifo.wok();
+        break;
+      case TGT_CMD_CLEANUP:
+        p_vci_tgt.cmdack  = m_cmd_cleanup_nline_fifo.wok();
+        break;
+      default:
+        p_vci_tgt.cmdack = false;
+        break;
+    }
+
+    ////////////////////////////////////////////////////
+    // Response signals on the p_vci_tgt port
+    ////////////////////////////////////////////////////
+    switch ( r_tgt_rsp_fsm.read() ) {
+
+      case TGT_RSP_READ_IDLE:
+      case TGT_RSP_WRITE_IDLE:
+      case TGT_RSP_LLSC_IDLE:
+      case TGT_RSP_CLEANUP_IDLE:
+      case TGT_RSP_XRAM_IDLE:
+      case TGT_RSP_INIT_IDLE:
+      case TGT_RSP_READ_TEST:
+      case TGT_RSP_XRAM_TEST:
+
+        p_vci_tgt.rspval  = false;
+        p_vci_tgt.rsrcid  = 0;
+        p_vci_tgt.rdata   = 0;
+        p_vci_tgt.rpktid  = 0;
+        p_vci_tgt.rtrdid  = 0;
+        p_vci_tgt.rerror  = 0;
+        p_vci_tgt.reop    = false;	
+        break;
+      case TGT_RSP_READ_LINE:
+        p_vci_tgt.rspval   = true;
+        p_vci_tgt.rdata    = r_read_to_tgt_rsp_data[r_tgt_rsp_cpt.read()].read();
+        p_vci_tgt.rsrcid   = r_read_to_tgt_rsp_srcid.read();
+        p_vci_tgt.rtrdid   = r_read_to_tgt_rsp_trdid.read();
+        p_vci_tgt.rpktid   = r_read_to_tgt_rsp_pktid.read();
+        p_vci_tgt.rerror   = 0;
+        p_vci_tgt.reop     = (r_tgt_rsp_cpt.read()==(m_words-1));
+        break;
+      case TGT_RSP_READ_WORD:
+        p_vci_tgt.rspval   = true;
+        p_vci_tgt.rdata    = r_read_to_tgt_rsp_data[r_tgt_rsp_cpt.read()].read();
+        p_vci_tgt.rsrcid   = r_read_to_tgt_rsp_srcid.read();
+        p_vci_tgt.rtrdid   = r_read_to_tgt_rsp_trdid.read();
+        p_vci_tgt.rpktid   = r_read_to_tgt_rsp_pktid.read();
+        p_vci_tgt.rerror   = 0;
+        p_vci_tgt.reop     = true;	
+        break;
+      case TGT_RSP_WRITE:
+        p_vci_tgt.rspval   = true;
+        p_vci_tgt.rdata    = 0;
+        p_vci_tgt.rsrcid   = r_write_to_tgt_rsp_srcid.read();
+        p_vci_tgt.rtrdid   = r_write_to_tgt_rsp_trdid.read();
+        p_vci_tgt.rpktid   = r_write_to_tgt_rsp_pktid.read();
+        p_vci_tgt.rerror   = 0;
+        p_vci_tgt.reop     = true;
+        break;
+      case TGT_RSP_CLEANUP:
+        p_vci_tgt.rspval   = true;
+        p_vci_tgt.rdata    = 0;
+        p_vci_tgt.rsrcid   = r_cleanup_to_tgt_rsp_srcid.read();
+        p_vci_tgt.rtrdid   = r_cleanup_to_tgt_rsp_trdid.read();
+        p_vci_tgt.rpktid   = r_cleanup_to_tgt_rsp_pktid.read();
+        p_vci_tgt.rerror   = 0;
+        p_vci_tgt.reop     = true;
+        break;
+      case TGT_RSP_LLSC:
+        p_vci_tgt.rspval   = true;
+        p_vci_tgt.rdata    = r_llsc_to_tgt_rsp_data.read();
+        p_vci_tgt.rsrcid   = r_llsc_to_tgt_rsp_srcid.read();
+        p_vci_tgt.rtrdid   = r_llsc_to_tgt_rsp_trdid.read();
+        p_vci_tgt.rpktid   = r_llsc_to_tgt_rsp_pktid.read();
+        p_vci_tgt.rerror   = 0;
+        p_vci_tgt.reop     = true;
+        break;
+      case TGT_RSP_XRAM_LINE:
+        p_vci_tgt.rspval   = true;
+        p_vci_tgt.rdata    = r_xram_rsp_to_tgt_rsp_data[r_tgt_rsp_cpt.read()].read();
+        p_vci_tgt.rsrcid   = r_xram_rsp_to_tgt_rsp_srcid.read();
+        p_vci_tgt.rtrdid   = r_xram_rsp_to_tgt_rsp_trdid.read();
+        p_vci_tgt.rpktid   = r_xram_rsp_to_tgt_rsp_pktid.read();
+        p_vci_tgt.rerror   = 0;
+        p_vci_tgt.reop     = (r_tgt_rsp_cpt.read()==(m_words-1));
+        break;
+      case TGT_RSP_XRAM_WORD:
+        p_vci_tgt.rspval   = true;
+        p_vci_tgt.rdata    = r_xram_rsp_to_tgt_rsp_data[r_tgt_rsp_cpt.read()].read();
+        p_vci_tgt.rsrcid   = r_xram_rsp_to_tgt_rsp_srcid.read();
+        p_vci_tgt.rtrdid   = r_xram_rsp_to_tgt_rsp_trdid.read();
+        p_vci_tgt.rpktid   = r_xram_rsp_to_tgt_rsp_pktid.read();
+        p_vci_tgt.rerror   = 0;
+        p_vci_tgt.reop     = true;
+        break;
+      case TGT_RSP_INIT:
+        p_vci_tgt.rspval   = true;
+        p_vci_tgt.rdata    = 0;
+        p_vci_tgt.rsrcid   = r_init_rsp_to_tgt_rsp_srcid.read();
+        p_vci_tgt.rtrdid   = r_init_rsp_to_tgt_rsp_trdid.read();
+        p_vci_tgt.rpktid   = r_init_rsp_to_tgt_rsp_pktid.read();
+        p_vci_tgt.rerror   = 0;
+        p_vci_tgt.reop     = true;	
+        break;
+    } // end switch r_tgt_rsp_fsm
+
+    ///////////////////////////////////////////////////
+    // Command signals on the p_vci_ini port
+    ///////////////////////////////////////////////////
+
+    p_vci_ini.cmd     = vci_param::CMD_WRITE;
+    p_vci_ini.srcid   = m_srcid_ini;
+    p_vci_ini.pktid   = 0;
+    p_vci_ini.cons    = true;
+    p_vci_ini.wrap    = false;
+    p_vci_ini.contig  = false;
+    p_vci_ini.clen    = 0;
+    p_vci_ini.cfixed  = false;
+
+    switch ( r_init_cmd_fsm.read() ) {
+
+      case INIT_CMD_UPDT_IDLE:
+      case INIT_CMD_INVAL_IDLE:
+      case INIT_CMD_UPDT_SEL:
+      case INIT_CMD_INVAL_SEL:
+        p_vci_ini.cmdval = false;
+        p_vci_ini.address = 0;
+        p_vci_ini.wdata   = 0;
+        p_vci_ini.be      = 0;
+        p_vci_ini.plen    = 0;
+        p_vci_ini.trdid   = 0;
+        p_vci_ini.eop     = false;
+        break;
+      case INIT_CMD_INVAL_NLINE:
+        p_vci_ini.cmdval  = true;
+        p_vci_ini.address = m_coherence_table[r_init_cmd_target.read()];
+        p_vci_ini.wdata   = r_xram_rsp_to_init_cmd_nline.read();
+        p_vci_ini.be      = 0xF;
+        p_vci_ini.plen    = 4;
+        p_vci_ini.trdid   = r_xram_rsp_to_init_cmd_trdid.read();
+        p_vci_ini.eop     = true;
+        break;
+      case INIT_CMD_UPDT_NLINE:
+        p_vci_ini.cmdval  = true;
+        p_vci_ini.address = m_coherence_table[r_init_cmd_target.read()] + 4;
+        p_vci_ini.wdata   = r_write_to_init_cmd_nline.read();
+        p_vci_ini.be      = 0xF;
+        p_vci_ini.plen    = 4 * (r_write_to_init_cmd_count.read() + 2);
+        p_vci_ini.trdid   = r_write_to_init_cmd_trdid.read();
+        p_vci_ini.eop     = false;
+        break;
+      case INIT_CMD_UPDT_INDEX:
+        p_vci_ini.cmdval  = true;
+        p_vci_ini.address = m_coherence_table[r_init_cmd_target.read()] + 4;
+        p_vci_ini.wdata   = r_write_to_init_cmd_index.read();
+        p_vci_ini.be      = 0xF;
+        p_vci_ini.plen    = 4 * (r_write_to_init_cmd_count.read() + 2);
+        p_vci_ini.trdid   = r_write_to_init_cmd_trdid.read();
+        p_vci_ini.eop     = false;
+        break;
+      case INIT_CMD_UPDT_DATA:
+        p_vci_ini.cmdval  = true;
+        p_vci_ini.address = m_coherence_table[r_init_cmd_target.read()] + 4;
+        p_vci_ini.wdata   = r_write_to_init_cmd_data[r_init_cmd_cpt.read() +
+          r_write_to_init_cmd_index.read()].read();
+        if(r_write_to_init_cmd_we[r_init_cmd_cpt.read() +
+            r_write_to_init_cmd_index.read()].read())  
+          p_vci_ini.be      = 0xF;
+        else			p_vci_ini.be      = 0x0;
+        p_vci_ini.plen    = 4 * (r_write_to_init_cmd_count.read() + 2);
+        p_vci_ini.trdid   = r_write_to_init_cmd_trdid.read();
+        p_vci_ini.eop     = ( r_init_cmd_cpt.read() == (r_write_to_init_cmd_count.read()-1) );
+        break;
+    } // end switch r_init_cmd_fsm
+
+    //////////////////////////////////////////////////////
+    // Response signals on the p_vci_ini port
+    //////////////////////////////////////////////////////
+
+    if ( r_init_rsp_fsm.read() == INIT_RSP_IDLE ) p_vci_ini.rspack  = true;
+    else                                          p_vci_ini.rspack  = false;
+
+  } // end genMoore()
+
+}} // end name space
Index: branches/v4/modules/vci_mem_cache_v1/caba/metadata/vci_mem_cache_v1.sd
===================================================================
--- branches/v4/modules/vci_mem_cache_v1/caba/metadata/vci_mem_cache_v1.sd	(revision 371)
+++ branches/v4/modules/vci_mem_cache_v1/caba/metadata/vci_mem_cache_v1.sd	(revision 371)
@@ -0,0 +1,47 @@
+
+# -*- python -*-
+
+__id__ = "$Id$"
+__version__ = "$Revision$"
+
+Module('caba:vci_mem_cache_v1',
+       classname = 'soclib::caba::VciMemCacheV1',
+       tmpl_parameters = [parameter.Module('vci_param', default = 'caba:vci_param'),],
+       header_files = ['../source/include/vci_mem_cache_v1.h',
+                       '../source/include/xram_transaction_v1.h',
+                       '../source/include/mem_cache_directory_v1.h',
+                       '../source/include/atomic_tab_v1.h',
+                       '../source/include/update_tab_v1.h',],
+       implementation_files = ['../source/src/vci_mem_cache_v1.cpp',],
+       uses = [Uses('caba:base_module'),
+               Uses('common:loader'),
+               Uses('common:mapping_table'),
+               Uses('caba:generic_fifo'),
+               ],
+       ports = [Port('caba:vci_target', 'p_vci_tgt'),
+		Port('caba:vci_target','p_vci_tgt_cleanup'),
+		Port('caba:vci_initiator','p_vci_ini'),
+		Port('caba:vci_initiator','p_vci_ixr'),
+                Port('caba:bit_in', 'p_resetn', auto = 'resetn'),
+                Port('caba:clock_in', 'p_clk', auto = 'clock'),],
+       instance_parameters = [
+		parameter.Module('mtp'),
+		parameter.Module('mtc'),
+		parameter.Module('mtx'),
+		parameter.IntTab('vci_ixr_index'),
+		parameter.IntTab('vci_ini_index'),
+		parameter.IntTab('vci_tgt_index'),
+		parameter.IntTab('vci_tgt_index_cleanup'),
+       		parameter.Int('nways'),
+		parameter.Int('nsets'),
+		parameter.Int('nwords'),
+		],
+       extensions = [
+          'dsx:get_ident='
+          'vci_ini_index:p_vci_ini:mtc,'
+          'vci_tgt_index_cleanup:p_vci_tgt_cleanup:mtc,'
+          'vci_tgt_index:p_vci_tgt:mtp,'
+          'vci_ixr_index:p_vci_ixr:mtx',
+          'dsx:addressable=vci_tgt_index,vci_tgt_index_cleanup',
+       ],
+)
Index: branches/v4/modules/vci_mem_cache_v1/caba/source/include/atomic_tab_v1.h
===================================================================
--- branches/v4/modules/vci_mem_cache_v1/caba/source/include/atomic_tab_v1.h	(revision 371)
+++ branches/v4/modules/vci_mem_cache_v1/caba/source/include/atomic_tab_v1.h	(revision 371)
@@ -0,0 +1,121 @@
+#ifndef ATOMIC_TAB_V1_H_
+#define ATOMIC_TAB_V1_H_
+
+#include <inttypes.h>
+#include <systemc>
+#include <cassert>
+#include "arithmetics.h"
+
+
+
+////////////////////////////////////////////////////////////////////////
+////////////////////////////////////////////////////////////////////////
+/*                  The atomic access tab                             */
+////////////////////////////////////////////////////////////////////////
+////////////////////////////////////////////////////////////////////////
+
+class AtomicTab{
+    typedef uint32_t size_t;
+    typedef sc_dt::sc_uint<40> addr_t;
+
+private:
+    size_t size_tab;                            // The size of the tab
+    std::vector<addr_t> addr_tab;               // Address entries
+    std::vector<bool>   valid_tab;              // Valid entries
+
+public:
+
+    AtomicTab()
+	: addr_tab(0),
+	  valid_tab(0)
+	{
+    	size_tab=0;
+    }
+
+    AtomicTab(size_t size_tab_i)
+	: addr_tab(size_tab_i),
+	  valid_tab(size_tab_i)
+	{
+	    size_tab=size_tab_i;
+    }
+
+
+    /////////////////////////////////////////////////////////////////////
+    /* The size() function returns the size of the tab */
+    /////////////////////////////////////////////////////////////////////
+    const size_t size(){
+	    return size_tab;
+    }
+
+
+    /////////////////////////////////////////////////////////////////////
+    /* The init() function initializes the transaction tab entries */
+    /////////////////////////////////////////////////////////////////////
+    void init(){
+    	for ( size_t i=0; i<size_tab; i++) {
+		    addr_tab[i]=0;
+		    valid_tab[i]=false;
+    	}
+    }
+
+
+    /////////////////////////////////////////////////////////////////////
+    /* The set() function sets an entry 
+       Arguments :
+       - id : the id of the initiator (index of the entry)
+       - addr : the address of the lock
+     */
+    /////////////////////////////////////////////////////////////////////
+    void set(const size_t id, const addr_t addr){
+	    assert( (id<size_tab) && "Atomic Tab Error : bad entry");
+	    addr_tab[id]=addr;
+	    valid_tab[id]=true;
+	    return;
+    }
+
+
+    /////////////////////////////////////////////////////////////////////
+    /* The isatomic() function tests if the SC request corresponds to an entry
+       Arguments :
+       - id : the id of the initiator (index of the entry)
+       - addr : the address of the lock
+
+       This function return true if the request corresponds
+     */
+    /////////////////////////////////////////////////////////////////////
+    bool isatomic(const size_t id, const addr_t addr){
+	    assert( (id<size_tab) && "Atomic Tab Error : bad entry");
+	    bool test=valid_tab[id];
+	    test=test && (addr == addr_tab[id]);
+	    return test;
+    }
+
+
+    /////////////////////////////////////////////////////////////////////
+    /* The reset() function resets all the entries for this lock
+       Arguments :
+       - addr : the address of the lock
+     */
+    /////////////////////////////////////////////////////////////////////
+    void reset(const addr_t addr){
+	    for(size_t i=0 ; i<size_tab ; i++){
+		    if(addr == addr_tab[i]){
+			    valid_tab[i]=false;
+		    }
+	    }
+	    return;
+    }
+
+};
+ 
+#endif
+
+// Local Variables:
+// tab-width: 4
+// c-basic-offset: 4
+// c-file-offsets:((innamespace . 0)(inline-open . 0))
+// indent-tabs-mode: nil
+// End:
+
+// vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4
+
Index: branches/v4/modules/vci_mem_cache_v1/caba/source/include/mem_cache_directory_v1.h
===================================================================
--- branches/v4/modules/vci_mem_cache_v1/caba/source/include/mem_cache_directory_v1.h	(revision 371)
+++ branches/v4/modules/vci_mem_cache_v1/caba/source/include/mem_cache_directory_v1.h	(revision 371)
@@ -0,0 +1,310 @@
+#ifndef SOCLIB_CABA_MEM_CACHE_DIRECTORY_V1_H
+#define SOCLIB_CABA_MEM_CACHE_DIRECTORY_V1_H 
+
+#include <inttypes.h>
+#include <systemc>
+#include <cassert>
+#include "arithmetics.h"
+
+namespace soclib { namespace caba {
+
+  using namespace sc_core;
+
+  ////////////////////////////////////////////////////////////////////////
+  //                    A LRU entry 
+  ////////////////////////////////////////////////////////////////////////
+  class LruEntry {
+
+    public:
+
+      bool recent;            
+
+      void init()
+      {
+        recent=false;
+      }
+
+  }; // end class LruEntry
+
+  ////////////////////////////////////////////////////////////////////////
+  //                    A directory entry                               
+  ////////////////////////////////////////////////////////////////////////
+  class DirectoryEntry {
+
+    typedef uint32_t tag_t;
+    typedef uint32_t size_t;
+    typedef uint32_t copy_t;
+
+    public:
+
+    bool    valid;                  // entry valid
+    bool    is_cnt;                 // directory entry is a counter
+    bool    dirty;                  // entry dirty
+    bool    lock;                   // entry locked
+    tag_t   tag;                    // tag of the entry
+    copy_t  d_copies;               // vector of copies for data
+    copy_t  i_copies;               // vector of copies for instructions
+    size_t  count;                  // number of copies
+
+    DirectoryEntry()
+    {
+      valid    = false;
+      is_cnt   = false;
+      dirty    = false;
+      lock     = false;
+      tag      = 0;
+      d_copies = 0;
+      i_copies = 0;
+      count    = 0;
+    }
+
+    DirectoryEntry(const DirectoryEntry &source)
+    {
+      valid    = source.valid;
+      is_cnt   = source.is_cnt;
+      dirty    = source.dirty;
+      tag      = source.tag;
+      lock     = source.lock;
+      d_copies = source.d_copies;
+      i_copies = source.i_copies;
+      count    = source.count;
+    }          
+
+    /////////////////////////////////////////////////////////////////////
+    // The init() function initializes the entry 
+    /////////////////////////////////////////////////////////////////////
+    void init()
+    {
+      valid = false;
+      is_cnt= false;
+      dirty = false;
+      lock  = false;
+    }
+
+    /////////////////////////////////////////////////////////////////////
+    // The copy() function copies an existing source entry to a target 
+    /////////////////////////////////////////////////////////////////////
+    void copy(const DirectoryEntry &source)
+    {
+      valid	= source.valid;
+      is_cnt    = source.is_cnt;
+      dirty	= source.dirty;
+      tag	= source.tag;
+      lock	= source.lock;
+      d_copies	= source.d_copies;
+      i_copies	= source.i_copies;
+      count     = source.count;
+    }
+
+    ////////////////////////////////////////////////////////////////////
+    // The print() function prints the entry 
+    ////////////////////////////////////////////////////////////////////
+    void print()
+    {
+      std::cout << "Valid = " << valid << " ; IS COUNT = " << is_cnt << " ; Dirty = " << dirty << " ; Lock = " 
+        << lock << " ; Tag = " << std::hex << tag << " ; d_copies = " << d_copies << " ; i_copies = " << i_copies << " ; count = " << count << std::endl;
+    }
+
+  }; // end class DirectoryEntry
+
+  ////////////////////////////////////////////////////////////////////////
+  //                       The directory  
+  ////////////////////////////////////////////////////////////////////////
+  class CacheDirectory {
+
+    typedef sc_dt::sc_uint<40> addr_t;
+    typedef uint32_t data_t;
+    typedef uint32_t tag_t;
+    typedef uint32_t size_t;
+
+    private:
+
+    // Directory constants
+    size_t					m_ways;
+    size_t					m_sets;
+    size_t					m_words;
+    size_t					m_width;
+
+    // the directory & lru tables
+    DirectoryEntry 				**m_dir_tab;
+    LruEntry	 				**m_lru_tab;
+
+    public:
+
+    ////////////////////////
+    // Constructor
+    ////////////////////////
+    CacheDirectory( size_t ways, size_t sets, size_t words, size_t address_width)	 
+    {
+      m_ways  = ways; 
+      m_sets  = sets;
+      m_words = words;
+      m_width = address_width;
+
+      m_dir_tab = new DirectoryEntry*[sets];
+      for ( size_t i=0; i<sets; i++ ) {
+        m_dir_tab[i] = new DirectoryEntry[ways];
+        for ( size_t j=0 ; j<ways ; j++) m_dir_tab[i][j].init();
+      }
+      m_lru_tab = new LruEntry*[sets];
+      for ( size_t i=0; i<sets; i++ ) {
+        m_lru_tab[i] = new LruEntry[ways];
+        for ( size_t j=0 ; j<ways ; j++) m_lru_tab[i][j].init();
+      }
+    } // end constructor
+
+    /////////////////
+    // Destructor
+    /////////////////
+    ~CacheDirectory()
+    {
+      for(size_t i=0 ; i<m_sets ; i++){
+        delete [] m_dir_tab[i];
+        delete [] m_lru_tab[i];
+      }
+      delete [] m_dir_tab;
+      delete [] m_lru_tab;
+    } // end destructor
+
+    /////////////////////////////////////////////////////////////////////
+    // The read() function reads a directory entry. In case of hit, the
+    // LRU is updated.
+    // Arguments :
+    // - address : the address of the entry 
+    // - way : (return argument) the way of the entry in case of hit
+    // The function returns a copy of a (valid or invalid) entry  
+    /////////////////////////////////////////////////////////////////////
+    DirectoryEntry read(const addr_t &address,size_t &way)
+    {
+
+#define L2 soclib::common::uint32_log2
+      const size_t set = (size_t)(address >> (L2(m_words) + 2)) & (m_sets - 1);
+      const tag_t  tag = (tag_t)(address >> (L2(m_sets) + L2(m_words) + 2));
+#undef L2
+
+      bool hit       = false;
+      for ( size_t i=0 ; i<m_ways ; i++ ) {
+        bool equal = ( m_dir_tab[set][i].tag == tag );
+        bool valid = m_dir_tab[set][i].valid;
+        hit = equal && valid;
+        if ( hit ) {			
+          way = i;
+          break;
+        } 
+      }
+      if ( hit ) {
+        return DirectoryEntry(m_dir_tab[set][way]);
+      } else {
+        return DirectoryEntry();
+      }
+    } // end read()
+
+    /////////////////////////////////////////////////////////////////////
+    // The write function writes a new entry, 
+    // and updates the LRU bits if necessary.
+    // Arguments :
+    // - set : the set of the entry
+    // - way : the way of the entry
+    // - entry : the entry value
+    /////////////////////////////////////////////////////////////////////
+    void write(const size_t &set, const size_t &way, const DirectoryEntry &entry)
+    {
+      assert( (set<m_sets) 
+          && "Cache Directory write : The set index is invalid");
+      assert( (way<m_ways) 
+          && "Cache Directory write : The way index is invalid");
+
+      // update Directory
+      m_dir_tab[set][way].copy(entry);
+
+      // update LRU bits
+      bool all_recent = true;
+      for ( size_t i=0 ; i<m_ways ; i++ ) {
+        if ( i != way ) all_recent = m_lru_tab[set][i].recent && all_recent;
+      }
+      if ( all_recent ) {
+        for( size_t i=0 ; i<m_ways ; i++ ) m_lru_tab[set][i].recent = false;
+      } else {
+        m_lru_tab[set][way].recent = true;
+      }
+    } // end write()
+
+    /////////////////////////////////////////////////////////////////////
+    // The print() function prints a selected directory entry
+    // Arguments :
+    // - set : the set of the entry to print
+    // - way : the way of the entry to print
+    /////////////////////////////////////////////////////////////////////
+    void print(const size_t &set, const size_t &way)
+    {
+      std::cout << std::dec << " set : " << set << " ; way : " << way << " ; " ;
+      m_dir_tab[set][way].print();
+    } // end print()
+
+    /////////////////////////////////////////////////////////////////////
+    // The select() function selects a directory entry to evince.
+    // Arguments :
+    // - set   : (input argument) the set to modify
+    // - way   : (return argument) the way to evince
+    /////////////////////////////////////////////////////////////////////
+    DirectoryEntry select(const size_t &set, size_t &way)
+    {
+      assert( (set < m_sets) 
+          && "Cache Directory : (select) The set index is invalid");
+
+      for(size_t i=0; i<m_ways; i++){
+        if(!m_dir_tab[set][i].valid){
+          way=i;
+          return DirectoryEntry(m_dir_tab[set][way]);
+        }
+      }
+      for(size_t i=0; i<m_ways; i++){
+        if(!(m_lru_tab[set][i].recent) && !(m_dir_tab[set][i].lock)){
+          way=i;
+          return DirectoryEntry(m_dir_tab[set][way]);
+        }
+      }
+      for(size_t i=0; i<m_ways; i++){
+        if( !(m_lru_tab[set][i].recent) && (m_dir_tab[set][i].lock)){
+          way=i;
+          return DirectoryEntry(m_dir_tab[set][way]);
+        }
+      }
+      for(size_t i=0; i<m_ways; i++){
+        if( (m_lru_tab[set][i].recent) && !(m_dir_tab[set][i].lock)){
+          way=i;
+          return DirectoryEntry(m_dir_tab[set][way]);
+        }
+      }
+      way = 0;
+      return DirectoryEntry(m_dir_tab[set][0]);
+    } // end select()
+
+    /////////////////////////////////////////////////////////////////////
+    // 		Global initialisation function
+    /////////////////////////////////////////////////////////////////////
+    void init()
+    {
+      for ( size_t set=0 ; set<m_sets ; set++ ) {
+        for ( size_t way=0 ; way<m_ways ; way++ ) {
+          m_dir_tab[set][way].init();
+          m_lru_tab[set][way].init();
+        }
+      }
+    } // end init()
+
+  }; // end class CacheDirectory
+
+}} // end namespaces
+
+#endif
+
+// Local Variables:
+// tab-width: 4
+// c-basic-offset: 4
+// c-file-offsets:((innamespace . 0)(inline-open . 0))
+// indent-tabs-mode: nil
+// End:
+
+// vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4
+
Index: branches/v4/modules/vci_mem_cache_v1/caba/source/include/update_tab_v1.h
===================================================================
--- branches/v4/modules/vci_mem_cache_v1/caba/source/include/update_tab_v1.h	(revision 371)
+++ branches/v4/modules/vci_mem_cache_v1/caba/source/include/update_tab_v1.h	(revision 371)
@@ -0,0 +1,402 @@
+#ifndef UPDATE_TAB_V1_H_
+#define UPDATE_TAB_V1_H_
+
+#include <inttypes.h>
+#include <systemc>
+#include <cassert>
+#include "arithmetics.h"
+
+////////////////////////////////////////////////////////////////////////
+//                  An update tab entry    
+////////////////////////////////////////////////////////////////////////
+class UpdateTabEntry {
+  typedef uint32_t size_t;
+  typedef sc_dt::sc_uint<40> addr_t;
+
+  public:
+  bool 	valid;                // It is a valid pending transaction
+  bool	update;               // It is an update transaction
+  bool  brdcast;              // It is a broadcast invalidate
+  bool  rsp;                  // It needs a response to the initiator
+  size_t 	srcid;        // The srcid of the initiator which wrote the data
+  size_t 	trdid;        // The trdid of the initiator which wrote the data
+  size_t 	pktid;        // The pktid of the initiator which wrote the data
+  addr_t	nline;	      // The identifier of the cache line
+  size_t 	count;        // The number of acknowledge responses to receive
+
+  UpdateTabEntry(){
+    valid	= false;
+    update  = false;
+    brdcast = false;
+    rsp     = false;
+    srcid	= 0;
+    trdid	= 0;
+    pktid	= 0;
+    nline	= 0;
+    count	= 0;
+  }
+
+  UpdateTabEntry(bool   i_valid, 
+      bool   i_update,
+      bool   i_brdcast,
+      bool   i_rsp,
+      size_t i_srcid, 
+      size_t i_trdid, 
+      size_t i_pktid, 
+      addr_t i_nline,
+      size_t i_count) 
+  {
+    valid		= i_valid;
+    update	    = i_update;
+    brdcast     = i_brdcast;
+    rsp         = i_rsp;
+    srcid		= i_srcid;
+    trdid		= i_trdid;
+    pktid		= i_pktid;
+    nline		= i_nline;
+    count		= i_count;
+  }
+
+  UpdateTabEntry(const UpdateTabEntry &source)
+  {
+    valid   = source.valid;
+    update  = source.update;
+    brdcast = source.brdcast;
+    rsp     = source.rsp;
+    srcid   = source.srcid;
+    trdid   = source.trdid;
+    pktid   = source.pktid;
+    nline   = source.nline;
+    count   = source.count;
+  }
+
+  ////////////////////////////////////////////////////
+  // The init() function initializes the entry 
+  ///////////////////////////////////////////////////
+  void init()
+  {
+    valid  = false;
+    update = false;
+    brdcast= false;
+    rsp    = false;
+    srcid  = 0;
+    trdid  = 0;
+    pktid  = 0;
+    nline  = 0;
+    count  = 0;
+  }
+
+  ////////////////////////////////////////////////////////////////////
+  // The copy() function copies an existing entry
+  // Its arguments are :
+  // - source : the update tab entry to copy
+  ////////////////////////////////////////////////////////////////////
+  void copy(const UpdateTabEntry &source)
+  {
+    valid  = source.valid;
+    update = source.update;
+    brdcast= source.brdcast;
+    rsp    = source.rsp;
+    srcid  = source.srcid;
+    trdid  = source.trdid;
+    pktid  = source.pktid;
+    nline  = source.nline;
+    count  = source.count;
+  }
+
+  ////////////////////////////////////////////////////////////////////
+  // The print() function prints the entry  
+  ////////////////////////////////////////////////////////////////////
+  void print(){
+    std::cout << std::dec << "valid  = " << valid  << std::endl;
+    std::cout << "update = " << update << std::endl;
+    std::cout << "brdcast= " << brdcast<< std::endl;
+    std::cout << "rsp    = " << rsp    << std::endl;
+    std::cout << "srcid  = " << srcid  << std::endl; 
+    std::cout << "trdid  = " << trdid  << std::endl; 
+    std::cout << "pktid  = " << pktid  << std::endl; 
+    std::cout << std::hex << "nline  = " << nline  << std::endl;
+    std::cout << std::dec << "count  = " << count  << std::endl;
+  }
+};
+
+////////////////////////////////////////////////////////////////////////
+//                        The update tab             
+////////////////////////////////////////////////////////////////////////
+class UpdateTab{
+
+  typedef uint32_t size_t;
+  typedef sc_dt::sc_uint<40> addr_t;
+
+  private:
+  size_t size_tab;
+  std::vector<UpdateTabEntry> tab;
+
+  public:
+
+  UpdateTab()
+    : tab(0)
+  {
+    size_tab=0;
+  }
+
+  UpdateTab(size_t size_tab_i)
+    : tab(size_tab_i)
+  {
+    size_tab=size_tab_i;
+  }
+
+  ////////////////////////////////////////////////////////////////////
+  // The size() function returns the size of the tab  
+  ////////////////////////////////////////////////////////////////////
+  const size_t size(){
+    return size_tab;
+  }
+
+
+  ////////////////////////////////////////////////////////////////////
+  // The size() function returns the size of the tab  
+  ////////////////////////////////////////////////////////////////////
+  void print(){
+    for(size_t i=0; i<size_tab; i++) {
+      std::cout << "UPDATE TAB ENTRY " << std::dec << i << "--------" << std::endl;
+      tab[i].print();
+    }
+    return;
+  }
+
+
+  /////////////////////////////////////////////////////////////////////
+  // The init() function initializes the tab 
+  /////////////////////////////////////////////////////////////////////
+  void init(){
+    for ( size_t i=0; i<size_tab; i++) {
+      tab[i].init();
+    }
+  }
+
+
+  /////////////////////////////////////////////////////////////////////
+  // The reads() function reads an entry 
+  // Arguments :
+  // - entry : the entry to read
+  // This function returns a copy of the entry.
+  /////////////////////////////////////////////////////////////////////
+  UpdateTabEntry read (size_t entry)
+  {
+    assert(entry<size_tab && "Bad Update Tab Entry");
+    return UpdateTabEntry(tab[entry]);
+  }
+
+  ///////////////////////////////////////////////////////////////////////////
+  // The set() function writes an entry in the Update Table
+  // Arguments :
+  // - update : transaction type (bool)
+  // - srcid : srcid of the initiator
+  // - trdid : trdid of the initiator
+  // - pktid : pktid of the initiator
+  // - count : number of expected responses
+  // - index : (return argument) index of the selected entry
+  // This function returns true if the write successed (an entry was empty).
+  ///////////////////////////////////////////////////////////////////////////
+  bool set(const bool	update,
+      const bool   brdcast,
+      const bool   rsp,
+      const size_t srcid,
+      const size_t trdid,
+      const size_t pktid,
+      const addr_t nline,
+      const size_t count,
+      size_t &index)
+  {
+    for ( size_t i=0 ; i<size_tab ; i++ ) {
+      if( !tab[i].valid ) {
+        tab[i].valid		= true;
+        tab[i].update		= update;
+        tab[i].brdcast      = brdcast;
+        tab[i].rsp          = rsp;
+        tab[i].srcid		= (size_t) srcid;
+        tab[i].trdid		= (size_t) trdid;
+        tab[i].pktid		= (size_t) pktid;
+        tab[i].nline		= (addr_t) nline;
+        tab[i].count		= (size_t) count;
+        index			    = i;
+        return true;
+      }
+    }
+    return false;
+  } // end set()
+
+  /////////////////////////////////////////////////////////////////////
+  // The decrement() function decrements the counter for a given entry.
+  // Arguments :
+  // - index   : the index of the entry
+  // - counter : (return argument) value of the counter after decrement
+  // This function returns true if the entry is valid.
+  /////////////////////////////////////////////////////////////////////
+  bool decrement( const size_t index,
+      size_t &counter ) 
+  {
+    assert((index<size_tab) && "Bad Update Tab Entry");
+    if ( tab[index].valid ) {
+      tab[index].count--;
+      counter = tab[index].count;
+      return true;
+    } else {
+      return false;
+    }
+  }
+
+  /////////////////////////////////////////////////////////////////////
+  // The is_full() function returns true if the table is full
+  /////////////////////////////////////////////////////////////////////
+  bool is_full()
+  {
+    for(size_t i = 0 ; i < size_tab ; i++){
+      if(!tab[i].valid){
+        return false;
+      }
+    }
+    return true;
+  }
+
+  /////////////////////////////////////////////////////////////////////
+  // The need_rsp() function returns the need of a response
+  // Arguments :
+  // - index : the index of the entry
+  /////////////////////////////////////////////////////////////////////
+  bool need_rsp(const size_t index)
+  {
+    assert(index<size_tab && "Bad Update Tab Entry");
+    return tab[index].rsp;	
+  }
+
+  /////////////////////////////////////////////////////////////////////
+  // The is_update() function returns the transaction type
+  // Arguments :
+  // - index : the index of the entry
+  /////////////////////////////////////////////////////////////////////
+  bool is_brdcast(const size_t index)
+  {
+    assert(index<size_tab && "Bad Update Tab Entry");
+    return tab[index].brdcast;	
+  }
+
+  /////////////////////////////////////////////////////////////////////
+  // The is_update() function returns the transaction type
+  // Arguments :
+  // - index : the index of the entry
+  /////////////////////////////////////////////////////////////////////
+  bool is_update(const size_t index)
+  {
+    assert(index<size_tab && "Bad Update Tab Entry");
+    return tab[index].update;	
+  }
+
+  /////////////////////////////////////////////////////////////////////
+  // The srcid() function returns the srcid value
+  // Arguments :
+  // - index : the index of the entry
+  /////////////////////////////////////////////////////////////////////
+  size_t srcid(const size_t index)
+  {
+    assert(index<size_tab && "Bad Update Tab Entry");
+    return tab[index].srcid;	
+  }
+
+  /////////////////////////////////////////////////////////////////////
+  // The trdid() function returns the trdid value
+  // Arguments :
+  // - index : the index of the entry
+  /////////////////////////////////////////////////////////////////////
+  size_t trdid(const size_t index)
+  {
+    assert(index<size_tab && "Bad Update Tab Entry");
+    return tab[index].trdid;	
+  }
+
+  /////////////////////////////////////////////////////////////////////
+  // The pktid() function returns the pktid value
+  // Arguments :
+  // - index : the index of the entry
+  /////////////////////////////////////////////////////////////////////
+  size_t pktid(const size_t index)
+  {
+    assert(index<size_tab && "Bad Update Tab Entry");
+    return tab[index].pktid;	
+  }
+
+  /////////////////////////////////////////////////////////////////////
+  // The nline() function returns the nline value
+  // Arguments :
+  // - index : the index of the entry
+  /////////////////////////////////////////////////////////////////////
+  addr_t nline(const size_t index)
+  {
+    assert(index<size_tab && "Bad Update Tab Entry");
+    return tab[index].nline;
+  }
+
+  /////////////////////////////////////////////////////////////////////
+  // The search_inval() function returns the index of the entry in UPT
+  // Arguments :
+  // - nline : the line number of the entry in the directory
+  /////////////////////////////////////////////////////////////////////
+  bool search_inval(const addr_t nline,size_t &index)
+  {
+    size_t i ;
+
+    for (i = 0 ; i < size_tab ; i++){
+      if((tab[i].nline == nline) && tab[i].valid){
+        if(!tab[i].update){
+          index = i ;
+          return true;
+        }
+      }
+    }
+    return false;
+  }
+
+  /////////////////////////////////////////////////////////////////////
+  // The read_nline() function returns the index of the entry in UPT
+  // Arguments :
+  // - nline : the line number of the entry in the directory
+  /////////////////////////////////////////////////////////////////////
+  bool read_nline(const addr_t nline,size_t &index) 
+  {
+    size_t i ;
+
+    for (i = 0 ; i < size_tab ; i++){
+      if((tab[i].nline == nline) && tab[i].valid){
+        index = i ;
+        return true;
+      }
+    }
+    return false;
+  }
+
+  /////////////////////////////////////////////////////////////////////
+  // The clear() function erases an entry of the tab
+  // Arguments :
+  // - index : the index of the entry
+  /////////////////////////////////////////////////////////////////////       
+  void clear(const size_t index)
+  {
+    assert(index<size_tab && "Bad Update Tab Entry");
+    tab[index].valid=false;
+    return;	
+  }
+
+};
+
+#endif
+
+// Local Variables:
+// tab-width: 4
+// c-basic-offset: 4
+// c-file-offsets:((innamespace . 0)(inline-open . 0))
+// indent-tabs-mode: nil
+// End:
+
+// vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4
+
Index: branches/v4/modules/vci_mem_cache_v1/caba/source/include/vci_mem_cache_v1.h
===================================================================
--- branches/v4/modules/vci_mem_cache_v1/caba/source/include/vci_mem_cache_v1.h	(revision 371)
+++ branches/v4/modules/vci_mem_cache_v1/caba/source/include/vci_mem_cache_v1.h	(revision 371)
@@ -0,0 +1,625 @@
+/* -*- c++ -*-
+ * File         : vci_mem_cache_v1.h
+ * Date         : 26/10/2008
+ * Copyright    : UPMC / LIP6
+ * Authors      : Alain Greiner / Eric Guthmuller
+ *
+ * SOCLIB_LGPL_HEADER_BEGIN
+ *
+ * This file is part of SoCLib, GNU LGPLv2.1.
+ *
+ * SoCLib is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU Lesser General Public License as published
+ * by the Free Software Foundation; version 2.1 of the License.
+ *
+ * SoCLib is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with SoCLib; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301 USA
+ *
+ * SOCLIB_LGPL_HEADER_END
+ *
+ * Maintainers: alain eric.guthmuller@polytechnique.edu choichillon.christophe@gmail.com
+ */
+
+#ifndef SOCLIB_CABA_MEM_CACHE_V1_H
+#define SOCLIB_CABA_MEM_CACHE_V1_H
+
+#include <inttypes.h>
+#include <systemc>
+#include <list>
+#include <cassert>
+#include "arithmetics.h"
+#include "alloc_elems.h"
+#include "caba_base_module.h"
+#include "vci_target.h"
+#include "vci_initiator.h"
+#include "generic_fifo.h"
+#include "mapping_table.h"
+#include "int_tab.h"
+#include "mem_cache_directory_v1.h"
+#include "xram_transaction_v1.h"
+#include "update_tab_v1.h"
+#include "atomic_tab_v1.h"
+
+#define TRANSACTION_TAB_LINES 4     // Number of lines in the transaction tab
+#define UPDATE_TAB_LINES 4          // Number of lines in the update tab
+//#define BROADCAST_ADDR 0x0000000003 // Address to send the broadcast invalidate
+
+namespace soclib {  namespace caba {
+  using namespace sc_core;
+
+  template<typename vci_param>
+    class VciMemCacheV1
+    : public soclib::caba::BaseModule
+    {
+      typedef sc_dt::sc_uint<40> addr_t;
+      typedef typename vci_param::fast_addr_t vci_addr_t;
+      typedef uint32_t data_t;
+      typedef uint32_t tag_t;
+      typedef uint32_t size_t;
+      typedef uint32_t be_t;
+      typedef uint32_t copy_t;
+
+      /* States of the TGT_CMD fsm */
+      enum tgt_cmd_fsm_state_e{
+        TGT_CMD_IDLE,
+        TGT_CMD_READ,
+        TGT_CMD_READ_EOP,
+        TGT_CMD_WRITE,
+        TGT_CMD_ATOMIC,
+      };
+
+      /* States of the TGT_RSP fsm */
+      enum tgt_rsp_fsm_state_e{
+        TGT_RSP_READ_IDLE,
+        TGT_RSP_WRITE_IDLE,
+        TGT_RSP_LLSC_IDLE,
+        TGT_RSP_XRAM_IDLE,
+        TGT_RSP_INIT_IDLE,
+        TGT_RSP_CLEANUP_IDLE,
+        TGT_RSP_READ_TEST,
+        TGT_RSP_READ_WORD,
+        TGT_RSP_READ_LINE,
+        TGT_RSP_WRITE,
+        TGT_RSP_LLSC,
+        TGT_RSP_XRAM_TEST,
+        TGT_RSP_XRAM_WORD,
+        TGT_RSP_XRAM_LINE,
+        TGT_RSP_INIT,
+        TGT_RSP_CLEANUP,
+      };
+
+      /* States of the INIT_CMD fsm */
+      enum init_cmd_fsm_state_e{
+        INIT_CMD_INVAL_IDLE,
+        INIT_CMD_INVAL_SEL,
+        INIT_CMD_INVAL_NLINE,
+        INIT_CMD_UPDT_IDLE,
+        INIT_CMD_UPDT_SEL,
+        INIT_CMD_BRDCAST,
+        INIT_CMD_UPDT_NLINE,
+        INIT_CMD_UPDT_INDEX,
+        INIT_CMD_UPDT_DATA,
+      };
+
+      /* States of the INIT_RSP fsm */
+      enum init_rsp_fsm_state_e{
+        INIT_RSP_IDLE,
+        INIT_RSP_UPT_LOCK,
+        INIT_RSP_UPT_CLEAR,
+        INIT_RSP_END,
+      };
+
+      /* States of the READ fsm */
+      enum read_fsm_state_e{
+        READ_IDLE,
+        READ_DIR_LOCK,
+        READ_DIR_HIT,
+        READ_RSP,
+        READ_TRT_LOCK,
+        READ_TRT_SET,
+        READ_XRAM_REQ,
+      };
+
+      /* States of the WRITE fsm */
+      enum write_fsm_state_e{
+        WRITE_IDLE,
+        WRITE_NEXT,
+        WRITE_DIR_LOCK,
+        WRITE_DIR_HIT_READ,
+        WRITE_DIR_HIT,
+        WRITE_DIR_HIT_RSP,
+        WRITE_UPT_LOCK,
+        WRITE_WAIT_UPT,
+        WRITE_UPDATE,
+        WRITE_RSP,
+        WRITE_TRT_LOCK,
+        WRITE_TRT_DATA,
+        WRITE_TRT_SET,
+        WRITE_WAIT_TRT,
+        WRITE_XRAM_REQ,
+        WRITE_TRT_WRITE_LOCK,
+        WRITE_INVAL_LOCK,
+        WRITE_DIR_INVAL,
+        WRITE_INVAL,
+        WRITE_XRAM_SEND,
+        WRITE_RESET
+      };
+
+      /* States of the IXR_RSP fsm */
+      enum ixr_rsp_fsm_state_e{
+        IXR_RSP_IDLE,
+        IXR_RSP_ACK,
+        IXR_RSP_TRT_ERASE,
+        IXR_RSP_TRT_READ,
+      };
+
+      /* States of the XRAM_RSP fsm */
+      enum xram_rsp_fsm_state_e{
+        XRAM_RSP_IDLE,
+        XRAM_RSP_TRT_COPY,
+        XRAM_RSP_TRT_DIRTY,
+        XRAM_RSP_DIR_LOCK,
+        XRAM_RSP_DIR_UPDT,
+        XRAM_RSP_DIR_RSP,
+        XRAM_RSP_INVAL_LOCK,
+        XRAM_RSP_INVAL_WAIT,
+        XRAM_RSP_INVAL,
+        XRAM_RSP_WRITE_DIRTY,
+      };
+
+      /* States of the IXR_CMD fsm */
+      enum ixr_cmd_fsm_state_e{
+        IXR_CMD_READ_IDLE,
+        IXR_CMD_WRITE_IDLE,
+        IXR_CMD_LLSC_IDLE,
+        IXR_CMD_XRAM_IDLE,
+        IXR_CMD_READ_NLINE,
+        IXR_CMD_WRITE_NLINE,
+        IXR_CMD_LLSC_NLINE,
+        IXR_CMD_XRAM_DATA,
+      };
+
+      /* States of the LLSC fsm */
+      enum llsc_fsm_state_e{
+        LLSC_IDLE,
+        LL_DIR_LOCK,
+        LL_DIR_HIT,
+        LL_RSP,
+        SC_DIR_LOCK,
+        SC_DIR_HIT,
+        SC_RSP_FALSE,
+        SC_RSP_TRUE,
+        LLSC_TRT_LOCK,
+        LLSC_TRT_SET,
+        LLSC_XRAM_REQ,
+      };
+
+      /* States of the CLEANUP fsm */
+      enum cleanup_fsm_state_e{
+        CLEANUP_IDLE,
+        CLEANUP_DIR_LOCK,
+        CLEANUP_DIR_WRITE,
+        CLEANUP_UPT_LOCK,
+        CLEANUP_UPT_WRITE,
+        CLEANUP_WRITE_RSP,
+        CLEANUP_RSP,
+      };
+
+      /* States of the ALLOC_DIR fsm */
+      enum alloc_dir_fsm_state_e{
+        ALLOC_DIR_READ,
+        ALLOC_DIR_WRITE,
+        ALLOC_DIR_LLSC,
+        ALLOC_DIR_CLEANUP,
+        ALLOC_DIR_XRAM_RSP,
+      };
+
+      /* States of the ALLOC_TRT fsm */
+      enum alloc_trt_fsm_state_e{
+        ALLOC_TRT_READ,
+        ALLOC_TRT_WRITE,
+        ALLOC_TRT_LLSC,
+        ALLOC_TRT_XRAM_RSP,
+        ALLOC_TRT_IXR_RSP,
+      };
+
+      /* States of the ALLOC_UPT fsm */
+      enum alloc_upt_fsm_state_e{
+        ALLOC_UPT_WRITE,
+        ALLOC_UPT_XRAM_RSP,
+        ALLOC_UPT_INIT_RSP,
+        ALLOC_UPT_CLEANUP,
+      };
+
+      uint32_t	   m_cpt_cycles;            // Counter of cycles 
+      uint32_t	   m_cpt_read;              // Number of READ transactions
+      uint32_t	   m_cpt_read_miss;         // Number of MISS READ 
+      uint32_t	   m_cpt_write;             // Number of WRITE transactions
+      uint32_t	   m_cpt_write_miss;        // Number of MISS WRITE
+      uint32_t     m_cpt_write_cells;	    // Cumulated length for WRITE transactions
+      uint32_t     m_cpt_write_dirty;	    // Cumulated length for WRITE transactions
+      uint32_t	   m_cpt_update;            // Number of UPDATE transactions
+      uint32_t	   m_cpt_update_mult;       // Number of targets for UPDATE
+      uint32_t	   m_cpt_inval;             // Number of INVAL  transactions
+      uint32_t	   m_cpt_inval_mult;        // Number of targets for INVAL  
+      uint32_t	   m_cpt_inval_brdcast;     // Number of BROADCAST INVAL  
+      uint32_t	   m_cpt_cleanup;           // Number of CLEANUP transactions
+      uint32_t	   m_cpt_ll;                // Number of LL transactions
+      uint32_t	   m_cpt_sc;                // Number of SC transactions
+
+      protected:
+
+      SC_HAS_PROCESS(VciMemCacheV1);
+
+      public:
+      sc_in<bool> 			  	p_clk;
+      sc_in<bool> 			  	p_resetn;
+      soclib::caba::VciTarget<vci_param>    	p_vci_tgt;
+      soclib::caba::VciTarget<vci_param>    	p_vci_tgt_cleanup;
+      soclib::caba::VciInitiator<vci_param> 	p_vci_ini;	
+      soclib::caba::VciInitiator<vci_param> 	p_vci_ixr;
+
+      VciMemCacheV1(
+          sc_module_name name,                              // Instance Name 
+          const soclib::common::MappingTable &mtp,          // Mapping table for primary requets
+          const soclib::common::MappingTable &mtc,          // Mapping table for coherence requets
+          const soclib::common::MappingTable &mtx,          // Mapping table for XRAM
+          const soclib::common::IntTab &vci_ixr_index,      // VCI port to XRAM (initiator)
+          const soclib::common::IntTab &vci_ini_index,      // VCI port to PROC (initiator)
+          const soclib::common::IntTab &vci_tgt_index,      // VCI port to PROC (target)
+          const soclib::common::IntTab &vci_tgt_index_cleanup,    // VCI port to PROC (target) for cleanup
+          size_t nways,                                   // Number of ways per set 
+          size_t nsets,                                   // Number of sets
+          size_t nwords);                                 // Number of words per line
+
+      ~VciMemCacheV1();
+
+      void transition();
+
+      void genMoore();
+
+      void print_stats();
+
+      private:
+
+      // Component attributes
+      const size_t              m_initiators;           // Number of initiators
+      const size_t              m_ways;                 // Number of ways in a set
+      const size_t              m_sets;                 // Number of cache sets
+      const size_t              m_words;		        // Number of words in a line
+      const size_t              m_srcid_ixr;		    // Srcid for requests to XRAM 
+      const size_t              m_srcid_ini;		    // Srcid for requests to processors
+      std::list<soclib::common::Segment>  m_seglist;    // memory cached into the cache
+      std::list<soclib::common::Segment>  m_cseglist;   // coherence segment for the cache
+      vci_addr_t        		*m_coherence_table; 	// address(srcid)
+      AtomicTab                 m_atomic_tab;           // atomic access table
+      TransactionTab      		m_transaction_tab;	    // xram transaction table
+      UpdateTab                 m_update_tab;		    // pending update & invalidate 
+      CacheDirectory			m_cache_directory;	    // data cache directory
+      vci_addr_t        		m_broadcast_address; 	// broadcast address
+
+      data_t	        	       ***m_cache_data;		// data array[set][way][word]
+
+      // adress masks
+      const soclib::common::AddressMaskingTable<vci_addr_t>   m_x;
+      const soclib::common::AddressMaskingTable<vci_addr_t>   m_y;
+      const soclib::common::AddressMaskingTable<vci_addr_t>   m_z;
+      const soclib::common::AddressMaskingTable<vci_addr_t>   m_nline; 
+
+      //////////////////////////////////////////////////
+      // Others registers
+      //////////////////////////////////////////////////
+      sc_signal<size_t>   r_copies_limit; // Limit of the number of copies for one line
+
+      //////////////////////////////////////////////////
+      // Registers controlled by the TGT_CMD fsm
+      //////////////////////////////////////////////////
+
+      // Fifo between TGT_CMD fsm and READ fsm
+      GenericFifo<uint64_t>  m_cmd_read_addr_fifo;
+      GenericFifo<bool>      m_cmd_read_word_fifo;
+      GenericFifo<size_t>    m_cmd_read_srcid_fifo;
+      GenericFifo<size_t>    m_cmd_read_trdid_fifo;
+      GenericFifo<size_t>    m_cmd_read_pktid_fifo;
+
+      // Fifo between TGT_CMD fsm and WRITE fsm    
+      GenericFifo<uint64_t>  m_cmd_write_addr_fifo;
+      GenericFifo<bool>      m_cmd_write_eop_fifo;
+      GenericFifo<size_t>    m_cmd_write_srcid_fifo;
+      GenericFifo<size_t>    m_cmd_write_trdid_fifo;
+      GenericFifo<size_t>    m_cmd_write_pktid_fifo;
+      GenericFifo<data_t>    m_cmd_write_data_fifo;
+      GenericFifo<be_t>	     m_cmd_write_be_fifo;
+
+      // Fifo between TGT_CMD fsm and LLSC fsm
+      GenericFifo<uint64_t>  m_cmd_llsc_addr_fifo;
+      GenericFifo<bool>      m_cmd_llsc_sc_fifo;
+      GenericFifo<size_t>    m_cmd_llsc_srcid_fifo;
+      GenericFifo<size_t>    m_cmd_llsc_trdid_fifo;
+      GenericFifo<size_t>    m_cmd_llsc_pktid_fifo;
+      GenericFifo<data_t>    m_cmd_llsc_wdata_fifo;
+
+      sc_signal<int>         r_tgt_cmd_fsm;
+
+      sc_signal<size_t>	     r_index;
+      size_t nseg;
+      size_t ncseg;
+      soclib::common::Segment  **m_seg;
+      soclib::common::Segment  **m_cseg;
+      ///////////////////////////////////////////////////////
+      // Registers controlled by the READ fsm
+      ///////////////////////////////////////////////////////
+
+      sc_signal<int>         r_read_fsm;        // FSM state 
+      sc_signal<copy_t>      r_read_d_copies;   // bit-vector of copies 
+      sc_signal<copy_t>      r_read_i_copies;   // bit-vector of copies 
+      sc_signal<tag_t>       r_read_tag;	    // cache line tag (in directory)
+      sc_signal<bool>        r_read_is_cnt;	    // is_cnt bit (in directory)
+      sc_signal<bool>        r_read_lock;	    // lock bit (in directory)
+      sc_signal<bool>        r_read_dirty;	    // dirty bit (in directory)
+      sc_signal<size_t>      r_read_count;      // number of copies
+      sc_signal<data_t>     *r_read_data;       // data (one cache line)
+      sc_signal<bool>        r_read_word;       // single word read
+      sc_signal<size_t>      r_read_way;        // associative way (in cache)
+      sc_signal<size_t>      r_read_trt_index;  // Transaction Table index
+      sc_signal<bool>        r_read_pass;       // Used to adjust with VHDL model
+
+      // Buffer between READ fsm and IXR_CMD fsm (ask a missing cache line to XRAM)   
+      sc_signal<bool>        r_read_to_ixr_cmd_req;     // valid request
+      sc_signal<addr_t>      r_read_to_ixr_cmd_nline;   // cache line index
+      sc_signal<size_t>      r_read_to_ixr_cmd_trdid;   // index in Transaction Table
+
+      // Buffer between READ fsm and TGT_RSP fsm (send a hit read response to L1 cache)
+      sc_signal<bool>	   r_read_to_tgt_rsp_req;       // valid request
+      sc_signal<size_t>	   r_read_to_tgt_rsp_srcid;	    // Transaction srcid
+      sc_signal<size_t>	   r_read_to_tgt_rsp_trdid;	    // Transaction trdid
+      sc_signal<size_t>	   r_read_to_tgt_rsp_pktid;	    // Transaction pktid
+      sc_signal<data_t>   *r_read_to_tgt_rsp_data;	    // data (one cache line)
+      sc_signal<bool> 	  *r_read_to_tgt_rsp_val;	    // valid bit (for single_word)
+
+      ///////////////////////////////////////////////////////////////
+      // Registers controlled by the WRITE fsm
+      ///////////////////////////////////////////////////////////////
+
+      sc_signal<int>       r_write_fsm;             // FSM state
+      sc_signal<addr_t>	   r_write_address;         // first word address
+      sc_signal<size_t>    r_write_word_index;      // first word index in line
+      sc_signal<size_t>    r_write_word_count;      // number of words in line
+      sc_signal<size_t>    r_write_srcid;           // transaction srcid
+      sc_signal<size_t>    r_write_trdid;           // transaction trdid
+      sc_signal<size_t>    r_write_pktid;           // transaction pktid
+      sc_signal<data_t>	  *r_write_data;            // data (one cache line)	
+      sc_signal<be_t>     *r_write_be;              // one byte enable per word
+      sc_signal<bool>      r_write_byte;            // is it a byte write
+      sc_signal<bool>      r_write_is_cnt;          // is_cnt bit (in directory)
+      sc_signal<bool>      r_write_lock;            // lock bit (in directory)
+      sc_signal<tag_t>     r_write_tag;             // cache line tag (in directory)
+      sc_signal<copy_t>    r_write_d_copies;        // bit vector of copies
+      sc_signal<copy_t>    r_write_i_copies;        // bit vector of copies
+      sc_signal<size_t>	   r_write_count;           // number of copies
+      sc_signal<size_t>	   r_write_way;		        // way of the line
+      sc_signal<size_t>    r_write_trt_index;	    // index in Transaction Table
+      sc_signal<size_t>    r_write_upt_index;	    // index in Update Table
+      sc_signal<bool>      r_write_pass;            // Used to adjust with VHDL model
+
+      // Buffer between WRITE fsm and TGT_RSP fsm (acknowledge a write command from L1)
+      sc_signal<bool>      r_write_to_tgt_rsp_req;		// valid request
+      sc_signal<size_t>    r_write_to_tgt_rsp_srcid;    // transaction srcid
+      sc_signal<size_t>    r_write_to_tgt_rsp_trdid;	// transaction trdid
+      sc_signal<size_t>    r_write_to_tgt_rsp_pktid;	// transaction pktid
+
+      // Buffer between WRITE fsm and IXR_CMD fsm (ask a missing cache line to XRAM) 
+      sc_signal<bool>	   r_write_to_ixr_cmd_req;      // valid request
+      sc_signal<bool>	   r_write_to_ixr_cmd_write;    // write request
+      sc_signal<addr_t>    r_write_to_ixr_cmd_nline; 	// cache line index
+      sc_signal<data_t>	  *r_write_to_ixr_cmd_data;	    // cache line data
+      sc_signal<size_t>    r_write_to_ixr_cmd_trdid;	// index in Transaction Table
+
+      // Buffer between WRITE fsm and INIT_CMD fsm (Update L1 caches)
+      sc_signal<bool>	   r_write_to_init_cmd_req;         // valid request
+      sc_signal<bool>	   r_write_to_init_cmd_brdcast;     // brdcast request
+      sc_signal<addr_t>	   r_write_to_init_cmd_nline;	    // cache line index
+      sc_signal<size_t>	   r_write_to_init_cmd_trdid;	    // index in Update Table
+      sc_signal<copy_t>    r_write_to_init_cmd_d_copies;    // bit_vector of L1 to update
+      sc_signal<copy_t>    r_write_to_init_cmd_i_copies;    // bit_vector of L1 to update
+      sc_signal<data_t>   *r_write_to_init_cmd_data;	    // data (one cache line)
+      sc_signal<bool>     *r_write_to_init_cmd_we;	        // word enable
+      sc_signal<size_t>	   r_write_to_init_cmd_count;	    // number of words in line
+      sc_signal<size_t>	   r_write_to_init_cmd_index;	    // index of first word in line
+
+      /////////////////////////////////////////////////////////
+      // Registers controlled by INIT_RSP fsm
+      //////////////////////////////////////////////////////////
+
+      sc_signal<int> 	   r_init_rsp_fsm;        // FSM state
+      sc_signal<size_t>	   r_init_rsp_upt_index;  // index in the Update Table
+      sc_signal<size_t>	   r_init_rsp_srcid;	  // pending write srcid      
+      sc_signal<size_t>	   r_init_rsp_trdid;	  // pending write trdid      
+      sc_signal<size_t>	   r_init_rsp_pktid;	  // pending write pktid      
+      sc_signal<addr_t>	   r_init_rsp_nline;	  // pending write nline      
+
+      // Buffer between INIT_RSP fsm and TGT_RSP fsm (complete write/update transaction)
+      sc_signal<bool>	     r_init_rsp_to_tgt_rsp_req;   	// valid request
+      sc_signal<size_t>	   r_init_rsp_to_tgt_rsp_srcid;		// Transaction srcid
+      sc_signal<size_t>	   r_init_rsp_to_tgt_rsp_trdid;		// Transaction trdid
+      sc_signal<size_t>	   r_init_rsp_to_tgt_rsp_pktid;		// Transaction pktid
+
+      ///////////////////////////////////////////////////////
+      // Registers controlled by CLEANUP fsm
+      ///////////////////////////////////////////////////////
+
+      sc_signal<int> 	     r_cleanup_fsm;         // FSM state
+      sc_signal<size_t>      r_cleanup_srcid;       // transaction srcid
+      sc_signal<size_t>      r_cleanup_trdid;       // transaction trdid
+      sc_signal<size_t>      r_cleanup_pktid;       // transaction pktid
+      sc_signal<addr_t>      r_cleanup_nline;       // cache line index
+
+      sc_signal<copy_t>      r_cleanup_d_copies;    // bit-vector of copies 
+      sc_signal<copy_t>      r_cleanup_i_copies;    // bit-vector of copies 
+      sc_signal<copy_t>      r_cleanup_count;       // number of copies 
+      sc_signal<tag_t>       r_cleanup_tag;	        // cache line tag (in directory)
+      sc_signal<bool>        r_cleanup_is_cnt;      // inst bit (in directory)
+      sc_signal<bool>        r_cleanup_lock;	    // lock bit (in directory)
+      sc_signal<bool>        r_cleanup_dirty;	    // dirty bit (in directory)
+      sc_signal<size_t>      r_cleanup_way;	        // associative way (in cache)
+      sc_signal<bool>        r_cleanup_pass;        // Used to adjust with the VHDL model
+
+      sc_signal<size_t>      r_cleanup_write_srcid; // srcid of write response
+      sc_signal<size_t>      r_cleanup_write_trdid; // trdid of write rsp
+      sc_signal<size_t>      r_cleanup_write_pktid; // pktid of write rsp
+      sc_signal<bool>        r_cleanup_need_rsp;    // needs a write rsp
+
+      sc_signal<size_t>      r_cleanup_index;	    // index of the INVAL line (in the UPT)
+
+      // Buffer between CLEANUP fsm and TGT_RSP fsm (acknowledge a write command from L1)
+      sc_signal<bool>      r_cleanup_to_tgt_rsp_req;    // valid request
+      sc_signal<size_t>    r_cleanup_to_tgt_rsp_srcid;  // transaction srcid
+      sc_signal<size_t>    r_cleanup_to_tgt_rsp_trdid;	// transaction trdid
+      sc_signal<size_t>    r_cleanup_to_tgt_rsp_pktid;	// transaction pktid
+
+      ///////////////////////////////////////////////////////
+      // Registers controlled by LLSC fsm
+      ///////////////////////////////////////////////////////
+
+      sc_signal<int>       r_llsc_fsm;          // FSM state
+      sc_signal<data_t>	   r_llsc_data;		    // read data word
+      sc_signal<uint32_t>  r_llsc_lfsr;         // lfsr for random introducing
+      sc_signal<copy_t>    r_llsc_i_copies;	    // bit_vector of copies
+      sc_signal<copy_t>    r_llsc_d_copies;	    // bit_vector of copies
+      sc_signal<copy_t>    r_llsc_count;	    // number of copies
+      sc_signal<bool>      r_llsc_is_cnt;	    // is_cnt bit (in directory)
+      sc_signal<bool>      r_llsc_dirty;	    // dirty bit (in directory)
+      sc_signal<size_t>    r_llsc_way;		    // way in directory
+      sc_signal<size_t>    r_llsc_set;		    // set in directory
+      sc_signal<data_t>    r_llsc_tag;		    // cache line tag (in directory)
+      sc_signal<size_t>    r_llsc_trt_index;    // Transaction Table index
+      sc_signal<bool>      r_llsc_pass;         // Used to adjust with the VHDL model
+
+      // Buffer between LLSC fsm and INIT_CMD fsm (XRAM read)	
+      sc_signal<bool>	   r_llsc_to_ixr_cmd_req;   // valid request
+      sc_signal<addr_t>	   r_llsc_to_ixr_cmd_nline; // cache line index
+      sc_signal<size_t>	   r_llsc_to_ixr_cmd_trdid; // index in Transaction Table
+
+      // Buffer between LLSC fsm and TGT_RSP fsm
+      sc_signal<bool>	   r_llsc_to_tgt_rsp_req;   // valid request
+      sc_signal<data_t>    r_llsc_to_tgt_rsp_data;  // read data word
+      sc_signal<size_t>	   r_llsc_to_tgt_rsp_srcid; // Transaction srcid
+      sc_signal<size_t>	   r_llsc_to_tgt_rsp_trdid; // Transaction trdid
+      sc_signal<size_t>	   r_llsc_to_tgt_rsp_pktid; // Transaction pktid
+
+      ////////////////////////////////////////////////////
+      // Registers controlled by the IXR_RSP fsm
+      ////////////////////////////////////////////////////
+
+      sc_signal<int> 	   r_ixr_rsp_fsm;       // FSM state
+      sc_signal<size_t>	   r_ixr_rsp_trt_index;	// TRT entry index
+      sc_signal<size_t>    r_ixr_rsp_cpt;	    // word counter
+
+      // Buffer between IXR_RSP fsm and XRAM_RSP fsm  (response from the XRAM)
+      sc_signal<bool>	  *r_ixr_rsp_to_xram_rsp_rok;	// A xram response is ready
+
+      ////////////////////////////////////////////////////
+      // Registers controlled by the XRAM_RSP fsm
+      ////////////////////////////////////////////////////
+
+      sc_signal<int> 	   r_xram_rsp_fsm;		        // FSM state
+      sc_signal<size_t>	   r_xram_rsp_trt_index;	    // TRT entry index
+      TransactionTabEntry  r_xram_rsp_trt_buf;		    // TRT entry local buffer
+      sc_signal<bool>	   r_xram_rsp_victim_inval;	    // victim line invalidate 
+      sc_signal<bool>	   r_xram_rsp_victim_is_cnt;    // victim line inst bit
+      sc_signal<bool>	   r_xram_rsp_victim_dirty;	    // victim line dirty bit
+      sc_signal<size_t>    r_xram_rsp_victim_way;	    // victim line way
+      sc_signal<size_t>    r_xram_rsp_victim_set;	    // victim line set
+      sc_signal<addr_t>    r_xram_rsp_victim_nline;     // victim line index
+      sc_signal<copy_t>    r_xram_rsp_victim_d_copies;	// victim line copies
+      sc_signal<copy_t>    r_xram_rsp_victim_i_copies;	// victim line copies
+      sc_signal<copy_t>    r_xram_rsp_victim_count;	    // victim line number of copies
+      sc_signal<data_t>	  *r_xram_rsp_victim_data;	    // victim line data
+      sc_signal<size_t>	   r_xram_rsp_upt_index;	    // UPT entry index
+      sc_signal<bool>      r_xram_rsp_pass;             // Used to adjust with VHDL model
+
+      // Buffer between XRAM_RSP fsm and TGT_RSP fsm  (response to L1 cache)
+      sc_signal<bool>	   r_xram_rsp_to_tgt_rsp_req;	// Valid request
+      sc_signal<size_t>    r_xram_rsp_to_tgt_rsp_srcid;	// Transaction srcid
+      sc_signal<size_t>    r_xram_rsp_to_tgt_rsp_trdid;	// Transaction trdid
+      sc_signal<size_t>    r_xram_rsp_to_tgt_rsp_pktid;	// Transaction pktid
+      sc_signal<data_t>   *r_xram_rsp_to_tgt_rsp_data;	// data (one cache line)
+      sc_signal<bool>     *r_xram_rsp_to_tgt_rsp_val;	// valid bit (for single word)
+
+      // Buffer between XRAM_RSP fsm and INIT_CMD fsm (Inval L1 Caches) 
+      sc_signal<bool>	   r_xram_rsp_to_init_cmd_req;    // Valid request
+      sc_signal<bool>      r_xram_rsp_to_init_cmd_brdcast;  // Broadcast request
+      sc_signal<addr_t>    r_xram_rsp_to_init_cmd_nline;    // cache line index;
+      sc_signal<size_t>	   r_xram_rsp_to_init_cmd_trdid;    // index of UPT entry
+      sc_signal<copy_t>    r_xram_rsp_to_init_cmd_d_copies; // bit_vector of copies
+      sc_signal<copy_t>    r_xram_rsp_to_init_cmd_i_copies; // bit_vector of copies
+
+      // Buffer between XRAM_RSP fsm and IXR_CMD fsm (XRAM write)
+      sc_signal<bool>	   r_xram_rsp_to_ixr_cmd_req;	// Valid request
+      sc_signal<addr_t>	   r_xram_rsp_to_ixr_cmd_nline;	// cache line index
+      sc_signal<data_t>	  *r_xram_rsp_to_ixr_cmd_data;	// cache line data
+      sc_signal<size_t>	   r_xram_rsp_to_ixr_cmd_trdid;	// index in transaction table
+
+      ////////////////////////////////////////////////////
+      // Registers controlled by the IXR_CMD fsm
+      ////////////////////////////////////////////////////
+
+      sc_signal<int> 	   r_ixr_cmd_fsm;
+      sc_signal<size_t>	   r_ixr_cmd_cpt;
+
+      ////////////////////////////////////////////////////
+      // Registers controlled by TGT_RSP fsm
+      ////////////////////////////////////////////////////
+
+      sc_signal<int> 	   r_tgt_rsp_fsm;
+      sc_signal<size_t>    r_tgt_rsp_cpt;
+
+      ////////////////////////////////////////////////////
+      // Registers controlled by INIT_CMD fsm
+      ////////////////////////////////////////////////////
+
+      sc_signal<int> 	  r_init_cmd_fsm;
+      sc_signal<size_t>   r_init_cmd_cpt;
+      sc_signal<size_t>	  r_init_cmd_target;
+      sc_signal<bool>     r_init_cmd_inst;
+
+      ////////////////////////////////////////////////////
+      // Registers controlled by ALLOC_DIR fsm
+      ////////////////////////////////////////////////////
+
+      sc_signal<int> 		r_alloc_dir_fsm;
+
+      ////////////////////////////////////////////////////
+      // Registers controlled by ALLOC_TRT fsm
+      ////////////////////////////////////////////////////
+
+      sc_signal<int> 		r_alloc_trt_fsm;
+
+      ////////////////////////////////////////////////////
+      // Registers controlled by ALLOC_UPT fsm
+      ////////////////////////////////////////////////////
+
+      sc_signal<int> 		r_alloc_upt_fsm;
+
+    }; // end class VciMemCacheV1
+
+}}
+
+#endif
+
+// Local Variables:
+// tab-width: 4
+// c-basic-offset: 4
+// c-file-offsets:((innamespace . 0)(inline-open . 0))
+// indent-tabs-mode: nil
+// End:
+
+// vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4
+
Index: branches/v4/modules/vci_mem_cache_v1/caba/source/include/xram_transaction_v1.h
===================================================================
--- branches/v4/modules/vci_mem_cache_v1/caba/source/include/xram_transaction_v1.h	(revision 371)
+++ branches/v4/modules/vci_mem_cache_v1/caba/source/include/xram_transaction_v1.h	(revision 371)
@@ -0,0 +1,404 @@
+#ifndef XRAM_TRANSACTION_V1_H_
+#define XRAM_TRANSACTION_V1_H_
+ 
+#include <inttypes.h>
+#include <systemc>
+#include <cassert>
+#include "arithmetics.h"
+
+#define DEBUG_XRAM_TRANSACTION 0
+
+////////////////////////////////////////////////////////////////////////
+//                  A transaction tab entry         
+////////////////////////////////////////////////////////////////////////
+
+class TransactionTabEntry {
+  typedef uint32_t size_t;
+  typedef uint32_t data_t;
+  typedef sc_dt::sc_uint<40> addr_t;
+  typedef uint32_t be_t;
+
+ public:
+  bool 		      valid;     	    // entry valid 
+  bool 		      xram_read; 	    // read request to XRAM
+  addr_t   	      nline;    	    // index (zy) of the requested line
+  size_t 	      srcid;     	    // processor requesting the transaction
+  size_t 	      trdid;     	    // processor requesting the transaction
+  size_t 	      pktid;     	    // processor requesting the transaction
+  bool 		      proc_read;	    // read request from processor
+  bool 		      single_word;   	// single word in case of processor read 
+  size_t 	      word_index;    	// word index in case of single word read
+  std::vector<data_t> wdata;        // write buffer (one cache line)
+  std::vector<be_t>   wdata_be;    	// be for each data in the write buffer
+
+  /////////////////////////////////////////////////////////////////////
+  // The init() function initializes the entry 
+  /////////////////////////////////////////////////////////////////////
+  void init()
+  {
+    valid		= false;
+  }
+
+  /////////////////////////////////////////////////////////////////////
+  // The alloc() function initializes the vectors of an entry
+  // Its arguments are :
+  // - n_words : number of words per line in the cache
+  /////////////////////////////////////////////////////////////////////
+  void alloc(size_t n_words)
+  {
+    wdata_be.reserve( (int)n_words );
+    wdata.reserve( (int)n_words );
+    for(size_t i=0; i<n_words; i++){
+      wdata_be.push_back(false);
+      wdata.push_back(0);
+    }
+  }
+
+  ////////////////////////////////////////////////////////////////////
+  // The copy() function copies an existing entry
+  // Its arguments are :
+  // - source : the transaction tab entry to copy
+  ////////////////////////////////////////////////////////////////////
+  void copy(const TransactionTabEntry &source)
+  {
+    valid	    = source.valid;
+    xram_read 	= source.xram_read;
+    nline	    = source.nline;
+    srcid	    = source.srcid;
+    trdid	    = source.trdid;
+    pktid	    = source.pktid;
+    proc_read 	= source.proc_read;
+    single_word = source.single_word;
+    word_index	= source.word_index;
+    wdata_be.assign(source.wdata_be.begin(),source.wdata_be.end());
+    wdata.assign(source.wdata.begin(),source.wdata.end());	
+  }
+
+  ////////////////////////////////////////////////////////////////////
+  // The print() function prints the entry 
+  ////////////////////////////////////////////////////////////////////
+  void print(){
+    std::cout << "valid       = " << valid             << std::endl;
+    std::cout << "xram_read   = " << xram_read         << std::endl;
+    std::cout << "nline       = " << std::hex << nline << std::endl;
+    std::cout << "srcid       = " << srcid             << std::endl;
+    std::cout << "trdid       = " << trdid             << std::endl;
+    std::cout << "pktid       = " << pktid             << std::endl;
+    std::cout << "proc_read   = " << proc_read         << std::endl;
+    std::cout << "single_word = " << single_word       << std::endl;
+    std::cout << "word_index  = " << word_index        << std::endl; 
+    for(size_t i=0; i<wdata_be.size() ; i++){
+      std::cout << "wdata_be [" << i << "] = " << wdata_be[i] << std::endl;
+    }
+    for(size_t i=0; i<wdata.size() ; i++){
+      std::cout << "wdata [" << i << "] = " << wdata[i] << std::endl;
+    }
+    std::cout << std::endl;
+  }
+
+  /////////////////////////////////////////////////////////////////////
+  // 		Constructors
+  /////////////////////////////////////////////////////////////////////
+
+  TransactionTabEntry()
+    {
+      wdata_be.clear();
+      wdata.clear();
+      valid=false;
+    }
+
+  TransactionTabEntry(const TransactionTabEntry &source){
+    valid	    = source.valid;
+    xram_read	= source.xram_read;
+    nline	    = source.nline;
+    srcid	    = source.srcid;
+    trdid	    = source.trdid;
+    pktid	    = source.pktid;
+    proc_read	= source.proc_read;
+    single_word = source.single_word;
+    word_index	= source.word_index;
+    wdata_be.assign(source.wdata_be.begin(),source.wdata_be.end());
+    wdata.assign(source.wdata.begin(),source.wdata.end());	
+  }
+
+}; // end class TransactionTabEntry
+
+////////////////////////////////////////////////////////////////////////
+//                  The transaction tab                              
+////////////////////////////////////////////////////////////////////////
+class TransactionTab{
+  typedef uint32_t size_t;
+  typedef uint32_t data_t;
+  typedef sc_dt::sc_uint<40> addr_t;
+  typedef uint32_t be_t;
+
+ private:
+  size_t size_tab;                // The size of the tab
+
+  data_t be_to_mask(be_t be)
+  {
+    data_t ret = 0;
+    if ( be&0x1 ) {
+      ret = ret | 0x000000FF;
+    }
+    if ( be&0x2 ) {
+      ret = ret | 0x0000FF00;
+    }
+    if ( be&0x4 ) {
+      ret = ret | 0x00FF0000;
+    }
+    if ( be&0x8 ) {
+      ret = ret | 0xFF000000;
+    }
+    return ret;
+  }
+
+ public:
+  TransactionTabEntry *tab;       // The transaction tab
+
+  ////////////////////////////////////////////////////////////////////
+  //		Constructors
+  ////////////////////////////////////////////////////////////////////
+  TransactionTab()
+    {
+      size_tab=0;
+      tab=NULL;
+    }
+
+  TransactionTab(size_t n_entries, size_t n_words)
+    {
+      size_tab = n_entries;
+      tab = new TransactionTabEntry[size_tab];
+      for ( size_t i=0; i<size_tab; i++) {
+	tab[i].alloc(n_words);
+      }
+    }
+
+  ~TransactionTab()
+    {
+      delete [] tab;
+    }
+
+  /////////////////////////////////////////////////////////////////////
+  // The size() function returns the size of the tab
+  /////////////////////////////////////////////////////////////////////
+  size_t size()
+  {
+    return size_tab;
+  }
+
+  /////////////////////////////////////////////////////////////////////
+  // The init() function initializes the transaction tab entries
+  /////////////////////////////////////////////////////////////////////
+  void init()
+  {
+    for ( size_t i=0; i<size_tab; i++) {
+      tab[i].init();
+    }
+  }
+
+  /////////////////////////////////////////////////////////////////////
+  // The print() function prints a transaction tab entry
+  // Arguments :
+  // - index : the index of the entry to print
+  /////////////////////////////////////////////////////////////////////
+  void print(const size_t index)
+  {
+    assert( (index < size_tab) 
+	    && "Invalid Transaction Tab Entry");
+    tab[index].print();
+    return;
+  }
+
+  /////////////////////////////////////////////////////////////////////
+  // The read() function returns a transaction tab entry.
+  // Arguments :
+  // - index : the index of the entry to read
+  /////////////////////////////////////////////////////////////////////
+  TransactionTabEntry read(const size_t index)
+  {
+    assert( (index < size_tab) 
+	    && "Invalid Transaction Tab Entry");
+    return tab[index];
+  }
+
+  /////////////////////////////////////////////////////////////////////
+  // The full() function returns the state of the transaction tab
+  // Arguments :
+  // - index : (return argument) the index of an empty entry 
+  // The function returns true if the transaction tab is full
+  /////////////////////////////////////////////////////////////////////
+  bool full(size_t &index)
+  {
+    for(size_t i=0; i<size_tab; i++){
+      if(!tab[i].valid){
+	    index=i;
+	    return false;	
+      }
+    }
+    return true;
+  }
+
+  /////////////////////////////////////////////////////////////////////
+  // The hit_read() function checks if an XRAM read transaction exists 
+  // for a given cache line.
+  // Arguments :
+  // - index : (return argument) the index of the hit entry, if there is 
+  // - nline : the index (zy) of the requested line
+  // The function returns true if a read request has already been sent
+  //////////////////////////////////////////////////////////////////////
+  bool hit_read(const addr_t nline,size_t &index)
+  {
+    for(size_t i=0; i<size_tab; i++){
+      if((tab[i].valid && (nline==tab[i].nline)) && (tab[i].xram_read)) {
+	    index=i;
+	    return true;	
+      }
+    }
+    return false;
+  }
+
+  ///////////////////////////////////////////////////////////////////////
+  // The hit_write() function looks if an XRAM write transaction exists 
+  // for a given line.
+  // Arguments :
+  // - nline : the index (zy) of the requested line
+  // The function returns true if a write request has already been sent
+  ///////////////////////////////////////////////////////////////////////
+  bool hit_write(const addr_t nline)
+  {
+    for(size_t i=0; i<size_tab; i++){
+      if(tab[i].valid && (nline==tab[i].nline) && !(tab[i].xram_read)) {
+	    return true;	
+      }
+    }
+    return false;
+  }
+
+  /////////////////////////////////////////////////////////////////////
+  // The write_data_mask() function writes a vector of data (a line).
+  // The data is written only if the corresponding bits are set
+  // in the be vector. 
+  // Arguments :
+  // - index : the index of the request in the transaction tab
+  // - be   : vector of be 
+  // - data : vector of data
+  /////////////////////////////////////////////////////////////////////
+  void write_data_mask(const size_t index, 
+		       const std::vector<be_t> &be, 
+		       const std::vector<data_t> &data) 
+  {
+    assert( (index < size_tab) 
+	    && "Invalid Transaction Tab Entry");
+    assert(be.size()==tab[index].wdata_be.size() 
+	   && "Bad data mask in write_data_mask in TransactionTab");
+    assert(data.size()==tab[index].wdata.size() 
+	   && "Bad data in write_data_mask in TransactionTab");
+
+    for(size_t i=0; i<tab[index].wdata_be.size() ; i++) {
+      tab[index].wdata_be[i] = tab[index].wdata_be[i] | be[i];
+      data_t mask = be_to_mask(be[i]);
+      tab[index].wdata[i] = (tab[index].wdata[i] & ~mask) | (data[i] & mask);
+    }
+  }
+
+  /////////////////////////////////////////////////////////////////////
+  // The set() function registers a transaction (read or write)
+  // to the XRAM in the transaction tab.
+  // Arguments :
+  // - index : index in the transaction tab
+  // - xram_read : transaction type (read or write a cache line)
+  // - nline : the index (zy) of the cache line
+  // - srcid : srcid of the initiator that caused the transaction
+  // - trdid : trdid of the initiator that caused the transaction
+  // - pktid : pktid of the initiator that caused the transaction
+  // - proc_read : does the initiator want a copy
+  // - single_word : single word read (in case of processor read)
+  // - word_index : index in the line (in case of single word read)
+  // - data : the data to write (in case of write)
+  // - data_be : the mask of the data to write (in case of write)
+  /////////////////////////////////////////////////////////////////////
+  void set(const size_t index,
+	   const bool xram_read,
+	   const addr_t nline,
+	   const size_t srcid,
+	   const size_t trdid,
+	   const size_t pktid,
+	   const bool proc_read,
+	   const bool single_word,
+	   const size_t word_index,
+	   const std::vector<be_t> &data_be,
+	   const std::vector<data_t> &data) 
+  {
+    assert( (index < size_tab) 
+	    && "The selected entry is out of range in set() Transaction Tab");
+    assert(data_be.size()==tab[index].wdata_be.size() 
+	   && "Bad data_be argument in set() TransactionTab");
+    assert(data.size()==tab[index].wdata.size() 
+	   && "Bad data argument in set() TransactionTab");
+
+    tab[index].valid	        = true;
+    tab[index].xram_read        = xram_read;
+    tab[index].nline	        = nline;
+    tab[index].srcid	        = srcid;
+    tab[index].trdid	        = trdid;
+    tab[index].pktid	        = pktid;
+    tab[index].proc_read	    = proc_read;
+    tab[index].single_word	    = single_word;
+    tab[index].word_index	    = word_index;
+    for(size_t i=0; i<tab[index].wdata.size(); i++) {
+      tab[index].wdata_be[i]    = data_be[i];
+      tab[index].wdata[i]       = data[i];
+    }
+  }
+
+  /////////////////////////////////////////////////////////////////////
+  // The write_rsp() function writes a word of the response to an 
+  // XRAM read transaction.
+  // The data is only written when the corresponding BE field is Ox0.
+  // Arguments :
+  // - index : the index of the transaction in the transaction tab
+  // - word_index : the index of the data in the line
+  // - data : the data to write
+  /////////////////////////////////////////////////////////////////////
+  void write_rsp(const size_t index,
+		 const size_t word,
+		 const data_t data)
+  {
+    assert( (index < size_tab) 
+	    && "Selected entry  out of range in write_rsp() Transaction Tab");
+    assert( (word <= tab[index].wdata_be.size()) 
+	    && "Bad word_index in write_rsp() in TransactionTab");
+    assert( tab[index].valid 
+	    && "Transaction Tab Entry invalid in write_rsp()");
+    assert( tab[index].xram_read 
+	    && "Selected entry is not an XRAM read transaction in write_rsp()");
+
+    data_t mask = be_to_mask(tab[index].wdata_be[word]);
+    tab[index].wdata[word] = (tab[index].wdata[word] & mask) | (data & ~mask);
+  }
+
+  /////////////////////////////////////////////////////////////////////
+  // The erase() function erases an entry in the transaction tab.
+  // Arguments :
+  // - index : the index of the request in the transaction tab
+  /////////////////////////////////////////////////////////////////////
+  void erase(const size_t index)
+  {
+    assert( (index < size_tab) 
+	    && "The selected entry is out of range in erase() Transaction Tab");
+    tab[index].valid	= false;
+  }
+}; // end class TransactionTab
+
+#endif
+
+// Local Variables:
+// tab-width: 4
+// c-basic-offset: 4
+// c-file-offsets:((innamespace . 0)(inline-open . 0))
+// indent-tabs-mode: nil
+// End:
+
+// vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4
+
Index: branches/v4/modules/vci_mem_cache_v1/caba/source/src/vci_mem_cache_v1.cpp
===================================================================
--- branches/v4/modules/vci_mem_cache_v1/caba/source/src/vci_mem_cache_v1.cpp	(revision 371)
+++ branches/v4/modules/vci_mem_cache_v1/caba/source/src/vci_mem_cache_v1.cpp	(revision 371)
@@ -0,0 +1,3726 @@
+/* -*- c++ -*-
+ * File 	: vci_mem_cache_v1.cpp
+ * Date 	: 30/10/2008
+ * Copyright 	: UPMC / LIP6
+ * Authors 	: Alain Greiner / Eric Guthmuller
+ *
+ * SOCLIB_LGPL_HEADER_BEGIN
+ *
+ * This file is part of SoCLib, GNU LGPLv2.1.
+ *
+ * SoCLib is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU Lesser General Public License as published
+ * by the Free Software Foundation; version 2.1 of the License.
+ *
+ * SoCLib is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with SoCLib; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301 USA
+ *
+ * SOCLIB_LGPL_HEADER_END
+ *
+ * Maintainers: alain eric.guthmuller@polytechnique.edu choichillon.christophe@gmail.com
+ */
+#include "../include/vci_mem_cache_v1.h"
+
+//#define IDEBUG
+//#define DEBUG_VCI_MEM_CACHE 2
+#define RANDOMIZE_SC
+#define VHDL_ACCURATE
+//#define DEBUG_CLEANUP
+
+namespace soclib { namespace caba {
+
+#ifdef DEBUG_VCI_MEM_CACHE 
+  const char *tgt_cmd_fsm_str[] = {
+    "TGT_CMD_IDLE",
+    "TGT_CMD_READ",
+    "TGT_CMD_READ_EOP",
+    "TGT_CMD_WRITE",
+    "TGT_CMD_ATOMIC",
+  };
+  const char *tgt_rsp_fsm_str[] = {
+    "TGT_RSP_READ_IDLE",
+    "TGT_RSP_WRITE_IDLE",
+    "TGT_RSP_LLSC_IDLE",
+    "TGT_RSP_XRAM_IDLE",
+    "TGT_RSP_INIT_IDLE",
+    "TGT_RSP_CLEANUP_IDLE",
+    "TGT_RSP_READ_TEST",
+    "TGT_RSP_READ_WORD",
+    "TGT_RSP_READ_LINE",
+    "TGT_RSP_WRITE",
+    "TGT_RSP_LLSC",
+    "TGT_RSP_XRAM_TEST",
+    "TGT_RSP_XRAM_WORD",
+    "TGT_RSP_XRAM_LINE",
+    "TGT_RSP_INIT",
+    "TGT_RSP_CLEANUP",
+  };
+  const char *init_cmd_fsm_str[] = {
+    "INIT_CMD_INVAL_IDLE",
+    "INIT_CMD_INVAL_SEL",
+    "INIT_CMD_INVAL_NLINE",
+    "INIT_CMD_UPDT_IDLE",
+    "INIT_CMD_UPDT_SEL",
+    "INIT_CMD_BRDCAST",
+    "INIT_CMD_UPDT_NLINE",
+    "INIT_CMD_UPDT_INDEX",
+    "INIT_CMD_UPDT_DATA",
+  };
+  const char *init_rsp_fsm_str[] = {
+    "INIT_RSP_IDLE",
+    "INIT_RSP_UPT_LOCK",
+    "INIT_RSP_UPT_CLEAR",
+    "INIT_RSP_END",
+  };
+  const char *read_fsm_str[] = {
+    "READ_IDLE",
+    "READ_DIR_LOCK",
+    "READ_DIR_HIT",
+    "READ_RSP",
+    "READ_TRT_LOCK",
+    "READ_TRT_SET",
+    "READ_XRAM_REQ",
+  };
+  const char *write_fsm_str[] = {
+    "WRITE_IDLE",
+    "WRITE_NEXT",
+    "WRITE_DIR_LOCK",
+    "WRITE_DIR_HIT_READ",
+    "WRITE_DIR_HIT",
+    "WRITE_DIR_HIT_RSP",
+    "WRITE_UPT_LOCK",
+    "WRITE_WAIT_UPT",
+    "WRITE_UPDATE",
+    "WRITE_RSP",
+    "WRITE_TRT_LOCK",
+    "WRITE_TRT_DATA",
+    "WRITE_TRT_SET",
+    "WRITE_WAIT_TRT",
+    "WRITE_XRAM_REQ",
+    "WRITE_TRT_WRITE_LOCK",
+    "WRITE_INVAL_LOCK",
+    "WRITE_DIR_INVAL",
+    "WRITE_INVAL",
+    "WRITE_XRAM_SEND"
+#ifdef VHDL_ACCURATE
+    , "WRITE_RESET"
+#endif
+  };
+  const char *ixr_rsp_fsm_str[] = {
+    "IXR_RSP_IDLE",
+    "IXR_RSP_ACK",
+    "IXR_RSP_TRT_ERASE",
+    "IXR_RSP_TRT_READ",
+  };
+  const char *xram_rsp_fsm_str[] = {
+    "XRAM_RSP_IDLE",
+    "XRAM_RSP_TRT_COPY",
+    "XRAM_RSP_TRT_DIRTY",
+    "XRAM_RSP_DIR_LOCK",
+    "XRAM_RSP_DIR_UPDT",
+    "XRAM_RSP_DIR_RSP",
+    "XRAM_RSP_INVAL_LOCK",
+    "XRAM_RSP_INVAL_WAIT",
+    "XRAM_RSP_INVAL",
+    "XRAM_RSP_WRITE_DIRTY",
+  };
+  const char *ixr_cmd_fsm_str[] = {
+    "IXR_CMD_READ_IDLE",
+    "IXR_CMD_WRITE_IDLE",
+    "IXR_CMD_LLSC_IDLE",
+    "IXR_CMD_XRAM_IDLE",
+    "IXR_CMD_READ_NLINE",
+    "IXR_CMD_WRITE_NLINE",
+    "IXR_CMD_LLSC_NLINE",
+    "IXR_CMD_XRAM_DATA",
+  };
+  const char *llsc_fsm_str[] = {
+    "LLSC_IDLE",
+    "LL_DIR_LOCK",
+    "LL_DIR_HIT",
+    "LL_RSP",
+    "SC_DIR_LOCK",
+    "SC_DIR_HIT",
+    "SC_RSP_FALSE",
+    "SC_RSP_TRUE",
+    "LLSC_TRT_LOCK",
+    "LLSC_TRT_SET",
+    "LLSC_XRAM_REQ",
+  };
+  const char *cleanup_fsm_str[] = {
+    "CLEANUP_IDLE",
+    "CLEANUP_DIR_LOCK",
+    "CLEANUP_DIR_WRITE",
+    "CLEANUP_UPT_LOCK",
+    "CLEANUP_UPT_WRITE",
+    "CLEANUP_WRITE_RSP",
+    "CLEANUP_RSP",
+  };
+  const char *alloc_dir_fsm_str[] = {
+    "ALLOC_DIR_READ",
+    "ALLOC_DIR_WRITE",
+    "ALLOC_DIR_LLSC",
+    "ALLOC_DIR_CLEANUP",
+    "ALLOC_DIR_XRAM_RSP",
+  };
+  const char *alloc_trt_fsm_str[] = {
+    "ALLOC_TRT_READ",
+    "ALLOC_TRT_WRITE",
+    "ALLOC_TRT_LLSC",
+    "ALLOC_TRT_XRAM_RSP",
+    "ALLOC_TRT_IXR_RSP",
+  };
+  const char *alloc_upt_fsm_str[] = {
+    "ALLOC_UPT_WRITE",
+    "ALLOC_UPT_XRAM_RSP",
+    "ALLOC_UPT_INIT_RSP",
+    "ALLOC_UPT_CLEANUP",
+  };
+#endif
+
+#define tmpl(x) template<typename vci_param> x VciMemCacheV1<vci_param>
+
+  using soclib::common::uint32_log2;
+
+  ////////////////////////////////
+  // 	Constructor 
+  ////////////////////////////////
+
+  tmpl(/**/)::VciMemCacheV1( 
+      sc_module_name name,
+      const soclib::common::MappingTable &mtp,
+      const soclib::common::MappingTable &mtc,
+      const soclib::common::MappingTable &mtx,
+      const soclib::common::IntTab &vci_ixr_index,
+      const soclib::common::IntTab &vci_ini_index,
+      const soclib::common::IntTab &vci_tgt_index,
+      const soclib::common::IntTab &vci_tgt_index_cleanup,
+      size_t nways,
+      size_t nsets,
+      size_t nwords)
+
+    : soclib::caba::BaseModule(name),
+
+    p_clk("clk"),
+    p_resetn("resetn"),
+    p_vci_tgt("vci_tgt"),
+    p_vci_tgt_cleanup("vci_tgt_cleanup"),
+    p_vci_ini("vci_ini"),
+    p_vci_ixr("vci_ixr"),
+
+    m_initiators( 32 ),
+    m_ways( nways ),
+    m_sets( nsets ),
+    m_words( nwords ),
+    m_srcid_ixr( mtx.indexForId(vci_ixr_index) ),
+    m_srcid_ini( mtc.indexForId(vci_ini_index) ),
+    m_seglist(mtp.getSegmentList(vci_tgt_index)),
+    m_cseglist(mtc.getSegmentList(vci_tgt_index_cleanup)),
+    m_coherence_table( mtc.getCoherenceTable<vci_addr_t>() ),
+    m_atomic_tab( m_initiators ),
+    m_transaction_tab( TRANSACTION_TAB_LINES, nwords ),
+    m_update_tab( UPDATE_TAB_LINES ),
+    m_cache_directory( nways, nsets, nwords, vci_param::N ),
+#define L2 soclib::common::uint32_log2
+    m_x( L2(m_words), 2),
+    m_y( L2(m_sets), L2(m_words) + 2),
+    m_z( vci_param::N - L2(m_sets) - L2(m_words) - 2, L2(m_sets) + L2(m_words) + 2),
+    m_nline( vci_param::N - L2(m_words) - 2, L2(m_words) + 2),
+#undef L2
+
+    //  FIFOs 
+    m_cmd_read_addr_fifo("m_cmd_read_addr_fifo", 4),
+    m_cmd_read_word_fifo("m_cmd_read_word_fifo", 4),
+    m_cmd_read_srcid_fifo("m_cmd_read_srcid_fifo", 4),
+    m_cmd_read_trdid_fifo("m_cmd_read_trdid_fifo", 4),
+    m_cmd_read_pktid_fifo("m_cmd_read_pktid_fifo", 4),
+
+    m_cmd_write_addr_fifo("m_cmd_write_addr_fifo",8),
+    m_cmd_write_eop_fifo("m_cmd_write_eop_fifo",8),
+    m_cmd_write_srcid_fifo("m_cmd_write_srcid_fifo",8),
+    m_cmd_write_trdid_fifo("m_cmd_write_trdid_fifo",8),
+    m_cmd_write_pktid_fifo("m_cmd_write_pktid_fifo",8),
+    m_cmd_write_data_fifo("m_cmd_write_data_fifo",8),
+    m_cmd_write_be_fifo("m_cmd_write_be_fifo",8),
+
+    m_cmd_llsc_addr_fifo("m_cmd_llsc_addr_fifo",4),
+    m_cmd_llsc_sc_fifo("m_cmd_llsc_sc_fifo",4),
+    m_cmd_llsc_srcid_fifo("m_cmd_llsc_srcid_fifo",4),
+    m_cmd_llsc_trdid_fifo("m_cmd_llsc_trdid_fifo",4),
+    m_cmd_llsc_pktid_fifo("m_cmd_llsc_pktid_fifo",4),
+    m_cmd_llsc_wdata_fifo("m_cmd_llsc_wdata_fifo",4),
+
+    r_tgt_cmd_fsm("r_tgt_cmd_fsm"),
+    nseg(0),	
+    ncseg(0),	
+    r_read_fsm("r_read_fsm"),
+    r_write_fsm("r_write_fsm"),
+    r_init_rsp_fsm("r_init_rsp_fsm"),
+    r_cleanup_fsm("r_cleanup_fsm"),
+    r_llsc_fsm("r_llsc_fsm"),
+    r_ixr_rsp_fsm("r_ixr_rsp_fsm"),
+    r_xram_rsp_fsm("r_xram_rsp_fsm"),
+    r_ixr_cmd_fsm("r_ixr_cmd_fsm"),
+    r_tgt_rsp_fsm("r_tgt_rsp_fsm"),
+    r_init_cmd_fsm("r_init_cmd_fsm"),
+    r_alloc_dir_fsm("r_alloc_dir_fsm"),
+    r_alloc_trt_fsm("r_alloc_trt_fsm"),
+    r_alloc_upt_fsm("r_alloc_upt_fsm")
+    {
+      assert(IS_POW_OF_2(nsets));
+      assert(IS_POW_OF_2(nwords));
+      assert(IS_POW_OF_2(nways));
+      assert(nsets);
+      assert(nwords);
+      assert(nways);
+      assert(nsets <= 1024);
+      assert(nwords <= 32);
+      assert(nways <= 32);
+
+      m_broadcast_address = 0x3 | (0x7C1F << (vci_param::N-20));
+
+      // Get the segments associated to the MemCache 
+      std::list<soclib::common::Segment>::iterator seg;
+
+      for(seg = m_seglist.begin(); seg != m_seglist.end() ; seg++) {
+        nseg++;
+      }
+      for(seg = m_cseglist.begin(); seg != m_cseglist.end() ; seg++) {
+        ncseg++;
+      }
+
+      m_seg = new soclib::common::Segment*[nseg];
+      size_t i = 0;
+      for ( seg = m_seglist.begin() ; seg != m_seglist.end() ; seg++ ) { 
+        m_seg[i] = &(*seg);
+        i++;
+      }
+      m_cseg = new soclib::common::Segment*[ncseg];
+      i = 0;
+      for ( seg = m_cseglist.begin() ; seg != m_cseglist.end() ; seg++ ) { 
+          m_cseg[i] = &(*seg);
+          i++;
+      }
+
+      // Memory cache allocation & initialisation
+      m_cache_data = new data_t**[nways];
+      for ( size_t i=0 ; i<nways ; ++i ) {
+        m_cache_data[i] = new data_t*[nsets];
+      }
+      for ( size_t i=0; i<nways; ++i ) {
+        for ( size_t j=0; j<nsets; ++j ) {
+          m_cache_data[i][j] = new data_t[nwords];
+          for ( size_t k=0; k<nwords; k++){
+            m_cache_data[i][j][k]=0;
+          }	
+        }
+      }
+
+      // Allocation for IXR_RSP FSM
+      r_ixr_rsp_to_xram_rsp_rok	    = new sc_signal<bool>[TRANSACTION_TAB_LINES];
+
+      // Allocation for XRAM_RSP FSM
+      r_xram_rsp_victim_data        = new sc_signal<data_t>[nwords];
+      r_xram_rsp_to_tgt_rsp_data    = new sc_signal<data_t>[nwords];
+      r_xram_rsp_to_tgt_rsp_val     = new sc_signal<bool>[nwords];
+      r_xram_rsp_to_ixr_cmd_data    = new sc_signal<data_t>[nwords];
+
+      // Allocation for READ FSM
+      r_read_data 			        = new sc_signal<data_t>[nwords];
+      r_read_to_tgt_rsp_data 		= new sc_signal<data_t>[nwords];
+      r_read_to_tgt_rsp_val 		= new sc_signal<bool>[nwords];
+
+      // Allocation for WRITE FSM
+      r_write_data 			        = new sc_signal<data_t>[nwords];
+      r_write_be 			        = new sc_signal<be_t>[nwords];
+      r_write_to_init_cmd_data 		= new sc_signal<data_t>[nwords];
+      r_write_to_init_cmd_we		= new sc_signal<bool>[nwords];
+      r_write_to_ixr_cmd_data	    = new sc_signal<data_t>[nwords];
+
+      // Simulation
+
+      SC_METHOD(transition);
+      dont_initialize();
+      sensitive << p_clk.pos();
+
+      SC_METHOD(genMoore);
+      dont_initialize();
+      sensitive << p_clk.neg();
+
+    } // end constructor
+
+  /////////////////////////////////////////
+  // This function prints the statistics 
+  /////////////////////////////////////////
+
+  tmpl(void)::print_stats()
+  {
+    std::cout << "----------------------------------" << std::dec << std::endl;
+    std::cout << "MEM_CACHE " << m_srcid_ini << " / Time = " << m_cpt_cycles << std::endl
+      << "- READ RATE            = " << (double)m_cpt_read/m_cpt_cycles << std::endl
+      << "- READ MISS RATE       = " << (double)m_cpt_read_miss/m_cpt_read << std::endl
+      << "- WRITE RATE           = " << (double)m_cpt_write/m_cpt_cycles << std::endl
+      << "- WRITE MISS RATE      = " << (double)m_cpt_write_miss/m_cpt_write << std::endl
+      << "- WRITE BURST LENGTH   = " << (double)m_cpt_write_cells/m_cpt_write << std::endl
+      << "- UPDATE RATE          = " << (double)m_cpt_update/m_cpt_cycles << std::endl
+      << "- UPDATE ARITY         = " << (double)m_cpt_update_mult/m_cpt_update << std::endl
+      << "- INVAL MULTICAST RATE = " << (double)(m_cpt_inval-m_cpt_inval_brdcast)/m_cpt_cycles << std::endl
+      << "- INVAL MULTICAST ARITY= " << (double)m_cpt_inval_mult/(m_cpt_inval-m_cpt_inval_brdcast) << std::endl
+      << "- INVAL BROADCAST RATE = " << (double)m_cpt_inval_brdcast/m_cpt_cycles << std::endl
+      << "- SAVE DIRTY RATE      = " << (double)m_cpt_write_dirty/m_cpt_cycles << std::endl
+      << "- CLEANUP RATE         = " << (double)m_cpt_cleanup/m_cpt_cycles << std::endl
+      << "- LL RATE              = " << (double)m_cpt_ll/m_cpt_cycles << std::endl
+      << "- SC RATE              = " << (double)m_cpt_sc/m_cpt_cycles << std::endl;
+  }
+
+  /////////////////////////////////
+  tmpl(/**/)::~VciMemCacheV1()
+    /////////////////////////////////
+  {
+    for(size_t i=0; i<m_ways ; i++){
+      for(size_t j=0; j<m_sets ; j++){
+        delete [] m_cache_data[i][j];
+      }
+    }
+    for(size_t i=0; i<m_ways ; i++){
+      delete [] m_cache_data[i];
+    }
+    delete [] m_cache_data;
+    delete [] m_coherence_table;
+
+    delete [] r_ixr_rsp_to_xram_rsp_rok;
+
+    delete [] r_xram_rsp_victim_data;
+    delete [] r_xram_rsp_to_tgt_rsp_data;
+    delete [] r_xram_rsp_to_tgt_rsp_val;
+    delete [] r_xram_rsp_to_ixr_cmd_data;
+
+    delete [] r_read_data;
+    delete [] r_read_to_tgt_rsp_data;
+    delete [] r_read_to_tgt_rsp_val;
+
+    delete [] r_write_data;
+    delete [] r_write_be;
+    delete [] r_write_to_init_cmd_data;
+  }
+
+  //////////////////////////////////
+  tmpl(void)::transition()
+    //////////////////////////////////
+  {
+    using soclib::common::uint32_log2;
+    //  RESET          
+    if ( ! p_resetn.read() ) {
+
+      //     Initializing FSMs
+      r_tgt_cmd_fsm 	= TGT_CMD_IDLE;
+      r_tgt_rsp_fsm 	= TGT_RSP_READ_IDLE;
+      r_init_cmd_fsm 	= INIT_CMD_INVAL_IDLE;
+      r_init_rsp_fsm 	= INIT_RSP_IDLE;
+      r_read_fsm        = READ_IDLE;
+
+#ifdef VHDL_ACCURATE
+      r_write_fsm       = WRITE_RESET;
+      r_alloc_dir_fsm   = ALLOC_DIR_WRITE;
+#else
+      r_write_fsm       = WRITE_IDLE;
+      r_alloc_dir_fsm   = ALLOC_DIR_READ;
+#endif
+
+      r_llsc_fsm        = LLSC_IDLE;
+      r_cleanup_fsm 	  = CLEANUP_IDLE;
+
+      r_alloc_trt_fsm   = ALLOC_TRT_READ;
+      r_alloc_upt_fsm   = ALLOC_UPT_WRITE;
+      r_ixr_rsp_fsm 	= IXR_RSP_IDLE;
+      r_xram_rsp_fsm 	= XRAM_RSP_IDLE;
+      r_ixr_cmd_fsm 	= IXR_CMD_READ_IDLE;
+
+      //  Initializing Tables
+      //  The Directory is initialized in the WRITE RESET state
+      //  in the VHDL ACCURATE model
+#ifndef VHDL_ACCURATE
+      m_cache_directory.init();
+#endif
+      m_atomic_tab.init();	
+      m_transaction_tab.init();
+
+      // initializing FIFOs and communication Buffers
+
+      m_cmd_read_addr_fifo.init();
+      m_cmd_read_word_fifo.init();
+      m_cmd_read_srcid_fifo.init();
+      m_cmd_read_trdid_fifo.init();
+      m_cmd_read_pktid_fifo.init();
+
+      m_cmd_write_addr_fifo.init();
+      m_cmd_write_eop_fifo.init();
+      m_cmd_write_srcid_fifo.init();
+      m_cmd_write_trdid_fifo.init();
+      m_cmd_write_pktid_fifo.init();
+      m_cmd_write_data_fifo.init();
+
+      m_cmd_llsc_addr_fifo.init();
+      m_cmd_llsc_srcid_fifo.init();
+      m_cmd_llsc_trdid_fifo.init();
+      m_cmd_llsc_pktid_fifo.init();
+      m_cmd_llsc_wdata_fifo.init();
+      m_cmd_llsc_sc_fifo.init();
+
+      r_read_to_tgt_rsp_req	    = false;
+      r_read_to_ixr_cmd_req	    = false;
+
+      r_write_to_tgt_rsp_req	= false;
+      r_write_to_ixr_cmd_req	= false;
+      r_write_to_init_cmd_req	= false;
+
+      r_cleanup_to_tgt_rsp_req	= false;
+
+      r_init_rsp_to_tgt_rsp_req	= false;
+
+      r_llsc_lfsr                       = -1;
+      r_llsc_to_tgt_rsp_req	    = false;
+      r_llsc_to_ixr_cmd_req	    = false;
+
+      for(size_t i=0; i<TRANSACTION_TAB_LINES ; i++){
+        r_ixr_rsp_to_xram_rsp_rok[i] = false;
+      }
+
+      r_xram_rsp_to_tgt_rsp_req	    = false;
+      r_xram_rsp_to_init_cmd_req    = false;
+      r_xram_rsp_to_ixr_cmd_req	    = false;
+      r_xram_rsp_trt_index	        = 0;
+
+      r_ixr_cmd_cpt         = 0;
+
+      r_copies_limit        = 3;
+
+      // Initialize WRITE FSM registers
+      r_write_way     = 0;
+      r_write_address	= 0;
+
+      // Activity counters
+      m_cpt_cycles		    = 0;
+      m_cpt_read		    = 0;
+      m_cpt_read_miss	    = 0;
+      m_cpt_write		    = 0;
+      m_cpt_write_miss	    = 0;
+      m_cpt_write_cells	    = 0;
+      m_cpt_write_dirty	    = 0;
+      m_cpt_update		    = 0;
+      m_cpt_update_mult     = 0;
+      m_cpt_inval_brdcast 	= 0;
+      m_cpt_inval 		    = 0;
+      m_cpt_inval_mult 		= 0;
+      m_cpt_cleanup		    = 0;
+      m_cpt_ll     		    = 0;
+      m_cpt_sc     		    = 0;
+
+      return;
+    }
+
+    bool    cmd_read_fifo_put = false;
+    bool    cmd_read_fifo_get = false;
+
+    bool    cmd_write_fifo_put = false;
+    bool    cmd_write_fifo_get = false;
+
+    bool    cmd_llsc_fifo_put = false;
+    bool    cmd_llsc_fifo_get = false;
+
+#if DEBUG_VCI_MEM_CACHE == 1
+    std::cout << "---------------------------------------------" << std::dec << std::endl;
+    std::cout << "MEM_CACHE " << m_srcid_ini << " ; Time = " << m_cpt_cycles << std::endl
+      << " - TGT_CMD FSM   = " << tgt_cmd_fsm_str[r_tgt_cmd_fsm] << std::endl
+      << " - TGT_RSP FSM   = " << tgt_rsp_fsm_str[r_tgt_rsp_fsm] << std::endl
+      << " - INIT_CMD FSM  = " << init_cmd_fsm_str[r_init_cmd_fsm] << std::endl
+      << " - INIT_RSP FSM  = " << init_rsp_fsm_str[r_init_rsp_fsm] << std::endl
+      << " - READ FSM      = " << read_fsm_str[r_read_fsm] << std::endl
+      << " - WRITE FSM     = " << write_fsm_str[r_write_fsm] << std::endl
+      << " - LLSC FSM      = " << llsc_fsm_str[r_llsc_fsm] << std::endl
+      << " - CLEANUP FSM   = " << cleanup_fsm_str[r_cleanup_fsm] << std::endl
+      << " - IXR_CMD FSM   = " << ixr_cmd_fsm_str[r_ixr_cmd_fsm] << std::endl
+      << " - IXR_RSP FSM   = " << ixr_rsp_fsm_str[r_ixr_rsp_fsm] << std::endl
+      << " - XRAM_RSP FSM  = " << xram_rsp_fsm_str[r_xram_rsp_fsm] << std::endl
+      << " - ALLOC_DIR FSM = " << alloc_dir_fsm_str[r_alloc_dir_fsm] << std::endl
+      << " - ALLOC_TRT FSM = " << alloc_trt_fsm_str[r_alloc_trt_fsm] << std::endl
+      << " - ALLOC_UPT FSM = " << alloc_upt_fsm_str[r_alloc_upt_fsm] << std::endl;
+#elif DEBUG_VCI_MEM_CACHE == 2
+    std::cout << "---------------------------------------------" << std::dec << std::endl;
+    std::cout << "MEM_CACHE " << m_srcid_ini << " ; Time = " << m_cpt_cycles << std::endl
+      << " - TGT_CMD FSM   = " << tgt_cmd_fsm_str[r_tgt_cmd_fsm] << std::endl
+      << " - TGT_RSP FSM   = " << tgt_rsp_fsm_str[r_tgt_rsp_fsm] << std::endl
+      << " - INIT_CMD FSM  = " << init_cmd_fsm_str[r_init_cmd_fsm] << std::endl
+      << " - INIT_RSP FSM  = " << init_rsp_fsm_str[r_init_rsp_fsm] << std::endl
+      << " - READ FSM      = " << read_fsm_str[r_read_fsm] << std::endl
+      << " - WRITE FSM     = " << write_fsm_str[r_write_fsm] << std::endl
+      << " - LLSC FSM      = " << llsc_fsm_str[r_llsc_fsm] << std::endl
+      << " - CLEANUP FSM   = " << cleanup_fsm_str[r_cleanup_fsm] << std::endl
+      << " - IXR_CMD FSM   = " << ixr_cmd_fsm_str[r_ixr_cmd_fsm] << std::endl
+      << " - IXR_RSP FSM   = " << ixr_rsp_fsm_str[r_ixr_rsp_fsm] << std::endl
+      << " - XRAM_RSP FSM  = " << xram_rsp_fsm_str[r_xram_rsp_fsm] << std::endl
+      << " - ALLOC_DIR FSM = " << alloc_dir_fsm_str[r_alloc_dir_fsm] << std::endl
+      << " - ALLOC_TRT FSM = " << alloc_trt_fsm_str[r_alloc_trt_fsm] << std::endl
+      << " - ALLOC_UPT FSM = " << alloc_upt_fsm_str[r_alloc_upt_fsm] << std::endl;
+    std::cout << " - UPDATE/INVAL TABLE : " << std::endl;
+    m_update_tab.print();
+    std::cout << " - TRANSACTION TABLE = : " << std::endl;
+    for (unsigned int i = 0 ; i < m_transaction_tab.size() ; i++){
+      m_transaction_tab.print(i);
+    }
+#endif
+
+
+
+    ////////////////////////////////////////////////////////////////////////////////////
+    //		TGT_CMD FSM
+    ////////////////////////////////////////////////////////////////////////////////////
+    // The TGT_CMD_FSM controls the incoming VCI command pakets from the processors
+    //
+    // There is 4 types of packets for the m_mem_segment :
+    // - READ    : a READ request has a length of 1 VCI cell. It can be a single word 
+    //             or an entire cache line, depending on the PLEN value.
+    // - WRITE   : a WRITE request has a maximum length of 16 cells, and can only
+    //             concern words in a same line.
+    // - LL      : The LL request has a length of 1 cell.
+    // - SC      : The SC request has a length of 1 cell. 
+    //             The WDATA field contains the data to write.
+    //
+    ////////////////////////////////////////////////////////////////////////////////////
+
+    switch ( r_tgt_cmd_fsm.read() ) {
+
+      //////////////////
+      case TGT_CMD_IDLE:
+        {
+          if ( p_vci_tgt.cmdval ) {
+            assert( (p_vci_tgt.srcid.read() < m_initiators)
+                && "VCI_MEM_CACHE error in VCI_MEM_CACHE : The received SRCID is larger than 31");
+
+            bool reached = false;
+            for ( size_t index = 0 ; index < nseg && !reached ; index++) 
+            {
+//              if ( m_seg[index]->contains((addr_t)(p_vci_tgt.address.read())) ) {
+              if ( m_seg[index]->contains(p_vci_tgt.address.read()) ) {
+                reached = true;
+                r_index = index;
+              }
+            }
+
+
+            if ( !reached ) 
+            { 
+              std::cout << "VCI_MEM_CACHE Out of segment access in VCI_MEM_CACHE" << std::endl;
+              std::cout << "Faulty address = " << std::hex << (addr_t)(p_vci_tgt.address.read()) << std::endl;
+              std::cout << "Faulty initiator = " << std::dec << p_vci_tgt.srcid.read() << std::endl;
+              exit(0);
+            } 
+            else if ( p_vci_tgt.cmd.read() == vci_param::CMD_READ ) 
+            {
+              r_tgt_cmd_fsm = TGT_CMD_READ;
+            } 
+            else if (( p_vci_tgt.cmd.read() == vci_param::CMD_WRITE )) //&& ( p_vci_tgt.trdid.read() == 0x0 ))
+            {  
+              r_tgt_cmd_fsm = TGT_CMD_WRITE;
+            } 
+            else if ((p_vci_tgt.cmd.read() == vci_param::CMD_LOCKED_READ) || 
+                (p_vci_tgt.cmd.read() == vci_param::CMD_STORE_COND) ) 
+            {
+              r_tgt_cmd_fsm = TGT_CMD_ATOMIC;
+            } 
+          }
+          break;
+        }
+        //////////////////
+      case TGT_CMD_READ:
+
+        {
+          assert(((p_vci_tgt.plen.read() == 4) || (p_vci_tgt.plen.read() == m_words*4))
+              && "VCI_MEM_CACHE All read request to the MemCache must have PLEN = 4 or PLEN = 4*nwords"); 
+
+          if ( p_vci_tgt.cmdval && m_cmd_read_addr_fifo.wok() ) {
+            cmd_read_fifo_put = true;
+            if ( p_vci_tgt.eop )  r_tgt_cmd_fsm = TGT_CMD_IDLE;
+            else                  r_tgt_cmd_fsm = TGT_CMD_READ_EOP;		
+          } 
+          break;
+        }
+        //////////////////////
+      case TGT_CMD_READ_EOP:
+        {
+          if ( p_vci_tgt.cmdval && p_vci_tgt.eop ){
+            r_tgt_cmd_fsm = TGT_CMD_IDLE;
+          }
+          break;
+        }
+        ///////////////////
+      case TGT_CMD_WRITE:
+        {
+
+          if ( p_vci_tgt.cmdval && m_cmd_write_addr_fifo.wok() ) {
+            cmd_write_fifo_put = true;
+            if(  p_vci_tgt.eop )  r_tgt_cmd_fsm = TGT_CMD_IDLE;
+
+          }
+          break;
+        }
+        ////////////////////
+      case TGT_CMD_ATOMIC:
+        {
+          assert(p_vci_tgt.eop && "Memory Cache Error: LL or SC command with length > 1 ");
+
+          if ( p_vci_tgt.cmdval && m_cmd_llsc_addr_fifo.wok() ) {
+            cmd_llsc_fifo_put = true;
+            r_tgt_cmd_fsm = TGT_CMD_IDLE;
+          }
+          break;
+        }
+    } // end switch tgt_cmd_fsm
+
+    /////////////////////////////////////////////////////////////////////////
+    //		INIT_RSP FSM
+    /////////////////////////////////////////////////////////////////////////
+    // This FSM controls the response to the update or invalidate requests
+    // sent by the memory cache to the L1 caches :
+    //
+    // - update request initiated by the WRITE FSM.  
+    //   The FSM decrements the proper entry in the Update/Inval Table.
+    //   It sends a request to the TGT_RSP FSM to complete the pending 
+    //   write transaction (acknowledge response to the writer processor), 
+    //   and clear the UPT entry when all responses have been received.  
+    // - invalidate request initiated by the XRAM_RSP FSM.
+    //   The FSM decrements the proper entry in the Update/Inval_Table,
+    //   and clear the entry when all responses have been received.
+    //
+    // All those response packets are one word, compact
+    // packets complying with the VCI advanced format. 
+    // The index in the Table is defined in the RTRDID field, and
+    // the Transaction type is defined in the Update/Inval Table.
+    /////////////////////////////////////////////////////////////////////
+
+    switch ( r_init_rsp_fsm.read() ) {
+
+      ///////////////////
+      case INIT_RSP_IDLE:
+        {
+
+          if ( p_vci_ini.rspval ) {
+
+            assert ( ( p_vci_ini.rtrdid.read() < m_update_tab.size() )
+                && "VCI_MEM_CACHE UPT index too large in VCI response paquet received by memory cache" );
+            assert ( p_vci_ini.reop 
+                && "VCI_MEM_CACHE All response packets to update/invalidate requests must be one cell" );
+            r_init_rsp_upt_index = p_vci_ini.rtrdid.read(); 
+            r_init_rsp_fsm = INIT_RSP_UPT_LOCK;
+          }
+          break;
+        }
+        ///////////////////////
+      case INIT_RSP_UPT_LOCK:	// decrement the number of expected responses
+        {
+
+          if ( r_alloc_upt_fsm.read() == ALLOC_UPT_INIT_RSP ) { 
+            size_t count = 0;
+            bool valid  = m_update_tab.decrement(r_init_rsp_upt_index.read(), count);
+#ifdef IDEBUG
+	std::cout << sc_time_stamp() << " " << name() << " INIT_RSP_UPT_LOCK update table : " << std::endl;
+	m_update_tab.print();
+#endif
+            assert ( valid 
+                && "VCI_MEM_CACHE Invalid UPT entry in VCI response paquet received by memory cache" );
+
+            if ( count == 0 ) r_init_rsp_fsm = INIT_RSP_UPT_CLEAR;
+            else              r_init_rsp_fsm = INIT_RSP_IDLE;
+          }
+          break;
+        }
+        ////////////////////////
+      case INIT_RSP_UPT_CLEAR:	// clear the UPT entry
+        {
+          if ( r_alloc_upt_fsm.read() == ALLOC_UPT_INIT_RSP ) {
+            r_init_rsp_srcid = m_update_tab.srcid(r_init_rsp_upt_index.read());
+            r_init_rsp_trdid = m_update_tab.trdid(r_init_rsp_upt_index.read());
+            r_init_rsp_pktid = m_update_tab.pktid(r_init_rsp_upt_index.read());
+            r_init_rsp_nline = m_update_tab.nline(r_init_rsp_upt_index.read());
+            bool need_rsp = m_update_tab.need_rsp(r_init_rsp_upt_index.read());
+            if ( need_rsp ) r_init_rsp_fsm = INIT_RSP_END;
+            else            r_init_rsp_fsm = INIT_RSP_IDLE;
+            m_update_tab.clear(r_init_rsp_upt_index.read());
+#ifdef IDEBUG
+	std::cout << sc_time_stamp() << " " << name() << " INIT_RSP_UPT_CLEAR update table : " << std::endl;
+	m_update_tab.print();
+#endif
+          }
+          break;
+        }
+        //////////////////
+      case INIT_RSP_END:
+        {
+
+          if ( !r_init_rsp_to_tgt_rsp_req ) {
+            r_init_rsp_to_tgt_rsp_req = true;
+            r_init_rsp_to_tgt_rsp_srcid = r_init_rsp_srcid.read();
+            r_init_rsp_to_tgt_rsp_trdid = r_init_rsp_trdid.read();
+            r_init_rsp_to_tgt_rsp_pktid = r_init_rsp_pktid.read();
+            r_init_rsp_fsm = INIT_RSP_IDLE;
+          }
+          break;
+        }
+    } // end switch r_init_rsp_fsm
+
+    ////////////////////////////////////////////////////////////////////////////////////
+    //		READ FSM
+    ////////////////////////////////////////////////////////////////////////////////////
+    // The READ FSM controls the read requests sent by processors.
+    // It takes the lock protecting the cache directory to check the cache line status:
+    // - In case of HIT, the fsm copies the data (one line, or one single word)
+    //   in the r_read_to_tgt_rsp buffer. It waits if this buffer is not empty.
+    //   The requesting initiator is registered in the cache directory.
+    // - In case of MISS, the READ fsm takes the lock protecting the transaction tab.
+    //   If a read transaction to the XRAM for this line already exists,
+    //   or if the transaction tab is full, the fsm is stalled.
+    //   If a transaction entry is free, the READ fsm sends a request to the XRAM.
+    ////////////////////////////////////////////////////////////////////////////////////
+
+    switch ( r_read_fsm.read() ) {
+
+      ///////////////
+      case READ_IDLE:
+        {
+          if (m_cmd_read_addr_fifo.rok()) {
+            m_cpt_read++;
+#ifdef VHDL_ACCURATE
+            r_read_pass = false;
+#endif
+            r_read_fsm = READ_DIR_LOCK;
+          }
+          break;
+        }
+        ///////////////////
+      case READ_DIR_LOCK:	// check directory for hit / miss
+        {
+          if( r_alloc_dir_fsm.read() == ALLOC_DIR_READ ) {
+#ifdef VHDL_ACCURATE
+            if(!r_read_pass.read()){
+#endif
+              size_t way = 0;
+              DirectoryEntry entry = m_cache_directory.read(m_cmd_read_addr_fifo.read(), way);
+#ifdef IDEBUG
+	   std::cout << "In READ_DIR_LOCK printing the entry of address is : " << std::hex << m_cmd_read_addr_fifo.read() << std::endl;
+	   entry.print();
+	   std::cout << "done" << std::endl;
+#endif
+
+              r_read_is_cnt   = entry.is_cnt;
+              r_read_dirty    = entry.dirty;
+              r_read_tag	  = entry.tag;
+              r_read_lock	  = entry.lock;
+              r_read_way	  = way;
+              r_read_word	  = m_cmd_read_word_fifo.read();
+              r_read_d_copies = entry.d_copies; 
+              r_read_i_copies = entry.i_copies; 
+              r_read_count    = entry.count;
+#ifdef VHDL_ACCURATE
+              r_read_pass     = true;
+#endif
+
+              // In case of hit, the read acces must be registered in the copies bit-vector
+              if( entry.valid )  { 
+                r_read_fsm = READ_DIR_LOCK;
+              } else {
+                r_read_fsm = READ_TRT_LOCK;
+                m_cpt_read_miss++;
+              }
+
+#ifdef VHDL_ACCURATE
+            } else {
+              r_read_pass = false;
+              r_read_fsm = READ_DIR_HIT;
+            }
+#endif
+          }
+          break;
+        }
+        //////////////////
+      case READ_DIR_HIT:	// read hit : update the memory cache
+        {
+          if( r_alloc_dir_fsm.read() == ALLOC_DIR_READ ) {
+            // signals generation
+            bool inst_read = (m_cmd_read_trdid_fifo.read() & 0x2);
+            bool cached_read = (m_cmd_read_trdid_fifo.read() & 0x1);
+            bool is_cnt = ((r_read_count.read() >= r_copies_limit.read()) && cached_read) || r_read_is_cnt.read();
+
+            // read data in the cache
+            size_t set = m_y[(vci_addr_t)(m_cmd_read_addr_fifo.read())];
+            size_t way = r_read_way.read();
+            for ( size_t i=0 ; i<m_words ; i++ ) {
+              r_read_data[i] = m_cache_data[way][set][i];
+            }
+
+            // update the cache directory (for the copies)
+            DirectoryEntry entry;
+            entry.valid	  = true;
+            entry.is_cnt  = is_cnt; // when we reach the limit of copies
+            entry.dirty	  = r_read_dirty.read();
+            entry.tag	  = r_read_tag.read();
+            entry.lock	  = r_read_lock.read();
+            if(cached_read){  // Cached read, we update the copies vector
+              if(inst_read && !is_cnt){ // Instruction read, vector mode
+                assert(!(r_read_i_copies.read() & (0x1 << m_cmd_read_srcid_fifo.read())) && "MemCache Error : processor read on an already owned cache line");
+                entry.d_copies  = r_read_d_copies.read();
+                entry.i_copies  = r_read_i_copies.read() | (0x1 << m_cmd_read_srcid_fifo.read()); 
+                entry.count     = r_read_count.read() + 1;
+              }
+              if(!inst_read && !is_cnt){ // Data read, vector mode
+                assert(!(r_read_d_copies.read() & (0x1 << m_cmd_read_srcid_fifo.read())) && "MemCache Error : processor read on an already owned cache line");
+                entry.d_copies  = r_read_d_copies.read() | (0x1 << m_cmd_read_srcid_fifo.read()); 
+                entry.i_copies  = r_read_i_copies.read();
+                entry.count     = r_read_count.read() + 1;
+              }
+              if( is_cnt ) { // Counter mode
+                entry.count     = r_read_count.read() + 1;
+                entry.d_copies  = 0;
+                entry.i_copies  = 0;
+              } 
+            } else { // Uncached read
+              entry.d_copies = r_read_d_copies.read();
+              entry.i_copies = r_read_i_copies.read();
+              entry.count    = r_read_count.read();
+            }
+#ifdef IDEBUG
+	   std::cout << "In READ_DIR_HIT printing the entry of address is : " << std::endl;
+	   entry.print();
+	   std::cout << "done" << std::endl;
+#endif
+
+            m_cache_directory.write(set, way, entry);
+            r_read_fsm    = READ_RSP;
+          }
+          break;
+        }
+        //////////////
+      case READ_RSP: 		//  request the TGT_RSP FSM to return data
+        {
+          if( !r_read_to_tgt_rsp_req ) {	
+            for ( size_t i=0 ; i<m_words ; i++ ) {
+              r_read_to_tgt_rsp_data[i] = r_read_data[i];
+              if ( r_read_word ) {	// single word
+                r_read_to_tgt_rsp_val[i] = (i == m_x[(vci_addr_t)(m_cmd_read_addr_fifo.read())]);
+              } else {			// cache line
+                r_read_to_tgt_rsp_val[i] = true;
+              }
+            }
+            cmd_read_fifo_get 		= true;
+            r_read_to_tgt_rsp_req	= true;
+            r_read_to_tgt_rsp_srcid	= m_cmd_read_srcid_fifo.read();
+            r_read_to_tgt_rsp_trdid	= m_cmd_read_trdid_fifo.read();
+            r_read_to_tgt_rsp_pktid	= m_cmd_read_pktid_fifo.read();
+            r_read_fsm 			= READ_IDLE;  
+          }
+          break;
+        }
+        ///////////////////
+      case READ_TRT_LOCK:	// read miss : check the Transaction Table
+        {
+          if ( r_alloc_trt_fsm.read() == ALLOC_TRT_READ ) {
+#ifdef IDEBUG
+            std::cout << sc_time_stamp() << " " << name() << " READ_TRT_LOCK " << std::endl;
+#endif
+            size_t index = 0;
+            bool   hit_read = m_transaction_tab.hit_read(m_nline[(vci_addr_t)(m_cmd_read_addr_fifo.read())], index);
+            bool   hit_write = m_transaction_tab.hit_write(m_nline[(vci_addr_t)(m_cmd_read_addr_fifo.read())]);
+            bool   wok = !m_transaction_tab.full(index);
+            if( hit_read || !wok || hit_write ) {  // missing line already requested or no space
+              r_read_fsm = READ_IDLE;
+            } else {			   // missing line is requested to the XRAM
+              r_read_trt_index = index;
+              r_read_fsm       = READ_TRT_SET;
+            }
+          }
+          break;
+        }
+        //////////////////
+      case READ_TRT_SET:
+        {
+          if ( r_alloc_trt_fsm.read() == ALLOC_TRT_READ ) {
+            m_transaction_tab.set(r_read_trt_index.read(),
+                true,
+                m_nline[(vci_addr_t)(m_cmd_read_addr_fifo.read())],
+                m_cmd_read_srcid_fifo.read(),
+                m_cmd_read_trdid_fifo.read(),
+                m_cmd_read_pktid_fifo.read(),
+                true,
+                m_cmd_read_word_fifo.read(),
+                m_x[(vci_addr_t)(m_cmd_read_addr_fifo.read())],
+                std::vector<be_t>(m_words,0),
+                std::vector<data_t>(m_words,0));
+#ifdef IDEBUG
+                std::cout << sc_time_stamp() << " " << name() << " READ_TRT_SET transaction table : " << std::endl;
+                for(size_t i = 0 ; i < m_transaction_tab.size() ; i++)
+                  m_transaction_tab.print(i);
+#endif
+
+            r_read_fsm 	 = READ_XRAM_REQ;
+          }
+          break;
+        }
+        /////////////////////
+      case READ_XRAM_REQ:
+        {
+          if( !r_read_to_ixr_cmd_req ) {
+            cmd_read_fifo_get		= true;
+            r_read_to_ixr_cmd_req  	= true;
+            r_read_to_ixr_cmd_nline 	= m_nline[(vci_addr_t)(m_cmd_read_addr_fifo.read())];
+            r_read_to_ixr_cmd_trdid 	= r_read_trt_index.read();
+            r_read_fsm 			          = READ_IDLE;
+          }
+          break;
+        }
+    } // end switch read_fsm
+
+    ///////////////////////////////////////////////////////////////////////////////////
+    //		WRITE FSM
+    ///////////////////////////////////////////////////////////////////////////////////
+    // The WRITE FSM handles the write bursts sent by the processors.
+    // All addresses in a burst must be in the same cache line.
+    // A complete write burst is consumed in the FIFO & copied to a local buffer.
+    // Then the FSM takes the lock protecting the cache directory, to check
+    // if the line is in the cache.
+    //
+    // - In case of HIT, the cache is updated.
+    //   If there is no other copy, an acknowledge response is immediately
+    //   returned to the writing processor.
+    //   if the data is cached by other processoris, the FSM takes the lock
+    //   protecting the Update Table (UPT) to register this update transaction.
+    //   If the UPT is full, it releases the lock  and waits. Then, it sends 
+    //   a multi-update request to all owners of the line (but the writer), 
+    //   through the INIT_CMD FSM. In case of multi-update transaction, the WRITE FSM 
+    //   does not respond to the writing processor, as this response will be sent by 
+    //   the INIT_RSP FSM when all update responses have been received.
+    //
+    // - In case of MISS, the WRITE FSM takes the lock protecting the transaction
+    //   table (TRT). If a read transaction to the XRAM for this line already exists, 
+    //   it writes in the TRT (write buffer). Otherwise, if a TRT entry is free, 
+    //   the WRITE FSM register a new transaction in TRT, and sends a read line request 
+    //   to the XRAM. If the TRT is full, it releases the lock, and waits.
+    //   Finally, the WRITE FSM returns an aknowledge response to the writing processor.
+    /////////////////////////////////////////////////////////////////////////////////////
+
+    switch ( r_write_fsm.read() ) {
+#ifdef VHDL_ACCURATE
+      case WRITE_RESET: 
+        {
+          r_write_word_index	= 0;
+          r_write_word_count	= 0;
+
+          for (int i=0; i < m_words ; i++) {
+            r_write_data[i]	= 0;
+          }
+
+          r_write_srcid	      = 0;
+          r_write_trdid	      = 0;
+          r_write_pktid	      = 0;
+          r_write_is_cnt      = false;
+          r_write_lock        = false;
+          r_write_d_copies    = 0;
+          r_write_i_copies    = 0;
+          r_write_count       = 0;
+          r_write_tag         = 0; 
+
+          if ( r_alloc_dir_fsm.read() == ALLOC_DIR_WRITE ) {
+          
+            r_write_way = (r_write_way.read()+1);
+            if(r_write_way.read() == (m_ways-1)) {
+              r_write_way     = 0;
+              
+#define L2 soclib::common::uint32_log2
+              r_write_address	= r_write_address.read() + (1<<(L2(m_words)+2));
+#undef L2
+            }
+
+
+            DirectoryEntry entry;
+            entry.valid	   = false;
+            entry.dirty	   = false;
+            entry.tag	     = 0;
+            entry.is_cnt   = false;
+            entry.lock	   = false;
+            entry.d_copies = 0;
+            entry.i_copies = 0;
+            entry.count    = 0;
+
+            size_t set	   = m_y[(vci_addr_t)(r_write_address.read())];
+            size_t way	   = r_write_way.read();
+
+            m_cache_directory.write(set, way, entry);
+
+#ifdef IDEBUG
+            std::cout  << "Initialize directory entry: "  << std::endl
+                  << "WRITE FSM: Way     = "              << way << std::endl
+                  << "WRITE FSM: Set     = "              << set << std::endl
+                  << "WRITE FSM: Address = "          << r_write_address.read()
+                  << std::endl;
+#endif
+            
+
+            if((set == (m_sets-1)) && (way == (m_ways-1))) {
+              r_write_fsm = WRITE_IDLE;
+            }
+          }
+          break;
+        }
+#endif
+      ////////////////
+      case WRITE_IDLE:	// copy first word of a write burst in local buffer	
+        {
+          if ( m_cmd_write_addr_fifo.rok()) {
+            m_cpt_write++;
+            m_cpt_write_cells++;
+            // consume a word in the FIFO & write it in the local buffer 
+            cmd_write_fifo_get	= true;
+            size_t index 	    = m_x[(vci_addr_t)(m_cmd_write_addr_fifo.read())];
+            r_write_address	    = (addr_t)(m_cmd_write_addr_fifo.read());
+            r_write_word_index	= index;
+            r_write_word_count	= 1;
+            r_write_data[index]	= m_cmd_write_data_fifo.read();
+            r_write_srcid	    = m_cmd_write_srcid_fifo.read();
+            r_write_trdid	    = m_cmd_write_trdid_fifo.read();
+            r_write_pktid	    = m_cmd_write_pktid_fifo.read();
+#ifdef VHDL_ACCURATE
+            r_write_pass        = false;
+#endif
+
+            // the be field must be set for all words 
+            for ( size_t i=0 ; i<m_words ; i++ ) {
+              if ( i == index ) r_write_be[i] = m_cmd_write_be_fifo.read();
+              else		        r_write_be[i] = 0x0;
+            }
+            if( !((m_cmd_write_be_fifo.read() == 0x0)||(m_cmd_write_be_fifo.read() == 0xF)) )
+                    r_write_byte=true;
+            else    r_write_byte=false;
+
+            if( m_cmd_write_eop_fifo.read() )  r_write_fsm = WRITE_DIR_LOCK;
+            else                               r_write_fsm = WRITE_NEXT;
+          }
+          break;
+        }
+        ////////////////
+      case WRITE_NEXT:	// copy next word of a write burst in local buffer
+        {
+          if ( m_cmd_write_addr_fifo.rok() ) {
+            m_cpt_write_cells++;
+
+            // check that the next word is in the same cache line
+            assert( (m_nline[(vci_addr_t)(r_write_address.read())] == m_nline[(vci_addr_t)(m_cmd_write_addr_fifo.read())])  
+                && "VCI_MEM_CACHE write error in vci_mem_cache : write burst over a line" );
+            // consume a word in the FIFO & write it in the local buffer 
+            cmd_write_fifo_get=true;
+            size_t index 	        = r_write_word_index.read() + r_write_word_count.read();
+            r_write_be[index]       = m_cmd_write_be_fifo.read();
+            r_write_data[index]     = m_cmd_write_data_fifo.read();
+            r_write_word_count 	    = r_write_word_count.read() + 1;
+            if( !((m_cmd_write_be_fifo.read() == 0x0)||(m_cmd_write_be_fifo.read() == 0xF)) )
+              r_write_byte=true;
+            if ( m_cmd_write_eop_fifo.read() )  r_write_fsm = WRITE_DIR_LOCK;
+          }
+          break;
+        }
+        ////////////////////
+      case WRITE_DIR_LOCK:	// access directory to check hit/miss
+        {
+          if ( r_alloc_dir_fsm.read() == ALLOC_DIR_WRITE ) {
+#ifdef VHDL_ACCURATE
+            if (!r_write_pass.read()){
+#endif
+              size_t  way = 0;
+              DirectoryEntry entry(m_cache_directory.read(r_write_address.read(), way));
+
+              // copy directory entry in local buffers in case of hit
+              if ( entry.valid )  {	
+                r_write_is_cnt    = entry.is_cnt;
+                r_write_lock	  = entry.lock;
+                r_write_tag       = entry.tag;
+                r_write_d_copies  = entry.d_copies;
+                r_write_i_copies  = entry.i_copies;
+                r_write_count     = entry.count;
+                r_write_way  	  = way;
+                r_write_fsm  = WRITE_DIR_LOCK;
+                r_write_pass = true;
+              } else {
+                r_write_fsm = WRITE_TRT_LOCK;
+                m_cpt_write_miss++;
+              }
+#ifdef VHDL_ACCURATE
+           } else {
+             if(r_write_is_cnt.read() && r_write_count.read()){
+               r_write_fsm     = WRITE_DIR_HIT_READ;
+             } else {
+               if(r_write_byte.read())
+                 r_write_fsm   = WRITE_DIR_HIT_READ;
+               else {
+                   bool owner     = (bool) (r_write_d_copies & (0x1 << r_write_srcid.read()));
+                   bool no_update = (owner && (r_write_count == 1)) || (r_write_count==0);
+                   if( no_update ) r_write_fsm  = WRITE_DIR_HIT_RSP; 
+                   else            r_write_fsm  = WRITE_DIR_HIT;
+               }
+             }
+             r_write_pass = false;
+           }
+#endif
+          }
+          break;
+        }
+        ///////////////////
+      case WRITE_DIR_HIT_READ:	// read the cache and complete the buffer (data, when be!=0xF)
+        {
+          // update local buffer
+          size_t set	= m_y[(vci_addr_t)(r_write_address.read())];
+          size_t way	= r_write_way.read();
+          for(size_t i=0 ; i<m_words ; i++) {
+            data_t mask      = 0;
+            if  (r_write_be[i].read() & 0x1) mask = mask | 0x000000FF;
+            if  (r_write_be[i].read() & 0x2) mask = mask | 0x0000FF00;
+            if  (r_write_be[i].read() & 0x4) mask = mask | 0x00FF0000;
+            if  (r_write_be[i].read() & 0x8) mask = mask | 0xFF000000;
+            if(r_write_be[i].read()||r_write_is_cnt.read()) { // complete only if mask is not null (for energy consumption)
+              r_write_data[i]  = (r_write_data[i].read() & mask) | 
+                (m_cache_data[way][set][i] & ~mask);
+            }
+          } // end for
+
+          if(r_write_is_cnt.read() && r_write_count.read()){
+            r_write_fsm            = WRITE_TRT_WRITE_LOCK;
+          } else {
+              bool owner     = (bool) (r_write_d_copies.read() & (0x1 << r_write_srcid.read()));
+              bool no_update = (owner && (r_write_count.read() == 1)) || (r_write_count.read()==0);
+              if( no_update )   r_write_fsm    = WRITE_DIR_HIT_RSP;
+              else              r_write_fsm    = WRITE_DIR_HIT;
+          }
+           break;
+        }
+        ///////////////////
+      case WRITE_DIR_HIT:	// update the cache (data & dirty bit)
+        {
+          // update directory with Dirty bit
+          DirectoryEntry entry;
+          entry.valid	    = true;
+          entry.dirty	    = true;
+          entry.tag	        = r_write_tag.read();
+          entry.is_cnt      = r_write_is_cnt.read();
+          entry.lock	    = r_write_lock.read();
+          entry.d_copies    = r_write_d_copies.read();
+          entry.i_copies    = r_write_i_copies.read();
+          entry.count       = r_write_count.read();
+          size_t set	    = m_y[(vci_addr_t)(r_write_address.read())];
+          size_t way	    = r_write_way.read();
+          m_cache_directory.write(set, way, entry);
+
+          size_t nb_copies=0;
+          for(size_t i=0; i<32 ; i++) {
+            if( r_write_d_copies.read() & (1<<i) )
+                nb_copies++;
+          }
+          for(size_t i=0; i<32 ; i++) {
+            if( r_write_i_copies.read() & (1<<i) )
+                nb_copies++;
+          }
+          assert((nb_copies == r_write_count.read()) && "MemCache Error, inconsistency in the directory");
+
+          // write data in cache
+          for(size_t i=0 ; i<m_words ; i++) {
+            if  ( r_write_be[i].read() ) {
+              m_cache_data[way][set][i]  = r_write_data[i].read();
+            }
+          } // end for
+
+          // compute the actual number of copies & the modified bit vector
+          bool owner = (bool) (r_write_d_copies.read() & (0x1 << r_write_srcid.read()));
+          copy_t d_copies = r_write_d_copies.read() & ~(0x1 << r_write_srcid.read());
+          r_write_d_copies      = d_copies;
+          size_t count_signal   = r_write_count.read();
+          if(owner){
+            count_signal        = count_signal - 1;
+          }
+          r_write_count         = count_signal;
+
+          r_write_fsm = WRITE_UPT_LOCK;
+          break;
+        }
+        ///////////////////
+      case WRITE_DIR_HIT_RSP:	// update the cache (data & dirty bit) (no update)
+        {
+          // update directory with Dirty bit
+          DirectoryEntry entry;
+          entry.valid	    = true;
+          entry.dirty	    = true;
+          entry.tag	        = r_write_tag.read();
+          entry.is_cnt      = r_write_is_cnt.read();
+          entry.lock	    = r_write_lock.read();
+          entry.d_copies    = r_write_d_copies.read();
+          entry.i_copies    = r_write_i_copies.read();
+          entry.count       = r_write_count.read();
+          size_t set	    = m_y[(vci_addr_t)(r_write_address.read())];
+          size_t way	    = r_write_way.read();
+          m_cache_directory.write(set, way, entry);
+
+          size_t nb_copies=0;
+          for(size_t i=0; i<32 ; i++) {
+            if( r_write_d_copies.read() & (1<<i) )
+                nb_copies++;
+          }
+          for(size_t i=0; i<32 ; i++) {
+            if( r_write_i_copies.read() & (1<<i) )
+                nb_copies++;
+          }
+          assert((nb_copies == r_write_count.read()) && "MemCache Error, inconsistency in the directory");
+
+          // write data in cache
+          for(size_t i=0 ; i<m_words ; i++) {
+            if  ( r_write_be[i].read() ) {
+              m_cache_data[way][set][i]  = r_write_data[i].read();
+            }
+          } // end for
+
+          if ( !r_write_to_tgt_rsp_req.read() ) {
+            r_write_to_tgt_rsp_req	    = true;
+            r_write_to_tgt_rsp_srcid	= r_write_srcid.read();
+            r_write_to_tgt_rsp_trdid	= r_write_trdid.read();
+            r_write_to_tgt_rsp_pktid	= r_write_pktid.read();
+            r_write_fsm 		        = WRITE_IDLE;
+          } else {
+            r_write_fsm = WRITE_RSP;
+          }
+          break;
+        }
+        /////////////////////
+      case WRITE_UPT_LOCK: 	// Try to register the request in Update Table
+        {
+
+          if ( r_alloc_upt_fsm.read() == ALLOC_UPT_WRITE ) {
+            bool          wok        = false;
+            size_t        index      = 0;
+            size_t        srcid      = r_write_srcid.read();
+            size_t        trdid      = r_write_trdid.read();
+            size_t        pktid      = r_write_pktid.read();
+            addr_t	      nline      = m_nline[(vci_addr_t)(r_write_address.read())];
+            size_t        nb_copies  = r_write_count.read();
+
+            wok =m_update_tab.set(true,	// it's an update transaction
+                false,                  // it's not a broadcast
+                true,                   // it needs a response
+                srcid,
+                trdid,
+                pktid,
+                nline,
+                nb_copies,
+                index);
+#ifdef IDEBUG
+            if(wok){
+	std::cout << sc_time_stamp() << " " << name() << " WRITE_UPT_LOCK update table : " << std::endl;
+	m_update_tab.print();
+            }
+#endif
+            r_write_upt_index = index;
+            //  releases the lock protecting Update Table if no entry...
+            if ( wok ) r_write_fsm = WRITE_UPDATE;
+            else       r_write_fsm = WRITE_WAIT_UPT;
+          }
+          break;
+        }
+        ////////////////////
+      case WRITE_WAIT_UPT:	// release the lock protecting UPT
+        {
+          r_write_fsm = WRITE_UPT_LOCK;
+          break;
+        }
+        //////////////////
+      case WRITE_UPDATE:	// send a multi-update request to INIT_CMD fsm
+        {
+
+          if ( !r_write_to_init_cmd_req ) {
+            r_write_to_init_cmd_req      = true;
+            r_write_to_init_cmd_brdcast  = false;
+            r_write_to_init_cmd_trdid    = r_write_upt_index.read();
+            r_write_to_init_cmd_nline    = m_nline[(vci_addr_t)(r_write_address.read())];
+            r_write_to_init_cmd_index    = r_write_word_index.read();
+            r_write_to_init_cmd_count    = r_write_word_count.read();
+            r_write_to_init_cmd_d_copies = r_write_d_copies.read();
+            r_write_to_init_cmd_i_copies = r_write_i_copies.read();
+
+            for(size_t i=0; i<m_words ; i++){
+              if(r_write_be[i].read())  r_write_to_init_cmd_we[i]=true;
+              else                      r_write_to_init_cmd_we[i]=false;
+            }
+
+            size_t min = r_write_word_index.read();
+            size_t max = r_write_word_index.read() + r_write_word_count.read();
+            for (size_t i=min ; i<max ; i++) {
+              r_write_to_init_cmd_data[i] = r_write_data[i];
+            }
+            r_write_fsm = WRITE_IDLE; // Response will be sent after receiving
+            // all update responses
+          }
+          break;
+        }
+        ///////////////
+      case WRITE_RSP:		// send a request to TGT_RSP FSM to acknowledge the write
+        {
+          if ( !r_write_to_tgt_rsp_req.read() ) {
+            r_write_to_tgt_rsp_req	    = true;
+            r_write_to_tgt_rsp_srcid	= r_write_srcid.read();
+            r_write_to_tgt_rsp_trdid	= r_write_trdid.read();
+            r_write_to_tgt_rsp_pktid	= r_write_pktid.read();
+            r_write_fsm 		        = WRITE_IDLE;
+          }
+          break;
+        }
+        ////////////////////
+      case WRITE_TRT_LOCK:	// Miss : check Transaction Table
+        {
+          if ( r_alloc_trt_fsm.read() == ALLOC_TRT_WRITE ) {
+#ifdef IDEBUG
+	std::cout << sc_time_stamp() << " " << name() << " READ_TRT_LOCK " << std::endl;
+#endif
+            size_t hit_index = 0;
+            size_t wok_index = 0;
+            bool hit_read  = m_transaction_tab.hit_read(m_nline[(vci_addr_t)(r_write_address.read())],hit_index);
+            bool hit_write = m_transaction_tab.hit_write(m_nline[(vci_addr_t)(r_write_address.read())]);
+            bool wok = !m_transaction_tab.full(wok_index);
+            if ( hit_read ) {	// register the modified data in TRT 
+              r_write_trt_index = hit_index;
+              r_write_fsm       = WRITE_TRT_DATA;
+            } else if ( wok && !hit_write ) {	// set a new entry in TRT
+              r_write_trt_index = wok_index;
+              r_write_fsm       = WRITE_TRT_SET;
+            } else {		// wait an empty entry in TRT
+              r_write_fsm       = WRITE_WAIT_TRT;
+            }
+          }
+          break;
+        }
+        ////////////////////
+      case WRITE_WAIT_TRT:	// release the lock protecting TRT
+        { 
+          r_write_fsm = WRITE_DIR_LOCK;
+          break;
+        }
+        ///////////////////
+      case WRITE_TRT_SET:	// register a new transaction in TRT (Write Buffer)
+        {  
+          if ( r_alloc_trt_fsm.read() == ALLOC_TRT_WRITE ) 
+          {
+            std::vector<be_t> be_vector;
+            std::vector<data_t> data_vector;
+            be_vector.clear();
+            data_vector.clear();
+            for ( size_t i=0; i<m_words; i++ ) 
+            {
+              be_vector.push_back(r_write_be[i]);
+              data_vector.push_back(r_write_data[i]);
+            }
+            m_transaction_tab.set(r_write_trt_index.read(),
+                true,				// read request to XRAM
+                m_nline[(vci_addr_t)(r_write_address.read())],
+                r_write_srcid.read(),
+                r_write_trdid.read(),
+                r_write_pktid.read(),
+                false,				// not a processor read
+                false,				// not a single word 
+                0,			        	// word index
+                be_vector,
+                data_vector);
+#ifdef IDEBUG
+	std::cout << sc_time_stamp() << " " << name() << " WRITE_TRT_SET transaction table : " << std::endl;
+	for(size_t i = 0 ; i < m_transaction_tab.size() ; i++)
+	  m_transaction_tab.print(i);
+#endif
+
+            r_write_fsm = WRITE_XRAM_REQ;
+          }
+          break;
+        }  
+        ///////////////////
+      case WRITE_TRT_DATA:	// update an entry in TRT (Write Buffer)
+        { 
+          if ( r_alloc_trt_fsm.read() == ALLOC_TRT_WRITE ) {
+            std::vector<be_t> be_vector;
+            std::vector<data_t> data_vector;
+            be_vector.clear();
+            data_vector.clear();
+            for ( size_t i=0; i<m_words; i++ ) {
+              be_vector.push_back(r_write_be[i]);
+              data_vector.push_back(r_write_data[i]);
+            }
+            m_transaction_tab.write_data_mask(r_write_trt_index.read(),
+                be_vector,
+                data_vector);
+            r_write_fsm = WRITE_RSP;
+#ifdef IDEBUG
+	std::cout << sc_time_stamp() << " " << name() << " WRITE_TRT_DATA transaction table : " << std::endl;
+	for(size_t i = 0 ; i < m_transaction_tab.size() ; i++)
+	  m_transaction_tab.print(i);
+#endif
+
+          }
+          break;
+        }
+        ////////////////////
+      case WRITE_XRAM_REQ:	// send a request to IXR_CMD FSM
+        {  
+
+          if ( !r_write_to_ixr_cmd_req ) {
+            r_write_to_ixr_cmd_req   = true;
+            r_write_to_ixr_cmd_write = false;
+            r_write_to_ixr_cmd_nline = m_nline[(vci_addr_t)(r_write_address.read())];
+            r_write_to_ixr_cmd_trdid = r_write_trt_index.read();
+            r_write_fsm              = WRITE_RSP;
+          }
+          break;
+        }
+        ////////////////////
+      case WRITE_TRT_WRITE_LOCK:
+        {
+          if ( r_alloc_trt_fsm.read() == ALLOC_TRT_WRITE ) {
+            size_t wok_index = 0;
+            bool wok = !m_transaction_tab.full(wok_index);
+            if ( wok ) {	// set a new entry in TRT
+              r_write_trt_index = wok_index;
+              r_write_fsm       = WRITE_INVAL_LOCK;
+            } else {		// wait an empty entry in TRT
+              r_write_fsm       = WRITE_WAIT_TRT;
+            }
+          }
+
+          break;
+        }
+        ////////////////////
+      case WRITE_INVAL_LOCK:
+        {
+          if ( r_alloc_upt_fsm.read() == ALLOC_UPT_WRITE ) {
+            bool        wok       = false;
+            size_t      index     = 0;
+            size_t      srcid     = r_write_srcid.read();
+            size_t      trdid     = r_write_trdid.read();
+            size_t      pktid     = r_write_pktid.read();
+            addr_t	    nline     = m_nline[(vci_addr_t)(r_write_address.read())];
+            size_t      nb_copies = r_write_count.read();
+
+            wok =m_update_tab.set(false,	// it's an inval transaction
+                true,                       // it's a broadcast
+                true,                       // it needs a response
+                srcid,
+                trdid,
+                pktid,
+                nline,
+                nb_copies,
+                index);
+#ifdef IDEBUG
+            if(wok){
+	std::cout << sc_time_stamp() << " " << name() << " WRITE_INVAL_LOCK update table : " << std::endl;
+	m_update_tab.print();
+            }
+#endif
+            r_write_upt_index = index;
+            //  releases the lock protecting Update Table if no entry...
+            if ( wok ) r_write_fsm = WRITE_DIR_INVAL;
+            else       r_write_fsm = WRITE_WAIT_TRT;
+          }
+
+          break;
+        }
+        ////////////////////
+      case WRITE_DIR_INVAL:
+        {
+          if ( (r_alloc_trt_fsm.read() == ALLOC_TRT_WRITE ) ||
+              (r_alloc_upt_fsm.read() == ALLOC_UPT_WRITE ) )
+          {
+            m_transaction_tab.set(r_write_trt_index.read(),
+                false,				// write request to XRAM
+                m_nline[(vci_addr_t)(r_write_address.read())],
+                0,
+                0,
+                0,
+                false,				// not a processor read
+                false,				// not a single word 
+                0,			        	// word index
+                std::vector<be_t>(m_words,0),
+                std::vector<data_t>(m_words,0));
+#ifdef IDEBUG
+	std::cout << sc_time_stamp() << " " << name() << " WRITE_DIR_INVAL transaction table : " << std::endl;
+	for(size_t i = 0 ; i < m_transaction_tab.size() ; i++)
+	  m_transaction_tab.print(i);
+#endif
+
+            // invalidate directory entry
+            DirectoryEntry entry;
+            entry.valid	   = false;
+            entry.dirty	   = false;
+            entry.tag	   = 0;
+            entry.is_cnt   = false;
+            entry.lock	   = false;
+            entry.d_copies = 0;
+            entry.i_copies = 0;
+            entry.count    = 0;
+            size_t set	   = m_y[(vci_addr_t)(r_write_address.read())];
+            size_t way	   = r_write_way.read();
+            m_cache_directory.write(set, way, entry);
+
+            r_write_fsm = WRITE_INVAL;
+          } else {
+            assert(false && "LOCK ERROR in WRITE_FSM, STATE = WRITE_DIR_INVAL");
+          }
+
+          break;
+        }
+        ////////////////////
+      case WRITE_INVAL:
+        {
+          if ( !r_write_to_init_cmd_req ) {
+            r_write_to_init_cmd_req      = true;
+            r_write_to_init_cmd_brdcast  = true;
+            r_write_to_init_cmd_trdid    = r_write_upt_index.read();
+            r_write_to_init_cmd_nline    = m_nline[(vci_addr_t)(r_write_address.read())];
+            r_write_to_init_cmd_index    = 0;
+            r_write_to_init_cmd_count    = 0;
+            r_write_to_init_cmd_d_copies = 0;
+            r_write_to_init_cmd_i_copies = 0;
+
+            for(size_t i=0; i<m_words ; i++){
+              r_write_to_init_cmd_we[i]=false;
+              r_write_to_init_cmd_data[i] = 0;
+            }
+            r_write_fsm = WRITE_XRAM_SEND;
+            // all update responses
+          }
+
+          break;
+        }
+        ////////////////////
+      case WRITE_XRAM_SEND:
+        {
+          if ( !r_write_to_ixr_cmd_req ) {
+            r_write_to_ixr_cmd_req     = true;
+            r_write_to_ixr_cmd_write   = true;
+            r_write_to_ixr_cmd_nline   = m_nline[(vci_addr_t)(r_write_address.read())];
+            r_write_to_ixr_cmd_trdid   = r_write_trt_index.read();
+            for(size_t i=0; i<m_words; i++){
+              r_write_to_ixr_cmd_data[i] = r_write_data[i];
+            }
+            r_write_fsm                 = WRITE_IDLE;
+          }
+          break;
+        }
+    } // end switch r_write_fsm
+
+    ///////////////////////////////////////////////////////////////////////
+    //		IXR_CMD FSM
+    ///////////////////////////////////////////////////////////////////////
+    // The IXR_CMD fsm controls the command packets to the XRAM :
+    // - It sends a single cell VCI read to the XRAM in case of MISS request
+    // posted by the READ, WRITE or LLSC FSMs : the TRDID field contains 
+    // the Transaction Tab index.
+    // The VCI response is a multi-cell packet : the N cells contain
+    // the N data words.
+    // - It sends a multi-cell VCI write when the XRAM_RSP FSM request 
+    // to save a dirty line to the XRAM. 
+    // The VCI response is a single cell packet.
+    // This FSM handles requests from the READ, WRITE, LLSC & XRAM_RSP FSMs 
+    // with a round-robin priority.
+    ////////////////////////////////////////////////////////////////////////
+
+    switch ( r_ixr_cmd_fsm.read() ) {
+      //////////////////////// 
+      case IXR_CMD_READ_IDLE:
+        if      ( r_write_to_ixr_cmd_req )     r_ixr_cmd_fsm = IXR_CMD_WRITE_NLINE;
+        else if ( r_llsc_to_ixr_cmd_req  )     r_ixr_cmd_fsm = IXR_CMD_LLSC_NLINE;
+        else if ( r_xram_rsp_to_ixr_cmd_req  ) r_ixr_cmd_fsm = IXR_CMD_XRAM_DATA;
+        else if ( r_read_to_ixr_cmd_req  )     r_ixr_cmd_fsm = IXR_CMD_READ_NLINE;
+        break;
+        //////////////////////// 
+      case IXR_CMD_WRITE_IDLE:
+        if      ( r_llsc_to_ixr_cmd_req  )     r_ixr_cmd_fsm = IXR_CMD_LLSC_NLINE;
+        else if ( r_xram_rsp_to_ixr_cmd_req  ) r_ixr_cmd_fsm = IXR_CMD_XRAM_DATA;
+        else if ( r_read_to_ixr_cmd_req  )     r_ixr_cmd_fsm = IXR_CMD_READ_NLINE;
+        else if ( r_write_to_ixr_cmd_req )     r_ixr_cmd_fsm = IXR_CMD_WRITE_NLINE;
+        break;
+        //////////////////////// 
+      case IXR_CMD_LLSC_IDLE:
+        if      ( r_xram_rsp_to_ixr_cmd_req  ) r_ixr_cmd_fsm = IXR_CMD_XRAM_DATA;
+        else if ( r_read_to_ixr_cmd_req  )     r_ixr_cmd_fsm = IXR_CMD_READ_NLINE;
+        else if ( r_write_to_ixr_cmd_req )     r_ixr_cmd_fsm = IXR_CMD_WRITE_NLINE;
+        else if ( r_llsc_to_ixr_cmd_req  )     r_ixr_cmd_fsm = IXR_CMD_LLSC_NLINE;
+        break;
+        //////////////////////// 
+      case IXR_CMD_XRAM_IDLE:
+        if      ( r_read_to_ixr_cmd_req  )     r_ixr_cmd_fsm = IXR_CMD_READ_NLINE;
+        else if ( r_write_to_ixr_cmd_req )     r_ixr_cmd_fsm = IXR_CMD_WRITE_NLINE;
+        else if ( r_llsc_to_ixr_cmd_req  )     r_ixr_cmd_fsm = IXR_CMD_LLSC_NLINE;
+        else if ( r_xram_rsp_to_ixr_cmd_req  ) r_ixr_cmd_fsm = IXR_CMD_XRAM_DATA;
+        break;
+        /////////////////////////
+      case IXR_CMD_READ_NLINE:
+        if ( p_vci_ixr.cmdack ) {
+          r_ixr_cmd_fsm = IXR_CMD_READ_IDLE;		
+          r_read_to_ixr_cmd_req = false;
+        }
+        break;
+        //////////////////////////
+      case IXR_CMD_WRITE_NLINE:
+        if ( p_vci_ixr.cmdack ) {
+          if( r_write_to_ixr_cmd_write.read()){
+            if ( r_ixr_cmd_cpt.read() == (m_words - 1) ) {
+              r_ixr_cmd_cpt = 0;
+              r_ixr_cmd_fsm = IXR_CMD_WRITE_IDLE;
+              r_write_to_ixr_cmd_req = false;
+            } else {
+              r_ixr_cmd_cpt = r_ixr_cmd_cpt + 1;
+            }
+          } else {
+            r_ixr_cmd_fsm = IXR_CMD_WRITE_IDLE;		
+            r_write_to_ixr_cmd_req = false;
+          }
+        }
+        break;
+        /////////////////////////
+      case IXR_CMD_LLSC_NLINE:
+        if ( p_vci_ixr.cmdack ) {
+          r_ixr_cmd_fsm = IXR_CMD_LLSC_IDLE;		
+          r_llsc_to_ixr_cmd_req = false;
+        }
+        break;
+        ////////////////////////
+      case IXR_CMD_XRAM_DATA:
+        if ( p_vci_ixr.cmdack ) {
+          if ( r_ixr_cmd_cpt.read() == (m_words - 1) ) {
+            r_ixr_cmd_cpt = 0;
+            r_ixr_cmd_fsm = IXR_CMD_XRAM_IDLE;
+            r_xram_rsp_to_ixr_cmd_req = false;
+          } else {
+            r_ixr_cmd_cpt = r_ixr_cmd_cpt + 1;
+          }
+        }
+        break;
+
+    } // end switch r_ixr_cmd_fsm
+
+    ////////////////////////////////////////////////////////////////////////////
+    //                IXR_RSP FSM
+    ////////////////////////////////////////////////////////////////////////////
+    // The IXR_RSP FSM receives the response packets from the XRAM,
+    // for both write transaction, and read transaction.
+    //
+    // - A response to a write request is a single-cell VCI packet.
+    // The Transaction Tab index is contained in the RTRDID field.
+    // The FSM takes the lock protecting the TRT, and the corresponding
+    // entry is erased.
+    //	
+    // - A response to a read request is a multi-cell VCI packet.
+    // The Transaction Tab index is contained in the RTRDID field.
+    // The N cells contain the N words of the cache line in the RDATA field.
+    // The FSM takes the lock protecting the TRT to store the line in the TRT
+    // (taking into account the write requests already stored in the TRT).
+    // When the line is completely written, the corresponding rok signal is set.
+    ///////////////////////////////////////////////////////////////////////////////
+
+    switch ( r_ixr_rsp_fsm.read() ) {
+
+      ///////////////////
+      case IXR_RSP_IDLE:	// test if it's a read or a write transaction
+        {
+          if ( p_vci_ixr.rspval ) {
+            r_ixr_rsp_cpt   = 0;
+            r_ixr_rsp_trt_index = p_vci_ixr.rtrdid.read();
+            if ( p_vci_ixr.reop )  r_ixr_rsp_fsm = IXR_RSP_ACK;
+            else                   r_ixr_rsp_fsm = IXR_RSP_TRT_READ;
+          }
+          break;  
+        }
+        ////////////////////////
+      case IXR_RSP_ACK:        // Acknowledge the vci response
+        r_ixr_rsp_fsm = IXR_RSP_TRT_ERASE;
+        break;
+        ////////////////////////
+      case IXR_RSP_TRT_ERASE: 	// erase the entry in the TRT
+        {
+          if ( r_alloc_trt_fsm.read() == ALLOC_TRT_IXR_RSP ) {
+            m_transaction_tab.erase(r_ixr_rsp_trt_index.read());
+            r_ixr_rsp_fsm = IXR_RSP_IDLE;
+#ifdef IDEBUG
+	std::cout << sc_time_stamp() << " " << name() << " IXR_RSP_TRT_ERASE transaction table : " << std::endl;
+	for(size_t i = 0 ; i < m_transaction_tab.size() ; i++)
+	  m_transaction_tab.print(i);
+#endif
+
+          }
+          break;
+        }
+        ///////////////////////
+      case IXR_RSP_TRT_READ:		// write data in the TRT
+        {
+          if ( (r_alloc_trt_fsm.read() == ALLOC_TRT_IXR_RSP) &&  p_vci_ixr.rspval ) {
+            bool   eop  	= p_vci_ixr.reop.read();
+            data_t data 	= p_vci_ixr.rdata.read();
+            size_t index        = r_ixr_rsp_trt_index.read();
+            assert( eop == (r_ixr_rsp_cpt.read() == (m_words-1)) 
+                && "Error in VCI_MEM_CACHE : invalid length for a response from XRAM");
+            m_transaction_tab.write_rsp(index, r_ixr_rsp_cpt.read(), data);
+            r_ixr_rsp_cpt = r_ixr_rsp_cpt.read() + 1;
+            if ( eop ) {
+#ifdef IDEBUG
+	std::cout << sc_time_stamp() << " " << name() << " IXR_RSP_TRT_READ transaction table : " << std::endl;
+	for(size_t i = 0 ; i < m_transaction_tab.size() ; i++)
+	  m_transaction_tab.print(i);
+#endif
+
+              r_ixr_rsp_to_xram_rsp_rok[r_ixr_rsp_trt_index.read()]=true;
+              r_ixr_rsp_fsm = IXR_RSP_IDLE;
+            }
+          }
+          break;
+        }
+    } // end swich r_ixr_rsp_fsm
+
+
+    ////////////////////////////////////////////////////////////////////////////
+    //                XRAM_RSP FSM
+    ////////////////////////////////////////////////////////////////////////////
+    // The XRAM_RSP FSM handles the incoming cache lines from the XRAM.
+    // The cache line has been written in the TRT buffer by the IXR_FSM.
+    //
+    // When a response is available, the corresponding TRT entry 
+    // is copied in a local buffer to be written in the cache. 
+    // Then, the FSM releases the lock protecting the TRT, and takes the lock 
+    // protecting the cache directory.
+    // It selects a cache slot and writes the line in the cache.
+    // If it was a read MISS, the XRAM_RSP FSM send a request to the TGT_RSP
+    // FSM to return the cache line to the registered processor.
+    // If there is no empty slot, a victim line is evicted, and
+    // invalidate requests are sent to the L1 caches containing copies.
+    // If this line is dirty, the XRAM_RSP FSM send a request to the IXR_CMD 
+    // FSM to save the victim line to the XRAM, and register the write transaction
+    // in the TRT (using the entry previously used by the read transaction).
+    ///////////////////////////////////////////////////////////////////////////////
+
+    switch ( r_xram_rsp_fsm.read() ) {
+
+      ///////////////////
+      case XRAM_RSP_IDLE:	// test if there is a response with a round robin priority
+        {
+          size_t ptr   = r_xram_rsp_trt_index.read();
+          size_t lines = TRANSACTION_TAB_LINES;
+          for(size_t i=0; i<lines; i++){
+            size_t index=(i+ptr+1)%lines;
+            if(r_ixr_rsp_to_xram_rsp_rok[index]){
+              r_xram_rsp_trt_index=index;
+              r_ixr_rsp_to_xram_rsp_rok[index]=false;
+              r_xram_rsp_fsm           = XRAM_RSP_DIR_LOCK;
+              break;
+#ifdef IDEBUG
+	std::cout << "XRAM_RSP FSM in XRAM_RSP_IDLE state" << std::endl;
+#endif
+            }
+          }
+          break;  
+        }
+        ///////////////////////
+      case XRAM_RSP_DIR_LOCK: 	// Take the lock on the directory
+        {
+          if( r_alloc_dir_fsm.read() == ALLOC_DIR_XRAM_RSP ) {
+#ifdef VHDL_ACCURATE
+            r_xram_rsp_pass          = false;
+#endif
+            r_xram_rsp_fsm           = XRAM_RSP_TRT_COPY;
+#ifdef IDEBUG
+	std::cout << "XRAM_RSP FSM in XRAM_RSP_DIR_LOCK state" << std::endl;
+#endif
+          }
+          break;
+        }
+        ///////////////////////
+      case XRAM_RSP_TRT_COPY:		// Copy the TRT entry in the local buffer and eviction of a cache line
+        {
+          if ( (r_alloc_trt_fsm.read() == ALLOC_TRT_XRAM_RSP) ) {
+#ifdef VHDL_ACCURATE
+            if (!r_xram_rsp_pass.read()){
+#endif
+              size_t index = r_xram_rsp_trt_index.read();
+              TransactionTabEntry    trt_entry(m_transaction_tab.read(index));	
+
+#ifdef IDEBUG
+              std::cout << "TRANSACTION ENTRY DEBUG" << std::endl;
+              trt_entry.print();
+#endif
+
+              r_xram_rsp_trt_buf.copy(trt_entry);  // TRT entry local buffer
+
+              // selects & extracts a victim line from cache
+              size_t way = 0;
+              size_t set = m_y[(vci_addr_t)(trt_entry.nline * m_words * 4)];
+              DirectoryEntry victim(m_cache_directory.select(set, way));
+
+              for (size_t i=0 ; i<m_words ; i++) r_xram_rsp_victim_data[i] = m_cache_data[way][set][i];
+
+              bool inval = (victim.count && victim.valid) ;
+
+              r_xram_rsp_victim_d_copies = victim.d_copies;
+              r_xram_rsp_victim_i_copies = victim.i_copies;
+              r_xram_rsp_victim_count    = victim.count;
+              r_xram_rsp_victim_way      = way;
+              r_xram_rsp_victim_set      = set;
+              r_xram_rsp_victim_nline    = victim.tag*m_sets + set;
+              r_xram_rsp_victim_is_cnt   = victim.is_cnt;
+              r_xram_rsp_victim_inval    = inval ;
+              r_xram_rsp_victim_dirty    = victim.dirty;
+
+#ifdef VHDL_ACCURATE
+              r_xram_rsp_fsm = XRAM_RSP_TRT_COPY;
+#else
+              r_xram_rsp_fsm = XRAM_RSP_INVAL_LOCK;
+#endif
+#ifdef IDEBUG
+	std::cout << "XRAM_RSP FSM in XRAM_RSP_TRT_COPY state" << std::endl;
+	std::cout << "Victim way : " << std::hex << way << " set " << std::hex << set << std::endl;
+	victim.print();
+#endif
+#ifdef VHDL_ACCURATE
+                r_xram_rsp_pass = true;
+              }else{
+                r_xram_rsp_pass = false;
+                r_xram_rsp_fsm = XRAM_RSP_INVAL_LOCK;
+              }
+#endif
+          }
+          break;
+        }
+        ///////////////////////
+      case XRAM_RSP_INVAL_LOCK:
+        {
+          if ( r_alloc_upt_fsm == ALLOC_UPT_XRAM_RSP ) {
+#ifdef IDEBUG
+	std::cout << "XRAM_RSP FSM in XRAM_RSP_INVAL_LOCK state" << std::endl;
+#endif
+            size_t index;
+            if(m_update_tab.search_inval(r_xram_rsp_trt_buf.nline, index)){
+              r_xram_rsp_fsm = XRAM_RSP_INVAL_WAIT;
+#ifdef IDEBUG
+	std::cout << "XRAM_RSP FSM in XRAM_RSP_INVAL_LOCK state to XRAM_RSP_INVAL_WAIT state" << std::endl;
+#endif
+
+            }
+	    else if(m_update_tab.is_full() && r_xram_rsp_victim_inval.read()){
+	      r_xram_rsp_fsm = XRAM_RSP_INVAL_WAIT;
+#ifdef IDEBUG
+	std::cout << "XRAM_RSP FSM in XRAM_RSP_INVAL_LOCK state to XRAM_RSP_INVAL_WAIT state" << std::endl;
+#endif
+	    }
+            else {
+              r_xram_rsp_fsm = XRAM_RSP_DIR_UPDT;
+#ifdef IDEBUG
+	std::cout << "XRAM_RSP FSM in XRAM_RSP_INVAL_LOCK state to XRAM_RSP_DIR_UPDT state" << std::endl;
+#endif
+            }
+          }
+          break;
+        }
+        ///////////////////////
+      case XRAM_RSP_INVAL_WAIT:
+        {
+          r_xram_rsp_fsm = XRAM_RSP_DIR_LOCK;
+          break;
+#ifdef IDEBUG
+	std::cout << "XRAM_RSP FSM in XRAM_RSP_INVAL_WAIT state" << std::endl;
+#endif
+        }
+        ///////////////////////
+      case XRAM_RSP_DIR_UPDT:		// updates the cache (both data & directory)
+        {
+          // signals generation
+          bool inst_read = (r_xram_rsp_trt_buf.trdid & 0x2) && r_xram_rsp_trt_buf.proc_read; // It is an instruction read
+          bool cached_read = (r_xram_rsp_trt_buf.trdid & 0x1) && r_xram_rsp_trt_buf.proc_read ;
+          // update data
+          size_t set   = r_xram_rsp_victim_set.read();
+          size_t way   = r_xram_rsp_victim_way.read();
+          for(size_t i=0; i<m_words ; i++){
+            m_cache_data[way][set][i] = r_xram_rsp_trt_buf.wdata[i];
+          }
+          // compute dirty 
+          bool dirty = false;
+          for(size_t i=0; i<m_words;i++){
+            dirty = dirty || (r_xram_rsp_trt_buf.wdata_be[i] != 0);
+          }
+
+          // update directory
+          DirectoryEntry entry;
+          entry.valid	  = true;
+          entry.is_cnt    = false;
+          entry.lock	  = false;
+          entry.dirty	  = dirty;
+          entry.tag	    = r_xram_rsp_trt_buf.nline / m_sets;
+          if(cached_read) {
+            if(inst_read) {
+              entry.i_copies = 0x1 << r_xram_rsp_trt_buf.srcid;
+              entry.d_copies = 0x0;
+              entry.count    = 1;
+            } else {
+              entry.i_copies = 0x0;
+              entry.d_copies = 0x1 << r_xram_rsp_trt_buf.srcid;
+              entry.count    = 1;
+            }
+          } else {
+            entry.d_copies = 0;
+            entry.i_copies = 0;
+            entry.count    = 0;
+          }
+          m_cache_directory.write(set, way, entry);
+#ifdef IDEBUG
+	   std::cout << "printing the entry : " << std::endl;
+	   entry.print();
+	   std::cout << "done" << std::endl;
+#endif
+
+#ifdef IDEBUG
+	std::cout << sc_time_stamp() << " " << name() << " XRAM_RSP_DIR_UPDT transaction table : " << std::endl;
+	for(size_t i = 0 ; i < m_transaction_tab.size() ; i++)
+	  m_transaction_tab.print(i);
+#endif
+
+          if(r_xram_rsp_victim_inval.read()){
+            bool    brdcast = r_xram_rsp_victim_is_cnt.read();
+            size_t index;
+            size_t count_copies = r_xram_rsp_victim_count.read();
+
+            bool	 wok = m_update_tab.set(false,	// it's an inval transaction
+                brdcast,                          // set brdcast bit
+                false,  // it does not need a response
+                0,
+                0,
+                0,
+                r_xram_rsp_victim_nline.read(),
+                count_copies,
+                index);
+
+#ifdef IDEBUG
+            std::cout << "xram_rsp : record invalidation, time = " << std::dec << m_cpt_cycles << std::endl;
+            m_update_tab.print();
+#endif
+            r_xram_rsp_upt_index = index;
+            if(!wok) {
+              assert(false && "mem_cache error : xram_rsp_dir_upt, an update_tab entry was free but write unsuccessful");
+            }
+          }
+          // If the victim is not dirty, we erase the entry in the TRT
+          if      (!r_xram_rsp_victim_dirty.read()){
+	  m_transaction_tab.erase(r_xram_rsp_trt_index.read());
+
+	  }
+          // Next state
+          if      ( r_xram_rsp_victim_dirty.read())       r_xram_rsp_fsm = XRAM_RSP_TRT_DIRTY;
+          else if ( r_xram_rsp_trt_buf.proc_read  )       r_xram_rsp_fsm = XRAM_RSP_DIR_RSP;
+          else if ( r_xram_rsp_victim_inval.read())       r_xram_rsp_fsm = XRAM_RSP_INVAL;
+          else                                            r_xram_rsp_fsm = XRAM_RSP_IDLE;
+          break;
+        }
+        ////////////////////////
+      case XRAM_RSP_TRT_DIRTY:		// set the TRT entry (write line to XRAM) if the victim is dirty
+        {
+          if ( r_alloc_trt_fsm.read() == ALLOC_TRT_XRAM_RSP ) {
+            m_transaction_tab.set(r_xram_rsp_trt_index.read(),
+                false,				// write to XRAM
+                r_xram_rsp_victim_nline.read(), // line index
+                0,
+                0,
+                0,
+                false,
+                false,
+                0,
+                std::vector<be_t>(m_words,0),
+                std::vector<data_t>(m_words,0) );
+#ifdef IDEBUG
+	std::cout << sc_time_stamp() << " " << name() << " XRAM_RSP_TRT_DIRTY transaction table : " << std::endl;
+	for(size_t i = 0 ; i < m_transaction_tab.size() ; i++)
+	  m_transaction_tab.print(i);
+#endif
+
+            if      ( r_xram_rsp_trt_buf.proc_read  )       r_xram_rsp_fsm = XRAM_RSP_DIR_RSP;
+            else if ( r_xram_rsp_victim_inval.read())       r_xram_rsp_fsm = XRAM_RSP_INVAL;
+            else                                            r_xram_rsp_fsm = XRAM_RSP_WRITE_DIRTY;
+          }
+          break;
+        }
+        //////////////////////
+      case XRAM_RSP_DIR_RSP:     // send a request to TGT_RSP FSM in case of read
+        {
+          if ( !r_xram_rsp_to_tgt_rsp_req ) {
+            r_xram_rsp_to_tgt_rsp_srcid = r_xram_rsp_trt_buf.srcid;
+            r_xram_rsp_to_tgt_rsp_trdid = r_xram_rsp_trt_buf.trdid;
+            r_xram_rsp_to_tgt_rsp_pktid = r_xram_rsp_trt_buf.pktid;
+            for (size_t i=0; i < m_words; i++) {
+              r_xram_rsp_to_tgt_rsp_data[i] = r_xram_rsp_trt_buf.wdata[i];
+              if( r_xram_rsp_trt_buf.single_word ) {
+                r_xram_rsp_to_tgt_rsp_val[i] = (r_xram_rsp_trt_buf.word_index == i);
+              } else {
+                r_xram_rsp_to_tgt_rsp_val[i] = true;
+              }
+            } 
+            r_xram_rsp_to_tgt_rsp_req   = true;
+
+            if      ( r_xram_rsp_victim_inval ) r_xram_rsp_fsm = XRAM_RSP_INVAL;
+            else if ( r_xram_rsp_victim_dirty ) r_xram_rsp_fsm = XRAM_RSP_WRITE_DIRTY; 
+            else                                r_xram_rsp_fsm = XRAM_RSP_IDLE;
+
+#ifdef IDEBUG
+	std::cout << "XRAM_RSP FSM in XRAM_RSP_DIR_RSP state" << std::endl;
+#endif
+          }
+          break;
+        }
+        ////////////////////
+      case XRAM_RSP_INVAL:	// send invalidate request to INIT_CMD FSM
+        {
+          if( !r_xram_rsp_to_init_cmd_req ) {	      
+            r_xram_rsp_to_init_cmd_req      = true; 
+            r_xram_rsp_to_init_cmd_brdcast  = r_xram_rsp_victim_is_cnt.read();
+            r_xram_rsp_to_init_cmd_nline    = r_xram_rsp_victim_nline.read();
+            r_xram_rsp_to_init_cmd_trdid    = r_xram_rsp_upt_index;
+            r_xram_rsp_to_init_cmd_d_copies = r_xram_rsp_victim_d_copies ;
+            r_xram_rsp_to_init_cmd_i_copies = r_xram_rsp_victim_i_copies ;
+            if ( r_xram_rsp_victim_dirty )  r_xram_rsp_fsm = XRAM_RSP_WRITE_DIRTY;
+            else		                    r_xram_rsp_fsm = XRAM_RSP_IDLE;
+#ifdef IDEBUG
+	std::cout << "XRAM_RSP FSM in XRAM_RSP_INVAL state" << std::endl;
+#endif
+          }
+          break;
+        }
+        //////////////////////////
+      case XRAM_RSP_WRITE_DIRTY:	// send a write request to IXR_CMD FSM
+        {
+          if ( !r_xram_rsp_to_ixr_cmd_req ) {
+            r_xram_rsp_to_ixr_cmd_req = true;
+            r_xram_rsp_to_ixr_cmd_nline = r_xram_rsp_victim_nline.read();
+            r_xram_rsp_to_ixr_cmd_trdid = r_xram_rsp_trt_index.read();
+            for(size_t i=0; i<m_words ; i++) {
+              r_xram_rsp_to_ixr_cmd_data[i] = r_xram_rsp_victim_data[i];
+            }
+            m_cpt_write_dirty++;
+            r_xram_rsp_fsm = XRAM_RSP_IDLE;
+#ifdef IDEBUG
+	std::cout << "XRAM_RSP FSM in XRAM_RSP_WRITE_DIRTY state" << std::endl;
+#endif
+          }
+          break;
+        }
+    } // end swich r_xram_rsp_fsm
+
+    ////////////////////////////////////////////////////////////////////////////////////
+    //		CLEANUP FSM
+    ////////////////////////////////////////////////////////////////////////////////////
+    // The CLEANUP FSM handles the cleanup request from L1 caches.
+    // It accesses the cache directory to update the list of copies.
+    //
+    ////////////////////////////////////////////////////////////////////////////////////
+    switch ( r_cleanup_fsm.read() ) {
+
+      ///////////////////
+      case CLEANUP_IDLE:
+        {        
+          if ( p_vci_tgt_cleanup.cmdval.read() ) {
+            
+            assert( (p_vci_tgt_cleanup.srcid.read() < m_initiators) &&
+                "VCI_MEM_CACHE error in VCI_MEM_CACHE in the CLEANUP network : The received SRCID is larger than 31");
+
+            addr_t nline_addr = ( ((addr_t) p_vci_tgt_cleanup.be.read()) << 32) 
+                                | ((addr_t) p_vci_tgt_cleanup.wdata.read());
+
+            bool reached = false;
+            for ( size_t index = 0 ; index < ncseg && !reached ; index++ ){
+              if ( m_cseg[index]->contains((addr_t)(p_vci_tgt_cleanup.address.read())) ){
+                reached = true;
+              }
+            }
+            if ( (p_vci_tgt_cleanup.cmd.read() == vci_param::CMD_WRITE) &&
+                (((addr_t)(p_vci_tgt_cleanup.address.read())) != m_broadcast_address) &&
+                reached) {
+
+              m_cpt_cleanup++;
+
+              r_cleanup_nline      = nline_addr;
+              r_cleanup_srcid      = p_vci_tgt_cleanup.srcid.read();
+              r_cleanup_trdid      = p_vci_tgt_cleanup.trdid.read();
+              r_cleanup_pktid      = p_vci_tgt_cleanup.pktid.read();
+
+#ifdef VHDL_ACCURATE
+              r_cleanup_pass       = false;
+#endif
+              r_cleanup_fsm        = CLEANUP_DIR_LOCK;
+
+#ifdef DEBUG_CLEANUP
+              std::cout << "Cleanup Received" << std::endl;
+              std::cout << "MemCache address: ";
+              std::cout << std::hex << p_vci_tgt_cleanup.address.read();
+              std::cout << std::endl;
+              std::cout << "SrcId: ";
+              std::cout << std::hex << p_vci_tgt_cleanup.srcid.read();
+              std::cout << std::endl;
+              std::cout << "Cache Line Address: ";
+              std::cout << std::hex << nline_addr;
+              std::cout << std::endl;
+#endif
+            }
+          }
+          break;
+        }
+        //////////////////////
+      case CLEANUP_DIR_LOCK:
+        {
+          if ( r_alloc_dir_fsm.read() == ALLOC_DIR_CLEANUP ) {
+#ifdef VHDL_ACCURATE
+            if (!r_cleanup_pass.read()){
+#endif
+              // Read the directory
+              size_t way = 0;
+              addr_t cleanup_address = r_cleanup_nline.read() * m_words * 4;
+              DirectoryEntry entry = m_cache_directory.read(cleanup_address , way);
+#ifdef IDEBUG
+	   std::cout << "In CLEANUP_DIR_LOCK printing the entry of address is : " << std::hex << cleanup_address << std::endl;
+	   entry.print();
+	   std::cout << "done" << std::endl;
+#endif
+              r_cleanup_is_cnt    = entry.is_cnt;
+              r_cleanup_dirty	    = entry.dirty;
+              r_cleanup_tag	    = entry.tag;
+              r_cleanup_lock	    = entry.lock;
+              r_cleanup_way	    = way;
+              r_cleanup_d_copies  = entry.d_copies;
+              r_cleanup_i_copies  = entry.i_copies;
+              r_cleanup_count     = entry.count;
+
+              // In case of hit, the copy must be cleaned in the copies bit-vector
+              if( entry.valid )  { 
+                r_cleanup_fsm = CLEANUP_DIR_LOCK;
+              } else {
+                r_cleanup_fsm = CLEANUP_UPT_LOCK;
+              }
+#ifdef VHDL_ACCURATE
+              r_cleanup_pass = true;
+            }else{
+              r_cleanup_pass = false;
+              r_cleanup_fsm  = CLEANUP_DIR_WRITE;
+            }
+#endif
+          }
+          break;
+        }
+        ///////////////////////
+      case CLEANUP_DIR_WRITE:
+        {
+          size_t way      = r_cleanup_way.read();
+#define L2 soclib::common::uint32_log2
+          size_t set      = m_y[(vci_addr_t)(r_cleanup_nline.read() << (L2(m_words) +2))];
+#undef L2
+          bool cleanup_inst  = r_cleanup_trdid.read() & 0x1; 
+
+          // update the cache directory (for the copies)
+          DirectoryEntry entry;
+          entry.valid	= true;
+          entry.is_cnt  = r_cleanup_is_cnt.read();
+          entry.dirty	= r_cleanup_dirty.read();
+          entry.tag	= r_cleanup_tag.read();
+          entry.lock	= r_cleanup_lock.read();
+          if(r_cleanup_is_cnt.read()) { // Directory is a counter
+            entry.count  = r_cleanup_count.read() -1;
+            entry.i_copies = 0;
+            entry.d_copies = 0;
+            // response to the cache 
+            r_cleanup_fsm = CLEANUP_RSP;
+          }
+          else{                         // Directory is a vector
+            if(cleanup_inst){           // Cleanup from a ICACHE
+              if(r_cleanup_i_copies.read() & (0x1 << r_cleanup_srcid.read())){ // hit
+                entry.count  = r_cleanup_count.read() -1;
+                r_cleanup_fsm = CLEANUP_RSP;
+              } else { // miss
+                assert(false && "MemCache ERROR : Cleanup instruction hit but the line is not shared");
+              }
+              entry.i_copies  = r_cleanup_i_copies.read() & ~(0x1 << r_cleanup_srcid.read());
+              entry.d_copies  = r_cleanup_d_copies.read();
+            } else {                    // Cleanup from a DCACHE
+              if(r_cleanup_d_copies.read() & (0x1 << r_cleanup_srcid.read())){ // hit
+                entry.count  = r_cleanup_count.read() -1;
+                r_cleanup_fsm = CLEANUP_RSP; 
+              } else { // miss
+                assert(false && "MemCache ERROR : Cleanup data hit but the line is not shared");
+              }
+              entry.i_copies  = r_cleanup_i_copies.read();
+              entry.d_copies  = r_cleanup_d_copies.read() & ~(0x1 << r_cleanup_srcid.read());
+            }
+          }
+          m_cache_directory.write(set, way, entry);  
+
+          break;
+        }
+        /////////////////
+      case CLEANUP_UPT_LOCK:
+        {
+          if( r_alloc_upt_fsm.read() == ALLOC_UPT_CLEANUP )
+          {
+            size_t index=0;
+            bool hit_inval;
+            hit_inval = m_update_tab.search_inval(r_cleanup_nline.read(),index);
+            if(!hit_inval) {
+#ifdef DEBUG_VCI_MEM_CACHE
+              std::cout << "MEM_CACHE WARNING: cleanup with no corresponding entry at address : " << std::hex << (r_cleanup_nline.read()*4*m_words) << std::dec << std::endl;
+#endif
+              r_cleanup_fsm = CLEANUP_RSP;
+            } else {
+              r_cleanup_write_srcid = m_update_tab.srcid(index);
+              r_cleanup_write_trdid = m_update_tab.trdid(index);
+              r_cleanup_write_pktid = m_update_tab.pktid(index);
+              r_cleanup_need_rsp    = m_update_tab.need_rsp(index);
+              r_cleanup_fsm = CLEANUP_UPT_WRITE;
+            }
+            r_cleanup_index.write(index) ; 
+          }
+          break;
+        }
+        /////////////////
+      case CLEANUP_UPT_WRITE:
+        {
+          size_t count = 0;
+          m_update_tab.decrement(r_cleanup_index.read(), count); // &count
+          if(count == 0){
+            m_update_tab.clear(r_cleanup_index.read());
+#ifdef IDEBUG
+	std::cout << sc_time_stamp() << " " << name() << " CLEANUP_UPT_WRITE update table : " << std::endl;
+	m_update_tab.print();
+#endif
+
+            if(r_cleanup_need_rsp.read()){
+              r_cleanup_fsm = CLEANUP_WRITE_RSP ;
+            } else {
+              r_cleanup_fsm = CLEANUP_RSP;
+            }
+          } else {
+            r_cleanup_fsm = CLEANUP_RSP ;
+          }
+          break;
+        }
+        /////////////////
+      case CLEANUP_WRITE_RSP:
+        {
+          if( !r_cleanup_to_tgt_rsp_req.read()) {
+            r_cleanup_to_tgt_rsp_req     = true;
+            r_cleanup_to_tgt_rsp_srcid   = r_cleanup_write_srcid.read();
+            r_cleanup_to_tgt_rsp_trdid   = r_cleanup_write_trdid.read();
+            r_cleanup_to_tgt_rsp_pktid   = r_cleanup_write_pktid.read();
+            r_cleanup_fsm = CLEANUP_RSP;
+          }
+          break;
+        }
+        /////////////////
+      case CLEANUP_RSP:
+        {
+          if(p_vci_tgt_cleanup.rspack)
+            r_cleanup_fsm = CLEANUP_IDLE;
+          break;
+        }
+    } // end switch cleanup fsm
+
+
+    ////////////////////////////////////////////////////////////////////////////////////
+    //		LLSC FSM
+    ////////////////////////////////////////////////////////////////////////////////////
+    // The LLSC FSM handles the LL & SC atomic access.
+    //
+    // For a LL :
+    // It access the directory to check hit / miss.
+    // - In case of hit, the LL request is registered in the Atomic Table and the
+    // response is sent to the requesting processor.
+    // - In case of miss, the LLSC FSM accesses the transaction table. 
+    // If a read transaction to the XRAM for this line already exists, 
+    // or if the transaction table is full, it returns to IDLE state.
+    // Otherwise, a new transaction to the XRAM is initiated.
+    // In both cases, the LL request is not consumed in the FIFO.
+    //
+    // For a SC :
+    // It access the directory to check hit / miss.
+    // - In case of hit, the Atomic Table is checked and the proper response
+    // (true or false is sent to the requesting processor.
+    // - In case of miss, the LLSC FSM accesses the transaction table. 
+    // If a read transaction to the XRAM for this line already exists, 
+    // or if the transaction table is full, it returns to IDLE state. 
+    // Otherwise, a new transaction to the XRAM is initiated.
+    // In both cases, the SC request is not consumed in the FIFO.
+    /////////////////////////////////////////////////////////////////////
+
+    switch ( r_llsc_fsm.read() ) {
+
+      ///////////////
+      case LLSC_IDLE:		// test LL / SC
+        {
+          if( m_cmd_llsc_addr_fifo.rok() ) {
+#ifdef VHDL_ACCURATE
+            r_llsc_pass = false;
+#endif
+            if(m_cmd_llsc_sc_fifo.read()){
+              m_cpt_sc++;
+              r_llsc_fsm = SC_DIR_LOCK;
+            }
+            else{
+              m_cpt_ll++;
+              r_llsc_fsm = LL_DIR_LOCK;
+            }
+          }	
+          break;
+        }
+        /////////////////
+      case LL_DIR_LOCK:		// check directory for hit / miss
+        {
+          if( r_alloc_dir_fsm.read() == ALLOC_DIR_LLSC ) {
+#ifdef VHDL_ACCURATE
+            if (!r_llsc_pass.read()){
+#endif
+              size_t way = 0;
+              DirectoryEntry entry(m_cache_directory.read(m_cmd_llsc_addr_fifo.read(), way));
+              r_llsc_is_cnt     = entry.is_cnt;
+              r_llsc_dirty      = entry.dirty;
+              r_llsc_tag        = entry.tag;
+              r_llsc_way        = way;
+              r_llsc_d_copies   = entry.d_copies;
+              r_llsc_i_copies   = entry.i_copies ;
+              r_llsc_count      = entry.count ;
+
+              if ( entry.valid )  r_llsc_fsm = LL_DIR_LOCK;
+              else                r_llsc_fsm = LLSC_TRT_LOCK;
+#ifdef VHDL_ACCURATE
+              r_llsc_pass        = true;
+            }else{
+              r_llsc_pass        = false;
+              r_llsc_fsm         = LL_DIR_HIT;
+            }
+#endif
+          }
+          break;
+        }
+        ////////////////
+      case LL_DIR_HIT:		// read hit : update the memory cache
+        {
+          size_t way	= r_llsc_way.read();
+          size_t set	= m_y[(vci_addr_t)(m_cmd_llsc_addr_fifo.read())];
+          size_t word	= m_x[(vci_addr_t)(m_cmd_llsc_addr_fifo.read())];
+
+          // update directory (lock bit & copies)
+          DirectoryEntry entry;
+          entry.valid	    = true;
+          entry.is_cnt      = r_llsc_is_cnt.read();
+          entry.dirty	    = r_llsc_dirty.read();
+          entry.lock	    = true;
+          entry.tag	        = r_llsc_tag.read();
+          entry.d_copies    = r_llsc_d_copies.read();
+          entry.i_copies    = r_llsc_i_copies.read();
+          entry.count       = r_llsc_count.read();
+          m_cache_directory.write(set, way, entry);
+
+          // read data in cache
+          r_llsc_data	= m_cache_data[way][set][word];
+
+          // set Atomic Table
+          m_atomic_tab.set(m_cmd_llsc_srcid_fifo.read(), m_cmd_llsc_addr_fifo.read());
+
+          r_llsc_fsm 	= LL_RSP;
+          break;
+        }
+        ////////////
+      case LL_RSP:		// request the TGT_RSP FSM to return data
+        {
+          if ( !r_llsc_to_tgt_rsp_req ) {
+            cmd_llsc_fifo_get		= true;
+            r_llsc_to_tgt_rsp_data	= r_llsc_data.read();
+            r_llsc_to_tgt_rsp_srcid	= m_cmd_llsc_srcid_fifo.read();
+            r_llsc_to_tgt_rsp_trdid	= m_cmd_llsc_trdid_fifo.read();
+            r_llsc_to_tgt_rsp_pktid	= m_cmd_llsc_pktid_fifo.read();
+            r_llsc_to_tgt_rsp_req	= true;
+            r_llsc_fsm = LLSC_IDLE;
+          }
+          break;
+        }
+        /////////////////
+      case SC_DIR_LOCK:
+        {
+          if( r_alloc_dir_fsm.read() == ALLOC_DIR_LLSC ) {
+#ifdef VHDL_ACCURATE
+            if(!r_llsc_pass.read()){
+#endif
+              size_t way = 0;
+              DirectoryEntry entry(m_cache_directory.read(m_cmd_llsc_addr_fifo.read(), way));
+              bool ok = m_atomic_tab.isatomic(m_cmd_llsc_srcid_fifo.read(),m_cmd_llsc_addr_fifo.read());
+              if( ok ) {
+                r_llsc_is_cnt   = entry.is_cnt;
+                r_llsc_dirty    = entry.dirty;
+                r_llsc_tag      = entry.tag;
+                r_llsc_way      = way;
+                r_llsc_d_copies = entry.d_copies;
+                r_llsc_i_copies = entry.i_copies;
+                r_llsc_count    = entry.count;
+              /* to avoid livelock, force the atomic access to fail (pseudo-)randomly */
+                bool fail = (r_llsc_lfsr % (64) == 0);
+                r_llsc_lfsr = (r_llsc_lfsr >> 1) ^ ((-(r_llsc_lfsr & 1)) & 0xd0000001);
+#ifdef RANDOMIZE_SC
+                if(fail){
+#else
+                if(0){
+#endif
+                  r_llsc_fsm = SC_RSP_FALSE;
+                } else {
+                  if ( entry.valid )  r_llsc_fsm = SC_DIR_LOCK;
+                  else                r_llsc_fsm = LLSC_TRT_LOCK;
+                }
+              } else {
+                r_llsc_fsm = SC_RSP_FALSE;
+              }
+#ifdef VHDL_ACCURATE
+              r_llsc_pass       = true;
+            }else{
+              r_llsc_pass       = false;
+              r_llsc_fsm        = SC_DIR_HIT;
+            }
+#endif
+          }
+          break;
+        }
+        ////////////////
+      case SC_DIR_HIT:
+        {
+          size_t way	= r_llsc_way.read();
+          size_t set	= m_y[(vci_addr_t)(m_cmd_llsc_addr_fifo.read())]; 
+          size_t word	= m_x[(vci_addr_t)(m_cmd_llsc_addr_fifo.read())]; 
+
+          // update directory (lock & dirty bits
+          DirectoryEntry entry;
+          entry.valid	    = true;
+          entry.is_cnt      = r_llsc_is_cnt.read();
+          entry.dirty	    = true;
+          entry.lock	    = true;
+          entry.tag	        = r_llsc_tag.read();
+          entry.d_copies    = r_llsc_d_copies.read();
+          entry.i_copies    = r_llsc_i_copies.read();
+          entry.count       = r_llsc_count.read();
+          m_cache_directory.write(set, way, entry);
+
+          // write data in cache
+          m_cache_data[way][set][word] = m_cmd_llsc_wdata_fifo.read();
+
+          // reset Atomic Table
+          m_atomic_tab.reset(m_cmd_llsc_addr_fifo.read());
+
+          r_llsc_fsm = SC_RSP_TRUE;
+          break;
+        }
+        //////////////////
+      case SC_RSP_FALSE:
+        {
+          if( !r_llsc_to_tgt_rsp_req ) {
+            cmd_llsc_fifo_get		= true;
+            r_llsc_to_tgt_rsp_req	= true;
+            //r_llsc_to_tgt_rsp_data	= 1;
+            r_llsc_to_tgt_rsp_data	= 1; // FIXME: SC done inverted
+            r_llsc_to_tgt_rsp_srcid	= m_cmd_llsc_srcid_fifo.read();
+            r_llsc_to_tgt_rsp_trdid	= m_cmd_llsc_trdid_fifo.read();
+            r_llsc_to_tgt_rsp_pktid	= m_cmd_llsc_pktid_fifo.read();
+            r_llsc_fsm 			    = LLSC_IDLE;
+          }
+          break;
+        }
+        /////////////////
+      case SC_RSP_TRUE:
+        {
+          if( !r_llsc_to_tgt_rsp_req ) {
+            cmd_llsc_fifo_get	    = true;
+            r_llsc_to_tgt_rsp_req	= true;
+            //r_llsc_to_tgt_rsp_data	= 0;
+            r_llsc_to_tgt_rsp_data	= 0; // FIXME: SC done inverted
+            r_llsc_to_tgt_rsp_srcid	= m_cmd_llsc_srcid_fifo.read();
+            r_llsc_to_tgt_rsp_trdid	= m_cmd_llsc_trdid_fifo.read();
+            r_llsc_to_tgt_rsp_pktid	= m_cmd_llsc_pktid_fifo.read();
+            r_llsc_fsm 			    = LLSC_IDLE;
+          }
+          break;
+        }
+        ///////////////////
+      case LLSC_TRT_LOCK:         // read or write miss : check the Transaction Table
+        {
+          if( r_alloc_trt_fsm.read() == ALLOC_TRT_LLSC ) {
+            size_t   index = 0;
+            bool hit_read = m_transaction_tab.hit_read(m_nline[(vci_addr_t)m_cmd_llsc_addr_fifo.read()],index);
+            bool hit_write = m_transaction_tab.hit_write(m_nline[(vci_addr_t)m_cmd_llsc_addr_fifo.read()]);
+            bool wok = !m_transaction_tab.full(index);
+
+            if ( hit_read || !wok || hit_write ) {  // missing line already requested or no space in TRT
+              r_llsc_fsm = LLSC_IDLE;
+            } else {
+              r_llsc_trt_index = index;
+              r_llsc_fsm       = LLSC_TRT_SET;
+            }
+          }
+          break;
+        }
+        //////////////////
+      case LLSC_TRT_SET:	// register the XRAM transaction in Transaction Table
+        {
+          if( r_alloc_trt_fsm.read() == ALLOC_TRT_LLSC ) {
+            bool proc_read = !m_cmd_llsc_sc_fifo.read();
+            if(proc_read){
+              m_transaction_tab.set(r_llsc_trt_index.read(),
+                  true,
+                  m_nline[(vci_addr_t)m_cmd_llsc_addr_fifo.read()],
+                  m_cmd_llsc_srcid_fifo.read(),
+                  m_cmd_llsc_trdid_fifo.read(),
+                  m_cmd_llsc_pktid_fifo.read(),
+                  true,
+                  true,
+                  m_x[(vci_addr_t)(m_cmd_llsc_addr_fifo.read())],
+                  std::vector<be_t>(m_words,0),
+                  std::vector<data_t>(m_words,0));
+            }else{
+              m_transaction_tab.set(r_llsc_trt_index.read(),
+                  true,
+                  m_nline[(vci_addr_t)m_cmd_llsc_addr_fifo.read()],
+                  m_cmd_llsc_srcid_fifo.read(),
+                  m_cmd_llsc_trdid_fifo.read(),
+                  m_cmd_llsc_pktid_fifo.read(),
+                  false,
+                  false,
+                  0,
+                  std::vector<be_t>(m_words,0),
+                  std::vector<data_t>(m_words,0));
+            }
+#ifdef IDEBUG
+	std::cout << sc_time_stamp() << " " << name() << " LLSC_TRT_SET transaction table : " << std::endl;
+	for(size_t i = 0 ; i < m_transaction_tab.size() ; i++)
+	  m_transaction_tab.print(i);
+#endif
+
+            r_llsc_fsm = LLSC_XRAM_REQ;
+          }
+          break;
+        }
+        ///////////////////
+      case LLSC_XRAM_REQ:	// request the IXR_CMD FSM to fetch the missing line
+        {
+          if ( !r_llsc_to_ixr_cmd_req ) {
+            r_llsc_to_ixr_cmd_req        = true;
+            r_llsc_to_ixr_cmd_trdid      = r_llsc_trt_index.read();
+            r_llsc_to_ixr_cmd_nline      = m_nline[(vci_addr_t)m_cmd_llsc_addr_fifo.read()];
+            if( m_cmd_llsc_sc_fifo.read() ) {
+              r_llsc_fsm                 = SC_RSP_FALSE;
+            } else {
+              cmd_llsc_fifo_get          = true;
+              r_llsc_fsm                 = LLSC_IDLE;
+            }
+          }
+          break;
+        }
+    } // end switch r_llsc_fsm
+
+
+    //////////////////////////////////////////////////////////////////////////////
+    //		INIT_CMD FSM
+    //////////////////////////////////////////////////////////////////////////////
+    // The INIT_CMD fsm controls the VCI CMD initiator port, used to update
+    // or invalidate cache lines in L1 caches.
+    // It implements a round-robin priority between the two following requests:
+    // - r_write_to_init_cmd_req : update request from WRITE FSM 
+    // - r_xram_rsp_to_init_cmd_req : invalidate request from XRAM_RSP FSM 
+    // The inval request is a single cell VCI write command containing the 
+    // index of the line to be invalidated.
+    // The update request is a multi-cells VCI write command : The first cell 
+    // contains the index of the cache line to be updated. The second cell contains 
+    // the index of the first modified word in the line. The following cells
+    // contain the data.
+    ///////////////////////////////////////////////////////////////////////////////
+
+    switch ( r_init_cmd_fsm.read() ) {
+
+      //////////////////////// 
+      case INIT_CMD_UPDT_IDLE:	// Invalidate requests have highest priority
+        {
+
+          if ( r_xram_rsp_to_init_cmd_req.read() ) {
+            r_init_cmd_fsm = INIT_CMD_INVAL_SEL;
+            m_cpt_inval++;
+          } else if ( r_write_to_init_cmd_req.read() ) {
+            if(r_write_to_init_cmd_brdcast.read()){
+              r_init_cmd_fsm = INIT_CMD_BRDCAST;
+              m_cpt_inval++;
+              m_cpt_inval_brdcast++;
+            } else {
+              r_init_cmd_fsm = INIT_CMD_UPDT_SEL;
+              m_cpt_update++;
+            }
+          }
+          break;
+        }
+        /////////////////////////
+      case INIT_CMD_INVAL_IDLE:	// Update requests have highest priority
+        {
+          if ( r_write_to_init_cmd_req.read() ) {
+            if(r_write_to_init_cmd_brdcast.read()){
+              r_init_cmd_fsm = INIT_CMD_BRDCAST;
+              m_cpt_inval++;
+              m_cpt_inval_brdcast++;
+            } else {
+              r_init_cmd_fsm = INIT_CMD_UPDT_SEL;
+              m_cpt_update++;
+            }
+          } else if ( r_xram_rsp_to_init_cmd_req.read() ) {
+            r_init_cmd_fsm = INIT_CMD_INVAL_SEL;
+            m_cpt_inval++;
+          }
+          break;
+        }
+        ////////////////////////
+      case INIT_CMD_INVAL_SEL:	// selects L1 caches
+        {
+          if(r_xram_rsp_to_init_cmd_brdcast.read()){
+            m_cpt_inval_brdcast++;
+            r_init_cmd_fsm = INIT_CMD_INVAL_NLINE;
+            break;
+          }
+          if ((r_xram_rsp_to_init_cmd_d_copies.read() == 0) &&
+              (r_xram_rsp_to_init_cmd_i_copies.read() == 0)) {	// no more copies
+            r_xram_rsp_to_init_cmd_req = false;
+            r_init_cmd_fsm = INIT_CMD_INVAL_IDLE;
+            break;
+          }
+          m_cpt_inval_mult++;
+          copy_t copies;
+          bool inst = false;
+          if(r_xram_rsp_to_init_cmd_i_copies.read()){
+            copies = r_xram_rsp_to_init_cmd_i_copies.read();
+            inst = true;
+          } else {
+            copies = r_xram_rsp_to_init_cmd_d_copies.read();
+          }
+          copy_t mask   = 0x1;
+          for ( size_t i=0 ; i<8*sizeof(copy_t) ; i++ ) {
+            if ( copies & mask ) {
+              r_init_cmd_target = i;
+              break;
+            }
+            mask = mask << 1;
+          } // end for 
+          r_init_cmd_fsm = INIT_CMD_INVAL_NLINE;
+          r_init_cmd_inst = inst;
+          if(inst){
+            r_xram_rsp_to_init_cmd_i_copies = copies & ~mask;
+          } else {
+            r_xram_rsp_to_init_cmd_d_copies = copies & ~mask;
+          }
+          break;
+        }
+        ////////////////////////
+      case INIT_CMD_INVAL_NLINE:	// send the cache line index
+        {
+          if ( p_vci_ini.cmdack ) {
+            if ( r_xram_rsp_to_init_cmd_brdcast.read() ) {
+              r_init_cmd_fsm = INIT_CMD_INVAL_IDLE;
+              r_xram_rsp_to_init_cmd_req = false;
+            }
+            else r_init_cmd_fsm = INIT_CMD_INVAL_SEL;
+          }
+          break;
+        }
+        ///////////////////////
+     case INIT_CMD_UPDT_SEL:	// selects the next L1 cache
+       {
+         if ((r_write_to_init_cmd_i_copies.read() == 0) &&
+             (r_write_to_init_cmd_d_copies.read() == 0)) {	// no more copies
+           r_write_to_init_cmd_req = false;
+           r_init_cmd_fsm    = INIT_CMD_UPDT_IDLE;
+         } else {						// select the first target
+           copy_t copies;
+           bool inst = false;
+           if(r_write_to_init_cmd_i_copies.read()){
+             inst   = true;
+             copies = r_write_to_init_cmd_i_copies.read();
+           } else {
+             copies = r_write_to_init_cmd_d_copies.read();
+           } 
+           copy_t mask   = 0x1;
+           for ( size_t i=0 ; i<8*sizeof(copy_t) ; i++ ) {
+             if ( copies & mask ) {
+               r_init_cmd_target = i;
+               break;
+             }
+             mask = mask << 1;
+           } // end for 
+           r_init_cmd_fsm    = INIT_CMD_UPDT_NLINE;
+           r_init_cmd_inst = inst;
+           if(inst){
+             r_write_to_init_cmd_i_copies = copies & ~mask;
+           } else {
+             r_write_to_init_cmd_d_copies = copies & ~mask;
+           }
+           r_init_cmd_cpt    = 0;
+           m_cpt_update_mult++;
+         }
+         break;
+       }
+       /////////////////////////
+      case INIT_CMD_BRDCAST:
+        {
+          if( p_vci_ini.cmdack ) {
+            r_write_to_init_cmd_req = false;
+            r_init_cmd_fsm = INIT_CMD_UPDT_IDLE;
+          }
+          break;
+        }
+        /////////////////////////
+     case INIT_CMD_UPDT_NLINE:	// send the cache line index
+       {
+         if ( p_vci_ini.cmdack ){
+             r_init_cmd_fsm = INIT_CMD_UPDT_INDEX;
+         }
+         break;
+       }
+        /////////////////////////
+      case INIT_CMD_UPDT_INDEX:	// send the first word index
+        {
+
+          if ( p_vci_ini.cmdack )  r_init_cmd_fsm = INIT_CMD_UPDT_DATA;
+          break;
+        }
+        ////////////////////////
+      case INIT_CMD_UPDT_DATA:	// send the data
+        {
+          if ( p_vci_ini.cmdack ) {
+            if ( r_init_cmd_cpt.read() == (r_write_to_init_cmd_count.read()-1) ) {
+              r_init_cmd_fsm = INIT_CMD_UPDT_SEL;
+            } else {
+              r_init_cmd_cpt = r_init_cmd_cpt.read() + 1;
+            }
+          }
+          break;
+        }
+    } // end switch r_init_cmd_fsm
+
+    /////////////////////////////////////////////////////////////////////
+    //		TGT_RSP FSM
+    /////////////////////////////////////////////////////////////////////
+    // The TGT_RSP fsm sends the responses on the VCI target port
+    // with a round robin priority between six requests :
+    // - r_read_to_tgt_rsp_req
+    // - r_write_to_tgt_rsp_req
+    // - r_llsc_to_tgt_rsp_req
+    // - r_cleanup_to_tgt_rsp_req
+    // - r_init_rsp_to_tgt_rsp_req
+    // - r_xram_rsp_to_tgt_rsp_req
+    // The  ordering is :  read > write > llsc > cleanup > xram > init
+    /////////////////////////////////////////////////////////////////////
+
+    switch ( r_tgt_rsp_fsm.read() ) {
+
+      ///////////////////////
+      case TGT_RSP_READ_IDLE:		// write requests have the highest priority
+        {
+
+          if      ( r_write_to_tgt_rsp_req    ) r_tgt_rsp_fsm = TGT_RSP_WRITE;
+          else if ( r_llsc_to_tgt_rsp_req     ) r_tgt_rsp_fsm = TGT_RSP_LLSC;
+          else if ( r_xram_rsp_to_tgt_rsp_req ) r_tgt_rsp_fsm = TGT_RSP_XRAM_TEST;
+          else if ( r_init_rsp_to_tgt_rsp_req ) r_tgt_rsp_fsm = TGT_RSP_INIT;
+          else if ( r_cleanup_to_tgt_rsp_req  ) r_tgt_rsp_fsm = TGT_RSP_CLEANUP;
+          else if ( r_read_to_tgt_rsp_req     ) r_tgt_rsp_fsm = TGT_RSP_READ_TEST;
+          break;
+        }
+        ////////////////////////
+      case TGT_RSP_WRITE_IDLE:		// llsc requests have the highest priority
+        {
+
+          if      ( r_llsc_to_tgt_rsp_req     ) r_tgt_rsp_fsm = TGT_RSP_LLSC;
+          else if ( r_xram_rsp_to_tgt_rsp_req ) r_tgt_rsp_fsm = TGT_RSP_XRAM_TEST;
+          else if ( r_init_rsp_to_tgt_rsp_req ) r_tgt_rsp_fsm = TGT_RSP_INIT;
+          else if ( r_cleanup_to_tgt_rsp_req  ) r_tgt_rsp_fsm = TGT_RSP_CLEANUP;
+          else if ( r_read_to_tgt_rsp_req     ) r_tgt_rsp_fsm = TGT_RSP_READ_TEST;
+          else if ( r_write_to_tgt_rsp_req    ) r_tgt_rsp_fsm = TGT_RSP_WRITE;
+          break;
+        }
+        ///////////////////////
+      case TGT_RSP_LLSC_IDLE:		// cleanup requests have the highest priority
+        {
+
+          if ( r_xram_rsp_to_tgt_rsp_req ) r_tgt_rsp_fsm = TGT_RSP_XRAM_TEST;
+          else if ( r_init_rsp_to_tgt_rsp_req ) r_tgt_rsp_fsm = TGT_RSP_INIT;
+          else if ( r_cleanup_to_tgt_rsp_req  ) r_tgt_rsp_fsm = TGT_RSP_CLEANUP;
+          else if ( r_read_to_tgt_rsp_req     ) r_tgt_rsp_fsm = TGT_RSP_READ_TEST;
+          else if ( r_write_to_tgt_rsp_req    ) r_tgt_rsp_fsm = TGT_RSP_WRITE;
+          else if ( r_llsc_to_tgt_rsp_req     ) r_tgt_rsp_fsm = TGT_RSP_LLSC;
+          break;
+        }
+      case TGT_RSP_XRAM_IDLE:		// init requests have the highest priority
+        {
+
+          if      ( r_init_rsp_to_tgt_rsp_req ) r_tgt_rsp_fsm = TGT_RSP_INIT;
+          else if ( r_cleanup_to_tgt_rsp_req  ) r_tgt_rsp_fsm = TGT_RSP_CLEANUP;
+          else if ( r_read_to_tgt_rsp_req     ) r_tgt_rsp_fsm = TGT_RSP_READ_TEST;
+          else if ( r_write_to_tgt_rsp_req    ) r_tgt_rsp_fsm = TGT_RSP_WRITE;
+          else if ( r_llsc_to_tgt_rsp_req     ) r_tgt_rsp_fsm = TGT_RSP_LLSC;
+          else if ( r_xram_rsp_to_tgt_rsp_req ) r_tgt_rsp_fsm = TGT_RSP_XRAM_TEST;
+          break;
+        }
+        ///////////////////////
+      case TGT_RSP_INIT_IDLE:		// cleanup requests have the highest priority
+        {
+          if      ( r_cleanup_to_tgt_rsp_req  ) r_tgt_rsp_fsm = TGT_RSP_CLEANUP;
+          else if ( r_read_to_tgt_rsp_req     ) r_tgt_rsp_fsm = TGT_RSP_READ_TEST;
+          else if ( r_write_to_tgt_rsp_req    ) r_tgt_rsp_fsm = TGT_RSP_WRITE;
+          else if ( r_llsc_to_tgt_rsp_req     ) r_tgt_rsp_fsm = TGT_RSP_LLSC;
+          else if ( r_xram_rsp_to_tgt_rsp_req ) r_tgt_rsp_fsm = TGT_RSP_XRAM_TEST;
+          else if ( r_init_rsp_to_tgt_rsp_req ) r_tgt_rsp_fsm = TGT_RSP_INIT;
+          break;
+        }
+        ///////////////////////
+      case TGT_RSP_CLEANUP_IDLE:		// read requests have the highest priority
+        {
+          if      ( r_read_to_tgt_rsp_req     ) r_tgt_rsp_fsm = TGT_RSP_READ_TEST;
+          else if ( r_write_to_tgt_rsp_req    ) r_tgt_rsp_fsm = TGT_RSP_WRITE;
+          else if ( r_llsc_to_tgt_rsp_req     ) r_tgt_rsp_fsm = TGT_RSP_LLSC;
+          else if ( r_xram_rsp_to_tgt_rsp_req ) r_tgt_rsp_fsm = TGT_RSP_XRAM_TEST;
+          else if ( r_init_rsp_to_tgt_rsp_req ) r_tgt_rsp_fsm = TGT_RSP_INIT;
+          else if ( r_cleanup_to_tgt_rsp_req  ) r_tgt_rsp_fsm = TGT_RSP_CLEANUP;
+          break;
+        }
+        ///////////////////////
+      case TGT_RSP_READ_TEST:		// test if word or cache line
+        {
+          bool 		line = true;
+          size_t	index;
+          for ( size_t i=0; i< m_words ; i++ ) {
+            line = line && r_read_to_tgt_rsp_val[i];
+            if ( r_read_to_tgt_rsp_val[i] ) index = i;
+          }
+          if ( line ) {
+            r_tgt_rsp_cpt = 0;
+            r_tgt_rsp_fsm = TGT_RSP_READ_LINE;
+          } else {
+            r_tgt_rsp_cpt = index;
+            r_tgt_rsp_fsm = TGT_RSP_READ_WORD;
+          } 
+          break;
+        }
+        ///////////////////////
+      case TGT_RSP_READ_WORD:		// send one word response
+        {
+          if ( p_vci_tgt.rspack ) {
+            r_tgt_rsp_fsm = TGT_RSP_READ_IDLE;
+            r_read_to_tgt_rsp_req = false;
+          }
+          break;
+        }
+        ///////////////////////
+      case TGT_RSP_READ_LINE:		// send one complete cache line
+        {
+          if ( p_vci_tgt.rspack ) {
+            if ( r_tgt_rsp_cpt.read() == (m_words-1) ) {
+              r_tgt_rsp_fsm = TGT_RSP_READ_IDLE;
+              r_read_to_tgt_rsp_req = false;
+            } else {
+              r_tgt_rsp_cpt = r_tgt_rsp_cpt.read() + 1;
+            }
+          }
+          break;
+        }
+        ///////////////////
+      case TGT_RSP_WRITE:		// send the write acknowledge
+        {
+          if ( p_vci_tgt.rspack ) {
+            r_tgt_rsp_fsm = TGT_RSP_WRITE_IDLE;
+            r_write_to_tgt_rsp_req = false;
+          }
+          break;
+        }
+        ///////////////////
+      case TGT_RSP_CLEANUP:		// send the write acknowledge
+        {
+          if ( p_vci_tgt.rspack ) {
+            r_tgt_rsp_fsm = TGT_RSP_CLEANUP_IDLE;
+            r_cleanup_to_tgt_rsp_req = false;
+          }
+          break;
+        }
+        //////////////////
+      case TGT_RSP_LLSC:		// send one atomic word response
+        {
+          if ( p_vci_tgt.rspack ) {
+            r_tgt_rsp_fsm = TGT_RSP_LLSC_IDLE;
+            r_llsc_to_tgt_rsp_req = false;
+          }
+          break;
+        }
+
+      case TGT_RSP_XRAM_TEST:		// test if word or cache line
+        {
+          bool 	line = true;
+          size_t	index;
+          for ( size_t i=0; i< m_words ; i++ ) {
+            line = line && r_xram_rsp_to_tgt_rsp_val[i];
+            if ( r_xram_rsp_to_tgt_rsp_val[i] ) index = i;
+          }
+          if ( line ) {
+            r_tgt_rsp_cpt = 0;
+            r_tgt_rsp_fsm = TGT_RSP_XRAM_LINE;
+          } else {
+            r_tgt_rsp_cpt = index;
+            r_tgt_rsp_fsm = TGT_RSP_XRAM_WORD;
+          } 
+          break;
+        }
+        ///////////////////////
+      case TGT_RSP_XRAM_WORD:		// send one word response
+        {
+          if ( p_vci_tgt.rspack ) {
+            r_tgt_rsp_fsm = TGT_RSP_XRAM_IDLE;
+            r_xram_rsp_to_tgt_rsp_req = false;
+          }
+          break;
+        }
+        ///////////////////////
+      case TGT_RSP_XRAM_LINE:		// send one complete cache line
+        {
+          if ( p_vci_tgt.rspack ) {
+            if ( r_tgt_rsp_cpt.read() == (m_words-1) ) {
+              r_tgt_rsp_fsm = TGT_RSP_XRAM_IDLE;
+              r_xram_rsp_to_tgt_rsp_req = false;
+            } else {
+              r_tgt_rsp_cpt = r_tgt_rsp_cpt.read() + 1;
+            }
+          }
+          break;
+        }
+        ///////////////////
+      case TGT_RSP_INIT:		// send the pending write acknowledge
+        {
+          if ( p_vci_tgt.rspack ) {
+            r_tgt_rsp_fsm = TGT_RSP_INIT_IDLE;
+            r_init_rsp_to_tgt_rsp_req = false;
+          }
+          break;
+        }
+    } // end switch tgt_rsp_fsm
+    ////////////////////////////////////////////////////////////////////////////////////
+    //		NEW ALLOC_UPT FSM
+    ////////////////////////////////////////////////////////////////////////////////////
+    // The ALLOC_UPT FSM allocates the access to the Update/Inval Table (UPT).
+    // with a round robin priority between three FSMs : INIT_RSP > WRITE > XRAM_RSP > CLEANUP 
+    // - The WRITE FSM initiates update transactions and sets  new entry in UPT.
+    // - The XRAM_RSP FSM initiates inval transactions and sets  new entry in UPT.
+    // - The INIT_RSP FSM complete those trasactions and erase the UPT entry.
+    // - The CLEANUP  FSM decrement an entry in UPT.
+    // The resource is always allocated.
+    /////////////////////////////////////////////////////////////////////////////////////
+
+    switch ( r_alloc_upt_fsm.read() ) {
+
+      ////////////////////////
+      case ALLOC_UPT_INIT_RSP:
+        if ( (r_init_rsp_fsm.read() != INIT_RSP_UPT_LOCK) && 
+             (r_init_rsp_fsm.read() != INIT_RSP_UPT_CLEAR) ) 
+        {
+          if      ((r_write_fsm.read() == WRITE_UPT_LOCK) ||
+                   (r_write_fsm.read() == WRITE_INVAL_LOCK))        r_alloc_upt_fsm = ALLOC_UPT_WRITE;
+          else if (r_xram_rsp_fsm.read() == XRAM_RSP_INVAL_LOCK)    r_alloc_upt_fsm = ALLOC_UPT_XRAM_RSP;
+          else if (r_cleanup_fsm.read() == CLEANUP_UPT_LOCK)        r_alloc_upt_fsm = ALLOC_UPT_CLEANUP;
+        }
+        break;
+
+        /////////////////////
+      case ALLOC_UPT_WRITE:
+        if ( (r_write_fsm.read() != WRITE_UPT_LOCK) &&
+             (r_write_fsm.read() != WRITE_INVAL_LOCK)) 
+        {
+          if      (r_xram_rsp_fsm.read() == XRAM_RSP_INVAL_LOCK)    r_alloc_upt_fsm = ALLOC_UPT_XRAM_RSP;
+          else if (r_cleanup_fsm.read() == CLEANUP_UPT_LOCK)        r_alloc_upt_fsm = ALLOC_UPT_CLEANUP;
+          else if (r_init_rsp_fsm.read() == INIT_RSP_UPT_LOCK)      r_alloc_upt_fsm = ALLOC_UPT_INIT_RSP;
+        }
+        break;
+
+        ////////////////////////
+      case ALLOC_UPT_XRAM_RSP:
+        if (r_xram_rsp_fsm.read() != XRAM_RSP_INVAL_LOCK) 
+        { 
+          if       (r_cleanup_fsm.read() == CLEANUP_UPT_LOCK)   r_alloc_upt_fsm = ALLOC_UPT_CLEANUP;
+          else if  (r_init_rsp_fsm.read() == INIT_RSP_UPT_LOCK) r_alloc_upt_fsm = ALLOC_UPT_INIT_RSP;
+          else if ((r_write_fsm.read() == WRITE_UPT_LOCK)   ||
+                   (r_write_fsm.read() == WRITE_INVAL_LOCK))    r_alloc_upt_fsm = ALLOC_UPT_WRITE;
+        }
+        break;
+
+        //////////////////////////
+      case ALLOC_UPT_CLEANUP:
+        if(r_cleanup_fsm.read() != CLEANUP_UPT_LOCK)
+        {
+          if 	   (r_init_rsp_fsm.read() == INIT_RSP_UPT_LOCK)     r_alloc_upt_fsm = ALLOC_UPT_INIT_RSP;
+          else if ((r_write_fsm.read() == WRITE_UPT_LOCK) ||
+                   (r_write_fsm.read() == WRITE_INVAL_LOCK))        r_alloc_upt_fsm = ALLOC_UPT_WRITE;
+          else if (r_xram_rsp_fsm.read() == XRAM_RSP_INVAL_LOCK)    r_alloc_upt_fsm = ALLOC_UPT_XRAM_RSP;
+        }
+        break;
+
+    } // end switch r_alloc_upt_fsm
+
+    ////////////////////////////////////////////////////////////////////////////////////
+    //		ALLOC_DIR FSM
+    ////////////////////////////////////////////////////////////////////////////////////
+    // The ALLOC_DIR FSM allocates the access to the directory and
+    // the data cache with a round robin priority between 5 user FSMs :
+    // The cyclic ordering is READ > WRITE > LLSC > CLEANUP > XRAM_RSP
+    // The ressource is always allocated.
+    /////////////////////////////////////////////////////////////////////////////////////
+
+    switch ( r_alloc_dir_fsm.read() ) {
+
+      ////////////////////
+      case ALLOC_DIR_READ:
+        if ( ( (r_read_fsm.read() != READ_DIR_LOCK) &&
+              (r_read_fsm.read() != READ_TRT_LOCK)     )
+            ||
+            ( (r_read_fsm.read()      == READ_TRT_LOCK)  &&
+              (r_alloc_trt_fsm.read() == ALLOC_TRT_READ)    )  ) 
+        {
+          if        (r_write_fsm.read() == WRITE_DIR_LOCK)          r_alloc_dir_fsm = ALLOC_DIR_WRITE;
+          else if   ((r_llsc_fsm.read() == LL_DIR_LOCK) || 
+                    (r_llsc_fsm.read() == SC_DIR_LOCK))             r_alloc_dir_fsm = ALLOC_DIR_LLSC;
+          else if   (r_cleanup_fsm.read() == CLEANUP_DIR_LOCK)      r_alloc_dir_fsm = ALLOC_DIR_CLEANUP;
+          else if   (r_xram_rsp_fsm.read() == XRAM_RSP_DIR_LOCK)    r_alloc_dir_fsm = ALLOC_DIR_XRAM_RSP;
+        }
+        break;
+
+        /////////////////////
+      case ALLOC_DIR_WRITE:
+        if (( 
+#ifdef VHDL_ACCURATE
+              (r_write_fsm.read() != WRITE_RESET)     &&
+#endif
+              (r_write_fsm.read() != WRITE_DIR_LOCK)     &&
+              (r_write_fsm.read() != WRITE_TRT_LOCK)     &&
+              (r_write_fsm.read() != WRITE_DIR_HIT_READ) &&
+              (r_write_fsm.read() != WRITE_TRT_WRITE_LOCK) &&
+              (r_write_fsm.read() != WRITE_INVAL_LOCK) )
+            ||
+            ( (r_write_fsm.read()     == WRITE_TRT_LOCK) &&
+              (r_alloc_trt_fsm.read() == ALLOC_TRT_WRITE)   )   )
+        {
+          if        ((r_llsc_fsm.read() == LL_DIR_LOCK) || 
+                    (r_llsc_fsm.read() == SC_DIR_LOCK))             r_alloc_dir_fsm = ALLOC_DIR_LLSC;
+          else if   (r_cleanup_fsm.read() == CLEANUP_DIR_LOCK)      r_alloc_dir_fsm = ALLOC_DIR_CLEANUP;
+          else if   (r_xram_rsp_fsm.read() == XRAM_RSP_DIR_LOCK)    r_alloc_dir_fsm = ALLOC_DIR_XRAM_RSP;
+          else if   (r_read_fsm.read() == READ_DIR_LOCK) 	        r_alloc_dir_fsm = ALLOC_DIR_READ;
+        }
+        break;
+
+        ////////////////////
+      case ALLOC_DIR_LLSC:
+        if ( ( (r_llsc_fsm.read() != LL_DIR_LOCK)    &&
+              (r_llsc_fsm.read() != LL_DIR_HIT )    &&
+              (r_llsc_fsm.read() != SC_DIR_LOCK)    &&
+              (r_llsc_fsm.read() != SC_DIR_HIT )    &&
+              (r_llsc_fsm.read() != LLSC_TRT_LOCK )    )
+            || 
+            ( (r_llsc_fsm.read()      == LLSC_TRT_LOCK ) &&
+              (r_alloc_trt_fsm.read() == ALLOC_TRT_LLSC)    ) )
+        {
+          if      (r_cleanup_fsm.read() == CLEANUP_DIR_LOCK)    r_alloc_dir_fsm = ALLOC_DIR_CLEANUP;
+          else if (r_xram_rsp_fsm.read() == XRAM_RSP_DIR_LOCK)  r_alloc_dir_fsm = ALLOC_DIR_XRAM_RSP;
+          else if (r_read_fsm.read() == READ_DIR_LOCK) 	        r_alloc_dir_fsm = ALLOC_DIR_READ;
+          else if (r_write_fsm.read() == WRITE_DIR_LOCK)        r_alloc_dir_fsm = ALLOC_DIR_WRITE;
+        }
+        break;
+
+        ///////////////////////
+      case ALLOC_DIR_CLEANUP:
+        if ( (r_cleanup_fsm.read() != CLEANUP_DIR_LOCK) &&
+            (r_cleanup_fsm.read() != CLEANUP_DIR_WRITE) )
+        {
+          if        (r_xram_rsp_fsm.read() == XRAM_RSP_DIR_LOCK)    r_alloc_dir_fsm = ALLOC_DIR_XRAM_RSP;
+          else if   (r_read_fsm.read() == READ_DIR_LOCK)            r_alloc_dir_fsm = ALLOC_DIR_READ;
+          else if   (r_write_fsm.read() == WRITE_DIR_LOCK)          r_alloc_dir_fsm = ALLOC_DIR_WRITE;
+          else if   ((r_llsc_fsm.read() == LL_DIR_LOCK) || 
+                    (r_llsc_fsm.read() == SC_DIR_LOCK))             r_alloc_dir_fsm = ALLOC_DIR_LLSC;
+        }
+        break;
+        ////////////////////////
+      case ALLOC_DIR_XRAM_RSP:
+        if ( (r_xram_rsp_fsm.read() != XRAM_RSP_DIR_LOCK)  &&
+            (r_xram_rsp_fsm.read() != XRAM_RSP_TRT_COPY)   && 
+            (r_xram_rsp_fsm.read() != XRAM_RSP_INVAL_LOCK))
+        {
+          if      (r_read_fsm.read() == READ_DIR_LOCK) 	        r_alloc_dir_fsm = ALLOC_DIR_READ;
+          else if (r_write_fsm.read() == WRITE_DIR_LOCK)        r_alloc_dir_fsm = ALLOC_DIR_WRITE;
+          else if ( (r_llsc_fsm.read() == LL_DIR_LOCK) || 
+                    (r_llsc_fsm.read() == SC_DIR_LOCK))         r_alloc_dir_fsm = ALLOC_DIR_LLSC;
+          else if (r_cleanup_fsm.read() == CLEANUP_DIR_LOCK)    r_alloc_dir_fsm = ALLOC_DIR_CLEANUP;
+        }
+        break;
+
+    } // end switch alloc_dir_fsm
+
+    ////////////////////////////////////////////////////////////////////////////////////
+    //		ALLOC_TRT FSM
+    ////////////////////////////////////////////////////////////////////////////////////
+    // The ALLOC_TRT fsm allocates the access to the Transaction Table (write buffer)
+    // with a round robin priority between 4 user FSMs :
+    // The cyclic priority is READ > WRITE > LLSC > XRAM_RSP
+    // The ressource is always allocated.
+    ///////////////////////////////////////////////////////////////////////////////////
+
+    switch (r_alloc_trt_fsm) {
+
+      ////////////////////
+      case ALLOC_TRT_READ:
+        if ( r_read_fsm.read() != READ_TRT_LOCK ) 
+        {
+          if      ((r_write_fsm.read() == WRITE_TRT_LOCK)   ||
+                   (r_write_fsm.read() == WRITE_TRT_WRITE_LOCK))    r_alloc_trt_fsm = ALLOC_TRT_WRITE;
+          else if (r_llsc_fsm.read() == LLSC_TRT_LOCK)              r_alloc_trt_fsm = ALLOC_TRT_LLSC;
+          else if (r_xram_rsp_fsm.read() == XRAM_RSP_TRT_COPY)      r_alloc_trt_fsm = ALLOC_TRT_XRAM_RSP;
+          else if ( (r_ixr_rsp_fsm.read() == IXR_RSP_TRT_ERASE) ||
+                    (r_ixr_rsp_fsm.read() == IXR_RSP_TRT_READ) )    r_alloc_trt_fsm = ALLOC_TRT_IXR_RSP;
+        }
+        break;
+        /////////////////////
+      case ALLOC_TRT_WRITE:
+        if ( (r_write_fsm.read() != WRITE_TRT_LOCK) &&
+             (r_write_fsm.read() != WRITE_TRT_WRITE_LOCK) &&
+             (r_write_fsm.read() != WRITE_INVAL_LOCK)) 
+        {
+          if      (r_llsc_fsm.read() == LLSC_TRT_LOCK) 	            r_alloc_trt_fsm = ALLOC_TRT_LLSC;
+          else if (r_xram_rsp_fsm.read() == XRAM_RSP_TRT_COPY)      r_alloc_trt_fsm = ALLOC_TRT_XRAM_RSP;
+          else if ( (r_ixr_rsp_fsm.read() == IXR_RSP_TRT_ERASE) ||
+                    (r_ixr_rsp_fsm.read() == IXR_RSP_TRT_READ))     r_alloc_trt_fsm = ALLOC_TRT_IXR_RSP;
+          else if (r_read_fsm.read() == READ_TRT_LOCK) 	            r_alloc_trt_fsm = ALLOC_TRT_READ;
+        }
+        break;
+        ////////////////////
+      case ALLOC_TRT_LLSC:
+        if ( r_llsc_fsm.read() != LLSC_TRT_LOCK )
+        { 
+          if      (r_xram_rsp_fsm.read() == XRAM_RSP_TRT_COPY)      r_alloc_trt_fsm = ALLOC_TRT_XRAM_RSP;
+          else if ( (r_ixr_rsp_fsm.read() == IXR_RSP_TRT_ERASE) ||
+                    (r_ixr_rsp_fsm.read() == IXR_RSP_TRT_READ))     r_alloc_trt_fsm = ALLOC_TRT_IXR_RSP;
+          else if (r_read_fsm.read() == READ_TRT_LOCK) 	            r_alloc_trt_fsm = ALLOC_TRT_READ;
+          else if ((r_write_fsm.read() == WRITE_TRT_LOCK)     ||
+                   (r_write_fsm.read() == WRITE_TRT_WRITE_LOCK))    r_alloc_trt_fsm = ALLOC_TRT_WRITE;
+        }
+        break;
+        ////////////////////////
+      case ALLOC_TRT_XRAM_RSP:
+        if ( (r_xram_rsp_fsm.read() != XRAM_RSP_TRT_COPY)  &&
+            (r_xram_rsp_fsm.read() != XRAM_RSP_DIR_UPDT)   &&
+            (r_xram_rsp_fsm.read() != XRAM_RSP_INVAL_LOCK)) {
+          if      ( (r_ixr_rsp_fsm.read() == IXR_RSP_TRT_ERASE) ||
+                    (r_ixr_rsp_fsm.read() == IXR_RSP_TRT_READ))     r_alloc_trt_fsm = ALLOC_TRT_IXR_RSP;
+          else if (r_read_fsm.read() == READ_TRT_LOCK) 	            r_alloc_trt_fsm = ALLOC_TRT_READ;
+          else if ((r_write_fsm.read() == WRITE_TRT_LOCK)    ||
+                   (r_write_fsm.read() == WRITE_TRT_WRITE_LOCK))    r_alloc_trt_fsm = ALLOC_TRT_WRITE;
+          else if (r_llsc_fsm.read() == LLSC_TRT_LOCK) 	            r_alloc_trt_fsm = ALLOC_TRT_LLSC;
+        }
+        break;
+        ////////////////////////
+      case ALLOC_TRT_IXR_RSP:
+        if ( (r_ixr_rsp_fsm.read() != IXR_RSP_TRT_ERASE) &&
+            (r_ixr_rsp_fsm.read() != IXR_RSP_TRT_READ) ) {
+          if      (r_read_fsm.read() == READ_TRT_LOCK) 	            r_alloc_trt_fsm = ALLOC_TRT_READ;
+          else if ((r_write_fsm.read() == WRITE_TRT_LOCK)   ||
+                   (r_write_fsm.read() == WRITE_TRT_WRITE_LOCK))    r_alloc_trt_fsm = ALLOC_TRT_WRITE;
+          else if (r_llsc_fsm.read() == LLSC_TRT_LOCK) 	            r_alloc_trt_fsm = ALLOC_TRT_LLSC;
+          else if (r_xram_rsp_fsm.read() == XRAM_RSP_TRT_COPY)      r_alloc_trt_fsm = ALLOC_TRT_XRAM_RSP;
+        }
+        break;
+
+    } // end switch alloc_trt_fsm
+
+    ////////////////////////////////////////////////////////////////////////////////////
+    //		TGT_CMD to READ FIFO
+    ////////////////////////////////////////////////////////////////////////////////////
+
+    if ( cmd_read_fifo_put ) {
+      if ( cmd_read_fifo_get ) {
+        m_cmd_read_addr_fifo.put_and_get((addr_t)(p_vci_tgt.address.read()));
+        m_cmd_read_word_fifo.put_and_get((p_vci_tgt.plen.read() == 4));
+        m_cmd_read_srcid_fifo.put_and_get(p_vci_tgt.srcid.read());
+        m_cmd_read_trdid_fifo.put_and_get(p_vci_tgt.trdid.read());
+        m_cmd_read_pktid_fifo.put_and_get(p_vci_tgt.pktid.read());
+      } else {
+        m_cmd_read_addr_fifo.simple_put((addr_t)(p_vci_tgt.address.read()));
+        m_cmd_read_word_fifo.simple_put((p_vci_tgt.plen.read() == 4));
+        m_cmd_read_srcid_fifo.simple_put(p_vci_tgt.srcid.read());
+        m_cmd_read_trdid_fifo.simple_put(p_vci_tgt.trdid.read());
+        m_cmd_read_pktid_fifo.simple_put(p_vci_tgt.pktid.read());
+      }
+    } else {
+      if ( cmd_read_fifo_get ) {
+        m_cmd_read_addr_fifo.simple_get();
+        m_cmd_read_word_fifo.simple_get();
+        m_cmd_read_srcid_fifo.simple_get();
+        m_cmd_read_trdid_fifo.simple_get();
+        m_cmd_read_pktid_fifo.simple_get();
+      }
+    }
+    /////////////////////////////////////////////////////////////////////
+    //		TGT_CMD to WRITE FIFO
+    /////////////////////////////////////////////////////////////////////
+
+    if ( cmd_write_fifo_put ) {
+      if ( cmd_write_fifo_get ) {
+        m_cmd_write_addr_fifo.put_and_get((addr_t)(p_vci_tgt.address.read()));
+        m_cmd_write_eop_fifo.put_and_get(p_vci_tgt.eop.read());
+        m_cmd_write_srcid_fifo.put_and_get(p_vci_tgt.srcid.read());
+        m_cmd_write_trdid_fifo.put_and_get(p_vci_tgt.trdid.read());
+        m_cmd_write_pktid_fifo.put_and_get(p_vci_tgt.pktid.read());
+        m_cmd_write_data_fifo.put_and_get(p_vci_tgt.wdata.read());
+        m_cmd_write_be_fifo.put_and_get(p_vci_tgt.be.read());
+      } else {
+        m_cmd_write_addr_fifo.simple_put((addr_t)(p_vci_tgt.address.read()));
+        m_cmd_write_eop_fifo.simple_put(p_vci_tgt.eop.read());
+        m_cmd_write_srcid_fifo.simple_put(p_vci_tgt.srcid.read());
+        m_cmd_write_trdid_fifo.simple_put(p_vci_tgt.trdid.read());
+        m_cmd_write_pktid_fifo.simple_put(p_vci_tgt.pktid.read());
+        m_cmd_write_data_fifo.simple_put(p_vci_tgt.wdata.read());
+        m_cmd_write_be_fifo.simple_put(p_vci_tgt.be.read());
+      }
+    } else {
+      if ( cmd_write_fifo_get ) {
+        m_cmd_write_addr_fifo.simple_get();
+        m_cmd_write_eop_fifo.simple_get();
+        m_cmd_write_srcid_fifo.simple_get();
+        m_cmd_write_trdid_fifo.simple_get();
+        m_cmd_write_pktid_fifo.simple_get();
+        m_cmd_write_data_fifo.simple_get();
+        m_cmd_write_be_fifo.simple_get();
+      }
+    }
+    ////////////////////////////////////////////////////////////////////////////////////
+    //		TGT_CMD to LLSC FIFO
+    ////////////////////////////////////////////////////////////////////////////////////
+
+    if ( cmd_llsc_fifo_put ) {
+      if ( cmd_llsc_fifo_get ) {
+        m_cmd_llsc_addr_fifo.put_and_get((addr_t)(p_vci_tgt.address.read()));
+        m_cmd_llsc_sc_fifo.put_and_get(p_vci_tgt.cmd.read() == vci_param::CMD_STORE_COND); 
+        m_cmd_llsc_srcid_fifo.put_and_get(p_vci_tgt.srcid.read());
+        m_cmd_llsc_trdid_fifo.put_and_get(p_vci_tgt.trdid.read());
+        m_cmd_llsc_pktid_fifo.put_and_get(p_vci_tgt.pktid.read());
+        m_cmd_llsc_wdata_fifo.put_and_get(p_vci_tgt.wdata.read());
+      } else {
+        m_cmd_llsc_addr_fifo.simple_put((addr_t)(p_vci_tgt.address.read()));
+        m_cmd_llsc_sc_fifo.simple_put(p_vci_tgt.cmd.read() == vci_param::CMD_STORE_COND); 
+        m_cmd_llsc_srcid_fifo.simple_put(p_vci_tgt.srcid.read());
+        m_cmd_llsc_trdid_fifo.simple_put(p_vci_tgt.trdid.read());
+        m_cmd_llsc_pktid_fifo.simple_put(p_vci_tgt.pktid.read());
+        m_cmd_llsc_wdata_fifo.simple_put(p_vci_tgt.wdata.read());
+      }
+    } else {
+      if ( cmd_llsc_fifo_get ) {
+        m_cmd_llsc_addr_fifo.simple_get();
+        m_cmd_llsc_sc_fifo.simple_get();
+        m_cmd_llsc_srcid_fifo.simple_get();
+        m_cmd_llsc_trdid_fifo.simple_get();
+        m_cmd_llsc_pktid_fifo.simple_get();
+        m_cmd_llsc_wdata_fifo.simple_get();
+      }
+    }
+
+  //////////////////////////////////////////////////////////////
+    m_cpt_cycles++;
+
+  } // end transition()
+
+  /////////////////////////////
+  tmpl(void)::genMoore()
+    /////////////////////////////
+  {
+    ////////////////////////////////////////////////////////////
+    // Command signals on the p_vci_ixr port
+    ////////////////////////////////////////////////////////////
+
+
+    p_vci_ixr.be      = 0xF;
+    p_vci_ixr.pktid   = 0;
+    p_vci_ixr.srcid   = m_srcid_ixr;
+    p_vci_ixr.cons    = false;
+    p_vci_ixr.wrap    = false;
+    p_vci_ixr.contig  = true;
+    p_vci_ixr.clen    = 0;
+    p_vci_ixr.cfixed  = false;
+
+    if ( r_ixr_cmd_fsm.read() == IXR_CMD_READ_NLINE ) {
+      p_vci_ixr.cmd     = vci_param::CMD_READ;
+      p_vci_ixr.cmdval  = true;
+      p_vci_ixr.address = (addr_t)(r_read_to_ixr_cmd_nline.read()*m_words*4);
+      p_vci_ixr.plen    = m_words*4;
+      p_vci_ixr.wdata   = 0x00000000;
+      p_vci_ixr.trdid   = r_read_to_ixr_cmd_trdid.read();
+      p_vci_ixr.eop     = true;
+    } 
+    else if ( r_ixr_cmd_fsm.read() == IXR_CMD_LLSC_NLINE ) {
+      p_vci_ixr.cmd     = vci_param::CMD_READ;
+      p_vci_ixr.cmdval  = true;
+      p_vci_ixr.address = (addr_t)(r_llsc_to_ixr_cmd_nline.read()*m_words*4);
+      p_vci_ixr.plen    = m_words*4;
+      p_vci_ixr.wdata   = 0x00000000;
+      p_vci_ixr.trdid   = r_llsc_to_ixr_cmd_trdid.read();
+      p_vci_ixr.eop     = true;
+    } 
+    else if ( r_ixr_cmd_fsm.read() == IXR_CMD_WRITE_NLINE ) {
+      if(r_write_to_ixr_cmd_write.read()){
+        p_vci_ixr.cmd     = vci_param::CMD_WRITE;
+        p_vci_ixr.cmdval  = true;
+        p_vci_ixr.address = (addr_t)((r_write_to_ixr_cmd_nline.read()*m_words+r_ixr_cmd_cpt.read())*4);
+        p_vci_ixr.plen    = m_words*4;
+        p_vci_ixr.wdata   = r_write_to_ixr_cmd_data[r_ixr_cmd_cpt.read()].read();
+        p_vci_ixr.trdid   = r_write_to_ixr_cmd_trdid.read();
+        p_vci_ixr.eop     = (r_ixr_cmd_cpt == (m_words-1));
+      } else {
+        p_vci_ixr.cmd     = vci_param::CMD_READ;
+        p_vci_ixr.cmdval  = true;
+        p_vci_ixr.address = (addr_t)(r_write_to_ixr_cmd_nline.read()*m_words*4);
+        p_vci_ixr.plen    = m_words*4;
+        p_vci_ixr.wdata   = 0x00000000;
+        p_vci_ixr.trdid   = r_write_to_ixr_cmd_trdid.read();
+        p_vci_ixr.eop     = true;
+      }
+    } 
+    else if ( r_ixr_cmd_fsm.read() == IXR_CMD_XRAM_DATA ) {
+      p_vci_ixr.cmd     = vci_param::CMD_WRITE;
+      p_vci_ixr.cmdval  = true;
+      p_vci_ixr.address = (addr_t)((r_xram_rsp_to_ixr_cmd_nline.read()*m_words+r_ixr_cmd_cpt.read())*4);
+      p_vci_ixr.plen    = m_words*4;
+      p_vci_ixr.wdata   = r_xram_rsp_to_ixr_cmd_data[r_ixr_cmd_cpt.read()].read();
+      p_vci_ixr.trdid   = r_xram_rsp_to_ixr_cmd_trdid.read();
+      p_vci_ixr.eop     = (r_ixr_cmd_cpt == (m_words-1));
+    } else {
+      p_vci_ixr.cmdval  = false;
+      p_vci_ixr.address = 0;
+      p_vci_ixr.plen    = 0;
+      p_vci_ixr.wdata   = 0;
+      p_vci_ixr.trdid   = 0;
+      p_vci_ixr.eop	= false;
+    }
+
+    ////////////////////////////////////////////////////
+    // Response signals on the p_vci_ixr port
+    ////////////////////////////////////////////////////
+
+    if ( ((r_alloc_trt_fsm.read() == ALLOC_TRT_IXR_RSP) &&
+          (r_ixr_rsp_fsm.read() == IXR_RSP_TRT_READ)) || 
+        (r_ixr_rsp_fsm.read() == IXR_RSP_ACK) ) p_vci_ixr.rspack = true;
+    else                                        p_vci_ixr.rspack = false;
+
+    ////////////////////////////////////////////////////
+    // Command signals on the p_vci_tgt port
+    ////////////////////////////////////////////////////
+
+    switch ((tgt_cmd_fsm_state_e)r_tgt_cmd_fsm.read()) {
+      case TGT_CMD_IDLE:
+        p_vci_tgt.cmdack  = false;
+        break;
+      case TGT_CMD_READ:
+        p_vci_tgt.cmdack  = m_cmd_read_addr_fifo.wok();
+        break;
+      case TGT_CMD_READ_EOP:
+        p_vci_tgt.cmdack  = true;
+        break;
+      case TGT_CMD_WRITE:
+        p_vci_tgt.cmdack  = m_cmd_write_addr_fifo.wok();
+        break;
+      case TGT_CMD_ATOMIC:
+        p_vci_tgt.cmdack  = m_cmd_llsc_addr_fifo.wok();
+        break;
+      default:
+        p_vci_tgt.cmdack = false;
+        break;
+    }
+
+    ////////////////////////////////////////////////////
+    // Response signals on the p_vci_tgt port
+    ////////////////////////////////////////////////////
+    switch ( r_tgt_rsp_fsm.read() ) {
+
+      case TGT_RSP_READ_IDLE:
+      case TGT_RSP_WRITE_IDLE:
+      case TGT_RSP_LLSC_IDLE:
+      case TGT_RSP_XRAM_IDLE:
+      case TGT_RSP_INIT_IDLE:
+      case TGT_RSP_CLEANUP_IDLE:
+      case TGT_RSP_READ_TEST:
+      case TGT_RSP_XRAM_TEST:
+
+        p_vci_tgt.rspval  = false;
+        p_vci_tgt.rsrcid  = 0;
+        p_vci_tgt.rdata   = 0;
+        p_vci_tgt.rpktid  = 0;
+        p_vci_tgt.rtrdid  = 0;
+        p_vci_tgt.rerror  = 0;
+        p_vci_tgt.reop    = false;	
+        break;
+      case TGT_RSP_READ_LINE:
+        p_vci_tgt.rspval   = true;
+        p_vci_tgt.rdata    = r_read_to_tgt_rsp_data[r_tgt_rsp_cpt.read()].read();
+        p_vci_tgt.rsrcid   = r_read_to_tgt_rsp_srcid.read();
+        p_vci_tgt.rtrdid   = r_read_to_tgt_rsp_trdid.read();
+        p_vci_tgt.rpktid   = r_read_to_tgt_rsp_pktid.read();
+        p_vci_tgt.rerror   = 0;
+        p_vci_tgt.reop     = (r_tgt_rsp_cpt.read() == (m_words-1));
+        break;
+      case TGT_RSP_READ_WORD:
+        p_vci_tgt.rspval   = true;
+        p_vci_tgt.rdata    = r_read_to_tgt_rsp_data[r_tgt_rsp_cpt.read()].read();
+        p_vci_tgt.rsrcid   = r_read_to_tgt_rsp_srcid.read();
+        p_vci_tgt.rtrdid   = r_read_to_tgt_rsp_trdid.read();
+        p_vci_tgt.rpktid   = r_read_to_tgt_rsp_pktid.read();
+        p_vci_tgt.rerror   = 0;
+        p_vci_tgt.reop     = true;	
+        break;
+      case TGT_RSP_WRITE:
+        p_vci_tgt.rspval   = true;
+        p_vci_tgt.rdata    = 0;
+        p_vci_tgt.rsrcid   = r_write_to_tgt_rsp_srcid.read();
+        p_vci_tgt.rtrdid   = r_write_to_tgt_rsp_trdid.read();
+        p_vci_tgt.rpktid   = r_write_to_tgt_rsp_pktid.read();
+        p_vci_tgt.rerror   = 0;
+        p_vci_tgt.reop     = true;
+        break;
+      case TGT_RSP_CLEANUP:
+        p_vci_tgt.rspval   = true;
+        p_vci_tgt.rdata    = 0;
+        p_vci_tgt.rsrcid   = r_cleanup_to_tgt_rsp_srcid.read();
+        p_vci_tgt.rtrdid   = r_cleanup_to_tgt_rsp_trdid.read();
+        p_vci_tgt.rpktid   = r_cleanup_to_tgt_rsp_pktid.read();
+        p_vci_tgt.rerror   = 0;
+        p_vci_tgt.reop     = true;
+        break;
+      case TGT_RSP_LLSC:
+        p_vci_tgt.rspval   = true;
+        p_vci_tgt.rdata    = r_llsc_to_tgt_rsp_data.read();
+        p_vci_tgt.rsrcid   = r_llsc_to_tgt_rsp_srcid.read();
+        p_vci_tgt.rtrdid   = r_llsc_to_tgt_rsp_trdid.read();
+        p_vci_tgt.rpktid   = r_llsc_to_tgt_rsp_pktid.read();
+        p_vci_tgt.rerror   = 0;
+        p_vci_tgt.reop     = true;
+        break;
+      case TGT_RSP_XRAM_LINE:
+        p_vci_tgt.rspval   = true;
+        p_vci_tgt.rdata    = r_xram_rsp_to_tgt_rsp_data[r_tgt_rsp_cpt.read()].read();
+        p_vci_tgt.rsrcid   = r_xram_rsp_to_tgt_rsp_srcid.read();
+        p_vci_tgt.rtrdid   = r_xram_rsp_to_tgt_rsp_trdid.read();
+        p_vci_tgt.rpktid   = r_xram_rsp_to_tgt_rsp_pktid.read();
+        p_vci_tgt.rerror   = 0;
+        p_vci_tgt.reop     = (r_tgt_rsp_cpt.read() == (m_words-1));
+        break;
+      case TGT_RSP_XRAM_WORD:
+        p_vci_tgt.rspval   = true;
+        p_vci_tgt.rdata    = r_xram_rsp_to_tgt_rsp_data[r_tgt_rsp_cpt.read()].read();
+        p_vci_tgt.rsrcid   = r_xram_rsp_to_tgt_rsp_srcid.read();
+        p_vci_tgt.rtrdid   = r_xram_rsp_to_tgt_rsp_trdid.read();
+        p_vci_tgt.rpktid   = r_xram_rsp_to_tgt_rsp_pktid.read();
+        p_vci_tgt.rerror   = 0;
+        p_vci_tgt.reop     = true;
+        break;
+      case TGT_RSP_INIT:
+        p_vci_tgt.rspval   = true;
+        p_vci_tgt.rdata    = 0;
+        p_vci_tgt.rsrcid   = r_init_rsp_to_tgt_rsp_srcid.read();
+        p_vci_tgt.rtrdid   = r_init_rsp_to_tgt_rsp_trdid.read();
+        p_vci_tgt.rpktid   = r_init_rsp_to_tgt_rsp_pktid.read();
+        p_vci_tgt.rerror   = 0;
+        p_vci_tgt.reop     = true;	
+        break;
+    } // end switch r_tgt_rsp_fsm
+
+    ///////////////////////////////////////////////////
+    // Command signals on the p_vci_ini port
+    ///////////////////////////////////////////////////
+
+    p_vci_ini.cmd     = vci_param::CMD_WRITE;
+    p_vci_ini.srcid   = m_srcid_ini;
+    p_vci_ini.pktid   = 0;
+    p_vci_ini.cons    = true;
+    p_vci_ini.wrap    = false;
+    p_vci_ini.contig  = false;
+    p_vci_ini.clen    = 0;
+    p_vci_ini.cfixed  = false;
+
+    switch ( r_init_cmd_fsm.read() ) {
+
+      case INIT_CMD_UPDT_IDLE:
+      case INIT_CMD_INVAL_IDLE:
+      case INIT_CMD_UPDT_SEL:
+      case INIT_CMD_INVAL_SEL:
+        p_vci_ini.cmdval  = false;
+        p_vci_ini.address = 0;
+        p_vci_ini.wdata   = 0;
+        p_vci_ini.be      = 0;
+        p_vci_ini.plen    = 0;
+        p_vci_ini.trdid   = 0;
+        p_vci_ini.eop     = false;
+        break;
+      case INIT_CMD_INVAL_NLINE:
+        p_vci_ini.cmdval  = true;
+        if(r_xram_rsp_to_init_cmd_brdcast.read())
+          p_vci_ini.address = m_broadcast_address;
+        else {
+          if(r_init_cmd_inst.read()) {
+            #define L2 soclib::common::uint32_log2
+            p_vci_ini.address = (addr_t)((r_init_cmd_target.read()<<(vci_param::N - L2(m_initiators))) + 8);
+            //p_vci_ini.address = (addr_t)(m_coherence_table[r_init_cmd_target.read()]+8);
+          } else {
+            #define L2 soclib::common::uint32_log2
+            p_vci_ini.address = (addr_t)((r_init_cmd_target.read()<<(vci_param::N - L2(m_initiators))));
+            //p_vci_ini.address = (addr_t)(m_coherence_table[r_init_cmd_target.read()]);
+          }
+        }
+
+        p_vci_ini.wdata   = (uint32_t)r_xram_rsp_to_init_cmd_nline.read();
+        p_vci_ini.be      = ((r_xram_rsp_to_init_cmd_nline.read() >> 32) & 0x3);
+        p_vci_ini.plen    = 4;
+        p_vci_ini.trdid   = r_xram_rsp_to_init_cmd_trdid.read();
+        p_vci_ini.eop     = true;
+        break;
+      case INIT_CMD_BRDCAST:
+
+        p_vci_ini.cmdval  = true;
+        p_vci_ini.address = m_broadcast_address;
+        p_vci_ini.wdata   = (addr_t)r_write_to_init_cmd_nline.read();
+        p_vci_ini.be      = ((r_write_to_init_cmd_nline.read() >> 32) & 0x3);
+        p_vci_ini.plen    = 4 ;
+        p_vci_ini.eop     = true;
+        p_vci_ini.trdid   = r_write_to_init_cmd_trdid.read();
+        break;
+      case INIT_CMD_UPDT_NLINE:
+        p_vci_ini.cmdval  = true;
+        if(r_init_cmd_inst.read()){
+          #define L2 soclib::common::uint32_log2
+          p_vci_ini.address = (addr_t)((r_init_cmd_target.read()<<(vci_param::N - L2(m_initiators))) + 12);
+          #undef L2
+          //p_vci_ini.address = (addr_t)(m_coherence_table[r_init_cmd_target.read()] + 12);
+        } else {
+          #define L2 soclib::common::uint32_log2
+          p_vci_ini.address = (addr_t)((r_init_cmd_target.read()<<(vci_param::N - L2(m_initiators))) + 4);
+          #undef L2
+          //p_vci_ini.address = (addr_t)(m_coherence_table[r_init_cmd_target.read()] + 4);
+        }
+
+        p_vci_ini.wdata   = (uint32_t)r_write_to_init_cmd_nline.read();
+        p_vci_ini.be      = ((r_write_to_init_cmd_nline.read() >> 32 ) & 0x3);
+        p_vci_ini.plen    = 4 * (r_write_to_init_cmd_count.read() + 2);
+        p_vci_ini.eop     = false;
+        p_vci_ini.trdid   = r_write_to_init_cmd_trdid.read();
+        break;
+      case INIT_CMD_UPDT_INDEX:
+        p_vci_ini.cmdval  = true;
+        if(r_init_cmd_inst.read()){
+          #define L2 soclib::common::uint32_log2
+          p_vci_ini.address = (addr_t)((r_init_cmd_target.read()<<(vci_param::N - L2(m_initiators))) + 12);
+          #undef L2
+          //p_vci_ini.address = (addr_t)(m_coherence_table[r_init_cmd_target.read()] + 12);
+        } else {
+          #define L2 soclib::common::uint32_log2
+          p_vci_ini.address = (addr_t)((r_init_cmd_target.read()<<(vci_param::N - L2(m_initiators))) + 4);
+          #undef L2
+          //p_vci_ini.address = (addr_t)(m_coherence_table[r_init_cmd_target.read()] + 4);
+        }
+
+        p_vci_ini.wdata   = r_write_to_init_cmd_index.read();
+        p_vci_ini.be      = 0xF;
+        p_vci_ini.plen    = 4 * (r_write_to_init_cmd_count.read() + 2);
+        p_vci_ini.trdid   = r_write_to_init_cmd_trdid.read();
+        p_vci_ini.eop     = false;
+        break;
+      case INIT_CMD_UPDT_DATA:
+        p_vci_ini.cmdval  = true;
+        if(r_init_cmd_inst.read()){
+          #define L2 soclib::common::uint32_log2
+          p_vci_ini.address = (addr_t)((r_init_cmd_target.read()<<(vci_param::N - L2(m_initiators))) + 12);
+          #undef L2
+          //p_vci_ini.address = (addr_t)(m_coherence_table[r_init_cmd_target.read()] + 12);
+        } else {
+          #define L2 soclib::common::uint32_log2
+          p_vci_ini.address = (addr_t)((r_init_cmd_target.read()<<(vci_param::N - L2(m_initiators))) + 4);
+          #undef L2
+          //p_vci_ini.address = (addr_t)(m_coherence_table[r_init_cmd_target.read()] + 4);
+        }
+
+        p_vci_ini.wdata   = r_write_to_init_cmd_data[r_init_cmd_cpt.read() +
+          r_write_to_init_cmd_index.read()].read();
+        if(r_write_to_init_cmd_we[r_init_cmd_cpt.read() +
+            r_write_to_init_cmd_index.read()].read())  
+          p_vci_ini.be      = 0xF;
+        else			p_vci_ini.be      = 0x0;
+        p_vci_ini.plen    = 4 * (r_write_to_init_cmd_count.read() + 2);
+        p_vci_ini.trdid   = r_write_to_init_cmd_trdid.read();
+        p_vci_ini.eop     = ( r_init_cmd_cpt.read() == (r_write_to_init_cmd_count.read()-1) );
+        break;
+    } // end switch r_init_cmd_fsm
+
+    //////////////////////////////////////////////////////
+    // Response signals on the p_vci_ini port
+    //////////////////////////////////////////////////////
+
+    if ( r_init_rsp_fsm.read() == INIT_RSP_IDLE ) p_vci_ini.rspack  = true;
+    else                                          p_vci_ini.rspack  = false;
+
+    //////////////////////////////////////////////////////
+    // Response signals on the p_vci_tgt_cleanup port
+    //////////////////////////////////////////////////////
+    p_vci_tgt_cleanup.rspval = false;
+    p_vci_tgt_cleanup.rsrcid = 0;
+    p_vci_tgt_cleanup.rdata  = 0;
+    p_vci_tgt_cleanup.rpktid = 0;
+    p_vci_tgt_cleanup.rtrdid = 0;
+    p_vci_tgt_cleanup.rerror = 0;
+    p_vci_tgt_cleanup.reop   = false;
+
+    switch(r_cleanup_fsm.read()){
+      case CLEANUP_IDLE:
+        {
+          p_vci_tgt_cleanup.cmdack = true ;
+          break;
+        }
+      case CLEANUP_DIR_LOCK:
+        {
+          p_vci_tgt_cleanup.cmdack = false ;
+          break;
+        }
+      case CLEANUP_RSP:
+        {
+          p_vci_tgt_cleanup.rspval = true;
+          p_vci_tgt_cleanup.rdata  = 0;
+          p_vci_tgt_cleanup.rsrcid = r_cleanup_srcid.read();
+          p_vci_tgt_cleanup.rpktid = r_cleanup_pktid.read();
+          p_vci_tgt_cleanup.rtrdid = r_cleanup_trdid.read();
+          p_vci_tgt_cleanup.rerror = 0;
+          p_vci_tgt_cleanup.reop   = 1;
+          break;
+        }
+
+    }
+
+  } // end genMoore()
+
+}} // end name space
+
+// Local Variables:
+// tab-width: 4
+// c-basic-offset: 4
+// c-file-offsets:((innamespace . 0)(inline-open . 0))
+// indent-tabs-mode: nil
+// End:
+
+// vim: filetype=cpp:expandtab:shiftwidth=2:tabstop=2
+
Index: branches/v4/modules/vci_mem_cache_v2/caba/metadata/vci_mem_cache_v2.sd
===================================================================
--- branches/v4/modules/vci_mem_cache_v2/caba/metadata/vci_mem_cache_v2.sd	(revision 371)
+++ branches/v4/modules/vci_mem_cache_v2/caba/metadata/vci_mem_cache_v2.sd	(revision 371)
@@ -0,0 +1,47 @@
+
+# -*- python -*-
+
+__id__ = "$Id$"
+__version__ = "$Revision$"
+
+Module('caba:vci_mem_cache_v2',
+       classname = 'soclib::caba::VciMemCacheV2',
+       tmpl_parameters = [parameter.Module('vci_param', default = 'caba:vci_param'),],
+       header_files = ['../source/include/vci_mem_cache_v2.h',
+                       '../source/include/xram_transaction_v2.h',
+                       '../source/include/mem_cache_directory_v2.h',
+                       '../source/include/atomic_tab_v2.h',
+                       '../source/include/update_tab_v2.h',],
+       implementation_files = ['../source/src/vci_mem_cache_v2.cpp',],
+       uses = [Uses('caba:base_module'),
+               Uses('common:loader'),
+               Uses('common:mapping_table'),
+               Uses('caba:generic_fifo'),
+               ],
+       ports = [Port('caba:vci_target', 'p_vci_tgt'),
+		Port('caba:vci_target','p_vci_tgt_cleanup'),
+		Port('caba:vci_initiator','p_vci_ini'),
+		Port('caba:vci_initiator','p_vci_ixr'),
+                Port('caba:bit_in', 'p_resetn', auto = 'resetn'),
+                Port('caba:clock_in', 'p_clk', auto = 'clock'),],
+       instance_parameters = [
+		parameter.Module('mtp', 'common:mapping_table'),
+		parameter.Module('mtc', 'common:mapping_table'),
+		parameter.Module('mtx', 'common:mapping_table'),
+		parameter.IntTab('vci_ixr_index'),
+		parameter.IntTab('vci_ini_index'),
+		parameter.IntTab('vci_tgt_index'),
+		parameter.IntTab('vci_tgt_index_cleanup'),
+       		parameter.Int('nways'),
+		parameter.Int('nsets'),
+		parameter.Int('nwords'),
+		],
+       extensions = [
+          'dsx:get_ident='
+          'vci_ini_index:p_vci_ini:mtc,'
+          'vci_tgt_index_cleanup:p_vci_tgt_cleanup:mtc,'
+          'vci_tgt_index:p_vci_tgt:mtp,'
+          'vci_ixr_index:p_vci_ixr:mtx',
+		'dsx:addressable=vci_tgt_index,vci_tgt_index_cleanup',
+       ],
+)
Index: branches/v4/modules/vci_mem_cache_v2/caba/source/include/atomic_tab_v2.h
===================================================================
--- branches/v4/modules/vci_mem_cache_v2/caba/source/include/atomic_tab_v2.h	(revision 371)
+++ branches/v4/modules/vci_mem_cache_v2/caba/source/include/atomic_tab_v2.h	(revision 371)
@@ -0,0 +1,121 @@
+#ifndef ATOMIC_TAB_V2_H_
+#define ATOMIC_TAB_V2_H_
+
+#include <inttypes.h>
+#include <systemc>
+#include <cassert>
+#include "arithmetics.h"
+
+
+
+////////////////////////////////////////////////////////////////////////
+////////////////////////////////////////////////////////////////////////
+/*                  The atomic access tab                             */
+////////////////////////////////////////////////////////////////////////
+////////////////////////////////////////////////////////////////////////
+
+class AtomicTab{
+    typedef uint32_t size_t;
+    typedef sc_dt::sc_uint<40> addr_t;
+
+private:
+    size_t size_tab;                            // The size of the tab
+    std::vector<addr_t> addr_tab;               // Address entries
+    std::vector<bool>   valid_tab;              // Valid entries
+
+public:
+
+    AtomicTab()
+	: addr_tab(0),
+	  valid_tab(0)
+	{
+    	size_tab=0;
+    }
+
+    AtomicTab(size_t size_tab_i)
+	: addr_tab(size_tab_i),
+	  valid_tab(size_tab_i)
+	{
+	    size_tab=size_tab_i;
+    }
+
+
+    /////////////////////////////////////////////////////////////////////
+    /* The size() function returns the size of the tab */
+    /////////////////////////////////////////////////////////////////////
+    const size_t size(){
+	    return size_tab;
+    }
+
+
+    /////////////////////////////////////////////////////////////////////
+    /* The init() function initializes the transaction tab entries */
+    /////////////////////////////////////////////////////////////////////
+    void init(){
+    	for ( size_t i=0; i<size_tab; i++) {
+		    addr_tab[i]=0;
+		    valid_tab[i]=false;
+    	}
+    }
+
+
+    /////////////////////////////////////////////////////////////////////
+    /* The set() function sets an entry 
+       Arguments :
+       - id : the id of the initiator (index of the entry)
+       - addr : the address of the lock
+     */
+    /////////////////////////////////////////////////////////////////////
+    void set(const size_t id, const addr_t addr){
+	    assert( (id<size_tab) && "Atomic Tab Error : bad entry");
+	    addr_tab[id]=addr;
+	    valid_tab[id]=true;
+	    return;
+    }
+
+
+    /////////////////////////////////////////////////////////////////////
+    /* The isatomic() function tests if the SC request corresponds to an entry
+       Arguments :
+       - id : the id of the initiator (index of the entry)
+       - addr : the address of the lock
+
+       This function return true if the request corresponds
+     */
+    /////////////////////////////////////////////////////////////////////
+    bool isatomic(const size_t id, const addr_t addr){
+	    assert( (id<size_tab) && "Atomic Tab Error : bad entry");
+	    bool test=valid_tab[id];
+	    test=test && (addr == addr_tab[id]);
+	    return test;
+    }
+
+
+    /////////////////////////////////////////////////////////////////////
+    /* The reset() function resets all the entries for this lock
+       Arguments :
+       - addr : the address of the lock
+     */
+    /////////////////////////////////////////////////////////////////////
+    void reset(const addr_t addr){
+	    for(size_t i=0 ; i<size_tab ; i++){
+		    if(addr == addr_tab[i]){
+			    valid_tab[i]=false;
+		    }
+	    }
+	    return;
+    }
+
+};
+ 
+#endif
+
+// Local Variables:
+// tab-width: 4
+// c-basic-offset: 4
+// c-file-offsets:((innamespace . 0)(inline-open . 0))
+// indent-tabs-mode: nil
+// End:
+
+// vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4
+
Index: branches/v4/modules/vci_mem_cache_v2/caba/source/include/mem_cache_directory_v2.h
===================================================================
--- branches/v4/modules/vci_mem_cache_v2/caba/source/include/mem_cache_directory_v2.h	(revision 371)
+++ branches/v4/modules/vci_mem_cache_v2/caba/source/include/mem_cache_directory_v2.h	(revision 371)
@@ -0,0 +1,311 @@
+#ifndef SOCLIB_CABA_MEM_CACHE_DIRECTORY_V2_H
+#define SOCLIB_CABA_MEM_CACHE_DIRECTORY_V2_H 
+
+#include <inttypes.h>
+#include <systemc>
+#include <cassert>
+#include "arithmetics.h"
+
+namespace soclib { namespace caba {
+
+  using namespace sc_core;
+
+  ////////////////////////////////////////////////////////////////////////
+  //                    A LRU entry 
+  ////////////////////////////////////////////////////////////////////////
+  class LruEntry {
+
+    public:
+
+      bool recent;            
+
+      void init()
+      {
+        recent=false;
+      }
+
+  }; // end class LruEntry
+
+  ////////////////////////////////////////////////////////////////////////
+  //                    A directory entry                               
+  ////////////////////////////////////////////////////////////////////////
+  class DirectoryEntry {
+
+    typedef uint32_t tag_t;
+    typedef uint32_t size_t;
+    typedef uint32_t copy_t;
+
+    public:
+
+    bool    valid;                  // entry valid
+    bool    is_cnt;                 // directory entry is a counter
+    bool    dirty;                  // entry dirty
+    bool    lock;                   // entry locked
+    tag_t   tag;                    // tag of the entry
+    copy_t  d_copies;               // vector of copies for data
+    copy_t  i_copies;               // vector of copies for instructions
+    size_t  count;                  // number of copies
+
+    DirectoryEntry()
+    {
+      valid    = false;
+      is_cnt   = false;
+      dirty    = false;
+      lock     = false;
+      tag      = 0;
+      d_copies = 0;
+      i_copies = 0;
+      count    = 0;
+    }
+
+    DirectoryEntry(const DirectoryEntry &source)
+    {
+      valid    = source.valid;
+      is_cnt   = source.is_cnt;
+      dirty    = source.dirty;
+      tag      = source.tag;
+      lock     = source.lock;
+      d_copies = source.d_copies;
+      i_copies = source.i_copies;
+      count    = source.count;
+    }          
+
+    /////////////////////////////////////////////////////////////////////
+    // The init() function initializes the entry 
+    /////////////////////////////////////////////////////////////////////
+    void init()
+    {
+      valid = false;
+      is_cnt= false;
+      dirty = false;
+      lock  = false;
+    }
+
+    /////////////////////////////////////////////////////////////////////
+    // The copy() function copies an existing source entry to a target 
+    /////////////////////////////////////////////////////////////////////
+    void copy(const DirectoryEntry &source)
+    {
+      valid	= source.valid;
+      is_cnt    = source.is_cnt;
+      dirty	= source.dirty;
+      tag	= source.tag;
+      lock	= source.lock;
+      d_copies	= source.d_copies;
+      i_copies	= source.i_copies;
+      count     = source.count;
+    }
+
+    ////////////////////////////////////////////////////////////////////
+    // The print() function prints the entry 
+    ////////////////////////////////////////////////////////////////////
+    void print()
+    {
+      std::cout << "Valid = " << valid << " ; IS COUNT = " << is_cnt << " ; Dirty = " << dirty << " ; Lock = " 
+        << lock << " ; Tag = " << std::hex << tag << " ; d_copies = " << d_copies << " ; i_copies = " << i_copies << " ; count = " << count << std::endl;
+    }
+
+  }; // end class DirectoryEntry
+
+  ////////////////////////////////////////////////////////////////////////
+  //                       The directory  
+  ////////////////////////////////////////////////////////////////////////
+  class CacheDirectory {
+
+    typedef sc_dt::sc_uint<40> addr_t;
+    typedef uint32_t data_t;
+    typedef uint32_t tag_t;
+    typedef uint32_t size_t;
+
+    private:
+
+    // Directory constants
+    size_t					m_ways;
+    size_t					m_sets;
+    size_t					m_words;
+    size_t					m_width;
+
+    // the directory & lru tables
+    DirectoryEntry 				**m_dir_tab;
+    LruEntry	 				**m_lru_tab;
+
+    public:
+
+    ////////////////////////
+    // Constructor
+    ////////////////////////
+    CacheDirectory( size_t ways, size_t sets, size_t words, size_t address_width)	 
+    {
+      m_ways  = ways; 
+      m_sets  = sets;
+      m_words = words;
+      m_width = address_width;
+
+      m_dir_tab = new DirectoryEntry*[sets];
+      for ( size_t i=0; i<sets; i++ ) {
+        m_dir_tab[i] = new DirectoryEntry[ways];
+        for ( size_t j=0 ; j<ways ; j++) m_dir_tab[i][j].init();
+      }
+      m_lru_tab = new LruEntry*[sets];
+      for ( size_t i=0; i<sets; i++ ) {
+        m_lru_tab[i] = new LruEntry[ways];
+        for ( size_t j=0 ; j<ways ; j++) m_lru_tab[i][j].init();
+      }
+    } // end constructor
+
+    /////////////////
+    // Destructor
+    /////////////////
+    ~CacheDirectory()
+    {
+      for(size_t i=0 ; i<m_sets ; i++){
+        delete [] m_dir_tab[i];
+        delete [] m_lru_tab[i];
+      }
+      delete [] m_dir_tab;
+      delete [] m_lru_tab;
+    } // end destructor
+
+    /////////////////////////////////////////////////////////////////////
+    // The read() function reads a directory entry. In case of hit, the
+    // LRU is updated.
+    // Arguments :
+    // - address : the address of the entry 
+    // - way : (return argument) the way of the entry in case of hit
+    // The function returns a copy of a (valid or invalid) entry  
+    /////////////////////////////////////////////////////////////////////
+    DirectoryEntry read(const addr_t &address,size_t &way)
+    {
+
+#define L2 soclib::common::uint32_log2
+      const size_t set = (size_t)(address >> (L2(m_words) + 2)) & (m_sets - 1);
+      const tag_t  tag = (tag_t)(address >> (L2(m_sets) + L2(m_words) + 2));
+#undef L2
+
+      bool hit       = false;
+      for ( size_t i=0 ; i<m_ways ; i++ ) {
+        bool equal = ( m_dir_tab[set][i].tag == tag );
+        bool valid = m_dir_tab[set][i].valid;
+        hit = equal && valid;
+        if ( hit ) {			
+          way = i;
+          break;
+        } 
+      }
+      if ( hit ) {
+        m_lru_tab[set][way].recent = true;
+        return DirectoryEntry(m_dir_tab[set][way]);
+      } else {
+        return DirectoryEntry();
+      }
+    } // end read()
+
+    /////////////////////////////////////////////////////////////////////
+    // The write function writes a new entry, 
+    // and updates the LRU bits if necessary.
+    // Arguments :
+    // - set : the set of the entry
+    // - way : the way of the entry
+    // - entry : the entry value
+    /////////////////////////////////////////////////////////////////////
+    void write(const size_t &set, const size_t &way, const DirectoryEntry &entry)
+    {
+      assert( (set<m_sets) 
+          && "Cache Directory write : The set index is invalid");
+      assert( (way<m_ways) 
+          && "Cache Directory write : The way index is invalid");
+
+      // update Directory
+      m_dir_tab[set][way].copy(entry);
+
+      // update LRU bits
+      bool all_recent = true;
+      for ( size_t i=0 ; i<m_ways ; i++ ) {
+        if ( i != way ) all_recent = m_lru_tab[set][i].recent && all_recent;
+      }
+      if ( all_recent ) {
+        for( size_t i=0 ; i<m_ways ; i++ ) m_lru_tab[set][i].recent = false;
+      } else {
+        m_lru_tab[set][way].recent = true;
+      }
+    } // end write()
+
+    /////////////////////////////////////////////////////////////////////
+    // The print() function prints a selected directory entry
+    // Arguments :
+    // - set : the set of the entry to print
+    // - way : the way of the entry to print
+    /////////////////////////////////////////////////////////////////////
+    void print(const size_t &set, const size_t &way)
+    {
+      std::cout << std::dec << " set : " << set << " ; way : " << way << " ; " ;
+      m_dir_tab[set][way].print();
+    } // end print()
+
+    /////////////////////////////////////////////////////////////////////
+    // The select() function selects a directory entry to evince.
+    // Arguments :
+    // - set   : (input argument) the set to modify
+    // - way   : (return argument) the way to evince
+    /////////////////////////////////////////////////////////////////////
+    DirectoryEntry select(const size_t &set, size_t &way)
+    {
+      assert( (set < m_sets) 
+          && "Cache Directory : (select) The set index is invalid");
+
+      for(size_t i=0; i<m_ways; i++){
+        if(!m_dir_tab[set][i].valid){
+          way=i;
+          return DirectoryEntry(m_dir_tab[set][way]);
+        }
+      }
+      for(size_t i=0; i<m_ways; i++){
+        if(!(m_lru_tab[set][i].recent) && !(m_dir_tab[set][i].lock)){
+          way=i;
+          return DirectoryEntry(m_dir_tab[set][way]);
+        }
+      }
+      for(size_t i=0; i<m_ways; i++){
+        if( !(m_lru_tab[set][i].recent) && (m_dir_tab[set][i].lock)){
+          way=i;
+          return DirectoryEntry(m_dir_tab[set][way]);
+        }
+      }
+      for(size_t i=0; i<m_ways; i++){
+        if( (m_lru_tab[set][i].recent) && !(m_dir_tab[set][i].lock)){
+          way=i;
+          return DirectoryEntry(m_dir_tab[set][way]);
+        }
+      }
+      way = 0;
+      return DirectoryEntry(m_dir_tab[set][0]);
+    } // end select()
+
+    /////////////////////////////////////////////////////////////////////
+    // 		Global initialisation function
+    /////////////////////////////////////////////////////////////////////
+    void init()
+    {
+      for ( size_t set=0 ; set<m_sets ; set++ ) {
+        for ( size_t way=0 ; way<m_ways ; way++ ) {
+          m_dir_tab[set][way].init();
+          m_lru_tab[set][way].init();
+        }
+      }
+    } // end init()
+
+  }; // end class CacheDirectory
+
+}} // end namespaces
+
+#endif
+
+// Local Variables:
+// tab-width: 4
+// c-basic-offset: 4
+// c-file-offsets:((innamespace . 0)(inline-open . 0))
+// indent-tabs-mode: nil
+// End:
+
+// vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4
+
Index: branches/v4/modules/vci_mem_cache_v2/caba/source/include/update_tab_v2.h
===================================================================
--- branches/v4/modules/vci_mem_cache_v2/caba/source/include/update_tab_v2.h	(revision 371)
+++ branches/v4/modules/vci_mem_cache_v2/caba/source/include/update_tab_v2.h	(revision 371)
@@ -0,0 +1,402 @@
+#ifndef UPDATE_TAB_V2_H_
+#define UPDATE_TAB_V2_H_
+
+#include <inttypes.h>
+#include <systemc>
+#include <cassert>
+#include "arithmetics.h"
+
+////////////////////////////////////////////////////////////////////////
+//                  An update tab entry    
+////////////////////////////////////////////////////////////////////////
+class UpdateTabEntry {
+  typedef uint32_t size_t;
+  typedef sc_dt::sc_uint<40> addr_t;
+
+  public:
+  bool 	valid;                // It is a valid pending transaction
+  bool	update;               // It is an update transaction
+  bool  brdcast;              // It is a broadcast invalidate
+  bool  rsp;                  // It needs a response to the initiator
+  size_t 	srcid;        // The srcid of the initiator which wrote the data
+  size_t 	trdid;        // The trdid of the initiator which wrote the data
+  size_t 	pktid;        // The pktid of the initiator which wrote the data
+  addr_t	nline;	      // The identifier of the cache line
+  size_t 	count;        // The number of acknowledge responses to receive
+
+  UpdateTabEntry(){
+    valid	= false;
+    update  = false;
+    brdcast = false;
+    rsp     = false;
+    srcid	= 0;
+    trdid	= 0;
+    pktid	= 0;
+    nline	= 0;
+    count	= 0;
+  }
+
+  UpdateTabEntry(bool   i_valid, 
+      bool   i_update,
+      bool   i_brdcast,
+      bool   i_rsp,
+      size_t i_srcid, 
+      size_t i_trdid, 
+      size_t i_pktid, 
+      addr_t i_nline,
+      size_t i_count) 
+  {
+    valid		= i_valid;
+    update	    = i_update;
+    brdcast     = i_brdcast;
+    rsp         = i_rsp;
+    srcid		= i_srcid;
+    trdid		= i_trdid;
+    pktid		= i_pktid;
+    nline		= i_nline;
+    count		= i_count;
+  }
+
+  UpdateTabEntry(const UpdateTabEntry &source)
+  {
+    valid   = source.valid;
+    update  = source.update;
+    brdcast = source.brdcast;
+    rsp     = source.rsp;
+    srcid   = source.srcid;
+    trdid   = source.trdid;
+    pktid   = source.pktid;
+    nline   = source.nline;
+    count   = source.count;
+  }
+
+  ////////////////////////////////////////////////////
+  // The init() function initializes the entry 
+  ///////////////////////////////////////////////////
+  void init()
+  {
+    valid  = false;
+    update = false;
+    brdcast= false;
+    rsp    = false;
+    srcid  = 0;
+    trdid  = 0;
+    pktid  = 0;
+    nline  = 0;
+    count  = 0;
+  }
+
+  ////////////////////////////////////////////////////////////////////
+  // The copy() function copies an existing entry
+  // Its arguments are :
+  // - source : the update tab entry to copy
+  ////////////////////////////////////////////////////////////////////
+  void copy(const UpdateTabEntry &source)
+  {
+    valid  = source.valid;
+    update = source.update;
+    brdcast= source.brdcast;
+    rsp    = source.rsp;
+    srcid  = source.srcid;
+    trdid  = source.trdid;
+    pktid  = source.pktid;
+    nline  = source.nline;
+    count  = source.count;
+  }
+
+  ////////////////////////////////////////////////////////////////////
+  // The print() function prints the entry  
+  ////////////////////////////////////////////////////////////////////
+  void print(){
+    std::cout << std::dec << "valid  = " << valid  << std::endl;
+    std::cout << "update = " << update << std::endl;
+    std::cout << "brdcast= " << brdcast<< std::endl;
+    std::cout << "rsp    = " << rsp    << std::endl;
+    std::cout << "srcid  = " << srcid  << std::endl; 
+    std::cout << "trdid  = " << trdid  << std::endl; 
+    std::cout << "pktid  = " << pktid  << std::endl; 
+    std::cout << std::hex << "nline  = " << nline  << std::endl;
+    std::cout << std::dec << "count  = " << count  << std::endl;
+  }
+};
+
+////////////////////////////////////////////////////////////////////////
+//                        The update tab             
+////////////////////////////////////////////////////////////////////////
+class UpdateTab{
+
+  typedef uint32_t size_t;
+  typedef sc_dt::sc_uint<40> addr_t;
+
+  private:
+  size_t size_tab;
+  std::vector<UpdateTabEntry> tab;
+
+  public:
+
+  UpdateTab()
+    : tab(0)
+  {
+    size_tab=0;
+  }
+
+  UpdateTab(size_t size_tab_i)
+    : tab(size_tab_i)
+  {
+    size_tab=size_tab_i;
+  }
+
+  ////////////////////////////////////////////////////////////////////
+  // The size() function returns the size of the tab  
+  ////////////////////////////////////////////////////////////////////
+  const size_t size(){
+    return size_tab;
+  }
+
+
+  ////////////////////////////////////////////////////////////////////
+  // The size() function returns the size of the tab  
+  ////////////////////////////////////////////////////////////////////
+  void print(){
+    for(size_t i=0; i<size_tab; i++) {
+      std::cout << "UPDATE TAB ENTRY " << std::dec << i << "--------" << std::endl;
+      tab[i].print();
+    }
+    return;
+  }
+
+
+  /////////////////////////////////////////////////////////////////////
+  // The init() function initializes the tab 
+  /////////////////////////////////////////////////////////////////////
+  void init(){
+    for ( size_t i=0; i<size_tab; i++) {
+      tab[i].init();
+    }
+  }
+
+
+  /////////////////////////////////////////////////////////////////////
+  // The reads() function reads an entry 
+  // Arguments :
+  // - entry : the entry to read
+  // This function returns a copy of the entry.
+  /////////////////////////////////////////////////////////////////////
+  UpdateTabEntry read (size_t entry)
+  {
+    assert(entry<size_tab && "Bad Update Tab Entry");
+    return UpdateTabEntry(tab[entry]);
+  }
+
+  ///////////////////////////////////////////////////////////////////////////
+  // The set() function writes an entry in the Update Table
+  // Arguments :
+  // - update : transaction type (bool)
+  // - srcid : srcid of the initiator
+  // - trdid : trdid of the initiator
+  // - pktid : pktid of the initiator
+  // - count : number of expected responses
+  // - index : (return argument) index of the selected entry
+  // This function returns true if the write successed (an entry was empty).
+  ///////////////////////////////////////////////////////////////////////////
+  bool set(const bool	update,
+      const bool   brdcast,
+      const bool   rsp,
+      const size_t srcid,
+      const size_t trdid,
+      const size_t pktid,
+      const addr_t nline,
+      const size_t count,
+      size_t &index)
+  {
+    for ( size_t i=0 ; i<size_tab ; i++ ) {
+      if( !tab[i].valid ) {
+        tab[i].valid		= true;
+        tab[i].update		= update;
+        tab[i].brdcast      = brdcast;
+        tab[i].rsp          = rsp;
+        tab[i].srcid		= (size_t) srcid;
+        tab[i].trdid		= (size_t) trdid;
+        tab[i].pktid		= (size_t) pktid;
+        tab[i].nline		= (addr_t) nline;
+        tab[i].count		= (size_t) count;
+        index			    = i;
+        return true;
+      }
+    }
+    return false;
+  } // end set()
+
+  /////////////////////////////////////////////////////////////////////
+  // The decrement() function decrements the counter for a given entry.
+  // Arguments :
+  // - index   : the index of the entry
+  // - counter : (return argument) value of the counter after decrement
+  // This function returns true if the entry is valid.
+  /////////////////////////////////////////////////////////////////////
+  bool decrement( const size_t index,
+      size_t &counter ) 
+  {
+    assert((index<size_tab) && "Bad Update Tab Entry");
+    if ( tab[index].valid ) {
+      tab[index].count--;
+      counter = tab[index].count;
+      return true;
+    } else {
+      return false;
+    }
+  }
+
+  /////////////////////////////////////////////////////////////////////
+  // The is_full() function returns true if the table is full
+  /////////////////////////////////////////////////////////////////////
+  bool is_full()
+  {
+    for(size_t i = 0 ; i < size_tab ; i++){
+      if(!tab[i].valid){
+        return false;
+      }
+    }
+    return true;
+  }
+
+  /////////////////////////////////////////////////////////////////////
+  // The need_rsp() function returns the need of a response
+  // Arguments :
+  // - index : the index of the entry
+  /////////////////////////////////////////////////////////////////////
+  bool need_rsp(const size_t index)
+  {
+    assert(index<size_tab && "Bad Update Tab Entry");
+    return tab[index].rsp;	
+  }
+
+  /////////////////////////////////////////////////////////////////////
+  // The is_update() function returns the transaction type
+  // Arguments :
+  // - index : the index of the entry
+  /////////////////////////////////////////////////////////////////////
+  bool is_brdcast(const size_t index)
+  {
+    assert(index<size_tab && "Bad Update Tab Entry");
+    return tab[index].brdcast;	
+  }
+
+  /////////////////////////////////////////////////////////////////////
+  // The is_update() function returns the transaction type
+  // Arguments :
+  // - index : the index of the entry
+  /////////////////////////////////////////////////////////////////////
+  bool is_update(const size_t index)
+  {
+    assert(index<size_tab && "Bad Update Tab Entry");
+    return tab[index].update;	
+  }
+
+  /////////////////////////////////////////////////////////////////////
+  // The srcid() function returns the srcid value
+  // Arguments :
+  // - index : the index of the entry
+  /////////////////////////////////////////////////////////////////////
+  size_t srcid(const size_t index)
+  {
+    assert(index<size_tab && "Bad Update Tab Entry");
+    return tab[index].srcid;	
+  }
+
+  /////////////////////////////////////////////////////////////////////
+  // The trdid() function returns the trdid value
+  // Arguments :
+  // - index : the index of the entry
+  /////////////////////////////////////////////////////////////////////
+  size_t trdid(const size_t index)
+  {
+    assert(index<size_tab && "Bad Update Tab Entry");
+    return tab[index].trdid;	
+  }
+
+  /////////////////////////////////////////////////////////////////////
+  // The pktid() function returns the pktid value
+  // Arguments :
+  // - index : the index of the entry
+  /////////////////////////////////////////////////////////////////////
+  size_t pktid(const size_t index)
+  {
+    assert(index<size_tab && "Bad Update Tab Entry");
+    return tab[index].pktid;	
+  }
+
+  /////////////////////////////////////////////////////////////////////
+  // The nline() function returns the nline value
+  // Arguments :
+  // - index : the index of the entry
+  /////////////////////////////////////////////////////////////////////
+  addr_t nline(const size_t index)
+  {
+    assert(index<size_tab && "Bad Update Tab Entry");
+    return tab[index].nline;
+  }
+
+  /////////////////////////////////////////////////////////////////////
+  // The search_inval() function returns the index of the entry in UPT
+  // Arguments :
+  // - nline : the line number of the entry in the directory
+  /////////////////////////////////////////////////////////////////////
+  bool search_inval(const addr_t nline,size_t &index)
+  {
+    size_t i ;
+
+    for (i = 0 ; i < size_tab ; i++){
+      if((tab[i].nline == nline) && tab[i].valid){
+        if(!tab[i].update){
+          index = i ;
+          return true;
+        }
+      }
+    }
+    return false;
+  }
+
+  /////////////////////////////////////////////////////////////////////
+  // The read_nline() function returns the index of the entry in UPT
+  // Arguments :
+  // - nline : the line number of the entry in the directory
+  /////////////////////////////////////////////////////////////////////
+  bool read_nline(const addr_t nline,size_t &index) 
+  {
+    size_t i ;
+
+    for (i = 0 ; i < size_tab ; i++){
+      if((tab[i].nline == nline) && tab[i].valid){
+        index = i ;
+        return true;
+      }
+    }
+    return false;
+  }
+
+  /////////////////////////////////////////////////////////////////////
+  // The clear() function erases an entry of the tab
+  // Arguments :
+  // - index : the index of the entry
+  /////////////////////////////////////////////////////////////////////       
+  void clear(const size_t index)
+  {
+    assert(index<size_tab && "Bad Update Tab Entry");
+    tab[index].valid=false;
+    return;	
+  }
+
+};
+
+#endif
+
+// Local Variables:
+// tab-width: 4
+// c-basic-offset: 4
+// c-file-offsets:((innamespace . 0)(inline-open . 0))
+// indent-tabs-mode: nil
+// End:
+
+// vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4
+
Index: branches/v4/modules/vci_mem_cache_v2/caba/source/include/vci_mem_cache_v2.h
===================================================================
--- branches/v4/modules/vci_mem_cache_v2/caba/source/include/vci_mem_cache_v2.h	(revision 371)
+++ branches/v4/modules/vci_mem_cache_v2/caba/source/include/vci_mem_cache_v2.h	(revision 371)
@@ -0,0 +1,656 @@
+/* -*- c++ -*-
+ * File         : vci_mem_cache_v2.h
+ * Date         : 26/10/2008
+ * Copyright    : UPMC / LIP6
+ * Authors      : Alain Greiner / Eric Guthmuller
+ *
+ * SOCLIB_LGPL_HEADER_BEGIN
+ *
+ * This file is part of SoCLib, GNU LGPLv2.1.
+ *
+ * SoCLib is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU Lesser General Public License as published
+ * by the Free Software Foundation; version 2.1 of the License.
+ *
+ * SoCLib is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with SoCLib; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301 USA
+ *
+ * SOCLIB_LGPL_HEADER_END
+ *
+ * Maintainers: alain eric.guthmuller@polytechnique.edu
+ */
+/*
+ *
+ * Modifications done by Christophe Choichillon on the 7/04/2009:
+ * - Adding new states in the CLEANUP FSM : CLEANUP_UPT_LOCK and CLEANUP_UPT_WRITE
+ * - Adding a new VCI target port for the CLEANUP network
+ * - Adding new state in the ALLOC_UPT_FSM : ALLOC_UPT_CLEANUP
+ * 
+ * Modifications to do :
+ * - Adding new variables used by the CLEANUP FSM
+ *
+ */
+
+#ifndef SOCLIB_CABA_MEM_CACHE_V2_H
+#define SOCLIB_CABA_MEM_CACHE_V2_H
+
+#include <inttypes.h>
+#include <systemc>
+#include <list>
+#include <cassert>
+#include "arithmetics.h"
+#include "alloc_elems.h"
+#include "caba_base_module.h"
+#include "vci_target.h"
+#include "vci_initiator.h"
+#include "generic_fifo.h"
+#include "mapping_table.h"
+#include "int_tab.h"
+#include "mem_cache_directory_v2.h"
+#include "xram_transaction_v2.h"
+#include "update_tab_v2.h"
+#include "atomic_tab_v2.h"
+
+#define TRANSACTION_TAB_LINES 4     // Number of lines in the transaction tab
+#define UPDATE_TAB_LINES 4          // Number of lines in the update tab
+#define BROADCAST_ADDR 0x0000000003 // Address to send the broadcast invalidate
+
+namespace soclib {  namespace caba {
+  using namespace sc_core;
+
+  template<typename vci_param>
+    class VciMemCacheV2
+    : public soclib::caba::BaseModule
+    {
+      typedef sc_dt::sc_uint<40> addr_t;
+      typedef typename vci_param::fast_addr_t vci_addr_t;
+      typedef uint32_t data_t;
+      typedef uint32_t tag_t;
+      typedef uint32_t size_t;
+      typedef uint32_t be_t;
+      typedef uint32_t copy_t;
+
+      /* States of the TGT_CMD fsm */
+      enum tgt_cmd_fsm_state_e{
+        TGT_CMD_IDLE,
+        TGT_CMD_READ,
+        TGT_CMD_READ_EOP,
+        TGT_CMD_WRITE,
+        TGT_CMD_ATOMIC,
+      };
+
+      /* States of the TGT_RSP fsm */
+      enum tgt_rsp_fsm_state_e{
+        TGT_RSP_READ_IDLE,
+        TGT_RSP_WRITE_IDLE,
+        TGT_RSP_LLSC_IDLE,
+        TGT_RSP_XRAM_IDLE,
+        TGT_RSP_INIT_IDLE,
+        TGT_RSP_CLEANUP_IDLE,
+        TGT_RSP_READ,
+        TGT_RSP_WRITE,
+        TGT_RSP_LLSC,
+        TGT_RSP_XRAM,
+        TGT_RSP_INIT,
+        TGT_RSP_CLEANUP,
+      };
+
+      /* States of the INIT_CMD fsm */
+      enum init_cmd_fsm_state_e{
+        INIT_CMD_INVAL_IDLE,
+        INIT_CMD_INVAL_SEL,
+        INIT_CMD_INVAL_NLINE,
+        INIT_CMD_UPDT_IDLE,
+        INIT_CMD_UPDT_SEL,
+        INIT_CMD_BRDCAST,
+        INIT_CMD_UPDT_NLINE,
+        INIT_CMD_UPDT_INDEX,
+        INIT_CMD_UPDT_DATA,
+        INIT_CMD_SC_UPDT_IDLE,
+        INIT_CMD_SC_UPDT_SEL,
+        INIT_CMD_SC_BRDCAST,
+        INIT_CMD_SC_UPDT_NLINE,
+        INIT_CMD_SC_UPDT_INDEX,
+        INIT_CMD_SC_UPDT_DATA,
+      };
+
+      /* States of the INIT_RSP fsm */
+      enum init_rsp_fsm_state_e{
+        INIT_RSP_IDLE,
+        INIT_RSP_UPT_LOCK,
+        INIT_RSP_UPT_CLEAR,
+        INIT_RSP_END,
+      };
+
+      /* States of the READ fsm */
+      enum read_fsm_state_e{
+        READ_IDLE,
+        READ_DIR_LOCK,
+        READ_DIR_HIT,
+        READ_RSP,
+        READ_TRT_LOCK,
+        READ_TRT_SET,
+        READ_XRAM_REQ,
+      };
+
+      /* States of the WRITE fsm */
+      enum write_fsm_state_e{
+        WRITE_IDLE,
+        WRITE_NEXT,
+        WRITE_DIR_LOCK,
+        WRITE_DIR_HIT_READ,
+        WRITE_DIR_HIT,
+        WRITE_DIR_HIT_RSP,
+        WRITE_UPT_LOCK,
+        WRITE_WAIT_UPT,
+        WRITE_UPDATE,
+        WRITE_RSP,
+        WRITE_TRT_LOCK,
+        WRITE_TRT_DATA,
+        WRITE_TRT_SET,
+        WRITE_WAIT_TRT,
+        WRITE_XRAM_REQ,
+        WRITE_TRT_WRITE_LOCK,
+        WRITE_INVAL_LOCK,
+        WRITE_DIR_INVAL,
+        WRITE_INVAL,
+        WRITE_XRAM_SEND,
+      };
+
+      /* States of the IXR_RSP fsm */
+      enum ixr_rsp_fsm_state_e{
+        IXR_RSP_IDLE,
+        IXR_RSP_ACK,
+        IXR_RSP_TRT_ERASE,
+        IXR_RSP_TRT_READ,
+      };
+
+      /* States of the XRAM_RSP fsm */
+      enum xram_rsp_fsm_state_e{
+        XRAM_RSP_IDLE,
+        XRAM_RSP_TRT_COPY,
+        XRAM_RSP_TRT_DIRTY,
+        XRAM_RSP_DIR_LOCK,
+        XRAM_RSP_DIR_UPDT,
+        XRAM_RSP_DIR_RSP,
+        XRAM_RSP_INVAL_LOCK,
+        XRAM_RSP_INVAL_WAIT,
+        XRAM_RSP_INVAL,
+        XRAM_RSP_WRITE_DIRTY,
+      };
+
+      /* States of the IXR_CMD fsm */
+      enum ixr_cmd_fsm_state_e{
+        IXR_CMD_READ_IDLE,
+        IXR_CMD_WRITE_IDLE,
+        IXR_CMD_LLSC_IDLE,
+        IXR_CMD_XRAM_IDLE,
+        IXR_CMD_READ_NLINE,
+        IXR_CMD_WRITE_NLINE,
+        IXR_CMD_LLSC_NLINE,
+        IXR_CMD_XRAM_DATA,
+      };
+
+      /* States of the LLSC fsm */
+      enum llsc_fsm_state_e{
+        LLSC_IDLE,
+        LL_DIR_LOCK,
+        LL_DIR_HIT,
+        LL_RSP,
+        SC_DIR_LOCK,
+        SC_DIR_HIT,
+        SC_UPT_LOCK,
+        SC_WAIT_UPT,
+        SC_UPDATE,
+        SC_TRT_LOCK,
+        SC_INVAL_LOCK,
+        SC_DIR_INVAL,
+        SC_INVAL,
+        SC_XRAM_SEND,
+        SC_RSP_FALSE,
+        SC_RSP_TRUE,
+        LLSC_TRT_LOCK,
+        LLSC_TRT_SET,
+        LLSC_XRAM_REQ,
+      };
+
+      /* States of the CLEANUP fsm */
+      enum cleanup_fsm_state_e{
+        CLEANUP_IDLE,
+        CLEANUP_DIR_LOCK,
+        CLEANUP_DIR_WRITE,
+        CLEANUP_UPT_LOCK,
+        CLEANUP_UPT_WRITE,
+        CLEANUP_WRITE_RSP,
+        CLEANUP_RSP,
+      };
+
+      /* States of the ALLOC_DIR fsm */
+      enum alloc_dir_fsm_state_e{
+        ALLOC_DIR_READ,
+        ALLOC_DIR_WRITE,
+        ALLOC_DIR_LLSC,
+        ALLOC_DIR_CLEANUP,
+        ALLOC_DIR_XRAM_RSP,
+      };
+
+      /* States of the ALLOC_TRT fsm */
+      enum alloc_trt_fsm_state_e{
+        ALLOC_TRT_READ,
+        ALLOC_TRT_WRITE,
+        ALLOC_TRT_LLSC,
+        ALLOC_TRT_XRAM_RSP,
+        ALLOC_TRT_IXR_RSP,
+      };
+
+      /* States of the ALLOC_UPT fsm */
+      enum alloc_upt_fsm_state_e{
+        ALLOC_UPT_WRITE,
+        ALLOC_UPT_XRAM_RSP,
+        ALLOC_UPT_INIT_RSP,
+        ALLOC_UPT_CLEANUP,
+        ALLOC_UPT_LLSC,
+      };
+
+      uint32_t	   m_cpt_cycles;            // Counter of cycles 
+      uint32_t	   m_cpt_read;              // Number of READ transactions
+      uint32_t	   m_cpt_read_miss;         // Number of MISS READ 
+      uint32_t	   m_cpt_write;             // Number of WRITE transactions
+      uint32_t	   m_cpt_write_miss;        // Number of MISS WRITE
+      uint32_t     m_cpt_write_cells;	    // Cumulated length for WRITE transactions
+      uint32_t     m_cpt_write_dirty;	    // Cumulated length for WRITE transactions
+      uint32_t	   m_cpt_update;            // Number of UPDATE transactions
+      uint32_t	   m_cpt_update_mult;       // Number of targets for UPDATE
+      uint32_t	   m_cpt_inval;             // Number of INVAL  transactions
+      uint32_t	   m_cpt_inval_mult;        // Number of targets for INVAL  
+      uint32_t	   m_cpt_inval_brdcast;     // Number of BROADCAST INVAL  
+      uint32_t	   m_cpt_cleanup;           // Number of CLEANUP transactions
+      uint32_t	   m_cpt_ll;                // Number of LL transactions
+      uint32_t	   m_cpt_sc;                // Number of SC transactions
+
+      protected:
+
+      SC_HAS_PROCESS(VciMemCacheV2);
+
+      public:
+      sc_in<bool> 			  	p_clk;
+      sc_in<bool> 			  	p_resetn;
+      soclib::caba::VciTarget<vci_param>    	p_vci_tgt;
+      soclib::caba::VciTarget<vci_param>    	p_vci_tgt_cleanup;
+      soclib::caba::VciInitiator<vci_param> 	p_vci_ini;	
+      soclib::caba::VciInitiator<vci_param> 	p_vci_ixr;
+
+      VciMemCacheV2(
+          sc_module_name name,                              // Instance Name 
+          const soclib::common::MappingTable &mtp,          // Mapping table for primary requets
+          const soclib::common::MappingTable &mtc,          // Mapping table for coherence requets
+          const soclib::common::MappingTable &mtx,          // Mapping table for XRAM
+          const soclib::common::IntTab &vci_ixr_index,      // VCI port to XRAM (initiator)
+          const soclib::common::IntTab &vci_ini_index,      // VCI port to PROC (initiator)
+          const soclib::common::IntTab &vci_tgt_index,      // VCI port to PROC (target)
+          const soclib::common::IntTab &vci_tgt_index_cleanup,    // VCI port to PROC (target) for cleanup
+          size_t nways,                                   // Number of ways per set 
+          size_t nsets,                                   // Number of sets
+          size_t nwords);                                 // Number of words per line
+
+      ~VciMemCacheV2();
+
+      void transition();
+
+      void genMoore();
+
+      void print_stats();
+
+      private:
+
+      // Component attributes
+      const size_t              m_initiators;           // Number of initiators
+      const size_t              m_ways;                 // Number of ways in a set
+      const size_t              m_sets;                 // Number of cache sets
+      const size_t              m_words;		        // Number of words in a line
+      const size_t              m_srcid_ixr;		    // Srcid for requests to XRAM 
+      const size_t              m_srcid_ini;		    // Srcid for requests to processors
+      std::list<soclib::common::Segment>  m_seglist;    // memory cached into the cache
+      std::list<soclib::common::Segment>  m_cseglist;   // coherence segment for the cache
+      vci_addr_t        		*m_coherence_table; 	// address(srcid)
+      AtomicTab                 m_atomic_tab;           // atomic access table
+      TransactionTab      		m_transaction_tab;	    // xram transaction table
+      UpdateTab                 m_update_tab;		    // pending update & invalidate 
+      CacheDirectory			m_cache_directory;	    // data cache directory
+
+      data_t	        	       ***m_cache_data;		// data array[set][way][word]
+
+      // adress masks
+      const soclib::common::AddressMaskingTable<vci_addr_t>   m_x;
+      const soclib::common::AddressMaskingTable<vci_addr_t>   m_y;
+      const soclib::common::AddressMaskingTable<vci_addr_t>   m_z;
+      const soclib::common::AddressMaskingTable<vci_addr_t>   m_nline; 
+
+      // broadcast address
+      vci_addr_t broadcast_addr;
+
+      //////////////////////////////////////////////////
+      // Others registers
+      //////////////////////////////////////////////////
+      sc_signal<size_t>   r_copies_limit; // Limit of the number of copies for one line
+
+      //////////////////////////////////////////////////
+      // Registers controlled by the TGT_CMD fsm
+      //////////////////////////////////////////////////
+
+      // Fifo between TGT_CMD fsm and READ fsm
+      GenericFifo<uint64_t>  m_cmd_read_addr_fifo;
+      GenericFifo<size_t>    m_cmd_read_length_fifo;
+      GenericFifo<size_t>    m_cmd_read_srcid_fifo;
+      GenericFifo<size_t>    m_cmd_read_trdid_fifo;
+      GenericFifo<size_t>    m_cmd_read_pktid_fifo;
+
+      // Fifo between TGT_CMD fsm and WRITE fsm    
+      GenericFifo<uint64_t>  m_cmd_write_addr_fifo;
+      GenericFifo<bool>      m_cmd_write_eop_fifo;
+      GenericFifo<size_t>    m_cmd_write_srcid_fifo;
+      GenericFifo<size_t>    m_cmd_write_trdid_fifo;
+      GenericFifo<size_t>    m_cmd_write_pktid_fifo;
+      GenericFifo<data_t>    m_cmd_write_data_fifo;
+      GenericFifo<be_t>	     m_cmd_write_be_fifo;
+
+      // Fifo between TGT_CMD fsm and LLSC fsm
+      GenericFifo<uint64_t>  m_cmd_llsc_addr_fifo;
+      GenericFifo<bool>      m_cmd_llsc_sc_fifo;
+      GenericFifo<size_t>    m_cmd_llsc_srcid_fifo;
+      GenericFifo<size_t>    m_cmd_llsc_trdid_fifo;
+      GenericFifo<size_t>    m_cmd_llsc_pktid_fifo;
+      GenericFifo<data_t>    m_cmd_llsc_wdata_fifo;
+
+      sc_signal<int>         r_tgt_cmd_fsm;
+
+      sc_signal<size_t>	     r_index;
+      size_t nseg;
+      size_t ncseg;
+      soclib::common::Segment  **m_seg;
+      soclib::common::Segment  **m_cseg;
+      ///////////////////////////////////////////////////////
+      // Registers controlled by the READ fsm
+      ///////////////////////////////////////////////////////
+
+      sc_signal<int>         r_read_fsm;        // FSM state 
+      sc_signal<copy_t>      r_read_d_copies;   // bit-vector of copies 
+      sc_signal<copy_t>      r_read_i_copies;   // bit-vector of copies 
+      sc_signal<tag_t>       r_read_tag;	    // cache line tag (in directory)
+      sc_signal<bool>        r_read_is_cnt;	    // is_cnt bit (in directory)
+      sc_signal<bool>        r_read_lock;	    // lock bit (in directory)
+      sc_signal<bool>        r_read_dirty;	    // dirty bit (in directory)
+      sc_signal<size_t>      r_read_count;      // number of copies
+      sc_signal<data_t>     *r_read_data;       // data (one cache line)
+      sc_signal<size_t>      r_read_way;        // associative way (in cache)
+      sc_signal<size_t>      r_read_trt_index;  // Transaction Table index
+
+      // Buffer between READ fsm and IXR_CMD fsm (ask a missing cache line to XRAM)   
+      sc_signal<bool>        r_read_to_ixr_cmd_req;     // valid request
+      sc_signal<addr_t>      r_read_to_ixr_cmd_nline;   // cache line index
+      sc_signal<size_t>      r_read_to_ixr_cmd_trdid;   // index in Transaction Table
+
+      // Buffer between READ fsm and TGT_RSP fsm (send a hit read response to L1 cache)
+      sc_signal<bool>	   r_read_to_tgt_rsp_req;       // valid request
+      sc_signal<size_t>	   r_read_to_tgt_rsp_srcid;	    // Transaction srcid
+      sc_signal<size_t>	   r_read_to_tgt_rsp_trdid;	    // Transaction trdid
+      sc_signal<size_t>	   r_read_to_tgt_rsp_pktid;	    // Transaction pktid
+      sc_signal<data_t>   *r_read_to_tgt_rsp_data;	    // data (one cache line)
+      sc_signal<size_t>    r_read_to_tgt_rsp_word;      // first word of the response
+      sc_signal<size_t>    r_read_to_tgt_rsp_length;    // length of the response
+
+      ///////////////////////////////////////////////////////////////
+      // Registers controlled by the WRITE fsm
+      ///////////////////////////////////////////////////////////////
+
+      sc_signal<int>       r_write_fsm;             // FSM state
+      sc_signal<addr_t>	   r_write_address;         // first word address
+      sc_signal<size_t>    r_write_word_index;      // first word index in line
+      sc_signal<size_t>    r_write_word_count;      // number of words in line
+      sc_signal<size_t>    r_write_srcid;           // transaction srcid
+      sc_signal<size_t>    r_write_trdid;           // transaction trdid
+      sc_signal<size_t>    r_write_pktid;           // transaction pktid
+      sc_signal<data_t>	  *r_write_data;            // data (one cache line)	
+      sc_signal<be_t>     *r_write_be;              // one byte enable per word
+      sc_signal<bool>      r_write_byte;            // is it a byte write
+      sc_signal<bool>      r_write_is_cnt;          // is_cnt bit (in directory)
+      sc_signal<bool>      r_write_lock;            // lock bit (in directory)
+      sc_signal<tag_t>     r_write_tag;             // cache line tag (in directory)
+      sc_signal<copy_t>    r_write_d_copies;        // bit vector of copies
+      sc_signal<copy_t>    r_write_i_copies;        // bit vector of copies
+      sc_signal<size_t>	   r_write_count;           // number of copies
+      sc_signal<size_t>	   r_write_way;		        // way of the line
+      sc_signal<size_t>    r_write_trt_index;	    // index in Transaction Table
+      sc_signal<size_t>    r_write_upt_index;	    // index in Update Table
+
+      // Buffer between WRITE fsm and TGT_RSP fsm (acknowledge a write command from L1)
+      sc_signal<bool>      r_write_to_tgt_rsp_req;		// valid request
+      sc_signal<size_t>    r_write_to_tgt_rsp_srcid;    // transaction srcid
+      sc_signal<size_t>    r_write_to_tgt_rsp_trdid;	// transaction trdid
+      sc_signal<size_t>    r_write_to_tgt_rsp_pktid;	// transaction pktid
+
+      // Buffer between WRITE fsm and IXR_CMD fsm (ask a missing cache line to XRAM) 
+      sc_signal<bool>	   r_write_to_ixr_cmd_req;      // valid request
+      sc_signal<bool>	   r_write_to_ixr_cmd_write;    // write request
+      sc_signal<addr_t>    r_write_to_ixr_cmd_nline; 	// cache line index
+      sc_signal<data_t>	  *r_write_to_ixr_cmd_data;	    // cache line data
+      sc_signal<size_t>    r_write_to_ixr_cmd_trdid;	// index in Transaction Table
+
+      // Buffer between WRITE fsm and INIT_CMD fsm (Update/Invalidate L1 caches)
+      sc_signal<bool>	   r_write_to_init_cmd_req;         // valid request
+      sc_signal<bool>	   r_write_to_init_cmd_brdcast;     // brdcast request
+      sc_signal<addr_t>	   r_write_to_init_cmd_nline;	    // cache line index
+      sc_signal<size_t>	   r_write_to_init_cmd_trdid;	    // index in Update Table
+      sc_signal<copy_t>    r_write_to_init_cmd_d_copies;    // bit_vector of L1 to update
+      sc_signal<data_t>   *r_write_to_init_cmd_data;	    // data (one cache line)
+      sc_signal<be_t>     *r_write_to_init_cmd_be;	        // word enable
+      sc_signal<size_t>	   r_write_to_init_cmd_count;	    // number of words in line
+      sc_signal<size_t>	   r_write_to_init_cmd_index;	    // index of first word in line
+
+      /////////////////////////////////////////////////////////
+      // Registers controlled by INIT_RSP fsm
+      //////////////////////////////////////////////////////////
+
+      sc_signal<int> 	   r_init_rsp_fsm;        // FSM state
+      sc_signal<size_t>	   r_init_rsp_upt_index;  // index in the Update Table
+      sc_signal<size_t>	   r_init_rsp_srcid;	  // pending write srcid      
+      sc_signal<size_t>	   r_init_rsp_trdid;	  // pending write trdid      
+      sc_signal<size_t>	   r_init_rsp_pktid;	  // pending write pktid      
+      sc_signal<addr_t>	   r_init_rsp_nline;	  // pending write nline      
+
+      // Buffer between INIT_RSP fsm and TGT_RSP fsm (complete write/update transaction)
+      sc_signal<bool>	     r_init_rsp_to_tgt_rsp_req;   	// valid request
+      sc_signal<size_t>	   r_init_rsp_to_tgt_rsp_srcid;		// Transaction srcid
+      sc_signal<size_t>	   r_init_rsp_to_tgt_rsp_trdid;		// Transaction trdid
+      sc_signal<size_t>	   r_init_rsp_to_tgt_rsp_pktid;		// Transaction pktid
+
+      ///////////////////////////////////////////////////////
+      // Registers controlled by CLEANUP fsm
+      ///////////////////////////////////////////////////////
+
+      sc_signal<int> 	     r_cleanup_fsm;         // FSM state
+      sc_signal<size_t>      r_cleanup_srcid;       // transaction srcid
+      sc_signal<size_t>      r_cleanup_trdid;       // transaction trdid
+      sc_signal<size_t>      r_cleanup_pktid;       // transaction pktid
+      sc_signal<addr_t>      r_cleanup_nline;       // cache line index
+
+      sc_signal<copy_t>      r_cleanup_d_copies;    // bit-vector of copies 
+      sc_signal<copy_t>      r_cleanup_i_copies;    // bit-vector of copies 
+      sc_signal<copy_t>      r_cleanup_count;       // number of copies 
+      sc_signal<tag_t>       r_cleanup_tag;	        // cache line tag (in directory)
+      sc_signal<bool>        r_cleanup_is_cnt;      // inst bit (in directory)
+      sc_signal<bool>        r_cleanup_lock;	    // lock bit (in directory)
+      sc_signal<bool>        r_cleanup_dirty;	    // dirty bit (in directory)
+      sc_signal<size_t>      r_cleanup_way;	        // associative way (in cache)
+
+      sc_signal<size_t>      r_cleanup_write_srcid; // srcid of write response
+      sc_signal<size_t>      r_cleanup_write_trdid; // trdid of write rsp
+      sc_signal<size_t>      r_cleanup_write_pktid; // pktid of write rsp
+      sc_signal<bool>        r_cleanup_need_rsp;    // needs a write rsp
+
+      sc_signal<size_t>      r_cleanup_index;	    // index of the INVAL line (in the UPT)
+
+      // Buffer between CLEANUP fsm and TGT_RSP fsm (acknowledge a write command from L1)
+      sc_signal<bool>      r_cleanup_to_tgt_rsp_req;    // valid request
+      sc_signal<size_t>    r_cleanup_to_tgt_rsp_srcid;  // transaction srcid
+      sc_signal<size_t>    r_cleanup_to_tgt_rsp_trdid;	// transaction trdid
+      sc_signal<size_t>    r_cleanup_to_tgt_rsp_pktid;	// transaction pktid
+
+      ///////////////////////////////////////////////////////
+      // Registers controlled by LLSC fsm
+      ///////////////////////////////////////////////////////
+
+      sc_signal<int>       r_llsc_fsm;          // FSM state
+      sc_signal<data_t>	   r_llsc_data;		    // read data word
+      sc_signal<uint32_t>  r_llsc_lfsr;         // lfsr for random introducing
+      sc_signal<copy_t>    r_llsc_i_copies;	    // bit_vector of copies
+      sc_signal<copy_t>    r_llsc_d_copies;	    // bit_vector of copies
+      sc_signal<copy_t>    r_llsc_count;	    // number of copies
+      sc_signal<bool>      r_llsc_is_cnt;	    // is_cnt bit (in directory)
+      sc_signal<bool>      r_llsc_dirty;	    // dirty bit (in directory)
+      sc_signal<size_t>    r_llsc_way;		    // way in directory
+      sc_signal<size_t>    r_llsc_set;		    // set in directory
+      sc_signal<data_t>    r_llsc_tag;		    // cache line tag (in directory)
+      sc_signal<size_t>    r_llsc_trt_index;    // Transaction Table index
+      sc_signal<size_t>    r_llsc_upt_index;    // Update Table index
+
+      // Buffer between LLSC fsm and INIT_CMD fsm (XRAM read)	
+      sc_signal<bool>	   r_llsc_to_ixr_cmd_req;   // valid request
+      sc_signal<addr_t>	   r_llsc_to_ixr_cmd_nline; // cache line index
+      sc_signal<size_t>	   r_llsc_to_ixr_cmd_trdid; // index in Transaction Table
+      sc_signal<bool>	   r_llsc_to_ixr_cmd_write; // write request
+      sc_signal<data_t>	  *r_llsc_to_ixr_cmd_data;  // cache line data
+
+
+      // Buffer between LLSC fsm and TGT_RSP fsm
+      sc_signal<bool>	   r_llsc_to_tgt_rsp_req;   // valid request
+      sc_signal<data_t>    r_llsc_to_tgt_rsp_data;  // read data word
+      sc_signal<size_t>	   r_llsc_to_tgt_rsp_srcid; // Transaction srcid
+      sc_signal<size_t>	   r_llsc_to_tgt_rsp_trdid; // Transaction trdid
+      sc_signal<size_t>	   r_llsc_to_tgt_rsp_pktid; // Transaction pktid
+
+      // Buffer between LLSC fsm and INIT_CMD fsm (Update/Invalidate L1 caches)
+      sc_signal<bool>	   r_llsc_to_init_cmd_req;          // valid request
+      sc_signal<bool>	   r_llsc_to_init_cmd_brdcast;      // brdcast request
+      sc_signal<addr_t>	   r_llsc_to_init_cmd_nline;	    // cache line index
+      sc_signal<size_t>	   r_llsc_to_init_cmd_trdid;	    // index in Update Table
+      sc_signal<copy_t>    r_llsc_to_init_cmd_d_copies;     // bit_vector of L1 to update
+      sc_signal<data_t>    r_llsc_to_init_cmd_wdata;        // data (one word)
+      sc_signal<size_t>	   r_llsc_to_init_cmd_index;	    // index of the word in line
+
+      ////////////////////////////////////////////////////
+      // Registers controlled by the IXR_RSP fsm
+      ////////////////////////////////////////////////////
+
+      sc_signal<int> 	   r_ixr_rsp_fsm;       // FSM state
+      sc_signal<size_t>	   r_ixr_rsp_trt_index;	// TRT entry index
+      sc_signal<size_t>    r_ixr_rsp_cpt;	    // word counter
+
+      // Buffer between IXR_RSP fsm and XRAM_RSP fsm  (response from the XRAM)
+      sc_signal<bool>	  *r_ixr_rsp_to_xram_rsp_rok;	// A xram response is ready
+
+      ////////////////////////////////////////////////////
+      // Registers controlled by the XRAM_RSP fsm
+      ////////////////////////////////////////////////////
+
+      sc_signal<int> 	   r_xram_rsp_fsm;		        // FSM state
+      sc_signal<size_t>	   r_xram_rsp_trt_index;	    // TRT entry index
+      TransactionTabEntry  r_xram_rsp_trt_buf;		    // TRT entry local buffer
+      sc_signal<bool>	   r_xram_rsp_victim_inval;	    // victim line invalidate 
+      sc_signal<bool>	   r_xram_rsp_victim_is_cnt;    // victim line inst bit
+      sc_signal<bool>	   r_xram_rsp_victim_dirty;	    // victim line dirty bit
+      sc_signal<size_t>    r_xram_rsp_victim_way;	    // victim line way
+      sc_signal<size_t>    r_xram_rsp_victim_set;	    // victim line set
+      sc_signal<addr_t>    r_xram_rsp_victim_nline;     // victim line index
+      sc_signal<copy_t>    r_xram_rsp_victim_d_copies;	// victim line copies
+      sc_signal<copy_t>    r_xram_rsp_victim_i_copies;	// victim line copies
+      sc_signal<copy_t>    r_xram_rsp_victim_count;	    // victim line number of copies
+      sc_signal<data_t>	  *r_xram_rsp_victim_data;	    // victim line data
+      sc_signal<size_t>	   r_xram_rsp_upt_index;	    // UPT entry index
+
+      // Buffer between XRAM_RSP fsm and TGT_RSP fsm  (response to L1 cache)
+      sc_signal<bool>	   r_xram_rsp_to_tgt_rsp_req;	// Valid request
+      sc_signal<size_t>    r_xram_rsp_to_tgt_rsp_srcid;	// Transaction srcid
+      sc_signal<size_t>    r_xram_rsp_to_tgt_rsp_trdid;	// Transaction trdid
+      sc_signal<size_t>    r_xram_rsp_to_tgt_rsp_pktid;	// Transaction pktid
+      sc_signal<data_t>   *r_xram_rsp_to_tgt_rsp_data;	// data (one cache line)
+      sc_signal<size_t>    r_xram_rsp_to_tgt_rsp_word;  // first word index
+      sc_signal<size_t>    r_xram_rsp_to_tgt_rsp_length;// length of the response
+
+      // Buffer between XRAM_RSP fsm and INIT_CMD fsm (Inval L1 Caches) 
+      sc_signal<bool>	     r_xram_rsp_to_init_cmd_req;    // Valid request
+      sc_signal<bool>      r_xram_rsp_to_init_cmd_brdcast;  // Broadcast request
+      sc_signal<addr_t>    r_xram_rsp_to_init_cmd_nline;    // cache line index;
+      sc_signal<size_t>	   r_xram_rsp_to_init_cmd_trdid;    // index of UPT entry
+      sc_signal<copy_t>    r_xram_rsp_to_init_cmd_d_copies; // bit_vector of copies
+      sc_signal<copy_t>    r_xram_rsp_to_init_cmd_i_copies; // bit_vector of copies
+
+      // Buffer between XRAM_RSP fsm and IXR_CMD fsm (XRAM write)
+      sc_signal<bool>	   r_xram_rsp_to_ixr_cmd_req;	// Valid request
+      sc_signal<addr_t>	   r_xram_rsp_to_ixr_cmd_nline;	// cache line index
+      sc_signal<data_t>	  *r_xram_rsp_to_ixr_cmd_data;	// cache line data
+      sc_signal<size_t>	   r_xram_rsp_to_ixr_cmd_trdid;	// index in transaction table
+
+      ////////////////////////////////////////////////////
+      // Registers controlled by the IXR_CMD fsm
+      ////////////////////////////////////////////////////
+
+      sc_signal<int> 	   r_ixr_cmd_fsm;
+      sc_signal<size_t>	   r_ixr_cmd_cpt;
+
+      ////////////////////////////////////////////////////
+      // Registers controlled by TGT_RSP fsm
+      ////////////////////////////////////////////////////
+
+      sc_signal<int> 	   r_tgt_rsp_fsm;
+      sc_signal<size_t>    r_tgt_rsp_cpt;
+
+      ////////////////////////////////////////////////////
+      // Registers controlled by INIT_CMD fsm
+      ////////////////////////////////////////////////////
+
+      sc_signal<int> 	  r_init_cmd_fsm;
+      sc_signal<size_t>   r_init_cmd_cpt;
+      sc_signal<size_t>	  r_init_cmd_target;
+      sc_signal<bool>     r_init_cmd_inst;
+
+      ////////////////////////////////////////////////////
+      // Registers controlled by ALLOC_DIR fsm
+      ////////////////////////////////////////////////////
+
+      sc_signal<int> 		r_alloc_dir_fsm;
+
+      ////////////////////////////////////////////////////
+      // Registers controlled by ALLOC_TRT fsm
+      ////////////////////////////////////////////////////
+
+      sc_signal<int> 		r_alloc_trt_fsm;
+
+      ////////////////////////////////////////////////////
+      // Registers controlled by ALLOC_UPT fsm
+      ////////////////////////////////////////////////////
+
+      sc_signal<int> 		r_alloc_upt_fsm;
+
+    }; // end class VciMemCacheV2
+
+}}
+
+#endif
+
+// Local Variables:
+// tab-width: 4
+// c-basic-offset: 4
+// c-file-offsets:((innamespace . 0)(inline-open . 0))
+// indent-tabs-mode: nil
+// End:
+
+// vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4
+
Index: branches/v4/modules/vci_mem_cache_v2/caba/source/include/xram_transaction_v2.h
===================================================================
--- branches/v4/modules/vci_mem_cache_v2/caba/source/include/xram_transaction_v2.h	(revision 371)
+++ branches/v4/modules/vci_mem_cache_v2/caba/source/include/xram_transaction_v2.h	(revision 371)
@@ -0,0 +1,404 @@
+#ifndef XRAM_TRANSACTION_V2_H_
+#define XRAM_TRANSACTION_V2_H_
+ 
+#include <inttypes.h>
+#include <systemc>
+#include <cassert>
+#include "arithmetics.h"
+
+#define DEBUG_XRAM_TRANSACTION 0
+
+////////////////////////////////////////////////////////////////////////
+//                  A transaction tab entry         
+////////////////////////////////////////////////////////////////////////
+
+class TransactionTabEntry {
+  typedef uint32_t size_t;
+  typedef uint32_t data_t;
+  typedef sc_dt::sc_uint<40> addr_t;
+  typedef uint32_t be_t;
+
+ public:
+  bool 		      valid;     	    // entry valid 
+  bool 		      xram_read; 	    // read request to XRAM
+  addr_t   	      nline;    	    // index (zy) of the requested line
+  size_t 	      srcid;     	    // processor requesting the transaction
+  size_t 	      trdid;     	    // processor requesting the transaction
+  size_t 	      pktid;     	    // processor requesting the transaction
+  bool 		      proc_read;	    // read request from processor
+  size_t 		  read_length;      // length of the read (for the response)
+  size_t 	      word_index;    	// index of the first read word (for the response)
+  std::vector<data_t> wdata;        // write buffer (one cache line)
+  std::vector<be_t>   wdata_be;    	// be for each data in the write buffer
+
+  /////////////////////////////////////////////////////////////////////
+  // The init() function initializes the entry 
+  /////////////////////////////////////////////////////////////////////
+  void init()
+  {
+    valid		= false;
+  }
+
+  /////////////////////////////////////////////////////////////////////
+  // The alloc() function initializes the vectors of an entry
+  // Its arguments are :
+  // - n_words : number of words per line in the cache
+  /////////////////////////////////////////////////////////////////////
+  void alloc(size_t n_words)
+  {
+    wdata_be.reserve( (int)n_words );
+    wdata.reserve( (int)n_words );
+    for(size_t i=0; i<n_words; i++){
+      wdata_be.push_back(false);
+      wdata.push_back(0);
+    }
+  }
+
+  ////////////////////////////////////////////////////////////////////
+  // The copy() function copies an existing entry
+  // Its arguments are :
+  // - source : the transaction tab entry to copy
+  ////////////////////////////////////////////////////////////////////
+  void copy(const TransactionTabEntry &source)
+  {
+    valid	    = source.valid;
+    xram_read 	= source.xram_read;
+    nline	    = source.nline;
+    srcid	    = source.srcid;
+    trdid	    = source.trdid;
+    pktid	    = source.pktid;
+    proc_read 	= source.proc_read;
+    read_length = source.read_length;
+    word_index	= source.word_index;
+    wdata_be.assign(source.wdata_be.begin(),source.wdata_be.end());
+    wdata.assign(source.wdata.begin(),source.wdata.end());	
+  }
+
+  ////////////////////////////////////////////////////////////////////
+  // The print() function prints the entry 
+  ////////////////////////////////////////////////////////////////////
+  void print(){
+    std::cout << "valid       = " << valid        << std::endl;
+    std::cout << "xram_read   = " << xram_read    << std::endl;
+    std::cout << "nline       = " << std::hex << nline << std::endl;
+    std::cout << "srcid       = " << srcid        << std::endl;
+    std::cout << "trdid       = " << trdid        << std::endl;
+    std::cout << "pktid       = " << pktid        << std::endl;
+    std::cout << "proc_read   = " << proc_read    << std::endl;
+    std::cout << "read_length = " << read_length  << std::endl;
+    std::cout << "word_index  = " << word_index   << std::endl; 
+    for(size_t i=0; i<wdata_be.size() ; i++){
+      std::cout << "wdata_be [" << i <<"] = " << wdata_be[i] << std::endl;
+    }
+    for(size_t i=0; i<wdata.size() ; i++){
+      std::cout << "wdata [" << i <<"] = " << wdata[i] << std::endl;
+    }
+    std::cout << std::endl;
+  }
+
+  /////////////////////////////////////////////////////////////////////
+  // 		Constructors
+  /////////////////////////////////////////////////////////////////////
+
+  TransactionTabEntry()
+    {
+      wdata_be.clear();
+      wdata.clear();
+      valid=false;
+    }
+
+  TransactionTabEntry(const TransactionTabEntry &source){
+    valid	    = source.valid;
+    xram_read	= source.xram_read;
+    nline	    = source.nline;
+    srcid	    = source.srcid;
+    trdid	    = source.trdid;
+    pktid	    = source.pktid;
+    proc_read	= source.proc_read;
+    read_length = source.read_length;
+    word_index	= source.word_index;
+    wdata_be.assign(source.wdata_be.begin(),source.wdata_be.end());
+    wdata.assign(source.wdata.begin(),source.wdata.end());	
+  }
+
+}; // end class TransactionTabEntry
+
+////////////////////////////////////////////////////////////////////////
+//                  The transaction tab                              
+////////////////////////////////////////////////////////////////////////
+class TransactionTab{
+  typedef uint32_t size_t;
+  typedef uint32_t data_t;
+  typedef sc_dt::sc_uint<40> addr_t;
+  typedef uint32_t be_t;
+
+ private:
+  size_t size_tab;                // The size of the tab
+
+  data_t be_to_mask(be_t be)
+  {
+    data_t ret = 0;
+    if ( be&0x1 ) {
+      ret = ret | 0x000000FF;
+    }
+    if ( be&0x2 ) {
+      ret = ret | 0x0000FF00;
+    }
+    if ( be&0x4 ) {
+      ret = ret | 0x00FF0000;
+    }
+    if ( be&0x8 ) {
+      ret = ret | 0xFF000000;
+    }
+    return ret;
+  }
+
+ public:
+  TransactionTabEntry *tab;       // The transaction tab
+
+  ////////////////////////////////////////////////////////////////////
+  //		Constructors
+  ////////////////////////////////////////////////////////////////////
+  TransactionTab()
+    {
+      size_tab=0;
+      tab=NULL;
+    }
+
+  TransactionTab(size_t n_entries, size_t n_words)
+    {
+      size_tab = n_entries;
+      tab = new TransactionTabEntry[size_tab];
+      for ( size_t i=0; i<size_tab; i++) {
+	tab[i].alloc(n_words);
+      }
+    }
+
+  ~TransactionTab()
+    {
+      delete [] tab;
+    }
+
+  /////////////////////////////////////////////////////////////////////
+  // The size() function returns the size of the tab
+  /////////////////////////////////////////////////////////////////////
+  size_t size()
+  {
+    return size_tab;
+  }
+
+  /////////////////////////////////////////////////////////////////////
+  // The init() function initializes the transaction tab entries
+  /////////////////////////////////////////////////////////////////////
+  void init()
+  {
+    for ( size_t i=0; i<size_tab; i++) {
+      tab[i].init();
+    }
+  }
+
+  /////////////////////////////////////////////////////////////////////
+  // The print() function prints a transaction tab entry
+  // Arguments :
+  // - index : the index of the entry to print
+  /////////////////////////////////////////////////////////////////////
+  void print(const size_t index)
+  {
+    assert( (index < size_tab) 
+	    && "Invalid Transaction Tab Entry");
+    tab[index].print();
+    return;
+  }
+
+  /////////////////////////////////////////////////////////////////////
+  // The read() function returns a transaction tab entry.
+  // Arguments :
+  // - index : the index of the entry to read
+  /////////////////////////////////////////////////////////////////////
+  TransactionTabEntry read(const size_t index)
+  {
+    assert( (index < size_tab) 
+	    && "Invalid Transaction Tab Entry");
+    return tab[index];
+  }
+
+  /////////////////////////////////////////////////////////////////////
+  // The full() function returns the state of the transaction tab
+  // Arguments :
+  // - index : (return argument) the index of an empty entry 
+  // The function returns true if the transaction tab is full
+  /////////////////////////////////////////////////////////////////////
+  bool full(size_t &index)
+  {
+    for(size_t i=0; i<size_tab; i++){
+      if(!tab[i].valid){
+	    index=i;
+	    return false;	
+      }
+    }
+    return true;
+  }
+
+  /////////////////////////////////////////////////////////////////////
+  // The hit_read() function checks if an XRAM read transaction exists 
+  // for a given cache line.
+  // Arguments :
+  // - index : (return argument) the index of the hit entry, if there is 
+  // - nline : the index (zy) of the requested line
+  // The function returns true if a read request has already been sent
+  //////////////////////////////////////////////////////////////////////
+  bool hit_read(const addr_t nline,size_t &index)
+  {
+    for(size_t i=0; i<size_tab; i++){
+      if((tab[i].valid && (nline==tab[i].nline)) && (tab[i].xram_read)) {
+	    index=i;
+	    return true;	
+      }
+    }
+    return false;
+  }
+
+  ///////////////////////////////////////////////////////////////////////
+  // The hit_write() function looks if an XRAM write transaction exists 
+  // for a given line.
+  // Arguments :
+  // - nline : the index (zy) of the requested line
+  // The function returns true if a write request has already been sent
+  ///////////////////////////////////////////////////////////////////////
+  bool hit_write(const addr_t nline)
+  {
+    for(size_t i=0; i<size_tab; i++){
+      if(tab[i].valid && (nline==tab[i].nline) && !(tab[i].xram_read)) {
+	    return true;	
+      }
+    }
+    return false;
+  }
+
+  /////////////////////////////////////////////////////////////////////
+  // The write_data_mask() function writes a vector of data (a line).
+  // The data is written only if the corresponding bits are set
+  // in the be vector. 
+  // Arguments :
+  // - index : the index of the request in the transaction tab
+  // - be   : vector of be 
+  // - data : vector of data
+  /////////////////////////////////////////////////////////////////////
+  void write_data_mask(const size_t index, 
+		       const std::vector<be_t> &be, 
+		       const std::vector<data_t> &data) 
+  {
+    assert( (index < size_tab) 
+	    && "Invalid Transaction Tab Entry");
+    assert(be.size()==tab[index].wdata_be.size() 
+	   && "Bad data mask in write_data_mask in TransactionTab");
+    assert(data.size()==tab[index].wdata.size() 
+	   && "Bad data in write_data_mask in TransactionTab");
+
+    for(size_t i=0; i<tab[index].wdata_be.size() ; i++) {
+      tab[index].wdata_be[i] = tab[index].wdata_be[i] | be[i];
+      data_t mask = be_to_mask(be[i]);
+      tab[index].wdata[i] = (tab[index].wdata[i] & ~mask) | (data[i] & mask);
+    }
+  }
+
+  /////////////////////////////////////////////////////////////////////
+  // The set() function registers a transaction (read or write)
+  // to the XRAM in the transaction tab.
+  // Arguments :
+  // - index : index in the transaction tab
+  // - xram_read : transaction type (read or write a cache line)
+  // - nline : the index (zy) of the cache line
+  // - srcid : srcid of the initiator that caused the transaction
+  // - trdid : trdid of the initiator that caused the transaction
+  // - pktid : pktid of the initiator that caused the transaction
+  // - proc_read : does the initiator want a copy
+  // - read_length : length of read (in case of processor read)
+  // - word_index : index in the line (in case of single word read)
+  // - data : the data to write (in case of write)
+  // - data_be : the mask of the data to write (in case of write)
+  /////////////////////////////////////////////////////////////////////
+  void set(const size_t index,
+	   const bool xram_read,
+	   const addr_t nline,
+	   const size_t srcid,
+	   const size_t trdid,
+	   const size_t pktid,
+	   const bool proc_read,
+	   const size_t read_length,
+	   const size_t word_index,
+	   const std::vector<be_t> &data_be,
+	   const std::vector<data_t> &data) 
+  {
+    assert( (index < size_tab) 
+	    && "The selected entry is out of range in set() Transaction Tab");
+    assert(data_be.size()==tab[index].wdata_be.size() 
+	   && "Bad data_be argument in set() TransactionTab");
+    assert(data.size()==tab[index].wdata.size() 
+	   && "Bad data argument in set() TransactionTab");
+
+    tab[index].valid	        = true;
+    tab[index].xram_read        = xram_read;
+    tab[index].nline	        = nline;
+    tab[index].srcid	        = srcid;
+    tab[index].trdid	        = trdid;
+    tab[index].pktid	        = pktid;
+    tab[index].proc_read	    = proc_read;
+    tab[index].read_length	    = read_length;
+    tab[index].word_index	    = word_index;
+    for(size_t i=0; i<tab[index].wdata.size(); i++) {
+      tab[index].wdata_be[i]    = data_be[i];
+      tab[index].wdata[i]       = data[i];
+    }
+  }
+
+  /////////////////////////////////////////////////////////////////////
+  // The write_rsp() function writes a word of the response to an 
+  // XRAM read transaction.
+  // The data is only written when the corresponding BE field is Ox0.
+  // Arguments :
+  // - index : the index of the transaction in the transaction tab
+  // - word_index : the index of the data in the line
+  // - data : the data to write
+  /////////////////////////////////////////////////////////////////////
+  void write_rsp(const size_t index,
+		 const size_t word,
+		 const data_t data)
+  {
+    assert( (index < size_tab) 
+	    && "Selected entry  out of range in write_rsp() Transaction Tab");
+    assert( (word <= tab[index].wdata_be.size()) 
+	    && "Bad word_index in write_rsp() in TransactionTab");
+    assert( tab[index].valid 
+	    && "Transaction Tab Entry invalid in write_rsp()");
+    assert( tab[index].xram_read 
+	    && "Selected entry is not an XRAM read transaction in write_rsp()");
+
+    data_t mask = be_to_mask(tab[index].wdata_be[word]);
+    tab[index].wdata[word] = (tab[index].wdata[word] & mask) | (data & ~mask);
+  }
+
+  /////////////////////////////////////////////////////////////////////
+  // The erase() function erases an entry in the transaction tab.
+  // Arguments :
+  // - index : the index of the request in the transaction tab
+  /////////////////////////////////////////////////////////////////////
+  void erase(const size_t index)
+  {
+    assert( (index < size_tab) 
+	    && "The selected entry is out of range in erase() Transaction Tab");
+    tab[index].valid	= false;
+  }
+}; // end class TransactionTab
+
+#endif
+
+// Local Variables:
+// tab-width: 4
+// c-basic-offset: 4
+// c-file-offsets:((innamespace . 0)(inline-open . 0))
+// indent-tabs-mode: nil
+// End:
+
+// vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4
+
Index: branches/v4/modules/vci_mem_cache_v2/caba/source/src/vci_mem_cache_v2.cpp
===================================================================
--- branches/v4/modules/vci_mem_cache_v2/caba/source/src/vci_mem_cache_v2.cpp	(revision 371)
+++ branches/v4/modules/vci_mem_cache_v2/caba/source/src/vci_mem_cache_v2.cpp	(revision 371)
@@ -0,0 +1,3917 @@
+/* -*- c++ -*-
+ * File 	: vci_mem_cache_v2.cpp
+ * Date 	: 30/10/2008
+ * Copyright 	: UPMC / LIP6
+ * Authors 	: Alain Greiner / Eric Guthmuller
+ *
+ * SOCLIB_LGPL_HEADER_BEGIN
+ *
+ * This file is part of SoCLib, GNU LGPLv2.1.
+ *
+ * SoCLib is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU Lesser General Public License as published
+ * by the Free Software Foundation; version 2.1 of the License.
+ *
+ * SoCLib is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with SoCLib; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301 USA
+ *
+ * SOCLIB_LGPL_HEADER_END
+ *
+ * Maintainers: alain eric.guthmuller@polytechnique.edu
+ */
+#include "../include/vci_mem_cache_v2.h"
+
+//#define TDEBUG // Transaction tab debug
+//#define IDEBUG // Update tab debug
+//#define DDEBUG // Directory debug
+//#define DEBUG_VCI_MEM_CACHE 1
+#define RANDOMIZE_SC
+#define DEBUG_START_CYCLE 33069000
+
+namespace soclib { namespace caba {
+
+#ifdef DEBUG_VCI_MEM_CACHE 
+  const char *tgt_cmd_fsm_str[] = {
+    "TGT_CMD_IDLE",
+    "TGT_CMD_READ",
+    "TGT_CMD_READ_EOP",
+    "TGT_CMD_WRITE",
+    "TGT_CMD_ATOMIC",
+  };
+  const char *tgt_rsp_fsm_str[] = {
+    "TGT_RSP_READ_IDLE",
+    "TGT_RSP_WRITE_IDLE",
+    "TGT_RSP_LLSC_IDLE",
+    "TGT_RSP_XRAM_IDLE",
+    "TGT_RSP_INIT_IDLE",
+    "TGT_RSP_CLEANUP_IDLE",
+    "TGT_RSP_READ",
+    "TGT_RSP_WRITE",
+    "TGT_RSP_LLSC",
+    "TGT_RSP_XRAM",
+    "TGT_RSP_INIT",
+    "TGT_RSP_CLEANUP",
+  };
+  const char *init_cmd_fsm_str[] = {
+    "INIT_CMD_INVAL_IDLE",
+    "INIT_CMD_INVAL_SEL",
+    "INIT_CMD_INVAL_NLINE",
+    "INIT_CMD_UPDT_IDLE",
+    "INIT_CMD_UPDT_SEL",
+    "INIT_CMD_BRDCAST",
+    "INIT_CMD_UPDT_NLINE",
+    "INIT_CMD_UPDT_INDEX",
+    "INIT_CMD_UPDT_DATA",
+    "INIT_CMD_SC_UPDT_IDLE",
+    "INIT_CMD_SC_UPDT_SEL",
+    "INIT_CMD_SC_BRDCAST",
+    "INIT_CMD_SC_UPDT_NLINE",
+    "INIT_CMD_SC_UPDT_INDEX",
+    "INIT_CMD_SC_UPDT_DATA",
+  };
+  const char *init_rsp_fsm_str[] = {
+    "INIT_RSP_IDLE",
+    "INIT_RSP_UPT_LOCK",
+    "INIT_RSP_UPT_CLEAR",
+    "INIT_RSP_END",
+  };
+  const char *read_fsm_str[] = {
+    "READ_IDLE",
+    "READ_DIR_LOCK",
+    "READ_DIR_HIT",
+    "READ_RSP",
+    "READ_TRT_LOCK",
+    "READ_TRT_SET",
+    "READ_XRAM_REQ",
+  };
+  const char *write_fsm_str[] = {
+    "WRITE_IDLE",
+    "WRITE_NEXT",
+    "WRITE_DIR_LOCK",
+    "WRITE_DIR_HIT_READ",
+    "WRITE_DIR_HIT",
+    "WRITE_DIR_HIT_RSP",
+    "WRITE_UPT_LOCK",
+    "WRITE_WAIT_UPT",
+    "WRITE_UPDATE",
+    "WRITE_RSP",
+    "WRITE_TRT_LOCK",
+    "WRITE_TRT_DATA",
+    "WRITE_TRT_SET",
+    "WRITE_WAIT_TRT",
+    "WRITE_XRAM_REQ",
+    "WRITE_TRT_WRITE_LOCK",
+    "WRITE_INVAL_LOCK",
+    "WRITE_DIR_INVAL",
+    "WRITE_INVAL",
+    "WRITE_XRAM_SEND",
+  };
+  const char *ixr_rsp_fsm_str[] = {
+    "IXR_RSP_IDLE",
+    "IXR_RSP_ACK",
+    "IXR_RSP_TRT_ERASE",
+    "IXR_RSP_TRT_READ",
+  };
+  const char *xram_rsp_fsm_str[] = {
+    "XRAM_RSP_IDLE",
+    "XRAM_RSP_TRT_COPY",
+    "XRAM_RSP_TRT_DIRTY",
+    "XRAM_RSP_DIR_LOCK",
+    "XRAM_RSP_DIR_UPDT",
+    "XRAM_RSP_DIR_RSP",
+    "XRAM_RSP_INVAL_LOCK",
+    "XRAM_RSP_INVAL_WAIT",
+    "XRAM_RSP_INVAL",
+    "XRAM_RSP_WRITE_DIRTY",
+  };
+  const char *ixr_cmd_fsm_str[] = {
+    "IXR_CMD_READ_IDLE",
+    "IXR_CMD_WRITE_IDLE",
+    "IXR_CMD_LLSC_IDLE",
+    "IXR_CMD_XRAM_IDLE",
+    "IXR_CMD_READ_NLINE",
+    "IXR_CMD_WRITE_NLINE",
+    "IXR_CMD_LLSC_NLINE",
+    "IXR_CMD_XRAM_DATA",
+  };
+  const char *llsc_fsm_str[] = {
+    "LLSC_IDLE",
+    "LL_DIR_LOCK",
+    "LL_DIR_HIT",
+    "LL_RSP",
+    "SC_DIR_LOCK",
+    "SC_DIR_HIT",
+    "SC_UPT_LOCK",
+    "SC_WAIT_UPT",
+    "SC_UPDATE",
+    "SC_TRT_LOCK",
+    "SC_INVAL_LOCK",
+    "SC_DIR_INVAL",
+    "SC_INVAL",
+    "SC_XRAM_SEND",
+    "SC_RSP_FALSE",
+    "SC_RSP_TRUE",
+    "LLSC_TRT_LOCK",
+    "LLSC_TRT_SET",
+    "LLSC_XRAM_REQ",
+  };
+  const char *cleanup_fsm_str[] = {
+    "CLEANUP_IDLE",
+    "CLEANUP_DIR_LOCK",
+    "CLEANUP_DIR_WRITE",
+    "CLEANUP_UPT_LOCK",
+    "CLEANUP_UPT_WRITE",
+    "CLEANUP_WRITE_RSP",
+    "CLEANUP_RSP",
+  };
+  const char *alloc_dir_fsm_str[] = {
+    "ALLOC_DIR_READ",
+    "ALLOC_DIR_WRITE",
+    "ALLOC_DIR_LLSC",
+    "ALLOC_DIR_CLEANUP",
+    "ALLOC_DIR_XRAM_RSP",
+  };
+  const char *alloc_trt_fsm_str[] = {
+    "ALLOC_TRT_READ",
+    "ALLOC_TRT_WRITE",
+    "ALLOC_TRT_LLSC",
+    "ALLOC_TRT_XRAM_RSP",
+    "ALLOC_TRT_IXR_RSP",
+  };
+  const char *alloc_upt_fsm_str[] = {
+    "ALLOC_UPT_WRITE",
+    "ALLOC_UPT_XRAM_RSP",
+    "ALLOC_UPT_INIT_RSP",
+    "ALLOC_UPT_CLEANUP",
+  };
+#endif
+
+#define tmpl(x) template<typename vci_param> x VciMemCacheV2<vci_param>
+
+  using soclib::common::uint32_log2;
+
+  ////////////////////////////////
+  // 	Constructor 
+  ////////////////////////////////
+
+  tmpl(/**/)::VciMemCacheV2( 
+      sc_module_name name,
+      const soclib::common::MappingTable &mtp,
+      const soclib::common::MappingTable &mtc,
+      const soclib::common::MappingTable &mtx,
+      const soclib::common::IntTab &vci_ixr_index,
+      const soclib::common::IntTab &vci_ini_index,
+      const soclib::common::IntTab &vci_tgt_index,
+      const soclib::common::IntTab &vci_tgt_index_cleanup,
+      size_t nways,
+      size_t nsets,
+      size_t nwords)
+
+    : soclib::caba::BaseModule(name),
+
+    p_clk("clk"),
+    p_resetn("resetn"),
+    p_vci_tgt("vci_tgt"),
+    p_vci_tgt_cleanup("vci_tgt_cleanup"),
+    p_vci_ini("vci_ini"),
+    p_vci_ixr("vci_ixr"),
+
+    m_initiators( 32 ),
+    m_ways( nways ),
+    m_sets( nsets ),
+    m_words( nwords ),
+    m_srcid_ixr( mtx.indexForId(vci_ixr_index) ),
+    m_srcid_ini( mtc.indexForId(vci_ini_index) ),
+    m_seglist(mtp.getSegmentList(vci_tgt_index)),
+    m_cseglist(mtc.getSegmentList(vci_tgt_index_cleanup)),
+    m_coherence_table( mtc.getCoherenceTable<vci_addr_t>() ),
+    m_atomic_tab( m_initiators ),
+    m_transaction_tab( TRANSACTION_TAB_LINES, nwords ),
+    m_update_tab( UPDATE_TAB_LINES ),
+    m_cache_directory( nways, nsets, nwords, vci_param::N ),
+#define L2 soclib::common::uint32_log2
+    m_x( L2(m_words), 2),
+    m_y( L2(m_sets), L2(m_words) + 2),
+    m_z( vci_param::N - L2(m_sets) - L2(m_words) - 2, L2(m_sets) + L2(m_words) + 2),
+    m_nline( vci_param::N - L2(m_words) - 2, L2(m_words) + 2),
+#undef L2
+
+    //  FIFOs 
+    m_cmd_read_addr_fifo("m_cmd_read_addr_fifo", 4),
+    m_cmd_read_length_fifo("m_cmd_read_length_fifo", 4),
+    m_cmd_read_srcid_fifo("m_cmd_read_srcid_fifo", 4),
+    m_cmd_read_trdid_fifo("m_cmd_read_trdid_fifo", 4),
+    m_cmd_read_pktid_fifo("m_cmd_read_pktid_fifo", 4),
+
+    m_cmd_write_addr_fifo("m_cmd_write_addr_fifo",8),
+    m_cmd_write_eop_fifo("m_cmd_write_eop_fifo",8),
+    m_cmd_write_srcid_fifo("m_cmd_write_srcid_fifo",8),
+    m_cmd_write_trdid_fifo("m_cmd_write_trdid_fifo",8),
+    m_cmd_write_pktid_fifo("m_cmd_write_pktid_fifo",8),
+    m_cmd_write_data_fifo("m_cmd_write_data_fifo",8),
+    m_cmd_write_be_fifo("m_cmd_write_be_fifo",8),
+
+    m_cmd_llsc_addr_fifo("m_cmd_llsc_addr_fifo",4),
+    m_cmd_llsc_sc_fifo("m_cmd_llsc_sc_fifo",4),
+    m_cmd_llsc_srcid_fifo("m_cmd_llsc_srcid_fifo",4),
+    m_cmd_llsc_trdid_fifo("m_cmd_llsc_trdid_fifo",4),
+    m_cmd_llsc_pktid_fifo("m_cmd_llsc_pktid_fifo",4),
+    m_cmd_llsc_wdata_fifo("m_cmd_llsc_wdata_fifo",4),
+
+    r_tgt_cmd_fsm("r_tgt_cmd_fsm"),
+    
+    nseg(0),	
+    ncseg(0),	
+
+    r_read_fsm("r_read_fsm"),
+    r_write_fsm("r_write_fsm"),
+    r_init_rsp_fsm("r_init_rsp_fsm"),
+    r_cleanup_fsm("r_cleanup_fsm"),
+    r_llsc_fsm("r_llsc_fsm"),
+    r_ixr_rsp_fsm("r_ixr_rsp_fsm"),
+    r_xram_rsp_fsm("r_xram_rsp_fsm"),
+    r_ixr_cmd_fsm("r_ixr_cmd_fsm"),
+    r_tgt_rsp_fsm("r_tgt_rsp_fsm"),
+    r_init_cmd_fsm("r_init_cmd_fsm"),
+    r_alloc_dir_fsm("r_alloc_dir_fsm"),
+    r_alloc_trt_fsm("r_alloc_trt_fsm"),
+    r_alloc_upt_fsm("r_alloc_upt_fsm")
+    {
+      assert(IS_POW_OF_2(nsets));
+      assert(IS_POW_OF_2(nwords));
+      assert(IS_POW_OF_2(nways));
+      assert(nsets);
+      assert(nwords);
+      assert(nways);
+      assert(nsets <= 4096);
+      assert(nwords <= 32);
+      assert(nways <= 32);
+
+
+      // Set the broadcast address with Xmin,Xmax,Ymin,Ymax set to maximum
+      broadcast_addr = 0x3 | (0x7C1F << (vci_param::N-20));
+
+      // Get the segments associated to the MemCache 
+      std::list<soclib::common::Segment>::iterator seg;
+
+      for(seg = m_seglist.begin(); seg != m_seglist.end() ; seg++) {
+        nseg++;
+      }
+      for(seg = m_cseglist.begin(); seg != m_cseglist.end() ; seg++) {
+        ncseg++;
+      }
+
+      m_seg = new soclib::common::Segment*[nseg];
+      size_t i = 0;
+      for ( seg = m_seglist.begin() ; seg != m_seglist.end() ; seg++ ) { 
+        m_seg[i] = &(*seg);
+        i++;
+      }
+      m_cseg = new soclib::common::Segment*[ncseg];
+      i = 0;
+      for ( seg = m_cseglist.begin() ; seg != m_cseglist.end() ; seg++ ) { 
+          m_cseg[i] = &(*seg);
+          i++;
+      }
+
+      // Memory cache allocation & initialisation
+      m_cache_data = new data_t**[nways];
+      for ( size_t i=0 ; i<nways ; ++i ) {
+        m_cache_data[i] = new data_t*[nsets];
+      }
+      for ( size_t i=0; i<nways; ++i ) {
+        for ( size_t j=0; j<nsets; ++j ) {
+          m_cache_data[i][j] = new data_t[nwords];
+          for ( size_t k=0; k<nwords; k++){
+            m_cache_data[i][j][k]=0;
+          }	
+        }
+      }
+
+      // Allocation for IXR_RSP FSM
+      r_ixr_rsp_to_xram_rsp_rok	    = new sc_signal<bool>[TRANSACTION_TAB_LINES];
+
+      // Allocation for XRAM_RSP FSM
+      r_xram_rsp_victim_data        = new sc_signal<data_t>[nwords];
+      r_xram_rsp_to_tgt_rsp_data    = new sc_signal<data_t>[nwords];
+      r_xram_rsp_to_ixr_cmd_data    = new sc_signal<data_t>[nwords];
+
+      // Allocation for READ FSM
+      r_read_data 			        = new sc_signal<data_t>[nwords];
+      r_read_to_tgt_rsp_data 		= new sc_signal<data_t>[nwords];
+
+      // Allocation for WRITE FSM
+      r_write_data 			        = new sc_signal<data_t>[nwords];
+      r_write_be 			        = new sc_signal<be_t>[nwords];
+      r_write_to_init_cmd_data 		= new sc_signal<data_t>[nwords];
+      r_write_to_init_cmd_be		= new sc_signal<be_t>[nwords];
+      r_write_to_ixr_cmd_data	    = new sc_signal<data_t>[nwords];
+
+      // Allocation for LLSC FSM
+      r_llsc_to_ixr_cmd_data	    = new sc_signal<data_t>[nwords];
+
+
+      // Simulation
+
+      SC_METHOD(transition);
+      dont_initialize();
+      sensitive << p_clk.pos();
+
+      SC_METHOD(genMoore);
+      dont_initialize();
+      sensitive << p_clk.neg();
+
+    } // end constructor
+
+  /////////////////////////////////////////
+  // This function prints the statistics 
+  /////////////////////////////////////////
+
+  tmpl(void)::print_stats()
+  {
+    std::cout << "----------------------------------" << std::dec << std::endl;
+    std::cout << "MEM_CACHE " << m_srcid_ini << " / Time = " << m_cpt_cycles << std::endl
+      << "- READ RATE            = " << (double)m_cpt_read/m_cpt_cycles << std::endl
+      << "- READ MISS RATE       = " << (double)m_cpt_read_miss/m_cpt_read << std::endl
+      << "- WRITE RATE           = " << (double)m_cpt_write/m_cpt_cycles << std::endl
+      << "- WRITE MISS RATE      = " << (double)m_cpt_write_miss/m_cpt_write << std::endl
+      << "- WRITE BURST LENGTH   = " << (double)m_cpt_write_cells/m_cpt_write << std::endl
+      << "- UPDATE RATE          = " << (double)m_cpt_update/m_cpt_cycles << std::endl
+      << "- UPDATE ARITY         = " << (double)m_cpt_update_mult/m_cpt_update << std::endl
+      << "- INVAL MULTICAST RATE = " << (double)(m_cpt_inval-m_cpt_inval_brdcast)/m_cpt_cycles << std::endl
+      << "- INVAL MULTICAST ARITY= " << (double)m_cpt_inval_mult/(m_cpt_inval-m_cpt_inval_brdcast) << std::endl
+      << "- INVAL BROADCAST RATE = " << (double)m_cpt_inval_brdcast/m_cpt_cycles << std::endl
+      << "- SAVE DIRTY RATE      = " << (double)m_cpt_write_dirty/m_cpt_cycles << std::endl
+      << "- CLEANUP RATE         = " << (double)m_cpt_cleanup/m_cpt_cycles << std::endl
+      << "- LL RATE              = " << (double)m_cpt_ll/m_cpt_cycles << std::endl
+      << "- SC RATE              = " << (double)m_cpt_sc/m_cpt_cycles << std::endl;
+  }
+
+  /////////////////////////////////
+  tmpl(/**/)::~VciMemCacheV2()
+    /////////////////////////////////
+  {
+    for(size_t i=0; i<m_ways ; i++){
+      for(size_t j=0; j<m_sets ; j++){
+        delete [] m_cache_data[i][j];
+      }
+    }
+    for(size_t i=0; i<m_ways ; i++){
+      delete [] m_cache_data[i];
+    }
+    delete [] m_cache_data;
+    delete [] m_coherence_table;
+
+    delete [] r_ixr_rsp_to_xram_rsp_rok;
+
+    delete [] r_xram_rsp_victim_data;
+    delete [] r_xram_rsp_to_tgt_rsp_data;
+    delete [] r_xram_rsp_to_ixr_cmd_data;
+
+    delete [] r_read_data;
+    delete [] r_read_to_tgt_rsp_data;
+
+    delete [] r_write_data;
+    delete [] r_write_be;
+    delete [] r_write_to_init_cmd_data;
+  }
+
+  //////////////////////////////////
+  tmpl(void)::transition()
+    //////////////////////////////////
+  {
+    using soclib::common::uint32_log2;
+    //  RESET          
+    if ( ! p_resetn.read() ) {
+
+      //     Initializing FSMs
+      r_tgt_cmd_fsm 	= TGT_CMD_IDLE;
+      r_tgt_rsp_fsm 	= TGT_RSP_READ_IDLE;
+      r_init_cmd_fsm 	= INIT_CMD_INVAL_IDLE;
+      r_init_rsp_fsm 	= INIT_RSP_IDLE;
+      r_read_fsm 	= READ_IDLE;
+      r_write_fsm 	= WRITE_IDLE;
+      r_llsc_fsm 	= LLSC_IDLE;
+      r_cleanup_fsm 	= CLEANUP_IDLE;
+      r_alloc_dir_fsm   = ALLOC_DIR_READ;
+      r_alloc_trt_fsm   = ALLOC_TRT_READ;
+      r_alloc_upt_fsm   = ALLOC_UPT_WRITE;
+      r_ixr_rsp_fsm 	= IXR_RSP_IDLE;
+      r_xram_rsp_fsm 	= XRAM_RSP_IDLE;
+      r_ixr_cmd_fsm 	= IXR_CMD_READ_IDLE;
+
+      //  Initializing Tables
+      m_cache_directory.init();
+      m_atomic_tab.init();	
+      m_transaction_tab.init();
+
+      // initializing FIFOs and communication Buffers
+
+      m_cmd_read_addr_fifo.init();
+      m_cmd_read_length_fifo.init();
+      m_cmd_read_srcid_fifo.init();
+      m_cmd_read_trdid_fifo.init();
+      m_cmd_read_pktid_fifo.init();
+
+      m_cmd_write_addr_fifo.init();
+      m_cmd_write_eop_fifo.init();
+      m_cmd_write_srcid_fifo.init();
+      m_cmd_write_trdid_fifo.init();
+      m_cmd_write_pktid_fifo.init();
+      m_cmd_write_data_fifo.init();
+
+      m_cmd_llsc_addr_fifo.init();
+      m_cmd_llsc_srcid_fifo.init();
+      m_cmd_llsc_trdid_fifo.init();
+      m_cmd_llsc_pktid_fifo.init();
+      m_cmd_llsc_wdata_fifo.init();
+      m_cmd_llsc_sc_fifo.init();
+
+      r_read_to_tgt_rsp_req	    = false;
+      r_read_to_ixr_cmd_req	    = false;
+
+      r_write_to_tgt_rsp_req	= false;
+      r_write_to_ixr_cmd_req	= false;
+      r_write_to_init_cmd_req	= false;
+
+      r_cleanup_to_tgt_rsp_req	= false;
+
+      r_init_rsp_to_tgt_rsp_req	= false;
+
+      r_llsc_lfsr                       = -1;
+      r_llsc_to_tgt_rsp_req	    = false;
+      r_llsc_to_ixr_cmd_req	    = false;
+      r_llsc_to_init_cmd_req	= false;
+
+      for(size_t i=0; i<TRANSACTION_TAB_LINES ; i++){
+        r_ixr_rsp_to_xram_rsp_rok[i] = false;
+      }
+
+      r_xram_rsp_to_tgt_rsp_req	    = false;
+      r_xram_rsp_to_init_cmd_req    = false;
+      r_xram_rsp_to_ixr_cmd_req	    = false;
+      r_xram_rsp_trt_index	        = 0;
+
+      r_ixr_cmd_cpt         = 0;
+
+      r_copies_limit        = 3;
+
+      // Activity counters
+      m_cpt_cycles		    = 0;
+      m_cpt_read		    = 0;
+      m_cpt_read_miss	    = 0;
+      m_cpt_write		    = 0;
+      m_cpt_write_miss	    = 0;
+      m_cpt_write_cells	    = 0;
+      m_cpt_write_dirty	    = 0;
+      m_cpt_update		    = 0;
+      m_cpt_update_mult     = 0;
+      m_cpt_inval_brdcast 	= 0;
+      m_cpt_inval 		    = 0;
+      m_cpt_inval_mult 		= 0;
+      m_cpt_cleanup		    = 0;
+      m_cpt_ll     		    = 0;
+      m_cpt_sc     		    = 0;
+
+      return;
+    }
+
+    bool    cmd_read_fifo_put = false;
+    bool    cmd_read_fifo_get = false;
+
+    bool    cmd_write_fifo_put = false;
+    bool    cmd_write_fifo_get = false;
+
+    bool    cmd_llsc_fifo_put = false;
+    bool    cmd_llsc_fifo_get = false;
+
+#if DEBUG_VCI_MEM_CACHE 
+if(m_cpt_cycles > DEBUG_START_CYCLE){
+    std::cout << "---------------------------------------------" << std::dec << std::endl;
+    std::cout << "MEM_CACHE " << m_srcid_ini << " ; Time = " << m_cpt_cycles << std::endl
+      << " - TGT_CMD FSM   = " << tgt_cmd_fsm_str[r_tgt_cmd_fsm] << std::endl
+      << " - TGT_RSP FSM   = " << tgt_rsp_fsm_str[r_tgt_rsp_fsm] << std::endl
+      << " - INIT_CMD FSM  = " << init_cmd_fsm_str[r_init_cmd_fsm] << std::endl
+      << " - INIT_RSP FSM  = " << init_rsp_fsm_str[r_init_rsp_fsm] << std::endl
+      << " - READ FSM      = " << read_fsm_str[r_read_fsm] << std::endl
+      << " - WRITE FSM     = " << write_fsm_str[r_write_fsm] << std::endl
+      << " - LLSC FSM      = " << llsc_fsm_str[r_llsc_fsm] << std::endl
+      << " - CLEANUP FSM   = " << cleanup_fsm_str[r_cleanup_fsm] << std::endl
+      << " - IXR_CMD FSM  = " << ixr_cmd_fsm_str[r_ixr_cmd_fsm] << std::endl
+      << " - IXR_RSP FSM   = " << ixr_rsp_fsm_str[r_ixr_rsp_fsm] << std::endl
+      << " - XRAM_RSP FSM  = " << xram_rsp_fsm_str[r_xram_rsp_fsm] << std::endl
+      << " - ALLOC_DIR FSM = " << alloc_dir_fsm_str[r_alloc_dir_fsm] << std::endl
+      << " - ALLOC_TRT FSM = " << alloc_trt_fsm_str[r_alloc_trt_fsm] << std::endl
+      << " - ALLOC_UPT FSM = " << alloc_upt_fsm_str[r_alloc_upt_fsm] << std::endl;
+}
+#endif
+
+
+    ////////////////////////////////////////////////////////////////////////////////////
+    //		TGT_CMD FSM
+    ////////////////////////////////////////////////////////////////////////////////////
+    // The TGT_CMD_FSM controls the incoming VCI command pakets from the processors
+    //
+    // There is 4 types of packets for the m_mem_segment :
+    // - READ    : a READ request has a length of 1 VCI cell. It can be a single word 
+    //             or an entire cache line, depending on the PLEN value.
+    // - WRITE   : a WRITE request has a maximum length of 16 cells, and can only
+    //             concern words in a same line.
+    // - LL      : The LL request has a length of 1 cell.
+    // - SC      : The SC request has a length of 1 cell. 
+    //             The WDATA field contains the data to write.
+    //
+    ////////////////////////////////////////////////////////////////////////////////////
+
+    switch ( r_tgt_cmd_fsm.read() ) {
+
+      //////////////////
+      case TGT_CMD_IDLE:
+        {
+          if ( p_vci_tgt.cmdval ) {
+            assert( (p_vci_tgt.srcid.read() < m_initiators)
+                && "VCI_MEM_CACHE error in VCI_MEM_CACHE : The received SRCID is larger than 31");
+
+            bool reached = false;
+            for ( size_t index = 0 ; index < nseg && !reached ; index++) 
+            {
+//              if ( m_seg[index]->contains((addr_t)(p_vci_tgt.address.read())) ) {
+              if ( m_seg[index]->contains(p_vci_tgt.address.read()) ) {
+                reached = true;
+                r_index = index;
+              }
+            }
+
+
+            if ( !reached ) 
+            { 
+              std::cout << "VCI_MEM_CACHE Out of segment access in VCI_MEM_CACHE" << std::endl;
+              std::cout << "Faulty address = " << std::hex << (addr_t)(p_vci_tgt.address.read()) << std::endl;
+              std::cout << "Faulty initiator = " << std::dec << p_vci_tgt.srcid.read() << std::endl;
+              exit(0);
+            } 
+            else if ( p_vci_tgt.cmd.read() == vci_param::CMD_READ ) 
+            {
+              r_tgt_cmd_fsm = TGT_CMD_READ;
+            } 
+            else if (( p_vci_tgt.cmd.read() == vci_param::CMD_WRITE ))
+            {  
+              r_tgt_cmd_fsm = TGT_CMD_WRITE;
+            } 
+            else if ((p_vci_tgt.cmd.read() == vci_param::CMD_LOCKED_READ) || 
+                (p_vci_tgt.cmd.read() == vci_param::CMD_STORE_COND) ) 
+            {
+              r_tgt_cmd_fsm = TGT_CMD_ATOMIC;
+            } 
+          }
+          break;
+        }
+        //////////////////
+      case TGT_CMD_READ:
+
+        {
+          assert(((m_x[(vci_addr_t)p_vci_tgt.address.read()]+(p_vci_tgt.plen.read()>>2))<=16)
+              && "VCI_MEM_CACHE All read request to the MemCache must stay within a cache line"); 
+
+          if ( p_vci_tgt.cmdval && m_cmd_read_addr_fifo.wok() ) {
+            cmd_read_fifo_put = true;
+            if ( p_vci_tgt.eop )  r_tgt_cmd_fsm = TGT_CMD_IDLE;
+            else                  r_tgt_cmd_fsm = TGT_CMD_READ_EOP;		
+          } 
+          break;
+        }
+        //////////////////////
+      case TGT_CMD_READ_EOP:
+        {
+          if ( p_vci_tgt.cmdval && p_vci_tgt.eop ){
+            r_tgt_cmd_fsm = TGT_CMD_IDLE;
+          }
+          break;
+        }
+        ///////////////////
+      case TGT_CMD_WRITE:
+        {
+
+          if ( p_vci_tgt.cmdval && m_cmd_write_addr_fifo.wok() ) {
+            cmd_write_fifo_put = true;
+            if(  p_vci_tgt.eop )  r_tgt_cmd_fsm = TGT_CMD_IDLE;
+
+          }
+          break;
+        }
+        ////////////////////
+      case TGT_CMD_ATOMIC:
+        {
+          assert(p_vci_tgt.eop && "Memory Cache Error: LL or SC command with length > 1 ");
+
+          if ( p_vci_tgt.cmdval && m_cmd_llsc_addr_fifo.wok() ) {
+            cmd_llsc_fifo_put = true;
+            r_tgt_cmd_fsm = TGT_CMD_IDLE;
+          }
+          break;
+        }
+    } // end switch tgt_cmd_fsm
+
+    /////////////////////////////////////////////////////////////////////////
+    //		INIT_RSP FSM
+    /////////////////////////////////////////////////////////////////////////
+    // This FSM controls the response to the update or invalidate requests
+    // sent by the memory cache to the L1 caches :
+    //
+    // - update request initiated by the WRITE FSM.  
+    //   The FSM decrements the proper entry in the Update/Inval Table.
+    //   It sends a request to the TGT_RSP FSM to complete the pending 
+    //   write transaction (acknowledge response to the writer processor), 
+    //   and clear the UPT entry when all responses have been received.  
+    // - invalidate request initiated by the XRAM_RSP FSM.
+    //   The FSM decrements the proper entry in the Update/Inval_Table,
+    //   and clear the entry when all responses have been received.
+    //
+    // All those response packets are one word, compact
+    // packets complying with the VCI advanced format. 
+    // The index in the Table is defined in the RTRDID field, and
+    // the Transaction type is defined in the Update/Inval Table.
+    /////////////////////////////////////////////////////////////////////
+
+    switch ( r_init_rsp_fsm.read() ) {
+
+      ///////////////////
+      case INIT_RSP_IDLE:
+        {
+
+          if ( p_vci_ini.rspval ) {
+
+            assert ( ( p_vci_ini.rtrdid.read() < m_update_tab.size() )
+                && "VCI_MEM_CACHE UPT index too large in VCI response paquet received by memory cache" );
+            assert ( p_vci_ini.reop 
+                && "VCI_MEM_CACHE All response packets to update/invalidate requests must be one cell" );
+            r_init_rsp_upt_index = p_vci_ini.rtrdid.read(); 
+            r_init_rsp_fsm = INIT_RSP_UPT_LOCK;
+          }
+          break;
+        }
+        ///////////////////////
+      case INIT_RSP_UPT_LOCK:	// decrement the number of expected responses
+        {
+
+          if ( r_alloc_upt_fsm.read() == ALLOC_UPT_INIT_RSP ) { 
+            size_t count = 0;
+            bool valid  = m_update_tab.decrement(r_init_rsp_upt_index.read(), count);
+#ifdef IDEBUG
+if(m_cpt_cycles > DEBUG_START_CYCLE){
+	std::cout << sc_time_stamp() << " " << name() << " INIT_RSP_UPT_LOCK update table : " << std::endl;
+	m_update_tab.print();
+}
+#endif
+            assert ( valid 
+                && "VCI_MEM_CACHE Invalid UPT entry in VCI response paquet received by memory cache" );
+
+            if ( count == 0 ) r_init_rsp_fsm = INIT_RSP_UPT_CLEAR;
+            else              r_init_rsp_fsm = INIT_RSP_IDLE;
+          }
+          break;
+        }
+        ////////////////////////
+      case INIT_RSP_UPT_CLEAR:	// clear the UPT entry
+        {
+          if ( r_alloc_upt_fsm.read() == ALLOC_UPT_INIT_RSP ) {
+            r_init_rsp_srcid = m_update_tab.srcid(r_init_rsp_upt_index.read());
+            r_init_rsp_trdid = m_update_tab.trdid(r_init_rsp_upt_index.read());
+            r_init_rsp_pktid = m_update_tab.pktid(r_init_rsp_upt_index.read());
+            r_init_rsp_nline = m_update_tab.nline(r_init_rsp_upt_index.read());
+            bool need_rsp = m_update_tab.need_rsp(r_init_rsp_upt_index.read());
+            if ( need_rsp ) r_init_rsp_fsm = INIT_RSP_END;
+            else            r_init_rsp_fsm = INIT_RSP_IDLE;
+            m_update_tab.clear(r_init_rsp_upt_index.read());
+#ifdef IDEBUG
+if(m_cpt_cycles > DEBUG_START_CYCLE){
+	std::cout << sc_time_stamp() << " " << name() << " INIT_RSP_UPT_CLEAR update table : " << std::endl;
+	m_update_tab.print();
+}
+#endif
+          }
+          break;
+        }
+        //////////////////
+      case INIT_RSP_END:
+        {
+
+          if ( !r_init_rsp_to_tgt_rsp_req ) {
+            r_init_rsp_to_tgt_rsp_req = true;
+            r_init_rsp_to_tgt_rsp_srcid = r_init_rsp_srcid.read();
+            r_init_rsp_to_tgt_rsp_trdid = r_init_rsp_trdid.read();
+            r_init_rsp_to_tgt_rsp_pktid = r_init_rsp_pktid.read();
+            r_init_rsp_fsm = INIT_RSP_IDLE;
+          }
+          break;
+        }
+    } // end switch r_init_rsp_fsm
+
+    ////////////////////////////////////////////////////////////////////////////////////
+    //		READ FSM
+    ////////////////////////////////////////////////////////////////////////////////////
+    // The READ FSM controls the read requests sent by processors.
+    // It takes the lock protecting the cache directory to check the cache line status:
+    // - In case of HIT, the fsm copies the data (one line, or one single word)
+    //   in the r_read_to_tgt_rsp buffer. It waits if this buffer is not empty.
+    //   The requesting initiator is registered in the cache directory.
+    // - In case of MISS, the READ fsm takes the lock protecting the transaction tab.
+    //   If a read transaction to the XRAM for this line already exists,
+    //   or if the transaction tab is full, the fsm is stalled.
+    //   If a transaction entry is free, the READ fsm sends a request to the XRAM.
+    ////////////////////////////////////////////////////////////////////////////////////
+
+    switch ( r_read_fsm.read() ) {
+
+      ///////////////
+      case READ_IDLE:
+        {
+          if (m_cmd_read_addr_fifo.rok()) {
+            m_cpt_read++;
+            r_read_fsm = READ_DIR_LOCK;
+          }
+          break;
+        }
+        ///////////////////
+      case READ_DIR_LOCK:	// check directory for hit / miss
+        {
+          if( r_alloc_dir_fsm.read() == ALLOC_DIR_READ ) {
+            size_t way = 0;
+            DirectoryEntry entry = m_cache_directory.read(m_cmd_read_addr_fifo.read(), way);
+#ifdef DDEBUG
+if(m_cpt_cycles > DEBUG_START_CYCLE){
+	   std::cout << "In READ_DIR_LOCK printing the entry of address is : " << std::hex << m_cmd_read_addr_fifo.read() << std::endl;
+	   entry.print();
+	   std::cout << "done" << std::endl;
+}
+#endif
+
+            r_read_is_cnt   = entry.is_cnt;
+            r_read_dirty    = entry.dirty;
+            r_read_tag	    = entry.tag;
+            r_read_lock	    = entry.lock;
+            r_read_way	    = way;
+            r_read_d_copies = entry.d_copies; 
+            r_read_i_copies = entry.i_copies; 
+            r_read_count    = entry.count;
+
+            // In case of hit, the read acces must be registered in the copies bit-vector
+            if( entry.valid )  { 
+              r_read_fsm = READ_DIR_HIT;
+            } else {
+              r_read_fsm = READ_TRT_LOCK;
+              m_cpt_read_miss++;
+            }
+          }
+          break;
+        }
+        //////////////////
+      case READ_DIR_HIT:	// read hit : update the memory cache
+        {
+          if( r_alloc_dir_fsm.read() == ALLOC_DIR_READ ) {
+            // signals generation
+            bool inst_read = (m_cmd_read_trdid_fifo.read() & 0x2);
+            bool cached_read = (m_cmd_read_trdid_fifo.read() & 0x1);
+            bool is_cnt = ((r_read_count.read() >= r_copies_limit.read()) && cached_read) || r_read_is_cnt.read();
+
+            // read data in the cache
+            size_t set = m_y[(vci_addr_t)(m_cmd_read_addr_fifo.read())];
+            size_t way = r_read_way.read();
+            for ( size_t i=0 ; i<m_words ; i++ ) {
+              r_read_data[i] = m_cache_data[way][set][i];
+            }
+
+            // update the cache directory (for the copies)
+            DirectoryEntry entry;
+            entry.valid	  = true;
+            entry.is_cnt  = is_cnt; // when we reach the limit of copies
+            entry.dirty	  = r_read_dirty.read();
+            entry.tag	  = r_read_tag.read();
+            entry.lock	  = r_read_lock.read();
+            if(cached_read){  // Cached read, we update the copies vector
+              if(inst_read && !is_cnt){ // Instruction read, vector mode
+                assert(!(r_read_i_copies.read() & (0x1 << m_cmd_read_srcid_fifo.read())) && "MemCache Error : processor read on an already owned cache line");
+                entry.d_copies  = r_read_d_copies.read();
+                entry.i_copies  = r_read_i_copies.read() | (0x1 << m_cmd_read_srcid_fifo.read()); 
+                entry.count     = r_read_count.read() + 1;
+              }
+              if(!inst_read && !is_cnt){ // Data read, vector mode
+                if(r_read_d_copies.read() & (0x1 << m_cmd_read_srcid_fifo.read())) {
+                    std::cout << "MemCache Error : processor read on an already owned cache line, Time : " << m_cpt_cycles << std::endl;
+                    exit(0);
+                }
+                entry.d_copies  = r_read_d_copies.read() | (0x1 << m_cmd_read_srcid_fifo.read()); 
+                entry.i_copies  = r_read_i_copies.read();
+                entry.count     = r_read_count.read() + 1;
+              }
+              if( is_cnt ) { // Counter mode
+                entry.count     = r_read_count.read() + 1;
+                entry.d_copies  = 0;
+                entry.i_copies  = 0;
+              } 
+            } else { // Uncached read
+              entry.d_copies = r_read_d_copies.read();
+              entry.i_copies = r_read_i_copies.read();
+              entry.count    = r_read_count.read();
+            }
+#ifdef DDEBUG
+if(m_cpt_cycles > DEBUG_START_CYCLE){
+	   std::cout << "In READ_DIR_HIT printing the entry of address is : " << std::endl;
+	   entry.print();
+	   std::cout << "done" << std::endl;
+}
+#endif
+
+            m_cache_directory.write(set, way, entry);
+            r_read_fsm    = READ_RSP;
+          }
+          break;
+        }
+        //////////////
+      case READ_RSP: 		//  request the TGT_RSP FSM to return data
+        {
+          if( !r_read_to_tgt_rsp_req ) {	
+            for ( size_t i=0 ; i<m_words ; i++ ) {
+              r_read_to_tgt_rsp_data[i] = r_read_data[i];
+            }
+            r_read_to_tgt_rsp_word   = m_x[(vci_addr_t)m_cmd_read_addr_fifo.read()];
+            r_read_to_tgt_rsp_length = m_cmd_read_length_fifo.read();
+            cmd_read_fifo_get 		 = true;
+            r_read_to_tgt_rsp_req	 = true;
+            r_read_to_tgt_rsp_srcid	 = m_cmd_read_srcid_fifo.read();
+            r_read_to_tgt_rsp_trdid	 = m_cmd_read_trdid_fifo.read();
+            r_read_to_tgt_rsp_pktid	 = m_cmd_read_pktid_fifo.read();
+            r_read_fsm 			     = READ_IDLE;  
+          }
+          break;
+        }
+        ///////////////////
+      case READ_TRT_LOCK:	// read miss : check the Transaction Table
+        {
+          if ( r_alloc_trt_fsm.read() == ALLOC_TRT_READ ) {
+#ifdef TDEBUG
+if(m_cpt_cycles > DEBUG_START_CYCLE){
+	std::cout << sc_time_stamp() << " " << name() << " READ_TRT_LOCK " << std::endl;
+}
+#endif
+            size_t index = 0;
+            bool   hit_read = m_transaction_tab.hit_read(m_nline[(vci_addr_t)(m_cmd_read_addr_fifo.read())], index);
+            bool   hit_write = m_transaction_tab.hit_write(m_nline[(vci_addr_t)(m_cmd_read_addr_fifo.read())]);
+            bool   wok = !m_transaction_tab.full(index);
+            if( hit_read || !wok || hit_write ) {  // missing line already requested or no space
+              r_read_fsm = READ_IDLE;
+            } else {			   // missing line is requested to the XRAM
+              r_read_trt_index = index;
+              r_read_fsm       = READ_TRT_SET;
+            }
+          }
+          break;
+        }
+        //////////////////
+      case READ_TRT_SET:
+        {
+          if ( r_alloc_trt_fsm.read() == ALLOC_TRT_READ ) {
+            m_transaction_tab.set(r_read_trt_index.read(),
+                true,
+                m_nline[(vci_addr_t)(m_cmd_read_addr_fifo.read())],
+                m_cmd_read_srcid_fifo.read(),
+                m_cmd_read_trdid_fifo.read(),
+                m_cmd_read_pktid_fifo.read(),
+                true,
+                m_cmd_read_length_fifo.read(),
+                m_x[(vci_addr_t)(m_cmd_read_addr_fifo.read())],
+                std::vector<be_t>(m_words,0),
+                std::vector<data_t>(m_words,0));
+#ifdef TDEBUG
+if(m_cpt_cycles > DEBUG_START_CYCLE){
+	std::cout << sc_time_stamp() << " " << name() << " READ_TRT_SET transaction table : " << std::endl;
+	for(size_t i = 0 ; i < m_transaction_tab.size() ; i++)
+	  m_transaction_tab.print(i);
+}
+#endif
+
+            r_read_fsm 	 = READ_XRAM_REQ;
+          }
+          break;
+        }
+        /////////////////////
+      case READ_XRAM_REQ:
+        {
+          if( !r_read_to_ixr_cmd_req ) {
+            cmd_read_fifo_get		= true;
+            r_read_to_ixr_cmd_req  	= true;
+            r_read_to_ixr_cmd_nline 	= m_nline[(vci_addr_t)(m_cmd_read_addr_fifo.read())];
+            r_read_to_ixr_cmd_trdid 	= r_read_trt_index.read();
+            r_read_fsm 			          = READ_IDLE;
+          }
+          break;
+        }
+    } // end switch read_fsm
+
+    ///////////////////////////////////////////////////////////////////////////////////
+    //		WRITE FSM
+    ///////////////////////////////////////////////////////////////////////////////////
+    // The WRITE FSM handles the write bursts sent by the processors.
+    // All addresses in a burst must be in the same cache line.
+    // A complete write burst is consumed in the FIFO & copied to a local buffer.
+    // Then the FSM takes the lock protecting the cache directory, to check
+    // if the line is in the cache.
+    //
+    // - In case of HIT, the cache is updated.
+    //   If there is no other copy, an acknowledge response is immediately
+    //   returned to the writing processor.
+    //   if the data is cached by other processoris, the FSM takes the lock
+    //   protecting the Update Table (UPT) to register this update transaction.
+    //   If the UPT is full, it releases the lock  and waits. Then, it sends 
+    //   a multi-update request to all owners of the line (but the writer), 
+    //   through the INIT_CMD FSM. In case of multi-update transaction, the WRITE FSM 
+    //   does not respond to the writing processor, as this response will be sent by 
+    //   the INIT_RSP FSM when all update responses have been received.
+    //
+    // - In case of MISS, the WRITE FSM takes the lock protecting the transaction
+    //   table (TRT). If a read transaction to the XRAM for this line already exists, 
+    //   it writes in the TRT (write buffer). Otherwise, if a TRT entry is free, 
+    //   the WRITE FSM register a new transaction in TRT, and sends a read line request 
+    //   to the XRAM. If the TRT is full, it releases the lock, and waits.
+    //   Finally, the WRITE FSM returns an aknowledge response to the writing processor.
+    /////////////////////////////////////////////////////////////////////////////////////
+
+    switch ( r_write_fsm.read() ) {
+
+      ////////////////
+      case WRITE_IDLE:	// copy first word of a write burst in local buffer	
+        {
+          if ( m_cmd_write_addr_fifo.rok()) {
+            m_cpt_write++;
+            m_cpt_write_cells++;
+            // consume a word in the FIFO & write it in the local buffer 
+            cmd_write_fifo_get	= true;
+            size_t index 	    = m_x[(vci_addr_t)(m_cmd_write_addr_fifo.read())];
+            r_write_address	    = (addr_t)(m_cmd_write_addr_fifo.read());
+            r_write_word_index	= index;
+            r_write_word_count	= 1;
+            r_write_data[index]	= m_cmd_write_data_fifo.read();
+            r_write_srcid	    = m_cmd_write_srcid_fifo.read();
+            r_write_trdid	    = m_cmd_write_trdid_fifo.read();
+            r_write_pktid	    = m_cmd_write_pktid_fifo.read();
+
+            // the be field must be set for all words 
+            for ( size_t i=0 ; i<m_words ; i++ ) {
+              if ( i == index ) r_write_be[i] = m_cmd_write_be_fifo.read();
+              else		        r_write_be[i] = 0x0;
+            }
+            if( !((m_cmd_write_be_fifo.read() == 0x0)||(m_cmd_write_be_fifo.read() == 0xF)) )
+                    r_write_byte=true;
+            else    r_write_byte=false;
+
+            if( m_cmd_write_eop_fifo.read() )  r_write_fsm = WRITE_DIR_LOCK;
+            else                               r_write_fsm = WRITE_NEXT;
+          }
+          break;
+        }
+        ////////////////
+      case WRITE_NEXT:	// copy next word of a write burst in local buffer
+        {
+          if ( m_cmd_write_addr_fifo.rok() ) {
+            m_cpt_write_cells++;
+
+            // check that the next word is in the same cache line
+            assert( (m_nline[(vci_addr_t)(r_write_address.read())] == m_nline[(vci_addr_t)(m_cmd_write_addr_fifo.read())])  
+                && "VCI_MEM_CACHE write error in vci_mem_cache : write burst over a line" );
+            // consume a word in the FIFO & write it in the local buffer 
+            cmd_write_fifo_get=true;
+            size_t index 	        = r_write_word_index.read() + r_write_word_count.read();
+            r_write_be[index]       = m_cmd_write_be_fifo.read();
+            r_write_data[index]     = m_cmd_write_data_fifo.read();
+            r_write_word_count 	    = r_write_word_count.read() + 1;
+            if( !((m_cmd_write_be_fifo.read() == 0x0)||(m_cmd_write_be_fifo.read() == 0xF)) )
+              r_write_byte=true;
+            if ( m_cmd_write_eop_fifo.read() )  r_write_fsm = WRITE_DIR_LOCK;
+          }
+          break;
+        }
+        ////////////////////
+      case WRITE_DIR_LOCK:	// access directory to check hit/miss
+        {
+          if ( r_alloc_dir_fsm.read() == ALLOC_DIR_WRITE ) {
+            size_t  way = 0;
+            DirectoryEntry entry(m_cache_directory.read(r_write_address.read(), way));
+
+            // copy directory entry in local buffers in case of hit
+            if ( entry.valid )  {	
+              r_write_is_cnt    = entry.is_cnt;
+              r_write_lock	    = entry.lock;
+              r_write_tag       = entry.tag;
+              r_write_d_copies  = entry.d_copies;
+              r_write_i_copies  = entry.i_copies;
+              r_write_count     = entry.count;
+              r_write_way  	    = way;
+              if((entry.is_cnt && entry.count) ||
+                  entry.i_copies){
+                r_write_fsm      = WRITE_DIR_HIT_READ;
+              } else {
+                if(r_write_byte.read())
+                  r_write_fsm      = WRITE_DIR_HIT_READ;
+                else {
+                    bool owner     = (bool) (entry.d_copies & (0x1 << r_write_srcid.read()));
+                    bool no_update = (owner && (entry.count == 1)) || (entry.count==0);
+                    if( no_update ) r_write_fsm  = WRITE_DIR_HIT_RSP; 
+                    else            r_write_fsm  = WRITE_DIR_HIT;
+                }
+              }
+            } else {
+              r_write_fsm = WRITE_TRT_LOCK;
+              m_cpt_write_miss++;
+            }
+          }
+          break;
+        }
+        ///////////////////
+      case WRITE_DIR_HIT_READ:	// read the cache and complete the buffer (data, when be!=0xF)
+        {
+          // update local buffer
+          size_t set	= m_y[(vci_addr_t)(r_write_address.read())];
+          size_t way	= r_write_way.read();
+          for(size_t i=0 ; i<m_words ; i++) {
+            data_t mask      = 0;
+            if  (r_write_be[i].read() & 0x1) mask = mask | 0x000000FF;
+            if  (r_write_be[i].read() & 0x2) mask = mask | 0x0000FF00;
+            if  (r_write_be[i].read() & 0x4) mask = mask | 0x00FF0000;
+            if  (r_write_be[i].read() & 0x8) mask = mask | 0xFF000000;
+            if(r_write_be[i].read()||r_write_is_cnt.read()||r_write_i_copies.read()) { // complete only if mask is not null (for energy consumption)
+              r_write_data[i]  = (r_write_data[i].read() & mask) | 
+                (m_cache_data[way][set][i] & ~mask);
+            }
+          } // end for
+
+          if((r_write_is_cnt.read() && r_write_count.read()) ||
+              r_write_i_copies.read()){
+              r_write_fsm    = WRITE_TRT_WRITE_LOCK;
+          } else {
+              bool owner     = (bool) (r_write_d_copies.read() & (0x1 << r_write_srcid.read()));
+              bool no_update = (owner && (r_write_count.read() == 1)) || (r_write_count.read()==0);
+              if( no_update )   r_write_fsm    = WRITE_DIR_HIT_RSP;
+              else              r_write_fsm    = WRITE_DIR_HIT;
+          }
+          break;
+        }
+        ///////////////////
+      case WRITE_DIR_HIT:	// update the cache (data & dirty bit)
+        {
+          // update directory with Dirty bit
+          DirectoryEntry entry;
+          entry.valid	    = true;
+          entry.dirty	    = true;
+          entry.tag	        = r_write_tag.read();
+          entry.is_cnt      = r_write_is_cnt.read();
+          entry.lock	    = r_write_lock.read();
+          entry.d_copies    = r_write_d_copies.read();
+          entry.i_copies    = 0;
+          entry.count       = r_write_count.read();
+          size_t set	    = m_y[(vci_addr_t)(r_write_address.read())];
+          size_t way	    = r_write_way.read();
+          m_cache_directory.write(set, way, entry);
+
+          // write data in cache
+          for(size_t i=0 ; i<m_words ; i++) {
+            if  ( r_write_be[i].read() ) {
+              m_cache_data[way][set][i]  = r_write_data[i].read();
+            }
+          } // end for
+
+          // compute the actual number of copies & the modified bit vector
+          bool owner = (bool) (r_write_d_copies.read() & (0x1 << r_write_srcid.read()));
+          copy_t d_copies = r_write_d_copies.read() & ~(0x1 << r_write_srcid.read());
+          r_write_d_copies      = d_copies;
+          size_t count_signal   = r_write_count.read();
+          if(owner){
+            count_signal        = count_signal - 1;
+          }
+          r_write_count         = count_signal;
+
+          r_write_fsm = WRITE_UPT_LOCK;
+          break;
+        }
+        ///////////////////
+      case WRITE_DIR_HIT_RSP:	// update the cache (data & dirty bit) (no update)
+        {
+          // update directory with Dirty bit
+          DirectoryEntry entry;
+          entry.valid	    = true;
+          entry.dirty	    = true;
+          entry.tag	        = r_write_tag.read();
+          entry.is_cnt      = r_write_is_cnt.read();
+          entry.lock	    = r_write_lock.read();
+          entry.d_copies    = r_write_d_copies.read();
+          entry.i_copies    = 0;
+          entry.count       = r_write_count.read();
+          size_t set	    = m_y[(vci_addr_t)(r_write_address.read())];
+          size_t way	    = r_write_way.read();
+          m_cache_directory.write(set, way, entry);
+
+          // write data in cache
+          for(size_t i=0 ; i<m_words ; i++) {
+            if  ( r_write_be[i].read() ) {
+              m_cache_data[way][set][i]  = r_write_data[i].read();
+            }
+          } // end for
+
+          if ( !r_write_to_tgt_rsp_req.read() ) {
+            r_write_to_tgt_rsp_req	    = true;
+            r_write_to_tgt_rsp_srcid	= r_write_srcid.read();
+            r_write_to_tgt_rsp_trdid	= r_write_trdid.read();
+            r_write_to_tgt_rsp_pktid	= r_write_pktid.read();
+            r_write_fsm 		        = WRITE_IDLE;
+          } else {
+            r_write_fsm = WRITE_RSP;
+          }
+          break;
+        }
+
+        /////////////////////
+      case WRITE_UPT_LOCK: 	// Try to register the request in Update Table
+        {
+
+          if ( r_alloc_upt_fsm.read() == ALLOC_UPT_WRITE ) {
+            bool        wok        = false;
+            size_t      index      = 0;
+            size_t      srcid      = r_write_srcid.read();
+            size_t      trdid      = r_write_trdid.read();
+            size_t      pktid      = r_write_pktid.read();
+            addr_t      nline      = m_nline[(vci_addr_t)(r_write_address.read())];
+            size_t      nb_copies  = r_write_count.read();
+
+            wok =m_update_tab.set(true,	// it's an update transaction
+                false,                  // it's not a broadcast
+                true,                   // it needs a response
+                srcid,
+                trdid,
+                pktid,
+                nline,
+                nb_copies,
+                index);
+#ifdef IDEBUG
+if(m_cpt_cycles > DEBUG_START_CYCLE){
+            if(wok){
+	std::cout << sc_time_stamp() << " " << name() << " WRITE_UPT_LOCK update table : " << std::endl;
+	m_update_tab.print();
+            }
+}
+#endif
+            r_write_upt_index = index;
+            //  releases the lock protecting Update Table if no entry...
+            if ( wok ) r_write_fsm = WRITE_UPDATE;
+            else       r_write_fsm = WRITE_WAIT_UPT;
+          }
+          break;
+        }
+        ////////////////////
+      case WRITE_WAIT_UPT:	// release the lock protecting UPT
+        {
+          r_write_fsm = WRITE_UPT_LOCK;
+          break;
+        }
+        //////////////////
+      case WRITE_UPDATE:	// send a multi-update request to INIT_CMD fsm
+        {
+
+          if ( !r_write_to_init_cmd_req ) {
+            r_write_to_init_cmd_req      = true;
+            r_write_to_init_cmd_brdcast  = false;
+            r_write_to_init_cmd_trdid    = r_write_upt_index.read();
+            r_write_to_init_cmd_nline    = m_nline[(vci_addr_t)(r_write_address.read())];
+            r_write_to_init_cmd_index    = r_write_word_index.read();
+            r_write_to_init_cmd_count    = r_write_word_count.read();
+            r_write_to_init_cmd_d_copies = r_write_d_copies.read();
+
+            for(size_t i=0; i<m_words ; i++){
+              r_write_to_init_cmd_be[i]=r_write_be[i].read();
+            }
+
+            size_t min = r_write_word_index.read();
+            size_t max = r_write_word_index.read() + r_write_word_count.read();
+            for (size_t i=min ; i<max ; i++) {
+              r_write_to_init_cmd_data[i] = r_write_data[i];
+            }
+            r_write_fsm = WRITE_IDLE; // Response will be sent after receiving
+            // all update responses
+          }
+          break;
+        }
+        ///////////////
+      case WRITE_RSP:		// send a request to TGT_RSP FSM to acknowledge the write
+        {
+          if ( !r_write_to_tgt_rsp_req.read() ) {
+            r_write_to_tgt_rsp_req	    = true;
+            r_write_to_tgt_rsp_srcid	= r_write_srcid.read();
+            r_write_to_tgt_rsp_trdid	= r_write_trdid.read();
+            r_write_to_tgt_rsp_pktid	= r_write_pktid.read();
+            r_write_fsm 		        = WRITE_IDLE;
+          }
+          break;
+        }
+        ////////////////////
+      case WRITE_TRT_LOCK:	// Miss : check Transaction Table
+        {
+          if ( r_alloc_trt_fsm.read() == ALLOC_TRT_WRITE ) {
+#ifdef TDEBUG
+if(m_cpt_cycles > DEBUG_START_CYCLE){
+	std::cout << sc_time_stamp() << " " << name() << " READ_TRT_LOCK " << std::endl;
+}
+#endif
+            size_t hit_index = 0;
+            size_t wok_index = 0;
+            bool hit_read  = m_transaction_tab.hit_read(m_nline[(vci_addr_t)(r_write_address.read())],hit_index);
+            bool hit_write = m_transaction_tab.hit_write(m_nline[(vci_addr_t)(r_write_address.read())]);
+            bool wok = !m_transaction_tab.full(wok_index);
+            if ( hit_read ) {	// register the modified data in TRT 
+              r_write_trt_index = hit_index;
+              r_write_fsm       = WRITE_TRT_DATA;
+            } else if ( wok && !hit_write ) {	// set a new entry in TRT
+              r_write_trt_index = wok_index;
+              r_write_fsm       = WRITE_TRT_SET;
+            } else {		// wait an empty entry in TRT
+              r_write_fsm       = WRITE_WAIT_TRT;
+            }
+          }
+          break;
+        }
+        ////////////////////
+      case WRITE_WAIT_TRT:	// release the lock protecting TRT
+        { 
+          r_write_fsm = WRITE_DIR_LOCK;
+          break;
+        }
+        ///////////////////
+      case WRITE_TRT_SET:	// register a new transaction in TRT (Write Buffer)
+        {  
+          if ( r_alloc_trt_fsm.read() == ALLOC_TRT_WRITE ) 
+          {
+            std::vector<be_t> be_vector;
+            std::vector<data_t> data_vector;
+            be_vector.clear();
+            data_vector.clear();
+            for ( size_t i=0; i<m_words; i++ ) 
+            {
+              be_vector.push_back(r_write_be[i]);
+              data_vector.push_back(r_write_data[i]);
+            }
+            m_transaction_tab.set(r_write_trt_index.read(),
+                true,				// read request to XRAM
+                m_nline[(vci_addr_t)(r_write_address.read())],
+                r_write_srcid.read(),
+                r_write_trdid.read(),
+                r_write_pktid.read(),
+                false,				// not a processor read
+                0,  				// not a single word 
+                0,		        	// word index
+                be_vector,
+                data_vector);
+#ifdef TDEBUG
+if(m_cpt_cycles > DEBUG_START_CYCLE){
+	std::cout << sc_time_stamp() << " " << name() << " WRITE_TRT_SET transaction table : " << std::endl;
+	for(size_t i = 0 ; i < m_transaction_tab.size() ; i++)
+	  m_transaction_tab.print(i);
+}
+#endif
+
+            r_write_fsm = WRITE_XRAM_REQ;
+          }
+          break;
+        }  
+        ///////////////////
+      case WRITE_TRT_DATA:	// update an entry in TRT (Write Buffer)
+        { 
+          if ( r_alloc_trt_fsm.read() == ALLOC_TRT_WRITE ) {
+            std::vector<be_t> be_vector;
+            std::vector<data_t> data_vector;
+            be_vector.clear();
+            data_vector.clear();
+            for ( size_t i=0; i<m_words; i++ ) {
+              be_vector.push_back(r_write_be[i]);
+              data_vector.push_back(r_write_data[i]);
+            }
+            m_transaction_tab.write_data_mask(r_write_trt_index.read(),
+                be_vector,
+                data_vector);
+            r_write_fsm = WRITE_RSP;
+#ifdef TDEBUG
+if(m_cpt_cycles > DEBUG_START_CYCLE){
+	std::cout << sc_time_stamp() << " " << name() << " WRITE_TRT_DATA transaction table : " << std::endl;
+	for(size_t i = 0 ; i < m_transaction_tab.size() ; i++)
+	  m_transaction_tab.print(i);
+}
+#endif
+
+          }
+          break;
+        }
+        ////////////////////
+      case WRITE_XRAM_REQ:	// send a request to IXR_CMD FSM
+        {  
+
+          if ( !r_write_to_ixr_cmd_req ) {
+            r_write_to_ixr_cmd_req   = true;
+            r_write_to_ixr_cmd_write = false;
+            r_write_to_ixr_cmd_nline = m_nline[(vci_addr_t)(r_write_address.read())];
+            r_write_to_ixr_cmd_trdid = r_write_trt_index.read();
+            r_write_fsm              = WRITE_RSP;
+          }
+          break;
+        }
+        ////////////////////
+      case WRITE_TRT_WRITE_LOCK:
+        {
+          if ( r_alloc_trt_fsm.read() == ALLOC_TRT_WRITE ) {
+            size_t wok_index = 0;
+            bool wok = !m_transaction_tab.full(wok_index);
+            if ( wok ) {	// set a new entry in TRT
+              r_write_trt_index = wok_index;
+              r_write_fsm       = WRITE_INVAL_LOCK;
+            } else {		// wait an empty entry in TRT
+              r_write_fsm       = WRITE_WAIT_TRT;
+            }
+          }
+
+          break;
+        }
+        ////////////////////
+      case WRITE_INVAL_LOCK:
+        {
+          if ( r_alloc_upt_fsm.read() == ALLOC_UPT_WRITE ) {
+            bool        wok       = false;
+            size_t      index     = 0;
+            size_t      srcid     = r_write_srcid.read();
+            size_t      trdid     = r_write_trdid.read();
+            size_t      pktid     = r_write_pktid.read();
+            addr_t	    nline     = m_nline[(vci_addr_t)(r_write_address.read())];
+            size_t      nb_copies = r_write_count.read();
+
+            wok =m_update_tab.set(false,	// it's an inval transaction
+                true,                       // it's a broadcast
+                true,                       // it needs a response
+                srcid,
+                trdid,
+                pktid,
+                nline,
+                nb_copies,
+                index);
+#ifdef IDEBUG
+if(m_cpt_cycles > DEBUG_START_CYCLE){
+            if(wok){
+	std::cout << sc_time_stamp() << " " << name() << " WRITE_INVAL_LOCK update table : " << std::endl;
+	m_update_tab.print();
+            }
+}
+#endif
+            r_write_upt_index = index;
+            //  releases the lock protecting Update Table if no entry...
+            if ( wok ) r_write_fsm = WRITE_DIR_INVAL;
+            else       r_write_fsm = WRITE_WAIT_TRT;
+          }
+
+          break;
+        }
+        ////////////////////
+      case WRITE_DIR_INVAL:
+        {
+          if ( (r_alloc_trt_fsm.read() == ALLOC_TRT_WRITE ) &&
+              (r_alloc_upt_fsm.read() == ALLOC_UPT_WRITE ) )
+          {
+            m_transaction_tab.set(r_write_trt_index.read(),
+                false,				// write request to XRAM
+                m_nline[(vci_addr_t)(r_write_address.read())],
+                0,
+                0,
+                0,
+                false,				// not a processor read
+                0,  				// not a single word 
+                0,		        	// word index
+                std::vector<be_t>(m_words,0),
+                std::vector<data_t>(m_words,0));
+#ifdef TDEBUG
+if(m_cpt_cycles > DEBUG_START_CYCLE){
+	std::cout << sc_time_stamp() << " " << name() << " WRITE_DIR_INVAL transaction table : " << std::endl;
+	for(size_t i = 0 ; i < m_transaction_tab.size() ; i++)
+	  m_transaction_tab.print(i);
+}
+#endif
+
+            // invalidate directory entry
+            DirectoryEntry entry;
+            entry.valid	   = false;
+            entry.dirty	   = false;
+            entry.tag	   = 0;
+            entry.is_cnt   = false;
+            entry.lock	   = false;
+            entry.d_copies = 0;
+            entry.i_copies = 0;
+            entry.count    = 0;
+            size_t set	   = m_y[(vci_addr_t)(r_write_address.read())];
+            size_t way	   = r_write_way.read();
+            m_cache_directory.write(set, way, entry);
+
+            r_write_fsm = WRITE_INVAL;
+          } else {
+            assert(false && "LOCK ERROR in WRITE_FSM, STATE = WRITE_DIR_INVAL");
+          }
+
+          break;
+        }
+        ////////////////////
+      case WRITE_INVAL:
+        {
+          if ( !r_write_to_init_cmd_req ) {
+            r_write_to_init_cmd_req      = true;
+            r_write_to_init_cmd_brdcast  = true;
+            r_write_to_init_cmd_trdid    = r_write_upt_index.read();
+            r_write_to_init_cmd_nline    = m_nline[(vci_addr_t)(r_write_address.read())];
+            r_write_to_init_cmd_index    = 0;
+            r_write_to_init_cmd_count    = 0;
+            r_write_to_init_cmd_d_copies = 0;
+
+            for(size_t i=0; i<m_words ; i++){
+              r_write_to_init_cmd_be[i]=0;
+              r_write_to_init_cmd_data[i] = 0;
+            }
+            r_write_fsm = WRITE_XRAM_SEND;
+            // all update responses
+          }
+
+          break;
+        }
+        ////////////////////
+      case WRITE_XRAM_SEND:
+        {
+          if ( !r_write_to_ixr_cmd_req ) {
+            r_write_to_ixr_cmd_req     = true;
+            r_write_to_ixr_cmd_write   = true;
+            r_write_to_ixr_cmd_nline   = m_nline[(vci_addr_t)(r_write_address.read())];
+            r_write_to_ixr_cmd_trdid   = r_write_trt_index.read();
+            for(size_t i=0; i<m_words; i++){
+              r_write_to_ixr_cmd_data[i] = r_write_data[i];
+            }
+            r_write_fsm                 = WRITE_IDLE;
+          }
+          break;
+        }
+    } // end switch r_write_fsm
+
+    ///////////////////////////////////////////////////////////////////////
+    //		IXR_CMD FSM
+    ///////////////////////////////////////////////////////////////////////
+    // The IXR_CMD fsm controls the command packets to the XRAM :
+    // - It sends a single cell VCI read to the XRAM in case of MISS request
+    // posted by the READ, WRITE or LLSC FSMs : the TRDID field contains 
+    // the Transaction Tab index.
+    // The VCI response is a multi-cell packet : the N cells contain
+    // the N data words.
+    // - It sends a multi-cell VCI write when the XRAM_RSP FSM request 
+    // to save a dirty line to the XRAM. 
+    // The VCI response is a single cell packet.
+    // This FSM handles requests from the READ, WRITE, LLSC & XRAM_RSP FSMs 
+    // with a round-robin priority.
+    ////////////////////////////////////////////////////////////////////////
+
+    switch ( r_ixr_cmd_fsm.read() ) {
+      //////////////////////// 
+      case IXR_CMD_READ_IDLE:
+        if      ( r_write_to_ixr_cmd_req )     r_ixr_cmd_fsm = IXR_CMD_WRITE_NLINE;
+        else if ( r_llsc_to_ixr_cmd_req  )     r_ixr_cmd_fsm = IXR_CMD_LLSC_NLINE;
+        else if ( r_xram_rsp_to_ixr_cmd_req  ) r_ixr_cmd_fsm = IXR_CMD_XRAM_DATA;
+        else if ( r_read_to_ixr_cmd_req  )     r_ixr_cmd_fsm = IXR_CMD_READ_NLINE;
+        break;
+        //////////////////////// 
+      case IXR_CMD_WRITE_IDLE:
+        if      ( r_llsc_to_ixr_cmd_req  )     r_ixr_cmd_fsm = IXR_CMD_LLSC_NLINE;
+        else if ( r_xram_rsp_to_ixr_cmd_req  ) r_ixr_cmd_fsm = IXR_CMD_XRAM_DATA;
+        else if ( r_read_to_ixr_cmd_req  )     r_ixr_cmd_fsm = IXR_CMD_READ_NLINE;
+        else if ( r_write_to_ixr_cmd_req )     r_ixr_cmd_fsm = IXR_CMD_WRITE_NLINE;
+        break;
+        //////////////////////// 
+      case IXR_CMD_LLSC_IDLE:
+        if      ( r_xram_rsp_to_ixr_cmd_req  ) r_ixr_cmd_fsm = IXR_CMD_XRAM_DATA;
+        else if ( r_read_to_ixr_cmd_req  )     r_ixr_cmd_fsm = IXR_CMD_READ_NLINE;
+        else if ( r_write_to_ixr_cmd_req )     r_ixr_cmd_fsm = IXR_CMD_WRITE_NLINE;
+        else if ( r_llsc_to_ixr_cmd_req  )     r_ixr_cmd_fsm = IXR_CMD_LLSC_NLINE;
+        break;
+        //////////////////////// 
+      case IXR_CMD_XRAM_IDLE:
+        if      ( r_read_to_ixr_cmd_req  )     r_ixr_cmd_fsm = IXR_CMD_READ_NLINE;
+        else if ( r_write_to_ixr_cmd_req )     r_ixr_cmd_fsm = IXR_CMD_WRITE_NLINE;
+        else if ( r_llsc_to_ixr_cmd_req  )     r_ixr_cmd_fsm = IXR_CMD_LLSC_NLINE;
+        else if ( r_xram_rsp_to_ixr_cmd_req  ) r_ixr_cmd_fsm = IXR_CMD_XRAM_DATA;
+        break;
+        /////////////////////////
+      case IXR_CMD_READ_NLINE:
+        if ( p_vci_ixr.cmdack ) {
+          r_ixr_cmd_fsm = IXR_CMD_READ_IDLE;		
+          r_read_to_ixr_cmd_req = false;
+        }
+        break;
+        //////////////////////////
+      case IXR_CMD_WRITE_NLINE:
+        if ( p_vci_ixr.cmdack ) {
+          if( r_write_to_ixr_cmd_write.read()){
+            if ( r_ixr_cmd_cpt.read() == (m_words - 1) ) {
+              r_ixr_cmd_cpt = 0;
+              r_ixr_cmd_fsm = IXR_CMD_WRITE_IDLE;
+              r_write_to_ixr_cmd_req = false;
+            } else {
+              r_ixr_cmd_cpt = r_ixr_cmd_cpt + 1;
+            }
+          } else {
+            r_ixr_cmd_fsm = IXR_CMD_WRITE_IDLE;		
+            r_write_to_ixr_cmd_req = false;
+          }
+        }
+        break;
+        /////////////////////////
+      case IXR_CMD_LLSC_NLINE:
+        if ( p_vci_ixr.cmdack ) {
+          if( r_llsc_to_ixr_cmd_write.read()){
+            if ( r_ixr_cmd_cpt.read() == (m_words - 1) ) {
+              r_ixr_cmd_cpt = 0;
+              r_ixr_cmd_fsm = IXR_CMD_LLSC_IDLE;
+              r_llsc_to_ixr_cmd_req = false;
+            } else {
+              r_ixr_cmd_cpt = r_ixr_cmd_cpt + 1;
+            }
+          } else {
+            r_ixr_cmd_fsm = IXR_CMD_LLSC_IDLE;		
+            r_llsc_to_ixr_cmd_req = false;
+          }
+        }
+        break;
+        ////////////////////////
+      case IXR_CMD_XRAM_DATA:
+        if ( p_vci_ixr.cmdack ) {
+          if ( r_ixr_cmd_cpt.read() == (m_words - 1) ) {
+            r_ixr_cmd_cpt = 0;
+            r_ixr_cmd_fsm = IXR_CMD_XRAM_IDLE;
+            r_xram_rsp_to_ixr_cmd_req = false;
+          } else {
+            r_ixr_cmd_cpt = r_ixr_cmd_cpt + 1;
+          }
+        }
+        break;
+
+    } // end switch r_ixr_cmd_fsm
+
+    ////////////////////////////////////////////////////////////////////////////
+    //                IXR_RSP FSM
+    ////////////////////////////////////////////////////////////////////////////
+    // The IXR_RSP FSM receives the response packets from the XRAM,
+    // for both write transaction, and read transaction.
+    //
+    // - A response to a write request is a single-cell VCI packet.
+    // The Transaction Tab index is contained in the RTRDID field.
+    // The FSM takes the lock protecting the TRT, and the corresponding
+    // entry is erased.
+    //	
+    // - A response to a read request is a multi-cell VCI packet.
+    // The Transaction Tab index is contained in the RTRDID field.
+    // The N cells contain the N words of the cache line in the RDATA field.
+    // The FSM takes the lock protecting the TRT to store the line in the TRT
+    // (taking into account the write requests already stored in the TRT).
+    // When the line is completely written, the corresponding rok signal is set.
+    ///////////////////////////////////////////////////////////////////////////////
+
+    switch ( r_ixr_rsp_fsm.read() ) {
+
+      ///////////////////
+      case IXR_RSP_IDLE:	// test if it's a read or a write transaction
+        {
+          if ( p_vci_ixr.rspval ) {
+            r_ixr_rsp_cpt   = 0;
+            r_ixr_rsp_trt_index = p_vci_ixr.rtrdid.read();
+            if ( p_vci_ixr.reop )  r_ixr_rsp_fsm = IXR_RSP_ACK;
+            else                   r_ixr_rsp_fsm = IXR_RSP_TRT_READ;
+          }
+          break;  
+        }
+        ////////////////////////
+      case IXR_RSP_ACK:        // Acknowledge the vci response
+        r_ixr_rsp_fsm = IXR_RSP_TRT_ERASE;
+        break;
+        ////////////////////////
+      case IXR_RSP_TRT_ERASE: 	// erase the entry in the TRT
+        {
+          if ( r_alloc_trt_fsm.read() == ALLOC_TRT_IXR_RSP ) {
+            m_transaction_tab.erase(r_ixr_rsp_trt_index.read());
+            r_ixr_rsp_fsm = IXR_RSP_IDLE;
+#ifdef TDEBUG
+if(m_cpt_cycles > DEBUG_START_CYCLE){
+	std::cout << sc_time_stamp() << " " << name() << " IXR_RSP_TRT_ERASE transaction table : " << std::endl;
+	for(size_t i = 0 ; i < m_transaction_tab.size() ; i++)
+	  m_transaction_tab.print(i);
+}
+#endif
+
+          }
+          break;
+        }
+        ///////////////////////
+      case IXR_RSP_TRT_READ:		// write data in the TRT
+        {
+          if ( (r_alloc_trt_fsm.read() == ALLOC_TRT_IXR_RSP) &&  p_vci_ixr.rspval ) {
+            bool   eop  	= p_vci_ixr.reop.read();
+            data_t data 	= p_vci_ixr.rdata.read();
+            size_t index        = r_ixr_rsp_trt_index.read();
+            assert( eop == (r_ixr_rsp_cpt.read() == (m_words-1)) 
+                && "Error in VCI_MEM_CACHE : invalid length for a response from XRAM");
+            m_transaction_tab.write_rsp(index, r_ixr_rsp_cpt.read(), data);
+            r_ixr_rsp_cpt = r_ixr_rsp_cpt.read() + 1;
+            if ( eop ) {
+#ifdef TDEBUG
+if(m_cpt_cycles > DEBUG_START_CYCLE){
+	std::cout << sc_time_stamp() << " " << name() << " IXR_RSP_TRT_READ transaction table : " << std::endl;
+	for(size_t i = 0 ; i < m_transaction_tab.size() ; i++)
+	  m_transaction_tab.print(i);
+}
+#endif
+
+              r_ixr_rsp_to_xram_rsp_rok[r_ixr_rsp_trt_index.read()]=true;
+              r_ixr_rsp_fsm = IXR_RSP_IDLE;
+            }
+          }
+          break;
+        }
+    } // end swich r_ixr_rsp_fsm
+
+
+    ////////////////////////////////////////////////////////////////////////////
+    //                XRAM_RSP FSM
+    ////////////////////////////////////////////////////////////////////////////
+    // The XRAM_RSP FSM handles the incoming cache lines from the XRAM.
+    // The cache line has been written in the TRT buffer by the IXR_FSM.
+    //
+    // When a response is available, the corresponding TRT entry 
+    // is copied in a local buffer to be written in the cache. 
+    // Then, the FSM releases the lock protecting the TRT, and takes the lock 
+    // protecting the cache directory.
+    // It selects a cache slot and writes the line in the cache.
+    // If it was a read MISS, the XRAM_RSP FSM send a request to the TGT_RSP
+    // FSM to return the cache line to the registered processor.
+    // If there is no empty slot, a victim line is evicted, and
+    // invalidate requests are sent to the L1 caches containing copies.
+    // If this line is dirty, the XRAM_RSP FSM send a request to the IXR_CMD 
+    // FSM to save the victim line to the XRAM, and register the write transaction
+    // in the TRT (using the entry previously used by the read transaction).
+    ///////////////////////////////////////////////////////////////////////////////
+
+    switch ( r_xram_rsp_fsm.read() ) {
+
+      ///////////////////
+      case XRAM_RSP_IDLE:	// test if there is a response with a round robin priority
+        {
+          size_t ptr   = r_xram_rsp_trt_index.read();
+          size_t lines = TRANSACTION_TAB_LINES;
+          for(size_t i=0; i<lines; i++){
+            size_t index=(i+ptr+1)%lines;
+            if(r_ixr_rsp_to_xram_rsp_rok[index]){
+              r_xram_rsp_trt_index=index;
+              r_ixr_rsp_to_xram_rsp_rok[index]=false;
+              r_xram_rsp_fsm           = XRAM_RSP_DIR_LOCK;
+              break;
+#ifdef TDEBUG
+if(m_cpt_cycles > DEBUG_START_CYCLE){
+	std::cout << "XRAM_RSP FSM in XRAM_RSP_IDLE state" << std::endl;
+}
+#endif
+            }
+          }
+          break;  
+        }
+        ///////////////////////
+      case XRAM_RSP_DIR_LOCK: 	// Take the lock on the directory
+        {
+          if( r_alloc_dir_fsm.read() == ALLOC_DIR_XRAM_RSP ) {
+            r_xram_rsp_fsm           = XRAM_RSP_TRT_COPY;
+#ifdef TDEBUG
+if(m_cpt_cycles > DEBUG_START_CYCLE){
+	std::cout << "XRAM_RSP FSM in XRAM_RSP_DIR_LOCK state" << std::endl;
+}
+#endif
+          }
+          break;
+        }
+        ///////////////////////
+      case XRAM_RSP_TRT_COPY:		// Copy the TRT entry in the local buffer and eviction of a cache line
+        {
+          if ( (r_alloc_trt_fsm.read() == ALLOC_TRT_XRAM_RSP) ) {
+            size_t index = r_xram_rsp_trt_index.read();
+            TransactionTabEntry    trt_entry(m_transaction_tab.read(index));	
+
+            r_xram_rsp_trt_buf.copy(trt_entry);  // TRT entry local buffer
+
+            // selects & extracts a victim line from cache
+            size_t way = 0;
+            size_t set = m_y[(vci_addr_t)(trt_entry.nline * m_words * 4)];
+            DirectoryEntry victim(m_cache_directory.select(set, way));
+
+            for (size_t i=0 ; i<m_words ; i++) r_xram_rsp_victim_data[i] = m_cache_data[way][set][i];
+
+            bool inval = (victim.count && victim.valid) ;
+
+            r_xram_rsp_victim_d_copies = victim.d_copies;
+            r_xram_rsp_victim_i_copies = victim.i_copies;
+            r_xram_rsp_victim_count    = victim.count;
+            r_xram_rsp_victim_way      = way;
+            r_xram_rsp_victim_set      = set;
+            r_xram_rsp_victim_nline    = victim.tag*m_sets + set;
+            r_xram_rsp_victim_is_cnt   = victim.is_cnt;
+            r_xram_rsp_victim_inval    = inval ;
+            r_xram_rsp_victim_dirty    = victim.dirty;
+
+            r_xram_rsp_fsm = XRAM_RSP_INVAL_LOCK;
+#ifdef TDEBUG
+if(m_cpt_cycles > DEBUG_START_CYCLE){
+	std::cout << "XRAM_RSP FSM in XRAM_RSP_TRT_COPY state" << std::endl;
+	std::cout << "Victim way : " << std::hex << way << " set " << std::hex << set << std::endl;
+	victim.print();
+}
+#endif
+          }
+          break;
+        }
+        ///////////////////////
+      case XRAM_RSP_INVAL_LOCK:
+        {
+          if ( r_alloc_upt_fsm == ALLOC_UPT_XRAM_RSP ) {
+#ifdef IDEBUG
+if(m_cpt_cycles > DEBUG_START_CYCLE){
+	std::cout << "XRAM_RSP FSM in XRAM_RSP_INVAL_LOCK state" << std::endl;
+}
+#endif
+            size_t index;
+            if(m_update_tab.search_inval(r_xram_rsp_trt_buf.nline, index)){
+              r_xram_rsp_fsm = XRAM_RSP_INVAL_WAIT;
+#ifdef IDEBUG
+if(m_cpt_cycles > DEBUG_START_CYCLE){
+	std::cout << "XRAM_RSP FSM in XRAM_RSP_INVAL_LOCK state to XRAM_RSP_INVAL_WAIT state" << std::endl;
+}
+#endif
+
+            }
+	    else if(m_update_tab.is_full() && r_xram_rsp_victim_inval.read()){
+	      r_xram_rsp_fsm = XRAM_RSP_INVAL_WAIT;
+#ifdef IDEBUG
+if(m_cpt_cycles > DEBUG_START_CYCLE){
+	std::cout << "XRAM_RSP FSM in XRAM_RSP_INVAL_LOCK state to XRAM_RSP_INVAL_WAIT state" << std::endl;
+}
+#endif
+	    }
+            else {
+              r_xram_rsp_fsm = XRAM_RSP_DIR_UPDT;
+#ifdef IDEBUG
+if(m_cpt_cycles > DEBUG_START_CYCLE){
+	std::cout << "XRAM_RSP FSM in XRAM_RSP_INVAL_LOCK state to XRAM_RSP_DIR_UPDT state" << std::endl;
+}
+#endif
+            }
+          }
+          break;
+        }
+        ///////////////////////
+      case XRAM_RSP_INVAL_WAIT:
+        {
+          r_xram_rsp_fsm = XRAM_RSP_DIR_LOCK;
+          break;
+#ifdef IDEBUG
+if(m_cpt_cycles > DEBUG_START_CYCLE){
+	std::cout << "XRAM_RSP FSM in XRAM_RSP_INVAL_WAIT state" << std::endl;
+}
+#endif
+        }
+        ///////////////////////
+      case XRAM_RSP_DIR_UPDT:		// updates the cache (both data & directory)
+        {
+          // signals generation
+          bool inst_read = (r_xram_rsp_trt_buf.trdid & 0x2) && r_xram_rsp_trt_buf.proc_read; // It is an instruction read
+          bool cached_read = (r_xram_rsp_trt_buf.trdid & 0x1) && r_xram_rsp_trt_buf.proc_read ;
+          // update data
+          size_t set   = r_xram_rsp_victim_set.read();
+          size_t way   = r_xram_rsp_victim_way.read();
+          for(size_t i=0; i<m_words ; i++){
+            m_cache_data[way][set][i] = r_xram_rsp_trt_buf.wdata[i];
+          }
+          // compute dirty 
+          bool dirty = false;
+          for(size_t i=0; i<m_words;i++){
+            dirty = dirty || (r_xram_rsp_trt_buf.wdata_be[i] != 0);
+          }
+
+          // update directory
+          DirectoryEntry entry;
+          entry.valid	  = true;
+          entry.is_cnt    = false;
+          entry.lock	  = false;
+          entry.dirty	  = dirty;
+          entry.tag	    = r_xram_rsp_trt_buf.nline / m_sets;
+          if(cached_read) {
+            if(inst_read) {
+              entry.i_copies = 0x1 << r_xram_rsp_trt_buf.srcid;
+              entry.d_copies = 0x0;
+              entry.count    = 1;
+            } else {
+              entry.i_copies = 0x0;
+              entry.d_copies = 0x1 << r_xram_rsp_trt_buf.srcid;
+              entry.count    = 1;
+            }
+          } else {
+            entry.d_copies = 0;
+            entry.i_copies = 0;
+            entry.count    = 0;
+          }
+          m_cache_directory.write(set, way, entry);
+#ifdef DDEBUG
+if(m_cpt_cycles > DEBUG_START_CYCLE){
+	   std::cout << "printing the entry : " << std::endl;
+	   entry.print();
+	   std::cout << "done" << std::endl;
+}
+#endif
+
+#ifdef TDEBUG
+if(m_cpt_cycles > DEBUG_START_CYCLE){
+	std::cout << sc_time_stamp() << " " << name() << " XRAM_RSP_DIR_UPDT transaction table : " << std::endl;
+	for(size_t i = 0 ; i < m_transaction_tab.size() ; i++)
+	  m_transaction_tab.print(i);
+}
+#endif
+
+          if(r_xram_rsp_victim_inval.read()){
+            bool    brdcast = r_xram_rsp_victim_is_cnt.read();
+            size_t index;
+            size_t count_copies = r_xram_rsp_victim_count.read();
+
+            bool	 wok = m_update_tab.set(false,	// it's an inval transaction
+                brdcast,                          // set brdcast bit
+                false,  // it does not need a response
+                0,
+                0,
+                0,
+                r_xram_rsp_victim_nline.read(),
+                count_copies,
+                index);
+
+#ifdef IDEBUG
+if(m_cpt_cycles > DEBUG_START_CYCLE){
+            std::cout << "xram_rsp : record invalidation, time = " << std::dec << m_cpt_cycles << std::endl;
+            m_update_tab.print();
+}
+#endif
+            r_xram_rsp_upt_index = index;
+            if(!wok) {
+              assert(false && "mem_cache error : xram_rsp_dir_upt, an update_tab entry was free but write unsuccessful");
+            }
+          }
+          // If the victim is not dirty, we erase the entry in the TRT
+          if      (!r_xram_rsp_victim_dirty.read()){
+	  m_transaction_tab.erase(r_xram_rsp_trt_index.read());
+
+	  }
+          // Next state
+          if      ( r_xram_rsp_victim_dirty.read())       r_xram_rsp_fsm = XRAM_RSP_TRT_DIRTY;
+          else if ( r_xram_rsp_trt_buf.proc_read  )       r_xram_rsp_fsm = XRAM_RSP_DIR_RSP;
+          else if ( r_xram_rsp_victim_inval.read())       r_xram_rsp_fsm = XRAM_RSP_INVAL;
+          else                                            r_xram_rsp_fsm = XRAM_RSP_IDLE;
+          break;
+        }
+        ////////////////////////
+      case XRAM_RSP_TRT_DIRTY:		// set the TRT entry (write line to XRAM) if the victim is dirty
+        {
+          if ( r_alloc_trt_fsm.read() == ALLOC_TRT_XRAM_RSP ) {
+            m_transaction_tab.set(r_xram_rsp_trt_index.read(),
+                false,				// write to XRAM
+                r_xram_rsp_victim_nline.read(), // line index
+                0,
+                0,
+                0,
+                false,
+                0,
+                0,
+                std::vector<be_t>(m_words,0),
+                std::vector<data_t>(m_words,0) );
+#ifdef TDEBUG
+if(m_cpt_cycles > DEBUG_START_CYCLE){
+	std::cout << sc_time_stamp() << " " << name() << " XRAM_RSP_TRT_DIRTY transaction table : " << std::endl;
+	for(size_t i = 0 ; i < m_transaction_tab.size() ; i++)
+	  m_transaction_tab.print(i);
+}
+#endif
+
+            if      ( r_xram_rsp_trt_buf.proc_read  )       r_xram_rsp_fsm = XRAM_RSP_DIR_RSP;
+            else if ( r_xram_rsp_victim_inval.read())       r_xram_rsp_fsm = XRAM_RSP_INVAL;
+            else                                            r_xram_rsp_fsm = XRAM_RSP_WRITE_DIRTY;
+          }
+          break;
+        }
+        //////////////////////
+      case XRAM_RSP_DIR_RSP:     // send a request to TGT_RSP FSM in case of read
+        {
+          if ( !r_xram_rsp_to_tgt_rsp_req ) {
+            r_xram_rsp_to_tgt_rsp_srcid = r_xram_rsp_trt_buf.srcid;
+            r_xram_rsp_to_tgt_rsp_trdid = r_xram_rsp_trt_buf.trdid;
+            r_xram_rsp_to_tgt_rsp_pktid = r_xram_rsp_trt_buf.pktid;
+            for (size_t i=0; i < m_words; i++) {
+              r_xram_rsp_to_tgt_rsp_data[i] = r_xram_rsp_trt_buf.wdata[i];
+            } 
+            r_xram_rsp_to_tgt_rsp_word   = r_xram_rsp_trt_buf.word_index;
+            r_xram_rsp_to_tgt_rsp_length = r_xram_rsp_trt_buf.read_length;
+            r_xram_rsp_to_tgt_rsp_req    = true;
+
+            if      ( r_xram_rsp_victim_inval ) r_xram_rsp_fsm = XRAM_RSP_INVAL;
+            else if ( r_xram_rsp_victim_dirty ) r_xram_rsp_fsm = XRAM_RSP_WRITE_DIRTY; 
+            else                                r_xram_rsp_fsm = XRAM_RSP_IDLE;
+
+#ifdef DDEBUG
+if(m_cpt_cycles > DEBUG_START_CYCLE){
+	std::cout << "XRAM_RSP FSM in XRAM_RSP_DIR_RSP state" << std::endl;
+}
+#endif
+          }
+          break;
+        }
+        ////////////////////
+      case XRAM_RSP_INVAL:	// send invalidate request to INIT_CMD FSM
+        {
+          if( !r_xram_rsp_to_init_cmd_req ) {	      
+            r_xram_rsp_to_init_cmd_req      = true; 
+            r_xram_rsp_to_init_cmd_brdcast  = r_xram_rsp_victim_is_cnt.read();
+            r_xram_rsp_to_init_cmd_nline    = r_xram_rsp_victim_nline.read();
+            r_xram_rsp_to_init_cmd_trdid    = r_xram_rsp_upt_index;
+            r_xram_rsp_to_init_cmd_d_copies = r_xram_rsp_victim_d_copies ;
+            r_xram_rsp_to_init_cmd_i_copies = r_xram_rsp_victim_i_copies ;
+            if ( r_xram_rsp_victim_dirty )  r_xram_rsp_fsm = XRAM_RSP_WRITE_DIRTY;
+            else		                    r_xram_rsp_fsm = XRAM_RSP_IDLE;
+#ifdef DDEBUG
+if(m_cpt_cycles > DEBUG_START_CYCLE){
+	std::cout << "XRAM_RSP FSM in XRAM_RSP_INVAL state" << std::endl;
+}
+#endif
+          }
+          break;
+        }
+        //////////////////////////
+      case XRAM_RSP_WRITE_DIRTY:	// send a write request to IXR_CMD FSM
+        {
+          if ( !r_xram_rsp_to_ixr_cmd_req ) {
+            r_xram_rsp_to_ixr_cmd_req = true;
+            r_xram_rsp_to_ixr_cmd_nline = r_xram_rsp_victim_nline.read();
+            r_xram_rsp_to_ixr_cmd_trdid = r_xram_rsp_trt_index.read();
+            for(size_t i=0; i<m_words ; i++) {
+              r_xram_rsp_to_ixr_cmd_data[i] = r_xram_rsp_victim_data[i];
+            }
+            m_cpt_write_dirty++;
+            r_xram_rsp_fsm = XRAM_RSP_IDLE;
+#ifdef TDEBUG
+if(m_cpt_cycles > DEBUG_START_CYCLE){
+	std::cout << "XRAM_RSP FSM in XRAM_RSP_WRITE_DIRTY state" << std::endl;
+}
+#endif
+          }
+          break;
+        }
+    } // end swich r_xram_rsp_fsm
+
+    ////////////////////////////////////////////////////////////////////////////////////
+    //		CLEANUP FSM
+    ////////////////////////////////////////////////////////////////////////////////////
+    // The CLEANUP FSM handles the cleanup request from L1 caches.
+    // It accesses the cache directory to update the list of copies.
+    //
+    ////////////////////////////////////////////////////////////////////////////////////
+    switch ( r_cleanup_fsm.read() ) {
+
+      ///////////////////
+      case CLEANUP_IDLE:
+        {
+
+          if ( p_vci_tgt_cleanup.cmdval.read() ) {
+            assert( (p_vci_tgt_cleanup.srcid.read() < m_initiators) &&
+                "VCI_MEM_CACHE error in VCI_MEM_CACHE in the CLEANUP network : The received SRCID is larger than 31");
+            bool reached = false;
+            for ( size_t index = 0 ; index < ncseg && !reached ; index++ ){
+              if ( m_cseg[index]->contains((addr_t)(p_vci_tgt_cleanup.address.read())) ){
+                reached = true;
+              }
+            }
+            if ( (p_vci_tgt_cleanup.cmd.read() == vci_param::CMD_WRITE) &&
+                (((addr_t)(p_vci_tgt_cleanup.address.read())&0x3) != 0x3) &&
+                reached) {
+
+              m_cpt_cleanup++;
+
+              r_cleanup_nline      = (addr_t)(m_nline[(vci_addr_t)(p_vci_tgt_cleanup.address.read())]) ;
+              r_cleanup_srcid      = p_vci_tgt_cleanup.srcid.read();
+              r_cleanup_trdid      = p_vci_tgt_cleanup.trdid.read();
+              r_cleanup_pktid      = p_vci_tgt_cleanup.pktid.read();
+
+              r_cleanup_fsm        = CLEANUP_DIR_LOCK;
+            }
+          }
+          break;
+        }
+        //////////////////////
+      case CLEANUP_DIR_LOCK:
+        {
+          if ( r_alloc_dir_fsm.read() == ALLOC_DIR_CLEANUP ) {
+
+            // Read the directory
+            size_t way = 0;
+	   addr_t cleanup_address = r_cleanup_nline.read() * m_words * 4;
+           DirectoryEntry entry = m_cache_directory.read(cleanup_address , way);
+#ifdef DDEBUG
+if(m_cpt_cycles > DEBUG_START_CYCLE){
+	   std::cout << "In CLEANUP_DIR_LOCK printing the entry of address is : " << std::hex << cleanup_address << std::endl;
+	   entry.print();
+	   std::cout << "done" << std::endl;
+}
+#endif
+            r_cleanup_is_cnt    = entry.is_cnt;
+            r_cleanup_dirty	    = entry.dirty;
+            r_cleanup_tag	    = entry.tag;
+            r_cleanup_lock	    = entry.lock;
+            r_cleanup_way	    = way;
+            r_cleanup_d_copies  = entry.d_copies;
+            r_cleanup_i_copies  = entry.i_copies;
+            r_cleanup_count     = entry.count;
+
+            // In case of hit, the copy must be cleaned in the copies bit-vector
+            if( entry.valid )  { 
+              r_cleanup_fsm = CLEANUP_DIR_WRITE;
+            } else {
+              r_cleanup_fsm = CLEANUP_UPT_LOCK;
+            }
+          }
+          break;
+        }
+        ///////////////////////
+      case CLEANUP_DIR_WRITE:
+        {
+          size_t way      = r_cleanup_way.read();
+#define L2 soclib::common::uint32_log2
+          size_t set      = m_y[(vci_addr_t)(r_cleanup_nline.read() << (L2(m_words) +2))];
+#undef L2
+          bool cleanup_inst  = r_cleanup_trdid.read() & 0x1; 
+
+          // update the cache directory (for the copies)
+          DirectoryEntry entry;
+          entry.valid	= true;
+          entry.is_cnt  = r_cleanup_is_cnt.read();
+          entry.dirty	= r_cleanup_dirty.read();
+          entry.tag	= r_cleanup_tag.read();
+          entry.lock	= r_cleanup_lock.read();
+          if(r_cleanup_is_cnt.read()) { // Directory is a counter
+            entry.count  = r_cleanup_count.read() -1;
+            entry.i_copies = 0;
+            entry.d_copies = 0;
+            // response to the cache 
+            r_cleanup_fsm = CLEANUP_RSP;
+          }
+          else{                         // Directory is a vector
+            if(cleanup_inst){           // Cleanup from a ICACHE
+              if(r_cleanup_i_copies.read() & (0x1 << r_cleanup_srcid.read())){ // hit
+                entry.count  = r_cleanup_count.read() -1;
+                r_cleanup_fsm = CLEANUP_RSP;
+              } else { // miss
+                assert(false && "MemCache ERROR : Cleanup instruction hit but the line is not shared");
+              }
+              entry.i_copies  = r_cleanup_i_copies.read() & ~(0x1 << r_cleanup_srcid.read());
+              entry.d_copies  = r_cleanup_d_copies.read();
+            } else {                    // Cleanup from a DCACHE
+              if(r_cleanup_d_copies.read() & (0x1 << r_cleanup_srcid.read())){ // hit
+                entry.count  = r_cleanup_count.read() -1;
+                r_cleanup_fsm = CLEANUP_RSP; 
+              } else { // miss
+                assert(false && "MemCache ERROR : Cleanup data hit but the line is not shared");
+              }
+              entry.i_copies  = r_cleanup_i_copies.read();
+              entry.d_copies  = r_cleanup_d_copies.read() & ~(0x1 << r_cleanup_srcid.read());
+            }
+          }
+          m_cache_directory.write(set, way, entry);  
+
+          // response to the cache      
+//          r_cleanup_fsm = CLEANUP_RSP;
+
+          break;
+        }
+        /////////////////
+      case CLEANUP_UPT_LOCK:
+        {
+          if( r_alloc_upt_fsm.read() == ALLOC_UPT_CLEANUP )
+          {
+            size_t index = 0;
+            bool hit_inval;
+            hit_inval = m_update_tab.search_inval(r_cleanup_nline.read(),index);
+            if(!hit_inval) {
+#ifdef DEBUG_VCI_MEM_CACHE
+if(m_cpt_cycles > DEBUG_START_CYCLE){
+              std::cout << "MEM_CACHE WARNING: cleanup with no corresponding entry at address : " << std::hex << (r_cleanup_nline.read()*4*m_words) << std::dec << std::endl;
+}
+#endif
+              r_cleanup_fsm = CLEANUP_RSP;
+            } else {
+              r_cleanup_write_srcid = m_update_tab.srcid(index);
+              r_cleanup_write_trdid = m_update_tab.trdid(index);
+              r_cleanup_write_pktid = m_update_tab.pktid(index);
+              r_cleanup_need_rsp    = m_update_tab.need_rsp(index);
+              r_cleanup_fsm = CLEANUP_UPT_WRITE;
+            }
+            r_cleanup_index.write(index) ; 
+          }
+          break;
+        }
+        /////////////////
+      case CLEANUP_UPT_WRITE:
+        {
+          size_t count = 0;
+          m_update_tab.decrement(r_cleanup_index.read(), count); // &count
+          if(count == 0){
+            m_update_tab.clear(r_cleanup_index.read());
+#ifdef IDEBUG
+if(m_cpt_cycles > DEBUG_START_CYCLE){
+	std::cout << sc_time_stamp() << " " << name() << " CLEANUP_UPT_WRITE update table : " << std::endl;
+	m_update_tab.print();
+}
+#endif
+
+            if(r_cleanup_need_rsp.read()){
+              r_cleanup_fsm = CLEANUP_WRITE_RSP ;
+            } else {
+              r_cleanup_fsm = CLEANUP_RSP;
+            }
+          } else {
+            r_cleanup_fsm = CLEANUP_RSP ;
+          }
+          break;
+        }
+        /////////////////
+      case CLEANUP_WRITE_RSP:
+        {
+          if( !r_cleanup_to_tgt_rsp_req.read()) {
+            r_cleanup_to_tgt_rsp_req     = true;
+            r_cleanup_to_tgt_rsp_srcid   = r_cleanup_write_srcid.read();
+            r_cleanup_to_tgt_rsp_trdid   = r_cleanup_write_trdid.read();
+            r_cleanup_to_tgt_rsp_pktid   = r_cleanup_write_pktid.read();
+            r_cleanup_fsm = CLEANUP_RSP;
+          }
+          break;
+        }
+        /////////////////
+      case CLEANUP_RSP:
+        {
+          if(p_vci_tgt_cleanup.rspack)
+            r_cleanup_fsm = CLEANUP_IDLE;
+          break;
+        }
+    } // end switch cleanup fsm
+
+
+    ////////////////////////////////////////////////////////////////////////////////////
+    //		LLSC FSM
+    ////////////////////////////////////////////////////////////////////////////////////
+    // The LLSC FSM handles the LL & SC atomic access.
+    //
+    // For a LL :
+    // It access the directory to check hit / miss.
+    // - In case of hit, the LL request is registered in the Atomic Table and the
+    // response is sent to the requesting processor.
+    // - In case of miss, the LLSC FSM accesses the transaction table. 
+    // If a read transaction to the XRAM for this line already exists, 
+    // or if the transaction table is full, it returns to IDLE state.
+    // Otherwise, a new transaction to the XRAM is initiated.
+    // In both cases, the LL request is not consumed in the FIFO.
+    //
+    // For a SC :
+    // It access the directory to check hit / miss.
+    // - In case of hit, the Atomic Table is checked and the proper response
+    // (true or false is sent to the requesting processor.
+    // - In case of miss, the LLSC FSM accesses the transaction table. 
+    // If a read transaction to the XRAM for this line already exists, 
+    // or if the transaction table is full, it returns to IDLE state. 
+    // Otherwise, a new transaction to the XRAM is initiated.
+    // In both cases, the SC request is not consumed in the FIFO.
+    /////////////////////////////////////////////////////////////////////
+
+    switch ( r_llsc_fsm.read() ) {
+
+      ///////////////
+      case LLSC_IDLE:		// test LL / SC
+        {
+          if( m_cmd_llsc_addr_fifo.rok() ) {
+            if(m_cmd_llsc_sc_fifo.read()){
+              m_cpt_sc++;
+              r_llsc_fsm = SC_DIR_LOCK;
+            }
+            else{
+              m_cpt_ll++;
+              r_llsc_fsm = LL_DIR_LOCK;
+            }
+          }	
+          break;
+        }
+        /////////////////
+      case LL_DIR_LOCK:		// check directory for hit / miss
+        {
+          if( r_alloc_dir_fsm.read() == ALLOC_DIR_LLSC ) {
+            size_t way = 0;
+            DirectoryEntry entry(m_cache_directory.read(m_cmd_llsc_addr_fifo.read(), way));
+            r_llsc_is_cnt     = entry.is_cnt;
+            r_llsc_dirty      = entry.dirty;
+            r_llsc_tag        = entry.tag;
+            r_llsc_way        = way;
+            r_llsc_d_copies   = entry.d_copies;
+            r_llsc_i_copies   = entry.i_copies ;
+            r_llsc_count      = entry.count ;
+
+            // set Atomic Table
+            m_atomic_tab.set(m_cmd_llsc_srcid_fifo.read(), m_cmd_llsc_addr_fifo.read());
+
+#ifdef DDEBUG
+if(m_cpt_cycles > DEBUG_START_CYCLE){
+	   std::cout << "In LLSC_DIR_LOCK printing the entry of address is : " << std::hex << m_cmd_llsc_addr_fifo.read() << std::endl;
+	   entry.print();
+	   std::cout << "done" << std::endl;
+}
+#endif
+
+
+            if ( entry.valid )  r_llsc_fsm = LL_DIR_HIT;
+            else                r_llsc_fsm = LLSC_TRT_LOCK;
+          }
+          break;
+        }
+        ////////////////
+      case LL_DIR_HIT:		// read hit : update the memory cache
+        {
+          size_t way	= r_llsc_way.read();
+          size_t set	= m_y[(vci_addr_t)(m_cmd_llsc_addr_fifo.read())];
+          size_t word	= m_x[(vci_addr_t)(m_cmd_llsc_addr_fifo.read())];
+
+          // update directory (lock bit & copies)
+          DirectoryEntry entry;
+          entry.valid	    = true;
+          entry.is_cnt      = r_llsc_is_cnt.read();
+          entry.dirty	    = r_llsc_dirty.read();
+          entry.lock	    = true;
+          entry.tag	        = r_llsc_tag.read();
+          entry.d_copies    = r_llsc_d_copies.read();
+          entry.i_copies    = r_llsc_i_copies.read();
+          entry.count       = r_llsc_count.read();
+          m_cache_directory.write(set, way, entry);
+
+          // read data in cache
+          r_llsc_data	= m_cache_data[way][set][word];
+
+          r_llsc_fsm 	= LL_RSP;
+          break;
+        }
+        ////////////
+      case LL_RSP:		// request the TGT_RSP FSM to return data
+        {
+          if ( !r_llsc_to_tgt_rsp_req ) {
+            cmd_llsc_fifo_get		= true;
+            r_llsc_to_tgt_rsp_data	= r_llsc_data.read();
+            r_llsc_to_tgt_rsp_srcid	= m_cmd_llsc_srcid_fifo.read();
+            r_llsc_to_tgt_rsp_trdid	= m_cmd_llsc_trdid_fifo.read();
+            r_llsc_to_tgt_rsp_pktid	= m_cmd_llsc_pktid_fifo.read();
+            r_llsc_to_tgt_rsp_req	= true;
+            r_llsc_fsm = LLSC_IDLE;
+          }
+          break;
+        }
+        /////////////////
+      case SC_DIR_LOCK:
+        {
+          if( r_alloc_dir_fsm.read() == ALLOC_DIR_LLSC ) {
+            size_t way = 0;
+            DirectoryEntry entry(m_cache_directory.read(m_cmd_llsc_addr_fifo.read(), way));
+            bool ok = m_atomic_tab.isatomic(m_cmd_llsc_srcid_fifo.read(),m_cmd_llsc_addr_fifo.read());
+            if( ok ) {
+              r_llsc_is_cnt   = entry.is_cnt;
+              r_llsc_dirty    = entry.dirty;
+              r_llsc_tag      = entry.tag;
+              r_llsc_way      = way;
+              r_llsc_d_copies = entry.d_copies;
+              r_llsc_i_copies = entry.i_copies;
+              r_llsc_count    = entry.count;
+              /* to avoid livelock, force the atomic access to fail (pseudo-)randomly */
+              bool fail = (r_llsc_lfsr % (64) == 0);
+              r_llsc_lfsr = (r_llsc_lfsr >> 1) ^ ((-(r_llsc_lfsr & 1)) & 0xd0000001);
+#ifdef RANDOMIZE_SC
+              if(fail){
+#else
+              if(0){
+#endif
+                r_llsc_fsm = SC_RSP_FALSE;
+              } else {
+                  if ( entry.valid ){
+                      if((entry.is_cnt && entry.count) || entry.i_copies) {
+                          r_llsc_fsm = SC_TRT_LOCK;
+                      } else {
+                          r_llsc_fsm = SC_DIR_HIT;
+                      }
+                  }
+                  else r_llsc_fsm = LLSC_TRT_LOCK;
+              }
+            } else {
+              r_llsc_fsm = SC_RSP_FALSE;
+            }
+          }
+          break;
+        }
+        ////////////////
+      case SC_DIR_HIT:
+        {
+          size_t way	= r_llsc_way.read();
+          size_t set	= m_y[(vci_addr_t)(m_cmd_llsc_addr_fifo.read())]; 
+          size_t word	= m_x[(vci_addr_t)(m_cmd_llsc_addr_fifo.read())]; 
+
+          // update directory (lock & dirty bits
+          DirectoryEntry entry;
+          entry.valid	    = true;
+          entry.is_cnt      = r_llsc_is_cnt.read();
+          entry.dirty	    = true;
+          entry.lock	    = true;
+          entry.tag	        = r_llsc_tag.read();
+          entry.d_copies    = r_llsc_d_copies.read();
+          entry.i_copies    = r_llsc_i_copies.read();
+          entry.count       = r_llsc_count.read();
+          m_cache_directory.write(set, way, entry);
+
+
+          // write data in cache
+          m_cache_data[way][set][word] = m_cmd_llsc_wdata_fifo.read();
+
+          // reset Atomic Table
+          m_atomic_tab.reset(m_cmd_llsc_addr_fifo.read());
+          
+          if(r_llsc_count.read()) {  // Shared line
+            r_llsc_fsm = SC_UPT_LOCK;
+          } else {
+            r_llsc_fsm = SC_RSP_TRUE;
+          }
+          break;
+        }
+        /////////////////////
+      case SC_UPT_LOCK: 	// Try to register the request in Update Table
+        {
+
+          if ( r_alloc_upt_fsm.read() == ALLOC_UPT_LLSC ) {
+            bool        wok        = false;
+            size_t      index      = 0;
+            size_t      srcid      = m_cmd_llsc_srcid_fifo.read();
+            size_t      trdid      = m_cmd_llsc_trdid_fifo.read();
+            size_t      pktid      = m_cmd_llsc_pktid_fifo.read();
+            addr_t	    nline      = m_nline[(vci_addr_t)(m_cmd_llsc_addr_fifo.read())];
+            size_t      nb_copies  = r_llsc_count.read();
+
+            wok =m_update_tab.set(true,	// it's an update transaction
+                false,                  // it's not a broadcast
+                true,                   // it needs a response
+                srcid,
+                trdid,
+                pktid,
+                nline,
+                nb_copies,
+                index);
+#ifdef IDEBUG
+if(m_cpt_cycles > DEBUG_START_CYCLE){
+            if(wok){
+	std::cout << sc_time_stamp() << " " << name() << " SC_UPT_LOCK update table : " << std::endl;
+	m_update_tab.print();
+            }
+}
+#endif
+            r_llsc_upt_index = index;
+            //  releases the lock protecting Update Table if no entry...
+            if ( wok ) r_llsc_fsm = SC_UPDATE;
+            else       r_llsc_fsm = SC_WAIT_UPT;
+          }
+          break;
+        }
+        ////////////////////
+      case SC_WAIT_UPT: 	// release the lock protecting UPT
+        {
+          r_llsc_fsm = SC_UPT_LOCK;
+          break;
+        }
+        //////////////////
+      case SC_UPDATE:   	// send a multi-update request to INIT_CMD fsm
+        {
+
+          if ( !r_llsc_to_init_cmd_req ) {
+            r_llsc_to_init_cmd_req      = true;
+            r_llsc_to_init_cmd_brdcast  = false;
+            r_llsc_to_init_cmd_trdid    = r_llsc_upt_index.read();
+            r_llsc_to_init_cmd_nline    = m_nline[(vci_addr_t)(m_cmd_llsc_addr_fifo.read())];
+            r_llsc_to_init_cmd_index    = m_x[(vci_addr_t)(m_cmd_llsc_addr_fifo.read())];
+            r_llsc_to_init_cmd_wdata    = m_cmd_llsc_wdata_fifo.read();
+            r_llsc_to_init_cmd_d_copies = r_llsc_d_copies.read();
+            
+            cmd_llsc_fifo_get         = true;
+
+            r_llsc_fsm = LLSC_IDLE; // Response will be sent after receiving
+            // all update responses
+          }
+          break;
+        }
+
+        //////////////////
+      case SC_TRT_LOCK:
+        {
+          if( r_alloc_trt_fsm.read() == ALLOC_TRT_LLSC ) {
+            if( !r_llsc_to_ixr_cmd_req ) { // we can transfer the data to the buffer
+              size_t way	= r_llsc_way.read();
+              size_t set	= m_y[(vci_addr_t)(m_cmd_llsc_addr_fifo.read())];
+              for(size_t i = 0; i<m_words; i++){
+                if(i==m_x[(vci_addr_t)m_cmd_llsc_addr_fifo.read()]) {
+                  r_llsc_to_ixr_cmd_data[i] = m_cmd_llsc_wdata_fifo.read();
+                } else {
+                  r_llsc_to_ixr_cmd_data[i] = m_cache_data[way][set][i];
+                }
+              }
+              size_t wok_index = 0;
+              bool wok = !m_transaction_tab.full(wok_index);
+              if ( wok ) { // set a new entry in TRT
+                r_llsc_trt_index = wok_index;
+                r_llsc_fsm       = SC_INVAL_LOCK; 
+              } else {
+                r_llsc_fsm       = LLSC_IDLE;
+              }
+            } else {
+              r_llsc_fsm = LLSC_IDLE;
+            }
+          }
+          break;
+        }
+        //////////////////
+      case SC_INVAL_LOCK:
+        {
+          if ( r_alloc_upt_fsm.read() == ALLOC_UPT_LLSC ) {
+            bool        wok       = false;
+            size_t      index     = 0;
+            size_t      srcid     = m_cmd_llsc_srcid_fifo.read();
+            size_t      trdid     = m_cmd_llsc_trdid_fifo.read();
+            size_t      pktid     = m_cmd_llsc_pktid_fifo.read();
+            addr_t	    nline     = m_nline[(vci_addr_t)(m_cmd_llsc_addr_fifo.read())];
+            size_t      nb_copies = r_llsc_count.read();
+
+            wok =m_update_tab.set(false,	// it's an inval transaction
+                true,                       // it's a broadcast
+                true,                       // it needs a response
+                srcid,
+                trdid,
+                pktid,
+                nline,
+                nb_copies,
+                index);
+#ifdef IDEBUG
+if(m_cpt_cycles > DEBUG_START_CYCLE){
+            if(wok){
+	std::cout << sc_time_stamp() << " " << name() << " LLSC_INVAL_LOCK update table : " << std::endl;
+	m_update_tab.print();
+            }
+}
+#endif
+            r_llsc_upt_index = index;
+            //  releases the lock protecting Update Table if no entry...
+            if ( wok ) r_llsc_fsm = SC_DIR_INVAL;
+            else       r_llsc_fsm = LLSC_IDLE;
+          }
+          break;
+        }
+        //////////////////
+      case SC_DIR_INVAL:
+        {
+          if ( (r_alloc_trt_fsm.read() == ALLOC_TRT_LLSC ) &&
+              (r_alloc_upt_fsm.read() == ALLOC_UPT_LLSC ) )
+          {
+            m_transaction_tab.set(r_llsc_trt_index.read(),
+                false,				// write request to XRAM
+                m_nline[(vci_addr_t)(m_cmd_llsc_addr_fifo.read())],
+                0,
+                0,
+                0,
+                false,				// not a processor read
+                0,  				// not a single word 
+                0,		        	// word index
+                std::vector<be_t>(m_words,0),
+                std::vector<data_t>(m_words,0));
+#ifdef TDEBUG
+if(m_cpt_cycles > DEBUG_START_CYCLE){
+	std::cout << sc_time_stamp() << " " << name() << " SC_DIR_INVAL transaction table : " << std::endl;
+	for(size_t i = 0 ; i < m_transaction_tab.size() ; i++)
+	  m_transaction_tab.print(i);
+}
+#endif
+            // reset Atomic Table
+            m_atomic_tab.reset(m_cmd_llsc_addr_fifo.read());
+
+            // invalidate directory entry
+            DirectoryEntry entry;
+            entry.valid	   = false;
+            entry.dirty	   = false;
+            entry.tag	   = 0;
+            entry.is_cnt   = false;
+            entry.lock	   = false;
+            entry.d_copies = 0;
+            entry.i_copies = 0;
+            entry.count    = 0;
+            size_t set	   = m_y[(vci_addr_t)(m_cmd_llsc_addr_fifo.read())];
+            size_t way	   = r_llsc_way.read();
+            m_cache_directory.write(set, way, entry);
+
+            r_llsc_fsm = SC_INVAL;
+          } else {
+            assert(false && "LOCK ERROR in LLSC_FSM, STATE = LLSC_DIR_INVAL");
+          }
+
+          break;
+
+        }
+        //////////////////
+      case SC_INVAL:
+        {
+          if ( !r_llsc_to_init_cmd_req ) {
+            r_llsc_to_init_cmd_req      = true;
+            r_llsc_to_init_cmd_brdcast  = true;
+            r_llsc_to_init_cmd_trdid    = r_llsc_upt_index.read();
+            r_llsc_to_init_cmd_nline    = m_nline[(vci_addr_t)(m_cmd_llsc_addr_fifo.read())];
+            r_llsc_to_init_cmd_index    = 0;
+            r_llsc_to_init_cmd_d_copies = 0;
+            r_llsc_to_init_cmd_wdata    = 0;
+
+            r_llsc_fsm = SC_XRAM_SEND;
+            // all update responses
+          }
+
+          break;
+        }
+        //////////////////
+      case SC_XRAM_SEND:
+        {
+          if ( !r_llsc_to_ixr_cmd_req ) {
+            r_llsc_to_ixr_cmd_req     = true;
+            r_llsc_to_ixr_cmd_write   = true;
+            r_llsc_to_ixr_cmd_nline   = m_nline[(vci_addr_t)(m_cmd_llsc_addr_fifo.read())];
+            r_llsc_to_ixr_cmd_trdid   = r_llsc_trt_index.read();
+            r_llsc_fsm                = LLSC_IDLE;
+            cmd_llsc_fifo_get         = true;
+          } else {
+            assert( false && "MEM_CACHE, LLSC FSM : SC_XRAM_SEND state : the request should not have been previously set");
+          }
+          break;
+
+        }
+        //////////////////
+      case SC_RSP_FALSE:
+        {
+          if( !r_llsc_to_tgt_rsp_req ) {
+            cmd_llsc_fifo_get		= true;
+            r_llsc_to_tgt_rsp_req	= true;
+            r_llsc_to_tgt_rsp_data	= 1;
+            r_llsc_to_tgt_rsp_srcid	= m_cmd_llsc_srcid_fifo.read();
+            r_llsc_to_tgt_rsp_trdid	= m_cmd_llsc_trdid_fifo.read();
+            r_llsc_to_tgt_rsp_pktid	= m_cmd_llsc_pktid_fifo.read();
+            r_llsc_fsm 			    = LLSC_IDLE;
+          }
+          break;
+        }
+        /////////////////
+      case SC_RSP_TRUE:
+        {
+          if( !r_llsc_to_tgt_rsp_req ) {
+            cmd_llsc_fifo_get	    = true;
+            r_llsc_to_tgt_rsp_req	= true;
+            r_llsc_to_tgt_rsp_data	= 0;
+            r_llsc_to_tgt_rsp_srcid	= m_cmd_llsc_srcid_fifo.read();
+            r_llsc_to_tgt_rsp_trdid	= m_cmd_llsc_trdid_fifo.read();
+            r_llsc_to_tgt_rsp_pktid	= m_cmd_llsc_pktid_fifo.read();
+            r_llsc_fsm 			    = LLSC_IDLE;
+          }
+          break;
+        }
+        ///////////////////
+      case LLSC_TRT_LOCK:         // read or write miss : check the Transaction Table
+        {
+          if( r_alloc_trt_fsm.read() == ALLOC_TRT_LLSC ) {
+            size_t   index = 0;
+            bool hit_read = m_transaction_tab.hit_read(m_nline[(vci_addr_t)m_cmd_llsc_addr_fifo.read()],index);
+            bool hit_write = m_transaction_tab.hit_write(m_nline[(vci_addr_t)m_cmd_llsc_addr_fifo.read()]);
+            bool wok = !m_transaction_tab.full(index);
+
+            if ( hit_read || !wok || hit_write ) {  // missing line already requested or no space in TRT
+              r_llsc_fsm = LLSC_IDLE;
+            } else {
+              r_llsc_trt_index = index;
+              r_llsc_fsm       = LLSC_TRT_SET;
+            }
+          }
+          break;
+        }
+        //////////////////
+      case LLSC_TRT_SET:	// register the XRAM transaction in Transaction Table
+        {
+          if( r_alloc_trt_fsm.read() == ALLOC_TRT_LLSC ) {
+            size_t word	= m_x[(vci_addr_t)(m_cmd_llsc_addr_fifo.read())]; 
+            bool proc_read = !m_cmd_llsc_sc_fifo.read();
+            if(proc_read){
+              m_transaction_tab.set(r_llsc_trt_index.read(),
+                  true,
+                  m_nline[(vci_addr_t)m_cmd_llsc_addr_fifo.read()],
+                  m_cmd_llsc_srcid_fifo.read(),
+                  m_cmd_llsc_trdid_fifo.read(),
+                  m_cmd_llsc_pktid_fifo.read(),
+                  true,
+                  1,
+                  word,
+                  std::vector<be_t>(m_words,0),
+                  std::vector<data_t>(m_words,0));
+            }else{
+              std::vector<be_t> be_vector;
+              std::vector<data_t> data_vector;
+              be_vector.clear();
+              data_vector.clear();
+              // reset Atomic Table
+              m_atomic_tab.reset(m_cmd_llsc_addr_fifo.read());
+              for ( size_t i=0; i<m_words; i++ ) 
+              {   
+                if(i == word){
+                  be_vector.push_back(0xF);
+                  data_vector.push_back(m_cmd_llsc_wdata_fifo.read());
+                } else {
+                  be_vector.push_back(0);
+                  data_vector.push_back(0);
+                }
+              }
+ 
+              m_transaction_tab.set(r_llsc_trt_index.read(),
+                  true,
+                  m_nline[(vci_addr_t)m_cmd_llsc_addr_fifo.read()],
+                  m_cmd_llsc_srcid_fifo.read(),
+                  m_cmd_llsc_trdid_fifo.read(),
+                  m_cmd_llsc_pktid_fifo.read(),
+                  false,
+                  0,
+                  0,
+                  be_vector,
+                  data_vector);
+            }
+#ifdef TDEBUG
+if(m_cpt_cycles > DEBUG_START_CYCLE){
+	std::cout << sc_time_stamp() << " " << name() << " LLSC_TRT_SET transaction table : " << std::endl;
+	for(size_t i = 0 ; i < m_transaction_tab.size() ; i++)
+	  m_transaction_tab.print(i);
+}
+#endif
+
+            r_llsc_fsm = LLSC_XRAM_REQ;
+          }
+          break;
+        }
+        ///////////////////
+      case LLSC_XRAM_REQ:	// request the IXR_CMD FSM to fetch the missing line
+        {
+          if ( !r_llsc_to_ixr_cmd_req ) {
+            r_llsc_to_ixr_cmd_req        = true;
+            r_llsc_to_ixr_cmd_write      = false;
+            r_llsc_to_ixr_cmd_trdid      = r_llsc_trt_index.read();
+            r_llsc_to_ixr_cmd_nline      = m_nline[(vci_addr_t)m_cmd_llsc_addr_fifo.read()];
+            if( m_cmd_llsc_sc_fifo.read() ) {
+              r_llsc_fsm                 = SC_RSP_TRUE;
+            } else {
+              cmd_llsc_fifo_get          = true;
+              r_llsc_fsm                 = LLSC_IDLE;
+            }
+          }
+          break;
+        }
+    } // end switch r_llsc_fsm
+
+
+    //////////////////////////////////////////////////////////////////////////////
+    //		INIT_CMD FSM
+    //////////////////////////////////////////////////////////////////////////////
+    // The INIT_CMD fsm controls the VCI CMD initiator port, used to update
+    // or invalidate cache lines in L1 caches.
+    // It implements a round-robin priority between the two following requests:
+    // - r_write_to_init_cmd_req : update request from WRITE FSM 
+    // - r_xram_rsp_to_init_cmd_req : invalidate request from XRAM_RSP FSM 
+    // The inval request is a single cell VCI write command containing the 
+    // index of the line to be invalidated.
+    // The update request is a multi-cells VCI write command : The first cell 
+    // contains the index of the cache line to be updated. The second cell contains 
+    // the index of the first modified word in the line. The following cells
+    // contain the data.
+    ///////////////////////////////////////////////////////////////////////////////
+
+    switch ( r_init_cmd_fsm.read() ) {
+
+      //////////////////////// 
+      case INIT_CMD_UPDT_IDLE:	// Invalidate requests have highest priority
+        {
+
+          if ( r_xram_rsp_to_init_cmd_req.read() ) {
+            r_init_cmd_fsm = INIT_CMD_INVAL_SEL;
+            m_cpt_inval++;
+          } else if ( r_write_to_init_cmd_req.read() ) {
+            if(r_write_to_init_cmd_brdcast.read()){
+              r_init_cmd_fsm = INIT_CMD_BRDCAST;
+              m_cpt_inval++;
+              m_cpt_inval_brdcast++;
+            } else {
+              r_init_cmd_fsm = INIT_CMD_UPDT_SEL;
+              m_cpt_update++;
+            }
+          } else if (r_llsc_to_init_cmd_req.read() ) {
+            if(r_llsc_to_init_cmd_brdcast.read()){
+              r_init_cmd_fsm = INIT_CMD_SC_BRDCAST;
+              m_cpt_inval++;
+              m_cpt_inval_brdcast++;
+            } else {
+              r_init_cmd_fsm = INIT_CMD_SC_UPDT_SEL;
+              m_cpt_update++;
+            }
+          }
+          break;
+        }
+        /////////////////////////
+      case INIT_CMD_INVAL_IDLE:	// Update requests have highest priority
+        {
+          if ( r_write_to_init_cmd_req.read() ) {
+            if(r_write_to_init_cmd_brdcast.read()){
+              r_init_cmd_fsm = INIT_CMD_BRDCAST;
+              m_cpt_inval++;
+              m_cpt_inval_brdcast++;
+            } else {
+              r_init_cmd_fsm = INIT_CMD_UPDT_SEL;
+              m_cpt_update++;
+            }
+          } else if (r_llsc_to_init_cmd_req.read() ) {
+            if(r_llsc_to_init_cmd_brdcast.read()){
+              r_init_cmd_fsm = INIT_CMD_SC_BRDCAST;
+              m_cpt_inval++;
+              m_cpt_inval_brdcast++;
+            } else {
+              r_init_cmd_fsm = INIT_CMD_SC_UPDT_SEL;
+              m_cpt_update++;
+            }
+          } else if ( r_xram_rsp_to_init_cmd_req.read() ) {
+            r_init_cmd_fsm = INIT_CMD_INVAL_SEL;
+            m_cpt_inval++;
+          }
+          break;
+        }
+        /////////////////////////
+      case INIT_CMD_SC_UPDT_IDLE:	// Update requests for SCs have highest priority
+        {
+          if (r_llsc_to_init_cmd_req.read() ) {
+            if(r_llsc_to_init_cmd_brdcast.read()){
+              r_init_cmd_fsm = INIT_CMD_SC_BRDCAST;
+              m_cpt_inval++;
+              m_cpt_inval_brdcast++;
+            } else {
+              r_init_cmd_fsm = INIT_CMD_SC_UPDT_SEL;
+              m_cpt_update++;
+            }
+          } else if ( r_xram_rsp_to_init_cmd_req.read() ) {
+            r_init_cmd_fsm = INIT_CMD_INVAL_SEL;
+            m_cpt_inval++;
+          } else if ( r_write_to_init_cmd_req.read() ) {
+            if(r_write_to_init_cmd_brdcast.read()){
+              r_init_cmd_fsm = INIT_CMD_BRDCAST;
+              m_cpt_inval++;
+              m_cpt_inval_brdcast++;
+            } else {
+              r_init_cmd_fsm = INIT_CMD_UPDT_SEL;
+              m_cpt_update++;
+            }
+          }
+          break;
+        }
+
+        ////////////////////////
+      case INIT_CMD_INVAL_SEL:	// selects L1 caches
+        {
+          if(r_xram_rsp_to_init_cmd_brdcast.read()){
+            m_cpt_inval_brdcast++;
+            r_init_cmd_fsm = INIT_CMD_INVAL_NLINE;
+            break;
+          }
+          if ((r_xram_rsp_to_init_cmd_d_copies.read() == 0) &&
+              (r_xram_rsp_to_init_cmd_i_copies.read() == 0)) {	// no more copies
+            r_xram_rsp_to_init_cmd_req = false;
+            r_init_cmd_fsm = INIT_CMD_INVAL_IDLE;
+            break;
+          }
+          m_cpt_inval_mult++;
+          copy_t copies;
+          bool inst = false;
+          if(r_xram_rsp_to_init_cmd_i_copies.read()){
+            copies = r_xram_rsp_to_init_cmd_i_copies.read();
+            inst = true;
+          } else {
+            copies = r_xram_rsp_to_init_cmd_d_copies.read();
+          }
+          copy_t mask   = 0x1;
+          for ( size_t i=0 ; i<8*sizeof(copy_t) ; i++ ) {
+            if ( copies & mask ) {
+              r_init_cmd_target = i;
+              break;
+            }
+            mask = mask << 1;
+          } // end for 
+          r_init_cmd_fsm = INIT_CMD_INVAL_NLINE;
+          r_init_cmd_inst = inst;
+          if(inst){
+            r_xram_rsp_to_init_cmd_i_copies = copies & ~mask;
+          } else {
+            r_xram_rsp_to_init_cmd_d_copies = copies & ~mask;
+          }
+          break;
+        }
+        ////////////////////////
+      case INIT_CMD_INVAL_NLINE:	// send the cache line index
+        {
+          if ( p_vci_ini.cmdack ) {
+            if ( r_xram_rsp_to_init_cmd_brdcast.read() ) {
+              r_init_cmd_fsm = INIT_CMD_INVAL_IDLE;
+              r_xram_rsp_to_init_cmd_req = false;
+            }
+            else r_init_cmd_fsm = INIT_CMD_INVAL_SEL;
+          }
+          break;
+        }
+        ///////////////////////
+      case INIT_CMD_UPDT_SEL:	// selects the next L1 cache
+        {
+          if (r_write_to_init_cmd_d_copies.read() == 0) {	// no more copies
+            r_write_to_init_cmd_req = false;
+            r_init_cmd_fsm    = INIT_CMD_UPDT_IDLE;
+          } else {						// select the first target
+            copy_t copies;
+            copies = r_write_to_init_cmd_d_copies.read();
+            copy_t mask   = 0x1;
+            for ( size_t i=0 ; i<8*sizeof(copy_t) ; i++ ) {
+              if ( copies & mask ) {
+                r_init_cmd_target = i;
+                break;
+              }
+              mask = mask << 1;
+            } // end for 
+            r_init_cmd_fsm    = INIT_CMD_UPDT_NLINE;
+            r_write_to_init_cmd_d_copies = copies & ~mask;
+            r_init_cmd_cpt    = 0;
+            m_cpt_update_mult++;
+          }
+          break;
+        }
+        /////////////////////////
+      case INIT_CMD_BRDCAST:
+        {
+          if( p_vci_ini.cmdack ) {
+            r_write_to_init_cmd_req = false;
+            r_init_cmd_fsm = INIT_CMD_UPDT_IDLE;
+          }
+          break;
+        }
+        /////////////////////////
+      case INIT_CMD_UPDT_NLINE:	// send the cache line index
+        {
+          if ( p_vci_ini.cmdack ){
+            r_init_cmd_fsm = INIT_CMD_UPDT_INDEX;
+          }
+          break;
+        }
+        /////////////////////////
+      case INIT_CMD_UPDT_INDEX:	// send the first word index
+        {
+
+          if ( p_vci_ini.cmdack )  r_init_cmd_fsm = INIT_CMD_UPDT_DATA;
+          break;
+        }
+        ////////////////////////
+      case INIT_CMD_UPDT_DATA:	// send the data
+        {
+          if ( p_vci_ini.cmdack ) {
+            if ( r_init_cmd_cpt.read() == (r_write_to_init_cmd_count.read()-1) ) {
+              r_init_cmd_fsm = INIT_CMD_UPDT_SEL;
+            } else {
+              r_init_cmd_cpt = r_init_cmd_cpt.read() + 1;
+            }
+          }
+          break;
+        }
+        ///////////////////////
+      case INIT_CMD_SC_UPDT_SEL:	// selects the next L1 cache
+        {
+          if (r_llsc_to_init_cmd_d_copies.read() == 0) {	// no more copies
+            r_llsc_to_init_cmd_req = false;
+            r_init_cmd_fsm    = INIT_CMD_SC_UPDT_IDLE;
+          } else {						// select the first target
+            copy_t copies;
+            copies = r_llsc_to_init_cmd_d_copies.read();
+            copy_t mask   = 0x1;
+            for ( size_t i=0 ; i<8*sizeof(copy_t) ; i++ ) {
+              if ( copies & mask ) {
+                r_init_cmd_target = i;
+                break;
+              }
+              mask = mask << 1;
+            } // end for 
+            r_init_cmd_fsm    = INIT_CMD_SC_UPDT_NLINE;
+            r_llsc_to_init_cmd_d_copies = copies & ~mask;
+            r_init_cmd_cpt    = 0;
+            m_cpt_update_mult++;
+          }
+          break;
+        }
+        /////////////////////////
+      case INIT_CMD_SC_BRDCAST:
+        {
+          if( p_vci_ini.cmdack ) {
+            r_llsc_to_init_cmd_req = false;
+            r_init_cmd_fsm = INIT_CMD_SC_UPDT_IDLE;
+          }
+          break;
+        }
+        /////////////////////////
+      case INIT_CMD_SC_UPDT_NLINE:	// send the cache line index
+        {
+          if ( p_vci_ini.cmdack ){
+            r_init_cmd_fsm = INIT_CMD_SC_UPDT_INDEX;
+          }
+          break;
+        }
+        /////////////////////////
+      case INIT_CMD_SC_UPDT_INDEX:	// send the first word index
+        {
+
+          if ( p_vci_ini.cmdack )  r_init_cmd_fsm = INIT_CMD_SC_UPDT_DATA;
+          break;
+        }
+        ////////////////////////
+      case INIT_CMD_SC_UPDT_DATA:	// send the data
+        {
+          if ( p_vci_ini.cmdack ) {
+            r_init_cmd_fsm = INIT_CMD_SC_UPDT_SEL;
+          }
+          break;
+        }
+
+    } // end switch r_init_cmd_fsm
+
+    /////////////////////////////////////////////////////////////////////
+    //		TGT_RSP FSM
+    /////////////////////////////////////////////////////////////////////
+    // The TGT_RSP fsm sends the responses on the VCI target port
+    // with a round robin priority between six requests :
+    // - r_read_to_tgt_rsp_req
+    // - r_write_to_tgt_rsp_req
+    // - r_llsc_to_tgt_rsp_req
+    // - r_cleanup_to_tgt_rsp_req
+    // - r_init_rsp_to_tgt_rsp_req
+    // - r_xram_rsp_to_tgt_rsp_req
+    // The  ordering is :  read > write > llsc > cleanup > xram > init
+    /////////////////////////////////////////////////////////////////////
+
+    switch ( r_tgt_rsp_fsm.read() ) {
+
+      ///////////////////////
+      case TGT_RSP_READ_IDLE:		// write requests have the highest priority
+        {
+          if      ( r_write_to_tgt_rsp_req    ) r_tgt_rsp_fsm = TGT_RSP_WRITE;
+          else if ( r_llsc_to_tgt_rsp_req     ) r_tgt_rsp_fsm = TGT_RSP_LLSC;
+          else if ( r_xram_rsp_to_tgt_rsp_req ) {
+            r_tgt_rsp_fsm = TGT_RSP_XRAM;
+            r_tgt_rsp_cpt = r_xram_rsp_to_tgt_rsp_word.read();
+          }
+          else if ( r_init_rsp_to_tgt_rsp_req ) r_tgt_rsp_fsm = TGT_RSP_INIT;
+          else if ( r_cleanup_to_tgt_rsp_req  ) r_tgt_rsp_fsm = TGT_RSP_CLEANUP;
+          else if ( r_read_to_tgt_rsp_req     ) {
+            r_tgt_rsp_fsm = TGT_RSP_READ;
+            r_tgt_rsp_cpt = r_read_to_tgt_rsp_word.read();
+          }
+          break;
+        }
+        ////////////////////////
+      case TGT_RSP_WRITE_IDLE:		// llsc requests have the highest priority
+        {
+          if      ( r_llsc_to_tgt_rsp_req     ) r_tgt_rsp_fsm = TGT_RSP_LLSC;
+          else if ( r_xram_rsp_to_tgt_rsp_req ) {
+            r_tgt_rsp_fsm = TGT_RSP_XRAM;
+            r_tgt_rsp_cpt = r_xram_rsp_to_tgt_rsp_word.read();
+          }
+          else if ( r_init_rsp_to_tgt_rsp_req ) r_tgt_rsp_fsm = TGT_RSP_INIT;
+          else if ( r_cleanup_to_tgt_rsp_req  ) r_tgt_rsp_fsm = TGT_RSP_CLEANUP;
+          else if ( r_read_to_tgt_rsp_req     ) {
+            r_tgt_rsp_fsm = TGT_RSP_READ;
+            r_tgt_rsp_cpt = r_read_to_tgt_rsp_word.read();
+          }
+
+          else if ( r_write_to_tgt_rsp_req    ) r_tgt_rsp_fsm = TGT_RSP_WRITE;
+          break;
+        }
+        ///////////////////////
+      case TGT_RSP_LLSC_IDLE:		// cleanup requests have the highest priority
+        {
+          if ( r_xram_rsp_to_tgt_rsp_req )  {
+            r_tgt_rsp_fsm = TGT_RSP_XRAM;
+            r_tgt_rsp_cpt = r_xram_rsp_to_tgt_rsp_word.read();
+          }
+          else if ( r_init_rsp_to_tgt_rsp_req ) r_tgt_rsp_fsm = TGT_RSP_INIT;
+          else if ( r_cleanup_to_tgt_rsp_req  ) r_tgt_rsp_fsm = TGT_RSP_CLEANUP;
+          else if ( r_read_to_tgt_rsp_req     ) {
+            r_tgt_rsp_fsm = TGT_RSP_READ;
+            r_tgt_rsp_cpt = r_read_to_tgt_rsp_word.read();
+          }
+          else if ( r_write_to_tgt_rsp_req    ) r_tgt_rsp_fsm = TGT_RSP_WRITE;
+          else if ( r_llsc_to_tgt_rsp_req     ) r_tgt_rsp_fsm = TGT_RSP_LLSC;
+          break;
+        }
+      case TGT_RSP_XRAM_IDLE:		// init requests have the highest priority
+        {
+
+          if      ( r_init_rsp_to_tgt_rsp_req ) r_tgt_rsp_fsm = TGT_RSP_INIT;
+          else if ( r_cleanup_to_tgt_rsp_req  ) r_tgt_rsp_fsm = TGT_RSP_CLEANUP;
+          else if ( r_read_to_tgt_rsp_req     ) {
+            r_tgt_rsp_fsm = TGT_RSP_READ;
+            r_tgt_rsp_cpt = r_read_to_tgt_rsp_word.read();
+          }
+          else if ( r_write_to_tgt_rsp_req    ) r_tgt_rsp_fsm = TGT_RSP_WRITE;
+          else if ( r_llsc_to_tgt_rsp_req     ) r_tgt_rsp_fsm = TGT_RSP_LLSC;
+          else if ( r_xram_rsp_to_tgt_rsp_req )  {
+            r_tgt_rsp_fsm = TGT_RSP_XRAM;
+            r_tgt_rsp_cpt = r_xram_rsp_to_tgt_rsp_word.read();
+          }
+          break;
+        }
+        ///////////////////////
+      case TGT_RSP_INIT_IDLE:		// cleanup requests have the highest priority
+        {
+          if      ( r_cleanup_to_tgt_rsp_req  ) r_tgt_rsp_fsm = TGT_RSP_CLEANUP;
+          else if ( r_read_to_tgt_rsp_req     ) {
+            r_tgt_rsp_fsm = TGT_RSP_READ;
+            r_tgt_rsp_cpt = r_read_to_tgt_rsp_word.read();
+          }
+          else if ( r_write_to_tgt_rsp_req    ) r_tgt_rsp_fsm = TGT_RSP_WRITE;
+          else if ( r_llsc_to_tgt_rsp_req     ) r_tgt_rsp_fsm = TGT_RSP_LLSC;
+          else if ( r_xram_rsp_to_tgt_rsp_req ) {
+            r_tgt_rsp_fsm = TGT_RSP_XRAM;
+            r_tgt_rsp_cpt = r_xram_rsp_to_tgt_rsp_word.read();
+          }
+          else if ( r_init_rsp_to_tgt_rsp_req ) r_tgt_rsp_fsm = TGT_RSP_INIT;
+          break;
+        }
+        ///////////////////////
+      case TGT_RSP_CLEANUP_IDLE:		// read requests have the highest priority
+        {
+          if      ( r_read_to_tgt_rsp_req     ) {
+            r_tgt_rsp_fsm = TGT_RSP_READ;
+            r_tgt_rsp_cpt = r_read_to_tgt_rsp_word.read();
+          }
+          else if ( r_write_to_tgt_rsp_req    ) r_tgt_rsp_fsm = TGT_RSP_WRITE;
+          else if ( r_llsc_to_tgt_rsp_req     ) r_tgt_rsp_fsm = TGT_RSP_LLSC;
+          else if ( r_xram_rsp_to_tgt_rsp_req ) {
+            r_tgt_rsp_fsm = TGT_RSP_XRAM;
+            r_tgt_rsp_cpt = r_xram_rsp_to_tgt_rsp_word.read();
+          }
+          else if ( r_init_rsp_to_tgt_rsp_req ) r_tgt_rsp_fsm = TGT_RSP_INIT;
+          else if ( r_cleanup_to_tgt_rsp_req  ) r_tgt_rsp_fsm = TGT_RSP_CLEANUP;
+          break;
+        }
+        ///////////////////////
+      case TGT_RSP_READ:		// send the response
+        {
+          if ( p_vci_tgt.rspack ) {
+            if ( r_tgt_rsp_cpt.read() == (r_read_to_tgt_rsp_word.read()+r_read_to_tgt_rsp_length-1) ) {
+              r_tgt_rsp_fsm = TGT_RSP_READ_IDLE;
+              r_read_to_tgt_rsp_req = false;
+            } else {
+              r_tgt_rsp_cpt = r_tgt_rsp_cpt.read() + 1;
+            }
+          }
+          break;
+        }
+        ///////////////////
+      case TGT_RSP_WRITE:		// send the write acknowledge
+        {
+          if ( p_vci_tgt.rspack ) {
+            r_tgt_rsp_fsm = TGT_RSP_WRITE_IDLE;
+            r_write_to_tgt_rsp_req = false;
+          }
+          break;
+        }
+        ///////////////////
+      case TGT_RSP_CLEANUP:		// send the write acknowledge
+        {
+          if ( p_vci_tgt.rspack ) {
+            r_tgt_rsp_fsm = TGT_RSP_CLEANUP_IDLE;
+            r_cleanup_to_tgt_rsp_req = false;
+          }
+          break;
+        }
+        //////////////////
+      case TGT_RSP_LLSC:		// send one atomic word response
+        {
+          if ( p_vci_tgt.rspack ) {
+            r_tgt_rsp_fsm = TGT_RSP_LLSC_IDLE;
+            r_llsc_to_tgt_rsp_req = false;
+          }
+          break;
+        }
+
+        ///////////////////////
+      case TGT_RSP_XRAM:		// send the response
+        {
+          if ( p_vci_tgt.rspack ) {
+            if ( r_tgt_rsp_cpt.read() == (r_xram_rsp_to_tgt_rsp_word.read()+r_xram_rsp_to_tgt_rsp_length.read()-1)) {
+              r_tgt_rsp_fsm = TGT_RSP_XRAM_IDLE;
+              r_xram_rsp_to_tgt_rsp_req = false;
+            } else {
+              r_tgt_rsp_cpt = r_tgt_rsp_cpt.read() + 1;
+            }
+          }
+          break;
+        }
+        ///////////////////
+      case TGT_RSP_INIT:		// send the pending write acknowledge
+        {
+          if ( p_vci_tgt.rspack ) {
+            r_tgt_rsp_fsm = TGT_RSP_INIT_IDLE;
+            r_init_rsp_to_tgt_rsp_req = false;
+          }
+          break;
+        }
+    } // end switch tgt_rsp_fsm
+    ////////////////////////////////////////////////////////////////////////////////////
+    //		NEW ALLOC_UPT FSM
+    ////////////////////////////////////////////////////////////////////////////////////
+    // The ALLOC_UPT FSM allocates the access to the Update/Inval Table (UPT).
+    // with a round robin priority between three FSMs : INIT_RSP > WRITE > XRAM_RSP > CLEANUP 
+    // - The WRITE FSM initiates update transactions and sets  new entry in UPT.
+    // - The XRAM_RSP FSM initiates inval transactions and sets  new entry in UPT.
+    // - The INIT_RSP FSM complete those trasactions and erase the UPT entry.
+    // - The CLEANUP  FSM decrement an entry in UPT.
+    // The resource is always allocated.
+    /////////////////////////////////////////////////////////////////////////////////////
+
+    switch ( r_alloc_upt_fsm.read() ) {
+
+      ////////////////////////
+      case ALLOC_UPT_INIT_RSP:
+        if ( (r_init_rsp_fsm.read() != INIT_RSP_UPT_LOCK) && 
+             (r_init_rsp_fsm.read() != INIT_RSP_UPT_CLEAR) ) 
+        {
+          if      ((r_write_fsm.read() == WRITE_UPT_LOCK) ||
+                   (r_write_fsm.read() == WRITE_INVAL_LOCK))        r_alloc_upt_fsm = ALLOC_UPT_WRITE;
+          else if (r_xram_rsp_fsm.read() == XRAM_RSP_INVAL_LOCK)    r_alloc_upt_fsm = ALLOC_UPT_XRAM_RSP;
+          else if (r_cleanup_fsm.read() == CLEANUP_UPT_LOCK)        r_alloc_upt_fsm = ALLOC_UPT_CLEANUP;
+          else if ((r_llsc_fsm.read() == SC_UPT_LOCK) ||
+                   (r_llsc_fsm.read() == SC_INVAL_LOCK))            r_alloc_upt_fsm = ALLOC_UPT_LLSC;
+        }
+        break;
+
+        /////////////////////
+      case ALLOC_UPT_WRITE:
+        if ( (r_write_fsm.read() != WRITE_UPT_LOCK) &&
+             (r_write_fsm.read() != WRITE_INVAL_LOCK)) 
+        {
+          if      (r_xram_rsp_fsm.read() == XRAM_RSP_INVAL_LOCK)    r_alloc_upt_fsm = ALLOC_UPT_XRAM_RSP;
+          else if (r_cleanup_fsm.read() == CLEANUP_UPT_LOCK)        r_alloc_upt_fsm = ALLOC_UPT_CLEANUP;
+          else if ((r_llsc_fsm.read() == SC_UPT_LOCK) ||
+                   (r_llsc_fsm.read() == SC_INVAL_LOCK))            r_alloc_upt_fsm = ALLOC_UPT_LLSC;
+          else if (r_init_rsp_fsm.read() == INIT_RSP_UPT_LOCK)      r_alloc_upt_fsm = ALLOC_UPT_INIT_RSP;
+        }
+        break;
+
+        ////////////////////////
+      case ALLOC_UPT_XRAM_RSP:
+        if (r_xram_rsp_fsm.read() != XRAM_RSP_INVAL_LOCK) 
+        { 
+          if       (r_cleanup_fsm.read() == CLEANUP_UPT_LOCK)       r_alloc_upt_fsm = ALLOC_UPT_CLEANUP;
+          else if ((r_llsc_fsm.read() == SC_UPT_LOCK) ||
+                   (r_llsc_fsm.read() == SC_INVAL_LOCK))            r_alloc_upt_fsm = ALLOC_UPT_LLSC;
+          else if  (r_init_rsp_fsm.read() == INIT_RSP_UPT_LOCK)     r_alloc_upt_fsm = ALLOC_UPT_INIT_RSP;
+          else if ((r_write_fsm.read() == WRITE_UPT_LOCK)   ||
+                   (r_write_fsm.read() == WRITE_INVAL_LOCK))        r_alloc_upt_fsm = ALLOC_UPT_WRITE;
+        }
+        break;
+
+        //////////////////////////
+      case ALLOC_UPT_CLEANUP:
+        if(r_cleanup_fsm.read() != CLEANUP_UPT_LOCK )
+        {
+          if      ((r_llsc_fsm.read() == SC_UPT_LOCK) ||
+                   (r_llsc_fsm.read() == SC_INVAL_LOCK))            r_alloc_upt_fsm = ALLOC_UPT_LLSC;
+          else if  (r_init_rsp_fsm.read() == INIT_RSP_UPT_LOCK)     r_alloc_upt_fsm = ALLOC_UPT_INIT_RSP;
+          else if ((r_write_fsm.read() == WRITE_UPT_LOCK) ||
+                   (r_write_fsm.read() == WRITE_INVAL_LOCK))        r_alloc_upt_fsm = ALLOC_UPT_WRITE;
+          else if (r_xram_rsp_fsm.read() == XRAM_RSP_INVAL_LOCK)    r_alloc_upt_fsm = ALLOC_UPT_XRAM_RSP;
+        }
+        break;
+        
+        //////////////////////////
+      case ALLOC_UPT_LLSC:
+        if( (r_llsc_fsm.read() != SC_UPT_LOCK) && 
+            (r_llsc_fsm.read() != SC_INVAL_LOCK))
+        {
+          if      (r_init_rsp_fsm.read() == INIT_RSP_UPT_LOCK)      r_alloc_upt_fsm = ALLOC_UPT_INIT_RSP;
+          else if ((r_write_fsm.read() == WRITE_UPT_LOCK) ||
+                   (r_write_fsm.read() == WRITE_INVAL_LOCK))        r_alloc_upt_fsm = ALLOC_UPT_WRITE;
+          else if (r_xram_rsp_fsm.read() == XRAM_RSP_INVAL_LOCK)    r_alloc_upt_fsm = ALLOC_UPT_XRAM_RSP;
+          else if (r_cleanup_fsm.read() == CLEANUP_UPT_LOCK)        r_alloc_upt_fsm = ALLOC_UPT_CLEANUP;
+        }
+        break;
+
+    } // end switch r_alloc_upt_fsm
+
+    ////////////////////////////////////////////////////////////////////////////////////
+    //		ALLOC_DIR FSM
+    ////////////////////////////////////////////////////////////////////////////////////
+    // The ALLOC_DIR FSM allocates the access to the directory and
+    // the data cache with a round robin priority between 5 user FSMs :
+    // The cyclic ordering is READ > WRITE > LLSC > CLEANUP > XRAM_RSP
+    // The ressource is always allocated.
+    /////////////////////////////////////////////////////////////////////////////////////
+
+    switch ( r_alloc_dir_fsm.read() ) {
+
+      ////////////////////
+      case ALLOC_DIR_READ:
+        if ( ( (r_read_fsm.read() != READ_DIR_LOCK) &&
+              (r_read_fsm.read() != READ_TRT_LOCK)     )
+            ||
+            ( (r_read_fsm.read()      == READ_TRT_LOCK)  &&
+              (r_alloc_trt_fsm.read() == ALLOC_TRT_READ)    )  ) 
+        {
+          if        (r_write_fsm.read() == WRITE_DIR_LOCK)          r_alloc_dir_fsm = ALLOC_DIR_WRITE;
+          else if   ((r_llsc_fsm.read() == LL_DIR_LOCK) || 
+                    (r_llsc_fsm.read() == SC_DIR_LOCK))             r_alloc_dir_fsm = ALLOC_DIR_LLSC;
+          else if   (r_cleanup_fsm.read() == CLEANUP_DIR_LOCK)      r_alloc_dir_fsm = ALLOC_DIR_CLEANUP;
+          else if   (r_xram_rsp_fsm.read() == XRAM_RSP_DIR_LOCK)    r_alloc_dir_fsm = ALLOC_DIR_XRAM_RSP;
+        }
+        break;
+
+        /////////////////////
+      case ALLOC_DIR_WRITE:
+        if ( ( (r_write_fsm.read() != WRITE_DIR_LOCK)     &&
+              (r_write_fsm.read() != WRITE_TRT_LOCK)     &&
+              (r_write_fsm.read() != WRITE_DIR_HIT_READ) &&
+              (r_write_fsm.read() != WRITE_TRT_WRITE_LOCK) &&
+              (r_write_fsm.read() != WRITE_INVAL_LOCK) )
+            ||
+            ( (r_write_fsm.read()     == WRITE_TRT_LOCK) &&
+              (r_alloc_trt_fsm.read() == ALLOC_TRT_WRITE)   )   )
+        {
+          if        ((r_llsc_fsm.read() == LL_DIR_LOCK) || 
+                    (r_llsc_fsm.read() == SC_DIR_LOCK))             r_alloc_dir_fsm = ALLOC_DIR_LLSC;
+          else if   (r_cleanup_fsm.read() == CLEANUP_DIR_LOCK)      r_alloc_dir_fsm = ALLOC_DIR_CLEANUP;
+          else if   (r_xram_rsp_fsm.read() == XRAM_RSP_DIR_LOCK)    r_alloc_dir_fsm = ALLOC_DIR_XRAM_RSP;
+          else if   (r_read_fsm.read() == READ_DIR_LOCK) 	        r_alloc_dir_fsm = ALLOC_DIR_READ;
+        }
+        break;
+
+        ////////////////////
+      case ALLOC_DIR_LLSC:
+        if ( ( (r_llsc_fsm.read() != LL_DIR_LOCK)    &&
+              (r_llsc_fsm.read() != LL_DIR_HIT )    &&
+              (r_llsc_fsm.read() != SC_DIR_LOCK)    &&
+              (r_llsc_fsm.read() != SC_DIR_HIT )    &&
+              (r_llsc_fsm.read() != LLSC_TRT_LOCK ) &&
+              (r_llsc_fsm.read() != SC_TRT_LOCK)    &&
+              (r_llsc_fsm.read() != SC_INVAL_LOCK))
+            || 
+            ( (r_llsc_fsm.read()      == LLSC_TRT_LOCK ) &&
+              (r_alloc_trt_fsm.read() == ALLOC_TRT_LLSC)    ) )
+        {
+          if      (r_cleanup_fsm.read() == CLEANUP_DIR_LOCK)    r_alloc_dir_fsm = ALLOC_DIR_CLEANUP;
+          else if (r_xram_rsp_fsm.read() == XRAM_RSP_DIR_LOCK)  r_alloc_dir_fsm = ALLOC_DIR_XRAM_RSP;
+          else if (r_read_fsm.read() == READ_DIR_LOCK) 	        r_alloc_dir_fsm = ALLOC_DIR_READ;
+          else if (r_write_fsm.read() == WRITE_DIR_LOCK)        r_alloc_dir_fsm = ALLOC_DIR_WRITE;
+        }
+        break;
+
+        ///////////////////////
+      case ALLOC_DIR_CLEANUP:
+        if ( (r_cleanup_fsm.read() != CLEANUP_DIR_LOCK) &&
+            (r_cleanup_fsm.read() != CLEANUP_DIR_WRITE) )
+        {
+          if        (r_xram_rsp_fsm.read() == XRAM_RSP_DIR_LOCK)    r_alloc_dir_fsm = ALLOC_DIR_XRAM_RSP;
+          else if   (r_read_fsm.read() == READ_DIR_LOCK)            r_alloc_dir_fsm = ALLOC_DIR_READ;
+          else if   (r_write_fsm.read() == WRITE_DIR_LOCK)          r_alloc_dir_fsm = ALLOC_DIR_WRITE;
+          else if   ((r_llsc_fsm.read() == LL_DIR_LOCK) || 
+                    (r_llsc_fsm.read() == SC_DIR_LOCK))             r_alloc_dir_fsm = ALLOC_DIR_LLSC;
+        }
+        break;
+        ////////////////////////
+      case ALLOC_DIR_XRAM_RSP:
+        if ( (r_xram_rsp_fsm.read() != XRAM_RSP_DIR_LOCK)  &&
+            (r_xram_rsp_fsm.read() != XRAM_RSP_TRT_COPY)   && 
+            (r_xram_rsp_fsm.read() != XRAM_RSP_INVAL_LOCK))
+        {
+          if      (r_read_fsm.read() == READ_DIR_LOCK) 	        r_alloc_dir_fsm = ALLOC_DIR_READ;
+          else if (r_write_fsm.read() == WRITE_DIR_LOCK)        r_alloc_dir_fsm = ALLOC_DIR_WRITE;
+          else if ( (r_llsc_fsm.read() == LL_DIR_LOCK) || 
+                    (r_llsc_fsm.read() == SC_DIR_LOCK))         r_alloc_dir_fsm = ALLOC_DIR_LLSC;
+          else if (r_cleanup_fsm.read() == CLEANUP_DIR_LOCK)    r_alloc_dir_fsm = ALLOC_DIR_CLEANUP;
+        }
+        break;
+
+    } // end switch alloc_dir_fsm
+
+    ////////////////////////////////////////////////////////////////////////////////////
+    //		ALLOC_TRT FSM
+    ////////////////////////////////////////////////////////////////////////////////////
+    // The ALLOC_TRT fsm allocates the access to the Transaction Table (write buffer)
+    // with a round robin priority between 4 user FSMs :
+    // The cyclic priority is READ > WRITE > LLSC > XRAM_RSP
+    // The ressource is always allocated.
+    ///////////////////////////////////////////////////////////////////////////////////
+
+    switch (r_alloc_trt_fsm) {
+
+      ////////////////////
+      case ALLOC_TRT_READ:
+        if ( r_read_fsm.read() != READ_TRT_LOCK ) 
+        {
+          if      ((r_write_fsm.read() == WRITE_TRT_LOCK)   ||
+                   (r_write_fsm.read() == WRITE_TRT_WRITE_LOCK))    r_alloc_trt_fsm = ALLOC_TRT_WRITE;
+          else if ((r_llsc_fsm.read() == LLSC_TRT_LOCK) ||
+                   (r_llsc_fsm.read() == SC_TRT_LOCK))              r_alloc_trt_fsm = ALLOC_TRT_LLSC;
+          else if (r_xram_rsp_fsm.read() == XRAM_RSP_TRT_COPY)      r_alloc_trt_fsm = ALLOC_TRT_XRAM_RSP;
+          else if ( (r_ixr_rsp_fsm.read() == IXR_RSP_TRT_ERASE) ||
+                    (r_ixr_rsp_fsm.read() == IXR_RSP_TRT_READ) )    r_alloc_trt_fsm = ALLOC_TRT_IXR_RSP;
+        }
+        break;
+        /////////////////////
+      case ALLOC_TRT_WRITE:
+        if ( (r_write_fsm.read() != WRITE_TRT_LOCK) &&
+             (r_write_fsm.read() != WRITE_TRT_WRITE_LOCK) &&
+             (r_write_fsm.read() != WRITE_INVAL_LOCK)) 
+        {
+          if      ((r_llsc_fsm.read() == LLSC_TRT_LOCK) ||
+                   (r_llsc_fsm.read() == SC_TRT_LOCK))              r_alloc_trt_fsm = ALLOC_TRT_LLSC;
+          else if (r_xram_rsp_fsm.read() == XRAM_RSP_TRT_COPY)      r_alloc_trt_fsm = ALLOC_TRT_XRAM_RSP;
+          else if ( (r_ixr_rsp_fsm.read() == IXR_RSP_TRT_ERASE) ||
+                    (r_ixr_rsp_fsm.read() == IXR_RSP_TRT_READ))     r_alloc_trt_fsm = ALLOC_TRT_IXR_RSP;
+          else if (r_read_fsm.read() == READ_TRT_LOCK) 	            r_alloc_trt_fsm = ALLOC_TRT_READ;
+        }
+        break;
+        ////////////////////
+      case ALLOC_TRT_LLSC:
+        if ( (r_llsc_fsm.read() != LLSC_TRT_LOCK) &&
+             (r_llsc_fsm.read() != SC_TRT_LOCK) &&
+             (r_llsc_fsm.read() != SC_INVAL_LOCK))
+        { 
+          if      (r_xram_rsp_fsm.read() == XRAM_RSP_TRT_COPY)      r_alloc_trt_fsm = ALLOC_TRT_XRAM_RSP;
+          else if ( (r_ixr_rsp_fsm.read() == IXR_RSP_TRT_ERASE) ||
+                    (r_ixr_rsp_fsm.read() == IXR_RSP_TRT_READ))     r_alloc_trt_fsm = ALLOC_TRT_IXR_RSP;
+          else if (r_read_fsm.read() == READ_TRT_LOCK) 	            r_alloc_trt_fsm = ALLOC_TRT_READ;
+          else if ((r_write_fsm.read() == WRITE_TRT_LOCK)     ||
+                   (r_write_fsm.read() == WRITE_TRT_WRITE_LOCK))    r_alloc_trt_fsm = ALLOC_TRT_WRITE;
+        }
+        break;
+        ////////////////////////
+      case ALLOC_TRT_XRAM_RSP:
+        if ( (r_xram_rsp_fsm.read() != XRAM_RSP_TRT_COPY)  &&
+            (r_xram_rsp_fsm.read() != XRAM_RSP_DIR_UPDT)   &&
+            (r_xram_rsp_fsm.read() != XRAM_RSP_INVAL_LOCK)) {
+          if      ( (r_ixr_rsp_fsm.read() == IXR_RSP_TRT_ERASE) ||
+                    (r_ixr_rsp_fsm.read() == IXR_RSP_TRT_READ))     r_alloc_trt_fsm = ALLOC_TRT_IXR_RSP;
+          else if (r_read_fsm.read() == READ_TRT_LOCK) 	            r_alloc_trt_fsm = ALLOC_TRT_READ;
+          else if ((r_write_fsm.read() == WRITE_TRT_LOCK)    ||
+                   (r_write_fsm.read() == WRITE_TRT_WRITE_LOCK))    r_alloc_trt_fsm = ALLOC_TRT_WRITE;
+          else if ((r_llsc_fsm.read() == LLSC_TRT_LOCK) ||
+                   (r_llsc_fsm.read() == SC_TRT_LOCK))              r_alloc_trt_fsm = ALLOC_TRT_LLSC;
+        }
+        break;
+        ////////////////////////
+      case ALLOC_TRT_IXR_RSP:
+        if ( (r_ixr_rsp_fsm.read() != IXR_RSP_TRT_ERASE) &&
+            (r_ixr_rsp_fsm.read() != IXR_RSP_TRT_READ) ) {
+          if      (r_read_fsm.read() == READ_TRT_LOCK) 	            r_alloc_trt_fsm = ALLOC_TRT_READ;
+          else if ((r_write_fsm.read() == WRITE_TRT_LOCK)   ||
+                   (r_write_fsm.read() == WRITE_TRT_WRITE_LOCK))    r_alloc_trt_fsm = ALLOC_TRT_WRITE;
+          else if ((r_llsc_fsm.read() == LLSC_TRT_LOCK) ||
+                   (r_llsc_fsm.read() == SC_TRT_LOCK))              r_alloc_trt_fsm = ALLOC_TRT_LLSC;
+          else if (r_xram_rsp_fsm.read() == XRAM_RSP_TRT_COPY)      r_alloc_trt_fsm = ALLOC_TRT_XRAM_RSP;
+        }
+        break;
+
+    } // end switch alloc_trt_fsm
+
+    ////////////////////////////////////////////////////////////////////////////////////
+    //		TGT_CMD to READ FIFO
+    ////////////////////////////////////////////////////////////////////////////////////
+
+    if ( cmd_read_fifo_put ) {
+      if ( cmd_read_fifo_get ) {
+        m_cmd_read_addr_fifo.put_and_get((addr_t)(p_vci_tgt.address.read()));
+        m_cmd_read_length_fifo.put_and_get(p_vci_tgt.plen.read()>>2);
+        m_cmd_read_srcid_fifo.put_and_get(p_vci_tgt.srcid.read());
+        m_cmd_read_trdid_fifo.put_and_get(p_vci_tgt.trdid.read());
+        m_cmd_read_pktid_fifo.put_and_get(p_vci_tgt.pktid.read());
+      } else {
+        m_cmd_read_addr_fifo.simple_put((addr_t)(p_vci_tgt.address.read()));
+        m_cmd_read_length_fifo.simple_put(p_vci_tgt.plen.read()>>2);
+        m_cmd_read_srcid_fifo.simple_put(p_vci_tgt.srcid.read());
+        m_cmd_read_trdid_fifo.simple_put(p_vci_tgt.trdid.read());
+        m_cmd_read_pktid_fifo.simple_put(p_vci_tgt.pktid.read());
+      }
+    } else {
+      if ( cmd_read_fifo_get ) {
+        m_cmd_read_addr_fifo.simple_get();
+        m_cmd_read_length_fifo.simple_get();
+        m_cmd_read_srcid_fifo.simple_get();
+        m_cmd_read_trdid_fifo.simple_get();
+        m_cmd_read_pktid_fifo.simple_get();
+      }
+    }
+    /////////////////////////////////////////////////////////////////////
+    //		TGT_CMD to WRITE FIFO
+    /////////////////////////////////////////////////////////////////////
+
+    if ( cmd_write_fifo_put ) {
+      if ( cmd_write_fifo_get ) {
+        m_cmd_write_addr_fifo.put_and_get((addr_t)(p_vci_tgt.address.read()));
+        m_cmd_write_eop_fifo.put_and_get(p_vci_tgt.eop.read());
+        m_cmd_write_srcid_fifo.put_and_get(p_vci_tgt.srcid.read());
+        m_cmd_write_trdid_fifo.put_and_get(p_vci_tgt.trdid.read());
+        m_cmd_write_pktid_fifo.put_and_get(p_vci_tgt.pktid.read());
+        m_cmd_write_data_fifo.put_and_get(p_vci_tgt.wdata.read());
+        m_cmd_write_be_fifo.put_and_get(p_vci_tgt.be.read());
+      } else {
+        m_cmd_write_addr_fifo.simple_put((addr_t)(p_vci_tgt.address.read()));
+        m_cmd_write_eop_fifo.simple_put(p_vci_tgt.eop.read());
+        m_cmd_write_srcid_fifo.simple_put(p_vci_tgt.srcid.read());
+        m_cmd_write_trdid_fifo.simple_put(p_vci_tgt.trdid.read());
+        m_cmd_write_pktid_fifo.simple_put(p_vci_tgt.pktid.read());
+        m_cmd_write_data_fifo.simple_put(p_vci_tgt.wdata.read());
+        m_cmd_write_be_fifo.simple_put(p_vci_tgt.be.read());
+      }
+    } else {
+      if ( cmd_write_fifo_get ) {
+        m_cmd_write_addr_fifo.simple_get();
+        m_cmd_write_eop_fifo.simple_get();
+        m_cmd_write_srcid_fifo.simple_get();
+        m_cmd_write_trdid_fifo.simple_get();
+        m_cmd_write_pktid_fifo.simple_get();
+        m_cmd_write_data_fifo.simple_get();
+        m_cmd_write_be_fifo.simple_get();
+      }
+    }
+    ////////////////////////////////////////////////////////////////////////////////////
+    //		TGT_CMD to LLSC FIFO
+    ////////////////////////////////////////////////////////////////////////////////////
+
+    if ( cmd_llsc_fifo_put ) {
+      if ( cmd_llsc_fifo_get ) {
+        m_cmd_llsc_addr_fifo.put_and_get((addr_t)(p_vci_tgt.address.read()));
+        m_cmd_llsc_sc_fifo.put_and_get(p_vci_tgt.cmd.read() == vci_param::CMD_STORE_COND); 
+        m_cmd_llsc_srcid_fifo.put_and_get(p_vci_tgt.srcid.read());
+        m_cmd_llsc_trdid_fifo.put_and_get(p_vci_tgt.trdid.read());
+        m_cmd_llsc_pktid_fifo.put_and_get(p_vci_tgt.pktid.read());
+        m_cmd_llsc_wdata_fifo.put_and_get(p_vci_tgt.wdata.read());
+      } else {
+        m_cmd_llsc_addr_fifo.simple_put((addr_t)(p_vci_tgt.address.read()));
+        m_cmd_llsc_sc_fifo.simple_put(p_vci_tgt.cmd.read() == vci_param::CMD_STORE_COND); 
+        m_cmd_llsc_srcid_fifo.simple_put(p_vci_tgt.srcid.read());
+        m_cmd_llsc_trdid_fifo.simple_put(p_vci_tgt.trdid.read());
+        m_cmd_llsc_pktid_fifo.simple_put(p_vci_tgt.pktid.read());
+        m_cmd_llsc_wdata_fifo.simple_put(p_vci_tgt.wdata.read());
+      }
+    } else {
+      if ( cmd_llsc_fifo_get ) {
+        m_cmd_llsc_addr_fifo.simple_get();
+        m_cmd_llsc_sc_fifo.simple_get();
+        m_cmd_llsc_srcid_fifo.simple_get();
+        m_cmd_llsc_trdid_fifo.simple_get();
+        m_cmd_llsc_pktid_fifo.simple_get();
+        m_cmd_llsc_wdata_fifo.simple_get();
+      }
+    }
+
+  //////////////////////////////////////////////////////////////
+    m_cpt_cycles++;
+
+  } // end transition()
+
+  /////////////////////////////
+  tmpl(void)::genMoore()
+    /////////////////////////////
+  {
+    ////////////////////////////////////////////////////////////
+    // Command signals on the p_vci_ixr port
+    ////////////////////////////////////////////////////////////
+
+
+    p_vci_ixr.be      = 0xF;
+    p_vci_ixr.pktid   = 0;
+    p_vci_ixr.srcid   = m_srcid_ixr;
+    p_vci_ixr.cons    = false;
+    p_vci_ixr.wrap    = false;
+    p_vci_ixr.contig  = true;
+    p_vci_ixr.clen    = 0;
+    p_vci_ixr.cfixed  = false;
+
+    if ( r_ixr_cmd_fsm.read() == IXR_CMD_READ_NLINE ) {
+      p_vci_ixr.cmd     = vci_param::CMD_READ;
+      p_vci_ixr.cmdval  = true;
+      p_vci_ixr.address = (addr_t)(r_read_to_ixr_cmd_nline.read()*m_words*4);
+      p_vci_ixr.plen    = m_words*4;
+      p_vci_ixr.wdata   = 0x00000000;
+      p_vci_ixr.trdid   = r_read_to_ixr_cmd_trdid.read();
+      p_vci_ixr.eop     = true;
+    } 
+    else if ( r_ixr_cmd_fsm.read() == IXR_CMD_LLSC_NLINE ) {
+      if(r_llsc_to_ixr_cmd_write.read()){
+        p_vci_ixr.cmd     = vci_param::CMD_WRITE;
+        p_vci_ixr.cmdval  = true;
+        p_vci_ixr.address = (addr_t)((r_llsc_to_ixr_cmd_nline.read()*m_words+r_ixr_cmd_cpt.read())*4);
+        p_vci_ixr.plen    = m_words*4;
+        p_vci_ixr.wdata   = r_llsc_to_ixr_cmd_data[r_ixr_cmd_cpt.read()].read();
+        p_vci_ixr.trdid   = r_llsc_to_ixr_cmd_trdid.read();
+        p_vci_ixr.eop     = (r_ixr_cmd_cpt == (m_words-1));
+      } else {
+        p_vci_ixr.cmd     = vci_param::CMD_READ;
+        p_vci_ixr.cmdval  = true;
+        p_vci_ixr.address = (addr_t)(r_llsc_to_ixr_cmd_nline.read()*m_words*4);
+        p_vci_ixr.plen    = m_words*4;
+        p_vci_ixr.wdata   = 0x00000000;
+        p_vci_ixr.trdid   = r_llsc_to_ixr_cmd_trdid.read();
+        p_vci_ixr.eop     = true;
+      }
+    } 
+    else if ( r_ixr_cmd_fsm.read() == IXR_CMD_WRITE_NLINE ) {
+      if(r_write_to_ixr_cmd_write.read()){
+        p_vci_ixr.cmd     = vci_param::CMD_WRITE;
+        p_vci_ixr.cmdval  = true;
+        p_vci_ixr.address = (addr_t)((r_write_to_ixr_cmd_nline.read()*m_words+r_ixr_cmd_cpt.read())*4);
+        p_vci_ixr.plen    = m_words*4;
+        p_vci_ixr.wdata   = r_write_to_ixr_cmd_data[r_ixr_cmd_cpt.read()].read();
+        p_vci_ixr.trdid   = r_write_to_ixr_cmd_trdid.read();
+        p_vci_ixr.eop     = (r_ixr_cmd_cpt == (m_words-1));
+      } else {
+        p_vci_ixr.cmd     = vci_param::CMD_READ;
+        p_vci_ixr.cmdval  = true;
+        p_vci_ixr.address = (addr_t)(r_write_to_ixr_cmd_nline.read()*m_words*4);
+        p_vci_ixr.plen    = m_words*4;
+        p_vci_ixr.wdata   = 0x00000000;
+        p_vci_ixr.trdid   = r_write_to_ixr_cmd_trdid.read();
+        p_vci_ixr.eop     = true;
+      }
+    } 
+    else if ( r_ixr_cmd_fsm.read() == IXR_CMD_XRAM_DATA ) {
+      p_vci_ixr.cmd     = vci_param::CMD_WRITE;
+      p_vci_ixr.cmdval  = true;
+      p_vci_ixr.address = (addr_t)((r_xram_rsp_to_ixr_cmd_nline.read()*m_words+r_ixr_cmd_cpt.read())*4);
+      p_vci_ixr.plen    = m_words*4;
+      p_vci_ixr.wdata   = r_xram_rsp_to_ixr_cmd_data[r_ixr_cmd_cpt.read()].read();
+      p_vci_ixr.trdid   = r_xram_rsp_to_ixr_cmd_trdid.read();
+      p_vci_ixr.eop     = (r_ixr_cmd_cpt == (m_words-1));
+    } else {
+      p_vci_ixr.cmdval  = false;
+      p_vci_ixr.address = 0;
+      p_vci_ixr.plen    = 0;
+      p_vci_ixr.wdata   = 0;
+      p_vci_ixr.trdid   = 0;
+      p_vci_ixr.eop	= false;
+    }
+
+    ////////////////////////////////////////////////////
+    // Response signals on the p_vci_ixr port
+    ////////////////////////////////////////////////////
+
+    if ( ((r_alloc_trt_fsm.read() == ALLOC_TRT_IXR_RSP) &&
+          (r_ixr_rsp_fsm.read() == IXR_RSP_TRT_READ)) || 
+        (r_ixr_rsp_fsm.read() == IXR_RSP_ACK) ) p_vci_ixr.rspack = true;
+    else                                        p_vci_ixr.rspack = false;
+
+    ////////////////////////////////////////////////////
+    // Command signals on the p_vci_tgt port
+    ////////////////////////////////////////////////////
+
+    switch ((tgt_cmd_fsm_state_e)r_tgt_cmd_fsm.read()) {
+      case TGT_CMD_IDLE:
+        p_vci_tgt.cmdack  = false;
+        break;
+      case TGT_CMD_READ:
+        p_vci_tgt.cmdack  = m_cmd_read_addr_fifo.wok();
+        break;
+      case TGT_CMD_READ_EOP:
+        p_vci_tgt.cmdack  = true;
+        break;
+      case TGT_CMD_WRITE:
+        p_vci_tgt.cmdack  = m_cmd_write_addr_fifo.wok();
+        break;
+      case TGT_CMD_ATOMIC:
+        p_vci_tgt.cmdack  = m_cmd_llsc_addr_fifo.wok();
+        break;
+      default:
+        p_vci_tgt.cmdack = false;
+        break;
+    }
+
+    ////////////////////////////////////////////////////
+    // Response signals on the p_vci_tgt port
+    ////////////////////////////////////////////////////
+    switch ( r_tgt_rsp_fsm.read() ) {
+
+      case TGT_RSP_READ_IDLE:
+      case TGT_RSP_WRITE_IDLE:
+      case TGT_RSP_LLSC_IDLE:
+      case TGT_RSP_XRAM_IDLE:
+      case TGT_RSP_INIT_IDLE:
+      case TGT_RSP_CLEANUP_IDLE:
+        p_vci_tgt.rspval  = false;
+        p_vci_tgt.rsrcid  = 0;
+        p_vci_tgt.rdata   = 0;
+        p_vci_tgt.rpktid  = 0;
+        p_vci_tgt.rtrdid  = 0;
+        p_vci_tgt.rerror  = 0;
+        p_vci_tgt.reop    = false;	
+        break;
+      case TGT_RSP_READ:
+        p_vci_tgt.rspval   = true;
+        p_vci_tgt.rdata    = r_read_to_tgt_rsp_data[r_tgt_rsp_cpt.read()].read();
+        p_vci_tgt.rsrcid   = r_read_to_tgt_rsp_srcid.read();
+        p_vci_tgt.rtrdid   = r_read_to_tgt_rsp_trdid.read();
+        p_vci_tgt.rpktid   = r_read_to_tgt_rsp_pktid.read();
+        p_vci_tgt.rerror   = 0;
+        p_vci_tgt.reop     = ( r_tgt_rsp_cpt.read() == (r_read_to_tgt_rsp_word.read()+r_read_to_tgt_rsp_length-1) );
+        break;
+      case TGT_RSP_WRITE:
+        p_vci_tgt.rspval   = true;
+        p_vci_tgt.rdata    = 0;
+        p_vci_tgt.rsrcid   = r_write_to_tgt_rsp_srcid.read();
+        p_vci_tgt.rtrdid   = r_write_to_tgt_rsp_trdid.read();
+        p_vci_tgt.rpktid   = r_write_to_tgt_rsp_pktid.read();
+        p_vci_tgt.rerror   = 0x2 & ( (1 << vci_param::E) - 1); // Write OK
+        p_vci_tgt.reop     = true;
+        break;
+      case TGT_RSP_CLEANUP:
+        p_vci_tgt.rspval   = true;
+        p_vci_tgt.rdata    = 0;
+        p_vci_tgt.rsrcid   = r_cleanup_to_tgt_rsp_srcid.read();
+        p_vci_tgt.rtrdid   = r_cleanup_to_tgt_rsp_trdid.read();
+        p_vci_tgt.rpktid   = r_cleanup_to_tgt_rsp_pktid.read();
+        p_vci_tgt.rerror   = 0;
+        p_vci_tgt.reop     = true;
+        break;
+      case TGT_RSP_LLSC:
+        p_vci_tgt.rspval   = true;
+        p_vci_tgt.rdata    = r_llsc_to_tgt_rsp_data.read();
+        p_vci_tgt.rsrcid   = r_llsc_to_tgt_rsp_srcid.read();
+        p_vci_tgt.rtrdid   = r_llsc_to_tgt_rsp_trdid.read();
+        p_vci_tgt.rpktid   = r_llsc_to_tgt_rsp_pktid.read();
+        p_vci_tgt.rerror   = 0;
+        p_vci_tgt.reop     = true;
+        break;
+      case TGT_RSP_XRAM:
+        p_vci_tgt.rspval   = true;
+        p_vci_tgt.rdata    = r_xram_rsp_to_tgt_rsp_data[r_tgt_rsp_cpt.read()].read();
+        p_vci_tgt.rsrcid   = r_xram_rsp_to_tgt_rsp_srcid.read();
+        p_vci_tgt.rtrdid   = r_xram_rsp_to_tgt_rsp_trdid.read();
+        p_vci_tgt.rpktid   = r_xram_rsp_to_tgt_rsp_pktid.read();
+        p_vci_tgt.rerror   = 0;
+        p_vci_tgt.reop     = ( r_tgt_rsp_cpt.read() == (r_xram_rsp_to_tgt_rsp_word.read()+r_xram_rsp_to_tgt_rsp_length.read()-1));
+        break;
+      case TGT_RSP_INIT:
+        p_vci_tgt.rspval   = true;
+        p_vci_tgt.rdata    = 0;
+        p_vci_tgt.rsrcid   = r_init_rsp_to_tgt_rsp_srcid.read();
+        p_vci_tgt.rtrdid   = r_init_rsp_to_tgt_rsp_trdid.read();
+        p_vci_tgt.rpktid   = r_init_rsp_to_tgt_rsp_pktid.read();
+        p_vci_tgt.rerror   = 0;
+        p_vci_tgt.reop     = true;	
+        break;
+    } // end switch r_tgt_rsp_fsm
+
+    ///////////////////////////////////////////////////
+    // Command signals on the p_vci_ini port
+    ///////////////////////////////////////////////////
+
+    p_vci_ini.cmd     = vci_param::CMD_WRITE;
+    p_vci_ini.srcid   = m_srcid_ini;
+    p_vci_ini.pktid   = 0;
+    p_vci_ini.cons    = true;
+    p_vci_ini.wrap    = false;
+    p_vci_ini.contig  = false;
+    p_vci_ini.clen    = 0;
+    p_vci_ini.cfixed  = false;
+
+    switch ( r_init_cmd_fsm.read() ) {
+
+      case INIT_CMD_UPDT_IDLE:
+      case INIT_CMD_INVAL_IDLE:
+      case INIT_CMD_SC_UPDT_IDLE:
+      case INIT_CMD_UPDT_SEL:
+      case INIT_CMD_INVAL_SEL:
+      case INIT_CMD_SC_UPDT_SEL:
+        p_vci_ini.cmdval  = false;
+        p_vci_ini.address = 0;
+        p_vci_ini.wdata   = 0;
+        p_vci_ini.be      = 0;
+        p_vci_ini.plen    = 0;
+        p_vci_ini.trdid   = 0;
+        p_vci_ini.eop     = false;
+        break;
+      case INIT_CMD_INVAL_NLINE:
+        p_vci_ini.cmdval  = true;
+        if(r_xram_rsp_to_init_cmd_brdcast.read())
+          p_vci_ini.address = broadcast_addr;
+        else {
+          if(r_init_cmd_inst.read()) {
+            p_vci_ini.address = (addr_t)(m_coherence_table[r_init_cmd_target.read()]+8);
+          } else {
+            p_vci_ini.address = (addr_t)(m_coherence_table[r_init_cmd_target.read()]);
+          }
+        }
+        p_vci_ini.wdata   = (uint32_t)r_xram_rsp_to_init_cmd_nline.read();
+        p_vci_ini.be      = ((r_xram_rsp_to_init_cmd_nline.read() >> 32) & 0x3);
+        p_vci_ini.plen    = 4;
+        p_vci_ini.trdid   = r_xram_rsp_to_init_cmd_trdid.read();
+        p_vci_ini.eop     = true;
+        break;
+      case INIT_CMD_BRDCAST:
+        p_vci_ini.cmdval  = true;
+        p_vci_ini.address = broadcast_addr;
+        p_vci_ini.wdata   = (addr_t)r_write_to_init_cmd_nline.read();
+        p_vci_ini.be      = ((r_write_to_init_cmd_nline.read() >> 32) & 0x3);
+        p_vci_ini.plen    = 4 ;
+        p_vci_ini.eop     = true;
+        p_vci_ini.trdid   = r_write_to_init_cmd_trdid.read();
+        break;
+      case INIT_CMD_UPDT_NLINE:
+        p_vci_ini.cmdval  = true;
+        p_vci_ini.address = (addr_t)(m_coherence_table[r_init_cmd_target.read()] + 4);
+        p_vci_ini.wdata   = (uint32_t)r_write_to_init_cmd_nline.read();
+        p_vci_ini.be      = ((r_write_to_init_cmd_nline.read() >> 32 ) & 0x3);
+        p_vci_ini.plen    = 4 * (r_write_to_init_cmd_count.read() + 2);
+        p_vci_ini.eop     = false;
+        p_vci_ini.trdid   = r_write_to_init_cmd_trdid.read();
+        break;
+      case INIT_CMD_UPDT_INDEX:
+        p_vci_ini.cmdval  = true;
+        p_vci_ini.address = (addr_t)(m_coherence_table[r_init_cmd_target.read()] + 4);
+        p_vci_ini.wdata   = r_write_to_init_cmd_index.read();
+        p_vci_ini.be      = 0xF;
+        p_vci_ini.plen    = 4 * (r_write_to_init_cmd_count.read() + 2);
+        p_vci_ini.trdid   = r_write_to_init_cmd_trdid.read();
+        p_vci_ini.eop     = false;
+        break;
+      case INIT_CMD_UPDT_DATA:
+        p_vci_ini.cmdval  = true;
+        p_vci_ini.address = (addr_t)(m_coherence_table[r_init_cmd_target.read()] + 4);
+        p_vci_ini.wdata   = r_write_to_init_cmd_data[r_init_cmd_cpt.read() +
+          r_write_to_init_cmd_index.read()].read();
+        p_vci_ini.be      = r_write_to_init_cmd_be[r_init_cmd_cpt.read() +r_write_to_init_cmd_index.read()].read() ;  
+        p_vci_ini.plen    = 4 * (r_write_to_init_cmd_count.read() + 2);
+        p_vci_ini.trdid   = r_write_to_init_cmd_trdid.read();
+        p_vci_ini.eop     = ( r_init_cmd_cpt.read() == (r_write_to_init_cmd_count.read()-1) );
+        break;
+
+      case INIT_CMD_SC_BRDCAST:
+        p_vci_ini.cmdval  = true;
+        p_vci_ini.address = broadcast_addr;
+        p_vci_ini.wdata   = (addr_t)r_llsc_to_init_cmd_nline.read();
+        p_vci_ini.be      = ((r_llsc_to_init_cmd_nline.read() >> 32) & 0x3);
+        p_vci_ini.plen    = 4 ;
+        p_vci_ini.eop     = true;
+        p_vci_ini.trdid   = r_llsc_to_init_cmd_trdid.read();
+        break;
+      case INIT_CMD_SC_UPDT_NLINE:
+        p_vci_ini.cmdval  = true;
+        p_vci_ini.address = (addr_t)(m_coherence_table[r_init_cmd_target.read()] + 4);
+        p_vci_ini.wdata   = (uint32_t)r_llsc_to_init_cmd_nline.read();
+        p_vci_ini.be      = ((r_llsc_to_init_cmd_nline.read() >> 32 ) & 0x3);
+        p_vci_ini.plen    = 4 * 3;
+        p_vci_ini.eop     = false;
+        p_vci_ini.trdid   = r_llsc_to_init_cmd_trdid.read();
+        break;
+      case INIT_CMD_SC_UPDT_INDEX:
+        p_vci_ini.cmdval  = true;
+        p_vci_ini.address = (addr_t)(m_coherence_table[r_init_cmd_target.read()] + 4);
+        p_vci_ini.wdata   = r_llsc_to_init_cmd_index.read();
+        p_vci_ini.be      = 0xF;
+        p_vci_ini.plen    = 4 * 3;
+        p_vci_ini.trdid   = r_llsc_to_init_cmd_trdid.read();
+        p_vci_ini.eop     = false;
+        break;
+      case INIT_CMD_SC_UPDT_DATA:
+        p_vci_ini.cmdval  = true;
+        p_vci_ini.address = (addr_t)(m_coherence_table[r_init_cmd_target.read()] + 4);
+        p_vci_ini.wdata   = r_llsc_to_init_cmd_wdata.read();
+        p_vci_ini.be      = 0xF;
+        p_vci_ini.plen    = 4 * 3;
+        p_vci_ini.trdid   = r_llsc_to_init_cmd_trdid.read();
+        p_vci_ini.eop     = true;
+        break;
+
+    } // end switch r_init_cmd_fsm
+
+    //////////////////////////////////////////////////////
+    // Response signals on the p_vci_ini port
+    //////////////////////////////////////////////////////
+
+    if ( r_init_rsp_fsm.read() == INIT_RSP_IDLE ) p_vci_ini.rspack  = true;
+    else                                          p_vci_ini.rspack  = false;
+
+    //////////////////////////////////////////////////////
+    // Response signals on the p_vci_tgt_cleanup port
+    //////////////////////////////////////////////////////
+    p_vci_tgt_cleanup.rspval = false;
+    p_vci_tgt_cleanup.rsrcid = 0;
+    p_vci_tgt_cleanup.rdata  = 0;
+    p_vci_tgt_cleanup.rpktid = 0;
+    p_vci_tgt_cleanup.rtrdid = 0;
+    p_vci_tgt_cleanup.rerror = 0;
+    p_vci_tgt_cleanup.reop   = false;
+    p_vci_tgt_cleanup.cmdack = false ;
+
+    switch(r_cleanup_fsm.read()){
+      case CLEANUP_IDLE:
+        {
+          p_vci_tgt_cleanup.cmdack = true ;
+          break;
+        }
+      case CLEANUP_RSP:
+        {
+          p_vci_tgt_cleanup.rspval = true;
+          p_vci_tgt_cleanup.rdata  = 0;
+          p_vci_tgt_cleanup.rsrcid = r_cleanup_srcid.read();
+          p_vci_tgt_cleanup.rpktid = r_cleanup_pktid.read();
+          p_vci_tgt_cleanup.rtrdid = r_cleanup_trdid.read();
+          p_vci_tgt_cleanup.rerror = 0x2 & ( (1 << vci_param::E) - 1);
+          p_vci_tgt_cleanup.reop   = 1;
+          break;
+        }
+
+    }
+
+  } // end genMoore()
+
+}} // end name space
+
+// Local Variables:
+// tab-width: 4
+// c-basic-offset: 4
+// c-file-offsets:((innamespace . 0)(inline-open . 0))
+// indent-tabs-mode: nil
+// End:
+
+// vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4
+
Index: branches/v4/modules/vci_mem_cache_v2s/caba/metadata/vci_mem_cache_v2s.sd
===================================================================
--- branches/v4/modules/vci_mem_cache_v2s/caba/metadata/vci_mem_cache_v2s.sd	(revision 371)
+++ branches/v4/modules/vci_mem_cache_v2s/caba/metadata/vci_mem_cache_v2s.sd	(revision 371)
@@ -0,0 +1,47 @@
+
+# -*- python -*-
+
+__id__ = "$Id: vci_mem_cache_v2s.sd 20 2010-04-14 03:27:59Z nipo $"
+__version__ = "$Revision: 20 $"
+
+Module('caba:vci_mem_cache_v2s',
+       classname = 'soclib::caba::VciMemCacheV2S',
+       tmpl_parameters = [parameter.Module('vci_param', default = 'caba:vci_param'),],
+       header_files = ['../source/include/vci_mem_cache_v2s.h',
+                       '../source/include/xram_transaction_v2.h',
+                       '../source/include/mem_cache_directory_v2.h',
+                       '../source/include/atomic_tab_v2.h',
+                       '../source/include/update_tab_v2.h',],
+       implementation_files = ['../source/src/vci_mem_cache_v2s.cpp',],
+       uses = [Uses('caba:base_module'),
+               Uses('common:loader'),
+               Uses('common:mapping_table'),
+               Uses('caba:generic_fifo'),
+               ],
+       ports = [Port('caba:vci_target', 'p_vci_tgt'),
+		Port('caba:vci_target','p_vci_tgt_cleanup'),
+		Port('caba:vci_initiator','p_vci_ini'),
+		Port('caba:vci_initiator','p_vci_ixr'),
+                Port('caba:bit_in', 'p_resetn', auto = 'resetn'),
+                Port('caba:clock_in', 'p_clk', auto = 'clock'),],
+       instance_parameters = [
+		parameter.Module('mtp', 'common:mapping_table'),
+		parameter.Module('mtc', 'common:mapping_table'),
+		parameter.Module('mtx', 'common:mapping_table'),
+		parameter.IntTab('vci_ixr_index'),
+		parameter.IntTab('vci_ini_index'),
+		parameter.IntTab('vci_tgt_index'),
+		parameter.IntTab('vci_tgt_index_cleanup'),
+       		parameter.Int('nways'),
+		parameter.Int('nsets'),
+		parameter.Int('nwords'),
+		],
+       extensions = [
+          'dsx:get_ident='
+          'vci_ini_index:p_vci_ini:mtc,'
+          'vci_tgt_index_cleanup:p_vci_tgt_cleanup:mtc,'
+          'vci_tgt_index:p_vci_tgt:mtp,'
+          'vci_ixr_index:p_vci_ixr:mtx',
+		'dsx:addressable=vci_tgt_index,vci_tgt_index_cleanup',
+       ],
+)
Index: branches/v4/modules/vci_mem_cache_v2s/caba/source/include/atomic_tab_v2.h
===================================================================
--- branches/v4/modules/vci_mem_cache_v2s/caba/source/include/atomic_tab_v2.h	(revision 371)
+++ branches/v4/modules/vci_mem_cache_v2s/caba/source/include/atomic_tab_v2.h	(revision 371)
@@ -0,0 +1,121 @@
+#ifndef ATOMIC_TAB_V2_H_
+#define ATOMIC_TAB_V2_H_
+
+#include <inttypes.h>
+#include <systemc>
+#include <cassert>
+#include "arithmetics.h"
+
+
+
+////////////////////////////////////////////////////////////////////////
+////////////////////////////////////////////////////////////////////////
+/*                  The atomic access tab                             */
+////////////////////////////////////////////////////////////////////////
+////////////////////////////////////////////////////////////////////////
+
+class AtomicTab{
+    typedef uint32_t size_t;
+    typedef sc_dt::sc_uint<40> addr_t;
+
+private:
+    size_t size_tab;                            // The size of the tab
+    std::vector<addr_t> addr_tab;               // Address entries
+    std::vector<bool>   valid_tab;              // Valid entries
+
+public:
+
+    AtomicTab()
+	: addr_tab(0),
+	  valid_tab(0)
+	{
+    	size_tab=0;
+    }
+
+    AtomicTab(size_t size_tab_i)
+	: addr_tab(size_tab_i),
+	  valid_tab(size_tab_i)
+	{
+	    size_tab=size_tab_i;
+    }
+
+
+    /////////////////////////////////////////////////////////////////////
+    /* The size() function returns the size of the tab */
+    /////////////////////////////////////////////////////////////////////
+    const size_t size(){
+	    return size_tab;
+    }
+
+
+    /////////////////////////////////////////////////////////////////////
+    /* The init() function initializes the transaction tab entries */
+    /////////////////////////////////////////////////////////////////////
+    void init(){
+    	for ( size_t i=0; i<size_tab; i++) {
+		    addr_tab[i]=0;
+		    valid_tab[i]=false;
+    	}
+    }
+
+
+    /////////////////////////////////////////////////////////////////////
+    /* The set() function sets an entry 
+       Arguments :
+       - id : the id of the initiator (index of the entry)
+       - addr : the address of the lock
+     */
+    /////////////////////////////////////////////////////////////////////
+    void set(const size_t id, const addr_t addr){
+	    assert( (id<size_tab) && "Atomic Tab Error : bad entry");
+	    addr_tab[id]=addr;
+	    valid_tab[id]=true;
+	    return;
+    }
+
+
+    /////////////////////////////////////////////////////////////////////
+    /* The isatomic() function tests if the SC request corresponds to an entry
+       Arguments :
+       - id : the id of the initiator (index of the entry)
+       - addr : the address of the lock
+
+       This function return true if the request corresponds
+     */
+    /////////////////////////////////////////////////////////////////////
+    bool isatomic(const size_t id, const addr_t addr){
+	    assert( (id<size_tab) && "Atomic Tab Error : bad entry");
+	    bool test=valid_tab[id];
+	    test=test && (addr == addr_tab[id]);
+	    return test;
+    }
+
+
+    /////////////////////////////////////////////////////////////////////
+    /* The reset() function resets all the entries for this lock
+       Arguments :
+       - addr : the address of the lock
+     */
+    /////////////////////////////////////////////////////////////////////
+    void reset(const addr_t addr){
+	    for(size_t i=0 ; i<size_tab ; i++){
+		    if(addr == addr_tab[i]){
+			    valid_tab[i]=false;
+		    }
+	    }
+	    return;
+    }
+
+};
+ 
+#endif
+
+// Local Variables:
+// tab-width: 4
+// c-basic-offset: 4
+// c-file-offsets:((innamespace . 0)(inline-open . 0))
+// indent-tabs-mode: nil
+// End:
+
+// vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4
+
Index: branches/v4/modules/vci_mem_cache_v2s/caba/source/include/mem_cache_directory_v2.h
===================================================================
--- branches/v4/modules/vci_mem_cache_v2s/caba/source/include/mem_cache_directory_v2.h	(revision 371)
+++ branches/v4/modules/vci_mem_cache_v2s/caba/source/include/mem_cache_directory_v2.h	(revision 371)
@@ -0,0 +1,311 @@
+#ifndef SOCLIB_CABA_MEM_CACHE_DIRECTORY_V2_H
+#define SOCLIB_CABA_MEM_CACHE_DIRECTORY_V2_H 
+
+#include <inttypes.h>
+#include <systemc>
+#include <cassert>
+#include "arithmetics.h"
+
+namespace soclib { namespace caba {
+
+  using namespace sc_core;
+
+  ////////////////////////////////////////////////////////////////////////
+  //                    A LRU entry 
+  ////////////////////////////////////////////////////////////////////////
+  class LruEntry {
+
+    public:
+
+      bool recent;            
+
+      void init()
+      {
+        recent=false;
+      }
+
+  }; // end class LruEntry
+
+  ////////////////////////////////////////////////////////////////////////
+  //                    A directory entry                               
+  ////////////////////////////////////////////////////////////////////////
+  class DirectoryEntry {
+
+    typedef uint32_t tag_t;
+    typedef uint32_t size_t;
+    typedef uint32_t copy_t;
+
+    public:
+
+    bool    valid;                  // entry valid
+    bool    is_cnt;                 // directory entry is a counter
+    bool    dirty;                  // entry dirty
+    bool    lock;                   // entry locked
+    tag_t   tag;                    // tag of the entry
+    copy_t  d_copies;               // vector of copies for data
+    copy_t  i_copies;               // vector of copies for instructions
+    size_t  count;                  // number of copies
+
+    DirectoryEntry()
+    {
+      valid    = false;
+      is_cnt   = false;
+      dirty    = false;
+      lock     = false;
+      tag      = 0;
+      d_copies = 0;
+      i_copies = 0;
+      count    = 0;
+    }
+
+    DirectoryEntry(const DirectoryEntry &source)
+    {
+      valid    = source.valid;
+      is_cnt   = source.is_cnt;
+      dirty    = source.dirty;
+      tag      = source.tag;
+      lock     = source.lock;
+      d_copies = source.d_copies;
+      i_copies = source.i_copies;
+      count    = source.count;
+    }          
+
+    /////////////////////////////////////////////////////////////////////
+    // The init() function initializes the entry 
+    /////////////////////////////////////////////////////////////////////
+    void init()
+    {
+      valid = false;
+      is_cnt= false;
+      dirty = false;
+      lock  = false;
+    }
+
+    /////////////////////////////////////////////////////////////////////
+    // The copy() function copies an existing source entry to a target 
+    /////////////////////////////////////////////////////////////////////
+    void copy(const DirectoryEntry &source)
+    {
+      valid	= source.valid;
+      is_cnt    = source.is_cnt;
+      dirty	= source.dirty;
+      tag	= source.tag;
+      lock	= source.lock;
+      d_copies	= source.d_copies;
+      i_copies	= source.i_copies;
+      count     = source.count;
+    }
+
+    ////////////////////////////////////////////////////////////////////
+    // The print() function prints the entry 
+    ////////////////////////////////////////////////////////////////////
+    void print()
+    {
+      std::cout << "Valid = " << valid << " ; IS COUNT = " << is_cnt << " ; Dirty = " << dirty << " ; Lock = " 
+        << lock << " ; Tag = " << std::hex << tag << " ; d_copies = " << d_copies << " ; i_copies = " << i_copies << " ; count = " << count << std::endl;
+    }
+
+  }; // end class DirectoryEntry
+
+  ////////////////////////////////////////////////////////////////////////
+  //                       The directory  
+  ////////////////////////////////////////////////////////////////////////
+  class CacheDirectory {
+
+    typedef sc_dt::sc_uint<40> addr_t;
+    typedef uint32_t data_t;
+    typedef uint32_t tag_t;
+    typedef uint32_t size_t;
+
+    private:
+
+    // Directory constants
+    size_t					m_ways;
+    size_t					m_sets;
+    size_t					m_words;
+    size_t					m_width;
+
+    // the directory & lru tables
+    DirectoryEntry 				**m_dir_tab;
+    LruEntry	 				**m_lru_tab;
+
+    public:
+
+    ////////////////////////
+    // Constructor
+    ////////////////////////
+    CacheDirectory( size_t ways, size_t sets, size_t words, size_t address_width)	 
+    {
+      m_ways  = ways; 
+      m_sets  = sets;
+      m_words = words;
+      m_width = address_width;
+
+      m_dir_tab = new DirectoryEntry*[sets];
+      for ( size_t i=0; i<sets; i++ ) {
+        m_dir_tab[i] = new DirectoryEntry[ways];
+        for ( size_t j=0 ; j<ways ; j++) m_dir_tab[i][j].init();
+      }
+      m_lru_tab = new LruEntry*[sets];
+      for ( size_t i=0; i<sets; i++ ) {
+        m_lru_tab[i] = new LruEntry[ways];
+        for ( size_t j=0 ; j<ways ; j++) m_lru_tab[i][j].init();
+      }
+    } // end constructor
+
+    /////////////////
+    // Destructor
+    /////////////////
+    ~CacheDirectory()
+    {
+      for(size_t i=0 ; i<m_sets ; i++){
+        delete [] m_dir_tab[i];
+        delete [] m_lru_tab[i];
+      }
+      delete [] m_dir_tab;
+      delete [] m_lru_tab;
+    } // end destructor
+
+    /////////////////////////////////////////////////////////////////////
+    // The read() function reads a directory entry. In case of hit, the
+    // LRU is updated.
+    // Arguments :
+    // - address : the address of the entry 
+    // - way : (return argument) the way of the entry in case of hit
+    // The function returns a copy of a (valid or invalid) entry  
+    /////////////////////////////////////////////////////////////////////
+    DirectoryEntry read(const addr_t &address,size_t &way)
+    {
+
+#define L2 soclib::common::uint32_log2
+      const size_t set = (size_t)(address >> (L2(m_words) + 2)) & (m_sets - 1);
+      const tag_t  tag = (tag_t)(address >> (L2(m_sets) + L2(m_words) + 2));
+#undef L2
+
+      bool hit       = false;
+      for ( size_t i=0 ; i<m_ways ; i++ ) {
+        bool equal = ( m_dir_tab[set][i].tag == tag );
+        bool valid = m_dir_tab[set][i].valid;
+        hit = equal && valid;
+        if ( hit ) {			
+          way = i;
+          break;
+        } 
+      }
+      if ( hit ) {
+        m_lru_tab[set][way].recent = true;
+        return DirectoryEntry(m_dir_tab[set][way]);
+      } else {
+        return DirectoryEntry();
+      }
+    } // end read()
+
+    /////////////////////////////////////////////////////////////////////
+    // The write function writes a new entry, 
+    // and updates the LRU bits if necessary.
+    // Arguments :
+    // - set : the set of the entry
+    // - way : the way of the entry
+    // - entry : the entry value
+    /////////////////////////////////////////////////////////////////////
+    void write(const size_t &set, const size_t &way, const DirectoryEntry &entry)
+    {
+      assert( (set<m_sets) 
+          && "Cache Directory write : The set index is invalid");
+      assert( (way<m_ways) 
+          && "Cache Directory write : The way index is invalid");
+
+      // update Directory
+      m_dir_tab[set][way].copy(entry);
+
+      // update LRU bits
+      bool all_recent = true;
+      for ( size_t i=0 ; i<m_ways ; i++ ) {
+        if ( i != way ) all_recent = m_lru_tab[set][i].recent && all_recent;
+      }
+      if ( all_recent ) {
+        for( size_t i=0 ; i<m_ways ; i++ ) m_lru_tab[set][i].recent = false;
+      } else {
+        m_lru_tab[set][way].recent = true;
+      }
+    } // end write()
+
+    /////////////////////////////////////////////////////////////////////
+    // The print() function prints a selected directory entry
+    // Arguments :
+    // - set : the set of the entry to print
+    // - way : the way of the entry to print
+    /////////////////////////////////////////////////////////////////////
+    void print(const size_t &set, const size_t &way)
+    {
+      std::cout << std::dec << " set : " << set << " ; way : " << way << " ; " ;
+      m_dir_tab[set][way].print();
+    } // end print()
+
+    /////////////////////////////////////////////////////////////////////
+    // The select() function selects a directory entry to evince.
+    // Arguments :
+    // - set   : (input argument) the set to modify
+    // - way   : (return argument) the way to evince
+    /////////////////////////////////////////////////////////////////////
+    DirectoryEntry select(const size_t &set, size_t &way)
+    {
+      assert( (set < m_sets) 
+          && "Cache Directory : (select) The set index is invalid");
+
+      for(size_t i=0; i<m_ways; i++){
+        if(!m_dir_tab[set][i].valid){
+          way=i;
+          return DirectoryEntry(m_dir_tab[set][way]);
+        }
+      }
+      for(size_t i=0; i<m_ways; i++){
+        if(!(m_lru_tab[set][i].recent) && !(m_dir_tab[set][i].lock)){
+          way=i;
+          return DirectoryEntry(m_dir_tab[set][way]);
+        }
+      }
+      for(size_t i=0; i<m_ways; i++){
+        if( !(m_lru_tab[set][i].recent) && (m_dir_tab[set][i].lock)){
+          way=i;
+          return DirectoryEntry(m_dir_tab[set][way]);
+        }
+      }
+      for(size_t i=0; i<m_ways; i++){
+        if( (m_lru_tab[set][i].recent) && !(m_dir_tab[set][i].lock)){
+          way=i;
+          return DirectoryEntry(m_dir_tab[set][way]);
+        }
+      }
+      way = 0;
+      return DirectoryEntry(m_dir_tab[set][0]);
+    } // end select()
+
+    /////////////////////////////////////////////////////////////////////
+    // 		Global initialisation function
+    /////////////////////////////////////////////////////////////////////
+    void init()
+    {
+      for ( size_t set=0 ; set<m_sets ; set++ ) {
+        for ( size_t way=0 ; way<m_ways ; way++ ) {
+          m_dir_tab[set][way].init();
+          m_lru_tab[set][way].init();
+        }
+      }
+    } // end init()
+
+  }; // end class CacheDirectory
+
+}} // end namespaces
+
+#endif
+
+// Local Variables:
+// tab-width: 4
+// c-basic-offset: 4
+// c-file-offsets:((innamespace . 0)(inline-open . 0))
+// indent-tabs-mode: nil
+// End:
+
+// vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4
+
Index: branches/v4/modules/vci_mem_cache_v2s/caba/source/include/update_tab_v2.h
===================================================================
--- branches/v4/modules/vci_mem_cache_v2s/caba/source/include/update_tab_v2.h	(revision 371)
+++ branches/v4/modules/vci_mem_cache_v2s/caba/source/include/update_tab_v2.h	(revision 371)
@@ -0,0 +1,402 @@
+#ifndef UPDATE_TAB_V2_H_
+#define UPDATE_TAB_V2_H_
+
+#include <inttypes.h>
+#include <systemc>
+#include <cassert>
+#include "arithmetics.h"
+
+////////////////////////////////////////////////////////////////////////
+//                  An update tab entry    
+////////////////////////////////////////////////////////////////////////
+class UpdateTabEntry {
+  typedef uint32_t size_t;
+  typedef sc_dt::sc_uint<40> addr_t;
+
+  public:
+  bool 	valid;                // It is a valid pending transaction
+  bool	update;               // It is an update transaction
+  bool  brdcast;              // It is a broadcast invalidate
+  bool  rsp;                  // It needs a response to the initiator
+  size_t 	srcid;        // The srcid of the initiator which wrote the data
+  size_t 	trdid;        // The trdid of the initiator which wrote the data
+  size_t 	pktid;        // The pktid of the initiator which wrote the data
+  addr_t	nline;	      // The identifier of the cache line
+  size_t 	count;        // The number of acknowledge responses to receive
+
+  UpdateTabEntry(){
+    valid	= false;
+    update  = false;
+    brdcast = false;
+    rsp     = false;
+    srcid	= 0;
+    trdid	= 0;
+    pktid	= 0;
+    nline	= 0;
+    count	= 0;
+  }
+
+  UpdateTabEntry(bool   i_valid, 
+      bool   i_update,
+      bool   i_brdcast,
+      bool   i_rsp,
+      size_t i_srcid, 
+      size_t i_trdid, 
+      size_t i_pktid, 
+      addr_t i_nline,
+      size_t i_count) 
+  {
+    valid		= i_valid;
+    update	    = i_update;
+    brdcast     = i_brdcast;
+    rsp         = i_rsp;
+    srcid		= i_srcid;
+    trdid		= i_trdid;
+    pktid		= i_pktid;
+    nline		= i_nline;
+    count		= i_count;
+  }
+
+  UpdateTabEntry(const UpdateTabEntry &source)
+  {
+    valid   = source.valid;
+    update  = source.update;
+    brdcast = source.brdcast;
+    rsp     = source.rsp;
+    srcid   = source.srcid;
+    trdid   = source.trdid;
+    pktid   = source.pktid;
+    nline   = source.nline;
+    count   = source.count;
+  }
+
+  ////////////////////////////////////////////////////
+  // The init() function initializes the entry 
+  ///////////////////////////////////////////////////
+  void init()
+  {
+    valid  = false;
+    update = false;
+    brdcast= false;
+    rsp    = false;
+    srcid  = 0;
+    trdid  = 0;
+    pktid  = 0;
+    nline  = 0;
+    count  = 0;
+  }
+
+  ////////////////////////////////////////////////////////////////////
+  // The copy() function copies an existing entry
+  // Its arguments are :
+  // - source : the update tab entry to copy
+  ////////////////////////////////////////////////////////////////////
+  void copy(const UpdateTabEntry &source)
+  {
+    valid  = source.valid;
+    update = source.update;
+    brdcast= source.brdcast;
+    rsp    = source.rsp;
+    srcid  = source.srcid;
+    trdid  = source.trdid;
+    pktid  = source.pktid;
+    nline  = source.nline;
+    count  = source.count;
+  }
+
+  ////////////////////////////////////////////////////////////////////
+  // The print() function prints the entry  
+  ////////////////////////////////////////////////////////////////////
+  void print(){
+    std::cout << std::dec << "valid  = " << valid  << std::endl;
+    std::cout << "update = " << update << std::endl;
+    std::cout << "brdcast= " << brdcast<< std::endl;
+    std::cout << "rsp    = " << rsp    << std::endl;
+    std::cout << "srcid  = " << srcid  << std::endl; 
+    std::cout << "trdid  = " << trdid  << std::endl; 
+    std::cout << "pktid  = " << pktid  << std::endl; 
+    std::cout << std::hex << "nline  = " << nline  << std::endl;
+    std::cout << std::dec << "count  = " << count  << std::endl;
+  }
+};
+
+////////////////////////////////////////////////////////////////////////
+//                        The update tab             
+////////////////////////////////////////////////////////////////////////
+class UpdateTab{
+
+  typedef uint32_t size_t;
+  typedef sc_dt::sc_uint<40> addr_t;
+
+  private:
+  size_t size_tab;
+  std::vector<UpdateTabEntry> tab;
+
+  public:
+
+  UpdateTab()
+    : tab(0)
+  {
+    size_tab=0;
+  }
+
+  UpdateTab(size_t size_tab_i)
+    : tab(size_tab_i)
+  {
+    size_tab=size_tab_i;
+  }
+
+  ////////////////////////////////////////////////////////////////////
+  // The size() function returns the size of the tab  
+  ////////////////////////////////////////////////////////////////////
+  const size_t size(){
+    return size_tab;
+  }
+
+
+  ////////////////////////////////////////////////////////////////////
+  // The size() function returns the size of the tab  
+  ////////////////////////////////////////////////////////////////////
+  void print(){
+    for(size_t i=0; i<size_tab; i++) {
+      std::cout << "UPDATE TAB ENTRY " << std::dec << i << "--------" << std::endl;
+      tab[i].print();
+    }
+    return;
+  }
+
+
+  /////////////////////////////////////////////////////////////////////
+  // The init() function initializes the tab 
+  /////////////////////////////////////////////////////////////////////
+  void init(){
+    for ( size_t i=0; i<size_tab; i++) {
+      tab[i].init();
+    }
+  }
+
+
+  /////////////////////////////////////////////////////////////////////
+  // The reads() function reads an entry 
+  // Arguments :
+  // - entry : the entry to read
+  // This function returns a copy of the entry.
+  /////////////////////////////////////////////////////////////////////
+  UpdateTabEntry read (size_t entry)
+  {
+    assert(entry<size_tab && "Bad Update Tab Entry");
+    return UpdateTabEntry(tab[entry]);
+  }
+
+  ///////////////////////////////////////////////////////////////////////////
+  // The set() function writes an entry in the Update Table
+  // Arguments :
+  // - update : transaction type (bool)
+  // - srcid : srcid of the initiator
+  // - trdid : trdid of the initiator
+  // - pktid : pktid of the initiator
+  // - count : number of expected responses
+  // - index : (return argument) index of the selected entry
+  // This function returns true if the write successed (an entry was empty).
+  ///////////////////////////////////////////////////////////////////////////
+  bool set(const bool	update,
+      const bool   brdcast,
+      const bool   rsp,
+      const size_t srcid,
+      const size_t trdid,
+      const size_t pktid,
+      const addr_t nline,
+      const size_t count,
+      size_t &index)
+  {
+    for ( size_t i=0 ; i<size_tab ; i++ ) {
+      if( !tab[i].valid ) {
+        tab[i].valid		= true;
+        tab[i].update		= update;
+        tab[i].brdcast      = brdcast;
+        tab[i].rsp          = rsp;
+        tab[i].srcid		= (size_t) srcid;
+        tab[i].trdid		= (size_t) trdid;
+        tab[i].pktid		= (size_t) pktid;
+        tab[i].nline		= (addr_t) nline;
+        tab[i].count		= (size_t) count;
+        index			    = i;
+        return true;
+      }
+    }
+    return false;
+  } // end set()
+
+  /////////////////////////////////////////////////////////////////////
+  // The decrement() function decrements the counter for a given entry.
+  // Arguments :
+  // - index   : the index of the entry
+  // - counter : (return argument) value of the counter after decrement
+  // This function returns true if the entry is valid.
+  /////////////////////////////////////////////////////////////////////
+  bool decrement( const size_t index,
+      size_t &counter ) 
+  {
+    assert((index<size_tab) && "Bad Update Tab Entry");
+    if ( tab[index].valid ) {
+      tab[index].count--;
+      counter = tab[index].count;
+      return true;
+    } else {
+      return false;
+    }
+  }
+
+  /////////////////////////////////////////////////////////////////////
+  // The is_full() function returns true if the table is full
+  /////////////////////////////////////////////////////////////////////
+  bool is_full()
+  {
+    for(size_t i = 0 ; i < size_tab ; i++){
+      if(!tab[i].valid){
+        return false;
+      }
+    }
+    return true;
+  }
+
+  /////////////////////////////////////////////////////////////////////
+  // The need_rsp() function returns the need of a response
+  // Arguments :
+  // - index : the index of the entry
+  /////////////////////////////////////////////////////////////////////
+  bool need_rsp(const size_t index)
+  {
+    assert(index<size_tab && "Bad Update Tab Entry");
+    return tab[index].rsp;	
+  }
+
+  /////////////////////////////////////////////////////////////////////
+  // The is_update() function returns the transaction type
+  // Arguments :
+  // - index : the index of the entry
+  /////////////////////////////////////////////////////////////////////
+  bool is_brdcast(const size_t index)
+  {
+    assert(index<size_tab && "Bad Update Tab Entry");
+    return tab[index].brdcast;	
+  }
+
+  /////////////////////////////////////////////////////////////////////
+  // The is_update() function returns the transaction type
+  // Arguments :
+  // - index : the index of the entry
+  /////////////////////////////////////////////////////////////////////
+  bool is_update(const size_t index)
+  {
+    assert(index<size_tab && "Bad Update Tab Entry");
+    return tab[index].update;	
+  }
+
+  /////////////////////////////////////////////////////////////////////
+  // The srcid() function returns the srcid value
+  // Arguments :
+  // - index : the index of the entry
+  /////////////////////////////////////////////////////////////////////
+  size_t srcid(const size_t index)
+  {
+    assert(index<size_tab && "Bad Update Tab Entry");
+    return tab[index].srcid;	
+  }
+
+  /////////////////////////////////////////////////////////////////////
+  // The trdid() function returns the trdid value
+  // Arguments :
+  // - index : the index of the entry
+  /////////////////////////////////////////////////////////////////////
+  size_t trdid(const size_t index)
+  {
+    assert(index<size_tab && "Bad Update Tab Entry");
+    return tab[index].trdid;	
+  }
+
+  /////////////////////////////////////////////////////////////////////
+  // The pktid() function returns the pktid value
+  // Arguments :
+  // - index : the index of the entry
+  /////////////////////////////////////////////////////////////////////
+  size_t pktid(const size_t index)
+  {
+    assert(index<size_tab && "Bad Update Tab Entry");
+    return tab[index].pktid;	
+  }
+
+  /////////////////////////////////////////////////////////////////////
+  // The nline() function returns the nline value
+  // Arguments :
+  // - index : the index of the entry
+  /////////////////////////////////////////////////////////////////////
+  addr_t nline(const size_t index)
+  {
+    assert(index<size_tab && "Bad Update Tab Entry");
+    return tab[index].nline;
+  }
+
+  /////////////////////////////////////////////////////////////////////
+  // The search_inval() function returns the index of the entry in UPT
+  // Arguments :
+  // - nline : the line number of the entry in the directory
+  /////////////////////////////////////////////////////////////////////
+  bool search_inval(const addr_t nline,size_t &index)
+  {
+    size_t i ;
+
+    for (i = 0 ; i < size_tab ; i++){
+      if((tab[i].nline == nline) && tab[i].valid){
+        if(!tab[i].update){
+          index = i ;
+          return true;
+        }
+      }
+    }
+    return false;
+  }
+
+  /////////////////////////////////////////////////////////////////////
+  // The read_nline() function returns the index of the entry in UPT
+  // Arguments :
+  // - nline : the line number of the entry in the directory
+  /////////////////////////////////////////////////////////////////////
+  bool read_nline(const addr_t nline,size_t &index) 
+  {
+    size_t i ;
+
+    for (i = 0 ; i < size_tab ; i++){
+      if((tab[i].nline == nline) && tab[i].valid){
+        index = i ;
+        return true;
+      }
+    }
+    return false;
+  }
+
+  /////////////////////////////////////////////////////////////////////
+  // The clear() function erases an entry of the tab
+  // Arguments :
+  // - index : the index of the entry
+  /////////////////////////////////////////////////////////////////////       
+  void clear(const size_t index)
+  {
+    assert(index<size_tab && "Bad Update Tab Entry");
+    tab[index].valid=false;
+    return;	
+  }
+
+};
+
+#endif
+
+// Local Variables:
+// tab-width: 4
+// c-basic-offset: 4
+// c-file-offsets:((innamespace . 0)(inline-open . 0))
+// indent-tabs-mode: nil
+// End:
+
+// vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4
+
Index: branches/v4/modules/vci_mem_cache_v2s/caba/source/include/vci_mem_cache_v2s.h
===================================================================
--- branches/v4/modules/vci_mem_cache_v2s/caba/source/include/vci_mem_cache_v2s.h	(revision 371)
+++ branches/v4/modules/vci_mem_cache_v2s/caba/source/include/vci_mem_cache_v2s.h	(revision 371)
@@ -0,0 +1,653 @@
+/* -*- c++ -*-
+ * File         : vci_mem_cache_v2s.h
+ * Date         : 26/10/2008
+ * Copyright    : UPMC / LIP6
+ * Authors      : Alain Greiner / Eric Guthmuller
+ *
+ * SOCLIB_LGPL_HEADER_BEGIN
+ *
+ * This file is part of SoCLib, GNU LGPLv2.1.
+ *
+ * SoCLib is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU Lesser General Public License as published
+ * by the Free Software Foundation; version 2.1 of the License.
+ *
+ * SoCLib is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with SoCLib; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301 USA
+ *
+ * SOCLIB_LGPL_HEADER_END
+ *
+ * Maintainers: alain eric.guthmuller@polytechnique.edu
+ */
+/*
+ *
+ * Modifications done by Christophe Choichillon on the 7/04/2009:
+ * - Adding new states in the CLEANUP FSM : CLEANUP_UPT_LOCK and CLEANUP_UPT_WRITE
+ * - Adding a new VCI target port for the CLEANUP network
+ * - Adding new state in the ALLOC_UPT_FSM : ALLOC_UPT_CLEANUP
+ * 
+ * Modifications to do :
+ * - Adding new variables used by the CLEANUP FSM
+ *
+ */
+
+#ifndef SOCLIB_CABA_MEM_CACHE_V2S_H
+#define SOCLIB_CABA_MEM_CACHE_V2S_H
+
+#include <inttypes.h>
+#include <systemc>
+#include <list>
+#include <cassert>
+#include "arithmetics.h"
+#include "alloc_elems.h"
+#include "caba_base_module.h"
+#include "vci_target.h"
+#include "vci_initiator.h"
+#include "generic_fifo.h"
+#include "mapping_table.h"
+#include "int_tab.h"
+#include "mem_cache_directory_v2.h"
+#include "xram_transaction_v2.h"
+#include "update_tab_v2.h"
+#include "atomic_tab_v2.h"
+
+#define TRANSACTION_TAB_LINES 4     // Number of lines in the transaction tab
+#define UPDATE_TAB_LINES 4          // Number of lines in the update tab
+#define BROADCAST_ADDR 0x0000000003 // Address to send the broadcast invalidate
+
+namespace soclib {  namespace caba {
+  using namespace sc_core;
+
+  template<typename vci_param>
+    class VciMemCacheV2S
+    : public soclib::caba::BaseModule
+    {
+      typedef sc_dt::sc_uint<40> addr_t;
+      typedef typename vci_param::fast_addr_t vci_addr_t;
+      typedef uint32_t data_t;
+      typedef uint32_t tag_t;
+      typedef uint32_t size_t;
+      typedef uint32_t be_t;
+      typedef uint32_t copy_t;
+
+      /* States of the TGT_CMD fsm */
+      enum tgt_cmd_fsm_state_e{
+        TGT_CMD_IDLE,
+        TGT_CMD_READ,
+        TGT_CMD_READ_EOP,
+        TGT_CMD_WRITE,
+        TGT_CMD_ATOMIC,
+      };
+
+      /* States of the TGT_RSP fsm */
+      enum tgt_rsp_fsm_state_e{
+        TGT_RSP_READ_IDLE,
+        TGT_RSP_WRITE_IDLE,
+        TGT_RSP_LLSC_IDLE,
+        TGT_RSP_XRAM_IDLE,
+        TGT_RSP_INIT_IDLE,
+        TGT_RSP_CLEANUP_IDLE,
+        TGT_RSP_READ,
+        TGT_RSP_WRITE,
+        TGT_RSP_LLSC,
+        TGT_RSP_XRAM,
+        TGT_RSP_INIT,
+        TGT_RSP_CLEANUP,
+      };
+
+      /* States of the INIT_CMD fsm */
+      enum init_cmd_fsm_state_e{
+        INIT_CMD_INVAL_IDLE,
+        INIT_CMD_INVAL_SEL,
+        INIT_CMD_INVAL_NLINE,
+        INIT_CMD_UPDT_IDLE,
+        INIT_CMD_UPDT_SEL,
+        INIT_CMD_BRDCAST,
+        INIT_CMD_UPDT_NLINE,
+        INIT_CMD_UPDT_INDEX,
+        INIT_CMD_UPDT_DATA,
+        INIT_CMD_SC_UPDT_IDLE,
+        INIT_CMD_SC_UPDT_SEL,
+        INIT_CMD_SC_BRDCAST,
+        INIT_CMD_SC_UPDT_NLINE,
+        INIT_CMD_SC_UPDT_INDEX,
+        INIT_CMD_SC_UPDT_DATA,
+      };
+
+      /* States of the INIT_RSP fsm */
+      enum init_rsp_fsm_state_e{
+        INIT_RSP_IDLE,
+        INIT_RSP_UPT_LOCK,
+        INIT_RSP_UPT_CLEAR,
+        INIT_RSP_END,
+      };
+
+      /* States of the READ fsm */
+      enum read_fsm_state_e{
+        READ_IDLE,
+        READ_DIR_LOCK,
+        READ_DIR_HIT,
+        READ_RSP,
+        READ_TRT_LOCK,
+        READ_TRT_SET,
+        READ_XRAM_REQ,
+      };
+
+      /* States of the WRITE fsm */
+      enum write_fsm_state_e{
+        WRITE_IDLE,
+        WRITE_NEXT,
+        WRITE_DIR_LOCK,
+        WRITE_DIR_HIT_READ,
+        WRITE_DIR_HIT,
+        WRITE_DIR_HIT_RSP,
+        WRITE_UPT_LOCK,
+        WRITE_WAIT_UPT,
+        WRITE_UPDATE,
+        WRITE_RSP,
+        WRITE_TRT_LOCK,
+        WRITE_TRT_DATA,
+        WRITE_TRT_SET,
+        WRITE_WAIT_TRT,
+        WRITE_XRAM_REQ,
+        WRITE_TRT_WRITE_LOCK,
+        WRITE_INVAL_LOCK,
+        WRITE_DIR_INVAL,
+        WRITE_INVAL,
+        WRITE_XRAM_SEND,
+      };
+
+      /* States of the IXR_RSP fsm */
+      enum ixr_rsp_fsm_state_e{
+        IXR_RSP_IDLE,
+        IXR_RSP_ACK,
+        IXR_RSP_TRT_ERASE,
+        IXR_RSP_TRT_READ,
+      };
+
+      /* States of the XRAM_RSP fsm */
+      enum xram_rsp_fsm_state_e{
+        XRAM_RSP_IDLE,
+        XRAM_RSP_TRT_COPY,
+        XRAM_RSP_TRT_DIRTY,
+        XRAM_RSP_DIR_LOCK,
+        XRAM_RSP_DIR_UPDT,
+        XRAM_RSP_DIR_RSP,
+        XRAM_RSP_INVAL_LOCK,
+        XRAM_RSP_INVAL_WAIT,
+        XRAM_RSP_INVAL,
+        XRAM_RSP_WRITE_DIRTY,
+      };
+
+      /* States of the IXR_CMD fsm */
+      enum ixr_cmd_fsm_state_e{
+        IXR_CMD_READ_IDLE,
+        IXR_CMD_WRITE_IDLE,
+        IXR_CMD_LLSC_IDLE,
+        IXR_CMD_XRAM_IDLE,
+        IXR_CMD_READ_NLINE,
+        IXR_CMD_WRITE_NLINE,
+        IXR_CMD_LLSC_NLINE,
+        IXR_CMD_XRAM_DATA,
+      };
+
+      /* States of the LLSC fsm */
+      enum llsc_fsm_state_e{
+        LLSC_IDLE,
+        LL_DIR_LOCK,
+        LL_DIR_HIT,
+        LL_RSP,
+        SC_DIR_LOCK,
+        SC_DIR_HIT,
+        SC_UPT_LOCK,
+        SC_WAIT_UPT,
+        SC_UPDATE,
+        SC_TRT_LOCK,
+        SC_INVAL_LOCK,
+        SC_DIR_INVAL,
+        SC_INVAL,
+        SC_XRAM_SEND,
+        SC_RSP_FALSE,
+        SC_RSP_TRUE,
+        LLSC_TRT_LOCK,
+        LLSC_TRT_SET,
+        LLSC_XRAM_REQ,
+      };
+
+      /* States of the CLEANUP fsm */
+      enum cleanup_fsm_state_e{
+        CLEANUP_IDLE,
+        CLEANUP_DIR_LOCK,
+        CLEANUP_DIR_WRITE,
+        CLEANUP_UPT_LOCK,
+        CLEANUP_UPT_WRITE,
+        CLEANUP_WRITE_RSP,
+        CLEANUP_RSP,
+      };
+
+      /* States of the ALLOC_DIR fsm */
+      enum alloc_dir_fsm_state_e{
+        ALLOC_DIR_READ,
+        ALLOC_DIR_WRITE,
+        ALLOC_DIR_LLSC,
+        ALLOC_DIR_CLEANUP,
+        ALLOC_DIR_XRAM_RSP,
+      };
+
+      /* States of the ALLOC_TRT fsm */
+      enum alloc_trt_fsm_state_e{
+        ALLOC_TRT_READ,
+        ALLOC_TRT_WRITE,
+        ALLOC_TRT_LLSC,
+        ALLOC_TRT_XRAM_RSP,
+        ALLOC_TRT_IXR_RSP,
+      };
+
+      /* States of the ALLOC_UPT fsm */
+      enum alloc_upt_fsm_state_e{
+        ALLOC_UPT_WRITE,
+        ALLOC_UPT_XRAM_RSP,
+        ALLOC_UPT_INIT_RSP,
+        ALLOC_UPT_CLEANUP,
+        ALLOC_UPT_LLSC,
+      };
+
+      uint32_t	   m_cpt_cycles;            // Counter of cycles 
+      uint32_t	   m_cpt_read;              // Number of READ transactions
+      uint32_t	   m_cpt_read_miss;         // Number of MISS READ 
+      uint32_t	   m_cpt_write;             // Number of WRITE transactions
+      uint32_t	   m_cpt_write_miss;        // Number of MISS WRITE
+      uint32_t     m_cpt_write_cells;	    // Cumulated length for WRITE transactions
+      uint32_t     m_cpt_write_dirty;	    // Cumulated length for WRITE transactions
+      uint32_t	   m_cpt_update;            // Number of UPDATE transactions
+      uint32_t	   m_cpt_update_mult;       // Number of targets for UPDATE
+      uint32_t	   m_cpt_inval;             // Number of INVAL  transactions
+      uint32_t	   m_cpt_inval_mult;        // Number of targets for INVAL  
+      uint32_t	   m_cpt_inval_brdcast;     // Number of BROADCAST INVAL  
+      uint32_t	   m_cpt_cleanup;           // Number of CLEANUP transactions
+      uint32_t	   m_cpt_ll;                // Number of LL transactions
+      uint32_t	   m_cpt_sc;                // Number of SC transactions
+
+      protected:
+
+      SC_HAS_PROCESS(VciMemCacheV2S);
+
+      public:
+      sc_in<bool> 			  	p_clk;
+      sc_in<bool> 			  	p_resetn;
+      soclib::caba::VciTarget<vci_param>    	p_vci_tgt;
+      soclib::caba::VciTarget<vci_param>    	p_vci_tgt_cleanup;
+      soclib::caba::VciInitiator<vci_param> 	p_vci_ini;	
+      soclib::caba::VciInitiator<vci_param> 	p_vci_ixr;
+
+      VciMemCacheV2S(
+          sc_module_name name,                              // Instance Name 
+          const soclib::common::MappingTable &mtp,          // Mapping table for primary requets
+          const soclib::common::MappingTable &mtc,          // Mapping table for coherence requets
+          const soclib::common::MappingTable &mtx,          // Mapping table for XRAM
+          const soclib::common::IntTab &vci_ixr_index,      // VCI port to XRAM (initiator)
+          const soclib::common::IntTab &vci_ini_index,      // VCI port to PROC (initiator)
+          const soclib::common::IntTab &vci_tgt_index,      // VCI port to PROC (target)
+          const soclib::common::IntTab &vci_tgt_index_cleanup,    // VCI port to PROC (target) for cleanup
+          size_t nways,                                   // Number of ways per set 
+          size_t nsets,                                   // Number of sets
+          size_t nwords);                                 // Number of words per line
+
+      ~VciMemCacheV2S();
+
+      void transition();
+
+      void genMoore();
+
+      void print_stats();
+
+      private:
+
+      // Component attributes
+      const size_t              m_initiators;           // Number of initiators
+      const size_t              m_ways;                 // Number of ways in a set
+      const size_t              m_sets;                 // Number of cache sets
+      const size_t              m_words;		        // Number of words in a line
+      const size_t              m_srcid_ixr;		    // Srcid for requests to XRAM 
+      const size_t              m_srcid_ini;		    // Srcid for requests to processors
+      std::list<soclib::common::Segment>  m_seglist;    // memory cached into the cache
+      std::list<soclib::common::Segment>  m_cseglist;   // coherence segment for the cache
+      vci_addr_t        		*m_coherence_table; 	// address(srcid)
+      AtomicTab                 m_atomic_tab;           // atomic access table
+      TransactionTab      		m_transaction_tab;	    // xram transaction table
+      UpdateTab                 m_update_tab;		    // pending update & invalidate 
+      CacheDirectory			m_cache_directory;	    // data cache directory
+
+      data_t	        	       ***m_cache_data;		// data array[set][way][word]
+
+      // adress masks
+      const soclib::common::AddressMaskingTable<vci_addr_t>   m_x;
+      const soclib::common::AddressMaskingTable<vci_addr_t>   m_y;
+      const soclib::common::AddressMaskingTable<vci_addr_t>   m_z;
+      const soclib::common::AddressMaskingTable<vci_addr_t>   m_nline; 
+
+      //////////////////////////////////////////////////
+      // Others registers
+      //////////////////////////////////////////////////
+      sc_signal<size_t>   r_copies_limit; // Limit of the number of copies for one line
+
+      //////////////////////////////////////////////////
+      // Registers controlled by the TGT_CMD fsm
+      //////////////////////////////////////////////////
+
+      // Fifo between TGT_CMD fsm and READ fsm
+      GenericFifo<uint64_t>  m_cmd_read_addr_fifo;
+      GenericFifo<size_t>    m_cmd_read_length_fifo;
+      GenericFifo<size_t>    m_cmd_read_srcid_fifo;
+      GenericFifo<size_t>    m_cmd_read_trdid_fifo;
+      GenericFifo<size_t>    m_cmd_read_pktid_fifo;
+
+      // Fifo between TGT_CMD fsm and WRITE fsm    
+      GenericFifo<uint64_t>  m_cmd_write_addr_fifo;
+      GenericFifo<bool>      m_cmd_write_eop_fifo;
+      GenericFifo<size_t>    m_cmd_write_srcid_fifo;
+      GenericFifo<size_t>    m_cmd_write_trdid_fifo;
+      GenericFifo<size_t>    m_cmd_write_pktid_fifo;
+      GenericFifo<data_t>    m_cmd_write_data_fifo;
+      GenericFifo<be_t>	     m_cmd_write_be_fifo;
+
+      // Fifo between TGT_CMD fsm and LLSC fsm
+      GenericFifo<uint64_t>  m_cmd_llsc_addr_fifo;
+      GenericFifo<bool>      m_cmd_llsc_sc_fifo;
+      GenericFifo<size_t>    m_cmd_llsc_srcid_fifo;
+      GenericFifo<size_t>    m_cmd_llsc_trdid_fifo;
+      GenericFifo<size_t>    m_cmd_llsc_pktid_fifo;
+      GenericFifo<data_t>    m_cmd_llsc_wdata_fifo;
+
+      sc_signal<int>         r_tgt_cmd_fsm;
+
+      sc_signal<size_t>	     r_index;
+      size_t nseg;
+      size_t ncseg;
+      soclib::common::Segment  **m_seg;
+      soclib::common::Segment  **m_cseg;
+      ///////////////////////////////////////////////////////
+      // Registers controlled by the READ fsm
+      ///////////////////////////////////////////////////////
+
+      sc_signal<int>         r_read_fsm;        // FSM state 
+      sc_signal<copy_t>      r_read_d_copies;   // bit-vector of copies 
+      sc_signal<copy_t>      r_read_i_copies;   // bit-vector of copies 
+      sc_signal<tag_t>       r_read_tag;	    // cache line tag (in directory)
+      sc_signal<bool>        r_read_is_cnt;	    // is_cnt bit (in directory)
+      sc_signal<bool>        r_read_lock;	    // lock bit (in directory)
+      sc_signal<bool>        r_read_dirty;	    // dirty bit (in directory)
+      sc_signal<size_t>      r_read_count;      // number of copies
+      sc_signal<data_t>     *r_read_data;       // data (one cache line)
+      sc_signal<size_t>      r_read_way;        // associative way (in cache)
+      sc_signal<size_t>      r_read_trt_index;  // Transaction Table index
+
+      // Buffer between READ fsm and IXR_CMD fsm (ask a missing cache line to XRAM)   
+      sc_signal<bool>        r_read_to_ixr_cmd_req;     // valid request
+      sc_signal<addr_t>      r_read_to_ixr_cmd_nline;   // cache line index
+      sc_signal<size_t>      r_read_to_ixr_cmd_trdid;   // index in Transaction Table
+
+      // Buffer between READ fsm and TGT_RSP fsm (send a hit read response to L1 cache)
+      sc_signal<bool>	   r_read_to_tgt_rsp_req;       // valid request
+      sc_signal<size_t>	   r_read_to_tgt_rsp_srcid;	    // Transaction srcid
+      sc_signal<size_t>	   r_read_to_tgt_rsp_trdid;	    // Transaction trdid
+      sc_signal<size_t>	   r_read_to_tgt_rsp_pktid;	    // Transaction pktid
+      sc_signal<data_t>   *r_read_to_tgt_rsp_data;	    // data (one cache line)
+      sc_signal<size_t>    r_read_to_tgt_rsp_word;      // first word of the response
+      sc_signal<size_t>    r_read_to_tgt_rsp_length;    // length of the response
+
+      ///////////////////////////////////////////////////////////////
+      // Registers controlled by the WRITE fsm
+      ///////////////////////////////////////////////////////////////
+
+      sc_signal<int>       r_write_fsm;             // FSM state
+      sc_signal<addr_t>	   r_write_address;         // first word address
+      sc_signal<size_t>    r_write_word_index;      // first word index in line
+      sc_signal<size_t>    r_write_word_count;      // number of words in line
+      sc_signal<size_t>    r_write_srcid;           // transaction srcid
+      sc_signal<size_t>    r_write_trdid;           // transaction trdid
+      sc_signal<size_t>    r_write_pktid;           // transaction pktid
+      sc_signal<data_t>	  *r_write_data;            // data (one cache line)	
+      sc_signal<be_t>     *r_write_be;              // one byte enable per word
+      sc_signal<bool>      r_write_byte;            // is it a byte write
+      sc_signal<bool>      r_write_is_cnt;          // is_cnt bit (in directory)
+      sc_signal<bool>      r_write_lock;            // lock bit (in directory)
+      sc_signal<tag_t>     r_write_tag;             // cache line tag (in directory)
+      sc_signal<copy_t>    r_write_d_copies;        // bit vector of copies
+      sc_signal<copy_t>    r_write_i_copies;        // bit vector of copies
+      sc_signal<size_t>	   r_write_count;           // number of copies
+      sc_signal<size_t>	   r_write_way;		        // way of the line
+      sc_signal<size_t>    r_write_trt_index;	    // index in Transaction Table
+      sc_signal<size_t>    r_write_upt_index;	    // index in Update Table
+
+      // Buffer between WRITE fsm and TGT_RSP fsm (acknowledge a write command from L1)
+      sc_signal<bool>      r_write_to_tgt_rsp_req;		// valid request
+      sc_signal<size_t>    r_write_to_tgt_rsp_srcid;    // transaction srcid
+      sc_signal<size_t>    r_write_to_tgt_rsp_trdid;	// transaction trdid
+      sc_signal<size_t>    r_write_to_tgt_rsp_pktid;	// transaction pktid
+
+      // Buffer between WRITE fsm and IXR_CMD fsm (ask a missing cache line to XRAM) 
+      sc_signal<bool>	   r_write_to_ixr_cmd_req;      // valid request
+      sc_signal<bool>	   r_write_to_ixr_cmd_write;    // write request
+      sc_signal<addr_t>    r_write_to_ixr_cmd_nline; 	// cache line index
+      sc_signal<data_t>	  *r_write_to_ixr_cmd_data;	    // cache line data
+      sc_signal<size_t>    r_write_to_ixr_cmd_trdid;	// index in Transaction Table
+
+      // Buffer between WRITE fsm and INIT_CMD fsm (Update/Invalidate L1 caches)
+      sc_signal<bool>	   r_write_to_init_cmd_req;         // valid request
+      sc_signal<bool>	   r_write_to_init_cmd_brdcast;     // brdcast request
+      sc_signal<addr_t>	   r_write_to_init_cmd_nline;	    // cache line index
+      sc_signal<size_t>	   r_write_to_init_cmd_trdid;	    // index in Update Table
+      sc_signal<copy_t>    r_write_to_init_cmd_d_copies;    // bit_vector of L1 to update
+      sc_signal<data_t>   *r_write_to_init_cmd_data;	    // data (one cache line)
+      sc_signal<bool>     *r_write_to_init_cmd_we;	        // word enable
+      sc_signal<size_t>	   r_write_to_init_cmd_count;	    // number of words in line
+      sc_signal<size_t>	   r_write_to_init_cmd_index;	    // index of first word in line
+
+      /////////////////////////////////////////////////////////
+      // Registers controlled by INIT_RSP fsm
+      //////////////////////////////////////////////////////////
+
+      sc_signal<int> 	   r_init_rsp_fsm;        // FSM state
+      sc_signal<size_t>	   r_init_rsp_upt_index;  // index in the Update Table
+      sc_signal<size_t>	   r_init_rsp_srcid;	  // pending write srcid      
+      sc_signal<size_t>	   r_init_rsp_trdid;	  // pending write trdid      
+      sc_signal<size_t>	   r_init_rsp_pktid;	  // pending write pktid      
+      sc_signal<addr_t>	   r_init_rsp_nline;	  // pending write nline      
+
+      // Buffer between INIT_RSP fsm and TGT_RSP fsm (complete write/update transaction)
+      sc_signal<bool>	     r_init_rsp_to_tgt_rsp_req;   	// valid request
+      sc_signal<size_t>	   r_init_rsp_to_tgt_rsp_srcid;		// Transaction srcid
+      sc_signal<size_t>	   r_init_rsp_to_tgt_rsp_trdid;		// Transaction trdid
+      sc_signal<size_t>	   r_init_rsp_to_tgt_rsp_pktid;		// Transaction pktid
+
+      ///////////////////////////////////////////////////////
+      // Registers controlled by CLEANUP fsm
+      ///////////////////////////////////////////////////////
+
+      sc_signal<int> 	     r_cleanup_fsm;         // FSM state
+      sc_signal<size_t>      r_cleanup_srcid;       // transaction srcid
+      sc_signal<size_t>      r_cleanup_trdid;       // transaction trdid
+      sc_signal<size_t>      r_cleanup_pktid;       // transaction pktid
+      sc_signal<addr_t>      r_cleanup_nline;       // cache line index
+
+      sc_signal<copy_t>      r_cleanup_d_copies;    // bit-vector of copies 
+      sc_signal<copy_t>      r_cleanup_i_copies;    // bit-vector of copies 
+      sc_signal<copy_t>      r_cleanup_count;       // number of copies 
+      sc_signal<tag_t>       r_cleanup_tag;	        // cache line tag (in directory)
+      sc_signal<bool>        r_cleanup_is_cnt;      // inst bit (in directory)
+      sc_signal<bool>        r_cleanup_lock;	    // lock bit (in directory)
+      sc_signal<bool>        r_cleanup_dirty;	    // dirty bit (in directory)
+      sc_signal<size_t>      r_cleanup_way;	        // associative way (in cache)
+
+      sc_signal<size_t>      r_cleanup_write_srcid; // srcid of write response
+      sc_signal<size_t>      r_cleanup_write_trdid; // trdid of write rsp
+      sc_signal<size_t>      r_cleanup_write_pktid; // pktid of write rsp
+      sc_signal<bool>        r_cleanup_need_rsp;    // needs a write rsp
+
+      sc_signal<size_t>      r_cleanup_index;	    // index of the INVAL line (in the UPT)
+
+      // Buffer between CLEANUP fsm and TGT_RSP fsm (acknowledge a write command from L1)
+      sc_signal<bool>      r_cleanup_to_tgt_rsp_req;    // valid request
+      sc_signal<size_t>    r_cleanup_to_tgt_rsp_srcid;  // transaction srcid
+      sc_signal<size_t>    r_cleanup_to_tgt_rsp_trdid;	// transaction trdid
+      sc_signal<size_t>    r_cleanup_to_tgt_rsp_pktid;	// transaction pktid
+
+      ///////////////////////////////////////////////////////
+      // Registers controlled by LLSC fsm
+      ///////////////////////////////////////////////////////
+
+      sc_signal<int>       r_llsc_fsm;          // FSM state
+      sc_signal<data_t>	   r_llsc_data;		    // read data word
+      sc_signal<uint32_t>  r_llsc_lfsr;         // lfsr for random introducing
+      sc_signal<copy_t>    r_llsc_i_copies;	    // bit_vector of copies
+      sc_signal<copy_t>    r_llsc_d_copies;	    // bit_vector of copies
+      sc_signal<copy_t>    r_llsc_count;	    // number of copies
+      sc_signal<bool>      r_llsc_is_cnt;	    // is_cnt bit (in directory)
+      sc_signal<bool>      r_llsc_dirty;	    // dirty bit (in directory)
+      sc_signal<size_t>    r_llsc_way;		    // way in directory
+      sc_signal<size_t>    r_llsc_set;		    // set in directory
+      sc_signal<data_t>    r_llsc_tag;		    // cache line tag (in directory)
+      sc_signal<size_t>    r_llsc_trt_index;    // Transaction Table index
+      sc_signal<size_t>    r_llsc_upt_index;    // Update Table index
+
+      // Buffer between LLSC fsm and INIT_CMD fsm (XRAM read)	
+      sc_signal<bool>	   r_llsc_to_ixr_cmd_req;   // valid request
+      sc_signal<addr_t>	   r_llsc_to_ixr_cmd_nline; // cache line index
+      sc_signal<size_t>	   r_llsc_to_ixr_cmd_trdid; // index in Transaction Table
+      sc_signal<bool>	   r_llsc_to_ixr_cmd_write; // write request
+      sc_signal<data_t>	  *r_llsc_to_ixr_cmd_data;  // cache line data
+
+
+      // Buffer between LLSC fsm and TGT_RSP fsm
+      sc_signal<bool>	   r_llsc_to_tgt_rsp_req;   // valid request
+      sc_signal<data_t>    r_llsc_to_tgt_rsp_data;  // read data word
+      sc_signal<size_t>	   r_llsc_to_tgt_rsp_srcid; // Transaction srcid
+      sc_signal<size_t>	   r_llsc_to_tgt_rsp_trdid; // Transaction trdid
+      sc_signal<size_t>	   r_llsc_to_tgt_rsp_pktid; // Transaction pktid
+
+      // Buffer between LLSC fsm and INIT_CMD fsm (Update/Invalidate L1 caches)
+      sc_signal<bool>	   r_llsc_to_init_cmd_req;          // valid request
+      sc_signal<bool>	   r_llsc_to_init_cmd_brdcast;      // brdcast request
+      sc_signal<addr_t>	   r_llsc_to_init_cmd_nline;	    // cache line index
+      sc_signal<size_t>	   r_llsc_to_init_cmd_trdid;	    // index in Update Table
+      sc_signal<copy_t>    r_llsc_to_init_cmd_d_copies;     // bit_vector of L1 to update
+      sc_signal<data_t>    r_llsc_to_init_cmd_wdata;        // data (one word)
+      sc_signal<size_t>	   r_llsc_to_init_cmd_index;	    // index of the word in line
+
+      ////////////////////////////////////////////////////
+      // Registers controlled by the IXR_RSP fsm
+      ////////////////////////////////////////////////////
+
+      sc_signal<int> 	   r_ixr_rsp_fsm;       // FSM state
+      sc_signal<size_t>	   r_ixr_rsp_trt_index;	// TRT entry index
+      sc_signal<size_t>    r_ixr_rsp_cpt;	    // word counter
+
+      // Buffer between IXR_RSP fsm and XRAM_RSP fsm  (response from the XRAM)
+      sc_signal<bool>	  *r_ixr_rsp_to_xram_rsp_rok;	// A xram response is ready
+
+      ////////////////////////////////////////////////////
+      // Registers controlled by the XRAM_RSP fsm
+      ////////////////////////////////////////////////////
+
+      sc_signal<int> 	   r_xram_rsp_fsm;		        // FSM state
+      sc_signal<size_t>	   r_xram_rsp_trt_index;	    // TRT entry index
+      TransactionTabEntry  r_xram_rsp_trt_buf;		    // TRT entry local buffer
+      sc_signal<bool>	   r_xram_rsp_victim_inval;	    // victim line invalidate 
+      sc_signal<bool>	   r_xram_rsp_victim_is_cnt;    // victim line inst bit
+      sc_signal<bool>	   r_xram_rsp_victim_dirty;	    // victim line dirty bit
+      sc_signal<size_t>    r_xram_rsp_victim_way;	    // victim line way
+      sc_signal<size_t>    r_xram_rsp_victim_set;	    // victim line set
+      sc_signal<addr_t>    r_xram_rsp_victim_nline;     // victim line index
+      sc_signal<copy_t>    r_xram_rsp_victim_d_copies;	// victim line copies
+      sc_signal<copy_t>    r_xram_rsp_victim_i_copies;	// victim line copies
+      sc_signal<copy_t>    r_xram_rsp_victim_count;	    // victim line number of copies
+      sc_signal<data_t>	  *r_xram_rsp_victim_data;	    // victim line data
+      sc_signal<size_t>	   r_xram_rsp_upt_index;	    // UPT entry index
+
+      // Buffer between XRAM_RSP fsm and TGT_RSP fsm  (response to L1 cache)
+      sc_signal<bool>	   r_xram_rsp_to_tgt_rsp_req;	// Valid request
+      sc_signal<size_t>    r_xram_rsp_to_tgt_rsp_srcid;	// Transaction srcid
+      sc_signal<size_t>    r_xram_rsp_to_tgt_rsp_trdid;	// Transaction trdid
+      sc_signal<size_t>    r_xram_rsp_to_tgt_rsp_pktid;	// Transaction pktid
+      sc_signal<data_t>   *r_xram_rsp_to_tgt_rsp_data;	// data (one cache line)
+      sc_signal<size_t>    r_xram_rsp_to_tgt_rsp_word;  // first word index
+      sc_signal<size_t>    r_xram_rsp_to_tgt_rsp_length;// length of the response
+
+      // Buffer between XRAM_RSP fsm and INIT_CMD fsm (Inval L1 Caches) 
+      sc_signal<bool>	     r_xram_rsp_to_init_cmd_req;    // Valid request
+      sc_signal<bool>      r_xram_rsp_to_init_cmd_brdcast;  // Broadcast request
+      sc_signal<addr_t>    r_xram_rsp_to_init_cmd_nline;    // cache line index;
+      sc_signal<size_t>	   r_xram_rsp_to_init_cmd_trdid;    // index of UPT entry
+      sc_signal<copy_t>    r_xram_rsp_to_init_cmd_d_copies; // bit_vector of copies
+      sc_signal<copy_t>    r_xram_rsp_to_init_cmd_i_copies; // bit_vector of copies
+
+      // Buffer between XRAM_RSP fsm and IXR_CMD fsm (XRAM write)
+      sc_signal<bool>	   r_xram_rsp_to_ixr_cmd_req;	// Valid request
+      sc_signal<addr_t>	   r_xram_rsp_to_ixr_cmd_nline;	// cache line index
+      sc_signal<data_t>	  *r_xram_rsp_to_ixr_cmd_data;	// cache line data
+      sc_signal<size_t>	   r_xram_rsp_to_ixr_cmd_trdid;	// index in transaction table
+
+      ////////////////////////////////////////////////////
+      // Registers controlled by the IXR_CMD fsm
+      ////////////////////////////////////////////////////
+
+      sc_signal<int> 	   r_ixr_cmd_fsm;
+      sc_signal<size_t>	   r_ixr_cmd_cpt;
+
+      ////////////////////////////////////////////////////
+      // Registers controlled by TGT_RSP fsm
+      ////////////////////////////////////////////////////
+
+      sc_signal<int> 	   r_tgt_rsp_fsm;
+      sc_signal<size_t>    r_tgt_rsp_cpt;
+
+      ////////////////////////////////////////////////////
+      // Registers controlled by INIT_CMD fsm
+      ////////////////////////////////////////////////////
+
+      sc_signal<int> 	  r_init_cmd_fsm;
+      sc_signal<size_t>   r_init_cmd_cpt;
+      sc_signal<size_t>	  r_init_cmd_target;
+      sc_signal<bool>     r_init_cmd_inst;
+
+      ////////////////////////////////////////////////////
+      // Registers controlled by ALLOC_DIR fsm
+      ////////////////////////////////////////////////////
+
+      sc_signal<int> 		r_alloc_dir_fsm;
+
+      ////////////////////////////////////////////////////
+      // Registers controlled by ALLOC_TRT fsm
+      ////////////////////////////////////////////////////
+
+      sc_signal<int> 		r_alloc_trt_fsm;
+
+      ////////////////////////////////////////////////////
+      // Registers controlled by ALLOC_UPT fsm
+      ////////////////////////////////////////////////////
+
+      sc_signal<int> 		r_alloc_upt_fsm;
+
+    }; // end class VciMemCacheV2S
+
+}}
+
+#endif
+
+// Local Variables:
+// tab-width: 4
+// c-basic-offset: 4
+// c-file-offsets:((innamespace . 0)(inline-open . 0))
+// indent-tabs-mode: nil
+// End:
+
+// vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4
+
Index: branches/v4/modules/vci_mem_cache_v2s/caba/source/include/xram_transaction_v2.h
===================================================================
--- branches/v4/modules/vci_mem_cache_v2s/caba/source/include/xram_transaction_v2.h	(revision 371)
+++ branches/v4/modules/vci_mem_cache_v2s/caba/source/include/xram_transaction_v2.h	(revision 371)
@@ -0,0 +1,404 @@
+#ifndef XRAM_TRANSACTION_V2_H_
+#define XRAM_TRANSACTION_V2_H_
+ 
+#include <inttypes.h>
+#include <systemc>
+#include <cassert>
+#include "arithmetics.h"
+
+#define DEBUG_XRAM_TRANSACTION 0
+
+////////////////////////////////////////////////////////////////////////
+//                  A transaction tab entry         
+////////////////////////////////////////////////////////////////////////
+
+class TransactionTabEntry {
+  typedef uint32_t size_t;
+  typedef uint32_t data_t;
+  typedef sc_dt::sc_uint<40> addr_t;
+  typedef uint32_t be_t;
+
+ public:
+  bool 		      valid;     	    // entry valid 
+  bool 		      xram_read; 	    // read request to XRAM
+  addr_t   	      nline;    	    // index (zy) of the requested line
+  size_t 	      srcid;     	    // processor requesting the transaction
+  size_t 	      trdid;     	    // processor requesting the transaction
+  size_t 	      pktid;     	    // processor requesting the transaction
+  bool 		      proc_read;	    // read request from processor
+  size_t 		  read_length;      // length of the read (for the response)
+  size_t 	      word_index;    	// index of the first read word (for the response)
+  std::vector<data_t> wdata;        // write buffer (one cache line)
+  std::vector<be_t>   wdata_be;    	// be for each data in the write buffer
+
+  /////////////////////////////////////////////////////////////////////
+  // The init() function initializes the entry 
+  /////////////////////////////////////////////////////////////////////
+  void init()
+  {
+    valid		= false;
+  }
+
+  /////////////////////////////////////////////////////////////////////
+  // The alloc() function initializes the vectors of an entry
+  // Its arguments are :
+  // - n_words : number of words per line in the cache
+  /////////////////////////////////////////////////////////////////////
+  void alloc(size_t n_words)
+  {
+    wdata_be.reserve( (int)n_words );
+    wdata.reserve( (int)n_words );
+    for(size_t i=0; i<n_words; i++){
+      wdata_be.push_back(false);
+      wdata.push_back(0);
+    }
+  }
+
+  ////////////////////////////////////////////////////////////////////
+  // The copy() function copies an existing entry
+  // Its arguments are :
+  // - source : the transaction tab entry to copy
+  ////////////////////////////////////////////////////////////////////
+  void copy(const TransactionTabEntry &source)
+  {
+    valid	    = source.valid;
+    xram_read 	= source.xram_read;
+    nline	    = source.nline;
+    srcid	    = source.srcid;
+    trdid	    = source.trdid;
+    pktid	    = source.pktid;
+    proc_read 	= source.proc_read;
+    read_length = source.read_length;
+    word_index	= source.word_index;
+    wdata_be.assign(source.wdata_be.begin(),source.wdata_be.end());
+    wdata.assign(source.wdata.begin(),source.wdata.end());	
+  }
+
+  ////////////////////////////////////////////////////////////////////
+  // The print() function prints the entry 
+  ////////////////////////////////////////////////////////////////////
+  void print(){
+    std::cout << "valid       = " << valid        << std::endl;
+    std::cout << "xram_read   = " << xram_read    << std::endl;
+    std::cout << "nline       = " << std::hex << nline << std::endl;
+    std::cout << "srcid       = " << srcid        << std::endl;
+    std::cout << "trdid       = " << trdid        << std::endl;
+    std::cout << "pktid       = " << pktid        << std::endl;
+    std::cout << "proc_read   = " << proc_read    << std::endl;
+    std::cout << "read_length = " << read_length  << std::endl;
+    std::cout << "word_index  = " << word_index   << std::endl; 
+    for(size_t i=0; i<wdata_be.size() ; i++){
+      std::cout << "wdata_be [" << i <<"] = " << wdata_be[i] << std::endl;
+    }
+    for(size_t i=0; i<wdata.size() ; i++){
+      std::cout << "wdata [" << i <<"] = " << wdata[i] << std::endl;
+    }
+    std::cout << std::endl;
+  }
+
+  /////////////////////////////////////////////////////////////////////
+  // 		Constructors
+  /////////////////////////////////////////////////////////////////////
+
+  TransactionTabEntry()
+    {
+      wdata_be.clear();
+      wdata.clear();
+      valid=false;
+    }
+
+  TransactionTabEntry(const TransactionTabEntry &source){
+    valid	    = source.valid;
+    xram_read	= source.xram_read;
+    nline	    = source.nline;
+    srcid	    = source.srcid;
+    trdid	    = source.trdid;
+    pktid	    = source.pktid;
+    proc_read	= source.proc_read;
+    read_length = source.read_length;
+    word_index	= source.word_index;
+    wdata_be.assign(source.wdata_be.begin(),source.wdata_be.end());
+    wdata.assign(source.wdata.begin(),source.wdata.end());	
+  }
+
+}; // end class TransactionTabEntry
+
+////////////////////////////////////////////////////////////////////////
+//                  The transaction tab                              
+////////////////////////////////////////////////////////////////////////
+class TransactionTab{
+  typedef uint32_t size_t;
+  typedef uint32_t data_t;
+  typedef sc_dt::sc_uint<40> addr_t;
+  typedef uint32_t be_t;
+
+ private:
+  size_t size_tab;                // The size of the tab
+
+  data_t be_to_mask(be_t be)
+  {
+    data_t ret = 0;
+    if ( be&0x1 ) {
+      ret = ret | 0x000000FF;
+    }
+    if ( be&0x2 ) {
+      ret = ret | 0x0000FF00;
+    }
+    if ( be&0x4 ) {
+      ret = ret | 0x00FF0000;
+    }
+    if ( be&0x8 ) {
+      ret = ret | 0xFF000000;
+    }
+    return ret;
+  }
+
+ public:
+  TransactionTabEntry *tab;       // The transaction tab
+
+  ////////////////////////////////////////////////////////////////////
+  //		Constructors
+  ////////////////////////////////////////////////////////////////////
+  TransactionTab()
+    {
+      size_tab=0;
+      tab=NULL;
+    }
+
+  TransactionTab(size_t n_entries, size_t n_words)
+    {
+      size_tab = n_entries;
+      tab = new TransactionTabEntry[size_tab];
+      for ( size_t i=0; i<size_tab; i++) {
+	tab[i].alloc(n_words);
+      }
+    }
+
+  ~TransactionTab()
+    {
+      delete [] tab;
+    }
+
+  /////////////////////////////////////////////////////////////////////
+  // The size() function returns the size of the tab
+  /////////////////////////////////////////////////////////////////////
+  size_t size()
+  {
+    return size_tab;
+  }
+
+  /////////////////////////////////////////////////////////////////////
+  // The init() function initializes the transaction tab entries
+  /////////////////////////////////////////////////////////////////////
+  void init()
+  {
+    for ( size_t i=0; i<size_tab; i++) {
+      tab[i].init();
+    }
+  }
+
+  /////////////////////////////////////////////////////////////////////
+  // The print() function prints a transaction tab entry
+  // Arguments :
+  // - index : the index of the entry to print
+  /////////////////////////////////////////////////////////////////////
+  void print(const size_t index)
+  {
+    assert( (index < size_tab) 
+	    && "Invalid Transaction Tab Entry");
+    tab[index].print();
+    return;
+  }
+
+  /////////////////////////////////////////////////////////////////////
+  // The read() function returns a transaction tab entry.
+  // Arguments :
+  // - index : the index of the entry to read
+  /////////////////////////////////////////////////////////////////////
+  TransactionTabEntry read(const size_t index)
+  {
+    assert( (index < size_tab) 
+	    && "Invalid Transaction Tab Entry");
+    return tab[index];
+  }
+
+  /////////////////////////////////////////////////////////////////////
+  // The full() function returns the state of the transaction tab
+  // Arguments :
+  // - index : (return argument) the index of an empty entry 
+  // The function returns true if the transaction tab is full
+  /////////////////////////////////////////////////////////////////////
+  bool full(size_t &index)
+  {
+    for(size_t i=0; i<size_tab; i++){
+      if(!tab[i].valid){
+	    index=i;
+	    return false;	
+      }
+    }
+    return true;
+  }
+
+  /////////////////////////////////////////////////////////////////////
+  // The hit_read() function checks if an XRAM read transaction exists 
+  // for a given cache line.
+  // Arguments :
+  // - index : (return argument) the index of the hit entry, if there is 
+  // - nline : the index (zy) of the requested line
+  // The function returns true if a read request has already been sent
+  //////////////////////////////////////////////////////////////////////
+  bool hit_read(const addr_t nline,size_t &index)
+  {
+    for(size_t i=0; i<size_tab; i++){
+      if((tab[i].valid && (nline==tab[i].nline)) && (tab[i].xram_read)) {
+	    index=i;
+	    return true;	
+      }
+    }
+    return false;
+  }
+
+  ///////////////////////////////////////////////////////////////////////
+  // The hit_write() function looks if an XRAM write transaction exists 
+  // for a given line.
+  // Arguments :
+  // - nline : the index (zy) of the requested line
+  // The function returns true if a write request has already been sent
+  ///////////////////////////////////////////////////////////////////////
+  bool hit_write(const addr_t nline)
+  {
+    for(size_t i=0; i<size_tab; i++){
+      if(tab[i].valid && (nline==tab[i].nline) && !(tab[i].xram_read)) {
+	    return true;	
+      }
+    }
+    return false;
+  }
+
+  /////////////////////////////////////////////////////////////////////
+  // The write_data_mask() function writes a vector of data (a line).
+  // The data is written only if the corresponding bits are set
+  // in the be vector. 
+  // Arguments :
+  // - index : the index of the request in the transaction tab
+  // - be   : vector of be 
+  // - data : vector of data
+  /////////////////////////////////////////////////////////////////////
+  void write_data_mask(const size_t index, 
+		       const std::vector<be_t> &be, 
+		       const std::vector<data_t> &data) 
+  {
+    assert( (index < size_tab) 
+	    && "Invalid Transaction Tab Entry");
+    assert(be.size()==tab[index].wdata_be.size() 
+	   && "Bad data mask in write_data_mask in TransactionTab");
+    assert(data.size()==tab[index].wdata.size() 
+	   && "Bad data in write_data_mask in TransactionTab");
+
+    for(size_t i=0; i<tab[index].wdata_be.size() ; i++) {
+      tab[index].wdata_be[i] = tab[index].wdata_be[i] | be[i];
+      data_t mask = be_to_mask(be[i]);
+      tab[index].wdata[i] = (tab[index].wdata[i] & ~mask) | (data[i] & mask);
+    }
+  }
+
+  /////////////////////////////////////////////////////////////////////
+  // The set() function registers a transaction (read or write)
+  // to the XRAM in the transaction tab.
+  // Arguments :
+  // - index : index in the transaction tab
+  // - xram_read : transaction type (read or write a cache line)
+  // - nline : the index (zy) of the cache line
+  // - srcid : srcid of the initiator that caused the transaction
+  // - trdid : trdid of the initiator that caused the transaction
+  // - pktid : pktid of the initiator that caused the transaction
+  // - proc_read : does the initiator want a copy
+  // - read_length : length of read (in case of processor read)
+  // - word_index : index in the line (in case of single word read)
+  // - data : the data to write (in case of write)
+  // - data_be : the mask of the data to write (in case of write)
+  /////////////////////////////////////////////////////////////////////
+  void set(const size_t index,
+	   const bool xram_read,
+	   const addr_t nline,
+	   const size_t srcid,
+	   const size_t trdid,
+	   const size_t pktid,
+	   const bool proc_read,
+	   const size_t read_length,
+	   const size_t word_index,
+	   const std::vector<be_t> &data_be,
+	   const std::vector<data_t> &data) 
+  {
+    assert( (index < size_tab) 
+	    && "The selected entry is out of range in set() Transaction Tab");
+    assert(data_be.size()==tab[index].wdata_be.size() 
+	   && "Bad data_be argument in set() TransactionTab");
+    assert(data.size()==tab[index].wdata.size() 
+	   && "Bad data argument in set() TransactionTab");
+
+    tab[index].valid	        = true;
+    tab[index].xram_read        = xram_read;
+    tab[index].nline	        = nline;
+    tab[index].srcid	        = srcid;
+    tab[index].trdid	        = trdid;
+    tab[index].pktid	        = pktid;
+    tab[index].proc_read	    = proc_read;
+    tab[index].read_length	    = read_length;
+    tab[index].word_index	    = word_index;
+    for(size_t i=0; i<tab[index].wdata.size(); i++) {
+      tab[index].wdata_be[i]    = data_be[i];
+      tab[index].wdata[i]       = data[i];
+    }
+  }
+
+  /////////////////////////////////////////////////////////////////////
+  // The write_rsp() function writes a word of the response to an 
+  // XRAM read transaction.
+  // The data is only written when the corresponding BE field is Ox0.
+  // Arguments :
+  // - index : the index of the transaction in the transaction tab
+  // - word_index : the index of the data in the line
+  // - data : the data to write
+  /////////////////////////////////////////////////////////////////////
+  void write_rsp(const size_t index,
+		 const size_t word,
+		 const data_t data)
+  {
+    assert( (index < size_tab) 
+	    && "Selected entry  out of range in write_rsp() Transaction Tab");
+    assert( (word <= tab[index].wdata_be.size()) 
+	    && "Bad word_index in write_rsp() in TransactionTab");
+    assert( tab[index].valid 
+	    && "Transaction Tab Entry invalid in write_rsp()");
+    assert( tab[index].xram_read 
+	    && "Selected entry is not an XRAM read transaction in write_rsp()");
+
+    data_t mask = be_to_mask(tab[index].wdata_be[word]);
+    tab[index].wdata[word] = (tab[index].wdata[word] & mask) | (data & ~mask);
+  }
+
+  /////////////////////////////////////////////////////////////////////
+  // The erase() function erases an entry in the transaction tab.
+  // Arguments :
+  // - index : the index of the request in the transaction tab
+  /////////////////////////////////////////////////////////////////////
+  void erase(const size_t index)
+  {
+    assert( (index < size_tab) 
+	    && "The selected entry is out of range in erase() Transaction Tab");
+    tab[index].valid	= false;
+  }
+}; // end class TransactionTab
+
+#endif
+
+// Local Variables:
+// tab-width: 4
+// c-basic-offset: 4
+// c-file-offsets:((innamespace . 0)(inline-open . 0))
+// indent-tabs-mode: nil
+// End:
+
+// vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4
+
Index: branches/v4/modules/vci_mem_cache_v2s/caba/source/src/vci_mem_cache_v2s.cpp
===================================================================
--- branches/v4/modules/vci_mem_cache_v2s/caba/source/src/vci_mem_cache_v2s.cpp	(revision 371)
+++ branches/v4/modules/vci_mem_cache_v2s/caba/source/src/vci_mem_cache_v2s.cpp	(revision 371)
@@ -0,0 +1,3837 @@
+/* -*- c++ -*-
+ * File 	: vci_mem_cache_v2s.cpp
+ * Date 	: 30/10/2008
+ * Copyright 	: UPMC / LIP6
+ * Authors 	: Alain Greiner / Eric Guthmuller
+ *
+ * SOCLIB_LGPL_HEADER_BEGIN
+ *
+ * This file is part of SoCLib, GNU LGPLv2.1.
+ *
+ * SoCLib is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU Lesser General Public License as published
+ * by the Free Software Foundation; version 2.1 of the License.
+ *
+ * SoCLib is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with SoCLib; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301 USA
+ *
+ * SOCLIB_LGPL_HEADER_END
+ *
+ * Maintainers: alain eric.guthmuller@polytechnique.edu
+ */
+#include "../include/vci_mem_cache_v2s.h"
+
+//#define TDEBUG // Transaction tab debug
+//#define IDEBUG // Update tab debug
+//#define DDEBUG // Directory debug
+//#define DEBUG_VCI_MEM_CACHE 1
+#define RANDOMIZE_SC
+
+namespace soclib { namespace caba {
+
+#ifdef DEBUG_VCI_MEM_CACHE 
+  const char *tgt_cmd_fsm_str[] = {
+    "TGT_CMD_IDLE",
+    "TGT_CMD_READ",
+    "TGT_CMD_READ_EOP",
+    "TGT_CMD_WRITE",
+    "TGT_CMD_ATOMIC",
+  };
+  const char *tgt_rsp_fsm_str[] = {
+    "TGT_RSP_READ_IDLE",
+    "TGT_RSP_WRITE_IDLE",
+    "TGT_RSP_LLSC_IDLE",
+    "TGT_RSP_XRAM_IDLE",
+    "TGT_RSP_INIT_IDLE",
+    "TGT_RSP_CLEANUP_IDLE",
+    "TGT_RSP_READ",
+    "TGT_RSP_WRITE",
+    "TGT_RSP_LLSC",
+    "TGT_RSP_XRAM",
+    "TGT_RSP_INIT",
+    "TGT_RSP_CLEANUP",
+  };
+  const char *init_cmd_fsm_str[] = {
+    "INIT_CMD_INVAL_IDLE",
+    "INIT_CMD_INVAL_SEL",
+    "INIT_CMD_INVAL_NLINE",
+    "INIT_CMD_UPDT_IDLE",
+    "INIT_CMD_UPDT_SEL",
+    "INIT_CMD_BRDCAST",
+    "INIT_CMD_UPDT_NLINE",
+    "INIT_CMD_UPDT_INDEX",
+    "INIT_CMD_UPDT_DATA",
+    "INIT_CMD_SC_UPDT_IDLE",
+    "INIT_CMD_SC_UPDT_SEL",
+    "INIT_CMD_SC_BRDCAST",
+    "INIT_CMD_SC_UPDT_NLINE",
+    "INIT_CMD_SC_UPDT_INDEX",
+    "INIT_CMD_SC_UPDT_DATA",
+  };
+  const char *init_rsp_fsm_str[] = {
+    "INIT_RSP_IDLE",
+    "INIT_RSP_UPT_LOCK",
+    "INIT_RSP_UPT_CLEAR",
+    "INIT_RSP_END",
+  };
+  const char *read_fsm_str[] = {
+    "READ_IDLE",
+    "READ_DIR_LOCK",
+    "READ_DIR_HIT",
+    "READ_RSP",
+    "READ_TRT_LOCK",
+    "READ_TRT_SET",
+    "READ_XRAM_REQ",
+  };
+  const char *write_fsm_str[] = {
+    "WRITE_IDLE",
+    "WRITE_NEXT",
+    "WRITE_DIR_LOCK",
+    "WRITE_DIR_HIT_READ",
+    "WRITE_DIR_HIT",
+    "WRITE_DIR_HIT_RSP",
+    "WRITE_UPT_LOCK",
+    "WRITE_WAIT_UPT",
+    "WRITE_UPDATE",
+    "WRITE_RSP",
+    "WRITE_TRT_LOCK",
+    "WRITE_TRT_DATA",
+    "WRITE_TRT_SET",
+    "WRITE_WAIT_TRT",
+    "WRITE_XRAM_REQ",
+    "WRITE_TRT_WRITE_LOCK",
+    "WRITE_INVAL_LOCK",
+    "WRITE_DIR_INVAL",
+    "WRITE_INVAL",
+    "WRITE_XRAM_SEND",
+  };
+  const char *ixr_rsp_fsm_str[] = {
+    "IXR_RSP_IDLE",
+    "IXR_RSP_ACK",
+    "IXR_RSP_TRT_ERASE",
+    "IXR_RSP_TRT_READ",
+  };
+  const char *xram_rsp_fsm_str[] = {
+    "XRAM_RSP_IDLE",
+    "XRAM_RSP_TRT_COPY",
+    "XRAM_RSP_TRT_DIRTY",
+    "XRAM_RSP_DIR_LOCK",
+    "XRAM_RSP_DIR_UPDT",
+    "XRAM_RSP_DIR_RSP",
+    "XRAM_RSP_INVAL_LOCK",
+    "XRAM_RSP_INVAL_WAIT",
+    "XRAM_RSP_INVAL",
+    "XRAM_RSP_WRITE_DIRTY",
+  };
+  const char *ixr_cmd_fsm_str[] = {
+    "IXR_CMD_READ_IDLE",
+    "IXR_CMD_WRITE_IDLE",
+    "IXR_CMD_LLSC_IDLE",
+    "IXR_CMD_XRAM_IDLE",
+    "IXR_CMD_READ_NLINE",
+    "IXR_CMD_WRITE_NLINE",
+    "IXR_CMD_LLSC_NLINE",
+    "IXR_CMD_XRAM_DATA",
+  };
+  const char *llsc_fsm_str[] = {
+    "LLSC_IDLE",
+    "LL_DIR_LOCK",
+    "LL_DIR_HIT",
+    "LL_RSP",
+    "SC_DIR_LOCK",
+    "SC_DIR_HIT",
+    "SC_UPT_LOCK",
+    "SC_WAIT_UPT",
+    "SC_UPDATE",
+    "SC_TRT_LOCK",
+    "SC_INVAL_LOCK",
+    "SC_DIR_INVAL",
+    "SC_INVAL",
+    "SC_XRAM_SEND",
+    "SC_RSP_FALSE",
+    "SC_RSP_TRUE",
+    "LLSC_TRT_LOCK",
+    "LLSC_TRT_SET",
+    "LLSC_XRAM_REQ",
+  };
+  const char *cleanup_fsm_str[] = {
+    "CLEANUP_IDLE",
+    "CLEANUP_DIR_LOCK",
+    "CLEANUP_DIR_WRITE",
+    "CLEANUP_UPT_LOCK",
+    "CLEANUP_UPT_WRITE",
+    "CLEANUP_WRITE_RSP",
+    "CLEANUP_RSP",
+  };
+  const char *alloc_dir_fsm_str[] = {
+    "ALLOC_DIR_READ",
+    "ALLOC_DIR_WRITE",
+    "ALLOC_DIR_LLSC",
+    "ALLOC_DIR_CLEANUP",
+    "ALLOC_DIR_XRAM_RSP",
+  };
+  const char *alloc_trt_fsm_str[] = {
+    "ALLOC_TRT_READ",
+    "ALLOC_TRT_WRITE",
+    "ALLOC_TRT_LLSC",
+    "ALLOC_TRT_XRAM_RSP",
+    "ALLOC_TRT_IXR_RSP",
+  };
+  const char *alloc_upt_fsm_str[] = {
+    "ALLOC_UPT_WRITE",
+    "ALLOC_UPT_XRAM_RSP",
+    "ALLOC_UPT_INIT_RSP",
+    "ALLOC_UPT_CLEANUP",
+  };
+#endif
+
+#define tmpl(x) template<typename vci_param> x VciMemCacheV2S<vci_param>
+
+  using soclib::common::uint32_log2;
+
+  ////////////////////////////////
+  // 	Constructor 
+  ////////////////////////////////
+
+  tmpl(/**/)::VciMemCacheV2S( 
+      sc_module_name name,
+      const soclib::common::MappingTable &mtp,
+      const soclib::common::MappingTable &mtc,
+      const soclib::common::MappingTable &mtx,
+      const soclib::common::IntTab &vci_ixr_index,
+      const soclib::common::IntTab &vci_ini_index,
+      const soclib::common::IntTab &vci_tgt_index,
+      const soclib::common::IntTab &vci_tgt_index_cleanup,
+      size_t nways,
+      size_t nsets,
+      size_t nwords)
+
+    : soclib::caba::BaseModule(name),
+
+    p_clk("clk"),
+    p_resetn("resetn"),
+    p_vci_tgt("vci_tgt"),
+    p_vci_tgt_cleanup("vci_tgt_cleanup"),
+    p_vci_ini("vci_ini"),
+    p_vci_ixr("vci_ixr"),
+
+    m_initiators( 32 ),
+    m_ways( nways ),
+    m_sets( nsets ),
+    m_words( nwords ),
+    m_srcid_ixr( mtx.indexForId(vci_ixr_index) ),
+    m_srcid_ini( mtc.indexForId(vci_ini_index) ),
+    m_seglist(mtp.getSegmentList(vci_tgt_index)),
+    m_cseglist(mtc.getSegmentList(vci_tgt_index_cleanup)),
+    m_coherence_table( mtc.getCoherenceTable<vci_addr_t>() ),
+    m_atomic_tab( m_initiators ),
+    m_transaction_tab( TRANSACTION_TAB_LINES, nwords ),
+    m_update_tab( UPDATE_TAB_LINES ),
+    m_cache_directory( nways, nsets, nwords, vci_param::N ),
+#define L2 soclib::common::uint32_log2
+    m_x( L2(m_words), 2),
+    m_y( L2(m_sets), L2(m_words) + 2),
+    m_z( vci_param::N - L2(m_sets) - L2(m_words) - 2, L2(m_sets) + L2(m_words) + 2),
+    m_nline( vci_param::N - L2(m_words) - 2, L2(m_words) + 2),
+#undef L2
+
+    //  FIFOs 
+    m_cmd_read_addr_fifo("m_cmd_read_addr_fifo", 4),
+    m_cmd_read_length_fifo("m_cmd_read_length_fifo", 4),
+    m_cmd_read_srcid_fifo("m_cmd_read_srcid_fifo", 4),
+    m_cmd_read_trdid_fifo("m_cmd_read_trdid_fifo", 4),
+    m_cmd_read_pktid_fifo("m_cmd_read_pktid_fifo", 4),
+
+    m_cmd_write_addr_fifo("m_cmd_write_addr_fifo",8),
+    m_cmd_write_eop_fifo("m_cmd_write_eop_fifo",8),
+    m_cmd_write_srcid_fifo("m_cmd_write_srcid_fifo",8),
+    m_cmd_write_trdid_fifo("m_cmd_write_trdid_fifo",8),
+    m_cmd_write_pktid_fifo("m_cmd_write_pktid_fifo",8),
+    m_cmd_write_data_fifo("m_cmd_write_data_fifo",8),
+    m_cmd_write_be_fifo("m_cmd_write_be_fifo",8),
+
+    m_cmd_llsc_addr_fifo("m_cmd_llsc_addr_fifo",4),
+    m_cmd_llsc_sc_fifo("m_cmd_llsc_sc_fifo",4),
+    m_cmd_llsc_srcid_fifo("m_cmd_llsc_srcid_fifo",4),
+    m_cmd_llsc_trdid_fifo("m_cmd_llsc_trdid_fifo",4),
+    m_cmd_llsc_pktid_fifo("m_cmd_llsc_pktid_fifo",4),
+    m_cmd_llsc_wdata_fifo("m_cmd_llsc_wdata_fifo",4),
+
+    r_tgt_cmd_fsm("r_tgt_cmd_fsm"),
+    
+    nseg(0),	
+    ncseg(0),	
+
+    r_read_fsm("r_read_fsm"),
+    r_write_fsm("r_write_fsm"),
+    r_init_rsp_fsm("r_init_rsp_fsm"),
+    r_cleanup_fsm("r_cleanup_fsm"),
+    r_llsc_fsm("r_llsc_fsm"),
+    r_ixr_rsp_fsm("r_ixr_rsp_fsm"),
+    r_xram_rsp_fsm("r_xram_rsp_fsm"),
+    r_ixr_cmd_fsm("r_ixr_cmd_fsm"),
+    r_tgt_rsp_fsm("r_tgt_rsp_fsm"),
+    r_init_cmd_fsm("r_init_cmd_fsm"),
+    r_alloc_dir_fsm("r_alloc_dir_fsm"),
+    r_alloc_trt_fsm("r_alloc_trt_fsm"),
+    r_alloc_upt_fsm("r_alloc_upt_fsm")
+    {
+      assert(IS_POW_OF_2(nsets));
+      assert(IS_POW_OF_2(nwords));
+      assert(IS_POW_OF_2(nways));
+      assert(nsets);
+      assert(nwords);
+      assert(nways);
+      assert(nsets <= 1024);
+      assert(nwords <= 32);
+      assert(nways <= 32);
+
+
+      // Get the segments associated to the MemCache 
+      std::list<soclib::common::Segment>::iterator seg;
+
+      for(seg = m_seglist.begin(); seg != m_seglist.end() ; seg++) {
+        nseg++;
+      }
+      for(seg = m_cseglist.begin(); seg != m_cseglist.end() ; seg++) {
+        ncseg++;
+      }
+
+      m_seg = new soclib::common::Segment*[nseg];
+      size_t i = 0;
+      for ( seg = m_seglist.begin() ; seg != m_seglist.end() ; seg++ ) { 
+        m_seg[i] = &(*seg);
+        i++;
+      }
+      m_cseg = new soclib::common::Segment*[ncseg];
+      i = 0;
+      for ( seg = m_cseglist.begin() ; seg != m_cseglist.end() ; seg++ ) { 
+          m_cseg[i] = &(*seg);
+          i++;
+      }
+
+      // Memory cache allocation & initialisation
+      m_cache_data = new data_t**[nways];
+      for ( size_t i=0 ; i<nways ; ++i ) {
+        m_cache_data[i] = new data_t*[nsets];
+      }
+      for ( size_t i=0; i<nways; ++i ) {
+        for ( size_t j=0; j<nsets; ++j ) {
+          m_cache_data[i][j] = new data_t[nwords];
+          for ( size_t k=0; k<nwords; k++){
+            m_cache_data[i][j][k]=0;
+          }	
+        }
+      }
+
+      // Allocation for IXR_RSP FSM
+      r_ixr_rsp_to_xram_rsp_rok	    = new sc_signal<bool>[TRANSACTION_TAB_LINES];
+
+      // Allocation for XRAM_RSP FSM
+      r_xram_rsp_victim_data        = new sc_signal<data_t>[nwords];
+      r_xram_rsp_to_tgt_rsp_data    = new sc_signal<data_t>[nwords];
+      r_xram_rsp_to_ixr_cmd_data    = new sc_signal<data_t>[nwords];
+
+      // Allocation for READ FSM
+      r_read_data 			        = new sc_signal<data_t>[nwords];
+      r_read_to_tgt_rsp_data 		= new sc_signal<data_t>[nwords];
+
+      // Allocation for WRITE FSM
+      r_write_data 			        = new sc_signal<data_t>[nwords];
+      r_write_be 			        = new sc_signal<be_t>[nwords];
+      r_write_to_init_cmd_data 		= new sc_signal<data_t>[nwords];
+      r_write_to_init_cmd_we		= new sc_signal<bool>[nwords];
+      r_write_to_ixr_cmd_data	    = new sc_signal<data_t>[nwords];
+
+      // Allocation for LLSC FSM
+      r_llsc_to_ixr_cmd_data	    = new sc_signal<data_t>[nwords];
+
+
+      // Simulation
+
+      SC_METHOD(transition);
+      dont_initialize();
+      sensitive << p_clk.pos();
+
+      SC_METHOD(genMoore);
+      dont_initialize();
+      sensitive << p_clk.neg();
+
+    } // end constructor
+
+  /////////////////////////////////////////
+  // This function prints the statistics 
+  /////////////////////////////////////////
+
+  tmpl(void)::print_stats()
+  {
+    std::cout << "----------------------------------" << std::dec << std::endl;
+    std::cout << "MEM_CACHE " << m_srcid_ini << " / Time = " << m_cpt_cycles << std::endl
+      << "- READ RATE            = " << (double)m_cpt_read/m_cpt_cycles << std::endl
+      << "- READ MISS RATE       = " << (double)m_cpt_read_miss/m_cpt_read << std::endl
+      << "- WRITE RATE           = " << (double)m_cpt_write/m_cpt_cycles << std::endl
+      << "- WRITE MISS RATE      = " << (double)m_cpt_write_miss/m_cpt_write << std::endl
+      << "- WRITE BURST LENGTH   = " << (double)m_cpt_write_cells/m_cpt_write << std::endl
+      << "- UPDATE RATE          = " << (double)m_cpt_update/m_cpt_cycles << std::endl
+      << "- UPDATE ARITY         = " << (double)m_cpt_update_mult/m_cpt_update << std::endl
+      << "- INVAL MULTICAST RATE = " << (double)(m_cpt_inval-m_cpt_inval_brdcast)/m_cpt_cycles << std::endl
+      << "- INVAL MULTICAST ARITY= " << (double)m_cpt_inval_mult/(m_cpt_inval-m_cpt_inval_brdcast) << std::endl
+      << "- INVAL BROADCAST RATE = " << (double)m_cpt_inval_brdcast/m_cpt_cycles << std::endl
+      << "- SAVE DIRTY RATE      = " << (double)m_cpt_write_dirty/m_cpt_cycles << std::endl
+      << "- CLEANUP RATE         = " << (double)m_cpt_cleanup/m_cpt_cycles << std::endl
+      << "- LL RATE              = " << (double)m_cpt_ll/m_cpt_cycles << std::endl
+      << "- SC RATE              = " << (double)m_cpt_sc/m_cpt_cycles << std::endl;
+  }
+
+  /////////////////////////////////
+  tmpl(/**/)::~VciMemCacheV2S()
+    /////////////////////////////////
+  {
+    for(size_t i=0; i<m_ways ; i++){
+      for(size_t j=0; j<m_sets ; j++){
+        delete [] m_cache_data[i][j];
+      }
+    }
+    for(size_t i=0; i<m_ways ; i++){
+      delete [] m_cache_data[i];
+    }
+    delete [] m_cache_data;
+    delete [] m_coherence_table;
+
+    delete [] r_ixr_rsp_to_xram_rsp_rok;
+
+    delete [] r_xram_rsp_victim_data;
+    delete [] r_xram_rsp_to_tgt_rsp_data;
+    delete [] r_xram_rsp_to_ixr_cmd_data;
+
+    delete [] r_read_data;
+    delete [] r_read_to_tgt_rsp_data;
+
+    delete [] r_write_data;
+    delete [] r_write_be;
+    delete [] r_write_to_init_cmd_data;
+  }
+
+  //////////////////////////////////
+  tmpl(void)::transition()
+    //////////////////////////////////
+  {
+    using soclib::common::uint32_log2;
+    //  RESET          
+    if ( ! p_resetn.read() ) {
+
+      //     Initializing FSMs
+      r_tgt_cmd_fsm 	= TGT_CMD_IDLE;
+      r_tgt_rsp_fsm 	= TGT_RSP_READ_IDLE;
+      r_init_cmd_fsm 	= INIT_CMD_INVAL_IDLE;
+      r_init_rsp_fsm 	= INIT_RSP_IDLE;
+      r_read_fsm 	= READ_IDLE;
+      r_write_fsm 	= WRITE_IDLE;
+      r_llsc_fsm 	= LLSC_IDLE;
+      r_cleanup_fsm 	= CLEANUP_IDLE;
+      r_alloc_dir_fsm   = ALLOC_DIR_READ;
+      r_alloc_trt_fsm   = ALLOC_TRT_READ;
+      r_alloc_upt_fsm   = ALLOC_UPT_WRITE;
+      r_ixr_rsp_fsm 	= IXR_RSP_IDLE;
+      r_xram_rsp_fsm 	= XRAM_RSP_IDLE;
+      r_ixr_cmd_fsm 	= IXR_CMD_READ_IDLE;
+
+      //  Initializing Tables
+      m_cache_directory.init();
+      m_atomic_tab.init();	
+      m_transaction_tab.init();
+
+      // initializing FIFOs and communication Buffers
+
+      m_cmd_read_addr_fifo.init();
+      m_cmd_read_length_fifo.init();
+      m_cmd_read_srcid_fifo.init();
+      m_cmd_read_trdid_fifo.init();
+      m_cmd_read_pktid_fifo.init();
+
+      m_cmd_write_addr_fifo.init();
+      m_cmd_write_eop_fifo.init();
+      m_cmd_write_srcid_fifo.init();
+      m_cmd_write_trdid_fifo.init();
+      m_cmd_write_pktid_fifo.init();
+      m_cmd_write_data_fifo.init();
+
+      m_cmd_llsc_addr_fifo.init();
+      m_cmd_llsc_srcid_fifo.init();
+      m_cmd_llsc_trdid_fifo.init();
+      m_cmd_llsc_pktid_fifo.init();
+      m_cmd_llsc_wdata_fifo.init();
+      m_cmd_llsc_sc_fifo.init();
+
+      r_read_to_tgt_rsp_req	    = false;
+      r_read_to_ixr_cmd_req	    = false;
+
+      r_write_to_tgt_rsp_req	= false;
+      r_write_to_ixr_cmd_req	= false;
+      r_write_to_init_cmd_req	= false;
+
+      r_cleanup_to_tgt_rsp_req	= false;
+
+      r_init_rsp_to_tgt_rsp_req	= false;
+
+      r_llsc_lfsr                       = -1;
+      r_llsc_to_tgt_rsp_req	    = false;
+      r_llsc_to_ixr_cmd_req	    = false;
+      r_llsc_to_init_cmd_req	= false;
+
+      for(size_t i=0; i<TRANSACTION_TAB_LINES ; i++){
+        r_ixr_rsp_to_xram_rsp_rok[i] = false;
+      }
+
+      r_xram_rsp_to_tgt_rsp_req	    = false;
+      r_xram_rsp_to_init_cmd_req    = false;
+      r_xram_rsp_to_ixr_cmd_req	    = false;
+      r_xram_rsp_trt_index	        = 0;
+
+      r_ixr_cmd_cpt         = 0;
+
+      r_copies_limit        = 3;
+
+      // Activity counters
+      m_cpt_cycles		    = 0;
+      m_cpt_read		    = 0;
+      m_cpt_read_miss	    = 0;
+      m_cpt_write		    = 0;
+      m_cpt_write_miss	    = 0;
+      m_cpt_write_cells	    = 0;
+      m_cpt_write_dirty	    = 0;
+      m_cpt_update		    = 0;
+      m_cpt_update_mult     = 0;
+      m_cpt_inval_brdcast 	= 0;
+      m_cpt_inval 		    = 0;
+      m_cpt_inval_mult 		= 0;
+      m_cpt_cleanup		    = 0;
+      m_cpt_ll     		    = 0;
+      m_cpt_sc     		    = 0;
+
+      return;
+    }
+
+    bool    cmd_read_fifo_put = false;
+    bool    cmd_read_fifo_get = false;
+
+    bool    cmd_write_fifo_put = false;
+    bool    cmd_write_fifo_get = false;
+
+    bool    cmd_llsc_fifo_put = false;
+    bool    cmd_llsc_fifo_get = false;
+
+#if DEBUG_VCI_MEM_CACHE 
+    std::cout << "---------------------------------------------" << std::dec << std::endl;
+    std::cout << "MEM_CACHE " << m_srcid_ini << " ; Time = " << m_cpt_cycles << std::endl
+      << " - TGT_CMD FSM   = " << tgt_cmd_fsm_str[r_tgt_cmd_fsm] << std::endl
+      << " - TGT_RSP FSM   = " << tgt_rsp_fsm_str[r_tgt_rsp_fsm] << std::endl
+      << " - INIT_CMD FSM  = " << init_cmd_fsm_str[r_init_cmd_fsm] << std::endl
+      << " - INIT_RSP FSM  = " << init_rsp_fsm_str[r_init_rsp_fsm] << std::endl
+      << " - READ FSM      = " << read_fsm_str[r_read_fsm] << std::endl
+      << " - WRITE FSM     = " << write_fsm_str[r_write_fsm] << std::endl
+      << " - LLSC FSM      = " << llsc_fsm_str[r_llsc_fsm] << std::endl
+      << " - CLEANUP FSM   = " << cleanup_fsm_str[r_cleanup_fsm] << std::endl
+      << " - IXR_CMD FSM  = " << ixr_cmd_fsm_str[r_ixr_cmd_fsm] << std::endl
+      << " - IXR_RSP FSM   = " << ixr_rsp_fsm_str[r_ixr_rsp_fsm] << std::endl
+      << " - XRAM_RSP FSM  = " << xram_rsp_fsm_str[r_xram_rsp_fsm] << std::endl
+      << " - ALLOC_DIR FSM = " << alloc_dir_fsm_str[r_alloc_dir_fsm] << std::endl
+      << " - ALLOC_TRT FSM = " << alloc_trt_fsm_str[r_alloc_trt_fsm] << std::endl
+      << " - ALLOC_UPT FSM = " << alloc_upt_fsm_str[r_alloc_upt_fsm] << std::endl;
+#endif
+
+
+    ////////////////////////////////////////////////////////////////////////////////////
+    //		TGT_CMD FSM
+    ////////////////////////////////////////////////////////////////////////////////////
+    // The TGT_CMD_FSM controls the incoming VCI command pakets from the processors
+    //
+    // There is 4 types of packets for the m_mem_segment :
+    // - READ    : a READ request has a length of 1 VCI cell. It can be a single word 
+    //             or an entire cache line, depending on the PLEN value.
+    // - WRITE   : a WRITE request has a maximum length of 16 cells, and can only
+    //             concern words in a same line.
+    // - LL      : The LL request has a length of 1 cell.
+    // - SC      : The SC request has a length of 1 cell. 
+    //             The WDATA field contains the data to write.
+    //
+    ////////////////////////////////////////////////////////////////////////////////////
+
+    switch ( r_tgt_cmd_fsm.read() ) {
+
+      //////////////////
+      case TGT_CMD_IDLE:
+        {
+          if ( p_vci_tgt.cmdval ) {
+            assert( (p_vci_tgt.srcid.read() < m_initiators)
+                && "VCI_MEM_CACHE error in VCI_MEM_CACHE : The received SRCID is larger than 31");
+
+            bool reached = false;
+            for ( size_t index = 0 ; index < nseg && !reached ; index++) 
+            {
+//              if ( m_seg[index]->contains((addr_t)(p_vci_tgt.address.read())) ) {
+              if ( m_seg[index]->contains(p_vci_tgt.address.read()) ) {
+                reached = true;
+                r_index = index;
+              }
+            }
+
+
+            if ( !reached ) 
+            { 
+              std::cout << "VCI_MEM_CACHE Out of segment access in VCI_MEM_CACHE" << std::endl;
+              std::cout << "Faulty address = " << std::hex << (addr_t)(p_vci_tgt.address.read()) << std::endl;
+              std::cout << "Faulty initiator = " << std::dec << p_vci_tgt.srcid.read() << std::endl;
+              exit(0);
+            } 
+            else if ( p_vci_tgt.cmd.read() == vci_param::CMD_READ ) 
+            {
+              r_tgt_cmd_fsm = TGT_CMD_READ;
+            } 
+            else if (( p_vci_tgt.cmd.read() == vci_param::CMD_WRITE ))
+            {  
+              r_tgt_cmd_fsm = TGT_CMD_WRITE;
+            } 
+            else if ((p_vci_tgt.cmd.read() == vci_param::CMD_LOCKED_READ) || 
+                (p_vci_tgt.cmd.read() == vci_param::CMD_STORE_COND) ) 
+            {
+              r_tgt_cmd_fsm = TGT_CMD_ATOMIC;
+            }
+          }
+          break;
+        }
+        //////////////////
+      case TGT_CMD_READ:
+
+        {
+          assert(((m_x[(vci_addr_t)p_vci_tgt.address.read()]+(p_vci_tgt.plen.read()>>2))<=16)
+              && "VCI_MEM_CACHE All read request to the MemCache must stay within a cache line"); 
+
+          if ( p_vci_tgt.cmdval && m_cmd_read_addr_fifo.wok() ) {
+            cmd_read_fifo_put = true;
+            if ( p_vci_tgt.eop )  r_tgt_cmd_fsm = TGT_CMD_IDLE;
+            else                  r_tgt_cmd_fsm = TGT_CMD_READ_EOP;		
+          } 
+          break;
+        }
+        //////////////////////
+      case TGT_CMD_READ_EOP:
+        {
+          if ( p_vci_tgt.cmdval && p_vci_tgt.eop ){
+            r_tgt_cmd_fsm = TGT_CMD_IDLE;
+          }
+          break;
+        }
+        ///////////////////
+      case TGT_CMD_WRITE:
+        {
+
+          if ( p_vci_tgt.cmdval && m_cmd_write_addr_fifo.wok() ) {
+            cmd_write_fifo_put = true;
+            if(  p_vci_tgt.eop )  r_tgt_cmd_fsm = TGT_CMD_IDLE;
+
+          }
+          break;
+        }
+        ////////////////////
+      case TGT_CMD_ATOMIC:
+        {
+          assert(p_vci_tgt.eop && "Memory Cache Error: LL or SC command with length > 1 ");
+
+          if ( p_vci_tgt.cmdval && m_cmd_llsc_addr_fifo.wok() ) {
+            cmd_llsc_fifo_put = true;
+            r_tgt_cmd_fsm = TGT_CMD_IDLE;
+          }
+          break;
+        }
+    } // end switch tgt_cmd_fsm
+
+    /////////////////////////////////////////////////////////////////////////
+    //		INIT_RSP FSM
+    /////////////////////////////////////////////////////////////////////////
+    // This FSM controls the response to the update or invalidate requests
+    // sent by the memory cache to the L1 caches :
+    //
+    // - update request initiated by the WRITE FSM.  
+    //   The FSM decrements the proper entry in the Update/Inval Table.
+    //   It sends a request to the TGT_RSP FSM to complete the pending 
+    //   write transaction (acknowledge response to the writer processor), 
+    //   and clear the UPT entry when all responses have been received.  
+    // - invalidate request initiated by the XRAM_RSP FSM.
+    //   The FSM decrements the proper entry in the Update/Inval_Table,
+    //   and clear the entry when all responses have been received.
+    //
+    // All those response packets are one word, compact
+    // packets complying with the VCI advanced format. 
+    // The index in the Table is defined in the RTRDID field, and
+    // the Transaction type is defined in the Update/Inval Table.
+    /////////////////////////////////////////////////////////////////////
+
+    switch ( r_init_rsp_fsm.read() ) {
+
+      ///////////////////
+      case INIT_RSP_IDLE:
+        {
+
+          if ( p_vci_ini.rspval ) {
+            assert ( ( p_vci_ini.rtrdid.read() < m_update_tab.size() )
+                && "VCI_MEM_CACHE UPT index too large in VCI response paquet received by memory cache" );
+            assert ( p_vci_ini.reop 
+                && "VCI_MEM_CACHE All response packets to update/invalidate requests must be one cell" );
+            r_init_rsp_upt_index = p_vci_ini.rtrdid.read(); 
+            r_init_rsp_fsm = INIT_RSP_UPT_LOCK;
+          }
+          break;
+        }
+        ///////////////////////
+      case INIT_RSP_UPT_LOCK:	// decrement the number of expected responses
+        {
+
+          if ( r_alloc_upt_fsm.read() == ALLOC_UPT_INIT_RSP ) { 
+            size_t count = 0;
+            bool valid  = m_update_tab.decrement(r_init_rsp_upt_index.read(), count);
+#ifdef IDEBUG
+	std::cout << sc_time_stamp() << " " << name() << " INIT_RSP_UPT_LOCK update table : " << std::endl;
+	m_update_tab.print();
+#endif
+            assert ( valid 
+                && "VCI_MEM_CACHE Invalid UPT entry in VCI response paquet received by memory cache" );
+
+            if ( count == 0 ) r_init_rsp_fsm = INIT_RSP_UPT_CLEAR;
+            else              r_init_rsp_fsm = INIT_RSP_IDLE;
+          }
+          break;
+        }
+        ////////////////////////
+      case INIT_RSP_UPT_CLEAR:	// clear the UPT entry
+        {
+          if ( r_alloc_upt_fsm.read() == ALLOC_UPT_INIT_RSP ) {
+            r_init_rsp_srcid = m_update_tab.srcid(r_init_rsp_upt_index.read());
+            r_init_rsp_trdid = m_update_tab.trdid(r_init_rsp_upt_index.read());
+            r_init_rsp_pktid = m_update_tab.pktid(r_init_rsp_upt_index.read());
+            r_init_rsp_nline = m_update_tab.nline(r_init_rsp_upt_index.read());
+            bool need_rsp = m_update_tab.need_rsp(r_init_rsp_upt_index.read());
+            if ( need_rsp ) r_init_rsp_fsm = INIT_RSP_END;
+            else            r_init_rsp_fsm = INIT_RSP_IDLE;
+            m_update_tab.clear(r_init_rsp_upt_index.read());
+#ifdef IDEBUG
+	std::cout << sc_time_stamp() << " " << name() << " INIT_RSP_UPT_CLEAR update table : " << std::endl;
+	m_update_tab.print();
+#endif
+          }
+          break;
+        }
+        //////////////////
+      case INIT_RSP_END:
+        {
+
+          if ( !r_init_rsp_to_tgt_rsp_req ) {
+            r_init_rsp_to_tgt_rsp_req = true;
+            r_init_rsp_to_tgt_rsp_srcid = r_init_rsp_srcid.read();
+            r_init_rsp_to_tgt_rsp_trdid = r_init_rsp_trdid.read();
+            r_init_rsp_to_tgt_rsp_pktid = r_init_rsp_pktid.read();
+            r_init_rsp_fsm = INIT_RSP_IDLE;
+          }
+          break;
+        }
+    } // end switch r_init_rsp_fsm
+
+    ////////////////////////////////////////////////////////////////////////////////////
+    //		READ FSM
+    ////////////////////////////////////////////////////////////////////////////////////
+    // The READ FSM controls the read requests sent by processors.
+    // It takes the lock protecting the cache directory to check the cache line status:
+    // - In case of HIT, the fsm copies the data (one line, or one single word)
+    //   in the r_read_to_tgt_rsp buffer. It waits if this buffer is not empty.
+    //   The requesting initiator is registered in the cache directory.
+    // - In case of MISS, the READ fsm takes the lock protecting the transaction tab.
+    //   If a read transaction to the XRAM for this line already exists,
+    //   or if the transaction tab is full, the fsm is stalled.
+    //   If a transaction entry is free, the READ fsm sends a request to the XRAM.
+    ////////////////////////////////////////////////////////////////////////////////////
+
+    switch ( r_read_fsm.read() ) {
+
+      ///////////////
+      case READ_IDLE:
+        {
+          if (m_cmd_read_addr_fifo.rok()) {
+            m_cpt_read++;
+            r_read_fsm = READ_DIR_LOCK;
+          }
+          break;
+        }
+        ///////////////////
+      case READ_DIR_LOCK:	// check directory for hit / miss
+        {
+          if( r_alloc_dir_fsm.read() == ALLOC_DIR_READ ) {
+            size_t way = 0;
+            DirectoryEntry entry = m_cache_directory.read(m_cmd_read_addr_fifo.read(), way);
+#ifdef DDEBUG
+	   std::cout << "In READ_DIR_LOCK printing the entry of address is : " << std::hex << m_cmd_read_addr_fifo.read() << std::endl;
+	   entry.print();
+	   std::cout << "done" << std::endl;
+#endif
+            r_read_is_cnt   = entry.is_cnt;
+            r_read_dirty    = entry.dirty;
+            r_read_tag	    = entry.tag;
+            r_read_lock	    = entry.lock;
+            r_read_way	    = way;
+            r_read_d_copies = entry.d_copies; 
+            r_read_i_copies = entry.i_copies; 
+            r_read_count    = entry.count;
+
+            // In case of hit, the read acces must be registered in the copies bit-vector
+            if( entry.valid )  { 
+              r_read_fsm = READ_DIR_HIT;
+            } else {
+              r_read_fsm = READ_TRT_LOCK;
+              m_cpt_read_miss++;
+            }
+          }
+          break;
+        }
+        //////////////////
+      case READ_DIR_HIT:	// read hit : update the memory cache
+        {
+          if( r_alloc_dir_fsm.read() == ALLOC_DIR_READ ) {
+            // signals generation
+            bool inst_read = (m_cmd_read_trdid_fifo.read() & 0x2);
+            bool cached_read = (m_cmd_read_trdid_fifo.read() & 0x1);
+            bool is_cnt = ((r_read_count.read() >= r_copies_limit.read()) && cached_read) || r_read_is_cnt.read() || (m_cmd_read_trdid_fifo.read() & 0x4);
+            bool is_tlb = (m_cmd_read_trdid_fifo.read() & 0x4);
+
+            // read data in the cache
+            size_t set = m_y[(vci_addr_t)(m_cmd_read_addr_fifo.read())];
+            size_t way = r_read_way.read();
+            for ( size_t i=0 ; i<m_words ; i++ ) {
+              r_read_data[i] = m_cache_data[way][set][i];
+            }
+
+            // update the cache directory (for the copies)
+            DirectoryEntry entry;
+            entry.valid	  = true;
+            entry.is_cnt  = is_cnt; // when we reach the limit of copies
+            entry.dirty	  = r_read_dirty.read();
+            entry.tag	  = r_read_tag.read();
+            entry.lock	  = r_read_lock.read();
+            if(cached_read && !is_tlb){  // Cached read, we update the copies vector
+              if(inst_read && !is_cnt){ // Instruction read, vector mode
+                assert(!(r_read_i_copies.read() & (0x1 << m_cmd_read_srcid_fifo.read())) && "MemCache Error : processor read on an already owned cache line");
+                entry.d_copies  = r_read_d_copies.read();
+                entry.i_copies  = r_read_i_copies.read() | (0x1 << m_cmd_read_srcid_fifo.read()); 
+                entry.count     = r_read_count.read() + 1;
+              }
+              if(!inst_read && !is_cnt){ // Data read, vector mode
+                assert(!(r_read_d_copies.read() & (0x1 << m_cmd_read_srcid_fifo.read())) && "MemCache Error : processor read on an already owned cache line");
+                entry.d_copies  = r_read_d_copies.read() | (0x1 << m_cmd_read_srcid_fifo.read()); 
+                entry.i_copies  = r_read_i_copies.read();
+                entry.count     = r_read_count.read() + 1;
+              }
+              if( is_cnt ) { // Counter mode
+                entry.count     = r_read_count.read() + 1;
+                entry.d_copies  = 0;
+                entry.i_copies  = 0;
+              } 
+            } else if( is_tlb && is_cnt ) { // Uncached read for TLB
+                entry.count     = r_read_count.read() + 1;
+                entry.d_copies  = 0;
+                entry.i_copies  = 0;
+            } else { // Uncached read
+              entry.d_copies = r_read_d_copies.read();
+              entry.i_copies = r_read_i_copies.read();
+              entry.count    = r_read_count.read();
+            }
+#ifdef DDEBUG
+	   std::cout << "In READ_DIR_HIT printing the entry of address is : " << std::endl;
+	   entry.print();
+	   std::cout << "done" << std::endl;
+#endif
+
+            m_cache_directory.write(set, way, entry);
+            r_read_fsm    = READ_RSP;
+          }
+          break;
+        }
+        //////////////
+      case READ_RSP: 		//  request the TGT_RSP FSM to return data
+        {
+          if( !r_read_to_tgt_rsp_req ) {	
+            for ( size_t i=0 ; i<m_words ; i++ ) {
+              r_read_to_tgt_rsp_data[i] = r_read_data[i];
+            }
+            r_read_to_tgt_rsp_word   = m_x[(vci_addr_t)m_cmd_read_addr_fifo.read()];
+            r_read_to_tgt_rsp_length = m_cmd_read_length_fifo.read();
+            cmd_read_fifo_get 		 = true;
+            r_read_to_tgt_rsp_req	 = true;
+            r_read_to_tgt_rsp_srcid	 = m_cmd_read_srcid_fifo.read();
+            r_read_to_tgt_rsp_trdid	 = m_cmd_read_trdid_fifo.read();
+            r_read_to_tgt_rsp_pktid	 = m_cmd_read_pktid_fifo.read();
+            r_read_fsm 			     = READ_IDLE;  
+          }
+          break;
+        }
+        ///////////////////
+      case READ_TRT_LOCK:	// read miss : check the Transaction Table
+        {
+          if ( r_alloc_trt_fsm.read() == ALLOC_TRT_READ ) {
+#ifdef TDEBUG
+	std::cout << sc_time_stamp() << " " << name() << " READ_TRT_LOCK " << std::endl;
+#endif
+            size_t index = 0;
+            bool   hit_read = m_transaction_tab.hit_read(m_nline[(vci_addr_t)(m_cmd_read_addr_fifo.read())], index);
+            bool   hit_write = m_transaction_tab.hit_write(m_nline[(vci_addr_t)(m_cmd_read_addr_fifo.read())]);
+            bool   wok = !m_transaction_tab.full(index);
+            if( hit_read || !wok || hit_write ) {  // missing line already requested or no space
+              r_read_fsm = READ_IDLE;
+            } else {			   // missing line is requested to the XRAM
+              r_read_trt_index = index;
+              r_read_fsm       = READ_TRT_SET;
+            }
+          }
+          break;
+        }
+        //////////////////
+      case READ_TRT_SET:
+        {
+          if ( r_alloc_trt_fsm.read() == ALLOC_TRT_READ ) {
+            m_transaction_tab.set(r_read_trt_index.read(),
+                true,
+                m_nline[(vci_addr_t)(m_cmd_read_addr_fifo.read())],
+                m_cmd_read_srcid_fifo.read(),
+                m_cmd_read_trdid_fifo.read(),
+                m_cmd_read_pktid_fifo.read(),
+                true,
+                m_cmd_read_length_fifo.read(),
+                m_x[(vci_addr_t)(m_cmd_read_addr_fifo.read())],
+                std::vector<be_t>(m_words,0),
+                std::vector<data_t>(m_words,0));
+#ifdef TDEBUG
+	std::cout << sc_time_stamp() << " " << name() << " READ_TRT_SET transaction table : " << std::endl;
+	for(size_t i = 0 ; i < m_transaction_tab.size() ; i++)
+	  m_transaction_tab.print(i);
+#endif
+
+            r_read_fsm 	 = READ_XRAM_REQ;
+          }
+          break;
+        }
+        /////////////////////
+      case READ_XRAM_REQ:
+        {
+          if( !r_read_to_ixr_cmd_req ) {
+            cmd_read_fifo_get		= true;
+            r_read_to_ixr_cmd_req  	= true;
+            r_read_to_ixr_cmd_nline 	= m_nline[(vci_addr_t)(m_cmd_read_addr_fifo.read())];
+            r_read_to_ixr_cmd_trdid 	= r_read_trt_index.read();
+            r_read_fsm 			          = READ_IDLE;
+          }
+          break;
+        }
+    } // end switch read_fsm
+
+    ///////////////////////////////////////////////////////////////////////////////////
+    //		WRITE FSM
+    ///////////////////////////////////////////////////////////////////////////////////
+    // The WRITE FSM handles the write bursts sent by the processors.
+    // All addresses in a burst must be in the same cache line.
+    // A complete write burst is consumed in the FIFO & copied to a local buffer.
+    // Then the FSM takes the lock protecting the cache directory, to check
+    // if the line is in the cache.
+    //
+    // - In case of HIT, the cache is updated.
+    //   If there is no other copy, an acknowledge response is immediately
+    //   returned to the writing processor.
+    //   if the data is cached by other processoris, the FSM takes the lock
+    //   protecting the Update Table (UPT) to register this update transaction.
+    //   If the UPT is full, it releases the lock  and waits. Then, it sends 
+    //   a multi-update request to all owners of the line (but the writer), 
+    //   through the INIT_CMD FSM. In case of multi-update transaction, the WRITE FSM 
+    //   does not respond to the writing processor, as this response will be sent by 
+    //   the INIT_RSP FSM when all update responses have been received.
+    //
+    // - In case of MISS, the WRITE FSM takes the lock protecting the transaction
+    //   table (TRT). If a read transaction to the XRAM for this line already exists, 
+    //   it writes in the TRT (write buffer). Otherwise, if a TRT entry is free, 
+    //   the WRITE FSM register a new transaction in TRT, and sends a read line request 
+    //   to the XRAM. If the TRT is full, it releases the lock, and waits.
+    //   Finally, the WRITE FSM returns an aknowledge response to the writing processor.
+    /////////////////////////////////////////////////////////////////////////////////////
+
+    switch ( r_write_fsm.read() ) {
+
+      ////////////////
+      case WRITE_IDLE:	// copy first word of a write burst in local buffer	
+        {
+          if ( m_cmd_write_addr_fifo.rok()) {
+            m_cpt_write++;
+            m_cpt_write_cells++;
+            // consume a word in the FIFO & write it in the local buffer 
+            cmd_write_fifo_get	= true;
+            size_t index 	    = m_x[(vci_addr_t)(m_cmd_write_addr_fifo.read())];
+            r_write_address	    = (addr_t)(m_cmd_write_addr_fifo.read());
+            r_write_word_index	= index;
+            r_write_word_count	= 1;
+            r_write_data[index]	= m_cmd_write_data_fifo.read();
+            r_write_srcid	    = m_cmd_write_srcid_fifo.read();
+            r_write_trdid	    = m_cmd_write_trdid_fifo.read();
+            r_write_pktid	    = m_cmd_write_pktid_fifo.read();
+
+            // the be field must be set for all words 
+            for ( size_t i=0 ; i<m_words ; i++ ) {
+              if ( i == index ) r_write_be[i] = m_cmd_write_be_fifo.read();
+              else		        r_write_be[i] = 0x0;
+            }
+            if( !((m_cmd_write_be_fifo.read() == 0x0)||(m_cmd_write_be_fifo.read() == 0xF)) )
+                    r_write_byte=true;
+            else    r_write_byte=false;
+
+            if( m_cmd_write_eop_fifo.read() )  r_write_fsm = WRITE_DIR_LOCK;
+            else                               r_write_fsm = WRITE_NEXT;
+          }
+          break;
+        }
+        ////////////////
+      case WRITE_NEXT:	// copy next word of a write burst in local buffer
+        {
+          if ( m_cmd_write_addr_fifo.rok() ) {
+            m_cpt_write_cells++;
+
+            // check that the next word is in the same cache line
+            assert( (m_nline[(vci_addr_t)(r_write_address.read())] == m_nline[(vci_addr_t)(m_cmd_write_addr_fifo.read())])  
+                && "VCI_MEM_CACHE write error in vci_mem_cache : write burst over a line" );
+            // consume a word in the FIFO & write it in the local buffer 
+            cmd_write_fifo_get=true;
+            size_t index 	        = r_write_word_index.read() + r_write_word_count.read();
+            r_write_be[index]       = m_cmd_write_be_fifo.read();
+            r_write_data[index]     = m_cmd_write_data_fifo.read();
+            r_write_word_count 	    = r_write_word_count.read() + 1;
+            if( !((m_cmd_write_be_fifo.read() == 0x0)||(m_cmd_write_be_fifo.read() == 0xF)) )
+              r_write_byte=true;
+            if ( m_cmd_write_eop_fifo.read() )  r_write_fsm = WRITE_DIR_LOCK;
+          }
+          break;
+        }
+        ////////////////////
+      case WRITE_DIR_LOCK:	// access directory to check hit/miss
+        {
+          if ( r_alloc_dir_fsm.read() == ALLOC_DIR_WRITE ) {
+            size_t  way = 0;
+            DirectoryEntry entry(m_cache_directory.read(r_write_address.read(), way));
+
+            // copy directory entry in local buffers in case of hit
+            if ( entry.valid )  {	
+              r_write_is_cnt    = entry.is_cnt;
+              r_write_lock	    = entry.lock;
+              r_write_tag       = entry.tag;
+              r_write_d_copies  = entry.d_copies;
+              r_write_i_copies  = entry.i_copies;
+              r_write_count     = entry.count;
+              r_write_way  	    = way;
+              if((entry.is_cnt && entry.count) ||
+                  entry.i_copies){
+                r_write_fsm      = WRITE_DIR_HIT_READ;
+              } else {
+                if(r_write_byte.read())
+                  r_write_fsm      = WRITE_DIR_HIT_READ;
+                else {
+                    bool owner     = (bool) (entry.d_copies & (0x1 << r_write_srcid.read()));
+                    bool no_update = (owner && (entry.count == 1)) || (entry.count==0);
+                    if( no_update ) r_write_fsm  = WRITE_DIR_HIT_RSP; 
+                    else            r_write_fsm  = WRITE_DIR_HIT;
+                }
+              }
+            } else {
+              r_write_fsm = WRITE_TRT_LOCK;
+              m_cpt_write_miss++;
+            }
+          }
+          break;
+        }
+        ///////////////////
+      case WRITE_DIR_HIT_READ:	// read the cache and complete the buffer (data, when be!=0xF)
+        {
+          // update local buffer
+          size_t set	= m_y[(vci_addr_t)(r_write_address.read())];
+          size_t way	= r_write_way.read();
+          for(size_t i=0 ; i<m_words ; i++) {
+            data_t mask      = 0;
+            if  (r_write_be[i].read() & 0x1) mask = mask | 0x000000FF;
+            if  (r_write_be[i].read() & 0x2) mask = mask | 0x0000FF00;
+            if  (r_write_be[i].read() & 0x4) mask = mask | 0x00FF0000;
+            if  (r_write_be[i].read() & 0x8) mask = mask | 0xFF000000;
+            if(r_write_be[i].read()||r_write_is_cnt.read()||r_write_i_copies.read()) { // complete only if mask is not null (for energy consumption)
+              r_write_data[i]  = (r_write_data[i].read() & mask) | 
+                (m_cache_data[way][set][i] & ~mask);
+            }
+          } // end for
+
+          if((r_write_is_cnt.read() && r_write_count.read()) ||
+              r_write_i_copies.read()){
+              r_write_fsm    = WRITE_TRT_WRITE_LOCK;
+          } else {
+              bool owner     = (bool) (r_write_d_copies.read() & (0x1 << r_write_srcid.read()));
+              bool no_update = (owner && (r_write_count.read() == 1)) || (r_write_count.read()==0);
+              if( no_update )   r_write_fsm    = WRITE_DIR_HIT_RSP;
+              else              r_write_fsm    = WRITE_DIR_HIT;
+          }
+          break;
+        }
+        ///////////////////
+      case WRITE_DIR_HIT:	// update the cache (data & dirty bit)
+        {
+          // update directory with Dirty bit
+          DirectoryEntry entry;
+          entry.valid	    = true;
+          entry.dirty	    = true;
+          entry.tag	        = r_write_tag.read();
+          entry.is_cnt      = r_write_is_cnt.read();
+          entry.lock	    = r_write_lock.read();
+          entry.d_copies    = r_write_d_copies.read();
+          entry.i_copies    = 0;
+          entry.count       = r_write_count.read();
+          size_t set	    = m_y[(vci_addr_t)(r_write_address.read())];
+          size_t way	    = r_write_way.read();
+          m_cache_directory.write(set, way, entry);
+
+          // write data in cache
+          for(size_t i=0 ; i<m_words ; i++) {
+            if  ( r_write_be[i].read() ) {
+              m_cache_data[way][set][i]  = r_write_data[i].read();
+            }
+          } // end for
+
+          // compute the actual number of copies & the modified bit vector
+          bool owner = (bool) (r_write_d_copies.read() & (0x1 << r_write_srcid.read()));
+          copy_t d_copies = r_write_d_copies.read() & ~(0x1 << r_write_srcid.read());
+          r_write_d_copies      = d_copies;
+          size_t count_signal   = r_write_count.read();
+          if(owner){
+            count_signal        = count_signal - 1;
+          }
+          r_write_count         = count_signal;
+
+          r_write_fsm = WRITE_UPT_LOCK;
+          break;
+        }
+        ///////////////////
+      case WRITE_DIR_HIT_RSP:	// update the cache (data & dirty bit) (no update)
+        {
+          // update directory with Dirty bit
+          DirectoryEntry entry;
+          entry.valid	    = true;
+          entry.dirty	    = true;
+          entry.tag	        = r_write_tag.read();
+          entry.is_cnt      = r_write_is_cnt.read();
+          entry.lock	    = r_write_lock.read();
+          entry.d_copies    = r_write_d_copies.read();
+          entry.i_copies    = 0;
+          entry.count       = r_write_count.read();
+          size_t set	    = m_y[(vci_addr_t)(r_write_address.read())];
+          size_t way	    = r_write_way.read();
+          m_cache_directory.write(set, way, entry);
+
+          // write data in cache
+          for(size_t i=0 ; i<m_words ; i++) {
+            if  ( r_write_be[i].read() ) {
+              m_cache_data[way][set][i]  = r_write_data[i].read();
+            }
+          } // end for
+
+          if ( !r_write_to_tgt_rsp_req.read() ) {
+            r_write_to_tgt_rsp_req	    = true;
+            r_write_to_tgt_rsp_srcid	= r_write_srcid.read();
+            r_write_to_tgt_rsp_trdid	= r_write_trdid.read();
+            r_write_to_tgt_rsp_pktid	= r_write_pktid.read();
+            r_write_fsm 		        = WRITE_IDLE;
+          } else {
+            r_write_fsm = WRITE_RSP;
+          }
+          break;
+        }
+
+        /////////////////////
+      case WRITE_UPT_LOCK: 	// Try to register the request in Update Table
+        {
+
+          if ( r_alloc_upt_fsm.read() == ALLOC_UPT_WRITE ) {
+            bool        wok        = false;
+            size_t      index      = 0;
+            size_t      srcid      = r_write_srcid.read();
+            size_t      trdid      = r_write_trdid.read();
+            size_t      pktid      = r_write_pktid.read();
+            addr_t      nline      = m_nline[(vci_addr_t)(r_write_address.read())];
+            size_t      nb_copies  = r_write_count.read();
+
+            wok =m_update_tab.set(true,	// it's an update transaction
+                false,                  // it's not a broadcast
+                true,                   // it needs a response
+                srcid,
+                trdid,
+                pktid,
+                nline,
+                nb_copies,
+                index);
+#ifdef IDEBUG
+            if(wok){
+	std::cout << sc_time_stamp() << " " << name() << " WRITE_UPT_LOCK update table : " << std::endl;
+	m_update_tab.print();
+            }
+#endif
+            r_write_upt_index = index;
+            //  releases the lock protecting Update Table if no entry...
+            if ( wok ) r_write_fsm = WRITE_UPDATE;
+            else       r_write_fsm = WRITE_WAIT_UPT;
+          }
+          break;
+        }
+        ////////////////////
+      case WRITE_WAIT_UPT:	// release the lock protecting UPT
+        {
+          r_write_fsm = WRITE_UPT_LOCK;
+          break;
+        }
+        //////////////////
+      case WRITE_UPDATE:	// send a multi-update request to INIT_CMD fsm
+        {
+
+          if ( !r_write_to_init_cmd_req ) {
+            r_write_to_init_cmd_req      = true;
+            r_write_to_init_cmd_brdcast  = false;
+            r_write_to_init_cmd_trdid    = r_write_upt_index.read();
+            r_write_to_init_cmd_nline    = m_nline[(vci_addr_t)(r_write_address.read())];
+            r_write_to_init_cmd_index    = r_write_word_index.read();
+            r_write_to_init_cmd_count    = r_write_word_count.read();
+            r_write_to_init_cmd_d_copies = r_write_d_copies.read();
+
+            for(size_t i=0; i<m_words ; i++){
+              if(r_write_be[i].read())  r_write_to_init_cmd_we[i]=true;
+              else                      r_write_to_init_cmd_we[i]=false;
+            }
+
+            size_t min = r_write_word_index.read();
+            size_t max = r_write_word_index.read() + r_write_word_count.read();
+            for (size_t i=min ; i<max ; i++) {
+              r_write_to_init_cmd_data[i] = r_write_data[i];
+            }
+            r_write_fsm = WRITE_IDLE; // Response will be sent after receiving
+            // all update responses
+          }
+          break;
+        }
+        ///////////////
+      case WRITE_RSP:		// send a request to TGT_RSP FSM to acknowledge the write
+        {
+          if ( !r_write_to_tgt_rsp_req.read() ) {
+            r_write_to_tgt_rsp_req	    = true;
+            r_write_to_tgt_rsp_srcid	= r_write_srcid.read();
+            r_write_to_tgt_rsp_trdid	= r_write_trdid.read();
+            r_write_to_tgt_rsp_pktid	= r_write_pktid.read();
+            r_write_fsm 		        = WRITE_IDLE;
+          }
+          break;
+        }
+        ////////////////////
+      case WRITE_TRT_LOCK:	// Miss : check Transaction Table
+        {
+          if ( r_alloc_trt_fsm.read() == ALLOC_TRT_WRITE ) {
+#ifdef TDEBUG
+	std::cout << sc_time_stamp() << " " << name() << " READ_TRT_LOCK " << std::endl;
+#endif
+            size_t hit_index = 0;
+            size_t wok_index = 0;
+            bool hit_read  = m_transaction_tab.hit_read(m_nline[(vci_addr_t)(r_write_address.read())],hit_index);
+            bool hit_write = m_transaction_tab.hit_write(m_nline[(vci_addr_t)(r_write_address.read())]);
+            bool wok = !m_transaction_tab.full(wok_index);
+            if ( hit_read ) {	// register the modified data in TRT 
+              r_write_trt_index = hit_index;
+              r_write_fsm       = WRITE_TRT_DATA;
+            } else if ( wok && !hit_write ) {	// set a new entry in TRT
+              r_write_trt_index = wok_index;
+              r_write_fsm       = WRITE_TRT_SET;
+            } else {		// wait an empty entry in TRT
+              r_write_fsm       = WRITE_WAIT_TRT;
+            }
+          }
+          break;
+        }
+        ////////////////////
+      case WRITE_WAIT_TRT:	// release the lock protecting TRT
+        { 
+          r_write_fsm = WRITE_DIR_LOCK;
+          break;
+        }
+        ///////////////////
+      case WRITE_TRT_SET:	// register a new transaction in TRT (Write Buffer)
+        {  
+          if ( r_alloc_trt_fsm.read() == ALLOC_TRT_WRITE ) 
+          {
+            std::vector<be_t> be_vector;
+            std::vector<data_t> data_vector;
+            be_vector.clear();
+            data_vector.clear();
+            for ( size_t i=0; i<m_words; i++ ) 
+            {
+              be_vector.push_back(r_write_be[i]);
+              data_vector.push_back(r_write_data[i]);
+            }
+            m_transaction_tab.set(r_write_trt_index.read(),
+                true,				// read request to XRAM
+                m_nline[(vci_addr_t)(r_write_address.read())],
+                r_write_srcid.read(),
+                r_write_trdid.read(),
+                r_write_pktid.read(),
+                false,				// not a processor read
+                0,  				// not a single word 
+                0,		        	// word index
+                be_vector,
+                data_vector);
+#ifdef TDEBUG
+	std::cout << sc_time_stamp() << " " << name() << " WRITE_TRT_SET transaction table : " << std::endl;
+	for(size_t i = 0 ; i < m_transaction_tab.size() ; i++)
+	  m_transaction_tab.print(i);
+#endif
+
+            r_write_fsm = WRITE_XRAM_REQ;
+          }
+          break;
+        }  
+        ///////////////////
+      case WRITE_TRT_DATA:	// update an entry in TRT (Write Buffer)
+        { 
+          if ( r_alloc_trt_fsm.read() == ALLOC_TRT_WRITE ) {
+            std::vector<be_t> be_vector;
+            std::vector<data_t> data_vector;
+            be_vector.clear();
+            data_vector.clear();
+            for ( size_t i=0; i<m_words; i++ ) {
+              be_vector.push_back(r_write_be[i]);
+              data_vector.push_back(r_write_data[i]);
+            }
+            m_transaction_tab.write_data_mask(r_write_trt_index.read(),
+                be_vector,
+                data_vector);
+            r_write_fsm = WRITE_RSP;
+#ifdef TDEBUG
+	std::cout << sc_time_stamp() << " " << name() << " WRITE_TRT_DATA transaction table : " << std::endl;
+	for(size_t i = 0 ; i < m_transaction_tab.size() ; i++)
+	  m_transaction_tab.print(i);
+#endif
+
+          }
+          break;
+        }
+        ////////////////////
+      case WRITE_XRAM_REQ:	// send a request to IXR_CMD FSM
+        {  
+
+          if ( !r_write_to_ixr_cmd_req ) {
+            r_write_to_ixr_cmd_req   = true;
+            r_write_to_ixr_cmd_write = false;
+            r_write_to_ixr_cmd_nline = m_nline[(vci_addr_t)(r_write_address.read())];
+            r_write_to_ixr_cmd_trdid = r_write_trt_index.read();
+            r_write_fsm              = WRITE_RSP;
+          }
+          break;
+        }
+        ////////////////////
+      case WRITE_TRT_WRITE_LOCK:
+        {
+          if ( r_alloc_trt_fsm.read() == ALLOC_TRT_WRITE ) {
+            size_t wok_index = 0;
+            bool wok = !m_transaction_tab.full(wok_index);
+            if ( wok ) {	// set a new entry in TRT
+              r_write_trt_index = wok_index;
+              r_write_fsm       = WRITE_INVAL_LOCK;
+            } else {		// wait an empty entry in TRT
+              r_write_fsm       = WRITE_WAIT_TRT;
+            }
+          }
+
+          break;
+        }
+        ////////////////////
+      case WRITE_INVAL_LOCK:
+        {
+          if ( r_alloc_upt_fsm.read() == ALLOC_UPT_WRITE ) {
+            bool        wok       = false;
+            size_t      index     = 0;
+            size_t      srcid     = r_write_srcid.read();
+            size_t      trdid     = r_write_trdid.read();
+            size_t      pktid     = r_write_pktid.read();
+            addr_t	    nline     = m_nline[(vci_addr_t)(r_write_address.read())];
+            size_t      nb_copies = r_write_count.read();
+
+            wok =m_update_tab.set(false,	// it's an inval transaction
+                true,                       // it's a broadcast
+                true,                       // it needs a response
+                srcid,
+                trdid,
+                pktid,
+                nline,
+                nb_copies,
+                index);
+#ifdef IDEBUG
+            if(wok){
+	std::cout << sc_time_stamp() << " " << name() << " WRITE_INVAL_LOCK update table : " << std::endl;
+	m_update_tab.print();
+            }
+#endif
+            r_write_upt_index = index;
+            //  releases the lock protecting Update Table if no entry...
+            if ( wok ) r_write_fsm = WRITE_DIR_INVAL;
+            else       r_write_fsm = WRITE_WAIT_TRT;
+          }
+
+          break;
+        }
+        ////////////////////
+      case WRITE_DIR_INVAL:
+        {
+          if ( (r_alloc_trt_fsm.read() == ALLOC_TRT_WRITE ) &&
+              (r_alloc_upt_fsm.read() == ALLOC_UPT_WRITE ) )
+          {
+            m_transaction_tab.set(r_write_trt_index.read(),
+                false,				// write request to XRAM
+                m_nline[(vci_addr_t)(r_write_address.read())],
+                0,
+                0,
+                0,
+                false,				// not a processor read
+                0,  				// not a single word 
+                0,		        	// word index
+                std::vector<be_t>(m_words,0),
+                std::vector<data_t>(m_words,0));
+#ifdef TDEBUG
+	std::cout << sc_time_stamp() << " " << name() << " WRITE_DIR_INVAL transaction table : " << std::endl;
+	for(size_t i = 0 ; i < m_transaction_tab.size() ; i++)
+	  m_transaction_tab.print(i);
+#endif
+
+            // invalidate directory entry
+            DirectoryEntry entry;
+            entry.valid	   = false;
+            entry.dirty	   = false;
+            entry.tag	   = 0;
+            entry.is_cnt   = false;
+            entry.lock	   = false;
+            entry.d_copies = 0;
+            entry.i_copies = 0;
+            entry.count    = 0;
+            size_t set	   = m_y[(vci_addr_t)(r_write_address.read())];
+            size_t way	   = r_write_way.read();
+            m_cache_directory.write(set, way, entry);
+
+            r_write_fsm = WRITE_INVAL;
+          } else {
+            assert(false && "LOCK ERROR in WRITE_FSM, STATE = WRITE_DIR_INVAL");
+          }
+
+          break;
+        }
+        ////////////////////
+      case WRITE_INVAL:
+        {
+          if ( !r_write_to_init_cmd_req ) {
+            r_write_to_init_cmd_req      = true;
+            r_write_to_init_cmd_brdcast  = true;
+            r_write_to_init_cmd_trdid    = r_write_upt_index.read();
+            r_write_to_init_cmd_nline    = m_nline[(vci_addr_t)(r_write_address.read())];
+            r_write_to_init_cmd_index    = 0;
+            r_write_to_init_cmd_count    = 0;
+            r_write_to_init_cmd_d_copies = 0;
+
+            for(size_t i=0; i<m_words ; i++){
+              r_write_to_init_cmd_we[i]=false;
+              r_write_to_init_cmd_data[i] = 0;
+            }
+            r_write_fsm = WRITE_XRAM_SEND;
+            // all update responses
+          }
+
+          break;
+        }
+        ////////////////////
+      case WRITE_XRAM_SEND:
+        {
+          if ( !r_write_to_ixr_cmd_req ) {
+            r_write_to_ixr_cmd_req     = true;
+            r_write_to_ixr_cmd_write   = true;
+            r_write_to_ixr_cmd_nline   = m_nline[(vci_addr_t)(r_write_address.read())];
+            r_write_to_ixr_cmd_trdid   = r_write_trt_index.read();
+            for(size_t i=0; i<m_words; i++){
+              r_write_to_ixr_cmd_data[i] = r_write_data[i];
+            }
+            r_write_fsm                 = WRITE_IDLE;
+          }
+          break;
+        }
+    } // end switch r_write_fsm
+
+    ///////////////////////////////////////////////////////////////////////
+    //		IXR_CMD FSM
+    ///////////////////////////////////////////////////////////////////////
+    // The IXR_CMD fsm controls the command packets to the XRAM :
+    // - It sends a single cell VCI read to the XRAM in case of MISS request
+    // posted by the READ, WRITE or LLSC FSMs : the TRDID field contains 
+    // the Transaction Tab index.
+    // The VCI response is a multi-cell packet : the N cells contain
+    // the N data words.
+    // - It sends a multi-cell VCI write when the XRAM_RSP FSM request 
+    // to save a dirty line to the XRAM. 
+    // The VCI response is a single cell packet.
+    // This FSM handles requests from the READ, WRITE, LLSC & XRAM_RSP FSMs 
+    // with a round-robin priority.
+    ////////////////////////////////////////////////////////////////////////
+
+    switch ( r_ixr_cmd_fsm.read() ) {
+      //////////////////////// 
+      case IXR_CMD_READ_IDLE:
+        if      ( r_write_to_ixr_cmd_req )     r_ixr_cmd_fsm = IXR_CMD_WRITE_NLINE;
+        else if ( r_llsc_to_ixr_cmd_req  )     r_ixr_cmd_fsm = IXR_CMD_LLSC_NLINE;
+        else if ( r_xram_rsp_to_ixr_cmd_req  ) r_ixr_cmd_fsm = IXR_CMD_XRAM_DATA;
+        else if ( r_read_to_ixr_cmd_req  )     r_ixr_cmd_fsm = IXR_CMD_READ_NLINE;
+        break;
+        //////////////////////// 
+      case IXR_CMD_WRITE_IDLE:
+        if      ( r_llsc_to_ixr_cmd_req  )     r_ixr_cmd_fsm = IXR_CMD_LLSC_NLINE;
+        else if ( r_xram_rsp_to_ixr_cmd_req  ) r_ixr_cmd_fsm = IXR_CMD_XRAM_DATA;
+        else if ( r_read_to_ixr_cmd_req  )     r_ixr_cmd_fsm = IXR_CMD_READ_NLINE;
+        else if ( r_write_to_ixr_cmd_req )     r_ixr_cmd_fsm = IXR_CMD_WRITE_NLINE;
+        break;
+        //////////////////////// 
+      case IXR_CMD_LLSC_IDLE:
+        if      ( r_xram_rsp_to_ixr_cmd_req  ) r_ixr_cmd_fsm = IXR_CMD_XRAM_DATA;
+        else if ( r_read_to_ixr_cmd_req  )     r_ixr_cmd_fsm = IXR_CMD_READ_NLINE;
+        else if ( r_write_to_ixr_cmd_req )     r_ixr_cmd_fsm = IXR_CMD_WRITE_NLINE;
+        else if ( r_llsc_to_ixr_cmd_req  )     r_ixr_cmd_fsm = IXR_CMD_LLSC_NLINE;
+        break;
+        //////////////////////// 
+      case IXR_CMD_XRAM_IDLE:
+        if      ( r_read_to_ixr_cmd_req  )     r_ixr_cmd_fsm = IXR_CMD_READ_NLINE;
+        else if ( r_write_to_ixr_cmd_req )     r_ixr_cmd_fsm = IXR_CMD_WRITE_NLINE;
+        else if ( r_llsc_to_ixr_cmd_req  )     r_ixr_cmd_fsm = IXR_CMD_LLSC_NLINE;
+        else if ( r_xram_rsp_to_ixr_cmd_req  ) r_ixr_cmd_fsm = IXR_CMD_XRAM_DATA;
+        break;
+        /////////////////////////
+      case IXR_CMD_READ_NLINE:
+        if ( p_vci_ixr.cmdack ) {
+          r_ixr_cmd_fsm = IXR_CMD_READ_IDLE;		
+          r_read_to_ixr_cmd_req = false;
+        }
+        break;
+        //////////////////////////
+      case IXR_CMD_WRITE_NLINE:
+        if ( p_vci_ixr.cmdack ) {
+          if( r_write_to_ixr_cmd_write.read()){
+            if ( r_ixr_cmd_cpt.read() == (m_words - 1) ) {
+              r_ixr_cmd_cpt = 0;
+              r_ixr_cmd_fsm = IXR_CMD_WRITE_IDLE;
+              r_write_to_ixr_cmd_req = false;
+            } else {
+              r_ixr_cmd_cpt = r_ixr_cmd_cpt + 1;
+            }
+          } else {
+            r_ixr_cmd_fsm = IXR_CMD_WRITE_IDLE;		
+            r_write_to_ixr_cmd_req = false;
+          }
+        }
+        break;
+        /////////////////////////
+      case IXR_CMD_LLSC_NLINE:
+        if ( p_vci_ixr.cmdack ) {
+          if( r_llsc_to_ixr_cmd_write.read()){
+            if ( r_ixr_cmd_cpt.read() == (m_words - 1) ) {
+              r_ixr_cmd_cpt = 0;
+              r_ixr_cmd_fsm = IXR_CMD_LLSC_IDLE;
+              r_llsc_to_ixr_cmd_req = false;
+            } else {
+              r_ixr_cmd_cpt = r_ixr_cmd_cpt + 1;
+            }
+          } else {
+            r_ixr_cmd_fsm = IXR_CMD_LLSC_IDLE;		
+            r_llsc_to_ixr_cmd_req = false;
+          }
+        }
+        break;
+        ////////////////////////
+      case IXR_CMD_XRAM_DATA:
+        if ( p_vci_ixr.cmdack ) {
+          if ( r_ixr_cmd_cpt.read() == (m_words - 1) ) {
+            r_ixr_cmd_cpt = 0;
+            r_ixr_cmd_fsm = IXR_CMD_XRAM_IDLE;
+            r_xram_rsp_to_ixr_cmd_req = false;
+          } else {
+            r_ixr_cmd_cpt = r_ixr_cmd_cpt + 1;
+          }
+        }
+        break;
+
+    } // end switch r_ixr_cmd_fsm
+
+    ////////////////////////////////////////////////////////////////////////////
+    //                IXR_RSP FSM
+    ////////////////////////////////////////////////////////////////////////////
+    // The IXR_RSP FSM receives the response packets from the XRAM,
+    // for both write transaction, and read transaction.
+    //
+    // - A response to a write request is a single-cell VCI packet.
+    // The Transaction Tab index is contained in the RTRDID field.
+    // The FSM takes the lock protecting the TRT, and the corresponding
+    // entry is erased.
+    //	
+    // - A response to a read request is a multi-cell VCI packet.
+    // The Transaction Tab index is contained in the RTRDID field.
+    // The N cells contain the N words of the cache line in the RDATA field.
+    // The FSM takes the lock protecting the TRT to store the line in the TRT
+    // (taking into account the write requests already stored in the TRT).
+    // When the line is completely written, the corresponding rok signal is set.
+    ///////////////////////////////////////////////////////////////////////////////
+
+    switch ( r_ixr_rsp_fsm.read() ) {
+
+      ///////////////////
+      case IXR_RSP_IDLE:	// test if it's a read or a write transaction
+        {
+          if ( p_vci_ixr.rspval ) {
+            r_ixr_rsp_cpt   = 0;
+            r_ixr_rsp_trt_index = p_vci_ixr.rtrdid.read();
+            if ( p_vci_ixr.reop )  r_ixr_rsp_fsm = IXR_RSP_ACK;
+            else                   r_ixr_rsp_fsm = IXR_RSP_TRT_READ;
+          }
+          break;  
+        }
+        ////////////////////////
+      case IXR_RSP_ACK:        // Acknowledge the vci response
+        r_ixr_rsp_fsm = IXR_RSP_TRT_ERASE;
+        break;
+        ////////////////////////
+      case IXR_RSP_TRT_ERASE: 	// erase the entry in the TRT
+        {
+          if ( r_alloc_trt_fsm.read() == ALLOC_TRT_IXR_RSP ) {
+            m_transaction_tab.erase(r_ixr_rsp_trt_index.read());
+            r_ixr_rsp_fsm = IXR_RSP_IDLE;
+#ifdef TDEBUG
+	std::cout << sc_time_stamp() << " " << name() << " IXR_RSP_TRT_ERASE transaction table : " << std::endl;
+	for(size_t i = 0 ; i < m_transaction_tab.size() ; i++)
+	  m_transaction_tab.print(i);
+#endif
+
+          }
+          break;
+        }
+        ///////////////////////
+      case IXR_RSP_TRT_READ:		// write data in the TRT
+        {
+          if ( (r_alloc_trt_fsm.read() == ALLOC_TRT_IXR_RSP) &&  p_vci_ixr.rspval ) {
+            bool   eop  	= p_vci_ixr.reop.read();
+            data_t data 	= p_vci_ixr.rdata.read();
+            size_t index        = r_ixr_rsp_trt_index.read();
+            assert( eop == (r_ixr_rsp_cpt.read() == (m_words-1)) 
+                && "Error in VCI_MEM_CACHE : invalid length for a response from XRAM");
+            m_transaction_tab.write_rsp(index, r_ixr_rsp_cpt.read(), data);
+            r_ixr_rsp_cpt = r_ixr_rsp_cpt.read() + 1;
+            if ( eop ) {
+#ifdef TDEBUG
+	std::cout << sc_time_stamp() << " " << name() << " IXR_RSP_TRT_READ transaction table : " << std::endl;
+	for(size_t i = 0 ; i < m_transaction_tab.size() ; i++)
+	  m_transaction_tab.print(i);
+#endif
+
+              r_ixr_rsp_to_xram_rsp_rok[r_ixr_rsp_trt_index.read()]=true;
+              r_ixr_rsp_fsm = IXR_RSP_IDLE;
+            }
+          }
+          break;
+        }
+    } // end swich r_ixr_rsp_fsm
+
+
+    ////////////////////////////////////////////////////////////////////////////
+    //                XRAM_RSP FSM
+    ////////////////////////////////////////////////////////////////////////////
+    // The XRAM_RSP FSM handles the incoming cache lines from the XRAM.
+    // The cache line has been written in the TRT buffer by the IXR_FSM.
+    //
+    // When a response is available, the corresponding TRT entry 
+    // is copied in a local buffer to be written in the cache. 
+    // Then, the FSM releases the lock protecting the TRT, and takes the lock 
+    // protecting the cache directory.
+    // It selects a cache slot and writes the line in the cache.
+    // If it was a read MISS, the XRAM_RSP FSM send a request to the TGT_RSP
+    // FSM to return the cache line to the registered processor.
+    // If there is no empty slot, a victim line is evicted, and
+    // invalidate requests are sent to the L1 caches containing copies.
+    // If this line is dirty, the XRAM_RSP FSM send a request to the IXR_CMD 
+    // FSM to save the victim line to the XRAM, and register the write transaction
+    // in the TRT (using the entry previously used by the read transaction).
+    ///////////////////////////////////////////////////////////////////////////////
+
+    switch ( r_xram_rsp_fsm.read() ) {
+
+      ///////////////////
+      case XRAM_RSP_IDLE:	// test if there is a response with a round robin priority
+        {
+          size_t ptr   = r_xram_rsp_trt_index.read();
+          size_t lines = TRANSACTION_TAB_LINES;
+          for(size_t i=0; i<lines; i++){
+            size_t index=(i+ptr+1)%lines;
+            if(r_ixr_rsp_to_xram_rsp_rok[index]){
+              r_xram_rsp_trt_index=index;
+              r_ixr_rsp_to_xram_rsp_rok[index]=false;
+              r_xram_rsp_fsm           = XRAM_RSP_DIR_LOCK;
+              break;
+#ifdef TDEBUG
+	std::cout << "XRAM_RSP FSM in XRAM_RSP_IDLE state" << std::endl;
+#endif
+            }
+          }
+          break;  
+        }
+        ///////////////////////
+      case XRAM_RSP_DIR_LOCK: 	// Take the lock on the directory
+        {
+          if( r_alloc_dir_fsm.read() == ALLOC_DIR_XRAM_RSP ) {
+            r_xram_rsp_fsm           = XRAM_RSP_TRT_COPY;
+#ifdef TDEBUG
+	std::cout << "XRAM_RSP FSM in XRAM_RSP_DIR_LOCK state" << std::endl;
+#endif
+          }
+          break;
+        }
+        ///////////////////////
+      case XRAM_RSP_TRT_COPY:		// Copy the TRT entry in the local buffer and eviction of a cache line
+        {
+          if ( (r_alloc_trt_fsm.read() == ALLOC_TRT_XRAM_RSP) ) {
+            size_t index = r_xram_rsp_trt_index.read();
+            TransactionTabEntry    trt_entry(m_transaction_tab.read(index));	
+
+            r_xram_rsp_trt_buf.copy(trt_entry);  // TRT entry local buffer
+
+            // selects & extracts a victim line from cache
+            size_t way = 0;
+            size_t set = m_y[(vci_addr_t)(trt_entry.nline * m_words * 4)];
+            DirectoryEntry victim(m_cache_directory.select(set, way));
+
+            for (size_t i=0 ; i<m_words ; i++) r_xram_rsp_victim_data[i] = m_cache_data[way][set][i];
+
+            bool inval = (victim.count && victim.valid) ;
+
+            r_xram_rsp_victim_d_copies = victim.d_copies;
+            r_xram_rsp_victim_i_copies = victim.i_copies;
+            r_xram_rsp_victim_count    = victim.count;
+            r_xram_rsp_victim_way      = way;
+            r_xram_rsp_victim_set      = set;
+            r_xram_rsp_victim_nline    = victim.tag*m_sets + set;
+            r_xram_rsp_victim_is_cnt   = victim.is_cnt;
+            r_xram_rsp_victim_inval    = inval ;
+            r_xram_rsp_victim_dirty    = victim.dirty;
+
+            r_xram_rsp_fsm = XRAM_RSP_INVAL_LOCK;
+#ifdef TDEBUG
+	std::cout << "XRAM_RSP FSM in XRAM_RSP_TRT_COPY state" << std::endl;
+	std::cout << "Victim way : " << std::hex << way << " set " << std::hex << set << std::endl;
+	victim.print();
+#endif
+          }
+          break;
+        }
+        ///////////////////////
+      case XRAM_RSP_INVAL_LOCK:
+        {
+          if ( r_alloc_upt_fsm == ALLOC_UPT_XRAM_RSP ) {
+#ifdef IDEBUG
+	std::cout << "XRAM_RSP FSM in XRAM_RSP_INVAL_LOCK state" << std::endl;
+#endif
+            size_t index;
+            if(m_update_tab.search_inval(r_xram_rsp_trt_buf.nline, index)){
+              r_xram_rsp_fsm = XRAM_RSP_INVAL_WAIT;
+#ifdef IDEBUG
+	std::cout << "XRAM_RSP FSM in XRAM_RSP_INVAL_LOCK state to XRAM_RSP_INVAL_WAIT state" << std::endl;
+#endif
+
+            }
+	    else if(m_update_tab.is_full() && r_xram_rsp_victim_inval.read()){
+	      r_xram_rsp_fsm = XRAM_RSP_INVAL_WAIT;
+#ifdef IDEBUG
+	std::cout << "XRAM_RSP FSM in XRAM_RSP_INVAL_LOCK state to XRAM_RSP_INVAL_WAIT state" << std::endl;
+#endif
+	    }
+            else {
+              r_xram_rsp_fsm = XRAM_RSP_DIR_UPDT;
+#ifdef IDEBUG
+	std::cout << "XRAM_RSP FSM in XRAM_RSP_INVAL_LOCK state to XRAM_RSP_DIR_UPDT state" << std::endl;
+#endif
+            }
+          }
+          break;
+        }
+        ///////////////////////
+      case XRAM_RSP_INVAL_WAIT:
+        {
+          r_xram_rsp_fsm = XRAM_RSP_DIR_LOCK;
+          break;
+#ifdef IDEBUG
+	std::cout << "XRAM_RSP FSM in XRAM_RSP_INVAL_WAIT state" << std::endl;
+#endif
+        }
+        ///////////////////////
+      case XRAM_RSP_DIR_UPDT:		// updates the cache (both data & directory)
+        {
+          // signals generation
+          bool inst_read = (r_xram_rsp_trt_buf.trdid & 0x2) && r_xram_rsp_trt_buf.proc_read; // It is an instruction read
+          bool cached_read = (r_xram_rsp_trt_buf.trdid & 0x1) && r_xram_rsp_trt_buf.proc_read;
+          bool is_tlb = (r_xram_rsp_trt_buf.trdid & 0x4) && r_xram_rsp_trt_buf.proc_read;
+
+          // update data
+          size_t set   = r_xram_rsp_victim_set.read();
+          size_t way   = r_xram_rsp_victim_way.read();
+          for(size_t i=0; i<m_words ; i++){
+            m_cache_data[way][set][i] = r_xram_rsp_trt_buf.wdata[i];
+          }
+          // compute dirty 
+          bool dirty = false;
+          for(size_t i=0; i<m_words;i++){
+            dirty = dirty || (r_xram_rsp_trt_buf.wdata_be[i] != 0);
+          }
+
+          // update directory
+          DirectoryEntry entry;
+          entry.valid	  = true;
+          entry.is_cnt    = is_tlb;
+          entry.lock	  = false;
+          entry.dirty	  = dirty;
+          entry.tag	    = r_xram_rsp_trt_buf.nline / m_sets;
+          if(cached_read && !is_tlb) {
+            if(inst_read) {
+              entry.i_copies = 0x1 << r_xram_rsp_trt_buf.srcid;
+              entry.d_copies = 0x0;
+              entry.count    = 1;
+            } else {
+              entry.i_copies = 0x0;
+              entry.d_copies = 0x1 << r_xram_rsp_trt_buf.srcid;
+              entry.count    = 1;
+            }
+          } else if (is_tlb && !r_xram_rsp_trt_buf.pktid) {
+              entry.count     = 1;
+              entry.d_copies  = 0;
+              entry.i_copies  = 0;
+          } else {
+            entry.d_copies = 0;
+            entry.i_copies = 0;
+            entry.count    = 0;
+          }
+          m_cache_directory.write(set, way, entry);
+#ifdef DDEBUG
+	   std::cout << "printing the entry : " << std::endl;
+	   entry.print();
+	   std::cout << "done" << std::endl;
+#endif
+
+#ifdef TDEBUG
+	std::cout << sc_time_stamp() << " " << name() << " XRAM_RSP_DIR_UPDT transaction table : " << std::endl;
+	for(size_t i = 0 ; i < m_transaction_tab.size() ; i++)
+	  m_transaction_tab.print(i);
+#endif
+
+          if(r_xram_rsp_victim_inval.read()){
+            bool    brdcast = r_xram_rsp_victim_is_cnt.read();
+            size_t index;
+            size_t count_copies = r_xram_rsp_victim_count.read();
+
+            bool	 wok = m_update_tab.set(false,	// it's an inval transaction
+                brdcast,                          // set brdcast bit
+                false,  // it does not need a response
+                0,
+                0,
+                0,
+                r_xram_rsp_victim_nline.read(),
+                count_copies,
+                index);
+
+#ifdef IDEBUG
+            std::cout << "xram_rsp : record invalidation, time = " << std::dec << m_cpt_cycles << std::endl;
+            m_update_tab.print();
+#endif
+            r_xram_rsp_upt_index = index;
+            if(!wok) {
+              assert(false && "mem_cache error : xram_rsp_dir_upt, an update_tab entry was free but write unsuccessful");
+            }
+          }
+          // If the victim is not dirty, we erase the entry in the TRT
+          if      (!r_xram_rsp_victim_dirty.read()){
+	  m_transaction_tab.erase(r_xram_rsp_trt_index.read());
+
+	  }
+          // Next state
+          if      ( r_xram_rsp_victim_dirty.read())       r_xram_rsp_fsm = XRAM_RSP_TRT_DIRTY;
+          else if ( r_xram_rsp_trt_buf.proc_read  )       r_xram_rsp_fsm = XRAM_RSP_DIR_RSP;
+          else if ( r_xram_rsp_victim_inval.read())       r_xram_rsp_fsm = XRAM_RSP_INVAL;
+          else                                            r_xram_rsp_fsm = XRAM_RSP_IDLE;
+          break;
+        }
+        ////////////////////////
+      case XRAM_RSP_TRT_DIRTY:		// set the TRT entry (write line to XRAM) if the victim is dirty
+        {
+          if ( r_alloc_trt_fsm.read() == ALLOC_TRT_XRAM_RSP ) {
+            m_transaction_tab.set(r_xram_rsp_trt_index.read(),
+                false,				// write to XRAM
+                r_xram_rsp_victim_nline.read(), // line index
+                0,
+                0,
+                0,
+                false,
+                0,
+                0,
+                std::vector<be_t>(m_words,0),
+                std::vector<data_t>(m_words,0) );
+#ifdef TDEBUG
+	std::cout << sc_time_stamp() << " " << name() << " XRAM_RSP_TRT_DIRTY transaction table : " << std::endl;
+	for(size_t i = 0 ; i < m_transaction_tab.size() ; i++)
+	  m_transaction_tab.print(i);
+#endif
+
+            if      ( r_xram_rsp_trt_buf.proc_read  )       r_xram_rsp_fsm = XRAM_RSP_DIR_RSP;
+            else if ( r_xram_rsp_victim_inval.read())       r_xram_rsp_fsm = XRAM_RSP_INVAL;
+            else                                            r_xram_rsp_fsm = XRAM_RSP_WRITE_DIRTY;
+          }
+          break;
+        }
+        //////////////////////
+      case XRAM_RSP_DIR_RSP:     // send a request to TGT_RSP FSM in case of read
+        {
+          if ( !r_xram_rsp_to_tgt_rsp_req ) {
+            r_xram_rsp_to_tgt_rsp_srcid = r_xram_rsp_trt_buf.srcid;
+            r_xram_rsp_to_tgt_rsp_trdid = r_xram_rsp_trt_buf.trdid;
+            r_xram_rsp_to_tgt_rsp_pktid = r_xram_rsp_trt_buf.pktid;
+            for (size_t i=0; i < m_words; i++) {
+              r_xram_rsp_to_tgt_rsp_data[i] = r_xram_rsp_trt_buf.wdata[i];
+            } 
+            r_xram_rsp_to_tgt_rsp_word   = r_xram_rsp_trt_buf.word_index;
+            r_xram_rsp_to_tgt_rsp_length = r_xram_rsp_trt_buf.read_length;
+            r_xram_rsp_to_tgt_rsp_req    = true;
+
+            if      ( r_xram_rsp_victim_inval ) r_xram_rsp_fsm = XRAM_RSP_INVAL;
+            else if ( r_xram_rsp_victim_dirty ) r_xram_rsp_fsm = XRAM_RSP_WRITE_DIRTY; 
+            else                                r_xram_rsp_fsm = XRAM_RSP_IDLE;
+
+#ifdef DDEBUG
+	std::cout << "XRAM_RSP FSM in XRAM_RSP_DIR_RSP state" << std::endl;
+#endif
+          }
+          break;
+        }
+        ////////////////////
+      case XRAM_RSP_INVAL:	// send invalidate request to INIT_CMD FSM
+        {
+          if( !r_xram_rsp_to_init_cmd_req ) {	      
+            r_xram_rsp_to_init_cmd_req      = true; 
+            r_xram_rsp_to_init_cmd_brdcast  = r_xram_rsp_victim_is_cnt.read();
+            r_xram_rsp_to_init_cmd_nline    = r_xram_rsp_victim_nline.read();
+            r_xram_rsp_to_init_cmd_trdid    = r_xram_rsp_upt_index;
+            r_xram_rsp_to_init_cmd_d_copies = r_xram_rsp_victim_d_copies ;
+            r_xram_rsp_to_init_cmd_i_copies = r_xram_rsp_victim_i_copies ;
+            if ( r_xram_rsp_victim_dirty )  r_xram_rsp_fsm = XRAM_RSP_WRITE_DIRTY;
+            else		                    r_xram_rsp_fsm = XRAM_RSP_IDLE;
+#ifdef DDEBUG
+	std::cout << "XRAM_RSP FSM in XRAM_RSP_INVAL state" << std::endl;
+#endif
+          }
+          break;
+        }
+        //////////////////////////
+      case XRAM_RSP_WRITE_DIRTY:	// send a write request to IXR_CMD FSM
+        {
+          if ( !r_xram_rsp_to_ixr_cmd_req ) {
+            r_xram_rsp_to_ixr_cmd_req = true;
+            r_xram_rsp_to_ixr_cmd_nline = r_xram_rsp_victim_nline.read();
+            r_xram_rsp_to_ixr_cmd_trdid = r_xram_rsp_trt_index.read();
+            for(size_t i=0; i<m_words ; i++) {
+              r_xram_rsp_to_ixr_cmd_data[i] = r_xram_rsp_victim_data[i];
+            }
+            m_cpt_write_dirty++;
+            r_xram_rsp_fsm = XRAM_RSP_IDLE;
+#ifdef TDEBUG
+	std::cout << "XRAM_RSP FSM in XRAM_RSP_WRITE_DIRTY state" << std::endl;
+#endif
+          }
+          break;
+        }
+    } // end swich r_xram_rsp_fsm
+
+    ////////////////////////////////////////////////////////////////////////////////////
+    //		CLEANUP FSM
+    ////////////////////////////////////////////////////////////////////////////////////
+    // The CLEANUP FSM handles the cleanup request from L1 caches.
+    // It accesses the cache directory to update the list of copies.
+    //
+    ////////////////////////////////////////////////////////////////////////////////////
+    switch ( r_cleanup_fsm.read() ) {
+
+      ///////////////////
+      case CLEANUP_IDLE:
+        {
+
+          if ( p_vci_tgt_cleanup.cmdval.read() ) {
+            assert( (p_vci_tgt_cleanup.srcid.read() < m_initiators) &&
+                "VCI_MEM_CACHE error in VCI_MEM_CACHE in the CLEANUP network : The received SRCID is larger than 31");
+            bool reached = false;
+            for ( size_t index = 0 ; index < ncseg && !reached ; index++ ){
+              if ( m_cseg[index]->contains((addr_t)(p_vci_tgt_cleanup.address.read())) ){
+                reached = true;
+              }
+            }
+            if ( (p_vci_tgt_cleanup.cmd.read() == vci_param::CMD_WRITE) &&
+                (((addr_t)(p_vci_tgt_cleanup.address.read())) != BROADCAST_ADDR) &&
+                reached) {
+
+              m_cpt_cleanup++;
+
+              r_cleanup_nline      = (addr_t)(m_nline[(vci_addr_t)(p_vci_tgt_cleanup.address.read())]) ;
+              r_cleanup_srcid      = p_vci_tgt_cleanup.srcid.read();
+              r_cleanup_trdid      = p_vci_tgt_cleanup.trdid.read();
+              r_cleanup_pktid      = p_vci_tgt_cleanup.pktid.read();
+
+              r_cleanup_fsm        = CLEANUP_DIR_LOCK;
+            }
+          }
+          break;
+        }
+        //////////////////////
+      case CLEANUP_DIR_LOCK:
+        {
+          if ( r_alloc_dir_fsm.read() == ALLOC_DIR_CLEANUP ) {
+
+            // Read the directory
+            size_t way = 0;
+	        addr_t cleanup_address = r_cleanup_nline.read() * m_words * 4;
+            DirectoryEntry entry = m_cache_directory.read(cleanup_address , way);
+#ifdef DDEBUG
+	   std::cout << "In CLEANUP_DIR_LOCK printing the entry of address is : " << std::hex << cleanup_address << std::endl;
+	   entry.print();
+	   std::cout << "done" << std::endl;
+#endif
+            r_cleanup_is_cnt    = entry.is_cnt;
+            r_cleanup_dirty	    = entry.dirty;
+            r_cleanup_tag	    = entry.tag;
+            r_cleanup_lock	    = entry.lock;
+            r_cleanup_way	    = way;
+            r_cleanup_d_copies  = entry.d_copies;
+            r_cleanup_i_copies  = entry.i_copies;
+            r_cleanup_count     = entry.count;
+            // In case of hit, the copy must be cleaned in the copies bit-vector
+            if( entry.valid )  {
+              r_cleanup_fsm = CLEANUP_DIR_WRITE;
+            } else {
+              r_cleanup_fsm = CLEANUP_UPT_LOCK;
+            }
+          }
+          break;
+        }
+        ///////////////////////
+      case CLEANUP_DIR_WRITE:
+        {
+          size_t way      = r_cleanup_way.read();
+#define L2 soclib::common::uint32_log2
+          size_t set      = m_y[(vci_addr_t)(r_cleanup_nline.read() << (L2(m_words) +2))];
+#undef L2
+          bool cleanup_inst  = r_cleanup_trdid.read() & 0x1; 
+
+          // update the cache directory (for the copies)
+          DirectoryEntry entry;
+          entry.valid	= true;
+          entry.is_cnt  = r_cleanup_is_cnt.read();
+          entry.dirty	= r_cleanup_dirty.read();
+          entry.tag	= r_cleanup_tag.read();
+          entry.lock	= r_cleanup_lock.read();
+          if(r_cleanup_is_cnt.read()) { // Directory is a counter
+            entry.count  = r_cleanup_count.read() -1;
+            entry.i_copies = 0;
+            entry.d_copies = 0;
+            // response to the cache 
+            r_cleanup_fsm = CLEANUP_RSP;
+          }
+          else{                         // Directory is a vector
+            if(cleanup_inst){           // Cleanup from a ICACHE
+              if(r_cleanup_i_copies.read() & (0x1 << r_cleanup_srcid.read())){ // hit
+                entry.count  = r_cleanup_count.read() -1;
+                r_cleanup_fsm = CLEANUP_RSP;
+              } else { // miss
+                assert(false && "MemCache ERROR : Cleanup instruction hit but the line is not shared");
+              }
+              entry.i_copies  = r_cleanup_i_copies.read() & ~(0x1 << r_cleanup_srcid.read());
+              entry.d_copies  = r_cleanup_d_copies.read();
+            } else {                    // Cleanup from a DCACHE
+              if(r_cleanup_d_copies.read() & (0x1 << r_cleanup_srcid.read())){ // hit
+                entry.count  = r_cleanup_count.read() -1;
+                r_cleanup_fsm = CLEANUP_RSP; 
+              } else { // miss
+                assert(false && "MemCache ERROR : Cleanup data hit but the line is not shared");
+              }
+              entry.i_copies  = r_cleanup_i_copies.read();
+              entry.d_copies  = r_cleanup_d_copies.read() & ~(0x1 << r_cleanup_srcid.read());
+            }
+          }
+          m_cache_directory.write(set, way, entry);  
+
+          // response to the cache      
+//          r_cleanup_fsm = CLEANUP_RSP;
+
+          break;
+        }
+        /////////////////
+      case CLEANUP_UPT_LOCK:
+        {
+          if( r_alloc_upt_fsm.read() == ALLOC_UPT_CLEANUP )
+          {
+            size_t index = 0;
+            bool hit_inval;
+            hit_inval = m_update_tab.search_inval(r_cleanup_nline.read(),index);
+            if(!hit_inval) {
+#ifdef DEBUG_VCI_MEM_CACHE
+              std::cout << "MEM_CACHE WARNING: cleanup with no corresponding entry at address : " << std::hex << (r_cleanup_nline.read()*4*m_words) << std::dec << std::endl;
+#endif
+              r_cleanup_fsm = CLEANUP_RSP;
+            } else {
+              r_cleanup_write_srcid = m_update_tab.srcid(index);
+              r_cleanup_write_trdid = m_update_tab.trdid(index);
+              r_cleanup_write_pktid = m_update_tab.pktid(index);
+              r_cleanup_need_rsp    = m_update_tab.need_rsp(index);
+              r_cleanup_fsm = CLEANUP_UPT_WRITE;
+            }
+            r_cleanup_index.write(index) ; 
+          }
+          break;
+        }
+        /////////////////
+      case CLEANUP_UPT_WRITE:
+        {
+          size_t count = 0;
+          m_update_tab.decrement(r_cleanup_index.read(), count); // &count
+          if(count == 0){
+            m_update_tab.clear(r_cleanup_index.read());
+#ifdef IDEBUG
+	std::cout << sc_time_stamp() << " " << name() << " CLEANUP_UPT_WRITE update table : " << std::endl;
+	m_update_tab.print();
+#endif
+
+            if(r_cleanup_need_rsp.read()){
+              r_cleanup_fsm = CLEANUP_WRITE_RSP ;
+            } else {
+              r_cleanup_fsm = CLEANUP_RSP;
+            }
+          } else {
+            r_cleanup_fsm = CLEANUP_RSP ;
+          }
+          break;
+        }
+        /////////////////
+      case CLEANUP_WRITE_RSP:
+        {
+          if( !r_cleanup_to_tgt_rsp_req.read()) {
+            r_cleanup_to_tgt_rsp_req     = true;
+            r_cleanup_to_tgt_rsp_srcid   = r_cleanup_write_srcid.read();
+            r_cleanup_to_tgt_rsp_trdid   = r_cleanup_write_trdid.read();
+            r_cleanup_to_tgt_rsp_pktid   = r_cleanup_write_pktid.read();
+            r_cleanup_fsm = CLEANUP_RSP;
+          }
+          break;
+        }
+        /////////////////
+      case CLEANUP_RSP:
+        {
+          if(p_vci_tgt_cleanup.rspack)
+            r_cleanup_fsm = CLEANUP_IDLE;
+          break;
+        }
+    } // end switch cleanup fsm
+
+
+    ////////////////////////////////////////////////////////////////////////////////////
+    //		LLSC FSM
+    ////////////////////////////////////////////////////////////////////////////////////
+    // The LLSC FSM handles the LL & SC atomic access.
+    //
+    // For a LL :
+    // It access the directory to check hit / miss.
+    // - In case of hit, the LL request is registered in the Atomic Table and the
+    // response is sent to the requesting processor.
+    // - In case of miss, the LLSC FSM accesses the transaction table. 
+    // If a read transaction to the XRAM for this line already exists, 
+    // or if the transaction table is full, it returns to IDLE state.
+    // Otherwise, a new transaction to the XRAM is initiated.
+    // In both cases, the LL request is not consumed in the FIFO.
+    //
+    // For a SC :
+    // It access the directory to check hit / miss.
+    // - In case of hit, the Atomic Table is checked and the proper response
+    // (true or false is sent to the requesting processor.
+    // - In case of miss, the LLSC FSM accesses the transaction table. 
+    // If a read transaction to the XRAM for this line already exists, 
+    // or if the transaction table is full, it returns to IDLE state. 
+    // Otherwise, a new transaction to the XRAM is initiated.
+    // In both cases, the SC request is not consumed in the FIFO.
+    /////////////////////////////////////////////////////////////////////
+
+    switch ( r_llsc_fsm.read() ) {
+
+      ///////////////
+      case LLSC_IDLE:		// test LL / SC
+        {
+          if( m_cmd_llsc_addr_fifo.rok() ) {
+            if(m_cmd_llsc_sc_fifo.read()){
+              m_cpt_sc++;
+              r_llsc_fsm = SC_DIR_LOCK;
+            }
+            else{
+              m_cpt_ll++;
+              r_llsc_fsm = LL_DIR_LOCK;
+            }
+          }	
+          break;
+        }
+        /////////////////
+      case LL_DIR_LOCK:		// check directory for hit / miss
+        {
+          if( r_alloc_dir_fsm.read() == ALLOC_DIR_LLSC ) {
+            size_t way = 0;
+            DirectoryEntry entry(m_cache_directory.read(m_cmd_llsc_addr_fifo.read(), way));
+            r_llsc_is_cnt     = entry.is_cnt;
+            r_llsc_dirty      = entry.dirty;
+            r_llsc_tag        = entry.tag;
+            r_llsc_way        = way;
+            r_llsc_d_copies   = entry.d_copies;
+            r_llsc_i_copies   = entry.i_copies ;
+            r_llsc_count      = entry.count ;
+
+            // set Atomic Table
+            m_atomic_tab.set(m_cmd_llsc_srcid_fifo.read(), m_cmd_llsc_addr_fifo.read());
+
+            if ( entry.valid )  r_llsc_fsm = LL_DIR_HIT;
+            else                r_llsc_fsm = LLSC_TRT_LOCK;
+          }
+          break;
+        }
+        ////////////////
+      case LL_DIR_HIT:		// read hit : update the memory cache
+        {
+          size_t way	= r_llsc_way.read();
+          size_t set	= m_y[(vci_addr_t)(m_cmd_llsc_addr_fifo.read())];
+          size_t word	= m_x[(vci_addr_t)(m_cmd_llsc_addr_fifo.read())];
+
+          // update directory (lock bit & copies)
+          DirectoryEntry entry;
+          entry.valid	    = true;
+          entry.is_cnt      = r_llsc_is_cnt.read();
+          entry.dirty	    = r_llsc_dirty.read();
+          entry.lock	    = true;
+          entry.tag	        = r_llsc_tag.read();
+          entry.d_copies    = r_llsc_d_copies.read();
+          entry.i_copies    = r_llsc_i_copies.read();
+          entry.count       = r_llsc_count.read();
+          m_cache_directory.write(set, way, entry);
+
+          // read data in cache
+          r_llsc_data	= m_cache_data[way][set][word];
+
+          r_llsc_fsm 	= LL_RSP;
+          break;
+        }
+        ////////////
+      case LL_RSP:		// request the TGT_RSP FSM to return data
+        {
+          if ( !r_llsc_to_tgt_rsp_req ) {
+            cmd_llsc_fifo_get		= true;
+            r_llsc_to_tgt_rsp_data	= r_llsc_data.read();
+            r_llsc_to_tgt_rsp_srcid	= m_cmd_llsc_srcid_fifo.read();
+            r_llsc_to_tgt_rsp_trdid	= m_cmd_llsc_trdid_fifo.read();
+            r_llsc_to_tgt_rsp_pktid	= m_cmd_llsc_pktid_fifo.read();
+            r_llsc_to_tgt_rsp_req	= true;
+            r_llsc_fsm = LLSC_IDLE;
+          }
+          break;
+        }
+        /////////////////
+      case SC_DIR_LOCK:
+        {
+          if( r_alloc_dir_fsm.read() == ALLOC_DIR_LLSC ) {
+            size_t way = 0;
+            DirectoryEntry entry(m_cache_directory.read(m_cmd_llsc_addr_fifo.read(), way));
+            bool ok = m_atomic_tab.isatomic(m_cmd_llsc_srcid_fifo.read(),m_cmd_llsc_addr_fifo.read());
+            if( ok ) {
+              r_llsc_is_cnt   = entry.is_cnt;
+              r_llsc_dirty    = entry.dirty;
+              r_llsc_tag      = entry.tag;
+              r_llsc_way      = way;
+              r_llsc_d_copies = entry.d_copies;
+              r_llsc_i_copies = entry.i_copies;
+              r_llsc_count    = entry.count;
+              /* to avoid livelock, force the atomic access to fail (pseudo-)randomly */
+              bool fail = (r_llsc_lfsr % (64) == 0);
+              r_llsc_lfsr = (r_llsc_lfsr >> 1) ^ ((-(r_llsc_lfsr & 1)) & 0xd0000001);
+#ifdef RANDOMIZE_SC
+              if(fail){
+#else
+              if(0){
+#endif
+                r_llsc_fsm = SC_RSP_FALSE;
+              } else {
+                  if ( entry.valid ){
+                      if((entry.is_cnt && entry.count) || entry.i_copies) {
+                          r_llsc_fsm = SC_TRT_LOCK;
+                      } else {
+                          r_llsc_fsm = SC_DIR_HIT;
+                      }
+                  }
+                  else r_llsc_fsm = LLSC_TRT_LOCK;
+              }
+            } else {
+              r_llsc_fsm = SC_RSP_FALSE;
+            }
+          }
+          break;
+        }
+        ////////////////
+      case SC_DIR_HIT:
+        {
+          size_t way	= r_llsc_way.read();
+          size_t set	= m_y[(vci_addr_t)(m_cmd_llsc_addr_fifo.read())]; 
+          size_t word	= m_x[(vci_addr_t)(m_cmd_llsc_addr_fifo.read())]; 
+
+          // update directory (lock & dirty bits
+          DirectoryEntry entry;
+          entry.valid	    = true;
+          entry.is_cnt      = r_llsc_is_cnt.read();
+          entry.dirty	    = true;
+          entry.lock	    = true;
+          entry.tag	        = r_llsc_tag.read();
+          entry.d_copies    = r_llsc_d_copies.read();
+          entry.i_copies    = r_llsc_i_copies.read();
+          entry.count       = r_llsc_count.read();
+          m_cache_directory.write(set, way, entry);
+
+          // write data in cache
+          m_cache_data[way][set][word] = m_cmd_llsc_wdata_fifo.read();
+
+          // reset Atomic Table
+          m_atomic_tab.reset(m_cmd_llsc_addr_fifo.read());
+          
+          if(r_llsc_count.read()) {  // Shared line
+            r_llsc_fsm = SC_UPT_LOCK;
+          } else {
+            r_llsc_fsm = SC_RSP_TRUE;
+          }
+          break;
+        }
+        /////////////////////
+      case SC_UPT_LOCK: 	// Try to register the request in Update Table
+        {
+
+          if ( r_alloc_upt_fsm.read() == ALLOC_UPT_LLSC ) {
+            bool        wok        = false;
+            size_t      index      = 0;
+            size_t      srcid      = m_cmd_llsc_srcid_fifo.read();
+            size_t      trdid      = m_cmd_llsc_trdid_fifo.read();
+            size_t      pktid      = m_cmd_llsc_pktid_fifo.read();
+            addr_t	    nline      = m_nline[(vci_addr_t)(m_cmd_llsc_addr_fifo.read())];
+            size_t      nb_copies  = r_llsc_count.read();
+
+            wok =m_update_tab.set(true,	// it's an update transaction
+                false,                  // it's not a broadcast
+                true,                   // it needs a response
+                srcid,
+                trdid,
+                pktid,
+                nline,
+                nb_copies,
+                index);
+#ifdef IDEBUG
+            if(wok){
+	std::cout << sc_time_stamp() << " " << name() << " SC_UPT_LOCK update table : " << std::endl;
+	m_update_tab.print();
+            }
+#endif
+            r_llsc_upt_index = index;
+            //  releases the lock protecting Update Table if no entry...
+            if ( wok ) r_llsc_fsm = SC_UPDATE;
+            else       r_llsc_fsm = SC_WAIT_UPT;
+          }
+          break;
+        }
+        ////////////////////
+      case SC_WAIT_UPT: 	// release the lock protecting UPT
+        {
+          r_llsc_fsm = SC_UPT_LOCK;
+          break;
+        }
+        //////////////////
+      case SC_UPDATE:   	// send a multi-update request to INIT_CMD fsm
+        {
+
+          if ( !r_llsc_to_init_cmd_req ) {
+            r_llsc_to_init_cmd_req      = true;
+            r_llsc_to_init_cmd_brdcast  = false;
+            r_llsc_to_init_cmd_trdid    = r_llsc_upt_index.read();
+            r_llsc_to_init_cmd_nline    = m_nline[(vci_addr_t)(m_cmd_llsc_addr_fifo.read())];
+            r_llsc_to_init_cmd_index    = m_x[(vci_addr_t)(m_cmd_llsc_addr_fifo.read())];
+            r_llsc_to_init_cmd_wdata    = m_cmd_llsc_wdata_fifo.read();
+            r_llsc_to_init_cmd_d_copies = r_llsc_d_copies.read();
+            
+            cmd_llsc_fifo_get         = true;
+
+            r_llsc_fsm = LLSC_IDLE; // Response will be sent after receiving
+            // all update responses
+          }
+          break;
+        }
+
+        //////////////////
+      case SC_TRT_LOCK:
+        {
+          if( r_alloc_trt_fsm.read() == ALLOC_TRT_LLSC ) {
+            if( !r_llsc_to_ixr_cmd_req ) { // we can transfer the data to the buffer
+              size_t way	= r_llsc_way.read();
+              size_t set	= m_y[(vci_addr_t)(m_cmd_llsc_addr_fifo.read())];
+              for(size_t i = 0; i<m_words; i++){
+                if(i==m_x[(vci_addr_t)m_cmd_llsc_addr_fifo.read()]) {
+                  r_llsc_to_ixr_cmd_data[i] = m_cmd_llsc_wdata_fifo.read();
+                } else {
+                  r_llsc_to_ixr_cmd_data[i] = m_cache_data[way][set][i];
+                }
+              }
+              size_t wok_index = 0;
+              bool wok = !m_transaction_tab.full(wok_index);
+              if ( wok ) { // set a new entry in TRT
+                r_llsc_trt_index = wok_index;
+                r_llsc_fsm       = SC_INVAL_LOCK;
+              } else {
+                r_llsc_fsm       = LLSC_IDLE;
+              }
+            } else {
+              r_llsc_fsm = LLSC_IDLE;
+            }
+          }
+          break;
+        }
+        //////////////////
+      case SC_INVAL_LOCK:
+        {
+          if ( r_alloc_upt_fsm.read() == ALLOC_UPT_LLSC ) {
+            bool        wok       = false;
+            size_t      index     = 0;
+            size_t      srcid     = m_cmd_llsc_srcid_fifo.read();
+            size_t      trdid     = m_cmd_llsc_trdid_fifo.read();
+            size_t      pktid     = m_cmd_llsc_pktid_fifo.read();
+            addr_t	    nline     = m_nline[(vci_addr_t)(m_cmd_llsc_addr_fifo.read())];
+            size_t      nb_copies = r_llsc_count.read();
+
+            wok =m_update_tab.set(false,	// it's an inval transaction
+                true,                       // it's a broadcast
+                true,                       // it needs a response
+                srcid,
+                trdid,
+                pktid,
+                nline,
+                nb_copies,
+                index);
+#ifdef IDEBUG
+            if(wok){
+	std::cout << sc_time_stamp() << " " << name() << " LLSC_INVAL_LOCK update table : " << std::endl;
+	m_update_tab.print();
+            }
+#endif
+            r_llsc_upt_index = index;
+            //  releases the lock protecting Update Table if no entry...
+            if ( wok ) r_llsc_fsm = SC_DIR_INVAL;
+            else       r_llsc_fsm = LLSC_IDLE;
+          }
+          break;
+        }
+        //////////////////
+      case SC_DIR_INVAL:
+        {
+          if ( (r_alloc_trt_fsm.read() == ALLOC_TRT_LLSC ) &&
+              (r_alloc_upt_fsm.read() == ALLOC_UPT_LLSC ) )
+          {
+            m_transaction_tab.set(r_llsc_trt_index.read(),
+                false,				// write request to XRAM
+                m_nline[(vci_addr_t)(m_cmd_llsc_addr_fifo.read())],
+                0,
+                0,
+                0,
+                false,				// not a processor read
+                0,  				// not a single word 
+                0,		        	// word index
+                std::vector<be_t>(m_words,0),
+                std::vector<data_t>(m_words,0));
+#ifdef TDEBUG
+	std::cout << sc_time_stamp() << " " << name() << " SC_DIR_INVAL transaction table : " << std::endl;
+	for(size_t i = 0 ; i < m_transaction_tab.size() ; i++)
+	  m_transaction_tab.print(i);
+#endif
+            // reset Atomic Table
+            m_atomic_tab.reset(m_cmd_llsc_addr_fifo.read());
+
+            // invalidate directory entry
+            DirectoryEntry entry;
+            entry.valid	   = false;
+            entry.dirty	   = false;
+            entry.tag	   = 0;
+            entry.is_cnt   = false;
+            entry.lock	   = false;
+            entry.d_copies = 0;
+            entry.i_copies = 0;
+            entry.count    = 0;
+            size_t set	   = m_y[(vci_addr_t)(m_cmd_llsc_addr_fifo.read())];
+            size_t way	   = r_llsc_way.read();
+            m_cache_directory.write(set, way, entry);
+            r_llsc_fsm = SC_INVAL;
+          } else {
+            assert(false && "LOCK ERROR in LLSC_FSM, STATE = LLSC_DIR_INVAL");
+          }
+
+          break;
+
+        }
+        //////////////////
+      case SC_INVAL:
+        {
+          if ( !r_llsc_to_init_cmd_req ) {
+            r_llsc_to_init_cmd_req      = true;
+            r_llsc_to_init_cmd_brdcast  = true;
+            r_llsc_to_init_cmd_trdid    = r_llsc_upt_index.read();
+            r_llsc_to_init_cmd_nline    = m_nline[(vci_addr_t)(m_cmd_llsc_addr_fifo.read())];
+            r_llsc_to_init_cmd_index    = 0;
+            r_llsc_to_init_cmd_d_copies = 0;
+            r_llsc_to_init_cmd_wdata    = 0;
+
+            r_llsc_fsm = SC_XRAM_SEND;
+            // all update responses
+          }
+
+          break;
+        }
+        //////////////////
+      case SC_XRAM_SEND:
+        {
+          if ( !r_llsc_to_ixr_cmd_req ) {
+            r_llsc_to_ixr_cmd_req     = true;
+            r_llsc_to_ixr_cmd_write   = true;
+            r_llsc_to_ixr_cmd_nline   = m_nline[(vci_addr_t)(m_cmd_llsc_addr_fifo.read())];
+            r_llsc_to_ixr_cmd_trdid   = r_llsc_trt_index.read();
+            r_llsc_fsm                = LLSC_IDLE;
+            cmd_llsc_fifo_get         = true;
+          } else {
+            assert( false && "MEM_CACHE, LLSC FSM : SC_XRAM_SEND state : the request should not have been previously set");
+          }
+          break;
+
+        }
+        //////////////////
+      case SC_RSP_FALSE:
+        {
+          if( !r_llsc_to_tgt_rsp_req ) {
+            cmd_llsc_fifo_get		= true;
+            r_llsc_to_tgt_rsp_req	= true;
+            r_llsc_to_tgt_rsp_data	= 1;
+            r_llsc_to_tgt_rsp_srcid	= m_cmd_llsc_srcid_fifo.read();
+            r_llsc_to_tgt_rsp_trdid	= m_cmd_llsc_trdid_fifo.read();
+            r_llsc_to_tgt_rsp_pktid	= m_cmd_llsc_pktid_fifo.read();
+            r_llsc_fsm 			    = LLSC_IDLE;
+          }
+          break;
+        }
+        /////////////////
+      case SC_RSP_TRUE:
+        {
+          if( !r_llsc_to_tgt_rsp_req ) {
+            cmd_llsc_fifo_get	    = true;
+            r_llsc_to_tgt_rsp_req	= true;
+            r_llsc_to_tgt_rsp_data	= 0;
+            r_llsc_to_tgt_rsp_srcid	= m_cmd_llsc_srcid_fifo.read();
+            r_llsc_to_tgt_rsp_trdid	= m_cmd_llsc_trdid_fifo.read();
+            r_llsc_to_tgt_rsp_pktid	= m_cmd_llsc_pktid_fifo.read();
+            r_llsc_fsm 			    = LLSC_IDLE;
+          }
+          break;
+        }
+        ///////////////////
+      case LLSC_TRT_LOCK:         // read or write miss : check the Transaction Table
+        {
+          if( r_alloc_trt_fsm.read() == ALLOC_TRT_LLSC ) {
+            size_t   index = 0;
+            bool hit_read = m_transaction_tab.hit_read(m_nline[(vci_addr_t)m_cmd_llsc_addr_fifo.read()],index);
+            bool hit_write = m_transaction_tab.hit_write(m_nline[(vci_addr_t)m_cmd_llsc_addr_fifo.read()]);
+            bool wok = !m_transaction_tab.full(index);
+
+            if ( hit_read || !wok || hit_write ) {  // missing line already requested or no space in TRT
+              r_llsc_fsm = LLSC_IDLE;
+            } else {
+              r_llsc_trt_index = index;
+              r_llsc_fsm       = LLSC_TRT_SET;
+            }
+          }
+          break;
+        }
+        //////////////////
+      case LLSC_TRT_SET:	// register the XRAM transaction in Transaction Table
+        {
+          if( r_alloc_trt_fsm.read() == ALLOC_TRT_LLSC ) {
+            size_t word	= m_x[(vci_addr_t)(m_cmd_llsc_addr_fifo.read())]; 
+            bool proc_read = !m_cmd_llsc_sc_fifo.read();
+            if(proc_read){
+              m_transaction_tab.set(r_llsc_trt_index.read(),
+                  true,
+                  m_nline[(vci_addr_t)m_cmd_llsc_addr_fifo.read()],
+                  m_cmd_llsc_srcid_fifo.read(),
+                  m_cmd_llsc_trdid_fifo.read(),
+                  (m_cmd_llsc_pktid_fifo.read()|0x1),
+                  true,
+                  1,
+                  word,
+                  std::vector<be_t>(m_words,0),
+                  std::vector<data_t>(m_words,0));
+            }else{
+              std::vector<be_t> be_vector;
+              std::vector<data_t> data_vector;
+              be_vector.clear();
+              data_vector.clear();
+              // reset Atomic Table
+              m_atomic_tab.reset(m_cmd_llsc_addr_fifo.read());
+              for ( size_t i=0; i<m_words; i++ ) 
+              {   
+                if(i == word){
+                  be_vector.push_back(0xF);
+                  data_vector.push_back(m_cmd_llsc_wdata_fifo.read());
+                } else {
+                  be_vector.push_back(0);
+                  data_vector.push_back(0);
+                }
+              }
+ 
+              m_transaction_tab.set(r_llsc_trt_index.read(),
+                  true,
+                  m_nline[(vci_addr_t)m_cmd_llsc_addr_fifo.read()],
+                  m_cmd_llsc_srcid_fifo.read(),
+                  m_cmd_llsc_trdid_fifo.read(),
+                  (m_cmd_llsc_pktid_fifo.read()|0x1),
+                  false,
+                  0,
+                  0,
+                  be_vector,
+                  data_vector);
+            }
+#ifdef TDEBUG
+	std::cout << sc_time_stamp() << " " << name() << " LLSC_TRT_SET transaction table : " << std::endl;
+	for(size_t i = 0 ; i < m_transaction_tab.size() ; i++)
+	  m_transaction_tab.print(i);
+#endif
+
+            r_llsc_fsm = LLSC_XRAM_REQ;
+          }
+          break;
+        }
+        ///////////////////
+      case LLSC_XRAM_REQ:	// request the IXR_CMD FSM to fetch the missing line
+        {
+          if ( !r_llsc_to_ixr_cmd_req ) {
+            r_llsc_to_ixr_cmd_req        = true;
+            r_llsc_to_ixr_cmd_write      = false;
+            r_llsc_to_ixr_cmd_trdid      = r_llsc_trt_index.read();
+            r_llsc_to_ixr_cmd_nline      = m_nline[(vci_addr_t)m_cmd_llsc_addr_fifo.read()];
+            if( m_cmd_llsc_sc_fifo.read() ) {
+              r_llsc_fsm                 = SC_RSP_TRUE;
+            } else {
+              cmd_llsc_fifo_get          = true;
+              r_llsc_fsm                 = LLSC_IDLE;
+            }
+          }
+          break;
+        }
+    } // end switch r_llsc_fsm
+
+
+    //////////////////////////////////////////////////////////////////////////////
+    //		INIT_CMD FSM
+    //////////////////////////////////////////////////////////////////////////////
+    // The INIT_CMD fsm controls the VCI CMD initiator port, used to update
+    // or invalidate cache lines in L1 caches.
+    // It implements a round-robin priority between the two following requests:
+    // - r_write_to_init_cmd_req : update request from WRITE FSM 
+    // - r_xram_rsp_to_init_cmd_req : invalidate request from XRAM_RSP FSM 
+    // The inval request is a single cell VCI write command containing the 
+    // index of the line to be invalidated.
+    // The update request is a multi-cells VCI write command : The first cell 
+    // contains the index of the cache line to be updated. The second cell contains 
+    // the index of the first modified word in the line. The following cells
+    // contain the data.
+    ///////////////////////////////////////////////////////////////////////////////
+
+    switch ( r_init_cmd_fsm.read() ) {
+
+      //////////////////////// 
+      case INIT_CMD_UPDT_IDLE:	// Invalidate requests have highest priority
+        {
+
+          if ( r_xram_rsp_to_init_cmd_req.read() ) {
+            r_init_cmd_fsm = INIT_CMD_INVAL_SEL;
+            m_cpt_inval++;
+          } else if ( r_write_to_init_cmd_req.read() ) {
+            if(r_write_to_init_cmd_brdcast.read()){
+              r_init_cmd_fsm = INIT_CMD_BRDCAST;
+              m_cpt_inval++;
+              m_cpt_inval_brdcast++;
+            } else {
+              r_init_cmd_fsm = INIT_CMD_UPDT_SEL;
+              m_cpt_update++;
+            }
+          } else if (r_llsc_to_init_cmd_req.read() ) {
+            if(r_llsc_to_init_cmd_brdcast.read()){
+              r_init_cmd_fsm = INIT_CMD_SC_BRDCAST;
+              m_cpt_inval++;
+              m_cpt_inval_brdcast++;
+            } else {
+              r_init_cmd_fsm = INIT_CMD_SC_UPDT_SEL;
+              m_cpt_update++;
+            }
+          }
+          break;
+        }
+        /////////////////////////
+      case INIT_CMD_INVAL_IDLE:	// Update requests have highest priority
+        {
+          if ( r_write_to_init_cmd_req.read() ) {
+            if(r_write_to_init_cmd_brdcast.read()){
+              r_init_cmd_fsm = INIT_CMD_BRDCAST;
+              m_cpt_inval++;
+              m_cpt_inval_brdcast++;
+            } else {
+              r_init_cmd_fsm = INIT_CMD_UPDT_SEL;
+              m_cpt_update++;
+            }
+          } else if (r_llsc_to_init_cmd_req.read() ) {
+            if(r_llsc_to_init_cmd_brdcast.read()){
+              r_init_cmd_fsm = INIT_CMD_SC_BRDCAST;
+              m_cpt_inval++;
+              m_cpt_inval_brdcast++;
+            } else {
+              r_init_cmd_fsm = INIT_CMD_SC_UPDT_SEL;
+              m_cpt_update++;
+            }
+          } else if ( r_xram_rsp_to_init_cmd_req.read() ) {
+            r_init_cmd_fsm = INIT_CMD_INVAL_SEL;
+            m_cpt_inval++;
+          }
+          break;
+        }
+        /////////////////////////
+      case INIT_CMD_SC_UPDT_IDLE:	// Update requests for SCs have highest priority
+        {
+          if (r_llsc_to_init_cmd_req.read() ) {
+            if(r_llsc_to_init_cmd_brdcast.read()){
+              r_init_cmd_fsm = INIT_CMD_SC_BRDCAST;
+              m_cpt_inval++;
+              m_cpt_inval_brdcast++;
+            } else {
+              r_init_cmd_fsm = INIT_CMD_SC_UPDT_SEL;
+              m_cpt_update++;
+            }
+          } else if ( r_xram_rsp_to_init_cmd_req.read() ) {
+            r_init_cmd_fsm = INIT_CMD_INVAL_SEL;
+            m_cpt_inval++;
+          } else if ( r_write_to_init_cmd_req.read() ) {
+            if(r_write_to_init_cmd_brdcast.read()){
+              r_init_cmd_fsm = INIT_CMD_BRDCAST;
+              m_cpt_inval++;
+              m_cpt_inval_brdcast++;
+            } else {
+              r_init_cmd_fsm = INIT_CMD_UPDT_SEL;
+              m_cpt_update++;
+            }
+          }
+          break;
+        }
+
+        ////////////////////////
+      case INIT_CMD_INVAL_SEL:	// selects L1 caches
+        {
+          if(r_xram_rsp_to_init_cmd_brdcast.read()){
+            m_cpt_inval_brdcast++;
+            r_init_cmd_fsm = INIT_CMD_INVAL_NLINE;
+            break;
+          }
+          if ((r_xram_rsp_to_init_cmd_d_copies.read() == 0) &&
+              (r_xram_rsp_to_init_cmd_i_copies.read() == 0)) {	// no more copies
+            r_xram_rsp_to_init_cmd_req = false;
+            r_init_cmd_fsm = INIT_CMD_INVAL_IDLE;
+            break;
+          }
+          m_cpt_inval_mult++;
+          copy_t copies;
+          bool inst = false;
+          if(r_xram_rsp_to_init_cmd_i_copies.read()){
+            copies = r_xram_rsp_to_init_cmd_i_copies.read();
+            inst = true;
+          } else {
+            copies = r_xram_rsp_to_init_cmd_d_copies.read();
+          }
+          copy_t mask   = 0x1;
+          for ( size_t i=0 ; i<8*sizeof(copy_t) ; i++ ) {
+            if ( copies & mask ) {
+              r_init_cmd_target = i;
+              break;
+            }
+            mask = mask << 1;
+          } // end for 
+          r_init_cmd_fsm = INIT_CMD_INVAL_NLINE;
+          r_init_cmd_inst = inst;
+          if(inst){
+            r_xram_rsp_to_init_cmd_i_copies = copies & ~mask;
+          } else {
+            r_xram_rsp_to_init_cmd_d_copies = copies & ~mask;
+          }
+          break;
+        }
+        ////////////////////////
+      case INIT_CMD_INVAL_NLINE:	// send the cache line index
+        {
+          if ( p_vci_ini.cmdack ) {
+            if ( r_xram_rsp_to_init_cmd_brdcast.read() ) {
+              r_init_cmd_fsm = INIT_CMD_INVAL_IDLE;
+              r_xram_rsp_to_init_cmd_req = false;
+            }
+            else r_init_cmd_fsm = INIT_CMD_INVAL_SEL;
+          }
+          break;
+        }
+        ///////////////////////
+      case INIT_CMD_UPDT_SEL:	// selects the next L1 cache
+        {
+          if (r_write_to_init_cmd_d_copies.read() == 0) {	// no more copies
+            r_write_to_init_cmd_req = false;
+            r_init_cmd_fsm    = INIT_CMD_UPDT_IDLE;
+          } else {						// select the first target
+            copy_t copies;
+            copies = r_write_to_init_cmd_d_copies.read();
+            copy_t mask   = 0x1;
+            for ( size_t i=0 ; i<8*sizeof(copy_t) ; i++ ) {
+              if ( copies & mask ) {
+                r_init_cmd_target = i;
+                break;
+              }
+              mask = mask << 1;
+            } // end for 
+            r_init_cmd_fsm    = INIT_CMD_UPDT_NLINE;
+            r_write_to_init_cmd_d_copies = copies & ~mask;
+            r_init_cmd_cpt    = 0;
+            m_cpt_update_mult++;
+          }
+          break;
+        }
+        /////////////////////////
+      case INIT_CMD_BRDCAST:
+        {
+          if( p_vci_ini.cmdack ) {
+            r_write_to_init_cmd_req = false;
+            r_init_cmd_fsm = INIT_CMD_UPDT_IDLE;
+          }
+          break;
+        }
+        /////////////////////////
+      case INIT_CMD_UPDT_NLINE:	// send the cache line index
+        {
+          if ( p_vci_ini.cmdack ){
+            r_init_cmd_fsm = INIT_CMD_UPDT_INDEX;
+          }
+          break;
+        }
+        /////////////////////////
+      case INIT_CMD_UPDT_INDEX:	// send the first word index
+        {
+
+          if ( p_vci_ini.cmdack )  r_init_cmd_fsm = INIT_CMD_UPDT_DATA;
+          break;
+        }
+        ////////////////////////
+      case INIT_CMD_UPDT_DATA:	// send the data
+        {
+          if ( p_vci_ini.cmdack ) {
+            if ( r_init_cmd_cpt.read() == (r_write_to_init_cmd_count.read()-1) ) {
+              r_init_cmd_fsm = INIT_CMD_UPDT_SEL;
+            } else {
+              r_init_cmd_cpt = r_init_cmd_cpt.read() + 1;
+            }
+          }
+          break;
+        }
+        ///////////////////////
+      case INIT_CMD_SC_UPDT_SEL:	// selects the next L1 cache
+        {
+          if (r_llsc_to_init_cmd_d_copies.read() == 0) {	// no more copies
+            r_llsc_to_init_cmd_req = false;
+            r_init_cmd_fsm    = INIT_CMD_SC_UPDT_IDLE;
+          } else {						// select the first target
+            copy_t copies;
+            copies = r_llsc_to_init_cmd_d_copies.read();
+            copy_t mask   = 0x1;
+            for ( size_t i=0 ; i<8*sizeof(copy_t) ; i++ ) {
+              if ( copies & mask ) {
+                r_init_cmd_target = i;
+                break;
+              }
+              mask = mask << 1;
+            } // end for 
+            r_init_cmd_fsm    = INIT_CMD_SC_UPDT_NLINE;
+            r_llsc_to_init_cmd_d_copies = copies & ~mask;
+            r_init_cmd_cpt    = 0;
+            m_cpt_update_mult++;
+          }
+          break;
+        }
+        /////////////////////////
+      case INIT_CMD_SC_BRDCAST:
+        {
+          if( p_vci_ini.cmdack ) {
+            r_llsc_to_init_cmd_req = false;
+            r_init_cmd_fsm = INIT_CMD_SC_UPDT_IDLE;
+          }
+          break;
+        }
+        /////////////////////////
+      case INIT_CMD_SC_UPDT_NLINE:	// send the cache line index
+        {
+          if ( p_vci_ini.cmdack ){
+            r_init_cmd_fsm = INIT_CMD_SC_UPDT_INDEX;
+          }
+          break;
+        }
+        /////////////////////////
+      case INIT_CMD_SC_UPDT_INDEX:	// send the first word index
+        {
+
+          if ( p_vci_ini.cmdack )  r_init_cmd_fsm = INIT_CMD_SC_UPDT_DATA;
+          break;
+        }
+        ////////////////////////
+      case INIT_CMD_SC_UPDT_DATA:	// send the data
+        {
+          if ( p_vci_ini.cmdack ) {
+            r_init_cmd_fsm = INIT_CMD_SC_UPDT_SEL;
+          }
+          break;
+        }
+
+    } // end switch r_init_cmd_fsm
+
+    /////////////////////////////////////////////////////////////////////
+    //		TGT_RSP FSM
+    /////////////////////////////////////////////////////////////////////
+    // The TGT_RSP fsm sends the responses on the VCI target port
+    // with a round robin priority between six requests :
+    // - r_read_to_tgt_rsp_req
+    // - r_write_to_tgt_rsp_req
+    // - r_llsc_to_tgt_rsp_req
+    // - r_cleanup_to_tgt_rsp_req
+    // - r_init_rsp_to_tgt_rsp_req
+    // - r_xram_rsp_to_tgt_rsp_req
+    // The  ordering is :  read > write > llsc > cleanup > xram > init
+    /////////////////////////////////////////////////////////////////////
+
+    switch ( r_tgt_rsp_fsm.read() ) {
+
+      ///////////////////////
+      case TGT_RSP_READ_IDLE:		// write requests have the highest priority
+        {
+          if      ( r_write_to_tgt_rsp_req    ) r_tgt_rsp_fsm = TGT_RSP_WRITE;
+          else if ( r_llsc_to_tgt_rsp_req     ) r_tgt_rsp_fsm = TGT_RSP_LLSC;
+          else if ( r_xram_rsp_to_tgt_rsp_req ) {
+            r_tgt_rsp_fsm = TGT_RSP_XRAM;
+            r_tgt_rsp_cpt = r_xram_rsp_to_tgt_rsp_word.read();
+          }
+          else if ( r_init_rsp_to_tgt_rsp_req ) r_tgt_rsp_fsm = TGT_RSP_INIT;
+          else if ( r_cleanup_to_tgt_rsp_req  ) r_tgt_rsp_fsm = TGT_RSP_CLEANUP;
+          else if ( r_read_to_tgt_rsp_req     ) {
+            r_tgt_rsp_fsm = TGT_RSP_READ;
+            r_tgt_rsp_cpt = r_read_to_tgt_rsp_word.read();
+          }
+          break;
+        }
+        ////////////////////////
+      case TGT_RSP_WRITE_IDLE:		// llsc requests have the highest priority
+        {
+          if      ( r_llsc_to_tgt_rsp_req     ) r_tgt_rsp_fsm = TGT_RSP_LLSC;
+          else if ( r_xram_rsp_to_tgt_rsp_req ) {
+            r_tgt_rsp_fsm = TGT_RSP_XRAM;
+            r_tgt_rsp_cpt = r_xram_rsp_to_tgt_rsp_word.read();
+          }
+          else if ( r_init_rsp_to_tgt_rsp_req ) r_tgt_rsp_fsm = TGT_RSP_INIT;
+          else if ( r_cleanup_to_tgt_rsp_req  ) r_tgt_rsp_fsm = TGT_RSP_CLEANUP;
+          else if ( r_read_to_tgt_rsp_req     ) {
+            r_tgt_rsp_fsm = TGT_RSP_READ;
+            r_tgt_rsp_cpt = r_read_to_tgt_rsp_word.read();
+          }
+
+          else if ( r_write_to_tgt_rsp_req    ) r_tgt_rsp_fsm = TGT_RSP_WRITE;
+          break;
+        }
+        ///////////////////////
+      case TGT_RSP_LLSC_IDLE:		// cleanup requests have the highest priority
+        {
+          if ( r_xram_rsp_to_tgt_rsp_req )  {
+            r_tgt_rsp_fsm = TGT_RSP_XRAM;
+            r_tgt_rsp_cpt = r_xram_rsp_to_tgt_rsp_word.read();
+          }
+          else if ( r_init_rsp_to_tgt_rsp_req ) r_tgt_rsp_fsm = TGT_RSP_INIT;
+          else if ( r_cleanup_to_tgt_rsp_req  ) r_tgt_rsp_fsm = TGT_RSP_CLEANUP;
+          else if ( r_read_to_tgt_rsp_req     ) {
+            r_tgt_rsp_fsm = TGT_RSP_READ;
+            r_tgt_rsp_cpt = r_read_to_tgt_rsp_word.read();
+          }
+          else if ( r_write_to_tgt_rsp_req    ) r_tgt_rsp_fsm = TGT_RSP_WRITE;
+          else if ( r_llsc_to_tgt_rsp_req     ) r_tgt_rsp_fsm = TGT_RSP_LLSC;
+          break;
+        }
+      case TGT_RSP_XRAM_IDLE:		// init requests have the highest priority
+        {
+
+          if      ( r_init_rsp_to_tgt_rsp_req ) r_tgt_rsp_fsm = TGT_RSP_INIT;
+          else if ( r_cleanup_to_tgt_rsp_req  ) r_tgt_rsp_fsm = TGT_RSP_CLEANUP;
+          else if ( r_read_to_tgt_rsp_req     ) {
+            r_tgt_rsp_fsm = TGT_RSP_READ;
+            r_tgt_rsp_cpt = r_read_to_tgt_rsp_word.read();
+          }
+          else if ( r_write_to_tgt_rsp_req    ) r_tgt_rsp_fsm = TGT_RSP_WRITE;
+          else if ( r_llsc_to_tgt_rsp_req     ) r_tgt_rsp_fsm = TGT_RSP_LLSC;
+          else if ( r_xram_rsp_to_tgt_rsp_req )  {
+            r_tgt_rsp_fsm = TGT_RSP_XRAM;
+            r_tgt_rsp_cpt = r_xram_rsp_to_tgt_rsp_word.read();
+          }
+          break;
+        }
+        ///////////////////////
+      case TGT_RSP_INIT_IDLE:		// cleanup requests have the highest priority
+        {
+          if      ( r_cleanup_to_tgt_rsp_req  ) r_tgt_rsp_fsm = TGT_RSP_CLEANUP;
+          else if ( r_read_to_tgt_rsp_req     ) {
+            r_tgt_rsp_fsm = TGT_RSP_READ;
+            r_tgt_rsp_cpt = r_read_to_tgt_rsp_word.read();
+          }
+          else if ( r_write_to_tgt_rsp_req    ) r_tgt_rsp_fsm = TGT_RSP_WRITE;
+          else if ( r_llsc_to_tgt_rsp_req     ) r_tgt_rsp_fsm = TGT_RSP_LLSC;
+          else if ( r_xram_rsp_to_tgt_rsp_req ) {
+            r_tgt_rsp_fsm = TGT_RSP_XRAM;
+            r_tgt_rsp_cpt = r_xram_rsp_to_tgt_rsp_word.read();
+          }
+          else if ( r_init_rsp_to_tgt_rsp_req ) r_tgt_rsp_fsm = TGT_RSP_INIT;
+          break;
+        }
+        ///////////////////////
+      case TGT_RSP_CLEANUP_IDLE:		// read requests have the highest priority
+        {
+          if      ( r_read_to_tgt_rsp_req     ) {
+            r_tgt_rsp_fsm = TGT_RSP_READ;
+            r_tgt_rsp_cpt = r_read_to_tgt_rsp_word.read();
+          }
+          else if ( r_write_to_tgt_rsp_req    ) r_tgt_rsp_fsm = TGT_RSP_WRITE;
+          else if ( r_llsc_to_tgt_rsp_req     ) r_tgt_rsp_fsm = TGT_RSP_LLSC;
+          else if ( r_xram_rsp_to_tgt_rsp_req ) {
+            r_tgt_rsp_fsm = TGT_RSP_XRAM;
+            r_tgt_rsp_cpt = r_xram_rsp_to_tgt_rsp_word.read();
+          }
+          else if ( r_init_rsp_to_tgt_rsp_req ) r_tgt_rsp_fsm = TGT_RSP_INIT;
+          else if ( r_cleanup_to_tgt_rsp_req  ) r_tgt_rsp_fsm = TGT_RSP_CLEANUP;
+          break;
+        }
+        ///////////////////////
+      case TGT_RSP_READ:		// send the response
+        {
+          if ( p_vci_tgt.rspack ) {
+            if ( r_tgt_rsp_cpt.read() == (r_read_to_tgt_rsp_word.read()+r_read_to_tgt_rsp_length-1) ) {
+              r_tgt_rsp_fsm = TGT_RSP_READ_IDLE;
+              r_read_to_tgt_rsp_req = false;
+            } else {
+              r_tgt_rsp_cpt = r_tgt_rsp_cpt.read() + 1;
+            }
+          }
+          break;
+        }
+        ///////////////////
+      case TGT_RSP_WRITE:		// send the write acknowledge
+        {
+          if ( p_vci_tgt.rspack ) {
+            r_tgt_rsp_fsm = TGT_RSP_WRITE_IDLE;
+            r_write_to_tgt_rsp_req = false;
+          }
+          break;
+        }
+        ///////////////////
+      case TGT_RSP_CLEANUP:		// send the write acknowledge
+        {
+          if ( p_vci_tgt.rspack ) {
+            r_tgt_rsp_fsm = TGT_RSP_CLEANUP_IDLE;
+            r_cleanup_to_tgt_rsp_req = false;
+          }
+          break;
+        }
+        //////////////////
+      case TGT_RSP_LLSC:		// send one atomic word response
+        {
+          if ( p_vci_tgt.rspack ) {
+            r_tgt_rsp_fsm = TGT_RSP_LLSC_IDLE;
+            r_llsc_to_tgt_rsp_req = false;
+          }
+          break;
+        }
+
+        ///////////////////////
+      case TGT_RSP_XRAM:		// send the response
+        {
+          if ( p_vci_tgt.rspack ) {
+            if ( r_tgt_rsp_cpt.read() == (r_xram_rsp_to_tgt_rsp_word.read()+r_xram_rsp_to_tgt_rsp_length.read()-1)) {
+              r_tgt_rsp_fsm = TGT_RSP_XRAM_IDLE;
+              r_xram_rsp_to_tgt_rsp_req = false;
+            } else {
+              r_tgt_rsp_cpt = r_tgt_rsp_cpt.read() + 1;
+            }
+          }
+          break;
+        }
+        ///////////////////
+      case TGT_RSP_INIT:		// send the pending write acknowledge
+        {
+          if ( p_vci_tgt.rspack ) {
+            r_tgt_rsp_fsm = TGT_RSP_INIT_IDLE;
+            r_init_rsp_to_tgt_rsp_req = false;
+          }
+          break;
+        }
+    } // end switch tgt_rsp_fsm
+    ////////////////////////////////////////////////////////////////////////////////////
+    //		NEW ALLOC_UPT FSM
+    ////////////////////////////////////////////////////////////////////////////////////
+    // The ALLOC_UPT FSM allocates the access to the Update/Inval Table (UPT).
+    // with a round robin priority between three FSMs : INIT_RSP > WRITE > XRAM_RSP > CLEANUP 
+    // - The WRITE FSM initiates update transactions and sets  new entry in UPT.
+    // - The XRAM_RSP FSM initiates inval transactions and sets  new entry in UPT.
+    // - The INIT_RSP FSM complete those trasactions and erase the UPT entry.
+    // - The CLEANUP  FSM decrement an entry in UPT.
+    // The resource is always allocated.
+    /////////////////////////////////////////////////////////////////////////////////////
+
+    switch ( r_alloc_upt_fsm.read() ) {
+
+      ////////////////////////
+      case ALLOC_UPT_INIT_RSP:
+        if ( (r_init_rsp_fsm.read() != INIT_RSP_UPT_LOCK) && 
+             (r_init_rsp_fsm.read() != INIT_RSP_UPT_CLEAR) ) 
+        {
+          if      ((r_write_fsm.read() == WRITE_UPT_LOCK) ||
+                   (r_write_fsm.read() == WRITE_INVAL_LOCK))        r_alloc_upt_fsm = ALLOC_UPT_WRITE;
+          else if (r_xram_rsp_fsm.read() == XRAM_RSP_INVAL_LOCK)    r_alloc_upt_fsm = ALLOC_UPT_XRAM_RSP;
+          else if (r_cleanup_fsm.read() == CLEANUP_UPT_LOCK)        r_alloc_upt_fsm = ALLOC_UPT_CLEANUP;
+          else if ((r_llsc_fsm.read() == SC_UPT_LOCK) ||
+                   (r_llsc_fsm.read() == SC_INVAL_LOCK))            r_alloc_upt_fsm = ALLOC_UPT_LLSC;
+        }
+        break;
+
+        /////////////////////
+      case ALLOC_UPT_WRITE:
+        if ( (r_write_fsm.read() != WRITE_UPT_LOCK) &&
+             (r_write_fsm.read() != WRITE_INVAL_LOCK)) 
+        {
+          if      (r_xram_rsp_fsm.read() == XRAM_RSP_INVAL_LOCK)    r_alloc_upt_fsm = ALLOC_UPT_XRAM_RSP;
+          else if (r_cleanup_fsm.read() == CLEANUP_UPT_LOCK)        r_alloc_upt_fsm = ALLOC_UPT_CLEANUP;
+          else if ((r_llsc_fsm.read() == SC_UPT_LOCK) ||
+                   (r_llsc_fsm.read() == SC_INVAL_LOCK))            r_alloc_upt_fsm = ALLOC_UPT_LLSC;
+          else if (r_init_rsp_fsm.read() == INIT_RSP_UPT_LOCK)      r_alloc_upt_fsm = ALLOC_UPT_INIT_RSP;
+        }
+        break;
+
+        ////////////////////////
+      case ALLOC_UPT_XRAM_RSP:
+        if (r_xram_rsp_fsm.read() != XRAM_RSP_INVAL_LOCK) 
+        { 
+          if       (r_cleanup_fsm.read() == CLEANUP_UPT_LOCK)       r_alloc_upt_fsm = ALLOC_UPT_CLEANUP;
+          else if ((r_llsc_fsm.read() == SC_UPT_LOCK) ||
+                   (r_llsc_fsm.read() == SC_INVAL_LOCK))            r_alloc_upt_fsm = ALLOC_UPT_LLSC;
+          else if  (r_init_rsp_fsm.read() == INIT_RSP_UPT_LOCK)     r_alloc_upt_fsm = ALLOC_UPT_INIT_RSP;
+          else if ((r_write_fsm.read() == WRITE_UPT_LOCK)   ||
+                   (r_write_fsm.read() == WRITE_INVAL_LOCK))        r_alloc_upt_fsm = ALLOC_UPT_WRITE;
+        }
+        break;
+
+        //////////////////////////
+      case ALLOC_UPT_CLEANUP:
+        if(r_cleanup_fsm.read() != CLEANUP_UPT_LOCK )
+        {
+          if      ((r_llsc_fsm.read() == SC_UPT_LOCK) ||
+                   (r_llsc_fsm.read() == SC_INVAL_LOCK))            r_alloc_upt_fsm = ALLOC_UPT_LLSC;
+          else if  (r_init_rsp_fsm.read() == INIT_RSP_UPT_LOCK)     r_alloc_upt_fsm = ALLOC_UPT_INIT_RSP;
+          else if ((r_write_fsm.read() == WRITE_UPT_LOCK) ||
+                   (r_write_fsm.read() == WRITE_INVAL_LOCK))        r_alloc_upt_fsm = ALLOC_UPT_WRITE;
+          else if (r_xram_rsp_fsm.read() == XRAM_RSP_INVAL_LOCK)    r_alloc_upt_fsm = ALLOC_UPT_XRAM_RSP;
+        }
+        break;
+        
+        //////////////////////////
+      case ALLOC_UPT_LLSC:
+        if( (r_llsc_fsm.read() != SC_UPT_LOCK) && 
+            (r_llsc_fsm.read() != SC_INVAL_LOCK))
+        {
+          if      (r_init_rsp_fsm.read() == INIT_RSP_UPT_LOCK)      r_alloc_upt_fsm = ALLOC_UPT_INIT_RSP;
+          else if ((r_write_fsm.read() == WRITE_UPT_LOCK) ||
+                   (r_write_fsm.read() == WRITE_INVAL_LOCK))        r_alloc_upt_fsm = ALLOC_UPT_WRITE;
+          else if (r_xram_rsp_fsm.read() == XRAM_RSP_INVAL_LOCK)    r_alloc_upt_fsm = ALLOC_UPT_XRAM_RSP;
+          else if (r_cleanup_fsm.read() == CLEANUP_UPT_LOCK)        r_alloc_upt_fsm = ALLOC_UPT_CLEANUP;
+        }
+        break;
+
+    } // end switch r_alloc_upt_fsm
+
+    ////////////////////////////////////////////////////////////////////////////////////
+    //		ALLOC_DIR FSM
+    ////////////////////////////////////////////////////////////////////////////////////
+    // The ALLOC_DIR FSM allocates the access to the directory and
+    // the data cache with a round robin priority between 5 user FSMs :
+    // The cyclic ordering is READ > WRITE > LLSC > CLEANUP > XRAM_RSP
+    // The ressource is always allocated.
+    /////////////////////////////////////////////////////////////////////////////////////
+
+    switch ( r_alloc_dir_fsm.read() ) {
+
+      ////////////////////
+      case ALLOC_DIR_READ:
+        if ( ( (r_read_fsm.read() != READ_DIR_LOCK) &&
+              (r_read_fsm.read() != READ_TRT_LOCK)     )
+            ||
+            ( (r_read_fsm.read()      == READ_TRT_LOCK)  &&
+              (r_alloc_trt_fsm.read() == ALLOC_TRT_READ)    )  ) 
+        {
+          if        (r_write_fsm.read() == WRITE_DIR_LOCK)          r_alloc_dir_fsm = ALLOC_DIR_WRITE;
+          else if   ((r_llsc_fsm.read() == LL_DIR_LOCK) || 
+                    (r_llsc_fsm.read() == SC_DIR_LOCK))             r_alloc_dir_fsm = ALLOC_DIR_LLSC;
+          else if   (r_cleanup_fsm.read() == CLEANUP_DIR_LOCK)      r_alloc_dir_fsm = ALLOC_DIR_CLEANUP;
+          else if   (r_xram_rsp_fsm.read() == XRAM_RSP_DIR_LOCK)    r_alloc_dir_fsm = ALLOC_DIR_XRAM_RSP;
+        }
+        break;
+
+        /////////////////////
+      case ALLOC_DIR_WRITE:
+        if ( ( (r_write_fsm.read() != WRITE_DIR_LOCK)     &&
+              (r_write_fsm.read() != WRITE_TRT_LOCK)     &&
+              (r_write_fsm.read() != WRITE_DIR_HIT_READ) &&
+              (r_write_fsm.read() != WRITE_TRT_WRITE_LOCK) &&
+              (r_write_fsm.read() != WRITE_INVAL_LOCK) )
+            ||
+            ( (r_write_fsm.read()     == WRITE_TRT_LOCK) &&
+              (r_alloc_trt_fsm.read() == ALLOC_TRT_WRITE)   )   )
+        {
+          if        ((r_llsc_fsm.read() == LL_DIR_LOCK) || 
+                    (r_llsc_fsm.read() == SC_DIR_LOCK))             r_alloc_dir_fsm = ALLOC_DIR_LLSC;
+          else if   (r_cleanup_fsm.read() == CLEANUP_DIR_LOCK)      r_alloc_dir_fsm = ALLOC_DIR_CLEANUP;
+          else if   (r_xram_rsp_fsm.read() == XRAM_RSP_DIR_LOCK)    r_alloc_dir_fsm = ALLOC_DIR_XRAM_RSP;
+          else if   (r_read_fsm.read() == READ_DIR_LOCK) 	        r_alloc_dir_fsm = ALLOC_DIR_READ;
+        }
+        break;
+
+        ////////////////////
+      case ALLOC_DIR_LLSC:
+        if ( ( (r_llsc_fsm.read() != LL_DIR_LOCK)    &&
+              (r_llsc_fsm.read() != LL_DIR_HIT )    &&
+              (r_llsc_fsm.read() != SC_DIR_LOCK)    &&
+              (r_llsc_fsm.read() != SC_DIR_HIT )    &&
+              (r_llsc_fsm.read() != LLSC_TRT_LOCK ) &&
+              (r_llsc_fsm.read() != SC_TRT_LOCK)    &&
+              (r_llsc_fsm.read() != SC_INVAL_LOCK))
+            || 
+            ( (r_llsc_fsm.read()      == LLSC_TRT_LOCK ) &&
+              (r_alloc_trt_fsm.read() == ALLOC_TRT_LLSC)    ) )
+        {
+          if      (r_cleanup_fsm.read() == CLEANUP_DIR_LOCK)    r_alloc_dir_fsm = ALLOC_DIR_CLEANUP;
+          else if (r_xram_rsp_fsm.read() == XRAM_RSP_DIR_LOCK)  r_alloc_dir_fsm = ALLOC_DIR_XRAM_RSP;
+          else if (r_read_fsm.read() == READ_DIR_LOCK) 	        r_alloc_dir_fsm = ALLOC_DIR_READ;
+          else if (r_write_fsm.read() == WRITE_DIR_LOCK)        r_alloc_dir_fsm = ALLOC_DIR_WRITE;
+        }
+        break;
+
+        ///////////////////////
+      case ALLOC_DIR_CLEANUP:
+        if ( (r_cleanup_fsm.read() != CLEANUP_DIR_LOCK) &&
+            (r_cleanup_fsm.read() != CLEANUP_DIR_WRITE) )
+        {
+          if        (r_xram_rsp_fsm.read() == XRAM_RSP_DIR_LOCK)    r_alloc_dir_fsm = ALLOC_DIR_XRAM_RSP;
+          else if   (r_read_fsm.read() == READ_DIR_LOCK)            r_alloc_dir_fsm = ALLOC_DIR_READ;
+          else if   (r_write_fsm.read() == WRITE_DIR_LOCK)          r_alloc_dir_fsm = ALLOC_DIR_WRITE;
+          else if   ((r_llsc_fsm.read() == LL_DIR_LOCK) || 
+                    (r_llsc_fsm.read() == SC_DIR_LOCK))             r_alloc_dir_fsm = ALLOC_DIR_LLSC;
+        }
+        break;
+        ////////////////////////
+      case ALLOC_DIR_XRAM_RSP:
+        if ( (r_xram_rsp_fsm.read() != XRAM_RSP_DIR_LOCK)  &&
+            (r_xram_rsp_fsm.read() != XRAM_RSP_TRT_COPY)   && 
+            (r_xram_rsp_fsm.read() != XRAM_RSP_INVAL_LOCK))
+        {
+          if      (r_read_fsm.read() == READ_DIR_LOCK) 	        r_alloc_dir_fsm = ALLOC_DIR_READ;
+          else if (r_write_fsm.read() == WRITE_DIR_LOCK)        r_alloc_dir_fsm = ALLOC_DIR_WRITE;
+          else if ( (r_llsc_fsm.read() == LL_DIR_LOCK) || 
+                    (r_llsc_fsm.read() == SC_DIR_LOCK))         r_alloc_dir_fsm = ALLOC_DIR_LLSC;
+          else if (r_cleanup_fsm.read() == CLEANUP_DIR_LOCK)    r_alloc_dir_fsm = ALLOC_DIR_CLEANUP;
+        }
+        break;
+
+    } // end switch alloc_dir_fsm
+
+    ////////////////////////////////////////////////////////////////////////////////////
+    //		ALLOC_TRT FSM
+    ////////////////////////////////////////////////////////////////////////////////////
+    // The ALLOC_TRT fsm allocates the access to the Transaction Table (write buffer)
+    // with a round robin priority between 4 user FSMs :
+    // The cyclic priority is READ > WRITE > LLSC > XRAM_RSP
+    // The ressource is always allocated.
+    ///////////////////////////////////////////////////////////////////////////////////
+
+    switch (r_alloc_trt_fsm) {
+
+      ////////////////////
+      case ALLOC_TRT_READ:
+        if ( r_read_fsm.read() != READ_TRT_LOCK ) 
+        {
+          if      ((r_write_fsm.read() == WRITE_TRT_LOCK)   ||
+                   (r_write_fsm.read() == WRITE_TRT_WRITE_LOCK))    r_alloc_trt_fsm = ALLOC_TRT_WRITE;
+          else if ((r_llsc_fsm.read() == LLSC_TRT_LOCK) ||
+                   (r_llsc_fsm.read() == SC_TRT_LOCK))              r_alloc_trt_fsm = ALLOC_TRT_LLSC;
+          else if (r_xram_rsp_fsm.read() == XRAM_RSP_TRT_COPY)      r_alloc_trt_fsm = ALLOC_TRT_XRAM_RSP;
+          else if ( (r_ixr_rsp_fsm.read() == IXR_RSP_TRT_ERASE) ||
+                    (r_ixr_rsp_fsm.read() == IXR_RSP_TRT_READ) )    r_alloc_trt_fsm = ALLOC_TRT_IXR_RSP;
+        }
+        break;
+        /////////////////////
+      case ALLOC_TRT_WRITE:
+        if ( (r_write_fsm.read() != WRITE_TRT_LOCK) &&
+             (r_write_fsm.read() != WRITE_TRT_WRITE_LOCK) &&
+             (r_write_fsm.read() != WRITE_INVAL_LOCK)) 
+        {
+          if      ((r_llsc_fsm.read() == LLSC_TRT_LOCK) ||
+                   (r_llsc_fsm.read() == SC_TRT_LOCK))              r_alloc_trt_fsm = ALLOC_TRT_LLSC;
+          else if (r_xram_rsp_fsm.read() == XRAM_RSP_TRT_COPY)      r_alloc_trt_fsm = ALLOC_TRT_XRAM_RSP;
+          else if ( (r_ixr_rsp_fsm.read() == IXR_RSP_TRT_ERASE) ||
+                    (r_ixr_rsp_fsm.read() == IXR_RSP_TRT_READ))     r_alloc_trt_fsm = ALLOC_TRT_IXR_RSP;
+          else if (r_read_fsm.read() == READ_TRT_LOCK) 	            r_alloc_trt_fsm = ALLOC_TRT_READ;
+        }
+        break;
+        ////////////////////
+      case ALLOC_TRT_LLSC:
+        if ( (r_llsc_fsm.read() != LLSC_TRT_LOCK) &&
+             (r_llsc_fsm.read() != SC_TRT_LOCK) &&
+             (r_llsc_fsm.read() != SC_INVAL_LOCK))
+        { 
+          if      (r_xram_rsp_fsm.read() == XRAM_RSP_TRT_COPY)      r_alloc_trt_fsm = ALLOC_TRT_XRAM_RSP;
+          else if ( (r_ixr_rsp_fsm.read() == IXR_RSP_TRT_ERASE) ||
+                    (r_ixr_rsp_fsm.read() == IXR_RSP_TRT_READ))     r_alloc_trt_fsm = ALLOC_TRT_IXR_RSP;
+          else if (r_read_fsm.read() == READ_TRT_LOCK) 	            r_alloc_trt_fsm = ALLOC_TRT_READ;
+          else if ((r_write_fsm.read() == WRITE_TRT_LOCK)     ||
+                   (r_write_fsm.read() == WRITE_TRT_WRITE_LOCK))    r_alloc_trt_fsm = ALLOC_TRT_WRITE;
+        }
+        break;
+        ////////////////////////
+      case ALLOC_TRT_XRAM_RSP:
+        if ( (r_xram_rsp_fsm.read() != XRAM_RSP_TRT_COPY)  &&
+            (r_xram_rsp_fsm.read() != XRAM_RSP_DIR_UPDT)   &&
+            (r_xram_rsp_fsm.read() != XRAM_RSP_INVAL_LOCK)) {
+          if      ( (r_ixr_rsp_fsm.read() == IXR_RSP_TRT_ERASE) ||
+                    (r_ixr_rsp_fsm.read() == IXR_RSP_TRT_READ))     r_alloc_trt_fsm = ALLOC_TRT_IXR_RSP;
+          else if (r_read_fsm.read() == READ_TRT_LOCK) 	            r_alloc_trt_fsm = ALLOC_TRT_READ;
+          else if ((r_write_fsm.read() == WRITE_TRT_LOCK)    ||
+                   (r_write_fsm.read() == WRITE_TRT_WRITE_LOCK))    r_alloc_trt_fsm = ALLOC_TRT_WRITE;
+          else if ((r_llsc_fsm.read() == LLSC_TRT_LOCK) ||
+                   (r_llsc_fsm.read() == SC_TRT_LOCK))              r_alloc_trt_fsm = ALLOC_TRT_LLSC;
+        }
+        break;
+        ////////////////////////
+      case ALLOC_TRT_IXR_RSP:
+        if ( (r_ixr_rsp_fsm.read() != IXR_RSP_TRT_ERASE) &&
+            (r_ixr_rsp_fsm.read() != IXR_RSP_TRT_READ) ) {
+          if      (r_read_fsm.read() == READ_TRT_LOCK) 	            r_alloc_trt_fsm = ALLOC_TRT_READ;
+          else if ((r_write_fsm.read() == WRITE_TRT_LOCK)   ||
+                   (r_write_fsm.read() == WRITE_TRT_WRITE_LOCK))    r_alloc_trt_fsm = ALLOC_TRT_WRITE;
+          else if ((r_llsc_fsm.read() == LLSC_TRT_LOCK) ||
+                   (r_llsc_fsm.read() == SC_TRT_LOCK))              r_alloc_trt_fsm = ALLOC_TRT_LLSC;
+          else if (r_xram_rsp_fsm.read() == XRAM_RSP_TRT_COPY)      r_alloc_trt_fsm = ALLOC_TRT_XRAM_RSP;
+        }
+        break;
+
+    } // end switch alloc_trt_fsm
+
+    ////////////////////////////////////////////////////////////////////////////////////
+    //		TGT_CMD to READ FIFO
+    ////////////////////////////////////////////////////////////////////////////////////
+
+    if ( cmd_read_fifo_put ) {
+      if ( cmd_read_fifo_get ) {
+        m_cmd_read_addr_fifo.put_and_get((addr_t)(p_vci_tgt.address.read()));
+        m_cmd_read_length_fifo.put_and_get(p_vci_tgt.plen.read()>>2);
+        m_cmd_read_srcid_fifo.put_and_get(p_vci_tgt.srcid.read());
+        m_cmd_read_trdid_fifo.put_and_get(p_vci_tgt.trdid.read());
+        m_cmd_read_pktid_fifo.put_and_get(p_vci_tgt.pktid.read());
+      } else {
+        m_cmd_read_addr_fifo.simple_put((addr_t)(p_vci_tgt.address.read()));
+        m_cmd_read_length_fifo.simple_put(p_vci_tgt.plen.read()>>2);
+        m_cmd_read_srcid_fifo.simple_put(p_vci_tgt.srcid.read());
+        m_cmd_read_trdid_fifo.simple_put(p_vci_tgt.trdid.read());
+        m_cmd_read_pktid_fifo.simple_put(p_vci_tgt.pktid.read());
+      }
+    } else {
+      if ( cmd_read_fifo_get ) {
+        m_cmd_read_addr_fifo.simple_get();
+        m_cmd_read_length_fifo.simple_get();
+        m_cmd_read_srcid_fifo.simple_get();
+        m_cmd_read_trdid_fifo.simple_get();
+        m_cmd_read_pktid_fifo.simple_get();
+      }
+    }
+    /////////////////////////////////////////////////////////////////////
+    //		TGT_CMD to WRITE FIFO
+    /////////////////////////////////////////////////////////////////////
+
+    if ( cmd_write_fifo_put ) {
+      if ( cmd_write_fifo_get ) {
+        m_cmd_write_addr_fifo.put_and_get((addr_t)(p_vci_tgt.address.read()));
+        m_cmd_write_eop_fifo.put_and_get(p_vci_tgt.eop.read());
+        m_cmd_write_srcid_fifo.put_and_get(p_vci_tgt.srcid.read());
+        m_cmd_write_trdid_fifo.put_and_get(p_vci_tgt.trdid.read());
+        m_cmd_write_pktid_fifo.put_and_get(p_vci_tgt.pktid.read());
+        m_cmd_write_data_fifo.put_and_get(p_vci_tgt.wdata.read());
+        m_cmd_write_be_fifo.put_and_get(p_vci_tgt.be.read());
+      } else {
+        m_cmd_write_addr_fifo.simple_put((addr_t)(p_vci_tgt.address.read()));
+        m_cmd_write_eop_fifo.simple_put(p_vci_tgt.eop.read());
+        m_cmd_write_srcid_fifo.simple_put(p_vci_tgt.srcid.read());
+        m_cmd_write_trdid_fifo.simple_put(p_vci_tgt.trdid.read());
+        m_cmd_write_pktid_fifo.simple_put(p_vci_tgt.pktid.read());
+        m_cmd_write_data_fifo.simple_put(p_vci_tgt.wdata.read());
+        m_cmd_write_be_fifo.simple_put(p_vci_tgt.be.read());
+      }
+    } else {
+      if ( cmd_write_fifo_get ) {
+        m_cmd_write_addr_fifo.simple_get();
+        m_cmd_write_eop_fifo.simple_get();
+        m_cmd_write_srcid_fifo.simple_get();
+        m_cmd_write_trdid_fifo.simple_get();
+        m_cmd_write_pktid_fifo.simple_get();
+        m_cmd_write_data_fifo.simple_get();
+        m_cmd_write_be_fifo.simple_get();
+      }
+    }
+    ////////////////////////////////////////////////////////////////////////////////////
+    //		TGT_CMD to LLSC FIFO
+    ////////////////////////////////////////////////////////////////////////////////////
+
+    if ( cmd_llsc_fifo_put ) {
+      if ( cmd_llsc_fifo_get ) {
+        m_cmd_llsc_addr_fifo.put_and_get((addr_t)(p_vci_tgt.address.read()));
+        m_cmd_llsc_sc_fifo.put_and_get(p_vci_tgt.cmd.read() == vci_param::CMD_STORE_COND); 
+        m_cmd_llsc_srcid_fifo.put_and_get(p_vci_tgt.srcid.read());
+        m_cmd_llsc_trdid_fifo.put_and_get(p_vci_tgt.trdid.read());
+        m_cmd_llsc_pktid_fifo.put_and_get(p_vci_tgt.pktid.read());
+        m_cmd_llsc_wdata_fifo.put_and_get(p_vci_tgt.wdata.read());
+      } else {
+        m_cmd_llsc_addr_fifo.simple_put((addr_t)(p_vci_tgt.address.read()));
+        m_cmd_llsc_sc_fifo.simple_put(p_vci_tgt.cmd.read() == vci_param::CMD_STORE_COND); 
+        m_cmd_llsc_srcid_fifo.simple_put(p_vci_tgt.srcid.read());
+        m_cmd_llsc_trdid_fifo.simple_put(p_vci_tgt.trdid.read());
+        m_cmd_llsc_pktid_fifo.simple_put(p_vci_tgt.pktid.read());
+        m_cmd_llsc_wdata_fifo.simple_put(p_vci_tgt.wdata.read());
+      }
+    } else {
+      if ( cmd_llsc_fifo_get ) {
+        m_cmd_llsc_addr_fifo.simple_get();
+        m_cmd_llsc_sc_fifo.simple_get();
+        m_cmd_llsc_srcid_fifo.simple_get();
+        m_cmd_llsc_trdid_fifo.simple_get();
+        m_cmd_llsc_pktid_fifo.simple_get();
+        m_cmd_llsc_wdata_fifo.simple_get();
+      }
+    }
+
+  //////////////////////////////////////////////////////////////
+    m_cpt_cycles++;
+
+  } // end transition()
+
+  /////////////////////////////
+  tmpl(void)::genMoore()
+    /////////////////////////////
+  {
+    ////////////////////////////////////////////////////////////
+    // Command signals on the p_vci_ixr port
+    ////////////////////////////////////////////////////////////
+
+
+    p_vci_ixr.be      = 0xF;
+    p_vci_ixr.pktid   = 0;
+    p_vci_ixr.srcid   = m_srcid_ixr;
+    p_vci_ixr.cons    = false;
+    p_vci_ixr.wrap    = false;
+    p_vci_ixr.contig  = true;
+    p_vci_ixr.clen    = 0;
+    p_vci_ixr.cfixed  = false;
+
+    if ( r_ixr_cmd_fsm.read() == IXR_CMD_READ_NLINE ) {
+      p_vci_ixr.cmd     = vci_param::CMD_READ;
+      p_vci_ixr.cmdval  = true;
+      p_vci_ixr.address = (addr_t)(r_read_to_ixr_cmd_nline.read()*m_words*4);
+      p_vci_ixr.plen    = m_words*4;
+      p_vci_ixr.wdata   = 0x00000000;
+      p_vci_ixr.trdid   = r_read_to_ixr_cmd_trdid.read();
+      p_vci_ixr.eop     = true;
+    } 
+    else if ( r_ixr_cmd_fsm.read() == IXR_CMD_LLSC_NLINE ) {
+      if(r_llsc_to_ixr_cmd_write.read()){
+        p_vci_ixr.cmd     = vci_param::CMD_WRITE;
+        p_vci_ixr.cmdval  = true;
+        p_vci_ixr.address = (addr_t)((r_llsc_to_ixr_cmd_nline.read()*m_words+r_ixr_cmd_cpt.read())*4);
+        p_vci_ixr.plen    = m_words*4;
+        p_vci_ixr.wdata   = r_llsc_to_ixr_cmd_data[r_ixr_cmd_cpt.read()].read();
+        p_vci_ixr.trdid   = r_llsc_to_ixr_cmd_trdid.read();
+        p_vci_ixr.eop     = (r_ixr_cmd_cpt == (m_words-1));
+      } else {
+        p_vci_ixr.cmd     = vci_param::CMD_READ;
+        p_vci_ixr.cmdval  = true;
+        p_vci_ixr.address = (addr_t)(r_llsc_to_ixr_cmd_nline.read()*m_words*4);
+        p_vci_ixr.plen    = m_words*4;
+        p_vci_ixr.wdata   = 0x00000000;
+        p_vci_ixr.trdid   = r_llsc_to_ixr_cmd_trdid.read();
+        p_vci_ixr.eop     = true;
+      }
+    } 
+    else if ( r_ixr_cmd_fsm.read() == IXR_CMD_WRITE_NLINE ) {
+      if(r_write_to_ixr_cmd_write.read()){
+        p_vci_ixr.cmd     = vci_param::CMD_WRITE;
+        p_vci_ixr.cmdval  = true;
+        p_vci_ixr.address = (addr_t)((r_write_to_ixr_cmd_nline.read()*m_words+r_ixr_cmd_cpt.read())*4);
+        p_vci_ixr.plen    = m_words*4;
+        p_vci_ixr.wdata   = r_write_to_ixr_cmd_data[r_ixr_cmd_cpt.read()].read();
+        p_vci_ixr.trdid   = r_write_to_ixr_cmd_trdid.read();
+        p_vci_ixr.eop     = (r_ixr_cmd_cpt == (m_words-1));
+      } else {
+        p_vci_ixr.cmd     = vci_param::CMD_READ;
+        p_vci_ixr.cmdval  = true;
+        p_vci_ixr.address = (addr_t)(r_write_to_ixr_cmd_nline.read()*m_words*4);
+        p_vci_ixr.plen    = m_words*4;
+        p_vci_ixr.wdata   = 0x00000000;
+        p_vci_ixr.trdid   = r_write_to_ixr_cmd_trdid.read();
+        p_vci_ixr.eop     = true;
+      }
+    } 
+    else if ( r_ixr_cmd_fsm.read() == IXR_CMD_XRAM_DATA ) {
+      p_vci_ixr.cmd     = vci_param::CMD_WRITE;
+      p_vci_ixr.cmdval  = true;
+      p_vci_ixr.address = (addr_t)((r_xram_rsp_to_ixr_cmd_nline.read()*m_words+r_ixr_cmd_cpt.read())*4);
+      p_vci_ixr.plen    = m_words*4;
+      p_vci_ixr.wdata   = r_xram_rsp_to_ixr_cmd_data[r_ixr_cmd_cpt.read()].read();
+      p_vci_ixr.trdid   = r_xram_rsp_to_ixr_cmd_trdid.read();
+      p_vci_ixr.eop     = (r_ixr_cmd_cpt == (m_words-1));
+    } else {
+      p_vci_ixr.cmdval  = false;
+      p_vci_ixr.address = 0;
+      p_vci_ixr.plen    = 0;
+      p_vci_ixr.wdata   = 0;
+      p_vci_ixr.trdid   = 0;
+      p_vci_ixr.eop	= false;
+    }
+
+    ////////////////////////////////////////////////////
+    // Response signals on the p_vci_ixr port
+    ////////////////////////////////////////////////////
+
+    if ( ((r_alloc_trt_fsm.read() == ALLOC_TRT_IXR_RSP) &&
+          (r_ixr_rsp_fsm.read() == IXR_RSP_TRT_READ)) || 
+        (r_ixr_rsp_fsm.read() == IXR_RSP_ACK) ) p_vci_ixr.rspack = true;
+    else                                        p_vci_ixr.rspack = false;
+
+    ////////////////////////////////////////////////////
+    // Command signals on the p_vci_tgt port
+    ////////////////////////////////////////////////////
+
+    switch ((tgt_cmd_fsm_state_e)r_tgt_cmd_fsm.read()) {
+      case TGT_CMD_IDLE:
+        p_vci_tgt.cmdack  = false;
+        break;
+      case TGT_CMD_READ:
+        p_vci_tgt.cmdack  = m_cmd_read_addr_fifo.wok();
+        break;
+      case TGT_CMD_READ_EOP:
+        p_vci_tgt.cmdack  = true;
+        break;
+      case TGT_CMD_WRITE:
+        p_vci_tgt.cmdack  = m_cmd_write_addr_fifo.wok();
+        break;
+      case TGT_CMD_ATOMIC:
+        p_vci_tgt.cmdack  = m_cmd_llsc_addr_fifo.wok();
+        break;
+      default:
+        p_vci_tgt.cmdack = false;
+        break;
+    }
+
+    ////////////////////////////////////////////////////
+    // Response signals on the p_vci_tgt port
+    ////////////////////////////////////////////////////
+    switch ( r_tgt_rsp_fsm.read() ) {
+
+      case TGT_RSP_READ_IDLE:
+      case TGT_RSP_WRITE_IDLE:
+      case TGT_RSP_LLSC_IDLE:
+      case TGT_RSP_XRAM_IDLE:
+      case TGT_RSP_INIT_IDLE:
+      case TGT_RSP_CLEANUP_IDLE:
+        p_vci_tgt.rspval  = false;
+        p_vci_tgt.rsrcid  = 0;
+        p_vci_tgt.rdata   = 0;
+        p_vci_tgt.rpktid  = 0;
+        p_vci_tgt.rtrdid  = 0;
+        p_vci_tgt.rerror  = 0;
+        p_vci_tgt.reop    = false;	
+        break;
+      case TGT_RSP_READ:
+        p_vci_tgt.rspval   = true;
+        p_vci_tgt.rdata    = r_read_to_tgt_rsp_data[r_tgt_rsp_cpt.read()].read();
+        p_vci_tgt.rsrcid   = r_read_to_tgt_rsp_srcid.read();
+        p_vci_tgt.rtrdid   = r_read_to_tgt_rsp_trdid.read();
+        p_vci_tgt.rpktid   = r_read_to_tgt_rsp_pktid.read();
+        p_vci_tgt.rerror   = 0;
+        p_vci_tgt.reop     = ( r_tgt_rsp_cpt.read() == (r_read_to_tgt_rsp_word.read()+r_read_to_tgt_rsp_length-1) );
+        break;
+      case TGT_RSP_WRITE:
+        p_vci_tgt.rspval   = true;
+        p_vci_tgt.rdata    = 0;
+        p_vci_tgt.rsrcid   = r_write_to_tgt_rsp_srcid.read();
+        p_vci_tgt.rtrdid   = r_write_to_tgt_rsp_trdid.read();
+        p_vci_tgt.rpktid   = r_write_to_tgt_rsp_pktid.read();
+        p_vci_tgt.rerror   = 0;
+        p_vci_tgt.reop     = true;
+        break;
+      case TGT_RSP_CLEANUP:
+        p_vci_tgt.rspval   = true;
+        p_vci_tgt.rdata    = 0;
+        p_vci_tgt.rsrcid   = r_cleanup_to_tgt_rsp_srcid.read();
+        p_vci_tgt.rtrdid   = r_cleanup_to_tgt_rsp_trdid.read();
+        p_vci_tgt.rpktid   = r_cleanup_to_tgt_rsp_pktid.read();
+        p_vci_tgt.rerror   = 0;
+        p_vci_tgt.reop     = true;
+        break;
+      case TGT_RSP_LLSC:
+        p_vci_tgt.rspval   = true;
+        p_vci_tgt.rdata    = r_llsc_to_tgt_rsp_data.read();
+        p_vci_tgt.rsrcid   = r_llsc_to_tgt_rsp_srcid.read();
+        p_vci_tgt.rtrdid   = r_llsc_to_tgt_rsp_trdid.read();
+        p_vci_tgt.rpktid   = r_llsc_to_tgt_rsp_pktid.read();
+        p_vci_tgt.rerror   = 0;
+        p_vci_tgt.reop     = true;
+        break;
+      case TGT_RSP_XRAM:
+        p_vci_tgt.rspval   = true;
+        p_vci_tgt.rdata    = r_xram_rsp_to_tgt_rsp_data[r_tgt_rsp_cpt.read()].read();
+        p_vci_tgt.rsrcid   = r_xram_rsp_to_tgt_rsp_srcid.read();
+        p_vci_tgt.rtrdid   = r_xram_rsp_to_tgt_rsp_trdid.read();
+        p_vci_tgt.rpktid   = r_xram_rsp_to_tgt_rsp_pktid.read();
+        p_vci_tgt.rerror   = 0;
+        p_vci_tgt.reop     = ( r_tgt_rsp_cpt.read() == (r_xram_rsp_to_tgt_rsp_word.read()+r_xram_rsp_to_tgt_rsp_length.read()-1));
+        break;
+      case TGT_RSP_INIT:
+        p_vci_tgt.rspval   = true;
+        p_vci_tgt.rdata    = 0;
+        p_vci_tgt.rsrcid   = r_init_rsp_to_tgt_rsp_srcid.read();
+        p_vci_tgt.rtrdid   = r_init_rsp_to_tgt_rsp_trdid.read();
+        p_vci_tgt.rpktid   = r_init_rsp_to_tgt_rsp_pktid.read();
+        p_vci_tgt.rerror   = 0;
+        p_vci_tgt.reop     = true;	
+        break;
+    } // end switch r_tgt_rsp_fsm
+
+    ///////////////////////////////////////////////////
+    // Command signals on the p_vci_ini port
+    ///////////////////////////////////////////////////
+
+    p_vci_ini.cmd     = vci_param::CMD_WRITE;
+    p_vci_ini.srcid   = m_srcid_ini;
+    p_vci_ini.pktid   = 0;
+    p_vci_ini.cons    = true;
+    p_vci_ini.wrap    = false;
+    p_vci_ini.contig  = false;
+    p_vci_ini.clen    = 0;
+    p_vci_ini.cfixed  = false;
+
+    switch ( r_init_cmd_fsm.read() ) {
+
+      case INIT_CMD_UPDT_IDLE:
+      case INIT_CMD_INVAL_IDLE:
+      case INIT_CMD_SC_UPDT_IDLE:
+      case INIT_CMD_UPDT_SEL:
+      case INIT_CMD_INVAL_SEL:
+      case INIT_CMD_SC_UPDT_SEL:
+        p_vci_ini.cmdval  = false;
+        p_vci_ini.address = 0;
+        p_vci_ini.wdata   = 0;
+        p_vci_ini.be      = 0;
+        p_vci_ini.plen    = 0;
+        p_vci_ini.trdid   = 0;
+        p_vci_ini.eop     = false;
+        break;
+      case INIT_CMD_INVAL_NLINE:
+        p_vci_ini.cmdval  = true;
+        if(r_xram_rsp_to_init_cmd_brdcast.read())
+          p_vci_ini.address = BROADCAST_ADDR;
+        else {
+          if(r_init_cmd_inst.read()) {
+            p_vci_ini.address = (addr_t)(m_coherence_table[r_init_cmd_target.read()]+8);
+          } else {
+            p_vci_ini.address = (addr_t)(m_coherence_table[r_init_cmd_target.read()]);
+          }
+        }
+        p_vci_ini.wdata   = (uint32_t)r_xram_rsp_to_init_cmd_nline.read();
+        p_vci_ini.be      = ((r_xram_rsp_to_init_cmd_nline.read() >> 32) & 0x3);
+        p_vci_ini.plen    = 4;
+        p_vci_ini.trdid   = r_xram_rsp_to_init_cmd_trdid.read();
+        p_vci_ini.eop     = true;
+        break;
+      case INIT_CMD_BRDCAST:
+        p_vci_ini.cmdval  = true;
+        p_vci_ini.address = BROADCAST_ADDR;
+        p_vci_ini.wdata   = (addr_t)r_write_to_init_cmd_nline.read();
+        p_vci_ini.be      = ((r_write_to_init_cmd_nline.read() >> 32) & 0x3);
+        p_vci_ini.plen    = 4 ;
+        p_vci_ini.eop     = true;
+        p_vci_ini.trdid   = r_write_to_init_cmd_trdid.read();
+        break;
+      case INIT_CMD_UPDT_NLINE:
+        p_vci_ini.cmdval  = true;
+        p_vci_ini.address = (addr_t)(m_coherence_table[r_init_cmd_target.read()] + 4);
+        p_vci_ini.wdata   = (uint32_t)r_write_to_init_cmd_nline.read();
+        p_vci_ini.be      = ((r_write_to_init_cmd_nline.read() >> 32 ) & 0x3);
+        p_vci_ini.plen    = 4 * (r_write_to_init_cmd_count.read() + 2);
+        p_vci_ini.eop     = false;
+        p_vci_ini.trdid   = r_write_to_init_cmd_trdid.read();
+        break;
+      case INIT_CMD_UPDT_INDEX:
+        p_vci_ini.cmdval  = true;
+        p_vci_ini.address = (addr_t)(m_coherence_table[r_init_cmd_target.read()] + 4);
+        p_vci_ini.wdata   = r_write_to_init_cmd_index.read();
+        p_vci_ini.be      = 0xF;
+        p_vci_ini.plen    = 4 * (r_write_to_init_cmd_count.read() + 2);
+        p_vci_ini.trdid   = r_write_to_init_cmd_trdid.read();
+        p_vci_ini.eop     = false;
+        break;
+      case INIT_CMD_UPDT_DATA:
+        p_vci_ini.cmdval  = true;
+        p_vci_ini.address = (addr_t)(m_coherence_table[r_init_cmd_target.read()] + 4);
+        p_vci_ini.wdata   = r_write_to_init_cmd_data[r_init_cmd_cpt.read() +
+          r_write_to_init_cmd_index.read()].read();
+        if(r_write_to_init_cmd_we[r_init_cmd_cpt.read() +
+            r_write_to_init_cmd_index.read()].read())  
+          p_vci_ini.be      = 0xF;
+        else			p_vci_ini.be      = 0x0;
+        p_vci_ini.plen    = 4 * (r_write_to_init_cmd_count.read() + 2);
+        p_vci_ini.trdid   = r_write_to_init_cmd_trdid.read();
+        p_vci_ini.eop     = ( r_init_cmd_cpt.read() == (r_write_to_init_cmd_count.read()-1) );
+        break;
+
+      case INIT_CMD_SC_BRDCAST:
+        p_vci_ini.cmdval  = true;
+        p_vci_ini.address = BROADCAST_ADDR;
+        p_vci_ini.wdata   = (addr_t)r_llsc_to_init_cmd_nline.read();
+        p_vci_ini.be      = ((r_llsc_to_init_cmd_nline.read() >> 32) & 0x3);
+        p_vci_ini.plen    = 4 ;
+        p_vci_ini.eop     = true;
+        p_vci_ini.trdid   = r_llsc_to_init_cmd_trdid.read();
+        break;
+      case INIT_CMD_SC_UPDT_NLINE:
+        p_vci_ini.cmdval  = true;
+        p_vci_ini.address = (addr_t)(m_coherence_table[r_init_cmd_target.read()] + 4);
+        p_vci_ini.wdata   = (uint32_t)r_llsc_to_init_cmd_nline.read();
+        p_vci_ini.be      = ((r_llsc_to_init_cmd_nline.read() >> 32 ) & 0x3);
+        p_vci_ini.plen    = 4 * 3;
+        p_vci_ini.eop     = false;
+        p_vci_ini.trdid   = r_llsc_to_init_cmd_trdid.read();
+        break;
+      case INIT_CMD_SC_UPDT_INDEX:
+        p_vci_ini.cmdval  = true;
+        p_vci_ini.address = (addr_t)(m_coherence_table[r_init_cmd_target.read()] + 4);
+        p_vci_ini.wdata   = r_llsc_to_init_cmd_index.read();
+        p_vci_ini.be      = 0xF;
+        p_vci_ini.plen    = 4 * 3;
+        p_vci_ini.trdid   = r_llsc_to_init_cmd_trdid.read();
+        p_vci_ini.eop     = false;
+        break;
+      case INIT_CMD_SC_UPDT_DATA:
+        p_vci_ini.cmdval  = true;
+        p_vci_ini.address = (addr_t)(m_coherence_table[r_init_cmd_target.read()] + 4);
+        p_vci_ini.wdata   = r_llsc_to_init_cmd_wdata.read();
+        p_vci_ini.be      = 0xF;
+        p_vci_ini.plen    = 4 * 3;
+        p_vci_ini.trdid   = r_llsc_to_init_cmd_trdid.read();
+        p_vci_ini.eop     = true;
+        break;
+
+    } // end switch r_init_cmd_fsm
+
+    //////////////////////////////////////////////////////
+    // Response signals on the p_vci_ini port
+    //////////////////////////////////////////////////////
+
+    if ( r_init_rsp_fsm.read() == INIT_RSP_IDLE ) p_vci_ini.rspack  = true;
+    else                                          p_vci_ini.rspack  = false;
+
+    //////////////////////////////////////////////////////
+    // Response signals on the p_vci_tgt_cleanup port
+    //////////////////////////////////////////////////////
+    p_vci_tgt_cleanup.rspval = false;
+    p_vci_tgt_cleanup.rsrcid = 0;
+    p_vci_tgt_cleanup.rdata  = 0;
+    p_vci_tgt_cleanup.rpktid = 0;
+    p_vci_tgt_cleanup.rtrdid = 0;
+    p_vci_tgt_cleanup.rerror = 0;
+    p_vci_tgt_cleanup.reop   = false;
+    p_vci_tgt_cleanup.cmdack = false ;
+
+    switch(r_cleanup_fsm.read()){
+      case CLEANUP_IDLE:
+        {
+          p_vci_tgt_cleanup.cmdack = true ;
+          break;
+        }
+      case CLEANUP_RSP:
+        {
+          p_vci_tgt_cleanup.rspval = true;
+          p_vci_tgt_cleanup.rdata  = 0;
+          p_vci_tgt_cleanup.rsrcid = r_cleanup_srcid.read();
+          p_vci_tgt_cleanup.rpktid = r_cleanup_pktid.read();
+          p_vci_tgt_cleanup.rtrdid = r_cleanup_trdid.read();
+          p_vci_tgt_cleanup.rerror = 0;
+          p_vci_tgt_cleanup.reop   = 1;
+          break;
+        }
+
+    }
+
+  } // end genMoore()
+
+}} // end name space
+
+// Local Variables:
+// tab-width: 4
+// c-basic-offset: 4
+// c-file-offsets:((innamespace . 0)(inline-open . 0))
+// indent-tabs-mode: nil
+// End:
+
+// vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4
+
Index: branches/v4/modules/vci_mem_cache_v3/caba/metadata/vci_mem_cache_v3.sd
===================================================================
--- branches/v4/modules/vci_mem_cache_v3/caba/metadata/vci_mem_cache_v3.sd	(revision 371)
+++ branches/v4/modules/vci_mem_cache_v3/caba/metadata/vci_mem_cache_v3.sd	(revision 371)
@@ -0,0 +1,48 @@
+
+# -*- python -*-
+
+__id__ = "$Id$"
+__version__ = "$Revision$"
+
+Module('caba:vci_mem_cache_v3',
+       classname = 'soclib::caba::VciMemCacheV3',
+       tmpl_parameters = [parameter.Module('vci_param', default = 'caba:vci_param'),],
+       header_files = ['../source/include/vci_mem_cache_v3.h',
+                       '../source/include/xram_transaction_v3.h',
+                       '../source/include/mem_cache_directory_v3.h',
+                       '../source/include/atomic_tab_v3.h',
+                       '../source/include/update_tab_v3.h',],
+       implementation_files = ['../source/src/vci_mem_cache_v3.cpp',],
+       uses = [Uses('caba:base_module'),
+               Uses('common:loader'),
+               Uses('common:mapping_table'),
+               Uses('caba:generic_fifo'),
+               ],
+       ports = [Port('caba:vci_target', 'p_vci_tgt'),
+		Port('caba:vci_target','p_vci_tgt_cleanup'),
+		Port('caba:vci_initiator','p_vci_ini'),
+		Port('caba:vci_initiator','p_vci_ixr'),
+                Port('caba:bit_in', 'p_resetn', auto = 'resetn'),
+                Port('caba:clock_in', 'p_clk', auto = 'clock'),],
+       instance_parameters = [
+		parameter.Module('mtp', 'common:mapping_table'),
+		parameter.Module('mtc', 'common:mapping_table'),
+		parameter.Module('mtx', 'common:mapping_table'),
+		parameter.IntTab('vci_ixr_index'),
+		parameter.IntTab('vci_ini_index'),
+		parameter.IntTab('vci_tgt_index'),
+		parameter.IntTab('vci_tgt_index_cleanup'),
+    parameter.Int('nways'),
+		parameter.Int('nsets'),
+		parameter.Int('nwords'),
+		parameter.Int('heap_size'),
+		],
+       extensions = [
+          'dsx:get_ident='
+          'vci_ini_index:p_vci_ini:mtc,'
+          'vci_tgt_index_cleanup:p_vci_tgt_cleanup:mtc,'
+          'vci_tgt_index:p_vci_tgt:mtp,'
+          'vci_ixr_index:p_vci_ixr:mtx',
+		'dsx:addressable=vci_tgt_index,vci_tgt_index_cleanup',
+       ],
+)
Index: branches/v4/modules/vci_mem_cache_v3/caba/source/include/atomic_tab_v3.h
===================================================================
--- branches/v4/modules/vci_mem_cache_v3/caba/source/include/atomic_tab_v3.h	(revision 371)
+++ branches/v4/modules/vci_mem_cache_v3/caba/source/include/atomic_tab_v3.h	(revision 371)
@@ -0,0 +1,121 @@
+#ifndef ATOMIC_TAB_V3_H_
+#define ATOMIC_TAB_V3_H_
+
+#include <inttypes.h>
+#include <systemc>
+#include <cassert>
+#include "arithmetics.h"
+
+
+
+////////////////////////////////////////////////////////////////////////
+////////////////////////////////////////////////////////////////////////
+/*                  The atomic access tab                             */
+////////////////////////////////////////////////////////////////////////
+////////////////////////////////////////////////////////////////////////
+
+class AtomicTab{
+    typedef uint32_t size_t;
+    typedef sc_dt::sc_uint<40> addr_t;
+
+private:
+    size_t size_tab;                            // The size of the tab
+    std::vector<addr_t> addr_tab;               // Address entries
+    std::vector<bool>   valid_tab;              // Valid entries
+
+public:
+
+    AtomicTab()
+	: addr_tab(0),
+	  valid_tab(0)
+	{
+    	size_tab=0;
+    }
+
+    AtomicTab(size_t size_tab_i)
+	: addr_tab(size_tab_i),
+	  valid_tab(size_tab_i)
+	{
+	    size_tab=size_tab_i;
+    }
+
+
+    /////////////////////////////////////////////////////////////////////
+    /* The size() function returns the size of the tab */
+    /////////////////////////////////////////////////////////////////////
+    const size_t size(){
+	    return size_tab;
+    }
+
+
+    /////////////////////////////////////////////////////////////////////
+    /* The init() function initializes the transaction tab entries */
+    /////////////////////////////////////////////////////////////////////
+    void init(){
+    	for ( size_t i=0; i<size_tab; i++) {
+		    addr_tab[i]=0;
+		    valid_tab[i]=false;
+    	}
+    }
+
+
+    /////////////////////////////////////////////////////////////////////
+    /* The set() function sets an entry 
+       Arguments :
+       - id : the id of the initiator (index of the entry)
+       - addr : the address of the lock
+     */
+    /////////////////////////////////////////////////////////////////////
+    void set(const size_t id, const addr_t addr){
+	    assert( (id<size_tab) && "Atomic Tab Error : bad entry");
+	    addr_tab[id]=addr;
+	    valid_tab[id]=true;
+	    return;
+    }
+
+
+    /////////////////////////////////////////////////////////////////////
+    /* The isatomic() function tests if the SC request corresponds to an entry
+       Arguments :
+       - id : the id of the initiator (index of the entry)
+       - addr : the address of the lock
+
+       This function return true if the request corresponds
+     */
+    /////////////////////////////////////////////////////////////////////
+    bool isatomic(const size_t id, const addr_t addr){
+	    assert( (id<size_tab) && "Atomic Tab Error : bad entry");
+	    bool test=valid_tab[id];
+	    test=test && (addr == addr_tab[id]);
+	    return test;
+    }
+
+
+    /////////////////////////////////////////////////////////////////////
+    /* The reset() function resets all the entries for this lock
+       Arguments :
+       - addr : the address of the lock
+     */
+    /////////////////////////////////////////////////////////////////////
+    void reset(const addr_t addr){
+	    for(size_t i=0 ; i<size_tab ; i++){
+		    if(addr == addr_tab[i]){
+			    valid_tab[i]=false;
+		    }
+	    }
+	    return;
+    }
+
+};
+ 
+#endif
+
+// Local Variables:
+// tab-width: 4
+// c-basic-offset: 4
+// c-file-offsets:((innamespace . 0)(inline-open . 0))
+// indent-tabs-mode: nil
+// End:
+
+// vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4
+
Index: branches/v4/modules/vci_mem_cache_v3/caba/source/include/mem_cache_directory_v3.h
===================================================================
--- branches/v4/modules/vci_mem_cache_v3/caba/source/include/mem_cache_directory_v3.h	(revision 371)
+++ branches/v4/modules/vci_mem_cache_v3/caba/source/include/mem_cache_directory_v3.h	(revision 371)
@@ -0,0 +1,555 @@
+#ifndef SOCLIB_CABA_MEM_CACHE_DIRECTORY_V3_H
+#define SOCLIB_CABA_MEM_CACHE_DIRECTORY_V3_H 
+
+#include <inttypes.h>
+#include <systemc>
+#include <cassert>
+#include "arithmetics.h"
+
+namespace soclib { namespace caba {
+
+  using namespace sc_core;
+
+  ////////////////////////////////////////////////////////////////////////
+  //                    A LRU entry 
+  ////////////////////////////////////////////////////////////////////////
+  class LruEntry {
+
+    public:
+
+      bool recent;            
+
+      void init()
+      {
+        recent=false;
+      }
+
+  }; // end class LruEntry
+
+  ////////////////////////////////////////////////////////////////////////
+  //                    An Owner
+  ////////////////////////////////////////////////////////////////////////
+  class Owner{
+    typedef uint32_t size_t;
+    
+    public:
+    // Fields
+      bool      inst;       // Is the owner an ICache ?
+      size_t    srcid;      // The SRCID of the owner
+
+    ////////////////////////
+    // Constructors
+    ////////////////////////
+      Owner(bool i_inst,size_t i_srcid){
+        inst    = i_inst;
+        srcid   = i_srcid;
+      }
+
+      Owner(const Owner &a){
+        inst    = a.inst;
+        srcid   = a.srcid;
+      }
+
+      Owner(){
+        inst    = false;
+        srcid   = 0;
+      }
+      // end constructors
+
+  }; // end class Owner
+
+
+  ////////////////////////////////////////////////////////////////////////
+  //                    A directory entry                               
+  ////////////////////////////////////////////////////////////////////////
+  class DirectoryEntry {
+
+    typedef uint32_t tag_t;
+    typedef uint32_t size_t;
+
+    public:
+
+    bool    valid;                  // entry valid
+    bool    is_cnt;                 // directory entry is in counter mode
+    bool    dirty;                  // entry dirty
+    bool    lock;                   // entry locked
+    bool    inst;                   // at least one ICache owner
+    tag_t   tag;                    // tag of the entry
+    size_t  count;                  // number of copies
+    Owner   owner;                  // an owner of the line 
+    size_t  ptr;                    // pointer to the next owner
+
+    DirectoryEntry()
+    {
+      valid         = false;
+      is_cnt        = false;
+      dirty         = false;
+      lock          = false;
+      inst          = false;
+      tag           = 0;
+      count         = 0;
+      owner.inst    = 0;
+      owner.srcid   = 0;
+      ptr           = 0;
+    }
+
+    DirectoryEntry(const DirectoryEntry &source)
+    {
+      valid         = source.valid;
+      is_cnt        = source.is_cnt;
+      dirty         = source.dirty;
+      lock          = source.lock;
+      inst          = source.inst;
+      tag           = source.tag;
+      count         = source.count;
+      owner         = source.owner;
+      ptr           = source.ptr;
+    }          
+
+    /////////////////////////////////////////////////////////////////////
+    // The init() function initializes the entry 
+    /////////////////////////////////////////////////////////////////////
+    void init()
+    {
+      valid     = false;
+      is_cnt    = false;
+      dirty     = false;
+      lock      = false;
+      inst      = false;
+      count     = 0;
+    }
+
+    /////////////////////////////////////////////////////////////////////
+    // The copy() function copies an existing source entry to a target 
+    /////////////////////////////////////////////////////////////////////
+    void copy(const DirectoryEntry &source)
+    {
+      valid	    = source.valid;
+      is_cnt    = source.is_cnt;
+      dirty	    = source.dirty;
+      lock	    = source.lock;
+      inst      = source.inst;
+      tag	    = source.tag;
+      count     = source.count;
+      owner     = source.owner;
+      ptr       = source.ptr;
+    }
+
+    ////////////////////////////////////////////////////////////////////
+    // The print() function prints the entry 
+    ////////////////////////////////////////////////////////////////////
+    void print()
+    {
+      std::cout << "Valid = " << valid << " ; IS COUNT = " << is_cnt << " ; Dirty = " << dirty << " ; Lock = " 
+        << lock << " ; Inst = " << inst << " ; Tag = " << std::hex << tag << std::dec << " ; Count = " << count << " ; Owner = " << owner.srcid << " " << owner.inst << " ; Pointer = " << ptr << std::endl;
+    }
+
+  }; // end class DirectoryEntry
+
+  ////////////////////////////////////////////////////////////////////////
+  //                       The directory  
+  ////////////////////////////////////////////////////////////////////////
+  class CacheDirectory {
+
+    typedef sc_dt::sc_uint<40> addr_t;
+    typedef uint32_t data_t;
+    typedef uint32_t tag_t;
+    typedef uint32_t size_t;
+
+    private:
+
+    // Directory constants
+    size_t					m_ways;
+    size_t					m_sets;
+    size_t					m_words;
+    size_t					m_width;
+
+    // the directory & lru tables
+    DirectoryEntry 				**m_dir_tab;
+    LruEntry	 				**m_lru_tab;
+
+    public:
+
+    ////////////////////////
+    // Constructor
+    ////////////////////////
+    CacheDirectory( size_t ways, size_t sets, size_t words, size_t address_width)	 
+    {
+      m_ways  = ways; 
+      m_sets  = sets;
+      m_words = words;
+      m_width = address_width;
+
+      m_dir_tab = new DirectoryEntry*[sets];
+      for ( size_t i=0; i<sets; i++ ) {
+        m_dir_tab[i] = new DirectoryEntry[ways];
+        for ( size_t j=0 ; j<ways ; j++) m_dir_tab[i][j].init();
+      }
+      m_lru_tab = new LruEntry*[sets];
+      for ( size_t i=0; i<sets; i++ ) {
+        m_lru_tab[i] = new LruEntry[ways];
+        for ( size_t j=0 ; j<ways ; j++) m_lru_tab[i][j].init();
+      }
+    } // end constructor
+
+    /////////////////
+    // Destructor
+    /////////////////
+    ~CacheDirectory()
+    {
+      for(size_t i=0 ; i<m_sets ; i++){
+        delete [] m_dir_tab[i];
+        delete [] m_lru_tab[i];
+      }
+      delete [] m_dir_tab;
+      delete [] m_lru_tab;
+    } // end destructor
+
+    /////////////////////////////////////////////////////////////////////
+    // The read() function reads a directory entry. In case of hit, the
+    // LRU is updated.
+    // Arguments :
+    // - address : the address of the entry 
+    // - way : (return argument) the way of the entry in case of hit
+    // The function returns a copy of a (valid or invalid) entry  
+    /////////////////////////////////////////////////////////////////////
+    DirectoryEntry read(const addr_t &address,size_t &way)
+    {
+
+#define L2 soclib::common::uint32_log2
+      const size_t set = (size_t)(address >> (L2(m_words) + 2)) & (m_sets - 1);
+      const tag_t  tag = (tag_t)(address >> (L2(m_sets) + L2(m_words) + 2));
+#undef L2
+
+      bool hit       = false;
+      for ( size_t i=0 ; i<m_ways ; i++ ) {
+        bool equal = ( m_dir_tab[set][i].tag == tag );
+        bool valid = m_dir_tab[set][i].valid;
+        hit = equal && valid;
+        if ( hit ) {			
+          way = i;
+          break;
+        } 
+      }
+      if ( hit ) {
+        m_lru_tab[set][way].recent = true;
+        return DirectoryEntry(m_dir_tab[set][way]);
+      } else {
+        return DirectoryEntry();
+      }
+    } // end read()
+
+    /////////////////////////////////////////////////////////////////////
+    // The write function writes a new entry, 
+    // and updates the LRU bits if necessary.
+    // Arguments :
+    // - set : the set of the entry
+    // - way : the way of the entry
+    // - entry : the entry value
+    /////////////////////////////////////////////////////////////////////
+    void write(const size_t &set, const size_t &way, const DirectoryEntry &entry)
+    {
+      assert( (set<m_sets) 
+          && "Cache Directory write : The set index is invalid");
+      assert( (way<m_ways) 
+          && "Cache Directory write : The way index is invalid");
+
+      // update Directory
+      m_dir_tab[set][way].copy(entry);
+
+      // update LRU bits
+      bool all_recent = true;
+      for ( size_t i=0 ; i<m_ways ; i++ ) {
+        if ( i != way ) all_recent = m_lru_tab[set][i].recent && all_recent;
+      }
+      if ( all_recent ) {
+        for( size_t i=0 ; i<m_ways ; i++ ) m_lru_tab[set][i].recent = false;
+      } else {
+        m_lru_tab[set][way].recent = true;
+      }
+    } // end write()
+
+    /////////////////////////////////////////////////////////////////////
+    // The print() function prints a selected directory entry
+    // Arguments :
+    // - set : the set of the entry to print
+    // - way : the way of the entry to print
+    /////////////////////////////////////////////////////////////////////
+    void print(const size_t &set, const size_t &way)
+    {
+      std::cout << std::dec << " set : " << set << " ; way : " << way << " ; " ;
+      m_dir_tab[set][way].print();
+    } // end print()
+
+    /////////////////////////////////////////////////////////////////////
+    // The select() function selects a directory entry to evince.
+    // Arguments :
+    // - set   : (input argument) the set to modify
+    // - way   : (return argument) the way to evince
+    /////////////////////////////////////////////////////////////////////
+    DirectoryEntry select(const size_t &set, size_t &way)
+    {
+      assert( (set < m_sets) 
+          && "Cache Directory : (select) The set index is invalid");
+
+      for(size_t i=0; i<m_ways; i++){
+        if(!m_dir_tab[set][i].valid){
+          way=i;
+          return DirectoryEntry(m_dir_tab[set][way]);
+        }
+      }
+      for(size_t i=0; i<m_ways; i++){
+        if(!(m_lru_tab[set][i].recent) && !(m_dir_tab[set][i].lock)){
+          way=i;
+          return DirectoryEntry(m_dir_tab[set][way]);
+        }
+      }
+      for(size_t i=0; i<m_ways; i++){
+        if( !(m_lru_tab[set][i].recent) && (m_dir_tab[set][i].lock)){
+          way=i;
+          return DirectoryEntry(m_dir_tab[set][way]);
+        }
+      }
+      for(size_t i=0; i<m_ways; i++){
+        if( (m_lru_tab[set][i].recent) && !(m_dir_tab[set][i].lock)){
+          way=i;
+          return DirectoryEntry(m_dir_tab[set][way]);
+        }
+      }
+      way = 0;
+      return DirectoryEntry(m_dir_tab[set][0]);
+    } // end select()
+
+    /////////////////////////////////////////////////////////////////////
+    // 		Global initialisation function
+    /////////////////////////////////////////////////////////////////////
+    void init()
+    {
+      for ( size_t set=0 ; set<m_sets ; set++ ) {
+        for ( size_t way=0 ; way<m_ways ; way++ ) {
+          m_dir_tab[set][way].init();
+          m_lru_tab[set][way].init();
+        }
+      }
+    } // end init()
+
+  }; // end class CacheDirectory
+
+  ///////////////////////////////////////////////////////////////////////
+  //                    A Heap Entry
+  ///////////////////////////////////////////////////////////////////////
+  class HeapEntry{
+    typedef uint32_t size_t;
+
+    public:
+    // Fields of the entry
+      Owner     owner;
+      size_t    next;
+
+    ////////////////////////
+    // Constructor
+    ////////////////////////
+      HeapEntry()
+      :owner(false,0)
+      {
+        next = 0;
+      } // end constructor
+
+    ////////////////////////
+    // Constructor
+    ////////////////////////
+      HeapEntry(const HeapEntry &entry){
+        owner.srcid = entry.owner.srcid;
+        owner.inst  = entry.owner.inst;
+        next        = entry.next;
+      } // end constructor
+
+    /////////////////////////////////////////////////////////////////////
+    // The copy() function copies an existing source entry to a target 
+    /////////////////////////////////////////////////////////////////////
+      void copy(const HeapEntry &entry){
+        owner.srcid = entry.owner.srcid;
+        owner.inst  = entry.owner.inst;
+        next        = entry.next;
+      } // end copy()
+
+    ////////////////////////////////////////////////////////////////////
+    // The print() function prints the entry 
+    ////////////////////////////////////////////////////////////////////
+      void print(){
+        std::cout 
+        << " -- owner.srcid : " << std::dec << owner.srcid << std::endl
+        << " -- owner.inst  : " << std::dec << owner.inst << std::endl
+        << " -- next        : " << std::dec << next << std::endl;
+
+      } // end print()
+
+  }; // end class HeapEntry
+
+  ////////////////////////////////////////////////////////////////////////
+  //                        The Heap 
+  ////////////////////////////////////////////////////////////////////////
+  class HeapDirectory{
+    typedef uint32_t size_t;
+    
+    private:
+    // Registers and the heap
+      size_t    ptr_free;
+      bool      full;
+      HeapEntry *m_heap_tab;
+
+    // Constants for debugging purpose
+      size_t    tab_size;
+
+    public:
+    ////////////////////////
+    // Constructor
+    ////////////////////////
+      HeapDirectory(uint32_t size){
+        assert(size>0 && "Memory Cache, HeapDirectory constructor : invalid size");
+        ptr_free    = 0;
+        full        = false;
+        m_heap_tab  = new HeapEntry[size];
+        tab_size    = size;
+      } // end constructor
+
+    /////////////////
+    // Destructor
+    /////////////////
+      ~HeapDirectory(){
+        delete [] m_heap_tab;
+      } // end destructor
+
+    /////////////////////////////////////////////////////////////////////
+    // 		Global initialisation function
+    /////////////////////////////////////////////////////////////////////
+      void init(){
+        ptr_free=0;
+        full=false;
+        for(size_t i=0; i< tab_size-1;i++){
+          m_heap_tab[i].next = i+1;
+        }
+        m_heap_tab[tab_size-1].next = tab_size-1;
+        return;
+      }
+
+    /////////////////////////////////////////////////////////////////////
+    // The print() function prints a selected directory entry
+    // Arguments :
+    // - ptr : the pointer to the entry to print
+    /////////////////////////////////////////////////////////////////////
+      void print(const size_t &ptr){
+        std::cout << "Heap, printing the entry : " << std::dec << ptr << std::endl;
+        m_heap_tab[ptr].print();
+      } // end print()
+
+    /////////////////////////////////////////////////////////////////////
+    // The print_list() function prints a list from selected directory entry
+    // Arguments :
+    // - ptr : the pointer to the first entry to print
+    /////////////////////////////////////////////////////////////////////
+      void print_list(const size_t &ptr){
+        bool end = false;
+        size_t ptr_temp = ptr;
+        std::cout << "Heap, printing the list from : " << std::dec << ptr << std::endl;
+        while(!end){
+            m_heap_tab[ptr_temp].print();
+            if(ptr_temp == m_heap_tab[ptr_temp].next) end = true;
+            ptr_temp = m_heap_tab[ptr_temp].next;
+        } 
+      } // end print_list()
+
+
+    /////////////////////////////////////////////////////////////////////
+    // The is_full() function return true if the heap is full.
+    /////////////////////////////////////////////////////////////////////
+      bool is_full(){
+        return full;
+      } // end is_full()
+
+    /////////////////////////////////////////////////////////////////////
+    // The next_free_ptr() function returns the pointer 
+    // to the next free entry.
+    /////////////////////////////////////////////////////////////////////
+      size_t next_free_ptr(){
+        return ptr_free;
+      } // end next_free_ptr()
+
+    /////////////////////////////////////////////////////////////////////
+    // The next_free_entry() function returns 
+    // a copy of the next free entry.
+    /////////////////////////////////////////////////////////////////////
+      HeapEntry next_free_entry(){
+        return HeapEntry(m_heap_tab[ptr_free]);
+      } // end next_free_entry()
+   
+    /////////////////////////////////////////////////////////////////////
+    // The write_free_entry() function modify the next free entry.
+    // Arguments :
+    // - entry : the entry to write
+    /////////////////////////////////////////////////////////////////////
+      void write_free_entry(const HeapEntry &entry){
+        m_heap_tab[ptr_free].copy(entry);
+      } // end write_free_entry()
+
+    /////////////////////////////////////////////////////////////////////
+    // The write_free_ptr() function writes the pointer
+    // to the next free entry
+    /////////////////////////////////////////////////////////////////////
+      void write_free_ptr(const size_t &ptr){
+        assert( (ptr<tab_size) && "HeapDirectory error : try to write a wrong free pointer");
+        ptr_free = ptr;
+      } // end write_free_ptr()
+
+    /////////////////////////////////////////////////////////////////////
+    // The set_full() function sets the full bit (to true).
+    /////////////////////////////////////////////////////////////////////
+      void set_full(){
+        full = true;
+      } // end set_full()
+
+    /////////////////////////////////////////////////////////////////////
+    // The unset_full() function unsets the full bit (to false).
+    /////////////////////////////////////////////////////////////////////
+      void unset_full(){
+        full = false;
+      } // end unset_full()
+
+    /////////////////////////////////////////////////////////////////////
+    // The read() function returns a copy of
+    // the entry pointed by the argument
+    // Arguments :
+    //  - ptr : the pointer to the entry to read
+    /////////////////////////////////////////////////////////////////////
+      HeapEntry read(const size_t &ptr){
+        assert( (ptr<tab_size) && "HeapDirectory error : try to write a wrong free pointer");
+        return HeapEntry(m_heap_tab[ptr]);
+      } // end read()
+
+    /////////////////////////////////////////////////////////////////////
+    // The write() function writes an entry in the heap
+    // Arguments :
+    //  - ptr : the pointer to the entry to replace
+    //  - entry : the entry to write
+    /////////////////////////////////////////////////////////////////////
+      void write(const size_t &ptr, const HeapEntry &entry){
+        assert( (ptr<tab_size) && "HeapDirectory error : try to write a wrong free pointer");
+        m_heap_tab[ptr].copy(entry);
+      } // end write()
+
+  }; // end class HeapDirectory
+
+
+}} // end namespaces
+
+#endif
+
+// Local Variables:
+// tab-width: 4
+// c-basic-offset: 4
+// c-file-offsets:((innamespace . 0)(inline-open . 0))
+// indent-tabs-mode: nil
+// End:
+
+// vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4
+
Index: branches/v4/modules/vci_mem_cache_v3/caba/source/include/update_tab_v3.h
===================================================================
--- branches/v4/modules/vci_mem_cache_v3/caba/source/include/update_tab_v3.h	(revision 371)
+++ branches/v4/modules/vci_mem_cache_v3/caba/source/include/update_tab_v3.h	(revision 371)
@@ -0,0 +1,402 @@
+#ifndef UPDATE_TAB_V3_H_
+#define UPDATE_TAB_V3_H_
+
+#include <inttypes.h>
+#include <systemc>
+#include <cassert>
+#include "arithmetics.h"
+
+////////////////////////////////////////////////////////////////////////
+//                  An update tab entry    
+////////////////////////////////////////////////////////////////////////
+class UpdateTabEntry {
+  typedef uint32_t size_t;
+  typedef sc_dt::sc_uint<40> addr_t;
+
+  public:
+  bool 	valid;                // It is a valid pending transaction
+  bool	update;               // It is an update transaction
+  bool  brdcast;              // It is a broadcast invalidate
+  bool  rsp;                  // It needs a response to the initiator
+  size_t 	srcid;        // The srcid of the initiator which wrote the data
+  size_t 	trdid;        // The trdid of the initiator which wrote the data
+  size_t 	pktid;        // The pktid of the initiator which wrote the data
+  addr_t	nline;	      // The identifier of the cache line
+  size_t 	count;        // The number of acknowledge responses to receive
+
+  UpdateTabEntry(){
+    valid	= false;
+    update  = false;
+    brdcast = false;
+    rsp     = false;
+    srcid	= 0;
+    trdid	= 0;
+    pktid	= 0;
+    nline	= 0;
+    count	= 0;
+  }
+
+  UpdateTabEntry(bool   i_valid, 
+      bool   i_update,
+      bool   i_brdcast,
+      bool   i_rsp,
+      size_t i_srcid, 
+      size_t i_trdid, 
+      size_t i_pktid, 
+      addr_t i_nline,
+      size_t i_count) 
+  {
+    valid		= i_valid;
+    update	    = i_update;
+    brdcast     = i_brdcast;
+    rsp         = i_rsp;
+    srcid		= i_srcid;
+    trdid		= i_trdid;
+    pktid		= i_pktid;
+    nline		= i_nline;
+    count		= i_count;
+  }
+
+  UpdateTabEntry(const UpdateTabEntry &source)
+  {
+    valid   = source.valid;
+    update  = source.update;
+    brdcast = source.brdcast;
+    rsp     = source.rsp;
+    srcid   = source.srcid;
+    trdid   = source.trdid;
+    pktid   = source.pktid;
+    nline   = source.nline;
+    count   = source.count;
+  }
+
+  ////////////////////////////////////////////////////
+  // The init() function initializes the entry 
+  ///////////////////////////////////////////////////
+  void init()
+  {
+    valid  = false;
+    update = false;
+    brdcast= false;
+    rsp    = false;
+    srcid  = 0;
+    trdid  = 0;
+    pktid  = 0;
+    nline  = 0;
+    count  = 0;
+  }
+
+  ////////////////////////////////////////////////////////////////////
+  // The copy() function copies an existing entry
+  // Its arguments are :
+  // - source : the update tab entry to copy
+  ////////////////////////////////////////////////////////////////////
+  void copy(const UpdateTabEntry &source)
+  {
+    valid  = source.valid;
+    update = source.update;
+    brdcast= source.brdcast;
+    rsp    = source.rsp;
+    srcid  = source.srcid;
+    trdid  = source.trdid;
+    pktid  = source.pktid;
+    nline  = source.nline;
+    count  = source.count;
+  }
+
+  ////////////////////////////////////////////////////////////////////
+  // The print() function prints the entry  
+  ////////////////////////////////////////////////////////////////////
+  void print(){
+    std::cout << std::dec << "valid  = " << valid  << std::endl;
+    std::cout << "update = " << update << std::endl;
+    std::cout << "brdcast= " << brdcast<< std::endl;
+    std::cout << "rsp    = " << rsp    << std::endl;
+    std::cout << "srcid  = " << srcid  << std::endl; 
+    std::cout << "trdid  = " << trdid  << std::endl; 
+    std::cout << "pktid  = " << pktid  << std::endl; 
+    std::cout << std::hex << "nline  = " << nline  << std::endl;
+    std::cout << std::dec << "count  = " << count  << std::endl;
+  }
+};
+
+////////////////////////////////////////////////////////////////////////
+//                        The update tab             
+////////////////////////////////////////////////////////////////////////
+class UpdateTab{
+
+  typedef uint32_t size_t;
+  typedef sc_dt::sc_uint<40> addr_t;
+
+  private:
+  size_t size_tab;
+  std::vector<UpdateTabEntry> tab;
+
+  public:
+
+  UpdateTab()
+    : tab(0)
+  {
+    size_tab=0;
+  }
+
+  UpdateTab(size_t size_tab_i)
+    : tab(size_tab_i)
+  {
+    size_tab=size_tab_i;
+  }
+
+  ////////////////////////////////////////////////////////////////////
+  // The size() function returns the size of the tab  
+  ////////////////////////////////////////////////////////////////////
+  const size_t size(){
+    return size_tab;
+  }
+
+
+  ////////////////////////////////////////////////////////////////////
+  // The size() function returns the size of the tab  
+  ////////////////////////////////////////////////////////////////////
+  void print(){
+    for(size_t i=0; i<size_tab; i++) {
+      std::cout << "UPDATE TAB ENTRY " << std::dec << i << "--------" << std::endl;
+      tab[i].print();
+    }
+    return;
+  }
+
+
+  /////////////////////////////////////////////////////////////////////
+  // The init() function initializes the tab 
+  /////////////////////////////////////////////////////////////////////
+  void init(){
+    for ( size_t i=0; i<size_tab; i++) {
+      tab[i].init();
+    }
+  }
+
+
+  /////////////////////////////////////////////////////////////////////
+  // The reads() function reads an entry 
+  // Arguments :
+  // - entry : the entry to read
+  // This function returns a copy of the entry.
+  /////////////////////////////////////////////////////////////////////
+  UpdateTabEntry read (size_t entry)
+  {
+    assert(entry<size_tab && "Bad Update Tab Entry");
+    return UpdateTabEntry(tab[entry]);
+  }
+
+  ///////////////////////////////////////////////////////////////////////////
+  // The set() function writes an entry in the Update Table
+  // Arguments :
+  // - update : transaction type (bool)
+  // - srcid : srcid of the initiator
+  // - trdid : trdid of the initiator
+  // - pktid : pktid of the initiator
+  // - count : number of expected responses
+  // - index : (return argument) index of the selected entry
+  // This function returns true if the write successed (an entry was empty).
+  ///////////////////////////////////////////////////////////////////////////
+  bool set(const bool	update,
+      const bool   brdcast,
+      const bool   rsp,
+      const size_t srcid,
+      const size_t trdid,
+      const size_t pktid,
+      const addr_t nline,
+      const size_t count,
+      size_t &index)
+  {
+    for ( size_t i=0 ; i<size_tab ; i++ ) {
+      if( !tab[i].valid ) {
+        tab[i].valid		= true;
+        tab[i].update		= update;
+        tab[i].brdcast      = brdcast;
+        tab[i].rsp          = rsp;
+        tab[i].srcid		= (size_t) srcid;
+        tab[i].trdid		= (size_t) trdid;
+        tab[i].pktid		= (size_t) pktid;
+        tab[i].nline		= (addr_t) nline;
+        tab[i].count		= (size_t) count;
+        index			    = i;
+        return true;
+      }
+    }
+    return false;
+  } // end set()
+
+  /////////////////////////////////////////////////////////////////////
+  // The decrement() function decrements the counter for a given entry.
+  // Arguments :
+  // - index   : the index of the entry
+  // - counter : (return argument) value of the counter after decrement
+  // This function returns true if the entry is valid.
+  /////////////////////////////////////////////////////////////////////
+  bool decrement( const size_t index,
+      size_t &counter ) 
+  {
+    assert((index<size_tab) && "Bad Update Tab Entry");
+    if ( tab[index].valid ) {
+      tab[index].count--;
+      counter = tab[index].count;
+      return true;
+    } else {
+      return false;
+    }
+  }
+
+  /////////////////////////////////////////////////////////////////////
+  // The is_full() function returns true if the table is full
+  /////////////////////////////////////////////////////////////////////
+  bool is_full()
+  {
+    for(size_t i = 0 ; i < size_tab ; i++){
+      if(!tab[i].valid){
+        return false;
+      }
+    }
+    return true;
+  }
+
+  /////////////////////////////////////////////////////////////////////
+  // The need_rsp() function returns the need of a response
+  // Arguments :
+  // - index : the index of the entry
+  /////////////////////////////////////////////////////////////////////
+  bool need_rsp(const size_t index)
+  {
+    assert(index<size_tab && "Bad Update Tab Entry");
+    return tab[index].rsp;	
+  }
+
+  /////////////////////////////////////////////////////////////////////
+  // The is_update() function returns the transaction type
+  // Arguments :
+  // - index : the index of the entry
+  /////////////////////////////////////////////////////////////////////
+  bool is_brdcast(const size_t index)
+  {
+    assert(index<size_tab && "Bad Update Tab Entry");
+    return tab[index].brdcast;	
+  }
+
+  /////////////////////////////////////////////////////////////////////
+  // The is_update() function returns the transaction type
+  // Arguments :
+  // - index : the index of the entry
+  /////////////////////////////////////////////////////////////////////
+  bool is_update(const size_t index)
+  {
+    assert(index<size_tab && "Bad Update Tab Entry");
+    return tab[index].update;	
+  }
+
+  /////////////////////////////////////////////////////////////////////
+  // The srcid() function returns the srcid value
+  // Arguments :
+  // - index : the index of the entry
+  /////////////////////////////////////////////////////////////////////
+  size_t srcid(const size_t index)
+  {
+    assert(index<size_tab && "Bad Update Tab Entry");
+    return tab[index].srcid;	
+  }
+
+  /////////////////////////////////////////////////////////////////////
+  // The trdid() function returns the trdid value
+  // Arguments :
+  // - index : the index of the entry
+  /////////////////////////////////////////////////////////////////////
+  size_t trdid(const size_t index)
+  {
+    assert(index<size_tab && "Bad Update Tab Entry");
+    return tab[index].trdid;	
+  }
+
+  /////////////////////////////////////////////////////////////////////
+  // The pktid() function returns the pktid value
+  // Arguments :
+  // - index : the index of the entry
+  /////////////////////////////////////////////////////////////////////
+  size_t pktid(const size_t index)
+  {
+    assert(index<size_tab && "Bad Update Tab Entry");
+    return tab[index].pktid;	
+  }
+
+  /////////////////////////////////////////////////////////////////////
+  // The nline() function returns the nline value
+  // Arguments :
+  // - index : the index of the entry
+  /////////////////////////////////////////////////////////////////////
+  addr_t nline(const size_t index)
+  {
+    assert(index<size_tab && "Bad Update Tab Entry");
+    return tab[index].nline;
+  }
+
+  /////////////////////////////////////////////////////////////////////
+  // The search_inval() function returns the index of the entry in UPT
+  // Arguments :
+  // - nline : the line number of the entry in the directory
+  /////////////////////////////////////////////////////////////////////
+  bool search_inval(const addr_t nline,size_t &index)
+  {
+    size_t i ;
+
+    for (i = 0 ; i < size_tab ; i++){
+      if((tab[i].nline == nline) && tab[i].valid){
+        if(!tab[i].update){
+          index = i ;
+          return true;
+        }
+      }
+    }
+    return false;
+  }
+
+  /////////////////////////////////////////////////////////////////////
+  // The read_nline() function returns the index of the entry in UPT
+  // Arguments :
+  // - nline : the line number of the entry in the directory
+  /////////////////////////////////////////////////////////////////////
+  bool read_nline(const addr_t nline,size_t &index) 
+  {
+    size_t i ;
+
+    for (i = 0 ; i < size_tab ; i++){
+      if((tab[i].nline == nline) && tab[i].valid){
+        index = i ;
+        return true;
+      }
+    }
+    return false;
+  }
+
+  /////////////////////////////////////////////////////////////////////
+  // The clear() function erases an entry of the tab
+  // Arguments :
+  // - index : the index of the entry
+  /////////////////////////////////////////////////////////////////////       
+  void clear(const size_t index)
+  {
+    assert(index<size_tab && "Bad Update Tab Entry");
+    tab[index].valid=false;
+    return;	
+  }
+
+};
+
+#endif
+
+// Local Variables:
+// tab-width: 4
+// c-basic-offset: 4
+// c-file-offsets:((innamespace . 0)(inline-open . 0))
+// indent-tabs-mode: nil
+// End:
+
+// vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4
+
Index: branches/v4/modules/vci_mem_cache_v3/caba/source/include/vci_mem_cache_v3.h
===================================================================
--- branches/v4/modules/vci_mem_cache_v3/caba/source/include/vci_mem_cache_v3.h	(revision 371)
+++ branches/v4/modules/vci_mem_cache_v3/caba/source/include/vci_mem_cache_v3.h	(revision 371)
@@ -0,0 +1,716 @@
+/* -*- c++ -*-
+ * File         : vci_mem_cache_v3.h
+ * Date         : 26/10/2008
+ * Copyright    : UPMC / LIP6
+ * Authors      : Alain Greiner / Eric Guthmuller
+ *
+ * SOCLIB_LGPL_HEADER_BEGIN
+ *
+ * This file is part of SoCLib, GNU LGPLv2.1.
+ *
+ * SoCLib is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU Lesser General Public License as published
+ * by the Free Software Foundation; version 2.1 of the License.
+ *
+ * SoCLib is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with SoCLib; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301 USA
+ *
+ * SOCLIB_LGPL_HEADER_END
+ *
+ * Maintainers: alain eric.guthmuller@polytechnique.edu
+ */
+/*
+ *
+ * Modifications done by Christophe Choichillon on the 7/04/2009:
+ * - Adding new states in the CLEANUP FSM : CLEANUP_UPT_LOCK and CLEANUP_UPT_WRITE
+ * - Adding a new VCI target port for the CLEANUP network
+ * - Adding new state in the ALLOC_UPT_FSM : ALLOC_UPT_CLEANUP
+ * 
+ * Modifications to do :
+ * - Adding new variables used by the CLEANUP FSM
+ *
+ */
+
+#ifndef SOCLIB_CABA_MEM_CACHE_V3_H
+#define SOCLIB_CABA_MEM_CACHE_V3_H
+
+#include <inttypes.h>
+#include <systemc>
+#include <list>
+#include <cassert>
+#include "arithmetics.h"
+#include "alloc_elems.h"
+#include "caba_base_module.h"
+#include "vci_target.h"
+#include "vci_initiator.h"
+#include "generic_fifo.h"
+#include "mapping_table.h"
+#include "int_tab.h"
+#include "mem_cache_directory_v3.h"
+#include "xram_transaction_v3.h"
+#include "update_tab_v3.h"
+#include "atomic_tab_v3.h"
+
+#define TRANSACTION_TAB_LINES 4     // Number of lines in the transaction tab
+#define UPDATE_TAB_LINES 4          // Number of lines in the update tab
+
+namespace soclib {  namespace caba {
+  using namespace sc_core;
+
+  template<typename vci_param>
+    class VciMemCacheV3
+    : public soclib::caba::BaseModule
+    {
+      typedef sc_dt::sc_uint<40> addr_t;
+      typedef typename vci_param::fast_addr_t vci_addr_t;
+      typedef uint32_t data_t;
+      typedef uint32_t tag_t;
+      typedef uint32_t size_t;
+      typedef uint32_t be_t;
+      typedef uint32_t copy_t;
+
+      /* States of the TGT_CMD fsm */
+      enum tgt_cmd_fsm_state_e{
+        TGT_CMD_IDLE,
+        TGT_CMD_READ,
+        TGT_CMD_READ_EOP,
+        TGT_CMD_WRITE,
+        TGT_CMD_ATOMIC,
+      };
+
+      /* States of the TGT_RSP fsm */
+      enum tgt_rsp_fsm_state_e{
+        TGT_RSP_READ_IDLE,
+        TGT_RSP_WRITE_IDLE,
+        TGT_RSP_LLSC_IDLE,
+        TGT_RSP_XRAM_IDLE,
+        TGT_RSP_INIT_IDLE,
+        TGT_RSP_CLEANUP_IDLE,
+        TGT_RSP_READ,
+        TGT_RSP_WRITE,
+        TGT_RSP_LLSC,
+        TGT_RSP_XRAM,
+        TGT_RSP_INIT,
+        TGT_RSP_CLEANUP,
+      };
+
+      /* States of the INIT_CMD fsm */
+      enum init_cmd_fsm_state_e{
+        INIT_CMD_INVAL_IDLE,
+        INIT_CMD_INVAL_NLINE,
+        INIT_CMD_XRAM_BRDCAST,
+        INIT_CMD_UPDT_IDLE,
+        INIT_CMD_WRITE_BRDCAST,
+        INIT_CMD_UPDT_NLINE,
+        INIT_CMD_UPDT_INDEX,
+        INIT_CMD_UPDT_DATA,
+        INIT_CMD_SC_UPDT_IDLE,
+        INIT_CMD_SC_BRDCAST,
+        INIT_CMD_SC_UPDT_NLINE,
+        INIT_CMD_SC_UPDT_INDEX,
+        INIT_CMD_SC_UPDT_DATA,
+      };
+
+      /* States of the INIT_RSP fsm */
+      enum init_rsp_fsm_state_e{
+        INIT_RSP_IDLE,
+        INIT_RSP_UPT_LOCK,
+        INIT_RSP_UPT_CLEAR,
+        INIT_RSP_END,
+      };
+
+      /* States of the READ fsm */
+      enum read_fsm_state_e{
+        READ_IDLE,
+        READ_DIR_LOCK,
+        READ_DIR_HIT,
+        READ_HEAP_LOCK,
+        READ_HEAP_WRITE,
+        READ_HEAP_ERASE,
+        READ_HEAP_LAST,
+        READ_RSP,
+        READ_TRT_LOCK,
+        READ_TRT_SET,
+        READ_XRAM_REQ,
+      };
+
+      /* States of the WRITE fsm */
+      enum write_fsm_state_e{
+        WRITE_IDLE,
+        WRITE_NEXT,
+        WRITE_DIR_LOCK,
+        WRITE_DIR_HIT_READ,
+        WRITE_DIR_HIT,
+        WRITE_DIR_HIT_RSP,
+        WRITE_UPT_LOCK,
+        WRITE_HEAP_LOCK,
+        WRITE_UPT_REQ,
+        WRITE_UPDATE,
+        WRITE_UPT_DEC,
+        WRITE_RSP,
+        WRITE_TRT_LOCK,
+        WRITE_TRT_DATA,
+        WRITE_TRT_SET,
+        WRITE_WAIT,
+        WRITE_XRAM_REQ,
+        WRITE_TRT_WRITE_LOCK,
+        WRITE_INVAL_LOCK,
+        WRITE_DIR_INVAL,
+        WRITE_INVAL,
+        WRITE_XRAM_SEND,
+        WRITE_HEAP_ERASE,
+        WRITE_HEAP_LAST,
+      };
+
+      /* States of the IXR_RSP fsm */
+      enum ixr_rsp_fsm_state_e{
+        IXR_RSP_IDLE,
+        IXR_RSP_ACK,
+        IXR_RSP_TRT_ERASE,
+        IXR_RSP_TRT_READ,
+      };
+
+      /* States of the XRAM_RSP fsm */
+      enum xram_rsp_fsm_state_e{
+        XRAM_RSP_IDLE,
+        XRAM_RSP_TRT_COPY,
+        XRAM_RSP_TRT_DIRTY,
+        XRAM_RSP_DIR_LOCK,
+        XRAM_RSP_DIR_UPDT,
+        XRAM_RSP_DIR_RSP,
+        XRAM_RSP_INVAL_LOCK,
+        XRAM_RSP_INVAL_WAIT,
+        XRAM_RSP_INVAL,
+        XRAM_RSP_WRITE_DIRTY,
+        XRAM_RSP_HEAP_ERASE,
+        XRAM_RSP_HEAP_LAST,
+      };
+
+      /* States of the IXR_CMD fsm */
+      enum ixr_cmd_fsm_state_e{
+        IXR_CMD_READ_IDLE,
+        IXR_CMD_WRITE_IDLE,
+        IXR_CMD_LLSC_IDLE,
+        IXR_CMD_XRAM_IDLE,
+        IXR_CMD_READ_NLINE,
+        IXR_CMD_WRITE_NLINE,
+        IXR_CMD_LLSC_NLINE,
+        IXR_CMD_XRAM_DATA,
+      };
+
+      /* States of the LLSC fsm */
+      enum llsc_fsm_state_e{
+        LLSC_IDLE,
+        LL_DIR_LOCK,
+        LL_DIR_HIT,
+        LL_RSP,
+        SC_DIR_LOCK,
+        SC_DIR_HIT,
+        SC_UPT_LOCK,
+        SC_WAIT,
+        SC_HEAP_LOCK,
+        SC_UPT_REQ,
+        SC_UPDATE,
+        SC_TRT_LOCK,
+        SC_INVAL_LOCK,
+        SC_DIR_INVAL,
+        SC_INVAL,
+        SC_XRAM_SEND,
+        SC_HEAP_ERASE,
+        SC_HEAP_LAST,
+        SC_RSP_FALSE,
+        SC_RSP_TRUE,
+        LLSC_TRT_LOCK,
+        LLSC_TRT_SET,
+        LLSC_XRAM_REQ,
+      };
+
+      /* States of the CLEANUP fsm */
+      enum cleanup_fsm_state_e{
+        CLEANUP_IDLE,
+        CLEANUP_DIR_LOCK,
+        CLEANUP_DIR_WRITE,
+        CLEANUP_HEAP_LOCK,
+        CLEANUP_HEAP_SEARCH,
+        CLEANUP_HEAP_CLEAN,
+        CLEANUP_HEAP_FREE,
+        CLEANUP_UPT_LOCK,
+        CLEANUP_UPT_WRITE,
+        CLEANUP_WRITE_RSP,
+        CLEANUP_RSP,
+      };
+
+      /* States of the ALLOC_DIR fsm */
+      enum alloc_dir_fsm_state_e{
+        ALLOC_DIR_READ,
+        ALLOC_DIR_WRITE,
+        ALLOC_DIR_LLSC,
+        ALLOC_DIR_CLEANUP,
+        ALLOC_DIR_XRAM_RSP,
+      };
+
+      /* States of the ALLOC_TRT fsm */
+      enum alloc_trt_fsm_state_e{
+        ALLOC_TRT_READ,
+        ALLOC_TRT_WRITE,
+        ALLOC_TRT_LLSC,
+        ALLOC_TRT_XRAM_RSP,
+        ALLOC_TRT_IXR_RSP,
+      };
+
+      /* States of the ALLOC_UPT fsm */
+      enum alloc_upt_fsm_state_e{
+        ALLOC_UPT_WRITE,
+        ALLOC_UPT_XRAM_RSP,
+        ALLOC_UPT_INIT_RSP,
+        ALLOC_UPT_CLEANUP,
+        ALLOC_UPT_LLSC,
+      };
+
+      /* States of the ALLOC_HEAP fsm */
+      enum alloc_heap_fsm_state_e{
+        ALLOC_HEAP_READ,
+        ALLOC_HEAP_WRITE,
+        ALLOC_HEAP_LLSC,
+        ALLOC_HEAP_CLEANUP,
+        ALLOC_HEAP_XRAM_RSP,
+      };
+
+      uint32_t	   m_cpt_cycles;            // Counter of cycles 
+      uint32_t	   m_cpt_read;              // Number of READ transactions
+      uint32_t	   m_cpt_read_miss;         // Number of MISS READ 
+      uint32_t	   m_cpt_write;             // Number of WRITE transactions
+      uint32_t	   m_cpt_write_miss;        // Number of MISS WRITE
+      uint32_t     m_cpt_write_cells;	    // Cumulated length for WRITE transactions
+      uint32_t     m_cpt_write_dirty;	    // Cumulated length for WRITE transactions
+      uint32_t	   m_cpt_update;            // Number of UPDATE transactions
+      uint32_t	   m_cpt_update_mult;       // Number of targets for UPDATE
+      uint32_t	   m_cpt_inval;             // Number of INVAL  transactions
+      uint32_t	   m_cpt_inval_mult;        // Number of targets for INVAL  
+      uint32_t	   m_cpt_inval_brdcast;     // Number of BROADCAST INVAL  
+      uint32_t	   m_cpt_cleanup;           // Number of CLEANUP transactions
+      uint32_t	   m_cpt_ll;                // Number of LL transactions
+      uint32_t	   m_cpt_sc;                // Number of SC transactions
+
+      protected:
+
+      SC_HAS_PROCESS(VciMemCacheV3);
+
+      public:
+      sc_in<bool> 			  	p_clk;
+      sc_in<bool> 			  	p_resetn;
+      soclib::caba::VciTarget<vci_param>    	p_vci_tgt;
+      soclib::caba::VciTarget<vci_param>    	p_vci_tgt_cleanup;
+      soclib::caba::VciInitiator<vci_param> 	p_vci_ini;	
+      soclib::caba::VciInitiator<vci_param> 	p_vci_ixr;
+
+      VciMemCacheV3(
+          sc_module_name name,                              // Instance Name 
+          const soclib::common::MappingTable &mtp,          // Mapping table for primary requets
+          const soclib::common::MappingTable &mtc,          // Mapping table for coherence requets
+          const soclib::common::MappingTable &mtx,          // Mapping table for XRAM
+          const soclib::common::IntTab &vci_ixr_index,      // VCI port to XRAM (initiator)
+          const soclib::common::IntTab &vci_ini_index,      // VCI port to PROC (initiator)
+          const soclib::common::IntTab &vci_tgt_index,      // VCI port to PROC (target)
+          const soclib::common::IntTab &vci_tgt_index_cleanup,    // VCI port to PROC (target) for cleanup
+          size_t nways,                                     // Number of ways per set 
+          size_t nsets,                                     // Number of sets
+          size_t nwords,                                    // Number of words per line
+          size_t heap_size=1024);                           // Size of the heap
+
+      ~VciMemCacheV3();
+
+      void transition();
+
+      void genMoore();
+
+      void print_stats();
+
+      private:
+
+      // Component attributes
+      const size_t              m_initiators;           // Number of initiators
+      const size_t              m_heap_size;            // Size of the heap
+      const size_t              m_ways;                 // Number of ways in a set
+      const size_t              m_sets;                 // Number of cache sets
+      const size_t              m_words;		        // Number of words in a line
+      const size_t              m_srcid_ixr;		    // Srcid for requests to XRAM 
+      const size_t              m_srcid_ini;		    // Srcid for requests to processors
+      std::list<soclib::common::Segment>  m_seglist;    // memory cached into the cache
+      std::list<soclib::common::Segment>  m_cseglist;   // coherence segment for the cache
+      vci_addr_t        		*m_coherence_table; 	// address(srcid)
+      AtomicTab                 m_atomic_tab;           // atomic access table
+      TransactionTab      		m_transaction_tab;	    // xram transaction table
+      UpdateTab                 m_update_tab;		    // pending update & invalidate 
+      CacheDirectory			m_cache_directory;	    // data cache directory
+      HeapDirectory             m_heap_directory;       // heap directory
+
+      data_t	        	       ***m_cache_data;		// data array[set][way][word]
+
+      // adress masks
+      const soclib::common::AddressMaskingTable<vci_addr_t>   m_x;
+      const soclib::common::AddressMaskingTable<vci_addr_t>   m_y;
+      const soclib::common::AddressMaskingTable<vci_addr_t>   m_z;
+      const soclib::common::AddressMaskingTable<vci_addr_t>   m_nline; 
+
+      // broadcast address
+      vci_addr_t broadcast_addr;
+
+      //////////////////////////////////////////////////
+      // Others registers
+      //////////////////////////////////////////////////
+      sc_signal<size_t>   r_copies_limit; // Limit of the number of copies for one line
+
+      //////////////////////////////////////////////////
+      // Registers controlled by the TGT_CMD fsm
+      //////////////////////////////////////////////////
+
+      // Fifo between TGT_CMD fsm and READ fsm
+      GenericFifo<uint64_t>  m_cmd_read_addr_fifo;
+      GenericFifo<size_t>    m_cmd_read_length_fifo;
+      GenericFifo<size_t>    m_cmd_read_srcid_fifo;
+      GenericFifo<size_t>    m_cmd_read_trdid_fifo;
+      GenericFifo<size_t>    m_cmd_read_pktid_fifo;
+
+      // Fifo between TGT_CMD fsm and WRITE fsm    
+      GenericFifo<uint64_t>  m_cmd_write_addr_fifo;
+      GenericFifo<bool>      m_cmd_write_eop_fifo;
+      GenericFifo<size_t>    m_cmd_write_srcid_fifo;
+      GenericFifo<size_t>    m_cmd_write_trdid_fifo;
+      GenericFifo<size_t>    m_cmd_write_pktid_fifo;
+      GenericFifo<data_t>    m_cmd_write_data_fifo;
+      GenericFifo<be_t>	     m_cmd_write_be_fifo;
+
+      // Fifo between TGT_CMD fsm and LLSC fsm
+      GenericFifo<uint64_t>  m_cmd_llsc_addr_fifo;
+      GenericFifo<bool>      m_cmd_llsc_sc_fifo;
+      GenericFifo<size_t>    m_cmd_llsc_srcid_fifo;
+      GenericFifo<size_t>    m_cmd_llsc_trdid_fifo;
+      GenericFifo<size_t>    m_cmd_llsc_pktid_fifo;
+      GenericFifo<data_t>    m_cmd_llsc_wdata_fifo;
+
+      sc_signal<int>         r_tgt_cmd_fsm;
+
+      sc_signal<size_t>	     r_index;
+      size_t nseg;
+      size_t ncseg;
+      soclib::common::Segment  **m_seg;
+      soclib::common::Segment  **m_cseg;
+      ///////////////////////////////////////////////////////
+      // Registers controlled by the READ fsm
+      ///////////////////////////////////////////////////////
+
+      sc_signal<int>         r_read_fsm;        // FSM state 
+      sc_signal<size_t>      r_read_copy;       // Srcid of the first copy
+      sc_signal<bool>        r_read_copy_inst;  // Type of the first copy
+      sc_signal<tag_t>       r_read_tag;	    // cache line tag (in directory)
+      sc_signal<bool>        r_read_is_cnt;	    // is_cnt bit (in directory)
+      sc_signal<bool>        r_read_lock;	    // lock bit (in directory)
+      sc_signal<bool>        r_read_dirty;	    // dirty bit (in directory)
+      sc_signal<bool>        r_read_inst;       // it is an instruction line
+      sc_signal<size_t>      r_read_count;      // number of copies
+      sc_signal<size_t>      r_read_ptr;        // pointer to the heap
+      sc_signal<data_t>     *r_read_data;       // data (one cache line)
+      sc_signal<size_t>      r_read_way;        // associative way (in cache)
+      sc_signal<size_t>      r_read_trt_index;  // Transaction Table index
+      sc_signal<size_t>      r_read_next_ptr;   // Next entry to point to
+      sc_signal<bool>        r_read_last_free;  // Last free entry
+
+      // Buffer between READ fsm and IXR_CMD fsm (ask a missing cache line to XRAM)   
+      sc_signal<bool>        r_read_to_ixr_cmd_req;     // valid request
+      sc_signal<addr_t>      r_read_to_ixr_cmd_nline;   // cache line index
+      sc_signal<size_t>      r_read_to_ixr_cmd_trdid;   // index in Transaction Table
+
+      // Buffer between READ fsm and TGT_RSP fsm (send a hit read response to L1 cache)
+      sc_signal<bool>	   r_read_to_tgt_rsp_req;       // valid request
+      sc_signal<size_t>	   r_read_to_tgt_rsp_srcid;	    // Transaction srcid
+      sc_signal<size_t>	   r_read_to_tgt_rsp_trdid;	    // Transaction trdid
+      sc_signal<size_t>	   r_read_to_tgt_rsp_pktid;	    // Transaction pktid
+      sc_signal<data_t>   *r_read_to_tgt_rsp_data;	    // data (one cache line)
+      sc_signal<size_t>    r_read_to_tgt_rsp_word;      // first word of the response
+      sc_signal<size_t>    r_read_to_tgt_rsp_length;    // length of the response
+
+      ///////////////////////////////////////////////////////////////
+      // Registers controlled by the WRITE fsm
+      ///////////////////////////////////////////////////////////////
+
+      sc_signal<int>       r_write_fsm;             // FSM state
+      sc_signal<addr_t>	   r_write_address;         // first word address
+      sc_signal<size_t>    r_write_word_index;      // first word index in line
+      sc_signal<size_t>    r_write_word_count;      // number of words in line
+      sc_signal<size_t>    r_write_srcid;           // transaction srcid
+      sc_signal<size_t>    r_write_trdid;           // transaction trdid
+      sc_signal<size_t>    r_write_pktid;           // transaction pktid
+      sc_signal<data_t>	  *r_write_data;            // data (one cache line)	
+      sc_signal<be_t>     *r_write_be;              // one byte enable per word
+      sc_signal<bool>      r_write_byte;            // is it a byte write
+      sc_signal<bool>      r_write_is_cnt;          // is_cnt bit (in directory)
+      sc_signal<bool>      r_write_lock;            // lock bit (in directory)
+      sc_signal<bool>      r_write_inst;            // instruction bit
+      sc_signal<tag_t>     r_write_tag;             // cache line tag (in directory)
+      sc_signal<size_t>    r_write_copy;            // first owner of the line
+      sc_signal<bool>      r_write_copy_inst;       // is this owner a ICache ?
+      sc_signal<size_t>	   r_write_count;           // number of copies
+      sc_signal<size_t>    r_write_ptr;             // pointer to the heap
+      sc_signal<size_t>    r_write_next_ptr;        // next pointer to the heap
+      sc_signal<bool>      r_write_to_dec;          // need to decrement update counter
+      sc_signal<size_t>	   r_write_way;		        // way of the line
+      sc_signal<size_t>    r_write_trt_index;	    // index in Transaction Table
+      sc_signal<size_t>    r_write_upt_index;	    // index in Update Table
+
+      // Buffer between WRITE fsm and TGT_RSP fsm (acknowledge a write command from L1)
+      sc_signal<bool>      r_write_to_tgt_rsp_req;		// valid request
+      sc_signal<size_t>    r_write_to_tgt_rsp_srcid;    // transaction srcid
+      sc_signal<size_t>    r_write_to_tgt_rsp_trdid;	// transaction trdid
+      sc_signal<size_t>    r_write_to_tgt_rsp_pktid;	// transaction pktid
+
+      // Buffer between WRITE fsm and IXR_CMD fsm (ask a missing cache line to XRAM) 
+      sc_signal<bool>	   r_write_to_ixr_cmd_req;      // valid request
+      sc_signal<bool>	   r_write_to_ixr_cmd_write;    // write request
+      sc_signal<addr_t>    r_write_to_ixr_cmd_nline; 	// cache line index
+      sc_signal<data_t>	  *r_write_to_ixr_cmd_data;	    // cache line data
+      sc_signal<size_t>    r_write_to_ixr_cmd_trdid;	// index in Transaction Table
+
+      // Buffer between WRITE fsm and INIT_CMD fsm (Update/Invalidate L1 caches)
+      sc_signal<bool>	   r_write_to_init_cmd_multi_req;   // valid multicast request
+      sc_signal<bool>	   r_write_to_init_cmd_brdcast_req; // valid brdcast request
+      sc_signal<addr_t>	   r_write_to_init_cmd_nline;	    // cache line index
+      sc_signal<size_t>	   r_write_to_init_cmd_trdid;	    // index in Update Table
+      sc_signal<data_t>   *r_write_to_init_cmd_data;	    // data (one cache line)
+      sc_signal<bool>     *r_write_to_init_cmd_we;	        // word enable
+      sc_signal<size_t>	   r_write_to_init_cmd_count;	    // number of words in line
+      sc_signal<size_t>	   r_write_to_init_cmd_index;	    // index of first word in line
+      GenericFifo<bool>    m_write_to_init_cmd_inst_fifo;   // fifo for the L1 type
+      GenericFifo<size_t>  m_write_to_init_cmd_srcid_fifo;  // fifo for srcids
+
+      // Buffer between WRITE fsm and INIT_RSP fsm (Decrement UPT entry)
+      sc_signal<bool>      r_write_to_init_rsp_req;         // valid request
+      sc_signal<size_t>    r_write_to_init_rsp_upt_index;   // index in update table
+
+      /////////////////////////////////////////////////////////
+      // Registers controlled by INIT_RSP fsm
+      //////////////////////////////////////////////////////////
+
+      sc_signal<int> 	   r_init_rsp_fsm;        // FSM state
+      sc_signal<size_t>	   r_init_rsp_upt_index;  // index in the Update Table
+      sc_signal<size_t>	   r_init_rsp_srcid;	  // pending write srcid      
+      sc_signal<size_t>	   r_init_rsp_trdid;	  // pending write trdid      
+      sc_signal<size_t>	   r_init_rsp_pktid;	  // pending write pktid      
+      sc_signal<addr_t>	   r_init_rsp_nline;	  // pending write nline      
+
+      // Buffer between INIT_RSP fsm and TGT_RSP fsm (complete write/update transaction)
+      sc_signal<bool>	     r_init_rsp_to_tgt_rsp_req;   	// valid request
+      sc_signal<size_t>	   r_init_rsp_to_tgt_rsp_srcid;		// Transaction srcid
+      sc_signal<size_t>	   r_init_rsp_to_tgt_rsp_trdid;		// Transaction trdid
+      sc_signal<size_t>	   r_init_rsp_to_tgt_rsp_pktid;		// Transaction pktid
+
+      ///////////////////////////////////////////////////////
+      // Registers controlled by CLEANUP fsm
+      ///////////////////////////////////////////////////////
+
+      sc_signal<int> 	     r_cleanup_fsm;         // FSM state
+      sc_signal<size_t>      r_cleanup_srcid;       // transaction srcid
+      sc_signal<size_t>      r_cleanup_trdid;       // transaction trdid
+      sc_signal<size_t>      r_cleanup_pktid;       // transaction pktid
+      sc_signal<addr_t>      r_cleanup_nline;       // cache line index
+
+      sc_signal<copy_t>      r_cleanup_copy;        // first copy
+      sc_signal<size_t>      r_cleanup_copy_inst;   // type of the first copy
+      sc_signal<copy_t>      r_cleanup_count;       // number of copies 
+      sc_signal<size_t>      r_cleanup_ptr;         // pointer to the heap
+      sc_signal<size_t>      r_cleanup_prev_ptr;    // previous pointer to the heap
+      sc_signal<size_t>      r_cleanup_prev_srcid;  // srcid of previous heap entry
+      sc_signal<bool>        r_cleanup_prev_inst;   // inst bit of previous heap entry
+      sc_signal<size_t>      r_cleanup_next_ptr;    // next pointer to the heap
+      sc_signal<tag_t>       r_cleanup_tag;	        // cache line tag (in directory)
+      sc_signal<bool>        r_cleanup_is_cnt;      // inst bit (in directory)
+      sc_signal<bool>        r_cleanup_lock;	    // lock bit (in directory)
+      sc_signal<bool>        r_cleanup_inst;	    // inst bit (in directory)
+      sc_signal<bool>        r_cleanup_dirty;	    // dirty bit (in directory)
+      sc_signal<size_t>      r_cleanup_way;	        // associative way (in cache)
+
+      sc_signal<size_t>      r_cleanup_write_srcid; // srcid of write response
+      sc_signal<size_t>      r_cleanup_write_trdid; // trdid of write rsp
+      sc_signal<size_t>      r_cleanup_write_pktid; // pktid of write rsp
+      sc_signal<bool>        r_cleanup_need_rsp;    // needs a write rsp
+
+      sc_signal<size_t>      r_cleanup_index;	    // index of the INVAL line (in the UPT)
+
+      // Buffer between CLEANUP fsm and TGT_RSP fsm (acknowledge a write command from L1)
+      sc_signal<bool>      r_cleanup_to_tgt_rsp_req;    // valid request
+      sc_signal<size_t>    r_cleanup_to_tgt_rsp_srcid;  // transaction srcid
+      sc_signal<size_t>    r_cleanup_to_tgt_rsp_trdid;	// transaction trdid
+      sc_signal<size_t>    r_cleanup_to_tgt_rsp_pktid;	// transaction pktid
+
+      ///////////////////////////////////////////////////////
+      // Registers controlled by LLSC fsm
+      ///////////////////////////////////////////////////////
+
+      sc_signal<int>       r_llsc_fsm;          // FSM state
+      sc_signal<data_t>	   r_llsc_data;		    // read data word
+      sc_signal<copy_t>    r_llsc_copy; 	    // Srcid of the first copy
+      sc_signal<bool>      r_llsc_copy_inst;	// Type of the first copy
+      sc_signal<size_t>    r_llsc_count;	    // number of copies
+      sc_signal<size_t>    r_llsc_ptr;  	    // pointer to the heap
+      sc_signal<size_t>    r_llsc_next_ptr;  	// next pointer to the heap
+      sc_signal<bool>      r_llsc_is_cnt;	    // is_cnt bit (in directory)
+      sc_signal<bool>      r_llsc_dirty;	    // dirty bit (in directory)
+      sc_signal<bool>      r_llsc_inst;         // inst bit
+      sc_signal<size_t>    r_llsc_way;		    // way in directory
+      sc_signal<size_t>    r_llsc_set;		    // set in directory
+      sc_signal<data_t>    r_llsc_tag;		    // cache line tag (in directory)
+      sc_signal<size_t>    r_llsc_trt_index;    // Transaction Table index
+      sc_signal<size_t>    r_llsc_upt_index;    // Update Table index
+
+      // Buffer between LLSC fsm and INIT_CMD fsm (XRAM read)	
+      sc_signal<bool>	   r_llsc_to_ixr_cmd_req;   // valid request
+      sc_signal<addr_t>	   r_llsc_to_ixr_cmd_nline; // cache line index
+      sc_signal<size_t>	   r_llsc_to_ixr_cmd_trdid; // index in Transaction Table
+      sc_signal<bool>	   r_llsc_to_ixr_cmd_write; // write request
+      sc_signal<data_t>	  *r_llsc_to_ixr_cmd_data;  // cache line data
+
+
+      // Buffer between LLSC fsm and TGT_RSP fsm
+      sc_signal<bool>	   r_llsc_to_tgt_rsp_req;   // valid request
+      sc_signal<data_t>    r_llsc_to_tgt_rsp_data;  // read data word
+      sc_signal<size_t>	   r_llsc_to_tgt_rsp_srcid; // Transaction srcid
+      sc_signal<size_t>	   r_llsc_to_tgt_rsp_trdid; // Transaction trdid
+      sc_signal<size_t>	   r_llsc_to_tgt_rsp_pktid; // Transaction pktid
+
+      // Buffer between LLSC fsm and INIT_CMD fsm (Update/Invalidate L1 caches)
+      sc_signal<bool>	   r_llsc_to_init_cmd_multi_req;    // valid request
+      sc_signal<bool>	   r_llsc_to_init_cmd_brdcast_req;  // brdcast request
+      sc_signal<addr_t>	   r_llsc_to_init_cmd_nline;	    // cache line index
+      sc_signal<size_t>	   r_llsc_to_init_cmd_trdid;	    // index in Update Table
+      sc_signal<data_t>    r_llsc_to_init_cmd_wdata;        // data (one word)
+      sc_signal<size_t>	   r_llsc_to_init_cmd_index;	    // index of the word in line
+      GenericFifo<bool>    m_llsc_to_init_cmd_inst_fifo;    // fifo for the L1 type
+      GenericFifo<size_t>  m_llsc_to_init_cmd_srcid_fifo;   // fifo for srcids
+
+      // Buffer between LLSC fsm and INIT_RSP fsm (Decrement UPT entry)
+      sc_signal<bool>      r_llsc_to_init_rsp_req;          // valid request
+      sc_signal<size_t>    r_llsc_to_init_rsp_upt_index;    // index in update table
+
+      ////////////////////////////////////////////////////
+      // Registers controlled by the IXR_RSP fsm
+      ////////////////////////////////////////////////////
+
+      sc_signal<int> 	   r_ixr_rsp_fsm;       // FSM state
+      sc_signal<size_t>	   r_ixr_rsp_trt_index;	// TRT entry index
+      sc_signal<size_t>    r_ixr_rsp_cpt;	    // word counter
+
+      // Buffer between IXR_RSP fsm and XRAM_RSP fsm  (response from the XRAM)
+      sc_signal<bool>	  *r_ixr_rsp_to_xram_rsp_rok;	// A xram response is ready
+
+      ////////////////////////////////////////////////////
+      // Registers controlled by the XRAM_RSP fsm
+      ////////////////////////////////////////////////////
+
+      sc_signal<int> 	   r_xram_rsp_fsm;		        // FSM state
+      sc_signal<size_t>	   r_xram_rsp_trt_index;	    // TRT entry index
+      TransactionTabEntry  r_xram_rsp_trt_buf;		    // TRT entry local buffer
+      sc_signal<bool>	   r_xram_rsp_victim_inval;	    // victim line invalidate 
+      sc_signal<bool>	   r_xram_rsp_victim_is_cnt;    // victim line inst bit
+      sc_signal<bool>	   r_xram_rsp_victim_dirty;	    // victim line dirty bit
+      sc_signal<size_t>    r_xram_rsp_victim_way;	    // victim line way
+      sc_signal<size_t>    r_xram_rsp_victim_set;	    // victim line set
+      sc_signal<addr_t>    r_xram_rsp_victim_nline;     // victim line index
+      sc_signal<copy_t>    r_xram_rsp_victim_copy;  	// victim line first copy
+      sc_signal<bool>      r_xram_rsp_victim_copy_inst;	// victim line type of first copy
+      sc_signal<size_t>    r_xram_rsp_victim_count;	    // victim line number of copies
+      sc_signal<size_t>    r_xram_rsp_victim_ptr;       // victim line pointer to the heap
+      sc_signal<data_t>	  *r_xram_rsp_victim_data;	    // victim line data
+      sc_signal<size_t>	   r_xram_rsp_upt_index;	    // UPT entry index
+      sc_signal<size_t>    r_xram_rsp_next_ptr;         // Next pointer to the heap
+
+      // Buffer between XRAM_RSP fsm and TGT_RSP fsm  (response to L1 cache)
+      sc_signal<bool>	   r_xram_rsp_to_tgt_rsp_req;	// Valid request
+      sc_signal<size_t>    r_xram_rsp_to_tgt_rsp_srcid;	// Transaction srcid
+      sc_signal<size_t>    r_xram_rsp_to_tgt_rsp_trdid;	// Transaction trdid
+      sc_signal<size_t>    r_xram_rsp_to_tgt_rsp_pktid;	// Transaction pktid
+      sc_signal<data_t>   *r_xram_rsp_to_tgt_rsp_data;	// data (one cache line)
+      sc_signal<size_t>    r_xram_rsp_to_tgt_rsp_word;  // first word index
+      sc_signal<size_t>    r_xram_rsp_to_tgt_rsp_length;// length of the response
+
+      // Buffer between XRAM_RSP fsm and INIT_CMD fsm (Inval L1 Caches) 
+      sc_signal<bool>	    r_xram_rsp_to_init_cmd_multi_req;       // Valid request
+      sc_signal<bool>       r_xram_rsp_to_init_cmd_brdcast_req;     // Broadcast request
+      sc_signal<addr_t>     r_xram_rsp_to_init_cmd_nline;           // cache line index;
+      sc_signal<size_t>	    r_xram_rsp_to_init_cmd_trdid;           // index of UPT entry
+      GenericFifo<bool>     m_xram_rsp_to_init_cmd_inst_fifo;       // fifo for the L1 type
+      GenericFifo<size_t>   m_xram_rsp_to_init_cmd_srcid_fifo;      // fifo for srcids
+
+      // Buffer between XRAM_RSP fsm and IXR_CMD fsm (XRAM write)
+      sc_signal<bool>	   r_xram_rsp_to_ixr_cmd_req;	// Valid request
+      sc_signal<addr_t>	   r_xram_rsp_to_ixr_cmd_nline;	// cache line index
+      sc_signal<data_t>	  *r_xram_rsp_to_ixr_cmd_data;	// cache line data
+      sc_signal<size_t>	   r_xram_rsp_to_ixr_cmd_trdid;	// index in transaction table
+
+      ////////////////////////////////////////////////////
+      // Registers controlled by the IXR_CMD fsm
+      ////////////////////////////////////////////////////
+
+      sc_signal<int> 	   r_ixr_cmd_fsm;
+      sc_signal<size_t>	   r_ixr_cmd_cpt;
+
+      ////////////////////////////////////////////////////
+      // Registers controlled by TGT_RSP fsm
+      ////////////////////////////////////////////////////
+
+      sc_signal<int> 	   r_tgt_rsp_fsm;
+      sc_signal<size_t>    r_tgt_rsp_cpt;
+
+      ////////////////////////////////////////////////////
+      // Registers controlled by INIT_CMD fsm
+      ////////////////////////////////////////////////////
+
+      sc_signal<int> 	  r_init_cmd_fsm;
+      sc_signal<size_t>   r_init_cmd_cpt;
+      sc_signal<bool>     r_init_cmd_inst;
+
+      ////////////////////////////////////////////////////
+      // Registers controlled by ALLOC_DIR fsm
+      ////////////////////////////////////////////////////
+
+      sc_signal<int> 		r_alloc_dir_fsm;
+
+      ////////////////////////////////////////////////////
+      // Registers controlled by ALLOC_TRT fsm
+      ////////////////////////////////////////////////////
+
+      sc_signal<int> 		r_alloc_trt_fsm;
+
+      ////////////////////////////////////////////////////
+      // Registers controlled by ALLOC_UPT fsm
+      ////////////////////////////////////////////////////
+
+      sc_signal<int> 		r_alloc_upt_fsm;
+
+      ////////////////////////////////////////////////////
+      // Registers controlled by ALLOC_HEAP fsm
+      ////////////////////////////////////////////////////
+
+      sc_signal<int> 		r_alloc_heap_fsm;
+
+    }; // end class VciMemCacheV3
+
+}}
+
+#endif
+
+// Local Variables:
+// tab-width: 4
+// c-basic-offset: 4
+// c-file-offsets:((innamespace . 0)(inline-open . 0))
+// indent-tabs-mode: nil
+// End:
+
+// vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4
+
Index: branches/v4/modules/vci_mem_cache_v3/caba/source/include/xram_transaction_v3.h
===================================================================
--- branches/v4/modules/vci_mem_cache_v3/caba/source/include/xram_transaction_v3.h	(revision 371)
+++ branches/v4/modules/vci_mem_cache_v3/caba/source/include/xram_transaction_v3.h	(revision 371)
@@ -0,0 +1,404 @@
+#ifndef XRAM_TRANSACTION_V3_H_
+#define XRAM_TRANSACTION_V3_H_
+ 
+#include <inttypes.h>
+#include <systemc>
+#include <cassert>
+#include "arithmetics.h"
+
+#define DEBUG_XRAM_TRANSACTION 0
+
+////////////////////////////////////////////////////////////////////////
+//                  A transaction tab entry         
+////////////////////////////////////////////////////////////////////////
+
+class TransactionTabEntry {
+  typedef uint32_t size_t;
+  typedef uint32_t data_t;
+  typedef sc_dt::sc_uint<40> addr_t;
+  typedef uint32_t be_t;
+
+ public:
+  bool 		      valid;     	    // entry valid 
+  bool 		      xram_read; 	    // read request to XRAM
+  addr_t   	      nline;    	    // index (zy) of the requested line
+  size_t 	      srcid;     	    // processor requesting the transaction
+  size_t 	      trdid;     	    // processor requesting the transaction
+  size_t 	      pktid;     	    // processor requesting the transaction
+  bool 		      proc_read;	    // read request from processor
+  size_t 		  read_length;      // length of the read (for the response)
+  size_t 	      word_index;    	// index of the first read word (for the response)
+  std::vector<data_t> wdata;        // write buffer (one cache line)
+  std::vector<be_t>   wdata_be;    	// be for each data in the write buffer
+
+  /////////////////////////////////////////////////////////////////////
+  // The init() function initializes the entry 
+  /////////////////////////////////////////////////////////////////////
+  void init()
+  {
+    valid		= false;
+  }
+
+  /////////////////////////////////////////////////////////////////////
+  // The alloc() function initializes the vectors of an entry
+  // Its arguments are :
+  // - n_words : number of words per line in the cache
+  /////////////////////////////////////////////////////////////////////
+  void alloc(size_t n_words)
+  {
+    wdata_be.reserve( (int)n_words );
+    wdata.reserve( (int)n_words );
+    for(size_t i=0; i<n_words; i++){
+      wdata_be.push_back(false);
+      wdata.push_back(0);
+    }
+  }
+
+  ////////////////////////////////////////////////////////////////////
+  // The copy() function copies an existing entry
+  // Its arguments are :
+  // - source : the transaction tab entry to copy
+  ////////////////////////////////////////////////////////////////////
+  void copy(const TransactionTabEntry &source)
+  {
+    valid	    = source.valid;
+    xram_read 	= source.xram_read;
+    nline	    = source.nline;
+    srcid	    = source.srcid;
+    trdid	    = source.trdid;
+    pktid	    = source.pktid;
+    proc_read 	= source.proc_read;
+    read_length = source.read_length;
+    word_index	= source.word_index;
+    wdata_be.assign(source.wdata_be.begin(),source.wdata_be.end());
+    wdata.assign(source.wdata.begin(),source.wdata.end());	
+  }
+
+  ////////////////////////////////////////////////////////////////////
+  // The print() function prints the entry 
+  ////////////////////////////////////////////////////////////////////
+  void print(){
+    std::cout << "valid       = " << valid        << std::endl;
+    std::cout << "xram_read   = " << xram_read    << std::endl;
+    std::cout << "nline       = " << std::hex << nline << std::endl;
+    std::cout << "srcid       = " << srcid        << std::endl;
+    std::cout << "trdid       = " << trdid        << std::endl;
+    std::cout << "pktid       = " << pktid        << std::endl;
+    std::cout << "proc_read   = " << proc_read    << std::endl;
+    std::cout << "read_length = " << read_length  << std::endl;
+    std::cout << "word_index  = " << word_index   << std::endl; 
+    for(size_t i=0; i<wdata_be.size() ; i++){
+      std::cout << "wdata_be [" << i <<"] = " << wdata_be[i] << std::endl;
+    }
+    for(size_t i=0; i<wdata.size() ; i++){
+      std::cout << "wdata [" << i <<"] = " << wdata[i] << std::endl;
+    }
+    std::cout << std::endl;
+  }
+
+  /////////////////////////////////////////////////////////////////////
+  // 		Constructors
+  /////////////////////////////////////////////////////////////////////
+
+  TransactionTabEntry()
+    {
+      wdata_be.clear();
+      wdata.clear();
+      valid=false;
+    }
+
+  TransactionTabEntry(const TransactionTabEntry &source){
+    valid	    = source.valid;
+    xram_read	= source.xram_read;
+    nline	    = source.nline;
+    srcid	    = source.srcid;
+    trdid	    = source.trdid;
+    pktid	    = source.pktid;
+    proc_read	= source.proc_read;
+    read_length = source.read_length;
+    word_index	= source.word_index;
+    wdata_be.assign(source.wdata_be.begin(),source.wdata_be.end());
+    wdata.assign(source.wdata.begin(),source.wdata.end());	
+  }
+
+}; // end class TransactionTabEntry
+
+////////////////////////////////////////////////////////////////////////
+//                  The transaction tab                              
+////////////////////////////////////////////////////////////////////////
+class TransactionTab{
+  typedef uint32_t size_t;
+  typedef uint32_t data_t;
+  typedef sc_dt::sc_uint<40> addr_t;
+  typedef uint32_t be_t;
+
+ private:
+  size_t size_tab;                // The size of the tab
+
+  data_t be_to_mask(be_t be)
+  {
+    data_t ret = 0;
+    if ( be&0x1 ) {
+      ret = ret | 0x000000FF;
+    }
+    if ( be&0x2 ) {
+      ret = ret | 0x0000FF00;
+    }
+    if ( be&0x4 ) {
+      ret = ret | 0x00FF0000;
+    }
+    if ( be&0x8 ) {
+      ret = ret | 0xFF000000;
+    }
+    return ret;
+  }
+
+ public:
+  TransactionTabEntry *tab;       // The transaction tab
+
+  ////////////////////////////////////////////////////////////////////
+  //		Constructors
+  ////////////////////////////////////////////////////////////////////
+  TransactionTab()
+    {
+      size_tab=0;
+      tab=NULL;
+    }
+
+  TransactionTab(size_t n_entries, size_t n_words)
+    {
+      size_tab = n_entries;
+      tab = new TransactionTabEntry[size_tab];
+      for ( size_t i=0; i<size_tab; i++) {
+	tab[i].alloc(n_words);
+      }
+    }
+
+  ~TransactionTab()
+    {
+      delete [] tab;
+    }
+
+  /////////////////////////////////////////////////////////////////////
+  // The size() function returns the size of the tab
+  /////////////////////////////////////////////////////////////////////
+  size_t size()
+  {
+    return size_tab;
+  }
+
+  /////////////////////////////////////////////////////////////////////
+  // The init() function initializes the transaction tab entries
+  /////////////////////////////////////////////////////////////////////
+  void init()
+  {
+    for ( size_t i=0; i<size_tab; i++) {
+      tab[i].init();
+    }
+  }
+
+  /////////////////////////////////////////////////////////////////////
+  // The print() function prints a transaction tab entry
+  // Arguments :
+  // - index : the index of the entry to print
+  /////////////////////////////////////////////////////////////////////
+  void print(const size_t index)
+  {
+    assert( (index < size_tab) 
+	    && "Invalid Transaction Tab Entry");
+    tab[index].print();
+    return;
+  }
+
+  /////////////////////////////////////////////////////////////////////
+  // The read() function returns a transaction tab entry.
+  // Arguments :
+  // - index : the index of the entry to read
+  /////////////////////////////////////////////////////////////////////
+  TransactionTabEntry read(const size_t index)
+  {
+    assert( (index < size_tab) 
+	    && "Invalid Transaction Tab Entry");
+    return tab[index];
+  }
+
+  /////////////////////////////////////////////////////////////////////
+  // The full() function returns the state of the transaction tab
+  // Arguments :
+  // - index : (return argument) the index of an empty entry 
+  // The function returns true if the transaction tab is full
+  /////////////////////////////////////////////////////////////////////
+  bool full(size_t &index)
+  {
+    for(size_t i=0; i<size_tab; i++){
+      if(!tab[i].valid){
+	    index=i;
+	    return false;	
+      }
+    }
+    return true;
+  }
+
+  /////////////////////////////////////////////////////////////////////
+  // The hit_read() function checks if an XRAM read transaction exists 
+  // for a given cache line.
+  // Arguments :
+  // - index : (return argument) the index of the hit entry, if there is 
+  // - nline : the index (zy) of the requested line
+  // The function returns true if a read request has already been sent
+  //////////////////////////////////////////////////////////////////////
+  bool hit_read(const addr_t nline,size_t &index)
+  {
+    for(size_t i=0; i<size_tab; i++){
+      if((tab[i].valid && (nline==tab[i].nline)) && (tab[i].xram_read)) {
+	    index=i;
+	    return true;	
+      }
+    }
+    return false;
+  }
+
+  ///////////////////////////////////////////////////////////////////////
+  // The hit_write() function looks if an XRAM write transaction exists 
+  // for a given line.
+  // Arguments :
+  // - nline : the index (zy) of the requested line
+  // The function returns true if a write request has already been sent
+  ///////////////////////////////////////////////////////////////////////
+  bool hit_write(const addr_t nline)
+  {
+    for(size_t i=0; i<size_tab; i++){
+      if(tab[i].valid && (nline==tab[i].nline) && !(tab[i].xram_read)) {
+	    return true;	
+      }
+    }
+    return false;
+  }
+
+  /////////////////////////////////////////////////////////////////////
+  // The write_data_mask() function writes a vector of data (a line).
+  // The data is written only if the corresponding bits are set
+  // in the be vector. 
+  // Arguments :
+  // - index : the index of the request in the transaction tab
+  // - be   : vector of be 
+  // - data : vector of data
+  /////////////////////////////////////////////////////////////////////
+  void write_data_mask(const size_t index, 
+		       const std::vector<be_t> &be, 
+		       const std::vector<data_t> &data) 
+  {
+    assert( (index < size_tab) 
+	    && "Invalid Transaction Tab Entry");
+    assert(be.size()==tab[index].wdata_be.size() 
+	   && "Bad data mask in write_data_mask in TransactionTab");
+    assert(data.size()==tab[index].wdata.size() 
+	   && "Bad data in write_data_mask in TransactionTab");
+
+    for(size_t i=0; i<tab[index].wdata_be.size() ; i++) {
+      tab[index].wdata_be[i] = tab[index].wdata_be[i] | be[i];
+      data_t mask = be_to_mask(be[i]);
+      tab[index].wdata[i] = (tab[index].wdata[i] & ~mask) | (data[i] & mask);
+    }
+  }
+
+  /////////////////////////////////////////////////////////////////////
+  // The set() function registers a transaction (read or write)
+  // to the XRAM in the transaction tab.
+  // Arguments :
+  // - index : index in the transaction tab
+  // - xram_read : transaction type (read or write a cache line)
+  // - nline : the index (zy) of the cache line
+  // - srcid : srcid of the initiator that caused the transaction
+  // - trdid : trdid of the initiator that caused the transaction
+  // - pktid : pktid of the initiator that caused the transaction
+  // - proc_read : does the initiator want a copy
+  // - read_length : length of read (in case of processor read)
+  // - word_index : index in the line (in case of single word read)
+  // - data : the data to write (in case of write)
+  // - data_be : the mask of the data to write (in case of write)
+  /////////////////////////////////////////////////////////////////////
+  void set(const size_t index,
+	   const bool xram_read,
+	   const addr_t nline,
+	   const size_t srcid,
+	   const size_t trdid,
+	   const size_t pktid,
+	   const bool proc_read,
+	   const size_t read_length,
+	   const size_t word_index,
+	   const std::vector<be_t> &data_be,
+	   const std::vector<data_t> &data) 
+  {
+    assert( (index < size_tab) 
+	    && "The selected entry is out of range in set() Transaction Tab");
+    assert(data_be.size()==tab[index].wdata_be.size() 
+	   && "Bad data_be argument in set() TransactionTab");
+    assert(data.size()==tab[index].wdata.size() 
+	   && "Bad data argument in set() TransactionTab");
+
+    tab[index].valid	        = true;
+    tab[index].xram_read        = xram_read;
+    tab[index].nline	        = nline;
+    tab[index].srcid	        = srcid;
+    tab[index].trdid	        = trdid;
+    tab[index].pktid	        = pktid;
+    tab[index].proc_read	    = proc_read;
+    tab[index].read_length	    = read_length;
+    tab[index].word_index	    = word_index;
+    for(size_t i=0; i<tab[index].wdata.size(); i++) {
+      tab[index].wdata_be[i]    = data_be[i];
+      tab[index].wdata[i]       = data[i];
+    }
+  }
+
+  /////////////////////////////////////////////////////////////////////
+  // The write_rsp() function writes a word of the response to an 
+  // XRAM read transaction.
+  // The data is only written when the corresponding BE field is Ox0.
+  // Arguments :
+  // - index : the index of the transaction in the transaction tab
+  // - word_index : the index of the data in the line
+  // - data : the data to write
+  /////////////////////////////////////////////////////////////////////
+  void write_rsp(const size_t index,
+		 const size_t word,
+		 const data_t data)
+  {
+    assert( (index < size_tab) 
+	    && "Selected entry  out of range in write_rsp() Transaction Tab");
+    assert( (word <= tab[index].wdata_be.size()) 
+	    && "Bad word_index in write_rsp() in TransactionTab");
+    assert( tab[index].valid 
+	    && "Transaction Tab Entry invalid in write_rsp()");
+    assert( tab[index].xram_read 
+	    && "Selected entry is not an XRAM read transaction in write_rsp()");
+
+    data_t mask = be_to_mask(tab[index].wdata_be[word]);
+    tab[index].wdata[word] = (tab[index].wdata[word] & mask) | (data & ~mask);
+  }
+
+  /////////////////////////////////////////////////////////////////////
+  // The erase() function erases an entry in the transaction tab.
+  // Arguments :
+  // - index : the index of the request in the transaction tab
+  /////////////////////////////////////////////////////////////////////
+  void erase(const size_t index)
+  {
+    assert( (index < size_tab) 
+	    && "The selected entry is out of range in erase() Transaction Tab");
+    tab[index].valid	= false;
+  }
+}; // end class TransactionTab
+
+#endif
+
+// Local Variables:
+// tab-width: 4
+// c-basic-offset: 4
+// c-file-offsets:((innamespace . 0)(inline-open . 0))
+// indent-tabs-mode: nil
+// End:
+
+// vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4
+
Index: branches/v4/modules/vci_mem_cache_v3/caba/source/src/vci_mem_cache_v3.cpp
===================================================================
--- branches/v4/modules/vci_mem_cache_v3/caba/source/src/vci_mem_cache_v3.cpp	(revision 371)
+++ branches/v4/modules/vci_mem_cache_v3/caba/source/src/vci_mem_cache_v3.cpp	(revision 371)
@@ -0,0 +1,4572 @@
+/* -*- c++ -*-
+ * File 	: vci_mem_cache_v3.cpp
+ * Date 	: 30/10/2008
+ * Copyright 	: UPMC / LIP6
+ * Authors 	: Alain Greiner / Eric Guthmuller
+ *
+ * SOCLIB_LGPL_HEADER_BEGIN
+ *
+ * This file is part of SoCLib, GNU LGPLv2.1.
+ *
+ * SoCLib is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU Lesser General Public License as published
+ * by the Free Software Foundation; version 2.1 of the License.
+ *
+ * SoCLib is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with SoCLib; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301 USA
+ *
+ * SOCLIB_LGPL_HEADER_END
+ *
+ * Maintainers: alain eric.guthmuller@polytechnique.edu
+ */
+#include "../include/vci_mem_cache_v3.h"
+
+//#define TDEBUG // Transaction tab debug
+//#define IDEBUG // Update tab debug
+//#define DDEBUG // Directory debug
+//#define DEBUG_VCI_MEM_CACHE 1
+namespace soclib { namespace caba {
+
+#ifdef DEBUG_VCI_MEM_CACHE 
+  const char *tgt_cmd_fsm_str[] = {
+    "TGT_CMD_IDLE",
+    "TGT_CMD_READ",
+    "TGT_CMD_READ_EOP",
+    "TGT_CMD_WRITE",
+    "TGT_CMD_ATOMIC",
+  };
+  const char *tgt_rsp_fsm_str[] = {
+    "TGT_RSP_READ_IDLE",
+    "TGT_RSP_WRITE_IDLE",
+    "TGT_RSP_LLSC_IDLE",
+    "TGT_RSP_XRAM_IDLE",
+    "TGT_RSP_INIT_IDLE",
+    "TGT_RSP_CLEANUP_IDLE",
+    "TGT_RSP_READ",
+    "TGT_RSP_WRITE",
+    "TGT_RSP_LLSC",
+    "TGT_RSP_XRAM",
+    "TGT_RSP_INIT",
+    "TGT_RSP_CLEANUP",
+  };
+  const char *init_cmd_fsm_str[] = {
+    "INIT_CMD_INVAL_IDLE",
+    "INIT_CMD_INVAL_NLINE",
+    "INIT_CMD_XRAM_BRDCAST",
+    "INIT_CMD_UPDT_IDLE",
+    "INIT_CMD_WRITE_BRDCAST",
+    "INIT_CMD_UPDT_NLINE",
+    "INIT_CMD_UPDT_INDEX",
+    "INIT_CMD_UPDT_DATA",
+    "INIT_CMD_SC_UPDT_IDLE",
+    "INIT_CMD_SC_BRDCAST",
+    "INIT_CMD_SC_UPDT_NLINE",
+    "INIT_CMD_SC_UPDT_INDEX",
+    "INIT_CMD_SC_UPDT_DATA",
+  };
+  const char *init_rsp_fsm_str[] = {
+    "INIT_RSP_IDLE",
+    "INIT_RSP_UPT_LOCK",
+    "INIT_RSP_UPT_CLEAR",
+    "INIT_RSP_END",
+  };
+  const char *read_fsm_str[] = {
+    "READ_IDLE",
+    "READ_DIR_LOCK",
+    "READ_DIR_HIT",
+    "READ_HEAP_LOCK",
+    "READ_HEAP_WRITE",
+    "READ_HEAP_ERASE",
+    "READ_HEAP_LAST",
+    "READ_RSP",
+    "READ_TRT_LOCK",
+    "READ_TRT_SET",
+    "READ_XRAM_REQ",
+  };
+  const char *write_fsm_str[] = {
+    "WRITE_IDLE",
+    "WRITE_NEXT",
+    "WRITE_DIR_LOCK",
+    "WRITE_DIR_HIT_READ",
+    "WRITE_DIR_HIT",
+    "WRITE_DIR_HIT_RSP",
+    "WRITE_UPT_LOCK",
+    "WRITE_HEAP_LOCK",
+    "WRITE_UPT_REQ",
+    "WRITE_UPDATE",
+    "WRITE_UPT_DEC",
+    "WRITE_RSP",
+    "WRITE_TRT_LOCK",
+    "WRITE_TRT_DATA",
+    "WRITE_TRT_SET",
+    "WRITE_WAIT",
+    "WRITE_XRAM_REQ",
+    "WRITE_TRT_WRITE_LOCK",
+    "WRITE_INVAL_LOCK",
+    "WRITE_DIR_INVAL",
+    "WRITE_INVAL",
+    "WRITE_XRAM_SEND",
+    "WRITE_HEAP_ERASE",
+    "WRITE_HEAP_LAST",
+  };
+  const char *ixr_rsp_fsm_str[] = {
+    "IXR_RSP_IDLE",
+    "IXR_RSP_ACK",
+    "IXR_RSP_TRT_ERASE",
+    "IXR_RSP_TRT_READ",
+  };
+  const char *xram_rsp_fsm_str[] = {
+    "XRAM_RSP_IDLE",
+    "XRAM_RSP_TRT_COPY",
+    "XRAM_RSP_TRT_DIRTY",
+    "XRAM_RSP_DIR_LOCK",
+    "XRAM_RSP_DIR_UPDT",
+    "XRAM_RSP_DIR_RSP",
+    "XRAM_RSP_INVAL_LOCK",
+    "XRAM_RSP_INVAL_WAIT",
+    "XRAM_RSP_INVAL",
+    "XRAM_RSP_WRITE_DIRTY",
+    "XRAM_RSP_HEAP_ERASE",
+    "XRAM_RSP_HEAP_LAST",
+  };
+  const char *ixr_cmd_fsm_str[] = {
+    "IXR_CMD_READ_IDLE",
+    "IXR_CMD_WRITE_IDLE",
+    "IXR_CMD_LLSC_IDLE",
+    "IXR_CMD_XRAM_IDLE",
+    "IXR_CMD_READ_NLINE",
+    "IXR_CMD_WRITE_NLINE",
+    "IXR_CMD_LLSC_NLINE",
+    "IXR_CMD_XRAM_DATA",
+  };
+  const char *llsc_fsm_str[] = {
+    "LLSC_IDLE",
+    "LL_DIR_LOCK",
+    "LL_DIR_HIT",
+    "LL_RSP",
+    "SC_DIR_LOCK",
+    "SC_DIR_HIT",
+    "SC_UPT_LOCK",
+    "SC_WAIT",
+    "SC_HEAP_LOCK",
+    "SC_UPT_REQ",
+    "SC_UPDATE",
+    "SC_TRT_LOCK",
+    "SC_INVAL_LOCK",
+    "SC_DIR_INVAL",
+    "SC_INVAL",
+    "SC_XRAM_SEND",
+    "SC_HEAP_ERASE",
+    "SC_HEAP_LAST",
+    "SC_RSP_FALSE",
+    "SC_RSP_TRUE",
+    "LLSC_TRT_LOCK",
+    "LLSC_TRT_SET",
+    "LLSC_XRAM_REQ",
+  };
+  const char *cleanup_fsm_str[] = {
+    "CLEANUP_IDLE",
+    "CLEANUP_DIR_LOCK",
+    "CLEANUP_DIR_WRITE",
+    "CLEANUP_HEAP_LOCK",
+    "CLEANUP_HEAP_SEARCH",
+    "CLEANUP_HEAP_CLEAN",
+    "CLEANUP_HEAP_FREE",
+    "CLEANUP_UPT_LOCK",
+    "CLEANUP_UPT_WRITE",
+    "CLEANUP_WRITE_RSP",
+    "CLEANUP_RSP",
+  };
+  const char *alloc_dir_fsm_str[] = {
+    "ALLOC_DIR_READ",
+    "ALLOC_DIR_WRITE",
+    "ALLOC_DIR_LLSC",
+    "ALLOC_DIR_CLEANUP",
+    "ALLOC_DIR_XRAM_RSP",
+  };
+  const char *alloc_trt_fsm_str[] = {
+    "ALLOC_TRT_READ",
+    "ALLOC_TRT_WRITE",
+    "ALLOC_TRT_LLSC",
+    "ALLOC_TRT_XRAM_RSP",
+    "ALLOC_TRT_IXR_RSP",
+  };
+  const char *alloc_upt_fsm_str[] = {
+    "ALLOC_UPT_WRITE",
+    "ALLOC_UPT_XRAM_RSP",
+    "ALLOC_UPT_INIT_RSP",
+    "ALLOC_UPT_CLEANUP",
+  };
+  const char *alloc_heap_fsm_str[] = {
+    "ALLOC_HEAP_READ",
+    "ALLOC_HEAP_WRITE",
+    "ALLOC_HEAP_LLSC",
+    "ALLOC_HEAP_CLEANUP",
+    "ALLOC_HEAP_XRAM_RSP",
+  };
+
+#endif
+
+#define tmpl(x) template<typename vci_param> x VciMemCacheV3<vci_param>
+
+  using soclib::common::uint32_log2;
+
+  ////////////////////////////////
+  // 	Constructor 
+  ////////////////////////////////
+
+  tmpl(/**/)::VciMemCacheV3( 
+      sc_module_name name,
+      const soclib::common::MappingTable &mtp,
+      const soclib::common::MappingTable &mtc,
+      const soclib::common::MappingTable &mtx,
+      const soclib::common::IntTab &vci_ixr_index,
+      const soclib::common::IntTab &vci_ini_index,
+      const soclib::common::IntTab &vci_tgt_index,
+      const soclib::common::IntTab &vci_tgt_index_cleanup,
+      size_t nways,
+      size_t nsets,
+      size_t nwords,
+      size_t heap_size)
+
+    : soclib::caba::BaseModule(name),
+
+    p_clk("clk"),
+    p_resetn("resetn"),
+    p_vci_tgt("vci_tgt"),
+    p_vci_tgt_cleanup("vci_tgt_cleanup"),
+    p_vci_ini("vci_ini"),
+    p_vci_ixr("vci_ixr"),
+
+    m_initiators( 1 << vci_param::S ),
+    m_heap_size( heap_size ),
+    m_ways( nways ),
+    m_sets( nsets ),
+    m_words( nwords ),
+    m_srcid_ixr( mtx.indexForId(vci_ixr_index) ),
+    m_srcid_ini( mtc.indexForId(vci_ini_index) ),
+    m_seglist(mtp.getSegmentList(vci_tgt_index)),
+    m_cseglist(mtc.getSegmentList(vci_tgt_index_cleanup)),
+    m_coherence_table( mtc.getCoherenceTable<vci_addr_t>() ),
+    m_atomic_tab( m_initiators ),
+    m_transaction_tab( TRANSACTION_TAB_LINES, nwords ),
+    m_update_tab( UPDATE_TAB_LINES ),
+    m_cache_directory( nways, nsets, nwords, vci_param::N ),
+    m_heap_directory( m_heap_size ),
+#define L2 soclib::common::uint32_log2
+    m_x( L2(m_words), 2),
+    m_y( L2(m_sets), L2(m_words) + 2),
+    m_z( vci_param::N - L2(m_sets) - L2(m_words) - 2, L2(m_sets) + L2(m_words) + 2),
+    m_nline( vci_param::N - L2(m_words) - 2, L2(m_words) + 2),
+#undef L2
+
+    //  FIFOs 
+    m_cmd_read_addr_fifo("m_cmd_read_addr_fifo", 4),
+    m_cmd_read_length_fifo("m_cmd_read_length_fifo", 4),
+    m_cmd_read_srcid_fifo("m_cmd_read_srcid_fifo", 4),
+    m_cmd_read_trdid_fifo("m_cmd_read_trdid_fifo", 4),
+    m_cmd_read_pktid_fifo("m_cmd_read_pktid_fifo", 4),
+
+    m_cmd_write_addr_fifo("m_cmd_write_addr_fifo",8),
+    m_cmd_write_eop_fifo("m_cmd_write_eop_fifo",8),
+    m_cmd_write_srcid_fifo("m_cmd_write_srcid_fifo",8),
+    m_cmd_write_trdid_fifo("m_cmd_write_trdid_fifo",8),
+    m_cmd_write_pktid_fifo("m_cmd_write_pktid_fifo",8),
+    m_cmd_write_data_fifo("m_cmd_write_data_fifo",8),
+    m_cmd_write_be_fifo("m_cmd_write_be_fifo",8),
+
+    m_cmd_llsc_addr_fifo("m_cmd_llsc_addr_fifo",4),
+    m_cmd_llsc_sc_fifo("m_cmd_llsc_sc_fifo",4),
+    m_cmd_llsc_srcid_fifo("m_cmd_llsc_srcid_fifo",4),
+    m_cmd_llsc_trdid_fifo("m_cmd_llsc_trdid_fifo",4),
+    m_cmd_llsc_pktid_fifo("m_cmd_llsc_pktid_fifo",4),
+    m_cmd_llsc_wdata_fifo("m_cmd_llsc_wdata_fifo",4),
+
+    r_tgt_cmd_fsm("r_tgt_cmd_fsm"),
+    
+    nseg(0),	
+    ncseg(0),	
+
+    r_read_fsm("r_read_fsm"),
+    r_write_fsm("r_write_fsm"),
+    m_write_to_init_cmd_inst_fifo("m_write_to_init_cmd_inst_fifo",8),
+    m_write_to_init_cmd_srcid_fifo("m_write_to_init_cmd_srcid_fifo",8),
+    r_init_rsp_fsm("r_init_rsp_fsm"),
+    r_cleanup_fsm("r_cleanup_fsm"),
+    r_llsc_fsm("r_llsc_fsm"),
+    m_llsc_to_init_cmd_inst_fifo("m_llsc_to_init_cmd_inst_fifo",8),
+    m_llsc_to_init_cmd_srcid_fifo("m_llsc_to_init_cmd_srcid_fifo",8),
+    r_ixr_rsp_fsm("r_ixr_rsp_fsm"),
+    r_xram_rsp_fsm("r_xram_rsp_fsm"),
+    m_xram_rsp_to_init_cmd_inst_fifo("m_xram_rsp_to_init_cmd_inst_fifo",8),
+    m_xram_rsp_to_init_cmd_srcid_fifo("m_xram_rsp_to_init_cmd_srcid_fifo",8),
+    r_ixr_cmd_fsm("r_ixr_cmd_fsm"),
+    r_tgt_rsp_fsm("r_tgt_rsp_fsm"),
+    r_init_cmd_fsm("r_init_cmd_fsm"),
+    r_alloc_dir_fsm("r_alloc_dir_fsm"),
+    r_alloc_trt_fsm("r_alloc_trt_fsm"),
+    r_alloc_upt_fsm("r_alloc_upt_fsm")
+    {
+      assert(IS_POW_OF_2(nsets));
+      assert(IS_POW_OF_2(nwords));
+      assert(IS_POW_OF_2(nways));
+      assert(nsets);
+      assert(nwords);
+      assert(nways);
+      assert(nsets <= 1024);
+      assert(nwords <= 32);
+      assert(nways <= 32);
+
+      // Set the broadcast address with Xmin,Xmax,Ymin,Ymax set to maximum
+      broadcast_addr = 0x3 | (0x7C1F << (vci_param::N-20));
+
+      // Get the segments associated to the MemCache 
+      std::list<soclib::common::Segment>::iterator seg;
+
+      for(seg = m_seglist.begin(); seg != m_seglist.end() ; seg++) {
+        nseg++;
+      }
+      for(seg = m_cseglist.begin(); seg != m_cseglist.end() ; seg++) {
+        ncseg++;
+      }
+
+      m_seg = new soclib::common::Segment*[nseg];
+      size_t i = 0;
+      for ( seg = m_seglist.begin() ; seg != m_seglist.end() ; seg++ ) { 
+        m_seg[i] = &(*seg);
+        i++;
+      }
+      m_cseg = new soclib::common::Segment*[ncseg];
+      i = 0;
+      for ( seg = m_cseglist.begin() ; seg != m_cseglist.end() ; seg++ ) { 
+          m_cseg[i] = &(*seg);
+          i++;
+      }
+
+      // Memory cache allocation & initialisation
+      m_cache_data = new data_t**[nways];
+      for ( size_t i=0 ; i<nways ; ++i ) {
+        m_cache_data[i] = new data_t*[nsets];
+      }
+      for ( size_t i=0; i<nways; ++i ) {
+        for ( size_t j=0; j<nsets; ++j ) {
+          m_cache_data[i][j] = new data_t[nwords];
+          for ( size_t k=0; k<nwords; k++){
+            m_cache_data[i][j][k]=0;
+          }	
+        }
+      }
+
+      // Allocation for IXR_RSP FSM
+      r_ixr_rsp_to_xram_rsp_rok	    = new sc_signal<bool>[TRANSACTION_TAB_LINES];
+
+      // Allocation for XRAM_RSP FSM
+      r_xram_rsp_victim_data        = new sc_signal<data_t>[nwords];
+      r_xram_rsp_to_tgt_rsp_data    = new sc_signal<data_t>[nwords];
+      r_xram_rsp_to_ixr_cmd_data    = new sc_signal<data_t>[nwords];
+
+      // Allocation for READ FSM
+      r_read_data 			        = new sc_signal<data_t>[nwords];
+      r_read_to_tgt_rsp_data 		= new sc_signal<data_t>[nwords];
+
+      // Allocation for WRITE FSM
+      r_write_data 			        = new sc_signal<data_t>[nwords];
+      r_write_be 			        = new sc_signal<be_t>[nwords];
+      r_write_to_init_cmd_data 		= new sc_signal<data_t>[nwords];
+      r_write_to_init_cmd_we		= new sc_signal<bool>[nwords];
+      r_write_to_ixr_cmd_data	    = new sc_signal<data_t>[nwords];
+
+      // Allocation for LLSC FSM
+      r_llsc_to_ixr_cmd_data	    = new sc_signal<data_t>[nwords];
+
+
+      // Simulation
+
+      SC_METHOD(transition);
+      dont_initialize();
+      sensitive << p_clk.pos();
+
+      SC_METHOD(genMoore);
+      dont_initialize();
+      sensitive << p_clk.neg();
+
+    } // end constructor
+
+  /////////////////////////////////////////
+  // This function prints the statistics 
+  /////////////////////////////////////////
+
+  tmpl(void)::print_stats()
+  {
+    std::cout << "----------------------------------" << std::dec << std::endl;
+    std::cout << "MEM_CACHE " << m_srcid_ini << " / Time = " << m_cpt_cycles << std::endl
+      << "- READ RATE            = " << (double)m_cpt_read/m_cpt_cycles << std::endl
+      << "- READ MISS RATE       = " << (double)m_cpt_read_miss/m_cpt_read << std::endl
+      << "- WRITE RATE           = " << (double)m_cpt_write/m_cpt_cycles << std::endl
+      << "- WRITE MISS RATE      = " << (double)m_cpt_write_miss/m_cpt_write << std::endl
+      << "- WRITE BURST LENGTH   = " << (double)m_cpt_write_cells/m_cpt_write << std::endl
+      << "- UPDATE RATE          = " << (double)m_cpt_update/m_cpt_cycles << std::endl
+      << "- UPDATE ARITY         = " << (double)m_cpt_update_mult/m_cpt_update << std::endl
+      << "- INVAL MULTICAST RATE = " << (double)(m_cpt_inval-m_cpt_inval_brdcast)/m_cpt_cycles << std::endl
+      << "- INVAL MULTICAST ARITY= " << (double)m_cpt_inval_mult/(m_cpt_inval-m_cpt_inval_brdcast) << std::endl
+      << "- INVAL BROADCAST RATE = " << (double)m_cpt_inval_brdcast/m_cpt_cycles << std::endl
+      << "- SAVE DIRTY RATE      = " << (double)m_cpt_write_dirty/m_cpt_cycles << std::endl
+      << "- CLEANUP RATE         = " << (double)m_cpt_cleanup/m_cpt_cycles << std::endl
+      << "- LL RATE              = " << (double)m_cpt_ll/m_cpt_cycles << std::endl
+      << "- SC RATE              = " << (double)m_cpt_sc/m_cpt_cycles << std::endl;
+  }
+
+  /////////////////////////////////
+  tmpl(/**/)::~VciMemCacheV3()
+    /////////////////////////////////
+  {
+    for(size_t i=0; i<m_ways ; i++){
+      for(size_t j=0; j<m_sets ; j++){
+        delete [] m_cache_data[i][j];
+      }
+    }
+    for(size_t i=0; i<m_ways ; i++){
+      delete [] m_cache_data[i];
+    }
+    delete [] m_cache_data;
+    delete [] m_coherence_table;
+
+    delete [] r_ixr_rsp_to_xram_rsp_rok;
+
+    delete [] r_xram_rsp_victim_data;
+    delete [] r_xram_rsp_to_tgt_rsp_data;
+    delete [] r_xram_rsp_to_ixr_cmd_data;
+
+    delete [] r_read_data;
+    delete [] r_read_to_tgt_rsp_data;
+
+    delete [] r_write_data;
+    delete [] r_write_be;
+    delete [] r_write_to_init_cmd_data;
+  }
+
+  //////////////////////////////////
+  tmpl(void)::transition()
+    //////////////////////////////////
+  {
+    using soclib::common::uint32_log2;
+    //  RESET          
+    if ( ! p_resetn.read() ) {
+
+      //     Initializing FSMs
+      r_tgt_cmd_fsm 	= TGT_CMD_IDLE;
+      r_tgt_rsp_fsm 	= TGT_RSP_READ_IDLE;
+      r_init_cmd_fsm 	= INIT_CMD_INVAL_IDLE;
+      r_init_rsp_fsm 	= INIT_RSP_IDLE;
+      r_read_fsm 	= READ_IDLE;
+      r_write_fsm 	= WRITE_IDLE;
+      r_llsc_fsm 	= LLSC_IDLE;
+      r_cleanup_fsm 	= CLEANUP_IDLE;
+      r_alloc_dir_fsm   = ALLOC_DIR_READ;
+      r_alloc_trt_fsm   = ALLOC_TRT_READ;
+      r_alloc_upt_fsm   = ALLOC_UPT_WRITE;
+      r_ixr_rsp_fsm 	= IXR_RSP_IDLE;
+      r_xram_rsp_fsm 	= XRAM_RSP_IDLE;
+      r_ixr_cmd_fsm 	= IXR_CMD_READ_IDLE;
+
+      //  Initializing Tables
+      m_cache_directory.init();
+      m_atomic_tab.init();	
+      m_transaction_tab.init();
+      m_heap_directory.init();
+
+      // initializing FIFOs and communication Buffers
+
+      m_cmd_read_addr_fifo.init();
+      m_cmd_read_length_fifo.init();
+      m_cmd_read_srcid_fifo.init();
+      m_cmd_read_trdid_fifo.init();
+      m_cmd_read_pktid_fifo.init();
+
+      m_cmd_write_addr_fifo.init();
+      m_cmd_write_eop_fifo.init();
+      m_cmd_write_srcid_fifo.init();
+      m_cmd_write_trdid_fifo.init();
+      m_cmd_write_pktid_fifo.init();
+      m_cmd_write_data_fifo.init();
+
+      m_cmd_llsc_addr_fifo.init();
+      m_cmd_llsc_srcid_fifo.init();
+      m_cmd_llsc_trdid_fifo.init();
+      m_cmd_llsc_pktid_fifo.init();
+      m_cmd_llsc_wdata_fifo.init();
+      m_cmd_llsc_sc_fifo.init();
+
+      r_read_to_tgt_rsp_req	    = false;
+      r_read_to_ixr_cmd_req	    = false;
+
+      r_write_to_tgt_rsp_req	        = false;
+      r_write_to_ixr_cmd_req	        = false;
+      r_write_to_init_cmd_multi_req	    = false;
+      r_write_to_init_cmd_brdcast_req	= false;
+      r_write_to_init_rsp_req           = false;
+      m_write_to_init_cmd_inst_fifo.init();
+      m_write_to_init_cmd_srcid_fifo.init();
+
+      r_cleanup_to_tgt_rsp_req	= false;
+
+      r_init_rsp_to_tgt_rsp_req	= false;
+
+      r_llsc_to_tgt_rsp_req	            = false;
+      r_llsc_to_ixr_cmd_req	            = false;
+      r_llsc_to_init_cmd_multi_req	    = false;
+      r_llsc_to_init_cmd_brdcast_req	= false;
+      m_llsc_to_init_cmd_inst_fifo.init();
+      m_llsc_to_init_cmd_srcid_fifo.init();
+
+      for(size_t i=0; i<TRANSACTION_TAB_LINES ; i++){
+        r_ixr_rsp_to_xram_rsp_rok[i] = false;
+      }
+
+      r_xram_rsp_to_tgt_rsp_req	            = false;
+      r_xram_rsp_to_init_cmd_multi_req      = false;
+      r_xram_rsp_to_init_cmd_brdcast_req    = false;
+      r_xram_rsp_to_ixr_cmd_req	            = false;
+      r_xram_rsp_trt_index	                = 0;
+      m_xram_rsp_to_init_cmd_inst_fifo.init();
+      m_xram_rsp_to_init_cmd_srcid_fifo.init();
+
+      r_ixr_cmd_cpt         = 0;
+
+      r_copies_limit        = 3;
+
+      // Activity counters
+      m_cpt_cycles		    = 0;
+      m_cpt_read		    = 0;
+      m_cpt_read_miss	    = 0;
+      m_cpt_write		    = 0;
+      m_cpt_write_miss	    = 0;
+      m_cpt_write_cells	    = 0;
+      m_cpt_write_dirty	    = 0;
+      m_cpt_update		    = 0;
+      m_cpt_update_mult     = 0;
+      m_cpt_inval_brdcast 	= 0;
+      m_cpt_inval 		    = 0;
+      m_cpt_inval_mult 		= 0;
+      m_cpt_cleanup		    = 0;
+      m_cpt_ll     		    = 0;
+      m_cpt_sc     		    = 0;
+
+      return;
+    }
+
+    bool    cmd_read_fifo_put = false;
+    bool    cmd_read_fifo_get = false;
+
+    bool    cmd_write_fifo_put = false;
+    bool    cmd_write_fifo_get = false;
+
+    bool    cmd_llsc_fifo_put = false;
+    bool    cmd_llsc_fifo_get = false;
+
+    bool    write_to_init_cmd_fifo_put   = false;
+    bool    write_to_init_cmd_fifo_get   = false;
+    bool    write_to_init_cmd_fifo_inst  = false;
+    size_t  write_to_init_cmd_fifo_srcid = 0;
+
+    bool    xram_rsp_to_init_cmd_fifo_put   = false;
+    bool    xram_rsp_to_init_cmd_fifo_get   = false;
+    bool    xram_rsp_to_init_cmd_fifo_inst  = false;
+    size_t  xram_rsp_to_init_cmd_fifo_srcid = 0;
+
+    bool    llsc_to_init_cmd_fifo_put   = false;
+    bool    llsc_to_init_cmd_fifo_get   = false;
+    bool    llsc_to_init_cmd_fifo_inst  = false;
+    size_t  llsc_to_init_cmd_fifo_srcid = 0;
+
+#if DEBUG_VCI_MEM_CACHE 
+    std::cout << "---------------------------------------------" << std::dec << std::endl;
+    std::cout << "MEM_CACHE " << m_srcid_ini << " ; Time = " << m_cpt_cycles << std::endl
+      << " - TGT_CMD FSM    = " << tgt_cmd_fsm_str[r_tgt_cmd_fsm] << std::endl
+      << " - TGT_RSP FSM    = " << tgt_rsp_fsm_str[r_tgt_rsp_fsm] << std::endl
+      << " - INIT_CMD FSM   = " << init_cmd_fsm_str[r_init_cmd_fsm] << std::endl
+      << " - INIT_RSP FSM   = " << init_rsp_fsm_str[r_init_rsp_fsm] << std::endl
+      << " - READ FSM       = " << read_fsm_str[r_read_fsm] << std::endl
+      << " - WRITE FSM      = " << write_fsm_str[r_write_fsm] << std::endl
+      << " - LLSC FSM       = " << llsc_fsm_str[r_llsc_fsm] << std::endl
+      << " - CLEANUP FSM    = " << cleanup_fsm_str[r_cleanup_fsm] << std::endl
+      << " - IXR_CMD FSM    = " << ixr_cmd_fsm_str[r_ixr_cmd_fsm] << std::endl
+      << " - IXR_RSP FSM    = " << ixr_rsp_fsm_str[r_ixr_rsp_fsm] << std::endl
+      << " - XRAM_RSP FSM   = " << xram_rsp_fsm_str[r_xram_rsp_fsm] << std::endl
+      << " - ALLOC_DIR FSM  = " << alloc_dir_fsm_str[r_alloc_dir_fsm] << std::endl
+      << " - ALLOC_TRT FSM  = " << alloc_trt_fsm_str[r_alloc_trt_fsm] << std::endl
+      << " - ALLOC_UPT FSM  = " << alloc_upt_fsm_str[r_alloc_upt_fsm] << std::endl
+      << " - ALLOC_HEAP FSM = " << alloc_heap_fsm_str[r_alloc_heap_fsm] << std::endl;
+#endif
+
+
+    ////////////////////////////////////////////////////////////////////////////////////
+    //		TGT_CMD FSM
+    ////////////////////////////////////////////////////////////////////////////////////
+    // The TGT_CMD_FSM controls the incoming VCI command pakets from the processors
+    //
+    // There is 4 types of packets for the m_mem_segment :
+    // - READ    : a READ request has a length of 1 VCI cell. It can be a single word 
+    //             or an entire cache line, depending on the PLEN value.
+    // - WRITE   : a WRITE request has a maximum length of 16 cells, and can only
+    //             concern words in a same line.
+    // - LL      : The LL request has a length of 1 cell.
+    // - SC      : The SC request has a length of 1 cell. 
+    //             The WDATA field contains the data to write.
+    //
+    ////////////////////////////////////////////////////////////////////////////////////
+
+    switch ( r_tgt_cmd_fsm.read() ) {
+
+      //////////////////
+      case TGT_CMD_IDLE:
+        {
+          if ( p_vci_tgt.cmdval ) {
+            assert( (p_vci_tgt.srcid.read() < m_initiators)
+                && "VCI_MEM_CACHE error in VCI_MEM_CACHE : The received SRCID is larger than the number of initiators");
+
+            bool reached = false;
+            for ( size_t index = 0 ; index < nseg && !reached ; index++) 
+            {
+//              if ( m_seg[index]->contains((addr_t)(p_vci_tgt.address.read())) ) {
+              if ( m_seg[index]->contains(p_vci_tgt.address.read()) ) {
+                reached = true;
+                r_index = index;
+              }
+            }
+
+
+            if ( !reached ) 
+            { 
+              std::cout << "VCI_MEM_CACHE Out of segment access in VCI_MEM_CACHE" << std::endl;
+              std::cout << "Faulty address = " << std::hex << (addr_t)(p_vci_tgt.address.read()) << std::endl;
+              std::cout << "Faulty initiator = " << std::dec << p_vci_tgt.srcid.read() << std::endl;
+              exit(0);
+            } 
+            else if ( p_vci_tgt.cmd.read() == vci_param::CMD_READ ) 
+            {
+              r_tgt_cmd_fsm = TGT_CMD_READ;
+            } 
+            else if ( p_vci_tgt.cmd.read() == vci_param::CMD_WRITE )
+            {  
+              r_tgt_cmd_fsm = TGT_CMD_WRITE;
+            } 
+            else if ((p_vci_tgt.cmd.read() == vci_param::CMD_LOCKED_READ) || 
+                (p_vci_tgt.cmd.read() == vci_param::CMD_STORE_COND) ) 
+            {
+              r_tgt_cmd_fsm = TGT_CMD_ATOMIC;
+            } 
+          }
+          break;
+        }
+        //////////////////
+      case TGT_CMD_READ:
+
+        {
+          assert(((m_x[(vci_addr_t)p_vci_tgt.address.read()]+(p_vci_tgt.plen.read()>>2))<=16)
+              && "VCI_MEM_CACHE All read request to the MemCache must stay within a cache line"); 
+
+          if ( p_vci_tgt.cmdval && m_cmd_read_addr_fifo.wok() ) {
+            cmd_read_fifo_put = true;
+            if ( p_vci_tgt.eop )  r_tgt_cmd_fsm = TGT_CMD_IDLE;
+            else                  r_tgt_cmd_fsm = TGT_CMD_READ_EOP;		
+          } 
+          break;
+        }
+        //////////////////////
+      case TGT_CMD_READ_EOP:
+        {
+          if ( p_vci_tgt.cmdval && p_vci_tgt.eop ){
+            r_tgt_cmd_fsm = TGT_CMD_IDLE;
+          }
+          break;
+        }
+        ///////////////////
+      case TGT_CMD_WRITE:
+        {
+
+          if ( p_vci_tgt.cmdval && m_cmd_write_addr_fifo.wok() ) {
+            cmd_write_fifo_put = true;
+            if(  p_vci_tgt.eop )  r_tgt_cmd_fsm = TGT_CMD_IDLE;
+
+          }
+          break;
+        }
+        ////////////////////
+      case TGT_CMD_ATOMIC:
+        {
+          assert(p_vci_tgt.eop && "Memory Cache Error: LL or SC command with length > 1 ");
+
+          if ( p_vci_tgt.cmdval && m_cmd_llsc_addr_fifo.wok() ) {
+            cmd_llsc_fifo_put = true;
+            r_tgt_cmd_fsm = TGT_CMD_IDLE;
+          }
+          break;
+        }
+    } // end switch tgt_cmd_fsm
+
+    /////////////////////////////////////////////////////////////////////////
+    //		INIT_RSP FSM
+    /////////////////////////////////////////////////////////////////////////
+    // This FSM controls the response to the update or invalidate requests
+    // sent by the memory cache to the L1 caches :
+    //
+    // - update request initiated by the WRITE FSM.  
+    //   The FSM decrements the proper entry in the Update/Inval Table.
+    //   It sends a request to the TGT_RSP FSM to complete the pending 
+    //   write transaction (acknowledge response to the writer processor), 
+    //   and clear the UPT entry when all responses have been received.  
+    // - invalidate request initiated by the XRAM_RSP FSM.
+    //   The FSM decrements the proper entry in the Update/Inval_Table,
+    //   and clear the entry when all responses have been received.
+    //
+    // All those response packets are one word, compact
+    // packets complying with the VCI advanced format. 
+    // The index in the Table is defined in the RTRDID field, and
+    // the Transaction type is defined in the Update/Inval Table.
+    /////////////////////////////////////////////////////////////////////
+
+    switch ( r_init_rsp_fsm.read() ) {
+
+      ///////////////////
+      case INIT_RSP_IDLE:
+        {
+
+          if ( p_vci_ini.rspval ) {
+
+            assert ( ( p_vci_ini.rtrdid.read() < m_update_tab.size() )
+                && "VCI_MEM_CACHE UPT index too large in VCI response paquet received by memory cache" );
+            assert ( p_vci_ini.reop 
+                && "VCI_MEM_CACHE All response packets to update/invalidate requests must be one cell" );
+            r_init_rsp_upt_index = p_vci_ini.rtrdid.read(); 
+            r_init_rsp_fsm = INIT_RSP_UPT_LOCK;
+          } else if( r_write_to_init_rsp_req.read() ){
+            r_init_rsp_upt_index = r_write_to_init_rsp_upt_index.read();
+            r_write_to_init_rsp_req = false;
+            r_init_rsp_fsm = INIT_RSP_UPT_LOCK;
+          }
+          break;
+        }
+        ///////////////////////
+      case INIT_RSP_UPT_LOCK:	// decrement the number of expected responses
+        {
+
+          if ( r_alloc_upt_fsm.read() == ALLOC_UPT_INIT_RSP ) { 
+            size_t count = 0;
+            bool valid  = m_update_tab.decrement(r_init_rsp_upt_index.read(), count);
+#ifdef IDEBUG
+	std::cout << sc_time_stamp() << " " << name() << " INIT_RSP_UPT_LOCK update table : " << std::endl;
+	m_update_tab.print();
+#endif
+            assert ( valid 
+                && "VCI_MEM_CACHE Invalid UPT entry in VCI response paquet received by memory cache" );
+
+            if ( count == 0 ) r_init_rsp_fsm = INIT_RSP_UPT_CLEAR;
+            else              r_init_rsp_fsm = INIT_RSP_IDLE;
+          }
+          break;
+        }
+        ////////////////////////
+      case INIT_RSP_UPT_CLEAR:	// clear the UPT entry
+        {
+          if ( r_alloc_upt_fsm.read() == ALLOC_UPT_INIT_RSP ) {
+            r_init_rsp_srcid = m_update_tab.srcid(r_init_rsp_upt_index.read());
+            r_init_rsp_trdid = m_update_tab.trdid(r_init_rsp_upt_index.read());
+            r_init_rsp_pktid = m_update_tab.pktid(r_init_rsp_upt_index.read());
+            r_init_rsp_nline = m_update_tab.nline(r_init_rsp_upt_index.read());
+            bool need_rsp = m_update_tab.need_rsp(r_init_rsp_upt_index.read());
+            if ( need_rsp ) r_init_rsp_fsm = INIT_RSP_END;
+            else            r_init_rsp_fsm = INIT_RSP_IDLE;
+            m_update_tab.clear(r_init_rsp_upt_index.read());
+#ifdef IDEBUG
+	std::cout << sc_time_stamp() << " " << name() << " INIT_RSP_UPT_CLEAR update table : " << std::endl;
+	m_update_tab.print();
+#endif
+          }
+          break;
+        }
+        //////////////////
+      case INIT_RSP_END:
+        {
+
+          if ( !r_init_rsp_to_tgt_rsp_req ) {
+            r_init_rsp_to_tgt_rsp_req = true;
+            r_init_rsp_to_tgt_rsp_srcid = r_init_rsp_srcid.read();
+            r_init_rsp_to_tgt_rsp_trdid = r_init_rsp_trdid.read();
+            r_init_rsp_to_tgt_rsp_pktid = r_init_rsp_pktid.read();
+            r_init_rsp_fsm = INIT_RSP_IDLE;
+          }
+          break;
+        }
+    } // end switch r_init_rsp_fsm
+
+    ////////////////////////////////////////////////////////////////////////////////////
+    //		READ FSM
+    ////////////////////////////////////////////////////////////////////////////////////
+    // The READ FSM controls the read requests sent by processors.
+    // It takes the lock protecting the cache directory to check the cache line status:
+    // - In case of HIT, the fsm copies the data (one line, or one single word)
+    //   in the r_read_to_tgt_rsp buffer. It waits if this buffer is not empty.
+    //   The requesting initiator is registered in the cache directory.
+    // - In case of MISS, the READ fsm takes the lock protecting the transaction tab.
+    //   If a read transaction to the XRAM for this line already exists,
+    //   or if the transaction tab is full, the fsm is stalled.
+    //   If a transaction entry is free, the READ fsm sends a request to the XRAM.
+    ////////////////////////////////////////////////////////////////////////////////////
+
+    switch ( r_read_fsm.read() ) {
+
+      ///////////////
+      case READ_IDLE:
+        {
+          if (m_cmd_read_addr_fifo.rok()) {
+            m_cpt_read++;
+            r_read_fsm = READ_DIR_LOCK;
+          }
+          break;
+        }
+        ///////////////////
+      case READ_DIR_LOCK:	// check directory for hit / miss
+        {
+          if( r_alloc_dir_fsm.read() == ALLOC_DIR_READ ) {
+            size_t way = 0;
+            DirectoryEntry entry = m_cache_directory.read(m_cmd_read_addr_fifo.read(), way);
+#ifdef DDEBUG
+	   std::cout << "In READ_DIR_LOCK printing the entry of address is : " << std::hex << m_cmd_read_addr_fifo.read() << std::endl;
+	   entry.print();
+	   std::cout << "done" << std::endl;
+#endif
+
+            r_read_is_cnt   = entry.is_cnt;
+            r_read_dirty    = entry.dirty;
+            r_read_lock	    = entry.lock;
+            r_read_inst     = entry.inst;
+            r_read_tag	    = entry.tag;
+            r_read_way	    = way;
+            r_read_count    = entry.count;
+            r_read_copy     = entry.owner.srcid; 
+            r_read_copy_inst= entry.owner.inst;
+            r_read_ptr      = entry.ptr;
+
+            bool cached_read = (m_cmd_read_trdid_fifo.read() & 0x1);
+            // In case of hit, the read acces must be registered in the copies bit-vector
+            if(  entry.valid ) {
+              if(entry.is_cnt || (entry.count == 0) || !cached_read)  { // No new entry in the heap
+                r_read_fsm = READ_DIR_HIT;
+              } else {
+                r_read_fsm = READ_HEAP_LOCK;
+              }
+            } else {
+              r_read_fsm = READ_TRT_LOCK;
+              m_cpt_read_miss++;
+            }
+          }
+          break;
+        }
+        //////////////////
+      case READ_DIR_HIT:	// read hit : update the memory cache
+        {
+          if( r_alloc_dir_fsm.read() == ALLOC_DIR_READ ) {
+            // signals generation
+            bool inst_read = (m_cmd_read_trdid_fifo.read() & 0x2);
+            bool cached_read = (m_cmd_read_trdid_fifo.read() & 0x1);
+            bool is_cnt = r_read_is_cnt.read();
+
+            // read data in the cache
+            size_t set = m_y[(vci_addr_t)(m_cmd_read_addr_fifo.read())];
+            size_t way = r_read_way.read();
+            for ( size_t i=0 ; i<m_words ; i++ ) {
+              r_read_data[i] = m_cache_data[way][set][i];
+            }
+
+            // update the cache directory (for the copies)
+            DirectoryEntry entry;
+            entry.valid	  = true;
+            entry.is_cnt  = is_cnt; 
+            entry.dirty	  = r_read_dirty.read();
+            entry.tag	  = r_read_tag.read();
+            entry.lock	  = r_read_lock.read();
+            entry.ptr     = r_read_ptr.read();
+            if(cached_read){  // Cached read, we update the copy
+              if(!is_cnt){ // Not counter mode
+                entry.owner.srcid   = m_cmd_read_srcid_fifo.read();
+                entry.owner.inst    = inst_read;
+                entry.inst          = r_read_inst.read() || inst_read;
+                entry.count         = r_read_count.read() + 1;
+              } else { // Counter mode
+                entry.owner.srcid   = 0;
+                entry.owner.inst    = false;
+                entry.inst          = r_read_inst.read() || inst_read;
+                entry.count         = r_read_count.read() + 1;
+              } 
+            } else { // Uncached read
+              entry.owner.srcid     = r_read_copy.read();
+              entry.owner.inst      = r_read_copy_inst.read();
+              entry.inst            = r_read_inst.read();
+              entry.count           = r_read_count.read();
+            }
+#ifdef DDEBUG
+	   std::cout << "In READ_DIR_HIT printing the entry of address is : " << std::endl;
+	   entry.print();
+	   std::cout << "done" << std::endl;
+#endif
+
+            m_cache_directory.write(set, way, entry);
+            r_read_fsm    = READ_RSP;
+          }
+          break;
+        }
+        //////////////
+      case READ_HEAP_LOCK:
+        {
+          if( r_alloc_heap_fsm.read() == ALLOC_HEAP_READ ) {
+            bool inst_read = (m_cmd_read_trdid_fifo.read() & 0x2);
+            bool is_cnt = (r_read_count.read() >= r_copies_limit.read()) || m_heap_directory.is_full();
+            // read data in the cache
+            size_t set = m_y[(vci_addr_t)(m_cmd_read_addr_fifo.read())];
+            size_t way = r_read_way.read();
+            for ( size_t i=0 ; i<m_words ; i++ ) {
+              r_read_data[i] = m_cache_data[way][set][i];
+            }
+
+            // update the cache directory (for the copies)
+            DirectoryEntry entry;
+            entry.valid	  = true;
+            entry.is_cnt  = is_cnt; // when we reach the limit of copies or the heap is full
+            entry.dirty	  = r_read_dirty.read();
+            entry.tag	  = r_read_tag.read();
+            entry.lock	  = r_read_lock.read();
+            if(!is_cnt){ // Not counter mode
+                entry.owner.srcid   = r_read_copy.read();
+                entry.owner.inst    = r_read_copy_inst.read();
+                entry.inst          = r_read_inst.read() || inst_read;
+                entry.count         = r_read_count.read() + 1;
+                entry.ptr           = m_heap_directory.next_free_ptr();
+            } else { // Counter mode
+                entry.owner.srcid   = 0;
+                entry.owner.inst    = false;
+                entry.inst          = r_read_inst.read() || inst_read;
+                entry.count         = r_read_count.read() + 1;
+                entry.ptr           = 0;
+            }
+#ifdef DDEBUG
+	   std::cout << "In READ_HEAP_LOCK printing the entry of address is : " << std::endl;
+	   entry.print();
+	   std::cout << "done" << std::endl;
+#endif
+
+            m_cache_directory.write(set, way, entry);
+
+            if(!is_cnt){
+              HeapEntry free_heap_entry = m_heap_directory.next_free_entry();
+              r_read_next_ptr = free_heap_entry.next;
+              if( free_heap_entry.next == m_heap_directory.next_free_ptr() ) { // Last free heap entry
+                r_read_last_free = true;
+              } else {
+                r_read_last_free = false;
+              }
+              r_read_fsm = READ_HEAP_WRITE; // we add an entry in the list of copies
+            } else {
+              if(r_read_count.read()>1) { // else there is no list of copies...
+                HeapEntry next_entry = m_heap_directory.read(r_read_ptr.read());
+                r_read_next_ptr = m_heap_directory.next_free_ptr();
+                m_heap_directory.write_free_ptr(r_read_ptr.read());
+                if( next_entry.next == r_read_ptr.read() ) { // The last list member
+                  r_read_fsm = READ_HEAP_LAST; // we erase the list of copies (counter mode)
+                } else { // Not the end of the list
+                  r_read_ptr = next_entry.next;
+                  r_read_fsm = READ_HEAP_ERASE; // we erase the list of copies (counter mode)
+                }
+              } else {
+                r_read_fsm = READ_RSP;
+              }
+            }
+          }
+          break;
+        }
+        //////////////
+      case READ_HEAP_WRITE:
+        {
+          if(r_alloc_heap_fsm.read() == ALLOC_HEAP_READ){
+            bool inst_read = (m_cmd_read_trdid_fifo.read() & 0x2);
+            HeapEntry new_heap_entry;
+            new_heap_entry.owner.srcid  = m_cmd_read_srcid_fifo.read();
+            new_heap_entry.owner.inst   = inst_read;
+            if(r_read_count.read() == 1){ // creation of a new list
+              new_heap_entry.next         = m_heap_directory.next_free_ptr(); 
+            } else {                      // it is an insertion
+              new_heap_entry.next         = r_read_ptr.read();
+            }
+            m_heap_directory.write_free_entry(new_heap_entry);
+            m_heap_directory.write_free_ptr(r_read_next_ptr.read());
+            if(r_read_last_free.read()) {
+              m_heap_directory.set_full();
+            }
+
+            r_read_fsm = READ_RSP;
+          } else {
+            assert(false && "MEMCACHE Error : Bad HEAP allocation");
+          }
+          break;
+        }
+        //////////////
+      case READ_HEAP_ERASE:
+        {
+          if(r_alloc_heap_fsm.read() == ALLOC_HEAP_READ){
+            HeapEntry next_entry = m_heap_directory.read(r_read_ptr.read());
+            if( next_entry.next == r_read_ptr.read() ){
+              r_read_fsm = READ_HEAP_LAST;
+            } else {
+              r_read_ptr = next_entry.next;
+              r_read_fsm = READ_HEAP_ERASE;
+            }
+          } else {
+            assert(false && "MEMCACHE Error : Bad HEAP allocation");
+          }
+          break;
+        }
+        //////////////
+      case READ_HEAP_LAST:
+        {
+          if(r_alloc_heap_fsm.read() == ALLOC_HEAP_READ){
+            HeapEntry last_entry;
+            last_entry.owner.srcid = 0;
+            last_entry.owner.inst  = false;
+            if(m_heap_directory.is_full()){
+              last_entry.next      = r_read_ptr.read();
+              m_heap_directory.unset_full();
+            } else {
+              last_entry.next      = r_read_next_ptr.read();
+            }
+            m_heap_directory.write(r_read_ptr.read(),last_entry);
+            r_read_fsm = READ_RSP;
+          } else {
+            assert(false && "MEMCACHE Error : Bad HEAP allocation");
+          }
+          break;
+        }
+        //////////////
+      case READ_RSP: 		//  request the TGT_RSP FSM to return data
+        {
+          if( !r_read_to_tgt_rsp_req ) {	
+            for ( size_t i=0 ; i<m_words ; i++ ) {
+              r_read_to_tgt_rsp_data[i] = r_read_data[i];
+            }
+            r_read_to_tgt_rsp_word   = m_x[(vci_addr_t)m_cmd_read_addr_fifo.read()];
+            r_read_to_tgt_rsp_length = m_cmd_read_length_fifo.read();
+            cmd_read_fifo_get 		 = true;
+            r_read_to_tgt_rsp_req	 = true;
+            r_read_to_tgt_rsp_srcid	 = m_cmd_read_srcid_fifo.read();
+            r_read_to_tgt_rsp_trdid	 = m_cmd_read_trdid_fifo.read();
+            r_read_to_tgt_rsp_pktid	 = m_cmd_read_pktid_fifo.read();
+            r_read_fsm 			     = READ_IDLE;  
+          }
+          break;
+        }
+        ///////////////////
+      case READ_TRT_LOCK:	// read miss : check the Transaction Table
+        {
+          if ( r_alloc_trt_fsm.read() == ALLOC_TRT_READ ) {
+#ifdef TDEBUG
+	std::cout << sc_time_stamp() << " " << name() << " READ_TRT_LOCK " << std::endl;
+#endif
+            size_t index = 0;
+            bool   hit_read = m_transaction_tab.hit_read(m_nline[(vci_addr_t)(m_cmd_read_addr_fifo.read())], index);
+            bool   hit_write = m_transaction_tab.hit_write(m_nline[(vci_addr_t)(m_cmd_read_addr_fifo.read())]);
+            bool   wok = !m_transaction_tab.full(index);
+            if( hit_read || !wok || hit_write ) {  // missing line already requested or no space
+              r_read_fsm = READ_IDLE;
+            } else {			   // missing line is requested to the XRAM
+              r_read_trt_index = index;
+              r_read_fsm       = READ_TRT_SET;
+            }
+          }
+          break;
+        }
+        //////////////////
+      case READ_TRT_SET:
+        {
+          if ( r_alloc_trt_fsm.read() == ALLOC_TRT_READ ) {
+            m_transaction_tab.set(r_read_trt_index.read(),
+                true,
+                m_nline[(vci_addr_t)(m_cmd_read_addr_fifo.read())],
+                m_cmd_read_srcid_fifo.read(),
+                m_cmd_read_trdid_fifo.read(),
+                m_cmd_read_pktid_fifo.read(),
+                true,
+                m_cmd_read_length_fifo.read(),
+                m_x[(vci_addr_t)(m_cmd_read_addr_fifo.read())],
+                std::vector<be_t>(m_words,0),
+                std::vector<data_t>(m_words,0));
+#ifdef TDEBUG
+	std::cout << sc_time_stamp() << " " << name() << " READ_TRT_SET transaction table : " << std::endl;
+	for(size_t i = 0 ; i < m_transaction_tab.size() ; i++)
+	  m_transaction_tab.print(i);
+#endif
+
+            r_read_fsm 	 = READ_XRAM_REQ;
+          }
+          break;
+        }
+        /////////////////////
+      case READ_XRAM_REQ:
+        {
+          if( !r_read_to_ixr_cmd_req ) {
+            cmd_read_fifo_get		= true;
+            r_read_to_ixr_cmd_req  	= true;
+            r_read_to_ixr_cmd_nline 	= m_nline[(vci_addr_t)(m_cmd_read_addr_fifo.read())];
+            r_read_to_ixr_cmd_trdid 	= r_read_trt_index.read();
+            r_read_fsm 			          = READ_IDLE;
+          }
+          break;
+        }
+    } // end switch read_fsm
+
+    ///////////////////////////////////////////////////////////////////////////////////
+    //		WRITE FSM
+    ///////////////////////////////////////////////////////////////////////////////////
+    // The WRITE FSM handles the write bursts sent by the processors.
+    // All addresses in a burst must be in the same cache line.
+    // A complete write burst is consumed in the FIFO & copied to a local buffer.
+    // Then the FSM takes the lock protecting the cache directory, to check
+    // if the line is in the cache.
+    //
+    // - In case of HIT, the cache is updated.
+    //   If there is no other copy, an acknowledge response is immediately
+    //   returned to the writing processor.
+    //   if the data is cached by other processoris, the FSM takes the lock
+    //   protecting the Update Table (UPT) to register this update transaction.
+    //   If the UPT is full, it releases the lock  and waits. Then, it sends 
+    //   a multi-update request to all owners of the line (but the writer), 
+    //   through the INIT_CMD FSM. In case of multi-update transaction, the WRITE FSM 
+    //   does not respond to the writing processor, as this response will be sent by 
+    //   the INIT_RSP FSM when all update responses have been received.
+    //
+    // - In case of MISS, the WRITE FSM takes the lock protecting the transaction
+    //   table (TRT). If a read transaction to the XRAM for this line already exists, 
+    //   it writes in the TRT (write buffer). Otherwise, if a TRT entry is free, 
+    //   the WRITE FSM register a new transaction in TRT, and sends a read line request 
+    //   to the XRAM. If the TRT is full, it releases the lock, and waits.
+    //   Finally, the WRITE FSM returns an aknowledge response to the writing processor.
+    /////////////////////////////////////////////////////////////////////////////////////
+
+    switch ( r_write_fsm.read() ) {
+
+      ////////////////
+      case WRITE_IDLE:	// copy first word of a write burst in local buffer	
+        {
+          if ( m_cmd_write_addr_fifo.rok()) {
+            m_cpt_write++;
+            m_cpt_write_cells++;
+            // consume a word in the FIFO & write it in the local buffer 
+            cmd_write_fifo_get	= true;
+            size_t index 	    = m_x[(vci_addr_t)(m_cmd_write_addr_fifo.read())];
+            r_write_address	    = (addr_t)(m_cmd_write_addr_fifo.read());
+            r_write_word_index	= index;
+            r_write_word_count	= 1;
+            r_write_data[index]	= m_cmd_write_data_fifo.read();
+            r_write_srcid	    = m_cmd_write_srcid_fifo.read();
+            r_write_trdid	    = m_cmd_write_trdid_fifo.read();
+            r_write_pktid	    = m_cmd_write_pktid_fifo.read();
+
+            // the be field must be set for all words 
+            for ( size_t i=0 ; i<m_words ; i++ ) {
+              if ( i == index ) r_write_be[i] = m_cmd_write_be_fifo.read();
+              else		        r_write_be[i] = 0x0;
+            }
+            if( !((m_cmd_write_be_fifo.read() == 0x0)||(m_cmd_write_be_fifo.read() == 0xF)) )
+                    r_write_byte=true;
+            else    r_write_byte=false;
+
+            if( m_cmd_write_eop_fifo.read() )  r_write_fsm = WRITE_DIR_LOCK;
+            else                               r_write_fsm = WRITE_NEXT;
+          }
+          break;
+        }
+        ////////////////
+      case WRITE_NEXT:	// copy next word of a write burst in local buffer
+        {
+          if ( m_cmd_write_addr_fifo.rok() ) {
+            m_cpt_write_cells++;
+
+            // check that the next word is in the same cache line
+            assert( (m_nline[(vci_addr_t)(r_write_address.read())] == m_nline[(vci_addr_t)(m_cmd_write_addr_fifo.read())])  
+                && "VCI_MEM_CACHE write error in vci_mem_cache : write burst over a line" );
+            // consume a word in the FIFO & write it in the local buffer 
+            cmd_write_fifo_get=true;
+            size_t index 	        = r_write_word_index.read() + r_write_word_count.read();
+            r_write_be[index]       = m_cmd_write_be_fifo.read();
+            r_write_data[index]     = m_cmd_write_data_fifo.read();
+            r_write_word_count 	    = r_write_word_count.read() + 1;
+            if( !((m_cmd_write_be_fifo.read() == 0x0)||(m_cmd_write_be_fifo.read() == 0xF)) )
+              r_write_byte=true;
+            if ( m_cmd_write_eop_fifo.read() )  r_write_fsm = WRITE_DIR_LOCK;
+          }
+          break;
+        }
+        ////////////////////
+      case WRITE_DIR_LOCK:	// access directory to check hit/miss
+        {
+          if ( r_alloc_dir_fsm.read() == ALLOC_DIR_WRITE ) {
+            size_t  way = 0;
+            DirectoryEntry entry(m_cache_directory.read(r_write_address.read(), way));
+
+            // copy directory entry in local buffers in case of hit
+            if ( entry.valid )  {	
+              r_write_is_cnt    = entry.is_cnt;
+              r_write_lock	    = entry.lock;
+              r_write_inst      = entry.inst;
+              r_write_tag       = entry.tag;
+              r_write_copy      = entry.owner.srcid;
+              r_write_copy_inst = entry.owner.inst;
+              r_write_count     = entry.count;
+              r_write_ptr       = entry.ptr;
+              r_write_way  	    = way;
+              
+              bool owner = (entry.owner.srcid==r_write_srcid.read()) && !entry.owner.inst;
+              bool no_update = (entry.count==0) || ( owner && (entry.count==1));
+              if((entry.is_cnt && entry.count) ||
+                  entry.inst){
+                r_write_fsm      = WRITE_DIR_HIT_READ;
+              } else {
+                if(r_write_byte.read())
+                  r_write_fsm      = WRITE_DIR_HIT_READ;
+                else{ 
+                    if( no_update) r_write_fsm  = WRITE_DIR_HIT_RSP;
+                    else           r_write_fsm  = WRITE_DIR_HIT;
+                }
+              }
+            } else {
+              r_write_fsm = WRITE_TRT_LOCK;
+              m_cpt_write_miss++;
+            }
+          }
+          break;
+        }
+        ///////////////////
+      case WRITE_DIR_HIT_READ:	// read the cache and complete the buffer (data, when be!=0xF)
+        {
+          // update local buffer
+          size_t set	= m_y[(vci_addr_t)(r_write_address.read())];
+          size_t way	= r_write_way.read();
+          for(size_t i=0 ; i<m_words ; i++) {
+            data_t mask      = 0;
+            if  (r_write_be[i].read() & 0x1) mask = mask | 0x000000FF;
+            if  (r_write_be[i].read() & 0x2) mask = mask | 0x0000FF00;
+            if  (r_write_be[i].read() & 0x4) mask = mask | 0x00FF0000;
+            if  (r_write_be[i].read() & 0x8) mask = mask | 0xFF000000;
+            if(r_write_be[i].read()||r_write_is_cnt.read()||r_write_inst.read()) { // complete only if mask is not null (for energy consumption)
+              r_write_data[i]  = (r_write_data[i].read() & mask) | 
+                (m_cache_data[way][set][i] & ~mask);
+            }
+          } // end for
+
+          bool owner = (r_write_copy.read()==r_write_srcid.read()) && !r_write_copy_inst.read();
+          bool no_update = (r_write_count.read()==0) || ( owner && (r_write_count.read()==1));
+          if((r_write_is_cnt.read() && r_write_count.read()) ||
+              r_write_inst.read()){
+            r_write_fsm            = WRITE_TRT_WRITE_LOCK;
+          } else {
+            if( no_update ) r_write_fsm = WRITE_DIR_HIT_RSP;
+            else            r_write_fsm = WRITE_DIR_HIT;
+          }
+          break;
+        }
+        ///////////////////
+      case WRITE_DIR_HIT:	// update the cache (data & dirty bit)
+        {
+          // update directory with Dirty bit
+          DirectoryEntry entry;
+          entry.valid	    = true;
+          entry.dirty	    = true;
+          entry.tag	        = r_write_tag.read();
+          entry.is_cnt      = r_write_is_cnt.read();
+          entry.lock	    = r_write_lock.read();
+          entry.inst        = r_write_inst.read();
+          entry.owner.srcid = r_write_copy.read();
+          entry.owner.inst  = r_write_copy_inst.read();
+          entry.count       = r_write_count.read();
+          entry.ptr         = r_write_ptr.read();
+          size_t set	    = m_y[(vci_addr_t)(r_write_address.read())];
+          size_t way	    = r_write_way.read();
+          m_cache_directory.write(set, way, entry);
+
+          bool owner = (r_write_copy.read()==r_write_srcid.read()) && !r_write_copy_inst.read();
+
+          size_t count_signal   = r_write_count.read();
+          if(owner){
+            count_signal        = count_signal - 1;
+          }
+          r_write_count         = count_signal;
+          r_write_to_dec        = false;
+
+          if( !r_write_to_init_cmd_multi_req.read() && 
+              !r_write_to_init_cmd_brdcast_req.read()  )
+            r_write_fsm = WRITE_UPT_LOCK;
+          else
+            r_write_fsm = WRITE_WAIT;
+          break;
+        }
+        ///////////////////
+      case WRITE_DIR_HIT_RSP:	// update the cache (data & dirty bit) no update
+        {
+          // update directory with Dirty bit
+          DirectoryEntry entry;
+          entry.valid	    = true;
+          entry.dirty	    = true;
+          entry.tag	        = r_write_tag.read();
+          entry.is_cnt      = r_write_is_cnt.read();
+          entry.lock	    = r_write_lock.read();
+          entry.inst        = r_write_inst.read();
+          entry.owner.srcid = r_write_copy.read();
+          entry.owner.inst  = r_write_copy_inst.read();
+          entry.count       = r_write_count.read();
+          entry.ptr         = r_write_ptr.read();
+          size_t set	    = m_y[(vci_addr_t)(r_write_address.read())];
+          size_t way	    = r_write_way.read();
+          m_cache_directory.write(set, way, entry);
+
+          bool owner = (r_write_copy.read()==r_write_srcid.read()) && !r_write_copy_inst.read();
+
+          // write data in cache
+          for(size_t i=0 ; i<m_words ; i++) {
+              if  ( r_write_be[i].read() ) {
+                  m_cache_data[way][set][i]  = r_write_data[i].read();
+              }
+          } // end for
+
+          if ( !r_write_to_tgt_rsp_req.read() ) {
+            r_write_to_tgt_rsp_req	    = true;
+            r_write_to_tgt_rsp_srcid	= r_write_srcid.read();
+            r_write_to_tgt_rsp_trdid	= r_write_trdid.read();
+            r_write_to_tgt_rsp_pktid	= r_write_pktid.read();
+            r_write_fsm 		        = WRITE_IDLE;
+          } else {
+            r_write_fsm = WRITE_RSP;
+          }
+          break;
+        }
+        /////////////////////
+      case WRITE_UPT_LOCK: 	// Try to register the request in Update Table
+        {
+
+          if ( r_alloc_upt_fsm.read() == ALLOC_UPT_WRITE ) {
+            bool        wok        = false;
+            size_t      index      = 0;
+            size_t      srcid      = r_write_srcid.read();
+            size_t      trdid      = r_write_trdid.read();
+            size_t      pktid      = r_write_pktid.read();
+            addr_t      nline      = m_nline[(vci_addr_t)(r_write_address.read())];
+            size_t      nb_copies  = r_write_count.read();
+            size_t set	    = m_y[(vci_addr_t)(r_write_address.read())];
+            size_t way	    = r_write_way.read();
+
+            wok =m_update_tab.set(true,	// it's an update transaction
+                false,                  // it's not a broadcast
+                true,                   // it needs a response
+                srcid,
+                trdid,
+                pktid,
+                nline,
+                nb_copies,
+                index);
+            if(wok){
+              // write data in cache
+              for(size_t i=0 ; i<m_words ; i++) {
+                if  ( r_write_be[i].read() ) {
+                  m_cache_data[way][set][i]  = r_write_data[i].read();
+                }
+              } // end for
+            }
+#ifdef IDEBUG
+            if(wok){
+	std::cout << sc_time_stamp() << " " << name() << " WRITE_UPT_LOCK update table : " << std::endl;
+	m_update_tab.print();
+            }
+#endif
+            r_write_upt_index = index;
+            //  releases the lock protecting the Update Table and the Directory if no entry...
+            if ( wok ) r_write_fsm = WRITE_HEAP_LOCK;
+            else       r_write_fsm = WRITE_WAIT;
+          }
+          break;
+        }
+        //////////////////
+      case WRITE_HEAP_LOCK:
+        {
+          if( r_alloc_heap_fsm.read() == ALLOC_HEAP_WRITE ){
+            r_write_fsm = WRITE_UPT_REQ;
+          }
+          break;
+        }
+        //////////////////
+      case WRITE_UPT_REQ:
+        {
+          assert( (r_alloc_heap_fsm.read() == ALLOC_HEAP_WRITE) &&
+                    "MemCache ERROR : bad HEAP allocation");
+          if( !r_write_to_init_cmd_multi_req.read() && 
+              !r_write_to_init_cmd_brdcast_req.read()  ){
+            r_write_to_init_cmd_brdcast_req  = false;
+            r_write_to_init_cmd_trdid        = r_write_upt_index.read();
+            r_write_to_init_cmd_nline        = m_nline[(vci_addr_t)(r_write_address.read())];
+            r_write_to_init_cmd_index        = r_write_word_index.read();
+            r_write_to_init_cmd_count        = r_write_word_count.read();
+
+            for(size_t i=0; i<m_words ; i++){
+              if(r_write_be[i].read())  r_write_to_init_cmd_we[i]=true;
+              else                      r_write_to_init_cmd_we[i]=false;
+            }
+
+            size_t min = r_write_word_index.read();
+            size_t max = r_write_word_index.read() + r_write_word_count.read();
+            for (size_t i=min ; i<max ; i++) {
+              r_write_to_init_cmd_data[i] = r_write_data[i];
+            }
+            
+            if( r_write_copy.read() != r_write_srcid.read() ) {
+              // We put the first copy in the fifo
+              write_to_init_cmd_fifo_put     = true;
+              write_to_init_cmd_fifo_inst    = r_write_copy_inst.read();
+              write_to_init_cmd_fifo_srcid   = r_write_copy.read();
+              if(r_write_count.read() == 1){
+                r_write_fsm = WRITE_IDLE;
+                r_write_to_init_cmd_multi_req = true;
+              } else {
+                r_write_fsm = WRITE_UPDATE;
+              }
+            } else {
+              r_write_fsm = WRITE_UPDATE;
+            }
+          }
+          break;
+        }
+        //////////////////
+      case WRITE_UPDATE:	// send a multi-update request to INIT_CMD fsm
+        {
+          assert( (r_alloc_heap_fsm.read() == ALLOC_HEAP_WRITE) &&
+                    "MemCache ERROR : bad HEAP allocation");
+          HeapEntry entry = m_heap_directory.read(r_write_ptr.read());
+          write_to_init_cmd_fifo_inst  = entry.owner.inst;
+          write_to_init_cmd_fifo_srcid = entry.owner.srcid;
+          bool dec_upt_counter = r_write_to_dec.read();
+          if( (entry.owner.srcid != r_write_srcid.read()) || entry.owner.inst ){
+            write_to_init_cmd_fifo_put = true;
+          } else {
+            dec_upt_counter = true;
+          }
+          r_write_to_dec = dec_upt_counter;
+
+          if( m_write_to_init_cmd_inst_fifo.wok() ){
+            r_write_ptr = entry.next;
+            if( entry.next == r_write_ptr.read() ) { // last copy
+              r_write_to_init_cmd_multi_req = true;
+              if(dec_upt_counter){
+                r_write_fsm = WRITE_UPT_DEC;
+              } else {
+                r_write_fsm = WRITE_IDLE;
+              }
+            } else {
+              r_write_fsm = WRITE_UPDATE;
+            }
+          } else {
+            r_write_fsm = WRITE_UPDATE;
+          }
+          break;
+        }
+        //////////////////
+      case WRITE_UPT_DEC:
+        {
+          if(!r_write_to_init_rsp_req.read()){
+            r_write_to_init_rsp_req = true;
+            r_write_to_init_rsp_upt_index = r_write_upt_index.read();
+            r_write_fsm = WRITE_IDLE;
+          }
+          break;
+        }
+        ///////////////
+      case WRITE_RSP:		// send a request to TGT_RSP FSM to acknowledge the write
+        {
+          if ( !r_write_to_tgt_rsp_req.read() ) {
+            r_write_to_tgt_rsp_req	    = true;
+            r_write_to_tgt_rsp_srcid	= r_write_srcid.read();
+            r_write_to_tgt_rsp_trdid	= r_write_trdid.read();
+            r_write_to_tgt_rsp_pktid	= r_write_pktid.read();
+            r_write_fsm 		        = WRITE_IDLE;
+          }
+          break;
+        }
+        ////////////////////
+      case WRITE_TRT_LOCK:	// Miss : check Transaction Table
+        {
+          if ( r_alloc_trt_fsm.read() == ALLOC_TRT_WRITE ) {
+#ifdef TDEBUG
+	std::cout << sc_time_stamp() << " " << name() << " READ_TRT_LOCK " << std::endl;
+#endif
+            size_t hit_index = 0;
+            size_t wok_index = 0;
+            bool hit_read  = m_transaction_tab.hit_read(m_nline[(vci_addr_t)(r_write_address.read())],hit_index);
+            bool hit_write = m_transaction_tab.hit_write(m_nline[(vci_addr_t)(r_write_address.read())]);
+            bool wok = !m_transaction_tab.full(wok_index);
+            if ( hit_read ) {	// register the modified data in TRT 
+              r_write_trt_index = hit_index;
+              r_write_fsm       = WRITE_TRT_DATA;
+            } else if ( wok && !hit_write ) {	// set a new entry in TRT
+              r_write_trt_index = wok_index;
+              r_write_fsm       = WRITE_TRT_SET;
+            } else {		// wait an empty entry in TRT
+              r_write_fsm       = WRITE_WAIT;
+            }
+          }
+          break;
+        }
+        ////////////////////
+      case WRITE_WAIT:	// release the lock protecting TRT
+        { 
+          r_write_fsm = WRITE_DIR_LOCK;
+          break;
+        }
+        ///////////////////
+      case WRITE_TRT_SET:	// register a new transaction in TRT (Write Buffer)
+        {  
+          if ( r_alloc_trt_fsm.read() == ALLOC_TRT_WRITE ) 
+          {
+            std::vector<be_t> be_vector;
+            std::vector<data_t> data_vector;
+            be_vector.clear();
+            data_vector.clear();
+            for ( size_t i=0; i<m_words; i++ ) 
+            {
+              be_vector.push_back(r_write_be[i]);
+              data_vector.push_back(r_write_data[i]);
+            }
+            m_transaction_tab.set(r_write_trt_index.read(),
+                true,				// read request to XRAM
+                m_nline[(vci_addr_t)(r_write_address.read())],
+                r_write_srcid.read(),
+                r_write_trdid.read(),
+                r_write_pktid.read(),
+                false,				// not a processor read
+                0,  				// not a single word 
+                0,		        	// word index
+                be_vector,
+                data_vector);
+#ifdef TDEBUG
+	std::cout << sc_time_stamp() << " " << name() << " WRITE_TRT_SET transaction table : " << std::endl;
+	for(size_t i = 0 ; i < m_transaction_tab.size() ; i++)
+	  m_transaction_tab.print(i);
+#endif
+
+            r_write_fsm = WRITE_XRAM_REQ;
+          }
+          break;
+        }  
+        ///////////////////
+      case WRITE_TRT_DATA:	// update an entry in TRT (Write Buffer)
+        { 
+          if ( r_alloc_trt_fsm.read() == ALLOC_TRT_WRITE ) {
+            std::vector<be_t> be_vector;
+            std::vector<data_t> data_vector;
+            be_vector.clear();
+            data_vector.clear();
+            for ( size_t i=0; i<m_words; i++ ) {
+              be_vector.push_back(r_write_be[i]);
+              data_vector.push_back(r_write_data[i]);
+            }
+            m_transaction_tab.write_data_mask(r_write_trt_index.read(),
+                be_vector,
+                data_vector);
+            r_write_fsm = WRITE_RSP;
+#ifdef TDEBUG
+	std::cout << sc_time_stamp() << " " << name() << " WRITE_TRT_DATA transaction table : " << std::endl;
+	for(size_t i = 0 ; i < m_transaction_tab.size() ; i++)
+	  m_transaction_tab.print(i);
+#endif
+
+          }
+          break;
+        }
+        ////////////////////
+      case WRITE_XRAM_REQ:	// send a request to IXR_CMD FSM
+        {  
+
+          if ( !r_write_to_ixr_cmd_req ) {
+            r_write_to_ixr_cmd_req   = true;
+            r_write_to_ixr_cmd_write = false;
+            r_write_to_ixr_cmd_nline = m_nline[(vci_addr_t)(r_write_address.read())];
+            r_write_to_ixr_cmd_trdid = r_write_trt_index.read();
+            r_write_fsm              = WRITE_RSP;
+          }
+          break;
+        }
+        ////////////////////
+      case WRITE_TRT_WRITE_LOCK:
+        {
+          if ( r_alloc_trt_fsm.read() == ALLOC_TRT_WRITE ) {
+            size_t wok_index = 0;
+            bool wok = !m_transaction_tab.full(wok_index);
+            if ( wok ) {	// set a new entry in TRT
+              r_write_trt_index = wok_index;
+              r_write_fsm       = WRITE_INVAL_LOCK;
+            } else {		// wait an empty entry in TRT
+              r_write_fsm       = WRITE_WAIT;
+            }
+          }
+
+          break;
+        }
+        ////////////////////
+      case WRITE_INVAL_LOCK:
+        {
+          if ( r_alloc_upt_fsm.read() == ALLOC_UPT_WRITE ) {
+            bool        wok       = false;
+            size_t      index     = 0;
+            size_t      srcid     = r_write_srcid.read();
+            size_t      trdid     = r_write_trdid.read();
+            size_t      pktid     = r_write_pktid.read();
+            addr_t	    nline     = m_nline[(vci_addr_t)(r_write_address.read())];
+            size_t      nb_copies = r_write_count.read();
+
+            wok =m_update_tab.set(false,	// it's an inval transaction
+                true,                       // it's a broadcast
+                true,                       // it needs a response
+                srcid,
+                trdid,
+                pktid,
+                nline,
+                nb_copies,
+                index);
+#ifdef IDEBUG
+            if(wok){
+	std::cout << sc_time_stamp() << " " << name() << " WRITE_INVAL_LOCK update table : " << std::endl;
+	m_update_tab.print();
+            }
+#endif
+            r_write_upt_index = index;
+            //  releases the lock protecting Update Table if no entry...
+            if ( wok ) r_write_fsm = WRITE_DIR_INVAL;
+            else       r_write_fsm = WRITE_WAIT;
+          }
+
+          break;
+        }
+        ////////////////////
+      case WRITE_DIR_INVAL:
+        {
+            assert(((r_alloc_trt_fsm.read() == ALLOC_TRT_WRITE ) &&
+                    (r_alloc_upt_fsm.read() == ALLOC_UPT_WRITE ) &&
+                    (r_alloc_dir_fsm.read() == ALLOC_DIR_WRITE ))&&
+                    "MemCache ERROR : bad TRT,DIR or UPT allocation error");
+            m_transaction_tab.set(r_write_trt_index.read(),
+                false,				// write request to XRAM
+                m_nline[(vci_addr_t)(r_write_address.read())],
+                0,
+                0,
+                0,
+                false,				// not a processor read
+                0,  				// not a single word 
+                0,		        	// word index
+                std::vector<be_t>(m_words,0),
+                std::vector<data_t>(m_words,0));
+#ifdef TDEBUG
+	std::cout << sc_time_stamp() << " " << name() << " WRITE_DIR_INVAL transaction table : " << std::endl;
+	for(size_t i = 0 ; i < m_transaction_tab.size() ; i++)
+	  m_transaction_tab.print(i);
+#endif
+
+            // invalidate directory entry
+            DirectoryEntry entry;
+            entry.valid	        = false;
+            entry.dirty	        = false;
+            entry.tag	        = 0;
+            entry.is_cnt        = false;
+            entry.lock          = false;
+            entry.inst          = false;
+            entry.owner.srcid   = 0;
+            entry.owner.inst    = false;
+            entry.ptr           = 0;
+            entry.count         = 0;
+            size_t set	        = m_y[(vci_addr_t)(r_write_address.read())];
+            size_t way	        = r_write_way.read();
+            m_cache_directory.write(set, way, entry);
+
+            r_write_fsm = WRITE_INVAL;
+            break;
+        }
+        ////////////////////
+      case WRITE_INVAL:
+        {
+          if (  !r_write_to_init_cmd_multi_req.read() &&
+                !r_write_to_init_cmd_brdcast_req.read() ) {
+            r_write_to_init_cmd_multi_req   = false;
+            r_write_to_init_cmd_brdcast_req = true;
+            r_write_to_init_cmd_trdid       = r_write_upt_index.read();
+            r_write_to_init_cmd_nline       = m_nline[(vci_addr_t)(r_write_address.read())];
+            r_write_to_init_cmd_index       = 0;
+            r_write_to_init_cmd_count       = 0;
+
+            for(size_t i=0; i<m_words ; i++){
+              r_write_to_init_cmd_we[i]=false;
+              r_write_to_init_cmd_data[i] = 0;
+            }
+            r_write_fsm = WRITE_XRAM_SEND;
+            // all inval responses
+          }
+
+          break;
+        }
+        ////////////////////
+      case WRITE_XRAM_SEND:
+        {
+          if ( !r_write_to_ixr_cmd_req ) {
+            r_write_to_ixr_cmd_req     = true;
+            r_write_to_ixr_cmd_write   = true;
+            r_write_to_ixr_cmd_nline   = m_nline[(vci_addr_t)(r_write_address.read())];
+            r_write_to_ixr_cmd_trdid   = r_write_trt_index.read();
+            for(size_t i=0; i<m_words; i++){
+              r_write_to_ixr_cmd_data[i] = r_write_data[i];
+            }
+            if(  r_write_is_cnt.read() ||
+                ((!r_write_is_cnt.read()) && (r_write_count.read()==1)) ){
+              r_write_fsm = WRITE_IDLE;
+            } else {
+              r_write_fsm = WRITE_HEAP_ERASE;
+              r_write_next_ptr = r_write_ptr.read();
+            }
+          }
+          break;
+        }
+        ////////////////////
+      case WRITE_HEAP_ERASE:
+        {
+          if(r_alloc_heap_fsm.read() == ALLOC_HEAP_WRITE){
+            HeapEntry next_entry = m_heap_directory.read(r_write_next_ptr.read());
+            if( next_entry.next == r_write_next_ptr.read()){
+              r_write_fsm = WRITE_HEAP_LAST;
+            } else {
+              r_write_next_ptr = next_entry.next;
+              r_write_fsm = WRITE_HEAP_ERASE;
+            }
+          }
+          break;
+        }
+        ////////////////////
+      case WRITE_HEAP_LAST:
+        {
+          assert((r_alloc_heap_fsm.read() == ALLOC_HEAP_WRITE) &&
+                  "MemCache ERROR : bad HEAP allocation");
+          size_t free_pointer = m_heap_directory.next_free_ptr();
+
+          HeapEntry last_entry;
+          last_entry.owner.srcid = 0;
+          last_entry.owner.inst  = false;
+          if(m_heap_directory.is_full()){
+            last_entry.next     = r_write_next_ptr.read();
+            m_heap_directory.unset_full();
+          } else {
+            last_entry.next     = free_pointer;
+          }
+
+          m_heap_directory.write_free_ptr(r_write_ptr.read());
+          m_heap_directory.write(r_write_next_ptr.read(),last_entry);
+
+          r_write_fsm = WRITE_IDLE;
+          break;
+        }
+    } // end switch r_write_fsm
+
+    ///////////////////////////////////////////////////////////////////////
+    //		IXR_CMD FSM
+    ///////////////////////////////////////////////////////////////////////
+    // The IXR_CMD fsm controls the command packets to the XRAM :
+    // - It sends a single cell VCI read to the XRAM in case of MISS request
+    // posted by the READ, WRITE or LLSC FSMs : the TRDID field contains 
+    // the Transaction Tab index.
+    // The VCI response is a multi-cell packet : the N cells contain
+    // the N data words.
+    // - It sends a multi-cell VCI write when the XRAM_RSP FSM request 
+    // to save a dirty line to the XRAM. 
+    // The VCI response is a single cell packet.
+    // This FSM handles requests from the READ, WRITE, LLSC & XRAM_RSP FSMs 
+    // with a round-robin priority.
+    ////////////////////////////////////////////////////////////////////////
+
+    switch ( r_ixr_cmd_fsm.read() ) {
+      //////////////////////// 
+      case IXR_CMD_READ_IDLE:
+        if      ( r_write_to_ixr_cmd_req )     r_ixr_cmd_fsm = IXR_CMD_WRITE_NLINE;
+        else if ( r_llsc_to_ixr_cmd_req  )     r_ixr_cmd_fsm = IXR_CMD_LLSC_NLINE;
+        else if ( r_xram_rsp_to_ixr_cmd_req  ) r_ixr_cmd_fsm = IXR_CMD_XRAM_DATA;
+        else if ( r_read_to_ixr_cmd_req  )     r_ixr_cmd_fsm = IXR_CMD_READ_NLINE;
+        break;
+        //////////////////////// 
+      case IXR_CMD_WRITE_IDLE:
+        if      ( r_llsc_to_ixr_cmd_req  )     r_ixr_cmd_fsm = IXR_CMD_LLSC_NLINE;
+        else if ( r_xram_rsp_to_ixr_cmd_req  ) r_ixr_cmd_fsm = IXR_CMD_XRAM_DATA;
+        else if ( r_read_to_ixr_cmd_req  )     r_ixr_cmd_fsm = IXR_CMD_READ_NLINE;
+        else if ( r_write_to_ixr_cmd_req )     r_ixr_cmd_fsm = IXR_CMD_WRITE_NLINE;
+        break;
+        //////////////////////// 
+      case IXR_CMD_LLSC_IDLE:
+        if      ( r_xram_rsp_to_ixr_cmd_req  ) r_ixr_cmd_fsm = IXR_CMD_XRAM_DATA;
+        else if ( r_read_to_ixr_cmd_req  )     r_ixr_cmd_fsm = IXR_CMD_READ_NLINE;
+        else if ( r_write_to_ixr_cmd_req )     r_ixr_cmd_fsm = IXR_CMD_WRITE_NLINE;
+        else if ( r_llsc_to_ixr_cmd_req  )     r_ixr_cmd_fsm = IXR_CMD_LLSC_NLINE;
+        break;
+        //////////////////////// 
+      case IXR_CMD_XRAM_IDLE:
+        if      ( r_read_to_ixr_cmd_req  )     r_ixr_cmd_fsm = IXR_CMD_READ_NLINE;
+        else if ( r_write_to_ixr_cmd_req )     r_ixr_cmd_fsm = IXR_CMD_WRITE_NLINE;
+        else if ( r_llsc_to_ixr_cmd_req  )     r_ixr_cmd_fsm = IXR_CMD_LLSC_NLINE;
+        else if ( r_xram_rsp_to_ixr_cmd_req  ) r_ixr_cmd_fsm = IXR_CMD_XRAM_DATA;
+        break;
+        /////////////////////////
+      case IXR_CMD_READ_NLINE:
+        if ( p_vci_ixr.cmdack ) {
+          r_ixr_cmd_fsm = IXR_CMD_READ_IDLE;		
+          r_read_to_ixr_cmd_req = false;
+        }
+        break;
+        //////////////////////////
+      case IXR_CMD_WRITE_NLINE:
+        if ( p_vci_ixr.cmdack ) {
+          if( r_write_to_ixr_cmd_write.read()){
+            if ( r_ixr_cmd_cpt.read() == (m_words - 1) ) {
+              r_ixr_cmd_cpt = 0;
+              r_ixr_cmd_fsm = IXR_CMD_WRITE_IDLE;
+              r_write_to_ixr_cmd_req = false;
+            } else {
+              r_ixr_cmd_cpt = r_ixr_cmd_cpt + 1;
+            }
+          } else {
+            r_ixr_cmd_fsm = IXR_CMD_WRITE_IDLE;		
+            r_write_to_ixr_cmd_req = false;
+          }
+        }
+        break;
+        /////////////////////////
+      case IXR_CMD_LLSC_NLINE:
+        if ( p_vci_ixr.cmdack ) {
+          if( r_llsc_to_ixr_cmd_write.read()){
+            if ( r_ixr_cmd_cpt.read() == (m_words - 1) ) {
+              r_ixr_cmd_cpt = 0;
+              r_ixr_cmd_fsm = IXR_CMD_LLSC_IDLE;
+              r_llsc_to_ixr_cmd_req = false;
+            } else {
+              r_ixr_cmd_cpt = r_ixr_cmd_cpt + 1;
+            }
+          } else {
+            r_ixr_cmd_fsm = IXR_CMD_LLSC_IDLE;		
+            r_llsc_to_ixr_cmd_req = false;
+          }
+        }
+        break;
+        ////////////////////////
+      case IXR_CMD_XRAM_DATA:
+        if ( p_vci_ixr.cmdack ) {
+          if ( r_ixr_cmd_cpt.read() == (m_words - 1) ) {
+            r_ixr_cmd_cpt = 0;
+            r_ixr_cmd_fsm = IXR_CMD_XRAM_IDLE;
+            r_xram_rsp_to_ixr_cmd_req = false;
+          } else {
+            r_ixr_cmd_cpt = r_ixr_cmd_cpt + 1;
+          }
+        }
+        break;
+
+    } // end switch r_ixr_cmd_fsm
+
+    ////////////////////////////////////////////////////////////////////////////
+    //                IXR_RSP FSM
+    ////////////////////////////////////////////////////////////////////////////
+    // The IXR_RSP FSM receives the response packets from the XRAM,
+    // for both write transaction, and read transaction.
+    //
+    // - A response to a write request is a single-cell VCI packet.
+    // The Transaction Tab index is contained in the RTRDID field.
+    // The FSM takes the lock protecting the TRT, and the corresponding
+    // entry is erased.
+    //	
+    // - A response to a read request is a multi-cell VCI packet.
+    // The Transaction Tab index is contained in the RTRDID field.
+    // The N cells contain the N words of the cache line in the RDATA field.
+    // The FSM takes the lock protecting the TRT to store the line in the TRT
+    // (taking into account the write requests already stored in the TRT).
+    // When the line is completely written, the corresponding rok signal is set.
+    ///////////////////////////////////////////////////////////////////////////////
+
+    switch ( r_ixr_rsp_fsm.read() ) {
+
+      ///////////////////
+      case IXR_RSP_IDLE:	// test if it's a read or a write transaction
+        {
+          if ( p_vci_ixr.rspval ) {
+            r_ixr_rsp_cpt   = 0;
+            r_ixr_rsp_trt_index = p_vci_ixr.rtrdid.read();
+            if ( p_vci_ixr.reop )  r_ixr_rsp_fsm = IXR_RSP_ACK;
+            else                   r_ixr_rsp_fsm = IXR_RSP_TRT_READ;
+          }
+          break;  
+        }
+        ////////////////////////
+      case IXR_RSP_ACK:        // Acknowledge the vci response
+        r_ixr_rsp_fsm = IXR_RSP_TRT_ERASE;
+        break;
+        ////////////////////////
+      case IXR_RSP_TRT_ERASE: 	// erase the entry in the TRT
+        {
+          if ( r_alloc_trt_fsm.read() == ALLOC_TRT_IXR_RSP ) {
+            m_transaction_tab.erase(r_ixr_rsp_trt_index.read());
+            r_ixr_rsp_fsm = IXR_RSP_IDLE;
+#ifdef TDEBUG
+	std::cout << sc_time_stamp() << " " << name() << " IXR_RSP_TRT_ERASE transaction table : " << std::endl;
+	for(size_t i = 0 ; i < m_transaction_tab.size() ; i++)
+	  m_transaction_tab.print(i);
+#endif
+
+          }
+          break;
+        }
+        ///////////////////////
+      case IXR_RSP_TRT_READ:		// write data in the TRT
+        {
+          if ( (r_alloc_trt_fsm.read() == ALLOC_TRT_IXR_RSP) &&  p_vci_ixr.rspval ) {
+            bool   eop  	= p_vci_ixr.reop.read();
+            data_t data 	= p_vci_ixr.rdata.read();
+            size_t index        = r_ixr_rsp_trt_index.read();
+            assert( eop == (r_ixr_rsp_cpt.read() == (m_words-1)) 
+                && "Error in VCI_MEM_CACHE : invalid length for a response from XRAM");
+            m_transaction_tab.write_rsp(index, r_ixr_rsp_cpt.read(), data);
+            r_ixr_rsp_cpt = r_ixr_rsp_cpt.read() + 1;
+            if ( eop ) {
+#ifdef TDEBUG
+	std::cout << sc_time_stamp() << " " << name() << " IXR_RSP_TRT_READ transaction table : " << std::endl;
+	for(size_t i = 0 ; i < m_transaction_tab.size() ; i++)
+	  m_transaction_tab.print(i);
+#endif
+
+              r_ixr_rsp_to_xram_rsp_rok[r_ixr_rsp_trt_index.read()]=true;
+              r_ixr_rsp_fsm = IXR_RSP_IDLE;
+            }
+          }
+          break;
+        }
+    } // end swich r_ixr_rsp_fsm
+
+
+    ////////////////////////////////////////////////////////////////////////////
+    //                XRAM_RSP FSM
+    ////////////////////////////////////////////////////////////////////////////
+    // The XRAM_RSP FSM handles the incoming cache lines from the XRAM.
+    // The cache line has been written in the TRT buffer by the IXR_FSM.
+    //
+    // When a response is available, the corresponding TRT entry 
+    // is copied in a local buffer to be written in the cache. 
+    // Then, the FSM releases the lock protecting the TRT, and takes the lock 
+    // protecting the cache directory.
+    // It selects a cache slot and writes the line in the cache.
+    // If it was a read MISS, the XRAM_RSP FSM send a request to the TGT_RSP
+    // FSM to return the cache line to the registered processor.
+    // If there is no empty slot, a victim line is evicted, and
+    // invalidate requests are sent to the L1 caches containing copies.
+    // If this line is dirty, the XRAM_RSP FSM send a request to the IXR_CMD 
+    // FSM to save the victim line to the XRAM, and register the write transaction
+    // in the TRT (using the entry previously used by the read transaction).
+    ///////////////////////////////////////////////////////////////////////////////
+
+    switch ( r_xram_rsp_fsm.read() ) {
+
+      ///////////////////
+      case XRAM_RSP_IDLE:	// test if there is a response with a round robin priority
+        {
+          size_t ptr   = r_xram_rsp_trt_index.read();
+          size_t lines = TRANSACTION_TAB_LINES;
+          for(size_t i=0; i<lines; i++){
+            size_t index=(i+ptr+1)%lines;
+            if(r_ixr_rsp_to_xram_rsp_rok[index]){
+              r_xram_rsp_trt_index=index;
+              r_ixr_rsp_to_xram_rsp_rok[index]=false;
+              r_xram_rsp_fsm           = XRAM_RSP_DIR_LOCK;
+              break;
+#ifdef TDEBUG
+	std::cout << "XRAM_RSP FSM in XRAM_RSP_IDLE state" << std::endl;
+#endif
+            }
+          }
+          break;  
+        }
+        ///////////////////////
+      case XRAM_RSP_DIR_LOCK: 	// Take the lock on the directory
+        {
+          if( r_alloc_dir_fsm.read() == ALLOC_DIR_XRAM_RSP ) {
+            r_xram_rsp_fsm           = XRAM_RSP_TRT_COPY;
+#ifdef TDEBUG
+	std::cout << "XRAM_RSP FSM in XRAM_RSP_DIR_LOCK state" << std::endl;
+#endif
+          }
+          break;
+        }
+        ///////////////////////
+      case XRAM_RSP_TRT_COPY:		// Copy the TRT entry in the local buffer and eviction of a cache line
+        {
+          if ( (r_alloc_trt_fsm.read() == ALLOC_TRT_XRAM_RSP) ) {
+            size_t index = r_xram_rsp_trt_index.read();
+            TransactionTabEntry    trt_entry(m_transaction_tab.read(index));	
+
+            r_xram_rsp_trt_buf.copy(trt_entry);  // TRT entry local buffer
+
+            // selects & extracts a victim line from cache
+            size_t way = 0;
+            size_t set = m_y[(vci_addr_t)(trt_entry.nline * m_words * 4)];
+            DirectoryEntry victim(m_cache_directory.select(set, way));
+
+            for (size_t i=0 ; i<m_words ; i++) r_xram_rsp_victim_data[i] = m_cache_data[way][set][i];
+
+            bool inval = (victim.count && victim.valid) ;
+
+            r_xram_rsp_victim_copy      = victim.owner.srcid;
+            r_xram_rsp_victim_copy_inst = victim.owner.inst;
+            r_xram_rsp_victim_count     = victim.count;
+            r_xram_rsp_victim_ptr       = victim.ptr;
+            r_xram_rsp_victim_way       = way;
+            r_xram_rsp_victim_set       = set;
+            r_xram_rsp_victim_nline     = victim.tag*m_sets + set;
+            r_xram_rsp_victim_is_cnt    = victim.is_cnt;
+            r_xram_rsp_victim_inval     = inval ;
+            r_xram_rsp_victim_dirty     = victim.dirty;
+
+            r_xram_rsp_fsm = XRAM_RSP_INVAL_LOCK;
+#ifdef TDEBUG
+	std::cout << "XRAM_RSP FSM in XRAM_RSP_TRT_COPY state" << std::endl;
+	std::cout << "Victim way : " << std::hex << way << " set " << std::hex << set << std::endl;
+	victim.print();
+#endif
+          }
+          break;
+        }
+        ///////////////////////
+      case XRAM_RSP_INVAL_LOCK:
+        {
+          if ( r_alloc_upt_fsm == ALLOC_UPT_XRAM_RSP ) {
+#ifdef IDEBUG
+	std::cout << "XRAM_RSP FSM in XRAM_RSP_INVAL_LOCK state" << std::endl;
+#endif
+            size_t index;
+            if(m_update_tab.search_inval(r_xram_rsp_trt_buf.nline, index)){
+              r_xram_rsp_fsm = XRAM_RSP_INVAL_WAIT;
+#ifdef IDEBUG
+	std::cout << "XRAM_RSP FSM in XRAM_RSP_INVAL_LOCK state to XRAM_RSP_INVAL_WAIT state" << std::endl;
+    std::cout << "A invalidation is already registered at this address" << std::endl;
+	m_update_tab.print();
+#endif
+
+            }
+	    else if(m_update_tab.is_full() && r_xram_rsp_victim_inval.read()){
+	      r_xram_rsp_fsm = XRAM_RSP_INVAL_WAIT;
+#ifdef IDEBUG
+	std::cout << "XRAM_RSP FSM in XRAM_RSP_INVAL_LOCK state to XRAM_RSP_INVAL_WAIT state" << std::endl;
+    std::cout << "The inval tab is full" << std::endl;
+	m_update_tab.print();
+#endif
+	    }
+            else {
+              r_xram_rsp_fsm = XRAM_RSP_DIR_UPDT;
+#ifdef IDEBUG
+	std::cout << "XRAM_RSP FSM in XRAM_RSP_INVAL_LOCK state to XRAM_RSP_DIR_UPDT state" << std::endl;
+	m_update_tab.print();
+#endif
+            }
+          }
+          break;
+        }
+        ///////////////////////
+      case XRAM_RSP_INVAL_WAIT:
+        {
+          r_xram_rsp_fsm = XRAM_RSP_DIR_LOCK;
+          break;
+#ifdef IDEBUG
+	std::cout << "XRAM_RSP FSM in XRAM_RSP_INVAL_WAIT state" << std::endl;
+#endif
+        }
+        ///////////////////////
+      case XRAM_RSP_DIR_UPDT:		// updates the cache (both data & directory)
+        {
+          // signals generation
+          bool inst_read = (r_xram_rsp_trt_buf.trdid & 0x2) && r_xram_rsp_trt_buf.proc_read; // It is an instruction read
+          bool cached_read = (r_xram_rsp_trt_buf.trdid & 0x1) && r_xram_rsp_trt_buf.proc_read ;
+          // update data
+          size_t set   = r_xram_rsp_victim_set.read();
+          size_t way   = r_xram_rsp_victim_way.read();
+          for(size_t i=0; i<m_words ; i++){
+            m_cache_data[way][set][i] = r_xram_rsp_trt_buf.wdata[i];
+          }
+          // compute dirty 
+          bool dirty = false;
+          for(size_t i=0; i<m_words;i++){
+            dirty = dirty || (r_xram_rsp_trt_buf.wdata_be[i] != 0);
+          }
+
+          // update directory
+          DirectoryEntry entry;
+          entry.valid	  = true;
+          entry.is_cnt    = false;
+          entry.lock	  = false;
+          entry.dirty	  = dirty;
+          entry.tag	      = r_xram_rsp_trt_buf.nline / m_sets;
+          entry.ptr       = 0;
+          if(cached_read) {
+            if(inst_read) {
+              entry.inst        = true;
+              entry.owner.srcid = r_xram_rsp_trt_buf.srcid;
+              entry.owner.inst  = true;
+              entry.count       = 1;
+            } else {
+              entry.inst        = false;
+              entry.owner.srcid = r_xram_rsp_trt_buf.srcid;
+              entry.owner.inst  = false;
+              entry.count       = 1;
+            }
+          } else {
+            entry.owner.srcid = 0;
+            entry.owner.inst  = 0;
+            entry.inst        = false;
+            entry.count       = 0;
+          }
+          m_cache_directory.write(set, way, entry);
+#ifdef DDEBUG
+	   std::cout << "printing the entry : " << std::endl;
+	   entry.print();
+	   std::cout << "done" << std::endl;
+#endif
+
+#ifdef TDEBUG
+	std::cout << sc_time_stamp() << " " << name() << " XRAM_RSP_DIR_UPDT transaction table : " << std::endl;
+	for(size_t i = 0 ; i < m_transaction_tab.size() ; i++)
+	  m_transaction_tab.print(i);
+#endif
+
+          if(r_xram_rsp_victim_inval.read()){
+            bool    brdcast = r_xram_rsp_victim_is_cnt.read();
+            size_t index;
+            size_t count_copies = r_xram_rsp_victim_count.read();
+
+            bool	 wok = m_update_tab.set(false,	// it's an inval transaction
+                brdcast,                          // set brdcast bit
+                false,  // it does not need a response
+                0,
+                0,
+                0,
+                r_xram_rsp_victim_nline.read(),
+                count_copies,
+                index);
+
+#ifdef IDEBUG
+            std::cout << "xram_rsp : record invalidation, time = " << std::dec << m_cpt_cycles << std::endl;
+            m_update_tab.print();
+#endif
+            r_xram_rsp_upt_index = index;
+            if(!wok) {
+              assert(false && "mem_cache error : xram_rsp_dir_upt, an update_tab entry was free but write unsuccessful");
+            }
+          }
+          // If the victim is not dirty, we erase the entry in the TRT
+          if      (!r_xram_rsp_victim_dirty.read()){
+	  m_transaction_tab.erase(r_xram_rsp_trt_index.read());
+
+	  }
+          // Next state
+          if      ( r_xram_rsp_victim_dirty.read())       r_xram_rsp_fsm = XRAM_RSP_TRT_DIRTY;
+          else if ( r_xram_rsp_trt_buf.proc_read  )       r_xram_rsp_fsm = XRAM_RSP_DIR_RSP;
+          else if ( r_xram_rsp_victim_inval.read())       r_xram_rsp_fsm = XRAM_RSP_INVAL;
+          else                                            r_xram_rsp_fsm = XRAM_RSP_IDLE;
+          break;
+        }
+        ////////////////////////
+      case XRAM_RSP_TRT_DIRTY:		// set the TRT entry (write line to XRAM) if the victim is dirty
+        {
+          if ( r_alloc_trt_fsm.read() == ALLOC_TRT_XRAM_RSP ) {
+            m_transaction_tab.set(r_xram_rsp_trt_index.read(),
+                false,				// write to XRAM
+                r_xram_rsp_victim_nline.read(), // line index
+                0,
+                0,
+                0,
+                false,
+                0,
+                0,
+                std::vector<be_t>(m_words,0),
+                std::vector<data_t>(m_words,0) );
+#ifdef TDEBUG
+	std::cout << sc_time_stamp() << " " << name() << " XRAM_RSP_TRT_DIRTY transaction table : " << std::endl;
+	for(size_t i = 0 ; i < m_transaction_tab.size() ; i++)
+	  m_transaction_tab.print(i);
+#endif
+
+            if      ( r_xram_rsp_trt_buf.proc_read  )       r_xram_rsp_fsm = XRAM_RSP_DIR_RSP;
+            else if ( r_xram_rsp_victim_inval.read())       r_xram_rsp_fsm = XRAM_RSP_INVAL;
+            else                                            r_xram_rsp_fsm = XRAM_RSP_WRITE_DIRTY;
+          }
+          break;
+        }
+        //////////////////////
+      case XRAM_RSP_DIR_RSP:     // send a request to TGT_RSP FSM in case of read
+        {
+          if ( !r_xram_rsp_to_tgt_rsp_req.read() ) {
+            r_xram_rsp_to_tgt_rsp_srcid = r_xram_rsp_trt_buf.srcid;
+            r_xram_rsp_to_tgt_rsp_trdid = r_xram_rsp_trt_buf.trdid;
+            r_xram_rsp_to_tgt_rsp_pktid = r_xram_rsp_trt_buf.pktid;
+            for (size_t i=0; i < m_words; i++) {
+              r_xram_rsp_to_tgt_rsp_data[i] = r_xram_rsp_trt_buf.wdata[i];
+            } 
+            r_xram_rsp_to_tgt_rsp_word   = r_xram_rsp_trt_buf.word_index;
+            r_xram_rsp_to_tgt_rsp_length = r_xram_rsp_trt_buf.read_length;
+            r_xram_rsp_to_tgt_rsp_req    = true;
+
+            if      ( r_xram_rsp_victim_inval ) r_xram_rsp_fsm = XRAM_RSP_INVAL;
+            else if ( r_xram_rsp_victim_dirty ) r_xram_rsp_fsm = XRAM_RSP_WRITE_DIRTY; 
+            else                                r_xram_rsp_fsm = XRAM_RSP_IDLE;
+
+#ifdef DDEBUG
+	std::cout << "XRAM_RSP FSM in XRAM_RSP_DIR_RSP state" << std::endl;
+#endif
+          }
+          break;
+        }
+        ////////////////////
+      case XRAM_RSP_INVAL:	// send invalidate request to INIT_CMD FSM
+        {
+          if(   !r_xram_rsp_to_init_cmd_multi_req.read() && 
+                !r_xram_rsp_to_init_cmd_brdcast_req.read() ) {	      
+            
+            bool multi_req = !r_xram_rsp_victim_is_cnt.read();
+            bool last_multi_req  = multi_req && (r_xram_rsp_victim_count.read() == 1);
+            bool not_last_multi_req = multi_req && (r_xram_rsp_victim_count.read() != 1);
+
+            r_xram_rsp_to_init_cmd_multi_req    = last_multi_req; 
+            r_xram_rsp_to_init_cmd_brdcast_req  = r_xram_rsp_victim_is_cnt.read();
+            r_xram_rsp_to_init_cmd_nline        = r_xram_rsp_victim_nline.read();
+            r_xram_rsp_to_init_cmd_trdid        = r_xram_rsp_upt_index;
+            xram_rsp_to_init_cmd_fifo_srcid     = r_xram_rsp_victim_copy.read();
+            xram_rsp_to_init_cmd_fifo_inst      = r_xram_rsp_victim_copy_inst.read();
+            xram_rsp_to_init_cmd_fifo_put       = multi_req;
+            
+            r_xram_rsp_next_ptr                 = r_xram_rsp_victim_ptr.read();
+
+            if ( r_xram_rsp_victim_dirty )  r_xram_rsp_fsm = XRAM_RSP_WRITE_DIRTY;
+            else if (not_last_multi_req)    r_xram_rsp_fsm = XRAM_RSP_HEAP_ERASE;
+            else                            r_xram_rsp_fsm = XRAM_RSP_IDLE;
+#ifdef IDEBUG
+	std::cout << "XRAM_RSP FSM in XRAM_RSP_INVAL state" << std::endl;
+#endif
+          }
+          break;
+        }
+        //////////////////////////
+      case XRAM_RSP_WRITE_DIRTY:	// send a write request to IXR_CMD FSM
+        {
+          if ( !r_xram_rsp_to_ixr_cmd_req.read() ) {
+            r_xram_rsp_to_ixr_cmd_req = true;
+            r_xram_rsp_to_ixr_cmd_nline = r_xram_rsp_victim_nline.read();
+            r_xram_rsp_to_ixr_cmd_trdid = r_xram_rsp_trt_index.read();
+            for(size_t i=0; i<m_words ; i++) {
+              r_xram_rsp_to_ixr_cmd_data[i] = r_xram_rsp_victim_data[i];
+            }
+            m_cpt_write_dirty++;
+            bool multi_req = !r_xram_rsp_victim_is_cnt.read() && r_xram_rsp_victim_inval.read();
+            bool not_last_multi_req = multi_req && (r_xram_rsp_victim_count.read() != 1);
+            if ( not_last_multi_req )   r_xram_rsp_fsm = XRAM_RSP_HEAP_ERASE;
+            else                        r_xram_rsp_fsm = XRAM_RSP_IDLE;
+#ifdef TDEBUG
+	std::cout << "XRAM_RSP FSM in XRAM_RSP_WRITE_DIRTY state" << std::endl;
+#endif
+          }
+          break;
+        }
+        //////////////////////////
+      case XRAM_RSP_HEAP_ERASE:	// erase the list of copies and sent invalidations
+        {
+          if( r_alloc_heap_fsm.read() == ALLOC_HEAP_XRAM_RSP ) {
+            HeapEntry entry = m_heap_directory.read(r_xram_rsp_next_ptr.read());
+            xram_rsp_to_init_cmd_fifo_srcid = entry.owner.srcid;
+            xram_rsp_to_init_cmd_fifo_inst  = entry.owner.inst;
+            xram_rsp_to_init_cmd_fifo_put   = true;
+            if( m_xram_rsp_to_init_cmd_inst_fifo.wok() ){
+              r_xram_rsp_next_ptr = entry.next;
+              if( entry.next == r_xram_rsp_next_ptr.read() ){ // last copy
+                r_xram_rsp_to_init_cmd_multi_req = true;
+                r_xram_rsp_fsm = XRAM_RSP_HEAP_LAST;
+              } else {
+                r_xram_rsp_fsm = XRAM_RSP_HEAP_ERASE;
+              }
+            } else {
+              r_xram_rsp_fsm = XRAM_RSP_HEAP_ERASE;
+            }
+          }
+          break;
+        }
+        //////////////////////////
+      case XRAM_RSP_HEAP_LAST:	// last member of the list
+        {
+          assert((r_alloc_heap_fsm.read() == ALLOC_HEAP_XRAM_RSP) &&
+                  "MemCache ERROR : bad HEAP allocation");
+          size_t free_pointer = m_heap_directory.next_free_ptr();
+
+          HeapEntry last_entry;
+          last_entry.owner.srcid = 0;
+          last_entry.owner.inst  = false;
+          if(m_heap_directory.is_full()){
+            last_entry.next     = r_xram_rsp_next_ptr.read();
+            m_heap_directory.unset_full();
+          } else {
+            last_entry.next     = free_pointer;
+          }
+
+          m_heap_directory.write_free_ptr(r_xram_rsp_victim_ptr.read());
+          m_heap_directory.write(r_xram_rsp_next_ptr.read(),last_entry);
+
+          r_xram_rsp_fsm = XRAM_RSP_IDLE;
+
+          break;
+        }
+    } // end swich r_xram_rsp_fsm
+
+    ////////////////////////////////////////////////////////////////////////////////////
+    //		CLEANUP FSM
+    ////////////////////////////////////////////////////////////////////////////////////
+    // The CLEANUP FSM handles the cleanup request from L1 caches.
+    // It accesses the cache directory to update the list of copies.
+    //
+    ////////////////////////////////////////////////////////////////////////////////////
+    switch ( r_cleanup_fsm.read() ) {
+
+      ///////////////////
+      case CLEANUP_IDLE:
+        {
+
+          if ( p_vci_tgt_cleanup.cmdval.read() ) {
+            assert( (p_vci_tgt_cleanup.srcid.read() < m_initiators) &&
+                "VCI_MEM_CACHE error in VCI_MEM_CACHE in the CLEANUP network : The received SRCID is larger than the number of initiators");
+            bool reached = false;
+            for ( size_t index = 0 ; index < ncseg && !reached ; index++ ){
+              if ( m_cseg[index]->contains((addr_t)(p_vci_tgt_cleanup.address.read())) ){
+                reached = true;
+              }
+            }
+            if ( (p_vci_tgt_cleanup.cmd.read() == vci_param::CMD_WRITE) &&
+                (((addr_t)(p_vci_tgt_cleanup.address.read())&0x3) != 0x3) &&
+                reached) {
+
+              m_cpt_cleanup++;
+
+              r_cleanup_nline      = (addr_t)(m_nline[(vci_addr_t)(p_vci_tgt_cleanup.address.read())]) ;
+              r_cleanup_srcid      = p_vci_tgt_cleanup.srcid.read();
+              r_cleanup_trdid      = p_vci_tgt_cleanup.trdid.read();
+              r_cleanup_pktid      = p_vci_tgt_cleanup.pktid.read();
+
+              r_cleanup_fsm        = CLEANUP_DIR_LOCK;
+            }
+          }
+          break;
+        }
+        //////////////////////
+      case CLEANUP_DIR_LOCK:
+        {
+          if ( r_alloc_dir_fsm.read() == ALLOC_DIR_CLEANUP ) {
+
+            // Read the directory
+            size_t way = 0;
+	   addr_t cleanup_address = r_cleanup_nline.read() * m_words * 4;
+           DirectoryEntry entry = m_cache_directory.read(cleanup_address , way);
+#ifdef DDEBUG
+	   std::cout << "In CLEANUP_DIR_LOCK printing the entry of address is : " << std::hex << cleanup_address << std::endl;
+	   entry.print();
+	   std::cout << "done" << std::endl;
+#endif
+            r_cleanup_is_cnt    = entry.is_cnt;
+            r_cleanup_dirty	    = entry.dirty;
+            r_cleanup_tag	    = entry.tag;
+            r_cleanup_lock	    = entry.lock;
+            r_cleanup_inst      = entry.inst;
+            r_cleanup_way	    = way;
+            r_cleanup_copy      = entry.owner.srcid;
+            r_cleanup_copy_inst = entry.owner.inst;
+            r_cleanup_count     = entry.count;
+            r_cleanup_ptr       = entry.ptr;
+
+
+            // In case of hit, the copy must be cleaned in the copies bit-vector
+            if( entry.valid){
+              if ( (entry.count==1) || (entry.is_cnt) )  { // no access to the heap
+                r_cleanup_fsm = CLEANUP_DIR_WRITE;
+              } else {
+                r_cleanup_fsm = CLEANUP_HEAP_LOCK;
+              }
+            } else {
+              r_cleanup_fsm = CLEANUP_UPT_LOCK;
+            }
+          }
+          break;
+        }
+        ///////////////////////
+      case CLEANUP_DIR_WRITE:
+        {
+          assert( (r_alloc_dir_fsm.read() == ALLOC_DIR_CLEANUP ) && 
+                "MemCache ERROR : Bad DIR allocation");
+          size_t way      = r_cleanup_way.read();
+#define L2 soclib::common::uint32_log2
+          size_t set      = m_y[(vci_addr_t)(r_cleanup_nline.read() << (L2(m_words) +2))];
+#undef L2
+          bool cleanup_inst  = r_cleanup_trdid.read() & 0x1; 
+          bool match_srcid   = (r_cleanup_copy.read() == r_cleanup_srcid.read());
+          bool match_inst    = (r_cleanup_copy_inst.read()  == cleanup_inst);
+          bool match         = match_srcid && match_inst;
+
+          // update the cache directory (for the copies)
+          DirectoryEntry entry;
+          entry.valid	= true;
+          entry.is_cnt  = r_cleanup_is_cnt.read();
+          entry.dirty	= r_cleanup_dirty.read();
+          entry.tag	    = r_cleanup_tag.read();
+          entry.lock	= r_cleanup_lock.read();
+          entry.ptr     = r_cleanup_ptr.read();
+          if(r_cleanup_is_cnt.read()) { // Directory is a counter
+            entry.count  = r_cleanup_count.read() -1;
+            if((r_cleanup_count.read()-1) == 0){
+              entry.inst    = false;
+            } else {
+              entry.inst    = r_cleanup_inst.read();
+            }
+            entry.owner.srcid = 0;
+            entry.owner.inst  = 0;
+            // response to the cache 
+            r_cleanup_fsm = CLEANUP_RSP;
+          }
+          else{                         // Directory is a list
+            if(match) { // hit
+              entry.count       = 0; // no more copy
+              entry.owner.srcid = 0;
+              entry.owner.inst  = 0;
+              entry.inst        = false;
+              r_cleanup_fsm     = CLEANUP_RSP; 
+            } else { // miss
+              entry.count       = r_cleanup_count.read();
+              entry.owner.srcid = r_cleanup_copy.read();
+              entry.owner.inst  = r_cleanup_copy_inst.read();
+              entry.inst        = r_cleanup_inst.read();
+              r_cleanup_fsm     = CLEANUP_UPT_LOCK;
+            }
+          }
+          m_cache_directory.write(set, way, entry);  
+
+          break;
+        }
+        /////////////////
+      case CLEANUP_HEAP_LOCK:
+        {
+          if(r_alloc_heap_fsm.read() == ALLOC_HEAP_CLEANUP){
+            size_t way      = r_cleanup_way.read();
+#define L2 soclib::common::uint32_log2
+            size_t set      = m_y[(vci_addr_t)(r_cleanup_nline.read() << (L2(m_words) +2))];
+#undef L2
+            HeapEntry heap_entry = m_heap_directory.read(r_cleanup_ptr.read());
+            bool last = (heap_entry.next == r_cleanup_ptr.read());
+            bool cleanup_inst       = r_cleanup_trdid.read() & 0x1; 
+            bool match_dir_srcid    = (r_cleanup_copy.read() == r_cleanup_srcid.read());
+            bool match_dir_inst     = (r_cleanup_copy_inst.read()  == cleanup_inst);
+            bool match_dir          = match_dir_srcid && match_dir_inst;
+            bool match_heap_srcid   = (heap_entry.owner.srcid == r_cleanup_srcid.read());
+            bool match_heap_inst    = (heap_entry.owner.inst  == cleanup_inst);
+            bool match_heap         = match_heap_srcid && match_heap_inst;
+
+            r_cleanup_prev_ptr = r_cleanup_ptr.read();
+            r_cleanup_prev_srcid = heap_entry.owner.srcid;
+            r_cleanup_prev_inst  = heap_entry.owner.inst;
+
+            if(match_dir){
+              DirectoryEntry dir_entry;
+              dir_entry.valid	    = true;
+              dir_entry.is_cnt      = r_cleanup_is_cnt.read();
+              dir_entry.dirty	    = r_cleanup_dirty.read();
+              dir_entry.tag	        = r_cleanup_tag.read();
+              dir_entry.lock	    = r_cleanup_lock.read();
+              dir_entry.ptr         = heap_entry.next;
+              dir_entry.count       = r_cleanup_count.read()-1;
+              dir_entry.owner.srcid = heap_entry.owner.srcid;
+              dir_entry.owner.inst  = heap_entry.owner.inst;
+              dir_entry.inst        = r_cleanup_inst.read();
+              m_cache_directory.write(set,way,dir_entry);
+              r_cleanup_next_ptr    = r_cleanup_ptr.read();
+              r_cleanup_fsm         = CLEANUP_HEAP_FREE;
+            }
+            else if(match_heap){
+              DirectoryEntry dir_entry;
+              dir_entry.valid	    = true;
+              dir_entry.is_cnt      = r_cleanup_is_cnt.read();
+              dir_entry.dirty	    = r_cleanup_dirty.read();
+              dir_entry.tag	        = r_cleanup_tag.read();
+              dir_entry.lock	    = r_cleanup_lock.read();
+              dir_entry.ptr         = heap_entry.next;
+              dir_entry.count       = r_cleanup_count.read()-1;
+              dir_entry.owner.srcid = r_cleanup_copy.read();
+              dir_entry.owner.inst  = r_cleanup_copy_inst.read();
+              dir_entry.inst        = r_cleanup_inst.read();
+              m_cache_directory.write(set,way,dir_entry);
+              r_cleanup_next_ptr    = r_cleanup_ptr.read();
+              r_cleanup_fsm         = CLEANUP_HEAP_FREE; 
+            }
+            else{
+              if(!last){
+                DirectoryEntry dir_entry;
+                dir_entry.valid	        = true;
+                dir_entry.is_cnt        = r_cleanup_is_cnt.read();
+                dir_entry.dirty	        = r_cleanup_dirty.read();
+                dir_entry.tag	        = r_cleanup_tag.read();
+                dir_entry.lock	        = r_cleanup_lock.read();
+                dir_entry.ptr           = r_cleanup_ptr.read();
+                dir_entry.count         = r_cleanup_count.read()-1;
+                dir_entry.owner.srcid   = r_cleanup_copy.read();
+                dir_entry.owner.inst    = r_cleanup_copy_inst.read();
+                dir_entry.inst          = r_cleanup_inst.read();
+                m_cache_directory.write(set,way,dir_entry);
+
+                r_cleanup_next_ptr = heap_entry.next;
+                r_cleanup_fsm      = CLEANUP_HEAP_SEARCH;
+
+              } else{
+                assert(false && "MemCache ERROR : CLEANUP hit but line not shared");
+              }
+            }
+          }
+          break;
+        }
+        /////////////////
+      case CLEANUP_HEAP_SEARCH:
+        {
+          assert( (r_alloc_heap_fsm.read() == ALLOC_HEAP_CLEANUP) &&
+                    "MemCache ERROR : bad HEAP allocation");
+          HeapEntry heap_entry = m_heap_directory.read(r_cleanup_next_ptr.read());
+          bool last = (heap_entry.next == r_cleanup_next_ptr.read());
+          bool cleanup_inst       = r_cleanup_trdid.read() & 0x1; 
+          bool match_heap_srcid   = (heap_entry.owner.srcid == r_cleanup_srcid.read());
+          bool match_heap_inst    = (heap_entry.owner.inst  == cleanup_inst);
+          bool match_heap         = match_heap_srcid && match_heap_inst;
+
+          if(match_heap){
+            r_cleanup_ptr           = heap_entry.next; // reuse ressources
+            r_cleanup_fsm = CLEANUP_HEAP_CLEAN;
+          }
+          else{
+            if(last) {
+              assert(false && "MemCache ERROR : CLEANUP hit but line not shared");
+            } else {
+              r_cleanup_prev_ptr = r_cleanup_next_ptr.read();
+              r_cleanup_prev_srcid = heap_entry.owner.srcid;
+              r_cleanup_prev_inst  = heap_entry.owner.inst;
+              r_cleanup_next_ptr = heap_entry.next;
+              r_cleanup_fsm      = CLEANUP_HEAP_SEARCH;
+            }
+          }
+
+          break;
+        }
+        /////////////////
+      case CLEANUP_HEAP_CLEAN:
+        {
+          assert( (r_alloc_heap_fsm.read() == ALLOC_HEAP_CLEANUP) &&
+                    "MemCache ERROR : bad HEAP allocation");
+          bool last = (r_cleanup_next_ptr.read() == r_cleanup_ptr.read());
+          HeapEntry heap_entry; 
+          heap_entry.owner.srcid = r_cleanup_prev_srcid.read();
+          heap_entry.owner.inst  = r_cleanup_prev_inst.read();
+          if(last){ // this is the last entry of the list of copies
+            heap_entry.next     = r_cleanup_prev_ptr.read();
+          } else { // this is not the last entry
+            heap_entry.next     = r_cleanup_ptr.read();
+          }
+          m_heap_directory.write(r_cleanup_prev_ptr.read(),heap_entry);
+          r_cleanup_fsm = CLEANUP_HEAP_FREE;
+          break;
+        }
+        /////////////////
+      case CLEANUP_HEAP_FREE:
+        {
+          assert( (r_alloc_heap_fsm.read() == ALLOC_HEAP_CLEANUP) &&
+                    "MemCache ERROR : bad HEAP allocation");
+          HeapEntry heap_entry;
+          heap_entry.owner.srcid = 0;
+          heap_entry.owner.inst  = false;
+          if(m_heap_directory.is_full()){
+            heap_entry.next     = r_cleanup_next_ptr.read();
+          } else {
+            heap_entry.next     = m_heap_directory.next_free_ptr();
+          }
+          m_heap_directory.write(r_cleanup_next_ptr.read(),heap_entry);
+          m_heap_directory.write_free_ptr(r_cleanup_next_ptr.read());
+          m_heap_directory.unset_full();
+          r_cleanup_fsm = CLEANUP_RSP;
+          break;
+        }
+        /////////////////
+      case CLEANUP_UPT_LOCK:
+        {
+          if( r_alloc_upt_fsm.read() == ALLOC_UPT_CLEANUP )
+          {
+            size_t index;
+            bool hit_inval;
+            hit_inval = m_update_tab.search_inval(r_cleanup_nline.read(),index);
+            if(!hit_inval) {
+#ifdef DEBUG_VCI_MEM_CACHE
+              std::cout << "MEM_CACHE WARNING: cleanup with no corresponding entry at address : " << std::hex << (r_cleanup_nline.read()*4*m_words) << std::dec << std::endl;
+#endif
+              r_cleanup_fsm = CLEANUP_RSP;
+            } else {
+              r_cleanup_write_srcid = m_update_tab.srcid(index);
+              r_cleanup_write_trdid = m_update_tab.trdid(index);
+              r_cleanup_write_pktid = m_update_tab.pktid(index);
+              r_cleanup_need_rsp    = m_update_tab.need_rsp(index);
+              r_cleanup_fsm = CLEANUP_UPT_WRITE;
+            }
+            r_cleanup_index.write(index) ; 
+          }
+          break;
+        }
+        /////////////////
+      case CLEANUP_UPT_WRITE:
+        {
+          size_t count = 0;
+          m_update_tab.decrement(r_cleanup_index.read(), count); // &count
+          if(count == 0){
+            m_update_tab.clear(r_cleanup_index.read());
+#ifdef IDEBUG
+	std::cout << sc_time_stamp() << " " << name() << " CLEANUP_UPT_WRITE update table : " << std::endl;
+	m_update_tab.print();
+#endif
+
+            if(r_cleanup_need_rsp.read()){
+              r_cleanup_fsm = CLEANUP_WRITE_RSP ;
+            } else {
+              r_cleanup_fsm = CLEANUP_RSP;
+            }
+          } else {
+            r_cleanup_fsm = CLEANUP_RSP ;
+          }
+          break;
+        }
+        /////////////////
+      case CLEANUP_WRITE_RSP:
+        {
+          if( !r_cleanup_to_tgt_rsp_req.read()) {
+            r_cleanup_to_tgt_rsp_req     = true;
+            r_cleanup_to_tgt_rsp_srcid   = r_cleanup_write_srcid.read();
+            r_cleanup_to_tgt_rsp_trdid   = r_cleanup_write_trdid.read();
+            r_cleanup_to_tgt_rsp_pktid   = r_cleanup_write_pktid.read();
+            r_cleanup_fsm = CLEANUP_RSP;
+          }
+          break;
+        }
+        /////////////////
+      case CLEANUP_RSP:
+        {
+          if(p_vci_tgt_cleanup.rspack)
+            r_cleanup_fsm = CLEANUP_IDLE;
+          break;
+        }
+    } // end switch cleanup fsm
+
+
+    ////////////////////////////////////////////////////////////////////////////////////
+    //		LLSC FSM
+    ////////////////////////////////////////////////////////////////////////////////////
+    // The LLSC FSM handles the LL & SC atomic access.
+    //
+    // For a LL :
+    // It access the directory to check hit / miss.
+    // - In case of hit, the LL request is registered in the Atomic Table and the
+    // response is sent to the requesting processor.
+    // - In case of miss, the LLSC FSM accesses the transaction table. 
+    // If a read transaction to the XRAM for this line already exists, 
+    // or if the transaction table is full, it returns to IDLE state.
+    // Otherwise, a new transaction to the XRAM is initiated.
+    // In both cases, the LL request is not consumed in the FIFO.
+    //
+    // For a SC :
+    // It access the directory to check hit / miss.
+    // - In case of hit, the Atomic Table is checked and the proper response
+    // (true or false is sent to the requesting processor.
+    // - In case of miss, the LLSC FSM accesses the transaction table. 
+    // If a read transaction to the XRAM for this line already exists, 
+    // or if the transaction table is full, it returns to IDLE state. 
+    // Otherwise, a new transaction to the XRAM is initiated.
+    // In both cases, the SC request is not consumed in the FIFO.
+    /////////////////////////////////////////////////////////////////////
+
+    switch ( r_llsc_fsm.read() ) {
+
+      ///////////////
+      case LLSC_IDLE:		// test LL / SC
+        {
+          if( m_cmd_llsc_addr_fifo.rok() ) {
+            if(m_cmd_llsc_sc_fifo.read()){
+              m_cpt_sc++;
+              r_llsc_fsm = SC_DIR_LOCK;
+            }
+            else{
+              m_cpt_ll++;
+              r_llsc_fsm = LL_DIR_LOCK;
+            }
+          }	
+          break;
+        }
+        /////////////////
+      case LL_DIR_LOCK:		// check directory for hit / miss
+        {
+          if( r_alloc_dir_fsm.read() == ALLOC_DIR_LLSC ) {
+            size_t way = 0;
+            DirectoryEntry entry(m_cache_directory.read(m_cmd_llsc_addr_fifo.read(), way));
+            r_llsc_is_cnt     = entry.is_cnt;
+            r_llsc_dirty      = entry.dirty;
+            r_llsc_inst       = entry.inst;
+            r_llsc_tag        = entry.tag;
+            r_llsc_way        = way;
+            r_llsc_copy       = entry.owner.srcid;
+            r_llsc_copy_inst  = entry.owner.inst;
+            r_llsc_count      = entry.count;
+            r_llsc_ptr        = entry.ptr;
+
+            // set Atomic Table
+            m_atomic_tab.set(m_cmd_llsc_srcid_fifo.read(), m_cmd_llsc_addr_fifo.read());
+
+            if ( entry.valid )  r_llsc_fsm = LL_DIR_HIT;
+            else                r_llsc_fsm = LLSC_TRT_LOCK;
+          }
+          break;
+        }
+        ////////////////
+      case LL_DIR_HIT:		// read hit : update the memory cache
+        {
+          size_t way	= r_llsc_way.read();
+          size_t set	= m_y[(vci_addr_t)(m_cmd_llsc_addr_fifo.read())];
+          size_t word	= m_x[(vci_addr_t)(m_cmd_llsc_addr_fifo.read())];
+
+          // update directory (lock bit & copies)
+          DirectoryEntry entry;
+          entry.valid	    = true;
+          entry.is_cnt      = r_llsc_is_cnt.read();
+          entry.dirty	    = r_llsc_dirty.read();
+          entry.lock	    = true;
+          entry.inst        = r_llsc_inst.read();
+          entry.tag	        = r_llsc_tag.read();
+          entry.owner.srcid = r_llsc_copy.read();
+          entry.owner.inst  = r_llsc_copy_inst.read();
+          entry.count       = r_llsc_count.read();
+          entry.ptr         = r_llsc_ptr.read();
+          m_cache_directory.write(set, way, entry);
+
+          // read data in cache
+          r_llsc_data	= m_cache_data[way][set][word];
+
+          r_llsc_fsm 	= LL_RSP;
+          break;
+        }
+        ////////////
+      case LL_RSP:		// request the TGT_RSP FSM to return data
+        {
+          if ( !r_llsc_to_tgt_rsp_req ) {
+            cmd_llsc_fifo_get		= true;
+            r_llsc_to_tgt_rsp_data	= r_llsc_data.read();
+            r_llsc_to_tgt_rsp_srcid	= m_cmd_llsc_srcid_fifo.read();
+            r_llsc_to_tgt_rsp_trdid	= m_cmd_llsc_trdid_fifo.read();
+            r_llsc_to_tgt_rsp_pktid	= m_cmd_llsc_pktid_fifo.read();
+            r_llsc_to_tgt_rsp_req	= true;
+            r_llsc_fsm = LLSC_IDLE;
+          }
+          break;
+        }
+        /////////////////
+      case SC_DIR_LOCK:
+        {
+          if( r_alloc_dir_fsm.read() == ALLOC_DIR_LLSC ) {
+            size_t way = 0;
+            DirectoryEntry entry(m_cache_directory.read(m_cmd_llsc_addr_fifo.read(), way));
+            bool ok = m_atomic_tab.isatomic(m_cmd_llsc_srcid_fifo.read(),m_cmd_llsc_addr_fifo.read());
+            if( ok ) {
+              r_llsc_is_cnt   = entry.is_cnt;
+              r_llsc_dirty    = entry.dirty;
+              r_llsc_tag      = entry.tag;
+              r_llsc_way      = way;
+              r_llsc_copy     = entry.owner.srcid;
+              r_llsc_copy_inst= entry.owner.inst;
+              r_llsc_inst     = entry.inst;
+              r_llsc_ptr      = entry.ptr;
+              r_llsc_count    = entry.count;
+              if ( entry.valid ){
+                if((entry.is_cnt && entry.count) || entry.inst) {
+                  r_llsc_fsm = SC_TRT_LOCK;
+                } else {
+                  r_llsc_fsm = SC_DIR_HIT;
+                }
+              }
+              else r_llsc_fsm = LLSC_TRT_LOCK;
+            } else {
+              r_llsc_fsm = SC_RSP_FALSE;
+            }
+          }
+          break;
+        }
+        ////////////////
+      case SC_DIR_HIT:
+        {
+          size_t way	= r_llsc_way.read();
+          size_t set	= m_y[(vci_addr_t)(m_cmd_llsc_addr_fifo.read())]; 
+          size_t word	= m_x[(vci_addr_t)(m_cmd_llsc_addr_fifo.read())]; 
+
+          // update directory (lock & dirty bits
+          DirectoryEntry entry;
+          entry.valid	    = true;
+          entry.is_cnt      = r_llsc_is_cnt.read();
+          entry.dirty	    = true;
+          entry.lock	    = true;
+          entry.inst        = r_llsc_inst.read();
+          entry.tag	        = r_llsc_tag.read();
+          entry.owner.srcid = r_llsc_copy.read();
+          entry.owner.inst  = r_llsc_copy_inst.read();
+          entry.count       = r_llsc_count.read();
+          entry.ptr         = r_llsc_ptr.read();
+          m_cache_directory.write(set, way, entry);
+
+          if(!r_llsc_count.read()){ // no update
+            // write data in cache
+            m_cache_data[way][set][word] = m_cmd_llsc_wdata_fifo.read();
+            // reset Atomic Table
+            m_atomic_tab.reset(m_cmd_llsc_addr_fifo.read());
+          }
+          
+          if(r_llsc_count.read()) {  // Shared line
+              if( !r_llsc_to_init_cmd_multi_req.read() && 
+                  !r_llsc_to_init_cmd_brdcast_req.read()  )
+                  r_llsc_fsm = SC_UPT_LOCK;
+              else
+                  r_llsc_fsm = SC_WAIT;
+          } else {
+            r_llsc_fsm = SC_RSP_TRUE;
+          }
+          break;
+        }
+        /////////////////////
+      case SC_UPT_LOCK: 	// Try to register the request in Update Table
+        {
+
+          if ( r_alloc_upt_fsm.read() == ALLOC_UPT_LLSC ) {
+            size_t way	= r_llsc_way.read();
+            size_t set	= m_y[(vci_addr_t)(m_cmd_llsc_addr_fifo.read())]; 
+            size_t word	= m_x[(vci_addr_t)(m_cmd_llsc_addr_fifo.read())]; 
+            bool        wok        = false;
+            size_t      index      = 0;
+            size_t      srcid      = m_cmd_llsc_srcid_fifo.read();
+            size_t      trdid      = m_cmd_llsc_trdid_fifo.read();
+            size_t      pktid      = m_cmd_llsc_pktid_fifo.read();
+            addr_t	    nline      = m_nline[(vci_addr_t)(m_cmd_llsc_addr_fifo.read())];
+            size_t      nb_copies  = r_llsc_count.read();
+
+            wok =m_update_tab.set(true,	// it's an update transaction
+                false,                  // it's not a broadcast
+                true,                   // it needs a response
+                srcid,
+                trdid,
+                pktid,
+                nline,
+                nb_copies,
+                index);
+            if(wok){
+              // write data in cache
+              m_cache_data[way][set][word] = m_cmd_llsc_wdata_fifo.read();
+              // reset Atomic Table
+              m_atomic_tab.reset(m_cmd_llsc_addr_fifo.read());
+            }
+#ifdef IDEBUG
+            if(wok){
+	std::cout << sc_time_stamp() << " " << name() << " SC_UPT_LOCK update table : " << std::endl;
+	m_update_tab.print();
+            }
+#endif
+            r_llsc_upt_index = index;
+            //  releases the lock protecting the Update Table and the Directory if no entry...
+            if ( wok ) r_llsc_fsm = SC_HEAP_LOCK;
+            else       r_llsc_fsm = SC_WAIT;
+          }
+          break;
+        }
+        ////////////////////
+      case SC_WAIT: 	// release all locks
+        {
+          r_llsc_fsm = SC_DIR_LOCK;
+          break;
+        }
+        ////////////////////
+      case SC_HEAP_LOCK: 	// lock the heap
+        {
+          if( r_alloc_heap_fsm.read() == ALLOC_HEAP_LLSC ){
+            r_llsc_fsm = SC_UPT_REQ;
+          }
+          break;
+        }
+        ////////////////////
+      case SC_UPT_REQ: 	// Request the update
+        {
+          assert( (r_alloc_heap_fsm.read() == ALLOC_HEAP_LLSC) &&
+                    "MemCache ERROR : bad HEAP allocation");
+          if( !r_llsc_to_init_cmd_multi_req.read() && 
+              !r_llsc_to_init_cmd_brdcast_req.read()  ){
+            r_llsc_to_init_cmd_brdcast_req  = false;
+            r_llsc_to_init_cmd_trdid        = r_llsc_upt_index.read();
+            r_llsc_to_init_cmd_nline        = m_nline[(vci_addr_t)(m_cmd_llsc_addr_fifo.read())];
+            r_llsc_to_init_cmd_index        = m_x[(vci_addr_t)(m_cmd_llsc_addr_fifo.read())];
+            r_llsc_to_init_cmd_wdata        = m_cmd_llsc_wdata_fifo.read();
+
+            // We put the first copy in the fifo
+            llsc_to_init_cmd_fifo_put     = true;
+            llsc_to_init_cmd_fifo_inst    = r_llsc_copy_inst.read();
+            llsc_to_init_cmd_fifo_srcid   = r_llsc_copy.read();
+            if(r_llsc_count.read() == 1){
+              r_llsc_fsm = LLSC_IDLE;
+              cmd_llsc_fifo_get            = true;
+              r_llsc_to_init_cmd_multi_req = true;
+            } else {
+              r_llsc_fsm = SC_UPDATE;
+            }
+          }
+          break;
+        }
+        //////////////////
+      case SC_UPDATE:   	// send a multi-update request to INIT_CMD fsm
+        {
+          assert( (r_alloc_heap_fsm.read() == ALLOC_HEAP_LLSC) &&
+                    "MemCache ERROR : bad HEAP allocation");
+          HeapEntry entry = m_heap_directory.read(r_llsc_ptr.read());
+          llsc_to_init_cmd_fifo_inst  = entry.owner.inst;
+          llsc_to_init_cmd_fifo_srcid = entry.owner.srcid;
+          llsc_to_init_cmd_fifo_put = true;
+
+          if( m_llsc_to_init_cmd_inst_fifo.wok() ){
+            r_llsc_ptr = entry.next;
+            if( entry.next == r_llsc_ptr.read() ) { // last copy
+              r_llsc_to_init_cmd_multi_req = true;
+              r_llsc_fsm = LLSC_IDLE; // Response will be sent after receiving
+                                      // all update responses
+              cmd_llsc_fifo_get         = true;
+            } else {
+              r_llsc_fsm = SC_UPDATE;
+            }
+          } else {
+            r_llsc_fsm = SC_UPDATE;
+          }
+          
+          break;
+        }
+        //////////////////
+      case SC_TRT_LOCK:
+        {
+          if( r_alloc_trt_fsm.read() == ALLOC_TRT_LLSC ) {
+            if( !r_llsc_to_ixr_cmd_req ) { // we can transfer the data to the buffer
+              size_t way	= r_llsc_way.read();
+              size_t set	= m_y[(vci_addr_t)(m_cmd_llsc_addr_fifo.read())];
+              for(size_t i = 0; i<m_words; i++){
+                if(i==m_x[(vci_addr_t)m_cmd_llsc_addr_fifo.read()]) {
+                  r_llsc_to_ixr_cmd_data[i] = m_cmd_llsc_wdata_fifo.read();
+                } else {
+                  r_llsc_to_ixr_cmd_data[i] = m_cache_data[way][set][i];
+                }
+              }
+              size_t wok_index = 0;
+              bool wok = !m_transaction_tab.full(wok_index);
+              if ( wok ) { // set a new entry in TRT
+                r_llsc_trt_index = wok_index;
+                r_llsc_fsm       = SC_INVAL_LOCK; 
+              } else {
+                r_llsc_fsm       = SC_WAIT;
+              }
+            } else {
+              r_llsc_fsm = SC_WAIT;
+            }
+          }
+          break;
+        }
+        //////////////////
+      case SC_INVAL_LOCK:
+        {
+          if ( r_alloc_upt_fsm.read() == ALLOC_UPT_LLSC ) {
+            bool        wok       = false;
+            size_t      index     = 0;
+            size_t      srcid     = m_cmd_llsc_srcid_fifo.read();
+            size_t      trdid     = m_cmd_llsc_trdid_fifo.read();
+            size_t      pktid     = m_cmd_llsc_pktid_fifo.read();
+            addr_t	    nline     = m_nline[(vci_addr_t)(m_cmd_llsc_addr_fifo.read())];
+            size_t      nb_copies = r_llsc_count.read();
+
+            wok =m_update_tab.set(false,	// it's an inval transaction
+                true,                       // it's a broadcast
+                true,                       // it needs a response
+                srcid,
+                trdid,
+                pktid,
+                nline,
+                nb_copies,
+                index);
+#ifdef IDEBUG
+            if(wok){
+	std::cout << sc_time_stamp() << " " << name() << " LLSC_INVAL_LOCK update table : " << std::endl;
+	m_update_tab.print();
+            }
+#endif
+            r_llsc_upt_index = index;
+            //  releases the lock protecting Update Table if no entry...
+            if ( wok ) r_llsc_fsm = SC_DIR_INVAL;
+            else       r_llsc_fsm = SC_WAIT;
+          }
+          break;
+        }
+        //////////////////
+      case SC_DIR_INVAL:
+        {
+          if ( (r_alloc_trt_fsm.read() == ALLOC_TRT_LLSC ) &&
+              (r_alloc_upt_fsm.read() == ALLOC_UPT_LLSC )  &&
+              (r_alloc_dir_fsm.read() == ALLOC_DIR_LLSC ))
+          {
+            m_transaction_tab.set(r_llsc_trt_index.read(),
+                false,				// write request to XRAM
+                m_nline[(vci_addr_t)(m_cmd_llsc_addr_fifo.read())],
+                0,
+                0,
+                0,
+                false,				// not a processor read
+                0,  				// not a single word 
+                0,		        	// word index
+                std::vector<be_t>(m_words,0),
+                std::vector<data_t>(m_words,0));
+#ifdef TDEBUG
+	std::cout << sc_time_stamp() << " " << name() << " SC_DIR_INVAL transaction table : " << std::endl;
+	for(size_t i = 0 ; i < m_transaction_tab.size() ; i++)
+	  m_transaction_tab.print(i);
+#endif
+            // reset Atomic Table
+            m_atomic_tab.reset(m_cmd_llsc_addr_fifo.read());
+
+            // invalidate directory entry
+            DirectoryEntry entry;
+            entry.valid	   = false;
+            entry.dirty	   = false;
+            entry.tag	   = 0;
+            entry.is_cnt   = false;
+            entry.lock	   = false;
+//            entry.d_copies = 0;
+//            entry.i_copies = 0;
+            entry.count    = 0;
+            size_t set	   = m_y[(vci_addr_t)(m_cmd_llsc_addr_fifo.read())];
+            size_t way	   = r_llsc_way.read();
+            m_cache_directory.write(set, way, entry);
+
+            r_llsc_fsm = SC_INVAL;
+          } else {
+            assert(false && "LOCK ERROR in LLSC_FSM, STATE = LLSC_DIR_INVAL");
+          }
+
+          break;
+
+        }
+        //////////////////
+      case SC_INVAL:
+        {
+          if ( !r_llsc_to_init_cmd_multi_req.read() &&
+               !r_llsc_to_init_cmd_brdcast_req.read()) {
+            r_llsc_to_init_cmd_multi_req    = false;
+            r_llsc_to_init_cmd_brdcast_req  = true;
+            r_llsc_to_init_cmd_trdid        = r_llsc_upt_index.read();
+            r_llsc_to_init_cmd_nline        = m_nline[(vci_addr_t)(m_cmd_llsc_addr_fifo.read())];
+            r_llsc_to_init_cmd_index        = 0;
+            r_llsc_to_init_cmd_wdata        = 0;
+
+            r_llsc_fsm = SC_XRAM_SEND;
+            // all update responses
+          }
+
+          break;
+        }
+        //////////////////
+      case SC_XRAM_SEND:
+        {
+          if ( !r_llsc_to_ixr_cmd_req ) {
+            r_llsc_to_ixr_cmd_req     = true;
+            r_llsc_to_ixr_cmd_write   = true;
+            r_llsc_to_ixr_cmd_nline   = m_nline[(vci_addr_t)(m_cmd_llsc_addr_fifo.read())];
+            r_llsc_to_ixr_cmd_trdid   = r_llsc_trt_index.read();
+            if(  r_llsc_is_cnt.read() ||
+                ((!r_llsc_is_cnt.read()) && (r_llsc_count.read()==1)) ){
+              r_llsc_fsm        = LLSC_IDLE;
+              cmd_llsc_fifo_get = true;
+            } else {
+              r_llsc_fsm        = SC_HEAP_ERASE;
+              r_llsc_next_ptr   = r_llsc_ptr.read();
+            }
+          } else {
+            assert( false && "MEM_CACHE, LLSC FSM : SC_XRAM_SEND state : the request should not have been previously set");
+          }
+          break;
+        }
+        //////////////////
+      case SC_HEAP_ERASE:
+        {
+          if(r_alloc_heap_fsm.read() == ALLOC_HEAP_LLSC){
+            HeapEntry next_entry = m_heap_directory.read(r_llsc_next_ptr.read());
+            if( next_entry.next == r_llsc_next_ptr.read()){
+              r_write_fsm = SC_HEAP_LAST;
+            } else {
+              r_llsc_next_ptr = next_entry.next;
+              r_llsc_fsm = SC_HEAP_ERASE;
+            }
+          }
+          break;
+        }
+        //////////////////
+      case SC_HEAP_LAST:
+        {
+          assert((r_alloc_heap_fsm.read() == ALLOC_HEAP_LLSC) &&
+                  "MemCache ERROR : bad HEAP allocation");
+          size_t free_pointer = m_heap_directory.next_free_ptr();
+
+          HeapEntry last_entry;
+          last_entry.owner.srcid = 0;
+          last_entry.owner.inst  = false;
+          if(m_heap_directory.is_full()){
+            last_entry.next     = r_llsc_next_ptr.read();
+            m_heap_directory.unset_full();
+          } else {
+            last_entry.next     = free_pointer;
+          }
+
+          m_heap_directory.write_free_ptr(r_llsc_ptr.read());
+          m_heap_directory.write(r_llsc_next_ptr.read(),last_entry);
+
+          cmd_llsc_fifo_get		= true;
+          r_llsc_fsm = LLSC_IDLE;
+          break;
+        }
+        //////////////////
+      case SC_RSP_FALSE:
+        {
+          if( !r_llsc_to_tgt_rsp_req ) {
+            cmd_llsc_fifo_get		= true;
+            r_llsc_to_tgt_rsp_req	= true;
+            r_llsc_to_tgt_rsp_data	= 1;
+            r_llsc_to_tgt_rsp_srcid	= m_cmd_llsc_srcid_fifo.read();
+            r_llsc_to_tgt_rsp_trdid	= m_cmd_llsc_trdid_fifo.read();
+            r_llsc_to_tgt_rsp_pktid	= m_cmd_llsc_pktid_fifo.read();
+            r_llsc_fsm 			    = LLSC_IDLE;
+          }
+          break;
+        }
+        /////////////////
+      case SC_RSP_TRUE:
+        {
+          if( !r_llsc_to_tgt_rsp_req ) {
+            cmd_llsc_fifo_get	    = true;
+            r_llsc_to_tgt_rsp_req	= true;
+            r_llsc_to_tgt_rsp_data	= 0;
+            r_llsc_to_tgt_rsp_srcid	= m_cmd_llsc_srcid_fifo.read();
+            r_llsc_to_tgt_rsp_trdid	= m_cmd_llsc_trdid_fifo.read();
+            r_llsc_to_tgt_rsp_pktid	= m_cmd_llsc_pktid_fifo.read();
+            r_llsc_fsm 			    = LLSC_IDLE;
+          }
+          break;
+        }
+        ///////////////////
+      case LLSC_TRT_LOCK:         // read or write miss : check the Transaction Table
+        {
+          if( r_alloc_trt_fsm.read() == ALLOC_TRT_LLSC ) {
+            size_t   index = 0;
+            bool hit_read = m_transaction_tab.hit_read(m_nline[(vci_addr_t)m_cmd_llsc_addr_fifo.read()],index);
+            bool hit_write = m_transaction_tab.hit_write(m_nline[(vci_addr_t)m_cmd_llsc_addr_fifo.read()]);
+            bool wok = !m_transaction_tab.full(index);
+
+            if ( hit_read || !wok || hit_write ) {  // missing line already requested or no space in TRT
+              r_llsc_fsm = LLSC_IDLE;
+            } else {
+              r_llsc_trt_index = index;
+              r_llsc_fsm       = LLSC_TRT_SET;
+            }
+          }
+          break;
+        }
+        //////////////////
+      case LLSC_TRT_SET:	// register the XRAM transaction in Transaction Table
+        {
+          if( r_alloc_trt_fsm.read() == ALLOC_TRT_LLSC ) {
+            size_t word	= m_x[(vci_addr_t)(m_cmd_llsc_addr_fifo.read())]; 
+            bool proc_read = !m_cmd_llsc_sc_fifo.read();
+            if(proc_read){
+              m_transaction_tab.set(r_llsc_trt_index.read(),
+                  true,
+                  m_nline[(vci_addr_t)m_cmd_llsc_addr_fifo.read()],
+                  m_cmd_llsc_srcid_fifo.read(),
+                  m_cmd_llsc_trdid_fifo.read(),
+                  m_cmd_llsc_pktid_fifo.read(),
+                  true,
+                  1,
+                  word,
+                  std::vector<be_t>(m_words,0),
+                  std::vector<data_t>(m_words,0));
+            }else{
+              std::vector<be_t> be_vector;
+              std::vector<data_t> data_vector;
+              be_vector.clear();
+              data_vector.clear();
+              // reset Atomic Table
+              m_atomic_tab.reset(m_cmd_llsc_addr_fifo.read());
+              for ( size_t i=0; i<m_words; i++ ) 
+              {   
+                if(i == word){
+                  be_vector.push_back(0xF);
+                  data_vector.push_back(m_cmd_llsc_wdata_fifo.read());
+                } else {
+                  be_vector.push_back(0);
+                  data_vector.push_back(0);
+                }
+              }
+ 
+              m_transaction_tab.set(r_llsc_trt_index.read(),
+                  true,
+                  m_nline[(vci_addr_t)m_cmd_llsc_addr_fifo.read()],
+                  m_cmd_llsc_srcid_fifo.read(),
+                  m_cmd_llsc_trdid_fifo.read(),
+                  m_cmd_llsc_pktid_fifo.read(),
+                  false,
+                  0,
+                  0,
+                  be_vector,
+                  data_vector);
+            }
+#ifdef TDEBUG
+	std::cout << sc_time_stamp() << " " << name() << " LLSC_TRT_SET transaction table : " << std::endl;
+	for(size_t i = 0 ; i < m_transaction_tab.size() ; i++)
+	  m_transaction_tab.print(i);
+#endif
+
+            r_llsc_fsm = LLSC_XRAM_REQ;
+          }
+          break;
+        }
+        ///////////////////
+      case LLSC_XRAM_REQ:	// request the IXR_CMD FSM to fetch the missing line
+        {
+          if ( !r_llsc_to_ixr_cmd_req ) {
+            r_llsc_to_ixr_cmd_req        = true;
+            r_llsc_to_ixr_cmd_write      = false;
+            r_llsc_to_ixr_cmd_trdid      = r_llsc_trt_index.read();
+            r_llsc_to_ixr_cmd_nline      = m_nline[(vci_addr_t)m_cmd_llsc_addr_fifo.read()];
+            if( m_cmd_llsc_sc_fifo.read() ) {
+              r_llsc_fsm                 = SC_RSP_TRUE;
+            } else {
+              cmd_llsc_fifo_get          = true;
+              r_llsc_fsm                 = LLSC_IDLE;
+            }
+          }
+          break;
+        }
+    } // end switch r_llsc_fsm
+
+
+    //////////////////////////////////////////////////////////////////////////////
+    //		INIT_CMD FSM
+    //////////////////////////////////////////////////////////////////////////////
+    // The INIT_CMD fsm controls the VCI CMD initiator port, used to update
+    // or invalidate cache lines in L1 caches.
+    // It implements a round-robin priority between the two following requests:
+    // - r_write_to_init_cmd_req : update request from WRITE FSM 
+    // - r_xram_rsp_to_init_cmd_req : invalidate request from XRAM_RSP FSM 
+    // The inval request is a single cell VCI write command containing the 
+    // index of the line to be invalidated.
+    // The update request is a multi-cells VCI write command : The first cell 
+    // contains the index of the cache line to be updated. The second cell contains 
+    // the index of the first modified word in the line. The following cells
+    // contain the data.
+    ///////////////////////////////////////////////////////////////////////////////
+
+    switch ( r_init_cmd_fsm.read() ) {
+
+      //////////////////////// 
+      case INIT_CMD_UPDT_IDLE:	// Invalidate requests have highest priority
+        {
+
+          if ( m_xram_rsp_to_init_cmd_inst_fifo.rok() ||
+               r_xram_rsp_to_init_cmd_multi_req.read()  ) {
+            r_init_cmd_fsm = INIT_CMD_INVAL_NLINE;
+            m_cpt_inval++;
+          } else if ( r_xram_rsp_to_init_cmd_brdcast_req.read() ) {
+            r_init_cmd_fsm = INIT_CMD_XRAM_BRDCAST;
+            m_cpt_inval++;
+          } else if ( m_write_to_init_cmd_inst_fifo.rok() ||
+                      r_write_to_init_cmd_multi_req.read() ) {
+            r_init_cmd_fsm = INIT_CMD_UPDT_NLINE;
+            m_cpt_update++;
+          } else if ( r_write_to_init_cmd_brdcast_req.read() ){
+            r_init_cmd_fsm = INIT_CMD_WRITE_BRDCAST;
+            m_cpt_inval++;
+          } else if ( m_llsc_to_init_cmd_inst_fifo.rok() ||
+                      r_llsc_to_init_cmd_multi_req.read()  ) {
+            r_init_cmd_fsm = INIT_CMD_SC_UPDT_NLINE;
+            m_cpt_update++;
+          } else if( r_llsc_to_init_cmd_brdcast_req.read() ){
+            r_init_cmd_fsm = INIT_CMD_SC_BRDCAST;
+            m_cpt_inval++;
+          }
+          break;
+        }
+        /////////////////////////
+      case INIT_CMD_INVAL_IDLE:	// Update requests have highest priority
+        {
+          if ( m_write_to_init_cmd_inst_fifo.rok() ||
+               r_write_to_init_cmd_multi_req.read() ) {
+            r_init_cmd_fsm = INIT_CMD_UPDT_NLINE;
+            m_cpt_update++;
+          } else if ( r_write_to_init_cmd_brdcast_req.read() ){
+            r_init_cmd_fsm = INIT_CMD_WRITE_BRDCAST;
+            m_cpt_inval++;
+          } else if ( m_llsc_to_init_cmd_inst_fifo.rok() ||
+                      r_llsc_to_init_cmd_multi_req.read()  ) {
+            r_init_cmd_fsm = INIT_CMD_SC_UPDT_NLINE;
+            m_cpt_update++;
+          } else if( r_llsc_to_init_cmd_brdcast_req.read() ){
+            r_init_cmd_fsm = INIT_CMD_SC_BRDCAST;
+            m_cpt_inval++;
+          } else if ( m_xram_rsp_to_init_cmd_inst_fifo.rok() ||
+                      r_xram_rsp_to_init_cmd_multi_req.read()  ) {
+            r_init_cmd_fsm = INIT_CMD_INVAL_NLINE;
+            m_cpt_inval++;
+          } else if ( r_xram_rsp_to_init_cmd_brdcast_req.read() ) {
+            r_init_cmd_fsm = INIT_CMD_XRAM_BRDCAST;
+            m_cpt_inval++;
+          }
+          break;
+        }
+        /////////////////////////
+      case INIT_CMD_SC_UPDT_IDLE:	// Update requests for SCs have highest priority
+        {
+          if ( m_llsc_to_init_cmd_inst_fifo.rok() ||
+               r_llsc_to_init_cmd_multi_req.read()  ) {
+            r_init_cmd_fsm = INIT_CMD_SC_UPDT_NLINE;
+            m_cpt_update++;
+          } else if( r_llsc_to_init_cmd_brdcast_req.read() ){
+            r_init_cmd_fsm = INIT_CMD_SC_BRDCAST;
+            m_cpt_inval++;
+          } else if ( m_xram_rsp_to_init_cmd_inst_fifo.rok() ||
+                      r_xram_rsp_to_init_cmd_multi_req.read()  ) {
+            r_init_cmd_fsm = INIT_CMD_INVAL_NLINE;
+            m_cpt_inval++;
+          } else if ( r_xram_rsp_to_init_cmd_brdcast_req.read() ) {
+            r_init_cmd_fsm = INIT_CMD_XRAM_BRDCAST;
+            m_cpt_inval++;
+          } else if ( m_write_to_init_cmd_inst_fifo.rok() ||
+                      r_write_to_init_cmd_multi_req.read() ) {
+            r_init_cmd_fsm = INIT_CMD_UPDT_NLINE;
+            m_cpt_update++;
+          } else if ( r_write_to_init_cmd_brdcast_req.read() ){
+            r_init_cmd_fsm = INIT_CMD_WRITE_BRDCAST;
+            m_cpt_inval++;
+          }
+          break;
+        }
+        ////////////////////////
+      case INIT_CMD_INVAL_NLINE:	// send the cache line index
+        {
+          if ( m_xram_rsp_to_init_cmd_inst_fifo.rok() ){
+            if ( p_vci_ini.cmdack ) {
+              m_cpt_inval_mult++;
+              r_init_cmd_fsm = INIT_CMD_INVAL_NLINE;
+              xram_rsp_to_init_cmd_fifo_get = true;
+            }
+          } else {
+            if( r_xram_rsp_to_init_cmd_multi_req.read() ){
+              r_xram_rsp_to_init_cmd_multi_req = false;
+            } 
+            r_init_cmd_fsm = INIT_CMD_INVAL_IDLE;
+          }
+          break;
+        }
+        ////////////////////////
+      case INIT_CMD_XRAM_BRDCAST:	// send the cache line index
+        {
+          if ( p_vci_ini.cmdack ) {
+            m_cpt_inval_brdcast++;
+            r_init_cmd_fsm = INIT_CMD_INVAL_IDLE;
+            r_xram_rsp_to_init_cmd_brdcast_req = false;
+          }
+          break;
+        }
+        /////////////////////////
+      case INIT_CMD_WRITE_BRDCAST:
+        {
+          if( p_vci_ini.cmdack ) {
+            m_cpt_inval_brdcast++;
+            r_write_to_init_cmd_brdcast_req = false;
+            r_init_cmd_fsm = INIT_CMD_UPDT_IDLE;
+          }
+          break;
+        }
+        /////////////////////////
+      case INIT_CMD_UPDT_NLINE:	// send the cache line index
+        {
+          if ( m_write_to_init_cmd_inst_fifo.rok() ) {
+            if ( p_vci_ini.cmdack ){
+              m_cpt_update_mult++;
+              r_init_cmd_fsm = INIT_CMD_UPDT_INDEX;
+            }
+          } else {
+            if ( r_write_to_init_cmd_multi_req.read() ){
+              r_write_to_init_cmd_multi_req = false;
+            }
+            r_init_cmd_fsm = INIT_CMD_UPDT_IDLE;
+          }
+          break;
+        }
+        /////////////////////////
+      case INIT_CMD_UPDT_INDEX:	// send the first word index
+        {
+          r_init_cmd_cpt    = 0;
+          if ( p_vci_ini.cmdack )  r_init_cmd_fsm = INIT_CMD_UPDT_DATA;
+          break;
+        }
+        ////////////////////////
+      case INIT_CMD_UPDT_DATA:	// send the data
+        {
+          if ( p_vci_ini.cmdack ) {
+            if ( r_init_cmd_cpt.read() == (r_write_to_init_cmd_count.read()-1) ) {
+              r_init_cmd_fsm = INIT_CMD_UPDT_NLINE;
+              write_to_init_cmd_fifo_get = true;
+            } else {
+              r_init_cmd_cpt = r_init_cmd_cpt.read() + 1;
+            }
+          }
+          break;
+        }
+        /////////////////////////
+      case INIT_CMD_SC_BRDCAST:
+        {
+          if( p_vci_ini.cmdack ) {
+            m_cpt_inval_brdcast++;
+            r_llsc_to_init_cmd_brdcast_req = false;
+            r_init_cmd_fsm = INIT_CMD_SC_UPDT_IDLE;
+          }
+          break;
+        }
+        /////////////////////////
+      case INIT_CMD_SC_UPDT_NLINE:	// send the cache line index
+        {
+          if ( m_llsc_to_init_cmd_inst_fifo.rok() ){
+            if ( p_vci_ini.cmdack ){
+              m_cpt_update_mult++;
+              r_init_cmd_fsm = INIT_CMD_SC_UPDT_INDEX;
+            }
+          } else {
+            if( r_llsc_to_init_cmd_multi_req.read() ){
+              r_llsc_to_init_cmd_multi_req = false;
+            }
+            r_init_cmd_fsm = INIT_CMD_SC_UPDT_IDLE;
+          }
+          break;
+        }
+        /////////////////////////
+      case INIT_CMD_SC_UPDT_INDEX:	// send the first word index
+        {
+          if ( p_vci_ini.cmdack )  r_init_cmd_fsm = INIT_CMD_SC_UPDT_DATA;
+          break;
+        }
+        ////////////////////////
+      case INIT_CMD_SC_UPDT_DATA:	// send the data
+        {
+          if ( p_vci_ini.cmdack ) {
+            llsc_to_init_cmd_fifo_get = true;
+            r_init_cmd_fsm = INIT_CMD_SC_UPDT_NLINE;
+          }
+          break;
+        }
+
+    } // end switch r_init_cmd_fsm
+
+    /////////////////////////////////////////////////////////////////////
+    //		TGT_RSP FSM
+    /////////////////////////////////////////////////////////////////////
+    // The TGT_RSP fsm sends the responses on the VCI target port
+    // with a round robin priority between six requests :
+    // - r_read_to_tgt_rsp_req
+    // - r_write_to_tgt_rsp_req
+    // - r_llsc_to_tgt_rsp_req
+    // - r_cleanup_to_tgt_rsp_req
+    // - r_init_rsp_to_tgt_rsp_req
+    // - r_xram_rsp_to_tgt_rsp_req
+    // The  ordering is :  read > write > llsc > cleanup > xram > init
+    /////////////////////////////////////////////////////////////////////
+
+    switch ( r_tgt_rsp_fsm.read() ) {
+
+      ///////////////////////
+      case TGT_RSP_READ_IDLE:		// write requests have the highest priority
+        {
+          if      ( r_write_to_tgt_rsp_req    ) r_tgt_rsp_fsm = TGT_RSP_WRITE;
+          else if ( r_llsc_to_tgt_rsp_req     ) r_tgt_rsp_fsm = TGT_RSP_LLSC;
+          else if ( r_xram_rsp_to_tgt_rsp_req ) {
+            r_tgt_rsp_fsm = TGT_RSP_XRAM;
+            r_tgt_rsp_cpt = r_xram_rsp_to_tgt_rsp_word.read();
+          }
+          else if ( r_init_rsp_to_tgt_rsp_req ) r_tgt_rsp_fsm = TGT_RSP_INIT;
+          else if ( r_cleanup_to_tgt_rsp_req  ) r_tgt_rsp_fsm = TGT_RSP_CLEANUP;
+          else if ( r_read_to_tgt_rsp_req     ) {
+            r_tgt_rsp_fsm = TGT_RSP_READ;
+            r_tgt_rsp_cpt = r_read_to_tgt_rsp_word.read();
+          }
+          break;
+        }
+        ////////////////////////
+      case TGT_RSP_WRITE_IDLE:		// llsc requests have the highest priority
+        {
+          if      ( r_llsc_to_tgt_rsp_req     ) r_tgt_rsp_fsm = TGT_RSP_LLSC;
+          else if ( r_xram_rsp_to_tgt_rsp_req ) {
+            r_tgt_rsp_fsm = TGT_RSP_XRAM;
+            r_tgt_rsp_cpt = r_xram_rsp_to_tgt_rsp_word.read();
+          }
+          else if ( r_init_rsp_to_tgt_rsp_req ) r_tgt_rsp_fsm = TGT_RSP_INIT;
+          else if ( r_cleanup_to_tgt_rsp_req  ) r_tgt_rsp_fsm = TGT_RSP_CLEANUP;
+          else if ( r_read_to_tgt_rsp_req     ) {
+            r_tgt_rsp_fsm = TGT_RSP_READ;
+            r_tgt_rsp_cpt = r_read_to_tgt_rsp_word.read();
+          }
+
+          else if ( r_write_to_tgt_rsp_req    ) r_tgt_rsp_fsm = TGT_RSP_WRITE;
+          break;
+        }
+        ///////////////////////
+      case TGT_RSP_LLSC_IDLE:		// cleanup requests have the highest priority
+        {
+          if ( r_xram_rsp_to_tgt_rsp_req )  {
+            r_tgt_rsp_fsm = TGT_RSP_XRAM;
+            r_tgt_rsp_cpt = r_xram_rsp_to_tgt_rsp_word.read();
+          }
+          else if ( r_init_rsp_to_tgt_rsp_req ) r_tgt_rsp_fsm = TGT_RSP_INIT;
+          else if ( r_cleanup_to_tgt_rsp_req  ) r_tgt_rsp_fsm = TGT_RSP_CLEANUP;
+          else if ( r_read_to_tgt_rsp_req     ) {
+            r_tgt_rsp_fsm = TGT_RSP_READ;
+            r_tgt_rsp_cpt = r_read_to_tgt_rsp_word.read();
+          }
+          else if ( r_write_to_tgt_rsp_req    ) r_tgt_rsp_fsm = TGT_RSP_WRITE;
+          else if ( r_llsc_to_tgt_rsp_req     ) r_tgt_rsp_fsm = TGT_RSP_LLSC;
+          break;
+        }
+      case TGT_RSP_XRAM_IDLE:		// init requests have the highest priority
+        {
+
+          if      ( r_init_rsp_to_tgt_rsp_req ) r_tgt_rsp_fsm = TGT_RSP_INIT;
+          else if ( r_cleanup_to_tgt_rsp_req  ) r_tgt_rsp_fsm = TGT_RSP_CLEANUP;
+          else if ( r_read_to_tgt_rsp_req     ) {
+            r_tgt_rsp_fsm = TGT_RSP_READ;
+            r_tgt_rsp_cpt = r_read_to_tgt_rsp_word.read();
+          }
+          else if ( r_write_to_tgt_rsp_req    ) r_tgt_rsp_fsm = TGT_RSP_WRITE;
+          else if ( r_llsc_to_tgt_rsp_req     ) r_tgt_rsp_fsm = TGT_RSP_LLSC;
+          else if ( r_xram_rsp_to_tgt_rsp_req )  {
+            r_tgt_rsp_fsm = TGT_RSP_XRAM;
+            r_tgt_rsp_cpt = r_xram_rsp_to_tgt_rsp_word.read();
+          }
+          break;
+        }
+        ///////////////////////
+      case TGT_RSP_INIT_IDLE:		// cleanup requests have the highest priority
+        {
+          if      ( r_cleanup_to_tgt_rsp_req  ) r_tgt_rsp_fsm = TGT_RSP_CLEANUP;
+          else if ( r_read_to_tgt_rsp_req     ) {
+            r_tgt_rsp_fsm = TGT_RSP_READ;
+            r_tgt_rsp_cpt = r_read_to_tgt_rsp_word.read();
+          }
+          else if ( r_write_to_tgt_rsp_req    ) r_tgt_rsp_fsm = TGT_RSP_WRITE;
+          else if ( r_llsc_to_tgt_rsp_req     ) r_tgt_rsp_fsm = TGT_RSP_LLSC;
+          else if ( r_xram_rsp_to_tgt_rsp_req ) {
+            r_tgt_rsp_fsm = TGT_RSP_XRAM;
+            r_tgt_rsp_cpt = r_xram_rsp_to_tgt_rsp_word.read();
+          }
+          else if ( r_init_rsp_to_tgt_rsp_req ) r_tgt_rsp_fsm = TGT_RSP_INIT;
+          break;
+        }
+        ///////////////////////
+      case TGT_RSP_CLEANUP_IDLE:		// read requests have the highest priority
+        {
+          if      ( r_read_to_tgt_rsp_req     ) {
+            r_tgt_rsp_fsm = TGT_RSP_READ;
+            r_tgt_rsp_cpt = r_read_to_tgt_rsp_word.read();
+          }
+          else if ( r_write_to_tgt_rsp_req    ) r_tgt_rsp_fsm = TGT_RSP_WRITE;
+          else if ( r_llsc_to_tgt_rsp_req     ) r_tgt_rsp_fsm = TGT_RSP_LLSC;
+          else if ( r_xram_rsp_to_tgt_rsp_req ) {
+            r_tgt_rsp_fsm = TGT_RSP_XRAM;
+            r_tgt_rsp_cpt = r_xram_rsp_to_tgt_rsp_word.read();
+          }
+          else if ( r_init_rsp_to_tgt_rsp_req ) r_tgt_rsp_fsm = TGT_RSP_INIT;
+          else if ( r_cleanup_to_tgt_rsp_req  ) r_tgt_rsp_fsm = TGT_RSP_CLEANUP;
+          break;
+        }
+        ///////////////////////
+      case TGT_RSP_READ:		// send the response
+        {
+          if ( p_vci_tgt.rspack ) {
+            if ( r_tgt_rsp_cpt.read() == (r_read_to_tgt_rsp_word.read()+r_read_to_tgt_rsp_length-1) ) {
+              r_tgt_rsp_fsm = TGT_RSP_READ_IDLE;
+              r_read_to_tgt_rsp_req = false;
+            } else {
+              r_tgt_rsp_cpt = r_tgt_rsp_cpt.read() + 1;
+            }
+          }
+          break;
+        }
+        ///////////////////
+      case TGT_RSP_WRITE:		// send the write acknowledge
+        {
+          if ( p_vci_tgt.rspack ) {
+            r_tgt_rsp_fsm = TGT_RSP_WRITE_IDLE;
+            r_write_to_tgt_rsp_req = false;
+          }
+          break;
+        }
+        ///////////////////
+      case TGT_RSP_CLEANUP:		// send the write acknowledge
+        {
+          if ( p_vci_tgt.rspack ) {
+            r_tgt_rsp_fsm = TGT_RSP_CLEANUP_IDLE;
+            r_cleanup_to_tgt_rsp_req = false;
+          }
+          break;
+        }
+        //////////////////
+      case TGT_RSP_LLSC:		// send one atomic word response
+        {
+          if ( p_vci_tgt.rspack ) {
+            r_tgt_rsp_fsm = TGT_RSP_LLSC_IDLE;
+            r_llsc_to_tgt_rsp_req = false;
+          }
+          break;
+        }
+
+        ///////////////////////
+      case TGT_RSP_XRAM:		// send the response
+        {
+          if ( p_vci_tgt.rspack ) {
+            if ( r_tgt_rsp_cpt.read() == (r_xram_rsp_to_tgt_rsp_word.read()+r_xram_rsp_to_tgt_rsp_length.read()-1)) {
+              r_tgt_rsp_fsm = TGT_RSP_XRAM_IDLE;
+              r_xram_rsp_to_tgt_rsp_req = false;
+            } else {
+              r_tgt_rsp_cpt = r_tgt_rsp_cpt.read() + 1;
+            }
+          }
+          break;
+        }
+        ///////////////////
+      case TGT_RSP_INIT:		// send the pending write acknowledge
+        {
+          if ( p_vci_tgt.rspack ) {
+            r_tgt_rsp_fsm = TGT_RSP_INIT_IDLE;
+            r_init_rsp_to_tgt_rsp_req = false;
+          }
+          break;
+        }
+    } // end switch tgt_rsp_fsm
+    ////////////////////////////////////////////////////////////////////////////////////
+    //		NEW ALLOC_UPT FSM
+    ////////////////////////////////////////////////////////////////////////////////////
+    // The ALLOC_UPT FSM allocates the access to the Update/Inval Table (UPT).
+    // with a round robin priority between three FSMs : INIT_RSP > WRITE > XRAM_RSP > CLEANUP 
+    // - The WRITE FSM initiates update transactions and sets  new entry in UPT.
+    // - The XRAM_RSP FSM initiates inval transactions and sets  new entry in UPT.
+    // - The INIT_RSP FSM complete those trasactions and erase the UPT entry.
+    // - The CLEANUP  FSM decrement an entry in UPT.
+    // The resource is always allocated.
+    /////////////////////////////////////////////////////////////////////////////////////
+
+    switch ( r_alloc_upt_fsm.read() ) {
+
+      ////////////////////////
+      case ALLOC_UPT_INIT_RSP:
+        if ( (r_init_rsp_fsm.read() != INIT_RSP_UPT_LOCK) && 
+             (r_init_rsp_fsm.read() != INIT_RSP_UPT_CLEAR) ) 
+        {
+          if      ((r_write_fsm.read() == WRITE_UPT_LOCK) ||
+                   (r_write_fsm.read() == WRITE_INVAL_LOCK))        r_alloc_upt_fsm = ALLOC_UPT_WRITE;
+          else if (r_xram_rsp_fsm.read() == XRAM_RSP_INVAL_LOCK)    r_alloc_upt_fsm = ALLOC_UPT_XRAM_RSP;
+          else if (r_cleanup_fsm.read() == CLEANUP_UPT_LOCK)        r_alloc_upt_fsm = ALLOC_UPT_CLEANUP;
+          else if ((r_llsc_fsm.read() == SC_UPT_LOCK) ||
+                   (r_llsc_fsm.read() == SC_INVAL_LOCK))            r_alloc_upt_fsm = ALLOC_UPT_LLSC;
+        }
+        break;
+
+        /////////////////////
+      case ALLOC_UPT_WRITE:
+        if ( (r_write_fsm.read() != WRITE_UPT_LOCK) &&
+             (r_write_fsm.read() != WRITE_INVAL_LOCK)) 
+        {
+          if      (r_xram_rsp_fsm.read() == XRAM_RSP_INVAL_LOCK)    r_alloc_upt_fsm = ALLOC_UPT_XRAM_RSP;
+          else if (r_cleanup_fsm.read() == CLEANUP_UPT_LOCK)        r_alloc_upt_fsm = ALLOC_UPT_CLEANUP;
+          else if ((r_llsc_fsm.read() == SC_UPT_LOCK) ||
+                   (r_llsc_fsm.read() == SC_INVAL_LOCK))            r_alloc_upt_fsm = ALLOC_UPT_LLSC;
+          else if (r_init_rsp_fsm.read() == INIT_RSP_UPT_LOCK)      r_alloc_upt_fsm = ALLOC_UPT_INIT_RSP;
+        }
+        break;
+
+        ////////////////////////
+      case ALLOC_UPT_XRAM_RSP:
+        if (r_xram_rsp_fsm.read() != XRAM_RSP_INVAL_LOCK) 
+        { 
+          if       (r_cleanup_fsm.read() == CLEANUP_UPT_LOCK)       r_alloc_upt_fsm = ALLOC_UPT_CLEANUP;
+          else if ((r_llsc_fsm.read() == SC_UPT_LOCK) ||
+                   (r_llsc_fsm.read() == SC_INVAL_LOCK))            r_alloc_upt_fsm = ALLOC_UPT_LLSC;
+          else if  (r_init_rsp_fsm.read() == INIT_RSP_UPT_LOCK)     r_alloc_upt_fsm = ALLOC_UPT_INIT_RSP;
+          else if ((r_write_fsm.read() == WRITE_UPT_LOCK)   ||
+                   (r_write_fsm.read() == WRITE_INVAL_LOCK))        r_alloc_upt_fsm = ALLOC_UPT_WRITE;
+        }
+        break;
+
+        //////////////////////////
+      case ALLOC_UPT_CLEANUP:
+        if(r_cleanup_fsm.read() != CLEANUP_UPT_LOCK )
+        {
+          if      ((r_llsc_fsm.read() == SC_UPT_LOCK) ||
+                   (r_llsc_fsm.read() == SC_INVAL_LOCK))            r_alloc_upt_fsm = ALLOC_UPT_LLSC;
+          else if  (r_init_rsp_fsm.read() == INIT_RSP_UPT_LOCK)     r_alloc_upt_fsm = ALLOC_UPT_INIT_RSP;
+          else if ((r_write_fsm.read() == WRITE_UPT_LOCK) ||
+                   (r_write_fsm.read() == WRITE_INVAL_LOCK))        r_alloc_upt_fsm = ALLOC_UPT_WRITE;
+          else if (r_xram_rsp_fsm.read() == XRAM_RSP_INVAL_LOCK)    r_alloc_upt_fsm = ALLOC_UPT_XRAM_RSP;
+        }
+        break;
+        
+        //////////////////////////
+      case ALLOC_UPT_LLSC:
+        if( (r_llsc_fsm.read() != SC_UPT_LOCK) && 
+            (r_llsc_fsm.read() != SC_INVAL_LOCK))
+        {
+          if      (r_init_rsp_fsm.read() == INIT_RSP_UPT_LOCK)      r_alloc_upt_fsm = ALLOC_UPT_INIT_RSP;
+          else if ((r_write_fsm.read() == WRITE_UPT_LOCK) ||
+                   (r_write_fsm.read() == WRITE_INVAL_LOCK))        r_alloc_upt_fsm = ALLOC_UPT_WRITE;
+          else if (r_xram_rsp_fsm.read() == XRAM_RSP_INVAL_LOCK)    r_alloc_upt_fsm = ALLOC_UPT_XRAM_RSP;
+          else if (r_cleanup_fsm.read() == CLEANUP_UPT_LOCK)        r_alloc_upt_fsm = ALLOC_UPT_CLEANUP;
+        }
+        break;
+
+    } // end switch r_alloc_upt_fsm
+
+    ////////////////////////////////////////////////////////////////////////////////////
+    //		ALLOC_DIR FSM
+    ////////////////////////////////////////////////////////////////////////////////////
+    // The ALLOC_DIR FSM allocates the access to the directory and
+    // the data cache with a round robin priority between 5 user FSMs :
+    // The cyclic ordering is READ > WRITE > LLSC > CLEANUP > XRAM_RSP
+    // The ressource is always allocated.
+    /////////////////////////////////////////////////////////////////////////////////////
+
+    switch ( r_alloc_dir_fsm.read() ) {
+
+      ////////////////////
+      case ALLOC_DIR_READ:
+        if ( ( (r_read_fsm.read() != READ_DIR_LOCK) &&
+              (r_read_fsm.read() != READ_TRT_LOCK)  &&
+              (r_read_fsm.read() != READ_HEAP_LOCK))
+            ||
+            ( (r_read_fsm.read()        == READ_HEAP_LOCK) &&
+              (r_alloc_heap_fsm.read()  == ALLOC_HEAP_READ) )
+            ||
+            ( (r_read_fsm.read()      == READ_TRT_LOCK)  &&
+              (r_alloc_trt_fsm.read() == ALLOC_TRT_READ)    )  ) 
+        {
+          if        (r_write_fsm.read() == WRITE_DIR_LOCK)          r_alloc_dir_fsm = ALLOC_DIR_WRITE;
+          else if   ((r_llsc_fsm.read() == LL_DIR_LOCK) || 
+                    (r_llsc_fsm.read() == SC_DIR_LOCK))             r_alloc_dir_fsm = ALLOC_DIR_LLSC;
+          else if   (r_cleanup_fsm.read() == CLEANUP_DIR_LOCK)      r_alloc_dir_fsm = ALLOC_DIR_CLEANUP;
+          else if   (r_xram_rsp_fsm.read() == XRAM_RSP_DIR_LOCK)    r_alloc_dir_fsm = ALLOC_DIR_XRAM_RSP;
+        }
+        break;
+
+        /////////////////////
+      case ALLOC_DIR_WRITE:
+        if ( ( (r_write_fsm.read() != WRITE_DIR_LOCK)     &&
+              (r_write_fsm.read() != WRITE_TRT_LOCK)     &&
+              (r_write_fsm.read() != WRITE_DIR_HIT_READ) &&
+              (r_write_fsm.read() != WRITE_DIR_HIT) &&
+              (r_write_fsm.read() != WRITE_TRT_WRITE_LOCK) &&
+              (r_write_fsm.read() != WRITE_INVAL_LOCK) &&
+              (r_write_fsm.read() != WRITE_UPT_LOCK) &&
+              (r_write_fsm.read() != WRITE_HEAP_LOCK))
+            ||
+            ( (r_write_fsm.read()       == WRITE_HEAP_LOCK) &&
+              (r_alloc_heap_fsm.read()  == ALLOC_HEAP_WRITE) )
+            ||
+            ( (r_write_fsm.read()     == WRITE_TRT_LOCK) &&
+              (r_alloc_trt_fsm.read() == ALLOC_TRT_WRITE)   )   )
+        {
+          if        ((r_llsc_fsm.read() == LL_DIR_LOCK) || 
+                    (r_llsc_fsm.read() == SC_DIR_LOCK))             r_alloc_dir_fsm = ALLOC_DIR_LLSC;
+          else if   (r_cleanup_fsm.read() == CLEANUP_DIR_LOCK)      r_alloc_dir_fsm = ALLOC_DIR_CLEANUP;
+          else if   (r_xram_rsp_fsm.read() == XRAM_RSP_DIR_LOCK)    r_alloc_dir_fsm = ALLOC_DIR_XRAM_RSP;
+          else if   (r_read_fsm.read() == READ_DIR_LOCK) 	        r_alloc_dir_fsm = ALLOC_DIR_READ;
+        }
+        break;
+
+        ////////////////////
+      case ALLOC_DIR_LLSC:
+        if ( ( (r_llsc_fsm.read() != LL_DIR_LOCK)    &&
+              (r_llsc_fsm.read() != LL_DIR_HIT )    &&
+              (r_llsc_fsm.read() != SC_DIR_LOCK)    &&
+              (r_llsc_fsm.read() != SC_DIR_HIT )    &&
+              (r_llsc_fsm.read() != LLSC_TRT_LOCK ) &&
+              (r_llsc_fsm.read() != SC_TRT_LOCK)    &&
+              (r_llsc_fsm.read() != SC_INVAL_LOCK)  &&
+              (r_llsc_fsm.read() != SC_UPT_LOCK)    &&
+              (r_llsc_fsm.read() != SC_HEAP_LOCK))
+            ||
+            ( (r_llsc_fsm.read()       == SC_HEAP_LOCK) &&
+              (r_alloc_heap_fsm.read() == ALLOC_HEAP_LLSC) )
+            ||
+            ( (r_llsc_fsm.read()      == LLSC_TRT_LOCK ) &&
+              (r_alloc_trt_fsm.read() == ALLOC_TRT_LLSC)    ) )
+        {
+          if      (r_cleanup_fsm.read() == CLEANUP_DIR_LOCK)    r_alloc_dir_fsm = ALLOC_DIR_CLEANUP;
+          else if (r_xram_rsp_fsm.read() == XRAM_RSP_DIR_LOCK)  r_alloc_dir_fsm = ALLOC_DIR_XRAM_RSP;
+          else if (r_read_fsm.read() == READ_DIR_LOCK) 	        r_alloc_dir_fsm = ALLOC_DIR_READ;
+          else if (r_write_fsm.read() == WRITE_DIR_LOCK)        r_alloc_dir_fsm = ALLOC_DIR_WRITE;
+        }
+        break;
+
+        ///////////////////////
+      case ALLOC_DIR_CLEANUP:
+        if ( (r_cleanup_fsm.read() != CLEANUP_DIR_LOCK) &&
+            (r_cleanup_fsm.read() != CLEANUP_HEAP_LOCK) )
+        {
+          if        (r_xram_rsp_fsm.read() == XRAM_RSP_DIR_LOCK)    r_alloc_dir_fsm = ALLOC_DIR_XRAM_RSP;
+          else if   (r_read_fsm.read() == READ_DIR_LOCK)            r_alloc_dir_fsm = ALLOC_DIR_READ;
+          else if   (r_write_fsm.read() == WRITE_DIR_LOCK)          r_alloc_dir_fsm = ALLOC_DIR_WRITE;
+          else if   ((r_llsc_fsm.read() == LL_DIR_LOCK) || 
+                    (r_llsc_fsm.read() == SC_DIR_LOCK))             r_alloc_dir_fsm = ALLOC_DIR_LLSC;
+        }
+        break;
+        ////////////////////////
+      case ALLOC_DIR_XRAM_RSP:
+        if ( (r_xram_rsp_fsm.read() != XRAM_RSP_DIR_LOCK)  &&
+            (r_xram_rsp_fsm.read() != XRAM_RSP_TRT_COPY)   && 
+            (r_xram_rsp_fsm.read() != XRAM_RSP_INVAL_LOCK))
+        {
+          if      (r_read_fsm.read() == READ_DIR_LOCK) 	        r_alloc_dir_fsm = ALLOC_DIR_READ;
+          else if (r_write_fsm.read() == WRITE_DIR_LOCK)        r_alloc_dir_fsm = ALLOC_DIR_WRITE;
+          else if ( (r_llsc_fsm.read() == LL_DIR_LOCK) || 
+                    (r_llsc_fsm.read() == SC_DIR_LOCK))         r_alloc_dir_fsm = ALLOC_DIR_LLSC;
+          else if (r_cleanup_fsm.read() == CLEANUP_DIR_LOCK)    r_alloc_dir_fsm = ALLOC_DIR_CLEANUP;
+        }
+        break;
+
+    } // end switch alloc_dir_fsm
+
+    ////////////////////////////////////////////////////////////////////////////////////
+    //		ALLOC_TRT FSM
+    ////////////////////////////////////////////////////////////////////////////////////
+    // The ALLOC_TRT fsm allocates the access to the Transaction Table (write buffer)
+    // with a round robin priority between 4 user FSMs :
+    // The cyclic priority is READ > WRITE > LLSC > XRAM_RSP
+    // The ressource is always allocated.
+    ///////////////////////////////////////////////////////////////////////////////////
+
+    switch (r_alloc_trt_fsm) {
+
+      ////////////////////
+      case ALLOC_TRT_READ:
+        if ( r_read_fsm.read() != READ_TRT_LOCK ) 
+        {
+          if      ((r_write_fsm.read() == WRITE_TRT_LOCK)   ||
+                   (r_write_fsm.read() == WRITE_TRT_WRITE_LOCK))    r_alloc_trt_fsm = ALLOC_TRT_WRITE;
+          else if ((r_llsc_fsm.read() == LLSC_TRT_LOCK) ||
+                   (r_llsc_fsm.read() == SC_TRT_LOCK))              r_alloc_trt_fsm = ALLOC_TRT_LLSC;
+          else if (r_xram_rsp_fsm.read() == XRAM_RSP_TRT_COPY)      r_alloc_trt_fsm = ALLOC_TRT_XRAM_RSP;
+          else if ( (r_ixr_rsp_fsm.read() == IXR_RSP_TRT_ERASE) ||
+                    (r_ixr_rsp_fsm.read() == IXR_RSP_TRT_READ) )    r_alloc_trt_fsm = ALLOC_TRT_IXR_RSP;
+        }
+        break;
+        /////////////////////
+      case ALLOC_TRT_WRITE:
+        if ( (r_write_fsm.read() != WRITE_TRT_LOCK) &&
+             (r_write_fsm.read() != WRITE_TRT_WRITE_LOCK) &&
+             (r_write_fsm.read() != WRITE_INVAL_LOCK)) 
+        {
+          if      ((r_llsc_fsm.read() == LLSC_TRT_LOCK) ||
+                   (r_llsc_fsm.read() == SC_TRT_LOCK))              r_alloc_trt_fsm = ALLOC_TRT_LLSC;
+          else if (r_xram_rsp_fsm.read() == XRAM_RSP_TRT_COPY)      r_alloc_trt_fsm = ALLOC_TRT_XRAM_RSP;
+          else if ( (r_ixr_rsp_fsm.read() == IXR_RSP_TRT_ERASE) ||
+                    (r_ixr_rsp_fsm.read() == IXR_RSP_TRT_READ))     r_alloc_trt_fsm = ALLOC_TRT_IXR_RSP;
+          else if (r_read_fsm.read() == READ_TRT_LOCK) 	            r_alloc_trt_fsm = ALLOC_TRT_READ;
+        }
+        break;
+        ////////////////////
+      case ALLOC_TRT_LLSC:
+        if ( (r_llsc_fsm.read() != LLSC_TRT_LOCK) &&
+             (r_llsc_fsm.read() != SC_TRT_LOCK) &&
+             (r_llsc_fsm.read() != SC_INVAL_LOCK))
+        { 
+          if      (r_xram_rsp_fsm.read() == XRAM_RSP_TRT_COPY)      r_alloc_trt_fsm = ALLOC_TRT_XRAM_RSP;
+          else if ( (r_ixr_rsp_fsm.read() == IXR_RSP_TRT_ERASE) ||
+                    (r_ixr_rsp_fsm.read() == IXR_RSP_TRT_READ))     r_alloc_trt_fsm = ALLOC_TRT_IXR_RSP;
+          else if (r_read_fsm.read() == READ_TRT_LOCK) 	            r_alloc_trt_fsm = ALLOC_TRT_READ;
+          else if ((r_write_fsm.read() == WRITE_TRT_LOCK)     ||
+                   (r_write_fsm.read() == WRITE_TRT_WRITE_LOCK))    r_alloc_trt_fsm = ALLOC_TRT_WRITE;
+        }
+        break;
+        ////////////////////////
+      case ALLOC_TRT_XRAM_RSP:
+        if ( (r_xram_rsp_fsm.read() != XRAM_RSP_TRT_COPY)  &&
+            (r_xram_rsp_fsm.read() != XRAM_RSP_DIR_UPDT)   &&
+            (r_xram_rsp_fsm.read() != XRAM_RSP_INVAL_LOCK)) {
+          if      ( (r_ixr_rsp_fsm.read() == IXR_RSP_TRT_ERASE) ||
+                    (r_ixr_rsp_fsm.read() == IXR_RSP_TRT_READ))     r_alloc_trt_fsm = ALLOC_TRT_IXR_RSP;
+          else if (r_read_fsm.read() == READ_TRT_LOCK) 	            r_alloc_trt_fsm = ALLOC_TRT_READ;
+          else if ((r_write_fsm.read() == WRITE_TRT_LOCK)    ||
+                   (r_write_fsm.read() == WRITE_TRT_WRITE_LOCK))    r_alloc_trt_fsm = ALLOC_TRT_WRITE;
+          else if ((r_llsc_fsm.read() == LLSC_TRT_LOCK) ||
+                   (r_llsc_fsm.read() == SC_TRT_LOCK))              r_alloc_trt_fsm = ALLOC_TRT_LLSC;
+        }
+        break;
+        ////////////////////////
+      case ALLOC_TRT_IXR_RSP:
+        if ( (r_ixr_rsp_fsm.read() != IXR_RSP_TRT_ERASE) &&
+            (r_ixr_rsp_fsm.read() != IXR_RSP_TRT_READ) ) {
+          if      (r_read_fsm.read() == READ_TRT_LOCK) 	            r_alloc_trt_fsm = ALLOC_TRT_READ;
+          else if ((r_write_fsm.read() == WRITE_TRT_LOCK)   ||
+                   (r_write_fsm.read() == WRITE_TRT_WRITE_LOCK))    r_alloc_trt_fsm = ALLOC_TRT_WRITE;
+          else if ((r_llsc_fsm.read() == LLSC_TRT_LOCK) ||
+                   (r_llsc_fsm.read() == SC_TRT_LOCK))              r_alloc_trt_fsm = ALLOC_TRT_LLSC;
+          else if (r_xram_rsp_fsm.read() == XRAM_RSP_TRT_COPY)      r_alloc_trt_fsm = ALLOC_TRT_XRAM_RSP;
+        }
+        break;
+
+    } // end switch alloc_trt_fsm
+
+    ////////////////////////////////////////////////////////////////////////////////////
+    //		ALLOC_HEAP FSM
+    ////////////////////////////////////////////////////////////////////////////////////
+    // The ALLOC_HEAP FSM allocates the access to the heap
+    // with a round robin priority between 5 user FSMs :
+    // The cyclic ordering is READ > WRITE > LLSC > CLEANUP > XRAM_RSP
+    // The ressource is always allocated.
+    /////////////////////////////////////////////////////////////////////////////////////
+
+    switch ( r_alloc_heap_fsm.read() ) {
+
+      ////////////////////
+      case ALLOC_HEAP_READ:
+        if (  (r_read_fsm.read() != READ_HEAP_LOCK) &&
+              (r_read_fsm.read() != READ_HEAP_ERASE)     ) 
+        {
+          if        ((r_write_fsm.read() == WRITE_HEAP_LOCK) ||         
+                     (r_write_fsm.read() == WRITE_HEAP_ERASE))      r_alloc_heap_fsm = ALLOC_HEAP_WRITE;
+          else if  ((r_llsc_fsm.read() == SC_HEAP_LOCK) || 
+                    (r_llsc_fsm.read() == SC_HEAP_ERASE))           r_alloc_heap_fsm = ALLOC_HEAP_LLSC;
+          else if   (r_cleanup_fsm.read() == CLEANUP_HEAP_LOCK)     r_alloc_heap_fsm = ALLOC_HEAP_CLEANUP;
+          else if   (r_xram_rsp_fsm.read() == XRAM_RSP_HEAP_ERASE)  r_alloc_heap_fsm = ALLOC_HEAP_XRAM_RSP;
+        }
+        break;
+
+        /////////////////////
+      case ALLOC_HEAP_WRITE:
+        if (  (r_write_fsm.read() != WRITE_HEAP_LOCK)   &&
+              (r_write_fsm.read() != WRITE_UPT_REQ)     &&
+              (r_write_fsm.read() != WRITE_UPDATE)      &&
+              (r_write_fsm.read() != WRITE_HEAP_ERASE))
+        {
+          if       ((r_llsc_fsm.read() == SC_HEAP_LOCK) || 
+                    (r_llsc_fsm.read() == SC_HEAP_ERASE))           r_alloc_heap_fsm = ALLOC_HEAP_LLSC;
+          else if   (r_cleanup_fsm.read() == CLEANUP_HEAP_LOCK)     r_alloc_heap_fsm = ALLOC_HEAP_CLEANUP;
+          else if   (r_xram_rsp_fsm.read() == XRAM_RSP_HEAP_ERASE)  r_alloc_heap_fsm = ALLOC_HEAP_XRAM_RSP;
+          else if   (r_read_fsm.read() == READ_HEAP_LOCK) 	        r_alloc_heap_fsm = ALLOC_HEAP_READ;
+        }
+        break;
+
+        ////////////////////
+      case ALLOC_HEAP_LLSC:
+        if (  (r_llsc_fsm.read() != SC_HEAP_LOCK)  &&
+              (r_llsc_fsm.read() != SC_UPT_REQ )    &&
+              (r_llsc_fsm.read() != SC_UPDATE)      &&
+              (r_llsc_fsm.read() != SC_HEAP_ERASE ) )
+        {
+          if      (r_cleanup_fsm.read() == CLEANUP_HEAP_LOCK)     r_alloc_heap_fsm = ALLOC_HEAP_CLEANUP;
+          else if (r_xram_rsp_fsm.read() == XRAM_RSP_HEAP_ERASE)  r_alloc_heap_fsm = ALLOC_HEAP_XRAM_RSP;
+          else if (r_read_fsm.read() == READ_HEAP_LOCK)           r_alloc_heap_fsm = ALLOC_HEAP_READ;
+          else if ((r_write_fsm.read() == WRITE_HEAP_LOCK) ||        
+                   (r_write_fsm.read() == WRITE_HEAP_ERASE))      r_alloc_heap_fsm = ALLOC_HEAP_WRITE;
+        }
+        break;
+
+        ///////////////////////
+      case ALLOC_HEAP_CLEANUP:
+        if ( (r_cleanup_fsm.read() != CLEANUP_HEAP_LOCK) &&
+            (r_cleanup_fsm.read() != CLEANUP_HEAP_SEARCH)&&
+            (r_cleanup_fsm.read() != CLEANUP_HEAP_CLEAN)    )
+        {
+          if        (r_xram_rsp_fsm.read() == XRAM_RSP_HEAP_ERASE)  r_alloc_heap_fsm = ALLOC_HEAP_XRAM_RSP;
+          else if   (r_read_fsm.read() == READ_HEAP_LOCK)           r_alloc_heap_fsm = ALLOC_HEAP_READ;
+          else if   ((r_write_fsm.read() == WRITE_HEAP_LOCK) ||        
+                     (r_write_fsm.read() == WRITE_HEAP_ERASE))      r_alloc_heap_fsm = ALLOC_HEAP_WRITE;
+          else if   ((r_llsc_fsm.read() == SC_HEAP_LOCK) || 
+                    (r_llsc_fsm.read() == SC_HEAP_ERASE))           r_alloc_heap_fsm = ALLOC_HEAP_LLSC;
+        }
+        break;
+        ////////////////////////
+      case ALLOC_HEAP_XRAM_RSP:
+        if ( r_xram_rsp_fsm.read() != XRAM_RSP_HEAP_ERASE )
+        {
+          if        (r_read_fsm.read() == READ_HEAP_LOCK) 	        r_alloc_heap_fsm = ALLOC_HEAP_READ;
+          else if   ((r_write_fsm.read() == WRITE_HEAP_LOCK) ||        
+                     (r_write_fsm.read() == WRITE_HEAP_ERASE))      r_alloc_heap_fsm = ALLOC_HEAP_WRITE;
+          else if   ( (r_llsc_fsm.read() == SC_HEAP_LOCK) || 
+                    (r_llsc_fsm.read() == SC_HEAP_ERASE))           r_alloc_heap_fsm = ALLOC_HEAP_LLSC;
+          else if   (r_cleanup_fsm.read() == CLEANUP_HEAP_LOCK)     r_alloc_heap_fsm = ALLOC_HEAP_CLEANUP;
+        }
+        break;
+
+    } // end switch alloc_heap_fsm
+
+
+    ////////////////////////////////////////////////////////////////////////////////////
+    //		TGT_CMD to READ FIFO
+    ////////////////////////////////////////////////////////////////////////////////////
+
+    if ( cmd_read_fifo_put ) {
+      if ( cmd_read_fifo_get ) {
+        m_cmd_read_addr_fifo.put_and_get((addr_t)(p_vci_tgt.address.read()));
+        m_cmd_read_length_fifo.put_and_get(p_vci_tgt.plen.read()>>2);
+        m_cmd_read_srcid_fifo.put_and_get(p_vci_tgt.srcid.read());
+        m_cmd_read_trdid_fifo.put_and_get(p_vci_tgt.trdid.read());
+        m_cmd_read_pktid_fifo.put_and_get(p_vci_tgt.pktid.read());
+      } else {
+        m_cmd_read_addr_fifo.simple_put((addr_t)(p_vci_tgt.address.read()));
+        m_cmd_read_length_fifo.simple_put(p_vci_tgt.plen.read()>>2);
+        m_cmd_read_srcid_fifo.simple_put(p_vci_tgt.srcid.read());
+        m_cmd_read_trdid_fifo.simple_put(p_vci_tgt.trdid.read());
+        m_cmd_read_pktid_fifo.simple_put(p_vci_tgt.pktid.read());
+      }
+    } else {
+      if ( cmd_read_fifo_get ) {
+        m_cmd_read_addr_fifo.simple_get();
+        m_cmd_read_length_fifo.simple_get();
+        m_cmd_read_srcid_fifo.simple_get();
+        m_cmd_read_trdid_fifo.simple_get();
+        m_cmd_read_pktid_fifo.simple_get();
+      }
+    }
+    /////////////////////////////////////////////////////////////////////
+    //		TGT_CMD to WRITE FIFO
+    /////////////////////////////////////////////////////////////////////
+
+    if ( cmd_write_fifo_put ) {
+      if ( cmd_write_fifo_get ) {
+        m_cmd_write_addr_fifo.put_and_get((addr_t)(p_vci_tgt.address.read()));
+        m_cmd_write_eop_fifo.put_and_get(p_vci_tgt.eop.read());
+        m_cmd_write_srcid_fifo.put_and_get(p_vci_tgt.srcid.read());
+        m_cmd_write_trdid_fifo.put_and_get(p_vci_tgt.trdid.read());
+        m_cmd_write_pktid_fifo.put_and_get(p_vci_tgt.pktid.read());
+        m_cmd_write_data_fifo.put_and_get(p_vci_tgt.wdata.read());
+        m_cmd_write_be_fifo.put_and_get(p_vci_tgt.be.read());
+      } else {
+        m_cmd_write_addr_fifo.simple_put((addr_t)(p_vci_tgt.address.read()));
+        m_cmd_write_eop_fifo.simple_put(p_vci_tgt.eop.read());
+        m_cmd_write_srcid_fifo.simple_put(p_vci_tgt.srcid.read());
+        m_cmd_write_trdid_fifo.simple_put(p_vci_tgt.trdid.read());
+        m_cmd_write_pktid_fifo.simple_put(p_vci_tgt.pktid.read());
+        m_cmd_write_data_fifo.simple_put(p_vci_tgt.wdata.read());
+        m_cmd_write_be_fifo.simple_put(p_vci_tgt.be.read());
+      }
+    } else {
+      if ( cmd_write_fifo_get ) {
+        m_cmd_write_addr_fifo.simple_get();
+        m_cmd_write_eop_fifo.simple_get();
+        m_cmd_write_srcid_fifo.simple_get();
+        m_cmd_write_trdid_fifo.simple_get();
+        m_cmd_write_pktid_fifo.simple_get();
+        m_cmd_write_data_fifo.simple_get();
+        m_cmd_write_be_fifo.simple_get();
+      }
+    }
+    ////////////////////////////////////////////////////////////////////////////////////
+    //		TGT_CMD to LLSC FIFO
+    ////////////////////////////////////////////////////////////////////////////////////
+
+    if ( cmd_llsc_fifo_put ) {
+      if ( cmd_llsc_fifo_get ) {
+        m_cmd_llsc_addr_fifo.put_and_get((addr_t)(p_vci_tgt.address.read()));
+        m_cmd_llsc_sc_fifo.put_and_get(p_vci_tgt.cmd.read() == vci_param::CMD_STORE_COND); 
+        m_cmd_llsc_srcid_fifo.put_and_get(p_vci_tgt.srcid.read());
+        m_cmd_llsc_trdid_fifo.put_and_get(p_vci_tgt.trdid.read());
+        m_cmd_llsc_pktid_fifo.put_and_get(p_vci_tgt.pktid.read());
+        m_cmd_llsc_wdata_fifo.put_and_get(p_vci_tgt.wdata.read());
+      } else {
+        m_cmd_llsc_addr_fifo.simple_put((addr_t)(p_vci_tgt.address.read()));
+        m_cmd_llsc_sc_fifo.simple_put(p_vci_tgt.cmd.read() == vci_param::CMD_STORE_COND); 
+        m_cmd_llsc_srcid_fifo.simple_put(p_vci_tgt.srcid.read());
+        m_cmd_llsc_trdid_fifo.simple_put(p_vci_tgt.trdid.read());
+        m_cmd_llsc_pktid_fifo.simple_put(p_vci_tgt.pktid.read());
+        m_cmd_llsc_wdata_fifo.simple_put(p_vci_tgt.wdata.read());
+      }
+    } else {
+      if ( cmd_llsc_fifo_get ) {
+        m_cmd_llsc_addr_fifo.simple_get();
+        m_cmd_llsc_sc_fifo.simple_get();
+        m_cmd_llsc_srcid_fifo.simple_get();
+        m_cmd_llsc_trdid_fifo.simple_get();
+        m_cmd_llsc_pktid_fifo.simple_get();
+        m_cmd_llsc_wdata_fifo.simple_get();
+      }
+    }
+    ////////////////////////////////////////////////////////////////////////////////////
+    //		WRITE to INIT_CMD FIFO
+    ////////////////////////////////////////////////////////////////////////////////////
+
+    if ( write_to_init_cmd_fifo_put ) {
+      if ( write_to_init_cmd_fifo_get ) {
+        m_write_to_init_cmd_inst_fifo.put_and_get(write_to_init_cmd_fifo_inst);
+        m_write_to_init_cmd_srcid_fifo.put_and_get(write_to_init_cmd_fifo_srcid);
+      } else {
+        m_write_to_init_cmd_inst_fifo.simple_put(write_to_init_cmd_fifo_inst);
+        m_write_to_init_cmd_srcid_fifo.simple_put(write_to_init_cmd_fifo_srcid);
+      }
+    } else {
+      if ( write_to_init_cmd_fifo_get ) {
+        m_write_to_init_cmd_inst_fifo.simple_get();
+        m_write_to_init_cmd_srcid_fifo.simple_get();
+      }
+    }
+    ////////////////////////////////////////////////////////////////////////////////////
+    //		XRAM_RSP to INIT_CMD FIFO
+    ////////////////////////////////////////////////////////////////////////////////////
+
+    if ( xram_rsp_to_init_cmd_fifo_put ) {
+      if ( xram_rsp_to_init_cmd_fifo_get ) {
+        m_xram_rsp_to_init_cmd_inst_fifo.put_and_get(xram_rsp_to_init_cmd_fifo_inst);
+        m_xram_rsp_to_init_cmd_srcid_fifo.put_and_get(xram_rsp_to_init_cmd_fifo_srcid);
+      } else {
+        m_xram_rsp_to_init_cmd_inst_fifo.simple_put(xram_rsp_to_init_cmd_fifo_inst);
+        m_xram_rsp_to_init_cmd_srcid_fifo.simple_put(xram_rsp_to_init_cmd_fifo_srcid);
+      }
+    } else {
+      if ( xram_rsp_to_init_cmd_fifo_get ) {
+        m_xram_rsp_to_init_cmd_inst_fifo.simple_get();
+        m_xram_rsp_to_init_cmd_srcid_fifo.simple_get();
+      }
+    }
+    ////////////////////////////////////////////////////////////////////////////////////
+    //		LLSC to INIT_CMD FIFO
+    ////////////////////////////////////////////////////////////////////////////////////
+
+    if ( llsc_to_init_cmd_fifo_put ) {
+      if ( llsc_to_init_cmd_fifo_get ) {
+        m_llsc_to_init_cmd_inst_fifo.put_and_get(llsc_to_init_cmd_fifo_inst);
+        m_llsc_to_init_cmd_srcid_fifo.put_and_get(llsc_to_init_cmd_fifo_srcid);
+      } else {
+        m_llsc_to_init_cmd_inst_fifo.simple_put(llsc_to_init_cmd_fifo_inst);
+        m_llsc_to_init_cmd_srcid_fifo.simple_put(llsc_to_init_cmd_fifo_srcid);
+      }
+    } else {
+      if ( llsc_to_init_cmd_fifo_get ) {
+        m_llsc_to_init_cmd_inst_fifo.simple_get();
+        m_llsc_to_init_cmd_srcid_fifo.simple_get();
+      }
+    }
+
+
+  //////////////////////////////////////////////////////////////
+    m_cpt_cycles++;
+
+  } // end transition()
+
+  /////////////////////////////
+  tmpl(void)::genMoore()
+    /////////////////////////////
+  {
+    ////////////////////////////////////////////////////////////
+    // Command signals on the p_vci_ixr port
+    ////////////////////////////////////////////////////////////
+
+
+    p_vci_ixr.be      = 0xF;
+    p_vci_ixr.pktid   = 0;
+    p_vci_ixr.srcid   = m_srcid_ixr;
+    p_vci_ixr.cons    = false;
+    p_vci_ixr.wrap    = false;
+    p_vci_ixr.contig  = true;
+    p_vci_ixr.clen    = 0;
+    p_vci_ixr.cfixed  = false;
+
+    if ( r_ixr_cmd_fsm.read() == IXR_CMD_READ_NLINE ) {
+      p_vci_ixr.cmd     = vci_param::CMD_READ;
+      p_vci_ixr.cmdval  = true;
+      p_vci_ixr.address = (addr_t)(r_read_to_ixr_cmd_nline.read()*m_words*4);
+      p_vci_ixr.plen    = m_words*4;
+      p_vci_ixr.wdata   = 0x00000000;
+      p_vci_ixr.trdid   = r_read_to_ixr_cmd_trdid.read();
+      p_vci_ixr.eop     = true;
+    } 
+    else if ( r_ixr_cmd_fsm.read() == IXR_CMD_LLSC_NLINE ) {
+      if(r_llsc_to_ixr_cmd_write.read()){
+        p_vci_ixr.cmd     = vci_param::CMD_WRITE;
+        p_vci_ixr.cmdval  = true;
+        p_vci_ixr.address = (addr_t)((r_llsc_to_ixr_cmd_nline.read()*m_words+r_ixr_cmd_cpt.read())*4);
+        p_vci_ixr.plen    = m_words*4;
+        p_vci_ixr.wdata   = r_llsc_to_ixr_cmd_data[r_ixr_cmd_cpt.read()].read();
+        p_vci_ixr.trdid   = r_llsc_to_ixr_cmd_trdid.read();
+        p_vci_ixr.eop     = (r_ixr_cmd_cpt == (m_words-1));
+      } else {
+        p_vci_ixr.cmd     = vci_param::CMD_READ;
+        p_vci_ixr.cmdval  = true;
+        p_vci_ixr.address = (addr_t)(r_llsc_to_ixr_cmd_nline.read()*m_words*4);
+        p_vci_ixr.plen    = m_words*4;
+        p_vci_ixr.wdata   = 0x00000000;
+        p_vci_ixr.trdid   = r_llsc_to_ixr_cmd_trdid.read();
+        p_vci_ixr.eop     = true;
+      }
+    } 
+    else if ( r_ixr_cmd_fsm.read() == IXR_CMD_WRITE_NLINE ) {
+      if(r_write_to_ixr_cmd_write.read()){
+        p_vci_ixr.cmd     = vci_param::CMD_WRITE;
+        p_vci_ixr.cmdval  = true;
+        p_vci_ixr.address = (addr_t)((r_write_to_ixr_cmd_nline.read()*m_words+r_ixr_cmd_cpt.read())*4);
+        p_vci_ixr.plen    = m_words*4;
+        p_vci_ixr.wdata   = r_write_to_ixr_cmd_data[r_ixr_cmd_cpt.read()].read();
+        p_vci_ixr.trdid   = r_write_to_ixr_cmd_trdid.read();
+        p_vci_ixr.eop     = (r_ixr_cmd_cpt == (m_words-1));
+      } else {
+        p_vci_ixr.cmd     = vci_param::CMD_READ;
+        p_vci_ixr.cmdval  = true;
+        p_vci_ixr.address = (addr_t)(r_write_to_ixr_cmd_nline.read()*m_words*4);
+        p_vci_ixr.plen    = m_words*4;
+        p_vci_ixr.wdata   = 0x00000000;
+        p_vci_ixr.trdid   = r_write_to_ixr_cmd_trdid.read();
+        p_vci_ixr.eop     = true;
+      }
+    } 
+    else if ( r_ixr_cmd_fsm.read() == IXR_CMD_XRAM_DATA ) {
+      p_vci_ixr.cmd     = vci_param::CMD_WRITE;
+      p_vci_ixr.cmdval  = true;
+      p_vci_ixr.address = (addr_t)((r_xram_rsp_to_ixr_cmd_nline.read()*m_words+r_ixr_cmd_cpt.read())*4);
+      p_vci_ixr.plen    = m_words*4;
+      p_vci_ixr.wdata   = r_xram_rsp_to_ixr_cmd_data[r_ixr_cmd_cpt.read()].read();
+      p_vci_ixr.trdid   = r_xram_rsp_to_ixr_cmd_trdid.read();
+      p_vci_ixr.eop     = (r_ixr_cmd_cpt == (m_words-1));
+    } else {
+      p_vci_ixr.cmdval  = false;
+      p_vci_ixr.address = 0;
+      p_vci_ixr.plen    = 0;
+      p_vci_ixr.wdata   = 0;
+      p_vci_ixr.trdid   = 0;
+      p_vci_ixr.eop	= false;
+    }
+
+    ////////////////////////////////////////////////////
+    // Response signals on the p_vci_ixr port
+    ////////////////////////////////////////////////////
+
+    if ( ((r_alloc_trt_fsm.read() == ALLOC_TRT_IXR_RSP) &&
+          (r_ixr_rsp_fsm.read() == IXR_RSP_TRT_READ)) || 
+        (r_ixr_rsp_fsm.read() == IXR_RSP_ACK) ) p_vci_ixr.rspack = true;
+    else                                        p_vci_ixr.rspack = false;
+
+    ////////////////////////////////////////////////////
+    // Command signals on the p_vci_tgt port
+    ////////////////////////////////////////////////////
+
+    switch ((tgt_cmd_fsm_state_e)r_tgt_cmd_fsm.read()) {
+      case TGT_CMD_IDLE:
+        p_vci_tgt.cmdack  = false;
+        break;
+      case TGT_CMD_READ:
+        p_vci_tgt.cmdack  = m_cmd_read_addr_fifo.wok();
+        break;
+      case TGT_CMD_READ_EOP:
+        p_vci_tgt.cmdack  = true;
+        break;
+      case TGT_CMD_WRITE:
+        p_vci_tgt.cmdack  = m_cmd_write_addr_fifo.wok();
+        break;
+      case TGT_CMD_ATOMIC:
+        p_vci_tgt.cmdack  = m_cmd_llsc_addr_fifo.wok();
+        break;
+      default:
+        p_vci_tgt.cmdack = false;
+        break;
+    }
+
+    ////////////////////////////////////////////////////
+    // Response signals on the p_vci_tgt port
+    ////////////////////////////////////////////////////
+    switch ( r_tgt_rsp_fsm.read() ) {
+
+      case TGT_RSP_READ_IDLE:
+      case TGT_RSP_WRITE_IDLE:
+      case TGT_RSP_LLSC_IDLE:
+      case TGT_RSP_XRAM_IDLE:
+      case TGT_RSP_INIT_IDLE:
+      case TGT_RSP_CLEANUP_IDLE:
+        p_vci_tgt.rspval  = false;
+        p_vci_tgt.rsrcid  = 0;
+        p_vci_tgt.rdata   = 0;
+        p_vci_tgt.rpktid  = 0;
+        p_vci_tgt.rtrdid  = 0;
+        p_vci_tgt.rerror  = 0;
+        p_vci_tgt.reop    = false;	
+        break;
+      case TGT_RSP_READ:
+        p_vci_tgt.rspval   = true;
+        p_vci_tgt.rdata    = r_read_to_tgt_rsp_data[r_tgt_rsp_cpt.read()].read();
+        p_vci_tgt.rsrcid   = r_read_to_tgt_rsp_srcid.read();
+        p_vci_tgt.rtrdid   = r_read_to_tgt_rsp_trdid.read();
+        p_vci_tgt.rpktid   = r_read_to_tgt_rsp_pktid.read();
+        p_vci_tgt.rerror   = 0;
+        p_vci_tgt.reop     = ( r_tgt_rsp_cpt.read() == (r_read_to_tgt_rsp_word.read()+r_read_to_tgt_rsp_length-1) );
+        break;
+      case TGT_RSP_WRITE:
+        p_vci_tgt.rspval   = true;
+        p_vci_tgt.rdata    = 0;
+        p_vci_tgt.rsrcid   = r_write_to_tgt_rsp_srcid.read();
+        p_vci_tgt.rtrdid   = r_write_to_tgt_rsp_trdid.read();
+        p_vci_tgt.rpktid   = r_write_to_tgt_rsp_pktid.read();
+        p_vci_tgt.rerror   = 0x2 & ( (1 << vci_param::E) - 1); // Write OK
+        p_vci_tgt.reop     = true;
+        break;
+      case TGT_RSP_CLEANUP:
+        p_vci_tgt.rspval   = true;
+        p_vci_tgt.rdata    = 0;
+        p_vci_tgt.rsrcid   = r_cleanup_to_tgt_rsp_srcid.read();
+        p_vci_tgt.rtrdid   = r_cleanup_to_tgt_rsp_trdid.read();
+        p_vci_tgt.rpktid   = r_cleanup_to_tgt_rsp_pktid.read();
+        p_vci_tgt.rerror   = 0;
+        p_vci_tgt.reop     = true;
+        break;
+      case TGT_RSP_LLSC:
+        p_vci_tgt.rspval   = true;
+        p_vci_tgt.rdata    = r_llsc_to_tgt_rsp_data.read();
+        p_vci_tgt.rsrcid   = r_llsc_to_tgt_rsp_srcid.read();
+        p_vci_tgt.rtrdid   = r_llsc_to_tgt_rsp_trdid.read();
+        p_vci_tgt.rpktid   = r_llsc_to_tgt_rsp_pktid.read();
+        p_vci_tgt.rerror   = 0;
+        p_vci_tgt.reop     = true;
+        break;
+      case TGT_RSP_XRAM:
+        p_vci_tgt.rspval   = true;
+        p_vci_tgt.rdata    = r_xram_rsp_to_tgt_rsp_data[r_tgt_rsp_cpt.read()].read();
+        p_vci_tgt.rsrcid   = r_xram_rsp_to_tgt_rsp_srcid.read();
+        p_vci_tgt.rtrdid   = r_xram_rsp_to_tgt_rsp_trdid.read();
+        p_vci_tgt.rpktid   = r_xram_rsp_to_tgt_rsp_pktid.read();
+        p_vci_tgt.rerror   = 0;
+        p_vci_tgt.reop     = ( r_tgt_rsp_cpt.read() == (r_xram_rsp_to_tgt_rsp_word.read()+r_xram_rsp_to_tgt_rsp_length.read()-1));
+        break;
+      case TGT_RSP_INIT:
+        p_vci_tgt.rspval   = true;
+        p_vci_tgt.rdata    = 0;
+        p_vci_tgt.rsrcid   = r_init_rsp_to_tgt_rsp_srcid.read();
+        p_vci_tgt.rtrdid   = r_init_rsp_to_tgt_rsp_trdid.read();
+        p_vci_tgt.rpktid   = r_init_rsp_to_tgt_rsp_pktid.read();
+        p_vci_tgt.rerror   = 0;
+        p_vci_tgt.reop     = true;	
+        break;
+    } // end switch r_tgt_rsp_fsm
+
+    ///////////////////////////////////////////////////
+    // Command signals on the p_vci_ini port
+    ///////////////////////////////////////////////////
+
+    p_vci_ini.cmd     = vci_param::CMD_WRITE;
+    p_vci_ini.srcid   = m_srcid_ini;
+    p_vci_ini.pktid   = 0;
+    p_vci_ini.cons    = true;
+    p_vci_ini.wrap    = false;
+    p_vci_ini.contig  = false;
+    p_vci_ini.clen    = 0;
+    p_vci_ini.cfixed  = false;
+
+    switch ( r_init_cmd_fsm.read() ) {
+
+      case INIT_CMD_UPDT_IDLE:
+      case INIT_CMD_INVAL_IDLE:
+      case INIT_CMD_SC_UPDT_IDLE:
+        p_vci_ini.cmdval  = false;
+        p_vci_ini.address = 0;
+        p_vci_ini.wdata   = 0;
+        p_vci_ini.be      = 0;
+        p_vci_ini.plen    = 0;
+        p_vci_ini.trdid   = 0;
+        p_vci_ini.eop     = false;
+        break;
+      case INIT_CMD_INVAL_NLINE:
+        p_vci_ini.cmdval  = m_xram_rsp_to_init_cmd_inst_fifo.rok();
+        if(m_xram_rsp_to_init_cmd_inst_fifo.rok()){
+          if(m_xram_rsp_to_init_cmd_inst_fifo.read()) {
+            p_vci_ini.address = (addr_t)(m_coherence_table[m_xram_rsp_to_init_cmd_srcid_fifo.read()]+8);
+          } else {
+            p_vci_ini.address = (addr_t)(m_coherence_table[m_xram_rsp_to_init_cmd_srcid_fifo.read()]);
+          }
+        } else p_vci_ini.address = 0; // prevent segmentation faults by reading an empty fifo
+        p_vci_ini.wdata   = (uint32_t)r_xram_rsp_to_init_cmd_nline.read();
+        p_vci_ini.be      = ((r_xram_rsp_to_init_cmd_nline.read() >> 32) & 0x3);
+        p_vci_ini.plen    = 4;
+        p_vci_ini.trdid   = r_xram_rsp_to_init_cmd_trdid.read();
+        p_vci_ini.eop     = true;
+        break;
+      case INIT_CMD_XRAM_BRDCAST:
+        p_vci_ini.cmdval  = true;
+        p_vci_ini.address = broadcast_addr;
+        p_vci_ini.wdata   = (uint32_t)r_xram_rsp_to_init_cmd_nline.read();
+        p_vci_ini.be      = ((r_xram_rsp_to_init_cmd_nline.read() >> 32) & 0x3);
+        p_vci_ini.plen    = 4;
+        p_vci_ini.trdid   = r_xram_rsp_to_init_cmd_trdid.read();
+        p_vci_ini.eop     = true;
+        break;
+
+      case INIT_CMD_WRITE_BRDCAST:
+        p_vci_ini.cmdval  = true;
+        p_vci_ini.address = broadcast_addr;
+        p_vci_ini.wdata   = (addr_t)r_write_to_init_cmd_nline.read();
+        p_vci_ini.be      = ((r_write_to_init_cmd_nline.read() >> 32) & 0x3);
+        p_vci_ini.plen    = 4 ;
+        p_vci_ini.eop     = true;
+        p_vci_ini.trdid   = r_write_to_init_cmd_trdid.read();
+        break;
+      case INIT_CMD_UPDT_NLINE:
+        p_vci_ini.cmdval  = m_write_to_init_cmd_inst_fifo.rok();
+        if(m_write_to_init_cmd_inst_fifo.rok()){
+          p_vci_ini.address = (addr_t)(m_coherence_table[m_write_to_init_cmd_srcid_fifo.read()] + 4);
+        } else {
+          p_vci_ini.address = 0;
+        }
+        p_vci_ini.wdata   = (uint32_t)r_write_to_init_cmd_nline.read();
+        p_vci_ini.be      = ((r_write_to_init_cmd_nline.read() >> 32 ) & 0x3);
+        p_vci_ini.plen    = 4 * (r_write_to_init_cmd_count.read() + 2);
+        p_vci_ini.eop     = false;
+        p_vci_ini.trdid   = r_write_to_init_cmd_trdid.read();
+        break;
+      case INIT_CMD_UPDT_INDEX:
+        p_vci_ini.cmdval  = true;
+        p_vci_ini.address = (addr_t)(m_coherence_table[m_write_to_init_cmd_srcid_fifo.read()] + 4);
+        p_vci_ini.wdata   = r_write_to_init_cmd_index.read();
+        p_vci_ini.be      = 0xF;
+        p_vci_ini.plen    = 4 * (r_write_to_init_cmd_count.read() + 2);
+        p_vci_ini.trdid   = r_write_to_init_cmd_trdid.read();
+        p_vci_ini.eop     = false;
+        break;
+      case INIT_CMD_UPDT_DATA:
+        p_vci_ini.cmdval  = true;
+        p_vci_ini.address = (addr_t)(m_coherence_table[m_write_to_init_cmd_srcid_fifo.read()] + 4);
+        p_vci_ini.wdata   = r_write_to_init_cmd_data[r_init_cmd_cpt.read() +
+          r_write_to_init_cmd_index.read()].read();
+        if(r_write_to_init_cmd_we[r_init_cmd_cpt.read() +
+            r_write_to_init_cmd_index.read()].read())  
+          p_vci_ini.be      = 0xF;
+        else			p_vci_ini.be      = 0x0;
+        p_vci_ini.plen    = 4 * (r_write_to_init_cmd_count.read() + 2);
+        p_vci_ini.trdid   = r_write_to_init_cmd_trdid.read();
+        p_vci_ini.eop     = ( r_init_cmd_cpt.read() == (r_write_to_init_cmd_count.read()-1) );
+        break;
+
+      case INIT_CMD_SC_BRDCAST:
+        p_vci_ini.cmdval  = true;
+        p_vci_ini.address = broadcast_addr;
+        p_vci_ini.wdata   = (addr_t)r_llsc_to_init_cmd_nline.read();
+        p_vci_ini.be      = ((r_llsc_to_init_cmd_nline.read() >> 32) & 0x3);
+        p_vci_ini.plen    = 4 ;
+        p_vci_ini.eop     = true;
+        p_vci_ini.trdid   = r_llsc_to_init_cmd_trdid.read();
+        break;
+      case INIT_CMD_SC_UPDT_NLINE:
+        p_vci_ini.cmdval  = m_llsc_to_init_cmd_inst_fifo.rok();
+        if(m_llsc_to_init_cmd_inst_fifo.rok()){
+          p_vci_ini.address = (addr_t)(m_coherence_table[m_llsc_to_init_cmd_srcid_fifo.read()] + 4);
+        } else {
+          p_vci_ini.address = 0;
+        }
+        p_vci_ini.wdata   = (uint32_t)r_llsc_to_init_cmd_nline.read();
+        p_vci_ini.be      = ((r_llsc_to_init_cmd_nline.read() >> 32 ) & 0x3);
+        p_vci_ini.plen    = 4 * 3;
+        p_vci_ini.eop     = false;
+        p_vci_ini.trdid   = r_llsc_to_init_cmd_trdid.read();
+        break;
+      case INIT_CMD_SC_UPDT_INDEX:
+        p_vci_ini.cmdval  = true;
+        p_vci_ini.address = (addr_t)(m_coherence_table[m_llsc_to_init_cmd_srcid_fifo.read()] + 4);
+        p_vci_ini.wdata   = r_llsc_to_init_cmd_index.read();
+        p_vci_ini.be      = 0xF;
+        p_vci_ini.plen    = 4 * 3;
+        p_vci_ini.trdid   = r_llsc_to_init_cmd_trdid.read();
+        p_vci_ini.eop     = false;
+        break;
+      case INIT_CMD_SC_UPDT_DATA:
+        p_vci_ini.cmdval  = true;
+        p_vci_ini.address = (addr_t)(m_coherence_table[m_llsc_to_init_cmd_srcid_fifo.read()] + 4);
+        p_vci_ini.wdata   = r_llsc_to_init_cmd_wdata.read();
+        p_vci_ini.be      = 0xF;
+        p_vci_ini.plen    = 4 * 3;
+        p_vci_ini.trdid   = r_llsc_to_init_cmd_trdid.read();
+        p_vci_ini.eop     = true;
+        break;
+
+    } // end switch r_init_cmd_fsm
+
+    //////////////////////////////////////////////////////
+    // Response signals on the p_vci_ini port
+    //////////////////////////////////////////////////////
+
+    if ( r_init_rsp_fsm.read() == INIT_RSP_IDLE ) p_vci_ini.rspack  = true;
+    else                                          p_vci_ini.rspack  = false;
+
+    //////////////////////////////////////////////////////
+    // Response signals on the p_vci_tgt_cleanup port
+    //////////////////////////////////////////////////////
+    p_vci_tgt_cleanup.rspval = false;
+    p_vci_tgt_cleanup.rsrcid = 0;
+    p_vci_tgt_cleanup.rdata  = 0;
+    p_vci_tgt_cleanup.rpktid = 0;
+    p_vci_tgt_cleanup.rtrdid = 0;
+    p_vci_tgt_cleanup.rerror = 0;
+    p_vci_tgt_cleanup.reop   = false;
+    p_vci_tgt_cleanup.cmdack = false ;
+
+    switch(r_cleanup_fsm.read()){
+      case CLEANUP_IDLE:
+        {
+          p_vci_tgt_cleanup.cmdack = true ;
+          break;
+        }
+      case CLEANUP_RSP:
+        {
+          p_vci_tgt_cleanup.rspval = true;
+          p_vci_tgt_cleanup.rdata  = 0;
+          p_vci_tgt_cleanup.rsrcid = r_cleanup_srcid.read();
+          p_vci_tgt_cleanup.rpktid = r_cleanup_pktid.read();
+          p_vci_tgt_cleanup.rtrdid = r_cleanup_trdid.read();
+          p_vci_tgt_cleanup.rerror = 0x2 & ( (1 << vci_param::E) - 1);
+          p_vci_tgt_cleanup.reop   = 1;
+          break;
+        }
+
+    }
+
+  } // end genMoore()
+
+}} // end name space
+
+// Local Variables:
+// tab-width: 4
+// c-basic-offset: 4
+// c-file-offsets:((innamespace . 0)(inline-open . 0))
+// indent-tabs-mode: nil
+// End:
+
+// vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4
+
Index: branches/v4/modules/vci_mem_cache_v4/caba/metadata/vci_mem_cache_v4.sd
===================================================================
--- branches/v4/modules/vci_mem_cache_v4/caba/metadata/vci_mem_cache_v4.sd	(revision 371)
+++ branches/v4/modules/vci_mem_cache_v4/caba/metadata/vci_mem_cache_v4.sd	(revision 371)
@@ -0,0 +1,60 @@
+
+# -*- python -*-
+
+__id__ = "$Id$"
+__version__ = "$Revision$"
+
+Module('caba:vci_mem_cache_v4',
+        classname = 'soclib::caba::VciMemCacheV4',
+
+        tmpl_parameters = [ parameter.Module('vci_param', default = 'caba:vci_param') ],
+
+        header_files = [
+            '../source/include/vci_mem_cache_v4.h',
+            '../source/include/xram_transaction_v4.h',
+            '../source/include/mem_cache_directory_v4.h',
+            '../source/include/update_tab_v4.h'
+        ],
+
+        implementation_files = [ '../source/src/vci_mem_cache_v4.cpp' ],
+
+        uses = [
+            Uses('caba:base_module'),
+            Uses('common:loader'),
+            Uses('common:mapping_table'),
+            Uses('caba:generic_fifo'),
+            Uses('caba:generic_llsc_global_table'),
+        ],
+
+        ports = [
+            Port( 'caba:vci_target'   , 'p_vci_tgt' ),
+            Port( 'caba:vci_target'   , 'p_vci_tgt_cleanup' ),
+            Port( 'caba:vci_initiator', 'p_vci_ini' ),
+            Port( 'caba:vci_initiator', 'p_vci_ixr' ),
+            Port( 'caba:bit_in'       , 'p_resetn'  , auto = 'resetn' ),
+            Port( 'caba:clock_in'     , 'p_clk'     , auto = 'clock'  ),
+        ],
+
+        instance_parameters = [
+            parameter.Module( 'mtp', 'common:mapping_table' ),
+            parameter.Module( 'mtc', 'common:mapping_table' ),
+            parameter.Module( 'mtx', 'common:mapping_table' ),
+            parameter.IntTab( 'vci_ixr_index' ),
+            parameter.IntTab( 'vci_ini_index' ),
+            parameter.IntTab( 'vci_tgt_index' ),
+            parameter.IntTab( 'vci_tgt_index_cleanup '),
+            parameter.Int   ( 'nways' ),
+            parameter.Int   ( 'nsets' ),
+            parameter.Int   ( 'nwords' ),
+            parameter.Int   ( 'heap_size' ),
+        ],
+
+        extensions = [
+            'dsx:get_ident='
+            'vci_ini_index:p_vci_ini:mtc,'
+            'vci_tgt_index_cleanup:p_vci_tgt_cleanup:mtc,'
+            'vci_tgt_index:p_vci_tgt:mtp,'
+            'vci_ixr_index:p_vci_ixr:mtx',
+            'dsx:addressable=vci_tgt_index,vci_tgt_index_cleanup',
+        ],
+)
Index: branches/v4/modules/vci_mem_cache_v4/caba/source/include/mem_cache_directory_v4.h
===================================================================
--- branches/v4/modules/vci_mem_cache_v4/caba/source/include/mem_cache_directory_v4.h	(revision 371)
+++ branches/v4/modules/vci_mem_cache_v4/caba/source/include/mem_cache_directory_v4.h	(revision 371)
@@ -0,0 +1,727 @@
+#ifndef SOCLIB_CABA_MEM_CACHE_DIRECTORY_V4_H
+#define SOCLIB_CABA_MEM_CACHE_DIRECTORY_V4_H 
+
+#include <inttypes.h>
+#include <systemc>
+#include <cassert>
+#include "arithmetics.h"
+
+// !!!
+// The L1_MULTI_CACHE mechanism does no longer work with the new pktid encoding
+// of TSAR. Turning the define below to a non null value will cause the memcache
+// to behave in an unpredicted way.
+// TODO Either remove the mechanism from the mem cache or update its behaviour.
+#define L1_MULTI_CACHE 0
+
+//#define RANDOM_EVICTION
+
+namespace soclib { namespace caba {
+
+  using namespace sc_core;
+
+  ////////////////////////////////////////////////////////////////////////
+  //                    A LRU entry 
+  ////////////////////////////////////////////////////////////////////////
+  class LruEntry {
+
+    public:
+
+      bool recent;            
+
+      void init()
+      {
+        recent=false;
+      }
+
+  }; // end class LruEntry
+
+  ////////////////////////////////////////////////////////////////////////
+  //                    An Owner
+  ////////////////////////////////////////////////////////////////////////
+  class Owner{
+    typedef uint32_t size_t;
+    
+    public:
+    // Fields
+      bool      inst;       // Is the owner an ICache ?
+      size_t    srcid;      // The SRCID of the owner
+#if L1_MULTI_CACHE
+      size_t    cache_id;   // In multi_cache configuration
+#endif
+
+    ////////////////////////
+    // Constructors
+    ////////////////////////
+      Owner(bool   i_inst
+            ,size_t i_srcid
+#if L1_MULTI_CACHE
+            ,size_t i_cache_id
+#endif
+            ){
+        inst    = i_inst;
+        srcid   = i_srcid;
+#if L1_MULTI_CACHE
+        cache_id= i_cache_id;
+#endif
+      }
+
+      Owner(const Owner &a){
+        inst    = a.inst;
+        srcid   = a.srcid;
+#if L1_MULTI_CACHE
+        cache_id= a.cache_id;
+#endif
+      }
+
+      Owner(){
+        inst    = false;
+        srcid   = 0;
+#if L1_MULTI_CACHE
+        cache_id= 0;
+#endif
+      }
+      // end constructors
+
+  }; // end class Owner
+
+
+  ////////////////////////////////////////////////////////////////////////
+  //                    A directory entry                               
+  ////////////////////////////////////////////////////////////////////////
+  class DirectoryEntry {
+
+    typedef uint32_t tag_t;
+    typedef uint32_t size_t;
+
+    public:
+
+    bool    valid;                  // entry valid
+    bool    is_cnt;                 // directory entry is in counter mode
+    bool    dirty;                  // entry dirty
+    bool    lock;                   // entry locked
+    tag_t   tag;                    // tag of the entry
+    size_t  count;                  // number of copies
+    Owner   owner;                  // an owner of the line 
+    size_t  ptr;                    // pointer to the next owner
+
+    DirectoryEntry()
+    {
+      valid         = false;
+      is_cnt        = false;
+      dirty         = false;
+      lock          = false;
+      tag           = 0;
+      count         = 0;
+      owner.inst    = 0;
+      owner.srcid   = 0;
+#if L1_MULTI_CACHE
+      owner.cache_id= 0;
+#endif
+      ptr           = 0;
+    }
+
+    DirectoryEntry(const DirectoryEntry &source)
+    {
+      valid         = source.valid;
+      is_cnt        = source.is_cnt;
+      dirty         = source.dirty;
+      lock          = source.lock;
+      tag           = source.tag;
+      count         = source.count;
+      owner         = source.owner;
+      ptr           = source.ptr;
+    }          
+
+    /////////////////////////////////////////////////////////////////////
+    // The init() function initializes the entry 
+    /////////////////////////////////////////////////////////////////////
+    void init()
+    {
+      valid     = false;
+      is_cnt    = false;
+      dirty     = false;
+      lock      = false;
+      count     = 0;
+    }
+
+    /////////////////////////////////////////////////////////////////////
+    // The copy() function copies an existing source entry to a target 
+    /////////////////////////////////////////////////////////////////////
+    void copy(const DirectoryEntry &source)
+    {
+      valid	    = source.valid;
+      is_cnt    = source.is_cnt;
+      dirty	    = source.dirty;
+      lock	    = source.lock;
+      tag	    = source.tag;
+      count     = source.count;
+      owner     = source.owner;
+      ptr       = source.ptr;
+    }
+
+    ////////////////////////////////////////////////////////////////////
+    // The print() function prints the entry 
+    ////////////////////////////////////////////////////////////////////
+    void print()
+    {
+      std::cout << "Valid = " << valid << " ; IS COUNT = " << is_cnt << " ; Dirty = " << dirty << " ; Lock = " 
+                << lock 
+                << " ; Tag = " << std::hex << tag << std::dec 
+                << " ; Count = " << count 
+                << " ; Owner = " << owner.srcid 
+#if L1_MULTI_CACHE
+                << "." << owner.cache_id 
+#endif
+                << " " << owner.inst 
+                << " ; Pointer = " << ptr << std::endl;
+    }
+
+  }; // end class DirectoryEntry
+
+  ////////////////////////////////////////////////////////////////////////
+  //                       The directory  
+  ////////////////////////////////////////////////////////////////////////
+  class CacheDirectory {
+
+    typedef sc_dt::sc_uint<40> addr_t;
+    typedef uint32_t data_t;
+    typedef uint32_t tag_t;
+    typedef uint32_t size_t;
+
+    private:
+
+    // Directory constants
+    size_t					m_ways;
+    size_t					m_sets;
+    size_t					m_words;
+    size_t					m_width;
+    uint32_t                lfsr;
+
+    // the directory & lru tables
+    DirectoryEntry 				**m_dir_tab;
+    LruEntry	 				**m_lru_tab;
+
+    public:
+
+    ////////////////////////
+    // Constructor
+    ////////////////////////
+    CacheDirectory( size_t ways, size_t sets, size_t words, size_t address_width)	 
+    {
+      m_ways  = ways; 
+      m_sets  = sets;
+      m_words = words;
+      m_width = address_width;
+      lfsr = -1;
+
+      m_dir_tab = new DirectoryEntry*[sets];
+      for ( size_t i=0; i<sets; i++ ) {
+        m_dir_tab[i] = new DirectoryEntry[ways];
+        for ( size_t j=0 ; j<ways ; j++) m_dir_tab[i][j].init();
+      }
+      m_lru_tab = new LruEntry*[sets];
+      for ( size_t i=0; i<sets; i++ ) {
+        m_lru_tab[i] = new LruEntry[ways];
+        for ( size_t j=0 ; j<ways ; j++) m_lru_tab[i][j].init();
+      }
+    } // end constructor
+
+    /////////////////
+    // Destructor
+    /////////////////
+    ~CacheDirectory()
+    {
+      for(size_t i=0 ; i<m_sets ; i++){
+        delete [] m_dir_tab[i];
+        delete [] m_lru_tab[i];
+      }
+      delete [] m_dir_tab;
+      delete [] m_lru_tab;
+    } // end destructor
+
+    /////////////////////////////////////////////////////////////////////
+    // The read() function reads a directory entry. In case of hit, the
+    // LRU is updated.
+    // Arguments :
+    // - address : the address of the entry 
+    // - way : (return argument) the way of the entry in case of hit
+    // The function returns a copy of a (valid or invalid) entry  
+    /////////////////////////////////////////////////////////////////////
+    DirectoryEntry read(const addr_t &address,size_t &way)
+    {
+
+#define L2 soclib::common::uint32_log2
+      const size_t set = (size_t)(address >> (L2(m_words) + 2)) & (m_sets - 1);
+      const tag_t  tag = (tag_t)(address >> (L2(m_sets) + L2(m_words) + 2));
+#undef L2
+
+      bool hit       = false;
+      for ( size_t i=0 ; i<m_ways ; i++ ) {
+        bool equal = ( m_dir_tab[set][i].tag == tag );
+        bool valid = m_dir_tab[set][i].valid;
+        hit = equal && valid;
+        if ( hit ) {			
+          way = i;
+          break;
+        } 
+      }
+      if ( hit ) {
+        m_lru_tab[set][way].recent = true;
+        return DirectoryEntry(m_dir_tab[set][way]);
+      } else {
+        return DirectoryEntry();
+      }
+    } // end read()
+
+    /////////////////////////////////////////////////////////////////////
+    // The read_neutral() function reads a directory entry, without
+    // changing the LRU
+    // Arguments :
+    // - address : the address of the entry 
+    // The function returns a copy of a (valid or invalid) entry  
+    /////////////////////////////////////////////////////////////////////
+    DirectoryEntry read_neutral(const addr_t &address)
+    {
+
+#define L2 soclib::common::uint32_log2
+      const size_t set = (size_t)(address >> (L2(m_words) + 2)) & (m_sets - 1);
+      const tag_t  tag = (tag_t)(address >> (L2(m_sets) + L2(m_words) + 2));
+#undef L2
+
+      bool hit       = false;
+      for ( size_t i=0 ; i<m_ways ; i++ ) {
+        bool equal = ( m_dir_tab[set][i].tag == tag );
+        bool valid = m_dir_tab[set][i].valid;
+        hit = equal && valid;
+        if ( hit ) {			
+          return DirectoryEntry(m_dir_tab[set][i]);
+        } 
+      }
+      return DirectoryEntry();
+    } // end read_neutral()
+
+    /////////////////////////////////////////////////////////////////////
+    // The write function writes a new entry, 
+    // and updates the LRU bits if necessary.
+    // Arguments :
+    // - set : the set of the entry
+    // - way : the way of the entry
+    // - entry : the entry value
+    /////////////////////////////////////////////////////////////////////
+    void write(const size_t &set, const size_t &way, const DirectoryEntry &entry)
+    {
+      assert( (set<m_sets) 
+          && "Cache Directory write : The set index is invalid");
+      assert( (way<m_ways) 
+          && "Cache Directory write : The way index is invalid");
+
+      // update Directory
+      m_dir_tab[set][way].copy(entry);
+
+      // update LRU bits
+      bool all_recent = true;
+      for ( size_t i=0 ; i<m_ways ; i++ ) {
+        if ( i != way ) all_recent = m_lru_tab[set][i].recent && all_recent;
+      }
+      if ( all_recent ) {
+        for( size_t i=0 ; i<m_ways ; i++ ) m_lru_tab[set][i].recent = false;
+      } else {
+        m_lru_tab[set][way].recent = true;
+      }
+    } // end write()
+
+    /////////////////////////////////////////////////////////////////////
+    // The print() function prints a selected directory entry
+    // Arguments :
+    // - set : the set of the entry to print
+    // - way : the way of the entry to print
+    /////////////////////////////////////////////////////////////////////
+    void print(const size_t &set, const size_t &way)
+    {
+      std::cout << std::dec << " set : " << set << " ; way : " << way << " ; " ;
+      m_dir_tab[set][way].print();
+    } // end print()
+
+    /////////////////////////////////////////////////////////////////////
+    // The select() function selects a directory entry to evince.
+    // Arguments :
+    // - set   : (input argument) the set to modify
+    // - way   : (return argument) the way to evince
+    /////////////////////////////////////////////////////////////////////
+    DirectoryEntry select(const size_t &set, size_t &way)
+    {
+      assert( (set < m_sets) 
+          && "Cache Directory : (select) The set index is invalid");
+
+      for(size_t i=0; i<m_ways; i++){
+        if(!m_dir_tab[set][i].valid){
+          way=i;
+          return DirectoryEntry(m_dir_tab[set][way]);
+        }
+      }
+
+#ifdef RANDOM_EVICTION
+      lfsr = (lfsr >> 1) ^ ((-(lfsr & 1)) & 0xd0000001);
+      way = lfsr % m_ways;
+      return DirectoryEntry(m_dir_tab[set][way]);
+#endif
+
+      for(size_t i=0; i<m_ways; i++){
+        if(!(m_lru_tab[set][i].recent) && !(m_dir_tab[set][i].lock)){
+          way=i;
+          return DirectoryEntry(m_dir_tab[set][way]);
+        }
+      }
+      for(size_t i=0; i<m_ways; i++){
+        if( !(m_lru_tab[set][i].recent) && (m_dir_tab[set][i].lock)){
+          way=i;
+          return DirectoryEntry(m_dir_tab[set][way]);
+        }
+      }
+      for(size_t i=0; i<m_ways; i++){
+        if( (m_lru_tab[set][i].recent) && !(m_dir_tab[set][i].lock)){
+          way=i;
+          return DirectoryEntry(m_dir_tab[set][way]);
+        }
+      }
+      way = 0;
+      return DirectoryEntry(m_dir_tab[set][0]);
+    } // end select()
+
+    /////////////////////////////////////////////////////////////////////
+    // 		Global initialisation function
+    /////////////////////////////////////////////////////////////////////
+    void init()
+    {
+      for ( size_t set=0 ; set<m_sets ; set++ ) {
+        for ( size_t way=0 ; way<m_ways ; way++ ) {
+          m_dir_tab[set][way].init();
+          m_lru_tab[set][way].init();
+        }
+      }
+    } // end init()
+
+  }; // end class CacheDirectory
+
+  ///////////////////////////////////////////////////////////////////////
+  //                    A Heap Entry
+  ///////////////////////////////////////////////////////////////////////
+  class HeapEntry{
+    typedef uint32_t size_t;
+
+    public:
+    // Fields of the entry
+      Owner     owner;
+      size_t    next;
+
+    ////////////////////////
+    // Constructor
+    ////////////////////////
+      HeapEntry()
+      :owner(false,0
+#if L1_MULTI_CACHE
+             ,0
+#endif
+             )
+      {
+        next = 0;
+      } // end constructor
+
+    ////////////////////////
+    // Constructor
+    ////////////////////////
+      HeapEntry(const HeapEntry &entry){
+        owner.inst  = entry.owner.inst;
+        owner.srcid = entry.owner.srcid;
+#if L1_MULTI_CACHE
+        owner.cache_id = entry.owner.cache_id;
+#endif        
+        next           = entry.next;
+      } // end constructor
+
+    /////////////////////////////////////////////////////////////////////
+    // The copy() function copies an existing source entry to a target 
+    /////////////////////////////////////////////////////////////////////
+      void copy(const HeapEntry &entry){
+        owner.inst     = entry.owner.inst;
+        owner.srcid    = entry.owner.srcid;
+#if L1_MULTI_CACHE
+        owner.cache_id = entry.owner.cache_id;
+#endif
+        next           = entry.next;
+      } // end copy()
+
+    ////////////////////////////////////////////////////////////////////
+    // The print() function prints the entry 
+    ////////////////////////////////////////////////////////////////////
+      void print(){
+        std::cout 
+        << " -- owner.inst     : " << std::dec << owner.inst << std::endl
+        << " -- owner.srcid    : " << std::dec << owner.srcid << std::endl
+#if L1_MULTI_CACHE
+        << " -- owner.cache_id : " << std::dec << owner.cache_id << std::endl
+#endif
+        << " -- next           : " << std::dec << next << std::endl;
+
+      } // end print()
+
+  }; // end class HeapEntry
+
+  ////////////////////////////////////////////////////////////////////////
+  //                        The Heap 
+  ////////////////////////////////////////////////////////////////////////
+  class HeapDirectory{
+    typedef uint32_t size_t;
+    
+    private:
+    // Registers and the heap
+      size_t    ptr_free;
+      bool      full;
+      HeapEntry *m_heap_tab;
+
+    // Constants for debugging purpose
+      size_t    tab_size;
+
+    public:
+    ////////////////////////
+    // Constructor
+    ////////////////////////
+      HeapDirectory(uint32_t size){
+        assert(size>0 && "Memory Cache, HeapDirectory constructor : invalid size");
+        ptr_free    = 0;
+        full        = false;
+        m_heap_tab  = new HeapEntry[size];
+        tab_size    = size;
+      } // end constructor
+
+    /////////////////
+    // Destructor
+    /////////////////
+      ~HeapDirectory(){
+        delete [] m_heap_tab;
+      } // end destructor
+
+    /////////////////////////////////////////////////////////////////////
+    // 		Global initialisation function
+    /////////////////////////////////////////////////////////////////////
+      void init(){
+        ptr_free=0;
+        full=false;
+        for(size_t i=0; i< tab_size-1;i++){
+          m_heap_tab[i].next = i+1;
+        }
+        m_heap_tab[tab_size-1].next = tab_size-1;
+        return;
+      }
+
+    /////////////////////////////////////////////////////////////////////
+    // The print() function prints a selected directory entry
+    // Arguments :
+    // - ptr : the pointer to the entry to print
+    /////////////////////////////////////////////////////////////////////
+      void print(const size_t &ptr){
+        std::cout << "Heap, printing the entry : " << std::dec << ptr << std::endl;
+        m_heap_tab[ptr].print();
+      } // end print()
+
+    /////////////////////////////////////////////////////////////////////
+    // The print_list() function prints a list from selected directory entry
+    // Arguments :
+    // - ptr : the pointer to the first entry to print
+    /////////////////////////////////////////////////////////////////////
+      void print_list(const size_t &ptr){
+        bool end = false;
+        size_t ptr_temp = ptr;
+        std::cout << "Heap, printing the list from : " << std::dec << ptr << std::endl;
+        while(!end){
+            m_heap_tab[ptr_temp].print();
+            if(ptr_temp == m_heap_tab[ptr_temp].next) end = true;
+            ptr_temp = m_heap_tab[ptr_temp].next;
+        } 
+      } // end print_list()
+
+    /////////////////////////////////////////////////////////////////////
+    // The is_full() function return true if the heap is full.
+    /////////////////////////////////////////////////////////////////////
+      bool is_full(){
+        return full;
+      } // end is_full()
+
+    /////////////////////////////////////////////////////////////////////
+    // The next_free_ptr() function returns the pointer 
+    // to the next free entry.
+    /////////////////////////////////////////////////////////////////////
+      size_t next_free_ptr(){
+        return ptr_free;
+      } // end next_free_ptr()
+
+    /////////////////////////////////////////////////////////////////////
+    // The next_free_entry() function returns 
+    // a copy of the next free entry.
+    /////////////////////////////////////////////////////////////////////
+      HeapEntry next_free_entry(){
+        return HeapEntry(m_heap_tab[ptr_free]);
+      } // end next_free_entry()
+   
+    /////////////////////////////////////////////////////////////////////
+    // The write_free_entry() function modify the next free entry.
+    // Arguments :
+    // - entry : the entry to write
+    /////////////////////////////////////////////////////////////////////
+      void write_free_entry(const HeapEntry &entry){
+        m_heap_tab[ptr_free].copy(entry);
+      } // end write_free_entry()
+
+    /////////////////////////////////////////////////////////////////////
+    // The write_free_ptr() function writes the pointer
+    // to the next free entry
+    /////////////////////////////////////////////////////////////////////
+      void write_free_ptr(const size_t &ptr){
+        assert( (ptr<tab_size) && "HeapDirectory error : try to write a wrong free pointer");
+        ptr_free = ptr;
+      } // end write_free_ptr()
+
+    /////////////////////////////////////////////////////////////////////
+    // The set_full() function sets the full bit (to true).
+    /////////////////////////////////////////////////////////////////////
+      void set_full(){
+        full = true;
+      } // end set_full()
+
+    /////////////////////////////////////////////////////////////////////
+    // The unset_full() function unsets the full bit (to false).
+    /////////////////////////////////////////////////////////////////////
+      void unset_full(){
+        full = false;
+      } // end unset_full()
+
+    /////////////////////////////////////////////////////////////////////
+    // The read() function returns a copy of
+    // the entry pointed by the argument
+    // Arguments :
+    //  - ptr : the pointer to the entry to read
+    /////////////////////////////////////////////////////////////////////
+      HeapEntry read(const size_t &ptr){
+        assert( (ptr<tab_size) && "HeapDirectory error : try to write a wrong free pointer");
+        return HeapEntry(m_heap_tab[ptr]);
+      } // end read()
+
+    /////////////////////////////////////////////////////////////////////
+    // The write() function writes an entry in the heap
+    // Arguments :
+    //  - ptr : the pointer to the entry to replace
+    //  - entry : the entry to write
+    /////////////////////////////////////////////////////////////////////
+      void write(const size_t &ptr, const HeapEntry &entry){
+        assert( (ptr<tab_size) && "HeapDirectory error : try to write a wrong free pointer");
+        m_heap_tab[ptr].copy(entry);
+      } // end write()
+
+  }; // end class HeapDirectory
+
+  ////////////////////////////////////////////////////////////////////////
+  //                        Cache Data 
+  ////////////////////////////////////////////////////////////////////////
+  class CacheData {
+    private:
+      const uint32_t m_sets;
+      const uint32_t m_ways;
+      const uint32_t m_words;
+
+      uint32_t *** m_cache_data;
+
+    public:
+
+      CacheData(uint32_t ways, uint32_t sets, uint32_t words)
+        : m_sets(sets), m_ways(ways), m_words(words) {
+
+          m_cache_data = new uint32_t ** [ways];
+          for ( size_t i=0 ; i < ways ; i++ ) {
+            m_cache_data[i] = new uint32_t * [sets];
+          }
+          for ( size_t i=0; i<ways; i++ ) {
+            for ( size_t j=0; j<sets; j++ ) {
+              m_cache_data[i][j] = new uint32_t [words];
+            }
+          }
+        }
+
+      ~CacheData() {
+          for(size_t i=0; i<m_ways ; i++){
+              for(size_t j=0; j<m_sets ; j++){
+                  delete [] m_cache_data[i][j];
+              }
+          }
+          for(size_t i=0; i<m_ways ; i++){
+              delete [] m_cache_data[i];
+          }
+          delete [] m_cache_data;
+      }
+
+      uint32_t read (
+          const uint32_t &way,
+          const uint32_t &set,
+          const uint32_t &word) const {
+
+        assert((set  < m_sets ) && "Cache data error: Trying to read a wrong set" );
+        assert((way  < m_ways ) && "Cache data error: Trying to read a wrong way" );
+        assert((word < m_words) && "Cache data error: Trying to read a wrong word");
+
+        return m_cache_data[way][set][word];
+      }
+
+      void read_line(
+          const uint32_t &way,
+          const uint32_t &set,
+          sc_core::sc_signal<uint32_t> * cache_line)
+      {
+        assert((set < m_sets ) && "Cache data error: Trying to read a wrong set" );
+        assert((way < m_ways ) && "Cache data error: Trying to read a wrong way" );
+      
+        for (uint32_t word=0; word<m_words; word++)
+          cache_line[word].write(m_cache_data[way][set][word]);
+      }
+
+      void write (
+          const uint32_t &way,
+          const uint32_t &set,
+          const uint32_t &word,
+          const uint32_t &data,
+          const uint32_t &be = 0xF) {
+
+        assert((set  < m_sets ) && "Cache data error: Trying to write a wrong set" );
+        assert((way  < m_ways ) && "Cache data error: Trying to write a wrong way" );
+        assert((word < m_words) && "Cache data error: Trying to write a wrong word");
+        assert((be  <= 0xF    ) && "Cache data error: Trying to write a wrong word cell");
+
+        if (be == 0x0) return;
+
+        if (be == 0xF) {
+            m_cache_data[way][set][word] = data; 
+            return;
+        }
+
+        uint32_t mask = 0;
+        if  (be & 0x1) mask = mask | 0x000000FF;
+        if  (be & 0x2) mask = mask | 0x0000FF00;
+        if  (be & 0x4) mask = mask | 0x00FF0000;
+        if  (be & 0x8) mask = mask | 0xFF000000;
+
+        m_cache_data[way][set][word] = 
+          (data & mask) | (m_cache_data[way][set][word] & ~mask);
+      }
+  }; // end class CacheData
+
+}} // end namespaces
+
+#endif
+
+// Local Variables:
+// tab-width: 4
+// c-basic-offset: 4
+// c-file-offsets:((innamespace . 0)(inline-open . 0))
+// indent-tabs-mode: nil
+// End:
+
+// vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4
+
Index: branches/v4/modules/vci_mem_cache_v4/caba/source/include/update_tab_v4.h
===================================================================
--- branches/v4/modules/vci_mem_cache_v4/caba/source/include/update_tab_v4.h	(revision 371)
+++ branches/v4/modules/vci_mem_cache_v4/caba/source/include/update_tab_v4.h	(revision 371)
@@ -0,0 +1,415 @@
+#ifndef UPDATE_TAB_V4_H_
+#define UPDATE_TAB_V4_H_
+
+#include <inttypes.h>
+#include <systemc>
+#include <cassert>
+#include "arithmetics.h"
+
+////////////////////////////////////////////////////////////////////////
+//                  An update tab entry    
+////////////////////////////////////////////////////////////////////////
+class UpdateTabEntry {
+  typedef uint32_t size_t;
+  typedef sc_dt::sc_uint<40> addr_t;
+
+  public:
+  bool 	    valid;      // It is a valid pending transaction
+  bool	    update;     // It is an update transaction
+  bool      brdcast;    // It is a broadcast invalidate
+  bool      rsp;        // It needs a response to the initiator
+  size_t 	srcid;      // The srcid of the initiator which wrote the data
+  size_t 	trdid;      // The trdid of the initiator which wrote the data
+  size_t 	pktid;      // The pktid of the initiator which wrote the data
+  addr_t	nline;	    // The identifier of the cache line
+  size_t 	count;      // The number of acknowledge responses to receive
+
+  UpdateTabEntry(){
+    valid	= false;
+    update  = false;
+    brdcast = false;
+    rsp     = false;
+    srcid	= 0;
+    trdid	= 0;
+    pktid	= 0;
+    nline	= 0;
+    count	= 0;
+  }
+
+  UpdateTabEntry(bool   i_valid, 
+      bool   i_update,
+      bool   i_brdcast,
+      bool   i_rsp,
+      size_t i_srcid, 
+      size_t i_trdid, 
+      size_t i_pktid, 
+      addr_t i_nline,
+      size_t i_count) 
+  {
+    valid	= i_valid;
+    update	= i_update;
+    brdcast = i_brdcast;
+    rsp     = i_rsp;
+    srcid	= i_srcid;
+    trdid	= i_trdid;
+    pktid	= i_pktid;
+    nline	= i_nline;
+    count	= i_count;
+  }
+
+  UpdateTabEntry(const UpdateTabEntry &source)
+  {
+    valid   = source.valid;
+    update  = source.update;
+    brdcast = source.brdcast;
+    rsp     = source.rsp;
+    srcid   = source.srcid;
+    trdid   = source.trdid;
+    pktid   = source.pktid;
+    nline   = source.nline;
+    count   = source.count;
+  }
+
+  ////////////////////////////////////////////////////
+  // The init() function initializes the entry 
+  ///////////////////////////////////////////////////
+  void init()
+  {
+    valid  = false;
+    update = false;
+    brdcast= false;
+    rsp    = false;
+    srcid  = 0;
+    trdid  = 0;
+    pktid  = 0;
+    nline  = 0;
+    count  = 0;
+  }
+
+  ////////////////////////////////////////////////////////////////////
+  // The copy() function copies an existing entry
+  // Its arguments are :
+  // - source : the update tab entry to copy
+  ////////////////////////////////////////////////////////////////////
+  void copy(const UpdateTabEntry &source)
+  {
+    valid  = source.valid;
+    update = source.update;
+    brdcast= source.brdcast;
+    rsp    = source.rsp;
+    srcid  = source.srcid;
+    trdid  = source.trdid;
+    pktid  = source.pktid;
+    nline  = source.nline;
+    count  = source.count;
+  }
+
+  ////////////////////////////////////////////////////////////////////
+  // The print() function prints the entry  
+  ////////////////////////////////////////////////////////////////////
+  void print(){
+    std::cout << std::dec << "valid  = " << valid  << std::endl;
+    std::cout << "update = " << update << std::endl;
+    std::cout << "brdcast= " << brdcast<< std::endl;
+    std::cout << "rsp    = " << rsp    << std::endl;
+    std::cout << "srcid  = " << srcid  << std::endl; 
+    std::cout << "trdid  = " << trdid  << std::endl; 
+    std::cout << "pktid  = " << pktid  << std::endl; 
+    std::cout << std::hex << "nline  = " << nline  << std::endl;
+    std::cout << std::dec << "count  = " << count  << std::endl;
+  }
+};
+
+////////////////////////////////////////////////////////////////////////
+//                        The update tab             
+////////////////////////////////////////////////////////////////////////
+class UpdateTab{
+
+  typedef uint32_t size_t;
+  typedef sc_dt::sc_uint<40> addr_t;
+
+  private:
+  size_t size_tab;
+  std::vector<UpdateTabEntry> tab;
+
+  public:
+
+  UpdateTab()
+    : tab(0)
+  {
+    size_tab=0;
+  }
+
+  UpdateTab(size_t size_tab_i)
+    : tab(size_tab_i)
+  {
+    size_tab=size_tab_i;
+  }
+
+  ////////////////////////////////////////////////////////////////////
+  // The size() function returns the size of the tab  
+  ////////////////////////////////////////////////////////////////////
+  const size_t size(){
+    return size_tab;
+  }
+
+
+  ////////////////////////////////////////////////////////////////////
+  // The print() function diplays the tab content 
+  ////////////////////////////////////////////////////////////////////
+  void print(){
+    for(size_t i=0; i<size_tab; i++) {
+      std::cout << "UPDATE TAB ENTRY " << std::dec << i << "--------" << std::endl;
+      tab[i].print();
+    }
+    return;
+  }
+
+
+  /////////////////////////////////////////////////////////////////////
+  // The init() function initializes the tab 
+  /////////////////////////////////////////////////////////////////////
+  void init(){
+    for ( size_t i=0; i<size_tab; i++) {
+      tab[i].init();
+    }
+  }
+
+
+  /////////////////////////////////////////////////////////////////////
+  // The reads() function reads an entry 
+  // Arguments :
+  // - entry : the entry to read
+  // This function returns a copy of the entry.
+  /////////////////////////////////////////////////////////////////////
+  UpdateTabEntry read (size_t entry)
+  {
+    assert(entry<size_tab && "Bad Update Tab Entry");
+    return UpdateTabEntry(tab[entry]);
+  }
+
+  ///////////////////////////////////////////////////////////////////////////
+  // The set() function writes an entry in the Update Table
+  // Arguments :
+  // - update : transaction type (bool)
+  // - srcid : srcid of the initiator
+  // - trdid : trdid of the initiator
+  // - pktid : pktid of the initiator
+  // - count : number of expected responses
+  // - index : (return argument) index of the selected entry
+  // This function returns true if the write successed (an entry was empty).
+  ///////////////////////////////////////////////////////////////////////////
+  bool set(const bool	update,
+      const bool   brdcast,
+      const bool   rsp,
+      const size_t srcid,
+      const size_t trdid,
+      const size_t pktid,
+      const addr_t nline,
+      const size_t count,
+      size_t &index)
+  {
+    for ( size_t i=0 ; i<size_tab ; i++ ) {
+      if( !tab[i].valid ) {
+        tab[i].valid		= true;
+        tab[i].update		= update;
+        tab[i].brdcast      = brdcast;
+        tab[i].rsp          = rsp;
+        tab[i].srcid		= (size_t) srcid;
+        tab[i].trdid		= (size_t) trdid;
+        tab[i].pktid		= (size_t) pktid;
+        tab[i].nline		= (addr_t) nline;
+        tab[i].count		= (size_t) count;
+        index			    = i;
+        return true;
+      }
+    }
+    return false;
+  } // end set()
+
+  /////////////////////////////////////////////////////////////////////
+  // The decrement() function decrements the counter for a given entry.
+  // Arguments :
+  // - index   : the index of the entry
+  // - counter : (return argument) value of the counter after decrement
+  // This function returns true if the entry is valid.
+  /////////////////////////////////////////////////////////////////////
+  bool decrement( const size_t index,
+      size_t &counter ) 
+  {
+    assert((index<size_tab) && "Bad Update Tab Entry");
+    if ( tab[index].valid ) {
+      tab[index].count--;
+      counter = tab[index].count;
+      return true;
+    } else {
+      return false;
+    }
+  }
+
+  /////////////////////////////////////////////////////////////////////
+  // The is_full() function returns true if the table is full
+  /////////////////////////////////////////////////////////////////////
+  bool is_full()
+  {
+    for(size_t i = 0 ; i < size_tab ; i++){
+      if(!tab[i].valid){
+        return false;
+      }
+    }
+    return true;
+  }
+
+  /////////////////////////////////////////////////////////////////////
+  // The is_not_empty() function returns true if the table is not empty
+  /////////////////////////////////////////////////////////////////////
+  bool is_not_empty()
+  {
+    for(size_t i = 0 ; i < size_tab ; i++){
+      if(tab[i].valid){
+        return true;
+      }
+    }
+    return false;
+  }
+
+  /////////////////////////////////////////////////////////////////////
+  // The need_rsp() function returns the need of a response
+  // Arguments :
+  // - index : the index of the entry
+  /////////////////////////////////////////////////////////////////////
+  bool need_rsp(const size_t index)
+  {
+    assert(index<size_tab && "Bad Update Tab Entry");
+    return tab[index].rsp;	
+  }
+
+  /////////////////////////////////////////////////////////////////////
+  // The is_update() function returns the transaction type
+  // Arguments :
+  // - index : the index of the entry
+  /////////////////////////////////////////////////////////////////////
+  bool is_brdcast(const size_t index)
+  {
+    assert(index<size_tab && "Bad Update Tab Entry");
+    return tab[index].brdcast;	
+  }
+
+  /////////////////////////////////////////////////////////////////////
+  // The is_update() function returns the transaction type
+  // Arguments :
+  // - index : the index of the entry
+  /////////////////////////////////////////////////////////////////////
+  bool is_update(const size_t index)
+  {
+    assert(index<size_tab && "Bad Update Tab Entry");
+    return tab[index].update;	
+  }
+
+  /////////////////////////////////////////////////////////////////////
+  // The srcid() function returns the srcid value
+  // Arguments :
+  // - index : the index of the entry
+  /////////////////////////////////////////////////////////////////////
+  size_t srcid(const size_t index)
+  {
+    assert(index<size_tab && "Bad Update Tab Entry");
+    return tab[index].srcid;	
+  }
+
+  /////////////////////////////////////////////////////////////////////
+  // The trdid() function returns the trdid value
+  // Arguments :
+  // - index : the index of the entry
+  /////////////////////////////////////////////////////////////////////
+  size_t trdid(const size_t index)
+  {
+    assert(index<size_tab && "Bad Update Tab Entry");
+    return tab[index].trdid;	
+  }
+
+  /////////////////////////////////////////////////////////////////////
+  // The pktid() function returns the pktid value
+  // Arguments :
+  // - index : the index of the entry
+  /////////////////////////////////////////////////////////////////////
+  size_t pktid(const size_t index)
+  {
+    assert(index<size_tab && "Bad Update Tab Entry");
+    return tab[index].pktid;	
+  }
+
+  /////////////////////////////////////////////////////////////////////
+  // The nline() function returns the nline value
+  // Arguments :
+  // - index : the index of the entry
+  /////////////////////////////////////////////////////////////////////
+  addr_t nline(const size_t index)
+  {
+    assert(index<size_tab && "Bad Update Tab Entry");
+    return tab[index].nline;
+  }
+
+  /////////////////////////////////////////////////////////////////////
+  // The search_inval() function returns the index of the entry in UPT
+  // Arguments :
+  // - nline : the line number of the entry in the directory
+  /////////////////////////////////////////////////////////////////////
+  bool search_inval(const addr_t nline,size_t &index)
+  {
+    size_t i ;
+
+    for (i = 0 ; i < size_tab ; i++){
+      if((tab[i].nline == nline) && tab[i].valid){
+        if(!tab[i].update){
+          index = i ;
+          return true;
+        }
+      }
+    }
+    return false;
+  }
+
+  /////////////////////////////////////////////////////////////////////
+  // The read_nline() function returns the index of the entry in UPT
+  // Arguments :
+  // - nline : the line number of the entry in the directory
+  /////////////////////////////////////////////////////////////////////
+  bool read_nline(const addr_t nline,size_t &index) 
+  {
+    size_t i ;
+
+    for (i = 0 ; i < size_tab ; i++){
+      if((tab[i].nline == nline) && tab[i].valid){
+        index = i ;
+        return true;
+      }
+    }
+    return false;
+  }
+
+  /////////////////////////////////////////////////////////////////////
+  // The clear() function erases an entry of the tab
+  // Arguments :
+  // - index : the index of the entry
+  /////////////////////////////////////////////////////////////////////       
+  void clear(const size_t index)
+  {
+    assert(index<size_tab && "Bad Update Tab Entry");
+    tab[index].valid=false;
+    return;	
+  }
+
+};
+
+#endif
+
+// Local Variables:
+// tab-width: 4
+// c-basic-offset: 4
+// c-file-offsets:((innamespace . 0)(inline-open . 0))
+// indent-tabs-mode: nil
+// End:
+
+// vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4
+
Index: branches/v4/modules/vci_mem_cache_v4/caba/source/include/vci_mem_cache_v4.h
===================================================================
--- branches/v4/modules/vci_mem_cache_v4/caba/source/include/vci_mem_cache_v4.h	(revision 371)
+++ branches/v4/modules/vci_mem_cache_v4/caba/source/include/vci_mem_cache_v4.h	(revision 371)
@@ -0,0 +1,833 @@
+/* -*- c++ -*-
+ * File         : vci_mem_cache_v4.h
+ * Date         : 26/10/2008
+ * Copyright    : UPMC / LIP6
+ * Authors      : Alain Greiner / Eric Guthmuller
+ *
+ * SOCLIB_LGPL_HEADER_BEGIN
+ *
+ * This file is part of SoCLib, GNU LGPLv2.1.
+ *
+ * SoCLib is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU Lesser General Public License as published
+ * by the Free Software Foundation; version 2.1 of the License.
+ *
+ * SoCLib is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with SoCLib; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301 USA
+ *
+ * SOCLIB_LGPL_HEADER_END
+ *
+ * Maintainers: alain eric.guthmuller@polytechnique.edu
+ *              cesar.fuguet-tortolero@lip6.fr
+ *              alexandre.joannou@lip6.fr
+ *
+ */
+
+#ifndef SOCLIB_CABA_MEM_CACHE_V4_H
+#define SOCLIB_CABA_MEM_CACHE_V4_H
+
+#include <inttypes.h>
+#include <systemc>
+#include <list>
+#include <cassert>
+#include "arithmetics.h"
+#include "alloc_elems.h"
+#include "caba_base_module.h"
+#include "vci_target.h"
+#include "vci_initiator.h"
+#include "generic_fifo.h"
+#include "mapping_table.h"
+#include "int_tab.h"
+#include "generic_llsc_global_table.h"
+#include "mem_cache_directory_v4.h"
+#include "xram_transaction_v4.h"
+#include "update_tab_v4.h"
+
+#define TRANSACTION_TAB_LINES 4 // Number of lines in the transaction tab
+#define UPDATE_TAB_LINES      4 // Number of lines in the update tab
+
+namespace soclib {  namespace caba {
+  using namespace sc_core;
+
+  template<typename vci_param>
+    class VciMemCacheV4
+    : public soclib::caba::BaseModule
+    {
+      typedef sc_dt::sc_uint<40> addr_t;
+      typedef typename vci_param::fast_addr_t vci_addr_t;
+      typedef uint32_t data_t;
+      typedef uint32_t tag_t;
+      typedef uint32_t size_t;
+      typedef uint32_t be_t;
+      typedef uint32_t copy_t;
+
+      /* States of the TGT_CMD fsm */
+      enum tgt_cmd_fsm_state_e{
+        TGT_CMD_IDLE,
+        TGT_CMD_READ,
+        TGT_CMD_WRITE,
+        TGT_CMD_CAS
+      };
+
+      /* States of the TGT_RSP fsm */
+      enum tgt_rsp_fsm_state_e{
+        TGT_RSP_READ_IDLE,
+        TGT_RSP_WRITE_IDLE,
+        TGT_RSP_CAS_IDLE,
+        TGT_RSP_XRAM_IDLE,
+        TGT_RSP_INIT_IDLE,
+        TGT_RSP_CLEANUP_IDLE,
+        TGT_RSP_READ,
+        TGT_RSP_WRITE,
+        TGT_RSP_CAS,
+        TGT_RSP_XRAM,
+        TGT_RSP_INIT,
+        TGT_RSP_CLEANUP
+      };
+
+      /* States of the INIT_CMD fsm */
+      enum init_cmd_fsm_state_e{
+        INIT_CMD_INVAL_IDLE,
+        INIT_CMD_INVAL_NLINE,
+        INIT_CMD_XRAM_BRDCAST,
+        INIT_CMD_WRITE_BRDCAST,
+        INIT_CMD_CAS_BRDCAST,
+        INIT_CMD_UPDT_IDLE,
+        INIT_CMD_UPDT_NLINE,
+        INIT_CMD_UPDT_INDEX,
+        INIT_CMD_UPDT_DATA,
+        INIT_CMD_CAS_UPDT_IDLE,
+        INIT_CMD_CAS_UPDT_NLINE,
+        INIT_CMD_CAS_UPDT_INDEX,
+        INIT_CMD_CAS_UPDT_DATA,
+        INIT_CMD_CAS_UPDT_DATA_HIGH
+      };
+
+      /* States of the INIT_RSP fsm */
+      enum init_rsp_fsm_state_e{
+        INIT_RSP_IDLE,
+        INIT_RSP_UPT_LOCK,
+        INIT_RSP_UPT_CLEAR,
+        INIT_RSP_END
+      };
+
+      /* States of the READ fsm */
+      enum read_fsm_state_e{
+        READ_IDLE,
+        READ_DIR_REQ,
+        READ_DIR_LOCK,
+        READ_DIR_HIT,
+        READ_HEAP_REQ,
+        READ_HEAP_LOCK,
+        READ_HEAP_WRITE,
+        READ_HEAP_ERASE,
+        READ_HEAP_LAST,
+        READ_RSP,
+        READ_TRT_LOCK,
+        READ_TRT_SET,
+        READ_TRT_REQ
+      };
+
+      /* States of the WRITE fsm */
+      enum write_fsm_state_e{
+        WRITE_IDLE,
+        WRITE_NEXT,
+        WRITE_DIR_REQ,
+        WRITE_DIR_LOCK,
+        WRITE_DIR_READ,
+        WRITE_DIR_HIT,
+        WRITE_UPT_LOCK,
+        WRITE_UPT_HEAP_LOCK,
+        WRITE_UPT_REQ,
+        WRITE_UPT_NEXT,
+        WRITE_UPT_DEC,
+        WRITE_RSP,
+        WRITE_MISS_TRT_LOCK,
+        WRITE_MISS_TRT_DATA,
+        WRITE_MISS_TRT_SET,
+        WRITE_MISS_XRAM_REQ,
+        WRITE_BC_TRT_LOCK,
+        WRITE_BC_UPT_LOCK,
+        WRITE_BC_DIR_INVAL,
+        WRITE_BC_CC_SEND,
+        WRITE_BC_XRAM_REQ,
+        WRITE_WAIT
+      };
+
+      /* States of the IXR_RSP fsm */
+      enum ixr_rsp_fsm_state_e{
+        IXR_RSP_IDLE,
+        IXR_RSP_ACK,
+        IXR_RSP_TRT_ERASE,
+        IXR_RSP_TRT_READ
+      };
+
+      /* States of the XRAM_RSP fsm */
+      enum xram_rsp_fsm_state_e{
+        XRAM_RSP_IDLE,
+        XRAM_RSP_TRT_COPY,
+        XRAM_RSP_TRT_DIRTY,
+        XRAM_RSP_DIR_LOCK,
+        XRAM_RSP_DIR_UPDT,
+        XRAM_RSP_DIR_RSP,
+        XRAM_RSP_INVAL_LOCK,
+        XRAM_RSP_INVAL_WAIT,
+        XRAM_RSP_INVAL,
+        XRAM_RSP_WRITE_DIRTY,
+        XRAM_RSP_HEAP_REQ,
+        XRAM_RSP_HEAP_ERASE,
+        XRAM_RSP_HEAP_LAST,
+        XRAM_RSP_ERROR_ERASE,
+        XRAM_RSP_ERROR_RSP
+      };
+
+      /* States of the IXR_CMD fsm */
+      enum ixr_cmd_fsm_state_e{
+        IXR_CMD_READ_IDLE,
+        IXR_CMD_WRITE_IDLE,
+        IXR_CMD_CAS_IDLE,
+        IXR_CMD_XRAM_IDLE,
+        IXR_CMD_READ_NLINE,
+        IXR_CMD_WRITE_NLINE,
+        IXR_CMD_CAS_NLINE,
+        IXR_CMD_XRAM_DATA
+      };
+
+      /* States of the CAS fsm */
+      enum cas_fsm_state_e{
+        CAS_IDLE,
+        CAS_DIR_REQ,
+        CAS_DIR_LOCK,
+        CAS_DIR_HIT_READ,
+        CAS_DIR_HIT_COMPARE,
+        CAS_DIR_HIT_WRITE,
+        CAS_UPT_LOCK,
+        CAS_UPT_HEAP_LOCK,
+        CAS_UPT_REQ,
+        CAS_UPT_NEXT,
+        CAS_BC_TRT_LOCK,
+        CAS_BC_UPT_LOCK,
+        CAS_BC_DIR_INVAL,
+        CAS_BC_CC_SEND,
+        CAS_BC_XRAM_REQ,
+        CAS_RSP_FAIL,
+        CAS_RSP_SUCCESS,
+        CAS_MISS_TRT_LOCK,
+        CAS_MISS_TRT_SET,
+        CAS_MISS_XRAM_REQ,
+        CAS_WAIT
+      };
+
+      /* States of the CLEANUP fsm */
+      enum cleanup_fsm_state_e{
+        CLEANUP_IDLE,
+        CLEANUP_DIR_REQ,
+        CLEANUP_DIR_LOCK,
+        CLEANUP_DIR_WRITE,
+        CLEANUP_HEAP_REQ,
+        CLEANUP_HEAP_LOCK,
+        CLEANUP_HEAP_SEARCH,
+        CLEANUP_HEAP_CLEAN,
+        CLEANUP_HEAP_FREE,
+        CLEANUP_UPT_LOCK,
+        CLEANUP_UPT_WRITE,
+        CLEANUP_WRITE_RSP,
+        CLEANUP_RSP
+      };
+
+      /* States of the ALLOC_DIR fsm */
+      enum alloc_dir_fsm_state_e{
+        ALLOC_DIR_RESET,
+        ALLOC_DIR_READ,
+        ALLOC_DIR_WRITE,
+        ALLOC_DIR_CAS,
+        ALLOC_DIR_CLEANUP,
+        ALLOC_DIR_XRAM_RSP
+      };
+
+      /* States of the ALLOC_TRT fsm */
+      enum alloc_trt_fsm_state_e{
+        ALLOC_TRT_READ,
+        ALLOC_TRT_WRITE,
+        ALLOC_TRT_CAS,
+        ALLOC_TRT_XRAM_RSP,
+        ALLOC_TRT_IXR_RSP
+      };
+
+      /* States of the ALLOC_UPT fsm */
+      enum alloc_upt_fsm_state_e{
+        ALLOC_UPT_WRITE,
+        ALLOC_UPT_XRAM_RSP,
+        ALLOC_UPT_INIT_RSP,
+        ALLOC_UPT_CLEANUP,
+        ALLOC_UPT_CAS
+      };
+
+      /* States of the ALLOC_HEAP fsm */
+      enum alloc_heap_fsm_state_e{
+        ALLOC_HEAP_RESET,
+        ALLOC_HEAP_READ,
+        ALLOC_HEAP_WRITE,
+        ALLOC_HEAP_CAS,
+        ALLOC_HEAP_CLEANUP,
+        ALLOC_HEAP_XRAM_RSP
+      };
+
+      /* transaction type, pktid field */
+      enum transaction_type_e
+      {
+          // b3 unused
+          // b2 READ / NOT READ
+          // Si READ
+          //  b1 DATA / INS
+          //  b0 UNC / MISS
+          // Si NOT READ
+          //  b1 accÃšs table llsc type SW / other
+          //  b2 WRITE/CAS/LL/SC
+          TYPE_READ_DATA_UNC          = 0x0,
+          TYPE_READ_DATA_MISS         = 0x1,
+          TYPE_READ_INS_UNC           = 0x2,
+          TYPE_READ_INS_MISS          = 0x3,
+          TYPE_WRITE                  = 0x4,
+          TYPE_CAS                    = 0x5,
+          TYPE_LL                     = 0x6,
+          TYPE_SC                     = 0x7
+      };
+
+      /* SC return values */
+      enum sc_status_type_e
+      {
+          SC_SUCCESS  =   0x00000000,
+          SC_FAIL     =   0x00000001
+      };
+
+      // debug variables (for each FSM)
+      size_t       m_debug_start_cycle;
+      bool         m_debug_ok;
+      bool         m_debug_global;
+      bool         m_debug_tgt_cmd_fsm;
+      bool         m_debug_tgt_rsp_fsm;
+      bool         m_debug_init_cmd_fsm;
+      bool         m_debug_init_rsp_fsm;
+      bool         m_debug_read_fsm;
+      bool         m_debug_write_fsm;
+      bool         m_debug_cas_fsm;
+      bool         m_debug_cleanup_fsm;
+      bool         m_debug_ixr_cmd_fsm;
+      bool         m_debug_ixr_rsp_fsm;
+      bool         m_debug_xram_rsp_fsm;
+      bool         m_debug_previous_hit;
+      size_t       m_debug_previous_count;
+
+      bool         m_monitor_ok;
+      vci_addr_t   m_monitor_base;
+      vci_addr_t   m_monitor_length;
+
+      // instrumentation counters
+      uint32_t     m_cpt_cycles;        // Counter of cycles
+      uint32_t     m_cpt_read;          // Number of READ transactions
+      uint32_t     m_cpt_read_miss;     // Number of MISS READ
+      uint32_t     m_cpt_write;         // Number of WRITE transactions
+      uint32_t     m_cpt_write_miss;    // Number of MISS WRITE
+      uint32_t     m_cpt_write_cells;   // Cumulated length for WRITE transactions
+      uint32_t     m_cpt_write_dirty;   // Cumulated length for WRITE transactions
+      uint32_t     m_cpt_update;        // Number of UPDATE transactions
+      uint32_t     m_cpt_trt_rb;        // Read blocked by a hit in trt
+      uint32_t     m_cpt_trt_full;      // Transaction blocked due to a full trt
+      uint32_t     m_cpt_update_mult;   // Number of targets for UPDATE
+      uint32_t     m_cpt_inval;         // Number of INVAL  transactions
+      uint32_t     m_cpt_inval_mult;    // Number of targets for INVAL
+      uint32_t     m_cpt_inval_brdcast; // Number of BROADCAST INVAL
+      uint32_t     m_cpt_cleanup;       // Number of CLEANUP transactions
+      uint32_t     m_cpt_ll;            // Number of LL transactions
+      uint32_t     m_cpt_sc;            // Number of SC transactions
+      uint32_t     m_cpt_cas;           // Number of CAS transactions
+
+      size_t       m_prev_count;
+
+      protected:
+
+      SC_HAS_PROCESS(VciMemCacheV4);
+
+      public:
+      sc_in<bool>                           p_clk;
+      sc_in<bool>                           p_resetn;
+      soclib::caba::VciTarget<vci_param>    p_vci_tgt;
+      soclib::caba::VciTarget<vci_param>    p_vci_tgt_cleanup;
+      soclib::caba::VciInitiator<vci_param> p_vci_ini;
+      soclib::caba::VciInitiator<vci_param> p_vci_ixr;
+
+#if MONITOR_MEMCACHE_FSM
+      sc_out<int>                           p_read_fsm; 
+      sc_out<int>                           p_write_fsm; 
+      sc_out<int>                           p_xram_rsp_fsm; 
+      sc_out<int>                           p_cas_fsm; 
+      sc_out<int>                           p_cleanup_fsm; 
+      sc_out<int>                           p_alloc_heap_fsm; 
+      sc_out<int>                           p_alloc_dir_fsm; 
+      sc_out<int>                           p_alloc_trt_fsm; 
+      sc_out<int>                           p_alloc_upt_fsm; 
+      sc_out<int>                           p_tgt_cmd_fsm; 
+      sc_out<int>                           p_tgt_rsp_fsm; 
+      sc_out<int>                           p_ixr_cmd_fsm; 
+      sc_out<int>                           p_ixr_rsp_fsm; 
+      sc_out<int>                           p_init_cmd_fsm; 
+      sc_out<int>                           p_init_rsp_fsm; 
+#endif
+                                                        
+      VciMemCacheV4(
+          sc_module_name name,                                // Instance Name
+          const soclib::common::MappingTable &mtp,            // Mapping table for primary requets
+          const soclib::common::MappingTable &mtc,            // Mapping table for coherence requets
+          const soclib::common::MappingTable &mtx,            // Mapping table for XRAM
+          const soclib::common::IntTab &vci_ixr_index,        // VCI port to XRAM (initiator)
+          const soclib::common::IntTab &vci_ini_index,        // VCI port to PROC (initiator)
+          const soclib::common::IntTab &vci_tgt_index,        // VCI port to PROC (target)
+          const soclib::common::IntTab &vci_tgt_index_cleanup,// VCI port to PROC (target) for cleanup
+          size_t nways,                                       // Number of ways per set
+          size_t nsets,                                       // Number of sets
+          size_t nwords,                                      // Number of words per line
+          size_t heap_size=1024,                              // Size of the heap
+          size_t transaction_tab_lines=TRANSACTION_TAB_LINES, // Size of the TRT
+          size_t update_tab_lines=UPDATE_TAB_LINES,           // Size of the UPT
+          size_t debug_start_cycle=0,
+          bool   debug_ok=false);
+
+      ~VciMemCacheV4();
+
+      void print_stats();
+      void print_trace();
+      void copies_monitor(vci_addr_t addr);
+      void start_monitor(vci_addr_t addr, vci_addr_t length);
+      void stop_monitor();
+
+      private:
+
+      void transition();
+      void genMoore();
+      void check_monitor( const char *buf, vci_addr_t addr, data_t data);
+
+      // Component attributes
+      std::list<soclib::common::Segment> m_seglist;  // memory cached into the cache
+      std::list<soclib::common::Segment> m_cseglist; // coherence segment for the cache
+
+      const size_t    m_initiators; // Number of initiators
+      const size_t    m_heap_size;  // Size of the heap
+      const size_t    m_ways;       // Number of ways in a set
+      const size_t    m_sets;       // Number of cache sets
+      const size_t    m_words;      // Number of words in a line
+      const size_t    m_srcid_ixr;  // Srcid for requests to XRAM
+      const size_t    m_srcid_ini;  // Srcid for requests to processors
+
+      uint32_t        m_transaction_tab_lines;
+      TransactionTab  m_transaction_tab;  // xram transaction table
+      uint32_t        m_update_tab_lines;
+      UpdateTab       m_update_tab;       // pending update & invalidate
+      CacheDirectory  m_cache_directory;  // data cache directory
+      CacheData       m_cache_data;       // data array[set][way][word]
+      HeapDirectory   m_heap;             // heap for copies
+      GenericLLSCGlobalTable
+      <
+        32  ,   // desired number of slots
+        4096,   // number of processors in the system
+        8000,   // registratioÃ§n life span (in # of LL operations)
+        typename vci_param::fast_addr_t // address type
+      >
+      m_llsc_table;       // ll/sc global registration table
+
+      // adress masks
+      const soclib::common::AddressMaskingTable<vci_addr_t> m_x;
+      const soclib::common::AddressMaskingTable<vci_addr_t> m_y;
+      const soclib::common::AddressMaskingTable<vci_addr_t> m_z;
+      const soclib::common::AddressMaskingTable<vci_addr_t> m_nline;
+
+      // broadcast address
+      vci_addr_t m_broadcast_address;
+
+      //////////////////////////////////////////////////
+      // Others registers
+      //////////////////////////////////////////////////
+      sc_signal<size_t> r_copies_limit; // Limit of the number of copies for one line
+      sc_signal<size_t> xxx_count;
+
+      //////////////////////////////////////////////////
+      // Registers controlled by the TGT_CMD fsm
+      //////////////////////////////////////////////////
+
+      // Fifo between TGT_CMD fsm and READ fsm
+      GenericFifo<uint64_t>  m_cmd_read_addr_fifo;
+      GenericFifo<size_t>    m_cmd_read_length_fifo;
+      GenericFifo<size_t>    m_cmd_read_srcid_fifo;
+      GenericFifo<size_t>    m_cmd_read_trdid_fifo;
+      GenericFifo<size_t>    m_cmd_read_pktid_fifo;
+
+      // Fifo between TGT_CMD fsm and WRITE fsm
+      GenericFifo<uint64_t>  m_cmd_write_addr_fifo;
+      GenericFifo<bool>      m_cmd_write_eop_fifo;
+      GenericFifo<size_t>    m_cmd_write_srcid_fifo;
+      GenericFifo<size_t>    m_cmd_write_trdid_fifo;
+      GenericFifo<size_t>    m_cmd_write_pktid_fifo;
+      GenericFifo<data_t>    m_cmd_write_data_fifo;
+      GenericFifo<be_t>      m_cmd_write_be_fifo;
+
+      // Fifo between TGT_CMD fsm and CAS fsm
+      GenericFifo<uint64_t>  m_cmd_cas_addr_fifo;
+      GenericFifo<bool>      m_cmd_cas_eop_fifo;
+      GenericFifo<size_t>    m_cmd_cas_srcid_fifo;
+      GenericFifo<size_t>    m_cmd_cas_trdid_fifo;
+      GenericFifo<size_t>    m_cmd_cas_pktid_fifo;
+      GenericFifo<data_t>    m_cmd_cas_wdata_fifo;
+
+      sc_signal<int>         r_tgt_cmd_fsm;
+
+      size_t                   m_nseg;
+      size_t                   m_ncseg;
+      soclib::common::Segment  **m_seg;
+      soclib::common::Segment  **m_cseg;
+      ///////////////////////////////////////////////////////
+      // Registers controlled by the READ fsm
+      ///////////////////////////////////////////////////////
+
+      sc_signal<int>      r_read_fsm;        // FSM state
+      sc_signal<size_t>   r_read_copy;       // Srcid of the first copy
+      sc_signal<size_t>   r_read_copy_cache; // Srcid of the first copy
+      sc_signal<bool>     r_read_copy_inst;  // Type of the first copy
+      sc_signal<tag_t>    r_read_tag;        // cache line tag (in directory)
+      sc_signal<bool>     r_read_is_cnt;     // is_cnt bit (in directory)
+      sc_signal<bool>     r_read_lock;       // lock bit (in directory)
+      sc_signal<bool>     r_read_dirty;      // dirty bit (in directory)
+      sc_signal<size_t>   r_read_count;      // number of copies
+      sc_signal<size_t>   r_read_ptr;        // pointer to the heap
+      sc_signal<data_t> * r_read_data;       // data (one cache line)
+      sc_signal<size_t>   r_read_way;        // associative way (in cache)
+      sc_signal<size_t>   r_read_trt_index;  // Transaction Table index
+      sc_signal<size_t>   r_read_next_ptr;   // Next entry to point to
+      sc_signal<bool>     r_read_last_free;  // Last free entry
+      sc_signal<typename vci_param::fast_addr_t>
+                          r_read_ll_key;     // LL key returned by the llsc_global_table
+
+      // Buffer between READ fsm and IXR_CMD fsm (ask a missing cache line to XRAM)
+      sc_signal<bool>     r_read_to_ixr_cmd_req;    // valid request
+      sc_signal<addr_t>   r_read_to_ixr_cmd_nline;  // cache line index
+      sc_signal<size_t>   r_read_to_ixr_cmd_trdid;  // index in Transaction Table
+
+      // Buffer between READ fsm and TGT_RSP fsm (send a hit read response to L1 cache)
+      sc_signal<bool>     r_read_to_tgt_rsp_req;    // valid request
+      sc_signal<size_t>   r_read_to_tgt_rsp_srcid;  // Transaction srcid
+      sc_signal<size_t>   r_read_to_tgt_rsp_trdid;  // Transaction trdid
+      sc_signal<size_t>   r_read_to_tgt_rsp_pktid;  // Transaction pktid
+      sc_signal<data_t> * r_read_to_tgt_rsp_data;   // data (one cache line)
+      sc_signal<size_t>   r_read_to_tgt_rsp_word;   // first word of the response
+      sc_signal<size_t>   r_read_to_tgt_rsp_length; // length of the response
+      sc_signal<typename vci_param::fast_addr_t>
+                          r_read_to_tgt_rsp_ll_key; // LL key returned by the llsc_global_table
+
+      ///////////////////////////////////////////////////////////////
+      // Registers controlled by the WRITE fsm
+      ///////////////////////////////////////////////////////////////
+
+      sc_signal<int>      r_write_fsm;        // FSM state
+      sc_signal<addr_t>   r_write_address;    // first word address
+      sc_signal<size_t>   r_write_word_index; // first word index in line
+      sc_signal<size_t>   r_write_word_count; // number of words in line
+      sc_signal<size_t>   r_write_srcid;      // transaction srcid
+      sc_signal<size_t>   r_write_trdid;      // transaction trdid
+      sc_signal<size_t>   r_write_pktid;      // transaction pktid
+      sc_signal<data_t> * r_write_data;       // data (one cache line)
+      sc_signal<be_t>   * r_write_be;         // one byte enable per word
+      sc_signal<bool>     r_write_byte;       // (BE != 0X0) and (BE != 0xF)
+      sc_signal<bool>     r_write_is_cnt;     // is_cnt bit (in directory)
+      sc_signal<bool>     r_write_lock;       // lock bit (in directory)
+      sc_signal<tag_t>    r_write_tag;        // cache line tag (in directory)
+      sc_signal<size_t>   r_write_copy;       // first owner of the line
+      sc_signal<size_t>   r_write_copy_cache; // first owner of the line
+      sc_signal<bool>     r_write_copy_inst;  // is this owner a ICache ?
+      sc_signal<size_t>   r_write_count;      // number of copies
+      sc_signal<size_t>   r_write_ptr;        // pointer to the heap
+      sc_signal<size_t>   r_write_next_ptr;   // next pointer to the heap
+      sc_signal<bool>     r_write_to_dec;     // need to decrement update counter
+      sc_signal<size_t>   r_write_way;        // way of the line
+      sc_signal<size_t>   r_write_trt_index;  // index in Transaction Table
+      sc_signal<size_t>   r_write_upt_index;  // index in Update Table
+      sc_signal<bool>     r_write_sc_fail;    // sc command failed
+      sc_signal<bool>     r_write_pending_sc; // sc command pending in WRITE fsm
+
+      // Buffer between WRITE fsm and TGT_RSP fsm (acknowledge a write command from L1)
+      sc_signal<bool>     r_write_to_tgt_rsp_req;     // valid request
+      sc_signal<size_t>   r_write_to_tgt_rsp_srcid;   // transaction srcid
+      sc_signal<size_t>   r_write_to_tgt_rsp_trdid;   // transaction trdid
+      sc_signal<size_t>   r_write_to_tgt_rsp_pktid;   // transaction pktid
+      sc_signal<bool>     r_write_to_tgt_rsp_sc_fail; // sc command failed
+
+      // Buffer between WRITE fsm and IXR_CMD fsm (ask a missing cache line to XRAM)
+      sc_signal<bool>     r_write_to_ixr_cmd_req;   // valid request
+      sc_signal<bool>     r_write_to_ixr_cmd_write; // write request
+      sc_signal<addr_t>   r_write_to_ixr_cmd_nline; // cache line index
+      sc_signal<data_t> * r_write_to_ixr_cmd_data;  // cache line data
+      sc_signal<size_t>   r_write_to_ixr_cmd_trdid; // index in Transaction Table
+
+      // Buffer between WRITE fsm and INIT_CMD fsm (Update/Invalidate L1 caches)
+      sc_signal<bool>     r_write_to_init_cmd_multi_req;     // valid multicast request
+      sc_signal<bool>     r_write_to_init_cmd_brdcast_req;   // valid brdcast request
+      sc_signal<addr_t>   r_write_to_init_cmd_nline;         // cache line index
+      sc_signal<size_t>   r_write_to_init_cmd_trdid;         // index in Update Table
+      sc_signal<data_t> * r_write_to_init_cmd_data;          // data (one cache line)
+      sc_signal<be_t>   * r_write_to_init_cmd_be;            // word enable
+      sc_signal<size_t>   r_write_to_init_cmd_count;         // number of words in line
+      sc_signal<size_t>   r_write_to_init_cmd_index;         // index of first word in line
+      GenericFifo<bool>   m_write_to_init_cmd_inst_fifo;     // fifo for the L1 type
+      GenericFifo<size_t> m_write_to_init_cmd_srcid_fifo;    // fifo for srcids
+#if L1_MULTI_CACHE
+      GenericFifo<size_t> m_write_to_init_cmd_cache_id_fifo; // fifo for srcids
+#endif
+
+      // Buffer between WRITE fsm and INIT_RSP fsm (Decrement UPT entry)
+      sc_signal<bool>     r_write_to_init_rsp_req;       // valid request
+      sc_signal<size_t>   r_write_to_init_rsp_upt_index; // index in update table
+
+      /////////////////////////////////////////////////////////
+      // Registers controlled by INIT_RSP fsm
+      //////////////////////////////////////////////////////////
+
+      sc_signal<int>      r_init_rsp_fsm;       // FSM state
+      sc_signal<size_t>   r_init_rsp_upt_index; // index in the Update Table
+      sc_signal<size_t>   r_init_rsp_srcid;     // pending write srcid
+      sc_signal<size_t>   r_init_rsp_trdid;     // pending write trdid
+      sc_signal<size_t>   r_init_rsp_pktid;     // pending write pktid
+      sc_signal<addr_t>   r_init_rsp_nline;     // pending write nline
+
+      // Buffer between INIT_RSP fsm and TGT_RSP fsm (complete write/update transaction)
+      sc_signal<bool>     r_init_rsp_to_tgt_rsp_req;   // valid request
+      sc_signal<size_t>   r_init_rsp_to_tgt_rsp_srcid; // Transaction srcid
+      sc_signal<size_t>   r_init_rsp_to_tgt_rsp_trdid; // Transaction trdid
+      sc_signal<size_t>   r_init_rsp_to_tgt_rsp_pktid; // Transaction pktid
+
+      ///////////////////////////////////////////////////////
+      // Registers controlled by CLEANUP fsm
+      ///////////////////////////////////////////////////////
+
+      sc_signal<int>      r_cleanup_fsm;           // FSM state
+      sc_signal<size_t>   r_cleanup_srcid;         // transaction srcid
+      sc_signal<size_t>   r_cleanup_trdid;         // transaction trdid
+      sc_signal<size_t>   r_cleanup_pktid;         // transaction pktid
+      sc_signal<addr_t>   r_cleanup_nline;         // cache line index
+
+      sc_signal<copy_t>   r_cleanup_copy;          // first copy
+      sc_signal<copy_t>   r_cleanup_copy_cache;    // first copy
+      sc_signal<size_t>   r_cleanup_copy_inst;     // type of the first copy
+      sc_signal<copy_t>   r_cleanup_count;         // number of copies
+      sc_signal<size_t>   r_cleanup_ptr;           // pointer to the heap
+      sc_signal<size_t>   r_cleanup_prev_ptr;      // previous pointer to the heap
+      sc_signal<size_t>   r_cleanup_prev_srcid;    // srcid of previous heap entry
+      sc_signal<size_t>   r_cleanup_prev_cache_id; // srcid of previous heap entry
+      sc_signal<bool>     r_cleanup_prev_inst;     // inst bit of previous heap entry
+      sc_signal<size_t>   r_cleanup_next_ptr;      // next pointer to the heap
+      sc_signal<tag_t>    r_cleanup_tag;           // cache line tag (in directory)
+      sc_signal<bool>     r_cleanup_is_cnt;        // inst bit (in directory)
+      sc_signal<bool>     r_cleanup_lock;          // lock bit (in directory)
+      sc_signal<bool>     r_cleanup_dirty;         // dirty bit (in directory)
+      sc_signal<size_t>   r_cleanup_way;           // associative way (in cache)
+
+      sc_signal<size_t>   r_cleanup_write_srcid;   // srcid of write response
+      sc_signal<size_t>   r_cleanup_write_trdid;   // trdid of write rsp
+      sc_signal<size_t>   r_cleanup_write_pktid;   // pktid of write rsp
+      sc_signal<bool>     r_cleanup_need_rsp;      // needs a write rsp
+
+      sc_signal<size_t>   r_cleanup_index;         // index of the INVAL line (in the UPT)
+
+      // Buffer between CLEANUP fsm and TGT_RSP fsm (acknowledge a write command from L1)
+      sc_signal<bool>     r_cleanup_to_tgt_rsp_req;   // valid request
+      sc_signal<size_t>   r_cleanup_to_tgt_rsp_srcid; // transaction srcid
+      sc_signal<size_t>   r_cleanup_to_tgt_rsp_trdid; // transaction trdid
+      sc_signal<size_t>   r_cleanup_to_tgt_rsp_pktid; // transaction pktid
+
+      ///////////////////////////////////////////////////////
+      // Registers controlled by CAS fsm
+      ///////////////////////////////////////////////////////
+
+      sc_signal<int>      r_cas_fsm;        // FSM state
+      sc_signal<data_t>   r_cas_wdata;      // write data word
+      sc_signal<data_t> * r_cas_rdata;      // read data word
+      sc_signal<uint32_t> r_cas_lfsr;       // lfsr for random introducing
+      sc_signal<size_t>   r_cas_cpt;        // size of command
+      sc_signal<copy_t>   r_cas_copy;       // Srcid of the first copy
+      sc_signal<copy_t>   r_cas_copy_cache; // Srcid of the first copy
+      sc_signal<bool>     r_cas_copy_inst;  // Type of the first copy
+      sc_signal<size_t>   r_cas_count;      // number of copies
+      sc_signal<size_t>   r_cas_ptr;        // pointer to the heap
+      sc_signal<size_t>   r_cas_next_ptr;   // next pointer to the heap
+      sc_signal<bool>     r_cas_is_cnt;     // is_cnt bit (in directory)
+      sc_signal<bool>     r_cas_dirty;      // dirty bit (in directory)
+      sc_signal<size_t>   r_cas_way;        // way in directory
+      sc_signal<size_t>   r_cas_set;        // set in directory
+      sc_signal<data_t>   r_cas_tag;        // cache line tag (in directory)
+      sc_signal<size_t>   r_cas_trt_index;  // Transaction Table index
+      sc_signal<size_t>   r_cas_upt_index;  // Update Table index
+      sc_signal<data_t> * r_cas_data;       // cache line data
+
+      // Buffer between CAS fsm and INIT_CMD fsm (XRAM read)
+      sc_signal<bool>     r_cas_to_ixr_cmd_req;   // valid request
+      sc_signal<addr_t>   r_cas_to_ixr_cmd_nline; // cache line index
+      sc_signal<size_t>   r_cas_to_ixr_cmd_trdid; // index in Transaction Table
+      sc_signal<bool>     r_cas_to_ixr_cmd_write; // write request
+      sc_signal<data_t> * r_cas_to_ixr_cmd_data;  // cache line data
+
+
+      // Buffer between CAS fsm and TGT_RSP fsm
+      sc_signal<bool>     r_cas_to_tgt_rsp_req;   // valid request
+      sc_signal<data_t>   r_cas_to_tgt_rsp_data;  // read data word
+      sc_signal<size_t>   r_cas_to_tgt_rsp_srcid; // Transaction srcid
+      sc_signal<size_t>   r_cas_to_tgt_rsp_trdid; // Transaction trdid
+      sc_signal<size_t>   r_cas_to_tgt_rsp_pktid; // Transaction pktid
+
+      // Buffer between CAS fsm and INIT_CMD fsm (Update/Invalidate L1 caches)
+      sc_signal<bool>     r_cas_to_init_cmd_multi_req;     // valid request
+      sc_signal<bool>     r_cas_to_init_cmd_brdcast_req;   // brdcast request
+      sc_signal<addr_t>   r_cas_to_init_cmd_nline;         // cache line index
+      sc_signal<size_t>   r_cas_to_init_cmd_trdid;         // index in Update Table
+      sc_signal<data_t>   r_cas_to_init_cmd_wdata;         // data (one word)
+      sc_signal<bool>     r_cas_to_init_cmd_is_long;       // it is a 64 bits CAS
+      sc_signal<data_t>   r_cas_to_init_cmd_wdata_high;    // data high (one word)
+      sc_signal<size_t>   r_cas_to_init_cmd_index;         // index of the word in line
+      GenericFifo<bool>   m_cas_to_init_cmd_inst_fifo;     // fifo for the L1 type
+      GenericFifo<size_t> m_cas_to_init_cmd_srcid_fifo;    // fifo for srcids
+#if L1_MULTI_CACHE
+      GenericFifo<size_t> m_cas_to_init_cmd_cache_id_fifo; // fifo for srcids
+#endif
+
+      // Buffer between CAS fsm and INIT_RSP fsm (Decrement UPT entry)
+      sc_signal<bool>     r_cas_to_init_rsp_req;       // valid request
+      sc_signal<size_t>   r_cas_to_init_rsp_upt_index; // index in update table
+
+      ////////////////////////////////////////////////////
+      // Registers controlled by the IXR_RSP fsm
+      ////////////////////////////////////////////////////
+
+      sc_signal<int>      r_ixr_rsp_fsm;       // FSM state
+      sc_signal<size_t>   r_ixr_rsp_trt_index; // TRT entry index
+      sc_signal<size_t>   r_ixr_rsp_cpt;       // word counter
+
+      // Buffer between IXR_RSP fsm and XRAM_RSP fsm  (response from the XRAM)
+      sc_signal<bool>   * r_ixr_rsp_to_xram_rsp_rok; // A xram response is ready
+
+      ////////////////////////////////////////////////////
+      // Registers controlled by the XRAM_RSP fsm
+      ////////////////////////////////////////////////////
+
+      sc_signal<int>      r_xram_rsp_fsm;               // FSM state
+      sc_signal<size_t>   r_xram_rsp_trt_index;         // TRT entry index
+      TransactionTabEntry r_xram_rsp_trt_buf;           // TRT entry local buffer
+      sc_signal<bool>     r_xram_rsp_victim_inval;      // victim line invalidate
+      sc_signal<bool>     r_xram_rsp_victim_is_cnt;     // victim line inst bit
+      sc_signal<bool>     r_xram_rsp_victim_dirty;      // victim line dirty bit
+      sc_signal<size_t>   r_xram_rsp_victim_way;        // victim line way
+      sc_signal<size_t>   r_xram_rsp_victim_set;        // victim line set
+      sc_signal<addr_t>   r_xram_rsp_victim_nline;      // victim line index
+      sc_signal<copy_t>   r_xram_rsp_victim_copy;       // victim line first copy
+      sc_signal<copy_t>   r_xram_rsp_victim_copy_cache; // victim line first copy
+      sc_signal<bool>     r_xram_rsp_victim_copy_inst;  // victim line type of first copy
+      sc_signal<size_t>   r_xram_rsp_victim_count;      // victim line number of copies
+      sc_signal<size_t>   r_xram_rsp_victim_ptr;        // victim line pointer to the heap
+      sc_signal<data_t> * r_xram_rsp_victim_data;       // victim line data
+      sc_signal<size_t>   r_xram_rsp_upt_index;         // UPT entry index
+      sc_signal<size_t>   r_xram_rsp_next_ptr;          // Next pointer to the heap
+
+      // Buffer between XRAM_RSP fsm and TGT_RSP fsm  (response to L1 cache)
+      sc_signal<bool>     r_xram_rsp_to_tgt_rsp_req;    // Valid request
+      sc_signal<size_t>   r_xram_rsp_to_tgt_rsp_srcid;  // Transaction srcid
+      sc_signal<size_t>   r_xram_rsp_to_tgt_rsp_trdid;  // Transaction trdid
+      sc_signal<size_t>   r_xram_rsp_to_tgt_rsp_pktid;  // Transaction pktid
+      sc_signal<data_t> * r_xram_rsp_to_tgt_rsp_data;   // data (one cache line)
+      sc_signal<size_t>   r_xram_rsp_to_tgt_rsp_word;   // first word index
+      sc_signal<size_t>   r_xram_rsp_to_tgt_rsp_length; // length of the response
+      sc_signal<bool>     r_xram_rsp_to_tgt_rsp_rerror; // send error to requester
+      sc_signal<typename vci_param::fast_addr_t>
+                          r_xram_rsp_to_tgt_rsp_ll_key; // LL key returned by the llsc_global_table
+
+      // Buffer between XRAM_RSP fsm and INIT_CMD fsm (Inval L1 Caches)
+      sc_signal<bool>     r_xram_rsp_to_init_cmd_multi_req;     // Valid request
+      sc_signal<bool>     r_xram_rsp_to_init_cmd_brdcast_req;   // Broadcast request
+      sc_signal<addr_t>   r_xram_rsp_to_init_cmd_nline;         // cache line index;
+      sc_signal<size_t>   r_xram_rsp_to_init_cmd_trdid;         // index of UPT entry
+      GenericFifo<bool>   m_xram_rsp_to_init_cmd_inst_fifo;     // fifo for the L1 type
+      GenericFifo<size_t> m_xram_rsp_to_init_cmd_srcid_fifo;    // fifo for srcids
+#if L1_MULTI_CACHE
+      GenericFifo<size_t> m_xram_rsp_to_init_cmd_cache_id_fifo; // fifo for srcids
+#endif
+
+      // Buffer between XRAM_RSP fsm and IXR_CMD fsm (XRAM write)
+      sc_signal<bool>     r_xram_rsp_to_ixr_cmd_req;   // Valid request
+      sc_signal<addr_t>   r_xram_rsp_to_ixr_cmd_nline; // cache line index
+      sc_signal<data_t> * r_xram_rsp_to_ixr_cmd_data;  // cache line data
+      sc_signal<size_t>   r_xram_rsp_to_ixr_cmd_trdid; // index in transaction table
+
+      ////////////////////////////////////////////////////
+      // Registers controlled by the IXR_CMD fsm
+      ////////////////////////////////////////////////////
+
+      sc_signal<int>      r_ixr_cmd_fsm;
+      sc_signal<size_t>   r_ixr_cmd_cpt;
+
+      ////////////////////////////////////////////////////
+      // Registers controlled by TGT_RSP fsm
+      ////////////////////////////////////////////////////
+
+      sc_signal<int>      r_tgt_rsp_fsm;
+      sc_signal<size_t>   r_tgt_rsp_cpt;
+      sc_signal<bool>     r_tgt_rsp_key_sent;
+
+      ////////////////////////////////////////////////////
+      // Registers controlled by INIT_CMD fsm
+      ////////////////////////////////////////////////////
+
+      sc_signal<int>      r_init_cmd_fsm;
+      sc_signal<size_t>   r_init_cmd_cpt;
+      sc_signal<bool>     r_init_cmd_inst;
+
+      ////////////////////////////////////////////////////
+      // Registers controlled by ALLOC_DIR fsm
+      ////////////////////////////////////////////////////
+
+      sc_signal<int>      r_alloc_dir_fsm;
+      sc_signal<unsigned> r_alloc_dir_reset_cpt;
+
+      ////////////////////////////////////////////////////
+      // Registers controlled by ALLOC_TRT fsm
+      ////////////////////////////////////////////////////
+
+      sc_signal<int>      r_alloc_trt_fsm;
+
+      ////////////////////////////////////////////////////
+      // Registers controlled by ALLOC_UPT fsm
+      ////////////////////////////////////////////////////
+
+      sc_signal<int>      r_alloc_upt_fsm;
+
+      ////////////////////////////////////////////////////
+      // Registers controlled by ALLOC_HEAP fsm
+      ////////////////////////////////////////////////////
+
+      sc_signal<int>      r_alloc_heap_fsm;
+      sc_signal<unsigned> r_alloc_heap_reset_cpt;
+    }; // end class VciMemCacheV4
+
+}}
+
+#endif
+
+// Local Variables:
+// tab-width: 2
+// c-basic-offset: 2
+// c-file-offsets:((innamespace . 0)(inline-open . 0))
+// indent-tabs-mode: nil
+// End:
+
+// vim: filetype=cpp:expandtab:shiftwidth=2:tabstop=2:softtabstop=2
+
Index: branches/v4/modules/vci_mem_cache_v4/caba/source/include/xram_transaction_v4.h
===================================================================
--- branches/v4/modules/vci_mem_cache_v4/caba/source/include/xram_transaction_v4.h	(revision 371)
+++ branches/v4/modules/vci_mem_cache_v4/caba/source/include/xram_transaction_v4.h	(revision 371)
@@ -0,0 +1,422 @@
+#ifndef XRAM_TRANSACTION_V4_H_
+#define XRAM_TRANSACTION_V4_H_
+
+#include <inttypes.h>
+#include <systemc>
+#include <cassert>
+#include "arithmetics.h"
+
+#define DEBUG_XRAM_TRANSACTION 0
+
+////////////////////////////////////////////////////////////////////////
+//                  A transaction tab entry         
+////////////////////////////////////////////////////////////////////////
+
+class TransactionTabEntry {
+    typedef uint32_t              size_t;
+    typedef uint32_t              data_t;
+    typedef sc_dt::sc_uint<40>    addr_t;
+    typedef uint32_t              be_t;
+
+    public:
+    bool 		        valid;     	    // entry valid 
+    bool 		        xram_read; 	    // read request to XRAM
+    addr_t   	        nline;    	    // index (zy) of the requested line
+    size_t 	            srcid;     	    // processor requesting the transaction
+    size_t 	            trdid;     	    // processor requesting the transaction
+    size_t 	            pktid;     	    // processor requesting the transaction
+    bool 		        proc_read;	    // read request from processor
+    size_t 	            read_length;    // length of the read (for the response)
+    size_t 	            word_index;    	// index of the first read word (for the response)
+    std::vector<data_t> wdata;          // write buffer (one cache line)
+    std::vector<be_t>   wdata_be;    	// be for each data in the write buffer
+    bool                rerror;         // error returned by xram
+    data_t              ll_key;         // LL key returned by the llsc_global_table
+
+    /////////////////////////////////////////////////////////////////////
+    // The init() function initializes the entry 
+    /////////////////////////////////////////////////////////////////////
+    void init()
+    {
+        valid		= false;
+        rerror      = false;
+    }
+
+    /////////////////////////////////////////////////////////////////////
+    // The alloc() function initializes the vectors of an entry
+    // Its arguments are :
+    // - n_words : number of words per line in the cache
+    /////////////////////////////////////////////////////////////////////
+    void alloc(size_t n_words)
+    {
+        wdata_be.reserve( (int)n_words );
+        wdata.reserve( (int)n_words );
+        for(size_t i=0; i<n_words; i++)
+        {
+            wdata_be.push_back(0);
+            wdata.push_back(0);
+        }
+    }
+
+    ////////////////////////////////////////////////////////////////////
+    // The copy() function copies an existing entry
+    // Its arguments are :
+    // - source : the transaction tab entry to copy
+    ////////////////////////////////////////////////////////////////////
+    void copy(const TransactionTabEntry &source)
+    {
+        valid	    = source.valid;
+        xram_read 	= source.xram_read;
+        nline	    = source.nline;
+        srcid	    = source.srcid;
+        trdid	    = source.trdid;
+        pktid	    = source.pktid;
+        proc_read 	= source.proc_read;
+        read_length = source.read_length;
+        word_index	= source.word_index;
+        wdata_be.assign(source.wdata_be.begin(),source.wdata_be.end());
+        wdata.assign(source.wdata.begin(),source.wdata.end());
+        rerror      = source.rerror;
+        ll_key      = source.ll_key;
+    }
+
+    ////////////////////////////////////////////////////////////////////
+    // The print() function prints the entry 
+    ////////////////////////////////////////////////////////////////////
+    void print(){
+        std::cout << "valid       = " << valid        << std::endl;
+        std::cout << "xram_read   = " << xram_read    << std::endl;
+        std::cout << "nline       = " << std::hex << nline << std::endl;
+        std::cout << "srcid       = " << srcid        << std::endl;
+        std::cout << "trdid       = " << trdid        << std::endl;
+        std::cout << "pktid       = " << pktid        << std::endl;
+        std::cout << "proc_read   = " << proc_read    << std::endl;
+        std::cout << "read_length = " << read_length  << std::endl;
+        std::cout << "word_index  = " << word_index   << std::endl; 
+        for(size_t i=0; i<wdata_be.size() ; i++){
+            std::cout << "wdata_be [" << i <<"] = " << wdata_be[i] << std::endl;
+        }
+        for(size_t i=0; i<wdata.size() ; i++){
+            std::cout << "wdata [" << i <<"] = " << wdata[i] << std::endl;
+        }
+        std::cout << std::endl;
+        std::cout << "rerror      = " << rerror       << std::endl;
+    }
+
+    /////////////////////////////////////////////////////////////////////
+    // 		Constructors
+    /////////////////////////////////////////////////////////////////////
+
+    TransactionTabEntry()
+    {
+        wdata_be.clear();
+        wdata.clear();
+        valid=false;
+        rerror=false;
+    }
+
+    TransactionTabEntry(const TransactionTabEntry &source){
+        valid	    = source.valid;
+        xram_read	= source.xram_read;
+        nline	    = source.nline;
+        srcid	    = source.srcid;
+        trdid	    = source.trdid;
+        pktid	    = source.pktid;
+        proc_read	= source.proc_read;
+        read_length = source.read_length;
+        word_index	= source.word_index;
+        wdata_be.assign(source.wdata_be.begin(),source.wdata_be.end());
+        wdata.assign(source.wdata.begin(),source.wdata.end());	
+        rerror      = source.rerror;
+        ll_key      = source.ll_key;
+    }
+
+}; // end class TransactionTabEntry
+
+////////////////////////////////////////////////////////////////////////
+//                  The transaction tab                              
+////////////////////////////////////////////////////////////////////////
+class TransactionTab{
+    typedef uint32_t size_t;
+    typedef uint32_t data_t;
+    typedef sc_dt::sc_uint<40> addr_t;
+    typedef uint32_t be_t;
+
+    private:
+    size_t size_tab;                // The size of the tab
+
+    data_t be_to_mask(be_t be)
+    {
+        data_t ret = 0;
+        if ( be&0x1 ) {
+            ret = ret | 0x000000FF;
+        }
+        if ( be&0x2 ) {
+            ret = ret | 0x0000FF00;
+        }
+        if ( be&0x4 ) {
+            ret = ret | 0x00FF0000;
+        }
+        if ( be&0x8 ) {
+            ret = ret | 0xFF000000;
+        }
+        return ret;
+    }
+
+    public:
+    TransactionTabEntry *tab;       // The transaction tab
+
+    ////////////////////////////////////////////////////////////////////
+    //		Constructors
+    ////////////////////////////////////////////////////////////////////
+    TransactionTab()
+    {
+        size_tab=0;
+        tab=NULL;
+    }
+
+    TransactionTab(size_t n_entries, size_t n_words)
+    {
+        size_tab = n_entries;
+        tab = new TransactionTabEntry[size_tab];
+        for ( size_t i=0; i<size_tab; i++) {
+            tab[i].alloc(n_words);
+        }
+    }
+
+    ~TransactionTab()
+    {
+        delete [] tab;
+    }
+
+    /////////////////////////////////////////////////////////////////////
+    // The size() function returns the size of the tab
+    /////////////////////////////////////////////////////////////////////
+    size_t size()
+    {
+        return size_tab;
+    }
+
+    /////////////////////////////////////////////////////////////////////
+    // The init() function initializes the transaction tab entries
+    /////////////////////////////////////////////////////////////////////
+    void init()
+    {
+        for ( size_t i=0; i<size_tab; i++) {
+            tab[i].init();
+        }
+    }
+
+    /////////////////////////////////////////////////////////////////////
+    // The print() function prints a transaction tab entry
+    // Arguments :
+    // - index : the index of the entry to print
+    /////////////////////////////////////////////////////////////////////
+    void print(const size_t index)
+    {
+        assert( (index < size_tab) 
+                && "Invalid Transaction Tab Entry");
+        tab[index].print();
+        return;
+    }
+
+    /////////////////////////////////////////////////////////////////////
+    // The read() function returns a transaction tab entry.
+    // Arguments :
+    // - index : the index of the entry to read
+    /////////////////////////////////////////////////////////////////////
+    TransactionTabEntry read(const size_t index)
+    {
+        assert( (index < size_tab) 
+                && "Invalid Transaction Tab Entry");
+        return tab[index];
+    }
+
+    /////////////////////////////////////////////////////////////////////
+    // The full() function returns the state of the transaction tab
+    // Arguments :
+    // - index : (return argument) the index of an empty entry 
+    // The function returns true if the transaction tab is full
+    /////////////////////////////////////////////////////////////////////
+    bool full(size_t &index)
+    {
+        for(size_t i=0; i<size_tab; i++){
+            if(!tab[i].valid){
+                index=i;
+                return false;	
+            }
+        }
+        return true;
+    }
+
+    /////////////////////////////////////////////////////////////////////
+    // The hit_read() function checks if an XRAM read transaction exists 
+    // for a given cache line.
+    // Arguments :
+    // - index : (return argument) the index of the hit entry, if there is 
+    // - nline : the index (zy) of the requested line
+    // The function returns true if a read request has already been sent
+    //////////////////////////////////////////////////////////////////////
+    bool hit_read(const addr_t nline,size_t &index)
+    {
+        for(size_t i=0; i<size_tab; i++){
+            if((tab[i].valid && (nline==tab[i].nline)) && (tab[i].xram_read)) {
+                index=i;
+                return true;	
+            }
+        }
+        return false;
+    }
+
+    ///////////////////////////////////////////////////////////////////////
+    // The hit_write() function looks if an XRAM write transaction exists 
+    // for a given line.
+    // Arguments :
+    // - nline : the index (zy) of the requested line
+    // The function returns true if a write request has already been sent
+    ///////////////////////////////////////////////////////////////////////
+    bool hit_write(const addr_t nline)
+    {
+        for(size_t i=0; i<size_tab; i++){
+            if(tab[i].valid && (nline==tab[i].nline) && !(tab[i].xram_read)) {
+                return true;	
+            }
+        }
+        return false;
+    }
+
+    /////////////////////////////////////////////////////////////////////
+    // The write_data_mask() function writes a vector of data (a line).
+    // The data is written only if the corresponding bits are set
+    // in the be vector. 
+    // Arguments :
+    // - index : the index of the request in the transaction tab
+    // - be   : vector of be 
+    // - data : vector of data
+    /////////////////////////////////////////////////////////////////////
+    void write_data_mask(const size_t index, 
+            const std::vector<be_t> &be, 
+            const std::vector<data_t> &data) 
+    {
+        assert( (index < size_tab) 
+                && "Invalid Transaction Tab Entry");
+        assert(be.size()==tab[index].wdata_be.size() 
+                && "Bad data mask in write_data_mask in TransactionTab");
+        assert(data.size()==tab[index].wdata.size() 
+                && "Bad data in write_data_mask in TransactionTab");
+
+        for(size_t i=0; i<tab[index].wdata_be.size() ; i++) {
+            tab[index].wdata_be[i] = tab[index].wdata_be[i] | be[i];
+            data_t mask = be_to_mask(be[i]);
+            tab[index].wdata[i] = (tab[index].wdata[i] & ~mask) | (data[i] & mask);
+        }
+    }
+
+    /////////////////////////////////////////////////////////////////////
+    // The set() function registers a transaction (read or write)
+    // to the XRAM in the transaction tab.
+    // Arguments :
+    // - index : index in the transaction tab
+    // - xram_read : transaction type (read or write a cache line)
+    // - nline : the index (zy) of the cache line
+    // - srcid : srcid of the initiator that caused the transaction
+    // - trdid : trdid of the initiator that caused the transaction
+    // - pktid : pktid of the initiator that caused the transaction
+    // - proc_read : does the initiator want a copy
+    // - read_length : length of read (in case of processor read)
+    // - word_index : index in the line (in case of single word read)
+    // - data : the data to write (in case of write)
+    // - data_be : the mask of the data to write (in case of write)
+    // - ll_key  : the ll key (if any) returned by the llsc_global_table
+    /////////////////////////////////////////////////////////////////////
+    void set(const size_t index,
+            const bool xram_read,
+            const addr_t nline,
+            const size_t srcid,
+            const size_t trdid,
+            const size_t pktid,
+            const bool proc_read,
+            const size_t read_length,
+            const size_t word_index,
+            const std::vector<be_t> &data_be,
+            const std::vector<data_t> &data, 
+            const data_t ll_key = 0) 
+    {
+        assert( (index < size_tab) 
+                && "The selected entry is out of range in set() Transaction Tab");
+        assert(data_be.size()==tab[index].wdata_be.size() 
+                && "Bad data_be argument in set() TransactionTab");
+        assert(data.size()==tab[index].wdata.size() 
+                && "Bad data argument in set() TransactionTab");
+
+        tab[index].valid	        = true;
+        tab[index].xram_read        = xram_read;
+        tab[index].nline	        = nline;
+        tab[index].srcid	        = srcid;
+        tab[index].trdid	        = trdid;
+        tab[index].pktid	        = pktid;
+        tab[index].proc_read	    = proc_read;
+        tab[index].read_length	    = read_length;
+        tab[index].word_index	    = word_index;
+        tab[index].ll_key   	    = ll_key;
+        for(size_t i=0; i<tab[index].wdata.size(); i++) 
+        {
+            tab[index].wdata_be[i]    = data_be[i];
+            tab[index].wdata[i]       = data[i];
+        }
+    }
+
+    /////////////////////////////////////////////////////////////////////
+    // The write_rsp() function writes a word of the response to an 
+    // XRAM read transaction.
+    // The BE field in TRT is taken into account.
+    // Arguments :
+    // - index : the index of the transaction in the transaction tab
+    // - word_index : the index of the data in the line
+    // - data : the data to write
+    // - error : invalid data
+    /////////////////////////////////////////////////////////////////////
+    void write_rsp(const size_t index,
+            const size_t word,
+            const data_t data,
+            const bool   rerror)
+    {
+        assert( (index < size_tab) 
+                && "Selected entry  out of range in write_rsp() Transaction Tab");
+        assert( (word <= tab[index].wdata_be.size()) 
+                && "Bad word_index in write_rsp() in TransactionTab");
+        assert( tab[index].valid 
+                && "Transaction Tab Entry invalid in write_rsp()");
+        assert( tab[index].xram_read 
+                && "Selected entry is not an XRAM read transaction in write_rsp()");
+
+        data_t mask = be_to_mask(tab[index].wdata_be[word]);
+        tab[index].wdata[word] = (tab[index].wdata[word] & mask) | (data & ~mask);
+        tab[index].rerror |= rerror;
+    }
+
+    /////////////////////////////////////////////////////////////////////
+    // The erase() function erases an entry in the transaction tab.
+    // Arguments :
+    // - index : the index of the request in the transaction tab
+    /////////////////////////////////////////////////////////////////////
+    void erase(const size_t index)
+    {
+        assert( (index < size_tab) 
+                && "The selected entry is out of range in erase() Transaction Tab");
+        tab[index].valid	= false;
+        tab[index].rerror   = false;
+    }
+}; // end class TransactionTab
+
+#endif
+
+// Local Variables:
+// tab-width: 4
+// c-basic-offset: 4
+// c-file-offsets:((innamespace . 0)(inline-open . 0))
+// indent-tabs-mode: nil
+// End:
+
+// vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4
+
Index: branches/v4/modules/vci_mem_cache_v4/caba/source/src/vci_mem_cache_v4.cpp
===================================================================
--- branches/v4/modules/vci_mem_cache_v4/caba/source/src/vci_mem_cache_v4.cpp	(revision 371)
+++ branches/v4/modules/vci_mem_cache_v4/caba/source/src/vci_mem_cache_v4.cpp	(revision 371)
@@ -0,0 +1,6943 @@
+ /* -*- c++ -*-
+ * File       : vci_mem_cache_v4.cpp
+ * Date       : 30/10/2008
+ * Copyright  : UPMC / LIP6
+ * Authors    : Alain Greiner / Eric Guthmuller
+ *
+ * SOCLIB_LGPL_HEADER_BEGIN
+ *
+ * This file is part of SoCLib, GNU LGPLv2.1.
+ *
+ * SoCLib is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU Lesser General Public License as published
+ * by the Free Software Foundation; version 2.1 of the License.
+ *
+ * SoCLib is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with SoCLib; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301 USA
+ *
+ * SOCLIB_LGPL_HEADER_END
+ *
+ * Maintainers: alain eric.guthmuller@polytechnique.edu
+ *              cesar.fuguet-tortolero@lip6.fr
+ *              alexandre.joannou@lip6.fr
+ */
+
+#include "../include/vci_mem_cache_v4.h"
+
+//////   debug services   ///////////////////////////////////////////////////////
+// All debug messages are conditionned by two variables:
+// - compile time   : DEBUG_MEMC_*** : defined below
+// - execution time : m_debug_***    : defined by constructor arguments
+//    m_debug_* = (m_debug_ok) and (m_cpt_cycle > m_debug_start_cycle)
+/////////////////////////////////////////////////////////////////////////////////
+
+#define DEBUG_MEMC_GLOBAL   0 // synthetic trace of all FSMs
+#define DEBUG_MEMC_READ     1 // detailed trace of READ FSM
+#define DEBUG_MEMC_WRITE    1 // detailed trace of WRITE FSM
+#define DEBUG_MEMC_CAS      1 // detailed trace of CAS FSM
+#define DEBUG_MEMC_IXR_CMD  1 // detailed trace of IXR_RSP FSM
+#define DEBUG_MEMC_IXR_RSP  1 // detailed trace of IXR_RSP FSM
+#define DEBUG_MEMC_XRAM_RSP 1 // detailed trace of XRAM_RSP FSM
+#define DEBUG_MEMC_INIT_CMD 1 // detailed trace of INIT_CMD FSM
+#define DEBUG_MEMC_INIT_RSP 1 // detailed trace of INIT_RSP FSM
+#define DEBUG_MEMC_TGT_CMD  1 // detailed trace of TGT_CMD FSM
+#define DEBUG_MEMC_TGT_RSP  1 // detailed trace of TGT_RSP FSM
+#define DEBUG_MEMC_CLEANUP  1 // detailed trace of CLEANUP FSM
+
+#define RANDOMIZE_CAS       1
+
+namespace soclib { namespace caba {
+
+  const char *tgt_cmd_fsm_str[] = {
+    "TGT_CMD_IDLE",
+    "TGT_CMD_READ",
+    "TGT_CMD_WRITE",
+    "TGT_CMD_CAS"
+  };
+  const char *tgt_rsp_fsm_str[] = {
+    "TGT_RSP_READ_IDLE",
+    "TGT_RSP_WRITE_IDLE",
+    "TGT_RSP_CAS_IDLE",
+    "TGT_RSP_XRAM_IDLE",
+    "TGT_RSP_INIT_IDLE",
+    "TGT_RSP_CLEANUP_IDLE",
+    "TGT_RSP_READ",
+    "TGT_RSP_WRITE",
+    "TGT_RSP_CAS",
+    "TGT_RSP_XRAM",
+    "TGT_RSP_INIT",
+    "TGT_RSP_CLEANUP"
+  };
+  const char *init_cmd_fsm_str[] = {
+    "INIT_CMD_INVAL_IDLE",
+    "INIT_CMD_INVAL_NLINE",
+    "INIT_CMD_XRAM_BRDCAST",
+    "INIT_CMD_WRITE_BRDCAST",
+    "INIT_CMD_CAS_BRDCAST",
+    "INIT_CMD_UPDT_IDLE",
+    "INIT_CMD_UPDT_NLINE",
+    "INIT_CMD_UPDT_INDEX",
+    "INIT_CMD_UPDT_DATA",
+    "INIT_CMD_CAS_UPDT_IDLE",
+    "INIT_CMD_CAS_UPDT_NLINE",
+    "INIT_CMD_CAS_UPDT_INDEX",
+    "INIT_CMD_CAS_UPDT_DATA",
+    "INIT_CMD_CAS_UPDT_DATA_HIGH"
+  };
+  const char *init_rsp_fsm_str[] = {
+    "INIT_RSP_IDLE",
+    "INIT_RSP_UPT_LOCK",
+    "INIT_RSP_UPT_CLEAR",
+    "INIT_RSP_END"
+  };
+  const char *read_fsm_str[] = {
+    "READ_IDLE",
+    "READ_DIR_REQ",
+    "READ_DIR_LOCK",
+    "READ_DIR_HIT",
+    "READ_HEAP_REQ",
+    "READ_HEAP_LOCK",
+    "READ_HEAP_WRITE",
+    "READ_HEAP_ERASE",
+    "READ_HEAP_LAST",
+    "READ_RSP",
+    "READ_TRT_LOCK",
+    "READ_TRT_SET",
+    "READ_TRT_REQ"
+  };
+  const char *write_fsm_str[] = {
+    "WRITE_IDLE",
+    "WRITE_NEXT",
+    "WRITE_DIR_REQ",
+    "WRITE_DIR_LOCK",
+    "WRITE_DIR_READ",
+    "WRITE_DIR_HIT",
+    "WRITE_UPT_LOCK",
+    "WRITE_UPT_HEAP_LOCK",
+    "WRITE_UPT_REQ",
+    "WRITE_UPT_NEXT",
+    "WRITE_UPT_DEC",
+    "WRITE_RSP",
+    "WRITE_MISS_TRT_LOCK",
+    "WRITE_MISS_TRT_DATA",
+    "WRITE_MISS_TRT_SET",
+    "WRITE_MISS_XRAM_REQ",
+    "WRITE_BC_TRT_LOCK",
+    "WRITE_BC_UPT_LOCK",
+    "WRITE_BC_DIR_INVAL",
+    "WRITE_BC_CC_SEND",
+    "WRITE_BC_XRAM_REQ",
+    "WRITE_WAIT"
+  };
+  const char *ixr_rsp_fsm_str[] = {
+    "IXR_RSP_IDLE",
+    "IXR_RSP_ACK",
+    "IXR_RSP_TRT_ERASE",
+    "IXR_RSP_TRT_READ"
+  };
+  const char *xram_rsp_fsm_str[] = {
+    "XRAM_RSP_IDLE",
+    "XRAM_RSP_TRT_COPY",
+    "XRAM_RSP_TRT_DIRTY",
+    "XRAM_RSP_DIR_LOCK",
+    "XRAM_RSP_DIR_UPDT",
+    "XRAM_RSP_DIR_RSP",
+    "XRAM_RSP_INVAL_LOCK",
+    "XRAM_RSP_INVAL_WAIT",
+    "XRAM_RSP_INVAL",
+    "XRAM_RSP_WRITE_DIRTY",
+    "XRAM_RSP_HEAP_REQ",
+    "XRAM_RSP_HEAP_ERASE",
+    "XRAM_RSP_HEAP_LAST",
+    "XRAM_RSP_ERROR_ERASE",
+    "XRAM_RSP_ERROR_RSP"
+  };
+  const char *ixr_cmd_fsm_str[] = {
+    "IXR_CMD_READ_IDLE",
+    "IXR_CMD_WRITE_IDLE",
+    "IXR_CMD_CAS_IDLE",
+    "IXR_CMD_XRAM_IDLE",
+    "IXR_CMD_READ_NLINE",
+    "IXR_CMD_WRITE_NLINE",
+    "IXR_CMD_CAS_NLINE",
+    "IXR_CMD_XRAM_DATA"
+  };
+  const char *cas_fsm_str[] = {
+    "CAS_IDLE",
+    "CAS_DIR_REQ",
+    "CAS_DIR_LOCK",
+    "CAS_DIR_HIT_READ",
+    "CAS_DIR_HIT_COMPARE",
+    "CAS_DIR_HIT_WRITE",
+    "CAS_UPT_LOCK",
+    "CAS_UPT_HEAP_LOCK",
+    "CAS_UPT_REQ",
+    "CAS_UPT_NEXT",
+    "CAS_BC_TRT_LOCK",
+    "CAS_BC_UPT_LOCK",
+    "CAS_BC_DIR_INVAL",
+    "CAS_BC_CC_SEND",
+    "CAS_BC_XRAM_REQ",
+    "CAS_RSP_FAIL",
+    "CAS_RSP_SUCCESS",
+    "CAS_MISS_TRT_LOCK",
+    "CAS_MISS_TRT_SET",
+    "CAS_MISS_XRAM_REQ",
+    "CAS_WAIT"
+  };
+  const char *cleanup_fsm_str[] = {
+    "CLEANUP_IDLE",
+    "CLEANUP_DIR_REQ",
+    "CLEANUP_DIR_LOCK",
+    "CLEANUP_DIR_WRITE",
+    "CLEANUP_HEAP_REQ",
+    "CLEANUP_HEAP_LOCK",
+    "CLEANUP_HEAP_SEARCH",
+    "CLEANUP_HEAP_CLEAN",
+    "CLEANUP_HEAP_FREE",
+    "CLEANUP_UPT_LOCK",
+    "CLEANUP_UPT_WRITE",
+    "CLEANUP_WRITE_RSP",
+    "CLEANUP_RSP"
+  };
+  const char *alloc_dir_fsm_str[] = {
+    "ALLOC_DIR_RESET",
+    "ALLOC_DIR_READ",
+    "ALLOC_DIR_WRITE",
+    "ALLOC_DIR_CAS",
+    "ALLOC_DIR_CLEANUP",
+    "ALLOC_DIR_XRAM_RSP"
+  };
+  const char *alloc_trt_fsm_str[] = {
+    "ALLOC_TRT_READ",
+    "ALLOC_TRT_WRITE",
+    "ALLOC_TRT_CAS",
+    "ALLOC_TRT_XRAM_RSP",
+    "ALLOC_TRT_IXR_RSP"
+  };
+  const char *alloc_upt_fsm_str[] = {
+    "ALLOC_UPT_WRITE",
+    "ALLOC_UPT_XRAM_RSP",
+    "ALLOC_UPT_INIT_RSP",
+    "ALLOC_UPT_CLEANUP",
+    "ALLOC_UPT_CAS"
+  };
+  const char *alloc_heap_fsm_str[] = {
+    "ALLOC_HEAP_RESET",
+    "ALLOC_HEAP_READ",
+    "ALLOC_HEAP_WRITE",
+    "ALLOC_HEAP_CAS",
+    "ALLOC_HEAP_CLEANUP",
+    "ALLOC_HEAP_XRAM_RSP"
+  };
+
+#define tmpl(x) template<typename vci_param> x VciMemCacheV4<vci_param>
+
+  using soclib::common::uint32_log2;
+
+  ////////////////////////////////
+  //  Constructor
+  ////////////////////////////////
+
+  tmpl(/**/)::VciMemCacheV4(
+      sc_module_name name,
+      const soclib::common::MappingTable &mtp,
+      const soclib::common::MappingTable &mtc,
+      const soclib::common::MappingTable &mtx,
+      const soclib::common::IntTab &vci_ixr_index,
+      const soclib::common::IntTab &vci_ini_index,
+      const soclib::common::IntTab &vci_tgt_index,
+      const soclib::common::IntTab &vci_tgt_index_cleanup,
+      size_t nways,                 // number of ways per set
+      size_t nsets,                 // number of cache sets
+      size_t nwords,                // number of words in cache line
+      size_t heap_size,             // number of heap entries
+      size_t transaction_tab_lines, // number of TRT entries
+      size_t update_tab_lines,      // number of UPT entries
+      size_t debug_start_cycle,
+      bool   debug_ok)
+
+    : soclib::caba::BaseModule(name),
+
+    m_debug_start_cycle( debug_start_cycle),
+    m_debug_ok ( debug_ok ),
+
+    p_clk("clk"),
+    p_resetn("resetn"),
+    p_vci_tgt("vci_tgt"),
+    p_vci_tgt_cleanup("vci_tgt_cleanup"),
+    p_vci_ini("vci_ini"),
+    p_vci_ixr("vci_ixr"),
+
+    m_seglist(mtp.getSegmentList(vci_tgt_index)),
+    m_cseglist(mtc.getSegmentList(vci_tgt_index_cleanup)),
+
+    m_initiators( 1 << vci_param::S ),
+    m_heap_size( heap_size ),
+    m_ways( nways ),
+    m_sets( nsets ),
+    m_words( nwords ),
+    m_srcid_ixr( mtx.indexForId(vci_ixr_index) ),
+    m_srcid_ini( mtc.indexForId(vci_ini_index) ),
+    m_transaction_tab_lines(transaction_tab_lines),
+    m_transaction_tab( transaction_tab_lines, nwords ),
+    m_update_tab_lines( update_tab_lines),
+    m_update_tab( update_tab_lines ),
+    m_cache_directory( nways, nsets, nwords, vci_param::N ),
+    m_cache_data( nways, nsets, nwords ),
+    m_heap( m_heap_size ),
+    m_llsc_table(),
+
+#define L2 soclib::common::uint32_log2
+    m_x( L2(m_words), 2),
+    m_y( L2(m_sets), L2(m_words) + 2),
+    m_z( vci_param::N - L2(m_sets) - L2(m_words) - 2, L2(m_sets) + L2(m_words) + 2),
+    m_nline( vci_param::N - L2(m_words) - 2, L2(m_words) + 2),
+#undef L2
+
+    //  FIFOs
+
+    m_cmd_read_addr_fifo("m_cmd_read_addr_fifo", 4),
+    m_cmd_read_length_fifo("m_cmd_read_length_fifo", 4),
+    m_cmd_read_srcid_fifo("m_cmd_read_srcid_fifo", 4),
+    m_cmd_read_trdid_fifo("m_cmd_read_trdid_fifo", 4),
+    m_cmd_read_pktid_fifo("m_cmd_read_pktid_fifo", 4),
+
+    m_cmd_write_addr_fifo("m_cmd_write_addr_fifo",8),
+    m_cmd_write_eop_fifo("m_cmd_write_eop_fifo",8),
+    m_cmd_write_srcid_fifo("m_cmd_write_srcid_fifo",8),
+    m_cmd_write_trdid_fifo("m_cmd_write_trdid_fifo",8),
+    m_cmd_write_pktid_fifo("m_cmd_write_pktid_fifo",8),
+    m_cmd_write_data_fifo("m_cmd_write_data_fifo",8),
+    m_cmd_write_be_fifo("m_cmd_write_be_fifo",8),
+
+    m_cmd_cas_addr_fifo("m_cmd_cas_addr_fifo",4),
+    m_cmd_cas_eop_fifo("m_cmd_cas_eop_fifo",4),
+    m_cmd_cas_srcid_fifo("m_cmd_cas_srcid_fifo",4),
+    m_cmd_cas_trdid_fifo("m_cmd_cas_trdid_fifo",4),
+    m_cmd_cas_pktid_fifo("m_cmd_cas_pktid_fifo",4),
+    m_cmd_cas_wdata_fifo("m_cmd_cas_wdata_fifo",4),
+
+    r_tgt_cmd_fsm("r_tgt_cmd_fsm"),
+
+    m_nseg(0),
+    m_ncseg(0),
+
+    r_read_fsm("r_read_fsm"),
+
+    r_write_fsm("r_write_fsm"),
+
+    m_write_to_init_cmd_inst_fifo("m_write_to_init_cmd_inst_fifo",8),
+    m_write_to_init_cmd_srcid_fifo("m_write_to_init_cmd_srcid_fifo",8),
+#if L1_MULTI_CACHE
+    m_write_to_init_cmd_cache_id_fifo("m_write_to_init_cmd_cache_id_fifo",8),
+#endif
+
+    r_init_rsp_fsm("r_init_rsp_fsm"),
+    r_cleanup_fsm("r_cleanup_fsm"),
+
+    r_cas_fsm("r_cas_fsm"),
+
+    m_cas_to_init_cmd_inst_fifo("m_cas_to_init_cmd_inst_fifo",8),
+    m_cas_to_init_cmd_srcid_fifo("m_cas_to_init_cmd_srcid_fifo",8),
+#if L1_MULTI_CACHE
+    m_cas_to_init_cmd_cache_id_fifo("m_cas_to_init_cmd_cache_id_fifo",8),
+#endif
+
+    r_ixr_rsp_fsm("r_ixr_rsp_fsm"),
+    r_xram_rsp_fsm("r_xram_rsp_fsm"),
+
+    m_xram_rsp_to_init_cmd_inst_fifo("m_xram_rsp_to_init_cmd_inst_fifo",8),
+    m_xram_rsp_to_init_cmd_srcid_fifo("m_xram_rsp_to_init_cmd_srcid_fifo",8),
+#if L1_MULTI_CACHE
+    m_xram_rsp_to_init_cmd_cache_id_fifo("m_xram_rsp_to_init_cmd_cache_id_fifo",8),
+#endif
+
+    r_ixr_cmd_fsm("r_ixr_cmd_fsm"),
+
+    r_tgt_rsp_fsm("r_tgt_rsp_fsm"),
+
+    r_init_cmd_fsm("r_init_cmd_fsm"),
+
+    r_alloc_dir_fsm("r_alloc_dir_fsm"),
+    r_alloc_dir_reset_cpt("r_alloc_dir_reset_cpt"),
+    r_alloc_trt_fsm("r_alloc_trt_fsm"),
+    r_alloc_upt_fsm("r_alloc_upt_fsm"),
+    r_alloc_heap_fsm("r_alloc_heap_fsm"),
+    r_alloc_heap_reset_cpt("r_alloc_heap_reset_cpt")
+
+#if MONITOR_MEMCACHE_FSM
+    ,
+    p_read_fsm       ("p_read_fsm"), 
+    p_write_fsm      ("p_write_fsm"), 
+    p_xram_rsp_fsm   ("p_xram_rsp_fsm"), 
+    p_cas_fsm        ("p_cas_fsm"), 
+    p_cleanup_fsm    ("p_cleanup_fsm"), 
+    p_alloc_heap_fsm ("p_alloc_heap_fsm"), 
+    p_alloc_dir_fsm  ("p_alloc_dir_fsm"), 
+    p_alloc_trt_fsm  ("p_alloc_trt_fsm"), 
+    p_alloc_upt_fsm  ("p_alloc_upt_fsm"), 
+    p_tgt_cmd_fsm    ("p_tgt_cmd_fsm"), 
+    p_tgt_rsp_fsm    ("p_tgt_rsp_fsm"), 
+    p_ixr_cmd_fsm    ("p_ixr_cmd_fsm"), 
+    p_ixr_rsp_fsm    ("p_ixr_rsp_fsm"), 
+    p_init_cmd_fsm   ("p_init_cmd_fsm"), 
+    p_init_rsp_fsm   ("p_init_rsp_fsm") 
+#endif
+    {
+      assert(IS_POW_OF_2(nsets));
+      assert(IS_POW_OF_2(nwords));
+      assert(IS_POW_OF_2(nways));
+      assert(nsets);
+      assert(nwords);
+      assert(nways);
+
+      // check Transaction table size
+      assert( (uint32_log2(transaction_tab_lines) <= vci_param::T) and
+             "Need more bits for VCI TRDID field");
+
+      // Set the broadcast address with Xmin,Xmax,Ymin,Ymax set to maximum
+      m_broadcast_address = 0x3 | (0x7C1F << (vci_param::N-20));
+
+      // Get the segments associated to the MemCache
+      std::list<soclib::common::Segment>::iterator seg;
+      size_t i;
+
+      for(seg = m_seglist.begin(); seg != m_seglist.end() ; seg++) {
+        m_nseg++;
+      }
+      for(seg = m_cseglist.begin(); seg != m_cseglist.end() ; seg++) {
+        m_ncseg++;
+      }
+
+      m_seg = new soclib::common::Segment*[m_nseg];
+
+      i = 0;
+      for ( seg = m_seglist.begin() ; seg != m_seglist.end() ; seg++ ) {
+        m_seg[i] = &(*seg);
+        i++;
+      }
+
+      m_cseg = new soclib::common::Segment*[m_ncseg];
+
+      i = 0;
+      for ( seg = m_cseglist.begin() ; seg != m_cseglist.end() ; seg++ ) {
+          m_cseg[i] = &(*seg);
+          i++;
+      }
+
+      // Allocation for IXR_RSP FSM
+      r_ixr_rsp_to_xram_rsp_rok   = new sc_signal<bool>[m_transaction_tab_lines];
+
+      // Allocation for XRAM_RSP FSM
+      r_xram_rsp_victim_data      = new sc_signal<data_t>[nwords];
+      r_xram_rsp_to_tgt_rsp_data  = new sc_signal<data_t>[nwords];
+      r_xram_rsp_to_ixr_cmd_data  = new sc_signal<data_t>[nwords];
+
+      // Allocation for READ FSM
+      r_read_data                 = new sc_signal<data_t>[nwords];
+      r_read_to_tgt_rsp_data      = new sc_signal<data_t>[nwords];
+
+      // Allocation for WRITE FSM
+      r_write_data                = new sc_signal<data_t>[nwords];
+      r_write_be                  = new sc_signal<be_t>[nwords];
+      r_write_to_init_cmd_data    = new sc_signal<data_t>[nwords];
+      r_write_to_init_cmd_be      = new sc_signal<be_t>[nwords];
+      r_write_to_ixr_cmd_data     = new sc_signal<data_t>[nwords];
+
+      // Allocation for CAS FSM
+      r_cas_to_ixr_cmd_data       = new sc_signal<data_t>[nwords];
+      r_cas_data                  = new sc_signal<data_t>[nwords];
+      r_cas_rdata                 = new sc_signal<data_t>[2];
+
+
+      // Simulation
+
+      SC_METHOD(transition);
+      dont_initialize();
+      sensitive << p_clk.pos();
+
+      SC_METHOD(genMoore);
+      dont_initialize();
+      sensitive << p_clk.neg();
+
+    } // end constructor
+
+///////////////////////////////////////////////////////////////////////
+tmpl(void)::start_monitor( vci_addr_t addr, vci_addr_t length )
+///////////////////////////////////////////////////////////////////////
+{
+    m_monitor_ok        = true;
+    m_monitor_base      = addr;
+    m_monitor_length    = length;
+}
+
+///////////////////////////////////////////////////////////////////////
+tmpl(void)::stop_monitor()
+///////////////////////////////////////////////////////////////////////
+{
+    m_monitor_ok        = false;
+}
+
+///////////////////////////////////////////////////////////////////////
+tmpl(void)::check_monitor( const char *buf, vci_addr_t addr, data_t data )
+///////////////////////////////////////////////////////////////////////
+{
+    if ( (addr >= m_monitor_base) and
+         (addr < m_monitor_base + m_monitor_length) )
+    {
+        std::cout << " MEMC Write Monitor : " << buf << " Address = " << std::hex << addr
+                  << " / Data = " << data << std::endl;
+    }
+}
+
+/////////////////////////////////////////////////////
+tmpl(void)::copies_monitor( vci_addr_t addr )
+/////////////////////////////////////////////////////
+{
+    DirectoryEntry entry = m_cache_directory.read_neutral(addr);
+    if ( (entry.count != m_debug_previous_count) or
+         (entry.valid != m_debug_previous_hit) )
+    {
+    std::cout << " MEMC " << name()
+              << " cache change at cycle " << std::dec << m_cpt_cycles
+              << " for address " << std::hex << addr
+              << " / HIT = " << entry.valid
+              << " / COUNT = " << std::dec << entry.count << std::endl;
+    }
+    m_debug_previous_count = entry.count;
+    m_debug_previous_hit = entry.valid;
+}
+
+//////////////////////////////////////////////////
+tmpl(void)::print_trace()
+//////////////////////////////////////////////////
+{
+    std::cout << "MEMC " << name() << std::endl;
+    std::cout << "  "  << tgt_cmd_fsm_str[r_tgt_cmd_fsm]
+              << " | " << tgt_rsp_fsm_str[r_tgt_rsp_fsm]
+              << " | " << read_fsm_str[r_read_fsm]
+              << " | " << write_fsm_str[r_write_fsm]
+              << " | " << cas_fsm_str[r_cas_fsm]
+              << " | " << cleanup_fsm_str[r_cleanup_fsm] << std::endl;
+    std::cout << "  "  << init_cmd_fsm_str[r_init_cmd_fsm]
+              << " | " << init_rsp_fsm_str[r_init_rsp_fsm]
+              << " | " << ixr_cmd_fsm_str[r_ixr_cmd_fsm]
+              << " | " << ixr_rsp_fsm_str[r_ixr_rsp_fsm]
+              << " | " << xram_rsp_fsm_str[r_xram_rsp_fsm] << std::endl;
+
+              //m_llsc_table.print_trace();
+
+}
+
+/////////////////////////////////////////
+tmpl(void)::print_stats()
+/////////////////////////////////////////
+{
+  std::cout << "----------------------------------" << std::dec << std::endl;
+  std::cout
+    << "MEM_CACHE " << m_srcid_ini << " / Time = " << m_cpt_cycles << std::endl
+    << "- READ RATE            = " << (double) m_cpt_read/m_cpt_cycles << std::endl
+    << "- READ TOTAL           = " << m_cpt_read << std::endl
+    << "- READ MISS RATE       = " << (double) m_cpt_read_miss/m_cpt_read << std::endl
+    << "- WRITE RATE           = " << (double) m_cpt_write/m_cpt_cycles << std::endl
+    << "- WRITE TOTAL          = " << m_cpt_write << std::endl
+    << "- WRITE MISS RATE      = " << (double) m_cpt_write_miss/m_cpt_write << std::endl
+    << "- WRITE BURST LENGTH   = " << (double) m_cpt_write_cells/m_cpt_write << std::endl
+    << "- WRITE BURST TOTAL    = " << m_cpt_write_cells << std::endl
+    << "- REQUESTS TRT FULL    = " << m_cpt_trt_full << std::endl
+    << "- READ TRT BLOKED HIT  = " << m_cpt_trt_rb << std::endl
+    << "- UPDATE RATE          = " << (double) m_cpt_update/m_cpt_cycles << std::endl
+    << "- UPDATE ARITY         = " << (double) m_cpt_update_mult/m_cpt_update << std::endl
+    << "- INVAL MULTICAST RATE = " << (double) (m_cpt_inval-m_cpt_inval_brdcast)/m_cpt_cycles << std::endl
+    << "- INVAL MULTICAST ARITY= " << (double) m_cpt_inval_mult/(m_cpt_inval-m_cpt_inval_brdcast) << std::endl
+    << "- INVAL BROADCAST RATE = " << (double) m_cpt_inval_brdcast/m_cpt_cycles << std::endl
+    << "- SAVE DIRTY RATE      = " << (double) m_cpt_write_dirty/m_cpt_cycles << std::endl
+    << "- CLEANUP RATE         = " << (double) m_cpt_cleanup/m_cpt_cycles << std::endl
+    << "- LL RATE              = " << (double) m_cpt_ll/m_cpt_cycles << std::endl
+    << "- SC RATE              = " << (double) m_cpt_sc/m_cpt_cycles << std::endl
+    << "- CAS RATE             = " << (double) m_cpt_cas/m_cpt_cycles << std::endl;
+}
+
+  /////////////////////////////////
+  tmpl(/**/)::~VciMemCacheV4()
+    /////////////////////////////////
+  {
+    delete [] r_ixr_rsp_to_xram_rsp_rok;
+
+    delete [] r_xram_rsp_victim_data;
+    delete [] r_xram_rsp_to_tgt_rsp_data;
+    delete [] r_xram_rsp_to_ixr_cmd_data;
+
+    delete [] r_read_data;
+    delete [] r_read_to_tgt_rsp_data;
+
+    delete [] r_write_data;
+    delete [] r_write_be;
+    delete [] r_write_to_init_cmd_data;
+  }
+
+//////////////////////////////////
+tmpl(void)::transition()
+//////////////////////////////////
+{
+  using soclib::common::uint32_log2;
+
+  // RESET
+  if ( ! p_resetn.read() ) {
+
+    // Initializing FSMs
+    r_tgt_cmd_fsm    = TGT_CMD_IDLE;
+    r_tgt_rsp_fsm    = TGT_RSP_READ_IDLE;
+    r_init_cmd_fsm   = INIT_CMD_INVAL_IDLE;
+    r_init_rsp_fsm   = INIT_RSP_IDLE;
+    r_read_fsm       = READ_IDLE;
+    r_write_fsm      = WRITE_IDLE;
+    r_cas_fsm        = CAS_IDLE;
+    r_cleanup_fsm    = CLEANUP_IDLE;
+    r_alloc_dir_fsm  = ALLOC_DIR_RESET;
+    r_alloc_heap_fsm = ALLOC_HEAP_RESET;
+    r_alloc_trt_fsm  = ALLOC_TRT_READ;
+    r_alloc_upt_fsm  = ALLOC_UPT_WRITE;
+    r_ixr_rsp_fsm    = IXR_RSP_IDLE;
+    r_xram_rsp_fsm   = XRAM_RSP_IDLE;
+    r_ixr_cmd_fsm    = IXR_CMD_READ_IDLE;
+
+    m_debug_global         = false;
+    m_debug_tgt_cmd_fsm    = false;
+    m_debug_tgt_rsp_fsm    = false;
+    m_debug_init_cmd_fsm   = false;
+    m_debug_init_rsp_fsm   = false;
+    m_debug_read_fsm       = false;
+    m_debug_write_fsm      = false;
+    m_debug_cas_fsm        = false;
+    m_debug_cleanup_fsm    = false;
+    m_debug_ixr_cmd_fsm    = false;
+    m_debug_ixr_rsp_fsm    = false;
+    m_debug_xram_rsp_fsm   = false;
+    m_debug_previous_hit   = false;
+    m_debug_previous_count = 0;
+
+    //  Initializing Tables
+    m_transaction_tab.init();
+    m_update_tab.init();
+
+    // initializing FIFOs and communication Buffers
+
+    m_cmd_read_addr_fifo.init();
+    m_cmd_read_length_fifo.init();
+    m_cmd_read_srcid_fifo.init();
+    m_cmd_read_trdid_fifo.init();
+    m_cmd_read_pktid_fifo.init();
+
+    m_cmd_write_addr_fifo.init();
+    m_cmd_write_eop_fifo.init();
+    m_cmd_write_srcid_fifo.init();
+    m_cmd_write_trdid_fifo.init();
+    m_cmd_write_pktid_fifo.init();
+    m_cmd_write_data_fifo.init();
+
+    m_cmd_cas_addr_fifo.init()  ;
+    m_cmd_cas_srcid_fifo.init() ;
+    m_cmd_cas_trdid_fifo.init() ;
+    m_cmd_cas_pktid_fifo.init() ;
+    m_cmd_cas_wdata_fifo.init() ;
+    m_cmd_cas_eop_fifo.init()   ;
+
+    r_read_to_tgt_rsp_req = false;
+    r_read_to_ixr_cmd_req = false;
+
+    r_write_to_tgt_rsp_req          = false;
+    r_write_to_ixr_cmd_req          = false;
+    r_write_to_init_cmd_multi_req   = false;
+    r_write_to_init_cmd_brdcast_req = false;
+    r_write_to_init_rsp_req         = false;
+
+    m_write_to_init_cmd_inst_fifo.init();
+    m_write_to_init_cmd_srcid_fifo.init();
+#if L1_MULTI_CACHE
+    m_write_to_init_cmd_cache_id_fifo.init();
+#endif
+
+    r_cleanup_to_tgt_rsp_req      = false;
+
+    r_init_rsp_to_tgt_rsp_req     = false;
+
+    r_cas_to_tgt_rsp_req          = false;
+    r_cas_cpt                     = 0    ;
+    r_cas_lfsr                    = -1   ;
+    r_cas_to_ixr_cmd_req          = false;
+    r_cas_to_init_cmd_multi_req   = false;
+    r_cas_to_init_cmd_brdcast_req = false;
+
+    m_cas_to_init_cmd_inst_fifo.init();
+    m_cas_to_init_cmd_srcid_fifo.init();
+#if L1_MULTI_CACHE
+    m_cas_to_init_cmd_cache_id_fifo.init();
+#endif
+
+    for(size_t i=0; i<m_transaction_tab_lines ; i++){
+      r_ixr_rsp_to_xram_rsp_rok[i] = false;
+    }
+
+    r_xram_rsp_to_tgt_rsp_req          = false;
+    r_xram_rsp_to_init_cmd_multi_req   = false;
+    r_xram_rsp_to_init_cmd_brdcast_req = false;
+    r_xram_rsp_to_ixr_cmd_req          = false;
+    r_xram_rsp_trt_index               = 0;
+
+    m_xram_rsp_to_init_cmd_inst_fifo.init();
+    m_xram_rsp_to_init_cmd_srcid_fifo.init();
+#if L1_MULTI_CACHE
+    m_xram_rsp_to_init_cmd_cache_id_fifo.init();
+#endif
+
+    r_ixr_cmd_cpt          = 0;
+    r_alloc_dir_reset_cpt  = 0;
+    r_alloc_heap_reset_cpt = 0;
+
+    r_copies_limit         = 3;
+
+    r_tgt_rsp_key_sent     = false;
+
+    // Activity counters
+    m_cpt_cycles        = 0;
+    m_cpt_read          = 0;
+    m_cpt_read_miss     = 0;
+    m_cpt_write         = 0;
+    m_cpt_write_miss    = 0;
+    m_cpt_write_cells   = 0;
+    m_cpt_write_dirty   = 0;
+    m_cpt_update        = 0;
+    m_cpt_update_mult   = 0;
+    m_cpt_inval_brdcast = 0;
+    m_cpt_inval         = 0;
+    m_cpt_inval_mult    = 0;
+    m_cpt_cleanup       = 0;
+    m_cpt_ll            = 0;
+    m_cpt_sc            = 0;
+    m_cpt_cas           = 0;
+    m_cpt_trt_full      = 0;
+    m_cpt_trt_rb        = 0;
+
+    return;
+  }
+
+  bool    cmd_read_fifo_put = false;
+  bool    cmd_read_fifo_get = false;
+
+  bool    cmd_write_fifo_put = false;
+  bool    cmd_write_fifo_get = false;
+
+  bool    cmd_cas_fifo_put = false;
+  bool    cmd_cas_fifo_get = false;
+
+  bool    write_to_init_cmd_fifo_put   = false;
+  bool    write_to_init_cmd_fifo_get   = false;
+  bool    write_to_init_cmd_fifo_inst  = false;
+  size_t  write_to_init_cmd_fifo_srcid = 0;
+
+#if L1_MULTI_CACHE
+  size_t  write_to_init_cmd_fifo_cache_id = 0;
+#endif
+
+  bool    xram_rsp_to_init_cmd_fifo_put   = false;
+  bool    xram_rsp_to_init_cmd_fifo_get   = false;
+  bool    xram_rsp_to_init_cmd_fifo_inst  = false;
+  size_t  xram_rsp_to_init_cmd_fifo_srcid = 0;
+
+#if L1_MULTI_CACHE
+  size_t  xram_rsp_to_init_cmd_fifo_cache_id = 0;
+#endif
+
+  bool    cas_to_init_cmd_fifo_put   = false;
+  bool    cas_to_init_cmd_fifo_get   = false;
+  bool    cas_to_init_cmd_fifo_inst  = false;
+  size_t  cas_to_init_cmd_fifo_srcid = 0;
+
+#if L1_MULTI_CACHE
+  size_t  cas_to_init_cmd_fifo_cache_id = 0;
+#endif
+
+  m_debug_global       = (m_cpt_cycles > m_debug_start_cycle) and m_debug_ok;
+  m_debug_tgt_cmd_fsm  = (m_cpt_cycles > m_debug_start_cycle) and m_debug_ok;
+  m_debug_tgt_rsp_fsm  = (m_cpt_cycles > m_debug_start_cycle) and m_debug_ok;
+  m_debug_init_cmd_fsm = (m_cpt_cycles > m_debug_start_cycle) and m_debug_ok;
+  m_debug_init_rsp_fsm = (m_cpt_cycles > m_debug_start_cycle) and m_debug_ok;
+  m_debug_read_fsm     = (m_cpt_cycles > m_debug_start_cycle) and m_debug_ok;
+  m_debug_write_fsm    = (m_cpt_cycles > m_debug_start_cycle) and m_debug_ok;
+  m_debug_cas_fsm      = (m_cpt_cycles > m_debug_start_cycle) and m_debug_ok;
+  m_debug_cleanup_fsm  = (m_cpt_cycles > m_debug_start_cycle) and m_debug_ok;
+  m_debug_ixr_cmd_fsm  = (m_cpt_cycles > m_debug_start_cycle) and m_debug_ok;
+  m_debug_ixr_rsp_fsm  = (m_cpt_cycles > m_debug_start_cycle) and m_debug_ok;
+  m_debug_xram_rsp_fsm = (m_cpt_cycles > m_debug_start_cycle) and m_debug_ok;
+
+#if DEBUG_MEMC_GLOBAL
+  if( m_debug_global )
+  {
+    std::cout
+      << "---------------------------------------------" << std::dec << std::endl
+      << "MEM_CACHE " << m_srcid_ini << " ; Time = " << m_cpt_cycles << std::endl
+      << " - TGT_CMD FSM    = " << tgt_cmd_fsm_str[r_tgt_cmd_fsm] << std::endl
+      << " - TGT_RSP FSM    = " << tgt_rsp_fsm_str[r_tgt_rsp_fsm] << std::endl
+      << " - INIT_CMD FSM   = " << init_cmd_fsm_str[r_init_cmd_fsm] << std::endl
+      << " - INIT_RSP FSM   = " << init_rsp_fsm_str[r_init_rsp_fsm] << std::endl
+      << " - READ FSM       = " << read_fsm_str[r_read_fsm] << std::endl
+      << " - WRITE FSM      = " << write_fsm_str[r_write_fsm] << std::endl
+      << " - CAS FSM        = " << cas_fsm_str[r_cas_fsm] << std::endl
+      << " - CLEANUP FSM    = " << cleanup_fsm_str[r_cleanup_fsm] << std::endl
+      << " - IXR_CMD FSM    = " << ixr_cmd_fsm_str[r_ixr_cmd_fsm] << std::endl
+      << " - IXR_RSP FSM    = " << ixr_rsp_fsm_str[r_ixr_rsp_fsm] << std::endl
+      << " - XRAM_RSP FSM   = " << xram_rsp_fsm_str[r_xram_rsp_fsm] << std::endl
+      << " - ALLOC_DIR FSM  = " << alloc_dir_fsm_str[r_alloc_dir_fsm] << std::endl
+      << " - ALLOC_TRT FSM  = " << alloc_trt_fsm_str[r_alloc_trt_fsm] << std::endl
+      << " - ALLOC_UPT FSM  = " << alloc_upt_fsm_str[r_alloc_upt_fsm] << std::endl
+      << " - ALLOC_HEAP FSM = " << alloc_heap_fsm_str[r_alloc_heap_fsm] << std::endl;
+  }
+#endif
+
+  ////////////////////////////////////////////////////////////////////////////////////
+  //    TGT_CMD FSM
+  ////////////////////////////////////////////////////////////////////////////////////
+  // The TGT_CMD_FSM controls the incoming VCI command pakets from the processors
+  //
+  // There are 5 types of accepted commands :
+  // - READ   : A READ request has a length of 1 VCI cell. It can be a single word
+  //            or an entire cache line, depending on the PLEN value.
+  // - WRITE  : A WRITE request has a maximum length of 16 cells, and can only
+  //            concern words in a same line.
+  // - CAS    : A CAS request has a length of 2 cells or 4 cells.
+  // - LL     : An LL request has a length of 1 cell.
+  // - SC     : An SC request has a length of 2 cells. First cell contains the
+  //            acces key, second cell the data to write in case of success.
+  ////////////////////////////////////////////////////////////////////////////////////
+
+  switch ( r_tgt_cmd_fsm.read() )
+  {
+    //////////////////
+    case TGT_CMD_IDLE:
+      if ( p_vci_tgt.cmdval )
+      {
+
+#if DEBUG_MEMC_TGT_CMD
+        if( m_debug_tgt_cmd_fsm )
+        {
+          std::cout
+            << "  <MEMC " << name() << ".TGT_CMD_IDLE> Receive command from srcid "
+            << std::dec << p_vci_tgt.srcid.read()
+            << " / for address " << std::hex << p_vci_tgt.address.read() << std::endl;
+        }
+#endif
+        // checking segmentation violation
+        vci_addr_t  address = p_vci_tgt.address.read();
+        uint32_t    plen    = p_vci_tgt.plen.read();
+        bool found = false;
+        for ( size_t seg_id = 0 ; seg_id < m_nseg ; seg_id++ )
+        {
+          if ( m_seg[seg_id]->contains(address) &&
+              m_seg[seg_id]->contains(address + plen - vci_param::B) )
+          {
+            found = true;
+          }
+        }
+        if ( not found )
+        {
+          std::cout << "VCI_MEM_CACHE ERROR " << name() << std::endl;
+          std::cout
+            << "Out of segment VCI address in TGT_CMD_IDLE state (address = "
+            << std::hex << address << ", srcid = " << p_vci_tgt.srcid.read()
+            << std::dec << ", cycle = " << m_cpt_cycles << ")" << std::endl;
+          exit(0);
+        }
+
+        if ( p_vci_tgt.cmd.read() == vci_param::CMD_READ )
+        {
+          // check that the pktid is either :
+          // TYPE_READ_DATA_UNC
+          // TYPE_READ_DATA_MISS
+          // TYPE_READ_INS_UNC
+          // TYPE_READ_INS_MISS
+          // ==> bit2 must be zero with the TSAR encoding
+          // ==> mask = 0b0100 = 0x4
+          assert(((p_vci_tgt.pktid.read() & 0x4) == 0x0) &&
+            "The type specified in the pktid field is incompatible with the READ CMD");
+          r_tgt_cmd_fsm = TGT_CMD_READ;
+        }
+        else if ( p_vci_tgt.cmd.read() == vci_param::CMD_WRITE )
+        {
+          // check that the pktid is TYPE_WRITE
+          // ==> TYPE_WRITE = X100 with the TSAR encoding
+          // ==> mask = 0b0111 = 0x7
+          assert(((p_vci_tgt.pktid.read() & 0x7) == 0x4) &&
+            "The type specified in the pktid field is incompatible with the WRITE CMD");
+          r_tgt_cmd_fsm = TGT_CMD_WRITE;
+        }
+        else if ( p_vci_tgt.cmd.read() == vci_param::CMD_LOCKED_READ )
+        {
+          // check that the pktid is TYPE_LL
+          // ==> TYPE_LL = X110 with the TSAR encoding
+          // ==> mask = 0b0111 = 0x7
+          assert(((p_vci_tgt.pktid.read() & 0x7) == 0x6) &&
+            "The type specified in the pktid field is incompatible with the LL CMD");
+          r_tgt_cmd_fsm = TGT_CMD_READ;
+        }
+        else if ( p_vci_tgt.cmd.read() == vci_param::CMD_NOP )
+        {
+          // check that the pktid is either :
+          // TYPE_CAS
+          // TYPE_SC
+          // ==> TYPE_CAS = X101 with the TSAR encoding
+          // ==> TYPE_SC  = X111 with the TSAR encoding
+          // ==> mask = 0b0101 = 0x5
+          assert(((p_vci_tgt.pktid.read() & 0x5) == 0x5 ) &&
+            "The type specified in the pktid field is incompatible with the NOP CMD");
+
+          if((p_vci_tgt.pktid.read() & 0x7) == TYPE_CAS)
+            r_tgt_cmd_fsm = TGT_CMD_CAS;
+          else // TYPE_SC
+            r_tgt_cmd_fsm = TGT_CMD_WRITE;
+        }
+        else
+        {
+          std::cout << "VCI_MEM_CACHE ERROR " << name()
+            << " TGT_CMD_IDLE state" << std::endl;
+          std::cout << " illegal VCI command type" << std::endl;
+          exit(0);
+        }
+      }
+      break;
+
+    //////////////////
+    case TGT_CMD_READ:
+      // This test checks that the read does not cross a cache line limit.
+      // It must not be taken into account when dealing with an LL CMD.
+      if (((m_x[(vci_addr_t)p_vci_tgt.address.read()]+(p_vci_tgt.plen.read()>>2)) > 16) && ( p_vci_tgt.cmd.read() != vci_param::CMD_LOCKED_READ ))
+      {
+        std::cout
+          << "VCI_MEM_CACHE ERROR " << name() << " TGT_CMD_READ state"
+          << std::endl;
+        std::cout
+          << " illegal address/plen combination for VCI read command" << std::endl;
+        exit(0);
+      }
+      if ( !p_vci_tgt.eop.read() )
+      {
+        std::cout
+          << "VCI_MEM_CACHE ERROR " << name() << " TGT_CMD_READ state"
+          << std::endl;
+        std::cout
+          << " read or ll command packets must contain one single flit"
+          << std::endl;
+        exit(0);
+      }
+
+      if ( p_vci_tgt.cmdval && m_cmd_read_addr_fifo.wok() )
+      {
+
+#if DEBUG_MEMC_TGT_CMD
+        if( m_debug_tgt_cmd_fsm )
+        {
+          std::cout << "  <MEMC " << name() << ".TGT_CMD_READ> Push into read_fifo:"
+            << " address = " << std::hex << p_vci_tgt.address.read()
+            << " srcid = " << std::dec << p_vci_tgt.srcid.read()
+            << " trdid = " << p_vci_tgt.trdid.read()
+            << " pktid = " << p_vci_tgt.pktid.read()
+            << " plen = " << std::dec << p_vci_tgt.plen.read() << std::endl;
+        }
+#endif
+        cmd_read_fifo_put = true;
+        if ( p_vci_tgt.cmd.read() == vci_param::CMD_LOCKED_READ )
+          m_cpt_ll++;
+        else
+          m_cpt_read++;
+        r_tgt_cmd_fsm = TGT_CMD_IDLE;
+      }
+      break;
+
+    ///////////////////
+    case TGT_CMD_WRITE:
+      if ( p_vci_tgt.cmdval && m_cmd_write_addr_fifo.wok() )
+      {
+
+#if DEBUG_MEMC_TGT_CMD
+        if( m_debug_tgt_cmd_fsm )
+        {
+          std::cout << "  <MEMC " << name() << ".TGT_CMD_WRITE> Push into write_fifo:"
+            << " address = " << std::hex << p_vci_tgt.address.read()
+            << " srcid = " << std::dec << p_vci_tgt.srcid.read()
+            << " trdid = " << p_vci_tgt.trdid.read()
+            << " pktid = " << p_vci_tgt.pktid.read()
+            << " wdata = " << std::hex << p_vci_tgt.wdata.read()
+            << " be = " << p_vci_tgt.be.read()
+            << " plen = " << std::dec << p_vci_tgt.plen.read() << std::endl;
+        }
+#endif
+        cmd_write_fifo_put = true;
+        if(  p_vci_tgt.eop )  r_tgt_cmd_fsm = TGT_CMD_IDLE;
+      }
+      break;
+
+    ////////////////////
+    case TGT_CMD_CAS:
+      if ( (p_vci_tgt.plen.read() != 8) && (p_vci_tgt.plen.read() != 16) )
+      {
+        std::cout
+          << "VCI_MEM_CACHE ERROR " << name() << " TGT_CMD_CAS state"
+          << std::endl
+          << "illegal format for CAS command " << std::endl;
+
+        exit(0);
+      }
+
+      if ( p_vci_tgt.cmdval && m_cmd_cas_addr_fifo.wok() )
+      {
+
+#if DEBUG_MEMC_TGT_CMD
+        if( m_debug_tgt_cmd_fsm )
+        {
+          std::cout << "  <MEMC " << name() << ".TGT_CMD_CAS> Pushing command into cmd_cas_fifo:"
+            << " address = " << std::hex << p_vci_tgt.address.read()
+            << " srcid = " << std::dec << p_vci_tgt.srcid.read()
+            << " trdid = " << p_vci_tgt.trdid.read()
+            << " pktid = " << p_vci_tgt.pktid.read()
+            << " wdata = " << std::hex << p_vci_tgt.wdata.read()
+            << " be = " << p_vci_tgt.be.read()
+            << " plen = " << std::dec << p_vci_tgt.plen.read() << std::endl;
+        }
+#endif
+        cmd_cas_fifo_put = true;
+        if( p_vci_tgt.eop ) r_tgt_cmd_fsm = TGT_CMD_IDLE;
+      }
+      break;
+  } // end switch tgt_cmd_fsm
+
+  /////////////////////////////////////////////////////////////////////////
+  //    INIT_RSP FSM
+  /////////////////////////////////////////////////////////////////////////
+  // This FSM controls the response to the update or inval coherence
+  // requests sent by the memory cache to the L1 caches and update the UPT.
+  //
+  // It can be update or inval requests initiated by the WRITE FSM,
+  // or inval requests initiated by the XRAM_RSP FSM.
+  // It can also be a direct request from the WRITE FSM.
+  //
+  // The FSM decrements the proper entry in UPT.
+  // It sends a request to the TGT_RSP FSM to complete the pending
+  // write transaction (acknowledge response to the writer processor),
+  // and clear the UPT entry when all responses have been received.
+  //
+  // All those response packets are one word, compact
+  // packets complying with the VCI advanced format.
+  // The index in the Table is defined in the RTRDID field, and
+  // the transaction type is defined in the UPT entry.
+  /////////////////////////////////////////////////////////////////////
+
+  switch ( r_init_rsp_fsm.read() )
+  {
+    ///////////////////
+    case INIT_RSP_IDLE:   // wait a response for a coherence transaction
+      if ( p_vci_ini.rspval )
+      {
+
+#if DEBUG_MEMC_INIT_RSP
+        if( m_debug_init_rsp_fsm )
+        {
+          std::cout <<  "  <MEMC " << name() << ".INIT_RSP_IDLE> Response for UPT entry "
+            << p_vci_ini.rtrdid.read() << std::endl;
+        }
+#endif
+        if ( p_vci_ini.rtrdid.read() >= m_update_tab.size() )
+        {
+          std::cout
+            << "VCI_MEM_CACHE ERROR " << name()
+            << " INIT_RSP_IDLE state" << std::endl
+            << "index too large for UPT: "
+            << " / rtrdid = " << std::dec << p_vci_ini.rtrdid.read()
+            << " / UPT size = " << std::dec << m_update_tab.size()
+            << std::endl;
+
+          exit(0);
+        }
+        if ( !p_vci_ini.reop.read() )
+        {
+          std::cout
+            << "VCI_MEM_CACHE ERROR " << name()
+            << " INIT_RSP_IDLE state" << std::endl
+            << "all coherence response packets must be one flit"
+            << std::endl;
+
+          exit(0);
+        }
+
+        r_init_rsp_upt_index = p_vci_ini.rtrdid.read();
+        r_init_rsp_fsm = INIT_RSP_UPT_LOCK;
+      }
+      else if( r_write_to_init_rsp_req.read() )
+      {
+        r_init_rsp_upt_index = r_write_to_init_rsp_upt_index.read();
+        r_write_to_init_rsp_req = false;
+        r_init_rsp_fsm = INIT_RSP_UPT_LOCK;
+      }
+      break;
+
+    ///////////////////////
+    case INIT_RSP_UPT_LOCK: // decrement the number of expected responses
+      if ( r_alloc_upt_fsm.read() == ALLOC_UPT_INIT_RSP )
+      {
+        size_t count = 0;
+        bool valid   = m_update_tab.decrement(r_init_rsp_upt_index.read(), count);
+
+#if DEBUG_MEMC_INIT_RSP
+        if( m_debug_init_rsp_fsm )
+        {
+          std::cout << "  <MEMC " << name() << ".INIT_RSP_UPT_LOCK> Decrement the responses counter for UPT:"
+            << " entry = " << r_init_rsp_upt_index.read()
+            << " / rsp_count = " << std::dec << count << std::endl;
+        }
+#endif
+        if ( not valid )
+        {
+          std::cout << "VCI_MEM_CACHE ERROR " << name()
+            << " INIT_RSP_UPT_LOCK state" << std::endl
+            << "unsuccessful access to decrement the UPT" << std::endl;
+
+          exit(0);
+        }
+
+        if ( count == 0 ) r_init_rsp_fsm = INIT_RSP_UPT_CLEAR;
+        else              r_init_rsp_fsm = INIT_RSP_IDLE;
+      }
+      break;
+
+      ////////////////////////
+    case INIT_RSP_UPT_CLEAR:  // clear the UPT entry
+      if ( r_alloc_upt_fsm.read() == ALLOC_UPT_INIT_RSP )
+      {
+        r_init_rsp_srcid = m_update_tab.srcid(r_init_rsp_upt_index.read());
+        r_init_rsp_trdid = m_update_tab.trdid(r_init_rsp_upt_index.read());
+        r_init_rsp_pktid = m_update_tab.pktid(r_init_rsp_upt_index.read());
+        r_init_rsp_nline = m_update_tab.nline(r_init_rsp_upt_index.read());
+        bool need_rsp    = m_update_tab.need_rsp(r_init_rsp_upt_index.read());
+
+        if ( need_rsp ) r_init_rsp_fsm = INIT_RSP_END;
+        else            r_init_rsp_fsm = INIT_RSP_IDLE;
+
+        m_update_tab.clear(r_init_rsp_upt_index.read());
+
+#if DEBUG_MEMC_INIT_RSP
+        if ( m_debug_init_rsp_fsm )
+        {
+          std::cout <<  "  <MEMC " << name() << ".INIT_RSP_UPT_CLEAR> Clear UPT entry "
+            << r_init_rsp_upt_index.read() <<  std::endl;
+        }
+#endif
+      }
+      break;
+
+    //////////////////
+    case INIT_RSP_END:  // Post a request to TGT_RSP FSM
+      if ( !r_init_rsp_to_tgt_rsp_req )
+      {
+        r_init_rsp_to_tgt_rsp_req   = true;
+        r_init_rsp_to_tgt_rsp_srcid = r_init_rsp_srcid.read();
+        r_init_rsp_to_tgt_rsp_trdid = r_init_rsp_trdid.read();
+        r_init_rsp_to_tgt_rsp_pktid = r_init_rsp_pktid.read();
+        r_init_rsp_fsm = INIT_RSP_IDLE;
+
+#if DEBUG_MEMC_INIT_RSP
+        if ( m_debug_init_rsp_fsm )
+        {
+          std::cout
+            << "  <MEMC " << name()
+            << ".INIT_RSP_END> Request TGT_RSP FSM to send a response to srcid "
+            << r_init_rsp_srcid.read()
+            << std::endl;
+        }
+#endif
+      }
+      break;
+  } // end switch r_init_rsp_fsm
+
+  ////////////////////////////////////////////////////////////////////////////////////
+  //    READ FSM
+  ////////////////////////////////////////////////////////////////////////////////////
+  // The READ FSM controls the VCI read  and ll requests.
+  // It takes the lock protecting the cache directory to check the cache line status:
+  // - In case of HIT
+  //   The fsm copies the data (one line, or one single word)
+  //   in the r_read_to_tgt_rsp buffer. It waits if this buffer is not empty.
+  //   The requesting initiator is registered in the cache directory.
+  //   If the number of copy is larger than 1, the new copy is registered
+  //   in the HEAP.
+  //   If the number of copy is larger than the threshold, the HEAP is cleared,
+  //   and the corresponding line switches to the counter mode.
+  // - In case of MISS
+  //   The READ fsm takes the lock protecting the transaction tab.
+  //   If a read transaction to the XRAM for this line already exists,
+  //   or if the transaction tab is full, the fsm is stalled.
+  //   If a TRT entry is free, the READ request is registered in TRT,
+  //   it is consumed in the request FIFO, and transmited to the IXR_CMD FSM.
+  //   The READ FSM returns in the IDLE state as the read transaction will be
+  //   completed when the missing line will be received.
+  ////////////////////////////////////////////////////////////////////////////////////
+
+  switch ( r_read_fsm.read() )
+  {
+    ///////////////
+    case READ_IDLE:
+    // waiting a read request
+    {
+      if (m_cmd_read_addr_fifo.rok())
+      {
+
+#if DEBUG_MEMC_READ
+        if( m_debug_read_fsm )
+        {
+          std::cout << "  <MEMC " << name() << ".READ_IDLE> Read request:"
+            << " srcid = " << std::dec << m_cmd_read_srcid_fifo.read()
+            << " / address = " << std::hex << m_cmd_read_addr_fifo.read()
+            << " / pktid = " << std::hex << m_cmd_read_pktid_fifo.read()
+            << " / nwords = " << std::dec << m_cmd_read_length_fifo.read() << std::endl;
+        }
+#endif
+        r_read_fsm = READ_DIR_REQ;
+      }
+      break;
+    }
+
+    ///////////////////
+    case READ_DIR_REQ:
+    // Get the lock to the directory
+    {
+      if ( r_alloc_dir_fsm.read() == ALLOC_DIR_READ )
+      {
+        r_read_fsm = READ_DIR_LOCK;
+      }
+
+#if DEBUG_MEMC_READ
+      if( m_debug_read_fsm )
+      {
+        std::cout 
+          << "  <MEMC " << name() << ".READ_DIR_REQ> Requesting DIR lock "
+          << std::endl;
+      }
+#endif
+      break;
+    }
+
+    ///////////////////
+    case READ_DIR_LOCK:
+    // check directory for hit / miss
+    {
+      if ( r_alloc_dir_fsm.read() == ALLOC_DIR_READ )
+      {
+        size_t way = 0;
+        DirectoryEntry entry =
+          m_cache_directory.read(m_cmd_read_addr_fifo.read(), way);
+        if((m_cmd_read_pktid_fifo.read() & 0x7) == TYPE_LL) // access the global table ONLY when we have an LL cmd
+        {
+          r_read_ll_key   = m_llsc_table.ll(m_cmd_read_addr_fifo.read());
+        }
+        r_read_is_cnt     = entry.is_cnt;
+        r_read_dirty      = entry.dirty;
+        r_read_lock       = entry.lock;
+        r_read_tag        = entry.tag;
+        r_read_way        = way;
+        r_read_count      = entry.count;
+        r_read_copy       = entry.owner.srcid;
+
+#if L1_MULTI_CACHE
+        r_read_copy_cache = entry.owner.cache_id;
+#endif
+        r_read_copy_inst  = entry.owner.inst;
+        r_read_ptr        = entry.ptr; // pointer to the heap
+
+        // check if this is a cached read, this means pktid is either
+        // TYPE_READ_DATA_MISS 0bX001 with TSAR encoding
+        // TYPE_READ_INS_MISS  0bX011 with TSAR encoding
+        bool cached_read = (m_cmd_read_pktid_fifo.read() & 0x1);
+        if(  entry.valid ) // hit
+        {
+          // test if we need to register a new copy in the heap
+          if ( entry.is_cnt || (entry.count == 0) || !cached_read )
+          {
+            r_read_fsm = READ_DIR_HIT;
+          }
+          else
+          {
+            r_read_fsm = READ_HEAP_REQ;
+          }
+        }
+        else      // miss
+        {
+          r_read_fsm = READ_TRT_LOCK;
+        }
+
+#if DEBUG_MEMC_READ
+        if( m_debug_read_fsm )
+        {
+          std::cout
+            << "  <MEMC " << name() << ".READ_DIR_LOCK> Accessing directory: "
+            << " address = " << std::hex << m_cmd_read_addr_fifo.read()
+            << " / hit = " << std::dec << entry.valid
+            << " / count = " <<std::dec << entry.count
+            << " / is_cnt = " << entry.is_cnt << std::endl;
+            if((m_cmd_read_pktid_fifo.read() & 0x7) == TYPE_LL)
+            {
+              std::cout
+                << "  <MEMC " << name() << ".READ_DIR_LOCK> global_llsc_table LL access" << std::endl;
+            }
+        }
+#endif
+      }
+      else
+      {
+        std::cout
+          << "VCI_MEM_CACHE ERROR " << name()
+          << " READ_DIR_LOCK state" << std::endl
+          << "Bad DIR allocation"   << std::endl;
+
+        exit(0);
+      }
+      break;
+    }
+
+    //////////////////
+    case READ_DIR_HIT:
+    {
+      //  read data in cache & update the directory
+      //  we enter this state in 3 cases:
+      //  - the read request is uncachable
+      //  - the cache line is in counter mode
+      //  - the cache line is valid but not replcated
+
+      if( r_alloc_dir_fsm.read() == ALLOC_DIR_READ )
+      {
+        // signals generation
+        // check if this is an instruction read, this means pktid is either
+        // TYPE_READ_INS_UNC   0bX010 with TSAR encoding
+        // TYPE_READ_INS_MISS  0bX011 with TSAR encoding
+        bool inst_read    = (m_cmd_read_pktid_fifo.read() & 0x2);
+        // check if this is a cached read, this means pktid is either
+        // TYPE_READ_DATA_MISS 0bX001 with TSAR encoding
+        // TYPE_READ_INS_MISS  0bX011 with TSAR encoding
+        bool cached_read  = (m_cmd_read_pktid_fifo.read() & 0x1);
+        bool is_cnt       = r_read_is_cnt.read();
+
+        // read data in the cache
+        size_t set        = m_y[(vci_addr_t)(m_cmd_read_addr_fifo.read())];
+        size_t way        = r_read_way.read();
+
+        m_cache_data.read_line(way, set, r_read_data);
+
+        // update the cache directory
+        DirectoryEntry entry;
+        entry.valid   = true;
+        entry.is_cnt  = is_cnt;
+        entry.dirty   = r_read_dirty.read();
+        entry.tag   = r_read_tag.read();
+        entry.lock    = r_read_lock.read();
+        entry.ptr     = r_read_ptr.read();
+        if (cached_read)  // Cached read => we must update the copies
+        {
+          if (!is_cnt) // Not counter mode
+          {
+            entry.owner.srcid    = m_cmd_read_srcid_fifo.read();
+#if L1_MULTI_CACHE
+            entry.owner.cache_id = m_cmd_read_pktid_fifo.read();
+#endif
+            entry.owner.inst     = inst_read;
+            entry.count          = r_read_count.read() + 1;
+          }
+          else  // Counter mode
+          {
+            entry.owner.srcid    = 0;
+#if L1_MULTI_CACHE
+            entry.owner.cache_id = 0;
+#endif
+            entry.owner.inst     = false;
+            entry.count          = r_read_count.read() + 1;
+          }
+        }
+        else  // Uncached read
+        {
+          entry.owner.srcid     = r_read_copy.read();
+#if L1_MULTI_CACHE
+          entry.owner.cache_id  = r_read_copy_cache.read();
+#endif
+          entry.owner.inst      = r_read_copy_inst.read();
+          entry.count           = r_read_count.read();
+        }
+
+#if DEBUG_MEMC_READ
+        if( m_debug_read_fsm )
+        {
+          std::cout
+            << "  <MEMC " << name() << ".READ_DIR_HIT> Update directory entry:"
+            << " set = " << std::dec << set
+            << " / way = " << way
+            << " / owner_id = " << entry.owner.srcid
+            << " / owner_ins = " << entry.owner.inst
+            << " / count = " << entry.count
+            << " / is_cnt = " << entry.is_cnt << std::endl;
+        }
+#endif
+
+        m_cache_directory.write(set, way, entry);
+        r_read_fsm    = READ_RSP;
+      }
+      break;
+    }
+
+    ////////////////////
+    case READ_HEAP_REQ:
+    // Get the lock to the HEAP directory
+    {
+      if( r_alloc_heap_fsm.read() == ALLOC_HEAP_READ )
+      {
+        r_read_fsm = READ_HEAP_LOCK;
+      }
+
+#if DEBUG_MEMC_READ
+      if( m_debug_read_fsm )
+      {
+        std::cout 
+          << "  <MEMC " << name() << ".READ_HEAP_REQ> Requesting HEAP lock "
+          << std::endl;
+      }
+#endif
+      break;
+    }
+
+    ////////////////////
+    case READ_HEAP_LOCK:
+    // read data in cache, update the directory
+    // and prepare the HEAP update
+    {
+      if( r_alloc_heap_fsm.read() == ALLOC_HEAP_READ )
+      {
+        // enter counter mode when we reach the limit of copies or the heap is full
+        bool go_cnt = (r_read_count.read() >= r_copies_limit.read()) || m_heap.is_full();
+
+        // read data in the cache
+        size_t set = m_y[(vci_addr_t)(m_cmd_read_addr_fifo.read())];
+        size_t way = r_read_way.read();
+
+        m_cache_data.read_line(way, set, r_read_data);
+
+        // update the cache directory
+        DirectoryEntry entry;
+        entry.valid  = true;
+        entry.is_cnt = go_cnt;
+        entry.dirty  = r_read_dirty.read();
+        entry.tag    = r_read_tag.read();
+        entry.lock   = r_read_lock.read();
+        entry.count  = r_read_count.read() + 1;
+
+        if (not go_cnt)        // Not entering counter mode
+        {
+          entry.owner.srcid    = r_read_copy.read();
+#if L1_MULTI_CACHE
+          entry.owner.cache_id = r_read_copy_cache.read();
+#endif
+          entry.owner.inst     = r_read_copy_inst.read();
+          entry.ptr            = m_heap.next_free_ptr();   // set pointer on the heap
+        }
+        else                // Entering Counter mode
+        {
+          entry.owner.srcid    = 0;
+#if L1_MULTI_CACHE
+          entry.owner.cache_id = 0;
+#endif
+          entry.owner.inst     = false;
+          entry.ptr            = 0;
+        }
+
+        m_cache_directory.write(set, way, entry);
+
+        // prepare the heap update (add an entry, or clear the linked list)
+        if (not go_cnt)     // not switching to counter mode
+        {
+          // We test if the next free entry in the heap is the last
+          HeapEntry heap_entry = m_heap.next_free_entry();
+          r_read_next_ptr      = heap_entry.next;
+          r_read_last_free     = ( heap_entry.next == m_heap.next_free_ptr() );
+
+          r_read_fsm           = READ_HEAP_WRITE; // add an entry in the HEAP
+        }
+        else            // switching to counter mode
+        {
+          if ( r_read_count.read()>1 )            // heap must be cleared
+          {
+            HeapEntry next_entry = m_heap.read(r_read_ptr.read());
+            r_read_next_ptr      = m_heap.next_free_ptr();
+            m_heap.write_free_ptr(r_read_ptr.read());
+
+            if( next_entry.next == r_read_ptr.read() )  // last entry
+            {
+              r_read_fsm = READ_HEAP_LAST;    // erase the entry
+            }
+            else                                        // not the last entry
+            {
+              r_read_ptr = next_entry.next;
+              r_read_fsm = READ_HEAP_ERASE;   // erase the list
+            }
+          }
+          else  // the heap is not used / nothing to do
+          {
+            r_read_fsm = READ_RSP;
+          }
+        }
+
+#if DEBUG_MEMC_READ
+        if( m_debug_read_fsm )
+        {
+          std::cout << "  <MEMC " << name() << ".READ_HEAP_LOCK> Update directory:"
+            << " tag = " << std::hex << entry.tag
+            << " set = " << std::dec << set
+            << " way = " << way
+            << " count = " << entry.count
+            << " is_cnt = " << entry.is_cnt << std::endl;
+        }
+#endif
+      }
+      else
+      {
+        std::cout
+          << "VCI_MEM_CACHE ERROR " << name()
+          << " READ_HEAP_LOCK state" << std::endl
+          << "Bad HEAP allocation"   << std::endl;
+
+        exit(0);
+      }
+
+      break;
+    }
+
+    /////////////////////
+    case READ_HEAP_WRITE:       // add a entry in the heap
+    {
+      if ( r_alloc_heap_fsm.read() == ALLOC_HEAP_READ )
+      {
+        HeapEntry heap_entry;
+        heap_entry.owner.srcid    = m_cmd_read_srcid_fifo.read();
+#if L1_MULTI_CACHE
+        heap_entry.owner.cache_id = m_cmd_read_pktid_fifo.read();
+#endif
+        heap_entry.owner.inst     = (m_cmd_read_pktid_fifo.read() & 0x2);
+
+        if(r_read_count.read() == 1) // creation of a new linked list
+        {
+          heap_entry.next         = m_heap.next_free_ptr();
+        }
+        else                         // head insertion in existing list
+        {
+          heap_entry.next         = r_read_ptr.read();
+        }
+        m_heap.write_free_entry(heap_entry);
+        m_heap.write_free_ptr(r_read_next_ptr.read());
+        if(r_read_last_free.read())  m_heap.set_full();
+
+        r_read_fsm = READ_RSP;
+
+#if DEBUG_MEMC_READ
+        if( m_debug_read_fsm )
+        {
+          std::cout
+            << "  <MEMC " << name() << ".READ_HEAP_WRITE> Add an entry in the heap:"
+            << " owner_id = " << heap_entry.owner.srcid
+            << " owner_ins = " << heap_entry.owner.inst << std::endl;
+        }
+#endif
+      }
+      else
+      {
+        std::cout
+          << "VCI_MEM_CACHE ERROR " << name()
+          << " READ_HEAP_WRITE state" << std::endl
+          << "Bad HEAP allocation" << std::endl;
+
+        exit(0);
+      }
+      break;
+    }
+
+    /////////////////////
+    case READ_HEAP_ERASE:
+    {
+      if ( r_alloc_heap_fsm.read() == ALLOC_HEAP_READ )
+      {
+        HeapEntry next_entry = m_heap.read(r_read_ptr.read());
+        if( next_entry.next == r_read_ptr.read() )
+        {
+          r_read_fsm = READ_HEAP_LAST;
+        }
+        else
+        {
+          r_read_ptr = next_entry.next;
+          r_read_fsm = READ_HEAP_ERASE;
+        }
+      }
+      else
+      {
+        std::cout
+          << "VCI_MEM_CACHE ERROR " << name()
+          << " READ_HEAP_ERASE state" << std::endl
+          << "Bad HEAP allocation" << std::endl;
+
+        exit(0);
+      }
+      break;
+    }
+
+    ////////////////////
+    case READ_HEAP_LAST:
+    {
+      if ( r_alloc_heap_fsm.read() == ALLOC_HEAP_READ )
+      {
+        HeapEntry last_entry;
+        last_entry.owner.srcid    = 0;
+#if L1_MULTI_CACHE
+        last_entry.owner.cache_id = 0;
+#endif
+        last_entry.owner.inst     = false;
+
+        if(m_heap.is_full())
+        {
+          last_entry.next       = r_read_ptr.read();
+          m_heap.unset_full();
+        }
+        else
+        {
+          last_entry.next       = r_read_next_ptr.read();
+        }
+        m_heap.write(r_read_ptr.read(),last_entry);
+        r_read_fsm = READ_RSP;
+      }
+      else
+      {
+        std::cout << "VCI_MEM_CACHE ERROR " << name()
+          << " READ_HEAP_LAST state" << std::endl;
+        std::cout << "Bad HEAP allocation" << std::endl;
+        exit(0);
+      }
+      break;
+    }
+
+    //////////////
+    case READ_RSP:    //  request the TGT_RSP FSM to return data
+    {
+      if( !r_read_to_tgt_rsp_req )
+      {
+        for ( size_t i=0 ; i<m_words ; i++ )  r_read_to_tgt_rsp_data[i] = r_read_data[i];
+        r_read_to_tgt_rsp_word   = m_x[(vci_addr_t)m_cmd_read_addr_fifo.read()];
+        r_read_to_tgt_rsp_length = m_cmd_read_length_fifo.read();
+        r_read_to_tgt_rsp_srcid  = m_cmd_read_srcid_fifo.read();
+        r_read_to_tgt_rsp_trdid  = m_cmd_read_trdid_fifo.read();
+        r_read_to_tgt_rsp_pktid  = m_cmd_read_pktid_fifo.read();
+        r_read_to_tgt_rsp_ll_key = r_read_ll_key.read();
+        cmd_read_fifo_get        = true;
+        r_read_to_tgt_rsp_req    = true;
+        r_read_fsm               = READ_IDLE;
+
+#if DEBUG_MEMC_READ
+        if( m_debug_read_fsm )
+        {
+          std::cout << "  <MEMC " << name() << ".READ_RSP> Request the TGT_RSP FSM to return data:"
+            << " rsrcid = " << std::dec << m_cmd_read_srcid_fifo.read()
+            << " / address = " << std::hex << m_cmd_read_addr_fifo.read()
+            << " / nwords = " << std::dec << m_cmd_read_length_fifo.read() << std::endl;
+        }
+#endif
+      }
+      break;
+    }
+
+    ///////////////////
+    case READ_TRT_LOCK: // read miss : check the Transaction Table
+    {
+      if ( r_alloc_trt_fsm.read() == ALLOC_TRT_READ )
+      {
+        size_t      index     = 0;
+        vci_addr_t  addr      = (vci_addr_t)m_cmd_read_addr_fifo.read();
+        bool        hit_read  = m_transaction_tab.hit_read(m_nline[addr], index);
+        bool        hit_write = m_transaction_tab.hit_write(m_nline[addr]);
+        bool        wok       = !m_transaction_tab.full(index);
+
+        if( hit_read || !wok || hit_write )  // missing line already requested or no space
+        {
+          if(!wok)      m_cpt_trt_full++;
+          if(hit_read || hit_write)   m_cpt_trt_rb++;
+          r_read_fsm = READ_IDLE;
+        }
+        else                  // missing line is requested to the XRAM
+        {
+          m_cpt_read_miss++;
+          r_read_trt_index = index;
+          r_read_fsm       = READ_TRT_SET;
+        }
+
+#if DEBUG_MEMC_READ
+        if( m_debug_read_fsm )
+        {
+          std::cout << "  <MEMC " << name() << ".READ_TRT_LOCK> Check TRT:"
+            << " hit_read = " << hit_read
+            << " / hit_write = " << hit_write
+            << " / full = " << !wok << std::endl;
+        }
+#endif
+      }
+      break;
+    }
+
+    //////////////////
+    case READ_TRT_SET:      // register get transaction in TRT
+    {
+      if ( r_alloc_trt_fsm.read() == ALLOC_TRT_READ )
+      {
+        m_transaction_tab.set(r_read_trt_index.read(),
+            true,
+            m_nline[(vci_addr_t)(m_cmd_read_addr_fifo.read())],
+            m_cmd_read_srcid_fifo.read(),
+            m_cmd_read_trdid_fifo.read(),
+            m_cmd_read_pktid_fifo.read(),
+            true,
+            m_cmd_read_length_fifo.read(),
+            m_x[(vci_addr_t)(m_cmd_read_addr_fifo.read())],
+            std::vector<be_t>(m_words,0),
+            std::vector<data_t>(m_words,0),
+            r_read_ll_key.read());
+#if DEBUG_MEMC_READ
+        if( m_debug_read_fsm )
+        {
+          std::cout << "  <MEMC " << name() << ".READ_TRT_SET> Write in Transaction Table: " << std::hex
+            << " address = " << std::hex << m_cmd_read_addr_fifo.read()
+            << " / srcid = " << std::dec << m_cmd_read_srcid_fifo.read()
+            << std::endl;
+        }
+#endif
+        r_read_fsm = READ_TRT_REQ;
+      }
+      break;
+    }
+
+    //////////////////
+    case READ_TRT_REQ:
+    {
+      // consume the read request in the FIFO,
+      // and send it to the ixr_cmd_fsm
+
+      if( not r_read_to_ixr_cmd_req )
+      {
+        cmd_read_fifo_get       = true;
+        r_read_to_ixr_cmd_req   = true;
+        r_read_to_ixr_cmd_nline = m_nline[(vci_addr_t)(m_cmd_read_addr_fifo.read())];
+        r_read_to_ixr_cmd_trdid = r_read_trt_index.read();
+        r_read_fsm              = READ_IDLE;
+
+#if DEBUG_MEMC_READ
+        if( m_debug_read_fsm )
+        {
+          std::cout
+            << "  <MEMC " << name() << ".READ_TRT_REQ> Request GET transaction for address "
+            << std::hex << m_cmd_read_addr_fifo.read() << std::endl;
+        }
+#endif
+      }
+      break;
+    }
+  } // end switch read_fsm
+
+  ///////////////////////////////////////////////////////////////////////////////////
+  //    WRITE FSM
+  ///////////////////////////////////////////////////////////////////////////////////
+  // The WRITE FSM handles the write bursts and sc requests sent by the processors.
+  // All addresses in a burst must be in the same cache line.
+  // A complete write burst is consumed in the FIFO & copied to a local buffer.
+  // Then the FSM takes the lock protecting the cache directory, to check
+  // if the line is in the cache.
+  //
+  // - In case of HIT, the cache is updated.
+  //   If there is no other copy, an acknowledge response is immediately
+  //   returned to the writing processor.
+  //   If the data is cached by other processors, a coherence transaction must
+  //   be launched (sc requests always require a coherence transaction):
+  //   It is a multicast update if the line is not in counter mode, and the processor
+  //   takes the lock protecting the Update Table (UPT) to register this transaction.
+  //   It is a broadcast invalidate if the line is in counter mode.
+  //   If the UPT is full, it releases the lock(s) and retry. Then, it sends
+  //   a multi-update request to all owners of the line (but the writer),
+  //   through the INIT_CMD FSM. In case of coherence transaction, the WRITE FSM
+  //   does not respond to the writing processor, as this response will be sent by
+  //   the INIT_RSP FSM when all update responses have been received.
+  //
+  // - In case of MISS, the WRITE FSM takes the lock protecting the transaction
+  //   table (TRT). If a read transaction to the XRAM for this line already exists,
+  //   it writes in the TRT (write buffer). Otherwise, if a TRT entry is free,
+  //   the WRITE FSM register a new transaction in TRT, and sends a read line request
+  //   to the XRAM. If the TRT is full, it releases the lock, and waits.
+  //   Finally, the WRITE FSM returns an aknowledge response to the writing processor.
+  /////////////////////////////////////////////////////////////////////////////////////
+
+  switch ( r_write_fsm.read() )
+  {
+    ////////////////
+    case WRITE_IDLE:  // copy first word of a write burst in local buffer
+    {
+      if ( m_cmd_write_addr_fifo.rok() )
+      {
+        if((m_cmd_write_pktid_fifo.read() & 0x7) == TYPE_SC)
+          m_cpt_sc++;
+        else
+        {
+          m_cpt_write++;
+          m_cpt_write_cells++;
+        }
+
+        // consume a word in the FIFO & write it in the local buffer
+        cmd_write_fifo_get  = true;
+        r_write_pending_sc  = false;
+        size_t index        = m_x[(vci_addr_t)(m_cmd_write_addr_fifo.read())];
+
+        r_write_address     = (addr_t)(m_cmd_write_addr_fifo.read());
+        r_write_word_index  = index;
+        r_write_word_count  = 1;
+        r_write_data[index] = m_cmd_write_data_fifo.read();
+        r_write_srcid       = m_cmd_write_srcid_fifo.read();
+        r_write_trdid       = m_cmd_write_trdid_fifo.read();
+        r_write_pktid       = m_cmd_write_pktid_fifo.read();
+
+        // initialize the be field for all words
+        for ( size_t word=0 ; word<m_words ; word++ )
+        {
+          if ( word == index ) r_write_be[word] = m_cmd_write_be_fifo.read();
+          else                 r_write_be[word] = 0x0;
+        }
+
+        if( m_cmd_write_eop_fifo.read() || ((m_cmd_write_pktid_fifo.read() & 0x7)  == TYPE_SC) )
+        {
+          r_write_fsm = WRITE_DIR_REQ;
+        }
+        else
+        {
+          r_write_fsm = WRITE_NEXT;
+        }
+
+#if DEBUG_MEMC_WRITE
+        if( m_debug_write_fsm )
+        {
+          std::cout << "  <MEMC " << name() << ".WRITE_IDLE> Write request "
+            << " srcid = " << std::dec << m_cmd_write_srcid_fifo.read()
+            << " / address = " << std::hex << m_cmd_write_addr_fifo.read()
+            << " / data = " << m_cmd_write_data_fifo.read() << std::endl;
+        }
+#endif
+      }
+      break;
+    }
+
+    ////////////////
+    case WRITE_NEXT:  // copy next word of a write burst in local buffer
+    {
+      if ( m_cmd_write_addr_fifo.rok() )
+      {
+
+#if DEBUG_MEMC_WRITE
+        if( m_debug_write_fsm )
+        {
+          std::cout << "  <MEMC " << name() << ".WRITE_NEXT> Write another word in local buffer"
+                    << std::endl;
+        }
+#endif
+        m_cpt_write_cells++;
+
+        // check that the next word is in the same cache line
+        if (( m_nline[(vci_addr_t)(r_write_address.read())]       !=
+              m_nline[(vci_addr_t)(m_cmd_write_addr_fifo.read())] ))
+        {
+          std::cout << "VCI_MEM_CACHE ERROR " << name() << " WRITE_NEXT state" << std::endl
+                    << "all words in a write burst must be in same cache line" << std::endl;
+
+          exit(0);
+        }
+
+        // consume a word in the FIFO & write it in the local buffer
+        cmd_write_fifo_get  = true;
+        r_write_pending_sc  = false;
+        size_t index        = r_write_word_index.read() + r_write_word_count.read();
+
+        r_write_be[index]   = m_cmd_write_be_fifo.read();
+        r_write_data[index] = m_cmd_write_data_fifo.read();
+        r_write_word_count  = r_write_word_count.read() + 1;
+
+        if ( m_cmd_write_eop_fifo.read() )
+        {
+          r_write_fsm = WRITE_DIR_REQ;
+        }
+      }
+      break;
+    }
+
+    ////////////////////
+    case WRITE_DIR_REQ:
+    // Get the lock to the directory
+    {
+      if ( r_alloc_dir_fsm.read() == ALLOC_DIR_WRITE )
+      {
+        if(((r_write_pktid.read() & 0x7) == TYPE_SC) && not r_write_pending_sc.read()) // check for an SC command (and check that its second flit is not already consumed)
+        {
+          if ( m_cmd_write_addr_fifo.rok() )
+          {
+            size_t index    = m_x[(vci_addr_t)(r_write_address.read())];
+            bool sc_success = m_llsc_table.sc(r_write_address.read(),r_write_data[index].read());
+            r_write_sc_fail = !sc_success;
+
+            assert(m_cmd_write_eop_fifo.read() && "Error in VCI_MEM_CACHE : invalid packet format for SC command");
+            // consume a word in the FIFO & write it in the local buffer
+            cmd_write_fifo_get  = true;
+            r_write_pending_sc  = true;
+            index               = m_x[(vci_addr_t)(m_cmd_write_addr_fifo.read())];
+
+            r_write_address     = (addr_t)(m_cmd_write_addr_fifo.read());
+            r_write_word_index  = index;
+            r_write_word_count  = 1;
+            r_write_data[index] = m_cmd_write_data_fifo.read();
+            if (!sc_success)
+            {
+              r_write_fsm = WRITE_RSP;
+              break;
+            }
+          }
+          else break;
+        }
+        //else it is a TYPE_WRITE, need a simple sw access to the
+        // llsc_global_table
+        else
+        {
+          m_llsc_table.sw(r_write_address.read());
+        }
+        r_write_fsm = WRITE_DIR_LOCK;
+      }
+
+#if DEBUG_MEMC_WRITE
+      if( m_debug_write_fsm )
+      {
+        std::cout 
+          << "  <MEMC " << name() << ".WRITE_DIR_REQ> Requesting DIR lock "
+          << std::endl;
+      }
+#endif
+
+      break;
+    }
+
+    ////////////////////
+    case WRITE_DIR_LOCK:
+    // access directory to check hit/miss
+    {
+      if ( r_alloc_dir_fsm.read() == ALLOC_DIR_WRITE )
+      {
+        size_t  way = 0;
+        DirectoryEntry entry(m_cache_directory.read(r_write_address.read(), way));
+
+        if ( entry.valid ) // hit
+        {
+          // copy directory entry in local buffer in case of hit
+          r_write_is_cnt     = entry.is_cnt;
+          r_write_lock       = entry.lock;
+          r_write_tag        = entry.tag;
+          r_write_copy       = entry.owner.srcid;
+#if L1_MULTI_CACHE
+          r_write_copy_cache = entry.owner.cache_id;
+#endif
+          r_write_copy_inst  = entry.owner.inst;
+          r_write_count      = entry.count;
+          r_write_ptr        = entry.ptr;
+          r_write_way        = way;
+
+          if( entry.is_cnt && entry.count )
+          {
+            r_write_fsm = WRITE_DIR_READ;
+          }
+          else
+          {
+            r_write_fsm = WRITE_DIR_HIT;
+          }
+        }
+        else  // miss
+        {
+          r_write_fsm = WRITE_MISS_TRT_LOCK;
+        }
+
+#if DEBUG_MEMC_WRITE
+        if( m_debug_write_fsm )
+        {
+          std::cout << "  <MEMC " << name() << ".WRITE_DIR_LOCK> Check the directory: "
+            << " address = " << std::hex << r_write_address.read()
+            << " hit = " << std::dec << entry.valid
+            << " count = " << entry.count
+            << " is_cnt = " << entry.is_cnt << std::endl;
+          if((r_write_pktid.read() & 0x7) == TYPE_SC)
+            std::cout << "  <MEMC " << name() << ".WRITE_DIR_LOCK> global_llsc_table SC access" << std::endl;
+          else
+            std::cout << "  <MEMC " << name() << ".WRITE_DIR_LOCK> global_llsc_table SW access" << std::endl;
+        }
+#endif
+      }
+      else
+      {
+        std::cout << "VCI_MEM_CACHE ERROR " << name()
+          << " WRITE_DIR_LOCK state"        << std::endl
+          << "bad DIR allocation"           << std::endl;
+
+        exit(0);
+      }
+
+      break;
+    }
+
+    ////////////////////
+    case WRITE_DIR_READ:  // read the cache and complete the buffer when be!=0xF
+    {
+      // update local buffer
+      size_t set  = m_y[(vci_addr_t)(r_write_address.read())];
+      size_t way  = r_write_way.read();
+      for(size_t word=0 ; word<m_words ; word++)
+      {
+        data_t mask = 0;
+        if  (r_write_be[word].read() & 0x1) mask = mask | 0x000000FF;
+        if  (r_write_be[word].read() & 0x2) mask = mask | 0x0000FF00;
+        if  (r_write_be[word].read() & 0x4) mask = mask | 0x00FF0000;
+        if  (r_write_be[word].read() & 0x8) mask = mask | 0xFF000000;
+
+        // complete only if mask is not null (for energy consumption)
+        r_write_data[word]  = (r_write_data[word].read() & mask) |
+          (m_cache_data.read(way, set, word) & ~mask);
+
+      } // end for
+
+      // test if a coherence broadcast is required
+      r_write_fsm = WRITE_BC_TRT_LOCK;
+
+#if DEBUG_MEMC_WRITE
+      if( m_debug_write_fsm )
+      {
+        std::cout << "  <MEMC " << name() << ".WRITE_DIR_READ> Read the cache to complete local buffer" << std::endl;
+      }
+#endif
+      break;
+    }
+
+    ///////////////////
+    case WRITE_DIR_HIT:
+    {
+      // update the cache directory
+      // update directory with Dirty bit
+      DirectoryEntry entry;
+      entry.valid          = true;
+      entry.dirty          = true;
+      entry.tag          = r_write_tag.read();
+      entry.is_cnt         = r_write_is_cnt.read();
+      entry.lock           = r_write_lock.read();
+      entry.owner.srcid    = r_write_copy.read();
+#if L1_MULTI_CACHE
+      entry.owner.cache_id = r_write_copy_cache.read();
+#endif
+      entry.owner.inst     = r_write_copy_inst.read();
+      entry.count          = r_write_count.read();
+      entry.ptr            = r_write_ptr.read();
+
+      size_t set           = m_y[(vci_addr_t)(r_write_address.read())];
+      size_t way           = r_write_way.read();
+
+      // update directory
+      m_cache_directory.write(set, way, entry);
+
+      // owner is true when the  the first registered copy is the writer itself
+      bool owner = (((r_write_copy.read() == r_write_srcid.read())
+#if L1_MULTI_CACHE
+            and (r_write_copy_cache.read()==r_write_pktid.read())
+#endif
+            ) and not r_write_copy_inst.read());
+
+      // no_update is true when there is no need for coherence transaction
+      // (tests for sc requests)
+      bool no_update = ((r_write_count.read()==0) || ( owner && (r_write_count.read()==1) && (r_write_pktid.read() != TYPE_SC)));
+
+      // write data in the cache if no coherence transaction
+      if( no_update )
+      {
+        for(size_t word=0 ; word<m_words ; word++)
+        {
+          m_cache_data.write(way, set, word, r_write_data[word].read(), r_write_be[word].read());
+
+          if ( m_monitor_ok )
+          {
+            vci_addr_t address = (r_write_address.read() & ~(vci_addr_t)0x3F) | word<<2;
+            char buf[80];
+            snprintf(buf, 80, "WRITE_DIR_HIT srcid %d", r_write_srcid.read());
+            check_monitor( buf, address, r_write_data[word].read() );
+          }
+        }
+      }
+
+      if ( owner and not no_update and (r_write_pktid.read() != TYPE_SC))
+      {
+        r_write_count = r_write_count.read() - 1;
+      }
+
+      if ( no_update )
+      // Write transaction completed
+      {
+        r_write_fsm = WRITE_RSP;
+      }
+      else
+      // coherence update required
+      {
+        if( !r_write_to_init_cmd_multi_req.read()   &&
+            !r_write_to_init_cmd_brdcast_req.read() )
+        {
+          r_write_fsm = WRITE_UPT_LOCK;
+        }
+        else
+        {
+          r_write_fsm = WRITE_WAIT;
+        }
+      }
+
+#if DEBUG_MEMC_WRITE
+      if( m_debug_write_fsm )
+      {
+        if ( no_update )
+        {
+          std::cout << "  <MEMC " << name() << ".WRITE_DIR_HIT> Write into cache / No coherence transaction"
+            << std::endl;
+        }
+        else
+        {
+          std::cout << "  <MEMC " << name() << ".WRITE_DIR_HIT> Coherence update required:"
+            << " is_cnt = " << r_write_is_cnt.read()
+            << " nb_copies = " << std::dec << r_write_count.read() << std::endl;
+          if (owner)
+            std::cout << "       ... but the first copy is the writer" << std::endl;
+        }
+      }
+#endif
+      break;
+    }
+
+      ////////////////////
+    case WRITE_UPT_LOCK:  // Try to register the update request in UPT
+    {
+      if ( r_alloc_upt_fsm.read() == ALLOC_UPT_WRITE )
+      {
+        bool        wok        = false;
+        size_t      index      = 0;
+        size_t      srcid      = r_write_srcid.read();
+        size_t      trdid      = r_write_trdid.read();
+        size_t      pktid      = r_write_pktid.read();
+        addr_t      nline      = m_nline[(vci_addr_t)(r_write_address.read())];
+        size_t      nb_copies  = r_write_count.read();
+        size_t      set        = m_y[(vci_addr_t)(r_write_address.read())];
+        size_t      way        = r_write_way.read();
+
+        wok = m_update_tab.set(true,  // it's an update transaction
+            false,    // it's not a broadcast
+            true,     // it needs a response
+            srcid,
+            trdid,
+            pktid,
+            nline,
+            nb_copies,
+            index);
+        if ( wok )    // write data in cache
+        {
+          for(size_t word=0 ; word<m_words ; word++)
+          {
+            m_cache_data.write(way, set, word, r_write_data[word].read(), r_write_be[word].read());
+
+            if ( m_monitor_ok )
+            {
+              vci_addr_t address = (r_write_address.read() & ~(vci_addr_t)0x3F) | word<<2;
+              char buf[80];
+              snprintf(buf, 80, "WRITE_UPT_LOCK srcid %d", srcid);
+              check_monitor(buf, address, r_write_data[word].read() );
+            }
+          }
+        }
+
+#if DEBUG_MEMC_WRITE
+        if( m_debug_write_fsm )
+        {
+          if ( wok )
+          {
+            std::cout << "  <MEMC " << name() << ".WRITE_UPT_LOCK> Register the multicast update in UPT / "
+              << " nb_copies = " << r_write_count.read() << std::endl;
+          }
+        }
+#endif
+        r_write_upt_index = index;
+        //  releases the lock protecting UPT and the DIR if no entry...
+        if ( wok ) r_write_fsm = WRITE_UPT_HEAP_LOCK;
+        else       r_write_fsm = WRITE_WAIT;
+      }
+      break;
+    }
+
+      /////////////////////////
+    case WRITE_UPT_HEAP_LOCK:   // get access to heap
+    {
+      if( r_alloc_heap_fsm.read() == ALLOC_HEAP_WRITE )
+      {
+
+#if DEBUG_MEMC_WRITE
+        if( m_debug_write_fsm )
+        {
+          std::cout << "  <MEMC " << name() << ".WRITE_UPT_HEAP_LOCK> Get acces to the HEAP" << std::endl;
+        }
+#endif
+        r_write_fsm = WRITE_UPT_REQ;
+      }
+      break;
+    }
+
+    //////////////////
+    case WRITE_UPT_REQ:
+    {
+      // prepare the coherence transaction for the INIT_CMD FSM
+      // and write the first copy in the FIFO
+      // send the request if only one copy
+
+      if( !r_write_to_init_cmd_multi_req.read() &&
+          !r_write_to_init_cmd_brdcast_req.read()  )  // no pending coherence request
+      {
+        r_write_to_init_cmd_brdcast_req  = false;
+        r_write_to_init_cmd_trdid        = r_write_upt_index.read();
+        r_write_to_init_cmd_nline        = m_nline[(vci_addr_t)(r_write_address.read())];
+        r_write_to_init_cmd_index        = r_write_word_index.read();
+        r_write_to_init_cmd_count        = r_write_word_count.read();
+
+        for(size_t i=0; i<m_words ; i++) r_write_to_init_cmd_be[i]=r_write_be[i].read();
+
+        size_t min = r_write_word_index.read();
+        size_t max = r_write_word_index.read() + r_write_word_count.read();
+        for (size_t i=min ; i<max ; i++) r_write_to_init_cmd_data[i] = r_write_data[i];
+
+        if( (r_write_copy.read() != r_write_srcid.read()) or (r_write_pktid.read() == TYPE_SC) or
+#if L1_MULTI_CACHE
+            (r_write_copy_cache.read() != r_write_pktid.read()) or
+#endif
+            r_write_copy_inst.read() )
+        {
+          // put the first srcid in the fifo
+          write_to_init_cmd_fifo_put     = true;
+          write_to_init_cmd_fifo_inst    = r_write_copy_inst.read();
+          write_to_init_cmd_fifo_srcid   = r_write_copy.read();
+#if L1_MULTI_CACHE
+          write_to_init_cmd_fifo_cache_id= r_write_copy_cache.read();
+#endif
+          if(r_write_count.read() == 1)
+          {
+            r_write_fsm = WRITE_IDLE;
+            r_write_to_init_cmd_multi_req = true;
+          }
+          else
+          {
+            r_write_fsm = WRITE_UPT_NEXT;
+            r_write_to_dec = false;
+
+          }
+        }
+        else
+        {
+          r_write_fsm = WRITE_UPT_NEXT;
+          r_write_to_dec = false;
+        }
+
+#if DEBUG_MEMC_WRITE
+        if( m_debug_write_fsm )
+        {
+          std::cout << "  <MEMC " << name() << ".WRITE_UPT_REQ> Post first request to INIT_CMD FSM"
+            << " / srcid = " << std::dec << r_write_copy.read()
+            << " / inst = "  << std::dec << r_write_copy_inst.read() << std::endl;
+          if ( r_write_count.read() == 1)
+            std::cout << "         ... and this is the last" << std::endl;
+        }
+#endif
+      }
+      break;
+    }
+
+    ///////////////////
+    case WRITE_UPT_NEXT:
+    {
+      // continue the multi-update request to INIT_CMD fsm
+      // when there is copies in the heap.
+      // if one copy in the heap is the writer itself
+      // the corresponding SRCID should not be written in the fifo,
+      // but the UPT counter must be decremented.
+      // As this decrement is done in the WRITE_UPT_DEC state,
+      // after the last copy has been found, the decrement request
+      // must be  registered in the r_write_to_dec flip-flop.
+
+      HeapEntry entry = m_heap.read(r_write_ptr.read());
+
+      bool dec_upt_counter;
+
+      if(((entry.owner.srcid != r_write_srcid.read()) || (r_write_pktid.read() == TYPE_SC)) or
+#if L1_MULTI_CACHE
+          (entry.owner.cache_id != r_write_pktid.read()) or
+#endif
+          entry.owner.inst)             // put the next srcid in the fifo
+      {
+        dec_upt_counter                 = false;
+        write_to_init_cmd_fifo_put      = true;
+        write_to_init_cmd_fifo_inst     = entry.owner.inst;
+        write_to_init_cmd_fifo_srcid    = entry.owner.srcid;
+#if L1_MULTI_CACHE
+        write_to_init_cmd_fifo_cache_id = entry.owner.cache_id;
+#endif
+
+#if DEBUG_MEMC_WRITE
+        if( m_debug_write_fsm )
+        {
+          std::cout << "  <MEMC " << name() << ".WRITE_UPT_NEXT> Post another request to INIT_CMD FSM"
+            << " / heap_index = " << std::dec << r_write_ptr.read()
+            << " / srcid = " << std::dec << r_write_copy.read()
+            << " / inst = "  << std::dec << r_write_copy_inst.read() << std::endl;
+          if( entry.next == r_write_ptr.read() )
+            std::cout << "        ... and this is the last" << std::endl;
+        }
+#endif
+      }
+      else                                // the UPT counter must be decremented
+      {
+        dec_upt_counter = true;
+
+#if DEBUG_MEMC_WRITE
+        if( m_debug_write_fsm )
+        {
+          std::cout << "  <MEMC " << name() << ".WRITE_UPT_NEXT> Skip one entry in heap matching the writer"
+            << " / heap_index = " << std::dec << r_write_ptr.read()
+            << " / srcid = " << std::dec << r_write_copy.read()
+            << " / inst = "  << std::dec << r_write_copy_inst.read() << std::endl;
+          if( entry.next == r_write_ptr.read() )
+            std::cout << "        ... and this is the last" << std::endl;
+        }
+#endif
+      }
+
+      // register the possible UPT decrement request
+      r_write_to_dec = dec_upt_counter or r_write_to_dec.read();
+
+      if( not m_write_to_init_cmd_inst_fifo.wok() )
+      {
+        std::cout << "VCI_MEM_CACHE ERROR " << name() << " WRITE_UPT_NEXT state" << std::endl
+          << "The write_to_init_cmd_fifo should not be full" << std::endl
+          << "as the depth should be larger than the max number of copies" << std::endl;
+        exit(0);
+      }
+
+      r_write_ptr = entry.next;
+
+      if( entry.next == r_write_ptr.read() )  // last copy
+      {
+        r_write_to_init_cmd_multi_req = true;
+        if( r_write_to_dec.read() or dec_upt_counter)   r_write_fsm = WRITE_UPT_DEC;
+        else                                          r_write_fsm = WRITE_IDLE;
+      }
+      break;
+    }
+
+    //////////////////
+    case WRITE_UPT_DEC:
+    {
+      // If the initial writer has a copy, it should not
+      // receive an update request, but the counter in the
+      // update table must be decremented by the INIT_RSP FSM.
+
+      if ( !r_write_to_init_rsp_req.read() )
+      {
+        r_write_to_init_rsp_req = true;
+        r_write_to_init_rsp_upt_index = r_write_upt_index.read();
+        r_write_fsm = WRITE_IDLE;
+      }
+      break;
+    }
+    
+    ///////////////
+    case WRITE_RSP:
+    {
+      // Post a request to TGT_RSP FSM to acknowledge the write
+      // In order to increase the Write requests throughput,
+      // we don't wait to return in the IDLE state to consume
+      // a new request in the write FIFO
+
+      if ( !r_write_to_tgt_rsp_req.read() )
+      {
+        // post the request to TGT_RSP_FSM
+        r_write_to_tgt_rsp_req     = true;
+        r_write_to_tgt_rsp_srcid   = r_write_srcid.read();
+        r_write_to_tgt_rsp_trdid   = r_write_trdid.read();
+        r_write_to_tgt_rsp_pktid   = r_write_pktid.read();
+        r_write_to_tgt_rsp_sc_fail = r_write_sc_fail.read();
+
+        // try to get a new write request from the FIFO
+        if ( m_cmd_write_addr_fifo.rok() )
+        {
+          if((m_cmd_write_pktid_fifo.read() & 0x7) == TYPE_SC)
+            m_cpt_sc++;
+          else
+          {
+            m_cpt_write++;
+            m_cpt_write_cells++;
+          }
+
+          // consume a word in the FIFO & write it in the local buffer
+          cmd_write_fifo_get  = true;
+          r_write_pending_sc  = false;
+          size_t index        = m_x[(vci_addr_t)(m_cmd_write_addr_fifo.read())];
+
+          r_write_address     = (addr_t)(m_cmd_write_addr_fifo.read());
+          r_write_word_index  = index;
+          r_write_word_count  = 1;
+          r_write_data[index] = m_cmd_write_data_fifo.read();
+          r_write_srcid       = m_cmd_write_srcid_fifo.read();
+          r_write_trdid       = m_cmd_write_trdid_fifo.read();
+          r_write_pktid       = m_cmd_write_pktid_fifo.read();
+
+          // initialize the be field for all words
+          for ( size_t word=0 ; word<m_words ; word++ )
+          {
+            if ( word == index ) r_write_be[word] = m_cmd_write_be_fifo.read();
+            else                 r_write_be[word] = 0x0;
+          }
+
+          if( m_cmd_write_eop_fifo.read() || ((m_cmd_write_pktid_fifo.read() & 0x7)  == TYPE_SC) )
+          {
+            r_write_fsm = WRITE_DIR_REQ;
+          }
+          else
+          {
+            r_write_fsm = WRITE_NEXT;
+          }
+        }
+        else
+        {
+          r_write_fsm = WRITE_IDLE;
+        }
+
+#if DEBUG_MEMC_WRITE
+        if( m_debug_write_fsm )
+        {
+          std::cout << "  <MEMC " << name() << ".WRITE_RSP> Post a request to TGT_RSP FSM: rsrcid = "
+            << std::dec << r_write_srcid.read() << std::endl;
+          if ( m_cmd_write_addr_fifo.rok() )
+          {
+            std::cout << "                    New Write request: "
+              << " srcid = " << std::dec << m_cmd_write_srcid_fifo.read()
+              << " / address = " << std::hex << m_cmd_write_addr_fifo.read()
+              << " / data = " << m_cmd_write_data_fifo.read() << std::endl;
+          }
+        }
+#endif
+      }
+      break;
+    }
+
+    /////////////////////////
+    case WRITE_MISS_TRT_LOCK: // Miss : check Transaction Table
+    {
+      if ( r_alloc_trt_fsm.read() == ALLOC_TRT_WRITE )
+      {
+
+#if DEBUG_MEMC_WRITE
+        if( m_debug_write_fsm )
+        {
+          std::cout << "  <MEMC " << name() << ".WRITE_MISS_TRT_LOCK> Check the TRT" << std::endl;
+        }
+#endif
+        size_t  hit_index = 0;
+        size_t  wok_index = 0;
+        vci_addr_t  addr  = (vci_addr_t)r_write_address.read();
+        bool    hit_read  = m_transaction_tab.hit_read(m_nline[addr], hit_index);
+        bool    hit_write = m_transaction_tab.hit_write(m_nline[addr]);
+        bool    wok       = !m_transaction_tab.full(wok_index);
+
+        if ( hit_read )   // register the modified data in TRT
+        {
+          r_write_trt_index = hit_index;
+          r_write_fsm       = WRITE_MISS_TRT_DATA;
+          m_cpt_write_miss++;
+        }
+        else if ( wok && !hit_write )   // set a new entry in TRT
+        {
+          r_write_trt_index = wok_index;
+          r_write_fsm       = WRITE_MISS_TRT_SET;
+          m_cpt_write_miss++;
+        }
+        else    // wait an empty entry in TRT
+        {
+          r_write_fsm       = WRITE_WAIT;
+          m_cpt_trt_full++;
+        }
+      }
+      break;
+    }
+
+    ////////////////
+    case WRITE_WAIT:  // release the locks protecting the shared ressources
+    {
+#if DEBUG_MEMC_WRITE
+      if( m_debug_write_fsm )
+      {
+        std::cout << "  <MEMC " << name() << ".WRITE_WAIT> Releases the locks before retry" << std::endl;
+      }
+#endif
+      r_write_fsm = WRITE_DIR_REQ;
+      break;
+    }
+
+    ////////////////////////
+    case WRITE_MISS_TRT_SET:  // register a new transaction in TRT (Write Buffer)
+    {
+      if ( r_alloc_trt_fsm.read() == ALLOC_TRT_WRITE )
+      {
+        std::vector<be_t>   be_vector;
+        std::vector<data_t> data_vector;
+        be_vector.clear();
+        data_vector.clear();
+        for ( size_t i=0; i<m_words; i++ )
+        {
+          be_vector.push_back(r_write_be[i]);
+          data_vector.push_back(r_write_data[i]);
+        }
+        m_transaction_tab.set(r_write_trt_index.read(),
+            true,     // read request to XRAM
+            m_nline[(vci_addr_t)(r_write_address.read())],
+            r_write_srcid.read(),
+            r_write_trdid.read(),
+            r_write_pktid.read(),
+            false,      // not a processor read
+            0,        // not a single word
+            0,            // word index
+            be_vector,
+            data_vector);
+        r_write_fsm = WRITE_MISS_XRAM_REQ;
+
+#if DEBUG_MEMC_WRITE
+        if( m_debug_write_fsm )
+        {
+          std::cout << "  <MEMC " << name() << ".WRITE_MISS_TRT_SET> Set a new entry in TRT" << std::endl;
+        }
+#endif
+      }
+      break;
+    }
+
+      /////////////////////////
+    case WRITE_MISS_TRT_DATA: // update an entry in TRT (used as a Write Buffer)
+    {
+      if ( r_alloc_trt_fsm.read() == ALLOC_TRT_WRITE )
+      {
+        std::vector<be_t> be_vector;
+        std::vector<data_t> data_vector;
+        be_vector.clear();
+        data_vector.clear();
+        for ( size_t i=0; i<m_words; i++ )
+        {
+          be_vector.push_back(r_write_be[i]);
+          data_vector.push_back(r_write_data[i]);
+        }
+        m_transaction_tab.write_data_mask(r_write_trt_index.read(),
+            be_vector,
+            data_vector);
+        r_write_fsm = WRITE_RSP;
+
+#if DEBUG_MEMC_WRITE
+        if( m_debug_write_fsm )
+        {
+          std::cout << "  <MEMC " << name() << ".WRITE_MISS_TRT_DATA> Modify an existing entry in TRT" << std::endl;
+          m_transaction_tab.print( r_write_trt_index.read() );
+        }
+#endif
+      }
+      break;
+    }
+
+    /////////////////////////
+    case WRITE_MISS_XRAM_REQ: // send a GET request to IXR_CMD FSM
+    {
+      if ( !r_write_to_ixr_cmd_req )
+      {
+        r_write_to_ixr_cmd_req   = true;
+        r_write_to_ixr_cmd_write = false;
+        r_write_to_ixr_cmd_nline = m_nline[(vci_addr_t)(r_write_address.read())];
+        r_write_to_ixr_cmd_trdid = r_write_trt_index.read();
+        r_write_fsm              = WRITE_RSP;
+
+#if DEBUG_MEMC_WRITE
+        if( m_debug_write_fsm )
+        {
+          std::cout << "  <MEMC " << name() << ".WRITE_MISS_XRAM_REQ> Post a GET request to the IXR_CMD FSM" << std::endl;
+        }
+#endif
+      }
+      break;
+    }
+
+    ///////////////////////
+    case WRITE_BC_TRT_LOCK:     // Check TRT not full
+    {
+      if ( r_alloc_trt_fsm.read() == ALLOC_TRT_WRITE )
+      {
+        size_t wok_index = 0;
+        bool wok = !m_transaction_tab.full( wok_index );
+        if ( wok )    // set a new entry in TRT
+        {
+          r_write_trt_index = wok_index;
+          r_write_fsm       = WRITE_BC_UPT_LOCK;
+        }
+        else  // wait an empty entry in TRT
+        {
+          r_write_fsm       = WRITE_WAIT;
+        }
+
+#if DEBUG_MEMC_WRITE
+        if( m_debug_write_fsm )
+        {
+          std::cout << "  <MEMC " << name() << ".WRITE_BC_TRT_LOCK> Check TRT : wok = "
+            << wok << " / index = " << wok_index << std::endl;
+        }
+#endif
+      }
+      break;
+    }
+
+    //////////////////////
+    case WRITE_BC_UPT_LOCK:      // register BC transaction in UPT
+    {
+      if ( r_alloc_upt_fsm.read() == ALLOC_UPT_WRITE )
+      {
+        bool        wok       = false;
+        size_t      index     = 0;
+        size_t      srcid     = r_write_srcid.read();
+        size_t      trdid     = r_write_trdid.read();
+        size_t      pktid     = r_write_pktid.read();
+        addr_t      nline     = m_nline[(vci_addr_t)(r_write_address.read())];
+        size_t      nb_copies = r_write_count.read();
+
+        wok =m_update_tab.set(false,  // it's an inval transaction
+            true,     // it's a broadcast
+            true,     // it needs a response
+            srcid,
+            trdid,
+            pktid,
+            nline,
+            nb_copies,
+            index);
+
+#if DEBUG_MEMC_WRITE
+        if( m_debug_write_fsm )
+        {
+          if ( wok )
+          {
+            std::cout << "  <MEMC " << name() << ".WRITE_BC_UPT_LOCK> Register the broadcast inval in UPT / "
+              << " nb_copies = " << r_write_count.read() << std::endl;
+          }
+        }
+#endif
+        r_write_upt_index = index;
+
+        if ( wok ) r_write_fsm = WRITE_BC_DIR_INVAL;
+        else       r_write_fsm = WRITE_WAIT;
+      }
+      break;
+    }
+
+    ////////////////////////
+    case WRITE_BC_DIR_INVAL:
+    {
+      // Register a put transaction to XRAM in TRT
+      // and invalidate the line in directory
+      if ( (r_alloc_trt_fsm.read() != ALLOC_TRT_WRITE ) ||
+          (r_alloc_upt_fsm.read() != ALLOC_UPT_WRITE ) ||
+          (r_alloc_dir_fsm.read() != ALLOC_DIR_WRITE ) )
+      {
+        std::cout << "VCI_MEM_CACHE ERROR " << name() << " WRITE_BC_DIR_INVAL state" << std::endl;
+        std::cout << "bad TRT, DIR, or UPT allocation" << std::endl;
+        exit(0);
+      }
+
+      // register a write request to XRAM in TRT
+      m_transaction_tab.set(r_write_trt_index.read(),
+          false,    // write request to XRAM
+          m_nline[(vci_addr_t)(r_write_address.read())],
+          0,
+          0,
+          0,
+          false,    // not a processor read
+          0,        // not a single word
+          0,            // word index
+          std::vector<be_t>(m_words,0),
+          std::vector<data_t>(m_words,0));
+
+      // invalidate directory entry
+      DirectoryEntry entry;
+      entry.valid         = false;
+      entry.dirty         = false;
+      entry.tag         = 0;
+      entry.is_cnt        = false;
+      entry.lock          = false;
+      entry.owner.srcid   = 0;
+#if L1_MULTI_CACHE
+      entry.owner.cache_id= 0;
+#endif
+      entry.owner.inst    = false;
+      entry.ptr           = 0;
+      entry.count         = 0;
+      size_t set          = m_y[(vci_addr_t)(r_write_address.read())];
+      size_t way          = r_write_way.read();
+
+      m_cache_directory.write(set, way, entry);
+
+#if DEBUG_MEMC_WRITE
+      if( m_debug_write_fsm )
+      {
+        std::cout << "  <MEMC " << name() << ".WRITE_BC_DIR_INVAL> Invalidate the directory entry: @ = "
+          << r_write_address.read() << " / register the put transaction in TRT:" << std::endl;
+      }
+#endif
+      r_write_fsm = WRITE_BC_CC_SEND;
+      break;
+    }
+
+    //////////////////////
+    case WRITE_BC_CC_SEND:    // Post a coherence broadcast request to INIT_CMD FSM
+    {
+      if ( !r_write_to_init_cmd_multi_req.read() && !r_write_to_init_cmd_brdcast_req.read() )
+      {
+        r_write_to_init_cmd_multi_req   = false;
+        r_write_to_init_cmd_brdcast_req = true;
+        r_write_to_init_cmd_trdid       = r_write_upt_index.read();
+        r_write_to_init_cmd_nline       = m_nline[(vci_addr_t)(r_write_address.read())];
+        r_write_to_init_cmd_index       = 0;
+        r_write_to_init_cmd_count       = 0;
+
+        for(size_t i=0; i<m_words ; i++)
+        {
+          r_write_to_init_cmd_be[i]=0;
+          r_write_to_init_cmd_data[i] = 0;
+        }
+        r_write_fsm = WRITE_BC_XRAM_REQ;
+
+#if DEBUG_MEMC_WRITE
+        if( m_debug_write_fsm )
+        {
+          std::cout << "  <MEMC " << name() << ".WRITE_BC_CC_SEND> Post a broadcast request to INIT_CMD FSM" << std::endl;
+        }
+#endif
+      }
+      break;
+    }
+
+    ///////////////////////
+    case WRITE_BC_XRAM_REQ:   // Post a put request to IXR_CMD FSM
+    {
+      if ( !r_write_to_ixr_cmd_req )
+      {
+        r_write_to_ixr_cmd_req     = true;
+        r_write_to_ixr_cmd_write   = true;
+        r_write_to_ixr_cmd_nline   = m_nline[(vci_addr_t)(r_write_address.read())];
+        r_write_to_ixr_cmd_trdid   = r_write_trt_index.read();
+
+        for(size_t i=0; i<m_words; i++) r_write_to_ixr_cmd_data[i] = r_write_data[i];
+
+        r_write_fsm = WRITE_IDLE;
+
+#if DEBUG_MEMC_WRITE
+        if( m_debug_write_fsm )
+        {
+          std::cout << "  <MEMC " << name() << ".WRITE_BC_XRAM_REQ> Post a put request to IXR_CMD FSM" << std::endl;
+        }
+#endif
+      }
+      break;
+    }
+  } // end switch r_write_fsm
+
+    ///////////////////////////////////////////////////////////////////////
+    //    IXR_CMD FSM
+    ///////////////////////////////////////////////////////////////////////
+    // The IXR_CMD fsm controls the command packets to the XRAM :
+    // - It sends a single cell VCI read request to the XRAM in case of MISS
+    // posted by the READ, WRITE or CAS FSMs : the TRDID field contains
+    // the Transaction Tab index.
+    // The VCI response is a multi-cell packet : the N cells contain
+    // the N data words.
+    // - It sends a multi-cell VCI write when the XRAM_RSP FSM, WRITE FSM
+    // or CAS FSM request to save a dirty line to the XRAM.
+    // The VCI response is a single cell packet.
+    // This FSM handles requests from the READ, WRITE, CAS & XRAM_RSP FSMs
+    // with a round-robin priority.
+    ////////////////////////////////////////////////////////////////////////
+
+    switch ( r_ixr_cmd_fsm.read() )
+    {
+        ////////////////////////
+        case IXR_CMD_READ_IDLE:
+        if      ( r_write_to_ixr_cmd_req )     r_ixr_cmd_fsm = IXR_CMD_WRITE_NLINE;
+        else if ( r_cas_to_ixr_cmd_req  )      r_ixr_cmd_fsm = IXR_CMD_CAS_NLINE;
+        else if ( r_xram_rsp_to_ixr_cmd_req  ) r_ixr_cmd_fsm = IXR_CMD_XRAM_DATA;
+        else if ( r_read_to_ixr_cmd_req  )     r_ixr_cmd_fsm = IXR_CMD_READ_NLINE;
+        break;
+        ////////////////////////
+        case IXR_CMD_WRITE_IDLE:
+        if      ( r_cas_to_ixr_cmd_req  )      r_ixr_cmd_fsm = IXR_CMD_CAS_NLINE;
+        else if ( r_xram_rsp_to_ixr_cmd_req  ) r_ixr_cmd_fsm = IXR_CMD_XRAM_DATA;
+        else if ( r_read_to_ixr_cmd_req  )     r_ixr_cmd_fsm = IXR_CMD_READ_NLINE;
+        else if ( r_write_to_ixr_cmd_req )     r_ixr_cmd_fsm = IXR_CMD_WRITE_NLINE;
+        break;
+        ////////////////////////
+        case IXR_CMD_CAS_IDLE:
+        if      ( r_xram_rsp_to_ixr_cmd_req  ) r_ixr_cmd_fsm = IXR_CMD_XRAM_DATA;
+        else if ( r_read_to_ixr_cmd_req  )     r_ixr_cmd_fsm = IXR_CMD_READ_NLINE;
+        else if ( r_write_to_ixr_cmd_req )     r_ixr_cmd_fsm = IXR_CMD_WRITE_NLINE;
+        else if ( r_cas_to_ixr_cmd_req  )      r_ixr_cmd_fsm = IXR_CMD_CAS_NLINE;
+        break;
+        ////////////////////////
+        case IXR_CMD_XRAM_IDLE:
+        if      ( r_read_to_ixr_cmd_req  )     r_ixr_cmd_fsm = IXR_CMD_READ_NLINE;
+        else if ( r_write_to_ixr_cmd_req )     r_ixr_cmd_fsm = IXR_CMD_WRITE_NLINE;
+        else if ( r_cas_to_ixr_cmd_req  )      r_ixr_cmd_fsm = IXR_CMD_CAS_NLINE;
+        else if ( r_xram_rsp_to_ixr_cmd_req  ) r_ixr_cmd_fsm = IXR_CMD_XRAM_DATA;
+        break;
+        /////////////////////////       // send a get request to XRAM
+        case IXR_CMD_READ_NLINE:
+        if ( p_vci_ixr.cmdack )
+        {
+            r_ixr_cmd_fsm = IXR_CMD_READ_IDLE;
+            r_read_to_ixr_cmd_req = false;
+
+#if DEBUG_MEMC_IXR_CMD
+if( m_debug_ixr_cmd_fsm )
+{
+    std::cout << "  <MEMC " << name() << ".IXR_CMD_READ_NLINE> Send a get request to xram" << std::endl;
+}
+#endif
+        }
+        break;
+        //////////////////////////
+        case IXR_CMD_WRITE_NLINE:     // send a put or get command to XRAM
+        if ( p_vci_ixr.cmdack )
+        {
+            if( r_write_to_ixr_cmd_write.read())
+            {
+                if ( r_ixr_cmd_cpt.read() == (m_words - 1) )
+                {
+                    r_ixr_cmd_cpt = 0;
+                    r_ixr_cmd_fsm = IXR_CMD_WRITE_IDLE;
+                    r_write_to_ixr_cmd_req = false;
+                }
+                else
+                {
+                    r_ixr_cmd_cpt = r_ixr_cmd_cpt + 1;
+                }
+
+#if DEBUG_MEMC_IXR_CMD
+if( m_debug_ixr_cmd_fsm )
+{
+    std::cout << "  <MEMC " << name() << ".IXR_CMD_WRITE_NLINE> Send a put request to xram" << std::endl;
+}
+#endif
+            }
+            else
+            {
+                r_ixr_cmd_fsm = IXR_CMD_WRITE_IDLE;
+                r_write_to_ixr_cmd_req = false;
+
+#if DEBUG_MEMC_IXR_CMD
+if( m_debug_ixr_cmd_fsm )
+{
+    std::cout << "  <MEMC " << name() << ".IXR_CMD_WRITE_NLINE> Send a get request to xram" << std::endl;
+}
+#endif
+            }
+        }
+        break;
+        //////////////////////
+        case IXR_CMD_CAS_NLINE:      // send a put or get command to XRAM
+        if ( p_vci_ixr.cmdack )
+        {
+            if( r_cas_to_ixr_cmd_write.read())
+            {
+                if ( r_ixr_cmd_cpt.read() == (m_words - 1) )
+                {
+                    r_ixr_cmd_cpt = 0;
+                    r_ixr_cmd_fsm = IXR_CMD_CAS_IDLE;
+                    r_cas_to_ixr_cmd_req = false;
+                }
+                else
+                {
+                    r_ixr_cmd_cpt = r_ixr_cmd_cpt + 1;
+                }
+
+#if DEBUG_MEMC_IXR_CMD
+if( m_debug_ixr_cmd_fsm )
+{
+    std::cout << "  <MEMC " << name() << ".IXR_CMD_CAS_NLINE> Send a put request to xram" << std::endl;
+}
+#endif
+            }
+            else
+            {
+                r_ixr_cmd_fsm = IXR_CMD_CAS_IDLE;
+                r_cas_to_ixr_cmd_req = false;
+
+#if DEBUG_MEMC_IXR_CMD
+if( m_debug_ixr_cmd_fsm )
+{
+    std::cout << "  <MEMC " << name() << ".IXR_CMD_CAS_NLINE> Send a get request to xram" << std::endl;
+}
+#endif
+            }
+        }
+        break;
+        ////////////////////////
+        case IXR_CMD_XRAM_DATA:     // send a put command to XRAM
+        if ( p_vci_ixr.cmdack )
+        {
+            if ( r_ixr_cmd_cpt.read() == (m_words - 1) )
+            {
+                r_ixr_cmd_cpt = 0;
+                r_ixr_cmd_fsm = IXR_CMD_XRAM_IDLE;
+                r_xram_rsp_to_ixr_cmd_req = false;
+            }
+            else
+            {
+                r_ixr_cmd_cpt = r_ixr_cmd_cpt + 1;
+            }
+
+#if DEBUG_MEMC_IXR_CMD
+if( m_debug_ixr_cmd_fsm )
+{
+    std::cout << "  <MEMC " << name() << ".IXR_CMD_XRAM_DATA> Send a put request to xram" << std::endl;
+}
+#endif
+        }
+        break;
+
+    } // end switch r_ixr_cmd_fsm
+
+    ////////////////////////////////////////////////////////////////////////////
+    //                IXR_RSP FSM
+    ////////////////////////////////////////////////////////////////////////////
+    // The IXR_RSP FSM receives the response packets from the XRAM,
+    // for both put transaction, and get transaction.
+    //
+    // - A response to a put request is a single-cell VCI packet.
+    // The Transaction Tab index is contained in the RTRDID field.
+    // The FSM takes the lock protecting the TRT, and the corresponding
+    // entry is erased.
+    //
+    // - A response to a get request is a multi-cell VCI packet.
+    // The Transaction Tab index is contained in the RTRDID field.
+    // The N cells contain the N words of the cache line in the RDATA field.
+    // The FSM takes the lock protecting the TRT to store the line in the TRT
+    // (taking into account the write requests already stored in the TRT).
+    // When the line is completely written, the corresponding rok signal is set.
+    ///////////////////////////////////////////////////////////////////////////////
+
+    switch ( r_ixr_rsp_fsm.read() )
+    {
+        //////////////////
+        case IXR_RSP_IDLE:  // test if it's a get or a put transaction
+        {
+            if ( p_vci_ixr.rspval.read() )
+            {
+                r_ixr_rsp_cpt   = 0;
+                r_ixr_rsp_trt_index = p_vci_ixr.rtrdid.read();
+                if ( p_vci_ixr.reop.read() && !(p_vci_ixr.rerror.read()&0x1))  // put transaction
+                {
+                    r_ixr_rsp_fsm = IXR_RSP_ACK;
+
+#if DEBUG_MEMC_IXR_RSP
+if( m_debug_ixr_rsp_fsm )
+{
+    std::cout << "  <MEMC " << name() << ".IXR_RSP_IDLE> Response from XRAM to a put transaction" << std::endl;
+}
+#endif
+                }
+                else                     // get transaction
+                {
+          r_ixr_rsp_fsm = IXR_RSP_TRT_READ;
+
+#if DEBUG_MEMC_IXR_RSP
+if( m_debug_ixr_rsp_fsm )
+{
+    std::cout << "  <MEMC " << name() << ".IXR_RSP_IDLE> Response from XRAM to a get transaction" << std::endl;
+}
+#endif
+                }
+            }
+            break;
+        }
+        ////////////////////////
+        case IXR_RSP_ACK:        // Aknowledge the VCI response
+        {
+            if(p_vci_ixr.rspval.read()) r_ixr_rsp_fsm = IXR_RSP_TRT_ERASE;
+
+#if DEBUG_MEMC_IXR_RSP
+if( m_debug_ixr_rsp_fsm )
+{
+    std::cout << "  <MEMC " << name() << ".IXR_RSP_ACK>" << std::endl;
+}
+#endif
+            break;
+        }
+        ////////////////////////
+        case IXR_RSP_TRT_ERASE:   // erase the entry in the TRT
+        {
+            if ( r_alloc_trt_fsm.read() == ALLOC_TRT_IXR_RSP )
+            {
+                m_transaction_tab.erase(r_ixr_rsp_trt_index.read());
+                r_ixr_rsp_fsm = IXR_RSP_IDLE;
+
+#if DEBUG_MEMC_IXR_RSP
+if( m_debug_ixr_rsp_fsm )
+{
+    std::cout << "  <MEMC " << name() << ".IXR_RSP_TRT_ERASE> Erase TRT entry "
+              << r_ixr_rsp_trt_index.read() << std::endl;
+}
+#endif
+            }
+            break;
+        }
+        ///////////////////////
+        case IXR_RSP_TRT_READ:    // write data in the TRT
+        {
+            if ( (r_alloc_trt_fsm.read() == ALLOC_TRT_IXR_RSP) &&  p_vci_ixr.rspval )
+            {
+                size_t index    = r_ixr_rsp_trt_index.read();
+                bool   eop    = p_vci_ixr.reop.read();
+                data_t data   = p_vci_ixr.rdata.read();
+                bool   error    = ((p_vci_ixr.rerror.read() & 0x1) == 1);
+                assert(((eop == (r_ixr_rsp_cpt.read() == (m_words-1))) || p_vci_ixr.rerror.read())
+                    and "Error in VCI_MEM_CACHE : invalid length for a response from XRAM");
+                m_transaction_tab.write_rsp(index,
+                                            r_ixr_rsp_cpt.read(),
+                                            data,
+                                            error);
+                r_ixr_rsp_cpt = r_ixr_rsp_cpt.read() + 1;
+                if ( eop )
+                {
+                    r_ixr_rsp_to_xram_rsp_rok[r_ixr_rsp_trt_index.read()]=true;
+                    r_ixr_rsp_fsm = IXR_RSP_IDLE;
+                }
+
+#if DEBUG_MEMC_IXR_RSP
+if( m_debug_ixr_rsp_fsm )
+{
+    std::cout << "  <MEMC " << name() << ".IXR_RSP_TRT_READ> Writing a word in TRT : "
+              << " index = " << std::dec << index
+              << " / word = " << r_ixr_rsp_cpt.read()
+              << " / data = " << std::hex << data << std::endl;
+}
+#endif
+            }
+            break;
+        }
+    } // end swich r_ixr_rsp_fsm
+
+    ////////////////////////////////////////////////////////////////////////////
+    //                XRAM_RSP FSM
+    ////////////////////////////////////////////////////////////////////////////
+    // The XRAM_RSP FSM handles the incoming cache lines from the XRAM.
+    // The cache line has been written in the TRT by the IXR_CMD_FSM.
+    // As the IXR_RSP FSM and the XRAM_RSP FSM are running in parallel,
+    // there is as many flip-flops r_ixr_rsp_to_xram_rsp_rok[i]
+    // as the number of entries in the TRT, that are handled with
+    // a round-robin priority...
+    //
+    // When a response is available, the corresponding TRT entry
+    // must be copied in a local buffer to be written in the cache.
+    // The FSM takes the lock protecting the TRT, and the lock protecting the DIR.
+    // It selects a cache slot and writes the line in the cache.
+    // If it was a read MISS, the XRAM_RSP FSM send a request to the TGT_RSP
+    // FSM to return the cache line to the registered processor.
+    // If there is no empty slot, a victim line is evicted, and
+    // invalidate requests are sent to the L1 caches containing copies.
+    // If this line is dirty, the XRAM_RSP FSM send a request to the IXR_CMD
+    // FSM to save the victim line to the XRAM, and register the write transaction
+    // in the TRT (using the entry previously used by the read transaction).
+    ///////////////////////////////////////////////////////////////////////////////
+
+    switch ( r_xram_rsp_fsm.read() )
+    {
+        ///////////////////
+        case XRAM_RSP_IDLE: // scan the XRAM responses to get the TRT index (round robin)
+        {
+            size_t ptr   = r_xram_rsp_trt_index.read();
+            size_t lines = m_transaction_tab_lines;
+            for( size_t i=0 ; i<lines ; i++)
+            {
+                size_t index=(i+ptr+1)%lines;
+                if ( r_ixr_rsp_to_xram_rsp_rok[index] )
+                {
+                    r_xram_rsp_trt_index             = index;
+                    r_ixr_rsp_to_xram_rsp_rok[index] = false;
+                    r_xram_rsp_fsm                   = XRAM_RSP_DIR_LOCK;
+
+#if DEBUG_MEMC_XRAM_RSP
+if( m_debug_xram_rsp_fsm )
+{
+    std::cout << "  <MEMC " << name() << ".XRAM_RSP_IDLE> Available cache line in TRT:"
+              << " index = " << std::dec << index << std::endl;
+}
+#endif
+                    break;
+                }
+            }
+            break;
+        }
+        ///////////////////////
+        case XRAM_RSP_DIR_LOCK:
+        // Takes the lock on the directory
+        // Takes the lock on TRT
+        // Copy the TRT entry in a local buffer
+        {
+            if (( r_alloc_dir_fsm.read() == ALLOC_DIR_XRAM_RSP ) &&
+                ( r_alloc_trt_fsm.read() == ALLOC_TRT_XRAM_RSP ))
+            {
+                // copy the TRT entry in the r_xram_rsp_trt_buf local buffer
+                size_t  index = r_xram_rsp_trt_index.read();
+
+                TransactionTabEntry trt_entry(m_transaction_tab.read(index));
+                r_xram_rsp_trt_buf.copy(trt_entry);  // TRT entry local buffer
+
+                r_xram_rsp_fsm = XRAM_RSP_TRT_COPY;
+
+#if DEBUG_MEMC_XRAM_RSP
+if( m_debug_xram_rsp_fsm )
+{
+    std::cout << "  <MEMC " << name() << ".XRAM_RSP_DIR_LOCK> Get access to directory" << std::endl;
+}
+#endif
+            }
+            break;
+        }
+        ///////////////////////
+        case XRAM_RSP_TRT_COPY:
+        // Select a victim cache line
+        {
+            if ( (r_alloc_trt_fsm.read() == ALLOC_TRT_XRAM_RSP) )
+            {
+                // selects & extracts a victim line from cache
+                size_t way = 0;
+                size_t set = m_y[(vci_addr_t)(r_xram_rsp_trt_buf.nline * m_words * 4)];
+
+                DirectoryEntry victim(m_cache_directory.select(set, way));
+
+                bool inval = (victim.count && victim.valid) ;
+
+                // copy the victim line in a local buffer
+                m_cache_data.read_line(way, set, r_xram_rsp_victim_data);
+
+                r_xram_rsp_victim_copy      = victim.owner.srcid;
+#if L1_MULTI_CACHE
+                r_xram_rsp_victim_copy_cache= victim.owner.cache_id;
+#endif
+                r_xram_rsp_victim_copy_inst = victim.owner.inst;
+                r_xram_rsp_victim_count     = victim.count;
+                r_xram_rsp_victim_ptr       = victim.ptr;
+                r_xram_rsp_victim_way       = way;
+                r_xram_rsp_victim_set       = set;
+                r_xram_rsp_victim_nline     = victim.tag*m_sets + set;
+                r_xram_rsp_victim_is_cnt    = victim.is_cnt;
+                r_xram_rsp_victim_inval     = inval ;
+                r_xram_rsp_victim_dirty     = victim.dirty;
+
+                if(!r_xram_rsp_trt_buf.rerror)
+                {
+                  r_xram_rsp_fsm = XRAM_RSP_INVAL_LOCK;
+                }
+                else
+                {
+                  r_xram_rsp_fsm = XRAM_RSP_ERROR_ERASE;
+                }
+
+#if DEBUG_MEMC_XRAM_RSP
+if( m_debug_xram_rsp_fsm )
+{
+    std::cout << "  <MEMC " << name() << ".XRAM_RSP_TRT_COPY> Select a slot: "
+              << " way = " << std::dec << way
+              << " / set = " << set
+              << " / inval_required = " << inval << std::endl;
+}
+#endif
+            }
+            else
+            {
+                std::cout << "VCI_MEM_CACHE ERROR "     << name()
+                          << " XRAM_RSP_TRT_COPY state" << std::endl
+                          << "bad TRT allocation"       << std::endl;
+
+                exit(0);
+            }
+            break;
+        }
+        /////////////////////////
+        case XRAM_RSP_INVAL_LOCK: // check a possible pending inval
+        {
+            if ( r_alloc_upt_fsm == ALLOC_UPT_XRAM_RSP )
+            {
+                size_t index;
+                if (m_update_tab.search_inval(r_xram_rsp_trt_buf.nline, index))
+                {
+                    r_xram_rsp_fsm = XRAM_RSP_INVAL_WAIT;
+
+#if DEBUG_MEMC_XRAM_RSP
+if( m_debug_xram_rsp_fsm )
+{
+    std::cout << "  <MEMC " << name() << ".XRAM_RSP_INVAL_LOCK> Get acces to UPT,"
+              << " but an invalidation is already registered at this address" << std::endl;
+    m_update_tab.print();
+}
+#endif
+
+                }
+              else if (m_update_tab.is_full() && r_xram_rsp_victim_inval.read())
+                {
+                  r_xram_rsp_fsm = XRAM_RSP_INVAL_WAIT;
+
+#if DEBUG_MEMC_XRAM_RSP
+if( m_debug_xram_rsp_fsm )
+{
+    std::cout << "  <MEMC " << name() << ".XRAM_RSP_INVAL_LOCK> Get acces to UPT,"
+              << " but the table is full" << std::endl;
+    m_update_tab.print();
+}
+#endif
+              }
+                else
+                {
+                    r_xram_rsp_fsm = XRAM_RSP_DIR_UPDT;
+
+#if DEBUG_MEMC_XRAM_RSP
+if( m_debug_xram_rsp_fsm )
+{
+    std::cout << "  <MEMC " << name() << ".XRAM_RSP_INVAL_LOCK> Get acces to UPT" << std::endl;
+}
+#endif
+                }
+            }
+            break;
+        }
+        /////////////////////////
+        case XRAM_RSP_INVAL_WAIT: // returns to DIR_LOCK to retry
+        {
+            r_xram_rsp_fsm = XRAM_RSP_DIR_LOCK;
+            break;
+        }
+        ///////////////////////
+        case XRAM_RSP_DIR_UPDT:   // updates the cache (both data & directory)
+                                        // and possibly set an inval request in UPT
+        {
+            // signals generation
+            // check if this is an instruction read, this means pktid is either
+            // TYPE_READ_INS_UNC   0bX010 with TSAR encoding
+            // TYPE_READ_INS_MISS  0bX011 with TSAR encoding
+            bool inst_read = (r_xram_rsp_trt_buf.pktid & 0x2) && r_xram_rsp_trt_buf.proc_read;
+            // check if this is a cached read, this means pktid is either
+            // TYPE_READ_DATA_MISS 0bX001 with TSAR encoding
+            // TYPE_READ_INS_MISS  0bX011 with TSAR encoding
+            bool cached_read = (r_xram_rsp_trt_buf.pktid & 0x1) && r_xram_rsp_trt_buf.proc_read;
+
+            // update data
+            size_t set   = r_xram_rsp_victim_set.read();
+            size_t way   = r_xram_rsp_victim_way.read();
+            for(size_t word=0; word<m_words ; word++)
+            {
+                m_cache_data.write(way, set, word, r_xram_rsp_trt_buf.wdata[word]);
+
+                if ( m_monitor_ok )
+                {
+                    vci_addr_t address = r_xram_rsp_trt_buf.nline<<6 | word<<2;
+                    check_monitor("XRAM_RSP_DIR_UPDT", address, r_xram_rsp_trt_buf.wdata[word]);
+                }
+            }
+            // compute dirty
+            bool dirty = false;
+            for(size_t i=0; i<m_words;i++) dirty = dirty || (r_xram_rsp_trt_buf.wdata_be[i] != 0);
+            // update directory
+            DirectoryEntry entry;
+            entry.valid   = true;
+            entry.is_cnt  = false;
+            entry.lock    = false;
+            entry.dirty   = dirty;
+            entry.tag     = r_xram_rsp_trt_buf.nline / m_sets;
+            entry.ptr     = 0;
+            if(cached_read)
+            {
+                entry.owner.srcid   = r_xram_rsp_trt_buf.srcid;
+#if L1_MULTI_CACHE
+                entry.owner.cache_id= r_xram_rsp_trt_buf.pktid;
+#endif
+                entry.owner.inst    = inst_read;
+                entry.count         = 1;
+            }
+            else
+            {
+                entry.owner.srcid    = 0;
+#if L1_MULTI_CACHE
+                entry.owner.cache_id = 0;
+#endif
+                entry.owner.inst     = 0;
+                entry.count          = 0;
+            }
+            m_cache_directory.write(set, way, entry);
+
+            if (r_xram_rsp_victim_inval.read())
+            {
+                bool   brdcast    = r_xram_rsp_victim_is_cnt.read();
+                size_t index    = 0;
+                size_t count_copies   = r_xram_rsp_victim_count.read();
+
+                bool   wok = m_update_tab.set(  false,    // it's an inval transaction
+                        brdcast,  // set brdcast bit
+                        false,    // it does not need a response
+                        0,    // srcid
+                        0,    // trdid
+                        0,    // pktid
+                        r_xram_rsp_victim_nline.read(),
+                        count_copies,
+                        index);
+                r_xram_rsp_upt_index = index;
+
+                if (!wok)
+                {
+                    std::cout << "VCI_MEM_CACHE ERROR " << name() << " XRAM_RSP_HEAP_LAST state" << std::endl;
+                    std::cout << "an update_tab entry was free but write is unsuccessful" << std::endl;
+                    exit(0);
+                }
+            }
+
+#if DEBUG_MEMC_XRAM_RSP
+if( m_debug_xram_rsp_fsm )
+{
+    std::cout << "  <MEMC " << name() << ".XRAM_RSP_DIR_UPDT> Directory update: "
+              << " way = " << std::dec << way
+              << " / set = " << set
+              << " / count = " << entry.count
+              << " / is_cnt = " << entry.is_cnt << std::endl;
+    if (r_xram_rsp_victim_inval.read())
+    std::cout << "                           Invalidation request for victim line "
+              << std::hex << r_xram_rsp_victim_nline.read()
+              << " / broadcast = " << r_xram_rsp_victim_is_cnt.read() << std::endl;
+}
+#endif
+
+            // If the victim is not dirty, we don't need another XRAM  put transaction,
+            // and we canwe erase the TRT entry
+            if (!r_xram_rsp_victim_dirty.read())  m_transaction_tab.erase(r_xram_rsp_trt_index.read());
+
+            // Next state
+            if      ( r_xram_rsp_victim_dirty.read())       r_xram_rsp_fsm = XRAM_RSP_TRT_DIRTY;
+            else if ( r_xram_rsp_trt_buf.proc_read  )       r_xram_rsp_fsm = XRAM_RSP_DIR_RSP;
+            else if ( r_xram_rsp_victim_inval.read())       r_xram_rsp_fsm = XRAM_RSP_INVAL;
+            else                                            r_xram_rsp_fsm = XRAM_RSP_IDLE;
+            break;
+        }
+        ////////////////////////
+        case XRAM_RSP_TRT_DIRTY:  // set the TRT entry (write to XRAM) if the victim is dirty
+        {
+            if ( r_alloc_trt_fsm.read() == ALLOC_TRT_XRAM_RSP )
+            {
+                m_transaction_tab.set( r_xram_rsp_trt_index.read(),
+                                       false,       // write to XRAM
+                                       r_xram_rsp_victim_nline.read(),  // line index
+                                       0,
+                                       0,
+                                       0,
+                                       false,
+                                       0,
+                                       0,
+                                       std::vector<be_t>(m_words,0),
+                                       std::vector<data_t>(m_words,0) );
+
+#if DEBUG_MEMC_XRAM_RSP
+if( m_debug_xram_rsp_fsm )
+{
+    std::cout << "  <MEMC " << name() << ".XRAM_RSP_TRT_DIRTY> Set TRT entry for the put transaction:"
+        << " dirty victim line = " << r_xram_rsp_victim_nline.read() << std::endl;
+}
+#endif
+                if      ( r_xram_rsp_trt_buf.proc_read  )       r_xram_rsp_fsm = XRAM_RSP_DIR_RSP;
+                else if ( r_xram_rsp_victim_inval.read())       r_xram_rsp_fsm = XRAM_RSP_INVAL;
+                else                                            r_xram_rsp_fsm = XRAM_RSP_WRITE_DIRTY;
+            }
+            break;
+        }
+        //////////////////////
+        case XRAM_RSP_DIR_RSP:     // Request a response to TGT_RSP FSM
+        {
+            if ( !r_xram_rsp_to_tgt_rsp_req.read() )
+            {
+                r_xram_rsp_to_tgt_rsp_srcid = r_xram_rsp_trt_buf.srcid;
+                r_xram_rsp_to_tgt_rsp_trdid = r_xram_rsp_trt_buf.trdid;
+                r_xram_rsp_to_tgt_rsp_pktid = r_xram_rsp_trt_buf.pktid;
+                for (size_t i=0; i < m_words; i++) r_xram_rsp_to_tgt_rsp_data[i] = r_xram_rsp_trt_buf.wdata[i];
+                r_xram_rsp_to_tgt_rsp_word   = r_xram_rsp_trt_buf.word_index;
+                r_xram_rsp_to_tgt_rsp_length = r_xram_rsp_trt_buf.read_length;
+                r_xram_rsp_to_tgt_rsp_ll_key = r_xram_rsp_trt_buf.ll_key;
+                r_xram_rsp_to_tgt_rsp_rerror = false;
+                r_xram_rsp_to_tgt_rsp_req    = true;
+
+                if      ( r_xram_rsp_victim_inval ) r_xram_rsp_fsm = XRAM_RSP_INVAL;
+                else if ( r_xram_rsp_victim_dirty ) r_xram_rsp_fsm = XRAM_RSP_WRITE_DIRTY;
+                else                                r_xram_rsp_fsm = XRAM_RSP_IDLE;
+
+
+#if DEBUG_MEMC_XRAM_RSP
+if( m_debug_xram_rsp_fsm )
+{
+    std::cout << "  <MEMC " << name() << ".XRAM_RSP_DIR_RSP> Request the TGT_RSP FSM to return data:"
+              << " rsrcid = " << std::dec << r_xram_rsp_trt_buf.srcid
+              << " / address = " << std::hex << r_xram_rsp_trt_buf.nline*m_words*4
+              << " / nwords = " << std::dec << r_xram_rsp_trt_buf.read_length << std::endl;
+}
+#endif
+            }
+            break;
+        }
+        ////////////////////
+        case XRAM_RSP_INVAL:  // send invalidate request to INIT_CMD FSM
+        {
+            if(   !r_xram_rsp_to_init_cmd_multi_req.read() &&
+                  !r_xram_rsp_to_init_cmd_brdcast_req.read() )
+            {
+                bool multi_req = !r_xram_rsp_victim_is_cnt.read();
+                bool last_multi_req  = multi_req && (r_xram_rsp_victim_count.read() == 1);
+                bool not_last_multi_req = multi_req && (r_xram_rsp_victim_count.read() != 1);
+
+                r_xram_rsp_to_init_cmd_multi_req    = last_multi_req;
+                r_xram_rsp_to_init_cmd_brdcast_req  = r_xram_rsp_victim_is_cnt.read();
+                r_xram_rsp_to_init_cmd_nline        = r_xram_rsp_victim_nline.read();
+                r_xram_rsp_to_init_cmd_trdid        = r_xram_rsp_upt_index;
+                xram_rsp_to_init_cmd_fifo_srcid     = r_xram_rsp_victim_copy.read();
+                xram_rsp_to_init_cmd_fifo_inst      = r_xram_rsp_victim_copy_inst.read();
+#if L1_MULTI_CACHE
+                xram_rsp_to_init_cmd_fifo_cache_id  = r_xram_rsp_victim_copy_cache.read();
+#endif
+                xram_rsp_to_init_cmd_fifo_put       = multi_req;
+                r_xram_rsp_next_ptr                 = r_xram_rsp_victim_ptr.read();
+
+                if ( r_xram_rsp_victim_dirty )  r_xram_rsp_fsm = XRAM_RSP_WRITE_DIRTY;
+                else if (not_last_multi_req)    r_xram_rsp_fsm = XRAM_RSP_HEAP_REQ;
+                else                            r_xram_rsp_fsm = XRAM_RSP_IDLE;
+
+#if DEBUG_MEMC_XRAM_RSP
+if( m_debug_xram_rsp_fsm )
+{
+    std::cout << "  <MEMC " << name() << ".XRAM_RSP_INVAL> Send an inval request to INIT_CMD FSM:"
+              << " victim line = " << r_xram_rsp_victim_nline.read() << std::endl;
+}
+#endif
+          }
+          break;
+        }
+        //////////////////////////
+        case XRAM_RSP_WRITE_DIRTY:  // send a write request to IXR_CMD FSM
+        {
+            if ( !r_xram_rsp_to_ixr_cmd_req.read() )
+            {
+                r_xram_rsp_to_ixr_cmd_req = true;
+                r_xram_rsp_to_ixr_cmd_nline = r_xram_rsp_victim_nline.read();
+                r_xram_rsp_to_ixr_cmd_trdid = r_xram_rsp_trt_index.read();
+                for(size_t i=0; i<m_words ; i++) r_xram_rsp_to_ixr_cmd_data[i] = r_xram_rsp_victim_data[i];
+                m_cpt_write_dirty++;
+
+                bool multi_req = !r_xram_rsp_victim_is_cnt.read() && r_xram_rsp_victim_inval.read();
+                bool not_last_multi_req = multi_req && (r_xram_rsp_victim_count.read() != 1);
+                if ( not_last_multi_req )   r_xram_rsp_fsm = XRAM_RSP_HEAP_REQ;
+                else                        r_xram_rsp_fsm = XRAM_RSP_IDLE;
+
+#if DEBUG_MEMC_XRAM_RSP
+if( m_debug_xram_rsp_fsm )
+{
+    std::cout << "  <MEMC " << name() << ".XRAM_RSP_WRITE_DIRTY> Send the put request to IXR_CMD FSM:"
+              << " victim line = " << r_xram_rsp_victim_nline.read() << std::endl;
+}
+#endif
+            }
+            break;
+        }
+
+        /////////////////////////
+        case XRAM_RSP_HEAP_REQ:
+        // Get the lock to the HEAP directory
+        {
+          if( r_alloc_heap_fsm.read() == ALLOC_HEAP_XRAM_RSP )
+          {
+            r_xram_rsp_fsm = XRAM_RSP_HEAP_ERASE;
+          }
+
+#if DEBUG_MEMC_XRAM_RSP
+          if( m_debug_xram_rsp_fsm )
+          {
+            std::cout 
+              << "  <MEMC " << name() << ".XRAM_RSP_HEAP_REQ> Requesting HEAP lock "
+              << std::endl;
+          }
+#endif
+          break;
+        }
+
+        /////////////////////////
+        case XRAM_RSP_HEAP_ERASE: // erase the list of copies and sent invalidations
+        {
+            if( r_alloc_heap_fsm.read() == ALLOC_HEAP_XRAM_RSP )
+            {
+                HeapEntry entry = m_heap.read(r_xram_rsp_next_ptr.read());
+
+                xram_rsp_to_init_cmd_fifo_srcid    = entry.owner.srcid;
+#if L1_MULTI_CACHE
+                xram_rsp_to_init_cmd_fifo_cache_id = entry.owner.cache_id;
+#endif
+                xram_rsp_to_init_cmd_fifo_inst  = entry.owner.inst;
+                xram_rsp_to_init_cmd_fifo_put   = true;
+                if( m_xram_rsp_to_init_cmd_inst_fifo.wok() )
+                {
+                    r_xram_rsp_next_ptr = entry.next;
+                    if( entry.next == r_xram_rsp_next_ptr.read() ) // last copy
+                    {
+                        r_xram_rsp_to_init_cmd_multi_req = true;
+                        r_xram_rsp_fsm = XRAM_RSP_HEAP_LAST;
+                    }
+                    else
+                    {
+                        r_xram_rsp_fsm = XRAM_RSP_HEAP_ERASE;
+                    }
+                }
+                else
+                {
+                    r_xram_rsp_fsm = XRAM_RSP_HEAP_ERASE;
+                }
+
+#if DEBUG_MEMC_XRAM_RSP
+if( m_debug_xram_rsp_fsm )
+{
+    std::cout << "  <MEMC " << name() << ".XRAM_RSP_HEAP_ERASE> Erase the list of copies:"
+              << " srcid = " << std::dec << entry.owner.srcid
+              << " / inst = " << std::dec << entry.owner.inst << std::endl;
+}
+#endif
+            }
+            break;
+        }
+        /////////////////////////
+        case XRAM_RSP_HEAP_LAST:  // last member of the list
+        {
+            if ( r_alloc_heap_fsm.read() != ALLOC_HEAP_XRAM_RSP )
+            {
+                std::cout << "VCI_MEM_CACHE ERROR " << name() << " XRAM_RSP_HEAP_LAST state" << std::endl;
+                std::cout << "bad HEAP allocation" << std::endl;
+                exit(0);
+            }
+            size_t free_pointer = m_heap.next_free_ptr();
+
+            HeapEntry last_entry;
+            last_entry.owner.srcid    = 0;
+#if L1_MULTI_CACHE
+            last_entry.owner.cache_id = 0;
+#endif
+            last_entry.owner.inst     = false;
+            if(m_heap.is_full())
+            {
+                last_entry.next     = r_xram_rsp_next_ptr.read();
+                m_heap.unset_full();
+            }
+            else
+            {
+                last_entry.next     = free_pointer;
+            }
+
+            m_heap.write_free_ptr(r_xram_rsp_victim_ptr.read());
+            m_heap.write(r_xram_rsp_next_ptr.read(),last_entry);
+
+            r_xram_rsp_fsm = XRAM_RSP_IDLE;
+
+#if DEBUG_MEMC_XRAM_RSP
+if( m_debug_xram_rsp_fsm )
+{
+    std::cout << "  <MEMC " << name() << ".XRAM_RSP_HEAP_LAST> Heap housekeeping" << std::endl;
+}
+#endif
+            break;
+        }
+        // ///////////////////////
+        case XRAM_RSP_ERROR_ERASE:  // erase TRT entry in case of error
+        {
+            m_transaction_tab.erase(r_xram_rsp_trt_index.read());
+
+            // Next state
+            if ( r_xram_rsp_trt_buf.proc_read  ) r_xram_rsp_fsm = XRAM_RSP_ERROR_RSP;
+            else                                 r_xram_rsp_fsm = XRAM_RSP_IDLE;
+
+#if DEBUG_MEMC_XRAM_RSP
+if( m_debug_xram_rsp_fsm )
+{
+    std::cout << "  <MEMC " << name() << ".XRAM_RSP_ERROR_ERASE> Error reported by XRAM / erase the TRT entry" << std::endl;
+}
+#endif
+            break;
+        }
+        ////////////////////////
+        case XRAM_RSP_ERROR_RSP:     // Request an error response to TGT_RSP FSM
+        {
+            if ( !r_xram_rsp_to_tgt_rsp_req.read() )
+            {
+                r_xram_rsp_to_tgt_rsp_srcid  = r_xram_rsp_trt_buf.srcid;
+                r_xram_rsp_to_tgt_rsp_trdid  = r_xram_rsp_trt_buf.trdid;
+                r_xram_rsp_to_tgt_rsp_pktid  = r_xram_rsp_trt_buf.pktid;
+                for (size_t i=0; i < m_words; i++) r_xram_rsp_to_tgt_rsp_data[i] = r_xram_rsp_trt_buf.wdata[i];
+                r_xram_rsp_to_tgt_rsp_word   = r_xram_rsp_trt_buf.word_index;
+                r_xram_rsp_to_tgt_rsp_length = r_xram_rsp_trt_buf.read_length;
+                r_xram_rsp_to_tgt_rsp_rerror = true;
+                r_xram_rsp_to_tgt_rsp_req    = true;
+
+                r_xram_rsp_fsm = XRAM_RSP_IDLE;
+
+#if DEBUG_MEMC_XRAM_RSP
+if( m_debug_xram_rsp_fsm )
+{
+    std::cout << "  <MEMC " << name() << ".XRAM_RSP_ERROR_RSP> Request a response error to TGT_RSP FSM:"
+              << " srcid = " << std::dec << r_xram_rsp_trt_buf.srcid << std::endl;
+}
+#endif
+            }
+            break;
+        }
+    } // end swich r_xram_rsp_fsm
+
+    ////////////////////////////////////////////////////////////////////////////////////
+    //    CLEANUP FSM
+    ////////////////////////////////////////////////////////////////////////////////////
+    // The CLEANUP FSM handles the cleanup request from L1 caches.
+    // It accesses the cache directory and the heap to update the list of copies.
+    ////////////////////////////////////////////////////////////////////////////////////
+
+    switch ( r_cleanup_fsm.read() )
+    {
+      //////////////////
+      case CLEANUP_IDLE:
+      {
+        if ( p_vci_tgt_cleanup.cmdval.read() )
+        {
+          if (p_vci_tgt_cleanup.srcid.read() >= m_initiators )
+          {
+            std::cout << "VCI_MEM_CACHE ERROR " << name()
+              << " CLEANUP_IDLE state" << std::endl;
+            std::cout << "illegal srcid for  cleanup request" << std::endl;
+            exit(0);
+          }
+
+          bool reached = false;
+          for ( size_t index = 0 ; index < m_ncseg && !reached ; index++ )
+          {
+            if ( m_cseg[index]->contains((addr_t)(p_vci_tgt_cleanup.address.read())) )
+              reached = true;
+          }
+          // only write request to a mapped address that are not broadcast are handled
+          if (( p_vci_tgt_cleanup.cmd.read() == vci_param::CMD_WRITE ) &&
+              (( p_vci_tgt_cleanup.address.read() & 0x3 ) == 0 ) && reached )
+          {
+            addr_t line =(((addr_t) p_vci_tgt_cleanup.be.read() << (vci_param::B*8))) |
+              (((addr_t) p_vci_tgt_cleanup.wdata.read()));
+
+            r_cleanup_nline = line;
+            r_cleanup_srcid = p_vci_tgt_cleanup.srcid.read();
+            r_cleanup_trdid = p_vci_tgt_cleanup.trdid.read();
+            r_cleanup_pktid = p_vci_tgt_cleanup.pktid.read();
+            r_cleanup_fsm   = CLEANUP_DIR_REQ;
+
+  #if DEBUG_MEMC_CLEANUP
+            if( m_debug_cleanup_fsm )
+            {
+              std::cout << "  <MEMC " << name() << ".CLEANUP_IDLE> Cleanup request:" << std::hex
+                << " line addr = " << line * m_words * 4
+                << " / owner_id = " << p_vci_tgt_cleanup.srcid.read()
+                << " / owner_ins = " << (p_vci_tgt_cleanup.trdid.read()&0x1)
+                << std::endl;
+            }
+  #endif
+            m_cpt_cleanup++;
+          }
+        }
+        break;
+      }
+
+      //////////////////////
+      case CLEANUP_DIR_REQ:
+      // Get the lock to the directory
+      {
+        if ( r_alloc_dir_fsm.read() == ALLOC_DIR_CLEANUP )
+        {
+          r_cleanup_fsm = CLEANUP_DIR_LOCK;
+        }
+
+#if DEBUG_MEMC_CLEANUP
+        if( m_debug_cleanup_fsm )
+        {
+          std::cout 
+            << "  <MEMC " << name() << ".CLEANUP_DIR_REQ> Requesting DIR lock "
+            << std::endl;
+        }
+#endif
+        break;
+      }
+
+      //////////////////////
+      case CLEANUP_DIR_LOCK:  // test directory status
+      {
+        if ( r_alloc_dir_fsm.read() == ALLOC_DIR_CLEANUP )
+        {
+          // Read the directory
+          size_t way = 0;
+          addr_t cleanup_address = r_cleanup_nline.read() * m_words * 4;
+          DirectoryEntry entry   = m_cache_directory.read(cleanup_address , way);
+          r_cleanup_is_cnt       = entry.is_cnt;
+          r_cleanup_dirty        = entry.dirty;
+          r_cleanup_tag          = entry.tag;
+          r_cleanup_lock         = entry.lock;
+          r_cleanup_way          = way;
+          r_cleanup_copy         = entry.owner.srcid;
+#if L1_MULTI_CACHE
+          r_cleanup_copy_cache   = entry.owner.cache_id;
+#endif
+          r_cleanup_copy_inst    = entry.owner.inst;
+          r_cleanup_count        = entry.count;
+          r_cleanup_ptr          = entry.ptr;
+
+          if( entry.valid) //  hit : the copy must be cleared
+          {
+            if ( (entry.count==1) || (entry.is_cnt) )  // no access to the heap
+            {
+              r_cleanup_fsm = CLEANUP_DIR_WRITE;
+            }
+            else          // access to the heap
+            {
+              r_cleanup_fsm = CLEANUP_HEAP_REQ;
+            }
+          }
+          else    // miss : we must check the update table
+          {
+            r_cleanup_fsm = CLEANUP_UPT_LOCK;
+          }
+
+#if DEBUG_MEMC_CLEANUP
+          if( m_debug_cleanup_fsm )
+          {
+            std::cout
+              << "  <MEMC " << name()
+              << ".CLEANUP_DIR_LOCK> Test directory status: " << std::hex
+              << " line = " << r_cleanup_nline.read() * m_words * 4
+              << " / hit = " << entry.valid
+              << " / dir_id = " << entry.owner.srcid
+              << " / dir_ins = " << entry.owner.inst
+              << " / search_id = " << r_cleanup_srcid.read()
+              << " / search_ins = " << (r_cleanup_trdid.read()&0x1)
+              << " / count = " << entry.count
+              << " / is_cnt = " << entry.is_cnt << std::endl;
+          }
+#endif
+        }
+        else
+        {
+          std::cout << "VCI_MEM_CACHE ERROR " << name()
+            << " CLEANUP_DIR_LOCK state"
+            << " bad DIR allocation" << std::endl;
+
+          exit(0);
+        }
+        break;
+      }
+
+      ///////////////////////
+      case CLEANUP_DIR_WRITE:
+      // Update the directory entry without heap access
+      {
+        if ( r_alloc_dir_fsm.read() != ALLOC_DIR_CLEANUP )
+        {
+          std::cout << "VCI_MEM_CACHE ERROR " << name()
+            << " CLEANUP_DIR_WRITE state"
+            << " bad DIR allocation" << std::endl;
+          exit(0);
+        }
+
+        size_t way         = r_cleanup_way.read();
+        size_t set         = m_y[(vci_addr_t)(r_cleanup_nline.read()*m_words*4)];
+        bool cleanup_inst  = r_cleanup_trdid.read() & 0x1;
+        bool match_srcid   = ((r_cleanup_copy.read() == r_cleanup_srcid.read())
+#if L1_MULTI_CACHE
+            and (r_cleanup_copy_cache.read() == r_cleanup_pktid.read())
+#endif
+            );
+        bool match_inst    = (r_cleanup_copy_inst.read()  == cleanup_inst);
+        bool match         = match_srcid && match_inst;
+
+        if (not r_cleanup_is_cnt.read() and not match) {
+            std::cout
+              << "VCI_MEM_CACHE ERROR : Cleanup request on a valid"
+              << "entry using linked list mode with no corresponding"
+              << "directory or heap entry"
+              << std::endl;
+
+            exit(1);
+        }
+
+        // update the cache directory (for the copies)
+        DirectoryEntry entry;
+        entry.valid       = true;
+        entry.is_cnt      = r_cleanup_is_cnt.read();
+        entry.dirty       = r_cleanup_dirty.read();
+        entry.tag         = r_cleanup_tag.read();
+        entry.lock        = r_cleanup_lock.read();
+        entry.ptr         = r_cleanup_ptr.read();
+        entry.count       = r_cleanup_count.read() - 1;
+        entry.owner.srcid = 0;
+        entry.owner.inst  = 0;
+#if L1_MULTI_CACHE
+        entry.owner.cache_id = 0;
+#endif
+
+        m_cache_directory.write(set, way, entry);
+
+        r_cleanup_fsm = CLEANUP_RSP;
+
+#if DEBUG_MEMC_CLEANUP
+        if( m_debug_cleanup_fsm )
+        {
+          std::cout
+            << "  <MEMC " << name()
+            << ".CLEANUP_DIR_WRITE> Update directory:" << std::hex
+            << " line = " << r_cleanup_nline.read() * m_words * 4
+            << " / dir_id = " << entry.owner.srcid
+            << " / dir_ins = " << entry.owner.inst
+            << " / count = " << entry.count
+            << " / is_cnt = " << entry.is_cnt << std::endl;
+        }
+#endif
+
+        break;
+      }
+      
+      ///////////////////////
+      case CLEANUP_HEAP_REQ:
+      // Get the lock to the HEAP directory
+      {
+        if ( r_alloc_heap_fsm.read() == ALLOC_HEAP_CLEANUP )
+        {
+          r_cleanup_fsm = CLEANUP_HEAP_LOCK;
+        }
+
+#if DEBUG_MEMC_CLEANUP
+        if( m_debug_cleanup_fsm )
+        {
+          std::cout 
+            << "  <MEMC " << name() << ".CLEANUP_HEAP_REQ> Requesting HEAP lock "
+            << std::endl;
+        }
+#endif
+        break;
+      }
+
+      ///////////////////////
+      case CLEANUP_HEAP_LOCK:
+      // two cases are handled in this state:
+      // - the matching copy is directly in the directory
+      // - the matching copy is the first copy in the heap
+      {
+        if ( r_alloc_heap_fsm.read() == ALLOC_HEAP_CLEANUP )
+        {
+          size_t way              = r_cleanup_way.read();
+          size_t set              = m_y[(vci_addr_t)(r_cleanup_nline.read()*m_words*4)];
+          HeapEntry heap_entry    = m_heap.read(r_cleanup_ptr.read());
+          bool last               = (heap_entry.next == r_cleanup_ptr.read());
+          bool cleanup_inst       = r_cleanup_trdid.read() & 0x1;
+
+          // match_dir computation
+          bool match_dir_srcid    = (r_cleanup_copy.read() == r_cleanup_srcid.read());
+          bool match_dir_inst     = (r_cleanup_copy_inst.read()  == cleanup_inst);
+          bool match_dir          = match_dir_srcid and match_dir_inst;
+#if L1_MULTI_CACHE
+          match_dir = match_dir and (r_cleanup_copy_cache.read() == r_cleanup_pktid.read());
+#endif
+
+          // match_heap computation
+          bool match_heap_srcid   = (heap_entry.owner.srcid == r_cleanup_srcid.read());
+          bool match_heap_inst    = (heap_entry.owner.inst  == cleanup_inst);
+          bool match_heap         = match_heap_srcid and match_heap_inst;
+#if L1_MULTI_CACHE
+          match_heap = match_heap and (heap_entry.owner.cache_id == r_cleanup_pktid.read());
+#endif
+
+          r_cleanup_prev_ptr      = r_cleanup_ptr.read();
+          r_cleanup_prev_srcid    = heap_entry.owner.srcid;
+#if L1_MULTI_CACHE
+          r_cleanup_prev_cache_id = heap_entry.owner.cache_id;
+#endif
+          r_cleanup_prev_inst     = heap_entry.owner.inst;
+
+          if (match_dir)
+          // the matching copy is registered in the directory
+          {
+            // the copy registered in the directory must be replaced
+            // by the first copy registered in the heap
+            // and the corresponding entry must be freed
+            DirectoryEntry dir_entry;
+            dir_entry.valid          = true;
+            dir_entry.is_cnt         = r_cleanup_is_cnt.read();
+            dir_entry.dirty          = r_cleanup_dirty.read();
+            dir_entry.tag            = r_cleanup_tag.read();
+            dir_entry.lock           = r_cleanup_lock.read();
+            dir_entry.ptr            = heap_entry.next;
+            dir_entry.count          = r_cleanup_count.read()-1;
+            dir_entry.owner.srcid    = heap_entry.owner.srcid;
+#if L1_MULTI_CACHE
+            dir_entry.owner.cache_id = heap_entry.owner.cache_id;
+#endif
+            dir_entry.owner.inst     = heap_entry.owner.inst;
+
+            m_cache_directory.write(set,way,dir_entry);
+
+            r_cleanup_next_ptr       = r_cleanup_ptr.read();
+            r_cleanup_fsm            = CLEANUP_HEAP_FREE;
+          }
+          else if (match_heap)
+          // the matching copy is the first copy in the heap
+          {
+            // The first copy in heap must be freed
+            // and the copy registered in directory must point to the next copy in heap
+            DirectoryEntry dir_entry;
+            dir_entry.valid          = true;
+            dir_entry.is_cnt         = r_cleanup_is_cnt.read();
+            dir_entry.dirty          = r_cleanup_dirty.read();
+            dir_entry.tag            = r_cleanup_tag.read();
+            dir_entry.lock           = r_cleanup_lock.read();
+            dir_entry.ptr            = heap_entry.next;
+            dir_entry.count          = r_cleanup_count.read()-1;
+            dir_entry.owner.srcid    = r_cleanup_copy.read();
+#if L1_MULTI_CACHE
+            dir_entry.owner.cache_id = r_cleanup_copy_cache.read();
+#endif
+            dir_entry.owner.inst     = r_cleanup_copy_inst.read();
+
+            m_cache_directory.write(set,way,dir_entry);
+
+            r_cleanup_next_ptr       = r_cleanup_ptr.read();
+            r_cleanup_fsm            = CLEANUP_HEAP_FREE;
+          }
+          else if(!last)
+          // The matching copy is in the heap, but is not the first copy
+          {
+            // The directory entry must be modified to decrement count
+            DirectoryEntry  dir_entry;
+            dir_entry.valid          = true;
+            dir_entry.is_cnt         = r_cleanup_is_cnt.read();
+            dir_entry.dirty          = r_cleanup_dirty.read();
+            dir_entry.tag            = r_cleanup_tag.read();
+            dir_entry.lock           = r_cleanup_lock.read();
+            dir_entry.ptr            = r_cleanup_ptr.read();
+            dir_entry.count          = r_cleanup_count.read()-1;
+            dir_entry.owner.srcid    = r_cleanup_copy.read();
+#if L1_MULTI_CACHE
+            dir_entry.owner.cache_id = r_cleanup_copy_cache.read();
+#endif
+            dir_entry.owner.inst     = r_cleanup_copy_inst.read();
+
+            m_cache_directory.write(set,way,dir_entry);
+
+            r_cleanup_next_ptr       = heap_entry.next;
+            r_cleanup_fsm            = CLEANUP_HEAP_SEARCH;
+          }
+          else
+          {
+            std::cout << "VCI_MEM_CACHE ERROR " << name()
+              << " CLEANUP_HEAP_LOCK state"
+              << " hit but copy not found" << std::endl;
+            exit(0);
+          }
+
+#if DEBUG_MEMC_CLEANUP
+          if( m_debug_cleanup_fsm )
+          {
+            std::cout
+              << "  <MEMC " << name() << ".CLEANUP_HEAP_LOCK> Checks matching:"
+              << " line = " << r_cleanup_nline.read() * m_words * 4
+              << " / dir_id = " << r_cleanup_copy.read()
+              << " / dir_ins = " << r_cleanup_copy_inst.read()
+              << " / heap_id = " << heap_entry.owner.srcid
+              << " / heap_ins = " << heap_entry.owner.inst
+              << " / search_id = " << r_cleanup_srcid.read()
+              << " / search_ins = " << (r_cleanup_trdid.read()&0x1) << std::endl;
+          }
+#endif
+        }
+        else
+        {
+          std::cout << "VCI_MEM_CACHE ERROR " << name()
+            << " CLEANUP_HEAP_LOCK state"
+            << " bad HEAP allocation" << std::endl;
+
+          exit(0);
+        }
+        break;
+      }
+
+      /////////////////////////
+      case CLEANUP_HEAP_SEARCH:  // This state is handling the case where the copy
+      // is in the heap, but is not the first in the linked list
+      {
+        if ( r_alloc_heap_fsm.read() != ALLOC_HEAP_CLEANUP )
+        {
+          std::cout << "VCI_MEM_CACHE ERROR " << name()
+            << " CLEANUP_HEAP_SEARCH state"
+            << " bad HEAP allocation" << std::endl;
+          exit(0);
+        }
+
+        HeapEntry heap_entry  = m_heap.read(r_cleanup_next_ptr.read());
+        bool last             = (heap_entry.next == r_cleanup_next_ptr.read());
+        bool cleanup_inst     = r_cleanup_trdid.read() & 0x1;
+        bool match_heap_srcid = (heap_entry.owner.srcid == r_cleanup_srcid.read());
+        bool match_heap_inst  = (heap_entry.owner.inst  == cleanup_inst);
+        bool match_heap       = match_heap_srcid && match_heap_inst;
+#if L1_MULTI_CACHE
+        match_heap = match_heap and (heap_entry.owner.cache_id == r_cleanup_pktid.read());
+#endif
+
+#if DEBUG_MEMC_CLEANUP
+        if( m_debug_cleanup_fsm )
+        {
+          std::cout << "  <MEMC " << name() << ".CLEANUP_HEAP_SEARCH> Cheks matching:"
+            << " line = " << r_cleanup_nline.read() * m_words * 4
+            << " / heap_id = " << heap_entry.owner.srcid
+            << " / heap_ins = " << heap_entry.owner.inst
+            << " / search_id = " << r_cleanup_srcid.read()
+            << " / search_ins = " << (r_cleanup_trdid.read()&0x1)
+            << " / last = " << last << std::endl;
+        }
+#endif
+        if(match_heap) // the matching copy must be removed
+        {
+          r_cleanup_ptr = heap_entry.next; // reuse ressources
+          r_cleanup_fsm = CLEANUP_HEAP_CLEAN;
+        }
+        else
+        {
+          if ( last )
+          {
+            std::cout << "VCI_MEM_CACHE_ERROR " << name()
+              << " CLEANUP_HEAP_SEARCH state"
+              << " cleanup hit but copy not found" << std::endl;
+            exit(0);
+          }
+          else // test the next in the linked list
+          {
+            r_cleanup_prev_ptr      = r_cleanup_next_ptr.read();
+            r_cleanup_prev_srcid    = heap_entry.owner.srcid;
+#if L1_MULTI_CACHE
+            r_cleanup_prev_cache_id = heap_entry.owner.cache_id;
+#endif
+            r_cleanup_prev_inst     = heap_entry.owner.inst;
+            r_cleanup_next_ptr      = heap_entry.next;
+            r_cleanup_fsm           = CLEANUP_HEAP_SEARCH;
+
+#if DEBUG_MEMC_CLEANUP
+            if( m_debug_cleanup_fsm )
+            {
+              std::cout << "  <MEMC " << name() << ".CLEANUP_HEAP_SEARCH> Matching copy not found, search next:"
+                << " line = " << r_cleanup_nline.read() * m_words * 4
+                << " / heap_id = " << heap_entry.owner.srcid
+                << " / heap_ins = " << heap_entry.owner.inst
+                << " / search_id = " << r_cleanup_srcid.read()
+                << " / search_ins = " << (r_cleanup_trdid.read()&0x1) << std::endl;
+            }
+#endif
+          }
+        }
+        break;
+      }
+
+      ////////////////////////
+      case CLEANUP_HEAP_CLEAN:  // remove a copy in the linked list
+      {
+        if ( r_alloc_heap_fsm.read() != ALLOC_HEAP_CLEANUP )
+        {
+          std::cout << "VCI_MEM_CACHE ERROR " << name()
+            << " CLEANUP_HEAP_CLEAN state"
+            << "Bad HEAP allocation" << std::endl;
+          exit(0);
+        }
+
+        bool last = (r_cleanup_next_ptr.read() == r_cleanup_ptr.read());
+        HeapEntry heap_entry;
+        heap_entry.owner.srcid    = r_cleanup_prev_srcid.read();
+#if L1_MULTI_CACHE
+        heap_entry.owner.cache_id = r_cleanup_prev_cache_id.read();
+#endif
+        heap_entry.owner.inst     = r_cleanup_prev_inst.read();
+        
+        if(last) // this is the last entry of the list of copies
+        {
+          heap_entry.next     = r_cleanup_prev_ptr.read();
+        }
+        else  // this is not the last entry
+        {
+          heap_entry.next     = r_cleanup_ptr.read();
+        }
+
+        m_heap.write(r_cleanup_prev_ptr.read(),heap_entry);
+        r_cleanup_fsm = CLEANUP_HEAP_FREE;
+
+#if DEBUG_MEMC_CLEANUP
+        if( m_debug_cleanup_fsm )
+        {
+          std::cout << "  <MEMC " << name() << ".CLEANUP_HEAP_SEARCH> Remove the copy in the linked list" << std::endl;
+        }
+#endif
+        break;
+      }
+
+      ///////////////////////
+      case CLEANUP_HEAP_FREE:
+      // The heap entry pointed by r_cleanup_next_ptr is freed
+      // and becomes the head of the list of free entries
+      {
+        if ( r_alloc_heap_fsm.read() != ALLOC_HEAP_CLEANUP )
+        {
+          std::cout 
+            << "VCI_MEM_CACHE ERROR " << name()
+            << " CLEANUP_HEAP_CLEAN state" << std::endl
+            << "Bad HEAP allocation" << std::endl;
+
+          exit(0);
+        }
+
+        HeapEntry heap_entry;
+        heap_entry.owner.srcid    = 0;
+#if L1_MULTI_CACHE
+        heap_entry.owner.cache_id = 0;
+#endif
+        heap_entry.owner.inst     = false;
+
+        if(m_heap.is_full())
+        {
+          heap_entry.next = r_cleanup_next_ptr.read();
+        }
+        else
+        {
+          heap_entry.next = m_heap.next_free_ptr();
+        }
+
+        m_heap.write(r_cleanup_next_ptr.read(),heap_entry);
+        m_heap.write_free_ptr(r_cleanup_next_ptr.read());
+        m_heap.unset_full();
+
+        r_cleanup_fsm = CLEANUP_RSP;
+
+#if DEBUG_MEMC_CLEANUP
+        if( m_debug_cleanup_fsm )
+        {
+          std::cout << "  <MEMC " << name() << ".CLEANUP_HEAP_SEARCH> Update the list of free entries" << std::endl;
+        }
+#endif
+        break;
+      }
+
+      //////////////////////
+      case CLEANUP_UPT_LOCK:
+      {
+        if ( r_alloc_upt_fsm.read() == ALLOC_UPT_CLEANUP )
+        {
+          size_t index = 0;
+          bool hit_inval;
+          hit_inval = m_update_tab.search_inval(r_cleanup_nline.read(),index);
+
+          if ( !hit_inval ) // no pending inval
+          {
+
+#if DEBUG_MEMC_CLEANUP
+            if( m_debug_cleanup_fsm )
+            {
+              std::cout << "  <MEMC " << name() << ".CLEANUP_UPT_LOCK> Unexpected cleanup with no corresponding UPT entry:"
+                << " address = " << std::hex << (r_cleanup_nline.read()*4*m_words) << std::endl;
+            }
+#endif
+            r_cleanup_fsm = CLEANUP_RSP;
+          }
+          else    // pending inval
+          {
+            r_cleanup_write_srcid = m_update_tab.srcid(index);
+            r_cleanup_write_trdid = m_update_tab.trdid(index);
+            r_cleanup_write_pktid = m_update_tab.pktid(index);
+            r_cleanup_need_rsp    = m_update_tab.need_rsp(index);
+            r_cleanup_fsm = CLEANUP_UPT_WRITE;
+          }
+          r_cleanup_index.write(index) ;
+        }
+        break;
+      }
+
+      ///////////////////////
+      case CLEANUP_UPT_WRITE:  // decrement response counter
+      {
+        size_t count = 0;
+        m_update_tab.decrement(r_cleanup_index.read(), count);
+        if ( count == 0 )
+        {
+          m_update_tab.clear(r_cleanup_index.read());
+
+#if DEBUG_MEMC_CLEANUP
+          if( m_debug_cleanup_fsm )
+          {
+            std::cout << "  <MEMC " << name() << ".CLEANUP_UPT_WRITE> Decrement response counter in UPT:"
+              << " UPT_index = " << r_cleanup_index.read()
+              << " rsp_count = " << count << std::endl;
+          }
+#endif
+          if( r_cleanup_need_rsp.read() ) r_cleanup_fsm = CLEANUP_WRITE_RSP ;
+          else                      r_cleanup_fsm = CLEANUP_RSP;
+        }
+        else
+        {
+          r_cleanup_fsm = CLEANUP_RSP ;
+        }
+        break;
+      }
+
+      ///////////////////////
+      case CLEANUP_WRITE_RSP: // Response to a previous write on the direct network
+      {
+        if( !r_cleanup_to_tgt_rsp_req.read() )
+        {
+          r_cleanup_to_tgt_rsp_req     = true;
+          r_cleanup_to_tgt_rsp_srcid   = r_cleanup_write_srcid.read();
+          r_cleanup_to_tgt_rsp_trdid   = r_cleanup_write_trdid.read();
+          r_cleanup_to_tgt_rsp_pktid   = r_cleanup_write_pktid.read();
+          r_cleanup_fsm                = CLEANUP_RSP;
+
+#if DEBUG_MEMC_CLEANUP
+          if( m_debug_cleanup_fsm )
+          {
+            std::cout << "  <MEMC " << name() << ".CLEANUP_WRITE_RSP> Send a response to a cleanup request:"
+              << " rsrcid = " << std::dec << r_cleanup_write_srcid.read()
+              << " / rtrdid = " << std::dec << r_cleanup_write_trdid.read() << std::endl;
+          }
+#endif
+        }
+        break;
+      }
+
+      /////////////////
+      case CLEANUP_RSP: // Response to a cleanup on the coherence network
+      {
+        if ( p_vci_tgt_cleanup.rspack.read() )
+        {
+          r_cleanup_fsm = CLEANUP_IDLE;
+
+#if DEBUG_MEMC_CLEANUP
+          if( m_debug_cleanup_fsm )
+          {
+            std::cout << "  <MEMC " << name() << ".CLEANUP_RSP> Send the response to a cleanup request:"
+              << " rsrcid = " << std::dec << r_cleanup_write_srcid.read()
+              << " / rtrdid = " << r_cleanup_write_trdid.read() << std::endl;
+          }
+#endif
+        }
+        break;
+      }
+    } // end switch cleanup fsm
+
+    ////////////////////////////////////////////////////////////////////////////////////
+    //    CAS FSM
+    ////////////////////////////////////////////////////////////////////////////////////
+    // The CAS FSM handles the CAS (Store Conditionnal) atomic commands,
+    // that are handled as "compare-and-swap instructions.
+    //
+    // This command contains two or four flits:
+    // - In case of 32 bits atomic access, the first flit contains the value read
+    // by a previous LL instruction, the second flit contains the value to be writen.
+    // - In case of 64 bits atomic access, the 2 first flits contains the value read
+    // by a previous LL instruction, the 2 next flits contains the value to be writen.
+    //
+    // The target address is cachable. If it is replicated in other L1 caches
+    // than the writer, a coherence operation is done.
+    //
+    // It access the directory to check hit / miss.
+    // - In case of miss, the CAS FSM must register a GET transaction in TRT.
+    // If a read transaction to the XRAM for this line already exists,
+    // or if the transaction table is full, it goes to the WAIT state
+    // to release the locks and try again. When the GET transaction has been
+    // launched, it goes to the WAIT state and try again.
+    // The CAS request is not consumed in the FIFO until a HIT is obtained.
+    // - In case of hit...
+    ///////////////////////////////////////////////////////////////////////////////////
+
+    switch ( r_cas_fsm.read() )
+    {
+        /////////////
+        case CAS_IDLE:     // fill the local rdata buffers
+        {
+            if( m_cmd_cas_addr_fifo.rok() )
+            {
+
+#if DEBUG_MEMC_CAS
+if( m_debug_cas_fsm )
+{
+    std::cout << "  <MEMC " << name() << ".CAS_IDLE> CAS command: " << std::hex
+              << " srcid = " <<  std::dec << m_cmd_cas_srcid_fifo.read()
+              << " addr = " << std::hex << m_cmd_cas_addr_fifo.read()
+              << " wdata = " << m_cmd_cas_wdata_fifo.read()
+              << " eop = " << std::dec << m_cmd_cas_eop_fifo.read()
+              << " cpt  = " << std::dec << r_cas_cpt.read() << std::endl;
+}
+#endif
+                if( m_cmd_cas_eop_fifo.read() )
+                {
+                    m_cpt_cas++;
+                    r_cas_fsm = CAS_DIR_REQ;
+                }
+                else  // we keep the last word in the FIFO
+                {
+                    cmd_cas_fifo_get = true;
+                }
+                // We fill the two buffers
+                if ( r_cas_cpt.read() < 2 ) // 32 bits access
+                    r_cas_rdata[r_cas_cpt.read()] = m_cmd_cas_wdata_fifo.read();
+
+                if((r_cas_cpt.read() == 1) && m_cmd_cas_eop_fifo.read())
+                    r_cas_wdata = m_cmd_cas_wdata_fifo.read();
+
+                if( r_cas_cpt.read()>3 ) // more than 4 flits...
+                {
+                    std::cout << "VCI_MEM_CACHE ERROR in CAS_IDLE state : illegal CAS command"
+                              << std::endl;
+                    exit(0);
+                }
+
+                if ( r_cas_cpt.read()==2 )
+                    r_cas_wdata = m_cmd_cas_wdata_fifo.read();
+
+                r_cas_cpt = r_cas_cpt.read()+1;
+            }
+            break;
+        }
+        
+        /////////////////
+        case CAS_DIR_REQ:
+        {
+            if( r_alloc_dir_fsm.read() == ALLOC_DIR_CAS )
+            {
+              r_cas_fsm = CAS_DIR_LOCK;
+            }
+
+#if DEBUG_MEMC_CAS
+            if( m_debug_cas_fsm )
+            {
+              std::cout 
+                << "  <MEMC " << name() << ".CAS_DIR_REQ> Requesting DIR lock "
+                << std::endl;
+            }
+#endif
+            break;
+        }
+
+        /////////////////
+        case CAS_DIR_LOCK:  // Read the directory
+        {
+            if( r_alloc_dir_fsm.read() == ALLOC_DIR_CAS )
+            {
+                size_t way = 0;
+                DirectoryEntry entry(m_cache_directory.read(m_cmd_cas_addr_fifo.read(), way));
+
+                r_cas_is_cnt     = entry.is_cnt;
+                r_cas_dirty      = entry.dirty;
+                r_cas_tag        = entry.tag;
+                r_cas_way        = way;
+                r_cas_copy       = entry.owner.srcid;
+#if L1_MULTI_CACHE
+                r_cas_copy_cache = entry.owner.cache_id;
+#endif
+                r_cas_copy_inst  = entry.owner.inst;
+                r_cas_ptr        = entry.ptr;
+                r_cas_count      = entry.count;
+
+                if ( entry.valid ) r_cas_fsm = CAS_DIR_HIT_READ;
+                else               r_cas_fsm = CAS_MISS_TRT_LOCK;
+
+#if DEBUG_MEMC_CAS
+if( m_debug_cas_fsm )
+{
+    std::cout << "  <MEMC " << name() << ".CAS_DIR_LOCK> Directory acces"
+              << " / address = " << std::hex << m_cmd_cas_addr_fifo.read()
+              << " / hit = " << std::dec << entry.valid
+              << " / count = " << entry.count
+              << " / is_cnt = " << entry.is_cnt << std::endl;
+}
+#endif
+            }
+            else
+            {
+              std::cout
+                << "VCI_MEM_CACHE ERROR " << name()
+                << " CAS_DIR_LOCK state" << std::endl
+                << "Bad DIR allocation"   << std::endl;
+
+              exit(0);
+            }
+
+            break;
+        }
+        /////////////////////
+        case CAS_DIR_HIT_READ:  // update directory for lock and dirty bit
+                                // and check data change in cache
+        {
+            size_t way  = r_cas_way.read();
+            size_t set  = m_y[(vci_addr_t)(m_cmd_cas_addr_fifo.read())];
+
+            // update directory (lock & dirty bits)
+            DirectoryEntry entry;
+            entry.valid          = true;
+            entry.is_cnt         = r_cas_is_cnt.read();
+            entry.dirty          = true;
+            entry.lock           = true;
+            entry.tag            = r_cas_tag.read();
+            entry.owner.srcid    = r_cas_copy.read();
+#if L1_MULTI_CACHE
+            entry.owner.cache_id = r_cas_copy_cache.read();
+#endif
+            entry.owner.inst     = r_cas_copy_inst.read();
+            entry.count          = r_cas_count.read();
+            entry.ptr            = r_cas_ptr.read();
+
+            m_cache_directory.write(set, way, entry);
+
+            // Stored data from cache in buffer to do the comparison in next state
+            m_cache_data.read_line(way, set, r_cas_data);
+
+            r_cas_fsm = CAS_DIR_HIT_COMPARE;
+
+#if DEBUG_MEMC_CAS
+            if(m_debug_cas_fsm)
+            {
+                std::cout
+                    << "  <MEMC " << name() << ".CAS_DIR_HIT_READ> Read data from "
+                    << " cache and store it in buffer"
+                    << std::endl;
+            }
+#endif
+            break;
+        }
+
+        case CAS_DIR_HIT_COMPARE:
+        {
+            size_t word = m_x[(vci_addr_t)(m_cmd_cas_addr_fifo.read())];
+
+            // Read data in buffer & check data change
+            bool ok = (r_cas_rdata[0].read() == r_cas_data[word].read());
+
+            if(r_cas_cpt.read() == 4)     // 64 bits CAS
+                ok &= (r_cas_rdata[1] == r_cas_data[word+1]);
+
+            // to avoid livelock, force the atomic access to fail pseudo-randomly
+            bool forced_fail = ((r_cas_lfsr % (64) == 0) && RANDOMIZE_CAS);
+            r_cas_lfsr = (r_cas_lfsr >> 1) ^ ((- (r_cas_lfsr & 1)) & 0xd0000001);
+
+            // cas success
+            if(ok and not forced_fail)
+            {
+                r_cas_fsm = CAS_DIR_HIT_WRITE;
+            }
+            // cas failure
+            else
+            {
+                r_cas_fsm = CAS_RSP_FAIL;
+            }
+
+#if DEBUG_MEMC_CAS
+            if(m_debug_cas_fsm)
+            {
+                std::cout
+                    << "  <MEMC " << name() << ".CAS_DIR_HIT_COMPARE> Compare the old"
+                    << " and the new data"
+                    << " / expected value = " << r_cas_rdata[0].read()
+                    << " / actual value = "   << r_cas_data[word].read()
+                    << " / forced_fail = "    << forced_fail << std::endl;
+            }
+#endif
+            break;
+        }
+        //////////////////////
+        case CAS_DIR_HIT_WRITE:    // test if a CC transaction is required
+                                   // write data in cache if no CC request
+        {
+            // The CAS is a success => sw access to the llsc_global_table
+            m_llsc_table.sw(m_cmd_cas_addr_fifo.read());
+
+            // test coherence request
+            if(r_cas_count.read())   // replicated line
+            {
+                if ( r_cas_is_cnt.read() )
+                {
+                    r_cas_fsm = CAS_BC_TRT_LOCK;    // broadcast invalidate required
+                }
+                else if( !r_cas_to_init_cmd_multi_req.read() &&
+                         !r_cas_to_init_cmd_brdcast_req.read()  )
+                {
+                    r_cas_fsm = CAS_UPT_LOCK;     // multi update required
+                }
+                else
+                {
+                    r_cas_fsm = CAS_WAIT;
+                }
+            }
+            else                    // no copies
+            {
+                size_t way  = r_cas_way.read();
+                size_t set  = m_y[(vci_addr_t)(m_cmd_cas_addr_fifo.read())];
+                size_t word = m_x[(vci_addr_t)(m_cmd_cas_addr_fifo.read())];
+
+                // cache update
+                m_cache_data.write(way, set, word, r_cas_wdata.read());
+                if(r_cas_cpt.read()==4)
+                    m_cache_data.write(way, set, word+1, m_cmd_cas_wdata_fifo.read());
+
+                // monitor
+                if ( m_monitor_ok )
+                {
+                    vci_addr_t address = m_cmd_cas_addr_fifo.read();
+                char buf[80];
+                snprintf(buf, 80, "CAS_DIR_HIT_WRITE srcid %d", m_cmd_cas_srcid_fifo.read());
+                    check_monitor( buf, address, r_cas_wdata.read() );
+                    if ( r_cas_cpt.read()==4 )
+                    check_monitor( buf, address+4, m_cmd_cas_wdata_fifo.read() );
+                }
+                r_cas_fsm = CAS_RSP_SUCCESS;
+
+#if DEBUG_MEMC_CAS
+if( m_debug_cas_fsm )
+{
+    std::cout << "  <MEMC " << name() << ".CAS_DIR_HIT_WRITE> Update cache:"
+              << " way = " << std::dec << way
+              << " / set = " << set
+              << " / word = " << word
+              << " / value = " << r_cas_wdata.read()
+              << " / count = " << r_cas_count.read() << std::endl;
+    std::cout << "  <MEMC " << name() << ".CAS_DIR_HIT_WRITE> global_llsc_table SW access" << std::endl;
+}
+#endif
+            }
+            break;
+        }
+        /////////////////
+        case CAS_UPT_LOCK:  // try to register the transaction in UPT
+                           // and write data in cache if successful registration
+                           // releases locks to retry later if UPT full
+        {
+            if ( r_alloc_upt_fsm.read() == ALLOC_UPT_CAS )
+            {
+                bool        wok        = false;
+                size_t      index      = 0;
+                size_t      srcid      = m_cmd_cas_srcid_fifo.read();
+                size_t      trdid      = m_cmd_cas_trdid_fifo.read();
+                size_t      pktid      = m_cmd_cas_pktid_fifo.read();
+                addr_t      nline      = m_nline[(vci_addr_t)(m_cmd_cas_addr_fifo.read())];
+                size_t      nb_copies  = r_cas_count.read();
+
+                wok = m_update_tab.set(true,  // it's an update transaction
+                                       false,   // it's not a broadcast
+                                       true,    // it needs a response
+                                       srcid,
+                                       trdid,
+                                       pktid,
+                                       nline,
+                                       nb_copies,
+                                       index);
+                if (wok)  // coherence transaction registered in UPT
+                {
+                    // cache update
+                    size_t way  = r_cas_way.read();
+                    size_t set  = m_y[(vci_addr_t)(m_cmd_cas_addr_fifo.read())];
+                    size_t word = m_x[(vci_addr_t)(m_cmd_cas_addr_fifo.read())];
+
+                    m_cache_data.write(way, set, word, r_cas_wdata.read());
+                    if(r_cas_cpt.read()==4)
+                        m_cache_data.write(way, set, word+1, m_cmd_cas_wdata_fifo.read());
+
+                    // monitor
+                    if ( m_monitor_ok )
+                    {
+                        vci_addr_t address = m_cmd_cas_addr_fifo.read();
+                    char buf[80];
+                    snprintf(buf, 80, "CAS_DIR_HIT_WRITE srcid %d", m_cmd_cas_srcid_fifo.read());
+                        check_monitor( buf, address, r_cas_wdata.read() );
+                        if ( r_cas_cpt.read()==4 )
+                        check_monitor( buf, address+4, m_cmd_cas_wdata_fifo.read() );
+                    }
+
+                    r_cas_upt_index = index;
+                    r_cas_fsm = CAS_UPT_HEAP_LOCK;
+                }
+                else       //  releases the locks protecting UPT and DIR UPT full
+                {
+                    r_cas_fsm = CAS_WAIT;
+                }
+
+#if DEBUG_MEMC_CAS
+if( m_debug_cas_fsm )
+{
+    std::cout << "  <MEMC " << name() << ".CAS_UPT_LOCK> Register multi-update transaction in UPT"
+              << " / wok = " << wok
+              << " / nline  = " << std::hex << nline
+              << " / count = " << nb_copies << std::endl;
+}
+#endif
+            }
+            break;
+        }
+        /////////////
+        case CAS_WAIT:   // release all locks and retry from beginning
+        {
+
+#if DEBUG_MEMC_CAS
+if( m_debug_cas_fsm )
+{
+    std::cout << "  <MEMC " << name() << ".CAS_WAIT> Release all locks" << std::endl;
+}
+#endif
+            r_cas_fsm = CAS_DIR_REQ;
+            break;
+        }
+        //////////////////
+        case CAS_UPT_HEAP_LOCK:  // lock the heap
+        {
+            if( r_alloc_heap_fsm.read() == ALLOC_HEAP_CAS )
+            {
+
+#if DEBUG_MEMC_CAS
+if( m_debug_cas_fsm )
+{
+    std::cout << "  <MEMC " << name() << ".CAS_UPT_HEAP_LOCK> Get access to the heap" << std::endl;
+}
+#endif
+                r_cas_fsm = CAS_UPT_REQ;
+            }
+            break;
+        }
+        ////////////////
+        case CAS_UPT_REQ:  // send a first update request to INIT_CMD FSM
+        {
+            assert((r_alloc_heap_fsm.read() == ALLOC_HEAP_CAS) and
+                   "VCI_MEM_CACHE ERROR : bad HEAP allocation");
+
+            if( !r_cas_to_init_cmd_multi_req.read() && !r_cas_to_init_cmd_brdcast_req.read() )
+            {
+                r_cas_to_init_cmd_brdcast_req  = false;
+                r_cas_to_init_cmd_trdid        = r_cas_upt_index.read();
+                r_cas_to_init_cmd_nline        = m_nline[(vci_addr_t)(m_cmd_cas_addr_fifo.read())];
+                r_cas_to_init_cmd_index        = m_x[(vci_addr_t)(m_cmd_cas_addr_fifo.read())];
+                r_cas_to_init_cmd_wdata        = r_cas_wdata.read();
+
+                if(r_cas_cpt.read() == 4)
+                {
+                    r_cas_to_init_cmd_is_long    = true;
+                    r_cas_to_init_cmd_wdata_high = m_cmd_cas_wdata_fifo.read();
+                }
+                else
+                {
+                    r_cas_to_init_cmd_is_long    = false;
+                    r_cas_to_init_cmd_wdata_high = 0;
+                }
+
+                // We put the first copy in the fifo
+                cas_to_init_cmd_fifo_put     = true;
+                cas_to_init_cmd_fifo_inst    = r_cas_copy_inst.read();
+                cas_to_init_cmd_fifo_srcid   = r_cas_copy.read();
+#if L1_MULTI_CACHE
+                cas_to_init_cmd_fifo_cache_id= r_cas_copy_cache.read();
+#endif
+                if(r_cas_count.read() == 1) // one single copy
+                {
+                    r_cas_fsm = CAS_IDLE;   // Response will be sent after receiving
+                                            // update responses
+                    cmd_cas_fifo_get            = true;
+                    r_cas_to_init_cmd_multi_req = true;
+                    r_cas_cpt = 0;
+                }
+                else      // several copies
+                {
+                    r_cas_fsm = CAS_UPT_NEXT;
+                }
+
+#if DEBUG_MEMC_CAS
+if( m_debug_cas_fsm )
+{
+    std::cout << "  <MEMC " << name() << ".CAS_UPT_REQ> Send the first update request to INIT_CMD FSM "
+              << " / address = " << std::hex << m_cmd_cas_addr_fifo.read()
+              << " / wdata = " << std::hex << r_cas_wdata.read()
+              << " / srcid = " << std::dec << r_cas_copy.read()
+              << " / inst = " << std::dec << r_cas_copy_inst.read() << std::endl;
+}
+#endif
+            }
+            break;
+        }
+        /////////////////
+        case CAS_UPT_NEXT:     // send a multi-update request to INIT_CMD FSM
+        {
+            assert((r_alloc_heap_fsm.read() == ALLOC_HEAP_CAS)
+                 and "VCI_MEM_CACHE ERROR : bad HEAP allocation");
+
+            HeapEntry entry = m_heap.read(r_cas_ptr.read());
+            cas_to_init_cmd_fifo_srcid    = entry.owner.srcid;
+#if L1_MULTI_CACHE
+            cas_to_init_cmd_fifo_cache_id = entry.owner.cache_id;
+#endif
+            cas_to_init_cmd_fifo_inst     = entry.owner.inst;
+            cas_to_init_cmd_fifo_put = true;
+
+            if( m_cas_to_init_cmd_inst_fifo.wok() ) // request accepted by INIT_CMD FSM
+            {
+                r_cas_ptr = entry.next;
+                if( entry.next == r_cas_ptr.read() )  // last copy
+                {
+                    r_cas_to_init_cmd_multi_req = true;
+                    r_cas_fsm = CAS_IDLE;   // Response will be sent after receiving
+                                            // all update responses
+                    cmd_cas_fifo_get = true;
+                    r_cas_cpt        = 0;
+                }
+            }
+
+#if DEBUG_MEMC_CAS
+if( m_debug_cas_fsm )
+{
+    std::cout << "  <MEMC " << name() << ".CAS_UPT_NEXT> Send the next update request to INIT_CMD FSM "
+              << " / address = " << std::hex << m_cmd_cas_addr_fifo.read()
+              << " / wdata = " << std::hex << r_cas_wdata.read()
+              << " / srcid = " << std::dec << entry.owner.srcid
+              << " / inst = " << std::dec << entry.owner.inst << std::endl;
+}
+#endif
+            break;
+        }
+        /////////////////////
+        case CAS_BC_TRT_LOCK:      // check the TRT to register a PUT transaction
+        {
+            if( r_alloc_trt_fsm.read() == ALLOC_TRT_CAS )
+            {
+                if( !r_cas_to_ixr_cmd_req )  // we can transfer the request to IXR_CMD FSM
+                {
+                    // fill the data buffer
+                    size_t way  = r_cas_way.read();
+                    size_t set  = m_y[(vci_addr_t)(m_cmd_cas_addr_fifo.read())];
+                        size_t word = m_x[(vci_addr_t)(m_cmd_cas_addr_fifo.read())];
+                    for(size_t i = 0; i<m_words; i++)
+                    {
+                        if (i == word)
+                        {
+                            r_cas_to_ixr_cmd_data[i] = r_cas_wdata.read();
+                        }
+                        else if ( (i == word+1) && (r_cas_cpt.read()==4) ) // 64 bit CAS
+                        {
+                            r_cas_to_ixr_cmd_data[i] = m_cmd_cas_wdata_fifo.read();
+                        }
+                        else
+                        {
+                            r_cas_to_ixr_cmd_data[i] = m_cache_data.read(way, set, i);
+                        }
+                    }
+                    size_t wok_index = 0;
+                    bool   wok       = !m_transaction_tab.full(wok_index);
+                    if ( wok )
+                    {
+                        r_cas_trt_index = wok_index;
+                        r_cas_fsm       = CAS_BC_UPT_LOCK;
+                    }
+                    else
+                    {
+                        r_cas_fsm       = CAS_WAIT;
+                    }
+                }
+                else
+                {
+                    r_cas_fsm = CAS_WAIT;
+                }
+            }
+            break;
+        }
+        ///////////////////
+        case CAS_BC_UPT_LOCK:  // register a broadcast inval transaction in UPT
+                              // write data in cache in case of successful registration
+        {
+            if ( r_alloc_upt_fsm.read() == ALLOC_UPT_CAS )
+            {
+                bool        wok       = false;
+                size_t      index     = 0;
+                size_t      srcid     = m_cmd_cas_srcid_fifo.read();
+                size_t      trdid     = m_cmd_cas_trdid_fifo.read();
+                size_t      pktid     = m_cmd_cas_pktid_fifo.read();
+                addr_t      nline     = m_nline[(vci_addr_t)(m_cmd_cas_addr_fifo.read())];
+                size_t      nb_copies = r_cas_count.read();
+
+                // register a broadcast inval transaction in UPT
+                wok = m_update_tab.set(false, // it's an inval transaction
+                                       true,    // it's a broadcast
+                                       true,    // it needs a response
+                                       srcid,
+                                       trdid,
+                                       pktid,
+                                       nline,
+                                       nb_copies,
+                                       index);
+
+                if ( wok )  // UPT not full
+                {
+                    // cache update
+                    size_t way  = r_cas_way.read();
+                    size_t set  = m_y[(vci_addr_t)(m_cmd_cas_addr_fifo.read())];
+                    size_t word = m_x[(vci_addr_t)(m_cmd_cas_addr_fifo.read())];
+
+                    m_cache_data.write(way, set, word, r_cas_wdata.read());
+                    if(r_cas_cpt.read()==4)
+                        m_cache_data.write(way, set, word+1, m_cmd_cas_wdata_fifo.read());
+
+                    // monitor
+                    if ( m_monitor_ok )
+                    {
+                        vci_addr_t address = m_cmd_cas_addr_fifo.read();
+                    char buf[80];
+                    snprintf(buf, 80, "CAS_DIR_HIT_WRITE srcid %d", m_cmd_cas_srcid_fifo.read());
+                        check_monitor( buf, address, r_cas_wdata.read() );
+                        if ( r_cas_cpt.read()==4 )
+                        check_monitor( buf, address+4, m_cmd_cas_wdata_fifo.read() );
+                    }
+                    r_cas_upt_index = index;
+                    r_cas_fsm = CAS_BC_DIR_INVAL;
+#if DEBUG_MEMC_CAS
+if( m_debug_cas_fsm )
+{
+    std::cout << "  <MEMC " << name() << ".CAS_BC_UPT_LOCK> Register a broadcast inval transaction in UPT"
+              << " / nline = " << nline
+              << " / count = " << nb_copies
+              << " / upt_index = " << index << std::endl;
+}
+#endif
+                }
+                else      //  releases the lock protecting UPT
+                {
+                     r_cas_fsm = CAS_WAIT;
+                }
+            }
+            break;
+        }
+        //////////////////
+        case CAS_BC_DIR_INVAL:  // Register the PUT transaction in TRT, and inval the DIR entry
+        {
+            if ( (r_alloc_trt_fsm.read() == ALLOC_TRT_CAS ) &&
+                 (r_alloc_upt_fsm.read() == ALLOC_UPT_CAS ) &&
+                 (r_alloc_dir_fsm.read() == ALLOC_DIR_CAS ))
+            {
+                // set TRT
+                m_transaction_tab.set(r_cas_trt_index.read(),
+                                      false,    // PUT request to XRAM
+                                      m_nline[(vci_addr_t)(m_cmd_cas_addr_fifo.read())],
+                                      0,
+                                      0,
+                                      0,
+                                      false,    // not a processor read
+                                      0,
+                                      0,
+                                      std::vector<be_t>(m_words,0),
+                                      std::vector<data_t>(m_words,0));
+
+                // invalidate directory entry
+                DirectoryEntry entry;
+                entry.valid         = false;
+                entry.dirty         = false;
+                entry.tag         = 0;
+                entry.is_cnt        = false;
+                entry.lock          = false;
+                entry.count         = 0;
+                entry.owner.srcid   = 0;
+#if L1_MULTI_CACHE
+                entry.owner.cache_id= 0;
+#endif
+                entry.owner.inst    = false;
+                entry.ptr           = 0;
+                size_t set          = m_y[(vci_addr_t)(m_cmd_cas_addr_fifo.read())];
+                size_t way          = r_cas_way.read();
+                m_cache_directory.write(set, way, entry);
+
+                r_cas_fsm = CAS_BC_CC_SEND;
+
+#if DEBUG_MEMC_CAS
+if( m_debug_cas_fsm )
+{
+    std::cout << "  <MEMC " << name() << ".CAS_BC_DIR_INVAL> Register the PUT in TRT and invalidate DIR entry"
+              << " / nline = " << std::hex << m_nline[(vci_addr_t)(m_cmd_cas_addr_fifo.read())]
+              << " / set = " << std::dec << set << " / way = " << way << std::endl;
+}
+#endif
+            }
+            else
+            {
+                assert(false and "LOCK ERROR in CAS_FSM, STATE = CAS_BC_DIR_INVAL");
+            }
+            break;
+        }
+        ///////////////////
+        case CAS_BC_CC_SEND:  // Request the broadcast inval to INIT_CMD FSM
+        {
+            if ( !r_cas_to_init_cmd_multi_req.read() &&
+                 !r_cas_to_init_cmd_brdcast_req.read())
+            {
+                r_cas_to_init_cmd_multi_req    = false;
+                r_cas_to_init_cmd_brdcast_req  = true;
+                r_cas_to_init_cmd_trdid        = r_cas_upt_index.read();
+                r_cas_to_init_cmd_nline        = m_nline[(vci_addr_t)(m_cmd_cas_addr_fifo.read())];
+                r_cas_to_init_cmd_index        = 0;
+                r_cas_to_init_cmd_wdata        = 0;
+
+                r_cas_fsm = CAS_BC_XRAM_REQ;
+            }
+            break;
+        }
+        ////////////////////
+        case CAS_BC_XRAM_REQ: // request the IXR FSM to start a put transaction
+        {
+            if ( !r_cas_to_ixr_cmd_req )
+            {
+                r_cas_to_ixr_cmd_req     = true;
+                r_cas_to_ixr_cmd_write   = true;
+                r_cas_to_ixr_cmd_nline   = m_nline[(vci_addr_t)(m_cmd_cas_addr_fifo.read())];
+                r_cas_to_ixr_cmd_trdid   = r_cas_trt_index.read();
+                r_cas_fsm                = CAS_IDLE;
+                cmd_cas_fifo_get         = true;
+                r_cas_cpt                = 0;
+
+#if DEBUG_MEMC_CAS
+if( m_debug_cas_fsm )
+{
+    std::cout << "  <MEMC " << name() << ".CAS_BC_XRAM_REQ> Request a PUT transaction to IXR_CMD FSM" << std::hex
+              << " / nline = " << m_nline[(vci_addr_t)m_cmd_cas_addr_fifo.read()]
+              << " / trt_index = " << r_cas_trt_index.read() << std::endl;
+}
+#endif
+            }
+            else
+            {
+               std::cout << "MEM_CACHE, CAS_BC_XRAM_REQ state : request should not have been previously set"
+                         << std::endl;
+            }
+            break;
+        }
+        /////////////////
+        case CAS_RSP_FAIL:  // request TGT_RSP FSM to send a failure response
+        {
+            if( !r_cas_to_tgt_rsp_req )
+            {
+                cmd_cas_fifo_get     = true;
+                r_cas_cpt              = 0;
+                r_cas_to_tgt_rsp_req = true;
+                r_cas_to_tgt_rsp_data  = 1;
+                r_cas_to_tgt_rsp_srcid = m_cmd_cas_srcid_fifo.read();
+                r_cas_to_tgt_rsp_trdid = m_cmd_cas_trdid_fifo.read();
+                r_cas_to_tgt_rsp_pktid = m_cmd_cas_pktid_fifo.read();
+                r_cas_fsm              = CAS_IDLE;
+
+#if DEBUG_MEMC_CAS
+if( m_debug_cas_fsm )
+{
+    std::cout << "  <MEMC " << name() << ".CAS_RSP_FAIL> Request TGT_RSP to send a failure response" << std::endl;
+}
+#endif
+            }
+            break;
+        }
+        ////////////////////
+        case CAS_RSP_SUCCESS:  // request TGT_RSP FSM to send a success response
+        {
+            if( !r_cas_to_tgt_rsp_req )
+            {
+                cmd_cas_fifo_get       = true;
+                r_cas_cpt              = 0;
+                r_cas_to_tgt_rsp_req = true;
+                r_cas_to_tgt_rsp_data  = 0;
+                r_cas_to_tgt_rsp_srcid = m_cmd_cas_srcid_fifo.read();
+                r_cas_to_tgt_rsp_trdid = m_cmd_cas_trdid_fifo.read();
+                r_cas_to_tgt_rsp_pktid = m_cmd_cas_pktid_fifo.read();
+                r_cas_fsm              = CAS_IDLE;
+
+#if DEBUG_MEMC_CAS
+if( m_debug_cas_fsm )
+{
+    std::cout << "  <MEMC " << name() << ".CAS_RSP_SUCCESS> Request TGT_RSP to send a success response" << std::endl;
+}
+#endif
+            }
+            break;
+        }
+        /////////////////////
+        case CAS_MISS_TRT_LOCK:         // cache miss : request access to transaction Table
+        {
+            if( r_alloc_trt_fsm.read() == ALLOC_TRT_CAS )
+            {
+                size_t   index = 0;
+                bool hit_read = m_transaction_tab.hit_read(
+                                  m_nline[(vci_addr_t)m_cmd_cas_addr_fifo.read()],index);
+                bool hit_write = m_transaction_tab.hit_write(
+                                   m_nline[(vci_addr_t)m_cmd_cas_addr_fifo.read()]);
+                bool wok = !m_transaction_tab.full(index);
+
+#if DEBUG_MEMC_CAS
+if( m_debug_cas_fsm )
+{
+    std::cout << "  <MEMC " << name() << ".CAS_MISS_TRT_LOCK> Check TRT state"
+              << " / hit_read = "  << hit_read
+              << " / hit_write = " << hit_write
+              << " / wok = " << wok
+              << " / index = " << index << std::endl;
+}
+#endif
+
+                if ( hit_read || !wok || hit_write ) // missing line already requested or no space in TRT
+                {
+                    r_cas_fsm = CAS_WAIT;
+                }
+                else
+                {
+                    r_cas_trt_index = index;
+                    r_cas_fsm       = CAS_MISS_TRT_SET;
+                }
+            }
+            break;
+        }
+        ////////////////////
+        case CAS_MISS_TRT_SET: // register the GET transaction in TRT
+        {
+            if( r_alloc_trt_fsm.read() == ALLOC_TRT_CAS )
+            {
+                std::vector<be_t> be_vector;
+                std::vector<data_t> data_vector;
+                be_vector.clear();
+                data_vector.clear();
+                for ( size_t i=0; i<m_words; i++ )
+                {
+                    be_vector.push_back(0);
+                    data_vector.push_back(0);
+                }
+
+                m_transaction_tab.set(r_cas_trt_index.read(),
+                                      true,   // read request
+                                      m_nline[(vci_addr_t)m_cmd_cas_addr_fifo.read()],
+                                      m_cmd_cas_srcid_fifo.read(),
+                                      m_cmd_cas_trdid_fifo.read(),
+                                      m_cmd_cas_pktid_fifo.read(),
+                                      false,    // write request from processor
+                                      0,
+                                      0,
+                                      be_vector,
+                                      data_vector);
+                r_cas_fsm = CAS_MISS_XRAM_REQ;
+
+#if DEBUG_MEMC_CAS
+if( m_debug_cas_fsm )
+{
+    std::cout << "  <MEMC " << name() << ".CAS_MISS_TRT_SET> Register a GET transaction in TRT" << std::hex
+              << " / nline = " << m_nline[(vci_addr_t)m_cmd_cas_addr_fifo.read()]
+              << " / trt_index = " << r_cas_trt_index.read() << std::endl;
+}
+#endif
+            }
+            break;
+        }
+        //////////////////////
+        case CAS_MISS_XRAM_REQ:  // request the IXR_CMD FSM to fetch the missing line
+        {
+            if ( !r_cas_to_ixr_cmd_req )
+            {
+                r_cas_to_ixr_cmd_req        = true;
+                r_cas_to_ixr_cmd_write      = false;
+                r_cas_to_ixr_cmd_trdid      = r_cas_trt_index.read();
+                r_cas_to_ixr_cmd_nline      = m_nline[(vci_addr_t)m_cmd_cas_addr_fifo.read()];
+                r_cas_fsm                   = CAS_WAIT;
+
+#if DEBUG_MEMC_CAS
+if( m_debug_cas_fsm )
+{
+    std::cout << "  <MEMC " << name() << ".CAS_MISS_XRAM_REQ> Request a GET transaction to IXR_CMD FSM" << std::hex
+              << " / nline = " << m_nline[(vci_addr_t)m_cmd_cas_addr_fifo.read()]
+              << " / trt_index = " << r_cas_trt_index.read() << std::endl;
+}
+#endif
+            }
+            break;
+        }
+    } // end switch r_cas_fsm
+
+
+    //////////////////////////////////////////////////////////////////////////////
+    //    INIT_CMD FSM
+    //////////////////////////////////////////////////////////////////////////////
+    // The INIT_CMD fsm controls the VCI CMD initiator port on the coherence
+    // network, used to update or invalidate cache lines in L1 caches.
+    //
+    // It implements a round-robin priority between the three possible client FSMs
+    // XRAM_RSP, WRITE and CAS. Each FSM can request two types of services:
+    // - r_xram_rsp_to_init_cmd_multi_req : multi-inval
+    //   r_xram_rsp_to_init_cmd_brdcast_req : broadcast-inval
+    // - r_write_to_init_cmd_multi_req : multi-update
+    //   r_write_to_init_cmd_brdcast_req : broadcast-inval
+    // - r_cas_to_init_cmd_multi_req : multi-update
+    //   r_cas_to_init_cmd_brdcast_req : broadcast-inval
+    //
+    // An inval request is a single cell VCI write command containing the
+    // index of the line to be invalidated.
+    // An update request is a multi-cells VCI write command : The first cell
+    // contains the index of the cache line to be updated. The second cell contains
+    // the index of the first modified word in the line. The following cells
+    // contain the data.
+    ///////////////////////////////////////////////////////////////////////////////
+
+    switch ( r_init_cmd_fsm.read() )
+    {
+        ////////////////////////
+        case INIT_CMD_UPDT_IDLE:  // XRAM_RSP FSM has highest priority
+        {
+            if ( m_xram_rsp_to_init_cmd_inst_fifo.rok() ||
+                 r_xram_rsp_to_init_cmd_multi_req.read()  )
+            {
+                r_init_cmd_fsm = INIT_CMD_INVAL_NLINE;
+                m_cpt_inval++;
+            }
+            else if ( r_xram_rsp_to_init_cmd_brdcast_req.read() )
+            {
+                r_init_cmd_fsm = INIT_CMD_XRAM_BRDCAST;
+                m_cpt_inval++;
+            }
+            else if ( m_write_to_init_cmd_inst_fifo.rok() ||
+                      r_write_to_init_cmd_multi_req.read() )
+            {
+                r_init_cmd_fsm = INIT_CMD_UPDT_NLINE;
+                m_cpt_update++;
+            }
+            else if ( r_write_to_init_cmd_brdcast_req.read() )
+            {
+                r_init_cmd_fsm = INIT_CMD_WRITE_BRDCAST;
+                m_cpt_inval++;
+            }
+            else if ( m_cas_to_init_cmd_inst_fifo.rok() ||
+                      r_cas_to_init_cmd_multi_req.read()  )
+            {
+                r_init_cmd_fsm = INIT_CMD_CAS_UPDT_NLINE;
+                m_cpt_update++;
+            }
+            else if( r_cas_to_init_cmd_brdcast_req.read() )
+            {
+                r_init_cmd_fsm = INIT_CMD_CAS_BRDCAST;
+                m_cpt_inval++;
+            }
+            break;
+        }
+        /////////////////////////
+        case INIT_CMD_INVAL_IDLE: // WRITE FSM has highest priority
+        {
+            if ( m_write_to_init_cmd_inst_fifo.rok() ||
+                 r_write_to_init_cmd_multi_req.read() )
+            {
+                r_init_cmd_fsm = INIT_CMD_UPDT_NLINE;
+                m_cpt_update++;
+            }
+            else if ( r_write_to_init_cmd_brdcast_req.read() )
+            {
+                r_init_cmd_fsm = INIT_CMD_WRITE_BRDCAST;
+                m_cpt_inval++;
+            }
+            else if ( m_cas_to_init_cmd_inst_fifo.rok() ||
+                      r_cas_to_init_cmd_multi_req.read()  )
+            {
+                r_init_cmd_fsm = INIT_CMD_CAS_UPDT_NLINE;
+                m_cpt_update++;
+            }
+            else if( r_cas_to_init_cmd_brdcast_req.read() )
+            {
+                r_init_cmd_fsm = INIT_CMD_CAS_BRDCAST;
+                m_cpt_inval++;
+            }
+            else if ( m_xram_rsp_to_init_cmd_inst_fifo.rok() ||
+                      r_xram_rsp_to_init_cmd_multi_req.read()  )
+            {
+                r_init_cmd_fsm = INIT_CMD_INVAL_NLINE;
+                m_cpt_inval++;
+            }
+            else if ( r_xram_rsp_to_init_cmd_brdcast_req.read() )
+            {
+                r_init_cmd_fsm = INIT_CMD_XRAM_BRDCAST;
+                m_cpt_inval++;
+            }
+            break;
+        }
+        //////////////////////////
+        case INIT_CMD_CAS_UPDT_IDLE: // CAS FSM has highest priority
+        {
+            if ( m_cas_to_init_cmd_inst_fifo.rok() ||
+                 r_cas_to_init_cmd_multi_req.read()  )
+            {
+                r_init_cmd_fsm = INIT_CMD_CAS_UPDT_NLINE;
+                m_cpt_update++;
+            }
+            else if( r_cas_to_init_cmd_brdcast_req.read() )
+            {
+                r_init_cmd_fsm = INIT_CMD_CAS_BRDCAST;
+                m_cpt_inval++;
+            }
+            else if ( m_xram_rsp_to_init_cmd_inst_fifo.rok() ||
+                      r_xram_rsp_to_init_cmd_multi_req.read()  )
+            {
+                r_init_cmd_fsm = INIT_CMD_INVAL_NLINE;
+                m_cpt_inval++;
+            }
+            else if ( r_xram_rsp_to_init_cmd_brdcast_req.read() )
+            {
+                r_init_cmd_fsm = INIT_CMD_XRAM_BRDCAST;
+                m_cpt_inval++;
+            }
+            else if ( m_write_to_init_cmd_inst_fifo.rok() ||
+                      r_write_to_init_cmd_multi_req.read() )
+            {
+                r_init_cmd_fsm = INIT_CMD_UPDT_NLINE;
+                m_cpt_update++;
+            }
+            else if ( r_write_to_init_cmd_brdcast_req.read() )
+            {
+                r_init_cmd_fsm = INIT_CMD_WRITE_BRDCAST;
+                m_cpt_inval++;
+            }
+            break;
+        }
+        //////////////////////////
+        case INIT_CMD_INVAL_NLINE:  // send a multi-inval (from XRAM_RSP)
+        {
+            if ( m_xram_rsp_to_init_cmd_inst_fifo.rok() )
+            {
+                if ( p_vci_ini.cmdack )
+                {
+                    m_cpt_inval_mult++;
+                    r_init_cmd_fsm = INIT_CMD_INVAL_NLINE;
+                    xram_rsp_to_init_cmd_fifo_get = true;
+                }
+            }
+            else
+            {
+                if( r_xram_rsp_to_init_cmd_multi_req.read() ) r_xram_rsp_to_init_cmd_multi_req = false;
+                r_init_cmd_fsm = INIT_CMD_INVAL_IDLE;
+            }
+            break;
+        }
+        ///////////////////////////
+        case INIT_CMD_XRAM_BRDCAST: // send a broadcast-inval (from XRAM_RSP)
+        {
+            if ( p_vci_ini.cmdack )
+            {
+                m_cpt_inval_brdcast++;
+                r_init_cmd_fsm = INIT_CMD_INVAL_IDLE;
+                r_xram_rsp_to_init_cmd_brdcast_req = false;
+            }
+            break;
+        }
+        ////////////////////////////
+        case INIT_CMD_WRITE_BRDCAST:  // send a broadcast-inval (from WRITE FSM)
+        {
+            if( p_vci_ini.cmdack )
+            {
+
+#if DEBUG_MEMC_INIT_CMD
+if( m_debug_init_cmd_fsm )
+{
+    std::cout << "  <MEMC " << name() << ".INIT_CMD_WRITE_BRDCAST> Broadcast-Inval for line "
+              << r_write_to_init_cmd_nline.read() << std::endl;
+}
+#endif
+                m_cpt_inval_brdcast++;
+                r_write_to_init_cmd_brdcast_req = false;
+                r_init_cmd_fsm = INIT_CMD_UPDT_IDLE;
+            }
+            break;
+        }
+        /////////////////////////
+        case INIT_CMD_UPDT_NLINE:  // send nline for a multi-update (from WRITE FSM)
+        {
+            if ( m_write_to_init_cmd_inst_fifo.rok() )
+            {
+                if ( p_vci_ini.cmdack )
+                {
+                    m_cpt_update_mult++;
+                    r_init_cmd_fsm = INIT_CMD_UPDT_INDEX;
+                    // write_to_init_cmd_fifo_get = true;
+                }
+            }
+            else
+            {
+                if ( r_write_to_init_cmd_multi_req.read() ) r_write_to_init_cmd_multi_req = false;
+                r_init_cmd_fsm = INIT_CMD_UPDT_IDLE;
+            }
+            break;
+        }
+        /////////////////////////
+        case INIT_CMD_UPDT_INDEX:  // send word index for a multi-update (from WRITE FSM)
+        {
+            r_init_cmd_cpt    = 0;
+            if ( p_vci_ini.cmdack )  r_init_cmd_fsm = INIT_CMD_UPDT_DATA;
+            break;
+        }
+        ////////////////////////
+        case INIT_CMD_UPDT_DATA:  // send the data for a multi-update (from WRITE FSM)
+        {
+            if ( p_vci_ini.cmdack )
+            {
+                if ( r_init_cmd_cpt.read() == (r_write_to_init_cmd_count.read()-1) )
+                {
+                    r_init_cmd_fsm = INIT_CMD_UPDT_NLINE;
+                    write_to_init_cmd_fifo_get = true;
+                }
+                else
+                {
+                    r_init_cmd_cpt = r_init_cmd_cpt.read() + 1;
+                }
+            }
+            break;
+        }
+        /////////////////////////
+        case INIT_CMD_CAS_BRDCAST: // send a broadcast-inval (from CAS FSM)
+        {
+            if( p_vci_ini.cmdack )
+            {
+                m_cpt_inval_brdcast++;
+                r_cas_to_init_cmd_brdcast_req = false;
+                r_init_cmd_fsm = INIT_CMD_CAS_UPDT_IDLE;
+            }
+            break;
+        }
+        ////////////////////////////
+        case INIT_CMD_CAS_UPDT_NLINE:   // send nline for a multi-update (from CAS FSM)
+        {
+            if ( m_cas_to_init_cmd_inst_fifo.rok() )
+            {
+                if ( p_vci_ini.cmdack )
+                {
+                    m_cpt_update_mult++;
+                    r_init_cmd_fsm = INIT_CMD_CAS_UPDT_INDEX;
+                }
+            }
+            else
+            {
+                if( r_cas_to_init_cmd_multi_req.read() ) r_cas_to_init_cmd_multi_req = false;
+                r_init_cmd_fsm = INIT_CMD_CAS_UPDT_IDLE;
+            }
+            break;
+        }
+        ////////////////////////////
+        case INIT_CMD_CAS_UPDT_INDEX:  // send word index for a multi-update (from CAS FSM)
+        {
+            if ( p_vci_ini.cmdack )  r_init_cmd_fsm = INIT_CMD_CAS_UPDT_DATA;
+            break;
+        }
+        ///////////////////////////
+        case INIT_CMD_CAS_UPDT_DATA:  // send first data for a multi-update (from CAS FSM)
+        {
+            if ( p_vci_ini.cmdack )
+            {
+                if ( r_cas_to_init_cmd_is_long.read() )
+                {
+                    r_init_cmd_fsm = INIT_CMD_CAS_UPDT_DATA_HIGH;
+                }
+                else
+                {
+                    cas_to_init_cmd_fifo_get = true;
+                    r_init_cmd_fsm = INIT_CMD_CAS_UPDT_NLINE;
+                }
+            }
+            break;
+        }
+        ////////////////////////
+        case INIT_CMD_CAS_UPDT_DATA_HIGH:  // send second data for a multi-update (from CAS FSM)
+        {
+            if ( p_vci_ini.cmdack )
+            {
+                cas_to_init_cmd_fifo_get = true;
+                r_init_cmd_fsm = INIT_CMD_CAS_UPDT_NLINE;
+            }
+            break;
+        }
+    } // end switch r_init_cmd_fsm
+
+    /////////////////////////////////////////////////////////////////////
+    //    TGT_RSP FSM
+    /////////////////////////////////////////////////////////////////////
+    // The TGT_RSP fsm sends the responses on the VCI target port
+    // with a round robin priority between six requests :
+    // - r_read_to_tgt_rsp_req
+    // - r_write_to_tgt_rsp_req
+    // - r_cas_to_tgt_rsp_req
+    // - r_cleanup_to_tgt_rsp_req
+    // - r_xram_rsp_to_tgt_rsp_req
+    // - r_init_rsp_to_tgt_rsp_req
+    // The  ordering is :  read > write > cas > xram > init > cleanup
+    /////////////////////////////////////////////////////////////////////
+
+    switch ( r_tgt_rsp_fsm.read() )
+    {
+        ///////////////////////
+        case TGT_RSP_READ_IDLE:   // write requests have the highest priority
+        {
+          if      ( r_write_to_tgt_rsp_req    ) r_tgt_rsp_fsm = TGT_RSP_WRITE;
+          else if ( r_cas_to_tgt_rsp_req      ) r_tgt_rsp_fsm = TGT_RSP_CAS  ;
+          else if ( r_xram_rsp_to_tgt_rsp_req )
+          {
+            r_tgt_rsp_fsm = TGT_RSP_XRAM;
+            r_tgt_rsp_cpt = r_xram_rsp_to_tgt_rsp_word.read();
+          }
+          else if ( r_init_rsp_to_tgt_rsp_req ) r_tgt_rsp_fsm = TGT_RSP_INIT   ;
+          else if ( r_cleanup_to_tgt_rsp_req  ) r_tgt_rsp_fsm = TGT_RSP_CLEANUP;
+          else if ( r_read_to_tgt_rsp_req     )
+          {
+            r_tgt_rsp_fsm = TGT_RSP_READ;
+            r_tgt_rsp_cpt = r_read_to_tgt_rsp_word.read();
+          }
+          break;
+        }
+        ////////////////////////
+        case TGT_RSP_WRITE_IDLE:  // cas requests have the highest priority
+        {
+          if      ( r_cas_to_tgt_rsp_req      ) r_tgt_rsp_fsm = TGT_RSP_CAS;
+          else if ( r_xram_rsp_to_tgt_rsp_req )
+          {
+            r_tgt_rsp_fsm = TGT_RSP_XRAM;
+            r_tgt_rsp_cpt = r_xram_rsp_to_tgt_rsp_word.read();
+          }
+          else if ( r_init_rsp_to_tgt_rsp_req ) r_tgt_rsp_fsm = TGT_RSP_INIT   ;
+          else if ( r_cleanup_to_tgt_rsp_req  ) r_tgt_rsp_fsm = TGT_RSP_CLEANUP;
+          else if ( r_read_to_tgt_rsp_req     )
+          {
+            r_tgt_rsp_fsm = TGT_RSP_READ;
+            r_tgt_rsp_cpt = r_read_to_tgt_rsp_word.read();
+          }
+
+          else if ( r_write_to_tgt_rsp_req    ) r_tgt_rsp_fsm = TGT_RSP_WRITE;
+          break;
+        }
+        ///////////////////////
+        case TGT_RSP_CAS_IDLE:   // xram_rsp requests have the highest priority
+        {
+          if ( r_xram_rsp_to_tgt_rsp_req )
+          {
+            r_tgt_rsp_fsm = TGT_RSP_XRAM;
+            r_tgt_rsp_cpt = r_xram_rsp_to_tgt_rsp_word.read();
+          }
+          else if ( r_init_rsp_to_tgt_rsp_req ) r_tgt_rsp_fsm = TGT_RSP_INIT   ;
+          else if ( r_cleanup_to_tgt_rsp_req  ) r_tgt_rsp_fsm = TGT_RSP_CLEANUP;
+          else if ( r_read_to_tgt_rsp_req     )
+          {
+            r_tgt_rsp_fsm = TGT_RSP_READ;
+            r_tgt_rsp_cpt = r_read_to_tgt_rsp_word.read();
+          }
+          else if ( r_write_to_tgt_rsp_req ) r_tgt_rsp_fsm = TGT_RSP_WRITE;
+          else if ( r_cas_to_tgt_rsp_req   ) r_tgt_rsp_fsm = TGT_RSP_CAS  ;
+          break;
+        }
+        ///////////////////////
+        case TGT_RSP_XRAM_IDLE:   // init requests have the highest priority
+        {
+
+          if      ( r_init_rsp_to_tgt_rsp_req ) r_tgt_rsp_fsm = TGT_RSP_INIT   ;
+          else if ( r_cleanup_to_tgt_rsp_req  ) r_tgt_rsp_fsm = TGT_RSP_CLEANUP;
+          else if ( r_read_to_tgt_rsp_req     )
+          {
+            r_tgt_rsp_fsm = TGT_RSP_READ;
+            r_tgt_rsp_cpt = r_read_to_tgt_rsp_word.read();
+          }
+          else if ( r_write_to_tgt_rsp_req    ) r_tgt_rsp_fsm = TGT_RSP_WRITE;
+          else if ( r_cas_to_tgt_rsp_req      ) r_tgt_rsp_fsm = TGT_RSP_CAS  ;
+          else if ( r_xram_rsp_to_tgt_rsp_req )
+          {
+            r_tgt_rsp_fsm = TGT_RSP_XRAM;
+            r_tgt_rsp_cpt = r_xram_rsp_to_tgt_rsp_word.read();
+          }
+          break;
+        }
+        ///////////////////////
+        case TGT_RSP_INIT_IDLE:   // cleanup requests have the highest priority
+        {
+          if      ( r_cleanup_to_tgt_rsp_req  ) r_tgt_rsp_fsm = TGT_RSP_CLEANUP;
+          else if ( r_read_to_tgt_rsp_req     )
+          {
+            r_tgt_rsp_fsm = TGT_RSP_READ;
+            r_tgt_rsp_cpt = r_read_to_tgt_rsp_word.read();
+          }
+          else if ( r_write_to_tgt_rsp_req    ) r_tgt_rsp_fsm = TGT_RSP_WRITE;
+          else if ( r_cas_to_tgt_rsp_req      ) r_tgt_rsp_fsm = TGT_RSP_CAS  ;
+          else if ( r_xram_rsp_to_tgt_rsp_req )
+          {
+            r_tgt_rsp_fsm = TGT_RSP_XRAM;
+            r_tgt_rsp_cpt = r_xram_rsp_to_tgt_rsp_word.read();
+          }
+          else if ( r_init_rsp_to_tgt_rsp_req ) r_tgt_rsp_fsm = TGT_RSP_INIT;
+          break;
+        }
+        ///////////////////////
+        case TGT_RSP_CLEANUP_IDLE:    // read requests have the highest priority
+        {
+          if      ( r_read_to_tgt_rsp_req     )
+          {
+            r_tgt_rsp_fsm = TGT_RSP_READ;
+            r_tgt_rsp_cpt = r_read_to_tgt_rsp_word.read();
+          }
+          else if ( r_write_to_tgt_rsp_req    ) r_tgt_rsp_fsm = TGT_RSP_WRITE;
+          else if ( r_cas_to_tgt_rsp_req      ) r_tgt_rsp_fsm = TGT_RSP_CAS  ;
+          else if ( r_xram_rsp_to_tgt_rsp_req )
+          {
+            r_tgt_rsp_fsm = TGT_RSP_XRAM;
+            r_tgt_rsp_cpt = r_xram_rsp_to_tgt_rsp_word.read();
+          }
+          else if ( r_init_rsp_to_tgt_rsp_req ) r_tgt_rsp_fsm = TGT_RSP_INIT   ;
+          else if ( r_cleanup_to_tgt_rsp_req  ) r_tgt_rsp_fsm = TGT_RSP_CLEANUP;
+          break;
+        }
+        //////////////////
+        case TGT_RSP_READ:    // send the response to a read
+        {
+            if ( p_vci_tgt.rspack )
+            {
+
+#if DEBUG_MEMC_TGT_RSP
+if( m_debug_tgt_rsp_fsm )
+{
+    std::cout << "  <MEMC " << name() << ".TGT_RSP_READ> Read response"
+              << " / rsrcid = " << std::dec << r_read_to_tgt_rsp_srcid.read()
+              << " / rtrdid = " << r_read_to_tgt_rsp_trdid.read()
+              << " / rpktid = " << r_read_to_tgt_rsp_pktid.read()
+              << " / rdata = " << std::hex << r_read_to_tgt_rsp_data[r_tgt_rsp_cpt.read()].read()
+              << " / cpt = " << std::dec << r_tgt_rsp_cpt.read() << std::endl;
+}
+#endif
+        
+                uint32_t last_word_idx = r_read_to_tgt_rsp_word.read() + r_read_to_tgt_rsp_length.read() - 1;
+                bool     is_last_word  = (r_tgt_rsp_cpt.read() == last_word_idx);
+                bool     is_ll         = ((r_read_to_tgt_rsp_pktid.read() & 0x7) == TYPE_LL);
+
+                if ( (is_last_word and not is_ll) or (r_tgt_rsp_key_sent.read() and is_ll))
+                {
+                    // Last word in case of READ or second flit in case if LL
+                    r_tgt_rsp_key_sent    = false;
+                    r_read_to_tgt_rsp_req = false;
+                    r_tgt_rsp_fsm         = TGT_RSP_READ_IDLE;
+                }
+                else
+                {
+                    if (is_ll) {
+                      r_tgt_rsp_key_sent = true;                // Send second flit of ll
+                    }
+                    else {
+                      r_tgt_rsp_cpt = r_tgt_rsp_cpt.read() + 1; // Send next word of read
+                    }
+                }
+            }
+            break;
+        }
+        ///////////////////
+        case TGT_RSP_WRITE:   // send the write acknowledge
+        {
+            if ( p_vci_tgt.rspack )
+            {
+
+#if DEBUG_MEMC_TGT_RSP
+if( m_debug_tgt_rsp_fsm )
+{
+    std::cout << "  <MEMC " << name() << ".TGT_RSP_WRITE> Write response"
+              << " / rsrcid = " << std::dec << r_write_to_tgt_rsp_srcid.read()
+              << " / rtrdid = " << r_write_to_tgt_rsp_trdid.read()
+              << " / rpktid = " << r_write_to_tgt_rsp_pktid.read() << std::endl;
+}
+#endif
+                r_tgt_rsp_fsm = TGT_RSP_WRITE_IDLE;
+                r_write_to_tgt_rsp_req = false;
+            }
+            break;
+        }
+        ///////////////////
+        case TGT_RSP_CLEANUP:   // pas clair pour moi (AG)
+        {
+            if ( p_vci_tgt.rspack )
+            {
+
+#if DEBUG_MEMC_TGT_RSP
+if( m_debug_tgt_rsp_fsm )
+{
+    std::cout << "  <MEMC " << name() << ".TGT_RSP_CLEANUP> Cleanup response"
+              << " / rsrcid = " << std::dec << r_cleanup_to_tgt_rsp_srcid.read()
+              << " / rtrdid = " << r_cleanup_to_tgt_rsp_trdid.read()
+              << " / rpktid = " << r_cleanup_to_tgt_rsp_pktid.read() << std::endl;
+}
+#endif
+                r_tgt_rsp_fsm = TGT_RSP_CLEANUP_IDLE;
+                r_cleanup_to_tgt_rsp_req = false;
+            }
+            break;
+        }
+        //////////////////
+        case TGT_RSP_CAS:    // send one atomic word response
+        {
+            if ( p_vci_tgt.rspack )
+            {
+
+#if DEBUG_MEMC_TGT_RSP
+if( m_debug_tgt_rsp_fsm )
+{
+    std::cout << "  <MEMC " << name() << ".TGT_RSP_CAS> CAS response"
+              << " / rsrcid = " << std::dec << r_cas_to_tgt_rsp_srcid.read()
+              << " / rtrdid = " << r_cas_to_tgt_rsp_trdid.read()
+              << " / rpktid = " << r_cas_to_tgt_rsp_pktid.read() << std::endl;
+}
+#endif
+                r_tgt_rsp_fsm = TGT_RSP_CAS_IDLE;
+                r_cas_to_tgt_rsp_req = false;
+            }
+            break;
+        }
+
+        ///////////////////////
+        case TGT_RSP_XRAM:    // send the response after XRAM access
+        {
+            if ( p_vci_tgt.rspack )
+            {
+
+#if DEBUG_MEMC_TGT_RSP
+if( m_debug_tgt_rsp_fsm )
+{
+    std::cout << "  <MEMC " << name() << ".TGT_RSP_XRAM> Response following XRAM access"
+              << " / rsrcid = " << std::dec << r_xram_rsp_to_tgt_rsp_srcid.read()
+              << " / rtrdid = " << r_xram_rsp_to_tgt_rsp_trdid.read()
+              << " / rpktid = " << r_xram_rsp_to_tgt_rsp_pktid.read()
+              << " / rdata = " << std::hex << r_xram_rsp_to_tgt_rsp_data[r_tgt_rsp_cpt.read()].read()
+              << " / cpt = " << std::dec << r_tgt_rsp_cpt.read() << std::endl;
+}
+#endif
+                uint32_t last_word_idx = r_xram_rsp_to_tgt_rsp_word.read() + r_xram_rsp_to_tgt_rsp_length.read() - 1;
+                bool     is_last_word  = (r_tgt_rsp_cpt.read() == last_word_idx);
+                bool     is_ll         = ((r_xram_rsp_to_tgt_rsp_pktid.read() & 0x7) == TYPE_LL);
+                bool     is_error      = r_xram_rsp_to_tgt_rsp_rerror.read();
+
+                if (((is_last_word or is_error) and not is_ll) or
+                     (r_tgt_rsp_key_sent.read() and     is_ll))
+                {
+                    // Last word sent in case of READ or second flit sent in case if LL
+                    r_tgt_rsp_key_sent        = false;
+                    r_xram_rsp_to_tgt_rsp_req = false;
+                    r_tgt_rsp_fsm             = TGT_RSP_XRAM_IDLE;
+                }
+                else
+                {
+                    if (is_ll)
+                    {
+                      r_tgt_rsp_key_sent = true;                     // Send second flit of ll
+                    }                                                                            
+                    else
+                    {                                                                       
+                      r_tgt_rsp_cpt      = r_tgt_rsp_cpt.read() + 1; // Send next word of read
+                    }
+                }
+            }
+            break;
+        }
+        //////////////////
+        case TGT_RSP_INIT:    // send the write response after coherence transaction
+        {
+            if ( p_vci_tgt.rspack )
+            {
+
+#if DEBUG_MEMC_TGT_RSP
+if( m_debug_tgt_rsp_fsm )
+{
+    std::cout << "  <MEMC " << name() << ".TGT_RSP_INIT> Write response after coherence transaction"
+              << " / rsrcid = " << std::dec << r_init_rsp_to_tgt_rsp_srcid.read()
+              << " / rtrdid = " << r_init_rsp_to_tgt_rsp_trdid.read()
+              << " / rpktid = " << r_init_rsp_to_tgt_rsp_pktid.read() << std::endl;
+}
+#endif
+                r_tgt_rsp_fsm = TGT_RSP_INIT_IDLE;
+                r_init_rsp_to_tgt_rsp_req = false;
+            }
+            break;
+        }
+    } // end switch tgt_rsp_fsm
+
+    ////////////////////////////////////////////////////////////////////////////////////
+    //    ALLOC_UPT FSM
+    ////////////////////////////////////////////////////////////////////////////////////
+    // The ALLOC_UPT FSM allocates the access to the Update/Inval Table (UPT).
+    // with a round robin priority between three FSMs : INIT_RSP > WRITE > XRAM_RSP > CLEANUP
+    // - The WRITE FSM initiates update transactions and sets  new entry in UPT.
+    // - The XRAM_RSP FSM initiates inval transactions and sets  new entry in UPT.
+    // - The INIT_RSP FSM complete those trasactions and erase the UPT entry.
+    // - The CLEANUP  FSM decrement an entry in UPT.
+    // The resource is always allocated.
+    /////////////////////////////////////////////////////////////////////////////////////
+
+    switch ( r_alloc_upt_fsm.read() )
+    {
+
+      ////////////////////////
+      case ALLOC_UPT_INIT_RSP:
+        if (( r_init_rsp_fsm.read() != INIT_RSP_UPT_LOCK  ) &&
+            ( r_init_rsp_fsm.read() != INIT_RSP_UPT_CLEAR ))
+        {
+          if (( r_write_fsm.read() == WRITE_UPT_LOCK    ) ||
+              ( r_write_fsm.read() == WRITE_BC_UPT_LOCK ))
+            r_alloc_upt_fsm = ALLOC_UPT_WRITE;
+
+          else if ( r_xram_rsp_fsm.read() == XRAM_RSP_INVAL_LOCK )
+            r_alloc_upt_fsm = ALLOC_UPT_XRAM_RSP;
+
+          else if ( r_cleanup_fsm.read() == CLEANUP_UPT_LOCK )
+            r_alloc_upt_fsm = ALLOC_UPT_CLEANUP;
+
+          else if (( r_cas_fsm.read() == CAS_UPT_LOCK    ) ||
+                   ( r_cas_fsm.read() == CAS_BC_UPT_LOCK ))
+            r_alloc_upt_fsm = ALLOC_UPT_CAS;
+        }
+        break;
+
+        /////////////////////
+      case ALLOC_UPT_WRITE:
+        if (( r_write_fsm.read() != WRITE_UPT_LOCK    ) &&
+            ( r_write_fsm.read() != WRITE_BC_UPT_LOCK ))
+        {
+          if ( r_xram_rsp_fsm.read() == XRAM_RSP_INVAL_LOCK )
+            r_alloc_upt_fsm = ALLOC_UPT_XRAM_RSP;
+
+          else if ( r_cleanup_fsm.read() == CLEANUP_UPT_LOCK )
+            r_alloc_upt_fsm = ALLOC_UPT_CLEANUP;
+
+          else if (( r_cas_fsm.read() == CAS_UPT_LOCK    ) ||
+                   ( r_cas_fsm.read() == CAS_BC_UPT_LOCK ))
+            r_alloc_upt_fsm = ALLOC_UPT_CAS;
+
+          else if ( r_init_rsp_fsm.read() == INIT_RSP_UPT_LOCK )
+            r_alloc_upt_fsm = ALLOC_UPT_INIT_RSP;
+        }
+        break;
+
+        ////////////////////////
+      case ALLOC_UPT_XRAM_RSP:
+        if (r_xram_rsp_fsm.read() != XRAM_RSP_INVAL_LOCK)
+        {
+          if ( r_cleanup_fsm.read() == CLEANUP_UPT_LOCK )
+            r_alloc_upt_fsm = ALLOC_UPT_CLEANUP;
+
+          else if (( r_cas_fsm.read() == CAS_UPT_LOCK    ) ||
+                   ( r_cas_fsm.read() == CAS_BC_UPT_LOCK ))
+            r_alloc_upt_fsm = ALLOC_UPT_CAS;
+
+          else if ( r_init_rsp_fsm.read() == INIT_RSP_UPT_LOCK )
+            r_alloc_upt_fsm = ALLOC_UPT_INIT_RSP;
+
+          else if (( r_write_fsm.read() == WRITE_UPT_LOCK    )   ||
+                   ( r_write_fsm.read() == WRITE_BC_UPT_LOCK ))
+            r_alloc_upt_fsm = ALLOC_UPT_WRITE;
+        }
+        break;
+
+        //////////////////////////
+      case ALLOC_UPT_CLEANUP:
+        if(r_cleanup_fsm.read() != CLEANUP_UPT_LOCK )
+        {
+          if (( r_cas_fsm.read() == CAS_UPT_LOCK    ) ||
+              ( r_cas_fsm.read() == CAS_BC_UPT_LOCK ))
+            r_alloc_upt_fsm = ALLOC_UPT_CAS;
+
+          else if ( r_init_rsp_fsm.read() == INIT_RSP_UPT_LOCK )
+            r_alloc_upt_fsm = ALLOC_UPT_INIT_RSP;
+
+          else if (( r_write_fsm.read() == WRITE_UPT_LOCK    ) ||
+                   ( r_write_fsm.read() == WRITE_BC_UPT_LOCK ))
+            r_alloc_upt_fsm = ALLOC_UPT_WRITE;
+
+          else if ( r_xram_rsp_fsm.read() == XRAM_RSP_INVAL_LOCK )
+            r_alloc_upt_fsm = ALLOC_UPT_XRAM_RSP;
+        }
+        break;
+
+        //////////////////////////
+      case ALLOC_UPT_CAS:
+        if (( r_cas_fsm.read() != CAS_UPT_LOCK    ) &&
+            ( r_cas_fsm.read() != CAS_BC_UPT_LOCK ))
+        {
+          if ( r_init_rsp_fsm.read() == INIT_RSP_UPT_LOCK )
+            r_alloc_upt_fsm = ALLOC_UPT_INIT_RSP;
+
+          else if (( r_write_fsm.read() == WRITE_UPT_LOCK    ) ||
+                   ( r_write_fsm.read() == WRITE_BC_UPT_LOCK ))
+            r_alloc_upt_fsm = ALLOC_UPT_WRITE;
+
+          else if ( r_xram_rsp_fsm.read() == XRAM_RSP_INVAL_LOCK )
+            r_alloc_upt_fsm = ALLOC_UPT_XRAM_RSP;
+
+          else if ( r_cleanup_fsm.read() == CLEANUP_UPT_LOCK )
+            r_alloc_upt_fsm = ALLOC_UPT_CLEANUP;
+        }
+        break;
+
+    } // end switch r_alloc_upt_fsm
+
+    ////////////////////////////////////////////////////////////////////////////////////
+    //    ALLOC_DIR FSM
+    ////////////////////////////////////////////////////////////////////////////////////
+    // The ALLOC_DIR FSM allocates the access to the directory and
+    // the data cache with a round robin priority between 5 user FSMs :
+    // The cyclic ordering is READ > WRITE > CAS > CLEANUP > XRAM_RSP
+    // The ressource is always allocated.
+    /////////////////////////////////////////////////////////////////////////////////////
+
+    switch ( r_alloc_dir_fsm.read() )
+    {
+      case ALLOC_DIR_RESET:
+        // Initializes the directory one SET each cycle. All the WAYS of a SET are
+        // initialize in parallel
+
+        r_alloc_dir_reset_cpt.write(r_alloc_dir_reset_cpt.read() + 1);
+
+        if (r_alloc_dir_reset_cpt.read() == (m_sets - 1)) {
+          m_cache_directory.init();
+
+          r_alloc_dir_fsm = ALLOC_DIR_READ;
+        }
+        break;
+
+      ////////////////////
+      case ALLOC_DIR_READ:
+        if ((( r_read_fsm.read()       != READ_DIR_REQ    )   &&
+             ( r_read_fsm.read()       != READ_DIR_LOCK   )   &&
+             ( r_read_fsm.read()       != READ_TRT_LOCK   )   &&
+             ( r_read_fsm.read()       != READ_HEAP_REQ   ))
+            ||
+            (( r_read_fsm.read()       == READ_TRT_LOCK   )   &&
+             ( r_alloc_trt_fsm.read()  == ALLOC_TRT_READ  )))
+        {
+          if (r_write_fsm.read() == WRITE_DIR_REQ)
+            r_alloc_dir_fsm = ALLOC_DIR_WRITE;
+
+          else if (r_cas_fsm.read() == CAS_DIR_REQ)
+            r_alloc_dir_fsm = ALLOC_DIR_CAS;
+
+          else if (r_cleanup_fsm.read() == CLEANUP_DIR_REQ )
+            r_alloc_dir_fsm = ALLOC_DIR_CLEANUP;
+
+          else if (r_xram_rsp_fsm.read() == XRAM_RSP_DIR_LOCK)
+            r_alloc_dir_fsm = ALLOC_DIR_XRAM_RSP;
+        }
+        break;
+
+        /////////////////////
+      case ALLOC_DIR_WRITE:
+        if ((( r_write_fsm.read()      != WRITE_DIR_REQ       )  &&
+             ( r_write_fsm.read()      != WRITE_DIR_LOCK      )  &&
+             ( r_write_fsm.read()      != WRITE_DIR_READ      )  &&
+             ( r_write_fsm.read()      != WRITE_DIR_HIT       )  &&
+             ( r_write_fsm.read()      != WRITE_BC_TRT_LOCK   )  &&
+             ( r_write_fsm.read()      != WRITE_BC_UPT_LOCK   )  &&
+             ( r_write_fsm.read()      != WRITE_MISS_TRT_LOCK )  &&
+             ( r_write_fsm.read()      != WRITE_UPT_LOCK      )  &&
+             ( r_write_fsm.read()      != WRITE_UPT_HEAP_LOCK ))
+            ||
+            (( r_write_fsm.read()      == WRITE_UPT_HEAP_LOCK )  &&
+             ( r_alloc_heap_fsm.read() == ALLOC_HEAP_WRITE    ))
+            ||
+            (( r_write_fsm.read()      == WRITE_MISS_TRT_LOCK )  &&
+             ( r_alloc_trt_fsm.read()  == ALLOC_TRT_WRITE     )))
+        {
+          if ( r_cas_fsm.read() == CAS_DIR_REQ )
+            r_alloc_dir_fsm = ALLOC_DIR_CAS;
+
+          else if ( r_cleanup_fsm.read() == CLEANUP_DIR_REQ )
+            r_alloc_dir_fsm = ALLOC_DIR_CLEANUP;
+
+          else if ( r_xram_rsp_fsm.read() == XRAM_RSP_DIR_LOCK )
+            r_alloc_dir_fsm = ALLOC_DIR_XRAM_RSP;
+
+          else if ( r_read_fsm.read() == READ_DIR_REQ )
+            r_alloc_dir_fsm = ALLOC_DIR_READ;
+        }
+        break;
+
+        ////////////////////
+        case ALLOC_DIR_CAS:
+        if ((( r_cas_fsm.read()        != CAS_DIR_REQ        )  &&
+             ( r_cas_fsm.read()        != CAS_DIR_LOCK       )  &&
+             ( r_cas_fsm.read()        != CAS_DIR_HIT_READ   )  &&
+             ( r_cas_fsm.read()        != CAS_DIR_HIT_COMPARE)  &&
+             ( r_cas_fsm.read()        != CAS_DIR_HIT_WRITE  )  &&
+             ( r_cas_fsm.read()        != CAS_BC_TRT_LOCK    )  &&
+             ( r_cas_fsm.read()        != CAS_BC_UPT_LOCK    )  &&
+             ( r_cas_fsm.read()        != CAS_MISS_TRT_LOCK  )  &&
+             ( r_cas_fsm.read()        != CAS_UPT_LOCK       )  &&
+             ( r_cas_fsm.read()        != CAS_UPT_HEAP_LOCK  ))
+            ||
+            (( r_cas_fsm.read()        == CAS_UPT_HEAP_LOCK  )  &&
+             ( r_alloc_heap_fsm.read() == ALLOC_HEAP_CAS     ))
+            ||
+            (( r_cas_fsm.read()        == CAS_MISS_TRT_LOCK  )  &&
+             ( r_alloc_trt_fsm.read()  == ALLOC_TRT_CAS      )))
+        {
+          if ( r_cleanup_fsm.read() == CLEANUP_DIR_REQ )
+            r_alloc_dir_fsm = ALLOC_DIR_CLEANUP;
+
+          else if ( r_xram_rsp_fsm.read() == XRAM_RSP_DIR_LOCK )
+            r_alloc_dir_fsm = ALLOC_DIR_XRAM_RSP;
+
+          else if ( r_read_fsm.read() == READ_DIR_REQ )
+            r_alloc_dir_fsm = ALLOC_DIR_READ;
+
+          else if ( r_write_fsm.read() == WRITE_DIR_REQ )
+            r_alloc_dir_fsm = ALLOC_DIR_WRITE;
+        }
+        break;
+
+        ///////////////////////
+        case ALLOC_DIR_CLEANUP:
+        if (( r_cleanup_fsm.read() != CLEANUP_DIR_REQ   ) &&
+            ( r_cleanup_fsm.read() != CLEANUP_DIR_LOCK  ) &&
+            ( r_cleanup_fsm.read() != CLEANUP_HEAP_REQ  ) &&
+            ( r_cleanup_fsm.read() != CLEANUP_HEAP_LOCK ))
+        {
+          if ( r_xram_rsp_fsm.read() == XRAM_RSP_DIR_LOCK )
+            r_alloc_dir_fsm = ALLOC_DIR_XRAM_RSP;
+
+          else if ( r_read_fsm.read() == READ_DIR_REQ )
+            r_alloc_dir_fsm = ALLOC_DIR_READ;
+
+          else if ( r_write_fsm.read() == WRITE_DIR_REQ )
+            r_alloc_dir_fsm = ALLOC_DIR_WRITE;
+
+          else if ( r_cas_fsm.read() == CAS_DIR_REQ )
+            r_alloc_dir_fsm = ALLOC_DIR_CAS;
+        }
+        break;
+
+        ////////////////////////
+        case ALLOC_DIR_XRAM_RSP:
+        if (( r_xram_rsp_fsm.read() != XRAM_RSP_DIR_LOCK   ) &&
+            ( r_xram_rsp_fsm.read() != XRAM_RSP_TRT_COPY   ) &&
+            ( r_xram_rsp_fsm.read() != XRAM_RSP_INVAL_LOCK ))
+        {
+          if ( r_read_fsm.read() == READ_DIR_REQ )
+            r_alloc_dir_fsm = ALLOC_DIR_READ;
+
+          else if ( r_write_fsm.read() == WRITE_DIR_REQ )
+            r_alloc_dir_fsm = ALLOC_DIR_WRITE;
+
+          else if ( r_cas_fsm.read() == CAS_DIR_REQ )
+            r_alloc_dir_fsm = ALLOC_DIR_CAS;
+
+          else if ( r_cleanup_fsm.read() == CLEANUP_DIR_REQ )
+            r_alloc_dir_fsm = ALLOC_DIR_CLEANUP;
+        }
+        break;
+
+    } // end switch alloc_dir_fsm
+
+    ////////////////////////////////////////////////////////////////////////////////////
+    //    ALLOC_TRT FSM
+    ////////////////////////////////////////////////////////////////////////////////////
+    // The ALLOC_TRT fsm allocates the access to the Transaction Table (write buffer)
+    // with a round robin priority between 4 user FSMs :
+    // The cyclic priority is READ > WRITE > CAS > XRAM_RSP
+    // The ressource is always allocated.
+    ///////////////////////////////////////////////////////////////////////////////////
+
+    switch ( r_alloc_trt_fsm.read() )
+    {
+      ////////////////////
+      case ALLOC_TRT_READ:
+        if ( r_read_fsm.read() != READ_TRT_LOCK )
+        {
+          if (( r_write_fsm.read() == WRITE_MISS_TRT_LOCK ) ||
+              ( r_write_fsm.read() == WRITE_BC_TRT_LOCK   ))
+            r_alloc_trt_fsm = ALLOC_TRT_WRITE;
+
+          else if (( r_cas_fsm.read() == CAS_MISS_TRT_LOCK ) ||
+                   ( r_cas_fsm.read() == CAS_BC_TRT_LOCK   ))
+            r_alloc_trt_fsm = ALLOC_TRT_CAS;
+
+          else if (( r_xram_rsp_fsm.read()  == XRAM_RSP_DIR_LOCK  ) &&
+                   ( r_alloc_dir_fsm.read() == ALLOC_DIR_XRAM_RSP ))
+            r_alloc_trt_fsm = ALLOC_TRT_XRAM_RSP;
+
+          else if (( r_ixr_rsp_fsm.read() == IXR_RSP_TRT_ERASE ) ||
+                   ( r_ixr_rsp_fsm.read() == IXR_RSP_TRT_READ  ))
+            r_alloc_trt_fsm = ALLOC_TRT_IXR_RSP;
+        }
+        break;
+
+      /////////////////////
+      case ALLOC_TRT_WRITE:
+        if (( r_write_fsm.read() != WRITE_MISS_TRT_LOCK ) &&
+            ( r_write_fsm.read() != WRITE_BC_TRT_LOCK   ) &&
+            ( r_write_fsm.read() != WRITE_BC_UPT_LOCK   ))
+        {
+          if (( r_cas_fsm.read() == CAS_MISS_TRT_LOCK ) ||
+              ( r_cas_fsm.read() == CAS_BC_TRT_LOCK   ))
+            r_alloc_trt_fsm = ALLOC_TRT_CAS;
+
+          else if (( r_xram_rsp_fsm.read()  == XRAM_RSP_DIR_LOCK  ) &&
+                   ( r_alloc_dir_fsm.read() == ALLOC_DIR_XRAM_RSP ))
+            r_alloc_trt_fsm = ALLOC_TRT_XRAM_RSP;
+
+          else if (( r_ixr_rsp_fsm.read() == IXR_RSP_TRT_ERASE ) ||
+                   ( r_ixr_rsp_fsm.read() == IXR_RSP_TRT_READ  ))
+            r_alloc_trt_fsm = ALLOC_TRT_IXR_RSP;
+
+          else if ( r_read_fsm.read() == READ_TRT_LOCK )
+            r_alloc_trt_fsm = ALLOC_TRT_READ;
+        }
+        break;
+
+      ////////////////////
+      case ALLOC_TRT_CAS:
+        if (( r_cas_fsm.read() != CAS_MISS_TRT_LOCK ) &&
+            ( r_cas_fsm.read() != CAS_BC_TRT_LOCK   ) &&
+            ( r_cas_fsm.read() != CAS_BC_UPT_LOCK   ))
+        {
+          if (( r_xram_rsp_fsm.read()  == XRAM_RSP_DIR_LOCK  ) &&
+              ( r_alloc_dir_fsm.read() == ALLOC_DIR_XRAM_RSP ))
+            r_alloc_trt_fsm = ALLOC_TRT_XRAM_RSP;
+
+          else if (( r_ixr_rsp_fsm.read() == IXR_RSP_TRT_ERASE ) ||
+                   ( r_ixr_rsp_fsm.read() == IXR_RSP_TRT_READ  ))
+            r_alloc_trt_fsm = ALLOC_TRT_IXR_RSP;
+
+          else if ( r_read_fsm.read() == READ_TRT_LOCK )
+            r_alloc_trt_fsm = ALLOC_TRT_READ;
+
+          else if (( r_write_fsm.read() == WRITE_MISS_TRT_LOCK ) ||
+                   ( r_write_fsm.read() == WRITE_BC_TRT_LOCK   ))
+            r_alloc_trt_fsm = ALLOC_TRT_WRITE;
+        }
+        break;
+
+      ////////////////////////
+      case ALLOC_TRT_XRAM_RSP:
+        if ((( r_xram_rsp_fsm.read()  != XRAM_RSP_DIR_LOCK   )  ||
+             ( r_alloc_dir_fsm.read() != ALLOC_DIR_XRAM_RSP  )) &&
+             ( r_xram_rsp_fsm.read()  != XRAM_RSP_TRT_COPY   )  &&
+             ( r_xram_rsp_fsm.read()  != XRAM_RSP_DIR_UPDT   )  &&
+             ( r_xram_rsp_fsm.read()  != XRAM_RSP_INVAL_LOCK ))
+        {
+          if (( r_ixr_rsp_fsm.read() == IXR_RSP_TRT_ERASE ) ||
+              ( r_ixr_rsp_fsm.read() == IXR_RSP_TRT_READ  ))
+            r_alloc_trt_fsm = ALLOC_TRT_IXR_RSP;
+
+          else if ( r_read_fsm.read() == READ_TRT_LOCK )
+            r_alloc_trt_fsm = ALLOC_TRT_READ;
+
+          else if (( r_write_fsm.read() == WRITE_MISS_TRT_LOCK ) ||
+                   ( r_write_fsm.read() == WRITE_BC_TRT_LOCK   ))
+            r_alloc_trt_fsm = ALLOC_TRT_WRITE;
+
+          else if (( r_cas_fsm.read() == CAS_MISS_TRT_LOCK ) ||
+                   ( r_cas_fsm.read() == CAS_BC_TRT_LOCK   ))
+            r_alloc_trt_fsm = ALLOC_TRT_CAS;
+        }
+        break;
+
+      ////////////////////////
+      case ALLOC_TRT_IXR_RSP:
+        if (( r_ixr_rsp_fsm.read() != IXR_RSP_TRT_ERASE ) &&
+            ( r_ixr_rsp_fsm.read() != IXR_RSP_TRT_READ  ))
+        {
+          if ( r_read_fsm.read() == READ_TRT_LOCK )
+            r_alloc_trt_fsm = ALLOC_TRT_READ;
+
+          else if (( r_write_fsm.read() == WRITE_MISS_TRT_LOCK ) ||
+                   ( r_write_fsm.read() == WRITE_BC_TRT_LOCK   ))
+            r_alloc_trt_fsm = ALLOC_TRT_WRITE;
+
+          else if (( r_cas_fsm.read() == CAS_MISS_TRT_LOCK ) ||
+                   ( r_cas_fsm.read() == CAS_BC_TRT_LOCK   ))
+            r_alloc_trt_fsm = ALLOC_TRT_CAS;
+
+          else if (( r_xram_rsp_fsm.read()  == XRAM_RSP_DIR_LOCK  ) &&
+                   ( r_alloc_dir_fsm.read() == ALLOC_DIR_XRAM_RSP ))
+            r_alloc_trt_fsm = ALLOC_TRT_XRAM_RSP;
+        }
+        break;
+
+    } // end switch alloc_trt_fsm
+
+    ////////////////////////////////////////////////////////////////////////////////////
+    //    ALLOC_HEAP FSM
+    ////////////////////////////////////////////////////////////////////////////////////
+    // The ALLOC_HEAP FSM allocates the access to the heap
+    // with a round robin priority between 5 user FSMs :
+    // The cyclic ordering is READ > WRITE > CAS > CLEANUP > XRAM_RSP
+    // The ressource is always allocated.
+    /////////////////////////////////////////////////////////////////////////////////////
+
+    switch ( r_alloc_heap_fsm.read() )
+    {
+        ////////////////////
+        case ALLOC_HEAP_RESET:
+          // Initializes the heap one ENTRY each cycle.
+
+          r_alloc_heap_reset_cpt.write(r_alloc_heap_reset_cpt.read() + 1);
+
+          if(r_alloc_heap_reset_cpt.read() == (m_heap_size-1)) {
+            m_heap.init();
+
+            r_alloc_heap_fsm = ALLOC_HEAP_READ;
+          }
+          break;
+
+        ////////////////////
+        case ALLOC_HEAP_READ:
+        if (( r_read_fsm.read() != READ_HEAP_REQ   ) &&
+            ( r_read_fsm.read() != READ_HEAP_LOCK  ) &&
+            ( r_read_fsm.read() != READ_HEAP_ERASE ))
+        {
+          if ( r_write_fsm.read() == WRITE_UPT_HEAP_LOCK )
+            r_alloc_heap_fsm = ALLOC_HEAP_WRITE;
+
+          else if ( r_cas_fsm.read() == CAS_UPT_HEAP_LOCK )
+            r_alloc_heap_fsm = ALLOC_HEAP_CAS;
+
+          else if ( r_cleanup_fsm.read() == CLEANUP_HEAP_REQ )
+            r_alloc_heap_fsm = ALLOC_HEAP_CLEANUP;
+
+          else if ( r_xram_rsp_fsm.read() == XRAM_RSP_HEAP_REQ )
+            r_alloc_heap_fsm = ALLOC_HEAP_XRAM_RSP;
+        }
+        break;
+
+        /////////////////////
+        case ALLOC_HEAP_WRITE:
+        if (( r_write_fsm.read() != WRITE_UPT_HEAP_LOCK ) &&
+            ( r_write_fsm.read() != WRITE_UPT_REQ       ) &&
+            ( r_write_fsm.read() != WRITE_UPT_NEXT      ))
+        {
+          if ( r_cas_fsm.read() == CAS_UPT_HEAP_LOCK )
+            r_alloc_heap_fsm = ALLOC_HEAP_CAS;
+
+          else if ( r_cleanup_fsm.read() == CLEANUP_HEAP_REQ )
+            r_alloc_heap_fsm = ALLOC_HEAP_CLEANUP;
+
+          else if ( r_xram_rsp_fsm.read() == XRAM_RSP_HEAP_REQ )
+            r_alloc_heap_fsm = ALLOC_HEAP_XRAM_RSP;
+
+          else if ( r_read_fsm.read() == READ_HEAP_REQ )
+            r_alloc_heap_fsm = ALLOC_HEAP_READ;
+        }
+        break;
+
+        ////////////////////
+        case ALLOC_HEAP_CAS:
+        if (( r_cas_fsm.read() != CAS_UPT_HEAP_LOCK ) &&
+            ( r_cas_fsm.read() != CAS_UPT_REQ       ) &&
+            ( r_cas_fsm.read() != CAS_UPT_NEXT      ))
+        {
+          if ( r_cleanup_fsm.read() == CLEANUP_HEAP_REQ )
+            r_alloc_heap_fsm = ALLOC_HEAP_CLEANUP;
+
+          else if ( r_xram_rsp_fsm.read() == XRAM_RSP_HEAP_REQ )
+            r_alloc_heap_fsm = ALLOC_HEAP_XRAM_RSP;
+
+          else if ( r_read_fsm.read() == READ_HEAP_REQ )
+            r_alloc_heap_fsm = ALLOC_HEAP_READ;
+
+          else if ( r_write_fsm.read() == WRITE_UPT_HEAP_LOCK )
+            r_alloc_heap_fsm = ALLOC_HEAP_WRITE;
+        }
+        break;
+
+        ///////////////////////
+        case ALLOC_HEAP_CLEANUP:
+        if (( r_cleanup_fsm.read() != CLEANUP_HEAP_REQ    ) &&
+            ( r_cleanup_fsm.read() != CLEANUP_HEAP_LOCK   ) &&
+            ( r_cleanup_fsm.read() != CLEANUP_HEAP_SEARCH ) &&
+            ( r_cleanup_fsm.read() != CLEANUP_HEAP_CLEAN  ))
+        {
+          if ( r_xram_rsp_fsm.read() == XRAM_RSP_HEAP_REQ )
+            r_alloc_heap_fsm = ALLOC_HEAP_XRAM_RSP;
+
+          else if ( r_read_fsm.read() == READ_HEAP_REQ )
+            r_alloc_heap_fsm = ALLOC_HEAP_READ;
+
+          else if ( r_write_fsm.read() == WRITE_UPT_HEAP_LOCK )
+            r_alloc_heap_fsm = ALLOC_HEAP_WRITE;
+
+          else if ( r_cas_fsm.read() == CAS_UPT_HEAP_LOCK )
+            r_alloc_heap_fsm = ALLOC_HEAP_CAS;
+        }
+        break;
+
+        ////////////////////////
+        case ALLOC_HEAP_XRAM_RSP:
+        if (( r_xram_rsp_fsm.read() != XRAM_RSP_HEAP_REQ   ) &&
+            ( r_xram_rsp_fsm.read() != XRAM_RSP_HEAP_ERASE ))
+        {
+          if  ( r_read_fsm.read() == READ_HEAP_REQ )
+            r_alloc_heap_fsm = ALLOC_HEAP_READ;
+
+          else if ( r_write_fsm.read() == WRITE_UPT_HEAP_LOCK )
+            r_alloc_heap_fsm = ALLOC_HEAP_WRITE;
+
+          else if ( r_cas_fsm.read() == CAS_UPT_HEAP_LOCK )
+            r_alloc_heap_fsm = ALLOC_HEAP_CAS;
+
+          else if ( r_cleanup_fsm.read() == CLEANUP_HEAP_REQ )
+            r_alloc_heap_fsm = ALLOC_HEAP_CLEANUP;
+
+        }
+        break;
+
+    } // end switch alloc_heap_fsm
+
+
+    ////////////////////////////////////////////////////////////////////////////////////
+    //    TGT_CMD to READ FIFO
+    ////////////////////////////////////////////////////////////////////////////////////
+
+    if ( cmd_read_fifo_put ) {
+      if ( cmd_read_fifo_get ) {
+        m_cmd_read_addr_fifo.put_and_get((addr_t)(p_vci_tgt.address.read()));
+        m_cmd_read_length_fifo.put_and_get(p_vci_tgt.plen.read()>>2);
+        m_cmd_read_srcid_fifo.put_and_get(p_vci_tgt.srcid.read());
+        m_cmd_read_trdid_fifo.put_and_get(p_vci_tgt.trdid.read());
+        m_cmd_read_pktid_fifo.put_and_get(p_vci_tgt.pktid.read());
+      } else {
+        m_cmd_read_addr_fifo.simple_put((addr_t)(p_vci_tgt.address.read()));
+        m_cmd_read_length_fifo.simple_put(p_vci_tgt.plen.read()>>2);
+        m_cmd_read_srcid_fifo.simple_put(p_vci_tgt.srcid.read());
+        m_cmd_read_trdid_fifo.simple_put(p_vci_tgt.trdid.read());
+        m_cmd_read_pktid_fifo.simple_put(p_vci_tgt.pktid.read());
+      }
+    } else {
+      if ( cmd_read_fifo_get ) {
+        m_cmd_read_addr_fifo.simple_get();
+        m_cmd_read_length_fifo.simple_get();
+        m_cmd_read_srcid_fifo.simple_get();
+        m_cmd_read_trdid_fifo.simple_get();
+        m_cmd_read_pktid_fifo.simple_get();
+      }
+    }
+    /////////////////////////////////////////////////////////////////////
+    //    TGT_CMD to WRITE FIFO
+    /////////////////////////////////////////////////////////////////////
+
+    if ( cmd_write_fifo_put ) {
+      if ( cmd_write_fifo_get ) {
+        m_cmd_write_addr_fifo.put_and_get((addr_t)(p_vci_tgt.address.read()));
+        m_cmd_write_eop_fifo.put_and_get(p_vci_tgt.eop.read());
+        m_cmd_write_srcid_fifo.put_and_get(p_vci_tgt.srcid.read());
+        m_cmd_write_trdid_fifo.put_and_get(p_vci_tgt.trdid.read());
+        m_cmd_write_pktid_fifo.put_and_get(p_vci_tgt.pktid.read());
+        m_cmd_write_data_fifo.put_and_get(p_vci_tgt.wdata.read());
+        m_cmd_write_be_fifo.put_and_get(p_vci_tgt.be.read());
+      } else {
+        m_cmd_write_addr_fifo.simple_put((addr_t)(p_vci_tgt.address.read()));
+        m_cmd_write_eop_fifo.simple_put(p_vci_tgt.eop.read());
+        m_cmd_write_srcid_fifo.simple_put(p_vci_tgt.srcid.read());
+        m_cmd_write_trdid_fifo.simple_put(p_vci_tgt.trdid.read());
+        m_cmd_write_pktid_fifo.simple_put(p_vci_tgt.pktid.read());
+        m_cmd_write_data_fifo.simple_put(p_vci_tgt.wdata.read());
+        m_cmd_write_be_fifo.simple_put(p_vci_tgt.be.read());
+      }
+    } else {
+      if ( cmd_write_fifo_get ) {
+        m_cmd_write_addr_fifo.simple_get();
+        m_cmd_write_eop_fifo.simple_get();
+        m_cmd_write_srcid_fifo.simple_get();
+        m_cmd_write_trdid_fifo.simple_get();
+        m_cmd_write_pktid_fifo.simple_get();
+        m_cmd_write_data_fifo.simple_get();
+        m_cmd_write_be_fifo.simple_get();
+      }
+    }
+    ////////////////////////////////////////////////////////////////////////////////////
+    //    TGT_CMD to CAS FIFO
+    ////////////////////////////////////////////////////////////////////////////////////
+
+    if ( cmd_cas_fifo_put ) {
+      if ( cmd_cas_fifo_get ) {
+        m_cmd_cas_addr_fifo.put_and_get((addr_t)(p_vci_tgt.address.read()));
+        m_cmd_cas_eop_fifo.put_and_get(p_vci_tgt.eop.read());
+        m_cmd_cas_srcid_fifo.put_and_get(p_vci_tgt.srcid.read());
+        m_cmd_cas_trdid_fifo.put_and_get(p_vci_tgt.trdid.read());
+        m_cmd_cas_pktid_fifo.put_and_get(p_vci_tgt.pktid.read());
+        m_cmd_cas_wdata_fifo.put_and_get(p_vci_tgt.wdata.read());
+      } else {
+        m_cmd_cas_addr_fifo.simple_put((addr_t)(p_vci_tgt.address.read()));
+        m_cmd_cas_eop_fifo.simple_put(p_vci_tgt.eop.read());
+        m_cmd_cas_srcid_fifo.simple_put(p_vci_tgt.srcid.read());
+        m_cmd_cas_trdid_fifo.simple_put(p_vci_tgt.trdid.read());
+        m_cmd_cas_pktid_fifo.simple_put(p_vci_tgt.pktid.read());
+        m_cmd_cas_wdata_fifo.simple_put(p_vci_tgt.wdata.read());
+      }
+    } else {
+      if ( cmd_cas_fifo_get ) {
+        m_cmd_cas_addr_fifo.simple_get();
+        m_cmd_cas_eop_fifo.simple_get();
+        m_cmd_cas_srcid_fifo.simple_get();
+        m_cmd_cas_trdid_fifo.simple_get();
+        m_cmd_cas_pktid_fifo.simple_get();
+        m_cmd_cas_wdata_fifo.simple_get();
+      }
+    }
+    ////////////////////////////////////////////////////////////////////////////////////
+    //    WRITE to INIT_CMD FIFO
+    ////////////////////////////////////////////////////////////////////////////////////
+
+    if ( write_to_init_cmd_fifo_put ) {
+      if ( write_to_init_cmd_fifo_get ) {
+        m_write_to_init_cmd_inst_fifo.put_and_get(write_to_init_cmd_fifo_inst);
+        m_write_to_init_cmd_srcid_fifo.put_and_get(write_to_init_cmd_fifo_srcid);
+#if L1_MULTI_CACHE
+        m_write_to_init_cmd_cache_id_fifo.put_and_get(write_to_init_cmd_fifo_cache_id);
+#endif
+      } else {
+        m_write_to_init_cmd_inst_fifo.simple_put(write_to_init_cmd_fifo_inst);
+        m_write_to_init_cmd_srcid_fifo.simple_put(write_to_init_cmd_fifo_srcid);
+#if L1_MULTI_CACHE
+        m_write_to_init_cmd_cache_id_fifo.simple_put(write_to_init_cmd_fifo_cache_id);
+#endif
+      }
+    } else {
+      if ( write_to_init_cmd_fifo_get ) {
+        m_write_to_init_cmd_inst_fifo.simple_get();
+        m_write_to_init_cmd_srcid_fifo.simple_get();
+#if L1_MULTI_CACHE
+        m_write_to_init_cmd_cache_id_fifo.simple_get();
+#endif
+      }
+    }
+    ////////////////////////////////////////////////////////////////////////////////////
+    //    XRAM_RSP to INIT_CMD FIFO
+    ////////////////////////////////////////////////////////////////////////////////////
+
+    if ( xram_rsp_to_init_cmd_fifo_put ) {
+      if ( xram_rsp_to_init_cmd_fifo_get ) {
+        m_xram_rsp_to_init_cmd_inst_fifo.put_and_get(xram_rsp_to_init_cmd_fifo_inst);
+        m_xram_rsp_to_init_cmd_srcid_fifo.put_and_get(xram_rsp_to_init_cmd_fifo_srcid);
+#if L1_MULTI_CACHE
+        m_xram_rsp_to_init_cmd_cache_id_fifo.put_and_get(xram_rsp_to_init_cmd_fifo_cache_id);
+#endif
+      } else {
+        m_xram_rsp_to_init_cmd_inst_fifo.simple_put(xram_rsp_to_init_cmd_fifo_inst);
+        m_xram_rsp_to_init_cmd_srcid_fifo.simple_put(xram_rsp_to_init_cmd_fifo_srcid);
+#if L1_MULTI_CACHE
+        m_xram_rsp_to_init_cmd_cache_id_fifo.simple_put(xram_rsp_to_init_cmd_fifo_cache_id);
+#endif
+      }
+    } else {
+      if ( xram_rsp_to_init_cmd_fifo_get ) {
+        m_xram_rsp_to_init_cmd_inst_fifo.simple_get();
+        m_xram_rsp_to_init_cmd_srcid_fifo.simple_get();
+#if L1_MULTI_CACHE
+        m_xram_rsp_to_init_cmd_cache_id_fifo.simple_get();
+#endif
+      }
+    }
+    ////////////////////////////////////////////////////////////////////////////////////
+    //    CAS to INIT_CMD FIFO
+    ////////////////////////////////////////////////////////////////////////////////////
+
+    if ( cas_to_init_cmd_fifo_put ) {
+      if ( cas_to_init_cmd_fifo_get ) {
+        m_cas_to_init_cmd_inst_fifo.put_and_get(cas_to_init_cmd_fifo_inst);
+        m_cas_to_init_cmd_srcid_fifo.put_and_get(cas_to_init_cmd_fifo_srcid);
+#if L1_MULTI_CACHE
+        m_cas_to_init_cmd_cache_id_fifo.put_and_get(cas_to_init_cmd_fifo_cache_id);
+#endif
+      } else {
+          m_cas_to_init_cmd_inst_fifo.simple_put(cas_to_init_cmd_fifo_inst);
+          m_cas_to_init_cmd_srcid_fifo.simple_put(cas_to_init_cmd_fifo_srcid);
+#if L1_MULTI_CACHE
+          m_cas_to_init_cmd_cache_id_fifo.simple_put(cas_to_init_cmd_fifo_cache_id);
+#endif
+      }
+    } else {
+        if ( cas_to_init_cmd_fifo_get ) {
+            m_cas_to_init_cmd_inst_fifo.simple_get();
+            m_cas_to_init_cmd_srcid_fifo.simple_get();
+#if L1_MULTI_CACHE
+            m_cas_to_init_cmd_cache_id_fifo.simple_get();
+#endif
+      }
+    }
+
+    m_cpt_cycles++;
+
+} // end transition()
+
+/////////////////////////////
+tmpl(void)::genMoore()
+/////////////////////////////
+{
+#if MONITOR_MEMCACHE_FSM
+    p_read_fsm.write      (r_read_fsm.read());
+    p_write_fsm.write     (r_write_fsm.read());
+    p_xram_rsp_fsm.write  (r_xram_rsp_fsm.read());
+    p_cas_fsm.write       (r_cas_fsm.read());
+    p_cleanup_fsm.write   (r_cleanup_fsm.read());
+    p_alloc_heap_fsm.write(r_alloc_heap_fsm.read());
+    p_alloc_dir_fsm.write (r_alloc_dir_fsm.read());
+    p_alloc_trt_fsm.write (r_alloc_trt_fsm.read());
+    p_alloc_upt_fsm.write (r_alloc_upt_fsm.read());
+    p_tgt_cmd_fsm.write   (r_tgt_cmd_fsm.read());
+    p_tgt_rsp_fsm.write   (r_tgt_rsp_fsm.read());
+    p_ixr_cmd_fsm.write   (r_ixr_cmd_fsm.read());
+    p_ixr_rsp_fsm.write   (r_ixr_rsp_fsm.read());
+    p_init_cmd_fsm.write  (r_init_cmd_fsm.read());
+    p_init_rsp_fsm.write  (r_init_rsp_fsm.read());
+#endif
+    ////////////////////////////////////////////////////////////
+    // Command signals on the p_vci_ixr port
+    ////////////////////////////////////////////////////////////
+
+    p_vci_ixr.be      = 0xF;
+    p_vci_ixr.pktid   = 0;
+    p_vci_ixr.srcid   = m_srcid_ixr;
+    p_vci_ixr.cons    = false;
+    p_vci_ixr.wrap    = false;
+    p_vci_ixr.contig  = true;
+    p_vci_ixr.clen    = 0;
+    p_vci_ixr.cfixed  = false;
+
+    if ( r_ixr_cmd_fsm.read() == IXR_CMD_READ_NLINE ) {
+      p_vci_ixr.cmd     = vci_param::CMD_READ;
+      p_vci_ixr.cmdval  = true;
+      p_vci_ixr.address = (addr_t)(r_read_to_ixr_cmd_nline.read()*m_words*4);
+      p_vci_ixr.plen    = m_words*4;
+      p_vci_ixr.wdata   = 0x00000000;
+      p_vci_ixr.trdid   = r_read_to_ixr_cmd_trdid.read();
+      p_vci_ixr.eop     = true;
+    }
+    else if ( r_ixr_cmd_fsm.read() == IXR_CMD_CAS_NLINE ) {
+      if(r_cas_to_ixr_cmd_write.read()){
+        p_vci_ixr.cmd     = vci_param::CMD_WRITE;
+        p_vci_ixr.cmdval  = true;
+        p_vci_ixr.address = (addr_t)((r_cas_to_ixr_cmd_nline.read()*m_words+r_ixr_cmd_cpt.read())*4);
+        p_vci_ixr.plen    = m_words*4;
+        p_vci_ixr.wdata   = r_cas_to_ixr_cmd_data[r_ixr_cmd_cpt.read()].read();
+        p_vci_ixr.trdid   = r_cas_to_ixr_cmd_trdid.read();
+        p_vci_ixr.eop     = (r_ixr_cmd_cpt == (m_words-1));
+      } else {
+        p_vci_ixr.cmd     = vci_param::CMD_READ;
+        p_vci_ixr.cmdval  = true;
+        p_vci_ixr.address = (addr_t)(r_cas_to_ixr_cmd_nline.read()*m_words*4);
+        p_vci_ixr.plen    = m_words*4;
+        p_vci_ixr.wdata   = 0x00000000;
+        p_vci_ixr.trdid   = r_cas_to_ixr_cmd_trdid.read();
+        p_vci_ixr.eop     = true;
+      }
+    }
+    else if ( r_ixr_cmd_fsm.read() == IXR_CMD_WRITE_NLINE ) {
+      if(r_write_to_ixr_cmd_write.read()){
+        p_vci_ixr.cmd     = vci_param::CMD_WRITE;
+        p_vci_ixr.cmdval  = true;
+        p_vci_ixr.address = (addr_t)((r_write_to_ixr_cmd_nline.read()*m_words+r_ixr_cmd_cpt.read())*4);
+        p_vci_ixr.plen    = m_words*4;
+        p_vci_ixr.wdata   = r_write_to_ixr_cmd_data[r_ixr_cmd_cpt.read()].read();
+        p_vci_ixr.trdid   = r_write_to_ixr_cmd_trdid.read();
+        p_vci_ixr.eop     = (r_ixr_cmd_cpt == (m_words-1));
+      } else {
+        p_vci_ixr.cmd     = vci_param::CMD_READ;
+        p_vci_ixr.cmdval  = true;
+        p_vci_ixr.address = (addr_t)(r_write_to_ixr_cmd_nline.read()*m_words*4);
+        p_vci_ixr.plen    = m_words*4;
+        p_vci_ixr.wdata   = 0x00000000;
+        p_vci_ixr.trdid   = r_write_to_ixr_cmd_trdid.read();
+        p_vci_ixr.eop     = true;
+      }
+    }
+    else if ( r_ixr_cmd_fsm.read() == IXR_CMD_XRAM_DATA ) {
+      p_vci_ixr.cmd     = vci_param::CMD_WRITE;
+      p_vci_ixr.cmdval  = true;
+      p_vci_ixr.address = (addr_t)((r_xram_rsp_to_ixr_cmd_nline.read()*m_words+r_ixr_cmd_cpt.read())*4);
+      p_vci_ixr.plen    = m_words*4;
+      p_vci_ixr.wdata   = r_xram_rsp_to_ixr_cmd_data[r_ixr_cmd_cpt.read()].read();
+      p_vci_ixr.trdid   = r_xram_rsp_to_ixr_cmd_trdid.read();
+      p_vci_ixr.eop     = (r_ixr_cmd_cpt == (m_words-1));
+    } else {
+      p_vci_ixr.cmdval  = false;
+      p_vci_ixr.address = 0;
+      p_vci_ixr.plen    = 0;
+      p_vci_ixr.wdata   = 0;
+      p_vci_ixr.trdid   = 0;
+      p_vci_ixr.eop = false;
+    }
+
+    ////////////////////////////////////////////////////
+    // Response signals on the p_vci_ixr port
+    ////////////////////////////////////////////////////
+
+    if ( ((r_alloc_trt_fsm.read() == ALLOC_TRT_IXR_RSP) &&
+          (r_ixr_rsp_fsm.read() == IXR_RSP_TRT_READ)) ||
+        (r_ixr_rsp_fsm.read() == IXR_RSP_ACK) ) p_vci_ixr.rspack = true;
+    else                                        p_vci_ixr.rspack = false;
+
+    ////////////////////////////////////////////////////
+    // Command signals on the p_vci_tgt port
+    ////////////////////////////////////////////////////
+
+    switch ((tgt_cmd_fsm_state_e)r_tgt_cmd_fsm.read()) {
+      case TGT_CMD_IDLE:
+        p_vci_tgt.cmdack  = false;
+        break;
+      case TGT_CMD_READ:
+        p_vci_tgt.cmdack  = m_cmd_read_addr_fifo.wok();
+        break;
+      case TGT_CMD_WRITE:
+        p_vci_tgt.cmdack  = m_cmd_write_addr_fifo.wok();
+        break;
+      case TGT_CMD_CAS:
+        p_vci_tgt.cmdack  = m_cmd_cas_addr_fifo.wok();
+        break;
+      default:
+        p_vci_tgt.cmdack  = false;
+        break;
+    }
+
+    ////////////////////////////////////////////////////
+    // Response signals on the p_vci_tgt port
+    ////////////////////////////////////////////////////
+    switch ( r_tgt_rsp_fsm.read() ) {
+
+      case TGT_RSP_READ_IDLE:
+      case TGT_RSP_WRITE_IDLE:
+      case TGT_RSP_CAS_IDLE:
+      case TGT_RSP_XRAM_IDLE:
+      case TGT_RSP_INIT_IDLE:
+      case TGT_RSP_CLEANUP_IDLE:
+        p_vci_tgt.rspval  = false;
+        p_vci_tgt.rsrcid  = 0;
+        p_vci_tgt.rdata   = 0;
+        p_vci_tgt.rpktid  = 0;
+        p_vci_tgt.rtrdid  = 0;
+        p_vci_tgt.rerror  = 0;
+        p_vci_tgt.reop    = false;
+        break;
+
+      case TGT_RSP_READ:
+      {
+        uint32_t last_word_idx = r_read_to_tgt_rsp_word.read() + r_read_to_tgt_rsp_length - 1;
+        bool     is_last_word  = (r_tgt_rsp_cpt.read() == last_word_idx);
+        bool     is_ll         = ((r_read_to_tgt_rsp_pktid.read() & 0x7) == TYPE_LL);
+
+        p_vci_tgt.rspval  = true;
+
+        if ( is_ll and not r_tgt_rsp_key_sent.read() )
+        {
+          // LL response first flit
+          p_vci_tgt.rdata = r_read_to_tgt_rsp_ll_key.read();
+        }
+        else
+        {
+          // LL response second flit or READ response
+          p_vci_tgt.rdata = r_read_to_tgt_rsp_data[r_tgt_rsp_cpt.read()].read();
+        }
+
+        p_vci_tgt.rsrcid  = r_read_to_tgt_rsp_srcid.read();
+        p_vci_tgt.rtrdid  = r_read_to_tgt_rsp_trdid.read();
+        p_vci_tgt.rpktid  = r_read_to_tgt_rsp_pktid.read();
+        p_vci_tgt.rerror  = 0;
+        p_vci_tgt.reop    = (is_last_word and not is_ll) or (r_tgt_rsp_key_sent.read() and is_ll);
+        break;
+      }
+
+      case TGT_RSP_WRITE:
+        /*if( ((r_write_to_tgt_rsp_pktid.read() & 0x7) == TYPE_SC) )
+            {
+              std::cout << "SC RSP / rsrcid = " << r_write_to_tgt_rsp_srcid.read() << " / rdata = " << r_write_to_tgt_rsp_sc_fail.read() << std::endl;
+            }*/
+        p_vci_tgt.rspval   = true;
+        if( ((r_write_to_tgt_rsp_pktid.read() & 0x7) == TYPE_SC) && r_write_to_tgt_rsp_sc_fail.read() )
+          p_vci_tgt.rdata  = 1;
+        else
+          p_vci_tgt.rdata  = 0;
+        p_vci_tgt.rsrcid   = r_write_to_tgt_rsp_srcid.read();
+        p_vci_tgt.rtrdid   = r_write_to_tgt_rsp_trdid.read();
+        p_vci_tgt.rpktid   = r_write_to_tgt_rsp_pktid.read();
+        //p_vci_tgt.rerror   = 0x2 & ( (1 << vci_param::E) - 1);
+        p_vci_tgt.rerror   = 0;
+        p_vci_tgt.reop     = true;
+        break;
+
+      case TGT_RSP_CLEANUP:
+        p_vci_tgt.rspval   = true;
+        p_vci_tgt.rdata    = 0;
+        p_vci_tgt.rsrcid   = r_cleanup_to_tgt_rsp_srcid.read();
+        p_vci_tgt.rtrdid   = r_cleanup_to_tgt_rsp_trdid.read();
+        p_vci_tgt.rpktid   = r_cleanup_to_tgt_rsp_pktid.read();
+        p_vci_tgt.rerror   = 0; // Can be a CAS rsp
+        p_vci_tgt.reop     = true;
+        break;
+
+      case TGT_RSP_CAS:
+        p_vci_tgt.rspval   = true;
+        p_vci_tgt.rdata    = r_cas_to_tgt_rsp_data.read();
+        p_vci_tgt.rsrcid   = r_cas_to_tgt_rsp_srcid.read();
+        p_vci_tgt.rtrdid   = r_cas_to_tgt_rsp_trdid.read();
+        p_vci_tgt.rpktid   = r_cas_to_tgt_rsp_pktid.read();
+        p_vci_tgt.rerror   = 0;
+        p_vci_tgt.reop     = true;
+        break;
+
+      case TGT_RSP_XRAM:
+      {
+        uint32_t last_word_idx = r_xram_rsp_to_tgt_rsp_word.read() + r_xram_rsp_to_tgt_rsp_length.read() - 1;
+        bool     is_last_word  = (r_tgt_rsp_cpt.read() == last_word_idx);
+        bool     is_ll         = ((r_xram_rsp_to_tgt_rsp_pktid.read() & 0x7) == TYPE_LL);
+        bool     is_error      = r_xram_rsp_to_tgt_rsp_rerror.read();
+
+        p_vci_tgt.rspval  = true;
+
+        if( is_ll and not r_tgt_rsp_key_sent.read() ) {
+          // LL response first flit
+          p_vci_tgt.rdata = r_xram_rsp_to_tgt_rsp_ll_key.read();
+        }
+        else {
+          // LL response second flit or READ response
+          p_vci_tgt.rdata = r_xram_rsp_to_tgt_rsp_data[r_tgt_rsp_cpt.read()].read();
+        }
+
+        p_vci_tgt.rsrcid  = r_xram_rsp_to_tgt_rsp_srcid.read();
+        p_vci_tgt.rtrdid  = r_xram_rsp_to_tgt_rsp_trdid.read();
+        p_vci_tgt.rpktid  = r_xram_rsp_to_tgt_rsp_pktid.read();
+        p_vci_tgt.rerror  = is_error;
+        p_vci_tgt.reop    = (((is_last_word or is_error) and not is_ll) or
+                              (r_tgt_rsp_key_sent.read() and     is_ll));
+        break;
+      }
+
+      case TGT_RSP_INIT:
+        p_vci_tgt.rspval   = true;
+        p_vci_tgt.rdata    = 0; // Can be a CAS or SC rsp
+        p_vci_tgt.rsrcid   = r_init_rsp_to_tgt_rsp_srcid.read();
+        p_vci_tgt.rtrdid   = r_init_rsp_to_tgt_rsp_trdid.read();
+        p_vci_tgt.rpktid   = r_init_rsp_to_tgt_rsp_pktid.read();
+        p_vci_tgt.rerror   = 0;
+        p_vci_tgt.reop     = true;
+        break;
+    } // end switch r_tgt_rsp_fsm
+
+    ///////////////////////////////////////////////////
+    // Command signals on the p_vci_ini port
+    ///////////////////////////////////////////////////
+
+    p_vci_ini.cmd     = vci_param::CMD_WRITE;
+    p_vci_ini.srcid   = m_srcid_ini;
+    p_vci_ini.cons    = true;
+    p_vci_ini.wrap    = false;
+    p_vci_ini.contig  = false;
+    p_vci_ini.clen    = 0;
+    p_vci_ini.cfixed  = false;
+
+    vci_addr_t vci_ini_address = 0;
+    switch ( r_init_cmd_fsm.read() ) {
+
+      case INIT_CMD_UPDT_IDLE:
+      case INIT_CMD_INVAL_IDLE:
+      case INIT_CMD_CAS_UPDT_IDLE:
+        p_vci_ini.cmdval  = false;
+        p_vci_ini.address = 0;
+        p_vci_ini.wdata   = 0;
+        p_vci_ini.be      = 0;
+        p_vci_ini.plen    = 0;
+        p_vci_ini.trdid   = 0;
+        p_vci_ini.pktid   = 0;
+        p_vci_ini.eop     = false;
+        break;
+      case INIT_CMD_INVAL_NLINE:
+      {
+        vci_ini_address = (vci_addr_t)
+            m_xram_rsp_to_init_cmd_srcid_fifo.read() << (vci_param::N - vci_param::S);
+
+        p_vci_ini.cmdval  = m_xram_rsp_to_init_cmd_inst_fifo.rok();
+        if(m_xram_rsp_to_init_cmd_inst_fifo.rok()){
+          if(m_xram_rsp_to_init_cmd_inst_fifo.read()) {
+              p_vci_ini.address = (addr_t) (vci_ini_address+4);
+          } else {
+              p_vci_ini.address = (addr_t) (vci_ini_address);
+          }
+        } else p_vci_ini.address = 0; // prevent segmentation faults by reading an empty fifo
+        p_vci_ini.wdata   = (uint32_t)r_xram_rsp_to_init_cmd_nline.read();
+        p_vci_ini.be      = ((r_xram_rsp_to_init_cmd_nline.read() >> 32) & 0x3);
+        p_vci_ini.plen    = 4;
+        p_vci_ini.trdid   = r_xram_rsp_to_init_cmd_trdid.read();
+#if L1_MULTI_CACHE
+        p_vci_ini.pktid   = m_xram_rsp_to_init_cmd_cache_id_fifo.read();
+#endif
+        p_vci_ini.eop     = true;
+        break;
+      }
+      case INIT_CMD_XRAM_BRDCAST:
+        p_vci_ini.cmdval  = true;
+        p_vci_ini.address = m_broadcast_address;
+        p_vci_ini.wdata   = (uint32_t)r_xram_rsp_to_init_cmd_nline.read();
+        p_vci_ini.be      = ((r_xram_rsp_to_init_cmd_nline.read() >> 32) & 0x3);
+        p_vci_ini.plen    = 4;
+        p_vci_ini.trdid   = r_xram_rsp_to_init_cmd_trdid.read();
+        p_vci_ini.pktid   = 0;
+        p_vci_ini.eop     = true;
+        break;
+
+      case INIT_CMD_WRITE_BRDCAST:
+        p_vci_ini.cmdval  = true;
+        p_vci_ini.address = m_broadcast_address;
+        p_vci_ini.wdata   = (addr_t)r_write_to_init_cmd_nline.read();
+        p_vci_ini.be      = ((r_write_to_init_cmd_nline.read() >> 32) & 0x3);
+        p_vci_ini.plen    = 4 ;
+        p_vci_ini.eop     = true;
+        p_vci_ini.trdid   = r_write_to_init_cmd_trdid.read();
+        p_vci_ini.pktid   = 0;
+        break;
+      case INIT_CMD_UPDT_NLINE:
+        vci_ini_address = (vci_addr_t)
+            m_write_to_init_cmd_srcid_fifo.read() << (vci_param::N - vci_param::S);
+
+        p_vci_ini.cmdval  = m_write_to_init_cmd_inst_fifo.rok();
+        if(m_write_to_init_cmd_inst_fifo.rok()){
+          if(m_write_to_init_cmd_inst_fifo.read()) {
+            p_vci_ini.address = (addr_t)(vci_ini_address + 12);
+          } else {
+            p_vci_ini.address = (addr_t)(vci_ini_address + 8);
+          }
+        } else {
+          p_vci_ini.address = 0;
+        }
+        p_vci_ini.wdata   = (uint32_t)r_write_to_init_cmd_nline.read();
+        p_vci_ini.be      = ((r_write_to_init_cmd_nline.read() >> 32 ) & 0x3);
+        p_vci_ini.plen    = 4 * (r_write_to_init_cmd_count.read() + 2);
+        p_vci_ini.eop     = false;
+        p_vci_ini.trdid   = r_write_to_init_cmd_trdid.read();
+#if L1_MULTI_CACHE
+        p_vci_ini.pktid   = m_write_to_init_cmd_cache_id_fifo.read();
+#endif
+        break;
+      case INIT_CMD_UPDT_INDEX:
+        vci_ini_address = (vci_addr_t)
+            m_write_to_init_cmd_srcid_fifo.read() << (vci_param::N - vci_param::S);
+
+        p_vci_ini.cmdval  = true;
+        if(m_write_to_init_cmd_inst_fifo.read()) {
+          p_vci_ini.address = (addr_t)(vci_ini_address + 12);
+        } else {
+          p_vci_ini.address = (addr_t)(vci_ini_address + 8);
+        }
+        p_vci_ini.wdata   = r_write_to_init_cmd_index.read();
+        p_vci_ini.be      = 0xF;
+        p_vci_ini.plen    = 4 * (r_write_to_init_cmd_count.read() + 2);
+        p_vci_ini.trdid   = r_write_to_init_cmd_trdid.read();
+#if L1_MULTI_CACHE
+        p_vci_ini.pktid   = m_write_to_init_cmd_cache_id_fifo.read();
+#endif
+        p_vci_ini.eop     = false;
+        break;
+      case INIT_CMD_UPDT_DATA:
+        vci_ini_address = (vci_addr_t)
+            m_write_to_init_cmd_srcid_fifo.read() << (vci_param::N - vci_param::S);
+
+        p_vci_ini.cmdval  = true;
+        if(m_write_to_init_cmd_inst_fifo.read()) {
+          p_vci_ini.address = (addr_t)(vci_ini_address + 12);
+        } else {
+          p_vci_ini.address = (addr_t)(vci_ini_address + 8);
+        }
+        p_vci_ini.wdata   = r_write_to_init_cmd_data[r_init_cmd_cpt.read() +
+          r_write_to_init_cmd_index.read()].read();
+        p_vci_ini.be      = r_write_to_init_cmd_be[r_init_cmd_cpt.read() +
+            r_write_to_init_cmd_index.read()].read()  ;
+        p_vci_ini.plen    = 4 * (r_write_to_init_cmd_count.read() + 2);
+        p_vci_ini.trdid   = r_write_to_init_cmd_trdid.read();
+#if L1_MULTI_CACHE
+        p_vci_ini.pktid   = m_write_to_init_cmd_cache_id_fifo.read();
+#endif
+        p_vci_ini.eop     = ( r_init_cmd_cpt.read() == (r_write_to_init_cmd_count.read()-1) );
+        break;
+
+      case INIT_CMD_CAS_BRDCAST:
+        p_vci_ini.cmdval  = true;
+        p_vci_ini.address = m_broadcast_address;
+        p_vci_ini.wdata   = (addr_t)r_cas_to_init_cmd_nline.read();
+        p_vci_ini.be      = ((r_cas_to_init_cmd_nline.read() >> 32) & 0x3);
+        p_vci_ini.plen    = 4 ;
+        p_vci_ini.eop     = true;
+        p_vci_ini.trdid   = r_cas_to_init_cmd_trdid.read();
+        p_vci_ini.pktid   = 0;
+        break;
+      case INIT_CMD_CAS_UPDT_NLINE:
+        vci_ini_address = (vci_addr_t)
+            m_cas_to_init_cmd_srcid_fifo.read() << (vci_param::N - vci_param::S);
+
+        p_vci_ini.cmdval  = m_cas_to_init_cmd_inst_fifo.rok();
+        if(m_cas_to_init_cmd_inst_fifo.rok()){
+          if( m_cas_to_init_cmd_inst_fifo.read() ) {
+            p_vci_ini.address = (addr_t)(vci_ini_address + 12);
+          } else {
+            p_vci_ini.address = (addr_t)(vci_ini_address + 8);
+          }
+        } else {
+          p_vci_ini.address = 0;
+        }
+        p_vci_ini.wdata   = (uint32_t)r_cas_to_init_cmd_nline.read();
+        p_vci_ini.be      = ((r_cas_to_init_cmd_nline.read() >> 32 ) & 0x3);
+        if(r_cas_to_init_cmd_is_long.read()){
+            p_vci_ini.plen    = 4 * 4;
+        } else {
+            p_vci_ini.plen    = 4 * 3;
+        }
+        p_vci_ini.eop     = false;
+        p_vci_ini.trdid   = r_cas_to_init_cmd_trdid.read();
+#if L1_MULTI_CACHE
+        p_vci_ini.pktid   = m_cas_to_init_cmd_cache_id_fifo.read();
+#endif
+        break;
+      case INIT_CMD_CAS_UPDT_INDEX:
+        vci_ini_address = (vci_addr_t)
+            m_cas_to_init_cmd_srcid_fifo.read() << (vci_param::N - vci_param::S);
+
+        p_vci_ini.cmdval  = true;
+        if( m_cas_to_init_cmd_inst_fifo.read() ) {
+          p_vci_ini.address = (addr_t)(vci_ini_address + 12);
+        } else {
+          p_vci_ini.address = (addr_t)(vci_ini_address + 8);
+        }
+        p_vci_ini.wdata   = r_cas_to_init_cmd_index.read();
+        p_vci_ini.be      = 0xF;
+        if(r_cas_to_init_cmd_is_long.read()){
+            p_vci_ini.plen    = 4 * 4;
+        } else {
+            p_vci_ini.plen    = 4 * 3;
+        }
+        p_vci_ini.trdid   = r_cas_to_init_cmd_trdid.read();
+#if L1_MULTI_CACHE
+        p_vci_ini.pktid   = m_cas_to_init_cmd_cache_id_fifo.read();
+#endif
+        p_vci_ini.eop     = false;
+        break;
+      case INIT_CMD_CAS_UPDT_DATA:
+        vci_ini_address = (vci_addr_t)
+            m_cas_to_init_cmd_srcid_fifo.read() << (vci_param::N - vci_param::S);
+
+        p_vci_ini.cmdval  = true;
+        if( m_cas_to_init_cmd_inst_fifo.read() ) {
+          p_vci_ini.address = (addr_t)(vci_ini_address + 12);
+        } else {
+          p_vci_ini.address = (addr_t)(vci_ini_address + 8);
+        }
+        p_vci_ini.wdata   = r_cas_to_init_cmd_wdata.read();
+        p_vci_ini.be      = 0xF;
+        p_vci_ini.trdid   = r_cas_to_init_cmd_trdid.read();
+#if L1_MULTI_CACHE
+        p_vci_ini.pktid   = m_cas_to_init_cmd_cache_id_fifo.read();
+#endif
+        if(r_cas_to_init_cmd_is_long.read()){
+            p_vci_ini.plen    = 4 * 4;
+            p_vci_ini.eop     = false;
+        } else {
+            p_vci_ini.plen    = 4 * 3;
+            p_vci_ini.eop     = true;
+        }
+        break;
+      case INIT_CMD_CAS_UPDT_DATA_HIGH:
+        vci_ini_address = (vci_addr_t)
+            m_cas_to_init_cmd_srcid_fifo.read() << (vci_param::N - vci_param::S);
+
+        p_vci_ini.cmdval  = true;
+        if( m_cas_to_init_cmd_inst_fifo.read() ) {
+          p_vci_ini.address = (addr_t)(vci_ini_address + 12);
+        } else {
+          p_vci_ini.address = (addr_t)(vci_ini_address + 8);
+        }
+        p_vci_ini.wdata   = r_cas_to_init_cmd_wdata_high.read();
+        p_vci_ini.be      = 0xF;
+        p_vci_ini.plen    = 4 * 4;
+        p_vci_ini.trdid   = r_cas_to_init_cmd_trdid.read();
+#if L1_MULTI_CACHE
+        p_vci_ini.pktid   = m_cas_to_init_cmd_cache_id_fifo.read();
+#endif
+        p_vci_ini.eop     = true;
+        break;
+
+    } // end switch r_init_cmd_fsm
+
+    //////////////////////////////////////////////////////
+    // Response signals on the p_vci_ini port
+    //////////////////////////////////////////////////////
+
+    if ( r_init_rsp_fsm.read() == INIT_RSP_IDLE ) p_vci_ini.rspack  = true;
+    else                                          p_vci_ini.rspack  = false;
+
+    //////////////////////////////////////////////////////
+    // Response signals on the p_vci_tgt_cleanup port
+    //////////////////////////////////////////////////////
+    p_vci_tgt_cleanup.rspval = false;
+    p_vci_tgt_cleanup.rsrcid = 0;
+    p_vci_tgt_cleanup.rdata  = 0;
+    p_vci_tgt_cleanup.rpktid = 0;
+    p_vci_tgt_cleanup.rtrdid = 0;
+    p_vci_tgt_cleanup.rerror = 0;
+    p_vci_tgt_cleanup.reop   = false;
+    p_vci_tgt_cleanup.cmdack = false ;
+
+    switch(r_cleanup_fsm.read()){
+      case CLEANUP_IDLE:
+        {
+          p_vci_tgt_cleanup.cmdack = true ;
+          break;
+        }
+      case CLEANUP_RSP:
+        {
+          p_vci_tgt_cleanup.rspval = true;
+          p_vci_tgt_cleanup.rdata  = 0;
+          p_vci_tgt_cleanup.rsrcid = r_cleanup_srcid.read();
+          p_vci_tgt_cleanup.rpktid = r_cleanup_pktid.read();
+          p_vci_tgt_cleanup.rtrdid = r_cleanup_trdid.read();
+          p_vci_tgt_cleanup.rerror = 0x2 & ( (1 << vci_param::E) - 1);
+          p_vci_tgt_cleanup.reop   = 1;
+          break;
+        }
+
+    }
+
+} // end genMoore()
+
+}} // end name space
+
+// Local Variables:
+// tab-width: 2
+// c-basic-offset: 2
+// c-file-offsets:((innamespace . 0)(inline-open . 0))
+// indent-tabs-mode: nil
+// End:
+
+// vim: filetype=cpp:expandtab:shiftwidth=2:tabstop=2:softtabstop=2
Index: branches/v4/modules/vci_profiler/caba/metadata/vci_profiler.sd
===================================================================
--- branches/v4/modules/vci_profiler/caba/metadata/vci_profiler.sd	(revision 371)
+++ branches/v4/modules/vci_profiler/caba/metadata/vci_profiler.sd	(revision 371)
@@ -0,0 +1,32 @@
+
+# -*- python -*-
+
+__id__ = "$Id: vci_profiler.sd 2060 2011-02-20 Ghassan $"
+__version__ = "$Revision: 2060 $"
+
+Module('caba:vci_profiler',
+	classname = 'soclib::caba::VciProfiler',
+	   tmpl_parameters = [
+	parameter.Module('vci_param',  default = 'caba:vci_param'),
+        parameter.Module('iss_t'),
+	],
+	header_files = ['../source/include/vci_profiler.h',],
+	implementation_files = ['../source/src/vci_profiler.cpp',],
+			  ports = [
+	Port('caba:vci_monitor', 'p_vci'),
+	Port('caba:bit_in', 'p_resetn', auto = 'resetn'),
+	Port('caba:clock_in', 'p_clk', auto = 'clock'),
+	],
+	uses = [
+		Uses('caba:base_module'),
+		Uses('common:mapping_table'),
+		Uses('caba:vci_buffers'),
+                Uses('config:config'),
+                Uses('common:iss2'),
+                Uses('caba:vci_cc_vcache_wrapper2_v1'),
+		],
+	instance_parameters = [
+	],
+	   extensions = [
+   ],
+)
Index: branches/v4/modules/vci_profiler/caba/source/include/vci_profiler.h
===================================================================
--- branches/v4/modules/vci_profiler/caba/source/include/vci_profiler.h	(revision 371)
+++ branches/v4/modules/vci_profiler/caba/source/include/vci_profiler.h	(revision 371)
@@ -0,0 +1,148 @@
+/* -*- c++ -*-
+ *
+ * SOCLIB_LGPL_HEADER_BEGIN
+ * 
+ * This file is part of SoCLib, GNU LGPLv2.1.
+ * 
+ * SoCLib is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU Lesser General Public License as published
+ * by the Free Software Foundation; version 2.1 of the License.
+ * 
+ * SoCLib is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * Lesser General Public License for more details.
+ * 
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with SoCLib; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301 USA
+ * 
+ * SOCLIB_LGPL_HEADER_END
+ *
+ * Copyright (c) UPMC, Lip6
+ *         Ghassan Almaless <ghassan.almaless@lip6.fr>, 2011
+ *
+ * Maintainers: Ghassan
+ */
+#ifndef SOCLIB_CABA_VCI_PROFILER_H
+#define SOCLIB_CABA_VCI_PROFILER_H
+
+#include <systemc>
+#include <iostream>
+#include <fstream>
+#include "vci_monitor.h"
+#include "vci_buffers.h"
+#include "caba_base_module.h"
+#include "mapping_table.h"
+//#include "config.h"
+#include "vci_cc_vcache_wrapper2_v1.h"
+
+namespace soclib {
+namespace caba {
+
+template<typename vci_param, typename iss_t>
+class VciProfiler
+	: public soclib::caba::BaseModule
+{
+
+protected:
+	SC_HAS_PROCESS(VciProfiler);
+
+public:
+    sc_core::sc_in<bool> p_resetn;
+    sc_core::sc_in<bool> p_clk;
+    soclib::caba::VciMonitor<vci_param> p_vci;
+
+    VciProfiler(
+              sc_core::sc_module_name insname,
+              size_t index, 
+              size_t x_id,
+              size_t y_id,
+              size_t x_width,
+              size_t y_width,
+              size_t addr_width);
+
+    void print_stats(void);
+    void clear_stats(void);
+    void set_limits(unsigned long limit1, unsigned long limit2);
+    void set_L1_cache(VciCcVCacheWrapper2V1<vci_param, iss_t> *l1);
+    ~VciProfiler();
+
+private:
+
+#define VCI_CMD_NR              4+7      // TODO: define vci_param::CMD_NR 
+
+
+    struct cmd_info_s
+    {
+        unsigned long trans;
+        unsigned long cost;
+        unsigned long remote;
+        unsigned long rcost;
+        unsigned long limit1;
+        unsigned long limit2;
+        unsigned long rmax_time;
+        unsigned long rmax_cost;
+        unsigned long raddr;
+        unsigned long lmax_time;
+        unsigned long lmax_cost;
+        unsigned long flits;
+        unsigned long rflits;
+        unsigned long distance;
+        unsigned long max_dist;
+        unsigned long d1_limit;
+        unsigned long d2_limit;
+    } m_cmd_tbl[VCI_CMD_NR]; 
+    
+    unsigned long m_index;
+    unsigned long m_xWidth;
+    unsigned long m_yWidth;
+    unsigned long m_width;
+    long m_x;
+    long m_y;
+    unsigned long m_bits;
+
+    unsigned long m_tm_now;
+    unsigned long m_tm_start;
+    unsigned long m_last_cmd;
+    unsigned long m_last_addr;
+    unsigned long m_limit1;
+    unsigned long m_limit2;
+    unsigned long m_d1_limit;
+    unsigned long m_d2_limit;
+    unsigned long m_period;
+    unsigned long m_threshold;
+    unsigned long m_debug_cntr;
+    bool m_isPending;
+    bool m_isCMDPending;
+    bool m_isPeriod;
+    bool m_isRemote;
+    bool m_isInstruction;
+    bool m_isDebug;
+
+    VciCcVCacheWrapper2V1<vci_param, iss_t> *m_l1;
+
+    unsigned long m_exchange_cntr;
+    unsigned long m_access_cntr;
+    unsigned long m_remote_cntr;
+    unsigned long m_cycles_cntr;
+    
+    //std::ofstream m_log;
+
+    void transition();
+};
+
+}}
+
+#endif /* SOCLIB_CABA_VCI_PROFILER_H */
+
+// Local Variables:
+// tab-width: 4
+// c-basic-offset: 4
+// c-file-offsets:((innamespace . 0)(inline-open . 0))
+// indent-tabs-mode: nil
+// End:
+
+// vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4
+
Index: branches/v4/modules/vci_profiler/caba/source/src/vci_profiler.cpp
===================================================================
--- branches/v4/modules/vci_profiler/caba/source/src/vci_profiler.cpp	(revision 371)
+++ branches/v4/modules/vci_profiler/caba/source/src/vci_profiler.cpp	(revision 371)
@@ -0,0 +1,448 @@
+/* -*- c++ -*-
+ *
+ * SOCLIB_LGPL_HEADER_BEGIN
+ * 
+ * This file is part of SoCLib, GNU LGPLv2.1.
+ * 
+ * SoCLib is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU Lesser General Public License as published
+ * by the Free Software Foundation; version 2.1 of the License.
+ * 
+ * SoCLib is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * Lesser General Public License for more details.
+ * 
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with SoCLib; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301 USA
+ * 
+ * SOCLIB_LGPL_HEADER_END
+ *
+ * Copyright (c) UPMC, Lip6
+ *         Ghassan Almaless <ghassan.almaless@lip6.fr>, 2011
+ *
+ * Maintainers: Ghassan
+ */
+
+#include "vci_profiler.h"
+#include <cstring>
+#include <iostream>
+#include "vci_buffers.h"
+#include <iostream>
+#include <iomanip>
+#include <cassert>
+#include <vector>
+
+namespace soclib {
+namespace caba {
+
+#define tmpl(...) template<typename vci_param, typename iss_t> __VA_ARGS__ VciProfiler<vci_param, iss_t>
+
+#define ABS(x) (((x) < 0) ? -(x) : (x))
+
+#define VCI_iRD_CMD             4
+#define VCI_iTLB_RD_CMD         5
+#define VCI_iTLB_LL_CMD         6
+#define VCI_iTLB_SC_CMD         7
+#define VCI_DTLB_RD_CMD         8
+#define VCI_DTLB_LL_CMD         9
+#define VCI_DTLB_SC_CMD         10
+
+#define _CMD_ITLB               0x1
+#define _CMD_DTLB               0x2   
+#define _CMD_USR                0x4
+
+static const char* vci_cmd_names[VCI_CMD_NR] = {"SC_CMD ", 
+                                                "RD_CMD ", 
+                                                "WR_CMD ", 
+                                                "LL_CMD ", 
+                                                "iRD_CMD",
+                                                "iTLB_RD_CMD",
+                                                "iTLB_LL_CMD",
+                                                "iTLB_SC_CMD",
+                                                "DTLB_RD_CMD",
+                                                "DTLB_LL_CMD",
+                                                "DTLB_SC_CMD"};
+
+tmpl(void)::print_stats()
+{
+    unsigned long local_cntr;
+    unsigned long total_cost;
+    unsigned long total_flits;
+    unsigned long total_rflits;
+    unsigned long total_estmtd_enrg;
+    std::ostream &output = m_l1->m_log;
+
+    if(m_period == 0)
+        return;
+    
+    total_cost        = 0;
+    total_flits       = 0;
+    total_rflits      = 0;
+    total_estmtd_enrg = 0;
+    
+    local_cntr = m_access_cntr - m_remote_cntr;
+    
+    output << name() << " Cycles: " << std::dec << m_tm_now << std::endl 
+           << "Access_Rate  = " << (double)  m_access_cntr / m_cycles_cntr << std::endl
+           << "Remote_%     = " << (double)  m_remote_cntr / m_access_cntr << std::endl
+           << "LL_%         = " << (double)  m_cmd_tbl[vci_param::CMD_LOCKED_READ].trans / m_access_cntr << std::endl
+           << "SC_%         = " << (double)  m_cmd_tbl[vci_param::CMD_STORE_COND].trans  / m_access_cntr << std::endl;
+    
+    for(long i = 0; i < VCI_CMD_NR; i++)
+    {
+
+        local_cntr = m_cmd_tbl[i].distance * m_cmd_tbl[i].rflits;
+
+        output << vci_cmd_names[i] << " [" 
+               << m_cmd_tbl[i].trans << ", "
+               << m_cmd_tbl[i].remote << ", "
+               << m_cmd_tbl[i].trans - m_cmd_tbl[i].remote  << ", "
+               << m_cmd_tbl[i].cost << ", "
+               << m_cmd_tbl[i].rcost << ", "
+               << m_cmd_tbl[i].cost - m_cmd_tbl[i].rcost << ", "
+               << m_cmd_tbl[i].limit1 << ", "
+               << m_cmd_tbl[i].limit2 << ", "
+               << m_cmd_tbl[i].rmax_cost << ", "
+               << m_cmd_tbl[i].rmax_time << ", "
+               << m_cmd_tbl[i].lmax_cost << ", "
+               << m_cmd_tbl[i].lmax_time << ", "
+               << m_cmd_tbl[i].flits <<  ", " 
+               << m_cmd_tbl[i].rflits << ", " << std::hex
+               << m_cmd_tbl[i].raddr << ", " << std::dec 
+               << m_cmd_tbl[i].distance << ","
+               << m_cmd_tbl[i].d1_limit << ","
+               << m_cmd_tbl[i].d2_limit << ","
+               << m_cmd_tbl[i].max_dist << ","
+               << local_cntr << "]" << std::endl;
+
+        total_cost        += m_cmd_tbl[i].cost;
+        total_flits       += m_cmd_tbl[i].flits;
+        total_rflits      += m_cmd_tbl[i].rflits;
+        total_estmtd_enrg += local_cntr;
+    }
+    
+    output << "Total_CMDs         = " << m_access_cntr << std::endl
+           << "Total_Cost         = " << total_cost << std::endl
+           << "Total_Flits        = " << total_flits << std::endl
+           << "Total_Remote_Flits = " << total_rflits << std::endl 
+           << "Total_Estmtd_Enrg  = " << total_estmtd_enrg << std::endl;
+}
+
+tmpl(void)::clear_stats()
+{
+    memset(m_cmd_tbl, 0, sizeof(m_cmd_tbl));
+    m_access_cntr = 0;
+    m_remote_cntr = 0;
+    m_cycles_cntr = 0;
+}
+
+
+tmpl(void)::set_limits(unsigned long limit1, unsigned long limit2)
+{
+    m_limit1 = limit1;
+    m_limit2 = limit2;
+}
+
+tmpl(void)::set_L1_cache(VciCcVCacheWrapper2V1<vci_param, iss_t> *l1)
+{
+    m_l1 = l1;
+}
+
+
+tmpl()::VciProfiler(
+                  sc_core::sc_module_name insname,
+                  size_t index, 
+                  size_t x_id,
+                  size_t y_id,
+                  size_t x_width,
+                  size_t y_width,
+                  size_t addr_width)
+	: BaseModule(insname),
+      p_resetn("resetn"),
+      p_clk("clk"),
+      p_vci("vci")
+{
+    clear_stats();
+    m_index        = index;
+    m_x            = x_id;
+    m_y            = y_id;
+    m_xWidth       = x_width;
+    m_yWidth       = y_width;
+    m_width        = x_width + y_width;
+    m_bits         = addr_width;
+    m_tm_now       = 0;
+    m_tm_start     = 0;
+    m_isPending    = false;
+    m_isCMDPending = false;
+    m_isPeriod     = false;
+    m_isDebug      = false;
+    m_last_cmd     = 0;
+    m_limit1       = 0;
+    m_limit2       = 0;
+    m_d1_limit     = 0;
+    m_d2_limit     = 0;
+    m_period       = 0;
+    m_debug_cntr   = 0;
+    m_threshold    = 1000000;
+
+    char *ptr = getenv("TSAR_PROFILER_PERIOD");
+
+    if(ptr != NULL)
+        m_period = atol(ptr);
+
+    ptr = getenv("TSAR_PROFILER_THRESHOLD");
+
+    if(ptr != NULL)
+        m_threshold = atol(ptr);
+
+    ptr = getenv("TSAR_PROFILER_DEBUG");
+
+    if(ptr != NULL)
+        m_isDebug = (atol(ptr) != 0) ? true : false;
+
+    ptr = getenv("TSAR_PROFILER_LIMIT1");
+
+    if(ptr != NULL)
+        m_limit1 = atol(ptr);
+
+    ptr = getenv("TSAR_PROFILER_LIMIT2");
+
+    if(ptr != NULL)
+        m_limit2 = atol(ptr);
+
+    ptr = getenv("TSAR_PROFILER_D1_LIMIT");
+
+    if(ptr != NULL)
+        m_d1_limit = atol(ptr);
+
+    ptr = getenv("TSAR_PROFILER_D2_LIMIT");
+
+    if(ptr != NULL)
+        m_d2_limit = atol(ptr);
+
+#if 0    
+    if(m_period != 0)
+        m_log.open(insname, std::ios::out);
+#endif
+
+	SC_METHOD(transition);
+	dont_initialize();
+	sensitive << p_clk.pos();
+}
+
+tmpl()::~VciProfiler()
+{
+}
+
+tmpl(void)::transition()
+{
+    unsigned long cmd;
+    unsigned long shift;
+    unsigned long msb;
+    long x_coord;
+    long y_coord;
+    unsigned long distance;
+    unsigned long cost;
+    bool isUser;
+    
+    std::ostream &output = m_l1->m_log;
+
+    if(m_period == 0)
+        return;
+
+    if( p_vci.cmdval.read() && p_vci.cmdack.read() )
+    {
+        if(m_isPending == false)
+        {
+            m_isCMDPending = true;
+            m_isPending    = true;
+            m_tm_start     = m_tm_now;
+            cmd            = p_vci.cmd.read();
+            m_access_cntr ++;
+
+            if((cmd == vci_param::CMD_READ) && (p_vci.trdid.read() > 1))
+                cmd = VCI_iRD_CMD;
+            
+            else if((cmd == vci_param::CMD_READ) && (p_vci.pktid.read() & _CMD_ITLB))
+                cmd = VCI_iTLB_RD_CMD;
+
+            else if((cmd == vci_param::CMD_READ) && (p_vci.pktid.read() & _CMD_DTLB))
+                cmd = VCI_DTLB_RD_CMD;
+
+            else if((cmd == vci_param::CMD_LOCKED_READ) && (p_vci.pktid.read() & _CMD_ITLB))
+                cmd = VCI_iTLB_LL_CMD;
+
+            else if((cmd == vci_param::CMD_LOCKED_READ) && (p_vci.pktid.read() & _CMD_DTLB))
+                cmd = VCI_DTLB_LL_CMD;
+
+            else if((cmd == vci_param::CMD_STORE_COND) && (p_vci.pktid.read() & _CMD_ITLB))
+                cmd = VCI_iTLB_SC_CMD;
+
+            else if((cmd == vci_param::CMD_STORE_COND) && (p_vci.pktid.read() & _CMD_DTLB))
+                cmd = VCI_DTLB_SC_CMD;
+
+            m_last_cmd  = cmd;
+            m_last_addr = p_vci.address.read();
+            m_cmd_tbl[cmd].trans ++;
+            m_cmd_tbl[cmd].flits += ((p_vci.plen.read() / 4) + 1);
+
+            shift    = m_bits - m_width;
+            msb      = m_last_addr >> shift;
+            distance = 0;
+
+            m_isRemote = (msb == m_index) ? false : true;
+            
+            if(m_isRemote == true)
+            {
+                isUser   = (p_vci.pktid.read() & _CMD_USR) ? true : false;
+                m_cmd_tbl[cmd].remote ++;
+                m_remote_cntr ++;
+                x_coord  = msb >> m_yWidth;
+                y_coord  = msb & ((1 << m_yWidth) - 1);
+                distance = ABS(m_x - x_coord) + ABS(m_y - y_coord);
+                
+                output << ">> " << vci_cmd_names[cmd] 
+                       << "\t(" << m_x << "," << m_y << ") --> (" 
+                       << x_coord << "," << y_coord << ")\t[ D: " 
+                       << distance << " @: " << std::hex << m_last_addr << std::dec 
+                       << " T: " << m_tm_now << " "<< ((isUser) ? "U" : "K") << " ]" << std::endl;
+                
+                m_cmd_tbl[cmd].rflits += ((p_vci.plen.read() / 4) + 1);
+                m_cmd_tbl[cmd].distance += distance;
+                
+                if(distance > m_cmd_tbl[cmd].max_dist)
+                    m_cmd_tbl[cmd].max_dist = distance;
+                
+                if(distance >= m_d2_limit)
+                    m_cmd_tbl[cmd].d2_limit ++;
+                else if(distance >= m_d1_limit)
+                    m_cmd_tbl[cmd].d1_limit ++;
+            }
+
+#if 1
+            if(m_isDebug)
+            {
+                output << ">>> " << std::dec
+                       << "Cycle: "<< m_tm_now
+                       << ", Addr " << std::hex << m_last_addr 
+                       << ", isRemote " << m_isRemote
+                       << ", Distance " << distance
+                       << ", " << vci_cmd_names[m_last_cmd];
+            }
+#endif
+        }
+
+        if(p_vci.eop.read())
+            m_isPending = false;
+    }
+
+    if ( p_vci.rspval.read() && p_vci.rspack.read() )
+    {
+        if( p_vci.reop.read() )
+        {
+            m_isCMDPending = false;
+            cost = m_tm_now - m_tm_start;
+
+            m_cmd_tbl[m_last_cmd].cost += cost;
+            
+            if(m_isRemote == true)
+                m_cmd_tbl[m_last_cmd].rcost += cost;
+
+            if(cost > m_limit2)
+                m_cmd_tbl[m_last_cmd].limit2 ++;
+            else if(cost > m_limit1) 
+                m_cmd_tbl[m_last_cmd].limit1 ++;
+
+            if(m_isRemote == true)
+            {   
+                if(cost > m_cmd_tbl[m_last_cmd].rmax_cost)
+                {
+                    m_cmd_tbl[m_last_cmd].rmax_time = m_tm_now;
+                    m_cmd_tbl[m_last_cmd].rmax_cost = cost;
+                    m_cmd_tbl[m_last_cmd].raddr = m_last_addr;
+                }
+            }
+            else
+            {
+                if(cost > m_cmd_tbl[m_last_cmd].lmax_cost)
+                {
+                    m_cmd_tbl[m_last_cmd].lmax_time = m_tm_now;
+                    m_cmd_tbl[m_last_cmd].lmax_cost = cost;
+                }
+            }
+#if 1
+            if(m_isDebug)
+            {
+                output << "  <<< " << std::dec
+                       << "Cycle: "<< m_tm_now
+                       << ", Cost: " << cost 
+                       << ", Addr " << std::hex << m_last_addr 
+                       << ", " << vci_cmd_names[m_last_cmd]
+                       << std::endl;
+            }
+#endif
+        }
+    }
+
+    m_tm_now ++;
+    m_cycles_cntr ++;
+
+#if 1
+    if((m_isCMDPending == true) && ((m_tm_now - m_tm_start) > m_threshold) && (m_isDebug == false))
+    {
+        output << "Threshold is reached: " << std::dec
+               << "Tm_now: " << m_tm_now 
+               << " Tm_start: " << m_tm_start
+               << " Val: " << m_tm_now - m_tm_start
+               << " Threshold: " << m_threshold
+               << std::endl;
+
+        m_isDebug = true;
+    }
+
+    if(m_isDebug == true)
+    {
+        m_l1->print_trace(0);
+        m_debug_cntr ++;
+    }
+
+    if(m_debug_cntr > 30)
+    {
+        m_isDebug = false;
+        print_stats();
+    }
+#endif
+
+    if((m_period != 0) && ((m_tm_now % m_period) == 0))
+    {
+        output << "Period reached, " << std::dec
+               << m_period << ", "
+               << m_tm_now << ", "
+               << m_isPeriod << ", "
+               << m_isCMDPending << std::endl;
+            
+        m_isPeriod = true;
+    }
+
+    if((m_isPeriod == true) && (m_isCMDPending == false))
+    {
+        print_stats();
+        clear_stats();
+        m_isPeriod = false;
+    }
+}
+
+}}
+
+// Local Variables:
+// tab-width: 4
+// c-basic-offset: 4
+// c-file-offsets:((innamespace . 0)(inline-open . 0))
+// indent-tabs-mode: nil
+// End:
+
+// vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4
+
Index: branches/v4/modules/vci_synthetic_initator/caba/metadata/vci_synthetic_initiator.sd
===================================================================
--- branches/v4/modules/vci_synthetic_initator/caba/metadata/vci_synthetic_initiator.sd	(revision 371)
+++ branches/v4/modules/vci_synthetic_initator/caba/metadata/vci_synthetic_initiator.sd	(revision 371)
@@ -0,0 +1,35 @@
+# -*- python -*-
+
+Module('caba:vci_synthetic_initiator',
+       classname = 'soclib::caba::VciSyntheticInitiator',
+       tmpl_parameters = [parameter.Module('vci_param', default = 'caba:vci_param'),],
+       header_files = ['../sources/include/vci_synthetic_initiator.h',
+                       ],
+       implementation_files = ['../sources/src/vci_synthetic_initiator.cpp',],
+       uses = [Uses('caba:base_module'),
+               Uses('common:mapping_table'),
+               Uses('caba:generic_fifo'),
+               ],
+       ports = [Port('caba:vci_initiator','p_vci'),
+                Port('caba:bit_in', 'p_resetn', auto = 'resetn'),
+                Port('caba:clock_in', 'p_clk', auto = 'clock'),],
+       instance_parameters = [
+                parameter.Module('mt'),
+                parameter.IntTab('vci_index'),
+                parameter.Int('length'),
+		parameter.Int('rho'),
+                parameter.Int('depth'),
+		parameter.Int('xmesh'),
+		parameter.Int('ymesh'),
+		parameter.Int('bc_period', default = 0),
+		parameter.Int('xmin', default = 0),
+		parameter.Int('xmax', default = 0),
+		parameter.Int('ymin', default = 0),
+		parameter.Int('ymax', default = 0),
+                ],
+       extensions = [
+          'dsx:get_ident='
+          'vci_ini_index:p_vci:mt,'
+       ],
+)
+
Index: branches/v4/modules/vci_synthetic_initator/caba/sources/include/vci_synthetic_initiator.h
===================================================================
--- branches/v4/modules/vci_synthetic_initator/caba/sources/include/vci_synthetic_initiator.h	(revision 371)
+++ branches/v4/modules/vci_synthetic_initator/caba/sources/include/vci_synthetic_initiator.h	(revision 371)
@@ -0,0 +1,170 @@
+/* -*- c++ -*-
+ * File         : vci_synthetic_initiator.h
+ * Date         : 26/08/2010
+ * Copyright    : UPMC / LIP6
+ * Authors      : Christophe Choichillon
+ * Version	: 2.1
+ * 
+ * SOCLIB_LGPL_HEADER_BEGIN
+ *
+ * This file is part of SoCLib, GNU LGPLv2.1.
+ *
+ * SoCLib is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU Lesser General Public License as published
+ * by the Free Software Foundation; version 2.1 of the License.
+ *
+ * SoCLib is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with SoCLib; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301 USA
+ *
+ * SOCLIB_LGPL_HEADER_END
+ *
+ * Versions :
+ *           - 1.0 Sending only one request at a time
+ *	     - 2.0 Sending multiple transactions and broadcast responses 
+ *		   identified with pktid (deprecated)
+ *	     - 2.1 Broadcast responses identified with the value 0 of trdid
+ *
+ * Maintainers: christophe.choichillon@lip6.fr
+ */
+
+#ifndef SOCLIB_CABA_SYNTHETIC_INITIATOR_H
+#define SOCLIB_CABA_SYNTHETIC_INITIATOR_H
+
+#include <cassert>
+#include <systemc>
+#include <inttypes.h>
+#include "generic_fifo.h"
+#include "vci_initiator.h"
+#include "soclib_endian.h"
+#include "caba_base_module.h"
+#include "int_tab.h"
+#include "mapping_table.h"
+#include "arithmetics.h"
+
+namespace soclib {  namespace caba {
+    using namespace sc_core;
+
+    template<typename vci_param>
+    class VciSyntheticInitiator
+      : public soclib::caba::BaseModule
+    {
+      typedef uint32_t addr_t;
+      typedef uint32_t data_t;
+      typedef uint32_t tag_t;
+      typedef uint32_t size_t;
+      typedef uint32_t be_t;
+      typedef uint32_t copy_t;
+
+
+      /* States of the VCI CMD fsm */
+      enum vci_fsm_state_e{
+	VCI_IDLE,
+	VCI_SINGLE_SEND,
+	VCI_BC_SEND,
+	VCI_SINGLE_REGISTER
+      };
+
+      enum bc_fsm_state_e{
+      	BC_RSP_IDLE,
+	BC_RSP_WAIT_RSP
+      };
+
+    protected:
+
+      SC_HAS_PROCESS(VciSyntheticInitiator);
+    
+    public:
+      sc_in<bool> 			  	p_clk;
+      sc_in<bool> 			  	p_resetn;
+      soclib::caba::VciInitiator<vci_param> 	p_vci;	
+
+      VciSyntheticInitiator(
+		sc_module_name name,
+		const soclib::common::MappingTable &mt,
+		const soclib::common::IntTab       &vci_index,
+		const uint32_t length,    // Packet length (flit numbers)
+		const uint32_t rho,       // Packets ratio on the network
+		const uint32_t depth,     // Fifo depth
+		const uint32_t xmesh,	
+		const uint32_t ymesh,
+		const uint32_t bc_period = 0, // Broadcast period, if no broadcast => 0
+		const uint32_t xmin = 0, 
+		const uint32_t xmax = 0,
+		const uint32_t ymin = 0,
+		const uint32_t ymax = 0
+		);                                 
+
+      ~VciSyntheticInitiator();
+
+      void transition();
+
+      void genMoore();
+
+      uint32_t destAdress();
+
+      uint32_t destAdress(uint32_t *rand_seed);
+
+      void printStats();
+
+      double getLatencySingle();
+
+      double getLatencyBC();
+
+      void print_trace();
+
+    private:
+
+      // Component attributes
+      const size_t   		  m_length;		// Number of words to write
+      const size_t		  m_rho;		// offered load * 1000
+      const size_t		  m_depth;     		// Fifo depth
+      const size_t		  m_xmesh;	
+      const size_t		  m_ymesh;
+      const size_t		  m_bc_period; 		// Broadcast period, if no broadcast => 0
+      const size_t		  m_xmin; 
+      const size_t		  m_xmax;
+      const size_t		  m_ymin;
+      const size_t		  m_ymax;
+      const size_t		  m_srcid;
+      static const size_t 	  m_tab_size = 1 << vci_param::T;
+
+
+      // Fifo transmitting requests from the generator FSM to the VCI FSM
+      GenericFifo<uint64_t>    	r_date_fifo;
+      GenericFifo<bool>    	r_bc_fifo;
+
+      // VCI CMD FSM
+      sc_signal<int>           	r_cmd_fsm;
+      sc_signal<addr_t>		r_cmd_address;  // Address for the single transaction
+      sc_signal<int>		r_cmd_trdid;	// TRDID for the single transaction
+      sc_signal<size_t>    	r_cmd_count;    // Numbers of words sent
+      sc_signal<uint32_t>	r_cmd_seed;	// seed for reproducible address generation 
+
+      // Broadcast FSM
+      sc_signal<uint32_t>	r_bc_nrsp;	   // Expected number of responses for a broadcast command
+      sc_signal<uint32_t>       r_time_to_next_bc; // Time to wait between 2 BC
+	
+      // Pending transaction FSMs
+      sc_signal<bool>*		r_pending_fsm;  // FSM states
+      sc_signal<uint64_t>*	r_pending_date; // single transaction requested date
+
+      // Instrumentation registers
+      sc_signal<uint64_t>	r_cpt_cycles;   // Local time 
+      sc_signal<uint64_t>	r_cpt_period;   // Number of cycles between 2 broadcast transactions
+      sc_signal<size_t>      	r_nb_single;	// Total number of single transactions
+      sc_signal<uint64_t>  	r_latency_single;	// Total cumulated latency for single transactions
+      sc_signal<size_t>		r_nb_bc;	// Total number of bc transactions
+      sc_signal<uint64_t>	r_latency_bc;	// Total cumulated latency for broadcast transactions
+
+    }; // end class VciSyntheticInitiator
+ 
+  }}
+
+#endif
Index: branches/v4/modules/vci_synthetic_initator/caba/sources/src/vci_synthetic_initiator.cpp
===================================================================
--- branches/v4/modules/vci_synthetic_initator/caba/sources/src/vci_synthetic_initiator.cpp	(revision 371)
+++ branches/v4/modules/vci_synthetic_initator/caba/sources/src/vci_synthetic_initiator.cpp	(revision 371)
@@ -0,0 +1,501 @@
+
+/* -*- c++ -*-
+ * File 	: vci_synthetic_initiator.cpp
+ * Date 	: 23/12/2010
+ * Copyright 	: UPMC / LIP6
+ * Authors 	: Christophe Choichillon
+ * Version	: 2.1
+ *
+ * SOCLIB_LGPL_HEADER_BEGIN
+ *
+ * This file is part of SoCLib, GNU LGPLv2.1.
+ *
+ * SoCLib is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU Lesser General Public License as published
+ * by the Free Software Foundation; version 2.1 of the License.
+ *
+ * SoCLib is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with SoCLib; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301 USA
+ *
+ * SOCLIB_LGPL_HEADER_END
+ *
+ * Maintainers: christophe.choichillon@lip6.fr
+ */
+
+#include "../include/vci_synthetic_initiator.h"
+#include <iostream>
+
+
+//#define DETERMINISTIC
+#define RANDOM_PERIOD
+
+namespace soclib { namespace caba {
+
+
+#define tmpl(x) template<typename vci_param> x VciSyntheticInitiator<vci_param>
+
+  //using soclib::common::uint32_log2;	
+  
+  ////////////////////////////////
+  // 	Constructor 
+  ////////////////////////////////
+
+  tmpl(/**/)::VciSyntheticInitiator( 
+      sc_module_name name,
+      const soclib::common::MappingTable &mt,
+      const soclib::common::IntTab       &vci_index,
+      const uint32_t length,    // Packet length (flit numbers)
+      const uint32_t rho,       // Offered load * 1000
+      const uint32_t depth,     // Fifo depth
+      const uint32_t xmesh,	
+      const uint32_t ymesh,
+      const uint32_t bc_period, // Broadcast period, if no broadcast => 0
+      const uint32_t xmin, 
+      const uint32_t xmax,
+      const uint32_t ymin,
+      const uint32_t ymax
+      )
+
+    : soclib::caba::BaseModule(name),
+
+    p_clk("clk"),
+    p_resetn("resetn"),
+    p_vci("vci_ini"),
+    //  FIFOs 
+    m_srcid( mt.indexForId(vci_index) ),
+    m_length(length),
+    m_rho(rho),
+    m_depth(depth),
+    m_xmesh(xmesh),
+    m_ymesh(ymesh),
+    m_bc_period(bc_period),
+    m_xmin(xmin),
+    m_xmax(xmax),
+    m_ymin(ymin),
+    m_ymax(ymax),
+    r_date_fifo("r_date_fifo", m_depth),
+    r_bc_fifo("r_bc_fifo", m_depth),
+    r_cmd_fsm("r_cmd_fsm"),
+    r_cmd_address("r_cmd_address"),  		
+    r_cmd_trdid("r_cmd_trdid"),	
+    r_cmd_count("r_cmd_count"),  	
+    r_cmd_seed("r_cmd_seed"),	
+    r_bc_nrsp("r_bc_nrsp"),	
+    r_cpt_cycles("r_cpt_cycles"),  		
+    r_cpt_period("r_cpt_period"),  		
+    r_nb_single("r_nb_single"),	
+    r_latency_single("r_latency_single"),	
+    r_nb_bc("r_nb_bc"),	
+    r_latency_bc("r_latency_bc"),
+    r_time_to_next_bc("r_time_to_next_bc")
+{
+
+      r_pending_fsm = new sc_signal<bool>[m_tab_size];
+      r_pending_date = new sc_signal<uint64_t>[m_tab_size];
+
+      SC_METHOD(transition);
+      dont_initialize();
+      sensitive << p_clk.pos();
+
+      SC_METHOD(genMoore);
+      dont_initialize();
+      sensitive << p_clk.neg();
+
+    } // end constructor
+
+
+  /////////////////////////////////
+  tmpl(/**/)::~VciSyntheticInitiator()
+    /////////////////////////////////
+  {
+	delete r_pending_fsm;
+	delete r_pending_date;
+  }
+
+  ///////////////////////////////////
+  tmpl(uint32_t)::destAdress()
+  ///////////////////////////////////
+  {
+    return (uint32_t) (rand() % (m_xmesh * m_ymesh)) ;
+  }
+
+
+  ///////////////////////////////////
+  tmpl(uint32_t)::destAdress(uint32_t *rand_seed)
+  ///////////////////////////////////
+  {
+    return (uint32_t) (rand_r(rand_seed) % (m_xmesh * m_ymesh)) ;
+  }
+
+  //////////////////////////////////
+  tmpl(double)::getLatencySingle()
+  //////////////////////////////////
+  {
+	if (m_rho) 
+	  return (double)(r_latency_single.read())/(double)(r_nb_single.read());
+	else
+	  return 0;
+
+  }
+
+  //////////////////////////////////
+  tmpl(double)::getLatencyBC()
+  //////////////////////////////////
+  {
+	double latency = (double)r_latency_bc.read();
+	double nb      = (double)r_nb_bc.read();
+	std::cout << "Latency BC : " <<std::dec << latency << " nb_bc : " << nb << std::endl;
+	if(m_bc_period)
+	  return (latency/nb);
+	else
+	  return 0;
+
+  }
+
+  //////////////////////////////////
+  tmpl(void)::print_trace()
+  //////////////////////////////////
+  {
+  	const char* state_cmd_str[] = { "IDLE",
+				        "SINGLE_SEND",
+					"BC_SEND"};
+
+	const char* state_bc_rsp_str[] = {"IDLE",
+					  "WAIT_RSP"};
+
+	std::cout << "Vci_Synthetic_Initiator " << name()
+		  << " : " << std::dec << r_cpt_cycles.read() << " cycles " 
+		  << " : state_cmd_fsm = " << state_cmd_str[r_cmd_fsm] 
+		  << " : state_rsp_fsm = " << state_bc_rsp_str[r_pending_fsm[0].read()] 
+		  << " Adresse to send : " << std::hex << r_cmd_address.read()
+		  << " Number of BC_RSP to receive : " << std::dec << r_bc_nrsp.read() 
+		  << " Number of packets sent : " << std::dec << r_nb_single.read() << " " << r_cmd_trdid.read() 
+		  << " Number of BC sent : " << r_nb_bc.read()
+		  << " Cycles to the next BC : " << r_time_to_next_bc.read()  
+		  << " FIFO status : " << r_date_fifo.filled_status() << std::endl;
+	for(int i = 0; i < (1<<vci_param::T) ; i++){
+	  std::cout << "ID : " << i << " " << (uint64_t)(r_pending_date[i].read()) << std::endl;
+	}
+  }
+
+  //////////////////////////////////
+  tmpl(void)::printStats()
+  //////////////////////////////////
+  {
+  	std::cout << name() << " : "<< std::dec << r_cpt_cycles.read() << " cycles, " << r_nb_single.read() << " packets sent" << std::endl;
+	if (m_rho) 
+	{
+	  std::cout << "Average latency : " << (double)(r_latency_single.read())/(double)(r_nb_single.read()) << std::endl;
+	}
+	if(m_bc_period)
+	{
+	  std::cout << "Number of broadcast sent and received : " << r_nb_bc.read() << std::endl;
+	  std::cout << "Average latency : " << ((double)r_latency_bc.read()/(double)r_nb_bc.read()) << std::endl;
+	}
+  }
+
+  //////////////////////////////////
+  tmpl(void)::transition()
+  //////////////////////////////////
+  {
+    //  RESET          
+    if ( ! p_resetn.read() ) 
+    {
+      // Initializing seed for random numbers generation
+
+//#ifndef DETERMINISTIC
+//      srand(time(NULL));
+//#endif
+
+      // Initializing FSMs
+      r_cmd_fsm = VCI_IDLE;
+      for(size_t i=0 ; i<m_tab_size ; i++) r_pending_fsm[i] = false;
+
+      // Initializing FIFOs 
+      r_date_fifo.init();
+      r_bc_fifo.init();
+
+      // Initializing the instrumentation registers
+      r_latency_single 		= 0;
+      r_nb_single		= 0;
+      r_latency_bc 		= 0;
+      r_nb_bc			= 0;
+      r_cpt_cycles		= 0;
+      r_cpt_period		= 0;
+      
+      r_cmd_seed       		= (uint32_t)m_srcid;
+      
+      //std::cout << name() << " " << std::dec << m_bc_period << std::endl;
+
+      if (m_bc_period){
+        uint32_t a = (uint32_t)(rand()%(2*m_bc_period));
+	//std::cout << name() << " " << std::dec << a << std::endl;
+        r_time_to_next_bc		= a;
+      } else {
+	//std::cout << "c'est 0 " << std::endl;
+        r_time_to_next_bc		= 0;
+      }
+
+      return;
+    }
+
+    bool    fifo_put = false;
+    bool    fifo_get = false;
+    bool    fifo_bc  = false;
+
+
+#ifdef DETERMINISTIC
+    uint32_t m_local_seed ;
+#endif
+
+    //////////////////
+    // VCI CMD FSM 
+    //////////////////
+    switch ( r_cmd_fsm.read() ) {
+      case VCI_IDLE:
+        {
+	  if (r_date_fifo.rok())
+          {
+	    if ( r_bc_fifo.read() == true )	// its a broadcast request
+            {
+	      if ( r_pending_fsm[0].read() == false )	// no current broadcast
+              {
+		//std::cout << name() << "SENDING BC" << std::endl;
+	        r_cmd_fsm = VCI_BC_SEND ;
+		r_cmd_address = 0x3 | (0x7c1f << vci_param::N-20) ;
+              }
+            }
+            else			// its a single request
+            {
+	      int id = -1;
+	      for(size_t i = 1; i < m_tab_size; i++){  	// ID 0 reserved for broadcast transactions
+	        if( r_pending_fsm[i].read() == false )
+                {
+		  id = (int)i;
+		  break;
+		}
+	      }
+	      if(id != -1){
+	        r_cmd_fsm = VCI_SINGLE_SEND ;
+	        r_cmd_count = 0;
+                r_cmd_trdid = id;
+	      }
+#ifdef DETERMINISTIC
+	      m_local_seed = r_cmd_seed.read();
+	      r_cmd_address = destAdress(&m_local_seed) << (vci_param::N)-(soclib::common::uint32_log2((uint32_t)m_xmesh)+soclib::common::uint32_log2((uint32_t)m_ymesh));
+	      r_cmd_seed = m_local_seed;
+#else
+	      r_cmd_address = destAdress() << (vci_param::N)-(soclib::common::uint32_log2((uint32_t)m_xmesh)+soclib::common::uint32_log2((uint32_t)m_ymesh));
+#endif
+	    }
+	  }
+          break;
+        }
+      case VCI_SINGLE_SEND:
+        {
+	  if ( p_vci.cmdack.read())
+          {
+	    r_cmd_count = r_cmd_count.read() + 1;
+	    if (r_cmd_count.read() == m_length-1) 
+            {
+	      //r_nb_single = r_nb_single.read() + 1;
+	      r_cmd_fsm = VCI_SINGLE_REGISTER ;
+	    }
+	  }
+          break;
+        }
+      case VCI_SINGLE_REGISTER:
+        {
+	  r_pending_date[r_cmd_trdid.read()] = (uint64_t)(r_date_fifo.read());
+          r_pending_fsm[r_cmd_trdid.read()] = true;
+          fifo_get = true;
+	  r_cmd_fsm = VCI_IDLE;
+          break;
+	}
+      case VCI_BC_SEND:
+        {
+	  if (p_vci.cmdack.read()) 
+          {
+	    //std::cout << std::dec << r_cpt_cycles.read() << "ns " << name() << " BC SEND " << r_nb_bc.read() << " " << r_time_to_next_bc.read() << std::endl;
+	    r_bc_nrsp = (m_xmax - m_xmin) * (m_ymax - m_ymin) ;
+	    r_pending_fsm[0] = true;
+	    r_pending_date[0] = (uint64_t)(r_date_fifo.read());
+	    fifo_get = true;
+	    r_cmd_fsm = VCI_IDLE;
+            break;
+	  }
+        }
+    } // end switch vci_fsm
+
+    
+    ///////////////////
+    // PENDING FSMs
+    //////////////////
+    if(p_vci.rspval.read())
+    {
+      if(p_vci.rtrdid.read() == 0)	// not a broadcast
+      {
+	assert( ( r_pending_fsm[0].read() == true ) && 
+                "illegal broadcast response received");
+	r_bc_nrsp = r_bc_nrsp.read() - 1 ;
+	if(r_bc_nrsp.read() == 1) 
+	{
+	  r_pending_fsm[0] = false;
+          r_latency_bc = r_latency_bc.read() + (r_cpt_cycles.read() - r_pending_date[0].read());
+	  //std::cout << std::dec << r_cpt_cycles.read() << "ns " << name() << " BC done " << std::endl;
+	}
+      }
+      else
+      {
+        assert( ( r_pending_fsm[(int)p_vci.rtrdid.read()] == true ) && 
+                "illegal single response received");
+        r_pending_fsm[p_vci.rtrdid.read()] = false;
+	r_latency_single = r_latency_single.read() + 
+                           (r_cpt_cycles.read() - r_pending_date[(int)p_vci.rtrdid.read()].read());
+      }
+    }
+
+    ////////////////////////
+    //  traffic regulator
+    ////////////////////////
+    if ( m_bc_period && (r_cpt_period.read() > r_time_to_next_bc.read()) )
+    { 
+      fifo_put = true ;
+      fifo_bc  = true;
+      if (r_date_fifo.wok())   
+      {
+        r_nb_bc = r_nb_bc.read() + 1;
+//        r_cpt_period = 0;
+//#ifdef RANDOM_PERIOD
+//	r_time_to_next_bc = (uint32_t)(rand()%(2*m_bc_period));
+//#endif
+      }
+    }
+    else if( ( (uint64_t)(m_rho*r_cpt_cycles.read()) > (uint64_t)(m_length*r_nb_single.read()*1000)) )
+    {
+      fifo_put = true ;
+      fifo_bc  = false;
+      if (r_date_fifo.wok())   r_nb_single = r_nb_single.read() + 1;
+    }
+
+    if ( m_bc_period && (r_cpt_period.read() > r_time_to_next_bc.read()) && r_date_fifo.wok() ) 
+    {
+#ifdef RANDOM_PERIOD
+      r_time_to_next_bc = (uint32_t)(rand()%(2*m_bc_period));
+#endif
+      r_cpt_period = 0;
+    }
+    else
+      r_cpt_period = r_cpt_period.read() + 1;
+
+    ////////////////////////
+    //  update fifos
+    ////////////////////////
+    if (fifo_put){
+      if (fifo_get){
+        r_date_fifo.put_and_get(r_cpt_cycles.read());
+        r_bc_fifo.put_and_get(fifo_bc);
+      } else {
+        r_date_fifo.simple_put(r_cpt_cycles.read());
+        r_bc_fifo.simple_put(fifo_bc);
+      }
+    } else {
+      if (fifo_get){
+        r_date_fifo.simple_get();
+        r_bc_fifo.simple_get();
+      }
+    }
+   
+    ///////////////////////////
+    //  increment local time
+    ///////////////////////////
+    r_cpt_cycles = r_cpt_cycles.read() + 1;
+
+    return;
+
+  } // end transition()
+
+  /////////////////////////////
+  tmpl(void)::genMoore()
+  /////////////////////////////
+  {
+    ////////////////////////////////////////////////////////////
+    // Command signals on the p_vci port
+    ////////////////////////////////////////////////////////////
+     p_vci.cmd        = vci_param::CMD_WRITE;   
+     p_vci.be         = 0xF;                             
+     p_vci.srcid      = m_srcid;   
+     p_vci.cons       = false;        
+     p_vci.wrap       = false;       
+     p_vci.contig     = true;       
+     p_vci.clen       = 0;         
+     p_vci.cfixed     = false;           
+     p_vci.rspack     = true;
+
+
+    switch ( r_cmd_fsm.read() ) {
+
+      //////////////////
+      case VCI_IDLE:
+        {
+	  p_vci.cmdval  = false;                 
+	  p_vci.address = 0; 
+	  p_vci.plen    = 0;                                         
+	  p_vci.wdata   = 0;                                       
+	  p_vci.trdid   = 0;                  
+	  p_vci.pktid      = 0;      
+	  p_vci.eop     = false;                                   
+          break;
+        }
+        //////////////////
+      case VCI_SINGLE_SEND:
+        {
+	  p_vci.cmdval  = true;                 
+	  p_vci.address = (addr_t)(r_cmd_address.read() + (r_cmd_count.read()*4)); 
+	  p_vci.plen    = m_length*4;                                         
+	  p_vci.wdata   = 0;                                       
+	  p_vci.trdid   = r_cmd_trdid.read();                  
+	  p_vci.pktid   = 0;      
+	  if (r_cmd_count.read() == m_length - 1 ) {
+	    p_vci.eop     = true;                                   
+	  } else {
+	    p_vci.eop     = false;                                   
+	  }
+          break;
+        }
+        ///////////////////
+      case VCI_BC_SEND:
+        {
+       	  p_vci.cmdval  = true;                 
+	  p_vci.address = (addr_t) r_cmd_address.read(); 
+	  p_vci.plen    = 4;                                         
+	  p_vci.wdata   = 0;                                       
+	  p_vci.trdid   = 0;                  
+          p_vci.pktid   = 0;      
+	  p_vci.eop     = true;                                   
+          break;
+        }
+      //////////////////
+      case VCI_SINGLE_REGISTER:
+        {
+	  p_vci.cmdval  = false;                 
+	  p_vci.address = 0; 
+	  p_vci.plen    = 0;                                         
+	  p_vci.wdata   = 0;                                       
+	  p_vci.trdid   = 0;                  
+	  p_vci.pktid   = 0;      
+	  p_vci.eop     = false;                                   
+          break;
+        }
+    } // end switch vci_cmd_fsm
+
+  } // end genMoore()
+
+}} // end name space
Index: branches/v4/modules/vci_synthetic_target/caba/metadata/vci_synthetic_target.sd
===================================================================
--- branches/v4/modules/vci_synthetic_target/caba/metadata/vci_synthetic_target.sd	(revision 371)
+++ branches/v4/modules/vci_synthetic_target/caba/metadata/vci_synthetic_target.sd	(revision 371)
@@ -0,0 +1,36 @@
+
+# -*- python -*-
+
+Module('caba:vci_synthetic_target',
+	classname = 'soclib::caba::VciSyntheticTarget',
+	   tmpl_parameters = [
+	parameter.Module('vci_param',  default = 'caba:vci_param'),
+	],
+	header_files = ['../source/include/vci_synthetic_target.h',],
+	implementation_files = ['../source/src/vci_synthetic_target.cpp',],
+			  ports = [
+	Port('caba:vci_target', 'p_vci'),
+	Port('caba:bit_in', 'p_resetn', auto = 'resetn'),
+	Port('caba:clock_in', 'p_clk', auto = 'clock'),
+	],
+	uses = [
+		Uses('caba:base_module'),
+	 	Uses('common:linked_access_buffer', 
+			 addr_t = parameter.StringExt('sc_dt::sc_uint<%d>', parameter.Reference('addr_size')),
+			 id_t = parameter.StringExt('sc_dt::sc_uint<%d>', parameter.Reference('srcid_size'))),
+		Uses('common:loader'),
+		Uses('common:mapping_table'),
+		],
+	instance_parameters = [
+	parameter.IntTab('ident'),
+	parameter.Module('mt', 'common:mapping_table'),
+	parameter.Module('loader', 'common:loader', auto='env:loader'),
+	parameter.Int('latency'),
+	],
+	   extensions = [
+	'dsx:addressable=ident',
+	'dsx:get_ident=ident:p_vci:mt',
+    'dsx:obtain_ident_method=param:ident',
+	'dsx:mapping_type=memory',
+   ],
+)
Index: branches/v4/modules/vci_synthetic_target/caba/source/include/vci_synthetic_target.h
===================================================================
--- branches/v4/modules/vci_synthetic_target/caba/source/include/vci_synthetic_target.h	(revision 371)
+++ branches/v4/modules/vci_synthetic_target/caba/source/include/vci_synthetic_target.h	(revision 371)
@@ -0,0 +1,140 @@
+/* -*- c++ -*-
+ *
+ * SOCLIB_LGPL_HEADER_BEGIN
+ * 
+ * This file is part of SoCLib, GNU LGPLv2.1.
+ * 
+ * SoCLib is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU Lesser General Public License as published
+ * by the Free Software Foundation; version 2.1 of the License.
+ * 
+ * SoCLib is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * Lesser General Public License for more details.
+ * 
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with SoCLib; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301 USA
+ * 
+ * SOCLIB_LGPL_HEADER_END
+ *
+ * Copyright (c) UPMC, Lip6, Asim
+ *         Christophe Choichillon <choichillon.christophe@gmail.com>, 2011
+ *
+ * Maintainers: Christophe Choichillon
+ */
+#ifndef SOCLIB_CABA_VCI_SYNTHETIC_TARGET_H
+#define SOCLIB_CABA_VCI_SYNTHETIC_TARGET_H
+
+#include <systemc>
+#include <vector>
+#include <list>
+#include <cassert>
+#include "caba_base_module.h"
+#include "vci_target.h"
+#include "mapping_table.h"
+#include "int_tab.h"
+#include "loader.h"
+#include "linked_access_buffer.h"
+#include "soclib_endian.h"
+
+namespace soclib {
+namespace caba {
+
+using namespace sc_core;
+
+template<typename vci_param>
+class VciSyntheticTarget
+	: public soclib::caba::BaseModule
+{
+public:
+
+	typedef typename vci_param::data_t  vci_data_t;
+	typedef typename vci_param::addr_t  vci_addr_t;
+	typedef typename vci_param::be_t    vci_be_t;
+	typedef typename vci_param::srcid_t vci_srcid_t;
+	typedef typename vci_param::trdid_t vci_trdid_t;
+	typedef typename vci_param::pktid_t vci_pktid_t;
+
+	typedef uint32_t       ram_t;
+
+    enum fsm_state_e {
+        FSM_IDLE,
+        FSM_CMD_GET,
+        FSM_CMD_WRITE,
+        FSM_CMD_ERROR,
+        FSM_RSP_READ,
+        FSM_RSP_WRITE,
+        FSM_RSP_LL,
+        FSM_RSP_SC,
+        FSM_RSP_ERROR,
+    };
+
+private:
+
+    soclib::common::Loader                  m_loader;
+    std::list<soclib::common::Segment>      m_seglist;
+    const uint32_t			    m_latency;
+
+    soclib::common::LinkedAccessBuffer<
+        vci_addr_t, vci_srcid_t>            r_llsc_buf;
+
+    sc_signal<int>                          r_fsm_state;
+    sc_signal<size_t>                       r_flit_count;
+    sc_signal<size_t>                       r_seg_index;
+    sc_signal<vci_addr_t>                   r_address;
+    sc_signal<vci_data_t>                   r_wdata;
+    sc_signal<vci_be_t>                     r_be;
+    sc_signal<vci_srcid_t>                  r_srcid;
+    sc_signal<vci_trdid_t>                  r_trdid;
+    sc_signal<vci_pktid_t>                  r_pktid;
+    sc_signal<bool>                         r_contig;
+    sc_signal<uint32_t>                     r_latency_count;
+
+    size_t                                  m_nbseg;
+    ram_t                                   **m_ram;
+    soclib::common::Segment                 **m_seg;
+
+    // Activity counters
+    uint32_t 				m_cpt_read;   // Count READ access
+    uint32_t 				m_cpt_write;  // Count WRITE access
+
+protected:
+
+	SC_HAS_PROCESS(VciSyntheticTarget);
+
+public:
+
+    // Ports
+    sc_in<bool>                             p_resetn;
+    sc_in<bool>                             p_clk;
+    soclib::caba::VciTarget<vci_param>      p_vci;
+
+    VciSyntheticTarget(sc_module_name insname,
+                 const soclib::common::IntTab index,
+                 const soclib::common::MappingTable &mt,
+                 const soclib::common::Loader &loader,
+                 const uint32_t latency = 0);
+
+    ~VciSyntheticTarget();
+
+    void print_trace();
+    void printStatistics();
+
+private:
+
+    bool write(size_t seg, vci_addr_t addr, vci_data_t wdata, vci_be_t be);
+    bool read( size_t seg, vci_addr_t addr, vci_data_t &rdata );
+    void transition();
+    void genMoore();
+    void reload();
+    void reset();
+
+};
+
+}}
+
+#endif 
+
Index: branches/v4/modules/vci_synthetic_target/caba/source/src/vci_synthetic_target.cpp
===================================================================
--- branches/v4/modules/vci_synthetic_target/caba/source/src/vci_synthetic_target.cpp	(revision 371)
+++ branches/v4/modules/vci_synthetic_target/caba/source/src/vci_synthetic_target.cpp	(revision 371)
@@ -0,0 +1,489 @@
+/*
+ *
+ * SOCLIB_LGPL_HEADER_BEGIN
+ * 
+ * This file is part of SoCLib, GNU LGPLv2.1.
+ * 
+ * SoCLib is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU Lesser General Public License as published
+ * by the Free Software Foundation; version 2.1 of the License.
+ * 
+ * SoCLib is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * Lesser General Public License for more details.
+ * 
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with SoCLib; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301 USA
+ * 
+ * SOCLIB_LGPL_HEADER_END
+ *
+ * Copyright (c) UPMC, Lip6, Asim
+ *         Alain Greiner <alain.greiner@lip6.fr>, 2008
+ *         Christophe Choichillon <choichillon.christophe@gmail.com>, 2011
+ *
+ * Maintainers: alain, Christophe Choichillon
+ */
+
+/////////////////////////////////////////////////////////////////////////
+//  This component is a multi-segments Ram controller.
+//
+//  It supports only the compact VCI packets defined 
+//  in the VCI advanced specification:
+//  - A READ burst command packet (such a cache line request) 
+//    contains one single flit. 
+//    The response packet length is defined by the PLEN field.
+//    The zero value for the PLEN field is not supported.
+//    An ERROR response packets contain one single flit,
+//  - WRITE burst command packets at consecutive addresses are supported.
+//    The zero value for the PLEN field is not supported.
+//    Write response packets contain always one single flit.
+//  - The LL & SC command packets are supported, but the packet
+//    must contain one single flit.
+//  The RAM latency is a parameter, that can have a zero value.
+////////////////////////////////////////////////////////////////////////
+//  Implementation note: This component does not contain any FIFO,
+//  and is controlled by a single FSM.
+//  The latency counter is decremented in the IDLE state.
+//  The VCI command is analysed and checked in the CMD_GET state.
+//  - For read, ll or sc commands, the command is acknowledged in
+//  the CMD_STATE. It is executed and the response is sent in the
+//  RSP_READ, RSP_LL or RSP_SC states. 
+//  - For write commands, the command is acknowledged in the CMD_STATE,
+//  or in the CMD_WRITE & CMD_ERROR states in case of bursts.
+//  The command is executed in the CMD_WRITE state, or in the RSP_WRITE
+//  state for the last flit of a burst. The response packet is sent
+//  in the RSP_WRITE state.
+/////////////////////////////////////////////////////////////////////////
+
+#include <iostream>
+#include <cstring>
+#include "vci_synthetic_target.h"
+
+namespace soclib {
+namespace caba {
+
+using namespace soclib;
+
+#define tmpl(x) template<typename vci_param> x VciSyntheticTarget<vci_param>
+
+//////////////////////////
+tmpl(/**/)::VciSyntheticTarget(
+    sc_module_name insname,
+    const soclib::common::IntTab index,
+    const soclib::common::MappingTable &mt,
+    const soclib::common::Loader &loader,
+    const uint32_t latency)
+	: caba::BaseModule(insname),
+      m_loader(loader),
+      m_seglist(mt.getSegmentList(index)),
+      m_latency(latency),
+
+      r_llsc_buf((size_t)(1<<vci_param::S)),
+
+      r_fsm_state("r_fsm_state"),
+      r_flit_count("r_flit_count"),
+      r_seg_index("r_seg_index"),
+      r_address("r_address"),
+      r_wdata("r_wdata"),
+      r_be("r_be"),
+      r_srcid("r_srcid"),
+      r_trdid("r_trdid"),
+      r_pktid("r_pktid"),
+      r_contig("r_contig"),
+      r_latency_count("r_latency_count"),
+
+      m_nbseg(0),
+
+      p_resetn("p_resetn"),
+      p_clk("p_clk"),
+      p_vci("p_vci")
+{
+    SC_METHOD(transition);
+    dont_initialize();
+    sensitive << p_clk.pos();
+
+    SC_METHOD(genMoore);
+    dont_initialize();
+    sensitive << p_clk.neg();
+
+    std::list<soclib::common::Segment>::iterator seg;
+    for ( seg = m_seglist.begin() ; seg != m_seglist.end() ; seg++ )  m_nbseg++;
+ 
+    m_ram = new ram_t*[m_nbseg];
+    m_seg = new soclib::common::Segment*[m_nbseg];
+
+    size_t i = 0;
+    size_t word_size = vci_param::B; // B is VCI's cell size
+    for ( seg = m_seglist.begin() ; seg != m_seglist.end() ; seg++ ) 
+    { 
+        m_ram[i] = new ram_t[(seg->size()+word_size-1)/word_size];
+        m_seg[i] = &(*seg);
+        i++;
+    }
+}
+
+///////////////////////////
+tmpl(/**/)::~VciSyntheticTarget()
+{
+    for (size_t i=0 ; i<m_nbseg ; ++i) delete [] m_ram[i];
+    delete [] m_ram;
+    delete [] m_seg;
+}
+
+/////////////////////
+tmpl(void)::reload()
+{
+    for ( size_t i=0 ; i<m_nbseg ; ++i ) 
+    {
+        m_loader.load(&m_ram[i][0], m_seg[i]->baseAddress(), m_seg[i]->size());
+        for ( size_t addr = 0 ; addr < m_seg[i]->size()/vci_param::B ; ++addr )
+            m_ram[i][addr] = le_to_machine(m_ram[i][addr]);
+    }
+}
+
+////////////////////
+tmpl(void)::reset()
+{
+    for ( size_t i=0 ; i<m_nbseg ; ++i ) std::memset(&m_ram[i][0], 0, m_seg[i]->size()); 
+    m_cpt_read = 0;
+    m_cpt_write = 0;
+    if (m_latency) {
+ 	r_fsm_state = FSM_IDLE;
+        r_latency_count = m_latency - 1;
+    } else {
+	r_fsm_state = FSM_CMD_GET;
+        r_latency_count = 0;
+    }
+    r_llsc_buf.clearAll();
+}
+
+/////////////////////////////////////////////////////////////////////////////
+tmpl(bool)::write(size_t seg, vci_addr_t addr, vci_data_t wdata, vci_be_t be)
+{
+    if ( m_seg[seg]->contains(addr) ) 
+    {
+        size_t index = (size_t)((addr - m_seg[seg]->baseAddress()) / vci_param::B);
+        vci_data_t cur = m_ram[seg][index];
+        vci_data_t mask = vci_param::be2mask(be);
+        m_ram[seg][index] = (cur & ~mask) | (wdata & mask);
+        m_cpt_write++;
+        return true;
+    } 
+    return false;
+}
+
+/////////////////////////////////////////////////////////////////
+tmpl(bool)::read(size_t seg, vci_addr_t addr, vci_data_t &rdata )
+{
+    if ( m_seg[seg]->contains(addr) ) 
+    {
+        size_t index = (size_t)((addr - m_seg[seg]->baseAddress()) / vci_param::B);
+        rdata = m_ram[seg][index];
+        m_cpt_read++;
+        return true;
+    }
+    return false;
+}
+
+//////////////////////////
+tmpl(void)::print_trace()
+{
+    const char* state_str[] = { "IDLE", 
+                                "CMD_GET",
+                                "CMD_WRITE",
+                                "CMD_ERROR",
+                                "RSP_READ",
+                                "RSP_WRITE",
+                                "RSP_LL",
+                                "RSP_SC",
+                                "RSP_ERROR" };
+    std::cout << "Simple_ram " << name() 
+              << " : state = " << state_str[r_fsm_state] 
+              << " / latency_count = " << r_latency_count 
+              << " / flit_count = " << r_flit_count << std::endl;
+}
+
+/////////////////////////
+tmpl(void)::transition()
+{
+    if (!p_resetn) 
+    {
+        reset();
+        reload();
+        return;
+    }
+
+#ifdef SOCLIB_MODULE_DEBUG
+std::cout << "Synthetic_target : " << name() << std::endl;
+std::cout << " fsm_state = " << r_fsm_state 
+          << " latency_count = " << r_latency_count << std::endl;
+#endif
+
+    switch ( r_fsm_state ) {
+    case FSM_IDLE: 	// unreachable state if m_latency == 0 
+    {
+        if ( p_vci.cmdval.read() ) 
+        {
+            if (r_latency_count.read() == 0) 
+            {
+                r_fsm_state = FSM_CMD_GET;
+                r_latency_count = m_latency - 1;
+            } 
+            else 
+            {
+                r_latency_count = r_latency_count.read() - 1;
+            }
+        }				   
+        break;
+    }
+    case FSM_CMD_GET:
+    {
+        if ( !p_vci.cmdval.read() ) break;
+
+        vci_addr_t   address = p_vci.address.read();
+        bool         error = true;
+        for ( size_t index = 0 ; index<m_nbseg  && error ; ++index) 
+        {
+            if(address & 0x3){
+                    error = false;
+            } else {
+                if ( (m_seg[index]->contains(address)) &&
+                     (m_seg[index]->contains(address + p_vci.plen.read() - vci_param::B)) ) 
+                {
+                    error = false;
+                    r_seg_index = index;
+                }
+            }
+        } 
+
+        r_address    = address;
+        r_be         = p_vci.be.read();
+        r_wdata      = p_vci.wdata.read();
+        r_srcid      = p_vci.srcid.read();
+        r_trdid      = p_vci.trdid.read();
+        r_pktid      = p_vci.pktid.read();
+
+        if ( error ) 
+        {
+            if( p_vci.eop.read() )	r_fsm_state = FSM_RSP_ERROR;
+            else			r_fsm_state = FSM_CMD_ERROR;
+        }
+        else
+        {
+            assert( (p_vci.plen.read() != 0) && "VCI command packets should have plen != 0");
+            if ( p_vci.cmd.read() == vci_param::CMD_WRITE ) 
+            {
+                r_contig     = p_vci.contig.read();
+                if( p_vci.eop.read() )  r_fsm_state = FSM_RSP_WRITE;
+                else 			r_fsm_state = FSM_CMD_WRITE;
+            }
+            else if ( p_vci.cmd.read() == vci_param::CMD_READ )
+            {
+                r_flit_count = p_vci.plen.read()/vci_param::B;
+                r_contig     = p_vci.contig.read();
+                r_fsm_state = FSM_RSP_READ;
+                assert( p_vci.eop.read() && "VCI read command packets should be one flit");
+            }
+            else if ( p_vci.cmd.read() == vci_param::CMD_STORE_COND )
+            {
+                r_fsm_state = FSM_RSP_SC;
+                assert( p_vci.eop.read() && "VCI sc command packets should be one flit");
+            }
+            else if ( p_vci.cmd.read() == vci_param::CMD_LOCKED_READ )
+            {
+                r_fsm_state = FSM_RSP_LL;
+                assert( p_vci.eop.read() && "VCI ll command packets should be one flit");
+            }
+        }
+        break;
+    }
+    case FSM_CMD_WRITE:
+    {
+        assert( write (r_seg_index, r_address , r_wdata, r_be ) && "out of bounds access in a write burst" );
+        if ( p_vci.cmdval.read() ) 
+        {
+            vci_addr_t next_address = r_address.read() + (vci_addr_t)vci_param::B;
+            assert( ((r_contig && (next_address == p_vci.address.read())) ||
+                     (!r_contig && (r_address.read() == p_vci.address.read()))) &&
+                        "addresses must be contiguous or constant in a VCI write burst" );
+            r_address   = p_vci.address.read();
+            r_be        = p_vci.be.read();
+            r_wdata     = p_vci.wdata.read();
+            if ( p_vci.eop.read() ) 	 r_fsm_state = FSM_RSP_WRITE;
+        }
+        break;
+    }
+    case FSM_RSP_WRITE:
+    {
+        if (r_address.read() != 0x3)
+            assert( write (r_seg_index, r_address , r_wdata, r_be ) && "out of bounds access in a write burst" );
+        if( p_vci.rspack.read() )
+        { 
+            if( m_latency )	r_fsm_state = FSM_IDLE;
+            else           	r_fsm_state = FSM_CMD_GET;
+        }
+        break;
+    }
+    case FSM_RSP_READ:
+    {
+        if ( p_vci.rspack.read() )
+        {
+            r_flit_count = r_flit_count - 1;
+            if ( r_contig ) 	r_address  = r_address.read() + vci_param::B;
+            if ( r_flit_count == 1) 	// last flit 
+            {
+                if( m_latency )	r_fsm_state = FSM_IDLE;
+                else           	r_fsm_state = FSM_CMD_GET;
+            }
+        }
+        break;
+    }
+    case FSM_CMD_ERROR:
+    {
+        if ( p_vci.cmdval.read() && p_vci.eop.read() )
+        {
+            r_fsm_state = FSM_RSP_ERROR;
+        }
+        break;
+    }
+    case FSM_RSP_ERROR:
+    {
+        if ( p_vci.rspack.read() ) 
+        {
+            if( m_latency )	r_fsm_state = FSM_IDLE;
+            else           	r_fsm_state = FSM_CMD_GET;
+        }
+        break;
+    }
+    case FSM_RSP_LL:
+    {
+        if ( p_vci.rspack.read() ) 
+        {   
+            r_llsc_buf.doLoadLinked(r_address.read(), r_srcid.read());
+            if( m_latency )	r_fsm_state = FSM_IDLE;
+            else           	r_fsm_state = FSM_CMD_GET;
+        }
+        break;
+    }
+    case FSM_RSP_SC:
+    {
+        if ( p_vci.rspack.read() ) 
+        {    
+            if ( r_llsc_buf.isAtomic(r_address.read(), r_srcid.read()) ) 
+            {
+                r_llsc_buf.accessDone(r_address.read());
+                write (r_seg_index, r_address , r_wdata, r_be);
+            }
+            if( m_latency )	r_fsm_state = FSM_IDLE;
+            else           	r_fsm_state = FSM_CMD_GET;
+        }
+        break;
+    }
+    } // end switch fsm_state
+
+} // end transition()
+
+///////////////////////
+tmpl(void)::genMoore()
+{
+    switch ( r_fsm_state ) {
+    case FSM_IDLE:
+    {
+        p_vci.cmdack  = false;
+        p_vci.rspval  = false;
+        p_vci.rdata   = 0;
+        p_vci.rsrcid  = 0;
+        p_vci.rtrdid  = 0;
+        p_vci.rpktid  = 0;
+        p_vci.rerror  = 0;
+        p_vci.reop    = false;
+        break;
+    }
+    case FSM_CMD_GET:
+    case FSM_CMD_WRITE:
+    case FSM_CMD_ERROR:
+    {
+        p_vci.cmdack  = true;
+        p_vci.rspval  = false;
+        p_vci.rdata   = 0;
+        p_vci.rsrcid  = 0;
+        p_vci.rtrdid  = 0;
+        p_vci.rpktid  = 0;
+        p_vci.rerror  = 0;
+        p_vci.reop    = false;
+        break;
+    }
+    case FSM_RSP_WRITE:
+    {
+        p_vci.cmdack  = false;
+        p_vci.rspval  = true;
+        p_vci.rdata   = 0;
+        p_vci.rsrcid  = r_srcid.read();
+        p_vci.rtrdid  = r_trdid.read();
+        p_vci.rpktid  = r_pktid.read();
+        p_vci.rerror  = vci_param::ERR_NORMAL;
+        p_vci.reop    = true;
+        break;
+    }
+    case FSM_RSP_READ:
+    {
+        vci_data_t   rdata;
+        assert( read(r_seg_index, r_address, rdata) && "out of bounds access in a read burst" );
+        p_vci.cmdack = false;
+        p_vci.rspval = true;
+        p_vci.rdata  = rdata;
+        p_vci.rsrcid = r_srcid.read();
+        p_vci.rtrdid = r_trdid.read();
+        p_vci.rpktid = r_pktid.read();
+        p_vci.rerror = vci_param::ERR_NORMAL;
+        p_vci.reop   = (r_flit_count.read() == 1);
+        break;
+    }
+    case FSM_RSP_LL:
+    {
+        vci_data_t   rdata;
+        assert( read(r_seg_index, r_address, rdata) && "out of bounds access in a ll access" );
+        p_vci.cmdack = false;
+        p_vci.rspval = true;
+        p_vci.rdata  = rdata;
+        p_vci.rsrcid = r_srcid.read();
+        p_vci.rtrdid = r_trdid.read();
+        p_vci.rpktid = r_pktid.read();
+        p_vci.rerror = vci_param::ERR_NORMAL;
+        p_vci.reop   = true;
+        break;
+    }
+    case FSM_RSP_SC:
+    {
+        p_vci.cmdack = false;
+        p_vci.rspval = true;
+        if ( r_llsc_buf.isAtomic(r_address.read(), r_srcid.read()) ) p_vci.rdata = 0;
+        else                                                         p_vci.rdata = 1;
+        p_vci.rsrcid = r_srcid.read();
+        p_vci.rtrdid = r_trdid.read();
+        p_vci.rpktid = r_pktid.read();
+        p_vci.rerror = vci_param::ERR_NORMAL;
+        p_vci.reop   = true;
+        break;
+    }
+    case FSM_RSP_ERROR:
+    {
+        p_vci.cmdack  = false;
+        p_vci.rspval  = true;
+        p_vci.rdata   = 0;
+        p_vci.rsrcid  = r_srcid.read();
+        p_vci.rtrdid  = r_trdid.read();
+        p_vci.rpktid  = r_pktid.read();
+        p_vci.rerror  = vci_param::ERR_GENERAL_DATA_ERROR;
+        p_vci.reop    = true;
+        break;
+    }
+    } // end switch fsm_state
+} // end genMoore()
+
+}} 
+
+
Index: branches/v4/modules/vci_vdspin_initiator_wrapper/caba/metadata/vci_vdspin_initiator_wrapper.sd
===================================================================
--- branches/v4/modules/vci_vdspin_initiator_wrapper/caba/metadata/vci_vdspin_initiator_wrapper.sd	(revision 371)
+++ branches/v4/modules/vci_vdspin_initiator_wrapper/caba/metadata/vci_vdspin_initiator_wrapper.sd	(revision 371)
@@ -0,0 +1,25 @@
+
+# -*- python -*-
+
+Module('caba:vci_vdspin_initiator_wrapper',
+		classname = 'soclib::caba::VciVdspinInitiatorWrapper',
+	tmpl_parameters = [
+		parameter.Module('vci_param',  default = 'caba:vci_param'),
+		parameter.Int('dspin_cmd_width'),
+		parameter.Int('dspin_rsp_width'), ],
+        header_files = ['../source/include/vci_vdspin_initiator_wrapper.h', ],
+        implementation_files = ['../source/src/vci_vdspin_initiator_wrapper.cpp',],
+        ports = [
+		Port('caba:vci_initiator', 'p_vci'),
+                Port('caba:dspin_output', 'p_dspin_out', dspin_data_size = parameter.Reference('dspin_cmd_width')),
+                Port('caba:dspin_input', 'p_dspin_in', dspin_data_size = parameter.Reference('dspin_rsp_width')),
+		Port('caba:bit_in', 'p_resetn', auto = 'resetn'),
+		Port('caba:clock_in', 'p_clk', auto = 'clock'), ],
+	uses = [
+		Uses('caba:base_module'),
+		Uses('caba:generic_fifo'),
+		],
+	instance_parameters = [
+		parameter.Int('cmd_fifo_depth'),
+		parameter.Int('rsp_fifo_depth'), ],
+)
Index: branches/v4/modules/vci_vdspin_initiator_wrapper/caba/source/include/vci_vdspin_initiator_wrapper.h
===================================================================
--- branches/v4/modules/vci_vdspin_initiator_wrapper/caba/source/include/vci_vdspin_initiator_wrapper.h	(revision 371)
+++ branches/v4/modules/vci_vdspin_initiator_wrapper/caba/source/include/vci_vdspin_initiator_wrapper.h	(revision 371)
@@ -0,0 +1,128 @@
+/* -*- c++ -*-
+  * File : vci_vdspin_initiator_wrapper.h
+  * Copyright (c) UPMC, Lip6
+  * Author : Alain Greiner
+  *
+  * SOCLIB_LGPL_HEADER_BEGIN
+  *
+  * This file is part of SoCLib, GNU LGPLv2.1.
+  *
+  * SoCLib is free software; you can redistribute it and/or modify it
+  * under the terms of the GNU Lesser General Public License as published
+  * by the Free Software Foundation; version 2.1 of the License.
+  *
+  * SoCLib is distributed in the hope that it will be useful, but
+  * WITHOUT ANY WARRANTY; without even the implied warranty of
+  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+  * Lesser General Public License for more details.
+  *
+  * You should have received a copy of the GNU Lesser General Public
+  * License along with SoCLib; if not, write to the Free Software
+  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+  * 02110-1301 USA
+  *
+  * SOCLIB_LGPL_HEADER_END
+  *
+  * Maintainers: alexandre.joannou@lip6.fr
+  *
+  */
+
+/////////////////////////////////////////////////////////////////////////
+// This component performs the protocol translation between VCI & DSPIN,
+// and can be used to connect a VCI initiator to a DSPIN network.
+// It is implemented as two fully independant sub-components:
+// - translation from a VCI CMD to a DSPIN CMD
+// - translation from a DSPIN RSP to a VCI RSP
+// Each subcomponent contains a FIFO containing DSPIN flits.
+// For the DSPIN interfaces, the widths of the CMD & RSP flits
+// are defined as template parameters for future evolutions,
+// but the VCI to DSPIN translation makes the following assumptions:
+// - DSPIN CMD flit width = 40 bits
+// - DSPIN RSP flit width = 33 bits
+// - VCI address width    <= 40 bits
+// - VCI data             == 32 bits
+// - VCI plen             == 8  bits
+// - VCI srcid            <= 14 bits
+// - VCI trdid            <= 4  bits
+// - VCI pktid            <= 4  bits
+// - VCI rerror           == 1  bit
+////////////////////////////////////////////////////////////////////////
+
+#ifndef VCI_VDSPIN_INITIATOR_WRAPPER_H_
+#define VCI_VDSPIN_INITIATOR_WRAPPER_H_
+
+#include <systemc>
+#include <assert.h>
+#include "caba_base_module.h"
+#include "vci_target.h"
+#include "generic_fifo.h"
+#include "dspin_interface.h"
+
+namespace soclib { namespace caba {
+
+template<typename vci_param, int dspin_cmd_width, int dspin_rsp_width>
+class VciVdspinInitiatorWrapper
+    : public soclib::caba::BaseModule
+{
+    // Command FSM
+    enum fsm_state_cmd{
+    CMD_IDLE,
+    CMD_BROADCAST,
+    CMD_READ,
+    CMD_WRITE,
+    CMD_WDATA,
+    };
+
+    // Response FSM
+    enum fsm_state_rsp{
+    RSP_IDLE,
+    RSP_DSPIN_SINGLE_FLIT,
+    RSP_DSPIN_MULTI_FLIT,
+    };
+
+protected:
+    SC_HAS_PROCESS(VciVdspinInitiatorWrapper);
+
+public:
+    // ports
+    sc_core::sc_in<bool>                                    p_clk;
+    sc_core::sc_in<bool>                                    p_resetn;
+    soclib::caba::DspinOutput<dspin_cmd_width>              p_dspin_out;
+    soclib::caba::DspinInput<dspin_rsp_width>               p_dspin_in;
+    soclib::caba::VciTarget<vci_param>                      p_vci;
+
+    // constructor / destructor
+    VciVdspinInitiatorWrapper(  sc_module_name              name,
+                                size_t                      cmd_fifo_depth,
+                                size_t                      rsp_fifo_depth  );
+private:
+    // internal registers
+    sc_core::sc_signal<int>                                 r_cmd_fsm;
+    sc_core::sc_signal<int>                                 r_rsp_fsm;
+    sc_core::sc_signal<sc_uint<dspin_rsp_width>    >        r_rsp_buf;
+
+    // fifos cmd and rsp
+    soclib::caba::GenericFifo<sc_uint<dspin_cmd_width> >    r_fifo_cmd;
+    soclib::caba::GenericFifo<sc_uint<dspin_rsp_width> >    r_fifo_rsp;
+
+    // methods systemc
+    void transition();
+    void genMoore();
+
+public:
+    void print_trace();
+
+};
+
+}} // end namespace
+
+#endif // VCI_VDSPIN_INITIATOR_WRAPPER_H_
+
+// Local Variables:
+// tab-width: 4
+// c-basic-offset: 4
+// c-file-offsets:((innamespace . 0)(inline-open . 0))
+// indent-tabs-mode: nil
+// End:
+
+// vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4
Index: branches/v4/modules/vci_vdspin_initiator_wrapper/caba/source/src/vci_vdspin_initiator_wrapper.cpp
===================================================================
--- branches/v4/modules/vci_vdspin_initiator_wrapper/caba/source/src/vci_vdspin_initiator_wrapper.cpp	(revision 371)
+++ branches/v4/modules/vci_vdspin_initiator_wrapper/caba/source/src/vci_vdspin_initiator_wrapper.cpp	(revision 371)
@@ -0,0 +1,365 @@
+/* -*- c++ -*-
+  * File : vci_vdspin_initiator_wrapper.cpp
+  * Copyright (c) UPMC, Lip6
+  * Authors : Alain Greiner
+  *
+  * SOCLIB_LGPL_HEADER_BEGIN
+  *
+  * This file is part of SoCLib, GNU LGPLv2.1.
+  *
+  * SoCLib is free software; you can redistribute it and/or modify it
+  * under the terms of the GNU Lesser General Public License as published
+  * by the Free Software Foundation; version 2.1 of the License.
+  *
+  * SoCLib is distributed in the hope that it will be useful, but
+  * WITHOUT ANY WARRANTY; without even the implied warranty of
+  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+  * Lesser General Public License for more details.
+  *
+  * You should have received a copy of the GNU Lesser General Public
+  * License along with SoCLib; if not, write to the Free Software
+  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+  * 02110-1301 USA
+  *
+  * SOCLIB_LGPL_HEADER_END
+  *
+  * Maintainers: alexandre.joannou@lip6.fr
+  *
+  */
+
+#include "../include/vci_vdspin_initiator_wrapper.h"
+
+namespace soclib { namespace caba {
+
+#define tmpl(x) template<typename vci_param, int dspin_cmd_width, int dspin_rsp_width> x VciVdspinInitiatorWrapper<vci_param, dspin_cmd_width, dspin_rsp_width>
+
+//////////////////////////////////////////////////////////////////////////////////////////
+tmpl(/**/)::VciVdspinInitiatorWrapper(  sc_module_name  name,
+                                        size_t          cmd_fifo_depth,
+                                        size_t          rsp_fifo_depth  )
+            :   soclib::caba::BaseModule(name),
+                p_clk("p_clk"),
+                p_resetn("p_resetn"),
+                p_dspin_out("p_dspin_out"),
+                p_dspin_in("p_dspin_in"),
+                p_vci("p_vci"),
+                r_cmd_fsm("r_cmd_fsm"),
+                r_rsp_fsm("r_rsp_fsm"),
+                r_fifo_cmd("r_fifo_cmd", cmd_fifo_depth),
+                r_fifo_rsp("r_fifo_rsp", rsp_fifo_depth)
+{
+    SC_METHOD (transition);
+    dont_initialize();
+    sensitive << p_clk.pos();
+
+    SC_METHOD (genMoore);
+    dont_initialize();
+    sensitive  << p_clk.neg();
+
+    assert( (dspin_cmd_width == 40) && "The DSPIN CMD flit width must have 40 bits");
+    assert( (dspin_rsp_width == 33) && "The DSPIN RSP flit width must have 33 bits");
+    assert( (vci_param::N    <= 40) && "The VCI ADDRESS field cannot have more than 40 bits");
+    assert( (vci_param::B    == 4 ) && "The VCI DATA filds must have 32 bits");
+    assert( (vci_param::K    == 8 ) && "The VCI PLEN field cannot have more than 8 bits");
+    assert( (vci_param::S    <= 14) && "The VCI SRCID field cannot have more than 14 bits");
+    assert( (vci_param::T    <= 4 ) && "The VCI TRDID field cannot have more than 4 bits");
+    assert( (vci_param::P    <= 4 ) && "The VCI PKTID field cannot have more than 4 bits");
+    assert( (vci_param::E    <= 2 ) && "The VCI RERROR field cannot have more than 2 bits");
+
+} //  end constructor
+
+/////////////////////////
+tmpl(void)::transition()
+{
+    sc_uint<dspin_cmd_width>    cmd_fifo_data;
+    bool                        cmd_fifo_write;
+    bool                        cmd_fifo_read;
+
+    sc_uint<dspin_rsp_width>    rsp_fifo_data;
+    bool                        rsp_fifo_write;
+    bool                        rsp_fifo_read;
+
+    if (p_resetn == false)
+    {
+        r_fifo_cmd.init();
+        r_fifo_rsp.init();
+        r_cmd_fsm = CMD_IDLE;
+        r_rsp_fsm = RSP_IDLE;
+        return;
+    } // end reset
+
+    /////////////////////////////////////////////////////////////
+    // VCI command packet to DSPIN command packet
+    // The VCI packet is analysed, translated,
+    // and the DSPIN packet is stored in the fifo_cmd
+    /////////////////////////////////////////////////////////////
+    // - A N flits VCI write command packet is translated
+    //   to a N+2 flits DSPIN command.
+    // - A single flit VCI read command packet is translated
+    //   to a 2 flits DSPIN command.
+    // - A single flit VCI broadcast packet is translated to
+    //   a 2 flits DSPIN command.
+    // A DSPIN flit is written in the fifo_cmd in all states
+    // but a VCI flit is consumed only in the CMD_READ,
+    // CMD_BROACAST,  and CMD_WDATA states.
+    //////////////////////////////////////////////////////////////
+
+    // cmd_fifo_read
+    cmd_fifo_read = p_dspin_out.read.read();
+
+    // r_cmd_fsm, cmd_fifo_write and cmd_fifo_data
+    cmd_fifo_write = false;        // default value
+
+    switch(r_cmd_fsm) {
+        case CMD_IDLE:        // write first DSPIN flit into fifo_cmd
+            {
+                if( p_vci.cmdval && r_fifo_cmd.wok() )
+                {
+                    cmd_fifo_write = true;
+                    sc_uint<dspin_cmd_width> address = (sc_uint<dspin_cmd_width>)p_vci.address.read();
+                    sc_uint<dspin_cmd_width> srcid   = (sc_uint<dspin_cmd_width>)p_vci.srcid.read();
+                    sc_uint<dspin_cmd_width> trdid   = (sc_uint<dspin_cmd_width>)p_vci.trdid.read();
+                    sc_uint<dspin_cmd_width> cmd     = (sc_uint<dspin_cmd_width>)p_vci.cmd.read();
+
+                    bool is_broadcast = ( (address & 0x3) != 0);
+                    bool is_read = ((cmd == vci_param::CMD_READ) || (cmd == vci_param::CMD_LOCKED_READ));
+
+                    if ( vci_param::N == 40 ) address = address >> 1;
+                    else                      address = address << (39 - vci_param::N);
+
+                    if ( is_broadcast ) // VCI broacast command
+                    {
+                        r_cmd_fsm     = CMD_BROADCAST;
+                        cmd_fifo_data = (address      & 0x7FFFF80000LL) |
+                                        ((srcid << 5) & 0x000007FFE0LL) |
+                                        ((trdid << 1) & 0x000000001ELL) |
+                                                        0x0000000001LL;
+                    }
+                    else if (is_read )  // VCI READ  command
+                    {
+                        r_cmd_fsm     = CMD_READ;
+                        cmd_fifo_data = address & 0x7FFFFFFFFELL;
+                    }
+                    else                // VCI WRITE command
+                    {
+                        r_cmd_fsm     = CMD_WRITE;
+                        cmd_fifo_data = address & 0x7FFFFFFFFELL;
+                    }
+                }
+         break;
+        }
+        case CMD_BROADCAST:             // write second DSPIN flit in case of broadcast
+            {
+                if( p_vci.cmdval && r_fifo_cmd.wok() )
+                {
+                    cmd_fifo_write   = true;
+                    sc_uint<dspin_cmd_width> data = (sc_uint<dspin_cmd_width>)p_vci.wdata.read();
+                    sc_uint<dspin_cmd_width> be   = (sc_uint<dspin_cmd_width>)p_vci.be.read();
+                    cmd_fifo_data    = (data       & 0x00FFFFFFFFLL) |
+                                       ((be << 32) & 0x0300000000LL) |
+                                                     0x8000000000LL;
+                    r_cmd_fsm = CMD_IDLE;
+                }
+                break;
+            }
+            case CMD_READ:              // write second DSPIN flit in case of read/write
+            case CMD_WRITE:
+            {
+                if( p_vci.cmdval && r_fifo_cmd.wok() )
+                {
+                    cmd_fifo_write      = true;
+                    sc_uint<dspin_cmd_width> srcid   = (sc_uint<dspin_cmd_width>)p_vci.srcid.read();
+                    sc_uint<dspin_cmd_width> pktid   = (sc_uint<dspin_cmd_width>)p_vci.pktid.read();
+                    sc_uint<dspin_cmd_width> trdid   = (sc_uint<dspin_cmd_width>)p_vci.trdid.read();
+                    sc_uint<dspin_cmd_width> cmd     = (sc_uint<dspin_cmd_width>)p_vci.cmd.read();
+                    sc_uint<dspin_cmd_width> plen    = (sc_uint<dspin_cmd_width>)p_vci.plen.read();
+                    sc_uint<dspin_cmd_width> be      = (sc_uint<dspin_cmd_width>)p_vci.be.read();
+                    cmd_fifo_data                    = ((be    << 1 ) & 0x000000001ELL) |
+                                                       ((pktid << 5 ) & 0x00000001E0LL) |
+                                                       ((trdid << 9 ) & 0x0000001E00LL) |
+                                                       ((plen  << 13) & 0x00001FE000LL) |
+                                                       ((cmd   << 23) & 0x0001800000LL) |
+                                                       ((srcid << 25) & 0x7FFE000000LL) ;
+                    if ( p_vci.contig.read() ) cmd_fifo_data = cmd_fifo_data | 0x0000400000LL ;
+                    if ( p_vci.cons.read()   ) cmd_fifo_data = cmd_fifo_data | 0x0000200000LL ;
+
+                    if( r_cmd_fsm == CMD_READ ) // read command
+                    {
+                        r_cmd_fsm = CMD_IDLE;
+                        cmd_fifo_data = cmd_fifo_data    | 0x8000000000LL ;
+                    }
+                    else                        // write command
+                    {
+                        r_cmd_fsm = CMD_WDATA;
+                    }
+        }
+        break;
+            }
+        case CMD_WDATA:
+            {
+                if( p_vci.cmdval && r_fifo_cmd.wok() )
+                {
+                    cmd_fifo_write = true;
+                    sc_uint<dspin_cmd_width> data = (sc_uint<dspin_cmd_width>)p_vci.wdata.read();
+                    sc_uint<dspin_cmd_width> be   = (sc_uint<dspin_cmd_width>)p_vci.be.read();
+                    cmd_fifo_data                 = (data       & 0x00FFFFFFFFLL) |
+                                                    ((be << 32) & 0x0F00000000LL) ;
+
+                    if ( p_vci.eop.read() )
+                    {
+                        cmd_fifo_data = cmd_fifo_data | 0x8000000000LL;
+                        r_cmd_fsm = CMD_IDLE;
+                    }
+                }
+                break;
+            }
+    } // end switch r_cmd_fsm
+
+    // fifo_cmd
+    if((cmd_fifo_write == true)  && (cmd_fifo_read == false)) { r_fifo_cmd.simple_put(cmd_fifo_data); }
+    if((cmd_fifo_write == true)  && (cmd_fifo_read == true))  { r_fifo_cmd.put_and_get(cmd_fifo_data); }
+    if((cmd_fifo_write == false) && (cmd_fifo_read == true))  { r_fifo_cmd.simple_get(); }
+
+    //////////////////////////////////////////////////////////////
+    // DSPIN response packet to VCI response packet
+    // The DSPIN packet is stored in the fifo_rsp
+    // The FIFO output is analysed and translated to a VCI packet
+    //////////////////////////////////////////////////////////////
+    // - A N+1 flits DSPIN response packet is translated
+    //   to a N flits VCI response.
+    // - A single flit DSPIN response packet is translated
+    //   to a single flit VCI response with RDATA = 0.
+    // A valid DSPIN flit in the fifo_rsp is always consumed
+    // in the CMD_IDLE state, but no VCI flit is transmitted.
+    // The VCI flits are sent in the RSP_DSPIN_SINGLE_FLIT &
+    // RSP_DSPIN_MULTI_FLIT states.
+    //////////////////////////////////////////////////////////////
+
+    // rsp_fifo_write, rsp_fifo_data
+    rsp_fifo_write = p_dspin_in.write.read();
+    rsp_fifo_data  = p_dspin_in.data.read();
+
+    // r_rsp_fsm, rsp_fifo_read
+    rsp_fifo_read = false;        // default value
+
+    switch(r_rsp_fsm)
+    {
+        case RSP_IDLE:
+        {
+            if( r_fifo_rsp.rok() )
+            {
+                rsp_fifo_read = true;
+                r_rsp_buf = r_fifo_rsp.read();
+                if ( (r_fifo_rsp.read() & 0x100000000LL) == 0x100000000LL )
+                    r_rsp_fsm = RSP_DSPIN_SINGLE_FLIT;
+                else
+                    r_rsp_fsm = RSP_DSPIN_MULTI_FLIT;
+            }
+            break;
+        }
+        case RSP_DSPIN_SINGLE_FLIT:
+        {
+            if ( p_vci.rspack.read() )
+                r_rsp_fsm = RSP_IDLE;
+            break;
+        }
+        case RSP_DSPIN_MULTI_FLIT:
+        {
+            if( r_fifo_rsp.rok() && p_vci.rspack.read() )
+            {
+                rsp_fifo_read = true;
+                if ( (r_fifo_rsp.read() & 0x100000000LL) == 0x100000000LL )
+                    r_rsp_fsm = RSP_IDLE;
+            }
+            break;
+        }
+    } // end switch r_rsp_fsm
+
+    // fifo_rsp
+    if((rsp_fifo_write == true)  && (rsp_fifo_read == false)) { r_fifo_rsp.simple_put(rsp_fifo_data); }
+    if((rsp_fifo_write == true)  && (rsp_fifo_read == true))  { r_fifo_rsp.put_and_get(rsp_fifo_data); }
+    if((rsp_fifo_write == false) && (rsp_fifo_read == true))  { r_fifo_rsp.simple_get(); }
+
+}; // end transition
+
+//////////////////////
+tmpl(void)::genMoore()
+{
+    // VCI CMD interface
+    if ( ( r_cmd_fsm.read() == CMD_IDLE ) || ( r_cmd_fsm.read() == CMD_WRITE ) )
+    {
+        p_vci.cmdack = false;
+    }
+    else
+    {
+        p_vci.cmdack = r_fifo_cmd.wok();
+    }
+
+    // VCI RSP interface
+    if ( r_rsp_fsm.read() == RSP_IDLE )
+    {
+        p_vci.rspval = false;
+    }
+    else if ( r_rsp_fsm.read() == RSP_DSPIN_SINGLE_FLIT )
+    {
+        p_vci.rspval = true;
+        p_vci.rdata  = 0;
+        p_vci.rsrcid = (sc_uint<vci_param::S>)((r_rsp_buf.read() & 0x0FFFC0000LL) >> 18);
+        p_vci.rpktid = (sc_uint<vci_param::T>)((r_rsp_buf.read() & 0x000000F00LL) >> 8);
+        p_vci.rtrdid = (sc_uint<vci_param::P>)((r_rsp_buf.read() & 0x00000F000LL) >> 12);
+        p_vci.rerror = (sc_uint<vci_param::E>)((r_rsp_buf.read() & 0x000030000LL) >> 16);
+        p_vci.reop   = true;
+    }
+    else if ( r_rsp_fsm.read() == RSP_DSPIN_MULTI_FLIT )
+    {
+        p_vci.rspval = r_fifo_rsp.rok();
+        p_vci.rdata  = (sc_uint<8*vci_param::B>)(r_fifo_rsp.read() & 0x0FFFFFFFFLL);
+        p_vci.rsrcid = (sc_uint<vci_param::S>)((r_rsp_buf.read()   & 0x0FFFC0000LL) >> 18);
+        p_vci.rpktid = (sc_uint<vci_param::T>)((r_rsp_buf.read()   & 0x000000F00LL) >> 8);
+        p_vci.rtrdid = (sc_uint<vci_param::P>)((r_rsp_buf.read()   & 0x00000F000LL) >> 12);
+        p_vci.rerror = (sc_uint<vci_param::E>)((r_rsp_buf.read()   & 0x000030000LL) >> 16);
+        p_vci.reop   = ((r_fifo_rsp.read() & 0x100000000LL) == 0x100000000LL);
+    }
+
+    // DSPIN_OUT interface
+    p_dspin_out.write = r_fifo_cmd.rok();
+    p_dspin_out.data  = r_fifo_cmd.read();
+
+    // DSPIN_IN interface
+    p_dspin_in.read   = r_fifo_rsp.wok();
+
+}; // end genMoore
+
+/////////////////////////
+tmpl(void)::print_trace()
+{
+    const char* cmd_str[] = {
+    "CMD_IDLE     ",
+    "CMD_BROADCAST",
+    "CMD_READ     ",
+    "CMD_WRITE    ",
+    "CMD_WDATA    ",
+    };
+    const char* rsp_str[] = {
+    "RSP_IDLE             ",
+    "RSP_DSPIN_SINGLE_FLIT",
+    "RSP_DSPIN_MULTI_FLIT ",
+    };
+
+    std::cout << name() << " : " << cmd_str[r_cmd_fsm.read()]
+                        << " | " << rsp_str[r_rsp_fsm.read()]
+                        << " | fifo_cmd = " << r_fifo_cmd.filled_status()
+                        << " | fifo_rsp = " << r_fifo_rsp.filled_status()
+                        << std::endl;
+}
+
+}} // end namespace
+
+// Local Variables:
+// tab-width: 4
+// c-basic-offset: 4
+// c-file-offsets:((innamespace . 0)(inline-open . 0))
+// indent-tabs-mode: nil
+// End:
+
+// vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4
Index: branches/v4/modules/vci_vdspin_target_wrapper/caba/metadata/vci_vdspin_target_wrapper.sd
===================================================================
--- branches/v4/modules/vci_vdspin_target_wrapper/caba/metadata/vci_vdspin_target_wrapper.sd	(revision 371)
+++ branches/v4/modules/vci_vdspin_target_wrapper/caba/metadata/vci_vdspin_target_wrapper.sd	(revision 371)
@@ -0,0 +1,25 @@
+
+# -*- python -*-
+
+Module('caba:vci_vdspin_target_wrapper',
+	classname = 'soclib::caba::VciVdspinTargetWrapper',
+	tmpl_parameters = [
+		parameter.Module('vci_param',  default = 'caba:vci_param'),
+		parameter.Int('dspin_cmd_width'),
+		parameter.Int('dspin_rsp_width'), ],
+        header_files = ['../source/include/vci_vdspin_target_wrapper.h', ],
+        implementation_files = ['../source/src/vci_vdspin_target_wrapper.cpp',],
+        ports = [
+		Port('caba:vci_initiator', 'p_vci'),
+                Port('caba:dspin_output', 'p_dspin_out', dspin_data_size = parameter.Reference('dspin_rsp_width')),
+                Port('caba:dspin_input', 'p_dspin_in', dspin_data_size = parameter.Reference('dspin_cmd_width')),
+		Port('caba:bit_in', 'p_resetn', auto = 'resetn'),
+		Port('caba:clock_in', 'p_clk', auto = 'clock'), ],
+	uses = [
+		Uses('caba:base_module'),
+		Uses('caba:generic_fifo'),
+		],
+	instance_parameters = [
+		parameter.Int('cmd_fifo_depth'),
+		parameter.Int('rsp_fifo_depth'), ],
+)
Index: branches/v4/modules/vci_vdspin_target_wrapper/caba/source/include/vci_vdspin_target_wrapper.h
===================================================================
--- branches/v4/modules/vci_vdspin_target_wrapper/caba/source/include/vci_vdspin_target_wrapper.h	(revision 371)
+++ branches/v4/modules/vci_vdspin_target_wrapper/caba/source/include/vci_vdspin_target_wrapper.h	(revision 371)
@@ -0,0 +1,133 @@
+/* -*- c++ -*-
+  * File : vci_vdspin_target_wrapper.h
+  * Copyright (c) UPMC, Lip6
+  * Author : Alain Greiner
+  *
+  * SOCLIB_LGPL_HEADER_BEGIN
+  *
+  * This file is part of SoCLib, GNU LGPLv2.1.
+  *
+  * SoCLib is free software; you can redistribute it and/or modify it
+  * under the terms of the GNU Lesser General Public License as published
+  * by the Free Software Foundation; version 2.1 of the License.
+  *
+  * SoCLib is distributed in the hope that it will be useful, but
+  * WITHOUT ANY WARRANTY; without even the implied warranty of
+  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+  * Lesser General Public License for more details.
+  *
+  * You should have received a copy of the GNU Lesser General Public
+  * License along with SoCLib; if not, write to the Free Software
+  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+  * 02110-1301 USA
+  *
+  * SOCLIB_LGPL_HEADER_END
+  *
+  * Maintainers: alexandre.joannou@lip6.fr
+  *
+  */
+
+/////////////////////////////////////////////////////////////////////////
+// This component performs the protocol translation between VCI & DSPIN,
+// and can be used to connect a VCI target to a DSPIN netnork.
+// It is implemented as two fully independant sub-components:
+// - translation from a DSPIN CMD to a VCI CMD
+// - translation from a VCI RSP to a DSPIN RSP
+// Each subcomponent contains a FIFO containing DSPIN flits.
+// For the DSPIN interfaces, the widths of the CMD & RSP flits
+// are defined as template parameters for future evolutions,
+// but the VCI to DSPIN translation makes the following assumptions:
+// - DSPIN CMD flit width == 40 bits
+// - DSPIN RSP flit width == 33 bits
+// - VCI address width    <= 40 bits
+// - VCI data             == 32 bits
+// - VCI plen             == 8  bits
+// - VCI srcid            <= 14 bits
+// - VCI trdid            <= 4  bits
+// - VCI pktid            <= 4  bits
+// - VCI rerror           == 1  bit
+////////////////////////////////////////////////////////////////////////
+
+#ifndef VCI_VDSPIN_TARGET_WRAPPER_H_
+#define VCI_VDSPIN_TARGET_WRAPPER_H_
+
+#include <systemc>
+#include <assert.h>
+#include "caba_base_module.h"
+#include "vci_initiator.h"
+#include "generic_fifo.h"
+#include "dspin_interface.h"
+#include "static_fast_int.h"
+
+namespace soclib { namespace caba {
+
+
+template<typename vci_param, int dspin_cmd_width, int dspin_rsp_width>
+class VciVdspinTargetWrapper
+    : public soclib::caba::BaseModule
+{
+
+    // Command FSM
+    enum fsm_state_cmd{
+    CMD_IDLE,
+    CMD_BROADCAST,
+    CMD_RW,
+    CMD_READ,
+    CMD_WDATA,
+    };
+
+    // Response FSM
+    enum fsm_state_rsp{
+    RSP_IDLE,
+    RSP_DSPIN_SINGLE_FLIT,
+    RSP_DSPIN_MULTI_FLIT,
+    };
+
+protected:
+    SC_HAS_PROCESS(VciVdspinTargetWrapper);
+
+public:
+    // ports
+    sc_core::sc_in<bool>                                    p_clk;
+    sc_core::sc_in<bool>                                    p_resetn;
+    soclib::caba::DspinOutput<dspin_rsp_width>              p_dspin_out;
+    soclib::caba::DspinInput<dspin_cmd_width>               p_dspin_in;
+    soclib::caba::VciInitiator<vci_param>                   p_vci;
+
+    // constructor / destructor
+    VciVdspinTargetWrapper( sc_module_name                  name,
+                            size_t                          cmd_fifo_depth,
+                            size_t                          rsp_fifo_depth  );
+private:
+    // internal registers
+    sc_core::sc_signal<int>                                 r_cmd_fsm;
+    sc_core::sc_signal<sc_uint<dspin_cmd_width> >           r_cmd_buf0;
+    sc_core::sc_signal<sc_uint<dspin_cmd_width> >           r_cmd_buf1;
+    sc_core::sc_signal<int>                                 r_rsp_fsm;
+    sc_core::sc_signal<size_t>                              r_flit_count;
+
+    // fifos cmd and rsp
+    soclib::caba::GenericFifo<sc_uint<dspin_cmd_width> >    r_fifo_cmd;
+    soclib::caba::GenericFifo<sc_uint<dspin_rsp_width> >    r_fifo_rsp;
+
+    // methods systemc
+    void transition();
+    void genMoore();
+
+public:
+    void print_trace();
+
+};
+
+}} // end namespace
+
+#endif // VCI_VDSPIN_TARGET_WRAPPER_H_
+
+// Local Variables:
+// tab-width: 4
+// c-basic-offset: 4
+// c-file-offsets:((innamespace . 0)(inline-open . 0))
+// indent-tabs-mode: nil
+// End:
+
+// vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4
Index: branches/v4/modules/vci_vdspin_target_wrapper/caba/source/src/vci_vdspin_target_wrapper.cpp
===================================================================
--- branches/v4/modules/vci_vdspin_target_wrapper/caba/source/src/vci_vdspin_target_wrapper.cpp	(revision 371)
+++ branches/v4/modules/vci_vdspin_target_wrapper/caba/source/src/vci_vdspin_target_wrapper.cpp	(revision 371)
@@ -0,0 +1,384 @@
+/* -*- c++ -*-
+  * File : vci_vdspin_target_wrapper.cpp
+  * Copyright (c) UPMC, Lip6
+  * Author : Alain Greiner
+  *
+  * SOCLIB_LGPL_HEADER_BEGIN
+  *
+  * This file is part of SoCLib, GNU LGPLv2.1.
+  *
+  * SoCLib is free software; you can redistribute it and/or modify it
+  * under the terms of the GNU Lesser General Public License as published
+  * by the Free Software Foundation; version 2.1 of the License.
+  *
+  * SoCLib is distributed in the hope that it will be useful, but
+  * WITHOUT ANY WARRANTY; without even the implied warranty of
+  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+  * Lesser General Public License for more details.
+  *
+  * You should have received a copy of the GNU Lesser General Public
+  * License along with SoCLib; if not, write to the Free Software
+  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+  * 02110-1301 USA
+  *
+  * SOCLIB_LGPL_HEADER_END
+  *
+  * Maintainers: alexandre.joannou@lip6.fr
+  *
+  */
+
+#include "../include/vci_vdspin_target_wrapper.h"
+
+using namespace soclib::common;
+
+namespace soclib { namespace caba {
+
+#define tmpl(x) template<typename vci_param, int dspin_cmd_width, int dspin_rsp_width> x VciVdspinTargetWrapper<vci_param, dspin_cmd_width, dspin_rsp_width>
+
+//////////////////////////////////////////////////////////////////////////////////////////
+tmpl(/**/)::VciVdspinTargetWrapper( sc_module_name  name,
+                                    size_t          cmd_fifo_depth,
+                                    size_t          rsp_fifo_depth  )
+        :   soclib::caba::BaseModule(name),
+            p_clk("p_clk"),
+            p_resetn("p_resetn"),
+            p_dspin_out("p_dspin_out"),
+            p_dspin_in("p_dspin_in"),
+            p_vci("p_vci"),
+            r_cmd_fsm("r_cmd_fsm"),
+            r_rsp_fsm("r_rsp_fsm"),
+            r_fifo_cmd("r_fifo_cmd", cmd_fifo_depth),
+            r_fifo_rsp("r_fifo_rsp", rsp_fifo_depth)
+{
+    SC_METHOD (transition);
+    dont_initialize();
+    sensitive << p_clk.pos();
+
+    SC_METHOD (genMoore);
+    dont_initialize();
+    sensitive  << p_clk.neg();
+
+    assert( (dspin_cmd_width == 40) && "The DSPIN CMD flit width must have 40 bits");
+    assert( (dspin_rsp_width == 33) && "The DSPIN RSP flit width must have 33 bits");
+    assert( (vci_param::N    <= 40) && "The VCI ADDRESS field cannot have more than 40 bits");
+    assert( (vci_param::B    == 4 ) && "The VCI DATA filds must have 32 bits");
+    assert( (vci_param::K    == 8 ) && "The VCI PLEN field cannot have more than 8 bits");
+    assert( (vci_param::S    <= 14) && "The VCI SRCID field cannot have more than 14 bits");
+    assert( (vci_param::T    <= 4 ) && "The VCI TRDID field cannot have more than 4 bits");
+    assert( (vci_param::P    <= 4 ) && "The VCI PKTID field cannot have more than 4 bits");
+    assert( (vci_param::E    <= 2 ) && "The VCI RERROR field cannot have more than 2 bits");
+
+} //  end constructor
+
+/////////////////////////
+tmpl(void)::transition()
+{
+    sc_uint<dspin_cmd_width>    cmd_fifo_data;
+    bool                        cmd_fifo_write;
+    bool                        cmd_fifo_read;
+
+    sc_uint<dspin_rsp_width>    rsp_fifo_data;
+    bool                        rsp_fifo_write;
+    bool                        rsp_fifo_read;
+
+    if (p_resetn == false)
+    {
+        r_fifo_cmd.init();
+        r_fifo_rsp.init();
+        r_cmd_fsm = CMD_IDLE;
+        r_rsp_fsm = RSP_IDLE;
+        return;
+    } // end reset
+
+    /////////////////////////////////////////////////////////////
+    // VCI response packet to DSPIN response packet.
+    // The VCI packet is analysed, translated,
+    // and the DSPIN packet is stored in the fifo_rsp
+    /////////////////////////////////////////////////////////////
+    // - A single flit VCI response packet with a 0 RDATA value
+    //   is translated to a single flit DSPIN response.
+    // - All other VCI responses are translated to a multi-flit
+    //   DSPIN response.
+    // In the RSP_IDLE state, the first DSPIN flit is written
+    // in fifo_rsp , but no VCI flit is consumed. The VCI flits
+    // are consumed in the RSP_DSPIN_SINGLE_FLIT, or the
+    // SP_DSPIN_MULTI_FLIT states.
+    //////////////////////////////////////////////////////////////
+
+    // rsp_fifo_read
+    rsp_fifo_read = p_dspin_out.read.read();
+
+    // r_rsp_fsm, rsp_fifo_write and rsp_fifo_data
+    rsp_fifo_write = false;        // default value
+
+    switch(r_rsp_fsm)
+    {
+        case RSP_IDLE:        // write first DSPIN flit into rsp_fifo
+        {
+            if( p_vci.rspval.read() && r_fifo_rsp.wok() )
+            {
+                bool is_single_flit = ( p_vci.reop.read() && ( p_vci.rdata.read() == 0) );
+
+                rsp_fifo_write = true;
+                rsp_fifo_data  = (((sc_uint<dspin_rsp_width>)p_vci.rsrcid.read()) << 18) |
+                                 (((sc_uint<dspin_rsp_width>)p_vci.rerror.read()) << 16) |
+                                 (((sc_uint<dspin_rsp_width>)p_vci.rtrdid.read()) << 12) |
+                                 (((sc_uint<dspin_rsp_width>)p_vci.rpktid.read()) << 8);
+                if ( is_single_flit )
+                {
+                    rsp_fifo_data = rsp_fifo_data | 0x100000000LL; // EOP = 1
+                    rsp_fifo_data = rsp_fifo_data & 0x1FFFFFFFELL; // BC  = 0
+                    r_rsp_fsm = RSP_DSPIN_SINGLE_FLIT;
+                }
+                else
+                {
+                    rsp_fifo_data = rsp_fifo_data & 0x0FFFFFFFFLL; // EOP = 0
+                    rsp_fifo_data = rsp_fifo_data & 0x1FFFFFFFELL; // BC  = 0
+                    r_rsp_fsm = RSP_DSPIN_MULTI_FLIT;
+                }
+            }
+            break;
+        }
+        case RSP_DSPIN_SINGLE_FLIT:
+        {
+            rsp_fifo_write = false;
+            if ( r_fifo_rsp.wok() )
+                r_rsp_fsm = RSP_IDLE;
+            break;
+        }
+        case RSP_DSPIN_MULTI_FLIT:        // write DSPIN data flit
+        {
+            if( p_vci.rspval && r_fifo_rsp.wok() )
+            {
+                rsp_fifo_write   = true;
+                rsp_fifo_data = ((sc_uint<dspin_rsp_width>)p_vci.rdata.read());
+                if ( p_vci.reop )
+                {
+                    rsp_fifo_data = rsp_fifo_data | 0x100000000LL; // EOP = 1
+                    r_rsp_fsm = RSP_IDLE;
+                }
+            }
+            break;
+        }
+    } // end switch r_cmd_fsm
+
+    // fifo_rsp
+    if((rsp_fifo_write == true)  && (rsp_fifo_read == false)) { r_fifo_rsp.simple_put(rsp_fifo_data); }
+    if((rsp_fifo_write == true)  && (rsp_fifo_read == true))  { r_fifo_rsp.put_and_get(rsp_fifo_data); }
+    if((rsp_fifo_write == false) && (rsp_fifo_read == true))  { r_fifo_rsp.simple_get(); }
+
+    //////////////////////////////////////////////////////////////
+    // DSPIN command packet to VCI command packet
+    // The DSPIN packet is stored in the fifo_cmd
+    // The FIFO output is analysed and translated to a VCI packet
+    //////////////////////////////////////////////////////////////
+    // - A 2 flits DSPIN broadcast command is translated
+    //   to a 1 flit VCI broadcast command.
+    // - A 2 flits DSPIN read command is translated
+    //   to a 1 flit VCI read command.
+    // - A N+2 flits DSPIN write command is translated
+    //   to a N flits VCI write command.
+    // The VCI flits are sent in the CMD_READ, CMD_WDATA
+    // & CMD_BROADCAST states.
+    // The r_cmd_buf0 et r_cmd_buf1 buffers are used to store
+    // the two first DSPIN flits (in case of write).
+    //////////////////////////////////////////////////////////////
+
+    // cmd_fifo_write, cmd_fifo_data
+    cmd_fifo_write = p_dspin_in.write.read();
+    cmd_fifo_data  = p_dspin_in.data.read();
+
+    // r_cmd_fsm, cmd_fifo_read
+    cmd_fifo_read = false;         // default value
+
+    switch(r_cmd_fsm)
+    {
+        case CMD_IDLE:
+        {
+            if( r_fifo_cmd.rok() )
+            {
+                bool is_broadcast = ( (r_fifo_cmd.read() & 0x1) == 0x1);
+
+                cmd_fifo_read = true;
+                r_cmd_buf0    = r_fifo_cmd.read();         // save address
+
+                if ( is_broadcast )
+                    r_cmd_fsm = CMD_BROADCAST;
+                else
+                    r_cmd_fsm = CMD_RW;
+            }
+            break;
+        }
+        case CMD_BROADCAST:
+        {
+            if( r_fifo_cmd.rok() && p_vci.cmdack )
+            {
+                cmd_fifo_read = true;
+                r_cmd_fsm = CMD_IDLE;
+            }
+            break;
+        }
+        case CMD_RW:
+        {
+            if( r_fifo_cmd.rok() )
+            {
+                cmd_fifo_read = true;
+                r_cmd_buf1 = r_fifo_cmd.read();        // save command parameters
+                // read command if EOP
+                if ( (r_fifo_cmd.read() & 0x8000000000LL) )
+                    r_cmd_fsm = CMD_READ;
+                else
+                    r_cmd_fsm = CMD_WDATA;
+                r_flit_count = 0;
+            }
+            break;
+        }
+        case CMD_READ:
+        {
+            if ( p_vci.cmdack.read() )
+                r_cmd_fsm = CMD_IDLE;
+            break;
+        }
+        case CMD_WDATA:
+        {
+            if( r_fifo_cmd.rok() && p_vci.cmdack.read() )
+            {
+                if ( (r_cmd_buf1.read() & 0x0000200000LL) == 0 )
+                    r_flit_count = r_flit_count + 1;
+                cmd_fifo_read = true;
+                if ( (r_fifo_cmd.read() & 0x8000000000LL) )
+                    r_cmd_fsm = CMD_IDLE;
+            }
+            break;
+        }
+    } // end switch r_cmd_fsm
+
+    // fifo_cmd
+    if((cmd_fifo_write == true)  && (cmd_fifo_read == false)) { r_fifo_cmd.simple_put(cmd_fifo_data); }
+    if((cmd_fifo_write == true)  && (cmd_fifo_read == true))  { r_fifo_cmd.put_and_get(cmd_fifo_data); }
+    if((cmd_fifo_write == false) && (cmd_fifo_read == true))  { r_fifo_cmd.simple_get(); }
+
+}; // end transition
+
+//////////////////////
+tmpl(void)::genMoore()
+{
+    // VCI RSP interface
+    if ( r_rsp_fsm.read() == RSP_IDLE ) p_vci.rspack = false;
+    else                                p_vci.rspack = r_fifo_rsp.wok();
+
+    // VCI CMD interface
+    if ( (r_cmd_fsm.read() == CMD_IDLE) || (r_cmd_fsm.read() == CMD_RW) )
+    {
+        p_vci.cmdval = false;
+    }
+    else if ( r_cmd_fsm.read() == CMD_BROADCAST )    // VCI CMD broadcast
+    {
+        if ( r_fifo_cmd.rok() )
+        {
+            sc_uint<dspin_cmd_width>  minmax = r_cmd_buf0.read() & 0x7FFFF80000LL;
+            if ( vci_param::N == 40 ) minmax = (minmax << 1);
+            else              minmax = (minmax >> (39 - vci_param::N) );
+            p_vci.cmdval  = true;
+            p_vci.address = (sc_uint<vci_param::N>)minmax | 0x3;
+            p_vci.cmd     = vci_param::CMD_WRITE;
+            p_vci.wdata   = (sc_uint<8*vci_param::B>)(r_fifo_cmd.read() & 0x00FFFFFFFFLL);
+            p_vci.be      = (sc_uint<vci_param::B>)((r_fifo_cmd.read()  & 0x0F00000000LL) >> 32);
+            p_vci.srcid   = (sc_uint<vci_param::S>)((r_cmd_buf0.read()  & 0x000007FFE0LL) >> 5);
+            p_vci.trdid   = (sc_uint<vci_param::T>)((r_cmd_buf0.read()  & 0x000000001ELL) >> 1);
+            p_vci.pktid   = 0;
+            p_vci.plen    = vci_param::B;
+            p_vci.contig  = true;
+            p_vci.cons    = false;
+            p_vci.eop     = true;
+        }
+        else
+        {
+            p_vci.cmdval = false;
+        }
+    }
+    else if ( r_cmd_fsm.read() == CMD_READ )    // VCI CMD read
+    {
+        sc_uint<vci_param::N> address;
+        if ( vci_param::N == 40 ) address = (r_cmd_buf0.read() << 1);
+        else                      address = (r_cmd_buf0.read() >> (39 - vci_param::N) );
+        p_vci.cmdval  = true;
+        p_vci.address = address;
+        p_vci.cmd     = (sc_uint<2>)((r_cmd_buf1.read()            & 0x0001800000LL) >> 23);
+        p_vci.wdata   = 0;
+        p_vci.be      = (sc_uint<vci_param::B>)((r_cmd_buf1.read() & 0x000000001ELL) >> 1);
+        p_vci.srcid   = (sc_uint<vci_param::S>)((r_cmd_buf1.read() & 0x7FFE000000LL) >> 25);
+        p_vci.pktid   = (sc_uint<vci_param::P>)((r_cmd_buf1.read() & 0x00000001E0LL) >> 5);
+        p_vci.trdid   = (sc_uint<vci_param::T>)((r_cmd_buf1.read() & 0x0000001E00LL) >> 9);
+        p_vci.plen    = (sc_uint<vci_param::K>)((r_cmd_buf1.read() & 0x00001FE000LL) >> 13);
+        p_vci.contig  = ((r_cmd_buf1.read() & 0x0000400000LL) != 0);
+        p_vci.cons    = ((r_cmd_buf1.read() & 0x0000200000LL) != 0);
+        p_vci.eop     = true;
+    }
+    else if ( r_cmd_fsm.read() == CMD_WDATA )    // VCI write command
+    {
+        if ( r_fifo_cmd.rok() )
+        {
+            sc_uint<vci_param::N> address;
+            if ( vci_param::N == 40 ) address = (r_cmd_buf0.read() << 1);
+            else                      address = (r_cmd_buf0.read() >> (39 - vci_param::N) );
+            p_vci.cmdval  = true;
+            p_vci.address = address + (r_flit_count.read()*vci_param::B);
+            p_vci.cmd     = (sc_uint<2>)((r_cmd_buf1.read()             & 0x0001800000LL) >> 23);
+            p_vci.wdata   = (sc_uint<8*vci_param::B>)(r_fifo_cmd.read() & 0x00FFFFFFFFLL);
+            p_vci.be      = (sc_uint<vci_param::B>)((r_fifo_cmd.read()  & 0x0F00000000LL) >> 32);
+            p_vci.srcid   = (sc_uint<vci_param::S>)((r_cmd_buf1.read()  & 0x7FFE000000LL) >> 25);
+            p_vci.pktid   = (sc_uint<vci_param::P>)((r_cmd_buf1.read()  & 0x00000001E0LL) >> 5);
+            p_vci.trdid   = (sc_uint<vci_param::T>)((r_cmd_buf1.read()  & 0x0000001E00LL) >> 9);
+            p_vci.plen    = (sc_uint<vci_param::K>)((r_cmd_buf1.read()  & 0x00001FE000LL) >> 13);
+            p_vci.contig  = ((r_cmd_buf1.read() & 0x0000400000LL) != 0);
+            p_vci.cons    = ((r_cmd_buf1.read() & 0x0000200000LL) != 0);
+            p_vci.eop     = ((r_fifo_cmd.read() & 0x8000000000LL) == 0x8000000000LL);
+        }
+        else
+        {
+            p_vci.cmdval = false;
+        }
+    }
+
+    // DSPIN_OUT interface
+    p_dspin_out.write = r_fifo_rsp.rok();
+    p_dspin_out.data  = r_fifo_rsp.read();
+
+    // DSPIN_IN interface
+    p_dspin_in.read = r_fifo_cmd.wok();
+
+}; // end genMoore
+
+/////////////////////////
+tmpl(void)::print_trace()
+{
+    const char* cmd_str[] = {
+    "CMD_IDLE     ",
+    "CMD_BROADCAST",
+    "CMD_RW       ",
+    "CMD_READ     ",
+    "CMD_WDATA    ",
+    };
+    const char* rsp_str[] = {
+    "RSP_IDLE             ",
+    "RSP_DSPIN_SINGLE_FLIT",
+    "RSP_DSPIN_MULTI_FLIT ",
+    };
+    std::cout << name() << " : " << cmd_str[r_cmd_fsm.read()]
+                        << " | " << rsp_str[r_rsp_fsm.read()]
+                        << " | fifo_cmd = " << r_fifo_cmd.filled_status()
+                        << " | fifo_rsp = " << r_fifo_rsp.filled_status()
+                        << std::endl;
+}
+
+}} // end namespace
+
+// Local Variables:
+// tab-width: 4
+// c-basic-offset: 4
+// c-file-offsets:((innamespace . 0)(inline-open . 0))
+// indent-tabs-mode: nil
+// End:
+
+// vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4
Index: branches/v4/platforms/almos-tsarv3-platforms/README
===================================================================
--- branches/v4/platforms/almos-tsarv3-platforms/README	(revision 371)
+++ branches/v4/platforms/almos-tsarv3-platforms/README	(revision 371)
@@ -0,0 +1,24 @@
+======================================================================
+=                      Note about this package                       =
+=                         (27 august 2012)                           =
+======================================================================
+
+Information
+============
+This directory contains the hardware description of two TSAR platforms
+(mono and multi clusters) used by the distribution (almos-tsar-mipsel) 
+of ALMOS (Advanced Locality Management Operating System) found on 
+the project website: www.almos.fr.
+
+
+Important
+============
+The platform descriptions and their related components found in this
+directory match a specific, intermediate and no more maintaned version 
+of TSAR. This deprecated version is code-named "v3" and it has been 
+dropped in favor of an enhanced and actively maintainted version, 
+code-named "v4". You are encouraged to update these TSAR platform 
+descriptions to refer to the last version ("v4") of TSAR.
+
+======================================================================
+======================================================================
Index: branches/v4/platforms/almos-tsarv3-platforms/common/generic_cache/include/generic_cache.h
===================================================================
--- branches/v4/platforms/almos-tsarv3-platforms/common/generic_cache/include/generic_cache.h	(revision 371)
+++ branches/v4/platforms/almos-tsarv3-platforms/common/generic_cache/include/generic_cache.h	(revision 371)
@@ -0,0 +1,721 @@
+/* -*- c++ -*-
+ *
+ * SOCLIB_LGPL_HEADER_BEGIN
+ *
+ * This file is part of SoCLib, GNU LGPLv2.1.
+ *
+ * SoCLib is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU Lesser General Public License as published
+ * by the Free Software Foundation; version 2.1 of the License.
+ *
+ * SoCLib is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with SoCLib; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301 USA
+ *
+ * SOCLIB_LGPL_HEADER_END
+ *
+ * Copyright (c) UPMC, Lip6
+ *         Alain Greiner <alain.greiner@lip6.fr> July 2008
+ *
+ * Maintainers: alain yang
+ */
+
+//////////////////////////////////////////////////////////////////////////////////
+// This object is a generic, set associative, cache providing read(), write(),
+// inval() and update() access primitives. The replacement policy is pseudo-LRU.
+// The DATA part is implemented as an int32_t array.
+// The DIRECTORY part is implemented as an uint32_t array.
+//
+// Constructor parameters are :
+// - std::string    &name
+// - size_t         nways   : number of associativity levels 
+// - size_t         nsets   : number of sets
+// - size_t         nwords  : number of words in a cache line
+// The nways, nsets, nwords parameters must be power of 2
+// The nsets parameter cannot be larger than 1024
+// The nways parameter cannot be larger than 16
+// The nwords parameter cannot be larger than 64
+//
+// Template parameter is :
+// - addr_t : address format to access the cache 
+// The address can be larger than 32 bits, but the TAG field 
+// cannot be larger than 32 bits.
+/////////////////////////////////////////////////////////////////////////////////
+// History :
+// 05/01/2010
+// Two new methods select_before_update(), and update_after_select() have
+// been introduced to support update in two cycles, when the cache directory
+// is implemented as a simple port RAM.
+/////////////////////////////////////////////////////////////////////////////////
+
+#ifndef SOCLIB_GENERIC_CACHE_H
+#define SOCLIB_GENERIC_CACHE_H
+
+#include <systemc>
+#include <cassert>
+#include "arithmetics.h"
+#include "static_assert.h"
+#include "mapping_table.h"
+#include <cstring>
+
+namespace soclib { 
+
+//////////////////////////
+template<typename addr_t>
+class GenericCache 
+//////////////////////////
+{
+    typedef uint32_t    data_t;
+    typedef uint32_t    tag_t;
+
+    data_t              *r_data ;
+    tag_t               *r_tag ;
+    bool                *r_val ;
+    bool                *r_lru ;
+
+    size_t              m_ways;	
+    size_t              m_sets;	
+    size_t              m_words;
+    size_t              m_next_way;
+
+    const soclib::common::AddressMaskingTable<addr_t>  m_x ;
+    const soclib::common::AddressMaskingTable<addr_t>  m_y ;
+    const soclib::common::AddressMaskingTable<addr_t>  m_z ;
+
+    //////////////////////////////////////////////////////////////
+    inline data_t &cache_data(size_t way, size_t set, size_t word)
+    {
+        return r_data[(way*m_sets*m_words)+(set*m_words)+word];
+    }
+
+    //////////////////////////////////////////////
+    inline tag_t &cache_tag(size_t way, size_t set)
+    {
+        return r_tag[(way*m_sets)+set];
+    }
+
+    //////////////////////////////////////////////
+    inline bool &cache_val(size_t way, size_t set)
+    {
+        return r_val[(way*m_sets)+set];
+    }
+
+    //////////////////////////////////////////////
+    inline bool &cache_lru(size_t way, size_t set)
+    {
+        return r_lru[(way*m_sets)+set];
+    }
+
+    //////////////////////////////////////////////
+    inline void cache_set_lru(size_t way, size_t set)
+    {
+	size_t way2;
+
+        cache_lru(way, set) = true;
+	for (way2 = 0; way2 < m_ways; way2++ ) {
+	    if (cache_lru(way2, set) == false) return;
+	}
+	/* all lines are new -> they all become old */
+	for (way2 = 0; way2 < m_ways; way2++ ) {
+	    cache_lru(way2, set) = false;
+	}
+    }
+
+public:
+
+    //////////////////////////////////////////////
+    GenericCache(   const std::string   &name,
+                    size_t              nways, 
+                    size_t              nsets, 
+                    size_t              nwords)
+        : m_ways(nways),
+          m_sets(nsets),
+          m_words(nwords),
+
+#define l2 soclib::common::uint32_log2
+
+          m_x( l2(nwords), l2(sizeof(data_t))),
+          m_y( l2(nsets), l2(nwords) + l2(sizeof(data_t))),
+          m_z( 8*sizeof(addr_t) - l2(nsets) - l2(nwords) - l2(sizeof(data_t)),
+               l2(nsets) + l2(nwords) + l2(sizeof(data_t)))
+
+#undef l2
+    {
+        assert(IS_POW_OF_2(nways));
+        assert(IS_POW_OF_2(nsets));
+        assert(IS_POW_OF_2(nwords));
+        assert(nwords);
+        assert(nsets);
+        assert(nways);
+        assert(nwords <= 64);
+        assert(nsets <= 1024);
+        assert(nways <= 16);
+
+#ifdef GENERIC_CACHE_DEBUG
+        std::cout
+            << " m_x: " << m_x
+            << " m_y: " << m_y
+            << " m_z: " << m_z
+            << std::endl;
+#endif
+
+        r_data = new data_t[nways*nsets*nwords];
+        r_tag  = new tag_t[nways*nsets];
+        r_val  = new bool[nways*nsets];
+        r_lru  = new bool[nways*nsets];
+        m_next_way = 0;
+    }
+
+    ////////////////
+    ~GenericCache()
+    {
+        delete [] r_data;
+        delete [] r_tag;
+        delete [] r_val;
+        delete [] r_lru;
+    }
+
+    ////////////////////
+    inline void reset( )
+    {
+        std::memset(r_data, 0, sizeof(*r_data)*m_ways*m_sets*m_words);
+        std::memset(r_tag, 0, sizeof(*r_tag)*m_ways*m_sets);
+        std::memset(r_val, 0, sizeof(*r_val)*m_ways*m_sets);
+        std::memset(r_lru, 0, sizeof(*r_lru)*m_ways*m_sets);
+    }
+
+    ////////////////////////////////////////////////////////
+    inline bool flush(size_t way, size_t set, addr_t* nline)
+    {
+        if ( cache_val(way,set) ) 
+        {
+            cache_val(way,set) = false;
+            *nline = (data_t)cache_tag(way,set)* m_sets + set;
+            return true;
+        }
+        return false;
+    }
+
+    /////////////////////////////////////////
+    inline bool read( addr_t ad, data_t* dt)
+    {
+        const tag_t       tag  = m_z[ad];
+        const size_t      set  = m_y[ad];
+        const size_t      word = m_x[ad];
+
+#ifdef GENERIC_CACHE_DEBUG
+        std::cout << "Reading data at " << ad << ", "
+                  << " s/t=" << set << '/' << tag
+                  << ", ";
+#endif
+
+        for ( size_t way = 0; way < m_ways; way++ ) {
+            if ( (tag == cache_tag(way, set)) && cache_val(way, set) ) {
+                *dt = cache_data(way, set, word);
+                cache_set_lru(way, set);
+
+#ifdef GENERIC_CACHE_DEBUG
+                std::cout << "hit"
+                          << " w/s/t=" << way << '/' << set << '/' << tag
+                          << " = " << *dt << std::endl;
+#endif
+                return true;
+            }
+        }
+
+#ifdef GENERIC_CACHE_DEBUG
+        std::cout << "miss" << std::endl;
+#endif
+        return false;
+    }
+
+    /////////////////////////////////////////////////////////////////////
+    inline bool read( addr_t ad, data_t* dt, size_t* n_way, size_t* n_set)
+    {
+        const tag_t       tag  = m_z[ad];
+        const size_t      set  = m_y[ad];
+        const size_t      word = m_x[ad];
+
+#ifdef GENERIC_CACHE_DEBUG
+        std::cout << "Reading data at " << ad << ", "
+                  << " s/t=" << set << '/' << tag
+                  << ", ";
+#endif
+
+        for ( size_t way = 0; way < m_ways; way++ ) {
+            if ( (tag == cache_tag(way, set)) && cache_val(way, set) ) {
+                *dt = cache_data(way, set, word);
+                cache_set_lru(way, set);
+                *n_way = way;
+                *n_set = set;
+
+#ifdef GENERIC_CACHE_DEBUG
+                std::cout << "hit"
+                          << " w/s/t=" << way << '/' << set << '/' << tag
+                          << " = " << *dt << std::endl;
+#endif
+                return true;
+            }
+        }
+#ifdef GENERIC_CACHE_DEBUG
+        std::cout << "miss" << std::endl;
+#endif
+        return false;
+    }
+
+    //////////////////////////////////////////////////////
+    inline bool setinbit( addr_t ad, bool* buf, bool val )
+    {
+        const tag_t       tag  = m_z[ad];
+        const size_t      set  = m_y[ad];
+
+        for ( size_t way = 0; way < m_ways; way++ ) {
+            if ( (tag == cache_tag(way, set)) && cache_val(way, set) ) {
+                buf[m_sets*way+set] = val;
+
+#ifdef GENERIC_CACHE_DEBUG
+                std::cout << "hit"
+                          << " w/s=" << way << '/' << set 
+                          << std::endl;
+#endif
+                return true;
+            }
+        }
+#ifdef GENERIC_CACHE_DEBUG
+        std::cout << "miss" << std::endl;
+#endif
+        return false;
+    }
+
+    ////////////////////////////////////////////
+    inline tag_t get_tag(size_t way, size_t set)
+    {
+        return cache_tag(way, set);
+    }
+
+    /////////////////////////////////////////
+    inline bool write( addr_t ad, data_t dt )
+    {
+        const tag_t       tag  = m_z[ad];
+        const size_t      set  = m_y[ad];
+        const size_t      word = m_x[ad];
+
+#ifdef GENERIC_CACHE_DEBUG
+        std::cout << "Writing data at " << ad << ", "
+                  << " s/t=" << set << '/' << tag
+                  << ", ";
+#endif
+
+        for ( size_t way = 0; way < m_ways; way++ ) {
+            if ( (tag == cache_tag(way, set)) && cache_val(way, set) ) {
+                cache_data(way, set, word) = dt;
+                cache_set_lru(way, set);
+
+#ifdef GENERIC_CACHE_DEBUG
+                std::cout << "hit"
+                          << " w/s/t=" << way << '/' << set << '/' << tag
+                          << std::endl;
+#endif
+                return true;
+            }
+        }
+
+#ifdef GENERIC_CACHE_DEBUG
+        std::cout << "miss" << std::endl;
+#endif
+        return false;
+    }
+
+    /////////////////////////////////////////////////////////////////////
+    inline bool write( addr_t ad, data_t dt, size_t* nway, size_t* nset )
+    {
+        const tag_t       tag  = m_z[ad];
+        const size_t      set  = m_y[ad];
+        const size_t      word = m_x[ad];
+
+#ifdef GENERIC_CACHE_DEBUG
+        std::cout << "Writing data at " << ad << ", "
+                  << " s/t=" << set << '/' << tag
+                  << ", ";
+#endif
+
+        for ( size_t way = 0; way < m_ways; way++ ) {
+            if ( (tag == cache_tag(way, set)) && cache_val(way, set) ) {
+                cache_data(way, set, word) = dt;
+                cache_set_lru(way, set);
+                *nway = way;
+                *nset = set;
+
+#ifdef GENERIC_CACHE_DEBUG
+                std::cout << "hit"
+                          << " w/s/t=" << way << '/' << set << '/' << tag
+                          << std::endl;
+#endif
+                return true;
+            }
+        }
+
+#ifdef GENERIC_CACHE_DEBUG
+        std::cout << "miss" << std::endl;
+#endif
+        return false;
+    }
+
+    inline void write(size_t way, size_t set, size_t word, data_t data)
+    {
+        cache_data(way, set, word) = data;
+    }
+
+    //////////////////////////////
+    inline bool inval( addr_t ad )
+    {
+        bool        hit = false;
+        const tag_t       tag = m_z[ad];
+        const size_t      set = m_y[ad];
+
+#ifdef GENERIC_CACHE_DEBUG
+        std::cout << "Invalidating data at " << ad << ", "
+                  << " s/t=" << set << '/' << tag
+                  << ", ";
+#endif
+
+        for ( size_t way = 0 ; way < m_ways && !hit ; way++ ) {
+            if ( (tag == cache_tag(way, set)) && cache_val(way, set) ) {
+                hit     = true;
+                cache_val(way, set) = false;
+                cache_lru(way, set) = false;
+
+#ifdef GENERIC_CACHE_DEBUG
+                std::cout << "hit"
+                          << " w/s/t=" << way << '/' << set << '/' << tag
+                          << " ";
+#endif
+            }
+        }
+
+#ifdef GENERIC_CACHE_DEBUG
+        std::cout << std::endl;
+#endif
+        return hit;
+    }
+
+    ////////////////////////////////////////////////////////////
+    inline bool inval( addr_t ad, size_t* n_way, size_t* n_set )
+    {
+        bool    hit = false;
+        const tag_t       tag = m_z[ad];
+        const size_t      set = m_y[ad];
+
+#ifdef GENERIC_CACHE_DEBUG
+        std::cout << "Invalidating data at " << ad << ", "
+                  << " s/t=" << set << '/' << tag
+                  << ", ";
+#endif
+
+        for ( size_t way = 0 ; way < m_ways && !hit ; way++ ) {
+            if ( (tag == cache_tag(way, set)) && cache_val(way, set) ) {
+                hit     = true;
+                cache_val(way, set) = false;
+                cache_lru(way, set) = false;
+                *n_way = way;
+                *n_set = set;
+
+#ifdef GENERIC_CACHE_DEBUG
+                std::cout << "hit"
+                          << " w/s/t=" << way << '/' << set << '/' << tag
+                          << " ";
+#endif
+            }
+        }
+
+#ifdef GENERIC_CACHE_DEBUG
+        std::cout << std::endl;
+#endif
+        return hit;
+    }
+
+    ///////////////////////////////////////////////////////////////////
+    // This function implements a pseudo LRU policy for a one cycle
+    // line replacement. It can be used if the directory is implemented
+    // as a dual port RAM.
+    // 1 - First we search an invalid way
+    // 2 - Il all ways are valid, we search the first old way
+    // 3 - If all ways are recent, they are all transformed to old.
+    //     and we select the way with index 0.
+    // The victim line index is returned in the victim parameter.
+    // This function returns true, if the victim line is valid.
+    ///////////////////////////////////////////////////////////////////
+    inline bool update( addr_t ad, data_t* buf, addr_t* victim )
+    {
+        size_t set, way;
+        bool   cleanup = victim_select(ad, victim, &way, &set);
+        victim_update_tag (ad, way, set);
+
+        for ( size_t word = 0 ; word < m_words ; word++ ) {
+            cache_data(way, set, word) = buf[word] ;
+        }
+
+        return cleanup;
+    }
+
+    inline bool victim_select( addr_t ad, addr_t* victim, size_t * way, size_t * set )
+    {
+        bool   found   = false;
+        bool   cleanup = false;
+        *set = m_y[ad];
+        *way = 0;
+
+        // Schearch and invalid slot
+        for ( size_t _way = 0 ; _way < m_ways && !found ; _way++ )
+        {
+            if ( !cache_val(_way, *set) )
+            {
+                found   = true;
+                cleanup = false;
+                *way    = _way;
+            }
+        }
+
+        // No invalid way, scearch the lru
+        if ( !found )
+        { 
+            for ( size_t _way = 0 ; _way < m_ways && !found ; _way++ )
+            {
+                if ( !cache_lru(_way, *set) )
+                {
+                    cache_val (_way, *set) = false;
+                    found   = true;
+                    cleanup = true;
+                    *way    = _way;
+                }
+            }
+        }
+
+        assert(found && "all ways can't be new at the same time");
+
+        *victim = (addr_t)((cache_tag(*way,*set) * m_sets) + *set);
+
+        return cleanup;
+    }
+
+    inline void victim_update_tag( addr_t ad, size_t way, size_t set )
+    {
+        tag_t  tag     = m_z[ad];
+
+        cache_tag    (way, set) = tag;
+        cache_val    (way, set) = true;
+        cache_set_lru(way, set);
+    }
+
+/*
+    //////////////////////////////////////////////////////////////////////////////
+    // The two functions select_before_update() & update_after_select()
+    // can be used to perform a line replacement in two cycles
+    // (when the directory is implemented as a single port RAM)
+    //
+    // The select_before_update function implements a pseudo LRU
+    // policy and and returns the victim line index and the selected 
+    // way in the return arguments. The selected cache line is invalidated.
+    // This function returns true, il the victim line is valid,
+    ////////////////////////////////////////////////////////////////////////////////
+    inline bool select_before_update( addr_t ad, size_t* selway, addr_t* victim )
+    {
+        size_t      set     = m_y[ad];
+        // search an empty slot (using valid bit)
+        for ( size_t way = 0 ; way < m_ways ; way++ ) 
+        {
+            if ( !cache_val(way, set) ) 
+            {
+                *selway = way;
+                *victim = (addr_t)((cache_tag(way, set) * m_sets) + set);
+                return  false;
+            }
+        }
+        // search an old line (using lru bit)
+        for ( size_t way = 0 ; way < m_ways ; way++ ) 
+        {
+            if ( !cache_lru(way, set) ) 
+            {
+                cache_val(way, set) = false;
+                *selway = way;
+                *victim = (addr_t)((cache_tag(way, set) * m_sets) + set);
+                return  true;
+            }
+        }
+        assert("all lines can't be new at the same time");
+        return true;
+    }
+
+    /////////////////////////////////////////////////////////////////////
+    // The two functions select_before_update() & update_after_select()
+    // can be used to perform a line replacement in two cycles
+    // (when the directory is implemented as a single port RAM)
+    //
+    // The update_after select() function performs the actual
+    // update of the cache line.
+    /////////////////////////////////////////////////////////////////////
+    inline void update_after_select( data_t* buf, size_t way, addr_t ad)
+    {
+        tag_t       tag     = m_z[ad];
+        size_t      set     = m_y[ad];
+
+        cache_tag(way, set) = tag;
+        cache_val(way, set) = true;
+        cache_set_lru(way, set);
+        for ( size_t word = 0 ; word < m_words ; word++ ) cache_data(way, set, word) = buf[word] ;
+    }
+*/
+    ///////////////////////////
+    inline bool find( addr_t ad, 
+                      bool* itlb_buf, bool* dtlb_buf,
+                      size_t* n_way, size_t* n_set, 
+                      addr_t* victim )
+    {
+        size_t      set     = m_y[ad];
+        size_t      selway  = 0;
+        bool        found   = false;
+        bool        cleanup = false;
+
+        for ( size_t way = 0 ; way < m_ways && !found ; way++ ) {
+            if ( !cache_val(way, set) ) {
+                found   = true;
+                cleanup = false;
+                selway  = way;
+            }
+        }
+        if ( !found ) {
+	    /* No invalid way, look for an old way, in priotity order:
+	     * an old way which is not refereced by any tlb
+	     * an old way which is not referenced by the itlb
+	     * an old way which is not referenced by the dtlb
+	     * an old way 
+	     */
+            for ( size_t way = 0 ; way < m_ways && !found ; way++ ) {
+                if ( !cache_lru(way, set) && !itlb_buf[m_sets*way+set]
+		    && !dtlb_buf[m_sets*way+set]) {
+                    found   = true;
+                    cleanup = true;
+                    selway  = way;
+                }
+            }
+            for ( size_t way = 0 ; way < m_ways && !found ; way++ ) {
+                if ( !cache_lru(way, set) && !itlb_buf[m_sets*way+set]) {
+                    found   = true;
+                    cleanup = true;
+                    selway = way;
+                }
+            }
+            for ( size_t way = 0 ; way < m_ways && !found ; way++ ) {
+                if ( !cache_lru(way, set) && !dtlb_buf[m_sets*way+set]) {
+                    found   = true;
+                    cleanup = true;
+                    selway = way;
+                }
+            }
+            for ( size_t way = 0 ; way < m_ways && !found ; way++ ) {
+                if ( !cache_lru(way, set)) {
+                    found   = true;
+                    cleanup = true;
+                    selway = way;
+                }
+            }
+        }
+	assert(found && "all ways can't be new at the same time");
+        *victim = (addr_t)((cache_tag(selway, set) * m_sets) + set);
+        cache_val(selway, set) = false;
+        *n_way = selway;
+        *n_set = set;
+        return cleanup;
+    }
+
+    /////////////////////////////////////////////////////////////////////////
+    inline void update( addr_t ad, size_t n_way, size_t n_set, data_t* buf )
+    {
+        tag_t tag = m_z[ad];
+
+        cache_tag(n_way, n_set) = tag;
+        cache_val(n_way, n_set) = true;
+        cache_set_lru(n_way, n_set);
+        for ( size_t word = 0 ; word < m_words ; word++ ) {
+            cache_data(n_way, n_set, word) = buf[word] ;
+        }
+    }
+
+    ///////////////////////////////////////////////////////////////////
+    // cleanupcheck function is used for checking whether a line exists
+    inline bool cleanupcheck( addr_t ad )
+    {
+        const tag_t       tag  = m_z[ad];
+        const size_t      set  = m_y[ad];
+
+        for ( size_t way = 0; way < m_ways; way++ ) {
+            if ( (tag == cache_tag(way, set)) && cache_val(way, set) ) {
+                return true;
+            }
+        }
+        return false;
+    }
+
+    ///////////////////////////
+    void fileTrace(FILE* file)
+    {
+        for( size_t nway = 0 ; nway < m_ways ; nway++) 
+        {
+            for( size_t nset = 0 ; nset < m_sets ; nset++) 
+            {
+                if( cache_val(nway, nset) ) fprintf(file, " V / ");
+                else                        fprintf(file, "   / ");
+                fprintf(file, "way %d / ", (int)nway);
+                fprintf(file, "set %d / ", (int)nset);
+                fprintf(file, "@ = %08zX / ", ((cache_tag(nway, nset)*m_sets+nset)*m_words*4));
+                for( size_t nword = m_words ; nword > 0 ; nword--) 
+                {
+                    unsigned int data = cache_data(nway, nset, nword-1);
+                    fprintf(file, "%08X ", data );
+                }
+                fprintf(file, "\n");
+            }
+        }
+    }
+
+    ////////////////////////
+    inline void printTrace()
+    {
+        for ( size_t way = 0; way < m_ways ; way++ ) 
+        {
+            for ( size_t set = 0 ; set < m_sets ; set++ )
+            {
+                if ( cache_val(way,set) ) std::cout << "  * " ;
+                else                      std::cout << "    " ;
+                std::cout << std::dec << "way " << way << std::hex << " | " ;
+                std::cout << "@ " << (cache_tag(way,set)*m_words*m_sets+m_words*set)*4 ;
+                for ( size_t word = 0 ; word < m_words ; word++ )
+                {
+                    std::cout << " | " << cache_data(way,set,word) ;
+                }
+                std::cout << std::endl ;
+            }
+        }
+    }
+    
+};
+
+} // namespace soclib
+
+#endif
+
+// Local Variables:
+// tab-width: 4
+// c-basic-offset: 4
+// c-file-offsets:((innamespace . 0)(inline-open . 0))
+// indent-tabs-mode: nil
+// End:
+
+// vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4
+
Index: branches/v4/platforms/almos-tsarv3-platforms/common/generic_cache/metadata/generic_cache.sd
===================================================================
--- branches/v4/platforms/almos-tsarv3-platforms/common/generic_cache/metadata/generic_cache.sd	(revision 371)
+++ branches/v4/platforms/almos-tsarv3-platforms/common/generic_cache/metadata/generic_cache.sd	(revision 371)
@@ -0,0 +1,16 @@
+
+# -*- python -*-
+
+__id__ = "$Id: generic_cache.sd 917 2009-03-12 10:10:06Z nipo $"
+__version__ = "$Revision: 917 $"
+
+Module('caba:generic_cache',
+	classname = 'soclib::GenericCache',
+	header_files = ['../include/generic_cache.h',],
+	   tmpl_parameters = [
+	parameter.Type('addr_t'),
+	],
+	uses = [Uses('common:mapping_table'),
+			Uses('common:address_masking_table',
+				 data_t = parameter.Reference('addr_t')),],
+)
Index: branches/v4/platforms/almos-tsarv3-platforms/common/generic_fifo/include/caba/generic_fifo.h
===================================================================
--- branches/v4/platforms/almos-tsarv3-platforms/common/generic_fifo/include/caba/generic_fifo.h	(revision 371)
+++ branches/v4/platforms/almos-tsarv3-platforms/common/generic_fifo/include/caba/generic_fifo.h	(revision 371)
@@ -0,0 +1,179 @@
+/* -*- c++ -*-
+ *
+ * SOCLIB_LGPL_HEADER_BEGIN
+ * 
+ * This file is part of SoCLib, GNU LGPLv2.1.
+ * 
+ * SoCLib is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU Lesser General Public License as published
+ * by the Free Software Foundation; version 2.1 of the License.
+ * 
+ * SoCLib is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * Lesser General Public License for more details.
+ * 
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with SoCLib; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301 USA
+ * 
+ * SOCLIB_LGPL_HEADER_END
+ *
+ * Copyright (c) UPMC, Lip6, Asim
+ *         Nicolas Pouillon <nipo@ssji.net>, 2007
+ *         Alain Greiner <alain.greiner@lip6.fr>, 2003
+ *
+ * Maintainers: nipo
+ */
+#ifndef SOCLIB_CABA_GENERIC_FIFO_H
+#define SOCLIB_CABA_GENERIC_FIFO_H
+
+#include <systemc>
+#include "register.h"
+
+namespace soclib { namespace caba {
+
+using namespace sc_core;
+
+template<typename T>
+class GenericFifo
+{
+    T *m_data;
+    sc_signal<int>    r_ptr;
+    sc_signal<int>    r_ptw;
+    sc_signal<int>    r_fill_state;
+    int m_depth;
+public:
+    typedef T data_t;
+
+    void print (void) const
+    {
+        std::cout << "r_fill_state  : " << r_fill_state << std::endl;
+        std::cout << "r_ptr/ptw/max : " << r_ptr << " - " << r_ptw << " - " << m_depth << std::endl;
+        std::cout << "m_data        : " << std::hex;
+        int i=0;
+        while (i<r_fill_state)
+            {
+                std::cout << m_data[(r_ptr+i)%m_depth] <<", ";
+                i++;
+            }
+        std::cout << std::dec << "end" << std::endl;
+    }
+
+    size_t size() const
+    {
+        return m_depth;
+    }
+
+    void init()
+    {
+        r_ptr = 0;
+        r_ptw = 0;
+        r_fill_state = 0;
+    }
+
+    inline uint32_t filled_status() const
+    {
+        return (uint32_t)r_fill_state;
+    }
+
+    inline bool empty() const
+    {
+        return !(uint32_t)r_fill_state;
+    }
+
+    inline bool full() const
+    {
+        return r_fill_state == m_depth;
+    }
+
+    void simple_put(const T &din)
+    {
+        if (r_fill_state != m_depth) { 
+            r_fill_state = r_fill_state + 1;
+            r_ptw = (r_ptw + 1) % m_depth;
+            m_data[r_ptw] = din; 
+        }
+    }
+
+    void simple_get()
+    {
+        if (r_fill_state != 0) {
+            r_fill_state = r_fill_state - 1;
+            r_ptr = (r_ptr + 1) % m_depth;
+        }
+    }
+
+    void put_and_get(const T &din)
+    {
+        if (r_fill_state == m_depth) {
+            r_fill_state = r_fill_state - 1;
+            r_ptr = (r_ptr + 1) % m_depth;
+        } else if (r_fill_state == 0) {
+            r_fill_state = r_fill_state + 1;
+            r_ptw = (r_ptw + 1) % m_depth;
+            m_data[r_ptw] = din; 
+        } else {
+            r_ptr = (r_ptr + 1) % m_depth;
+            r_ptw = (r_ptw + 1) % m_depth;
+            m_data[r_ptw] = din; 
+        }
+    }
+
+    void update (bool get, bool put, const T& din)
+    {
+        if (put and get)
+            put_and_get(din);
+        else
+        {
+            if (put)
+                simple_put(din);
+            if (get)
+                simple_get();
+        }
+    }
+
+    inline bool rok() const
+    {
+        return (r_fill_state != 0);
+    }
+
+    inline bool wok() const
+    {
+        return (r_fill_state != m_depth);
+    }
+
+    inline const T &read() const
+    {
+        return m_data[r_ptr];
+    }
+
+    GenericFifo(const std::string &name, size_t depth)
+        : m_data(new T[depth]),
+          r_ptr((name+"_r_ptr").c_str()),
+          r_ptw((name+"_r_ptw").c_str()),
+          r_fill_state((name+"_r_fill_state").c_str()),
+          m_depth(depth)
+    {
+    }
+
+    ~GenericFifo()
+    {
+        delete [] m_data;
+    }
+};
+
+}}
+
+#endif /* SOCLIB_CABA_GENERIC_FIFO_H */
+
+// Local Variables:
+// tab-width: 4
+// c-basic-offset: 4
+// c-file-offsets:((innamespace . 0)(inline-open . 0))
+// indent-tabs-mode: nil
+// End:
+
+// vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4
+
Index: branches/v4/platforms/almos-tsarv3-platforms/common/generic_fifo/metadata/generic_fifo.sd
===================================================================
--- branches/v4/platforms/almos-tsarv3-platforms/common/generic_fifo/metadata/generic_fifo.sd	(revision 371)
+++ branches/v4/platforms/almos-tsarv3-platforms/common/generic_fifo/metadata/generic_fifo.sd	(revision 371)
@@ -0,0 +1,10 @@
+
+# -*- python -*-
+
+__id__ = "$Id: generic_fifo.sd 917 2009-03-12 10:10:06Z nipo $"
+__version__ = "$Revision: 917 $"
+
+Module('caba:generic_fifo',
+	classname = 'soclib::caba::GenericFifo',
+	header_files = ['../include/caba/generic_fifo.h',],
+)
Index: branches/v4/platforms/almos-tsarv3-platforms/common/generic_tlb/include/generic_tlb.h
===================================================================
--- branches/v4/platforms/almos-tsarv3-platforms/common/generic_tlb/include/generic_tlb.h	(revision 371)
+++ branches/v4/platforms/almos-tsarv3-platforms/common/generic_tlb/include/generic_tlb.h	(revision 371)
@@ -0,0 +1,1149 @@
+/*****************************************************************
+ * File         : generic_tlb_40bits.h
+ * Date         : 02/06/2009
+ * Authors      : Alain Greiner, Yang GAO
+ * Copyright    : UPMC/LIP6
+ * 
+ * This file is distributed under the LGPL licence agreement.
+ ******************************************************************
+ * This object is a generic TLB (Translation Lookaside Buffer) to
+ * translate a 40 bits physical address for Hypertransport.
+ * It is implemented as a set-associative cache.
+ * The replacement algorithm is pseudo-LRU.
+ * Each TLB entry has the following format:
+ * - bool       valid            (0: unmapped; 1: mapped)
+ * - bool       locally accessed 
+ * - bool       remotely accessed 
+ * - bool       cacheable   (cached)
+ * - bool       writable    (writable access bit)
+ * - bool       executable  (executable access bit)
+ * - bool       user        (access in user mode allowed)
+ * - bool       global      (PTE not invalidated by a TLB flush)
+ * - bool       dirty       (page has been modified)
+ * Additional flag bits for every tlb entry: 
+ * - bool       pagesize    (0: 4K page size; 1: 2M page size)
+ * - bool       lru         (recently used for replace in TLB)
+ * - uint32_t   vpn         (virtual page number)
+ * - uint32_t   ppn         (physical page number)
+ *
+ * valid, lru and global are stored in registers, others are in ram.
+ *
+ *****************************************************************
+ * This file has three constructor parameters:
+ * - nways  : number of ways per associative set.
+ * - nsets  : number of associative sets.
+ * Both nways & nsets must be power of 2 no larger than 64.
+ *****************************************************************/
+
+#ifndef SOCLIB_CABA_GENERIC_TLB_H
+#define SOCLIB_CABA_GENERIC_TLB_H
+
+#include <inttypes.h>
+#include <systemc>
+#include <assert.h>
+#include "static_assert.h"
+#include "arithmetics.h"
+
+namespace soclib { 
+namespace caba {
+
+using namespace sc_core;
+
+    // PTE information struct
+    typedef struct pte_info_s {
+        bool v;    // valid             
+        bool t;    // type              
+        bool l;    // locally accessed     
+        bool r;    // remotely accessed 
+        bool c;    // cacheable    
+        bool w;    // writable    
+        bool x;    // executable  
+        bool u;    // user        
+        bool g;    // global      
+        bool d;    // dirty       
+    }pte_info_t;
+
+    enum {  
+        PTD_ID2_MASK  = 0x001FF000,
+        PAGE_K_MASK   = 0x00000FFF,
+        PAGE_M_MASK   = 0x001FFFFF,
+    };
+
+    enum {
+        PTE_V_MASK = 0x80000000,
+        PTE_T_MASK = 0x40000000,
+        PTE_L_MASK = 0x20000000,
+        PTE_R_MASK = 0x10000000,
+        PTE_C_MASK = 0x08000000,
+        PTE_W_MASK = 0x04000000,
+        PTE_X_MASK = 0x02000000,
+        PTE_U_MASK = 0x01000000,
+        PTE_G_MASK = 0x00800000,
+        PTE_D_MASK = 0x00400000,
+    };
+
+    enum {  
+        PTE_V_SHIFT = 31,
+        PTE_T_SHIFT = 30,
+        PTE_L_SHIFT = 29,
+        PTE_R_SHIFT = 28,
+        PTE_C_SHIFT = 27,
+        PTE_W_SHIFT = 26,
+        PTE_X_SHIFT = 25,
+        PTE_U_SHIFT = 24,
+        PTE_G_SHIFT = 23,
+        PTE_D_SHIFT = 22,
+    };
+
+    enum {  
+        PAGE_M_NBITS = 21,
+        PAGE_K_NBITS = 12,
+        INDEX1_NBITS = 11,
+    };
+
+using soclib::common::uint32_log2;
+
+// registers describing a TLB entry state
+typedef struct tlb_entry_state {
+	sc_signal<bool> v; //valid
+	sc_signal<bool> g; //global
+	sc_signal<bool> l; //LRU
+} tlb_entry_state_t;
+
+// registers describing a tlb set state
+typedef class tlb_set_state {
+private:
+	tlb_entry_state_t *entries;
+	size_t nways;
+public:
+	tlb_set_state()
+	{
+	}
+
+	~tlb_set_state()
+	{
+		delete [] entries;
+	}
+
+	void
+	init(size_t m_nways)
+	{
+		nways = m_nways;
+		entries = new tlb_entry_state_t[nways];
+	}
+
+	bool get_valid(size_t way)
+	{
+		return entries[way].v;
+	}
+	void set_valid(size_t way)
+	{
+		assert(entries[way].l == false &&
+		    "invalid entry should not have LRU");
+		entries[way].v = true;
+	}
+	void clear_valid(size_t way)
+	{
+		entries[way].v = false;
+		entries[way].l = false;
+	}
+
+	bool get_global(size_t way)
+	{
+		return entries[way].g;
+	}
+	void set_global(size_t way)
+	{
+		entries[way].g = true;
+	}
+	void clear_global(size_t way)
+	{
+		entries[way].g = false;
+	}
+
+	bool get_lru(size_t way)
+	{
+		return entries[way].l;
+	}
+	void set_lru(size_t way)
+	{
+		entries[way].l = true;
+		/*
+		 * if all LRU bits for the set are true, clear them
+		 */
+		for (size_t i = 0; i < nways; i++) 
+        {
+			if (i == way)
+				continue;
+			if (entries[i].l == false)
+				return;
+		}
+		// all LRU bits are set
+		for (size_t i = 0; i < nways; i++) 
+        {
+			entries[i].l = false;
+		}
+	}
+	void clear_lru(size_t way)
+	{
+		entries[way].l = false;
+	}
+
+	void reset()
+	{
+		for (size_t i = 0; i < nways; i++) 
+        {
+			entries[i].l = false;
+			entries[i].g = false;
+			entries[i].v = false;
+		}
+	}
+} tlb_set_state_t;
+
+template<typename paddr_t>
+class GenericTlb
+{
+protected:
+    typedef uint32_t vaddr_t;
+    typedef uint32_t data_t;
+
+    const size_t  m_nways;
+    const size_t  m_nsets;
+    const size_t  m_paddr_nbits;
+    const size_t  m_sets_shift;
+    const size_t  m_sets_mask;
+
+    data_t  *m_ppn; 
+    data_t  *m_vpn;
+    bool    *m_pagesize;  
+    bool    *m_locacc;
+    bool    *m_remacc;
+    bool    *m_cacheable;
+    bool    *m_writable;
+    bool    *m_executable;
+    bool    *m_user;
+    bool    *m_dirty;
+
+    tlb_set_state_t *m_setsstate;
+
+public:
+    // access methods 
+    void setlru(size_t way, size_t set)
+    { 
+        m_setsstate[set].set_lru(way); 
+    }
+
+    void clearlru(size_t way, size_t set)
+    { 
+        m_setsstate[set].clear_lru(way); 
+    }
+
+    bool lru(size_t way, size_t set)
+    { 
+        return m_setsstate[set].get_lru(way); 
+    }
+
+    void setvalid(size_t way, size_t set)
+    { 
+        m_setsstate[set].set_valid(way); 
+    }
+
+    void clearvalid(size_t way, size_t set)
+    { 
+        m_setsstate[set].clear_valid(way); 
+    }
+
+    bool valid(size_t way, size_t set)
+    { 
+        return m_setsstate[set].get_valid(way); 
+    }
+
+    void setglobal(size_t way, size_t set)
+    { 
+        m_setsstate[set].set_global(way); 
+    }
+
+    void clearglobal(size_t way, size_t set)
+    { 
+        m_setsstate[set].clear_global(way); 
+    }
+
+    bool global(size_t way, size_t set)
+    { 
+        return m_setsstate[set].get_global(way); 
+    }
+
+    data_t &ppn(size_t way, size_t set)
+    { 
+        return m_ppn[(way*m_nsets)+set]; 
+    }
+
+    data_t &vpn(size_t way, size_t set)
+    { 
+        return m_vpn[(way*m_nsets)+set]; 
+    }
+
+    bool &pagesize(size_t way, size_t set)
+    { 
+        return m_pagesize[(way*m_nsets)+set]; 
+    }
+
+    bool &locacc(size_t way, size_t set)
+    { 
+        return m_locacc[(way*m_nsets)+set]; 
+    }
+
+    bool &remacc(size_t way, size_t set)
+    { 
+        return m_remacc[(way*m_nsets)+set]; 
+    }
+
+    bool &cacheable(size_t way, size_t set)
+    { 
+        return m_cacheable[(way*m_nsets)+set]; 
+    }
+
+    bool &writable(size_t way, size_t set)
+    { 
+        return m_writable[(way*m_nsets)+set]; 
+    }
+
+    bool &executable(size_t way, size_t set)
+    { 
+        return m_executable[(way*m_nsets)+set]; 
+    }
+
+    bool &user(size_t way, size_t set)
+    { 
+        return m_user[(way*m_nsets)+set]; 
+    }
+
+    bool &dirty(size_t way, size_t set)
+    { 
+        return m_dirty[(way*m_nsets)+set]; 
+    }
+
+    //////////////////////////////////////////////////////////////
+    // constructor checks parameters, allocates the memory
+    // and computes m_page_mask, m_sets_mask and m_sets_shift
+    //////////////////////////////////////////////////////////////
+    GenericTlb(size_t nways, size_t nsets, size_t paddr_nbits):
+    m_nways(nways),
+    m_nsets(nsets),
+    m_paddr_nbits(paddr_nbits),
+    m_sets_shift(uint32_log2(nsets)),
+    m_sets_mask((1<<(int)uint32_log2(nsets))-1)
+    {
+        assert(IS_POW_OF_2(nsets));
+        assert(IS_POW_OF_2(nways));
+        assert(nsets <= 64);
+        assert(nways <= 64);
+
+        if((m_paddr_nbits < 32) || (m_paddr_nbits > 42))
+        {
+            printf("Error in the genericTlb component\n");
+            printf("The physical address parameter must be in the range [32,42]\n");
+            exit(1);
+        } 
+
+        m_ppn        = new data_t[nways * nsets];
+        m_vpn        = new data_t[nways * nsets];
+        m_pagesize   = new bool[nways * nsets];
+        m_locacc     = new bool[nways * nsets];
+        m_remacc     = new bool[nways * nsets];
+        m_cacheable   = new bool[nways * nsets];
+        m_writable   = new bool[nways * nsets];
+        m_executable = new bool[nways * nsets];
+        m_user       = new bool[nways * nsets];
+        m_dirty      = new bool[nways * nsets];
+	    m_setsstate = new tlb_set_state_t[nsets];
+	    for (size_t i = 0; i < nsets; i++)
+		    m_setsstate[i].init(nways);
+
+    } // end constructor
+
+    ~GenericTlb()
+    {
+        delete [] m_ppn;
+        delete [] m_vpn;
+        delete [] m_pagesize;
+        delete [] m_locacc;
+        delete [] m_remacc;
+        delete [] m_cacheable;
+        delete [] m_writable;
+        delete [] m_executable;
+        delete [] m_user;
+        delete [] m_dirty;
+	    delete [] m_setsstate;
+    }
+
+    /////////////////////////////////////////////////////////////
+    //  This method resets all the TLB entry.
+    /////////////////////////////////////////////////////////////
+    void reset() 
+    {
+	    for (size_t i = 0; i < m_nsets; i++)
+		    m_setsstate[i].reset();
+    } 
+
+    /////////////////////////////////////////////////////////
+    //  This method returns "false" in case of MISS
+    //  In case of HIT, the physical address, 
+    //  the pte informations, way and set are returned. 
+    /////////////////////////////////////////////////////////
+    bool translate(  vaddr_t vaddress,      // virtual address
+                            paddr_t *paddress,     // return physique address
+                            pte_info_t *pte_info,  // return pte information
+                            size_t *tw,            // return way  
+                            size_t *ts )           // return set   
+    {
+        size_t m_set = (vaddress >> PAGE_M_NBITS) & m_sets_mask; 
+        size_t k_set = (vaddress >> PAGE_K_NBITS) & m_sets_mask; 
+
+        for( size_t way = 0; way < m_nways; way++ ) 
+        {
+            // TLB hit test for 2M page size
+            if( valid(way,m_set) && pagesize(way,m_set) &&
+               (vpn(way,m_set) == (vaddress >> (PAGE_M_NBITS + m_sets_shift))) ) 
+            {
+                pte_info->l = locacc(way,m_set);
+                pte_info->r = remacc(way,m_set);
+                pte_info->c = cacheable(way,m_set);
+                pte_info->w = writable(way,m_set);
+                pte_info->x = executable(way,m_set);
+                pte_info->u = user(way,m_set);
+                pte_info->g = global(way,m_set);
+                pte_info->d = dirty(way,m_set);
+                *tw = way;
+                *ts = m_set;
+                *paddress = (paddr_t)((paddr_t)ppn(way,m_set) << PAGE_M_NBITS) | (paddr_t)(vaddress & PAGE_M_MASK);
+		setlru(way, m_set);
+                return true;
+            }
+
+            // TLB hit test for 4K page size
+            if( valid(way,k_set) && !pagesize(way,k_set) &&
+               (vpn(way,k_set) == (vaddress >> (PAGE_K_NBITS + m_sets_shift))) ) 
+            {  
+                pte_info->l = locacc(way,k_set);
+                pte_info->r = remacc(way,k_set);
+                pte_info->c = cacheable(way,k_set);
+                pte_info->w = writable(way,k_set);
+                pte_info->x = executable(way,k_set);
+                pte_info->u = user(way,k_set);
+                pte_info->g = global(way,k_set);
+                pte_info->d = dirty(way,k_set);
+                *tw = way;
+                *ts = k_set;
+                *paddress = (paddr_t)((paddr_t)ppn(way,k_set) << PAGE_K_NBITS) | (paddr_t)(vaddress & PAGE_K_MASK);
+		setlru(way, k_set);
+                return true;   
+            } 
+        } 
+        return false;
+    } // end translate()
+
+    /////////////////////////////////////////////////////////
+    //  This method returns "false" in case of MISS
+    //  In case of HIT, the physical page number is returned. 
+    /////////////////////////////////////////////////////////
+    bool translate(vaddr_t vaddress, paddr_t *paddress) 
+    {
+        size_t m_set = (vaddress >> PAGE_M_NBITS) & m_sets_mask; 
+        size_t k_set = (vaddress >> PAGE_K_NBITS) & m_sets_mask; 
+        for( size_t way = 0; way < m_nways; way++ ) 
+        {
+            // TLB hit test for 2M page size
+            if( valid(way,m_set) && pagesize(way,m_set) &&
+               (vpn(way,m_set) == (vaddress >> (PAGE_M_NBITS + m_sets_shift))) ) 
+            {
+                *paddress = (paddr_t)((paddr_t)ppn(way,m_set) << PAGE_M_NBITS) | (paddr_t)(vaddress & PAGE_M_MASK);
+		setlru(way, m_set);
+                return true;
+            }
+
+            // TLB hit test for 4K page size
+            if( valid(way,k_set) && !pagesize(way,k_set) &&
+               (vpn(way,k_set) == (vaddress >> (PAGE_K_NBITS + m_sets_shift))) ) 
+            {  
+                *paddress = (paddr_t)((paddr_t)ppn(way,k_set) << PAGE_K_NBITS) | (paddr_t)(vaddress & PAGE_K_MASK);
+		setlru(way, k_set);
+                return true;   
+            } 
+        }
+        return false;
+    } // end translate()
+    /////////////////////////////////////////////////////////////
+    //  This method resets all VALID bits in one cycle,
+    //  when the the argument is true.
+    //  Locked descriptors are preserved when it is false.
+    /////////////////////////////////////////////////////////////
+    void flush(bool all) 
+    {
+        for( size_t way = 0; way < m_nways; way++ ) 
+        {
+            for(size_t set = 0; set < m_nsets; set++) 
+            {
+		        if (!valid (way,set))
+			        continue;
+                if(global(way,set)) 
+                {
+                    if(all) 
+                    {
+			            clearvalid(way,set); // forced reset, the locked page invalid too
+		            }
+                } 
+                else 
+                {
+                    clearvalid(way,set); // not forced reset, the locked page conserve  
+                }
+            } 
+        } 
+    } // end flush
+
+    uint32_t getpte(size_t way,size_t set)   
+    {
+        data_t pte = 0; 
+        if ( pagesize(way,set) )    // 2M page size
+        {
+           pte = (data_t)ppn(way,set) | (PTE_V_MASK & (valid(way,set) << PTE_V_SHIFT));
+    
+           if ( locacc(way,set) )
+               pte = pte | PTE_L_MASK;
+           if ( remacc(way,set) )
+               pte = pte | PTE_R_MASK;
+           if ( cacheable(way,set) )
+               pte = pte | PTE_C_MASK;
+           if ( writable(way,set) )
+               pte = pte | PTE_W_MASK;
+           if ( executable(way,set) )
+               pte = pte | PTE_X_MASK;
+           if ( user(way,set) )
+               pte = pte | PTE_U_MASK;
+           if ( global(way,set) )
+               pte = pte | PTE_G_MASK;
+           if ( dirty(way,set) )
+               pte = pte | PTE_D_MASK;
+        }
+        else    // 4K page size
+        {
+           pte = (data_t)(PTE_V_MASK & (valid(way,set) << PTE_V_SHIFT));
+    
+           if ( locacc(way,set) )
+               pte = pte | PTE_L_MASK;
+           if ( remacc(way,set) )
+               pte = pte | PTE_R_MASK;
+           if ( cacheable(way,set) )
+               pte = pte | PTE_C_MASK;
+           if ( writable(way,set) )
+               pte = pte | PTE_W_MASK;
+           if ( executable(way,set) )
+               pte = pte | PTE_X_MASK;
+           if ( user(way,set) )
+               pte = pte | PTE_U_MASK;
+           if ( global(way,set) )
+               pte = pte | PTE_G_MASK;
+           if ( dirty(way,set) )
+               pte = pte | PTE_D_MASK;
+        }
+        return pte;
+    } // end getpte()
+
+    /////////////////////////////////////////////////////////////
+    //  This method return the index of the least recently
+    //  used descriptor in the associative set.
+    /////////////////////////////////////////////////////////////
+    size_t getlru(size_t set)
+    {
+        // check val bit firstly, replace the invalid PTE
+        for(size_t way = 0; way < m_nways; way++) 
+        {
+            if( !valid(way,set) ) 
+            {
+                return way;
+            }
+        } 
+
+        // then we check bit lock, remplace and old way which is not global
+        for( size_t way = 0; way < m_nways; way++ ) 
+        {
+            if( !global(way,set) && !lru(way,set) ) 
+            {
+                return way;
+            } 
+        }
+	
+	    // finally remplace the first old way
+        for( size_t way = 0; way < m_nways; way++ ) 
+        {
+            if( !lru(way,set) ) 
+            {
+                return way;
+            } 
+        }
+
+        assert(0 && "all TLB ways can't be new at the same time");
+	    return 0; /* avoid gcc warning */
+    } // end getlru()
+
+    /////////////////////////////////////////////////////////////
+    //  This method writes a new 2M page size entry in the TLB.
+    /////////////////////////////////////////////////////////////
+    void update(data_t pte, vaddr_t vaddress) 
+    {
+        size_t set = (vaddress >> PAGE_M_NBITS) & m_sets_mask; 
+        size_t way = getlru(set);
+      
+        vpn(way,set) = vaddress >> (PAGE_M_NBITS + m_sets_shift);
+        ppn(way,set) = pte & ((1<<(m_paddr_nbits - PAGE_M_NBITS))-1);
+
+        setvalid(way,set);
+        pagesize(way,set)   = true;
+        setlru(way,set);
+        locacc(way,set)     = (((pte & PTE_L_MASK) >> PTE_L_SHIFT) == 1) ? true : false;
+        remacc(way,set)     = (((pte & PTE_R_MASK) >> PTE_R_SHIFT) == 1) ? true : false;
+        cacheable(way,set)  = (((pte & PTE_C_MASK) >> PTE_C_SHIFT) == 1) ? true : false;
+        writable(way,set)   = (((pte & PTE_W_MASK) >> PTE_W_SHIFT) == 1) ? true : false;       
+        executable(way,set) = (((pte & PTE_X_MASK) >> PTE_X_SHIFT) == 1) ? true : false;
+        user(way,set)       = (((pte & PTE_U_MASK) >> PTE_U_SHIFT) == 1) ? true : false;
+	    if (((pte & PTE_G_MASK) >> PTE_G_SHIFT) == 1)
+		    setglobal(way,set);
+	    else
+		    clearglobal(way,set);
+
+        dirty(way,set)      = (((pte & PTE_D_MASK) >> PTE_D_SHIFT) == 1) ? true : false; 
+    } // end update()
+
+    /////////////////////////////////////////////////////////////
+    //  This method writes a new 4K page size entry in the TLB.
+    /////////////////////////////////////////////////////////////
+    void update(data_t pte, data_t ppn2 , vaddr_t vaddress) 
+    {
+        size_t set = (vaddress >> PAGE_K_NBITS) & m_sets_mask; 
+        size_t way = getlru(set);
+      
+        vpn(way,set) = vaddress >> (PAGE_K_NBITS + m_sets_shift);
+        ppn(way,set) = ppn2 & ((1<<(m_paddr_nbits - PAGE_K_NBITS))-1);  
+
+        setvalid(way,set);
+        pagesize(way,set)   = false;
+        setlru(way,set);
+        locacc(way,set)     = (((pte & PTE_L_MASK) >> PTE_L_SHIFT) == 1) ? true : false;
+        remacc(way,set)     = (((pte & PTE_R_MASK) >> PTE_R_SHIFT) == 1) ? true : false;
+        cacheable(way,set)  = (((pte & PTE_C_MASK) >> PTE_C_SHIFT) == 1) ? true : false;
+        writable(way,set)   = (((pte & PTE_W_MASK) >> PTE_W_SHIFT) == 1) ? true : false;       
+        executable(way,set) = (((pte & PTE_X_MASK) >> PTE_X_SHIFT) == 1) ? true : false;
+        user(way,set)       = (((pte & PTE_U_MASK) >> PTE_U_SHIFT) == 1) ? true : false;
+	    if (((pte & PTE_G_MASK) >> PTE_G_SHIFT) == 1)
+		    setglobal(way,set);
+	    else
+		    clearglobal(way,set);
+        dirty(way,set)      = (((pte & PTE_D_MASK) >> PTE_D_SHIFT) == 1) ? true : false; 
+    } // end update()
+
+    //////////////////////////////////////////////////////////////
+    //  This method invalidates a TLB entry
+    //  identified by the virtual page number.
+    //////////////////////////////////////////////////////////////
+    bool inval(vaddr_t vaddress) 
+    {
+        size_t m_set = (vaddress >> PAGE_M_NBITS) & m_sets_mask; 
+        size_t k_set = (vaddress >> PAGE_K_NBITS) & m_sets_mask; 
+        for( size_t way = 0; way < m_nways; way++ ) 
+        {
+            // TLB hit test for 2M page size
+            if( valid(way,m_set) && pagesize(way,m_set) &&
+               (vpn(way,m_set) == (vaddress >> (PAGE_M_NBITS + m_sets_shift))) ) 
+            {
+                clearvalid(way,m_set);
+                return true;
+            }
+
+            // TLB hit test for 4K page size
+            if( valid(way,k_set) && !pagesize(way,k_set) &&
+               (vpn(way,k_set) == (vaddress >> (PAGE_K_NBITS + m_sets_shift))) ) 
+            {  
+                clearvalid(way,k_set);
+                return true;   
+            } 
+        } 
+        return false;
+    } // end translate()
+
+    /////////////////////////////////////////////////////////////
+    //  This method writes a new entry in the TLB.
+    /////////////////////////////////////////////////////////////
+    void setdirty(size_t way, size_t set)
+    {
+        dirty(way,set) = true;
+    } // end setdirty()
+
+    /////////////////////////////////////////////////////////////
+    //  This method return the page size. 
+    /////////////////////////////////////////////////////////////
+    bool getpagesize(size_t way, size_t set)
+    {
+        return pagesize(way,set);
+    }
+
+}; // GenericTlb
+
+template<typename paddr_t>
+class GenericCcTlb : public GenericTlb<paddr_t>
+{
+public:
+    typedef uint32_t vaddr_t;
+    typedef uint32_t data_t;
+
+    paddr_t  *m_nline; 
+
+    // access methods 
+    paddr_t &nline(size_t way, size_t set)
+    { 
+        return m_nline[(way*this->m_nsets)+set]; 
+    }
+
+public:
+    //////////////////////////////////////////////////////////////
+    // constructor checks parameters, allocates the memory
+    // and computes m_page_mask, m_sets_mask and m_sets_shift
+    //////////////////////////////////////////////////////////////
+    GenericCcTlb(size_t nways, size_t nsets, size_t paddr_nbits):GenericTlb<paddr_t>::GenericTlb(nways, nsets, paddr_nbits)
+    {
+        m_nline = new paddr_t[this->m_nways * this->m_nsets];
+    } // end constructor
+
+    ~GenericCcTlb()
+    {
+        delete [] m_nline;
+    }
+
+    /////////////////////////////////////////////////////////
+    //  This method returns "false" in case of MISS
+    //  In case of HIT, the physical address, 
+    //  the pte informations, way and set are returned. 
+    /////////////////////////////////////////////////////////
+    bool cctranslate( vaddr_t vaddress,      // virtual address
+                             paddr_t *paddress,     // return physique address
+                             pte_info_t *pte_info,  // return pte information
+                             paddr_t *victim_index, // return nline
+                             size_t *tw,            // return way  
+                             size_t *ts )           // return set   
+    {
+        size_t m_set = (vaddress >> PAGE_M_NBITS) & this->m_sets_mask; 
+        size_t k_set = (vaddress >> PAGE_K_NBITS) & this->m_sets_mask; 
+
+        for( size_t way = 0; way < this->m_nways; way++ ) 
+        {
+            // TLB hit test for 2M page size
+            if( this->valid(way,m_set) && this->pagesize(way,m_set) &&
+               (this->vpn(way,m_set) == (vaddress >> (PAGE_M_NBITS + this->m_sets_shift))) ) 
+            {
+                pte_info->l = this->locacc(way,m_set);
+                pte_info->r = this->remacc(way,m_set);
+                pte_info->c = this->cacheable(way,m_set);
+                pte_info->w = this->writable(way,m_set);
+                pte_info->x = this->executable(way,m_set);
+                pte_info->u = this->user(way,m_set);
+                pte_info->g = this->global(way,m_set);
+                pte_info->d = this->dirty(way,m_set);
+                *victim_index = nline(way,m_set);
+                *tw = way;
+                *ts = m_set;
+                *paddress = (paddr_t)((paddr_t)this->ppn(way,m_set) << PAGE_M_NBITS) | (paddr_t)(vaddress & PAGE_M_MASK);
+		//this->setlru(way, m_set);
+                return true;
+            }
+
+            // TLB hit test for 4K page size
+            if( this->valid(way,k_set) && !(this->pagesize(way,k_set)) &&
+               (this->vpn(way,k_set) == (vaddress >> (PAGE_K_NBITS + this->m_sets_shift))) ) 
+            {  
+                pte_info->l = this->locacc(way,k_set);
+                pte_info->r = this->remacc(way,k_set);
+                pte_info->c = this->cacheable(way,k_set);
+                pte_info->w = this->writable(way,k_set);
+                pte_info->x = this->executable(way,k_set);
+                pte_info->u = this->user(way,k_set);
+                pte_info->g = this->global(way,k_set);
+                pte_info->d = this->dirty(way,k_set);
+                *victim_index = nline(way,k_set);
+                *tw = way;
+                *ts = k_set;
+                *paddress = (paddr_t)((paddr_t)this->ppn(way,k_set) << PAGE_K_NBITS) | (paddr_t)(vaddress & PAGE_K_MASK);
+		//this->setlru(way, k_set);
+                return true;   
+            } 
+        } 
+        return false;
+    } // end translate()
+
+    //////////////////////////////////////////////////////////////
+    //  This method invalidates a TLB entry for cc_vcache2
+    //  identified by the virtual page number.
+    //////////////////////////////////////////////////////////////
+    bool inval(vaddr_t vaddress, paddr_t* victim)
+    {
+        paddr_t vic_nline = 0;
+        size_t m_set = (vaddress >> PAGE_M_NBITS) & this->m_sets_mask; 
+        size_t k_set = (vaddress >> PAGE_K_NBITS) & this->m_sets_mask; 
+
+        for( size_t way = 0; way < this->m_nways; way++ ) 
+        {
+            if( this->valid(way,m_set) && this->pagesize(way,m_set) &&
+                (this->vpn(way,m_set) == (vaddress >> (PAGE_M_NBITS + this->m_sets_shift))) ) 
+            {
+                vic_nline = nline(way,m_set);
+                this->clearvalid(way,m_set);
+                break;
+            } 
+
+            if( this->valid(way,k_set) && !(this->pagesize(way,k_set)) &&
+                (this->vpn(way,k_set) == (vaddress >> (PAGE_K_NBITS + this->m_sets_shift))) ) 
+            {
+                vic_nline = nline(way,k_set);
+                this->clearvalid(way,k_set);
+                break;
+            }
+            if ( way == (this->m_nways-1)) return false; 
+        } 
+
+        *victim = vic_nline;
+        // verify whether need a cleanup
+        for( size_t way = 0; way < this->m_nways; way++ ) 
+        {
+            for( size_t set = 0; set < this->m_nsets; set++ ) 
+            {
+                if( (nline(way,set) == vic_nline) && (this->valid(way,set)) ) 
+                {
+                    return false;
+                }
+            } 
+        } 
+        return true;
+    } // end inval()
+
+    //////////////////////////////////////////////////////////////
+    //  This method invalidates a TLB entry for cc_vcache
+    //  identified by the virtual page number.
+    //////////////////////////////////////////////////////////////
+    bool inval1(vaddr_t vaddress, paddr_t* victim)
+    {
+        paddr_t vic_nline = 0;
+        size_t m_set = (vaddress >> PAGE_M_NBITS) & this->m_sets_mask; 
+        size_t k_set = (vaddress >> PAGE_K_NBITS) & this->m_sets_mask; 
+
+        for( size_t way = 0; way < this->m_nways; way++ ) 
+        {
+            if( this->valid(way,m_set) && this->pagesize(way,m_set) &&
+                (this->vpn(way,m_set) == (vaddress >> (PAGE_M_NBITS + this->m_sets_shift))) ) 
+            {
+                vic_nline = nline(way,m_set);
+                this->clearvalid(way,m_set);
+                break;
+            } 
+
+            if( this->valid(way,k_set) && !(this->pagesize(way,k_set)) &&
+                (this->vpn(way,k_set) == (vaddress >> (PAGE_K_NBITS + this->m_sets_shift))) ) 
+            {
+                vic_nline = nline(way,k_set);
+                this->clearvalid(way,k_set);
+                break;
+            }
+            if ( way == (this->m_nways-1)) return false; 
+        } 
+
+        *victim = vic_nline;
+        return true;
+    } // end inval1()
+
+    //////////////////////////////////////////////////////////////
+    //  This method coherence invalidates a TLB entry
+    //  identified by the virtual page number.
+    //////////////////////////////////////////////////////////////
+    void ccinval(size_t invway, size_t invset)
+    {
+        this->clearvalid(invway,invset);
+    } // end ccinval()
+
+    //////////////////////////////////////////////////////////////
+    //  This method coherence invalidates a TLB entry
+    //  identified by the virtual page number.
+    //////////////////////////////////////////////////////////////
+    size_t getnline(size_t way, size_t set)
+    {
+        return nline(way,set);
+    } // end getnline()
+
+    /////////////////////////////////////////////////////////////
+    //  This method for cc_vcache2 is used for context switch.  
+    //  In this case, allTLB entries should be invalidated except 
+    //  global entries.All the entries that are in the same data 
+    //  cache line have the same NLINE. Therefore only all the  
+    //  entries of one datacache line are not global, it send a  
+    //  cleanup request todata cache. The return value indicates 
+    //  whether need a cleanupand cleanup_nline contains the NLINE 
+    //  that is for cleanup.   
+    /////////////////////////////////////////////////////////////
+    bool checkcleanup(size_t nway, size_t nset, paddr_t* cleanup_nline)
+    {
+        bool cleanup = false;
+        bool isglobal = false;
+        if ( this->valid(nway,nset) )
+        {
+            size_t inval_line = nline(nway,nset);
+            for (size_t start = (nway*this->m_nsets+nset); start < this->m_nways*this->m_nsets; start++)
+            {
+                if ( this->valid(start/this->m_nsets,start%this->m_nsets) && (inval_line == nline(start/this->m_nsets,start%this->m_nsets)) )
+                {
+                    if (!this->global(start/this->m_nsets,start%this->m_nsets))
+                    {
+                        this->clearvalid(start/this->m_nsets,start%this->m_nsets);
+                    }
+                    else
+                    {
+                        isglobal = true;
+                    }
+                }
+            }
+
+            cleanup = !isglobal;
+            if(cleanup)
+                *cleanup_nline = inval_line;
+        }
+        return cleanup;
+    } // end checkcleanup
+
+    /////////////////////////////////////////////////////////////
+    //  This method for cc_vcache is used for context switch.  
+    //  In this case, allTLB entries should be invalidated except 
+    //  global entries.All the entries that are in the same data 
+    //  cache line have the same NLINE. Therefore only all the  
+    //  entries of one datacache line are not global, it send a  
+    //  cleanup request todata cache. The return value indicates 
+    //  whether need a cleanupand cleanup_nline contains the NLINE 
+    //  that is for cleanup.   
+    /////////////////////////////////////////////////////////////
+    bool checkcleanup1(size_t nway, size_t nset, paddr_t* cleanup_nline)
+    {
+        bool cleanup = false;
+        bool isglobal = false;
+        if ( this->valid(nway,nset) )
+        {
+            size_t inval_line = nline(nway,nset);
+            if (!this->global(nway,nset))
+            {
+                this->clearvalid(nway,nset);
+            }
+            else
+            {
+                isglobal = true;
+            }
+
+            cleanup = !isglobal;
+            if(cleanup)
+                *cleanup_nline = inval_line;
+        }
+        return cleanup;
+    } // end checkcleanup1
+
+    //////////////////////////////////////////////////////////////////////////
+    //  This method searchs a place for the missed TLB entry, if there is victim,
+    //  a cleanup must be sent. 
+    //////////////////////////////////////////////////////////////////////////
+    bool select(vaddr_t vaddress, paddr_t* victim, size_t *newway, size_t *newset)
+    {
+        size_t selset = vaddress & this->m_sets_mask;
+        size_t selway = this->getlru(selset);
+        bool cleanup = this->valid(selway,selset);
+
+	    if (cleanup) {
+            for( size_t way = 0; way < this->m_nways; way++ ) 
+            {
+                for( size_t set = 0; set < this->m_nsets; set++ ) 
+                {
+		            if ((way == selway) && (set == selset))
+			        continue;
+                    if ((nline(way,set) == nline(selway,selset)) && this->valid(way,set)) 
+                    {
+                        cleanup = false;
+                        break;
+                    }
+                } 
+            } 
+        }
+        
+        if (cleanup) *victim = nline(selway,selset);
+        *newway = selway;
+        *newset = selset;
+        return cleanup;
+    }
+
+    //////////////////////////////////////////////////////////////////////////
+    //  This method searchs a place for the missed TLB entry, if there is victim,
+    //  a cleanup must be sent. 
+    //////////////////////////////////////////////////////////////////////////
+    bool select1(vaddr_t vaddress, paddr_t* victim, size_t *newway, size_t *newset)
+    {
+        size_t selset = vaddress & this->m_sets_mask;
+        size_t selway = this->getlru(selset);
+        bool cleanup = this->valid(selway,selset);
+     
+        if (cleanup) *victim = nline(selway,selset);
+        *newway = selway;
+        *newset = selset;
+        return cleanup;
+    }
+
+    //////////////////////////////////////////////////////////////////////////
+    //  This method writes a new 2M page size entry in the TLB for cc_vcache2.
+    //////////////////////////////////////////////////////////////////////////
+    void update(data_t pte, vaddr_t vaddress, size_t selway, size_t selset, paddr_t line) 
+    {
+        this->vpn(selway,selset) = vaddress >> (PAGE_M_NBITS + this->m_sets_shift);
+        this->ppn(selway,selset) = pte & ((1<<(this->m_paddr_nbits - PAGE_M_NBITS))-1); 
+ 
+        this->setvalid(selway,selset);
+        this->pagesize(selway,selset)   = true;
+	    this->setlru(selway,selset);
+
+        this->locacc(selway,selset)     = (((pte & PTE_L_MASK) >> PTE_L_SHIFT) == 1) ? true : false;
+        this->remacc(selway,selset)     = (((pte & PTE_R_MASK) >> PTE_R_SHIFT) == 1) ? true : false;
+        this->cacheable(selway,selset)  = (((pte & PTE_C_MASK) >> PTE_C_SHIFT) == 1) ? true : false;
+        this->writable(selway,selset)   = (((pte & PTE_W_MASK) >> PTE_W_SHIFT) == 1) ? true : false;       
+        this->executable(selway,selset) = (((pte & PTE_X_MASK) >> PTE_X_SHIFT) == 1) ? true : false;
+        this->user(selway,selset)       = (((pte & PTE_U_MASK) >> PTE_U_SHIFT) == 1) ? true : false;
+	    if (((pte & PTE_G_MASK) >> PTE_G_SHIFT) == 1)
+		    this->setglobal(selway,selset);
+	    else
+		    this->clearglobal(selway,selset);
+        this->dirty(selway,selset)      = (((pte & PTE_D_MASK) >> PTE_D_SHIFT) == 1) ? true : false; 
+        nline(selway,selset) = line;  
+    } // end update()
+
+    //////////////////////////////////////////////////////////////////////////
+    //  This method writes a new 4K page size entry in the TLB for cc_vcache2.
+    //////////////////////////////////////////////////////////////////////////
+    void update(data_t pte, data_t ppn2, vaddr_t vaddress, size_t selway, size_t selset, paddr_t line) 
+    {
+        this->vpn(selway,selset) = vaddress >> (PAGE_K_NBITS + this->m_sets_shift);
+        this->ppn(selway,selset) = ppn2 & ((1<<(this->m_paddr_nbits - PAGE_K_NBITS))-1);  
+        this->setvalid(selway,selset);
+        this->pagesize(selway,selset)   = false;
+	    this->setlru(selway,selset);
+
+        this->locacc(selway,selset)     = (((pte & PTE_L_MASK) >> PTE_L_SHIFT) == 1) ? true : false;
+        this->remacc(selway,selset)     = (((pte & PTE_R_MASK) >> PTE_R_SHIFT) == 1) ? true : false;
+        this->cacheable(selway,selset)  = (((pte & PTE_C_MASK) >> PTE_C_SHIFT) == 1) ? true : false;
+        this->writable(selway,selset)   = (((pte & PTE_W_MASK) >> PTE_W_SHIFT) == 1) ? true : false;       
+        this->executable(selway,selset) = (((pte & PTE_X_MASK) >> PTE_X_SHIFT) == 1) ? true : false;
+        this->user(selway,selset)       = (((pte & PTE_U_MASK) >> PTE_U_SHIFT) == 1) ? true : false;
+	    if (((pte & PTE_G_MASK) >> PTE_G_SHIFT) == 1)
+		    this->setglobal(selway,selset);
+	    else
+		    this->clearglobal(selway,selset);
+		
+        this->dirty(selway,selset)      = (((pte & PTE_D_MASK) >> PTE_D_SHIFT) == 1) ? true : false; 
+        
+        nline(selway,selset) = line; 
+    } // end update()
+#if 0
+    //////////////////////////////////////////////////////////////////////////
+    //  This method writes a new 4K page size entry in the TLB for cc_vcache.
+    //////////////////////////////////////////////////////////////////////////
+    bool update1(data_t pte, data_t ppn2, vaddr_t vaddress, paddr_t line, paddr_t* victim ) 
+    {
+        size_t set = (vaddress >> PAGE_K_NBITS) & this->m_sets_mask;
+        size_t selway = this->getlru(set);
+        bool cleanup = this->valid(selway,set);
+
+        this->vpn(selway,set) = vaddress >> (PAGE_K_NBITS + this->m_sets_shift);
+        this->ppn(selway,set) = ppn2 & ((1<<(this->m_paddr_nbits - PAGE_K_NBITS))-1);  
+        this->setvalid(selway,set);
+        this->pagesize(selway,set)   = false;
+        this->setlru(selway,set);
+
+        this->locacc(selway,set)     = (((pte & PTE_L_MASK) >> PTE_L_SHIFT) == 1) ? true : false;
+        this->remacc(selway,set)     = (((pte & PTE_R_MASK) >> PTE_R_SHIFT) == 1) ? true : false;
+        this->cacheable(selway,set)  = (((pte & PTE_C_MASK) >> PTE_C_SHIFT) == 1) ? true : false;
+        this->writable(selway,set)   = (((pte & PTE_W_MASK) >> PTE_W_SHIFT) == 1) ? true : false;       
+        this->executable(selway,set) = (((pte & PTE_X_MASK) >> PTE_X_SHIFT) == 1) ? true : false;
+        this->user(selway,set)       = (((pte & PTE_U_MASK) >> PTE_U_SHIFT) == 1) ? true : false;
+	    if (((pte & PTE_G_MASK) >> PTE_G_SHIFT) == 1)
+		    this->setglobal(selway,set);
+	    else
+		    this->clearglobal(selway,set);
+        this->dirty(selway,set)      = (((pte & PTE_D_MASK) >> PTE_D_SHIFT) == 1) ? true : false; 
+        
+        *victim = nline(selway,set);
+        nline(selway,set) = line; 
+
+        return cleanup;
+    } // end update1()
+#endif
+    //////////////////////////////////////////////////////////////
+    //  This method verify whether all 16 words of a data cache line 
+    //  that are as PTE don't exist in TLB. If is true, a cleanup 
+    //  request is actived.
+    //////////////////////////////////////////////////////////////
+    bool cleanupcheck( paddr_t n_line ) 
+    {
+        for( size_t way = 0; way < this->m_nways; way++ ) 
+        {
+            for( size_t set = 0; set < this->m_nsets; set++ ) 
+            {
+                if ( (nline(way,set) == n_line) && this->valid(way,set) ) 
+                {
+                    return true;
+                }
+            } 
+        } 
+        return false;
+    } // end cccheck()
+
+    //////////////////////////////////////////////////////////////
+    //  This method invalidates a TLB entry
+    //  identified by the virtual page number.
+    //////////////////////////////////////////////////////////////
+    bool cccheck( paddr_t n_line, 
+                         size_t start_way, size_t start_set, 
+                         size_t* n_way, size_t* n_set,
+                         bool* end )
+    {
+        for ( size_t start = start_way*(this->m_nsets)+start_set; start < this->m_nways*this->m_nsets; start++ )
+        {
+            if (( nline((start/this->m_nsets),(start%this->m_nsets)) == n_line ) && this->valid((start/this->m_nsets),(start%this->m_nsets))) 
+            {
+                *n_way = start/this->m_nsets;
+                *n_set = start%this->m_nsets;
+                if ( ((start/this->m_nsets) == (this->m_nways-1)) && ((start%this->m_nsets) == (this->m_nsets-1)) )
+                {
+                    *end = true;
+                }
+                else
+                {
+                    *end = false;
+                }
+                return true;
+            }
+        }
+        *end = true;
+        return false;
+    } // end cccheck()
+}; // GenericCcTlb
+
+}}
+
+#endif /* SOCLIB_CABA_GENERIC_TLB_H */
+
+// Local Variables:
+// tab-width: 4
+// c-basic-offset: 4
+// c-file-offsets:((innamespace . 0)(inline-open . 0))
+// indent-tabs-mode: nil
+// End:
+
+// vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4
+
+
+
Index: branches/v4/platforms/almos-tsarv3-platforms/common/generic_tlb/metadata/generic_tlb.sd
===================================================================
--- branches/v4/platforms/almos-tsarv3-platforms/common/generic_tlb/metadata/generic_tlb.sd	(revision 371)
+++ branches/v4/platforms/almos-tsarv3-platforms/common/generic_tlb/metadata/generic_tlb.sd	(revision 371)
@@ -0,0 +1,13 @@
+
+# -*- python -*-
+
+__id__ = "$Id: generic_tlb.sd 917 2009-03-12 10:10:06Z nipo $"
+__version__ = "$Revision: 917 $"
+
+Module('caba:generic_tlb',
+	classname = 'soclib::GenericTlb',
+	header_files = ['../include/generic_tlb.h',],
+	   tmpl_parameters = [
+	parameter.Type('addr_t'),
+	],
+)
Index: branches/v4/platforms/almos-tsarv3-platforms/common/vci_cc_vcache_wrapper2_v1/caba/metadata/vci_cc_vcache_wrapper2_v1.sd
===================================================================
--- branches/v4/platforms/almos-tsarv3-platforms/common/vci_cc_vcache_wrapper2_v1/caba/metadata/vci_cc_vcache_wrapper2_v1.sd	(revision 371)
+++ branches/v4/platforms/almos-tsarv3-platforms/common/vci_cc_vcache_wrapper2_v1/caba/metadata/vci_cc_vcache_wrapper2_v1.sd	(revision 371)
@@ -0,0 +1,67 @@
+
+# -*- python -*-
+
+__id__ = "$Id: vci_cc_vcache_wrapper2_v1.sd 20 2010-04-14 03:27:59Z nipo $"
+__version__ = "$Revision: 20 $"
+
+Module('caba:vci_cc_vcache_wrapper2_v1',
+	classname = 'soclib::caba::VciCcVCacheWrapper2V1',
+	   tmpl_parameters = [
+	parameter.Module('vci_param', default = 'caba:vci_param'),
+	parameter.Module('iss_t'),
+	],
+	header_files = [
+	'../source/include/vci_cc_vcache_wrapper2_v1.h',
+	],
+	implementation_files = [
+	'../source/src/vci_cc_vcache_wrapper2_v1.cpp',
+	],
+	uses = [
+	Uses('caba:base_module'),
+	Uses('caba:write_buffer'),
+	Uses('caba:generic_tlb', addr_t = parameter.StringExt('sc_dt::sc_uint<%d> ', parameter.Reference('addr_size'))),
+	Uses('caba:generic_cache', addr_t = parameter.StringExt('sc_dt::sc_uint<%d> ', parameter.Reference('addr_size'))),
+	Uses('common:address_masking_table', data_t = parameter.StringExt('sc_dt::sc_uint<%d> ', parameter.Reference('addr_size'))),
+	Uses('common:iss2'),
+	Uses('common:mapping_table'),
+	],
+	ports = [
+	Port('caba:vci_initiator', 'p_vci_ini_rw'),
+	Port('caba:vci_initiator', 'p_vci_ini_c'),
+	Port('caba:vci_target', 'p_vci_tgt'),
+	Port('caba:bit_in','p_irq', parameter.Constant('n_irq')),
+	Port('caba:bit_in', 'p_resetn', auto = 'resetn'),
+	Port('caba:clock_in', 'p_clk', auto = 'clock'),
+	],
+	instance_parameters = [
+	parameter.Int('proc_id'),
+	parameter.Module('mt', 'common:mapping_table'),
+	parameter.Module('mc', 'common:mapping_table'),
+	parameter.IntTab('initiator_rw_index'),
+	parameter.IntTab('initiator_c_index'),
+	parameter.IntTab('target_index'),
+    	parameter.Int('itlb_ways'),
+    	parameter.Int('itlb_sets'),
+    	parameter.Int('dtlb_ways'),
+    	parameter.Int('dtlb_sets'),
+    	parameter.Int('icache_ways'),
+    	parameter.Int('icache_sets'),
+    	parameter.Int('icache_words'),
+    	parameter.Int('dcache_ways'),
+    	parameter.Int('dcache_sets'),
+    	parameter.Int('dcache_words'),
+    	parameter.Int('write_buf_size'),
+	],
+	   extensions = [
+	'dsx:get_ident='
+        'initiator_rw_index:p_vci_ini_rw:mt,'
+        'initiator_c_index:p_vci_ini_c:mc,'
+        'target_index:p_vci_tgt:mc',
+	'dsx:cpu=wrapper:iss_t',
+	'dsx:addressable=target_index',
+    'dsx:on_segment=mc:add_index:initiator_rw_index',
+	'dsx:mapping_type=processor:proc_id',
+   ],
+)
+
+
Index: branches/v4/platforms/almos-tsarv3-platforms/common/vci_cc_vcache_wrapper2_v1/caba/source/include/vci_cc_vcache_wrapper2_v1.h
===================================================================
--- branches/v4/platforms/almos-tsarv3-platforms/common/vci_cc_vcache_wrapper2_v1/caba/source/include/vci_cc_vcache_wrapper2_v1.h	(revision 371)
+++ branches/v4/platforms/almos-tsarv3-platforms/common/vci_cc_vcache_wrapper2_v1/caba/source/include/vci_cc_vcache_wrapper2_v1.h	(revision 371)
@@ -0,0 +1,618 @@
+/* -*- c++ -*-
+ * File : vci_cc_vcache_wrapper2_v1.h
+ * Copyright (c) UPMC, Lip6, SoC
+ * Authors : Alain GREINER, Yang GAO
+ *
+ * SOCLIB_LGPL_HEADER_BEGIN
+ * 
+ * This file is part of SoCLib, GNU LGPLv2.1.
+ * 
+ * SoCLib is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU Lesser General Public License as published
+ * by the Free Software Foundation; version 2.1 of the License.
+ * 
+ * SoCLib is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * Lesser General Public License for more details.
+ * 
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with SoCLib; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301 USA
+ * 
+ * SOCLIB_LGPL_HEADER_END
+ */
+ 
+#ifndef SOCLIB_CABA_VCI_CC_VCACHE_WRAPPER2_V1_H
+#define SOCLIB_CABA_VCI_CC_VCACHE_WRAPPER2_V1_H
+
+#include <inttypes.h>
+#include <iostream>
+#include <fstream>
+#include <systemc>
+#include "caba_base_module.h"
+#include "write_buffer.h"
+#include "generic_cache.h"
+#include "vci_initiator.h"
+#include "vci_target.h"
+#include "mapping_table.h"
+#include "generic_tlb.h"
+#include "static_assert.h"
+
+namespace soclib {
+namespace caba {
+
+using namespace sc_core;
+
+////////////////////////////////////////////
+template<typename vci_param, typename iss_t>
+class VciCcVCacheWrapper2V1
+////////////////////////////////////////////
+    : public soclib::caba::BaseModule
+{
+    typedef uint32_t vaddr_t;
+    typedef uint32_t data_t;
+    typedef uint32_t tag_t;
+    typedef uint32_t type_t;
+    typedef typename iss_t::DataOperationType data_op_t;
+
+    typedef typename vci_param::addr_t  paddr_t;
+    typedef typename vci_param::be_t    vci_be_t;
+	typedef typename vci_param::srcid_t vci_srcid_t;
+	typedef typename vci_param::trdid_t vci_trdid_t;
+	typedef typename vci_param::pktid_t vci_pktid_t;
+	typedef typename vci_param::plen_t  vci_plen_t;
+
+    enum icache_fsm_state_e {  
+        ICACHE_IDLE,                // 00
+        ICACHE_BIS,                 // 01
+        ICACHE_TLB1_READ,           // 02
+        ICACHE_TLB1_WRITE,          // 03
+        ICACHE_TLB1_UPDT_SEL,       // 04
+        ICACHE_TLB1_UPDT,           // 05
+        ICACHE_TLB2_READ,           // 06
+        ICACHE_TLB2_WRITE,          // 07
+        ICACHE_TLB2_UPDT_SEL,       // 08
+        ICACHE_TLB2_UPDT,           // 09
+        ICACHE_SW_FLUSH,            // 0a
+        ICACHE_TLB_FLUSH,           // 0b
+        ICACHE_CACHE_FLUSH,         // 0c
+        ICACHE_TLB_INVAL,           // 0d
+        ICACHE_CACHE_INVAL,         // 0e
+        ICACHE_CACHE_INVAL_PA,      // 0f
+        ICACHE_MISS_WAIT,           // 10
+        ICACHE_UNC_WAIT,            // 11
+        ICACHE_MISS_UPDT,           // 12
+        ICACHE_ERROR,               // 13
+        ICACHE_CC_INVAL,            // 14
+        ICACHE_TLB_CC_INVAL,        // 15
+    };
+
+    enum dcache_fsm_state_e {  
+        DCACHE_IDLE,                // 00
+        DCACHE_BIS,                 // 01
+        DCACHE_DTLB1_READ_CACHE,    // 02
+        DCACHE_TLB1_LL_WAIT,        // 03
+        DCACHE_TLB1_SC_WAIT,        // 04
+        DCACHE_TLB1_READ,           // 05
+        DCACHE_TLB1_READ_UPDT,      // 06
+        DCACHE_TLB1_UPDT_SEL,       // 07
+        DCACHE_TLB1_UPDT,           // 08
+        DCACHE_DTLB2_READ_CACHE,    // 09
+        DCACHE_TLB2_LL_WAIT,        // 0a
+        DCACHE_TLB2_SC_WAIT,        // 0b
+        DCACHE_TLB2_READ,           // 0c
+        DCACHE_TLB2_READ_UPDT,      // 0d
+        DCACHE_TLB2_UPDT_SEL,       // 0e
+        DCACHE_TLB2_UPDT,           // 0f
+        DCACHE_CTXT_SWITCH,         // 10
+        DCACHE_ICACHE_FLUSH,        // 11
+        DCACHE_DCACHE_FLUSH,        // 12
+        DCACHE_ITLB_INVAL,          // 13
+        DCACHE_DTLB_INVAL,          // 14
+        DCACHE_ICACHE_INVAL,        // 15
+        DCACHE_DCACHE_INVAL,        // 16
+	    DCACHE_ICACHE_INVAL_PA,     // 17
+	    DCACHE_DCACHE_INVAL_PA,     // 18
+        DCACHE_DCACHE_SYNC,         // 19
+        DCACHE_LL_DIRTY_WAIT,       // 1a
+        DCACHE_SC_DIRTY_WAIT,       // 1b
+        DCACHE_WRITE_UPDT,          // 1c
+        DCACHE_WRITE_DIRTY,         // 1d
+        DCACHE_WRITE_REQ,           // 1e
+        DCACHE_MISS_WAIT,           // 1f
+        DCACHE_MISS_UPDT,           // 20
+        DCACHE_UNC_WAIT,            // 21
+        DCACHE_ERROR,               // 22
+        DCACHE_ITLB_READ,           // 23
+        DCACHE_ITLB_UPDT,           // 24
+        DCACHE_ITLB_LL_WAIT,        // 25
+        DCACHE_ITLB_SC_WAIT,        // 26
+        DCACHE_CC_CHECK,            // 27
+        DCACHE_CC_INVAL,            // 28
+        DCACHE_CC_UPDT,             // 29
+        DCACHE_CC_NOP,              // 2a
+        DCACHE_TLB_CC_INVAL,        // 2b
+        DCACHE_ITLB_CLEANUP,        // 2c
+    };
+
+    enum cmd_fsm_state_e {      
+        CMD_IDLE,                   // 00
+        CMD_ITLB_READ,              // 01
+        CMD_ITLB_ACC_LL,            // 02
+        CMD_ITLB_ACC_SC,            // 03
+        CMD_INS_MISS,               // 04
+        CMD_INS_UNC,                // 05
+        CMD_DTLB_READ,              // 06
+        CMD_DTLB_ACC_LL,            // 07
+        CMD_DTLB_ACC_SC,            // 08
+        CMD_DTLB_DIRTY_LL,          // 09
+        CMD_DTLB_DIRTY_SC,          // 0a
+        CMD_DATA_UNC,               // 0b
+        CMD_DATA_MISS,              // 0c
+        CMD_DATA_WRITE,             // 0d
+    };
+
+    enum rsp_fsm_state_e {       
+        RSP_IDLE,                   // 00
+        RSP_ITLB_READ,              // 01
+        RSP_ITLB_ACC_LL,            // 02
+        RSP_ITLB_ACC_SC,            // 03
+        RSP_INS_MISS,               // 04
+        RSP_INS_UNC,                // 05
+        RSP_DTLB_READ,              // 06
+        RSP_DTLB_ACC_LL,            // 07
+        RSP_DTLB_ACC_SC,            // 08
+        RSP_DTLB_DIRTY_LL,          // 09
+        RSP_DTLB_DIRTY_SC,          // 0a
+        RSP_DATA_MISS,              // 0b
+        RSP_DATA_UNC,               // 0c
+        RSP_DATA_WRITE,             // 0d
+    };
+    enum cleanup_cmd_fsm_state_e {
+        CLEANUP_CMD_IDLE,               // 00
+        CLEANUP_CMD_DATA,               // 01
+        CLEANUP_CMD_INS,                // 02
+    };
+
+    enum cleanup_rsp_fsm_state_e {
+        CLEANUP_RSP_IDLE,               // 00
+        CLEANUP_RSP_DATA,               // 01
+        CLEANUP_RSP_INS,                // 02
+    };
+
+    enum tgt_fsm_state_e {  
+        TGT_IDLE,                   // 00
+        TGT_UPDT_WORD,              // 01
+        TGT_UPDT_DATA,              // 02
+        TGT_REQ_BROADCAST,          // 03
+        TGT_REQ_ICACHE,             // 04
+        TGT_REQ_DCACHE,             // 05
+        TGT_RSP_BROADCAST,          // 06
+        TGT_RSP_ICACHE,             // 07
+        TGT_RSP_DCACHE,             // 08
+    };
+
+    enum inval_itlb_fsm_state_e {
+        INVAL_ITLB_IDLE,            // 00
+        INVAL_ITLB_CHECK,           // 01
+        INVAL_ITLB_INVAL,           // 02
+        INVAL_ITLB_CLEAR,           // 03
+    };
+
+    enum inval_dtlb_fsm_state_e {
+        INVAL_DTLB_IDLE,            // 00
+        INVAL_DTLB_CHECK,           // 01
+        INVAL_DTLB_INVAL,           // 02
+        INVAL_DTLB_CLEAR,           // 03
+    };
+
+    // TLB Mode ITLB / DTLB / ICACHE / DCACHE
+    enum {          
+        ALL_DEACTIVE = 0x0000,   // TLBs disactive caches disactive
+        INS_TLB_MASK    = 0x8,
+        DATA_TLB_MASK   = 0x4,
+        INS_CACHE_MASK  = 0x2,
+        DATA_CACHE_MASK = 0x1,
+    };
+
+    // Error Type
+    enum mmu_error_type_e {
+        MMU_NONE                      = 0x0000, // None
+        MMU_WRITE_PT1_UNMAPPED 	      = 0x0001, // Write access of Page fault on Page Table 1          (non fatal error)
+        MMU_WRITE_PT2_UNMAPPED 	      = 0x0002, // Write access of Page fault on Page Table 2          (non fatal error)
+        MMU_WRITE_PRIVILEGE_VIOLATION = 0x0004, // Write access of Protected access in user mode       (user error)
+        MMU_WRITE_ACCES_VIOLATION 	  = 0x0008, // Write access of write access to a non writable page (user error)
+        MMU_WRITE_UNDEFINED_XTN 	  = 0x0020, // Write access of undefined external access address   (user error)
+        MMU_WRITE_PT1_ILLEGAL_ACCESS  = 0x0040, // Write access of Bus Error accessing Table 1         (kernel error)
+        MMU_WRITE_PT2_ILLEGAL_ACCESS  = 0x0080, // Write access of Bus Error accessing Table 2         (kernel error)
+        MMU_WRITE_DATA_ILLEGAL_ACCESS = 0x0100, // Write access of Bus Error in cache access           (kernel error)
+        MMU_READ_PT1_UNMAPPED 	      = 0x1001, // Read access of Page fault on Page Table 1  	       (non fatal error)
+        MMU_READ_PT2_UNMAPPED 	      = 0x1002, // Read access of Page fault on Page Table 2  	       (non fatal error)
+        MMU_READ_PRIVILEGE_VIOLATION  = 0x1004, // Read access of Protected access in user mode 	   (user error)
+        MMU_READ_EXEC_VIOLATION 	  = 0x1010, // Exec access to a non exec page                      (user error)
+        MMU_READ_UNDEFINED_XTN 	      = 0x1020, // Read access of Undefined external access address    (user error)
+        MMU_READ_PT1_ILLEGAL_ACCESS   = 0x1040, // Read access of Bus Error in Table1 access           (kernel error)
+        MMU_READ_PT2_ILLEGAL_ACCESS   = 0x1080, // Read access of Bus Error in Table2 access 	       (kernel error)
+        MMU_READ_DATA_ILLEGAL_ACCESS  = 0x1100, // Read access of Bus Error in cache access 	       (kernel error)
+    };
+
+public:
+    sc_in<bool>                             p_clk;
+    sc_in<bool>                             p_resetn;
+    sc_in<bool>                             p_irq[iss_t::n_irq];
+    soclib::caba::VciInitiator<vci_param>   p_vci_ini_rw;
+    soclib::caba::VciInitiator<vci_param>   p_vci_ini_c;
+    soclib::caba::VciTarget<vci_param>      p_vci_tgt;
+
+private:
+    // STRUCTURAL PARAMETERS
+    soclib::common::AddressDecodingTable<uint32_t, bool>    m_cacheability_table;
+    const soclib::common::Segment                           m_segment;
+    iss_t                                                   m_iss;   
+    const vci_srcid_t                                       m_srcid_rw;
+    const vci_srcid_t                                       m_srcid_c;
+
+    const size_t  m_itlb_ways;
+    const size_t  m_itlb_sets;
+
+    const size_t  m_dtlb_ways;
+    const size_t  m_dtlb_sets;
+
+    const size_t  m_icache_ways;
+    const size_t  m_icache_sets;
+    const size_t  m_icache_yzmask;
+    const size_t  m_icache_words;
+
+    const size_t  m_dcache_ways;
+    const size_t  m_dcache_sets;
+    const size_t  m_dcache_yzmask;
+    const size_t  m_dcache_words;
+
+    const size_t  m_write_buf_size;  
+    const size_t  m_paddr_nbits;  
+
+    // instruction and data vcache tlb instances 
+    soclib::caba::GenericCcTlb<paddr_t>    icache_tlb;
+    soclib::caba::GenericCcTlb<paddr_t>    dcache_tlb;
+
+    sc_signal<vaddr_t>      r_mmu_ptpr;             // page table pointer register
+    sc_signal<int>          r_mmu_mode;             // tlb mode register
+    sc_signal<int>          r_mmu_params;           // mmu parameters register
+    sc_signal<int>          r_mmu_release;          // mmu release register
+    sc_signal<int>          r_mmu_word_lo;          // mmu misc data low
+    sc_signal<int>          r_mmu_word_hi;          // mmu mmu misc data hight
+
+    // DCACHE FSM REGISTERS
+    sc_signal<int>          r_dcache_fsm;               // state register
+    sc_signal<paddr_t>      r_dcache_paddr_save;        // physical address
+    sc_signal<data_t>       r_dcache_wdata_save;        // write data
+    sc_signal<data_t>       r_dcache_rdata_save;        // read data
+    sc_signal<type_t>       r_dcache_type_save;         // access type
+    sc_signal<vci_be_t>     r_dcache_be_save;           // byte enable
+    sc_signal<bool>         r_dcache_cached_save;       // used by the write buffer
+    sc_signal<paddr_t>      r_dcache_tlb_paddr;         // physical address of tlb miss
+    sc_signal<bool>         r_dcache_dirty_save;        // used for TLB dirty bit update
+    sc_signal<size_t>       r_dcache_tlb_set_save;      // used for TLB dirty bit update
+    sc_signal<size_t>       r_dcache_tlb_way_save;      // used for TLB dirty bit update
+    sc_signal<vaddr_t>      r_dcache_id1_save;          // used by the PT1 bypass
+    sc_signal<paddr_t>      r_dcache_ptba_save;         // used by the PT1 bypass
+    sc_signal<bool>         r_dcache_ptba_ok;           // used by the PT1 bypass
+    sc_signal<data_t>       r_dcache_pte_update;        // used for page table update
+    sc_signal<data_t>       r_dcache_ppn_update;        // used for physical page number update 
+    sc_signal<tag_t>        r_dcache_ppn_save;          // used for speculative cache access
+    sc_signal<tag_t>        r_dcache_vpn_save;          // used for speculative cache access
+    sc_signal<bool>         r_dtlb_translation_valid;   // used for speculative address
+    sc_signal<bool>         r_dcache_buf_unc_valid;     // used for uncached read
+    sc_signal<bool>         r_dcache_hit_p_save;        // used to save hit_p in case BIS
+
+    sc_signal<data_t>       r_dcache_error_type;        // software visible register
+    sc_signal<vaddr_t>      r_dcache_bad_vaddr;         // software visible register 
+
+    sc_signal<bool>         r_dcache_miss_req;          // used for cached read miss
+    sc_signal<bool>         r_dcache_unc_req;           // used for uncached read miss
+    sc_signal<bool>         r_dcache_write_req;         // used for write 
+    sc_signal<bool>         r_dcache_tlb_read_req;      // used for tlb ptba or pte read
+
+    sc_signal<bool>         r_dcache_llsc_reserved;     // used for check address reserved
+    sc_signal<paddr_t>      r_dcache_llsc_addr_save;    // used for save llsc address
+ 
+    sc_signal<bool>         r_dcache_tlb_ll_acc_req;    // used for tlb access bit update
+    sc_signal<bool>         r_dcache_tlb_sc_acc_req;    // used for tlb access bit update
+    sc_signal<bool>         r_dcache_tlb_ll_dirty_req;  // used for tlb dirty bit update 
+    sc_signal<bool>         r_dcache_tlb_sc_dirty_req;  // used for tlb dirty bit update 
+    sc_signal<bool>         r_dcache_sc_updt_dirty;     // used for tlb dirty bit update 
+    sc_signal<bool>         r_dcache_tlb_ptba_read;     // used for tlb ptba read when write dirty bit 
+    sc_signal<bool>         r_dcache_xtn_req;           // used for xtn write for ICACHE
+
+    bool                    *r_dcache_in_itlb;          // indicates some words of dcache line in ins TLB 
+    bool                    *r_dcache_in_dtlb;          // indicates some words of dcache line in data TLB 
+    sc_signal<bool>         r_dreq_isUser_save;         // For instrumentation: is User access ? 
+
+    // coherence registers
+    sc_signal<int>          r_dcache_fsm_save;          // state save register
+    sc_signal<size_t>       r_dcache_way;
+    sc_signal<size_t>       r_dcache_set;
+    sc_signal<bool>         r_dcache_cleanup_req;       // data cleanup request
+    sc_signal<paddr_t>      r_dcache_cleanup_line;      // data cleanup NLINE
+    sc_signal<bool>         r_dcache_inval_rsp;         // data cache invalidate
+
+    // ICACHE FSM REGISTERS
+    sc_signal<int>          r_icache_fsm;               // state register
+    sc_signal<paddr_t>      r_icache_paddr_save;        // physical address
+    sc_signal<vaddr_t>      r_icache_id1_save;          // used by the PT1 bypass
+    sc_signal<paddr_t>      r_icache_ptba_save;         // used by the PT1 bypass
+    sc_signal<bool>         r_icache_ptba_ok;           // used by the PT1 bypass
+    sc_signal<data_t>       r_icache_pte_update;        // used for page table update
+    sc_signal<tag_t>        r_icache_ppn_save;          // used for speculative cache access
+    sc_signal<tag_t>        r_icache_vpn_save;          // used for speculative cache access
+    sc_signal<bool>         r_itlb_translation_valid;   // used for speculative physical address
+    sc_signal<bool>         r_icache_buf_unc_valid;     // used for uncached read
+    sc_signal<data_t>       r_icache_error_type;        // software visible registers
+    sc_signal<vaddr_t>      r_icache_bad_vaddr;         // software visible registers
+
+    sc_signal<bool>         r_icache_miss_req;          // used for cached read miss
+    sc_signal<bool>         r_icache_unc_req;           // used for uncached read miss
+    sc_signal<bool>         r_dcache_itlb_read_req;     // used for tlb ptba or pte read 
+
+    sc_signal<bool>         r_dcache_itlb_ll_acc_req;   // used for tlb access bit update
+    sc_signal<bool>         r_dcache_itlb_sc_acc_req;   // used for tlb access bit update
+
+    sc_signal<bool>	        r_itlb_read_dcache_req;     // used for instruction tlb miss, request in data cache
+    sc_signal<bool>	        r_itlb_k_read_dcache;       // used for instruction tlb miss, request in data cache
+    sc_signal<bool>	        r_itlb_acc_dcache_req;      // used for itlb update access bit via dcache
+    sc_signal<bool>	        r_itlb_acc_redo_req;        // used for itlb update access bit via dcache
+    sc_signal<bool>	        r_dcache_rsp_itlb_error;    // used for data cache rsp error when itlb miss
+    sc_signal<data_t>	    r_dcache_rsp_itlb_miss;	    // used for dcache rsp data when itlb miss
+    sc_signal<data_t>	    r_dcache_rsp_itlb_ppn;	    // used for dcache rsp ppn when itlb miss
+    sc_signal<vaddr_t>      r_icache_vaddr_req;			// virtual address requested by the CPU
+    sc_signal<bool>         r_ireq_isUser_save;         // For instrumentation: is User access ? 
+
+    // coherence registers
+    sc_signal<int>          r_icache_fsm_save;          // state save register
+    sc_signal<size_t>       r_icache_way;
+    sc_signal<size_t>       r_icache_set;
+    sc_signal<bool>         r_icache_cleanup_req;       // ins cleanup request
+    sc_signal<paddr_t>      r_icache_cleanup_line;      // ins cleanup NLINE
+    sc_signal<bool>         r_icache_inval_rsp;         // ins cache invalidate
+
+    // VCI_CMD FSM REGISTERS
+    sc_signal<int>          r_vci_cmd_fsm;
+    sc_signal<size_t>       r_vci_cmd_min;       
+    sc_signal<size_t>       r_vci_cmd_max;       
+    sc_signal<size_t>       r_vci_cmd_cpt;     
+
+    // VCI_RSP FSM REGISTERS
+    sc_signal<int>          r_vci_rsp_fsm;
+    sc_signal<size_t>       r_vci_rsp_cpt;
+    sc_signal<bool>         r_vci_rsp_ins_error;
+    sc_signal<bool>         r_vci_rsp_data_error;
+    sc_signal<bool>         r_dcache_tlb_sc_fail;
+
+    data_t                  *r_icache_miss_buf;    
+    data_t                  *r_dcache_miss_buf;  
+
+    sc_signal<int>          r_cleanup_cmd_fsm;
+    sc_signal<int>          r_cleanup_rsp_fsm;
+
+    // VCI_TGT FSM REGISTERS
+    data_t                  *r_tgt_buf;
+    bool                    *r_tgt_val;
+
+    sc_signal<int>          r_vci_tgt_fsm;
+    sc_signal<paddr_t>      r_tgt_addr;
+    sc_signal<size_t>       r_tgt_word;
+    sc_signal<bool>         r_tgt_update;
+    sc_signal<vci_srcid_t>  r_tgt_srcid;
+    sc_signal<vci_pktid_t>  r_tgt_pktid;
+    sc_signal<vci_trdid_t>  r_tgt_trdid;
+    sc_signal<vci_plen_t>   r_tgt_plen;
+    sc_signal<bool>         r_tgt_req;
+    sc_signal<bool>         r_tgt_icache_req;
+    sc_signal<bool>         r_tgt_dcache_req;
+    sc_signal<bool>         r_tgt_icache_rsp;
+    sc_signal<bool>         r_tgt_dcache_rsp;
+
+    // INVAL CHECK FSM
+    sc_signal<int>          r_inval_itlb_fsm;          
+    sc_signal<bool>         r_dcache_itlb_inval_req;
+    sc_signal<paddr_t>      r_dcache_itlb_inval_line;
+    sc_signal<bool>         r_itlb_cc_check_end;
+    sc_signal<size_t>       r_ccinval_itlb_way; 
+    sc_signal<size_t>       r_ccinval_itlb_set; 
+    sc_signal<bool>         r_icache_inval_tlb_rsp;
+    sc_signal<paddr_t>      r_icache_tlb_nline;
+
+    sc_signal<int>          r_inval_dtlb_fsm;          
+    sc_signal<bool>         r_dcache_dtlb_inval_req;
+    sc_signal<paddr_t>      r_dcache_dtlb_inval_line;
+    sc_signal<bool>         r_dtlb_cc_check_end;
+    sc_signal<size_t>       r_ccinval_dtlb_way; 
+    sc_signal<size_t>       r_ccinval_dtlb_set; 
+    sc_signal<bool>         r_dcache_inval_tlb_rsp;
+    sc_signal<paddr_t>      r_dcache_tlb_nline;
+
+    sc_signal<bool>         r_dcache_itlb_cleanup_req;
+    sc_signal<paddr_t>      r_dcache_itlb_cleanup_line;
+
+    sc_signal<bool>         r_dcache_dtlb_cleanup_req;
+    sc_signal<paddr_t>      r_dcache_dtlb_cleanup_line;
+
+    sc_signal<bool>         r_itlb_inval_req;
+    sc_signal<bool>         r_dcache_cc_check;
+
+    WriteBuffer<paddr_t>     r_wbuf;
+    GenericCache<paddr_t>    r_icache;
+    GenericCache<paddr_t>    r_dcache;
+
+    uint32_t m_proc_id;
+
+    // Activity counters
+    uint32_t m_cpt_dcache_data_read;        // DCACHE DATA READ
+    uint32_t m_cpt_dcache_data_write;       // DCACHE DATA WRITE
+    uint32_t m_cpt_dcache_dir_read;         // DCACHE DIR READ
+    uint32_t m_cpt_dcache_dir_write;        // DCACHE DIR WRITE
+
+    uint32_t m_cpt_icache_data_read;        // ICACHE DATA READ
+    uint32_t m_cpt_icache_data_write;       // ICACHE DATA WRITE
+    uint32_t m_cpt_icache_dir_read;         // ICACHE DIR READ
+    uint32_t m_cpt_icache_dir_write;        // ICACHE DIR WRITE
+
+    uint32_t m_cpt_frz_cycles;	            // number of cycles where the cpu is frozen
+    uint32_t m_cpt_total_cycles;	        // total number of cycles
+    uint32_t m_cpt_dcache_frz_cycles;       // number of cycles where the data cache is frozen    
+
+    // Cache activity counters
+    uint32_t m_cpt_read;                    // total number of read data
+    uint32_t m_cpt_write;                   // total number of write data
+    uint32_t m_cpt_data_miss;               // number of read miss
+    uint32_t m_cpt_ins_miss;                // number of instruction miss
+    uint32_t m_cpt_unc_read;                // number of read uncached
+    uint32_t m_cpt_write_cached;            // number of cached write
+    uint32_t m_cpt_ins_read;                // number of instruction read
+
+    uint32_t m_cost_write_frz;              // number of frozen cycles related to write buffer         
+    uint32_t m_cost_data_miss_frz;          // number of frozen cycles related to data miss
+    uint32_t m_cost_unc_read_frz;           // number of frozen cycles related to uncached read
+    uint32_t m_cost_ins_miss_frz;           // number of frozen cycles related to ins miss
+
+    uint32_t m_cpt_imiss_transaction;       // number of VCI instruction miss transactions
+    uint32_t m_cpt_dmiss_transaction;       // number of VCI data miss transactions
+    uint32_t m_cpt_unc_transaction;         // number of VCI uncached read transactions
+    uint32_t m_cpt_write_transaction;       // number of VCI write transactions
+    uint32_t m_cpt_icache_unc_transaction;
+
+    uint32_t m_cost_imiss_transaction;      // cumulated duration for VCI IMISS transactions
+    uint32_t m_cost_dmiss_transaction;      // cumulated duration for VCI DMISS transactions
+    uint32_t m_cost_unc_transaction;        // cumulated duration for VCI UNC transactions
+    uint32_t m_cost_write_transaction;      // cumulated duration for VCI WRITE transactions
+    uint32_t m_cost_icache_unc_transaction; // cumulated duration for VCI IUNC transactions    
+    uint32_t m_length_write_transaction;    // cumulated length for VCI WRITE transactions
+
+    // TLB activity counters
+    uint32_t m_cpt_ins_tlb_read;            // number of instruction tlb read
+    uint32_t m_cpt_ins_tlb_miss;            // number of instruction tlb miss
+    uint32_t m_cpt_ins_tlb_update_acc;      // number of instruction tlb update acc
+    uint32_t m_cpt_data_tlb_read;           // number of data tlb read
+    uint32_t m_cpt_data_tlb_miss;           // number of data tlb miss
+    uint32_t m_cpt_data_tlb_update_acc;     // number of data tlb update acc
+    uint32_t m_cpt_data_tlb_update_dirty;   // number of data tlb update dirty
+    uint32_t m_cpt_ins_tlb_hit_dcache;      // number of instruction tlb hit in data cache
+    uint32_t m_cpt_data_tlb_hit_dcache;     // number of data tlb hit in data cache
+    uint32_t m_cpt_ins_tlb_occup_cache;     // number of instruction tlb occupy data cache line 
+    uint32_t m_cpt_data_tlb_occup_cache;    // number of data tlb occupy data cache line
+    uint32_t m_cpt_tlb_occup_dcache;
+    
+    uint32_t m_cost_ins_tlb_miss_frz;       // number of frozen cycles related to instruction tlb miss
+    uint32_t m_cost_data_tlb_miss_frz;      // number of frozen cycles related to data tlb miss
+    uint32_t m_cost_ins_tlb_update_acc_frz;    // number of frozen cycles related to instruction tlb update acc
+    uint32_t m_cost_data_tlb_update_acc_frz;   // number of frozen cycles related to data tlb update acc
+    uint32_t m_cost_data_tlb_update_dirty_frz; // number of frozen cycles related to data tlb update dirty
+    uint32_t m_cost_ins_tlb_occup_cache_frz;   // number of frozen cycles related to instruction tlb miss operate in dcache
+    uint32_t m_cost_data_tlb_occup_cache_frz;  // number of frozen cycles related to data tlb miss operate in dcache
+
+    uint32_t m_cpt_itlbmiss_transaction;       // number of itlb miss transactions
+    uint32_t m_cpt_itlb_ll_transaction;        // number of itlb ll acc transactions
+    uint32_t m_cpt_itlb_sc_transaction;        // number of itlb sc acc transactions
+    uint32_t m_cpt_dtlbmiss_transaction;       // number of dtlb miss transactions
+    uint32_t m_cpt_dtlb_ll_transaction;        // number of dtlb ll acc transactions
+    uint32_t m_cpt_dtlb_sc_transaction;        // number of dtlb sc acc transactions
+    uint32_t m_cpt_dtlb_ll_dirty_transaction;  // number of dtlb ll dirty transactions
+    uint32_t m_cpt_dtlb_sc_dirty_transaction;  // number of dtlb sc dirty transactions
+
+    uint32_t m_cost_itlbmiss_transaction;     // cumulated duration for VCI instruction TLB miss transactions
+    uint32_t m_cost_itlb_ll_transaction;      // cumulated duration for VCI instruction TLB ll acc transactions
+    uint32_t m_cost_itlb_sc_transaction;      // cumulated duration for VCI instruction TLB sc acc transactions
+    uint32_t m_cost_dtlbmiss_transaction;     // cumulated duration for VCI data TLB miss transactions
+    uint32_t m_cost_dtlb_ll_transaction;      // cumulated duration for VCI data TLB ll acc transactions
+    uint32_t m_cost_dtlb_sc_transaction;      // cumulated duration for VCI data TLB sc acc transactions
+    uint32_t m_cost_dtlb_ll_dirty_transaction;// cumulated duration for VCI data TLB ll dirty transactions
+    uint32_t m_cost_dtlb_sc_dirty_transaction;// cumulated duration for VCI data TLB sc dirty transactions
+
+    uint32_t m_cpt_cc_update_data;              // number of coherence update data packets 
+    uint32_t m_cpt_cc_inval_ins;                // number of coherence inval instruction packets
+    uint32_t m_cpt_cc_inval_data;               // number of coherence inval data packets
+    uint32_t m_cpt_cc_broadcast;                // number of coherence broadcast packets
+    
+    uint32_t m_cost_updt_data_frz;              // number of frozen cycles related to coherence update data packets
+    uint32_t m_cost_inval_ins_frz;              // number of frozen cycles related to coherence inval instruction packets
+    uint32_t m_cost_inval_data_frz;             // number of frozen cycles related to coherence inval data packets
+    uint32_t m_cost_broadcast_frz;              // number of frozen cycles related to coherence broadcast packets
+
+    uint32_t m_cpt_cc_cleanup_ins;              // number of coherence cleanup packets
+    uint32_t m_cpt_cc_cleanup_data;             // number of coherence cleanup packets
+
+    uint32_t m_cpt_icleanup_transaction;        // number of instruction cleanup transactions
+    uint32_t m_cpt_dcleanup_transaction;        // number of instructinumber of data cleanup transactions
+    uint32_t m_cost_icleanup_transaction;       // cumulated duration for VCI instruction cleanup transactions
+    uint32_t m_cost_dcleanup_transaction;       // cumulated duration for VCI data cleanup transactions
+
+    uint32_t m_cost_ins_tlb_inval_frz;      // number of frozen cycles related to checking ins tlb invalidate
+    uint32_t m_cpt_ins_tlb_inval;           // number of ins tlb invalidate
+
+    uint32_t m_cost_data_tlb_inval_frz;     // number of frozen cycles related to checking data tlb invalidate    
+    uint32_t m_cpt_data_tlb_inval;          // number of data tlb invalidate
+    
+    size_t m_tm_start;
+    size_t m_tm_end;
+    size_t m_period;
+
+public:
+    std::ofstream m_log;    
+    
+protected:
+    SC_HAS_PROCESS(VciCcVCacheWrapper2V1);
+
+public:
+    VciCcVCacheWrapper2V1(
+        sc_module_name insname,
+        int proc_id,
+        const soclib::common::MappingTable &mtp,
+        const soclib::common::MappingTable &mtc,
+        const soclib::common::IntTab &initiator_index_rw,
+        const soclib::common::IntTab &initiator_index_c,
+        const soclib::common::IntTab &target_index,
+        size_t itlb_ways,
+        size_t itlb_sets,
+        size_t dtlb_ways,
+        size_t dtlb_sets,
+        size_t icache_ways,
+        size_t icache_sets,
+        size_t icache_words,
+        size_t dcache_ways,
+        size_t dcache_sets,
+        size_t dcache_words,
+        size_t write_buf_size );
+
+    ~VciCcVCacheWrapper2V1();
+
+    void print_cpi();
+    void print_stats();
+    void clear_stats();
+    void print_trace(size_t mode = 0);
+
+private:
+    void transition();
+    void genMoore();
+
+    soclib_static_assert((int)iss_t::SC_ATOMIC == (int)vci_param::STORE_COND_ATOMIC);
+    soclib_static_assert((int)iss_t::SC_NOT_ATOMIC == (int)vci_param::STORE_COND_NOT_ATOMIC);
+};
+
+}}
+
+#endif /* SOCLIB_CABA_VCI_CC_VCACHE_WRAPPER2_V1_H */
+
+// Local Variables:
+// tab-width: 4
+// c-basic-offset: 4
+// c-file-offsets:((innamespace . 0)(inline-open . 0))
+// indent-tabs-mode: nil
+// End:
+
+// vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4
+
+
+
+
Index: branches/v4/platforms/almos-tsarv3-platforms/common/vci_cc_vcache_wrapper2_v1/caba/source/src/vci_cc_vcache_wrapper2_v1.cpp
===================================================================
--- branches/v4/platforms/almos-tsarv3-platforms/common/vci_cc_vcache_wrapper2_v1/caba/source/src/vci_cc_vcache_wrapper2_v1.cpp	(revision 371)
+++ branches/v4/platforms/almos-tsarv3-platforms/common/vci_cc_vcache_wrapper2_v1/caba/source/src/vci_cc_vcache_wrapper2_v1.cpp	(revision 371)
@@ -0,0 +1,6470 @@
+/* -*- c++ -*-
+ * File : vci_cc_vcache_wrapper2_v1.cpp
+ * Copyright (c) UPMC, Lip6, SoC
+ * Authors : Alain GREINER, Yang GAO
+ *
+ * SOCLIB_LGPL_HEADER_BEGIN
+ * 
+ * This file is part of SoCLib, GNU LGPLv2.1.
+ * 
+ * SoCLib is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU Lesser General Public License as published
+ * by the Free Software Foundation; version 2.1 of the License.
+ * 
+ * SoCLib is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * Lesser General Public License for more details.
+ * 
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with SoCLib; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301 USA
+ * 
+ * SOCLIB_LGPL_HEADER_END
+ */
+
+#include <cassert>
+#include "arithmetics.h"
+#include "../include/vci_cc_vcache_wrapper2_v1.h"
+
+namespace soclib { 
+namespace caba {
+
+//#define SOCLIB_MODULE_DEBUG
+//#define EVALUATION_CACHE
+
+//#ifdef SOCLIB_MODULE_DEBUG
+namespace {
+const char *icache_fsm_state_str[] = {
+        "ICACHE_IDLE",
+        "ICACHE_BIS",       
+        "ICACHE_TLB1_READ",  
+        "ICACHE_TLB1_WRITE",
+        "ICACHE_TLB1_UPDT_SEL",  
+        "ICACHE_TLB1_UPDT",  
+        "ICACHE_TLB2_READ",  
+        "ICACHE_TLB2_WRITE",
+        "ICACHE_TLB2_UPDT_SEL",  
+        "ICACHE_TLB2_UPDT",  
+        "ICACHE_SW_FLUSH", 
+        "ICACHE_TLB_FLUSH", 
+        "ICACHE_CACHE_FLUSH", 
+        "ICACHE_TLB_INVAL",  
+        "ICACHE_CACHE_INVAL",
+        "ICACHE_CACHE_INVAL_PA",
+        "ICACHE_MISS_WAIT",
+        "ICACHE_UNC_WAIT",  
+        "ICACHE_MISS_UPDT",  
+        "ICACHE_ERROR", 
+        "ICACHE_CC_INVAL", 
+        "ICACHE_TLB_CC_INVAL",        
+    };
+const char *dcache_fsm_state_str[] = {
+        "DCACHE_IDLE",       
+        "DCACHE_BIS",   
+        "DCACHE_DTLB1_READ_CACHE",
+        "DCACHE_TLB1_LL_WAIT",
+        "DCACHE_TLB1_SC_WAIT",    
+        "DCACHE_TLB1_READ",
+        "DCACHE_TLB1_READ_UPDT",
+        "DCACHE_TLB1_UPDT_SEL",  
+        "DCACHE_TLB1_UPDT", 
+        "DCACHE_DTLB2_READ_CACHE", 
+        "DCACHE_TLB2_LL_WAIT",
+        "DCACHE_TLB2_SC_WAIT",   
+        "DCACHE_TLB2_READ",
+        "DCACHE_TLB2_READ_UPDT",  
+        "DCACHE_TLB2_UPDT_SEL",
+        "DCACHE_TLB2_UPDT",   
+        "DCACHE_CTXT_SWITCH",   
+        "DCACHE_ICACHE_FLUSH", 
+        "DCACHE_DCACHE_FLUSH", 
+        "DCACHE_ITLB_INVAL",
+        "DCACHE_DTLB_INVAL",
+        "DCACHE_ICACHE_INVAL",
+        "DCACHE_DCACHE_INVAL",
+        "DCACHE_ICACHE_INVAL_PA",
+        "DCACHE_DCACHE_INVAL_PA",
+        "DCACHE_DCACHE_SYNC",
+        "DCACHE_LL_DIRTY_WAIT",
+        "DCACHE_SC_DIRTY_WAIT",
+        "DCACHE_WRITE_UPDT", 
+        "DCACHE_WRITE_DIRTY",
+        "DCACHE_WRITE_REQ",  
+        "DCACHE_MISS_WAIT",  
+        "DCACHE_MISS_UPDT",  
+        "DCACHE_UNC_WAIT",   
+        "DCACHE_ERROR", 
+        "DCACHE_ITLB_READ",
+        "DCACHE_ITLB_UPDT",
+        "DCACHE_ITLB_LL_WAIT",        
+        "DCACHE_ITLB_SC_WAIT",        
+        "DCACHE_CC_CHECK",
+        "DCACHE_CC_INVAL",
+        "DCACHE_CC_UPDT",
+        "DCACHE_CC_NOP",
+        "DCACHE_TLB_CC_INVAL",
+        "DCACHE_ITLB_CLEANUP",
+    };
+const char *cmd_fsm_state_str[] = {
+        "CMD_IDLE",           
+        "CMD_ITLB_READ", 
+        "CMD_ITLB_ACC_LL",                
+        "CMD_ITLB_ACC_SC",                
+        "CMD_INS_MISS",     
+        "CMD_INS_UNC",     
+        "CMD_DTLB_READ",   
+        "CMD_DTLB_ACC_LL",            
+        "CMD_DTLB_ACC_SC",            
+        "CMD_DTLB_DIRTY_LL",          
+        "CMD_DTLB_DIRTY_SC",          
+        "CMD_DATA_UNC",     
+        "CMD_DATA_MISS",    
+        "CMD_DATA_WRITE", 
+    };
+const char *rsp_fsm_state_str[] = {
+        "RSP_IDLE",                  
+        "RSP_ITLB_READ",             
+        "RSP_ITLB_ACC_LL",                
+        "RSP_ITLB_ACC_SC",                
+        "RSP_INS_MISS",   
+        "RSP_INS_UNC",           
+        "RSP_DTLB_READ",            
+        "RSP_DTLB_ACC_LL",            
+        "RSP_DTLB_ACC_SC",            
+        "RSP_DTLB_DIRTY_LL",          
+        "RSP_DTLB_DIRTY_SC",          
+        "RSP_DATA_MISS",             
+        "RSP_DATA_UNC",              
+        "RSP_DATA_WRITE",     
+    };
+const char *cleanup_cmd_fsm_state_str[] = {
+        "CLEANUP_CMD_IDLE",           
+        "CLEANUP_CMD_DATA",    
+        "CLEANUP_CMD_INS",      
+    };
+const char *cleanup_rsp_fsm_state_str[] = {
+        "CLEANUP_RSP_IDLE",           
+        "CLEANUP_RSP_DATA",    
+        "CLEANUP_RSP_INS",      
+    };
+const char *tgt_fsm_state_str[] = {
+        "TGT_IDLE",
+        "TGT_UPDT_WORD",
+        "TGT_UPDT_DATA",
+        "TGT_REQ_BROADCAST",
+        "TGT_REQ_ICACHE",
+        "TGT_REQ_DCACHE",
+        "TGT_RSP_BROADCAST",
+        "TGT_RSP_ICACHE",
+        "TGT_RSP_DCACHE",
+    };	
+const char *inval_itlb_fsm_state_str[] = {
+        "INVAL_ITLB_IDLE",        
+        "INVAL_ITLB_CHECK"  , 
+        "INVAL_ITLB_INVAL",      
+        "INVAL_ITLB_CLEAR",           
+    };
+const char *inval_dtlb_fsm_state_str[] = {
+        "INVAL_DTLB_IDLE",        
+        "INVAL_DTLB_CHECK", 
+        "INVAL_DTLB_INVAL",    
+        "INVAL_DTLB_CLEAR",         
+    };
+}
+//#endif
+
+#define tmpl(...)  template<typename vci_param, typename iss_t> __VA_ARGS__ VciCcVCacheWrapper2V1<vci_param, iss_t>
+
+using soclib::common::uint32_log2;
+
+/***********************************************/
+tmpl(/**/)::VciCcVCacheWrapper2V1(
+    sc_module_name name,
+    int proc_id,
+    const soclib::common::MappingTable &mtp,
+    const soclib::common::MappingTable &mtc,
+    const soclib::common::IntTab &initiator_index_rw,
+    const soclib::common::IntTab &initiator_index_c,
+    const soclib::common::IntTab &target_index,
+    size_t itlb_ways,
+    size_t itlb_sets,
+    size_t dtlb_ways,
+    size_t dtlb_sets,
+    size_t icache_ways,
+    size_t icache_sets,
+    size_t icache_words,
+    size_t dcache_ways,
+    size_t dcache_sets,
+    size_t dcache_words,
+    size_t write_buf_size )
+/***********************************************/
+    : soclib::caba::BaseModule(name),
+
+      p_clk("clk"),
+      p_resetn("resetn"),
+      p_vci_ini_rw("vci_ini_rw"),
+      p_vci_ini_c("vci_ini_c"),
+      p_vci_tgt("vci_tgt"),
+
+      m_cacheability_table(mtp.getCacheabilityTable()),
+      m_segment(mtc.getSegment(target_index)),
+      m_iss(this->name(), proc_id),
+      m_srcid_rw(mtp.indexForId(initiator_index_rw)),
+      m_srcid_c(mtp.indexForId(initiator_index_c)),
+
+      m_itlb_ways(itlb_ways),
+      m_itlb_sets(itlb_sets),
+
+      m_dtlb_ways(dtlb_ways),
+      m_dtlb_sets(dtlb_sets),
+
+      m_icache_ways(icache_ways),
+      m_icache_sets(icache_sets),
+      m_icache_yzmask((~0)<<(uint32_log2(icache_words) + 2)),
+      m_icache_words(icache_words),
+
+      m_dcache_ways(dcache_ways),
+      m_dcache_sets(dcache_sets),
+      m_dcache_yzmask((~0)<<(uint32_log2(dcache_words) + 2)),
+      m_dcache_words(dcache_words),
+
+      m_write_buf_size(write_buf_size),	
+      m_paddr_nbits(vci_param::N),
+
+      icache_tlb(itlb_ways,itlb_sets,vci_param::N),
+      dcache_tlb(dtlb_ways,dtlb_sets,vci_param::N),
+
+      r_dcache_fsm("r_dcache_fsm"),
+      r_dcache_paddr_save("r_dcache_paddr_save"),
+      r_dcache_wdata_save("r_dcache_wdata_save"),
+      r_dcache_rdata_save("r_dcache_rdata_save"),
+      r_dcache_type_save("r_dcache_type_save"),
+      r_dcache_be_save("r_dcache_be_save"),
+      r_dcache_cached_save("r_dcache_cached_save"),
+      r_dcache_tlb_paddr("r_dcache_tlb_paddr"),
+      r_dcache_miss_req("r_dcache_miss_req"),
+      r_dcache_unc_req("r_dcache_unc_req"),
+      r_dcache_write_req("r_dcache_write_req"),
+      r_dcache_tlb_read_req("r_dcache_tlb_read_req"),
+
+      r_dcache_tlb_ll_acc_req("r_dcache_tlb_ll_acc_req"),       
+      r_dcache_tlb_sc_acc_req("r_dcache_tlb_sc_acc_req"),       
+      r_dcache_tlb_ll_dirty_req("r_dcache_tlb_ll_dirty_req"),    
+      r_dcache_tlb_sc_dirty_req("r_dcache_tlb_sc_dirty_req"), 
+      r_dcache_tlb_ptba_read("r_dcache_tlb_ptba_read"),
+      r_dcache_xtn_req("r_dcache_xtn_req"),
+
+      r_dcache_fsm_save("r_dcache_fsm_save"),
+      r_dcache_cleanup_req("r_dcache_cleanup_req"),
+      r_dcache_inval_rsp("r_dcache_inval_rsp"),
+
+      r_icache_fsm("r_icache_fsm"),
+      r_icache_paddr_save("r_icache_paddr_save"),
+      r_icache_miss_req("r_icache_miss_req"),
+      r_icache_unc_req("r_icache_unc_req"),
+      r_dcache_itlb_read_req("r_dcache_itlb_read_req"),
+      r_dcache_itlb_ll_acc_req("r_dcache_itlb_ll_acc_req"),     
+      r_dcache_itlb_sc_acc_req("r_dcache_itlb_sc_acc_req"),
+
+      r_itlb_read_dcache_req("r_itlb_read_dcache_req"),
+      r_itlb_k_read_dcache("r_itlb_k_read_dcache"),
+      r_itlb_acc_dcache_req("r_itlb_acc_dcache_req"),
+      r_dcache_rsp_itlb_error("r_dcache_rsp_itlb_error"),
+
+      r_icache_fsm_save("r_icache_fsm_save"),
+      r_icache_cleanup_req("r_icache_cleanup_req"),
+      r_icache_inval_rsp("r_icache_inval_rsp"),
+
+      r_vci_cmd_fsm("r_vci_cmd_fsm"),
+      r_vci_cmd_min("r_vci_cmd_min"),
+      r_vci_cmd_max("r_vci_cmd_max"),
+      r_vci_cmd_cpt("r_vci_cmd_cpt"),
+
+      r_vci_rsp_fsm("r_vci_rsp_fsm"),
+      r_vci_rsp_cpt("r_vci_rsp_cpt"),
+      r_vci_rsp_ins_error("r_vci_rsp_ins_error"),
+      r_vci_rsp_data_error("r_vci_rsp_data_error"),
+      r_dcache_tlb_sc_fail("r_dcache_tlb_sc_fail"),
+
+      r_cleanup_cmd_fsm("r_cleanup_cmd_fsm"),
+      r_cleanup_rsp_fsm("r_cleanup_rsp_fsm"),
+
+      r_vci_tgt_fsm("r_vci_tgt_fsm"),
+      r_tgt_addr("r_tgt_addr"),
+      r_tgt_word("r_tgt_word"),
+      r_tgt_update("r_tgt_update"),
+      r_tgt_srcid("r_tgt_srcid"),
+      r_tgt_pktid("r_tgt_pktid"),
+      r_tgt_trdid("r_tgt_trdid"),
+      r_tgt_icache_req("r_tgt_icache_req"),
+      r_tgt_dcache_req("r_tgt_dcache_req"),
+
+      r_inval_itlb_fsm("r_inval_itlb_fsm"),          
+      r_dcache_itlb_inval_req("r_dcache_itlb_inval_req"),
+      r_dcache_itlb_inval_line("r_dcache_itlb_inval_line"),
+      r_itlb_cc_check_end("r_itlb_cc_check_end"),
+      r_ccinval_itlb_way("r_ccinval_itlb_way"), 
+      r_ccinval_itlb_set("r_ccinval_itlb_set"), 
+      r_icache_inval_tlb_rsp("r_icache_inval_tlb_rsp"),
+      r_icache_tlb_nline("r_icache_tlb_nline"),
+
+      r_inval_dtlb_fsm("r_inval_dtlb_fsm"),          
+      r_dcache_dtlb_inval_req("r_dcache_dtlb_inval_req"),
+      r_dcache_dtlb_inval_line("r_dcache_dtlb_inval_line"),
+      r_dtlb_cc_check_end("r_dtlb_cc_check_end"),
+      r_ccinval_dtlb_way("r_ccinval_dtlb_way"), 
+      r_ccinval_dtlb_set("r_ccinval_dtlb_set"), 
+      r_dcache_inval_tlb_rsp("r_dcache_inval_tlb_rsp"),
+      r_dcache_tlb_nline("r_dcache_tlb_nline"),
+
+      r_dcache_itlb_cleanup_req("r_dcache_itlb_cleanup_req"),
+      r_dcache_itlb_cleanup_line("r_dcache_itlb_cleanup_line"),
+
+      r_dcache_dtlb_cleanup_req("r_dcache_dtlb_cleanup_req"),
+      r_dcache_dtlb_cleanup_line("r_dcache_dtlb_cleanup_line"),
+
+      r_wbuf("wbuf", write_buf_size ),
+      r_icache("icache", icache_ways, icache_sets, icache_words),
+      r_dcache("dcache", dcache_ways, dcache_sets, dcache_words)
+{
+    r_icache_miss_buf = new data_t[icache_words];
+    r_dcache_miss_buf = new data_t[dcache_words];
+    r_tgt_buf         = new data_t[dcache_words];
+    r_tgt_val         = new bool[dcache_words];
+    r_dcache_in_itlb  = new bool[dcache_ways*dcache_sets];           
+    r_dcache_in_dtlb  = new bool[dcache_ways*dcache_sets];          
+
+    m_proc_id = proc_id;
+
+    m_tm_start = 0;
+    m_tm_end = 0;
+    m_period = 0;
+    
+    char *ptr;
+    
+    ptr = getenv("TSAR_L1_TM_START");
+    
+    if(ptr != NULL)
+        m_tm_start = (size_t) atol(ptr);
+    
+    ptr = getenv("TSAR_L1_TM_END");
+    
+    if(ptr != NULL)
+        m_tm_end = (size_t) atol(ptr);
+    
+    ptr = getenv("TSAR_L1_PERIOD");
+    
+    if(ptr != NULL)
+        m_period = (size_t) atol(ptr);
+    
+    if(m_period != 0)
+        m_log.open(name, std::ios::out);
+    else
+        m_log.open("/dev/null", std::ios::out);
+    
+    if(m_proc_id == 0)
+    {
+        std::cout << "TSAR_L1_TM_START =" << m_tm_start << std::endl
+                  << "TSAR_L1_TM_END   =" << m_tm_end << std::endl
+                  << "TSAR_L1_PERIOD   =" << m_period << std::endl;
+    }
+
+    SC_METHOD(transition);
+    dont_initialize();
+    sensitive << p_clk.pos();
+  
+    SC_METHOD(genMoore);
+    dont_initialize();
+    sensitive << p_clk.neg();
+
+    typename iss_t::CacheInfo cache_info;
+    cache_info.has_mmu = true;
+    cache_info.icache_line_size = icache_words*sizeof(data_t);
+    cache_info.icache_assoc = icache_ways;
+    cache_info.icache_n_lines = icache_sets;
+    cache_info.dcache_line_size = dcache_words*sizeof(data_t);
+    cache_info.dcache_assoc = dcache_ways;
+    cache_info.dcache_n_lines = dcache_sets;
+    m_iss.setCacheInfo(cache_info);
+}
+
+/////////////////////////////////////
+tmpl(/**/)::~VciCcVCacheWrapper2V1()
+/////////////////////////////////////
+{
+    delete [] r_icache_miss_buf;
+    delete [] r_dcache_miss_buf;
+    delete [] r_tgt_val;
+    delete [] r_tgt_buf;
+    delete [] r_dcache_in_itlb;           
+    delete [] r_dcache_in_dtlb;          
+}
+
+////////////////////////
+tmpl(void)::print_cpi()
+////////////////////////
+{
+    std::cout << name() << " CPI = " 
+        << (float)m_cpt_total_cycles/(m_cpt_total_cycles - m_cpt_frz_cycles) << std::endl ;
+}
+
+////////////////////////////////////
+tmpl(void)::print_trace(size_t mode)
+////////////////////////////////////
+{
+    typename iss_t::InstructionRequest  ireq;
+    typename iss_t::DataRequest         dreq;
+
+    std::ostream  &output = m_log;
+
+    m_iss.getRequests( ireq, dreq );
+   
+    output << std::dec << "L1_(" << name() << ") cycle: " << m_cpt_total_cycles << std::endl;
+    output << " Proc state: PC = " << std::hex << ireq.addr << " / AD = " << dreq.addr 
+              << std::dec << " / V = " << dreq.valid << " / TYPE = " << dreq.type << std::endl;
+    
+    output << " Cache state:"
+              << " tgt fsm: " << tgt_fsm_state_str[r_vci_tgt_fsm]
+              << " dcache fsm: " << dcache_fsm_state_str[r_dcache_fsm]
+              << " icache fsm: " << icache_fsm_state_str[r_icache_fsm]
+              << " cmd fsm: " << cmd_fsm_state_str[r_vci_cmd_fsm]
+              << " rsp fsm: " << rsp_fsm_state_str[r_vci_rsp_fsm] 
+              << " cleanup cmd fsm: " << cleanup_cmd_fsm_state_str[r_cleanup_cmd_fsm]
+              << " cleanup rsp fsm: " << cleanup_rsp_fsm_state_str[r_cleanup_rsp_fsm]
+              << " inval itlb fsm: " << inval_itlb_fsm_state_str[r_inval_itlb_fsm] 
+              << " inval dtlb fsm: " << inval_dtlb_fsm_state_str[r_inval_dtlb_fsm] << std::endl;
+
+    if( r_vci_tgt_fsm != TGT_IDLE ) 
+        output << "    ... coherence request address = " << std::hex << r_tgt_addr.read() << std::endl;
+    
+    if(mode & 0x1)
+    {
+        r_wbuf.printTrace();
+    }
+}
+
+////////////////////////
+tmpl(void)::print_stats()
+////////////////////////
+{
+    std::ostream  &output = m_log;
+
+    float run_cycles = (float)(m_cpt_total_cycles - m_cpt_frz_cycles);
+    output << name() << std::endl
+              << "CPI                     = " << (float)m_cpt_total_cycles/run_cycles << std::endl 
+              << "READ_RATE               = " << (float)m_cpt_read/run_cycles << std::endl 
+              << "WRITE_RATE              = " << (float)m_cpt_write/run_cycles << std::endl
+              << "IMISS_RATE              = " << (float)m_cpt_ins_miss/m_cpt_ins_read << std::endl
+              << "DMISS_RATE              = " << (float)m_cpt_data_miss/(m_cpt_read-m_cpt_unc_read) << std::endl  
+              << "INS_MISS_COST           = " << (float)m_cost_ins_miss_frz/m_cpt_ins_miss << std::endl     
+              << "DATA_MISS_COST          = " << (float)m_cost_data_miss_frz/m_cpt_data_miss << std::endl 
+              << "WRITE_COST              = " << (float)m_cost_write_frz/m_cpt_write << std::endl        
+              << "UNC_COST                = " << (float)m_cost_unc_read_frz/m_cpt_unc_read << std::endl
+              << "UNCACHED_READ_RATE      = " << (float)m_cpt_unc_read/m_cpt_read << std::endl 
+              << "CACHED_WRITE_RATE       = " << (float)m_cpt_write_cached/m_cpt_write << std::endl 
+              << "INS_TLB_MISS_RATE       = " << (float)m_cpt_ins_tlb_miss/m_cpt_ins_tlb_read << std::endl
+              << "DATA_TLB_MISS_RATE      = " << (float)m_cpt_data_tlb_miss/m_cpt_data_tlb_read << std::endl
+              << "ITLB_MISS_COST          = " << (float)m_cost_ins_tlb_miss_frz/m_cpt_ins_tlb_miss << std::endl
+              << "DTLB_MISS_COST          = " << (float)m_cost_data_tlb_miss_frz/m_cpt_data_tlb_miss << std::endl   
+              << "ITLB_UPDATE_ACC_COST    = " << (float)m_cost_ins_tlb_update_acc_frz/m_cpt_ins_tlb_update_acc << std::endl
+              << "DTLB_UPDATE_ACC_COST    = " << (float)m_cost_data_tlb_update_acc_frz/m_cpt_data_tlb_update_acc << std::endl
+              << "DTLB_UPDATE_DIRTY_COST  = " << (float)m_cost_data_tlb_update_dirty_frz/m_cpt_data_tlb_update_dirty << std::endl
+              << "ITLB_HIT_IN_DCACHE_RATE = " << (float)m_cpt_ins_tlb_hit_dcache/m_cpt_ins_tlb_miss << std::endl
+              << "DTLB_HIT_IN_DCACHE_RATE = " << (float)m_cpt_data_tlb_hit_dcache/m_cpt_data_tlb_miss << std::endl
+              << "DCACHE FROZEN BY ITLB   = " << (float)m_cost_ins_tlb_occup_cache_frz/m_cpt_dcache_frz_cycles << std::endl
+              << "DCACHE_FOR_TLB_%        = " << (float)m_cpt_tlb_occup_dcache/(m_dcache_ways*m_dcache_sets) << std::endl
+              << "NB_CC_BROADCAST         = " << m_cpt_cc_broadcast << std::endl
+              << "NB_CC_UPDATE_DATA       = " << m_cpt_cc_update_data << std::endl
+              << "NB_CC_INVAL_DATA        = " << m_cpt_cc_inval_data << std::endl
+              << "NB_CC_INVAL_INS         = " << m_cpt_cc_inval_ins << std::endl
+              << "NB_CC_CLEANUP_DATA      = " << m_cpt_cc_cleanup_data << std::endl
+              << "NB_CC_CLEANUP_INS       = " << m_cpt_cc_cleanup_ins << std::endl
+              << "CC BROADCAST COST       = " << (float)m_cost_broadcast_frz/m_cpt_cc_broadcast << std::endl
+              << "CC UPDATE DATA COST     = " << (float)m_cost_updt_data_frz/m_cpt_cc_update_data << std::endl
+              << "CC INVAL DATA COST      = " << (float)m_cost_inval_data_frz/m_cpt_cc_inval_data << std::endl
+              << "CC INVAL INS COST       = " << (float)m_cost_inval_ins_frz/m_cpt_cc_inval_ins << std::endl
+              << "IMISS_TRANSACTION       = " << (float)m_cost_imiss_transaction/m_cpt_imiss_transaction << std::endl
+              << "DMISS_TRANSACTION       = " << (float)m_cost_dmiss_transaction/m_cpt_dmiss_transaction << std::endl
+              << "UNC_TRANSACTION         = " << (float)m_cost_unc_transaction/m_cpt_unc_transaction << std::endl
+              << "WRITE_TRANSACTION       = " << (float)m_cost_write_transaction/m_cpt_write_transaction << std::endl
+              << "WRITE_LENGTH            = " << (float)m_length_write_transaction/m_cpt_write_transaction << std::endl
+              << "ITLB_MISS_TRANSACTION   = " << (float)m_cost_itlbmiss_transaction/m_cpt_itlbmiss_transaction << std::endl
+              << "DTLB_MISS_TRANSACTION   = " << (float)m_cost_dtlbmiss_transaction/m_cpt_dtlbmiss_transaction << std::endl;
+}
+
+////////////////////////
+tmpl(void)::clear_stats()
+////////////////////////
+{
+    m_cpt_dcache_data_read  = 0;
+    m_cpt_dcache_data_write = 0;
+    m_cpt_dcache_dir_read   = 0;
+    m_cpt_dcache_dir_write  = 0;
+    m_cpt_icache_data_read  = 0;
+    m_cpt_icache_data_write = 0;
+    m_cpt_icache_dir_read   = 0;
+    m_cpt_icache_dir_write  = 0;
+    
+    m_cpt_frz_cycles        = 0;
+    m_cpt_dcache_frz_cycles = 0;
+    m_cpt_total_cycles      = 0;
+    
+    m_cpt_read         = 0;
+    m_cpt_write        = 0;
+    m_cpt_data_miss    = 0;
+    m_cpt_ins_miss     = 0;
+    m_cpt_unc_read     = 0;
+    m_cpt_write_cached = 0;
+    m_cpt_ins_read     = 0;
+    
+    m_cost_write_frz     = 0;
+    m_cost_data_miss_frz = 0;
+    m_cost_unc_read_frz  = 0;
+    m_cost_ins_miss_frz  = 0;
+    
+    m_cpt_imiss_transaction      = 0;
+    m_cpt_dmiss_transaction      = 0;
+    m_cpt_unc_transaction        = 0;
+    m_cpt_write_transaction      = 0;
+    m_cpt_icache_unc_transaction = 0;	
+    
+    m_cost_imiss_transaction      = 0;
+    m_cost_dmiss_transaction      = 0;
+    m_cost_unc_transaction        = 0;
+    m_cost_write_transaction      = 0;
+    m_cost_icache_unc_transaction = 0;
+    m_length_write_transaction    = 0;
+    
+    m_cpt_ins_tlb_read       = 0;             
+    m_cpt_ins_tlb_miss       = 0;             
+    m_cpt_ins_tlb_update_acc = 0;         
+    
+    m_cpt_data_tlb_read         = 0;           
+    m_cpt_data_tlb_miss         = 0;           
+    m_cpt_data_tlb_update_acc   = 0;       
+    m_cpt_data_tlb_update_dirty = 0;    
+    m_cpt_ins_tlb_hit_dcache    = 0;
+    m_cpt_data_tlb_hit_dcache   = 0;
+    m_cpt_ins_tlb_occup_cache   = 0;
+    m_cpt_data_tlb_occup_cache  = 0;
+    
+    m_cost_ins_tlb_miss_frz          = 0;      
+    m_cost_data_tlb_miss_frz         = 0;      
+    m_cost_ins_tlb_update_acc_frz    = 0;
+    m_cost_data_tlb_update_acc_frz   = 0;
+    m_cost_data_tlb_update_dirty_frz = 0;
+    m_cost_ins_tlb_occup_cache_frz   = 0;
+    m_cost_data_tlb_occup_cache_frz  = 0;
+    
+    m_cpt_itlbmiss_transaction      = 0;    
+    m_cpt_itlb_ll_transaction       = 0;  
+    m_cpt_itlb_sc_transaction       = 0;  
+    m_cpt_dtlbmiss_transaction      = 0;  
+    m_cpt_dtlb_ll_transaction       = 0;  
+    m_cpt_dtlb_sc_transaction       = 0;  
+    m_cpt_dtlb_ll_dirty_transaction = 0;  
+    m_cpt_dtlb_sc_dirty_transaction = 0;  
+    
+    m_cost_itlbmiss_transaction      = 0;   
+    m_cost_itlb_ll_transaction       = 0;  
+    m_cost_itlb_sc_transaction       = 0;  
+    m_cost_dtlbmiss_transaction      = 0;   
+    m_cost_dtlb_ll_transaction       = 0;   
+    m_cost_dtlb_sc_transaction       = 0;   
+    m_cost_dtlb_ll_dirty_transaction = 0;   
+    m_cost_dtlb_sc_dirty_transaction = 0;
+
+    m_cpt_cc_update_data = 0;
+    m_cpt_cc_inval_ins   = 0;
+    m_cpt_cc_inval_data  = 0;
+    m_cpt_cc_broadcast   = 0;
+
+    m_cost_updt_data_frz  = 0;
+    m_cost_inval_ins_frz  = 0;
+    m_cost_inval_data_frz = 0;
+    m_cost_broadcast_frz  = 0;
+
+    m_cpt_cc_cleanup_data = 0;
+    m_cpt_cc_cleanup_ins  = 0;
+}
+
+/*************************************************/
+tmpl(void)::transition()
+/*************************************************/
+{
+    if ( ! p_resetn.read() ) 
+    {
+        m_iss.reset();
+
+        r_dcache_fsm = DCACHE_IDLE;
+        r_icache_fsm = ICACHE_IDLE;
+        r_vci_cmd_fsm = CMD_IDLE;
+        r_vci_rsp_fsm = RSP_IDLE;
+        r_vci_tgt_fsm = TGT_IDLE;
+        r_inval_itlb_fsm = INVAL_ITLB_IDLE;          
+        r_inval_dtlb_fsm = INVAL_DTLB_IDLE;          
+        r_cleanup_cmd_fsm = CLEANUP_CMD_IDLE;
+        r_cleanup_rsp_fsm = CLEANUP_RSP_IDLE;
+
+        // write buffer & caches
+        r_wbuf.reset();
+        r_icache.reset();
+        r_dcache.reset();
+
+        icache_tlb.reset();    
+        dcache_tlb.reset();    
+
+        std::memset(r_dcache_in_itlb, 0, sizeof(*r_dcache_in_itlb)*m_icache_ways*m_icache_sets);
+        std::memset(r_dcache_in_dtlb, 0, sizeof(*r_dcache_in_dtlb)*m_dcache_ways*m_dcache_sets);
+
+        //r_mmu_mode = ALL_DEACTIVE;
+        r_mmu_mode = 0x3;
+        r_mmu_params = (uint32_log2(m_dtlb_ways) << 29)   | (uint32_log2(m_dtlb_sets) << 25)   |
+                       (uint32_log2(m_dcache_ways) << 22) | (uint32_log2(m_dcache_sets) << 18) |
+                       (uint32_log2(m_itlb_ways) << 15)   | (uint32_log2(m_itlb_sets) << 11)   |
+                       (uint32_log2(m_icache_ways) << 8)  | (uint32_log2(m_icache_sets) << 4)  |
+                       (uint32_log2(m_icache_words * 4));
+        r_mmu_release = (uint32_t)(1 << 16) | 0x1;
+
+        r_icache_miss_req         = false;
+        r_icache_unc_req          = false;
+        r_dcache_itlb_read_req    = false;
+
+        r_itlb_read_dcache_req    = false;      
+        r_itlb_k_read_dcache      = false;      
+        r_itlb_acc_dcache_req     = false;   
+        r_itlb_acc_redo_req 	  = false;
+        r_dcache_rsp_itlb_error   = false;
+ 
+        r_dcache_miss_req         = false;
+        r_dcache_unc_req          = false;
+        r_dcache_write_req        = false;
+        r_dcache_tlb_read_req     = false;
+        r_dcache_tlb_ptba_read    = false;
+        r_dcache_xtn_req          = false;
+        r_dcache_llsc_reserved    = false;
+
+        r_dcache_tlb_ll_acc_req   = false;    
+        r_dcache_tlb_sc_acc_req   = false;    
+        r_dcache_tlb_ll_dirty_req = false;   
+        r_dcache_tlb_sc_dirty_req = false; 
+        r_dcache_sc_updt_dirty    = false;	
+        r_dcache_itlb_ll_acc_req  = false;   
+        r_dcache_itlb_sc_acc_req  = false;   
+
+        r_icache_cleanup_req      = false;
+        r_dcache_cleanup_req      = false;
+
+        r_tgt_icache_req          = false;
+        r_tgt_dcache_req          = false;
+
+        r_icache_inval_rsp        = false;
+        r_dcache_inval_rsp        = false;
+
+        r_dcache_dirty_save       = false;
+        r_dcache_hit_p_save       = false;
+        r_dcache_cached_save      = false;
+
+        r_icache_buf_unc_valid    = false;
+        r_dcache_buf_unc_valid    = false;
+
+        r_vci_rsp_ins_error       = false;
+        r_vci_rsp_data_error      = false;
+
+        r_icache_id1_save         = 0;
+        r_icache_ppn_save         = 0;
+        r_icache_vpn_save         = 0;
+        r_itlb_translation_valid  = false;
+
+        r_dcache_id1_save         = 0;
+        r_dcache_ppn_save         = 0;
+        r_dcache_vpn_save         = 0;
+        r_dtlb_translation_valid  = false;
+
+        r_icache_ptba_ok          = false;
+        r_dcache_ptba_ok          = false;
+
+        r_icache_error_type       = MMU_NONE;
+        r_dcache_error_type       = MMU_NONE;
+
+        // coherence registers
+        r_icache_way              = 0;
+        r_icache_set              = 0;
+        r_icache_cleanup_req      = false;
+        r_icache_inval_rsp        = false;
+
+        r_dcache_way              = 0;
+        r_dcache_set              = 0;
+        r_dcache_cleanup_req      = false;
+        r_dcache_inval_rsp        = false;
+
+        r_itlb_inval_req 	  = false;
+        r_dcache_itlb_inval_req   = false;
+        r_itlb_cc_check_end       = false;
+        r_ccinval_itlb_way        = 0; 
+        r_ccinval_itlb_set        = 0; 
+        r_icache_inval_tlb_rsp    = false;
+
+        r_dcache_dtlb_inval_req   = false;
+        r_dtlb_cc_check_end       = false;
+        r_ccinval_dtlb_way        = 0; 
+        r_ccinval_dtlb_set        = 0; 
+        r_dcache_inval_tlb_rsp    = false;
+
+        r_dcache_itlb_cleanup_req = false;
+        r_dcache_dtlb_cleanup_req = false;
+
+        r_dcache_cc_check         = false;
+        r_dcache_tlb_sc_fail	  = false;
+
+        // activity counters
+        m_cpt_dcache_data_read  = 0;
+        m_cpt_dcache_data_write = 0;
+        m_cpt_dcache_dir_read   = 0;
+        m_cpt_dcache_dir_write  = 0;
+        m_cpt_icache_data_read  = 0;
+        m_cpt_icache_data_write = 0;
+        m_cpt_icache_dir_read   = 0;
+        m_cpt_icache_dir_write  = 0;
+
+        m_cpt_frz_cycles        = 0;
+        m_cpt_dcache_frz_cycles = 0;
+        m_cpt_total_cycles      = 0;
+
+        m_cpt_read         = 0;
+        m_cpt_write        = 0;
+        m_cpt_data_miss    = 0;
+        m_cpt_ins_miss     = 0;
+        m_cpt_unc_read     = 0;
+        m_cpt_write_cached = 0;
+        m_cpt_ins_read     = 0;
+
+        m_cost_write_frz     = 0;
+        m_cost_data_miss_frz = 0;
+        m_cost_unc_read_frz  = 0;
+        m_cost_ins_miss_frz  = 0;
+
+        m_cpt_imiss_transaction      = 0;
+        m_cpt_dmiss_transaction      = 0;
+        m_cpt_unc_transaction        = 0;
+        m_cpt_write_transaction      = 0;
+        m_cpt_icache_unc_transaction = 0;	
+
+        m_cost_imiss_transaction      = 0;
+        m_cost_dmiss_transaction      = 0;
+        m_cost_unc_transaction        = 0;
+        m_cost_write_transaction      = 0;
+        m_cost_icache_unc_transaction = 0;
+        m_length_write_transaction    = 0;
+
+        m_cpt_ins_tlb_read       = 0;             
+        m_cpt_ins_tlb_miss       = 0;             
+        m_cpt_ins_tlb_update_acc = 0;         
+
+        m_cpt_data_tlb_read         = 0;           
+        m_cpt_data_tlb_miss         = 0;           
+        m_cpt_data_tlb_update_acc   = 0;       
+        m_cpt_data_tlb_update_dirty = 0;    
+        m_cpt_ins_tlb_hit_dcache    = 0;
+        m_cpt_data_tlb_hit_dcache   = 0;
+        m_cpt_ins_tlb_occup_cache   = 0;
+        m_cpt_data_tlb_occup_cache  = 0;
+
+        m_cost_ins_tlb_miss_frz          = 0;      
+        m_cost_data_tlb_miss_frz         = 0;      
+        m_cost_ins_tlb_update_acc_frz    = 0;
+        m_cost_data_tlb_update_acc_frz   = 0;
+        m_cost_data_tlb_update_dirty_frz = 0;
+        m_cost_ins_tlb_occup_cache_frz   = 0;
+        m_cost_data_tlb_occup_cache_frz  = 0;
+
+    	m_cpt_ins_tlb_inval       = 0;           
+    	m_cpt_data_tlb_inval      = 0;          
+    	m_cost_ins_tlb_inval_frz  = 0;     
+    	m_cost_data_tlb_inval_frz = 0;         
+
+        m_cpt_cc_update_data = 0;
+        m_cpt_cc_inval_ins   = 0;
+        m_cpt_cc_inval_data  = 0;
+        m_cpt_cc_broadcast   = 0;
+        
+        m_cost_updt_data_frz  = 0;
+        m_cost_inval_ins_frz  = 0;
+        m_cost_inval_data_frz = 0;
+        m_cost_broadcast_frz  = 0;
+
+        m_cpt_cc_cleanup_data = 0;
+        m_cpt_cc_cleanup_ins  = 0;
+
+        m_cpt_itlbmiss_transaction      = 0;    
+        m_cpt_itlb_ll_transaction       = 0;  
+        m_cpt_itlb_sc_transaction       = 0;  
+        m_cpt_dtlbmiss_transaction      = 0;  
+        m_cpt_dtlb_ll_transaction       = 0;  
+        m_cpt_dtlb_sc_transaction       = 0;  
+        m_cpt_dtlb_ll_dirty_transaction = 0;  
+        m_cpt_dtlb_sc_dirty_transaction = 0;  
+ 
+        m_cost_itlbmiss_transaction      = 0;   
+        m_cost_itlb_ll_transaction       = 0;  
+        m_cost_itlb_sc_transaction       = 0;  
+        m_cost_dtlbmiss_transaction      = 0;   
+        m_cost_dtlb_ll_transaction       = 0;   
+        m_cost_dtlb_sc_transaction       = 0;   
+        m_cost_dtlb_ll_dirty_transaction = 0;   
+        m_cost_dtlb_sc_dirty_transaction = 0;   
+
+        /// For instrumentation
+        r_ireq_isUser_save = false;
+        r_dreq_isUser_save = false;
+        return;
+    }
+
+#ifdef SOCLIB_MODULE_DEBUG
+std::cout << name() << " cycle = " << std::dec << m_cpt_total_cycles  
+       	  << " tgt fsm: " << tgt_fsm_state_str[r_vci_tgt_fsm]
+       	  << " dcache fsm: " << dcache_fsm_state_str[r_dcache_fsm]
+       	  << " icache fsm: " << icache_fsm_state_str[r_icache_fsm]
+       	  << " cmd fsm: " << cmd_fsm_state_str[r_vci_cmd_fsm]
+       	  << " rsp fsm: " << rsp_fsm_state_str[r_vci_rsp_fsm] 
+          << " cleanup cmd fsm: " << cleanup_cmd_fsm_state_str[r_cleanup_cmd_fsm]
+          << " cleanup rsp fsm: " << cleanup_rsp_fsm_state_str[r_cleanup_rsp_fsm]
+       	  << " inval itlb fsm: " << inval_itlb_fsm_state_str[r_inval_itlb_fsm] 
+          << " inval dtlb fsm: " << inval_dtlb_fsm_state_str[r_inval_dtlb_fsm] << std::endl;
+#endif
+
+    m_cpt_total_cycles++;
+
+    if((m_period != 0) && ((m_cpt_total_cycles % m_period) == 0))
+    {
+        print_stats();
+        clear_stats();
+    }
+
+    typename iss_t::InstructionRequest ireq = ISS_IREQ_INITIALIZER;
+    typename iss_t::InstructionResponse irsp = ISS_IRSP_INITIALIZER;
+
+    typename iss_t::DataRequest dreq = ISS_DREQ_INITIALIZER;
+    typename iss_t::DataResponse drsp = ISS_DRSP_INITIALIZER;
+
+    m_iss.getRequests( ireq, dreq );
+
+#ifdef SOCLIB_MODULE_DEBUG
+    std::cout << name() << " Instruction Request: " << ireq << std::endl;
+    std::cout << name() << " Data Request: " << dreq << std::endl;
+#endif
+
+    /////////////////////////////////////////////////////////////////////
+    // The TGT_FSM controls the following ressources:
+    // - r_vci_tgt_fsm
+    // - r_tgt_buf[nwords]
+    // - r_tgt_val[nwords]
+    // - r_tgt_update
+    // - r_tgt_word
+    // - r_tgt_addr
+    // - r_tgt_srcid
+    // - r_tgt_trdid
+    // - r_tgt_pktid
+    // All VCI commands must be CMD_WRITE.
+    // If the VCI address offset is null, the command is an invalidate 
+    // request. It is an update request otherwise.
+    // The VCI_TGT FSM stores the external request arguments in the
+    // IDLE, UPDT_WORD & UPDT_DATA states. It sets the r_tgt_icache_req 
+    // & r_tgt_dcache_req flip-flops to signal the external request to 
+    // the ICACHE & DCACHE FSMs in the REQ state. It waits the completion
+    // of the update or invalidate request in the RSP state.
+    // -  for an invalidate request the VCI packet length is 1 word.
+    // The WDATA field contains the line index (i.e. the Z & Y fields).
+    // -  for an update request the VCI packet length is (n+2) words.
+    // The WDATA field of the first VCI word contains the line number.
+    // The WDATA field of the second VCI word contains the word index.
+    // The WDATA field of the n following words contains the values.
+    // -  for both invalidate & update requests, the VCI response
+    // is one single word.
+    // In case of errors in the VCI command packet, the simulation
+    // is stopped with an error message.
+    /////////////////////////////////////////////////////////////////////
+    
+    switch(r_vci_tgt_fsm) {
+    //////////////
+    case TGT_IDLE:
+    {
+        if ( p_vci_tgt.cmdval.read() ) 
+        {
+            paddr_t address = p_vci_tgt.address.read();
+
+            if ( p_vci_tgt.cmd.read() != vci_param::CMD_WRITE) 
+            {
+                std::cout << "error in component VCI_CC_VCACHE_WRAPPER " << name() << std::endl;
+                std::cout << "the received VCI command is not a write" << std::endl;
+                exit(0);
+            }
+
+            // multi-update or multi-invalidate for data type
+            if ( ( (address & 0x3) != 0x3 ) && ( ! m_segment.contains(address)) ) 
+            {
+                std::cout << "error in component VCI_CC_VCACHE_WRAPPER " << name() << std::endl;
+                std::cout << "out of segment VCI command received for a multi-updt or multi-inval request" << std::endl;
+                exit(0);
+            }
+
+            r_tgt_srcid = p_vci_tgt.srcid.read();
+            r_tgt_trdid = p_vci_tgt.trdid.read();
+            r_tgt_pktid = p_vci_tgt.pktid.read();
+            r_tgt_plen  = p_vci_tgt.plen.read(); // todo: wait L2 modification
+            r_tgt_addr  = ((paddr_t)(p_vci_tgt.be.read() & 0x3) << 32)   |
+                          ((paddr_t)p_vci_tgt.wdata.read() * m_dcache_words * 4); 
+
+            if ( (address & 0x3) == 0x3 ) // broadcast invalidate for data or instruction type
+            {
+                if ( ! p_vci_tgt.eop.read() ) 
+                {
+                    std::cout << "error in component VCI_CC_VCACHE_WRAPPER " << name() << std::endl;
+                    std::cout << "the BROADCAST INVALIDATE command length must be one word" << std::endl;
+                    exit(0);
+                }
+
+                r_tgt_update = false; 
+                r_vci_tgt_fsm = TGT_REQ_BROADCAST;
+                m_cpt_cc_broadcast++;
+                m_cost_broadcast_frz++;
+            }
+            else                // multi-update or multi-invalidate for data type
+            {
+                paddr_t cell = address - m_segment.baseAddress();   
+
+                if (cell == 0)                      // invalidate   
+                {                         
+                    if ( ! p_vci_tgt.eop.read() ) 
+                    {
+                        std::cout << "error in component VCI_CC_VCACHE_WRAPPER " << name() << std::endl;
+                        std::cout << "the MULTI-INVALIDATE command length must be one word" << std::endl;
+                        exit(0);
+                    }
+
+                    r_tgt_update = false; 
+                    r_vci_tgt_fsm = TGT_REQ_DCACHE;
+                    m_cpt_cc_inval_data++ ;
+                    m_cost_inval_data_frz++;
+                }
+                else if (cell == 4)                // update 
+                {                                
+                    if ( p_vci_tgt.eop.read() ) 
+                    {
+                        std::cout << "error in component VCI_CC_VCACHE_WRAPPER " << name() << std::endl;
+                        std::cout << "the MULTI-UPDATE command length must be N+2 words" << std::endl;
+                        exit(0);
+                    }
+
+                    r_tgt_update = true; 
+                    r_vci_tgt_fsm = TGT_UPDT_WORD;
+                    m_cpt_cc_update_data++ ;
+                    m_cost_updt_data_frz++;
+                }     
+                else if (cell == 8)
+                {
+                    if ( ! p_vci_tgt.eop.read() ) 
+                    {
+                        std::cout << "error in component VCI_CC_VCACHE_WRAPPER " << name() << std::endl;
+                        std::cout << "the MULTI-INVALIDATE command length must be one word" << std::endl;
+                        exit(0);
+                    }
+                
+                    r_tgt_update = false; 
+                    r_vci_tgt_fsm = TGT_REQ_ICACHE;
+                    m_cpt_cc_inval_ins++ ;
+                    m_cost_inval_ins_frz++;
+                }
+            } // end if address    
+        } // end if cmdval
+        break;
+    }
+    ///////////////////
+    case TGT_UPDT_WORD:
+    {
+        m_cost_updt_data_frz++;
+
+        if (p_vci_tgt.cmdval.read()) 
+        {
+            if ( p_vci_tgt.eop.read() ) 
+            {
+                std::cout << "error in component VCI_CC_VCACHE_WRAPPER " << name() << std::endl;
+                std::cout << "the MULTI-UPDATE command length must be N+2 words" << std::endl;
+                exit(0);
+            }
+            for ( size_t i=0 ; i < m_dcache_words ; i++ ) r_tgt_val[i] = false;
+            r_tgt_word = p_vci_tgt.wdata.read(); // the first modified word index
+            r_vci_tgt_fsm = TGT_UPDT_DATA;
+        }
+        break;
+    }
+    ///////////////////
+    case TGT_UPDT_DATA:
+    {
+        m_cost_updt_data_frz++;
+
+        if (p_vci_tgt.cmdval.read()) 
+        {
+            size_t word = r_tgt_word.read();
+            if (word >= m_dcache_words) 
+            {
+                std::cout << "error in component VCI_CC_VCACHE_WRAPPER " << name() << std::endl;
+                std::cout << "the reveived MULTI-UPDATE command length is wrong" << std::endl;
+                exit(0);
+            }
+            r_tgt_buf[word] = p_vci_tgt.wdata.read();
+            if(p_vci_tgt.be.read())    r_tgt_val[word] = true;
+            r_tgt_word = word + 1;
+            if (p_vci_tgt.eop.read())  r_vci_tgt_fsm = TGT_REQ_DCACHE;
+        }
+        break;
+    }
+    ////////////////////////
+    case TGT_REQ_BROADCAST:
+    {
+        m_cost_broadcast_frz++;
+
+        if ( !r_tgt_icache_req.read() && !r_tgt_dcache_req.read() ) 
+        {
+            r_vci_tgt_fsm = TGT_RSP_BROADCAST; 
+            r_tgt_icache_req = true;
+            r_tgt_dcache_req = true;
+        }
+        break;
+    }
+    /////////////////////
+    case TGT_REQ_ICACHE:
+    {
+        m_cost_inval_ins_frz++;
+
+        if ( !r_tgt_icache_req.read() ) 
+        {
+            r_vci_tgt_fsm = TGT_RSP_ICACHE; 
+            r_tgt_icache_req = true;
+        }
+        break;
+    }
+    /////////////////////
+    case TGT_REQ_DCACHE:
+    {
+        if (r_tgt_update) 
+            m_cost_updt_data_frz++;
+        else 
+            m_cost_inval_data_frz++;
+
+        if ( !r_tgt_dcache_req.read() ) 
+        {
+            r_vci_tgt_fsm = TGT_RSP_DCACHE; 
+            r_tgt_dcache_req = true;
+        }
+        break;
+    }
+    ///////////////////////
+    case TGT_RSP_BROADCAST:
+    {
+        m_cost_broadcast_frz++;
+
+        // no response
+        if ( !r_tgt_icache_rsp.read() && !r_tgt_dcache_rsp.read() && !r_tgt_icache_req.read() && !r_tgt_dcache_req.read() )
+        {
+            r_vci_tgt_fsm = TGT_IDLE;
+            break;
+        }
+
+        if ( p_vci_tgt.rspack.read() && !r_tgt_icache_req.read() && !r_tgt_dcache_req.read() ) 
+        {
+            // one response
+            if ( !r_tgt_icache_rsp || !r_tgt_dcache_rsp )
+            {
+                r_vci_tgt_fsm = TGT_IDLE; 
+                r_tgt_icache_rsp = false;
+                r_tgt_dcache_rsp = false;
+            }
+
+            // if data and instruction have the inval line, need two responses  
+            if ( r_tgt_icache_rsp && r_tgt_dcache_rsp )
+            {
+                r_tgt_icache_rsp = false; // only reset one for respond the second time 
+            }
+        }
+        break;
+    }
+    /////////////////////
+    case TGT_RSP_ICACHE:
+    {
+        m_cost_inval_ins_frz++;
+
+        if ( (p_vci_tgt.rspack.read() || !r_tgt_icache_rsp.read()) && !r_tgt_icache_req.read() ) 
+        {
+            r_vci_tgt_fsm = TGT_IDLE;
+            r_tgt_icache_rsp = false; 
+        }
+        break;
+    }
+    /////////////////////
+    case TGT_RSP_DCACHE:
+    {
+        if (r_tgt_update) 
+            m_cost_updt_data_frz++;
+        else 
+            m_cost_inval_data_frz++;
+        
+        if ( (p_vci_tgt.rspack.read() || !r_tgt_dcache_rsp.read()) && !r_tgt_dcache_req.read() )
+        {
+            r_vci_tgt_fsm = TGT_IDLE;
+            r_tgt_dcache_rsp = false; 
+        }
+        break;
+    }
+    } // end switch TGT_FSM
+
+    ////////////////////////////////////////////////////////////////////////////////////////
+    //      ICACHE_FSM
+    //
+    // There is 9 mutually exclusive conditions to exit the IDLE state.
+    // Four configurations corresponding to an XTN request from processor,
+    // - Flush TLB (in case of Context switch) => TLB_FLUSH state 
+    // - Flush cache => CACHE_FLUSH state 
+    // - Invalidate a TLB entry => TLB_INVAL state
+    // - Invalidate a cache line => CACHE_INVAL state
+    // Five configurations corresponding to various TLB or cache MISS :
+    // - TLB miss(in case hit_p miss) => TLB1_READ state
+    // - TLB miss(in case hit_p hit) => TLB2_READ state
+    // - Hit in TLB but VPN changed => BIS state
+    // - Cached read miss => MISS_REQ state
+    // - Uncache read miss => UNC_REQ state
+    // 
+    // In case of MISS, the controller writes a request in the r_icache_paddr_save register 
+    // and sets the corresponding request flip-flop : r_dcache_itlb_read_req, r_icache_miss_req 
+    // or r_icache_unc_req. These request flip-flops are reset by the VCI_RSP controller 
+    // when the response is ready in the ICACHE buffer.
+    //
+    // The DCACHE FSM signals XTN processor requests using the r_dcache_xtn_req flip-flop. 
+    // The request opcod and the address to be invalidated are transmitted
+    // in the r_dcache_paddr_save & r_dcache_wdata_save registers respectively.
+    // The request flip-flop is reset by the ICACHE_FSM when the operation is completed.
+    //
+    // The r_vci_rsp_ins_error flip-flop is set by the VCI_RSP FSM and reset
+    // by the ICACHE-FSM in the ICACHE_ERROR state.
+    //
+    //----------------------------------------------------------------------------------- 
+    // Instruction TLB: 
+    //  
+    // - int        ET          (00: unmapped; 01: unused or PTD)
+    //                          (10: PTE new;  11: PTE old      )
+    // - bool       cachable    (cached bit)
+    // - bool       writable    (** not used alwayse false) 
+    // - bool       executable  (executable bit)
+    // - bool       user        (access in user mode allowed)
+    // - bool       global      (PTE not invalidated by a TLB flush)
+    // - bool       dirty       (** not used alwayse false) 
+    // - uint32_t   vpn         (virtual page number)
+    // - uint32_t   ppn         (physical page number)
+    ////////////////////////////////////////////////////////////////////////////////////////
+
+    switch(r_icache_fsm) {
+
+    ////////////////
+    case ICACHE_IDLE:
+    {
+        pte_info_t  icache_pte_info;
+        paddr_t     tlb_ipaddr       = 0;    	// physical address obtained from TLB                         
+        paddr_t     spc_ipaddr       = 0;    	// physical adress obtained from PPN_save (speculative)       
+        data_t      icache_ins       = 0;    	// read instruction
+        bool        icache_hit_c     = false;	// Cache hit
+        bool        icache_cached    = false;	// cacheable access (read)
+        bool        icache_hit_t     = false;	// hit on TLB
+        bool        icache_hit_x     = false;	// VPN unmodified (can use spc_dpaddr)
+        bool        icache_hit_p     = false;	// PTP unmodified (can skip first level page table walk)
+        size_t      icache_tlb_way   = 0;    	// selected way (in case of cache hit)
+        size_t      icache_tlb_set   = 0;    	// selected set (Y field in address)
+        paddr_t     icache_tlb_nline = 0;  	    // TLB NLINE 
+
+        // Decoding processor XTN requests
+        // They are sent by DCACHE FSM  
+
+        if (r_dcache_xtn_req)
+        {
+            if ((int)r_dcache_type_save == (int)iss_t::XTN_PTPR )  
+            {
+                r_icache_way = 0;
+                r_icache_set = 0;
+                r_icache_fsm = ICACHE_SW_FLUSH;   
+                break;
+            }
+            if ((int)r_dcache_type_save == (int)iss_t::XTN_ICACHE_FLUSH)
+            {
+                r_icache_way = 0;
+                r_icache_set = 0;
+                r_icache_fsm = ICACHE_CACHE_FLUSH;   
+                break;
+            }
+            if ((int)r_dcache_type_save == (int)iss_t::XTN_ITLB_INVAL) 
+            {
+                r_icache_fsm = ICACHE_TLB_INVAL;   
+                break;
+            }
+            if ((int)r_dcache_type_save == (int)iss_t::XTN_ICACHE_INVAL) 
+            {
+                r_icache_fsm = ICACHE_CACHE_INVAL;   
+                break;
+            }
+            if ((int)r_dcache_type_save == (int)iss_t::XTN_MMU_ICACHE_PA_INV) 
+            {
+                r_icache_fsm = ICACHE_CACHE_INVAL_PA;   
+                break;
+            }
+            if ((int)r_dcache_type_save == (int)iss_t::XTN_DCACHE_FLUSH )  
+            {
+                // special for ins tlb miss via data cache
+                r_icache_fsm = ICACHE_TLB_FLUSH;   
+                break;
+            }
+        } // end if xtn_req
+
+        // external cache invalidate request
+        if ( r_tgt_icache_req )
+        {
+            r_icache_fsm = ICACHE_CC_INVAL;
+            r_icache_fsm_save = r_icache_fsm;
+            break;
+        }
+
+        // external tlb invalidate request
+        if ( r_dcache_itlb_inval_req )
+        {
+            r_itlb_inval_req = true;
+            r_icache_fsm = ICACHE_TLB_CC_INVAL;
+            r_icache_fsm_save = r_icache_fsm;
+            break;
+        }
+
+        // icache_hit_t_m, icache_hit_t_k, icache_hit_x, icache_hit_p 
+        // icache_pte_info, icache_tlb_way, icache_tlb_set & ipaddr & cacheability 
+        // - If MMU activated : cacheability is defined by the cachable bit in the TLB
+        // - If MMU not activated : cacheability is defined by the segment table.
+
+        if ( !(r_mmu_mode.read() & INS_TLB_MASK) )   // MMU not activated 
+        {
+            icache_hit_t  = true;         
+            icache_hit_x  = true;         
+            icache_hit_p  = true;         
+            tlb_ipaddr    = ireq.addr;
+            spc_ipaddr    = ireq.addr;
+            icache_cached = m_cacheability_table[ireq.addr];
+        } 
+        else                                                                // MMU activated
+        { 
+            m_cpt_ins_tlb_read++;
+            icache_hit_t  = icache_tlb.cctranslate(ireq.addr, 
+                                                   &tlb_ipaddr, 
+                                                   &icache_pte_info, 
+                                                   &icache_tlb_nline, 
+                                                   &icache_tlb_way, 
+                                                   &icache_tlb_set);
+ 
+            icache_hit_x  = (((vaddr_t)r_icache_vpn_save << PAGE_K_NBITS) == (ireq.addr & ~PAGE_K_MASK)) && r_itlb_translation_valid;
+            icache_hit_p  = (((ireq.addr >> PAGE_M_NBITS) == r_icache_id1_save) && r_icache_ptba_ok); 
+            spc_ipaddr    = ((paddr_t)r_icache_ppn_save << PAGE_K_NBITS) | (paddr_t)(ireq.addr & PAGE_K_MASK);
+            icache_cached = icache_pte_info.c; 
+        }
+
+        if ( !(r_mmu_mode.read() & INS_CACHE_MASK) )   // cache not actived
+        {
+            icache_cached = false;
+        }
+
+        if ( ireq.valid ) 
+        {
+            m_cpt_icache_dir_read += m_icache_ways;
+            m_cpt_icache_data_read += m_icache_ways;
+
+            // icache_hit_c & icache_ins
+            if ( icache_cached )    // using speculative physical address for cached access
+            {
+                icache_hit_c = r_icache.read(spc_ipaddr, &icache_ins);
+            }
+            else                    // using actual physical address for uncached access
+            {
+                icache_hit_c = ( r_icache_buf_unc_valid && (tlb_ipaddr == (paddr_t)r_icache_paddr_save) );
+                icache_ins = r_icache_miss_buf[0];
+            }
+
+            // For instrumentation: is User access ? 
+            r_ireq_isUser_save = (dreq.mode == iss_t::MODE_USER) ? true : false;        
+
+            if ( r_mmu_mode.read() & INS_TLB_MASK ) 
+            {
+                if ( icache_hit_t ) 
+                {
+                    // check access rights
+                    if ( !icache_pte_info.u && (ireq.mode == iss_t::MODE_USER)) 
+                    {
+                        r_icache_error_type = MMU_READ_PRIVILEGE_VIOLATION;  
+                        r_icache_bad_vaddr = ireq.addr;
+                        irsp.valid = true;
+                        irsp.error = true;
+                        irsp.instruction = 0;
+                        break;
+                    }
+                    if ( !icache_pte_info.x ) 
+                    {
+                        r_icache_error_type = MMU_READ_EXEC_VIOLATION;  
+                        r_icache_bad_vaddr = ireq.addr;
+                        irsp.valid = true;
+                        irsp.error = true;
+                        irsp.instruction = 0;
+                        break;
+                    }
+                }
+
+                // update LRU, save ppn, vpn and page type
+                if ( icache_hit_t )
+                {  
+                    icache_tlb.setlru(icache_tlb_way,icache_tlb_set);     
+                    r_icache_ppn_save = tlb_ipaddr >> PAGE_K_NBITS;
+                    r_icache_vpn_save = ireq.addr >> PAGE_K_NBITS;
+                    r_icache_tlb_nline = icache_tlb_nline;
+                    r_itlb_translation_valid = true;
+                }
+                else
+                {
+                    r_itlb_translation_valid = false;
+                }
+
+            } // end if MMU activated
+
+            // compute next state 
+            if ( !icache_hit_t && !icache_hit_p )      // TLB miss
+            {
+                // walk page table  level 1
+                r_icache_paddr_save = (paddr_t)r_mmu_ptpr << (INDEX1_NBITS+2) | (paddr_t)((ireq.addr>>PAGE_M_NBITS)<<2);
+                r_itlb_read_dcache_req = true;
+                r_icache_vaddr_req = ireq.addr;
+                r_icache_fsm = ICACHE_TLB1_READ;
+                m_cpt_ins_tlb_miss++;
+                m_cost_ins_tlb_miss_frz++;
+            }
+            else if ( !icache_hit_t && icache_hit_p )  // TLB Miss with possibility of bypass first level page
+            {
+                // walk page table level 2
+                r_icache_paddr_save = (paddr_t)r_icache_ptba_save | 
+                                      (paddr_t)(((ireq.addr&PTD_ID2_MASK)>>PAGE_K_NBITS) << 3);
+                r_itlb_read_dcache_req = true;
+                r_icache_vaddr_req = ireq.addr;
+                r_itlb_k_read_dcache   = true;
+                r_icache_fsm = ICACHE_TLB2_READ;
+                m_cpt_ins_tlb_miss++;
+                m_cost_ins_tlb_miss_frz++;
+            }
+            else if ( icache_hit_t && !icache_hit_x && icache_cached ) // cached access with an ucorrect speculative physical address
+            {
+                r_icache_paddr_save = tlb_ipaddr;   // save actual physical address for BIS
+                r_icache_vaddr_req = ireq.addr;
+                r_icache_fsm = ICACHE_BIS;
+                //m_cost_ins_miss_frz++;
+            }
+            else    // cached or uncached access with a correct speculative physical address 
+            {        
+                m_cpt_ins_read++; 
+                if ( !icache_hit_c ) 
+                {
+                    if ( icache_cached ) 
+                    {
+                        r_icache_miss_req = true;
+                    	r_icache_paddr_save = spc_ipaddr; 
+                        r_icache_vaddr_req = ireq.addr;
+                        r_icache_fsm = ICACHE_MISS_WAIT;
+                    	m_cpt_ins_miss++;
+                    	m_cost_ins_miss_frz++;
+                    } 
+                    else 
+                    {
+                        r_icache_unc_req = true;
+                        r_icache_buf_unc_valid = false;
+                    	r_icache_paddr_save = tlb_ipaddr; 
+                        r_icache_vaddr_req = ireq.addr;
+                        r_icache_fsm = ICACHE_UNC_WAIT;
+                    } 
+                } 
+                else 
+                {
+                    r_icache_buf_unc_valid = false;
+                    r_icache_fsm = ICACHE_IDLE;
+                }
+                irsp.valid = icache_hit_c;
+                irsp.instruction = icache_ins;
+            } // end if next states
+            
+        } // end if ireq.valid
+        break;
+    }
+    ////////////////
+    case ICACHE_BIS: 
+    {
+        // external cache invalidate request
+        if ( r_tgt_icache_req )
+        {
+            r_icache_fsm = ICACHE_CC_INVAL;
+            r_icache_fsm_save = r_icache_fsm;
+            break;
+        }
+
+        // external tlb invalidate request
+        if ( r_dcache_itlb_inval_req )
+        {
+	    r_itlb_inval_req = true;
+            r_icache_fsm = ICACHE_TLB_CC_INVAL;
+            r_icache_fsm_save = r_icache_fsm;
+            break;
+        }
+      
+        // using page is invalidated 
+        if ( r_icache_inval_tlb_rsp )
+        {
+            r_icache_inval_tlb_rsp = false;
+            r_icache_fsm = ICACHE_IDLE;
+            break;
+        }
+ 
+        data_t	icache_ins = 0;
+        bool	icache_hit_c = false;
+        bool    icache_hit_t = false;
+        paddr_t	tlb_ipaddr = 0;
+
+        icache_hit_t = icache_tlb.translate(ireq.addr, &tlb_ipaddr);
+
+        if ( (tlb_ipaddr == r_icache_paddr_save.read()) && ireq.valid && icache_hit_t )		// unmodified & valid
+        {
+            m_cpt_ins_read++;
+
+            // acces is always cached in this state
+            icache_hit_c = r_icache.read(r_icache_paddr_save, &icache_ins);
+
+            if ( !icache_hit_c )
+            {
+                r_icache_miss_req = true;
+                r_icache_fsm = ICACHE_MISS_WAIT;
+                m_cpt_ins_miss++;
+                m_cost_ins_miss_frz++;
+            } 
+            else
+            {
+                r_icache_fsm = ICACHE_IDLE; 
+            }
+            irsp.valid = icache_hit_c;
+            if (irsp.valid)
+                assert((r_icache_vaddr_req.read() == ireq.addr) &&
+                       "vaddress should not be modified while ICACHE_BIS");
+            irsp.error = false;
+            irsp.instruction = icache_ins;
+        }
+        else	// modified or invalid
+        {
+            irsp.valid = false;
+            irsp.error = false;
+            irsp.instruction = 0;
+            r_icache_fsm = ICACHE_IDLE;
+        }
+        break;
+    }
+    //////////////////////
+    case ICACHE_TLB1_READ:
+    {
+        if ( ireq.valid ) m_cost_ins_tlb_miss_frz++;
+
+        // external cache invalidate request
+        if ( r_tgt_icache_req )
+        {
+            r_icache_fsm = ICACHE_CC_INVAL;
+            r_icache_fsm_save = r_icache_fsm;
+            break;
+        }
+
+        // external tlb invalidate request
+        if ( r_dcache_itlb_inval_req )
+        {
+	    r_itlb_inval_req = true;
+            r_icache_fsm = ICACHE_TLB_CC_INVAL;
+            r_icache_fsm_save = r_icache_fsm;
+            break;
+        }
+
+        if ( !r_itlb_read_dcache_req )
+        {
+            if (r_icache_vaddr_req.read() != ireq.addr || !ireq.valid) 
+            {
+                /* request modified, drop response and restart */
+                r_icache_ptba_ok = false;
+            	if ( r_icache_inval_tlb_rsp )	r_icache_inval_tlb_rsp = false;
+                if ( r_dcache_rsp_itlb_error )	r_dcache_rsp_itlb_error = false;
+                r_icache_fsm = ICACHE_IDLE;
+                break;
+            }
+
+            if ( !r_icache_inval_tlb_rsp ) // TLB miss read response and no invalidation
+            {
+                if ( !r_dcache_rsp_itlb_error ) // vci response ok
+                {  
+                    if (r_itlb_acc_redo_req)
+                    {
+                        r_itlb_acc_redo_req = false;
+                        r_itlb_read_dcache_req = true;
+                        //r_icache_fsm = ICACHE_IDLE;  
+                    }
+            	    else if ( !(r_dcache_rsp_itlb_miss >> PTE_V_SHIFT) ) // unmapped
+            	    {
+                        r_icache_ptba_ok    = false;	
+                        r_icache_error_type = MMU_READ_PT1_UNMAPPED;  
+                        r_icache_bad_vaddr  = r_icache_vaddr_req.read();
+                        r_icache_fsm        = ICACHE_ERROR;
+            	    }
+            	    else if ( (r_dcache_rsp_itlb_miss & PTE_T_MASK ) >> PTE_T_SHIFT ) // PTD
+            	    {
+                        r_icache_ptba_ok       = true;	
+                        r_icache_ptba_save     = (paddr_t)(r_dcache_rsp_itlb_miss & ((1<<(m_paddr_nbits - PAGE_K_NBITS))-1)) << PAGE_K_NBITS; 
+                        r_icache_id1_save      = r_icache_vaddr_req.read() >> PAGE_M_NBITS;
+                        r_icache_paddr_save    = (paddr_t)(r_dcache_rsp_itlb_miss & ((1<<(m_paddr_nbits - PAGE_K_NBITS))-1)) << PAGE_K_NBITS |
+                                                 (paddr_t)(((r_icache_vaddr_req.read() & PTD_ID2_MASK) >> PAGE_K_NBITS) << 3); 
+                        r_itlb_read_dcache_req = true;
+                        r_itlb_k_read_dcache   = true;
+                        r_icache_fsm           = ICACHE_TLB2_READ;
+             	    }	
+            	    else
+            	    {
+                        r_icache_ptba_ok = false;
+            
+            	        if ( (m_srcid_rw >> 4) == ((r_dcache_rsp_itlb_miss & ((1<<(m_paddr_nbits - PAGE_M_NBITS))-1)) >> (m_paddr_nbits - PAGE_M_NBITS -10)) ) // local
+            	        {
+                            if ( (r_dcache_rsp_itlb_miss & PTE_L_MASK ) >> PTE_L_SHIFT ) // L bit is set
+                            {
+                                r_icache_pte_update = r_dcache_rsp_itlb_miss;
+                                r_icache_fsm        = ICACHE_TLB1_UPDT_SEL;
+                            }
+                            else
+                            {
+                                r_icache_pte_update   = r_dcache_rsp_itlb_miss | PTE_L_MASK;
+                                r_itlb_acc_dcache_req = true;
+                                r_icache_fsm          = ICACHE_TLB1_WRITE;
+                                m_cpt_ins_tlb_update_acc++;
+                                m_cost_ins_tlb_update_acc_frz++;
+                            }
+                        }
+            	        else // remotely
+            	        {
+                            if ( (r_dcache_rsp_itlb_miss & PTE_R_MASK ) >> PTE_R_SHIFT ) // R bit is set
+                            {
+                                r_icache_pte_update = r_dcache_rsp_itlb_miss;
+                                r_icache_fsm        = ICACHE_TLB1_UPDT_SEL;
+                            }
+                            else
+                            {
+                                r_icache_pte_update   = r_dcache_rsp_itlb_miss | PTE_R_MASK;
+                                r_itlb_acc_dcache_req = true;
+                                r_icache_fsm          = ICACHE_TLB1_WRITE;
+                                m_cpt_ins_tlb_update_acc++;
+                                m_cost_ins_tlb_update_acc_frz++;
+                            }
+            	        }
+            	    }
+                }
+                else                        // vci response error
+                {  
+                    r_icache_fsm = ICACHE_ERROR;
+                    r_icache_error_type = MMU_READ_PT1_ILLEGAL_ACCESS;    
+                    r_icache_bad_vaddr = r_icache_vaddr_req.read();
+                }
+            }
+            else  // TLB miss read response and invalidation
+            {
+                if ( r_dcache_rsp_itlb_error ) 
+                {
+                    r_icache_inval_tlb_rsp = false;
+                    r_icache_error_type = MMU_READ_PT1_ILLEGAL_ACCESS;    
+                    r_icache_bad_vaddr = r_icache_vaddr_req.read();
+                    r_icache_fsm = ICACHE_ERROR;
+                } 
+                else 
+                {
+	            if ( r_itlb_acc_redo_req ) r_itlb_acc_redo_req = false;
+                    r_icache_inval_tlb_rsp = false;
+                    r_icache_fsm = ICACHE_IDLE;  
+                } 
+            }
+        }
+        break;
+    }
+    ///////////////////////
+    case ICACHE_TLB1_WRITE:  
+    {
+        if ( ireq.valid ) m_cost_ins_tlb_miss_frz++;
+        m_cost_ins_tlb_update_acc_frz++;
+
+        // external cache invalidate request
+        if ( r_tgt_icache_req )
+        {
+            r_icache_fsm = ICACHE_CC_INVAL;
+            r_icache_fsm_save = r_icache_fsm;
+            break;
+        }
+        // external tlb invalidate request
+        if ( r_dcache_itlb_inval_req )
+        {
+            r_itlb_inval_req = true;
+            r_icache_fsm = ICACHE_TLB_CC_INVAL;
+            r_icache_fsm_save = r_icache_fsm;
+            break;
+        }
+
+        if ( !r_itlb_acc_dcache_req ) // TLB access bits write response 
+        {        
+            if ( !r_icache_inval_tlb_rsp ) // TLB access bits write response and no invalidation        
+            { 
+                if ( r_dcache_rsp_itlb_error ) 
+                {
+                    r_icache_error_type = MMU_READ_PT1_ILLEGAL_ACCESS;  
+                    r_icache_bad_vaddr = r_icache_vaddr_req.read();
+                    r_icache_fsm = ICACHE_ERROR;
+                } 
+                else if ( r_itlb_acc_redo_req )
+                {
+                    r_itlb_acc_redo_req = false;
+                    r_icache_fsm = ICACHE_IDLE;    
+                }
+                else  
+                {
+                    r_icache_fsm = ICACHE_TLB1_UPDT_SEL;  
+                }
+            } 
+            else   // TLB ET write response and invalidation     
+            {   
+                if ( r_dcache_rsp_itlb_error ) 
+                {
+                    r_icache_inval_tlb_rsp = false;
+                    r_icache_error_type = MMU_READ_PT1_ILLEGAL_ACCESS;  
+                    r_icache_bad_vaddr = r_icache_vaddr_req.read();
+                    r_icache_fsm = ICACHE_ERROR;
+                } 
+                else if ( r_itlb_acc_redo_req )
+                {
+                    r_itlb_acc_redo_req = false;
+                    r_icache_inval_tlb_rsp = false;
+                    r_icache_fsm = ICACHE_IDLE;    
+                }
+                else  
+                {
+                    r_icache_inval_tlb_rsp = false;
+                    r_icache_fsm = ICACHE_IDLE;    
+                }
+            }
+        }
+        break;
+    }
+    //////////////////////
+    case ICACHE_TLB1_UPDT_SEL:
+    {
+        if ( ireq.valid ) m_cost_ins_tlb_miss_frz++;
+        m_cost_ins_tlb_update_acc_frz++;
+
+        // external cache invalidate request
+        if ( r_tgt_icache_req )
+        {
+            r_icache_fsm = ICACHE_CC_INVAL;
+            r_icache_fsm_save = r_icache_fsm;
+            break;
+        }
+
+        // external tlb invalidate request
+        if ( r_dcache_itlb_inval_req ) 
+        {
+            r_itlb_inval_req = true;
+            r_icache_fsm = ICACHE_TLB_CC_INVAL;
+            r_icache_fsm_save = r_icache_fsm;
+            break;
+        }
+
+        // TLB update and invalidate same PTE
+        if ( r_icache_inval_tlb_rsp )                                 
+        {
+            r_icache_inval_tlb_rsp = false;
+            r_icache_fsm = ICACHE_IDLE;
+            break;
+        }
+
+        if ( r_dcache_itlb_cleanup_req ) break; 
+
+        size_t way = 0;
+        size_t set = 0;
+        paddr_t victim_index = 0;
+        
+        bool cleanup = icache_tlb.select((r_icache_vaddr_req.read()>> PAGE_M_NBITS),&victim_index,&way,&set);
+        r_icache_way = way;
+        r_icache_set = set;
+        if (cleanup)
+        {
+            r_dcache_itlb_cleanup_req = true;
+            r_dcache_itlb_cleanup_line = victim_index;
+            //m_cpt_cc_cleanup_ins++;
+        }
+        r_icache_fsm = ICACHE_TLB1_UPDT;
+        break; 
+    }
+    /////////////////////
+    case ICACHE_TLB1_UPDT:
+    {
+        if ( ireq.valid ) m_cost_ins_tlb_miss_frz++;
+        m_cost_ins_tlb_update_acc_frz++;
+        
+        icache_tlb.update(r_icache_pte_update,r_icache_vaddr_req.read(),r_icache_way.read(),r_icache_set.read(),(r_icache_paddr_save.read() >> (uint32_log2(m_dcache_words)+2)));
+        r_icache_fsm = ICACHE_IDLE;
+        break;
+    }
+    /////////////////////
+    case ICACHE_TLB2_READ:
+    {
+        if ( ireq.valid ) m_cost_ins_tlb_miss_frz++;
+
+        // external cache invalidate request
+        if ( r_tgt_icache_req )
+        {
+            r_icache_fsm = ICACHE_CC_INVAL;
+            r_icache_fsm_save = r_icache_fsm;
+            break;
+        }
+
+        // external tlb invalidate request
+        if ( r_dcache_itlb_inval_req )
+        {
+            r_itlb_inval_req = true;
+            r_icache_fsm = ICACHE_TLB_CC_INVAL;
+            r_icache_fsm_save = r_icache_fsm;
+            break;
+        }
+
+        if ( !r_itlb_read_dcache_req  ) // TLB miss read response
+        { 
+            if (r_icache_vaddr_req.read() != ireq.addr || !ireq.valid) 
+            {
+                /* request modified, drop response and restart */
+                r_icache_ptba_ok = false;
+            	if ( r_icache_inval_tlb_rsp )	r_icache_inval_tlb_rsp = false;
+                if ( r_dcache_rsp_itlb_error )	r_dcache_rsp_itlb_error = false;
+                r_icache_fsm = ICACHE_IDLE;
+                break;
+            }
+            
+            if ( !r_icache_inval_tlb_rsp ) // TLB miss read response 
+            {
+                if ( !r_dcache_rsp_itlb_error ) // VCI response ok        
+                {
+                    if (r_itlb_acc_redo_req)
+                    {
+                        r_itlb_acc_redo_req = false;
+                        r_itlb_read_dcache_req = true;
+                    }
+            	    else if ( !(r_dcache_rsp_itlb_miss >> PTE_V_SHIFT) ) // unmapped
+                    {
+                        r_icache_error_type = MMU_READ_PT2_UNMAPPED;  
+                        r_icache_bad_vaddr  = r_icache_vaddr_req.read();
+                        r_icache_fsm = ICACHE_ERROR;
+            	    }
+            	    else
+            	    {
+            	        if ( (m_srcid_rw >> 4) == ((r_dcache_rsp_itlb_miss & ((1<<(m_paddr_nbits - PAGE_M_NBITS))-1)) >> (m_paddr_nbits - PAGE_M_NBITS -10)) ) // local
+                        {
+                            if ( (r_dcache_rsp_itlb_miss & PTE_L_MASK ) >> PTE_L_SHIFT ) // L bit is set
+                            {
+                                r_icache_fsm        = ICACHE_TLB2_UPDT_SEL;
+                                r_icache_pte_update = r_dcache_rsp_itlb_miss;
+                            }
+                            else
+                            {
+                                r_icache_pte_update   = r_dcache_rsp_itlb_miss | PTE_L_MASK;
+                                r_itlb_acc_dcache_req = true;
+                                r_icache_fsm          = ICACHE_TLB2_WRITE;
+                                m_cpt_ins_tlb_update_acc++;
+                                m_cost_ins_tlb_update_acc_frz++;
+                            }
+                        }
+            	    	else // remotely
+                        {
+                            if ( (r_dcache_rsp_itlb_miss & PTE_R_MASK ) >> PTE_R_SHIFT ) // R bit is set
+                            {
+                                r_icache_fsm        = ICACHE_TLB2_UPDT_SEL;
+                                r_icache_pte_update = r_dcache_rsp_itlb_miss;
+                            }
+                            else
+                            {
+                                r_icache_pte_update   = r_dcache_rsp_itlb_miss | PTE_R_MASK;
+                                r_itlb_acc_dcache_req = true;
+                                r_icache_fsm          = ICACHE_TLB2_WRITE;
+                                m_cpt_ins_tlb_update_acc++;
+                                m_cost_ins_tlb_update_acc_frz++;
+                            }
+            	        }
+            	    }
+                }
+                else                            // VCI response error        
+                {
+                    r_icache_error_type = MMU_READ_PT2_ILLEGAL_ACCESS;
+                    r_icache_bad_vaddr = r_icache_vaddr_req.read();
+                    r_icache_fsm = ICACHE_ERROR;
+                }
+            }
+            else  // TLB miss read response and invalidation
+            {
+                if ( r_dcache_rsp_itlb_error ) 
+                {
+                    r_icache_inval_tlb_rsp = false;
+                    r_icache_error_type = MMU_READ_PT2_ILLEGAL_ACCESS;    
+                    r_icache_bad_vaddr = r_icache_vaddr_req.read();
+                    r_icache_fsm = ICACHE_ERROR;
+                } 
+                else 
+                {
+                    if ( r_itlb_acc_redo_req ) r_itlb_acc_redo_req = false;
+                    r_icache_inval_tlb_rsp = false;
+                    r_icache_fsm = ICACHE_IDLE;  
+                } 
+            }
+	}
+        break;
+    }
+    /////////////////////////
+    case ICACHE_TLB2_WRITE:
+    {  
+        if ( ireq.valid ) m_cost_ins_tlb_miss_frz++;
+        m_cost_ins_tlb_update_acc_frz++;
+
+        // external cache invalidate request
+        if ( r_tgt_icache_req )
+        {
+            r_icache_fsm = ICACHE_CC_INVAL;
+            r_icache_fsm_save = r_icache_fsm;
+            break;
+        }
+        // external tlb invalidate request
+        if ( r_dcache_itlb_inval_req )
+        {
+	    r_itlb_inval_req = true;
+            r_icache_fsm = ICACHE_TLB_CC_INVAL;
+            r_icache_fsm_save = r_icache_fsm;
+            break;
+        }
+
+        if ( !r_itlb_acc_dcache_req ) // TLB access bits write response          
+        {
+            if ( !r_icache_inval_tlb_rsp ) // TLB access bits write response          
+            {
+                if ( r_dcache_rsp_itlb_error )             
+                {
+                    r_icache_error_type = MMU_READ_PT2_ILLEGAL_ACCESS;  
+                    r_icache_bad_vaddr = r_icache_vaddr_req.read();
+                    r_icache_fsm = ICACHE_ERROR;
+                } 
+                else if ( r_itlb_acc_redo_req )
+                {
+                    r_itlb_acc_redo_req = false;
+                    r_icache_fsm = ICACHE_IDLE;    
+                }
+                else  
+                {
+                    r_icache_fsm = ICACHE_TLB2_UPDT_SEL;  
+                }
+            }
+            else // TLB ET write response and invalidation     
+            {   
+                if ( r_dcache_rsp_itlb_error ) 
+                {
+                    r_icache_inval_tlb_rsp = false;
+                    r_icache_error_type = MMU_READ_PT2_ILLEGAL_ACCESS;  
+                    r_icache_bad_vaddr = r_icache_vaddr_req.read();
+                    r_icache_fsm = ICACHE_ERROR;
+                } 
+                else if ( r_itlb_acc_redo_req )
+                {
+                    r_itlb_acc_redo_req = false;
+                    r_icache_inval_tlb_rsp = false;
+                    r_icache_fsm = ICACHE_IDLE;    
+                }
+                else  
+                {
+                    r_icache_inval_tlb_rsp = false;
+                    r_icache_fsm = ICACHE_IDLE;    
+                }
+            }
+        }
+        break;
+    }
+    //////////////////////////
+    case ICACHE_TLB2_UPDT_SEL: 
+    {
+        if ( ireq.valid ) m_cost_ins_tlb_miss_frz++;
+        m_cost_ins_tlb_update_acc_frz++;
+
+        // external cache invalidate request
+        if ( r_tgt_icache_req )
+        {
+            r_icache_fsm = ICACHE_CC_INVAL;
+            r_icache_fsm_save = r_icache_fsm;
+            break;
+        }
+
+        // external tlb invalidate request
+        if ( r_dcache_itlb_inval_req ) 
+        {
+            r_itlb_inval_req = true;
+            r_icache_fsm = ICACHE_TLB_CC_INVAL;
+            r_icache_fsm_save = r_icache_fsm;
+            break;
+        }
+
+        // TLB update and invalidate same PTE
+        if ( r_icache_inval_tlb_rsp )                            
+        {
+            r_icache_inval_tlb_rsp = false;
+            r_icache_fsm = ICACHE_IDLE;
+            break;
+        }
+
+        if ( r_dcache_itlb_cleanup_req ) break; 
+
+        size_t way = 0;
+        size_t set = 0;
+        paddr_t victim_index = 0;
+        
+        bool cleanup = icache_tlb.select((r_icache_vaddr_req.read()>> PAGE_K_NBITS),&victim_index,&way,&set);
+        r_icache_way = way;
+        r_icache_set = set;
+        if (cleanup)
+        {
+            r_dcache_itlb_cleanup_req = true;
+            r_dcache_itlb_cleanup_line = victim_index;
+            //m_cpt_cc_cleanup_ins++;
+        }
+        r_icache_fsm = ICACHE_TLB2_UPDT;
+        break;
+    }
+    /////////////////////
+    case ICACHE_TLB2_UPDT: 
+    {
+        if ( ireq.valid ) m_cost_ins_tlb_miss_frz++;
+        m_cost_ins_tlb_update_acc_frz++;
+
+        icache_tlb.update(r_icache_pte_update,r_dcache_rsp_itlb_ppn,r_icache_vaddr_req.read(),r_icache_way.read(),r_icache_set.read(),(r_icache_paddr_save.read() >> (uint32_log2(m_dcache_words)+2)));
+        r_icache_fsm = ICACHE_IDLE;
+        break;
+    }
+    /////////////////////////////
+    case ICACHE_SW_FLUSH:
+    {
+        size_t way = r_icache_way;
+        size_t set = r_icache_set;
+        bool clean = false;
+
+        // 4K page size TLB flush leads to cleanup req to data cache 
+        if ( !r_dcache_itlb_cleanup_req )    // last cleanup finish
+        {
+            paddr_t victim_index = 0;
+            for ( ; way < m_itlb_ways; way++)
+            {
+                for ( ; set < m_itlb_sets; set++)
+                {
+                    if(icache_tlb.checkcleanup(way, set, &victim_index))
+                    {
+                        clean = true;
+                        r_dcache_itlb_cleanup_req = true;
+                        r_dcache_itlb_cleanup_line = victim_index;
+                        r_icache_way = way + ((set+1)/m_itlb_sets);
+                        r_icache_set = (set+1) % m_itlb_sets;
+                        break;
+                    }
+                }
+                if (clean) break;
+                set = 0;
+            }
+
+            if (way == m_itlb_ways)
+            {
+                r_dcache_xtn_req = false;
+                r_itlb_translation_valid = false;
+                r_icache_ptba_ok = false;
+                r_icache_fsm = ICACHE_IDLE;
+                break;
+            }
+        }
+        break;
+    }
+    /////////////////////
+    case ICACHE_TLB_FLUSH:
+    {   
+        // data cache flush leads to ins tlb flush, flush all tlb entry 
+        icache_tlb.flush(true);    // global entries are invalidated
+        r_dcache_xtn_req = false;
+        r_itlb_translation_valid = false;
+        r_icache_ptba_ok = false;
+        r_icache_fsm = ICACHE_IDLE;
+        break;
+    }
+    ////////////////////////
+    case ICACHE_CACHE_FLUSH:
+    {
+        // external cache invalidate request
+        if ( r_tgt_icache_req )
+        {
+            r_icache_fsm = ICACHE_CC_INVAL;
+            r_icache_fsm_save = r_icache_fsm;
+            break;
+        }
+
+        size_t way = r_icache_way;
+        size_t set = r_icache_set;
+        bool clean = false;
+
+        // cache flush and send cleanup to external
+        if ( !r_icache_cleanup_req )
+        {
+            paddr_t victim_index = 0;
+            for ( ; way < m_icache_ways; way++ )
+            {    
+                for ( ; set < m_icache_sets; set++ )
+                {    
+                    if ( r_icache.flush(way, set, &victim_index) )
+                    {
+                        clean = true;
+                        r_icache_cleanup_req = true;
+                        r_icache_cleanup_line = victim_index;
+                        m_cpt_cc_cleanup_ins++;
+                        r_icache_way = way + ((set+1)/m_icache_sets);
+                        r_icache_set = (set+1) % m_icache_sets;
+                        break;
+                    }
+                }
+                if (clean) break;
+                set = 0;
+            }
+            if (way == m_icache_ways)
+            {
+                r_dcache_xtn_req = false;
+                r_icache_fsm = ICACHE_IDLE;
+                break;
+            }
+        }
+        break;
+    }
+    /////////////////////
+    case ICACHE_TLB_INVAL:  
+    {
+        paddr_t victim_index = 0;
+
+        if ( !r_dcache_itlb_cleanup_req )
+        {
+            bool dcache_itlb_cleanup_req = icache_tlb.inval(r_dcache_wdata_save, &victim_index);
+            r_dcache_itlb_cleanup_req = dcache_itlb_cleanup_req;
+            r_dcache_itlb_cleanup_line = victim_index;
+            //if (dcache_itlb_cleanup_req) m_cpt_cc_cleanup_ins++;
+            r_dcache_xtn_req = false;
+            r_itlb_translation_valid = false;
+            r_icache_ptba_ok = false;
+            r_icache_fsm = ICACHE_IDLE;
+        }
+        break;
+    }
+    ////////////////////////
+    case ICACHE_CACHE_INVAL:
+    {	
+        // external cache invalidate request
+        if ( r_tgt_icache_req )
+        {
+            r_icache_fsm = ICACHE_CC_INVAL;
+            r_icache_fsm_save = r_icache_fsm;
+            break;
+        }
+
+        paddr_t ipaddr = 0;                     
+        bool    icache_hit_t = false;
+
+        if ( !r_icache_cleanup_req )
+        {    
+            if ( r_mmu_mode.read() & INS_TLB_MASK ) 
+            {
+                icache_hit_t = icache_tlb.translate(r_dcache_wdata_save, &ipaddr); 
+            } 
+            else 
+            {
+                ipaddr = (paddr_t)r_dcache_wdata_save;
+                icache_hit_t = true;
+            }
+            if ( icache_hit_t )
+            {
+                // invalidate and cleanup if necessary
+                bool icache_cleanup_req = r_icache.inval(ipaddr);
+                r_icache_cleanup_req = icache_cleanup_req;
+                r_icache_cleanup_line = ipaddr >> (uint32_log2(m_icache_words) + 2);  
+                if (icache_cleanup_req) m_cpt_cc_cleanup_ins++;	
+            }
+            r_dcache_xtn_req = false; 
+            r_icache_fsm = ICACHE_IDLE;
+        }
+        break;
+    }
+    ////////////////////////
+    case ICACHE_CACHE_INVAL_PA:
+    {
+        // external cache invalidate request
+        if ( r_tgt_icache_req )
+        {
+            r_icache_fsm = ICACHE_CC_INVAL;
+            r_icache_fsm_save = r_icache_fsm;
+            break;
+        }
+	
+        paddr_t ipaddr = (paddr_t)r_mmu_word_hi.read() << 32 | r_mmu_word_lo.read();
+
+        if ( !r_icache_cleanup_req )
+        {    
+            // invalidate and cleanup if necessary
+            bool icache_cleanup_req = r_icache.inval(ipaddr);
+            r_icache_cleanup_req = icache_cleanup_req;
+            r_icache_cleanup_line = ipaddr >> (uint32_log2(m_icache_words) + 2);  
+            if (icache_cleanup_req) m_cpt_cc_cleanup_ins++; 
+            r_dcache_xtn_req = false; 
+            r_icache_fsm = ICACHE_IDLE;
+        }
+        break;
+    }
+    ///////////////////////
+    case ICACHE_MISS_WAIT:
+    {
+        m_cost_ins_miss_frz++;
+
+        // external cache invalidate request
+        if ( r_tgt_icache_req )     
+        {
+            r_icache_fsm = ICACHE_CC_INVAL;
+            r_icache_fsm_save = r_icache_fsm;
+            break;
+        }
+
+        // external tlb invalidate request
+        if ( r_dcache_itlb_inval_req )
+        {
+            r_itlb_inval_req = true;
+            r_icache_fsm = ICACHE_TLB_CC_INVAL;
+            r_icache_fsm_save = r_icache_fsm;
+            break;
+        }
+       
+        if ( !r_icache_miss_req )
+        {
+            if ( r_vci_rsp_ins_error ) 
+            {
+                r_icache_error_type = MMU_READ_DATA_ILLEGAL_ACCESS; 
+                r_icache_bad_vaddr = ireq.addr;
+                r_icache_fsm = ICACHE_ERROR;
+
+            	if ( r_icache_inval_tlb_rsp ) r_icache_inval_tlb_rsp = false;
+            	if ( r_icache_inval_rsp ) r_icache_inval_rsp = false;
+                break;
+            }
+
+            if ( r_icache_inval_tlb_rsp ) // Miss read response and tlb invalidation
+            {
+                if ( r_icache_cleanup_req ) break;
+                r_icache_cleanup_req = true;
+                r_icache_cleanup_line = r_icache_paddr_save.read() >> (uint32_log2(m_icache_words) + 2); 
+                m_cpt_cc_cleanup_ins++;	
+                r_icache_fsm = ICACHE_IDLE;
+                r_icache_inval_tlb_rsp = false;
+                if ( r_icache_inval_rsp ) r_icache_inval_rsp = false;
+                break;
+            }
+	
+            if ( r_icache_inval_rsp ) // Miss read response and tlb invalidation
+            {
+                if ( r_icache_cleanup_req ) break;
+                r_icache_cleanup_req = true;
+                r_icache_cleanup_line = r_icache_paddr_save.read() >> (uint32_log2(m_icache_words) + 2);  
+                m_cpt_cc_cleanup_ins++;
+                r_icache_fsm = ICACHE_IDLE;
+                r_icache_inval_rsp = false;
+                break;
+            }
+            r_icache_fsm = ICACHE_MISS_UPDT;  
+        }	
+        break;
+    }
+    ////////////////////
+    case ICACHE_UNC_WAIT:
+    {
+        // external cache invalidate request
+        if ( r_tgt_icache_req ) 
+        {
+            r_icache_fsm = ICACHE_CC_INVAL;
+            r_icache_fsm_save = r_icache_fsm;
+            break;
+        }
+
+        // external tlb invalidate request
+        if ( r_dcache_itlb_inval_req )
+        {
+            r_itlb_inval_req = true;
+            r_icache_fsm = ICACHE_TLB_CC_INVAL;
+            r_icache_fsm_save = r_icache_fsm;
+            break;
+        }
+
+        if ( !r_icache_unc_req )
+        {
+            if ( r_vci_rsp_ins_error ) 
+            {
+                r_icache_error_type = MMU_READ_DATA_ILLEGAL_ACCESS;    
+                r_icache_bad_vaddr = ireq.addr;
+                r_icache_fsm = ICACHE_ERROR;
+
+            	if ( r_icache_inval_tlb_rsp ) r_icache_inval_tlb_rsp = false;
+                break;
+            }
+
+            if ( r_icache_inval_tlb_rsp ) // Miss read response and tlb invalidation
+            {
+                r_icache_inval_tlb_rsp = false;
+                r_icache_fsm = ICACHE_IDLE;
+                break;
+            }
+
+            // Miss read response and no invalidation
+            r_icache_buf_unc_valid = true;
+            r_icache_fsm = ICACHE_IDLE;
+        }	
+        break;
+    }
+    //////////////////////
+    case ICACHE_MISS_UPDT:
+    {
+        m_cost_ins_miss_frz++;
+
+        // external cache invalidate request
+        if ( r_tgt_icache_req )   
+        {
+            r_icache_fsm = ICACHE_CC_INVAL;
+            r_icache_fsm_save = r_icache_fsm;
+            break;
+        }
+
+        // external tlb invalidate request
+        if ( r_dcache_itlb_inval_req )
+        {
+            r_itlb_inval_req = true;
+            r_icache_fsm = ICACHE_TLB_CC_INVAL;
+            r_icache_fsm_save = r_icache_fsm;
+            break;
+        }
+
+        if ( r_icache_inval_tlb_rsp ) // tlb invalidation
+        {
+            if ( r_icache_cleanup_req ) break;
+            r_icache_cleanup_req = true;
+            r_icache_cleanup_line = r_icache_paddr_save.read() >> (uint32_log2(m_icache_words) + 2); 
+            m_cpt_cc_cleanup_ins++; 
+            r_icache_inval_tlb_rsp = false;
+            if ( r_icache_inval_rsp ) r_icache_inval_rsp = false;
+            r_icache_fsm = ICACHE_IDLE;
+            break;
+        }
+
+        if ( !r_icache_cleanup_req ) // Miss update and no invalidation
+        {
+            if ( r_icache_inval_rsp ) // invalidation
+            {
+                r_icache_cleanup_req = true;
+                r_icache_cleanup_line = r_icache_paddr_save.read() >> (uint32_log2(m_icache_words) + 2); 
+                m_cpt_cc_cleanup_ins++;	
+                r_icache_fsm = ICACHE_IDLE;
+                r_icache_inval_rsp = false;
+            } 
+	    else
+	    {
+                data_t* buf = r_icache_miss_buf;
+                paddr_t  victim_index = 0;
+                m_cpt_icache_dir_write++;
+                m_cpt_icache_data_write++;
+
+                bool icache_cleanup_req = r_icache.update(r_icache_paddr_save.read(), buf, &victim_index);
+                r_icache_cleanup_req = icache_cleanup_req;
+                r_icache_cleanup_line = victim_index;                        
+                if (icache_cleanup_req) m_cpt_cc_cleanup_ins++;
+                r_icache_fsm = ICACHE_IDLE;
+	    }
+        }
+        break;
+    }
+    ///////////////////
+    case ICACHE_ERROR:
+    {
+        r_vci_rsp_ins_error = false;
+        r_dcache_rsp_itlb_error = false;
+        irsp.valid = true;
+        irsp.error = true;
+        irsp.instruction = 0; 
+        r_icache_fsm = ICACHE_IDLE;
+        break;
+    }
+    /////////////////////
+    case ICACHE_CC_INVAL:  
+    {                       
+        m_cpt_icache_dir_read += m_icache_ways;
+        /* activity counter */
+        if ( (( r_icache_fsm_save == ICACHE_BIS ) ||( r_icache_fsm_save == ICACHE_MISS_WAIT ) || ( r_icache_fsm_save == ICACHE_MISS_UPDT ) ) && ( ireq.valid ) )        
+        {
+            m_cost_ins_miss_frz++;
+        }
+        if( (( r_icache_fsm_save == ICACHE_TLB1_READ )     || ( r_icache_fsm_save == ICACHE_TLB2_READ )      ||
+             ( r_icache_fsm_save == ICACHE_TLB1_WRITE )    || ( r_icache_fsm_save == ICACHE_TLB2_WRITE )     ||
+             ( r_icache_fsm_save == ICACHE_TLB1_UPDT_SEL ) || ( r_icache_fsm_save == ICACHE_TLB2_UPDT_SEL )) && (ireq.valid) )
+        {
+            m_cost_ins_tlb_miss_frz++;
+        }
+
+        // invalidate cache
+        if( (( r_icache_fsm_save == ICACHE_MISS_WAIT ) || ( r_icache_fsm_save == ICACHE_MISS_UPDT ) /*|| 
+             ( r_icache_fsm_save == ICACHE_UNC_WAIT )*/ ) && 
+            ((r_icache_paddr_save.read() & ~((m_icache_words<<2)-1)) == (r_tgt_addr.read() & ~((m_icache_words<<2)-1))) ) 
+        {
+            r_icache_inval_rsp = true;
+            r_tgt_icache_rsp = false;
+        } 
+        else 
+        {
+            r_tgt_icache_rsp = r_icache.inval(r_tgt_addr.read());
+        }
+        r_tgt_icache_req = false;
+        r_icache_fsm = r_icache_fsm_save;
+        break;
+    }
+    /////////////////////////
+    case ICACHE_TLB_CC_INVAL:
+    {
+        /* activity counter */
+        if ( (( r_icache_fsm_save == ICACHE_BIS ) ||( r_icache_fsm_save == ICACHE_MISS_WAIT ) || ( r_icache_fsm_save == ICACHE_MISS_UPDT ) ) && ( ireq.valid ) )        
+        {
+            m_cost_ins_miss_frz++;
+        }
+        if( (( r_icache_fsm_save == ICACHE_TLB1_READ )     || ( r_icache_fsm_save == ICACHE_TLB2_READ )      ||
+             ( r_icache_fsm_save == ICACHE_TLB1_WRITE )    || ( r_icache_fsm_save == ICACHE_TLB2_WRITE )     ||
+             ( r_icache_fsm_save == ICACHE_TLB1_UPDT_SEL ) || ( r_icache_fsm_save == ICACHE_TLB2_UPDT_SEL )) && (ireq.valid) )
+        {
+            m_cost_ins_tlb_miss_frz++;
+        }
+
+        if ( r_itlb_inval_req ) break;
+        // invalidate cache
+        if( (( r_icache_fsm_save == ICACHE_TLB1_READ )     || ( r_icache_fsm_save == ICACHE_TLB2_READ )  ||
+             ( r_icache_fsm_save == ICACHE_TLB1_WRITE )    || ( r_icache_fsm_save == ICACHE_TLB2_WRITE ) ||
+             ( r_icache_fsm_save == ICACHE_TLB1_UPDT_SEL ) || ( r_icache_fsm_save == ICACHE_TLB2_UPDT_SEL )) && 
+            (((r_icache_paddr_save.read() & ~((m_icache_words<<2)-1)) >> (uint32_log2(m_icache_words) + 2) ) == r_dcache_itlb_inval_line.read()) ) 
+        {
+            r_icache_inval_tlb_rsp = true;
+        } 
+        else if (((r_icache_fsm_save == ICACHE_BIS)||(r_icache_fsm_save == ICACHE_MISS_WAIT) ||
+               /* (r_icache_fsm_save == ICACHE_UNC_WAIT)||*/(r_icache_fsm_save == ICACHE_MISS_UPDT)) && 
+                (r_icache_tlb_nline.read() == r_dcache_itlb_inval_line.read()))
+        {
+            r_icache_inval_tlb_rsp = true;
+        }
+        r_dcache_itlb_inval_req = false;
+        r_itlb_translation_valid = false;
+        r_icache_ptba_ok = false;
+        r_icache_fsm = r_icache_fsm_save;
+        break;
+    }
+    } // end switch r_icache_fsm
+
+#ifdef SOCLIB_MODULE_DEBUG
+    std::cout << name() << " Instruction Response: " << irsp << std::endl;
+#endif
+
+    ////////////////////////////////////////////////////////////////////////////////////
+    //      INVAL ITLB CHECK FSM 
+    ////////////////////////////////////////////////////////////////////////////////////////
+    switch(r_inval_itlb_fsm) {
+    /////////////////////
+    case INVAL_ITLB_IDLE:
+    {
+        if ( r_itlb_inval_req )
+        {
+            r_ccinval_itlb_way = 0; 
+            r_ccinval_itlb_set = 0;
+            r_inval_itlb_fsm = INVAL_ITLB_CHECK;   
+            m_cost_ins_tlb_inval_frz++; 
+        }   
+        break;
+    }
+    ////////////////////////////
+    case INVAL_ITLB_CHECK:
+    {
+        m_cost_ins_tlb_inval_frz++; 
+
+        size_t way = r_ccinval_itlb_way; 
+        size_t set = r_ccinval_itlb_set;
+        bool end = false;        
+        bool tlb_hit = icache_tlb.cccheck(r_dcache_itlb_inval_line.read(), way, set, &way, &set, &end); 
+    
+        if ( tlb_hit )
+        {
+            r_ccinval_itlb_way = way; 
+            r_ccinval_itlb_set = set;
+            r_itlb_cc_check_end = end;
+            r_inval_itlb_fsm = INVAL_ITLB_INVAL; 
+            m_cpt_ins_tlb_inval++;   
+        }        
+        else
+        {
+            r_inval_itlb_fsm = INVAL_ITLB_CLEAR;    
+        }
+        break;
+    }
+    /////////////////////////
+    case INVAL_ITLB_INVAL:
+    {
+        m_cost_ins_tlb_inval_frz++;
+ 
+        icache_tlb.ccinval(r_ccinval_itlb_way, r_ccinval_itlb_set);
+
+        if ( !r_itlb_cc_check_end )
+        {
+            r_inval_itlb_fsm = INVAL_ITLB_CHECK; 
+        }
+        else
+        {
+            r_inval_itlb_fsm = INVAL_ITLB_CLEAR;    
+        }
+        break;
+    }
+    ////////////////////
+    case INVAL_ITLB_CLEAR:
+    {
+        r_itlb_inval_req = false;
+        r_itlb_cc_check_end = false;
+        r_ccinval_itlb_way = 0; 
+        r_ccinval_itlb_set = 0; 
+        r_inval_itlb_fsm = INVAL_ITLB_IDLE;    
+        m_cost_ins_tlb_inval_frz++; 
+        break;
+    }
+    } // end switch r_inval_itlb_fsm
+
+    ////////////////////////////////////////////////////////////////////////////////////
+    //      DCACHE FSM 
+    //
+    // Both the Cacheability Table, and the MMU cached bit are used to define
+    // the cacheability.
+    // 
+    // There is 14 mutually exclusive conditions to exit the IDLE state.
+    // Seven configurations corresponding to an XTN request from processor:
+    // - Context switch => CTXT_SWITCH state
+    // - Flush dcache => DCACHE_FLUSH state 
+    // - Flush icache => ICACHE_FLUSH state 
+    // - Invalidate a dtlb entry => DTLB_INVAL state
+    // - Invalidate a itlb entry => ITLB_INVAL state
+    // - Invalidate a dcache line => DCACHE_INVAL state
+    // - Invalidate a icache line => ICACHE_INVAL state
+    // Seven configurations corresponding to various read miss or write requests: 
+    // - TLB miss(in case hit_p miss) => TLB1_READ state
+    // - TLB miss(in case hit_p hit) => TLB2_READ state
+    // - Hit in TLB but VPN changed => BIS state
+    // - Cached read miss => MISS_REQ state
+    // - Uncache read miss => UNC_REQ state
+    // - Write hit => WRITE_UPDT state
+    // - Write miss => WRITE_REQ
+    //
+    // The r_vci_rsp_data_error flip-flop is set by the VCI_RSP controller and reset 
+    // by DCACHE-FSM when its state is in DCACHE_ERROR. 
+    //--------------------------------------------------------------------- 
+    // Data TLB: 
+    //  
+    // - int        ET          (00: unmapped; 01: unused or PTD)
+    //                          (10: PTE new;  11: PTE old      )
+    // - bool       cachable    (cached bit)
+    // - bool       writable    (writable bit) 
+    // - bool       executable  (** not used alwayse false)
+    // - bool       user        (access in user mode allowed)
+    // - bool       global      (PTE not invalidated by a TLB flush)
+    // - bool       dirty       (page has been modified) 
+    // - uint32_t   vpn         (virtual page number)
+    // - uint32_t   ppn         (physical page number)
+    ////////////////////////////////////////////////////////////////////////////////////////
+
+    switch (r_dcache_fsm) {
+    //////////////////////
+    case DCACHE_WRITE_REQ:
+    {
+        // external cache invalidate request
+        if ( r_tgt_dcache_req ) 
+        {
+            r_dcache_fsm = DCACHE_CC_CHECK;
+            r_dcache_fsm_save = r_dcache_fsm;
+            break;
+        }
+
+        // try to post the write request in the write buffer
+        if ( !r_dcache_write_req )     // no previous write transaction     
+        {
+            if ( r_wbuf.wok(r_dcache_paddr_save) )   // write request in the same cache line 
+            {    
+                r_wbuf.write(r_dcache_paddr_save.read(), r_dcache_be_save.read(), r_dcache_wdata_save);
+                // closing the write packet if uncached
+                if ( !r_dcache_cached_save )
+                { 
+                    r_dcache_write_req = true;
+                }
+            } 
+            else 
+            {    // close the write packet if write request not in the same cache line
+                r_dcache_write_req = true;
+                m_cost_write_frz++;
+                break;  //  posting not possible : stay in DCACHE_WRITEREQ state
+            }
+        } 
+        else     //  previous write transaction not completed
+        {
+            m_cost_write_frz++;
+            break;  //  posting not possible : stay in DCACHE_WRITEREQ state
+        }
+
+        // close the write packet if the next processor request is not a write 
+        if ( !dreq.valid || (dreq.type != iss_t::DATA_WRITE)) 
+        {
+            r_dcache_write_req = true;
+        }
+        
+        // The next state and the processor request parameters are computed 
+        // as in the DCACHE_IDLE state (see below ...)
+    }
+    /////////////////
+    case DCACHE_IDLE:
+    {
+        // external cache invalidate request
+        if ( r_tgt_dcache_req )   
+        {
+            r_dcache_fsm = DCACHE_CC_CHECK;
+            r_dcache_fsm_save = DCACHE_IDLE;
+            break;
+        }        
+
+        // ins tlb cleanup
+        if ( r_dcache_itlb_cleanup_req )
+        {
+            r_dcache_fsm = DCACHE_ITLB_CLEANUP;
+            break;
+        }    
+        // ins tlb miss
+    	if ( r_itlb_read_dcache_req )
+    	{
+            if ( dreq.valid ) m_cost_ins_tlb_occup_cache_frz++;		
+            data_t rsp_itlb_miss;
+            data_t rsp_itlb_ppn;
+
+    	    bool itlb_hit_dcache = r_dcache.read(r_icache_paddr_save, &rsp_itlb_miss);
+	    if ( r_itlb_k_read_dcache && itlb_hit_dcache )
+	    {	
+            r_itlb_k_read_dcache = false;
+	        bool itlb_hit_ppn = r_dcache.read(r_icache_paddr_save.read()+4, &rsp_itlb_ppn);
+            assert(itlb_hit_ppn && "Address of pte[64-32] and pte[31-0] should be successive");
+	    }
+
+        m_cpt_dcache_data_read += m_dcache_ways;
+        m_cpt_dcache_dir_read += m_dcache_ways;
+        
+        if ( itlb_hit_dcache )  // ins TLB request hits in data cache 
+    	{
+            if (!((rsp_itlb_miss & PTE_T_MASK ) >> PTE_T_SHIFT)) m_cpt_ins_tlb_hit_dcache++;		    
+            r_dcache_rsp_itlb_miss = rsp_itlb_miss; 
+            r_dcache_rsp_itlb_ppn = rsp_itlb_ppn; 
+            r_itlb_read_dcache_req = false;
+            r_dcache_fsm = DCACHE_IDLE;
+                
+            // set TLB bit if it's a PTE
+            if ( !((rsp_itlb_miss & PTE_T_MASK ) >> PTE_T_SHIFT) )
+            {
+                bool set_hit = r_dcache.setinbit(r_icache_paddr_save, r_dcache_in_itlb, true);
+                assert(set_hit && "D$ IDLE ITLB set hit error");  
+            }
+        }
+        else                    // ins TLB request miss in data cache
+    	{
+            r_dcache_itlb_read_req = true;
+            r_dcache_fsm = DCACHE_ITLB_READ;
+        }
+    	}
+    	else if ( r_itlb_acc_dcache_req ) // ins tlb write access bit
+    	{
+            if ( dreq.valid ) m_cost_ins_tlb_occup_cache_frz++;
+            
+            data_t rsp_itlb_miss;
+    	    bool itlb_hit_dcache = r_dcache.read(r_icache_paddr_save, &rsp_itlb_miss);
+            if ( itlb_hit_dcache )
+            {
+                r_dcache_itlb_ll_acc_req = true;
+                r_dcache_fsm = DCACHE_ITLB_LL_WAIT;	    	
+                m_cpt_dcache_data_write++;	    
+            }
+            else
+            {
+                r_itlb_acc_dcache_req = false;
+                r_itlb_acc_redo_req = true;
+                r_dcache_fsm = DCACHE_IDLE;
+            }    
+    	}
+        else if (dreq.valid) 
+        {
+            pte_info_t  dcache_pte_info;
+            int         xtn_opcod        = (int)dreq.addr/4;
+            paddr_t     tlb_dpaddr       = 0;        // physical address obtained from TLB
+            paddr_t     spc_dpaddr       = 0;        // physical adress obtained from PPN_save (speculative)
+            bool        dcache_hit_t     = false;    // hit on 4Kilo TLB
+            bool        dcache_hit_x     = false;    // VPN unmodified (can use spc_dpaddr)
+            bool        dcache_hit_p     = false;    // PTP unmodified (can skip first level page table walk)
+            bool        dcache_hit_c     = false;    // Cache hit
+            bool        dcache_cached    = false;    // cacheable access (read or write)
+            size_t      dcache_tlb_way   = 0;        // selected way (in case of cache hit)
+            size_t      dcache_tlb_set   = 0;        // selected set (Y field in address)
+            data_t      dcache_rdata     = 0;        // read data
+            paddr_t     dcache_tlb_nline = 0;        // TLB NLINE 
+
+            m_cpt_dcache_data_read += m_dcache_ways;
+            m_cpt_dcache_dir_read += m_dcache_ways;
+
+            // Decoding READ XTN requests from processor
+            // They are executed in this DCACHE_IDLE state
+
+            if (dreq.type == iss_t::XTN_READ) 
+            {
+                switch(xtn_opcod) {
+                case iss_t::XTN_INS_ERROR_TYPE:
+                    drsp.rdata = (uint32_t)r_icache_error_type;
+                    r_icache_error_type = MMU_NONE;
+                    drsp.valid = true;
+                    drsp.error = false;
+                    break;
+                case iss_t::XTN_DATA_ERROR_TYPE:
+                    drsp.rdata = (uint32_t)r_dcache_error_type;
+                    r_dcache_error_type = MMU_NONE;
+                    drsp.valid = true;
+                    drsp.error = false;
+                    break;
+                case iss_t::XTN_INS_BAD_VADDR:
+                    drsp.rdata = (uint32_t)r_icache_bad_vaddr;       
+                    drsp.valid = true;
+                    drsp.error = false;
+                    break;
+                case iss_t::XTN_DATA_BAD_VADDR:
+                    drsp.rdata = (uint32_t)r_dcache_bad_vaddr;        
+                    drsp.valid = true;
+                    drsp.error = false;
+                    break;
+                case iss_t::XTN_PTPR:
+                    drsp.rdata = (uint32_t)r_mmu_ptpr;
+                    drsp.valid = true;
+                    drsp.error = false;
+                    break;
+                case iss_t::XTN_TLB_MODE:
+                    drsp.rdata = (uint32_t)r_mmu_mode;
+                    drsp.valid = true;
+                    drsp.error = false;
+                    break;
+                case iss_t::XTN_MMU_PARAMS:
+                    drsp.rdata = (uint32_t)r_mmu_params;
+                    drsp.valid = true;
+                    drsp.error = false;
+                    break;
+                case iss_t::XTN_MMU_RELEASE:
+                    drsp.rdata = (uint32_t)r_mmu_release;
+                    drsp.valid = true;
+                    drsp.error = false;
+                    break;
+                case iss_t::XTN_MMU_WORD_LO:
+                    drsp.rdata = (uint32_t)r_mmu_word_lo;
+                    drsp.valid = true;
+                    drsp.error = false;
+                    break;
+                case iss_t::XTN_MMU_WORD_HI:
+                    drsp.rdata = (uint32_t)r_mmu_word_hi;
+                    drsp.valid = true;
+                    drsp.error = false;
+                    break;
+                default:
+                    r_dcache_error_type = MMU_READ_UNDEFINED_XTN; 
+                    r_dcache_bad_vaddr  = dreq.addr;
+                    drsp.valid = true;
+                    drsp.error = true;
+                    break;
+                }
+                r_dcache_fsm = DCACHE_IDLE;
+                break;
+            }
+
+            // Decoding WRITE XTN requests from processor
+            // If there is no privilege violation, they are not executed in this DCACHE_IDLE state,
+            // but in the next state, because they generally require access to the caches or the TLBs 
+
+            if (dreq.type == iss_t::XTN_WRITE) 
+            {
+                drsp.valid = false;
+                drsp.error = false;
+                drsp.rdata = 0;
+                r_dcache_wdata_save = dreq.wdata;   
+                switch(xtn_opcod) {     
+
+                case iss_t::XTN_PTPR:       // context switch : checking the kernel mode
+                                            // both instruction & data TLBs must be flushed
+                    if ((dreq.mode == iss_t::MODE_HYPER) || (dreq.mode == iss_t::MODE_KERNEL)) 
+                    {
+                        r_mmu_ptpr = dreq.wdata;
+                        r_icache_error_type = MMU_NONE;
+                        r_dcache_error_type = MMU_NONE;
+                        r_dcache_type_save = dreq.addr/4; 
+                        r_dcache_xtn_req = true;
+                        r_dcache_fsm = DCACHE_CTXT_SWITCH;
+                    } 
+                    else 
+                    { 
+                        r_dcache_error_type = MMU_WRITE_PRIVILEGE_VIOLATION; 
+                        r_dcache_bad_vaddr  = dreq.addr;
+                        drsp.valid = true;
+                        drsp.error = true;
+                        r_dcache_fsm = DCACHE_IDLE;
+                    }
+                    break;
+
+                case iss_t::XTN_TLB_MODE:     // modifying TLBs mode : checking the kernel mode
+                    if ((dreq.mode == iss_t::MODE_HYPER) || (dreq.mode == iss_t::MODE_KERNEL)) 
+                    {
+                        r_mmu_mode = (int)dreq.wdata;
+                        drsp.valid = true;
+                    } 
+                    else 
+                    {
+                        r_dcache_error_type = MMU_WRITE_PRIVILEGE_VIOLATION; 
+                        r_dcache_bad_vaddr  = dreq.addr;
+                        drsp.valid = true;
+                        drsp.error = true;
+                    }
+                    r_dcache_fsm = DCACHE_IDLE;
+                    break;
+
+                case iss_t::XTN_DTLB_INVAL:     //  checking the kernel mode
+                    if ((dreq.mode == iss_t::MODE_HYPER) || (dreq.mode == iss_t::MODE_KERNEL)) 
+                    {
+                        r_dcache_fsm = DCACHE_DTLB_INVAL;  
+                    } 
+                    else 
+                    {
+                        r_dcache_error_type = MMU_WRITE_PRIVILEGE_VIOLATION; 
+                        r_dcache_bad_vaddr  = dreq.addr;
+                        drsp.valid = true;
+                        drsp.error = true;
+                	r_dcache_fsm = DCACHE_IDLE;
+                    }
+                    break;
+
+                case iss_t::XTN_ITLB_INVAL:     //  checking the kernel mode
+                    if ((dreq.mode == iss_t::MODE_HYPER) || (dreq.mode == iss_t::MODE_KERNEL)) 
+                    {
+                        r_dcache_xtn_req = true;
+                        r_dcache_type_save = dreq.addr/4;
+                        r_dcache_fsm = DCACHE_ITLB_INVAL;  
+                    } 
+                    else 
+                    {
+                        r_dcache_error_type = MMU_WRITE_PRIVILEGE_VIOLATION; 
+                        r_dcache_bad_vaddr  = dreq.addr;
+                        drsp.valid = true;
+                        drsp.error = true;
+                	r_dcache_fsm = DCACHE_IDLE;
+                    }
+                    break;
+
+                case iss_t::XTN_DCACHE_INVAL:   // cache inval can be executed in user mode.
+                    r_dcache_fsm = DCACHE_DCACHE_INVAL;
+                    break;
+
+                case iss_t::XTN_MMU_DCACHE_PA_INV:   // cache inval can be executed in user mode.
+                    r_dcache_fsm = DCACHE_DCACHE_INVAL_PA;
+                    break;
+
+                case iss_t::XTN_DCACHE_FLUSH:   // cache flush can be executed in user mode.
+                    r_dcache_type_save = dreq.addr/4; 
+                    r_dcache_xtn_req = true;
+                    r_dcache_way = 0;
+                    r_dcache_set = 0;
+                    r_dcache_fsm = DCACHE_DCACHE_FLUSH; 
+                    break;
+
+                case iss_t::XTN_ICACHE_INVAL:   // cache inval can be executed in user mode.
+                    r_dcache_type_save = dreq.addr/4; 
+                    r_dcache_xtn_req = true;
+                    r_dcache_fsm = DCACHE_ICACHE_INVAL; 
+                    break;
+
+                case iss_t::XTN_MMU_ICACHE_PA_INV:   // cache inval can be executed in user mode.
+                    r_dcache_type_save = dreq.addr/4; 
+                    r_dcache_xtn_req = true;
+                    r_dcache_fsm = DCACHE_ICACHE_INVAL_PA; 
+                    break;
+
+                case iss_t::XTN_ICACHE_FLUSH:   // cache flush can be executed in user mode.
+                    r_dcache_type_save = dreq.addr/4; 
+                    r_dcache_xtn_req = true; 
+                    r_dcache_fsm = DCACHE_ICACHE_FLUSH;
+                    break;
+
+                case iss_t::XTN_SYNC:           // cache synchronization can be executed in user mode.
+                    if (r_wbuf.rok())
+                    {
+                        r_dcache_fsm = DCACHE_DCACHE_SYNC; 
+                    }
+                    else
+                    {
+                        drsp.valid = true;
+                        r_dcache_fsm = DCACHE_IDLE;
+                    }
+                    break;
+
+                case iss_t::XTN_MMU_WORD_LO: // modifying MMU misc registers
+                    if ((dreq.mode == iss_t::MODE_HYPER) || (dreq.mode == iss_t::MODE_KERNEL)) 
+                    {
+                        r_mmu_word_lo = (int)dreq.wdata;
+                        drsp.valid = true;
+                    } 
+                    else 
+                    {
+                        r_dcache_error_type = MMU_WRITE_PRIVILEGE_VIOLATION; 
+                        r_dcache_bad_vaddr  = dreq.addr;
+                        drsp.valid = true;
+                        drsp.error = true;
+                    }
+                    r_dcache_fsm = DCACHE_IDLE;
+                    break;
+
+                case iss_t::XTN_MMU_WORD_HI: // modifying MMU misc registers
+                    if ((dreq.mode == iss_t::MODE_HYPER) || (dreq.mode == iss_t::MODE_KERNEL)) 
+                    {
+                        r_mmu_word_hi = (int)dreq.wdata;
+                        drsp.valid = true;
+                    } 
+                    else 
+                    {
+                        r_dcache_error_type = MMU_WRITE_PRIVILEGE_VIOLATION; 
+                        r_dcache_bad_vaddr  = dreq.addr;
+                        drsp.valid = true;
+                        drsp.error = true;
+                    }
+                    r_dcache_fsm = DCACHE_IDLE;
+                    break;
+
+                case iss_t::XTN_ICACHE_PREFETCH:
+                case iss_t::XTN_DCACHE_PREFETCH:
+                    drsp.valid = true;
+                    drsp.error = false;
+                    break;
+                    
+                default:
+                    r_dcache_error_type = MMU_WRITE_UNDEFINED_XTN; 
+                    r_dcache_bad_vaddr  = dreq.addr;
+                    drsp.valid = true;
+                    drsp.error = true;
+                    r_dcache_fsm = DCACHE_IDLE;
+                    break;
+                } // end switch xtn_opcod
+
+                break;
+            } // end if XTN_WRITE
+
+            // Evaluating dcache_hit_t, dcache_hit_x, dcache_hit_p, dcache_hit_c,
+            // dcache_pte_info, dcache_tlb_way, dcache_tlb_set & dpaddr & cacheability 
+            // - If MMU activated : cacheability is defined by the cachable bit in the TLB
+            // - If MMU not activated : cacheability is defined by the segment table.
+            
+            // For instrumentation: is User access ? 
+            r_dreq_isUser_save = (dreq.mode == iss_t::MODE_USER) ? true : false;        
+
+            if ( !(r_mmu_mode.read() & DATA_TLB_MASK) ) // MMU not activated
+            {
+                dcache_hit_t  = true;       
+                dcache_hit_x  = true;   
+                dcache_hit_p  = true;  
+                tlb_dpaddr    = dreq.addr; 
+                spc_dpaddr    = dreq.addr;    
+                dcache_cached = m_cacheability_table[dreq.addr] && 
+                    ((dreq.type != iss_t::DATA_LL)  && (dreq.type != iss_t::DATA_SC) &&
+                     (dreq.type != iss_t::XTN_READ) && (dreq.type != iss_t::XTN_WRITE));     
+            } 
+            else                                                            // MMU activated
+            {
+                m_cpt_data_tlb_read++;
+                dcache_hit_t  = dcache_tlb.cctranslate(dreq.addr, &tlb_dpaddr, &dcache_pte_info, 
+                                                       &dcache_tlb_nline, &dcache_tlb_way, &dcache_tlb_set);                  
+                dcache_hit_x  = (((vaddr_t)r_dcache_vpn_save << PAGE_K_NBITS) == (dreq.addr & ~PAGE_K_MASK)) && r_dtlb_translation_valid; 
+                dcache_hit_p  = (((dreq.addr >> PAGE_M_NBITS) == r_dcache_id1_save) && r_dcache_ptba_ok );
+                spc_dpaddr    = ((paddr_t)r_dcache_ppn_save << PAGE_K_NBITS) | (paddr_t)((dreq.addr & PAGE_K_MASK));
+                dcache_cached = dcache_pte_info.c && 
+                                ((dreq.type != iss_t::DATA_LL)  && (dreq.type != iss_t::DATA_SC) &&
+                                 (dreq.type != iss_t::XTN_READ) && (dreq.type != iss_t::XTN_WRITE));    
+            }
+
+            if ( !(r_mmu_mode.read() & DATA_CACHE_MASK) )   // cache not actived
+            {
+                dcache_cached = false;
+            }
+
+            // dcache_hit_c & dcache_rdata
+            if ( dcache_cached )    // using speculative physical address for cached access
+            {
+                dcache_hit_c = r_dcache.read(spc_dpaddr, &dcache_rdata);
+            } 
+            else                    // using actual physical address for uncached access
+            {
+                dcache_hit_c = false;
+            }
+            if ( r_mmu_mode.read() & DATA_TLB_MASK ) 
+            {
+                // Checking access rights
+                if ( dcache_hit_t ) 
+                {
+                    if (!dcache_pte_info.u && (dreq.mode == iss_t::MODE_USER)) 
+                    {
+                        if ((dreq.type == iss_t::DATA_READ)||(dreq.type == iss_t::DATA_LL))
+                        {
+                            r_dcache_error_type = MMU_READ_PRIVILEGE_VIOLATION;
+                        }
+                        else /*if ((dreq.type == iss_t::DATA_WRITE)||(dreq.type == iss_t::DATA_SC))*/
+                        {
+                            r_dcache_error_type = MMU_WRITE_PRIVILEGE_VIOLATION;
+                        }  
+                        r_dcache_bad_vaddr = dreq.addr;
+                        drsp.valid = true;
+                        drsp.error = true;
+                        drsp.rdata = 0;
+                        r_dcache_fsm = DCACHE_IDLE;
+                        break;
+                    }
+                    if (!dcache_pte_info.w && ((dreq.type == iss_t::DATA_WRITE)||(dreq.type == iss_t::DATA_SC))) 
+                    {
+                        r_dcache_error_type = MMU_WRITE_ACCES_VIOLATION;  
+                        r_dcache_bad_vaddr = dreq.addr;
+                        drsp.valid = true;
+                        drsp.error = true;
+                        drsp.rdata = 0;
+                        r_dcache_fsm = DCACHE_IDLE;
+                        break;
+                    }
+                }
+
+                // update LRU, save ppn, vpn and page type
+                if ( dcache_hit_t ) {
+                    dcache_tlb.setlru(dcache_tlb_way,dcache_tlb_set); 
+                    r_dcache_ppn_save = tlb_dpaddr >> PAGE_K_NBITS;
+                    r_dcache_vpn_save = dreq.addr >> PAGE_K_NBITS;
+                    r_dcache_tlb_nline = dcache_tlb_nline;
+                    r_dtlb_translation_valid = true;
+                }
+                else
+                {
+                    r_dtlb_translation_valid = false;
+                }
+
+            } // end if MMU activated
+
+            // compute next state 
+            if ( !dcache_hit_p && !dcache_hit_t )  // TLB miss
+            {
+                r_dcache_tlb_paddr = (paddr_t)r_mmu_ptpr << (INDEX1_NBITS+2) | (paddr_t)((dreq.addr>>PAGE_M_NBITS)<<2);
+                r_dcache_fsm = DCACHE_DTLB1_READ_CACHE;
+                m_cpt_data_tlb_miss++;
+                m_cost_data_tlb_miss_frz++;
+            }
+            else if ( dcache_hit_p && !dcache_hit_t )  // TLB Miss with possibility of bypass first level page
+            {
+                // walk page table level 2
+                r_dcache_tlb_paddr = (paddr_t)r_dcache_ptba_save | 
+                                     (paddr_t)(((dreq.addr&PTD_ID2_MASK)>>PAGE_K_NBITS) << 3); 
+                r_dcache_fsm = DCACHE_DTLB2_READ_CACHE;
+                m_cpt_data_tlb_miss++;
+                m_cost_data_tlb_miss_frz++;
+            }
+            else if ( dcache_hit_t && !dcache_hit_x && dcache_cached )// cached access with an ucorrect speculative physical address
+            {
+                r_dcache_hit_p_save = dcache_hit_p;
+                r_dcache_fsm = DCACHE_BIS;
+                //m_cost_data_tlb_miss_frz++;
+            }
+            else  // cached or uncached access with a correct speculative physical address
+            {
+                switch( dreq.type ) {
+                    case iss_t::DATA_READ:
+                    case iss_t::DATA_LL:
+                    case iss_t::DATA_SC:
+                        m_cpt_read++;
+                        if ( dcache_hit_c ) 
+                        {
+                            r_dcache_fsm = DCACHE_IDLE;
+                            drsp.valid = true;
+                            drsp.rdata = dcache_rdata;
+                        } 
+                        else 
+                        {
+                            if ( dcache_cached ) 
+                            {
+                                r_dcache_miss_req = true;
+                                r_dcache_fsm = DCACHE_MISS_WAIT;
+                                m_cpt_data_miss++;
+                                m_cost_data_miss_frz++;
+                            } 
+                            else 
+                            {
+                                if ((dreq.type == iss_t::DATA_SC) && !dcache_pte_info.d && (r_mmu_mode.read() & DATA_TLB_MASK))
+                                {
+                                    m_cpt_data_tlb_update_dirty++;
+                                    m_cost_data_tlb_update_dirty_frz++;
+                                    r_dcache_sc_updt_dirty = true;
+                                    if ( dcache_tlb.getpagesize(dcache_tlb_way, dcache_tlb_set) )	// 2M page size, one level page table 
+                            	    {
+                                        r_dcache_pte_update = dcache_tlb.getpte(dcache_tlb_way, dcache_tlb_set) | PTE_D_MASK;
+                                        r_dcache_tlb_paddr = (paddr_t)r_mmu_ptpr << (INDEX1_NBITS+2) | (paddr_t)((dreq.addr>>PAGE_M_NBITS)<<2);
+                                        r_dcache_tlb_ll_dirty_req = true;
+                                        r_dcache_fsm = DCACHE_LL_DIRTY_WAIT;
+                            	    }
+                                    else	// 4k page size, two levels page table 
+                                    {   
+                                        if (dcache_hit_p) 
+                                        {
+                                            r_dcache_pte_update = dcache_tlb.getpte(dcache_tlb_way, dcache_tlb_set) | PTE_D_MASK;
+                                            r_dcache_tlb_paddr = (paddr_t)r_dcache_ptba_save | (paddr_t)(((dreq.addr&PTD_ID2_MASK)>>PAGE_K_NBITS) << 3);
+                                            r_dcache_tlb_ll_dirty_req = true;
+                                            r_dcache_fsm = DCACHE_LL_DIRTY_WAIT;
+                                        }
+                                        else    // get PTBA to calculate the physical address of PTE
+                                        {
+                                            data_t ptba;
+                                            if (r_dcache.read((paddr_t)r_mmu_ptpr << (INDEX1_NBITS+2) | (paddr_t)((dreq.addr>>PAGE_M_NBITS)<<2), &ptba))
+                                            {
+                                                r_dcache_pte_update = dcache_tlb.getpte(dcache_tlb_way, dcache_tlb_set) | PTE_D_MASK;
+                                                r_dcache_tlb_paddr = (paddr_t)(ptba & ((1<<(m_paddr_nbits - PAGE_K_NBITS))-1)) << PAGE_K_NBITS | 
+                                                    (paddr_t)(((dreq.addr & PTD_ID2_MASK) >> PAGE_K_NBITS) << 3);
+                                            	r_dcache_tlb_ll_dirty_req = true;
+                                            	r_dcache_fsm = DCACHE_LL_DIRTY_WAIT;
+                                                
+                                            }
+                                            else
+                                            {
+                                                r_dcache_pte_update = dcache_tlb.getpte(dcache_tlb_way, dcache_tlb_set) | PTE_D_MASK;
+                                                r_dcache_tlb_paddr = (paddr_t)r_mmu_ptpr << (INDEX1_NBITS+2) | (paddr_t)((dreq.addr>>PAGE_M_NBITS)<<2);
+                                                r_dcache_tlb_ptba_read = true;
+                                                r_dcache_fsm = DCACHE_DTLB1_READ_CACHE;
+                                            }
+                                        }
+                                    }		
+                                }
+                                else
+                                {	
+                                    r_dcache_unc_req = true;
+                                    r_dcache_fsm = DCACHE_UNC_WAIT;
+                                    m_cpt_unc_read++;
+                                }
+                                m_cost_unc_read_frz++;
+                            }
+                        }
+                        break;
+                case iss_t::DATA_WRITE:
+                        m_cpt_write++;
+                        if ( dcache_cached ) m_cpt_write_cached++;
+                        m_cost_write_frz++;
+                        if ( dcache_hit_c && dcache_cached )    // cache update required
+                        {
+                            r_dcache_fsm = DCACHE_WRITE_UPDT;
+                        } 
+                        else if ( !dcache_pte_info.d && (r_mmu_mode.read() & DATA_TLB_MASK) )   // dirty bit update required
+                        {
+                            m_cpt_data_tlb_update_dirty++;
+                            m_cost_data_tlb_update_dirty_frz++;
+                            if ( dcache_tlb.getpagesize(dcache_tlb_way, dcache_tlb_set) )	// 2M page size, one level page table 
+                            {
+                                r_dcache_pte_update = dcache_tlb.getpte(dcache_tlb_way, dcache_tlb_set) | PTE_D_MASK;
+                                r_dcache_tlb_paddr = (paddr_t)r_mmu_ptpr << (INDEX1_NBITS+2) | (paddr_t)((dreq.addr>>PAGE_M_NBITS)<<2);
+                                r_dcache_tlb_ll_dirty_req = true;
+                                r_dcache_fsm = DCACHE_LL_DIRTY_WAIT;
+                            }
+                            else	// 4k page size, two levels page table 
+                            {   
+                                if (dcache_hit_p) 
+                                {
+                                    r_dcache_pte_update = dcache_tlb.getpte(dcache_tlb_way, dcache_tlb_set) | PTE_D_MASK;
+                                    r_dcache_tlb_paddr = (paddr_t)r_dcache_ptba_save | (paddr_t)(((dreq.addr&PTD_ID2_MASK)>>PAGE_K_NBITS) << 3);
+                                    r_dcache_tlb_ll_dirty_req = true;
+                                    r_dcache_fsm = DCACHE_LL_DIRTY_WAIT;
+                                }
+                                else    // get PTBA to calculate the physical address of PTE
+                                {
+                                    r_dcache_pte_update = dcache_tlb.getpte(dcache_tlb_way, dcache_tlb_set) | PTE_D_MASK;
+                                    data_t ptba;
+                                    if (r_dcache.read((paddr_t)r_mmu_ptpr << (INDEX1_NBITS+2) | (paddr_t)((dreq.addr>>PAGE_M_NBITS)<<2), &ptba))
+                                        {
+                                            r_dcache_tlb_paddr = (paddr_t)(ptba & ((1<<(m_paddr_nbits - PAGE_K_NBITS))-1)) << PAGE_K_NBITS | (paddr_t)(((dreq.addr & PTD_ID2_MASK) >> PAGE_K_NBITS) << 3);
+                                            r_dcache_tlb_ll_dirty_req = true;
+                                            r_dcache_fsm = DCACHE_LL_DIRTY_WAIT;
+                                        }
+                                    else
+                                        {
+                                            r_dcache_tlb_paddr = (paddr_t)r_mmu_ptpr << (INDEX1_NBITS+2) | (paddr_t)((dreq.addr>>PAGE_M_NBITS)<<2);
+                                            r_dcache_tlb_ptba_read = true;
+                                            r_dcache_fsm = DCACHE_DTLB1_READ_CACHE;
+                                        }
+                                }
+                            }
+                        }
+                        else                                    // no cache update, not dirty bit update
+                        {
+                            r_dcache_fsm = DCACHE_WRITE_REQ;
+                            drsp.valid = true;
+                            drsp.rdata = 0;
+                        }
+                        break;
+                    default:
+                        break;
+                } // end switch dreq.type
+            } // end if next states
+
+            // save values for the next states
+            r_dcache_paddr_save   = tlb_dpaddr;
+            r_dcache_type_save    = dreq.type;
+            r_dcache_wdata_save   = dreq.wdata;
+            r_dcache_be_save      = dreq.be;
+            r_dcache_rdata_save   = dcache_rdata;
+            r_dcache_cached_save  = dcache_cached;
+            r_dcache_dirty_save   = dcache_pte_info.d;
+            r_dcache_tlb_set_save = dcache_tlb_set;
+            r_dcache_tlb_way_save = dcache_tlb_way;
+
+        } // end if dreq.valid
+        else 
+        {   
+            r_dcache_fsm = DCACHE_IDLE;
+        }
+
+        // processor request are not accepted in the WRITE_REQ state 
+        // when the write buffer is not writeable
+
+        if ((r_dcache_fsm == DCACHE_WRITE_REQ) && 
+            (r_dcache_write_req || !r_wbuf.wok(r_dcache_paddr_save))) 
+        {
+            drsp.valid = false;
+        }
+        break;
+    }
+    /////////////////
+    case DCACHE_BIS:
+    {
+        // external cache invalidate request
+        if ( r_tgt_dcache_req )   
+        {
+            r_dcache_fsm = DCACHE_CC_CHECK;
+            r_dcache_fsm_save = r_dcache_fsm;
+            break;
+        }
+
+        // Using tlb entry is invalidated 
+        if ( r_dcache_inval_tlb_rsp )
+        {
+            r_dcache_inval_tlb_rsp = false;
+            r_dcache_fsm = DCACHE_IDLE;
+            break;
+        }
+
+        data_t  dcache_rdata = 0;
+        bool    dcache_hit_c = false;
+        bool    dcache_hit_t = false;
+        paddr_t tlb_dpaddr   = 0;
+
+	dcache_hit_t = dcache_tlb.translate(dreq.addr, &tlb_dpaddr);
+
+	if ( (tlb_dpaddr == r_dcache_paddr_save.read()) && dreq.valid && dcache_hit_t ) 
+	{
+	    // acces always cached in this state
+	    dcache_hit_c = r_dcache.read(r_dcache_paddr_save, &dcache_rdata);
+	    
+	    if ( dreq.type == iss_t::DATA_READ )  // cached read
+	    {
+	        m_cpt_read++;
+	        if ( !dcache_hit_c ) 
+	        {
+	            r_dcache_miss_req = true;
+	            r_dcache_fsm = DCACHE_MISS_WAIT;
+	            m_cpt_data_miss++;
+	            m_cost_data_miss_frz++;
+	        }
+	        else
+	        {
+	            r_dcache_fsm = DCACHE_IDLE;
+	        }
+	        drsp.valid = dcache_hit_c;
+	        drsp.error = false;
+	        drsp.rdata = dcache_rdata;
+	    }
+	    else    // cached write
+	    {
+	        m_cpt_write++;
+	        m_cpt_write_cached++;
+	        if ( dcache_hit_c )    // cache update required
+	        {
+	            r_dcache_rdata_save = dcache_rdata;
+	            r_dcache_fsm = DCACHE_WRITE_UPDT;
+	        } 
+	        else if (!r_dcache_dirty_save && (r_mmu_mode.read() & DATA_TLB_MASK))   // dirty bit update required
+	        {
+                    m_cpt_data_tlb_update_dirty++;
+                    m_cost_data_tlb_update_dirty_frz++;  			
+	            if (dcache_tlb.getpagesize(r_dcache_tlb_way_save, r_dcache_tlb_set_save)) 
+	            {
+	                r_dcache_pte_update = dcache_tlb.getpte(r_dcache_tlb_way_save, r_dcache_tlb_set_save) | PTE_D_MASK;
+	                r_dcache_tlb_paddr = (paddr_t)r_mmu_ptpr << (INDEX1_NBITS+2) | (paddr_t)((dreq.addr>>PAGE_M_NBITS)<<2);
+	                r_dcache_tlb_ll_dirty_req = true;
+	                r_dcache_fsm = DCACHE_LL_DIRTY_WAIT;
+	            }
+	            else
+	            {   
+	                if (r_dcache_hit_p_save) 
+	                {
+	                    r_dcache_pte_update = dcache_tlb.getpte(r_dcache_tlb_way_save, r_dcache_tlb_set_save) | PTE_D_MASK;
+	                    r_dcache_tlb_paddr = (paddr_t)r_dcache_ptba_save|(paddr_t)(((dreq.addr&PTD_ID2_MASK)>>PAGE_K_NBITS) << 3);
+	                    r_dcache_tlb_ll_dirty_req = true;
+	                    r_dcache_fsm = DCACHE_LL_DIRTY_WAIT;
+	                }
+	                else
+	                {
+	                    r_dcache_pte_update = dcache_tlb.getpte(r_dcache_tlb_way_save, r_dcache_tlb_set_save) | PTE_D_MASK;
+                        data_t ptba;
+            		    if (r_dcache.read((paddr_t)r_mmu_ptpr << (INDEX1_NBITS+2) | (paddr_t)((dreq.addr>>PAGE_M_NBITS)<<2), &ptba))
+                        {
+                	        r_dcache_tlb_paddr = (paddr_t)(ptba & ((1<<(m_paddr_nbits - PAGE_K_NBITS))-1)) << PAGE_K_NBITS | (paddr_t)(((dreq.addr & PTD_ID2_MASK) >> PAGE_K_NBITS) << 3);
+                            r_dcache_tlb_ll_dirty_req = true;
+                            r_dcache_fsm = DCACHE_LL_DIRTY_WAIT;
+                        }
+                        else
+                        {
+                            r_dcache_tlb_paddr = (paddr_t)r_mmu_ptpr << (INDEX1_NBITS+2) | (paddr_t)((dreq.addr>>PAGE_M_NBITS)<<2);
+                            r_dcache_tlb_ptba_read = true;
+                            r_dcache_fsm = DCACHE_DTLB1_READ_CACHE;
+                        }
+	                }
+	            }
+	        }
+	        else                                    // no cache update, not dirty bit update
+	        {
+	            r_dcache_fsm = DCACHE_WRITE_REQ;
+	            drsp.valid = true;
+	            drsp.rdata = 0;
+	        }
+	    }
+	}
+	else
+	{
+            drsp.valid = false;
+            drsp.error = false;
+            drsp.rdata = 0;
+            r_dcache_fsm = DCACHE_IDLE;
+	}
+        break;
+    }
+    //////////////////////////
+    case DCACHE_LL_DIRTY_WAIT:
+    {
+        m_cost_data_tlb_update_dirty_frz++;
+
+        // external cache invalidate request
+        if ( r_tgt_dcache_req )   
+        {
+            r_dcache_fsm = DCACHE_CC_CHECK;
+            r_dcache_fsm_save = r_dcache_fsm;
+            break;
+        }
+
+	if (!r_dcache_tlb_ll_dirty_req)
+	{
+        if ( r_vci_rsp_data_error ) // VCI response ko
+        {
+            if (dcache_tlb.getpagesize(r_dcache_tlb_way_save, r_dcache_tlb_set_save)) 
+            {
+                r_dcache_error_type = MMU_WRITE_PT1_ILLEGAL_ACCESS;     
+            }
+            else
+            {
+                r_dcache_error_type = MMU_WRITE_PT2_ILLEGAL_ACCESS;     
+            }
+            r_dcache_bad_vaddr = dreq.addr;
+            r_dcache_fsm = DCACHE_ERROR; 
+
+            if (r_dcache_inval_tlb_rsp) r_dcache_inval_tlb_rsp = false;
+            if (r_dcache_inval_rsp) r_dcache_inval_rsp = false;
+            if (r_dcache_sc_updt_dirty) r_dcache_sc_updt_dirty = false;
+        }
+	    else
+        {
+            if ( !(r_dcache_miss_buf[0] >> PTE_V_SHIFT) )	// unmapped
+            {
+                if (dcache_tlb.getpagesize(r_dcache_tlb_way_save, r_dcache_tlb_set_save))
+                { 
+                    r_dcache_error_type = MMU_WRITE_PT1_UNMAPPED;       
+                }
+                else
+                {
+                    r_dcache_error_type = MMU_WRITE_PT2_UNMAPPED;       
+                }
+                
+                r_dcache_bad_vaddr = dreq.addr;
+                r_dcache_fsm = DCACHE_ERROR;
+
+                if (r_dcache_inval_tlb_rsp) r_dcache_inval_tlb_rsp = false;
+                if (r_dcache_inval_rsp) r_dcache_inval_rsp = false;
+                if (r_dcache_sc_updt_dirty) r_dcache_sc_updt_dirty = false;
+	        }
+        	else if ( r_dcache_inval_tlb_rsp )
+        	{
+        	    r_dcache_inval_tlb_rsp = false;
+        	    r_dcache_fsm = DCACHE_IDLE;
+                if (r_dcache_sc_updt_dirty) r_dcache_sc_updt_dirty = false;
+        	}
+            else if ( r_dcache_inval_rsp )
+            {
+        	    r_dcache_inval_rsp = false;
+                r_dcache_fsm = DCACHE_IDLE;
+                if (r_dcache_sc_updt_dirty) r_dcache_sc_updt_dirty = false;
+            }
+            else
+            {
+                r_dcache_tlb_sc_dirty_req = true;
+                r_dcache_pte_update = r_dcache_miss_buf[0] | r_dcache_pte_update.read();
+                r_dcache_fsm = DCACHE_SC_DIRTY_WAIT; 
+            }
+	    }
+	}
+	break;
+    }
+    //////////////////////////
+    case DCACHE_SC_DIRTY_WAIT:
+    {
+        m_cost_data_tlb_update_dirty_frz++;	    
+        // external cache invalidate request
+        if ( r_tgt_dcache_req )   
+        {
+            r_dcache_fsm = DCACHE_CC_CHECK;
+            r_dcache_fsm_save = r_dcache_fsm;
+            break;
+        }
+
+	if ( !r_dcache_tlb_sc_dirty_req )
+	{
+	    if ( r_vci_rsp_data_error ) // VCI response ko
+	    {
+	        if (dcache_tlb.getpagesize(r_dcache_tlb_way_save, r_dcache_tlb_set_save))
+	        {
+	            r_dcache_error_type = MMU_WRITE_PT1_ILLEGAL_ACCESS;    
+	        }
+	        else
+	        {
+	            r_dcache_error_type = MMU_WRITE_PT2_ILLEGAL_ACCESS;    
+	        }
+	        r_dcache_bad_vaddr = dreq.addr;
+	        r_dcache_fsm = DCACHE_ERROR;
+
+            if (r_dcache_inval_tlb_rsp) r_dcache_inval_tlb_rsp = false;
+            if (r_dcache_inval_rsp) r_dcache_inval_rsp = false;		 	    
+            if (r_dcache_sc_updt_dirty) r_dcache_sc_updt_dirty = false;
+	    }
+	    else 
+	    {
+                // Using tlb entry is invalidated 
+                if ( r_dcache_inval_tlb_rsp )
+                {
+                    r_dcache_inval_tlb_rsp = false;
+                    r_dcache_fsm = DCACHE_IDLE;
+                    if (r_dcache_tlb_sc_fail) r_dcache_tlb_sc_fail = false;
+                    if (r_dcache_sc_updt_dirty) r_dcache_sc_updt_dirty = false;
+                }
+		else if ( r_dcache_inval_rsp )
+		{
+            r_dcache_inval_rsp = false;
+		    r_dcache_fsm = DCACHE_IDLE;
+		    if (r_dcache_tlb_sc_fail) r_dcache_tlb_sc_fail = false;
+		    if (r_dcache_sc_updt_dirty) r_dcache_sc_updt_dirty = false;
+		}
+		else if ( r_dcache_tlb_sc_fail )
+	    {
+		    r_dcache_tlb_ll_dirty_req = true;
+		    r_dcache_tlb_sc_fail = false;
+            r_dcache_fsm = DCACHE_LL_DIRTY_WAIT;
+		    m_cpt_data_tlb_update_dirty++; 
+        }
+		else
+		{
+                    bool write_hit = r_dcache.write(r_dcache_tlb_paddr, r_dcache_pte_update);
+                    assert(write_hit && "Write on miss ignores data for data MMU update dirty bit");
+                    r_dcache_fsm = DCACHE_WRITE_DIRTY; 
+                    m_cpt_dcache_data_write++; 
+		}
+	    }
+	}
+	break;
+    }
+    ////////////////////////////
+    case DCACHE_DTLB1_READ_CACHE:
+    {
+        m_cost_data_tlb_miss_frz++;
+        if ( r_dcache_tlb_ptba_read ) m_cost_data_tlb_update_dirty_frz++;
+
+        // external cache invalidate request
+        if ( r_tgt_dcache_req )   
+        {
+            r_dcache_fsm = DCACHE_CC_CHECK;
+            r_dcache_fsm_save = r_dcache_fsm;
+            break;
+        }        
+
+        // Using tlb entry is invalidated 
+        if ( r_dcache_inval_tlb_rsp )
+        {
+            r_dcache_inval_tlb_rsp = false;
+            r_dcache_fsm = DCACHE_IDLE;
+            if ( r_dcache_tlb_ptba_read ) r_dcache_tlb_ptba_read = false;
+            break;
+        }
+
+        data_t tlb_data = 0;
+        bool tlb_hit_cache = r_dcache.read(r_dcache_tlb_paddr, &tlb_data);
+
+        // DTLB request hit in cache
+        if ( tlb_hit_cache )
+        {
+            if ( !(tlb_data >> PTE_V_SHIFT) )	// unmapped
+            {
+                r_dcache_ptba_ok    = false;
+                if ((r_dcache_type_save == iss_t::DATA_READ)||(r_dcache_type_save == iss_t::DATA_LL))
+                {
+                    r_dcache_error_type = MMU_READ_PT1_UNMAPPED;
+                }
+                else /*if ((dreq.type == iss_t::DATA_WRITE)||(dreq.type == iss_t::DATA_SC))*/
+                {
+                    r_dcache_error_type = MMU_WRITE_PT1_UNMAPPED;
+                }  
+                r_dcache_bad_vaddr  = dreq.addr;
+                r_dcache_fsm        = DCACHE_ERROR;
+            }
+            else if ( (tlb_data & PTE_T_MASK) >> PTE_T_SHIFT )	// PTD
+            {
+                r_dcache_ptba_ok   = true;
+                r_dcache_ptba_save = (paddr_t)(tlb_data & ((1<<(m_paddr_nbits - PAGE_K_NBITS))-1)) << PAGE_K_NBITS;  
+                r_dcache_id1_save  = dreq.addr >> PAGE_M_NBITS;
+                r_dcache_tlb_paddr = (paddr_t)(tlb_data & ((1<<(m_paddr_nbits - PAGE_K_NBITS))-1)) << PAGE_K_NBITS | 
+                                     (paddr_t)(((dreq.addr & PTD_ID2_MASK) >> PAGE_K_NBITS) << 3);
+                if ( r_dcache_tlb_ptba_read )
+                {
+                    paddr_t tlb_dpaddr;
+                    data_t data;
+                    r_dcache_tlb_ptba_read = false;
+                    if (dcache_tlb.translate(dreq.addr, &tlb_dpaddr) && r_dcache.read( (paddr_t)(tlb_data & ((1<<(m_paddr_nbits - PAGE_K_NBITS))-1)) << PAGE_K_NBITS | (paddr_t)(((dreq.addr & PTD_ID2_MASK) >> PAGE_K_NBITS) << 3) ,&data))
+                    {
+                        r_dcache_tlb_ll_dirty_req = true;
+                        r_dcache_fsm = DCACHE_LL_DIRTY_WAIT;
+                    }	        
+                    else
+                    {
+                        r_dcache_fsm = DCACHE_IDLE;
+                    }
+                }
+                else
+                {
+                    r_dcache_fsm = DCACHE_DTLB2_READ_CACHE;
+                }
+            }
+            else	// PTE
+            {
+                m_cpt_data_tlb_hit_dcache++;
+                r_dcache_ptba_ok = false;
+                if ( (m_srcid_rw >> 4) == ((r_dcache_tlb_paddr.read() & ((1<<(m_paddr_nbits - PAGE_M_NBITS))-1)) >> (m_paddr_nbits - PAGE_M_NBITS -10)) ) // local
+                {
+                    if ( (tlb_data & PTE_L_MASK ) >> PTE_L_SHIFT ) // L bit is set
+                    {
+                        r_dcache_pte_update = tlb_data;
+                        r_dcache_fsm = DCACHE_TLB1_UPDT_SEL;
+                    }
+                    else
+                    {
+                        r_dcache_pte_update = tlb_data | PTE_L_MASK;
+                        r_dcache_tlb_ll_acc_req = true;
+                        r_dcache_fsm = DCACHE_TLB1_LL_WAIT;
+                        m_cpt_data_tlb_update_acc++;
+                        m_cost_data_tlb_update_acc_frz++;
+                    }
+                }
+                else // remotely
+                {
+                    if ( (tlb_data & PTE_R_MASK ) >> PTE_R_SHIFT ) // R bit is set
+                    {
+                        r_dcache_pte_update = tlb_data;
+                        r_dcache_fsm = DCACHE_TLB1_UPDT_SEL;
+                    }
+                    else
+                    {
+                        r_dcache_pte_update = tlb_data | PTE_R_MASK;
+                        r_dcache_tlb_ll_acc_req = true;
+                        r_dcache_fsm = DCACHE_TLB1_LL_WAIT;
+                        m_cpt_data_tlb_update_acc++;
+                        m_cost_data_tlb_update_acc_frz++;
+                    }
+                }
+            }
+        }
+        else
+        {
+            // DTLB request miss in cache and walk page table level 1
+            r_dcache_tlb_read_req = true;
+            r_dcache_fsm = DCACHE_TLB1_READ;
+        }
+        break;
+    }
+    ///////////////////////
+    case DCACHE_TLB1_LL_WAIT:
+    {
+        if ( dreq.valid ) m_cost_data_tlb_miss_frz++;
+        m_cost_data_tlb_update_acc_frz++;
+	    
+        // external cache invalidate request
+        if ( r_tgt_dcache_req )   
+        {
+            r_dcache_fsm = DCACHE_CC_CHECK;
+            r_dcache_fsm_save = r_dcache_fsm;
+            break;
+        }
+
+	if (!r_dcache_tlb_ll_acc_req)
+	{
+            if ( r_vci_rsp_data_error ) // VCI response ko
+            {
+                if ((r_dcache_type_save == iss_t::DATA_READ)||(r_dcache_type_save == iss_t::DATA_LL))
+                {
+                    r_dcache_error_type = MMU_READ_PT1_ILLEGAL_ACCESS;
+                }
+                else /*if ((dreq.type == iss_t::DATA_WRITE)||(dreq.type == iss_t::DATA_SC))*/
+                {
+                    r_dcache_error_type = MMU_WRITE_PT1_ILLEGAL_ACCESS;
+                } 
+                r_dcache_bad_vaddr = dreq.addr;
+                r_dcache_fsm = DCACHE_ERROR;
+
+		if (r_dcache_inval_tlb_rsp) r_dcache_inval_tlb_rsp = false;
+		if (r_dcache_inval_rsp) r_dcache_inval_rsp = false;		 
+            }
+	    else
+	    {
+		if ( !(r_dcache_miss_buf[0] >> PTE_V_SHIFT) )	// unmapped
+	        {
+               	    if ((r_dcache_type_save == iss_t::DATA_READ)||(r_dcache_type_save == iss_t::DATA_LL))
+               	    {
+               	        r_dcache_error_type = MMU_READ_PT1_UNMAPPED;
+               	    }
+               	    else /*if ((dreq.type == iss_t::DATA_WRITE)||(dreq.type == iss_t::DATA_SC))*/
+               	    {
+               	        r_dcache_error_type = MMU_WRITE_PT1_UNMAPPED;
+               	    }  
+                    r_dcache_bad_vaddr  = dreq.addr;
+                    r_dcache_fsm        = DCACHE_ERROR;
+
+		    if (r_dcache_inval_tlb_rsp) r_dcache_inval_tlb_rsp = false;
+		    if (r_dcache_inval_rsp) r_dcache_inval_rsp = false;	
+	        }
+       		else if ( r_dcache_inval_tlb_rsp )
+       		{
+       		    r_dcache_inval_tlb_rsp = false;
+       		    r_dcache_fsm = DCACHE_IDLE;
+       		}
+		else if ( r_dcache_inval_rsp )
+       		{
+       		    r_dcache_inval_rsp = false;
+       		    r_dcache_fsm = DCACHE_IDLE;
+       		}
+		else
+		{
+		    r_dcache_tlb_sc_acc_req = true;
+		    r_dcache_pte_update = r_dcache_miss_buf[0] | r_dcache_pte_update.read();
+                    r_dcache_fsm = DCACHE_TLB1_SC_WAIT; 
+		}
+	    }
+	}
+	break;
+    }
+    ///////////////////////
+    case DCACHE_TLB1_SC_WAIT:
+    {
+        if ( dreq.valid ) m_cost_data_tlb_miss_frz++;
+        m_cost_data_tlb_update_acc_frz++;	    
+        // external cache invalidate request
+        if ( r_tgt_dcache_req )   
+        {
+            r_dcache_fsm = DCACHE_CC_CHECK;
+            r_dcache_fsm_save = r_dcache_fsm;
+            break;
+        }
+
+	if ( !r_dcache_tlb_sc_acc_req )
+	{
+	    if ( r_vci_rsp_data_error ) // VCI response ko
+	    {
+                if ((r_dcache_type_save == iss_t::DATA_READ)||(r_dcache_type_save == iss_t::DATA_LL))
+                {
+                    r_dcache_error_type = MMU_READ_PT1_ILLEGAL_ACCESS;
+                }
+                else /*if ((dreq.type == iss_t::DATA_WRITE)||(dreq.type == iss_t::DATA_SC))*/
+                {
+                    r_dcache_error_type = MMU_WRITE_PT1_ILLEGAL_ACCESS;
+                } 
+	        r_dcache_bad_vaddr = dreq.addr;
+	        r_dcache_fsm = DCACHE_ERROR; 
+
+		if (r_dcache_inval_tlb_rsp) r_dcache_inval_tlb_rsp = false;
+		if (r_dcache_inval_rsp) r_dcache_inval_rsp = false;	
+	    }
+	    else
+	    {
+        	// Using tlb entry is invalidated 
+        	if ( r_dcache_inval_tlb_rsp )
+        	{
+        	    r_dcache_inval_tlb_rsp = false;
+        	    r_dcache_fsm = DCACHE_IDLE;
+		    if (r_dcache_tlb_sc_fail) r_dcache_tlb_sc_fail = false;
+        	}
+		else if ( r_dcache_inval_rsp )
+        	{
+        	    r_dcache_inval_rsp = false;
+		    if (r_dcache_tlb_sc_fail) r_dcache_tlb_sc_fail = false;
+        	    r_dcache_fsm = DCACHE_IDLE;
+        	}
+	    	else if ( r_dcache_tlb_sc_fail )
+	    	{
+		    r_dcache_tlb_sc_fail = false;
+		    r_dcache_tlb_ll_acc_req = true;
+	    	    r_dcache_fsm = DCACHE_TLB1_LL_WAIT;
+                    m_cpt_data_tlb_update_acc++;
+	    	}
+	    	else 
+	    	{
+		    bool write_hit = r_dcache.write(r_dcache_tlb_paddr,r_dcache_pte_update);  
+                    assert(write_hit && "Write on miss ignores data for data MMU update data access bit"); 
+	    	    r_dcache_fsm = DCACHE_TLB1_UPDT_SEL; 
+		    m_cpt_dcache_data_write++;
+	    	}
+	    }
+	}
+	break;
+    }
+    //////////////////////
+    case DCACHE_TLB1_READ:
+    {
+        if ( dreq.valid ) m_cost_data_tlb_miss_frz++;
+        if ( r_dcache_tlb_ptba_read ) m_cost_data_tlb_update_dirty_frz++;
+
+        // external cache invalidate request
+        if ( r_tgt_dcache_req )   
+        {
+            r_dcache_fsm = DCACHE_CC_CHECK;
+            r_dcache_fsm_save = r_dcache_fsm;
+            break;
+        }        
+
+	if ( !r_dcache_tlb_read_req )
+	{	
+            if ( r_vci_rsp_data_error ) // VCI response ko
+            {
+                if ((r_dcache_type_save == iss_t::DATA_READ)||(r_dcache_type_save == iss_t::DATA_LL))
+                {
+                    r_dcache_error_type = MMU_READ_PT1_ILLEGAL_ACCESS;
+                }
+                else /*if ((dreq.type == iss_t::DATA_WRITE)||(dreq.type == iss_t::DATA_SC))*/
+                {
+                    r_dcache_error_type = MMU_WRITE_PT1_ILLEGAL_ACCESS;
+                } 
+                r_dcache_bad_vaddr = dreq.addr;
+                r_dcache_fsm = DCACHE_ERROR; 
+
+		if (r_dcache_inval_tlb_rsp) r_dcache_inval_tlb_rsp = false;
+		if (r_dcache_inval_rsp) r_dcache_inval_rsp = false;	
+                if ( r_dcache_tlb_ptba_read ) r_dcache_tlb_ptba_read = false;
+		break;
+            }
+
+            if ( r_dcache_inval_tlb_rsp )  // TLB miss response and invalidation
+            {
+                r_dcache_fsm = DCACHE_IDLE; 
+            	r_dcache_inval_tlb_rsp = false;
+                if ( r_dcache_tlb_ptba_read ) r_dcache_tlb_ptba_read = false;
+		break;
+            }
+
+	    if ( r_dcache_inval_rsp ) // TLB miss response and cache invalidation
+	    {
+	        if ( r_dcache_cleanup_req ) break;
+                r_dcache_cleanup_req = true;
+                r_dcache_cleanup_line = r_dcache_tlb_paddr.read() >> (uint32_log2(m_dcache_words) + 2);  
+		m_cpt_cc_cleanup_data++;
+                r_dcache_fsm = DCACHE_IDLE;
+                r_dcache_inval_rsp = false;
+                if ( r_dcache_tlb_ptba_read ) r_dcache_tlb_ptba_read = false;
+                break;
+	    }
+
+	    // TLB miss response and no invalidation
+	    r_dcache_fsm = DCACHE_TLB1_READ_UPDT;
+	}
+        break;
+    }
+    //////////////////////////
+    case DCACHE_TLB1_READ_UPDT:
+    {
+        m_cost_data_tlb_miss_frz++;
+        if ( r_dcache_tlb_ptba_read ) m_cost_data_tlb_update_dirty_frz++;
+
+        // external cache invalidate request
+        if ( r_tgt_dcache_req )   
+        {
+            r_dcache_fsm = DCACHE_CC_CHECK;
+            r_dcache_fsm_save = r_dcache_fsm;
+            break;
+        }        
+
+        // Using tlb entry is invalidated 
+        if ( r_dcache_inval_tlb_rsp )
+        {
+            r_dcache_inval_tlb_rsp = false;
+            r_dcache_fsm = DCACHE_IDLE;
+            if ( r_dcache_tlb_ptba_read ) r_dcache_tlb_ptba_read = false;
+            break;
+        }
+
+        if ( !r_dcache_cleanup_req ) // Miss update and no invalidation
+        {
+            // update dcache
+            data_t   rsp_dtlb_miss = 0;
+            paddr_t  victim_index = 0;
+            size_t way = 0;
+            size_t set = 0;
+
+            // Using tlb entry is in the invalidated cache line  
+            if ( r_dcache_inval_rsp )
+            {
+                r_dcache_cleanup_req = true;
+                r_dcache_cleanup_line = r_dcache_tlb_paddr.read() >> (uint32_log2(m_dcache_words) + 2); 
+	        m_cpt_cc_cleanup_data++;	
+                r_dcache_fsm = DCACHE_IDLE;
+                r_dcache_inval_rsp = false;
+                if ( r_dcache_tlb_ptba_read ) r_dcache_tlb_ptba_read = false;
+                break;
+            }
+
+            bool cleanup_req = r_dcache.find(r_dcache_tlb_paddr, r_dcache_in_itlb, r_dcache_in_dtlb, &way, &set, &victim_index);
+            
+	    if ( cleanup_req )
+	    {	    
+		// ins tlb invalidate verification    
+                r_dcache_itlb_inval_req = r_dcache_in_itlb[m_dcache_sets*way+set];
+                r_dcache_itlb_inval_line = victim_index;
+                r_dcache_in_itlb[way*m_dcache_sets+set] = false;
+
+                // data tlb invalidate verification
+                r_dcache_dtlb_inval_req = r_dcache_in_dtlb[m_dcache_sets*way+set]; 
+                r_dcache_dtlb_inval_line = victim_index;
+                r_dcache_in_dtlb[way*m_dcache_sets+set] = false;
+
+                r_dcache_cleanup_req = true; 
+                r_dcache_cleanup_line = victim_index;
+		m_cpt_cc_cleanup_data++;
+		r_dcache_fsm = DCACHE_TLB_CC_INVAL;
+                r_dcache_fsm_save = r_dcache_fsm;
+		break;
+	    }
+
+	    r_dcache.update(r_dcache_tlb_paddr, way, set, r_dcache_miss_buf);
+            r_dcache.read(r_dcache_tlb_paddr, &rsp_dtlb_miss);	
+	    m_cpt_data_tlb_occup_cache++;
+
+	    if ( !(rsp_dtlb_miss >> PTE_V_SHIFT) )	// unmapped
+	    {
+                r_dcache_ptba_ok    = false;
+                if ((r_dcache_type_save == iss_t::DATA_READ)||(r_dcache_type_save == iss_t::DATA_LL))
+                {
+                    r_dcache_error_type = MMU_READ_PT1_UNMAPPED;
+                }
+                else /*if ((dreq.type == iss_t::DATA_WRITE)||(dreq.type == iss_t::DATA_SC))*/
+                {
+                    r_dcache_error_type = MMU_WRITE_PT1_UNMAPPED;
+                } 
+                r_dcache_bad_vaddr  = dreq.addr;
+                r_dcache_fsm        = DCACHE_ERROR;
+                if ( r_dcache_tlb_ptba_read ) r_dcache_tlb_ptba_read = false;
+	    }
+	    else if ( (rsp_dtlb_miss & PTE_T_MASK) >> PTE_T_SHIFT ) // PTD
+	    {
+                r_dcache_ptba_ok   = true;
+                r_dcache_ptba_save = (paddr_t)(rsp_dtlb_miss & ((1<<(m_paddr_nbits - PAGE_K_NBITS))-1)) << PAGE_K_NBITS;  
+                r_dcache_id1_save  = dreq.addr >> PAGE_M_NBITS;
+                r_dcache_tlb_paddr = (paddr_t)(rsp_dtlb_miss & ((1<<(m_paddr_nbits - PAGE_K_NBITS))-1)) << PAGE_K_NBITS | 
+                                     (paddr_t)(((dreq.addr & PTD_ID2_MASK) >> PAGE_K_NBITS) << 3);
+                if ( r_dcache_tlb_ptba_read )
+                {
+                    paddr_t tlb_dpaddr;
+		    data_t data;
+                    r_dcache_tlb_ptba_read = false;
+		    if (dcache_tlb.translate(dreq.addr, &tlb_dpaddr) && r_dcache.read((paddr_t)(rsp_dtlb_miss & ((1<<(m_paddr_nbits - PAGE_K_NBITS))-1)) << PAGE_K_NBITS | (paddr_t)(((dreq.addr & PTD_ID2_MASK) >> PAGE_K_NBITS) << 3),&data))
+		    {
+                        r_dcache_tlb_ll_dirty_req = true;
+                        r_dcache_fsm = DCACHE_LL_DIRTY_WAIT;
+ 		    }	        
+		    else
+		    {
+		    	r_dcache_fsm = DCACHE_IDLE;
+                    }
+                }
+                else
+                {
+                    r_dcache_fsm = DCACHE_DTLB2_READ_CACHE;
+                }
+	    }
+	    else	// PTE
+	    {
+                r_dcache_ptba_ok = false;
+	        if ( (m_srcid_rw >> 4) == ((r_dcache_tlb_paddr.read() & ((1<<(m_paddr_nbits - PAGE_M_NBITS))-1)) >> (m_paddr_nbits - PAGE_M_NBITS -10)) ) // local
+		{
+		    if ( (rsp_dtlb_miss & PTE_L_MASK ) >> PTE_L_SHIFT ) // L bit is set
+		    {
+                        r_dcache_pte_update = rsp_dtlb_miss;
+                        r_dcache_fsm        = DCACHE_TLB1_UPDT_SEL;
+		    }
+		    else
+		    {
+                        r_dcache_pte_update = rsp_dtlb_miss | PTE_L_MASK;
+                        r_dcache_tlb_ll_acc_req = true;
+                        r_dcache_fsm        = DCACHE_TLB1_LL_WAIT;
+			m_cpt_data_tlb_update_acc++;
+                        m_cost_data_tlb_update_acc_frz++;
+		    }
+    	        }
+		else // remotely
+		{
+		    if ( (rsp_dtlb_miss & PTE_R_MASK ) >> PTE_R_SHIFT ) // R bit is set
+		    {
+                        r_dcache_pte_update = rsp_dtlb_miss;
+                        r_dcache_fsm        = DCACHE_TLB1_UPDT_SEL;
+		    }
+		    else
+		    {
+                        r_dcache_pte_update = rsp_dtlb_miss | PTE_R_MASK;
+                        r_dcache_tlb_ll_acc_req = true;
+                        r_dcache_fsm        = DCACHE_TLB1_LL_WAIT;
+			m_cpt_data_tlb_update_acc++;
+                        m_cost_data_tlb_update_acc_frz++;
+		    }
+		}
+	    }
+        }
+        break;
+    }
+    /////////////////////////
+    case DCACHE_TLB1_UPDT_SEL: 
+    {
+        m_cost_data_tlb_miss_frz++;
+        m_cost_data_tlb_update_acc_frz++;
+	
+        // external cache invalidate request
+        if ( r_tgt_dcache_req )   
+        {
+            r_dcache_fsm = DCACHE_CC_CHECK;
+            r_dcache_fsm_save = r_dcache_fsm;
+            break;
+        }        
+
+        if ( !r_dcache_inval_tlb_rsp && !r_dcache_inval_rsp )
+        {
+	    size_t way = 0;
+	    size_t set = 0;
+            paddr_t victim_index = 0;
+	    bool cleanup = dcache_tlb.select((dreq.addr >> PAGE_M_NBITS),&victim_index,&way,&set);
+	    if (cleanup)
+	    {
+	        r_dcache_dtlb_cleanup_req = true;
+		r_dcache_dtlb_cleanup_line = victim_index;
+		//m_cpt_cc_cleanup_data++;
+	    }
+	    r_dcache_way = way;
+	    r_dcache_set = set;
+            r_dcache_fsm = DCACHE_TLB1_UPDT;
+        }
+        else  
+        {
+            if ( r_dcache_inval_tlb_rsp ) r_dcache_inval_tlb_rsp = false;
+            if ( r_dcache_inval_rsp ) r_dcache_inval_rsp = false;
+            r_dcache_fsm = DCACHE_IDLE;
+        }
+        break;
+    }
+    //////////////////////
+    case DCACHE_TLB1_UPDT: 
+    {
+        m_cost_data_tlb_miss_frz++;
+        m_cost_data_tlb_update_acc_frz++;
+
+	if (r_dcache_dtlb_cleanup_req) r_dcache.setinbit(r_dcache_dtlb_cleanup_line.read() << (uint32_log2(m_dcache_words)+2), r_dcache_in_dtlb, false);
+        bool set_hit = r_dcache.setinbit(r_dcache_tlb_paddr, r_dcache_in_dtlb, true);
+        assert(set_hit && "TLB1_UPDT set hit error");  
+	dcache_tlb.update(r_dcache_pte_update,dreq.addr,r_dcache_way.read(),r_dcache_set.read(),(r_dcache_tlb_paddr.read() >> (uint32_log2(m_dcache_words)+2)));
+        r_dcache_fsm = DCACHE_IDLE;
+	break;
+    }
+    /////////////////////////////
+    case DCACHE_DTLB2_READ_CACHE:
+    {
+        m_cost_data_tlb_miss_frz++;
+
+        // external cache invalidate request
+        if ( r_tgt_dcache_req )   
+        {
+            r_dcache_fsm = DCACHE_CC_CHECK;
+            r_dcache_fsm_save = r_dcache_fsm;
+            break;
+        }        
+
+        // Using tlb entry is invalidated 
+        if ( r_dcache_inval_tlb_rsp )
+        {
+            r_dcache_inval_tlb_rsp = false;
+            r_dcache_fsm = DCACHE_IDLE;
+            break;
+        }
+
+        data_t tlb_data = 0;
+        data_t tlb_data_ppn = 0;
+        bool tlb_hit_cache = r_dcache.read(r_dcache_tlb_paddr, &tlb_data);
+
+	if ( tlb_hit_cache )
+	{
+            bool tlb_hit_ppn = r_dcache.read(r_dcache_tlb_paddr.read()+4, &tlb_data_ppn);
+	    assert(tlb_hit_ppn && "Address of pte[64-32] and pte[31-0] should be successive");
+	}
+
+        // DTLB request hit in cache
+        if ( tlb_hit_cache )
+        {
+	    if ( !(tlb_data >> PTE_V_SHIFT) )	// unmapped
+	    {
+                if ((r_dcache_type_save == iss_t::DATA_READ)||(r_dcache_type_save == iss_t::DATA_LL))
+                {
+                    r_dcache_error_type = MMU_READ_PT2_UNMAPPED;
+                }
+                else /*if ((dreq.type == iss_t::DATA_WRITE)||(dreq.type == iss_t::DATA_SC))*/
+                {
+                    r_dcache_error_type = MMU_WRITE_PT2_UNMAPPED;
+                } 
+                r_dcache_bad_vaddr  = dreq.addr;
+                r_dcache_fsm        = DCACHE_ERROR;
+	    }
+	    else if ( (tlb_data & PTE_T_MASK) >> PTE_T_SHIFT ) //PTD
+	    {
+                r_dcache_pte_update = tlb_data;
+	        r_dcache_ppn_update = tlb_data_ppn;
+		r_dcache_fsm = DCACHE_TLB2_UPDT_SEL;
+	    }
+	    else 
+	    {
+		m_cpt_data_tlb_hit_dcache++;
+	        if ( (m_srcid_rw >> 4) == ((r_dcache_tlb_paddr.read() & ((1<<(m_paddr_nbits - PAGE_M_NBITS))-1)) >> (m_paddr_nbits - PAGE_M_NBITS -10)) ) // local
+		{
+		    if ( (tlb_data & PTE_L_MASK ) >> PTE_L_SHIFT ) // L bit is set
+		    {
+                        r_dcache_pte_update = tlb_data;
+			r_dcache_ppn_update = tlb_data_ppn;
+                        r_dcache_fsm        = DCACHE_TLB2_UPDT_SEL;
+		    }
+		    else
+		    {
+                        r_dcache_pte_update = tlb_data | PTE_L_MASK;
+	        	r_dcache_ppn_update = tlb_data_ppn;
+                        r_dcache_tlb_ll_acc_req = true;
+                        r_dcache_fsm = DCACHE_TLB2_LL_WAIT;
+                        m_cpt_data_tlb_update_acc++;
+                        m_cost_data_tlb_update_acc_frz++;
+		    }
+    	        }
+		else // remotely
+		{
+		    if ( (tlb_data & PTE_R_MASK ) >> PTE_R_SHIFT ) // R bit is set
+		    {
+                        r_dcache_pte_update = tlb_data;
+			r_dcache_ppn_update = tlb_data_ppn;
+                        r_dcache_fsm        = DCACHE_TLB2_UPDT_SEL;
+		    }
+		    else
+		    {
+                        r_dcache_pte_update = tlb_data | PTE_R_MASK;
+	        	r_dcache_ppn_update = tlb_data_ppn;
+                        r_dcache_tlb_ll_acc_req = true;
+                        r_dcache_fsm = DCACHE_TLB2_LL_WAIT;
+                        m_cpt_data_tlb_update_acc++;
+                        m_cost_data_tlb_update_acc_frz++;
+		    }
+		}
+	    }
+        }
+        else
+        {
+            // DTLB request miss in cache and walk page table level 2
+            r_dcache_tlb_read_req = true;
+            r_dcache_fsm = DCACHE_TLB2_READ;
+        }
+        break;
+    }
+    ///////////////////////
+    case DCACHE_TLB2_LL_WAIT:
+    {
+        if ( dreq.valid ) m_cost_data_tlb_miss_frz++;
+        m_cost_data_tlb_update_acc_frz++;
+
+        // external cache invalidate request
+        if ( r_tgt_dcache_req )   
+        {
+            r_dcache_fsm = DCACHE_CC_CHECK;
+            r_dcache_fsm_save = r_dcache_fsm;
+            break;
+        }
+
+	if (!r_dcache_tlb_ll_acc_req)
+	{
+            if ( r_vci_rsp_data_error ) // VCI response ko
+            {
+                if ((r_dcache_type_save == iss_t::DATA_READ)||(r_dcache_type_save == iss_t::DATA_LL))
+                {
+                    r_dcache_error_type = MMU_READ_PT2_ILLEGAL_ACCESS;
+                }
+                else /*if ((dreq.type == iss_t::DATA_WRITE)||(dreq.type == iss_t::DATA_SC))*/
+                {
+                    r_dcache_error_type = MMU_WRITE_PT2_ILLEGAL_ACCESS;
+                } 
+                r_dcache_bad_vaddr = dreq.addr;
+                r_dcache_fsm = DCACHE_ERROR; 
+
+		if (r_dcache_inval_tlb_rsp) r_dcache_inval_tlb_rsp = false;
+		if (r_dcache_inval_rsp) r_dcache_inval_rsp = false;
+            }
+	    else
+	    {
+	        if ( !(r_dcache_miss_buf[0] >> PTE_V_SHIFT) )	// unmapped
+	        {
+               	    if ((r_dcache_type_save == iss_t::DATA_READ)||(r_dcache_type_save == iss_t::DATA_LL))
+               	    {
+               	        r_dcache_error_type = MMU_READ_PT2_UNMAPPED;
+               	    }
+               	    else /*if ((dreq.type == iss_t::DATA_WRITE)||(dreq.type == iss_t::DATA_SC))*/
+               	    {
+               	        r_dcache_error_type = MMU_WRITE_PT2_UNMAPPED;
+               	    } 
+                    r_dcache_bad_vaddr = dreq.addr;
+                    r_dcache_fsm = DCACHE_ERROR;
+
+		    if (r_dcache_inval_tlb_rsp) r_dcache_inval_tlb_rsp = false;
+		    if (r_dcache_inval_rsp) r_dcache_inval_rsp = false;
+	        }
+        	else if ( r_dcache_inval_tlb_rsp )
+        	{
+        	    r_dcache_inval_tlb_rsp = false;
+        	    r_dcache_fsm = DCACHE_IDLE;
+        	}
+		else if ( r_dcache_inval_rsp )
+		{
+        	    r_dcache_inval_rsp = false;
+		    r_dcache_fsm = DCACHE_IDLE;
+		}
+		else
+		{
+		    r_dcache_tlb_sc_acc_req = true;
+		    r_dcache_pte_update = r_dcache_miss_buf[0] | r_dcache_pte_update.read();
+                    r_dcache_fsm = DCACHE_TLB2_SC_WAIT; 
+		}
+	    }
+	}
+	break;
+    }
+    ///////////////////////
+    case DCACHE_TLB2_SC_WAIT:
+    {
+        if ( dreq.valid ) m_cost_data_tlb_miss_frz++;
+        m_cost_data_tlb_update_acc_frz++;	    
+        // external cache invalidate request
+        if ( r_tgt_dcache_req )   
+        {
+            r_dcache_fsm = DCACHE_CC_CHECK;
+            r_dcache_fsm_save = r_dcache_fsm;
+            break;
+        }
+
+	if ( !r_dcache_tlb_sc_acc_req )
+	{
+	    if ( r_vci_rsp_data_error ) // VCI response ko
+	    {
+                if ((r_dcache_type_save == iss_t::DATA_READ)||(r_dcache_type_save == iss_t::DATA_LL))
+                {
+                    r_dcache_error_type = MMU_READ_PT2_ILLEGAL_ACCESS;
+                }
+                else /*if ((dreq.type == iss_t::DATA_WRITE)||(dreq.type == iss_t::DATA_SC))*/
+                {
+                    r_dcache_error_type = MMU_WRITE_PT2_ILLEGAL_ACCESS;
+                } 
+	        r_dcache_bad_vaddr = dreq.addr;
+	        r_dcache_fsm = DCACHE_ERROR; 
+
+		if (r_dcache_inval_tlb_rsp) r_dcache_inval_tlb_rsp = false;
+		if (r_dcache_inval_rsp) r_dcache_inval_rsp = false;	
+	    }
+	    else
+	    { 
+                // Using tlb entry is invalidated 
+                if ( r_dcache_inval_tlb_rsp )
+                {
+                    r_dcache_inval_tlb_rsp = false;
+		    if (r_dcache_tlb_sc_fail) r_dcache_tlb_sc_fail = false;
+                    r_dcache_fsm = DCACHE_IDLE;
+                }
+		else if ( r_dcache_inval_rsp )
+		{
+        	    r_dcache_inval_rsp = false;
+		    if (r_dcache_tlb_sc_fail) r_dcache_tlb_sc_fail = false;
+		    r_dcache_fsm = DCACHE_IDLE;
+		}
+	        else if ( r_dcache_tlb_sc_fail )
+	        {
+	            r_dcache_tlb_ll_acc_req = true;
+		    r_dcache_tlb_sc_fail = false;
+	            r_dcache_fsm = DCACHE_TLB2_LL_WAIT;
+		    m_cpt_data_tlb_update_acc++;
+	        }
+	        else 
+	        {
+		    bool write_hit = r_dcache.write(r_dcache_tlb_paddr,r_dcache_pte_update);  
+                    assert(write_hit && "Write on miss ignores data for data MMU update data access bit"); 
+	            r_dcache_fsm = DCACHE_TLB2_UPDT_SEL; 
+		    m_cpt_dcache_data_write++;
+	        }
+	    }
+	}
+	break;
+    }
+    /////////////////////
+    case DCACHE_TLB2_READ:
+    {
+        m_cost_data_tlb_miss_frz++;
+
+        // external cache invalidate request
+        if ( r_tgt_dcache_req )   
+        {
+            r_dcache_fsm = DCACHE_CC_CHECK;
+            r_dcache_fsm_save = r_dcache_fsm;
+            break;
+        }        
+
+	if ( !r_dcache_tlb_read_req )
+	{
+            if ( r_vci_rsp_data_error ) // VCI response ko
+            {
+                if ((r_dcache_type_save == iss_t::DATA_READ)||(r_dcache_type_save == iss_t::DATA_LL))
+                {
+                    r_dcache_error_type = MMU_READ_PT2_ILLEGAL_ACCESS;
+                }
+                else /*if ((dreq.type == iss_t::DATA_WRITE)||(dreq.type == iss_t::DATA_SC))*/
+                {
+                    r_dcache_error_type = MMU_WRITE_PT2_ILLEGAL_ACCESS;
+                } 
+                r_dcache_bad_vaddr = dreq.addr;
+                r_dcache_fsm = DCACHE_ERROR; 
+
+		if (r_dcache_inval_tlb_rsp) r_dcache_inval_tlb_rsp = false;
+		if (r_dcache_inval_rsp) r_dcache_inval_rsp = false;
+		break;
+            }	
+
+            if ( r_dcache_inval_tlb_rsp )  // TLB miss response and invalidation
+            {
+                r_dcache_fsm = DCACHE_IDLE; 
+                r_dcache_inval_tlb_rsp = false;
+                break;
+            }  
+
+	    if ( r_dcache_inval_rsp ) // TLB miss response and cache invalidation
+	    {
+	        if ( r_dcache_cleanup_req ) break;
+                r_dcache_cleanup_req = true;
+                r_dcache_cleanup_line = r_dcache_tlb_paddr.read() >> (uint32_log2(m_dcache_words) + 2);  
+		m_cpt_cc_cleanup_data++;
+                r_dcache_fsm = DCACHE_IDLE;
+                r_dcache_inval_rsp = false;
+                break;
+	    } 
+
+	    // TLB miss response and no invalidation
+	    r_dcache_fsm = DCACHE_TLB2_READ_UPDT;
+	}	
+        break;
+    }
+    //////////////////////////
+    case DCACHE_TLB2_READ_UPDT:
+    {
+        m_cost_data_tlb_miss_frz++;
+
+        // external cache invalidate request
+        if ( r_tgt_dcache_req )   
+        {
+            r_dcache_fsm = DCACHE_CC_CHECK;
+            r_dcache_fsm_save = r_dcache_fsm;
+            break;
+        }        
+
+        // Using tlb entry is invalidated 
+        if ( r_dcache_inval_tlb_rsp )
+        {
+            r_dcache_inval_tlb_rsp = false;
+            r_dcache_fsm = DCACHE_IDLE;
+            break;
+        }
+
+        if ( !r_dcache_cleanup_req )
+        {
+            // update cache
+            data_t rsp_dtlb_miss;
+            data_t tlb_data_ppn;
+            paddr_t  victim_index = 0;
+            size_t way = 0;
+            size_t set = 0;
+
+            // Using tlb entry is in the invalidated cache line  
+            if ( r_dcache_inval_rsp )
+            {
+                r_dcache_cleanup_req = true;
+                r_dcache_cleanup_line = r_dcache_tlb_paddr.read() >> (uint32_log2(m_dcache_words) + 2);  
+		m_cpt_cc_cleanup_data++;
+                r_dcache_fsm = DCACHE_IDLE;
+                r_dcache_inval_rsp = false;
+                break;
+            }
+
+            bool cleanup_req = r_dcache.find(r_dcache_tlb_paddr, r_dcache_in_itlb, r_dcache_in_dtlb, &way, &set, &victim_index);
+
+	    if ( cleanup_req )
+	    {	    
+		// ins tlb invalidate verification    
+                r_dcache_itlb_inval_req = r_dcache_in_itlb[m_dcache_sets*way+set];
+                r_dcache_itlb_inval_line = victim_index;
+                r_dcache_in_itlb[way*m_dcache_sets+set] = false;
+
+                // data tlb invalidate verification
+                r_dcache_dtlb_inval_req = r_dcache_in_dtlb[m_dcache_sets*way+set]; 
+                r_dcache_dtlb_inval_line = victim_index;
+                r_dcache_in_dtlb[way*m_dcache_sets+set] = false;
+
+                r_dcache_cleanup_req = true; 
+                r_dcache_cleanup_line = victim_index;
+		m_cpt_cc_cleanup_data++;
+		r_dcache_fsm = DCACHE_TLB_CC_INVAL;
+                r_dcache_fsm_save = r_dcache_fsm;
+		break;
+	    }
+
+	    r_dcache.update(r_dcache_tlb_paddr, way, set, r_dcache_miss_buf);
+	    r_dcache.read(r_dcache_tlb_paddr, &rsp_dtlb_miss);
+	    m_cpt_data_tlb_occup_cache++;
+
+	    bool tlb_hit_ppn = r_dcache.read(r_dcache_tlb_paddr.read()+4, &tlb_data_ppn);
+	    assert(tlb_hit_ppn && "Address of pte[64-32] and pte[31-0] should be successive");
+
+	    if ( !(rsp_dtlb_miss >> PTE_V_SHIFT) )	// unmapped
+	    {
+                if ((r_dcache_type_save == iss_t::DATA_READ)||(r_dcache_type_save == iss_t::DATA_LL))
+                {
+                    r_dcache_error_type = MMU_READ_PT2_UNMAPPED;
+                }
+                else /*if ((dreq.type == iss_t::DATA_WRITE)||(dreq.type == iss_t::DATA_SC))*/
+                {
+                    r_dcache_error_type = MMU_WRITE_PT2_UNMAPPED;
+                }  
+                r_dcache_bad_vaddr  = dreq.addr;
+                r_dcache_fsm        = DCACHE_ERROR;
+	    }
+	    else if ( (rsp_dtlb_miss & PTE_T_MASK) >> PTE_T_SHIFT ) // PTD
+	    {
+                r_dcache_pte_update = rsp_dtlb_miss;
+	        r_dcache_ppn_update = tlb_data_ppn;
+		r_dcache_fsm = DCACHE_TLB2_UPDT_SEL;
+	    }
+	    else
+	    {
+	        if ( (m_srcid_rw >> 4) == ((r_dcache_tlb_paddr.read() & ((1<<(m_paddr_nbits - PAGE_M_NBITS))-1)) >> (m_paddr_nbits - PAGE_M_NBITS -10)) ) // local
+		{
+		    if ( (rsp_dtlb_miss & PTE_L_MASK ) >> PTE_L_SHIFT ) // L bit is set
+		    {
+                        r_dcache_pte_update = rsp_dtlb_miss;
+			r_dcache_ppn_update = tlb_data_ppn;
+                        r_dcache_fsm        = DCACHE_TLB2_UPDT_SEL;
+		    }
+		    else
+		    {
+                        r_dcache_pte_update = rsp_dtlb_miss | PTE_L_MASK;
+	        	r_dcache_ppn_update = tlb_data_ppn;
+                        r_dcache_tlb_ll_acc_req = true;
+                        r_dcache_fsm = DCACHE_TLB2_LL_WAIT;
+                        m_cpt_data_tlb_update_acc++;
+                        m_cost_data_tlb_update_acc_frz++;
+		    }
+    	        }
+		else // remotely
+		{
+		    if ( (rsp_dtlb_miss & PTE_R_MASK ) >> PTE_R_SHIFT ) // R bit is set
+		    {
+                        r_dcache_pte_update = rsp_dtlb_miss;
+			r_dcache_ppn_update = tlb_data_ppn;
+                        r_dcache_fsm        = DCACHE_TLB2_UPDT_SEL;
+		    }
+		    else
+		    {
+                        r_dcache_pte_update = rsp_dtlb_miss | PTE_R_MASK;
+	        	r_dcache_ppn_update = tlb_data_ppn;
+                        r_dcache_tlb_ll_acc_req = true;
+                        r_dcache_fsm = DCACHE_TLB2_LL_WAIT;
+                        m_cpt_data_tlb_update_acc++;
+                        m_cost_data_tlb_update_acc_frz++;
+		    }
+		}
+	    }
+        }
+        break;
+    }
+    //////////////////////////
+    case DCACHE_TLB2_UPDT_SEL:  
+    {
+        m_cost_data_tlb_miss_frz++;
+        m_cost_data_tlb_update_acc_frz++;
+
+        // external cache invalidate request
+        if ( r_tgt_dcache_req )   
+        {
+            r_dcache_fsm = DCACHE_CC_CHECK;
+            r_dcache_fsm_save = r_dcache_fsm;
+            break;
+        }        
+
+        if ( !r_dcache_inval_tlb_rsp && !r_dcache_inval_rsp )
+        {
+	    size_t way = 0;
+	    size_t set = 0;
+            paddr_t victim_index = 0;
+	    bool cleanup = dcache_tlb.select((dreq.addr >> PAGE_K_NBITS),&victim_index,&way,&set);
+	    if (cleanup) 
+	    {
+	        r_dcache_dtlb_cleanup_req = true;
+		r_dcache_dtlb_cleanup_line = victim_index;
+		//m_cpt_cc_cleanup_data++;
+	    }
+	    r_dcache_way = way;
+	    r_dcache_set = set;
+            r_dcache_fsm = DCACHE_TLB2_UPDT;
+        }
+        else  
+        {
+            if ( r_dcache_inval_tlb_rsp ) r_dcache_inval_tlb_rsp = false;
+            if ( r_dcache_inval_rsp ) r_dcache_inval_rsp = false;
+            r_dcache_fsm = DCACHE_IDLE;
+        }
+        break;
+    }
+    //////////////////////
+    case DCACHE_TLB2_UPDT:  
+    {
+        m_cost_data_tlb_miss_frz++;
+        m_cost_data_tlb_update_acc_frz++;
+
+	if (r_dcache_dtlb_cleanup_req) r_dcache.setinbit(r_dcache_dtlb_cleanup_line.read() << (uint32_log2(m_dcache_words)+2), r_dcache_in_dtlb, false);
+        bool set_hit = r_dcache.setinbit(r_dcache_tlb_paddr, r_dcache_in_dtlb, true);
+        assert(set_hit && "TLB2_UPDT set hit error");  
+        dcache_tlb.update(r_dcache_pte_update,r_dcache_ppn_update,dreq.addr,r_dcache_way.read(),r_dcache_set.read(),(r_dcache_tlb_paddr.read() >> (uint32_log2(m_dcache_words)+2)));
+        r_dcache_fsm = DCACHE_IDLE;
+	break;
+    }
+    ///////////////////////
+    case DCACHE_CTXT_SWITCH:
+    {
+        // TLB flush leads to cleanup corresponding data cache line 
+        paddr_t victim_index = 0;
+        size_t way = 0;
+        size_t set = 0;
+
+        if ( r_dcache_itlb_cleanup_req )
+        {    
+            r_dcache.setinbit(((paddr_t)r_dcache_itlb_cleanup_line.read() << (uint32_log2(m_dcache_words)+2)), r_dcache_in_itlb, false);
+            r_dcache_itlb_cleanup_req = false;
+	}
+
+        for ( way = 0; way < m_dtlb_ways; way++)
+        {
+            for ( set = 0; set < m_dtlb_sets; set++)
+            {
+                if(dcache_tlb.checkcleanup(way, set, &victim_index))
+                {
+                    r_dcache.setinbit((paddr_t)(victim_index << (uint32_log2(m_dcache_words)+2)), r_dcache_in_dtlb, false); 
+                }
+            }
+        }
+
+        if ( !r_dcache_xtn_req )
+        {
+            r_dcache_fsm = DCACHE_IDLE;
+            r_dtlb_translation_valid = false;
+            r_dcache_ptba_ok = false;
+            drsp.valid = true;
+        }
+        break;
+    }
+    ////////////////////////
+    case DCACHE_ICACHE_FLUSH:
+    case DCACHE_ICACHE_INVAL:
+    case DCACHE_ICACHE_INVAL_PA:
+    case DCACHE_ITLB_INVAL:
+    {
+        // external cache invalidate request
+        if ( r_tgt_dcache_req )   
+        {
+            r_dcache_fsm = DCACHE_CC_CHECK;
+            r_dcache_fsm_save = r_dcache_fsm;
+            break;
+        }  
+        if ( !r_dcache_xtn_req ) 
+        {
+            r_dcache_fsm = DCACHE_IDLE;
+            drsp.valid = true;
+        }
+        break;
+    }
+    ////////////////////////
+    case DCACHE_DCACHE_FLUSH:
+    {
+        // external cache invalidate request
+        if ( r_tgt_dcache_req )   
+        {
+            r_dcache_fsm = DCACHE_CC_CHECK;
+            r_dcache_fsm_save = r_dcache_fsm;
+            break;
+        }  
+        size_t way = r_dcache_way;
+        size_t set = r_dcache_set;
+        bool clean = false;
+        
+        // cache flush and send cleanup to external
+        if ( !r_dcache_cleanup_req )
+        {
+            paddr_t victim_index = 0;
+            for ( ; way < m_dcache_ways; way++ )
+            {    
+                for ( ; set < m_dcache_sets; set++ )
+                {  
+                    if ( r_dcache.flush(way, set, &victim_index) )
+                    {
+                        clean = true;
+                        r_dcache_cleanup_req = true;
+                        r_dcache_cleanup_line = victim_index;
+                        m_cpt_cc_cleanup_data++;
+                        r_dcache_way = way + ((set+1)/m_dcache_sets);
+                        r_dcache_set = (set+1) % m_dcache_sets;
+                        break;
+                    }
+                }
+                if (clean) break;
+                set = 0;
+            }
+
+            if ((way == m_dcache_ways) && !r_dcache_xtn_req ) 
+            {
+                // data TLB flush 
+                dcache_tlb.flush(true);      // global entries are invalidated
+            	r_dtlb_translation_valid = false;
+            	r_dcache_ptba_ok = false;
+
+                for (size_t line = 0; line < m_dcache_ways*m_dcache_sets; line++)
+                {
+                    r_dcache_in_itlb[line] = false;
+                    r_dcache_in_dtlb[line] = false;
+                }
+
+                r_dcache_fsm = DCACHE_IDLE;
+                drsp.valid = true;
+                break;
+            }
+        }
+	break;
+    }
+    //////////////////////
+    case DCACHE_DTLB_INVAL: 
+    {
+        paddr_t victim_index = 0;
+        // clean indicate data tlb bit
+        if ( dcache_tlb.inval(r_dcache_wdata_save, &victim_index) )
+        {  
+            r_dcache.setinbit((paddr_t)(victim_index << (uint32_log2(m_dcache_words)+2)), r_dcache_in_dtlb, false); 
+        }
+        r_dtlb_translation_valid = false;
+        r_dcache_ptba_ok = false;
+        r_dcache_fsm = DCACHE_IDLE;
+        drsp.valid = true;
+        break;
+    }
+    ////////////////////////
+    case DCACHE_DCACHE_INVAL:
+    {
+        // external cache invalidate request
+        if ( r_tgt_dcache_req )   
+        {
+            r_dcache_fsm = DCACHE_CC_CHECK;
+            r_dcache_fsm_save = r_dcache_fsm;
+            break;
+        }  
+
+        m_cpt_dcache_dir_read += m_dcache_ways;
+        vaddr_t invadr = dreq.wdata;
+        paddr_t dpaddr = 0;
+        bool dcache_hit_t = false; 
+        size_t way = 0;
+        size_t set = 0;
+
+	if ( !r_dcache_cleanup_req )
+	{
+            if ( r_mmu_mode.read() & DATA_TLB_MASK ) 
+            {
+                dcache_hit_t = dcache_tlb.translate(invadr, &dpaddr); 
+            } 
+            else 
+            {
+                dpaddr = invadr;  
+                dcache_hit_t = true;
+            }
+
+            if ( dcache_hit_t )
+            {
+		bool dcache_cleanup_req = r_dcache.inval(dpaddr, &way, &set);
+		r_dcache_cleanup_req = dcache_cleanup_req;
+		r_dcache_cleanup_line = dpaddr >> (uint32_log2(m_dcache_words)+2);
+		if (dcache_cleanup_req) m_cpt_cc_cleanup_data++;
+		
+		if ( r_dcache_in_itlb[way*m_dcache_sets+set] || r_dcache_in_dtlb[way*m_dcache_sets+set] ) 
+		{	
+		    // ins tlb invalidate verification
+		    r_dcache_itlb_inval_req = r_dcache_in_itlb[way*m_dcache_sets+set];
+		    r_dcache_itlb_inval_line = dpaddr >> (uint32_log2(m_dcache_words)+2);
+		    r_dcache_in_itlb[way*m_dcache_sets+set] = false;
+		
+		    // data tlb invalidate verification
+		    r_dcache_dtlb_inval_req = r_dcache_in_dtlb[way*m_dcache_sets+set];
+		    r_dcache_dtlb_inval_line = dpaddr >> (uint32_log2(m_dcache_words)+2);
+		    r_dcache_in_dtlb[way*m_dcache_sets+set] = false;
+		    r_dcache_fsm = DCACHE_TLB_CC_INVAL;
+		    r_dcache_fsm_save = r_dcache_fsm;
+		    break;
+		}
+            }
+            r_dcache_fsm = DCACHE_IDLE;
+            drsp.valid = true;
+	}
+        break;
+    }
+    ////////////////////////
+    case DCACHE_DCACHE_INVAL_PA:
+    {
+        // external cache invalidate request
+        if ( r_tgt_dcache_req )   
+        {
+            r_dcache_fsm = DCACHE_CC_CHECK;
+            r_dcache_fsm_save = r_dcache_fsm;
+            break;
+        }  
+        m_cpt_dcache_dir_read += m_dcache_ways;
+        paddr_t dpaddr = (paddr_t)r_mmu_word_hi.read() << 32 | r_mmu_word_lo.read();
+        size_t way = 0;
+        size_t set = 0;
+
+	if ( !r_dcache_cleanup_req )
+	{
+	    bool dcache_cleanup_req = r_dcache.inval(dpaddr, &way, &set);
+	    r_dcache_cleanup_req = dcache_cleanup_req;
+	    r_dcache_cleanup_line = dpaddr >> (uint32_log2(m_dcache_words)+2);
+	    if (dcache_cleanup_req) m_cpt_cc_cleanup_data++;
+	    
+	    if ( r_dcache_in_itlb[way*m_dcache_sets+set] || r_dcache_in_dtlb[way*m_dcache_sets+set] ) 
+	    {	
+	        // ins tlb invalidate verification
+	        r_dcache_itlb_inval_req = r_dcache_in_itlb[way*m_dcache_sets+set];
+	        r_dcache_itlb_inval_line = dpaddr >> (uint32_log2(m_dcache_words)+2);
+	        r_dcache_in_itlb[way*m_dcache_sets+set] = false;
+	    
+	        // data tlb invalidate verification
+	        r_dcache_dtlb_inval_req = r_dcache_in_dtlb[way*m_dcache_sets+set];
+	        r_dcache_dtlb_inval_line = dpaddr >> (uint32_log2(m_dcache_words)+2);
+	        r_dcache_in_dtlb[way*m_dcache_sets+set] = false;
+	        r_dcache_fsm = DCACHE_TLB_CC_INVAL;
+	        r_dcache_fsm_save = r_dcache_fsm;
+	        break;
+	    }
+            r_dcache_fsm = DCACHE_IDLE;
+            drsp.valid = true;
+	}
+        break;
+    }
+    /////////////////////////
+    case DCACHE_DCACHE_SYNC:
+    {
+        // external cache invalidate request
+        if ( r_tgt_dcache_req )   
+        {
+            r_dcache_fsm = DCACHE_CC_CHECK;
+            r_dcache_fsm_save = r_dcache_fsm;
+            break;
+        }  
+        if ( !r_dcache_write_req ) 
+        {
+            r_dcache_write_req = r_wbuf.rok();
+            drsp.valid = true;
+            r_dcache_fsm = DCACHE_IDLE;
+        }    
+        break;
+    }
+    /////////////////////
+    case DCACHE_MISS_WAIT:
+    {
+        m_cost_data_miss_frz++; 
+
+        // external cache invalidate request
+        if ( r_tgt_dcache_req ) 
+        {
+            r_dcache_fsm = DCACHE_CC_CHECK;
+            r_dcache_fsm_save = r_dcache_fsm;
+            break;
+        }
+
+	if ( !r_dcache_miss_req )
+	{
+            if ( r_vci_rsp_data_error ) 
+            {
+                r_dcache_error_type = MMU_READ_DATA_ILLEGAL_ACCESS; 
+                r_dcache_bad_vaddr = dreq.addr;
+                r_dcache_fsm = DCACHE_ERROR;
+
+		if (r_dcache_inval_tlb_rsp) r_dcache_inval_tlb_rsp = false;
+		if (r_dcache_inval_rsp) r_dcache_inval_rsp = false;
+		break;
+            } 
+
+            if ( r_dcache_inval_tlb_rsp ) // Miss read response and tlb invalidation
+            {
+                if ( r_dcache_cleanup_req ) break;
+                r_dcache_cleanup_req = true;
+                r_dcache_cleanup_line = r_dcache_paddr_save.read() >> (uint32_log2(m_dcache_words) + 2);  
+                m_cpt_cc_cleanup_data++;
+                r_dcache_fsm = DCACHE_IDLE;
+                r_dcache_inval_tlb_rsp = false;
+                if ( r_dcache_inval_rsp ) r_dcache_inval_rsp = false;
+                break;
+            }	
+
+	    if ( r_dcache_inval_rsp ) // TLB miss response and cache invalidation
+	    {
+                if ( r_dcache_cleanup_req ) break;
+                r_dcache_cleanup_req = true;
+                r_dcache_cleanup_line = r_dcache_paddr_save.read() >> (uint32_log2(m_dcache_words) + 2);  
+                m_cpt_cc_cleanup_data++;
+                r_dcache_fsm = DCACHE_IDLE;
+                r_dcache_inval_rsp = false;
+                break;
+	    }
+	    // Miss read response and no tlb invalidation
+	    r_dcache_fsm = DCACHE_MISS_UPDT;
+	}	
+        break;
+    }
+    /////////////////////
+    case DCACHE_MISS_UPDT:
+    {
+        m_cost_data_miss_frz++;
+
+        // external cache invalidate request
+        if ( r_tgt_dcache_req ) 
+        {
+            r_dcache_fsm = DCACHE_CC_CHECK;
+            r_dcache_fsm_save = r_dcache_fsm;
+            break;
+        }
+
+        if ( r_dcache_inval_tlb_rsp ) // tlb invalidation
+        {
+            if ( r_dcache_cleanup_req ) break;
+            r_dcache_cleanup_req = true;
+            r_dcache_cleanup_line = r_dcache_paddr_save.read() >> (uint32_log2(m_dcache_words) + 2);  
+            m_cpt_cc_cleanup_data++;
+            r_dcache_inval_tlb_rsp = false;
+            r_dcache_inval_rsp = false;
+            r_dcache_fsm = DCACHE_IDLE;
+            break;
+        }
+
+        if (!r_dcache_cleanup_req ) // Miss update and no invalidation
+        {
+            paddr_t  victim_index = 0;
+            size_t way = 0;
+            size_t set = 0;
+
+            // Using tlb entry is in the invalidated cache line  
+            if ( r_dcache_inval_rsp )
+            {
+                r_dcache_cleanup_req = true;
+                r_dcache_cleanup_line = r_dcache_paddr_save.read() >> (uint32_log2(m_dcache_words) + 2);  
+                m_cpt_cc_cleanup_data++;
+                r_dcache_fsm = DCACHE_IDLE;
+                r_dcache_inval_rsp = false;
+                break;
+            }
+
+            bool cleanup_req = r_dcache.find(r_dcache_paddr_save.read(), r_dcache_in_itlb, r_dcache_in_dtlb, &way, &set, &victim_index);
+
+            if ( cleanup_req )
+            {	    
+                // ins tlb invalidate verification    
+                r_dcache_itlb_inval_req = r_dcache_in_itlb[m_dcache_sets*way+set];
+                r_dcache_itlb_inval_line = victim_index;
+                
+                // data tlb invalidate verification
+                r_dcache_dtlb_inval_req = r_dcache_in_dtlb[m_dcache_sets*way+set]; 
+                r_dcache_dtlb_inval_line = victim_index;
+
+                r_dcache_cleanup_req = true; 
+                r_dcache_cleanup_line = victim_index;
+                m_cpt_cc_cleanup_data++;
+
+                if ( r_dcache_in_itlb[m_dcache_sets*way+set] || r_dcache_in_dtlb[m_dcache_sets*way+set] )
+                {
+                    r_dcache_fsm = DCACHE_TLB_CC_INVAL;
+                    r_dcache_fsm_save = r_dcache_fsm;
+                    r_dcache_in_itlb[way*m_dcache_sets+set] = false;
+                    r_dcache_in_dtlb[way*m_dcache_sets+set] = false;
+                    break;
+                }
+            }
+            m_cpt_dcache_dir_write++;
+            m_cpt_dcache_data_write++;
+            r_dcache.update(r_dcache_paddr_save.read(), way, set, r_dcache_miss_buf);
+            r_dcache_fsm = DCACHE_IDLE;
+        }
+        break;
+    }
+    //////////////////////
+    case DCACHE_UNC_WAIT:
+    {
+        m_cost_unc_read_frz++;
+
+        // external cache invalidate request
+        if ( r_tgt_dcache_req ) 
+        {
+            r_dcache_fsm = DCACHE_CC_CHECK;
+            r_dcache_fsm_save = r_dcache_fsm;
+            break;
+        }
+
+	if ( !r_dcache_unc_req )
+	{
+            if ( r_vci_rsp_data_error ) 
+            {
+                r_dcache_error_type = MMU_READ_DATA_ILLEGAL_ACCESS; 
+                r_dcache_bad_vaddr = dreq.addr;
+                r_dcache_fsm = DCACHE_ERROR;
+
+		if (r_dcache_inval_tlb_rsp) r_dcache_inval_tlb_rsp = false;
+		break;
+            }
+
+            if ( r_dcache_inval_tlb_rsp ) // Miss read response and tlb invalidation
+            {
+                r_dcache_inval_tlb_rsp = false;
+            }
+
+	    drsp.valid = true;
+	    drsp.rdata = r_dcache_miss_buf[0];
+	    r_dcache_fsm = DCACHE_IDLE;
+	}	
+        break;
+    }
+    ///////////////////////
+    case DCACHE_WRITE_UPDT:
+    {
+        m_cost_write_frz++;
+	m_cpt_dcache_data_write++; 
+        size_t way = 0;
+        size_t set = 0;
+	bool write_hit = false;
+        data_t mask = vci_param::be2mask(r_dcache_be_save.read());
+        data_t wdata = (mask & r_dcache_wdata_save) | (~mask & r_dcache_rdata_save);
+        write_hit = r_dcache.write(r_dcache_paddr_save, wdata, &way, &set);
+        assert(write_hit && "Write on miss ignores data");
+        
+        if (r_dcache_in_itlb[way*m_dcache_sets+set] || r_dcache_in_dtlb[m_dcache_sets*way+set])
+        {
+	    // ins tlb invalidate verification    
+            r_dcache_itlb_inval_req = r_dcache_in_itlb[m_dcache_sets*way+set];
+            r_dcache_itlb_inval_line = (r_dcache.get_tag(way, set) * m_dcache_sets) + set;
+            r_dcache_in_itlb[way*m_dcache_sets+set] = false;
+
+            // data tlb invalidate verification
+            r_dcache_dtlb_inval_req = r_dcache_in_dtlb[m_dcache_sets*way+set]; 
+            r_dcache_dtlb_inval_line = (r_dcache.get_tag(way, set) * m_dcache_sets) + set;
+            r_dcache_in_dtlb[way*m_dcache_sets+set] = false;
+
+	    r_dcache_fsm = DCACHE_TLB_CC_INVAL;
+            r_dcache_fsm_save = r_dcache_fsm;
+            break;
+	}
+
+        if ( !r_dcache_dirty_save && (r_mmu_mode.read() & DATA_TLB_MASK) )   
+        {
+            m_cpt_data_tlb_update_dirty++;
+            m_cost_data_tlb_update_dirty_frz++;	
+            if ( dcache_tlb.getpagesize(r_dcache_tlb_way_save, r_dcache_tlb_set_save) )	// 2M page size, one level page table 
+            {		    
+                r_dcache_pte_update = dcache_tlb.getpte(r_dcache_tlb_way_save, r_dcache_tlb_set_save) | PTE_D_MASK;
+                r_dcache_tlb_paddr = (paddr_t)r_mmu_ptpr << (INDEX1_NBITS+2) | (paddr_t)((dreq.addr>>PAGE_M_NBITS)<<2);
+                r_dcache_tlb_ll_dirty_req = true;
+                r_dcache_fsm = DCACHE_LL_DIRTY_WAIT;          
+            }
+            else
+            {   
+                if (r_dcache_hit_p_save) 
+                {
+                    r_dcache_pte_update = dcache_tlb.getpte(r_dcache_tlb_way_save, r_dcache_tlb_set_save) | PTE_D_MASK;
+                    r_dcache_tlb_paddr = (paddr_t)r_dcache_ptba_save|(paddr_t)(((dreq.addr&PTD_ID2_MASK)>>PAGE_K_NBITS) << 3);
+                    r_dcache_tlb_ll_dirty_req = true;
+                    r_dcache_fsm = DCACHE_LL_DIRTY_WAIT;
+                }
+                else
+                {
+                    r_dcache_pte_update = dcache_tlb.getpte(r_dcache_tlb_way_save, r_dcache_tlb_set_save) | PTE_D_MASK;
+		    data_t ptba;
+            	    if (r_dcache.read((paddr_t)r_mmu_ptpr << (INDEX1_NBITS+2) | (paddr_t)((dreq.addr>>PAGE_M_NBITS)<<2), &ptba))
+		    {
+                        r_dcache_tlb_paddr = (paddr_t)(ptba & ((1<<(m_paddr_nbits - PAGE_K_NBITS))-1)) << PAGE_K_NBITS | (paddr_t)(((dreq.addr & PTD_ID2_MASK) >> PAGE_K_NBITS) << 3);
+                    	r_dcache_tlb_ll_dirty_req = true;
+                    	r_dcache_fsm = DCACHE_LL_DIRTY_WAIT;
+		        
+		    }
+		    else
+		    {
+                        r_dcache_tlb_paddr = (paddr_t)r_mmu_ptpr << (INDEX1_NBITS+2) | (paddr_t)((dreq.addr>>PAGE_M_NBITS)<<2);
+                        r_dcache_tlb_ptba_read = true;
+                        r_dcache_fsm = DCACHE_DTLB1_READ_CACHE;
+		    }
+                }
+            }
+        }
+        else
+        {
+            r_dcache_fsm = DCACHE_WRITE_REQ;
+            drsp.valid = true;
+            drsp.rdata = 0;
+        }
+        break;
+    }
+    ////////////////////////
+    case DCACHE_WRITE_DIRTY:
+    {
+	m_cost_data_tlb_update_dirty_frz++;
+
+        // external cache invalidate request
+        if ( r_tgt_dcache_req ) 
+        {
+            r_dcache_fsm = DCACHE_CC_CHECK;
+            r_dcache_fsm_save = r_dcache_fsm;
+            break;
+        }
+
+        if ( r_dcache_inval_tlb_rsp ) // Miss read response and tlb invalidation
+        {
+            r_dcache_fsm = DCACHE_IDLE;
+	    if ( r_dcache_sc_updt_dirty ) r_dcache_sc_updt_dirty = false;
+            r_dcache_inval_tlb_rsp = false;
+	    break;
+        }
+
+	if ( r_dcache_inval_rsp ) // TLB miss response and cache invalidation
+	{
+            r_dcache_fsm = DCACHE_IDLE; 
+	    if ( r_dcache_sc_updt_dirty ) r_dcache_sc_updt_dirty = false;
+            r_dcache_inval_rsp = false;
+	    break;	    
+	}
+
+        dcache_tlb.setdirty(r_dcache_tlb_way_save, r_dcache_tlb_set_save);
+	if (  r_dcache_sc_updt_dirty )
+	{
+	    r_dcache_sc_updt_dirty = false;
+            r_dcache_unc_req = true;
+            r_dcache_fsm = DCACHE_UNC_WAIT;
+            m_cpt_unc_read++;
+	}
+	else
+	{
+            r_dcache_fsm = DCACHE_WRITE_REQ;
+            drsp.valid = true;
+            drsp.rdata = 0;	
+	}	
+        break;
+    }
+    /////////////////
+    case DCACHE_ERROR:
+    {
+        r_vci_rsp_data_error = false;
+        drsp.valid = true;
+        drsp.error = true;
+        drsp.rdata = 0;
+        r_dcache_fsm = DCACHE_IDLE;
+        break;
+    }   
+    ////////////////////// 
+    case DCACHE_ITLB_READ:
+    {
+       if ( dreq.valid ) m_cost_ins_tlb_occup_cache_frz++;
+
+        // external cache invalidate request
+        if ( r_tgt_dcache_req ) 
+        {
+            r_dcache_fsm = DCACHE_CC_CHECK;
+            r_dcache_fsm_save = r_dcache_fsm;
+            break;
+        }
+
+    	if ( !r_dcache_itlb_read_req ) // vci response ok
+        {  
+            if ( r_vci_rsp_data_error )
+            {
+                r_dcache_rsp_itlb_error = true;	
+                r_itlb_read_dcache_req = false;
+                r_vci_rsp_data_error = false;
+                r_dcache_fsm = DCACHE_IDLE;
+
+		if (r_dcache_inval_rsp) r_dcache_inval_rsp = false;
+            }
+	    else if ( r_dcache_inval_rsp ) // TLB miss response and cache invalidation
+	    {
+	        if ( r_dcache_cleanup_req ) break;
+                r_dcache_cleanup_req = true;
+                r_dcache_cleanup_line = r_icache_paddr_save.read() >> (uint32_log2(m_dcache_words) + 2);  
+		m_cpt_cc_cleanup_data++;
+                r_dcache_fsm = DCACHE_IDLE;
+                r_dcache_inval_rsp = false;
+                r_itlb_read_dcache_req = false;
+	        r_itlb_acc_redo_req = true;
+	    }
+	    else
+	    {
+                r_dcache_fsm = DCACHE_ITLB_UPDT;
+	    }
+        }
+	break;    	
+    }
+    //////////////////////
+    case DCACHE_ITLB_UPDT:
+    {
+        if ( dreq.valid ) m_cost_ins_tlb_occup_cache_frz++;  
+
+        // external cache invalidate request
+        if ( r_tgt_dcache_req ) 
+        {
+            r_dcache_fsm = DCACHE_CC_CHECK;
+            r_dcache_fsm_save = r_dcache_fsm;
+            break;
+        }
+
+        if ( !r_dcache_cleanup_req )
+        {
+            data_t rsp_itlb_miss = 0;
+	    data_t rsp_itlb_ppn = 0;
+
+            paddr_t  victim_index = 0;
+            size_t way = 0;
+            size_t set = 0;
+
+	    if ( r_dcache_inval_rsp ) // TLB miss response and cache invalidation
+	    {
+                r_dcache_cleanup_req = true;
+                r_dcache_cleanup_line = r_icache_paddr_save.read() >> (uint32_log2(m_dcache_words) + 2);  
+                m_cpt_cc_cleanup_data++;
+                r_dcache_fsm = DCACHE_IDLE;
+                r_dcache_inval_rsp = false;
+                r_itlb_read_dcache_req = false;
+                r_itlb_acc_redo_req = true;
+                break;
+	    }           
+ 
+            bool cleanup = r_dcache.find(r_icache_paddr_save, r_dcache_in_itlb, r_dcache_in_dtlb, &way, &set, &victim_index);
+
+	    if ( cleanup )
+	    {	    
+                // ins tlb invalidate verification    
+                r_dcache_itlb_inval_req = r_dcache_in_itlb[m_dcache_sets*way+set];
+                r_dcache_itlb_inval_line = victim_index;
+
+                // data tlb invalidate verification
+                r_dcache_dtlb_inval_req = r_dcache_in_dtlb[m_dcache_sets*way+set]; 
+                r_dcache_dtlb_inval_line = victim_index;
+
+                r_dcache_cleanup_req = true; 
+                r_dcache_cleanup_line = victim_index;
+                m_cpt_cc_cleanup_data++;
+		if ( r_dcache_in_itlb[m_dcache_sets*way+set] || r_dcache_in_dtlb[m_dcache_sets*way+set] )
+		{
+		    r_dcache_fsm = DCACHE_TLB_CC_INVAL;
+                    r_dcache_fsm_save = r_dcache_fsm;
+                    r_dcache_in_itlb[way*m_dcache_sets+set] = false;
+                    r_dcache_in_dtlb[way*m_dcache_sets+set] = false;
+		    break;
+		}
+	    }
+
+            r_dcache.update(r_icache_paddr_save, way, set, r_dcache_miss_buf);
+
+            bool set_hit = r_dcache.setinbit(r_icache_paddr_save, r_dcache_in_itlb, true);
+            assert(set_hit && "ITLB_UPDT set hit error");  
+            bool itlb_hit_dcache = r_dcache.read(r_icache_paddr_save, &rsp_itlb_miss);	
+            m_cpt_ins_tlb_occup_cache++; 
+
+	    if ( r_itlb_k_read_dcache && itlb_hit_dcache )
+	    {	
+		r_itlb_k_read_dcache = false;
+            	bool itlb_hit_ppn = r_dcache.read(r_icache_paddr_save.read()+4, &rsp_itlb_ppn);
+		assert(itlb_hit_ppn && "Address of pte[64-32] and pte[31-0] should be successive");
+	    }
+
+            r_dcache_rsp_itlb_miss = rsp_itlb_miss;
+            r_dcache_rsp_itlb_ppn = rsp_itlb_ppn;
+            r_dcache_rsp_itlb_error = false;	
+            r_itlb_read_dcache_req = false;
+            r_dcache_fsm = DCACHE_IDLE;
+        }
+        break;
+    }
+    //////////////////////////
+    case DCACHE_ITLB_LL_WAIT:
+    {
+        if ( dreq.valid ) 
+            m_cost_ins_tlb_occup_cache_frz++;	    
+        
+        // external cache invalidate request
+        if ( r_tgt_dcache_req )   
+        {
+            r_dcache_fsm = DCACHE_CC_CHECK;
+            r_dcache_fsm_save = r_dcache_fsm;
+            break;
+        }
+
+	if (!r_dcache_itlb_ll_acc_req)
+	{
+            if ( r_vci_rsp_data_error ) // VCI response ko
+            {
+                r_dcache_rsp_itlb_error = true;  
+                r_vci_rsp_data_error = false;
+                r_itlb_acc_dcache_req = false;
+                r_dcache_fsm = DCACHE_IDLE;
+                if (r_dcache_inval_rsp) r_dcache_inval_rsp = false;	
+            }
+            else
+            {
+                if ( !(r_dcache_miss_buf[0] >> PTE_V_SHIFT) )	// unmapped
+                {
+                    r_dcache_rsp_itlb_error = true;  
+                    r_itlb_acc_dcache_req = false;
+                    r_dcache_fsm = DCACHE_IDLE;	
+                    if (r_dcache_inval_rsp) r_dcache_inval_rsp = false;	
+                }
+                else if ( r_dcache_inval_rsp )
+                {
+                    r_dcache_inval_rsp = false;
+                    r_dcache_fsm = DCACHE_IDLE;
+                }
+                else
+                {
+                    r_dcache_itlb_sc_acc_req = true;
+                    r_icache_pte_update = r_dcache_miss_buf[0] | r_icache_pte_update.read();	
+                    r_dcache_fsm = DCACHE_ITLB_SC_WAIT; 
+                }
+            }
+	}
+	break;
+    }
+    //////////////////////////
+    case DCACHE_ITLB_SC_WAIT:
+    {
+        if ( dreq.valid ) m_cost_ins_tlb_occup_cache_frz++; 	    
+        // external cache invalidate request
+        if ( r_tgt_dcache_req )   
+        {
+            r_dcache_fsm = DCACHE_CC_CHECK;
+            r_dcache_fsm_save = r_dcache_fsm;
+            break;
+        }
+	
+        if ( !r_dcache_itlb_sc_acc_req ) 
+        {
+            if ( r_vci_rsp_data_error ) // VCI response ko
+            {
+                r_dcache_rsp_itlb_error = true;  
+                r_vci_rsp_data_error = false;
+                r_itlb_acc_dcache_req = false;
+                r_dcache_fsm = DCACHE_IDLE;
+                if (r_dcache_inval_rsp) r_dcache_inval_rsp = false;		
+            }
+            else
+            {
+                if ( r_dcache_inval_rsp )
+                {
+                        r_itlb_acc_dcache_req = false;
+                        r_itlb_acc_redo_req = true;
+                        r_dcache_inval_rsp = false;
+                        r_dcache_fsm = DCACHE_IDLE;
+                        if (r_dcache_tlb_sc_fail) r_dcache_tlb_sc_fail = false;
+                }
+                else if ( r_dcache_tlb_sc_fail )
+                {
+                    r_dcache_tlb_sc_fail = false;
+                    r_dcache_itlb_ll_acc_req = true;
+                    r_dcache_fsm = DCACHE_ITLB_LL_WAIT; 
+                }
+                else 
+                {
+                    bool write_hit = r_dcache.write(r_icache_paddr_save, r_icache_pte_update);
+                    assert(write_hit && "Write on miss ignores data for data MMU update ins access bit");
+                    r_itlb_acc_dcache_req = false;
+                    r_dcache_fsm = DCACHE_IDLE; 
+                }
+            }
+        }
+        break;
+    }
+    /////////////////////
+    case DCACHE_CC_CHECK:   // read directory in case of invalidate or update request
+    {
+        m_cpt_dcache_dir_read += m_dcache_ways;
+        m_cpt_dcache_data_read += m_dcache_ways;
+
+        /* activity counter */
+        if ( (( r_dcache_fsm_save == DCACHE_BIS ) ||( r_dcache_fsm_save == DCACHE_MISS_WAIT ) || ( r_dcache_fsm_save == DCACHE_MISS_UPDT ) ) && ( dreq.valid ) )        
+        {
+            m_cost_data_miss_frz++;
+        }
+        if( (( r_dcache_fsm_save == DCACHE_DTLB1_READ_CACHE ) || ( r_dcache_fsm_save == DCACHE_DTLB2_READ_CACHE ) ||
+             ( r_dcache_fsm_save == DCACHE_TLB1_READ )        || ( r_dcache_fsm_save == DCACHE_TLB2_READ )        ||
+             ( r_dcache_fsm_save == DCACHE_TLB1_LL_WAIT )     || ( r_dcache_fsm_save == DCACHE_TLB2_LL_WAIT )     ||
+             ( r_dcache_fsm_save == DCACHE_TLB1_SC_WAIT )     || ( r_dcache_fsm_save == DCACHE_TLB2_SC_WAIT )     || 
+             ( r_dcache_fsm_save == DCACHE_TLB1_READ_UPDT )   || ( r_dcache_fsm_save == DCACHE_TLB2_READ_UPDT )   ||
+             ( r_dcache_fsm_save == DCACHE_TLB1_UPDT_SEL )    || ( r_dcache_fsm_save == DCACHE_TLB2_UPDT_SEL )) && (dreq.valid) )
+        {
+            m_cost_data_tlb_miss_frz++;
+        }
+
+        if ( ( r_dcache_fsm_save == DCACHE_ITLB_READ ) ||( r_dcache_fsm_save == DCACHE_ITLB_UPDT ) || ( r_dcache_fsm_save == DCACHE_ITLB_LL_WAIT ) || ( r_dcache_fsm_save == DCACHE_ITLB_SC_WAIT ) )        
+        {
+            m_cost_ins_tlb_occup_cache_frz++;
+        }
+
+	// DCACHE_TLB1_LL_WAIT  DCACHE_TLB1_SC_WAIT  DCACHE_LL_DIRTY_WAIT  DCACHE_WRITE_DIRTY DCACHE_ITLB_LL_WAIT  DCACHE_ITLB_SC_WAIT
+	// DCACHE_TLB2_LL_WAIT  DCACHE_TLB2_SC_WAIT  DCACHE_SC_DIRTY_WAIT
+        if((( /*( r_dcache_fsm_save == DCACHE_UNC_WAIT ) ||*/
+	     ( r_dcache_fsm_save == DCACHE_MISS_WAIT ) || ( r_dcache_fsm_save == DCACHE_MISS_UPDT ) ) && 
+           ( (r_dcache_paddr_save.read() & ~((m_dcache_words<<2)-1)) == (r_tgt_addr.read() & ~((m_dcache_words<<2)-1)))) 
+        || (( ( r_dcache_fsm_save == DCACHE_TLB1_READ )      || ( r_dcache_fsm_save == DCACHE_TLB2_READ )      ||
+	     ( r_dcache_fsm_save == DCACHE_TLB1_READ_UPDT ) || ( r_dcache_fsm_save == DCACHE_TLB2_READ_UPDT ) ) && 
+           ( (r_dcache_tlb_paddr.read() & ~((m_dcache_words<<2)-1)) == (r_tgt_addr.read() & ~((m_dcache_words<<2)-1))) ) 
+        || (( ( r_dcache_fsm_save == DCACHE_ITLB_READ ) ) && 
+           ( (r_icache_paddr_save.read() & ~((m_dcache_words<<2)-1)) == (r_tgt_addr.read() & ~((m_dcache_words<<2)-1))) ) ) 
+        {
+            r_dcache_inval_rsp = true;
+            r_tgt_dcache_req = false;
+            if ( r_tgt_update )
+	    {    // Also send a cleanup and answer
+                r_tgt_dcache_rsp = true;
+            } 
+	    else 
+	    {            // Also send a cleanup but don't answer
+                r_tgt_dcache_rsp = false;
+            }
+            r_dcache_fsm = r_dcache_fsm_save;
+        }
+	else
+	{
+            data_t dcache_rdata = 0;
+            size_t way = 0;
+            size_t set = 0;
+
+            bool dcache_hit = r_dcache.read(r_tgt_addr.read(), &dcache_rdata, &way, &set);
+
+            if ( dcache_hit )
+            {
+		if (((( r_dcache_fsm_save == DCACHE_TLB1_UPDT_SEL ) || ( r_dcache_fsm_save == DCACHE_TLB2_UPDT_SEL ) ||
+		      ( r_dcache_fsm_save == DCACHE_TLB1_LL_WAIT )  || ( r_dcache_fsm_save == DCACHE_TLB2_LL_WAIT )  ||
+	              ( r_dcache_fsm_save == DCACHE_TLB1_SC_WAIT )  || ( r_dcache_fsm_save == DCACHE_TLB2_SC_WAIT )  ||
+	              ( r_dcache_fsm_save == DCACHE_LL_DIRTY_WAIT ) || ( r_dcache_fsm_save == DCACHE_SC_DIRTY_WAIT ) ||
+		      ( r_dcache_fsm_save == DCACHE_WRITE_DIRTY )) &&
+	            ((r_dcache_tlb_paddr.read() & ~((m_dcache_words<<2)-1)) == (r_tgt_addr.read() & ~((m_dcache_words<<2)-1)) )) ||
+		    ((( r_dcache_fsm_save == DCACHE_ITLB_UPDT )    ||
+                      ( r_dcache_fsm_save == DCACHE_ITLB_LL_WAIT ) || ( r_dcache_fsm_save == DCACHE_ITLB_SC_WAIT ) ) && 
+                    ((r_icache_paddr_save.read() & ~((m_dcache_words<<2)-1)) == (r_tgt_addr.read() & ~((m_dcache_words<<2)-1)))))
+		{
+		    r_dcache_inval_rsp = true;
+		}
+
+                if ( r_dcache_in_dtlb[m_dcache_sets*way+set] || r_dcache_in_itlb[m_dcache_sets*way+set] )
+                {
+            	    // ins tlb invalidate verification    
+                    r_dcache_itlb_inval_req = r_dcache_in_itlb[m_dcache_sets*way+set];
+                    r_dcache_itlb_inval_line = r_tgt_addr.read() >> (uint32_log2(m_dcache_words)+2);
+                    r_dcache_in_itlb[way*m_dcache_sets+set] = false;
+
+                    // data tlb invalidate verification
+                    r_dcache_dtlb_inval_req = r_dcache_in_dtlb[m_dcache_sets*way+set]; 
+                    r_dcache_dtlb_inval_line = r_tgt_addr.read() >> (uint32_log2(m_dcache_words)+2);
+                    r_dcache_in_dtlb[way*m_dcache_sets+set] = false;
+            	
+            	    r_dcache_cc_check = true;
+            	    r_dcache_fsm = DCACHE_TLB_CC_INVAL;
+            	    break;
+                }
+
+                if ( r_tgt_update ) // update 
+                {
+                    r_dcache_fsm = DCACHE_CC_UPDT;
+                } 
+                else                // invalidate 
+                {
+                    r_dcache_fsm = DCACHE_CC_INVAL;
+                }
+            }
+            else                    // nothing
+            {
+                r_dcache_fsm = DCACHE_CC_NOP;
+            }
+	}
+        break;
+    }
+    ///////////////////
+    case DCACHE_CC_UPDT:    // update directory and data cache        
+    {
+        /* activity counter */
+        if ( (( r_dcache_fsm_save == DCACHE_BIS ) ||( r_dcache_fsm_save == DCACHE_MISS_WAIT ) || ( r_dcache_fsm_save == DCACHE_MISS_UPDT ) ) && ( dreq.valid ) )        
+        {
+            m_cost_data_miss_frz++;
+        }
+        if( (( r_dcache_fsm_save == DCACHE_DTLB1_READ_CACHE ) || ( r_dcache_fsm_save == DCACHE_DTLB2_READ_CACHE ) ||
+             ( r_dcache_fsm_save == DCACHE_TLB1_READ )        || ( r_dcache_fsm_save == DCACHE_TLB2_READ )        ||
+             ( r_dcache_fsm_save == DCACHE_TLB1_LL_WAIT )     || ( r_dcache_fsm_save == DCACHE_TLB2_LL_WAIT )     ||
+             ( r_dcache_fsm_save == DCACHE_TLB1_SC_WAIT )     || ( r_dcache_fsm_save == DCACHE_TLB2_SC_WAIT )     || 
+             ( r_dcache_fsm_save == DCACHE_TLB1_READ_UPDT )   || ( r_dcache_fsm_save == DCACHE_TLB2_READ_UPDT )   ||
+             ( r_dcache_fsm_save == DCACHE_TLB1_UPDT_SEL )    || ( r_dcache_fsm_save == DCACHE_TLB2_UPDT_SEL )) && (dreq.valid) )
+        {
+            m_cost_data_tlb_miss_frz++;
+        }
+
+        if ( ( r_dcache_fsm_save == DCACHE_ITLB_READ ) ||( r_dcache_fsm_save == DCACHE_ITLB_UPDT ) || ( r_dcache_fsm_save == DCACHE_ITLB_LL_WAIT ) || ( r_dcache_fsm_save == DCACHE_ITLB_SC_WAIT ) )        
+        {
+            m_cost_ins_tlb_occup_cache_frz++;
+        }
+
+        m_cpt_dcache_dir_write++;
+        m_cpt_dcache_data_write++;
+        data_t* buf = r_tgt_buf;
+        for( size_t i = 0; i < m_dcache_words; i++ )
+        {
+            if( r_tgt_val[i] ) r_dcache.write( r_tgt_addr.read() + i*4, buf[i] );
+        }
+           
+        r_tgt_dcache_req = false;
+	r_tgt_dcache_rsp = true;
+        r_dcache_fsm = r_dcache_fsm_save;
+        break;
+    }
+    /////////////////////
+    case DCACHE_CC_INVAL:   // invalidate a cache line
+    {
+        /* activity counter */
+        if ( (( r_dcache_fsm_save == DCACHE_BIS ) ||( r_dcache_fsm_save == DCACHE_MISS_WAIT ) || ( r_dcache_fsm_save == DCACHE_MISS_UPDT ) ) && ( dreq.valid ) )        
+        {
+            m_cost_data_miss_frz++;
+        }
+        if( (( r_dcache_fsm_save == DCACHE_DTLB1_READ_CACHE ) || ( r_dcache_fsm_save == DCACHE_DTLB2_READ_CACHE ) ||
+             ( r_dcache_fsm_save == DCACHE_TLB1_READ )        || ( r_dcache_fsm_save == DCACHE_TLB2_READ )        ||
+             ( r_dcache_fsm_save == DCACHE_TLB1_LL_WAIT )     || ( r_dcache_fsm_save == DCACHE_TLB2_LL_WAIT )     ||
+             ( r_dcache_fsm_save == DCACHE_TLB1_SC_WAIT )     || ( r_dcache_fsm_save == DCACHE_TLB2_SC_WAIT )     || 
+             ( r_dcache_fsm_save == DCACHE_TLB1_READ_UPDT )   || ( r_dcache_fsm_save == DCACHE_TLB2_READ_UPDT )   ||
+             ( r_dcache_fsm_save == DCACHE_TLB1_UPDT_SEL )    || ( r_dcache_fsm_save == DCACHE_TLB2_UPDT_SEL )) && (dreq.valid) )
+        {
+            m_cost_data_tlb_miss_frz++;
+        }
+        if ( ( r_dcache_fsm_save == DCACHE_ITLB_READ ) ||( r_dcache_fsm_save == DCACHE_ITLB_UPDT ) || ( r_dcache_fsm_save == DCACHE_ITLB_LL_WAIT ) || ( r_dcache_fsm_save == DCACHE_ITLB_SC_WAIT ) )        
+        {
+            m_cost_ins_tlb_occup_cache_frz++;
+        }
+
+        r_tgt_dcache_rsp = r_dcache.inval(r_tgt_addr.read());
+        r_tgt_dcache_req = false;
+        r_dcache_fsm = r_dcache_fsm_save;
+        break;
+    }
+    ///////////////////
+    case DCACHE_CC_NOP:     // no external hit
+    {
+        /* activity counter */
+        if ( (( r_dcache_fsm_save == DCACHE_BIS ) ||( r_dcache_fsm_save == DCACHE_MISS_WAIT ) || ( r_dcache_fsm_save == DCACHE_MISS_UPDT ) ) && ( dreq.valid ) )        
+        {
+            m_cost_data_miss_frz++;
+        }
+        if( (( r_dcache_fsm_save == DCACHE_DTLB1_READ_CACHE ) || ( r_dcache_fsm_save == DCACHE_DTLB2_READ_CACHE ) ||
+             ( r_dcache_fsm_save == DCACHE_TLB1_READ )        || ( r_dcache_fsm_save == DCACHE_TLB2_READ )        ||
+             ( r_dcache_fsm_save == DCACHE_TLB1_LL_WAIT )     || ( r_dcache_fsm_save == DCACHE_TLB2_LL_WAIT )     ||
+             ( r_dcache_fsm_save == DCACHE_TLB1_SC_WAIT )     || ( r_dcache_fsm_save == DCACHE_TLB2_SC_WAIT )     || 
+             ( r_dcache_fsm_save == DCACHE_TLB1_READ_UPDT )   || ( r_dcache_fsm_save == DCACHE_TLB2_READ_UPDT )   ||
+             ( r_dcache_fsm_save == DCACHE_TLB1_UPDT_SEL )    || ( r_dcache_fsm_save == DCACHE_TLB2_UPDT_SEL )) && (dreq.valid) )
+        {
+            m_cost_data_tlb_miss_frz++;
+        }
+        if ( ( r_dcache_fsm_save == DCACHE_ITLB_READ ) ||( r_dcache_fsm_save == DCACHE_ITLB_UPDT ) || ( r_dcache_fsm_save == DCACHE_ITLB_LL_WAIT ) || ( r_dcache_fsm_save == DCACHE_ITLB_SC_WAIT ) )        
+        {
+            m_cost_ins_tlb_occup_cache_frz++;
+        }
+
+        r_tgt_dcache_req = false;
+        if ( r_tgt_update )
+	{
+            r_tgt_dcache_rsp = true;
+        } 
+	else 
+	{
+            r_tgt_dcache_rsp = false;
+        }
+
+        r_dcache_fsm = r_dcache_fsm_save;
+        break;
+    }   
+    /////////////////////////
+    case DCACHE_TLB_CC_INVAL:
+    {
+        /* activity counter */
+        if ( (( r_dcache_fsm_save == DCACHE_BIS ) ||( r_dcache_fsm_save == DCACHE_MISS_WAIT ) || ( r_dcache_fsm_save == DCACHE_MISS_UPDT ) ) && ( dreq.valid ) )        
+        {
+            m_cost_data_miss_frz++;
+        }
+        if( (( r_dcache_fsm_save == DCACHE_DTLB1_READ_CACHE ) || ( r_dcache_fsm_save == DCACHE_DTLB2_READ_CACHE ) ||
+             ( r_dcache_fsm_save == DCACHE_TLB1_READ )        || ( r_dcache_fsm_save == DCACHE_TLB2_READ )        ||
+             ( r_dcache_fsm_save == DCACHE_TLB1_LL_WAIT )     || ( r_dcache_fsm_save == DCACHE_TLB2_LL_WAIT )     ||
+             ( r_dcache_fsm_save == DCACHE_TLB1_SC_WAIT )     || ( r_dcache_fsm_save == DCACHE_TLB2_SC_WAIT )     || 
+             ( r_dcache_fsm_save == DCACHE_TLB1_READ_UPDT )   || ( r_dcache_fsm_save == DCACHE_TLB2_READ_UPDT )   ||
+             ( r_dcache_fsm_save == DCACHE_TLB1_UPDT_SEL )    || ( r_dcache_fsm_save == DCACHE_TLB2_UPDT_SEL )) && (dreq.valid) )
+        {
+            m_cost_data_tlb_miss_frz++;
+        }
+        if ( ( r_dcache_fsm_save == DCACHE_ITLB_READ ) ||( r_dcache_fsm_save == DCACHE_ITLB_UPDT ) || ( r_dcache_fsm_save == DCACHE_ITLB_LL_WAIT ) || ( r_dcache_fsm_save == DCACHE_ITLB_SC_WAIT ) )        
+        {
+            m_cost_ins_tlb_occup_cache_frz++;
+        }
+
+	if ( r_dcache_itlb_inval_req || r_dcache_dtlb_inval_req ) break;
+
+        if( (( r_dcache_fsm_save == DCACHE_TLB1_READ )        || ( r_dcache_fsm_save == DCACHE_TLB2_READ )        ||
+             ( r_dcache_fsm_save == DCACHE_TLB1_READ_UPDT )   || ( r_dcache_fsm_save == DCACHE_TLB2_READ_UPDT )   ||
+             ( r_dcache_fsm_save == DCACHE_TLB1_LL_WAIT )     || ( r_dcache_fsm_save == DCACHE_TLB2_LL_WAIT )     ||
+             ( r_dcache_fsm_save == DCACHE_TLB1_SC_WAIT )     || ( r_dcache_fsm_save == DCACHE_TLB2_SC_WAIT )     ||
+             ( r_dcache_fsm_save == DCACHE_TLB1_UPDT_SEL )    || ( r_dcache_fsm_save == DCACHE_TLB2_UPDT_SEL )    ||
+             ( r_dcache_fsm_save == DCACHE_DTLB1_READ_CACHE ) || ( r_dcache_fsm_save == DCACHE_DTLB2_READ_CACHE ) ||
+             ( r_dcache_fsm_save == DCACHE_LL_DIRTY_WAIT )    || ( r_dcache_fsm_save == DCACHE_SC_DIRTY_WAIT )    ||
+	     ( r_dcache_fsm_save == DCACHE_WRITE_DIRTY )) && 
+            (((r_dcache_tlb_paddr.read() & ~((m_dcache_words<<2)-1)) >> (uint32_log2(m_dcache_words) + 2)) == r_dcache_dtlb_inval_line.read()) ) 
+        {
+            r_dcache_inval_tlb_rsp = true;
+        } 
+
+        if (((r_dcache_fsm_save == DCACHE_BIS)||(r_dcache_fsm_save == DCACHE_MISS_WAIT) ||
+             (r_dcache_fsm_save == DCACHE_MISS_UPDT)) && 
+             (r_dcache_tlb_nline.read() == r_dcache_dtlb_inval_line.read()))
+        {
+            r_dcache_inval_tlb_rsp = true;
+        }
+
+	if ( !r_dcache_cc_check )
+	{
+            r_dcache_fsm = r_dcache_fsm_save;
+	}
+	else
+	{
+            r_dcache_fsm = DCACHE_CC_CHECK;
+	    r_dcache_cc_check = false;
+	}
+	r_dtlb_translation_valid = false;
+        r_dcache_ptba_ok = false;
+        break;
+    }
+    /////////////////////////
+    case DCACHE_ITLB_CLEANUP:
+    {
+        r_dcache.setinbit(((paddr_t)r_dcache_itlb_cleanup_line.read()<<(uint32_log2(m_dcache_words)+2)), r_dcache_in_itlb, false);
+        r_dcache_itlb_cleanup_req = false;
+        r_dcache_fsm = DCACHE_IDLE;
+        break;
+    }
+    } // end switch r_dcache_fsm
+
+#ifdef SOCLIB_MODULE_DEBUG
+    std::cout << name() << " Data Response: " << drsp << std::endl;
+#endif
+    ////////////////////////////////////////////////////////////////////////////////////
+    //      INVAL DTLB CHECK FSM 
+    ////////////////////////////////////////////////////////////////////////////////////////
+    switch(r_inval_dtlb_fsm) {
+    /////////////////////
+    case INVAL_DTLB_IDLE:
+    {
+        if ( r_dcache_dtlb_inval_req ) 
+        {
+            r_ccinval_dtlb_way = 0;
+            r_ccinval_dtlb_set = 0;
+            r_inval_dtlb_fsm = INVAL_DTLB_CHECK;    
+            m_cost_data_tlb_inval_frz++;
+        }   
+        break;
+    }
+    ////////////////////////////
+    case INVAL_DTLB_CHECK:
+    {
+        m_cost_data_tlb_inval_frz++;
+
+        size_t way = r_ccinval_dtlb_way; 
+        size_t set = r_ccinval_dtlb_set;
+        bool end = false;        
+        bool tlb_hit = dcache_tlb.cccheck(r_dcache_dtlb_inval_line.read(), way, set, &way, &set, &end); 
+    
+        if ( tlb_hit )
+        {
+            r_ccinval_dtlb_way = way; 
+            r_ccinval_dtlb_set = set;
+            r_dtlb_cc_check_end = end;
+            r_inval_dtlb_fsm = INVAL_DTLB_INVAL;
+            m_cpt_data_tlb_inval++;    
+        }        
+        else
+        {
+            r_inval_dtlb_fsm = INVAL_DTLB_CLEAR;    
+        }
+        break;
+    }
+    /////////////////////////
+    case INVAL_DTLB_INVAL:
+    {
+        m_cost_data_tlb_inval_frz++;
+
+        dcache_tlb.ccinval(r_ccinval_dtlb_way, r_ccinval_dtlb_set);
+
+        if ( !r_dtlb_cc_check_end )
+        {
+            r_inval_dtlb_fsm = INVAL_DTLB_CHECK; 
+        }
+        else
+        {
+            r_inval_dtlb_fsm = INVAL_DTLB_CLEAR;    
+        }
+        break;
+    }
+    ////////////////////
+    case INVAL_DTLB_CLEAR:
+    {
+        r_dcache_dtlb_inval_req = false;
+        r_dtlb_cc_check_end = false;
+        r_ccinval_dtlb_way = 0; 
+        r_ccinval_dtlb_set = 0; 
+        r_inval_dtlb_fsm = INVAL_DTLB_IDLE;   
+        m_cpt_data_tlb_inval++;    
+        break;
+    }
+    } // end switch r_inval_itlb_fsm
+
+    /////////// execute one iss cycle /////////////////////////////////
+    {
+    uint32_t it = 0;
+    for (size_t i=0; i<(size_t)iss_t::n_irq; i++) if(p_irq[i].read()) it |= (1<<i);
+    m_iss.executeNCycles(1, irsp, drsp, it);
+    }
+
+    ////////////// number of frozen cycles //////////////////////////
+    if ( (ireq.valid && !irsp.valid) || (dreq.valid && !drsp.valid) )
+    {
+        m_cpt_frz_cycles++;
+    }
+    if ( dreq.valid && !drsp.valid ) 
+    {
+        m_cpt_dcache_frz_cycles++;
+    }
+#ifdef EVALUATION_CACHE
+    for (size_t way = 0; way < m_dcache_ways; way++ )
+    {    
+        for (size_t set = 0; set < m_dcache_sets; set++ )
+        {
+	    if (r_dcache_in_itlb[way*m_dcache_sets+set] || r_dcache_in_dtlb[way*m_dcache_sets+set])
+		m_cpt_tlb_occup_dcache++;
+	}
+    }
+#endif
+    ////////////////////////////////////////////////////////////////////////////
+    //     VCI_CMD FSM 
+    //
+    // This FSM handles requests from both the DCACHE controler
+    // (request registers) and the ICACHE controler (request registers).
+    // There is 10 VCI transaction types :
+    // - INS_TLB_READ
+    // - INS_TLB_WRITE
+    // - INS_MISS
+    // - INS_UNC_MISS
+    // - DATA_TLB_READ
+    // - DATA_TLB_WRITE
+    // - DATA_TLB_DIRTY
+    // - DATA_MISS
+    // - DATA_UNC 
+    // - DATA_WRITE
+    // The ICACHE requests have the highest priority.
+    // There is at most one (CMD/RSP) VCI transaction, as both CMD_FSM and RSP_FSM
+    // exit simultaneously the IDLE state.
+    //////////////////////////////////////////////////////////////////////////////
+
+    switch (r_vci_cmd_fsm) {
+    
+    case CMD_IDLE:
+        if (r_vci_rsp_fsm != RSP_IDLE)
+            break;
+
+        r_vci_cmd_cpt = 0;
+
+        if ( (r_dcache_cleanup_req && r_dcache_itlb_read_req && (((r_icache_paddr_save.read() & ~((m_dcache_words<<2)-1)) >> (uint32_log2(m_dcache_words) + 2)) == r_dcache_cleanup_line.read())) 
+             || (r_dcache_cleanup_req && r_dcache_tlb_read_req && (((r_dcache_tlb_paddr.read() & ~((m_dcache_words<<2)-1)) >> (uint32_log2(m_dcache_words) + 2)) == r_dcache_cleanup_line.read()))
+             || (r_dcache_cleanup_req && r_dcache_miss_req && (((r_dcache_paddr_save.read() & ~((m_dcache_words<<2)-1)) >> (uint32_log2(m_dcache_words) + 2)) == r_dcache_cleanup_line.read()))
+             || (r_icache_cleanup_req && r_icache_miss_req && (((r_icache_paddr_save.read() & ~((m_icache_words<<2)-1)) >> (uint32_log2(m_icache_words) + 2)) == r_icache_cleanup_line.read())) )
+        {
+            break;
+        }
+
+        if (r_dcache_itlb_read_req)           
+        {            
+            r_vci_cmd_fsm = CMD_ITLB_READ;
+            m_cpt_itlbmiss_transaction++; 
+        } 
+        else if (r_dcache_itlb_ll_acc_req)
+        {
+            r_vci_cmd_fsm = CMD_ITLB_ACC_LL;
+            m_cpt_itlb_ll_transaction++; 
+        }
+        else if (r_dcache_itlb_sc_acc_req)
+        {
+            r_vci_cmd_fsm = CMD_ITLB_ACC_SC;
+            m_cpt_itlb_sc_transaction++; 
+        }
+        else if (r_icache_miss_req) 
+        {    
+            r_vci_cmd_fsm = CMD_INS_MISS;
+            m_cpt_imiss_transaction++; 
+        }
+        else if (r_icache_unc_req) 
+        {    
+            r_vci_cmd_fsm = CMD_INS_UNC;
+            m_cpt_icache_unc_transaction++; 
+        }  
+        else if (r_dcache_tlb_read_req) 
+        {            
+            r_vci_cmd_fsm = CMD_DTLB_READ;
+            m_cpt_dtlbmiss_transaction++; 
+        } 
+        else if (r_dcache_tlb_ll_acc_req) 
+        {  
+            r_vci_cmd_fsm = CMD_DTLB_ACC_LL;
+            m_cpt_dtlb_ll_transaction++; 
+        } 
+        else if (r_dcache_tlb_sc_acc_req) 
+        {  
+            r_vci_cmd_fsm = CMD_DTLB_ACC_SC;
+            m_cpt_dtlb_sc_transaction++; 
+        } 
+        else if (r_dcache_tlb_ll_dirty_req) 
+        {  
+            r_vci_cmd_fsm = CMD_DTLB_DIRTY_LL;
+            m_cpt_dtlb_ll_dirty_transaction++; 
+        } 
+        else if (r_dcache_tlb_sc_dirty_req) 
+        {  
+            r_vci_cmd_fsm = CMD_DTLB_DIRTY_SC;
+            m_cpt_dtlb_sc_dirty_transaction++; 
+        } 
+        else if (r_dcache_write_req)
+        {
+            r_vci_cmd_fsm = CMD_DATA_WRITE;
+            r_vci_cmd_cpt = r_wbuf.getMin();
+            r_vci_cmd_min = r_wbuf.getMin();
+            r_vci_cmd_max = r_wbuf.getMax(); 
+            m_cpt_write_transaction++; 
+            m_length_write_transaction += (r_wbuf.getMax() - r_wbuf.getMin() + 1);
+        }
+        else if (r_dcache_miss_req)  
+        {
+            r_vci_cmd_fsm = CMD_DATA_MISS;
+            m_cpt_dmiss_transaction++; 
+        }
+        else if (r_dcache_unc_req)  
+        {
+            r_vci_cmd_fsm = CMD_DATA_UNC;
+            m_cpt_unc_transaction++; 
+        }
+        break;
+
+    case CMD_DATA_WRITE:
+        if ( p_vci_ini_rw.cmdack.read() ) 
+        {
+            r_vci_cmd_cpt = r_vci_cmd_cpt + 1;
+            if (r_vci_cmd_cpt == r_vci_cmd_max) 
+            {
+                r_vci_cmd_fsm = CMD_IDLE;
+                r_wbuf.reset();
+            }
+        }
+        break;
+
+    default:
+        if ( p_vci_ini_rw.cmdack.read() )
+        {  
+            r_vci_cmd_fsm = CMD_IDLE;
+        }
+        break;
+
+    } // end  switch r_vci_cmd_fsm
+
+    //////////////////////////////////////////////////////////////////////////
+    //      VCI_RSP FSM 
+    //
+    // This FSM is synchronized with the VCI_CMD FSM, as both FSMs exit the
+    // IDLE state simultaneously.
+    //////////////////////////////////////////////////////////////////////////
+
+    switch (r_vci_rsp_fsm) {
+
+    case RSP_IDLE:
+        assert( !p_vci_ini_rw.rspval.read() && "Unexpected response" );
+
+        if (r_vci_cmd_fsm != CMD_IDLE)
+            break;
+
+        r_vci_rsp_cpt = 0;
+
+	if ( (r_dcache_cleanup_req && r_dcache_itlb_read_req && (((r_icache_paddr_save.read() & ~((m_dcache_words<<2)-1)) >> (uint32_log2(m_dcache_words) + 2)) == r_dcache_cleanup_line.read())) 
+	  || (r_dcache_cleanup_req && r_dcache_tlb_read_req && (((r_dcache_tlb_paddr.read() & ~((m_dcache_words<<2)-1)) >> (uint32_log2(m_dcache_words) + 2)) == r_dcache_cleanup_line.read()))
+	  || (r_dcache_cleanup_req && r_dcache_miss_req && (((r_dcache_paddr_save.read() & ~((m_dcache_words<<2)-1)) >> (uint32_log2(m_dcache_words) + 2)) == r_dcache_cleanup_line.read()))
+	  || (r_icache_cleanup_req && r_icache_miss_req && (((r_icache_paddr_save.read() & ~((m_icache_words<<2)-1)) >> (uint32_log2(m_icache_words) + 2)) == r_icache_cleanup_line.read())) )
+	{
+	    break;
+	}
+
+        if (r_dcache_itlb_read_req)          // ITLB miss response
+        {            
+            r_vci_rsp_fsm = RSP_ITLB_READ;
+        } 
+        else if (r_dcache_itlb_ll_acc_req)   // ITLB linked load response
+        {   
+            r_vci_rsp_fsm = RSP_ITLB_ACC_LL;
+        } 
+        else if (r_dcache_itlb_sc_acc_req)   // ITLB store conditional response
+        {   
+            r_vci_rsp_fsm = RSP_ITLB_ACC_SC;
+        } 
+        else if (r_icache_miss_req)          // ICACHE cached miss response
+        {   
+            r_vci_rsp_fsm = RSP_INS_MISS;
+        }
+        else if (r_icache_unc_req)           // ICACHE uncached miss response
+        {   
+            r_vci_rsp_fsm = RSP_INS_UNC;
+        }  
+        else if (r_dcache_tlb_read_req)      // ITLB miss response
+        {
+            r_vci_rsp_fsm = RSP_DTLB_READ; 
+        }
+        else if (r_dcache_tlb_ll_acc_req)    // DTLB access bits linked load response
+        {
+            r_vci_rsp_fsm = RSP_DTLB_ACC_LL; 
+        }
+        else if (r_dcache_tlb_sc_acc_req)    // DTLB access bits store conditional response
+        {
+            r_vci_rsp_fsm = RSP_DTLB_ACC_SC; 
+        }
+        else if (r_dcache_tlb_ll_dirty_req)  // DTLB dirty bit linked load response
+        {
+            r_vci_rsp_fsm = RSP_DTLB_DIRTY_LL; 
+        }
+        else if (r_dcache_tlb_sc_dirty_req)  // DTLB dirty bit store conditional response
+        {
+            r_vci_rsp_fsm = RSP_DTLB_DIRTY_SC; 
+        }
+        else if (r_dcache_write_req)         // DCACHE write response
+        {
+            r_vci_rsp_fsm = RSP_DATA_WRITE;
+        }
+        else if (r_dcache_miss_req)          // DCACHE read response
+        {
+            r_vci_rsp_fsm = RSP_DATA_MISS;
+        }
+        else if (r_dcache_unc_req)           // DCACHE uncached read response
+        {
+            r_vci_rsp_fsm = RSP_DATA_UNC;
+        }
+        break;
+
+    case RSP_ITLB_READ:
+        m_cost_itlbmiss_transaction++;
+        if ( ! p_vci_ini_rw.rspval.read() )
+            break;
+
+        assert(r_vci_rsp_cpt != m_dcache_words &&
+               "illegal VCI response packet for data read miss");
+
+        r_vci_rsp_cpt = r_vci_rsp_cpt + 1;
+        r_dcache_miss_buf[r_vci_rsp_cpt] = (data_t)p_vci_ini_rw.rdata.read();
+        if ( p_vci_ini_rw.reop.read() ) 
+        {
+            assert(r_vci_rsp_cpt == m_dcache_words - 1 &&
+                    "illegal VCI response packet for data read miss");
+            r_dcache_itlb_read_req = false;
+            r_vci_rsp_fsm = RSP_IDLE;
+        } 
+        if ( (p_vci_ini_rw.rerror.read() % 1) != vci_param::ERR_NORMAL )
+        {
+            r_vci_rsp_data_error = true;
+        }
+        break;
+
+    case RSP_ITLB_ACC_LL:
+	m_cost_itlb_ll_transaction++;
+        if ( ! p_vci_ini_rw.rspval.read() )
+            break;
+
+        assert(p_vci_ini_rw.reop.read() &&
+               "illegal VCI response packet for ll tlb");
+
+        if ( (p_vci_ini_rw.rerror.read() % 1) != vci_param::ERR_NORMAL ) 
+        {
+            r_vci_rsp_data_error = true;
+        }
+	else
+	{
+	    r_dcache_miss_buf[0] = (data_t)p_vci_ini_rw.rdata.read();
+	}
+        r_dcache_itlb_ll_acc_req = false;
+        r_vci_rsp_fsm = RSP_IDLE;
+	break;
+
+    case RSP_ITLB_ACC_SC:
+	m_cost_itlb_sc_transaction++;
+        if ( ! p_vci_ini_rw.rspval.read() )
+            break;
+
+        assert(p_vci_ini_rw.reop.read() &&
+               "illegal VCI response packet for sc tlb");
+
+        if ( (p_vci_ini_rw.rerror.read() % 1) != vci_param::ERR_NORMAL ) 
+        {
+            r_vci_rsp_data_error = true;
+        }
+	else if ( p_vci_ini_rw.rdata.read() == 1 ) // store conditional is not successful
+	{
+	    r_dcache_tlb_sc_fail = true;
+	    //r_dcache_itlb_ll_acc_req = true;
+	}
+        r_dcache_itlb_sc_acc_req = false;
+        r_vci_rsp_fsm = RSP_IDLE;
+	break;
+
+    case RSP_INS_MISS:
+        m_cost_imiss_transaction++;
+        if ( ! p_vci_ini_rw.rspval.read() )
+            break;
+
+        assert( (r_vci_rsp_cpt < m_icache_words) && 
+               "The VCI response packet for instruction miss is too long");
+        r_vci_rsp_cpt = r_vci_rsp_cpt + 1;
+        r_icache_miss_buf[r_vci_rsp_cpt] = (data_t)p_vci_ini_rw.rdata.read();
+
+        if ( p_vci_ini_rw.reop.read() ) 
+        {
+            assert( (r_vci_rsp_cpt == m_icache_words - 1) &&
+                       "The VCI response packet for instruction miss is too short");
+            r_icache_miss_req = false;
+            r_vci_rsp_fsm = RSP_IDLE;
+                
+        } 
+        if ( (p_vci_ini_rw.rerror.read() % 1) != vci_param::ERR_NORMAL )
+        {
+            r_vci_rsp_ins_error = true;
+        }
+        break;
+
+    case RSP_INS_UNC:
+        m_cost_icache_unc_transaction++;
+        if ( ! p_vci_ini_rw.rspval.read() )
+            break;
+
+        assert(p_vci_ini_rw.reop.read() &&
+               "illegal VCI response packet for uncached instruction");
+
+        r_icache_miss_buf[0] = (data_t)p_vci_ini_rw.rdata.read();
+        r_icache_buf_unc_valid = true;
+        r_icache_unc_req = false;
+        r_vci_rsp_fsm = RSP_IDLE;
+
+        if ( (p_vci_ini_rw.rerror.read() % 1) != vci_param::ERR_NORMAL )
+        {
+            r_vci_rsp_ins_error = true;
+        }
+        break;
+
+    case RSP_DTLB_READ:
+        m_cost_dtlbmiss_transaction++;
+        if ( ! p_vci_ini_rw.rspval.read() )
+            break;
+
+        assert(r_vci_rsp_cpt != m_dcache_words &&
+               "illegal VCI response packet for data read miss");
+
+        r_vci_rsp_cpt = r_vci_rsp_cpt + 1;
+        r_dcache_miss_buf[r_vci_rsp_cpt] = (data_t)p_vci_ini_rw.rdata.read();
+        if ( p_vci_ini_rw.reop.read() ) 
+        {
+            assert(r_vci_rsp_cpt == m_dcache_words - 1 &&
+                    "illegal VCI response packet for data read miss");
+            r_dcache_tlb_read_req = false;
+            r_vci_rsp_fsm = RSP_IDLE;
+        } 
+        if ( (p_vci_ini_rw.rerror.read() % 1) != vci_param::ERR_NORMAL )
+        {
+            r_vci_rsp_data_error = true;
+        }
+        break;
+
+    case RSP_DTLB_ACC_LL:
+	m_cost_dtlb_ll_transaction++; 
+        if ( ! p_vci_ini_rw.rspval.read() )
+            break;
+
+        assert(p_vci_ini_rw.reop.read() &&
+               "illegal VCI response packet for ll tlb");
+
+        if ( (p_vci_ini_rw.rerror.read() % 1) != vci_param::ERR_NORMAL ) 
+        {
+            r_vci_rsp_data_error = true;
+        }
+	else
+	{
+	    r_dcache_miss_buf[0] = (data_t)p_vci_ini_rw.rdata.read();
+	}
+        r_dcache_tlb_ll_acc_req = false;
+        r_vci_rsp_fsm = RSP_IDLE;
+	break;
+
+    case RSP_DTLB_ACC_SC:
+	m_cost_dtlb_sc_transaction++;
+        if ( ! p_vci_ini_rw.rspval.read() )
+            break;
+
+        assert(p_vci_ini_rw.reop.read() &&
+               "illegal VCI response packet for sc tlb");
+
+        if ( (p_vci_ini_rw.rerror.read()  % 1 )!= vci_param::ERR_NORMAL ) 
+        {
+            r_vci_rsp_data_error = true;
+        }
+	else if ( p_vci_ini_rw.rdata.read() == 1 ) // store conditional is not successful
+	{
+	    r_dcache_tlb_sc_fail = true;
+	}
+        r_dcache_tlb_sc_acc_req = false;
+        r_vci_rsp_fsm = RSP_IDLE;
+	break;
+
+    case RSP_DTLB_DIRTY_LL:
+	m_cost_dtlb_ll_dirty_transaction++; 
+        if ( ! p_vci_ini_rw.rspval.read() )
+            break;
+
+        assert(p_vci_ini_rw.reop.read() &&
+               "illegal VCI response packet for ll tlb");
+
+        if ( (p_vci_ini_rw.rerror.read() % 1) != vci_param::ERR_NORMAL ) 
+        {
+            r_vci_rsp_data_error = true;
+        }
+	else
+	{
+	    r_dcache_miss_buf[0] = (data_t)p_vci_ini_rw.rdata.read();
+	}
+        r_dcache_tlb_ll_dirty_req = false;
+        r_vci_rsp_fsm = RSP_IDLE;
+	break;
+
+    case RSP_DTLB_DIRTY_SC:
+	m_cost_dtlb_sc_dirty_transaction++; 
+        if ( ! p_vci_ini_rw.rspval.read() )
+            break;
+
+        assert(p_vci_ini_rw.reop.read() &&
+               "illegal VCI response packet for sc tlb");
+
+        if ( (p_vci_ini_rw.rerror.read() % 1) != vci_param::ERR_NORMAL ) 
+        {
+            r_vci_rsp_data_error = true;
+        }
+	else if ( p_vci_ini_rw.rdata.read() == 1 ) // store conditional is not successful
+	{
+	    r_dcache_tlb_sc_fail = true;
+	}
+        r_dcache_tlb_sc_dirty_req = false;
+        r_vci_rsp_fsm = RSP_IDLE;
+	break;
+
+    case RSP_DATA_UNC:
+        m_cost_unc_transaction++;
+        if ( ! p_vci_ini_rw.rspval.read() ) 
+            break;
+
+        assert(p_vci_ini_rw.reop.read() &&
+               "illegal VCI response packet for data read uncached");
+
+        if ( (p_vci_ini_rw.rerror.read() % 1) != vci_param::ERR_NORMAL ) 
+        {
+            r_vci_rsp_data_error = true;
+        }
+        else
+        {
+            r_dcache_miss_buf[0] = (data_t)p_vci_ini_rw.rdata.read();
+            r_dcache_buf_unc_valid = true;
+        }
+        r_dcache_unc_req = false;
+        r_vci_rsp_fsm = RSP_IDLE;
+        break;
+
+    case RSP_DATA_MISS:
+        m_cost_dmiss_transaction++;
+        if ( ! p_vci_ini_rw.rspval.read() )
+            break;
+
+        assert(r_vci_rsp_cpt != m_dcache_words &&
+               "illegal VCI response packet for data read miss");
+
+        r_vci_rsp_cpt = r_vci_rsp_cpt + 1;
+        r_dcache_miss_buf[r_vci_rsp_cpt] = (data_t)p_vci_ini_rw.rdata.read();
+        if ( p_vci_ini_rw.reop.read() ) 
+        {
+            assert(r_vci_rsp_cpt == m_dcache_words - 1 &&
+                    "illegal VCI response packet for data read miss");
+            r_dcache_miss_req = false;
+            r_vci_rsp_fsm = RSP_IDLE;
+        } 
+        if ( (p_vci_ini_rw.rerror.read() % 1) != vci_param::ERR_NORMAL )
+        {
+            r_vci_rsp_data_error = true;
+        }
+        break;
+
+    case RSP_DATA_WRITE:
+        m_cost_write_transaction++;
+        if ( ! p_vci_ini_rw.rspval.read() )
+            break;
+
+        if ( p_vci_ini_rw.reop.read() ) 
+        {
+            r_vci_rsp_fsm = RSP_IDLE;
+            r_dcache_write_req = false;
+        }
+        if ( (p_vci_ini_rw.rerror.read() % 1) != vci_param::ERR_NORMAL ) 
+        {
+            m_iss.setWriteBerr();
+        }
+        break;
+    } // end switch r_vci_rsp_fsm
+
+    //////////////////////////////////////////////////////////////////////////
+    //      CLEANUP CMD FSM 
+    //
+    // This FSM is synchronized with the CLEANUP RSP FSM, as both FSMs exit the
+    // IDLE state simultaneously.
+    //////////////////////////////////////////////////////////////////////////
+
+    switch (r_cleanup_cmd_fsm) {
+    
+    case CLEANUP_CMD_IDLE:
+        if (r_cleanup_rsp_fsm != CLEANUP_RSP_IDLE)
+            break;
+
+        if (r_dcache_cleanup_req)
+        {
+            r_cleanup_cmd_fsm = CLEANUP_CMD_DATA;
+	        m_cpt_dcleanup_transaction++;
+        }
+        else if (r_icache_cleanup_req)
+        {
+            r_cleanup_cmd_fsm = CLEANUP_CMD_INS;
+	        m_cpt_icleanup_transaction++;
+        }
+        break;
+
+    default:
+        if ( p_vci_ini_c.cmdack.read() )
+        {  
+            r_cleanup_cmd_fsm = CLEANUP_CMD_IDLE;
+        }
+        break;
+
+    } // end  switch r_vci_cmd_fsm
+
+    //////////////////////////////////////////////////////////////////////////
+    //      CLEANUP RSP FSM 
+    //
+    // This FSM is synchronized with the CLEANUP CMD FSM, as both FSMs exit the
+    // IDLE state simultaneously.
+    //////////////////////////////////////////////////////////////////////////
+
+    switch (r_cleanup_rsp_fsm) {
+
+    case CLEANUP_RSP_IDLE:	
+    {
+        assert(!p_vci_ini_c.rspval.read() && "Unexpected response" );
+
+        if (r_cleanup_cmd_fsm != CLEANUP_CMD_IDLE)
+            break;
+
+        if (r_dcache_cleanup_req)
+        {
+            r_cleanup_rsp_fsm = CLEANUP_RSP_DATA;
+        }
+        else if (r_icache_cleanup_req)
+        {
+            r_cleanup_rsp_fsm = CLEANUP_RSP_INS;
+        }
+        break;
+    }
+    case CLEANUP_RSP_DATA:
+    {
+	    m_cost_dcleanup_transaction++;
+        if ( ! p_vci_ini_c.rspval.read() )
+            break;
+        assert( p_vci_ini_c.reop.read() &&
+                "illegal VCI response packet for dcache cleanup");
+        assert( ((p_vci_ini_c.rerror.read() % 1) == vci_param::ERR_NORMAL) &&
+                "error in response packet for dcache cleanup");    
+
+        r_dcache_cleanup_req = false;
+        r_cleanup_rsp_fsm = CLEANUP_RSP_IDLE;    
+	break;  	    
+    }
+    case CLEANUP_RSP_INS:
+    {
+	    m_cost_icleanup_transaction++;
+        if ( ! p_vci_ini_c.rspval.read() )
+            break;
+        assert( p_vci_ini_c.reop.read() &&
+                "illegal VCI response packet for icache cleanup");
+        assert( ((p_vci_ini_c.rerror.read() % 1) == vci_param::ERR_NORMAL) &&
+                "error in response packet for icache cleanup");
+
+        r_icache_cleanup_req = false;
+        r_cleanup_rsp_fsm = CLEANUP_RSP_IDLE;    
+	break;    
+    }
+    } // end  switch r_cleanup_fsm
+
+} // end transition()
+
+
+#define   _CMD_ITLB    0x1
+#define   _CMD_DTLB    0x2   
+#define   _CMD_USR     0x4
+
+///////////////////////
+tmpl(void)::genMoore()
+///////////////////////
+{
+    // VCI initiator response
+    p_vci_ini_rw.rspack = true;
+
+    // VCI initiator command
+    p_vci_ini_rw.pktid  = 0;
+    p_vci_ini_rw.srcid  = m_srcid_rw;
+    p_vci_ini_rw.cons   = false;
+    p_vci_ini_rw.wrap   = false;
+    p_vci_ini_rw.contig = true;
+    p_vci_ini_rw.clen   = 0;
+    p_vci_ini_rw.cfixed = false;
+
+    switch (r_vci_cmd_fsm) {
+
+    case CMD_IDLE:
+        p_vci_ini_rw.cmdval  = false;
+        p_vci_ini_rw.address = 0;
+        p_vci_ini_rw.wdata   = 0;
+        p_vci_ini_rw.be      = 0;
+        p_vci_ini_rw.trdid   = 0;
+        p_vci_ini_rw.plen    = 0;
+        p_vci_ini_rw.cmd     = vci_param::CMD_NOP;
+        p_vci_ini_rw.eop     = false;
+        break;
+
+    case CMD_ITLB_READ:     
+        p_vci_ini_rw.cmdval  = true;
+        p_vci_ini_rw.address = r_icache_paddr_save.read() & m_dcache_yzmask;
+        p_vci_ini_rw.wdata   = 0;
+        p_vci_ini_rw.be      = 0xF;
+        p_vci_ini_rw.trdid   = 1; // via data cache cached read
+        p_vci_ini_rw.plen    = m_dcache_words << 2;
+        p_vci_ini_rw.cmd     = vci_param::CMD_READ;
+        p_vci_ini_rw.eop     = true;
+        p_vci_ini_rw.pktid   = (r_ireq_isUser_save == true) ? _CMD_ITLB | _CMD_USR : _CMD_ITLB;
+        break;
+
+    case CMD_ITLB_ACC_LL:
+        p_vci_ini_rw.cmdval  = true;
+        p_vci_ini_rw.address = r_icache_paddr_save.read() & ~0x3;
+        p_vci_ini_rw.wdata   = 0;
+        p_vci_ini_rw.be      = 0xF;
+        p_vci_ini_rw.trdid   = 0; // data cache uncached read
+        p_vci_ini_rw.plen    = 4;
+        p_vci_ini_rw.cmd     = vci_param::CMD_LOCKED_READ;
+        p_vci_ini_rw.eop     = true;
+        p_vci_ini_rw.pktid   = (r_ireq_isUser_save == true) ? _CMD_ITLB | _CMD_USR : _CMD_ITLB;
+	break;
+
+    case CMD_ITLB_ACC_SC:
+        p_vci_ini_rw.cmdval  = true;
+        p_vci_ini_rw.address = r_icache_paddr_save.read() & ~0x3;
+        p_vci_ini_rw.wdata   = r_icache_pte_update.read();
+        p_vci_ini_rw.be      = 0xF;
+        p_vci_ini_rw.trdid   = 0; // data cache uncached read
+        p_vci_ini_rw.plen    = 4;
+        p_vci_ini_rw.cmd     = vci_param::CMD_STORE_COND;
+        p_vci_ini_rw.eop     = true;
+        p_vci_ini_rw.pktid   = (r_ireq_isUser_save == true) ? _CMD_ITLB | _CMD_USR : _CMD_ITLB;
+	break;	
+
+    case CMD_INS_MISS:
+        p_vci_ini_rw.cmdval  = true;
+        p_vci_ini_rw.address = r_icache_paddr_save.read() & m_icache_yzmask;
+        p_vci_ini_rw.wdata   = 0;
+        p_vci_ini_rw.be      = 0xF;
+        p_vci_ini_rw.trdid   = 3; // ins cache cached read
+        p_vci_ini_rw.plen    = m_icache_words << 2;
+        p_vci_ini_rw.cmd     = vci_param::CMD_READ;
+        p_vci_ini_rw.eop     = true;
+        p_vci_ini_rw.pktid   = (r_ireq_isUser_save == true) ? _CMD_USR : 0;
+        break;
+
+    case CMD_INS_UNC:
+        p_vci_ini_rw.cmdval  = true;
+        p_vci_ini_rw.address = r_icache_paddr_save.read() & ~0x3;
+        p_vci_ini_rw.wdata   = 0;
+        p_vci_ini_rw.be      = 0xF;
+        p_vci_ini_rw.trdid   = 2; // ins cache uncached read
+        p_vci_ini_rw.plen    = 4;
+        p_vci_ini_rw.cmd     = vci_param::CMD_READ;
+        p_vci_ini_rw.eop     = true;
+        p_vci_ini_rw.pktid   = (r_ireq_isUser_save == true) ? _CMD_USR : 0;
+        break;
+
+    case CMD_DTLB_READ:     
+        p_vci_ini_rw.cmdval  = true;
+        p_vci_ini_rw.address = r_dcache_tlb_paddr.read() & m_dcache_yzmask;
+        p_vci_ini_rw.wdata   = 0;
+        p_vci_ini_rw.be      = 0xF;
+        p_vci_ini_rw.trdid   = 1; // via dcache cached read
+        p_vci_ini_rw.plen    = m_dcache_words << 2;
+        p_vci_ini_rw.cmd     = vci_param::CMD_READ;
+        p_vci_ini_rw.eop     = true;
+        p_vci_ini_rw.pktid   = (r_dreq_isUser_save == true) ? _CMD_DTLB | _CMD_USR : _CMD_DTLB;
+        break;
+
+    case CMD_DTLB_ACC_LL:
+        p_vci_ini_rw.cmdval  = true;
+        p_vci_ini_rw.address = r_dcache_tlb_paddr.read() & ~0x3;
+        p_vci_ini_rw.wdata   = 0;
+        p_vci_ini_rw.be      = 0xF;
+        p_vci_ini_rw.trdid   = 0; // data cache uncached read
+        p_vci_ini_rw.plen    = 4;
+        p_vci_ini_rw.cmd     = vci_param::CMD_LOCKED_READ;
+        p_vci_ini_rw.eop     = true;
+        p_vci_ini_rw.pktid   = (r_dreq_isUser_save == true) ? _CMD_DTLB | _CMD_USR : _CMD_DTLB;
+	break;
+
+    case CMD_DTLB_ACC_SC:
+        p_vci_ini_rw.cmdval  = true;
+        p_vci_ini_rw.address = r_dcache_tlb_paddr.read() & ~0x3;
+        p_vci_ini_rw.wdata   = r_dcache_pte_update.read();
+        p_vci_ini_rw.be      = 0xF;
+        p_vci_ini_rw.trdid   = 0; // data cache uncached read
+        p_vci_ini_rw.plen    = 4;
+        p_vci_ini_rw.cmd     = vci_param::CMD_STORE_COND;
+        p_vci_ini_rw.eop     = true;
+        p_vci_ini_rw.pktid   = (r_dreq_isUser_save == true) ? _CMD_DTLB | _CMD_USR : _CMD_DTLB;
+	break;	
+
+    case CMD_DTLB_DIRTY_LL:
+        p_vci_ini_rw.cmdval  = true;
+        p_vci_ini_rw.address = r_dcache_tlb_paddr.read() & ~0x3;
+        p_vci_ini_rw.wdata   = 0;
+        p_vci_ini_rw.be      = 0xF;
+        p_vci_ini_rw.trdid   = 0; // data cache uncached read
+        p_vci_ini_rw.plen    = 4;
+        p_vci_ini_rw.cmd     = vci_param::CMD_LOCKED_READ;
+        p_vci_ini_rw.eop     = true;
+        p_vci_ini_rw.pktid   = (r_dreq_isUser_save == true) ? _CMD_DTLB | _CMD_USR : _CMD_DTLB;
+	break;
+
+    case CMD_DTLB_DIRTY_SC:
+        p_vci_ini_rw.cmdval  = true;
+        p_vci_ini_rw.address = r_dcache_tlb_paddr.read() & ~0x3;
+        p_vci_ini_rw.wdata   = r_dcache_pte_update.read();
+        p_vci_ini_rw.be      = 0xF;
+        p_vci_ini_rw.trdid   = 0; // data cache uncached read
+        p_vci_ini_rw.plen    = 4;
+        p_vci_ini_rw.cmd     = vci_param::CMD_STORE_COND;
+        p_vci_ini_rw.eop     = true;
+        p_vci_ini_rw.pktid   = (r_dreq_isUser_save == true) ? _CMD_DTLB | _CMD_USR : _CMD_DTLB;
+	break;	
+
+    case CMD_DATA_UNC:
+        p_vci_ini_rw.cmdval  = true;
+        p_vci_ini_rw.address = r_dcache_paddr_save.read() & ~0x3;
+        p_vci_ini_rw.trdid   = 0; // data cache uncached read
+        p_vci_ini_rw.plen    = 4;
+        p_vci_ini_rw.eop     = true;
+        p_vci_ini_rw.pktid   = (r_dreq_isUser_save == true) ? _CMD_USR : 0;
+        switch(r_dcache_type_save) {
+        case iss_t::DATA_READ:
+            p_vci_ini_rw.wdata = 0;
+            p_vci_ini_rw.be    = r_dcache_be_save.read();
+            p_vci_ini_rw.cmd   = vci_param::CMD_READ;
+            break;
+        case iss_t::DATA_LL:
+            p_vci_ini_rw.wdata = 0;
+            p_vci_ini_rw.be    = 0xF;
+            p_vci_ini_rw.cmd   = vci_param::CMD_LOCKED_READ;
+            break;
+        case iss_t::DATA_SC:
+            p_vci_ini_rw.wdata = r_dcache_wdata_save.read();
+            p_vci_ini_rw.be    = 0xF;
+            p_vci_ini_rw.cmd   = vci_param::CMD_STORE_COND;
+            break;
+        default:
+            assert("this should not happen");
+        }
+        break;
+
+    case CMD_DATA_WRITE:
+        p_vci_ini_rw.cmdval  = true;
+        p_vci_ini_rw.address = r_wbuf.getAddress(r_vci_cmd_cpt);
+        p_vci_ini_rw.wdata   = r_wbuf.getData(r_vci_cmd_cpt);
+        p_vci_ini_rw.be      = r_wbuf.getBe(r_vci_cmd_cpt);
+        p_vci_ini_rw.trdid   = 0; // data cache write
+        p_vci_ini_rw.plen    = (r_vci_cmd_max - r_vci_cmd_min + 1)<<2;
+        p_vci_ini_rw.cmd     = vci_param::CMD_WRITE;
+        p_vci_ini_rw.eop     = (r_vci_cmd_cpt == r_vci_cmd_max);
+        p_vci_ini_rw.pktid   = (r_dreq_isUser_save == true) ? _CMD_USR : 0;
+        break;
+
+    case CMD_DATA_MISS:
+        p_vci_ini_rw.cmdval  = true;
+        p_vci_ini_rw.address = r_dcache_paddr_save.read() & m_dcache_yzmask;
+        p_vci_ini_rw.wdata   = 0;
+        p_vci_ini_rw.be      = 0xF;
+        p_vci_ini_rw.trdid   = 1; // data cache cached read
+        p_vci_ini_rw.plen    = m_dcache_words << 2;
+        p_vci_ini_rw.cmd     = vci_param::CMD_READ;
+        p_vci_ini_rw.eop     = true;
+        p_vci_ini_rw.pktid   = (r_dreq_isUser_save == true) ? _CMD_USR : 0;
+        break;
+    } // end switch r_vci_cmd_fsm
+
+    p_vci_ini_c.rspack = true;
+
+    switch (r_cleanup_cmd_fsm) {
+
+    case CLEANUP_CMD_IDLE:
+        p_vci_ini_c.cmdval  = false;
+        p_vci_ini_c.address = 0;
+        p_vci_ini_c.trdid   = 0; 
+        p_vci_ini_c.wdata   = 0;
+        p_vci_ini_c.be      = 0;
+        p_vci_ini_c.plen    = 0;
+        p_vci_ini_c.cmd     = vci_param::CMD_NOP;
+        p_vci_ini_c.pktid   = 0;
+        p_vci_ini_c.srcid   = m_srcid_c;
+        p_vci_ini_c.cons    = false;
+        p_vci_ini_c.wrap    = false;
+        p_vci_ini_c.contig  = false;
+        p_vci_ini_c.clen    = 0;
+        p_vci_ini_c.cfixed  = false;
+        p_vci_ini_c.eop     = false;
+        break;
+
+    case CLEANUP_CMD_DATA:
+        p_vci_ini_c.cmdval  = true;
+        p_vci_ini_c.address = r_dcache_cleanup_line.read() * (m_dcache_words<<2);
+        p_vci_ini_c.trdid  = 0; // data cleanup 
+        p_vci_ini_c.wdata  = 0;
+        p_vci_ini_c.be     = 0;
+        p_vci_ini_c.plen   = 4;
+        p_vci_ini_c.cmd    = vci_param::CMD_WRITE;
+        p_vci_ini_c.pktid  = 0;
+        p_vci_ini_c.srcid  = m_srcid_c;
+        p_vci_ini_c.cons   = false;
+        p_vci_ini_c.wrap   = false;
+        p_vci_ini_c.contig = false;
+        p_vci_ini_c.clen   = 0;
+        p_vci_ini_c.cfixed = false;
+        p_vci_ini_c.eop    = true;
+        break;
+
+    case CLEANUP_CMD_INS:
+        p_vci_ini_c.cmdval  = true;
+        p_vci_ini_c.address = r_icache_cleanup_line.read() * (m_icache_words<<2);
+        p_vci_ini_c.trdid  = 1; // ins cleanup 
+        p_vci_ini_c.wdata  = 0;
+        p_vci_ini_c.be     = 0;
+        p_vci_ini_c.plen   = 4;
+        p_vci_ini_c.cmd    = vci_param::CMD_WRITE;
+        p_vci_ini_c.pktid  = 0;
+        p_vci_ini_c.srcid  = m_srcid_c;
+        p_vci_ini_c.cons   = false;
+        p_vci_ini_c.wrap   = false;
+        p_vci_ini_c.contig = false;
+        p_vci_ini_c.clen   = 0;
+        p_vci_ini_c.cfixed = false;
+        p_vci_ini_c.eop    = true;
+        break;
+      } // end switch r_vci_cmd_cleanup_fsm
+
+    // VCI_TGT
+    switch ( r_vci_tgt_fsm.read() ) {
+
+    case TGT_IDLE:
+    case TGT_UPDT_WORD:
+    case TGT_UPDT_DATA:
+        p_vci_tgt.cmdack  = true;
+        p_vci_tgt.rspval  = false;
+        break;
+
+    case TGT_RSP_BROADCAST:
+        p_vci_tgt.cmdack  = false;
+        p_vci_tgt.rspval  = !r_tgt_icache_req.read() && !r_tgt_dcache_req.read() && ( r_tgt_icache_rsp | r_tgt_dcache_rsp );
+        p_vci_tgt.rsrcid  = r_tgt_srcid.read();
+        p_vci_tgt.rpktid  = r_tgt_pktid.read();
+        p_vci_tgt.rtrdid  = r_tgt_trdid.read();
+        p_vci_tgt.rdata   = 0;
+        p_vci_tgt.rerror  = 0;
+        p_vci_tgt.reop    = true;
+        break;
+
+    case TGT_RSP_ICACHE:
+        p_vci_tgt.cmdack  = false;
+        p_vci_tgt.rspval  = !r_tgt_icache_req.read() && r_tgt_icache_rsp.read();
+        p_vci_tgt.rsrcid  = r_tgt_srcid.read();
+        p_vci_tgt.rpktid  = r_tgt_pktid.read();
+        p_vci_tgt.rtrdid  = r_tgt_trdid.read();
+        p_vci_tgt.rdata   = 0;
+        p_vci_tgt.rerror  = 0;
+        p_vci_tgt.reop    = true;
+        break;
+
+    case TGT_RSP_DCACHE:
+        p_vci_tgt.cmdack  = false;
+        p_vci_tgt.rspval  = !r_tgt_dcache_req.read() && r_tgt_dcache_rsp.read();
+        p_vci_tgt.rsrcid  = r_tgt_srcid.read();
+        p_vci_tgt.rpktid  = r_tgt_pktid.read();
+        p_vci_tgt.rtrdid  = r_tgt_trdid.read();
+        p_vci_tgt.rdata   = 0;
+        p_vci_tgt.rerror  = 0;
+        p_vci_tgt.reop    = true;
+        break;
+
+    case TGT_REQ_BROADCAST:
+    case TGT_REQ_ICACHE:
+    case TGT_REQ_DCACHE:
+        p_vci_tgt.cmdack  = false;
+        p_vci_tgt.rspval  = false;
+        break;
+
+    } // end switch TGT_FSM
+
+#ifdef SOCLIB_MODULE_DEBUG
+   std::cout << name() 
+      	     << " Moore R/W:" << std::hex
+      	     << " p_vci_ini_rw.cmdval: " << p_vci_ini_rw.cmdval
+      	     << " p_vci_ini_rw.address: " << p_vci_ini_rw.address
+      	     << " p_vci_ini_rw.srcid: " << p_vci_ini_rw.srcid
+      	     << " p_vci_ini_rw.wdata: " << p_vci_ini_rw.wdata
+      	     << " p_vci_ini_rw.cmd: " << p_vci_ini_rw.cmd
+      	     << " p_vci_ini_rw.eop: " << p_vci_ini_rw.eop
+      	     << std::endl;
+
+   std::cout << name() 
+      	     << " Moore TGT:" << std::hex
+      	     << " p_vci_tgt.rspval: " << p_vci_tgt.rspval
+      	     << std::endl;
+
+   std::cout << name() 
+      	     << " Moore Cleanup:" << std::hex
+      	     << " p_vci_ini_c.cmdval: " << p_vci_ini_c.cmdval
+      	     << " p_vci_ini_c.address: " << p_vci_ini_c.address
+      	     << " p_vci_ini_c.trdid: " << p_vci_ini_c.trdid
+      	     << " p_vci_ini_c.cmd: " << p_vci_ini_c.cmd
+      	     << " p_vci_ini_c.eop: " << p_vci_ini_c.eop
+      	     << std::endl;
+#endif
+}
+
+}}
+
+// Local Variables:
+// tab-width: 4
+// c-basic-offset: 4
+// c-file-offsets:((innamespace . 0)(inline-open . 0))
+// indent-tabs-mode: nil
+// End:
+
+// vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4
+
+
+
+
+
+
+
+
+
+
Index: branches/v4/platforms/almos-tsarv3-platforms/common/vci_dma_tsar_v2/caba/metadata/vci_dma_tsar_v2.sd
===================================================================
--- branches/v4/platforms/almos-tsarv3-platforms/common/vci_dma_tsar_v2/caba/metadata/vci_dma_tsar_v2.sd	(revision 371)
+++ branches/v4/platforms/almos-tsarv3-platforms/common/vci_dma_tsar_v2/caba/metadata/vci_dma_tsar_v2.sd	(revision 371)
@@ -0,0 +1,43 @@
+
+# -*- python -*-
+
+__id__ = "$Id: vci_dma_tsar_v2.sd 20 2010-04-14 03:27:59Z nipo $"
+__version__ = "$Revision: 20 $"
+
+Module('caba:vci_dma_tsar_v2',
+	classname = 'soclib::caba::VciDmaTsarV2',
+	   tmpl_parameters = [
+	parameter.Module('vci_param',  default = 'caba:vci_param'),
+	],
+	header_files = ['../source/include/vci_dma_tsar_v2.h',
+					],
+    interface_files = [
+					'../../include/soclib/dma_tsar_v2.h',
+					],
+	implementation_files = ['../source/src/vci_dma_tsar_v2.cpp',],
+			  ports = [
+	Port('caba:vci_target', 'p_vci_target'),
+	Port('caba:vci_initiator', 'p_vci_initiator'),
+	Port('caba:bit_out', 'p_irq'),
+	Port('caba:bit_in', 'p_resetn', auto = 'resetn'),
+	Port('caba:clock_in', 'p_clk', auto = 'clock'),
+	],
+	uses = [
+		Uses('caba:base_module'),
+		Uses('caba:vci_target_fsm', default_target = 'true', support_llsc = 'false'),
+		Uses('caba:vci_initiator_simple_read_req'),
+		Uses('caba:vci_initiator_simple_write_req'),
+		Uses('caba:vci_initiator_fsm'),
+		],
+	instance_parameters = [
+        parameter.Module('mt', typename = 'common:mapping_table', auto = 'env:mapping_table'),
+		parameter.IntTab('srcid'),
+		parameter.IntTab('tgtid'),
+        parameter.Int('burst_size'),
+	],
+	   extensions = [
+	'dsx:addressable=tgtid',
+	'dsx:max_segments=1',
+	'dsx:get_ident=tgtid:p_vci_target:mt,srcid:p_vci_initiator:mt',
+   ],
+)
Index: branches/v4/platforms/almos-tsarv3-platforms/common/vci_dma_tsar_v2/caba/source/include/vci_dma_tsar_v2.h
===================================================================
--- branches/v4/platforms/almos-tsarv3-platforms/common/vci_dma_tsar_v2/caba/source/include/vci_dma_tsar_v2.h	(revision 371)
+++ branches/v4/platforms/almos-tsarv3-platforms/common/vci_dma_tsar_v2/caba/source/include/vci_dma_tsar_v2.h	(revision 371)
@@ -0,0 +1,106 @@
+/* -*- c++ -*-
+ *
+ * SOCLIB_LGPL_HEADER_BEGIN
+ * 
+ * This file is part of SoCLib, GNU LGPLv2.1.
+ * 
+ * SoCLib is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU Lesser General Public License as published
+ * by the Free Software Foundation; version 2.1 of the License.
+ * 
+ * SoCLib is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * Lesser General Public License for more details.
+ * 
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with SoCLib; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301 USA
+ * 
+ * SOCLIB_LGPL_HEADER_END
+ *
+ * Copyright (c) UPMC, Lip6, Asim
+ *         Nicolas Pouillon <nipo@ssji.net>, 2007
+ *
+ * Maintainers: nipo
+ */
+#ifndef SOCLIB_VCI_DMA_TSAR_V2_H
+#define SOCLIB_VCI_DMA_TSAR_V2_H
+
+#include <stdint.h>
+#include <systemc>
+#include "vci_target_fsm.h"
+#include "vci_initiator_fsm.h"
+#include "caba_base_module.h"
+#include "mapping_table.h"
+
+namespace soclib {
+namespace caba {
+
+using namespace sc_core;
+
+template<typename vci_param>
+class VciDmaTsarV2
+	: public caba::BaseModule
+{
+private:
+    soclib::caba::VciTargetFsm<vci_param, true> m_vci_target_fsm;
+    soclib::caba::VciInitiatorFsm<vci_param> m_vci_init_fsm;
+    typedef typename soclib::caba::VciInitiatorReq<vci_param> req_t;
+
+    bool on_write(int seg, typename vci_param::addr_t addr, typename vci_param::data_t data, int be);
+    bool on_read(int seg, typename vci_param::addr_t addr, typename vci_param::data_t &data);
+    void read_done( req_t *req );
+    void write_finish( req_t *req );
+    void transition();
+    void genMoore();
+
+	uint32_t m_src;
+	uint32_t m_dst;
+	uint32_t m_len;
+	uint32_t m_offset;
+    uint32_t m_offset_buffer;
+    bool m_partial;
+    bool m_must_finish;
+	bool m_irq_enabled;
+	bool r_irq;
+
+	std::vector<uint8_t> m_data;
+
+	bool m_handling;
+
+	void next_req();
+	void ended();
+
+protected:
+    SC_HAS_PROCESS(VciDmaTsarV2);
+
+public:
+    sc_in<bool> p_clk;
+    sc_in<bool> p_resetn;
+    soclib::caba::VciTarget<vci_param> p_vci_target;
+    soclib::caba::VciInitiator<vci_param> p_vci_initiator;
+    sc_out<bool> p_irq;
+
+	VciDmaTsarV2(
+		sc_module_name name,
+		const soclib::common::MappingTable &mt,
+		const soclib::common::IntTab &srcid,
+		const soclib::common::IntTab &tgtid,
+		const size_t burst_size );
+};
+
+}}
+
+#endif /* SOCLIB_VCI_DMA_TSAR_V2_H */
+
+// Local Variables:
+// tab-width: 4
+// c-basic-offset: 4
+// c-file-offsets:((innamespace . 0)(inline-open . 0))
+// indent-tabs-mode: nil
+// End:
+
+// vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4
+
Index: branches/v4/platforms/almos-tsarv3-platforms/common/vci_dma_tsar_v2/caba/source/src/vci_dma_tsar_v2.cpp
===================================================================
--- branches/v4/platforms/almos-tsarv3-platforms/common/vci_dma_tsar_v2/caba/source/src/vci_dma_tsar_v2.cpp	(revision 371)
+++ branches/v4/platforms/almos-tsarv3-platforms/common/vci_dma_tsar_v2/caba/source/src/vci_dma_tsar_v2.cpp	(revision 371)
@@ -0,0 +1,246 @@
+/* -*- c++ -*-
+ *
+ * SOCLIB_LGPL_HEADER_BEGIN
+ * 
+ * This file is part of SoCLib, GNU LGPLv2.1.
+ * 
+ * SoCLib is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU Lesser General Public License as published
+ * by the Free Software Foundation; version 2.1 of the License.
+ * 
+ * SoCLib is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * Lesser General Public License for more details.
+ * 
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with SoCLib; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301 USA
+ * 
+ * SOCLIB_LGPL_HEADER_END
+ *
+ * Copyright (c) UPMC, Lip6, Asim
+ *         Nicolas Pouillon <nipo@ssji.net>, 2007
+ */
+
+#include <stdint.h>
+#include "register.h"
+#include "../include/vci_dma_tsar_v2.h"
+#include "dma_tsar_v2.h"
+
+namespace soclib { namespace caba {
+
+#define tmpl(t) template<typename vci_param> t VciDmaTsarV2<vci_param>
+
+tmpl(bool)::on_write(int seg, typename vci_param::addr_t addr, typename vci_param::data_t data, int be)
+{
+    int cell = (int)addr / vci_param::B;
+
+	switch ((enum SoclibDmaRegisters)cell) {
+	case DMA_SRC:
+		m_src = data;
+		return true;
+    case DMA_DST:
+		m_dst = data;
+		return true;
+    case DMA_LEN:
+		m_len = data;
+		return true;
+    case DMA_RESET:
+        m_must_finish = true;
+        m_irq_enabled = false;
+		r_irq = false;
+        return true;
+    case DMA_IRQ_DISABLED:
+		m_irq_enabled = !data;
+		return true;
+	};
+	return false;
+}
+
+tmpl(void)::ended()
+{
+	if ( m_irq_enabled )
+		r_irq = true;
+	m_len = 0;
+    m_must_finish = false;
+	m_handling = false;
+}
+
+tmpl(bool)::on_read(int seg, typename vci_param::addr_t addr, typename vci_param::data_t &data)
+{
+    int cell = (int)addr / vci_param::B;
+
+	switch ((enum SoclibDmaRegisters)cell) {
+	case DMA_SRC:
+		data = m_src;
+		return true;
+    case DMA_DST:
+		data = m_dst;
+		return true;
+	case DMA_LEN:
+		data = m_len;
+		return true;
+    default:
+        return false;
+	}
+	return false;
+}
+
+tmpl(void)::read_done( req_t *req )
+{
+	if ( !req->failed() && !m_must_finish ) {
+		ssize_t burst = m_offset_buffer;
+
+        m_partial = false;
+        if( (( m_dst+m_offset ) & ~( m_data.size()-1 )) !=
+            (( m_dst+m_offset+m_offset_buffer-1 ) & ~( m_data.size()-1 )) ){
+            burst = (((m_dst+m_offset) & ~( m_data.size()-1))+m_data.size()) - (m_dst+m_offset);
+            m_partial = true;
+        }
+		VciInitSimpleWriteReq<vci_param> *new_req =
+			new VciInitSimpleWriteReq<vci_param>( m_dst+m_offset, &m_data[0], burst );
+		new_req->setDone( this, ON_T(write_finish) );
+		m_vci_init_fsm.doReq( new_req );
+	} else {
+		ended();
+	}
+	delete req;
+}
+
+tmpl(void)::write_finish( req_t *req )
+{
+    ssize_t burst = 0;
+    uint32_t offset = 0;
+    if( m_partial ){
+        burst = m_dst + m_offset + m_offset_buffer - ((m_dst+m_offset+m_offset_buffer) & ~( m_data.size()-1));
+        offset = m_offset_buffer - burst ;
+    } else {
+	    m_offset += m_offset_buffer;
+    }
+	if ( !req->failed() && !m_must_finish ){
+        if(m_partial){
+            VciInitSimpleWriteReq<vci_param> *new_req =
+                new VciInitSimpleWriteReq<vci_param>( m_dst+m_offset+offset, &m_data[offset], burst );
+            new_req->setDone( this, ON_T(write_finish) );
+            m_partial = false;
+            m_vci_init_fsm.doReq( new_req );
+            delete req;
+            return;
+        }
+		next_req();
+    }
+	else {
+		ended();
+	}
+	delete req;
+}
+
+tmpl(void)::next_req()
+{
+	ssize_t remaining = (ssize_t)m_len-(size_t)m_offset;
+	if ( remaining <= 0 ) {
+		ended();
+		return;
+	}
+
+	ssize_t burst = m_data.size();
+    m_partial = false;
+    if ( ( m_src+m_offset ) & ( m_data.size()-1 ) ){
+        burst = m_data.size() - ( (m_src+m_offset) & (m_data.size()-1) );
+        m_partial = true;
+    }
+	if ( remaining < burst ){
+		burst = remaining;
+        m_partial = true;
+    }
+
+    m_offset_buffer = burst;
+
+	VciInitSimpleReadReq<vci_param> *req =
+		new VciInitSimpleReadReq<vci_param>(
+			&m_data[0], (m_src+m_offset), burst );
+	req->setDone( this, ON_T(read_done) );
+	m_vci_init_fsm.doReq( req );
+}
+
+tmpl(void)::transition()
+{
+	if (!p_resetn) {
+		m_vci_target_fsm.reset();
+		m_vci_init_fsm.reset();
+		r_irq = false;
+		m_irq_enabled = false;
+		m_len = 0;
+        m_offset_buffer = 0;
+		m_handling = false;
+        m_must_finish = false;
+		return;
+	}
+
+
+	if ( m_len && !m_handling ) {
+		m_handling = true;
+		m_offset = 0;
+
+		next_req();
+	}
+    
+    if( !m_handling )
+        m_must_finish = false;
+
+	m_vci_target_fsm.transition();
+	m_vci_init_fsm.transition();
+}
+
+tmpl(void)::genMoore()
+{
+	m_vci_target_fsm.genMoore();
+	m_vci_init_fsm.genMoore();
+
+	p_irq = r_irq && m_irq_enabled;
+}
+
+tmpl(/**/)::VciDmaTsarV2(
+    sc_module_name name,
+    const MappingTable &mt,
+    const IntTab &srcid,
+    const IntTab &tgtid,
+	const size_t burst_size )
+	: caba::BaseModule(name),
+	  m_vci_target_fsm(p_vci_target, mt.getSegmentList(tgtid)),
+	  m_vci_init_fsm(p_vci_initiator, mt.indexForId(srcid)),
+	  m_len(0),
+	  m_data(burst_size, (uint8_t)0),
+      p_clk("clk"),
+      p_resetn("resetn"),
+      p_vci_target("vci_target"),
+      p_vci_initiator("vci_initiator"),
+      p_irq("irq")
+{
+	m_vci_target_fsm.on_read_write(on_read, on_write);
+    
+    assert(burst_size && "Useless DMA with no buffer");
+    assert(burst_size < (1<<vci_param::K) && "I will be unable to create requests that big");
+
+	SC_METHOD(transition);
+	dont_initialize();
+	sensitive << p_clk.pos();
+
+	SC_METHOD(genMoore);
+	dont_initialize();
+	sensitive << p_clk.neg();
+}
+
+}}
+
+// Local Variables:
+// tab-width: 4
+// c-basic-offset: 4
+// c-file-offsets:((innamespace . 0)(inline-open . 0))
+// indent-tabs-mode: nil
+// End:
+
+// vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4
+
Index: branches/v4/platforms/almos-tsarv3-platforms/common/vci_dma_tsar_v2/include/soclib/dma_tsar_v2.h
===================================================================
--- branches/v4/platforms/almos-tsarv3-platforms/common/vci_dma_tsar_v2/include/soclib/dma_tsar_v2.h	(revision 371)
+++ branches/v4/platforms/almos-tsarv3-platforms/common/vci_dma_tsar_v2/include/soclib/dma_tsar_v2.h	(revision 371)
@@ -0,0 +1,49 @@
+/*
+ * SOCLIB_LGPL_HEADER_BEGIN
+ * 
+ * This file is part of SoCLib, GNU LGPLv2.1.
+ * 
+ * SoCLib is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU Lesser General Public License as published
+ * by the Free Software Foundation; version 2.1 of the License.
+ * 
+ * SoCLib is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * Lesser General Public License for more details.
+ * 
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with SoCLib; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301 USA
+ * 
+ * SOCLIB_LGPL_HEADER_END
+ *
+ * Copyright (c) UPMC, Lip6, Asim
+ *         Nicolas Pouillon <nipo@ssji.net>, 2007
+ *         Eric Guthmuller  <eric.guthmuller@polytechnique.edu>, 2009
+ *
+ * Maintainers: nipo eric.guthmuller@polytechnique.edu
+ */
+#ifndef DMA_REGS_TSAR_V2_H
+#define DMA_REGS_TSAR_V2_H
+
+enum SoclibDmaRegisters {
+    DMA_SRC,
+    DMA_DST,
+    DMA_LEN,
+    DMA_RESET,
+    DMA_IRQ_DISABLED,
+};
+
+#endif /* DMA_REGS_TSAR_V2_H */
+
+// Local Variables:
+// tab-width: 4
+// c-basic-offset: 4
+// c-file-offsets:((innamespace . 0)(inline-open . 0))
+// indent-tabs-mode: nil
+// End:
+
+// vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4
+
Index: branches/v4/platforms/almos-tsarv3-platforms/common/vci_mem_cache_v3/caba/metadata/vci_mem_cache_v3.sd
===================================================================
--- branches/v4/platforms/almos-tsarv3-platforms/common/vci_mem_cache_v3/caba/metadata/vci_mem_cache_v3.sd	(revision 371)
+++ branches/v4/platforms/almos-tsarv3-platforms/common/vci_mem_cache_v3/caba/metadata/vci_mem_cache_v3.sd	(revision 371)
@@ -0,0 +1,49 @@
+
+# -*- python -*-
+
+__id__ = "$Id: vci_mem_cache_v3.sd 20 2010-04-14 03:27:59Z nipo $"
+__version__ = "$Revision: 20 $"
+
+Module('caba:vci_mem_cache_v3',
+       classname = 'soclib::caba::VciMemCacheV3',
+       tmpl_parameters = [parameter.Module('vci_param', default = 'caba:vci_param'),],
+       header_files = ['../source/include/vci_mem_cache_v3.h',
+                       '../source/include/xram_transaction_v3.h',
+                       '../source/include/mem_cache_directory_v3.h',
+                       '../source/include/atomic_tab_v3.h',
+                       '../source/include/update_tab_v3.h',],
+       implementation_files = ['../source/src/vci_mem_cache_v3.cpp',],
+       uses = [Uses('caba:base_module'),
+               Uses('common:loader'),
+               Uses('common:mapping_table'),
+               Uses('caba:generic_fifo'),
+               Uses('config:config'),
+               ],
+       ports = [Port('caba:vci_target', 'p_vci_tgt'),
+		Port('caba:vci_target','p_vci_tgt_cleanup'),
+		Port('caba:vci_initiator','p_vci_ini'),
+		Port('caba:vci_initiator','p_vci_ixr'),
+                Port('caba:bit_in', 'p_resetn', auto = 'resetn'),
+                Port('caba:clock_in', 'p_clk', auto = 'clock'),],
+       instance_parameters = [
+		parameter.Module('mtp', 'common:mapping_table'),
+		parameter.Module('mtc', 'common:mapping_table'),
+		parameter.Module('mtx', 'common:mapping_table'),
+		parameter.IntTab('vci_ixr_index'),
+		parameter.IntTab('vci_ini_index'),
+		parameter.IntTab('vci_tgt_index'),
+		parameter.IntTab('vci_tgt_index_cleanup'),
+    parameter.Int('nways'),
+		parameter.Int('nsets'),
+		parameter.Int('nwords'),
+		parameter.Int('heap_size'),
+		],
+       extensions = [
+          'dsx:get_ident='
+          'vci_ini_index:p_vci_ini:mtc,'
+          'vci_tgt_index_cleanup:p_vci_tgt_cleanup:mtc,'
+          'vci_tgt_index:p_vci_tgt:mtp,'
+          'vci_ixr_index:p_vci_ixr:mtx',
+		'dsx:addressable=vci_tgt_index,vci_tgt_index_cleanup',
+       ],
+)
Index: branches/v4/platforms/almos-tsarv3-platforms/common/vci_mem_cache_v3/caba/source/include/atomic_tab_v3.h
===================================================================
--- branches/v4/platforms/almos-tsarv3-platforms/common/vci_mem_cache_v3/caba/source/include/atomic_tab_v3.h	(revision 371)
+++ branches/v4/platforms/almos-tsarv3-platforms/common/vci_mem_cache_v3/caba/source/include/atomic_tab_v3.h	(revision 371)
@@ -0,0 +1,121 @@
+#ifndef ATOMIC_TAB_V3_H_
+#define ATOMIC_TAB_V3_H_
+
+#include <inttypes.h>
+#include <systemc>
+#include <cassert>
+#include "arithmetics.h"
+
+
+
+////////////////////////////////////////////////////////////////////////
+////////////////////////////////////////////////////////////////////////
+/*                  The atomic access tab                             */
+////////////////////////////////////////////////////////////////////////
+////////////////////////////////////////////////////////////////////////
+
+class AtomicTab{
+    typedef uint32_t size_t;
+    typedef sc_dt::sc_uint<40> addr_t;
+
+private:
+    size_t size_tab;                            // The size of the tab
+    std::vector<addr_t> addr_tab;               // Address entries
+    std::vector<bool>   valid_tab;              // Valid entries
+
+public:
+
+    AtomicTab()
+	: addr_tab(0),
+	  valid_tab(0)
+	{
+    	size_tab=0;
+    }
+
+    AtomicTab(size_t size_tab_i)
+	: addr_tab(size_tab_i),
+	  valid_tab(size_tab_i)
+	{
+	    size_tab=size_tab_i;
+    }
+
+
+    /////////////////////////////////////////////////////////////////////
+    /* The size() function returns the size of the tab */
+    /////////////////////////////////////////////////////////////////////
+    const size_t size(){
+	    return size_tab;
+    }
+
+
+    /////////////////////////////////////////////////////////////////////
+    /* The init() function initializes the transaction tab entries */
+    /////////////////////////////////////////////////////////////////////
+    void init(){
+    	for ( size_t i=0; i<size_tab; i++) {
+		    addr_tab[i]=0;
+		    valid_tab[i]=false;
+    	}
+    }
+
+
+    /////////////////////////////////////////////////////////////////////
+    /* The set() function sets an entry 
+       Arguments :
+       - id : the id of the initiator (index of the entry)
+       - addr : the address of the lock
+     */
+    /////////////////////////////////////////////////////////////////////
+    void set(const size_t id, const addr_t addr){
+	    assert( (id<size_tab) && "Atomic Tab Error : bad entry");
+	    addr_tab[id]=addr;
+	    valid_tab[id]=true;
+	    return;
+    }
+
+
+    /////////////////////////////////////////////////////////////////////
+    /* The isatomic() function tests if the SC request corresponds to an entry
+       Arguments :
+       - id : the id of the initiator (index of the entry)
+       - addr : the address of the lock
+
+       This function return true if the request corresponds
+     */
+    /////////////////////////////////////////////////////////////////////
+    bool isatomic(const size_t id, const addr_t addr){
+	    assert( (id<size_tab) && "Atomic Tab Error : bad entry");
+	    bool test=valid_tab[id];
+	    test=test && (addr == addr_tab[id]);
+	    return test;
+    }
+
+
+    /////////////////////////////////////////////////////////////////////
+    /* The reset() function resets all the entries for this lock
+       Arguments :
+       - addr : the address of the lock
+     */
+    /////////////////////////////////////////////////////////////////////
+    void reset(const addr_t addr){
+	    for(size_t i=0 ; i<size_tab ; i++){
+		    if(addr == addr_tab[i]){
+			    valid_tab[i]=false;
+		    }
+	    }
+	    return;
+    }
+
+};
+ 
+#endif
+
+// Local Variables:
+// tab-width: 4
+// c-basic-offset: 4
+// c-file-offsets:((innamespace . 0)(inline-open . 0))
+// indent-tabs-mode: nil
+// End:
+
+// vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4
+
Index: branches/v4/platforms/almos-tsarv3-platforms/common/vci_mem_cache_v3/caba/source/include/mem_cache_directory_v3.h
===================================================================
--- branches/v4/platforms/almos-tsarv3-platforms/common/vci_mem_cache_v3/caba/source/include/mem_cache_directory_v3.h	(revision 371)
+++ branches/v4/platforms/almos-tsarv3-platforms/common/vci_mem_cache_v3/caba/source/include/mem_cache_directory_v3.h	(revision 371)
@@ -0,0 +1,562 @@
+#ifndef SOCLIB_CABA_MEM_CACHE_DIRECTORY_V3_H
+#define SOCLIB_CABA_MEM_CACHE_DIRECTORY_V3_H 
+
+#include <inttypes.h>
+#include <systemc>
+#include <cassert>
+#include "arithmetics.h"
+
+namespace soclib { namespace caba {
+
+  using namespace sc_core;
+
+  ////////////////////////////////////////////////////////////////////////
+  //                    A LRU entry 
+  ////////////////////////////////////////////////////////////////////////
+  class LruEntry {
+
+    public:
+
+      bool recent;            
+
+      void init()
+      {
+        recent=false;
+      }
+
+  }; // end class LruEntry
+
+  ////////////////////////////////////////////////////////////////////////
+  //                    An Owner
+  ////////////////////////////////////////////////////////////////////////
+  class Owner{
+    typedef uint32_t size_t;
+    
+    public:
+    // Fields
+      bool      inst;       // Is the owner an ICache ?
+      size_t    srcid;      // The SRCID of the owner
+
+    ////////////////////////
+    // Constructors
+    ////////////////////////
+      Owner(bool i_inst,size_t i_srcid){
+        inst    = i_inst;
+        srcid   = i_srcid;
+      }
+
+      Owner(const Owner &a){
+        inst    = a.inst;
+        srcid   = a.srcid;
+      }
+
+      Owner(){
+        inst    = false;
+        srcid   = 0;
+      }
+      // end constructors
+
+  }; // end class Owner
+
+
+  ////////////////////////////////////////////////////////////////////////
+  //                    A directory entry                               
+  ////////////////////////////////////////////////////////////////////////
+  class DirectoryEntry {
+
+    typedef uint32_t tag_t;
+    typedef uint32_t size_t;
+
+    public:
+
+    bool    valid;                  // entry valid
+    bool    is_cnt;                 // directory entry is in counter mode
+    bool    dirty;                  // entry dirty
+    bool    lock;                   // entry locked
+    bool    inst;                   // at least one ICache owner
+    tag_t   tag;                    // tag of the entry
+    size_t  count;                  // number of copies
+    Owner   owner;                  // an owner of the line 
+    size_t  ptr;                    // pointer to the next owner
+
+    DirectoryEntry()
+    {
+      valid         = false;
+      is_cnt        = false;
+      dirty         = false;
+      lock          = false;
+      inst          = false;
+      tag           = 0;
+      count         = 0;
+      owner.inst    = 0;
+      owner.srcid   = 0;
+      ptr           = 0;
+    }
+
+    DirectoryEntry(const DirectoryEntry &source)
+    {
+      valid         = source.valid;
+      is_cnt        = source.is_cnt;
+      dirty         = source.dirty;
+      lock          = source.lock;
+      inst          = source.inst;
+      tag           = source.tag;
+      count         = source.count;
+      owner         = source.owner;
+      ptr           = source.ptr;
+    }          
+
+    /////////////////////////////////////////////////////////////////////
+    // The init() function initializes the entry 
+    /////////////////////////////////////////////////////////////////////
+    void init()
+    {
+      valid     = false;
+      is_cnt    = false;
+      dirty     = false;
+      lock      = false;
+      inst      = false;
+      count     = 0;
+    }
+
+    /////////////////////////////////////////////////////////////////////
+    // The copy() function copies an existing source entry to a target 
+    /////////////////////////////////////////////////////////////////////
+    void copy(const DirectoryEntry &source)
+    {
+      valid	    = source.valid;
+      is_cnt    = source.is_cnt;
+      dirty	    = source.dirty;
+      lock	    = source.lock;
+      inst      = source.inst;
+      tag	    = source.tag;
+      count     = source.count;
+      owner     = source.owner;
+      ptr       = source.ptr;
+    }
+
+    ////////////////////////////////////////////////////////////////////
+    // The print() function prints the entry 
+    ////////////////////////////////////////////////////////////////////
+    void print(std::ostream &output)
+    {
+        output << "Valid = " << valid 
+                  << " ; IS COUNT = " << is_cnt 
+                  << " ; Dirty = " << dirty 
+                  << " ; Lock = "  << lock 
+                  << " ; Inst = " << inst 
+                  << " ; Tag = " << std::hex << tag 
+                  << std::dec << " ; Count = " << count 
+                  << " ; Owner = " << owner.srcid << " " 
+                  << owner.inst << " ; Pointer = " << ptr << std::endl;
+    }
+
+  }; // end class DirectoryEntry
+
+  ////////////////////////////////////////////////////////////////////////
+  //                       The directory  
+  ////////////////////////////////////////////////////////////////////////
+  class CacheDirectory {
+
+    typedef sc_dt::sc_uint<40> addr_t;
+    typedef uint32_t data_t;
+    typedef uint32_t tag_t;
+    typedef uint32_t size_t;
+
+    private:
+
+    // Directory constants
+    size_t					m_ways;
+    size_t					m_sets;
+    size_t					m_words;
+    size_t					m_width;
+
+    // the directory & lru tables
+    DirectoryEntry 				**m_dir_tab;
+    LruEntry	 				**m_lru_tab;
+
+    public:
+
+    ////////////////////////
+    // Constructor
+    ////////////////////////
+    CacheDirectory( size_t ways, size_t sets, size_t words, size_t address_width)	 
+    {
+      m_ways  = ways; 
+      m_sets  = sets;
+      m_words = words;
+      m_width = address_width;
+
+      m_dir_tab = new DirectoryEntry*[sets];
+      for ( size_t i=0; i<sets; i++ ) {
+        m_dir_tab[i] = new DirectoryEntry[ways];
+        for ( size_t j=0 ; j<ways ; j++) m_dir_tab[i][j].init();
+      }
+      m_lru_tab = new LruEntry*[sets];
+      for ( size_t i=0; i<sets; i++ ) {
+        m_lru_tab[i] = new LruEntry[ways];
+        for ( size_t j=0 ; j<ways ; j++) m_lru_tab[i][j].init();
+      }
+    } // end constructor
+
+    /////////////////
+    // Destructor
+    /////////////////
+    ~CacheDirectory()
+    {
+      for(size_t i=0 ; i<m_sets ; i++){
+        delete [] m_dir_tab[i];
+        delete [] m_lru_tab[i];
+      }
+      delete [] m_dir_tab;
+      delete [] m_lru_tab;
+    } // end destructor
+
+    /////////////////////////////////////////////////////////////////////
+    // The read() function reads a directory entry. In case of hit, the
+    // LRU is updated.
+    // Arguments :
+    // - address : the address of the entry 
+    // - way : (return argument) the way of the entry in case of hit
+    // The function returns a copy of a (valid or invalid) entry  
+    /////////////////////////////////////////////////////////////////////
+    DirectoryEntry read(const addr_t &address,size_t &way)
+    {
+
+#define L2 soclib::common::uint32_log2
+      const size_t set = (size_t)(address >> (L2(m_words) + 2)) & (m_sets - 1);
+      const tag_t  tag = (tag_t)(address >> (L2(m_sets) + L2(m_words) + 2));
+#undef L2
+
+      bool hit       = false;
+      for ( size_t i=0 ; i<m_ways ; i++ ) {
+        bool equal = ( m_dir_tab[set][i].tag == tag );
+        bool valid = m_dir_tab[set][i].valid;
+        hit = equal && valid;
+        if ( hit ) {			
+          way = i;
+          break;
+        } 
+      }
+      if ( hit ) {
+        m_lru_tab[set][way].recent = true;
+        return DirectoryEntry(m_dir_tab[set][way]);
+      } else {
+        return DirectoryEntry();
+      }
+    } // end read()
+
+    /////////////////////////////////////////////////////////////////////
+    // The write function writes a new entry, 
+    // and updates the LRU bits if necessary.
+    // Arguments :
+    // - set : the set of the entry
+    // - way : the way of the entry
+    // - entry : the entry value
+    /////////////////////////////////////////////////////////////////////
+    void write(const size_t &set, const size_t &way, const DirectoryEntry &entry)
+    {
+      assert( (set<m_sets) 
+          && "Cache Directory write : The set index is invalid");
+      assert( (way<m_ways) 
+          && "Cache Directory write : The way index is invalid");
+
+      // update Directory
+      m_dir_tab[set][way].copy(entry);
+
+      // update LRU bits
+      bool all_recent = true;
+      for ( size_t i=0 ; i<m_ways ; i++ ) {
+        if ( i != way ) all_recent = m_lru_tab[set][i].recent && all_recent;
+      }
+      if ( all_recent ) {
+        for( size_t i=0 ; i<m_ways ; i++ ) m_lru_tab[set][i].recent = false;
+      } else {
+        m_lru_tab[set][way].recent = true;
+      }
+    } // end write()
+
+    /////////////////////////////////////////////////////////////////////
+    // The print() function prints a selected directory entry
+    // Arguments :
+    // - set : the set of the entry to print
+    // - way : the way of the entry to print
+    /////////////////////////////////////////////////////////////////////
+    void print(const size_t &set, const size_t &way, std::ostream &output)
+    {
+      output << std::dec << " set : " << set << " ; way : " << way << " ; " ;
+      m_dir_tab[set][way].print(output);
+    } // end print()
+
+    /////////////////////////////////////////////////////////////////////
+    // The select() function selects a directory entry to evince.
+    // Arguments :
+    // - set   : (input argument) the set to modify
+    // - way   : (return argument) the way to evince
+    /////////////////////////////////////////////////////////////////////
+    DirectoryEntry select(const size_t &set, size_t &way)
+    {
+      assert( (set < m_sets) 
+          && "Cache Directory : (select) The set index is invalid");
+
+      for(size_t i=0; i<m_ways; i++){
+        if(!m_dir_tab[set][i].valid){
+          way=i;
+          return DirectoryEntry(m_dir_tab[set][way]);
+        }
+      }
+      for(size_t i=0; i<m_ways; i++){
+        if(!(m_lru_tab[set][i].recent) && !(m_dir_tab[set][i].lock)){
+          way=i;
+          return DirectoryEntry(m_dir_tab[set][way]);
+        }
+      }
+      for(size_t i=0; i<m_ways; i++){
+        if( !(m_lru_tab[set][i].recent) && (m_dir_tab[set][i].lock)){
+          way=i;
+          return DirectoryEntry(m_dir_tab[set][way]);
+        }
+      }
+      for(size_t i=0; i<m_ways; i++){
+        if( (m_lru_tab[set][i].recent) && !(m_dir_tab[set][i].lock)){
+          way=i;
+          return DirectoryEntry(m_dir_tab[set][way]);
+        }
+      }
+      way = 0;
+      return DirectoryEntry(m_dir_tab[set][0]);
+    } // end select()
+
+    /////////////////////////////////////////////////////////////////////
+    // 		Global initialisation function
+    /////////////////////////////////////////////////////////////////////
+    void init()
+    {
+      for ( size_t set=0 ; set<m_sets ; set++ ) {
+        for ( size_t way=0 ; way<m_ways ; way++ ) {
+          m_dir_tab[set][way].init();
+          m_lru_tab[set][way].init();
+        }
+      }
+    } // end init()
+
+  }; // end class CacheDirectory
+
+  ///////////////////////////////////////////////////////////////////////
+  //                    A Heap Entry
+  ///////////////////////////////////////////////////////////////////////
+  class HeapEntry{
+    typedef uint32_t size_t;
+
+    public:
+    // Fields of the entry
+      Owner     owner;
+      size_t    next;
+
+    ////////////////////////
+    // Constructor
+    ////////////////////////
+      HeapEntry()
+      :owner(false,0)
+      {
+        next = 0;
+      } // end constructor
+
+    ////////////////////////
+    // Constructor
+    ////////////////////////
+      HeapEntry(const HeapEntry &entry){
+        owner.srcid = entry.owner.srcid;
+        owner.inst  = entry.owner.inst;
+        next        = entry.next;
+      } // end constructor
+
+    /////////////////////////////////////////////////////////////////////
+    // The copy() function copies an existing source entry to a target 
+    /////////////////////////////////////////////////////////////////////
+      void copy(const HeapEntry &entry){
+        owner.srcid = entry.owner.srcid;
+        owner.inst  = entry.owner.inst;
+        next        = entry.next;
+      } // end copy()
+
+    ////////////////////////////////////////////////////////////////////
+    // The print() function prints the entry 
+    ////////////////////////////////////////////////////////////////////
+      void print(std::ostream &output){
+        output
+        << " -- owner.srcid : " << std::dec << owner.srcid << std::endl
+        << " -- owner.inst  : " << std::dec << owner.inst << std::endl
+        << " -- next        : " << std::dec << next << std::endl;
+
+      } // end print()
+
+  }; // end class HeapEntry
+
+  ////////////////////////////////////////////////////////////////////////
+  //                        The Heap 
+  ////////////////////////////////////////////////////////////////////////
+  class HeapDirectory{
+    typedef uint32_t size_t;
+    
+    private:
+    // Registers and the heap
+      size_t    ptr_free;
+      bool      full;
+      HeapEntry *m_heap_tab;
+
+    // Constants for debugging purpose
+      size_t    tab_size;
+
+    public:
+    ////////////////////////
+    // Constructor
+    ////////////////////////
+      HeapDirectory(uint32_t size){
+        assert(size>0 && "Memory Cache, HeapDirectory constructor : invalid size");
+        ptr_free    = 0;
+        full        = false;
+        m_heap_tab  = new HeapEntry[size];
+        tab_size    = size;
+      } // end constructor
+
+    /////////////////
+    // Destructor
+    /////////////////
+      ~HeapDirectory(){
+        delete [] m_heap_tab;
+      } // end destructor
+
+    /////////////////////////////////////////////////////////////////////
+    // 		Global initialisation function
+    /////////////////////////////////////////////////////////////////////
+      void init(){
+        ptr_free=0;
+        full=false;
+        for(size_t i=0; i< tab_size-1;i++){
+          m_heap_tab[i].next = i+1;
+        }
+        m_heap_tab[tab_size-1].next = tab_size-1;
+        return;
+      }
+
+    /////////////////////////////////////////////////////////////////////
+    // The print() function prints a selected directory entry
+    // Arguments :
+    // - ptr : the pointer to the entry to print
+    /////////////////////////////////////////////////////////////////////
+      void print(const size_t &ptr, std::ostream &output){
+        output << "Heap, printing the entry : " << std::dec << ptr << std::endl;
+        m_heap_tab[ptr].print(output);
+      } // end print()
+
+    /////////////////////////////////////////////////////////////////////
+    // The print_list() function prints a list from selected directory entry
+    // Arguments :
+    // - ptr : the pointer to the first entry to print
+    /////////////////////////////////////////////////////////////////////
+      void print_list(const size_t &ptr, std::ostream &output){
+        bool end = false;
+        size_t ptr_temp = ptr;
+        output << "Heap, printing the list from : " << std::dec << ptr << std::endl;
+        while(!end){
+            m_heap_tab[ptr_temp].print(output);
+            if(ptr_temp == m_heap_tab[ptr_temp].next) end = true;
+            ptr_temp = m_heap_tab[ptr_temp].next;
+        } 
+      } // end print_list()
+
+
+    /////////////////////////////////////////////////////////////////////
+    // The is_full() function return true if the heap is full.
+    /////////////////////////////////////////////////////////////////////
+      bool is_full(){
+        return full;
+      } // end is_full()
+
+    /////////////////////////////////////////////////////////////////////
+    // The next_free_ptr() function returns the pointer 
+    // to the next free entry.
+    /////////////////////////////////////////////////////////////////////
+      size_t next_free_ptr(){
+        return ptr_free;
+      } // end next_free_ptr()
+
+    /////////////////////////////////////////////////////////////////////
+    // The next_free_entry() function returns 
+    // a copy of the next free entry.
+    /////////////////////////////////////////////////////////////////////
+      HeapEntry next_free_entry(){
+        return HeapEntry(m_heap_tab[ptr_free]);
+      } // end next_free_entry()
+   
+    /////////////////////////////////////////////////////////////////////
+    // The write_free_entry() function modify the next free entry.
+    // Arguments :
+    // - entry : the entry to write
+    /////////////////////////////////////////////////////////////////////
+      void write_free_entry(const HeapEntry &entry){
+        m_heap_tab[ptr_free].copy(entry);
+      } // end write_free_entry()
+
+    /////////////////////////////////////////////////////////////////////
+    // The write_free_ptr() function writes the pointer
+    // to the next free entry
+    /////////////////////////////////////////////////////////////////////
+      void write_free_ptr(const size_t &ptr){
+        assert( (ptr<tab_size) && "HeapDirectory error : try to write a wrong free pointer");
+        ptr_free = ptr;
+      } // end write_free_ptr()
+
+    /////////////////////////////////////////////////////////////////////
+    // The set_full() function sets the full bit (to true).
+    /////////////////////////////////////////////////////////////////////
+      void set_full(){
+        full = true;
+      } // end set_full()
+
+    /////////////////////////////////////////////////////////////////////
+    // The unset_full() function unsets the full bit (to false).
+    /////////////////////////////////////////////////////////////////////
+      void unset_full(){
+        full = false;
+      } // end unset_full()
+
+    /////////////////////////////////////////////////////////////////////
+    // The read() function returns a copy of
+    // the entry pointed by the argument
+    // Arguments :
+    //  - ptr : the pointer to the entry to read
+    /////////////////////////////////////////////////////////////////////
+      HeapEntry read(const size_t &ptr){
+        assert( (ptr<tab_size) && "HeapDirectory error : try to write a wrong free pointer");
+        return HeapEntry(m_heap_tab[ptr]);
+      } // end read()
+
+    /////////////////////////////////////////////////////////////////////
+    // The write() function writes an entry in the heap
+    // Arguments :
+    //  - ptr : the pointer to the entry to replace
+    //  - entry : the entry to write
+    /////////////////////////////////////////////////////////////////////
+      void write(const size_t &ptr, const HeapEntry &entry){
+        assert( (ptr<tab_size) && "HeapDirectory error : try to write a wrong free pointer");
+        m_heap_tab[ptr].copy(entry);
+      } // end write()
+
+  }; // end class HeapDirectory
+
+
+}} // end namespaces
+
+#endif
+
+// Local Variables:
+// tab-width: 4
+// c-basic-offset: 4
+// c-file-offsets:((innamespace . 0)(inline-open . 0))
+// indent-tabs-mode: nil
+// End:
+
+// vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4
+
Index: branches/v4/platforms/almos-tsarv3-platforms/common/vci_mem_cache_v3/caba/source/include/update_tab_v3.h
===================================================================
--- branches/v4/platforms/almos-tsarv3-platforms/common/vci_mem_cache_v3/caba/source/include/update_tab_v3.h	(revision 371)
+++ branches/v4/platforms/almos-tsarv3-platforms/common/vci_mem_cache_v3/caba/source/include/update_tab_v3.h	(revision 371)
@@ -0,0 +1,402 @@
+#ifndef UPDATE_TAB_V3_H_
+#define UPDATE_TAB_V3_H_
+
+#include <inttypes.h>
+#include <systemc>
+#include <cassert>
+#include "arithmetics.h"
+
+////////////////////////////////////////////////////////////////////////
+//                  An update tab entry    
+////////////////////////////////////////////////////////////////////////
+class UpdateTabEntry {
+  typedef uint32_t size_t;
+  typedef sc_dt::sc_uint<40> addr_t;
+
+  public:
+  bool 	valid;                // It is a valid pending transaction
+  bool	update;               // It is an update transaction
+  bool  brdcast;              // It is a broadcast invalidate
+  bool  rsp;                  // It needs a response to the initiator
+  size_t 	srcid;        // The srcid of the initiator which wrote the data
+  size_t 	trdid;        // The trdid of the initiator which wrote the data
+  size_t 	pktid;        // The pktid of the initiator which wrote the data
+  addr_t	nline;	      // The identifier of the cache line
+  size_t 	count;        // The number of acknowledge responses to receive
+
+  UpdateTabEntry(){
+    valid	= false;
+    update  = false;
+    brdcast = false;
+    rsp     = false;
+    srcid	= 0;
+    trdid	= 0;
+    pktid	= 0;
+    nline	= 0;
+    count	= 0;
+  }
+
+  UpdateTabEntry(bool   i_valid, 
+      bool   i_update,
+      bool   i_brdcast,
+      bool   i_rsp,
+      size_t i_srcid, 
+      size_t i_trdid, 
+      size_t i_pktid, 
+      addr_t i_nline,
+      size_t i_count) 
+  {
+    valid		= i_valid;
+    update	    = i_update;
+    brdcast     = i_brdcast;
+    rsp         = i_rsp;
+    srcid		= i_srcid;
+    trdid		= i_trdid;
+    pktid		= i_pktid;
+    nline		= i_nline;
+    count		= i_count;
+  }
+
+  UpdateTabEntry(const UpdateTabEntry &source)
+  {
+    valid   = source.valid;
+    update  = source.update;
+    brdcast = source.brdcast;
+    rsp     = source.rsp;
+    srcid   = source.srcid;
+    trdid   = source.trdid;
+    pktid   = source.pktid;
+    nline   = source.nline;
+    count   = source.count;
+  }
+
+  ////////////////////////////////////////////////////
+  // The init() function initializes the entry 
+  ///////////////////////////////////////////////////
+  void init()
+  {
+    valid  = false;
+    update = false;
+    brdcast= false;
+    rsp    = false;
+    srcid  = 0;
+    trdid  = 0;
+    pktid  = 0;
+    nline  = 0;
+    count  = 0;
+  }
+
+  ////////////////////////////////////////////////////////////////////
+  // The copy() function copies an existing entry
+  // Its arguments are :
+  // - source : the update tab entry to copy
+  ////////////////////////////////////////////////////////////////////
+  void copy(const UpdateTabEntry &source)
+  {
+    valid  = source.valid;
+    update = source.update;
+    brdcast= source.brdcast;
+    rsp    = source.rsp;
+    srcid  = source.srcid;
+    trdid  = source.trdid;
+    pktid  = source.pktid;
+    nline  = source.nline;
+    count  = source.count;
+  }
+
+  ////////////////////////////////////////////////////////////////////
+  // The print() function prints the entry  
+  ////////////////////////////////////////////////////////////////////
+  void print(){
+    std::cout << std::dec << "valid  = " << valid  << std::endl;
+    std::cout << "update = " << update << std::endl;
+    std::cout << "brdcast= " << brdcast<< std::endl;
+    std::cout << "rsp    = " << rsp    << std::endl;
+    std::cout << "srcid  = " << srcid  << std::endl; 
+    std::cout << "trdid  = " << trdid  << std::endl; 
+    std::cout << "pktid  = " << pktid  << std::endl; 
+    std::cout << std::hex << "nline  = " << nline  << std::endl;
+    std::cout << std::dec << "count  = " << count  << std::endl;
+  }
+};
+
+////////////////////////////////////////////////////////////////////////
+//                        The update tab             
+////////////////////////////////////////////////////////////////////////
+class UpdateTab{
+
+  typedef uint32_t size_t;
+  typedef sc_dt::sc_uint<40> addr_t;
+
+  private:
+  size_t size_tab;
+  std::vector<UpdateTabEntry> tab;
+
+  public:
+
+  UpdateTab()
+    : tab(0)
+  {
+    size_tab=0;
+  }
+
+  UpdateTab(size_t size_tab_i)
+    : tab(size_tab_i)
+  {
+    size_tab=size_tab_i;
+  }
+
+  ////////////////////////////////////////////////////////////////////
+  // The size() function returns the size of the tab  
+  ////////////////////////////////////////////////////////////////////
+  const size_t size(){
+    return size_tab;
+  }
+
+
+  ////////////////////////////////////////////////////////////////////
+  // The size() function returns the size of the tab  
+  ////////////////////////////////////////////////////////////////////
+  void print(){
+    for(size_t i=0; i<size_tab; i++) {
+      std::cout << "UPDATE TAB ENTRY " << std::dec << i << "--------" << std::endl;
+      tab[i].print();
+    }
+    return;
+  }
+
+
+  /////////////////////////////////////////////////////////////////////
+  // The init() function initializes the tab 
+  /////////////////////////////////////////////////////////////////////
+  void init(){
+    for ( size_t i=0; i<size_tab; i++) {
+      tab[i].init();
+    }
+  }
+
+
+  /////////////////////////////////////////////////////////////////////
+  // The reads() function reads an entry 
+  // Arguments :
+  // - entry : the entry to read
+  // This function returns a copy of the entry.
+  /////////////////////////////////////////////////////////////////////
+  UpdateTabEntry read (size_t entry)
+  {
+    assert(entry<size_tab && "Bad Update Tab Entry");
+    return UpdateTabEntry(tab[entry]);
+  }
+
+  ///////////////////////////////////////////////////////////////////////////
+  // The set() function writes an entry in the Update Table
+  // Arguments :
+  // - update : transaction type (bool)
+  // - srcid : srcid of the initiator
+  // - trdid : trdid of the initiator
+  // - pktid : pktid of the initiator
+  // - count : number of expected responses
+  // - index : (return argument) index of the selected entry
+  // This function returns true if the write successed (an entry was empty).
+  ///////////////////////////////////////////////////////////////////////////
+  bool set(const bool	update,
+      const bool   brdcast,
+      const bool   rsp,
+      const size_t srcid,
+      const size_t trdid,
+      const size_t pktid,
+      const addr_t nline,
+      const size_t count,
+      size_t &index)
+  {
+    for ( size_t i=0 ; i<size_tab ; i++ ) {
+      if( !tab[i].valid ) {
+        tab[i].valid		= true;
+        tab[i].update		= update;
+        tab[i].brdcast      = brdcast;
+        tab[i].rsp          = rsp;
+        tab[i].srcid		= (size_t) srcid;
+        tab[i].trdid		= (size_t) trdid;
+        tab[i].pktid		= (size_t) pktid;
+        tab[i].nline		= (addr_t) nline;
+        tab[i].count		= (size_t) count;
+        index			    = i;
+        return true;
+      }
+    }
+    return false;
+  } // end set()
+
+  /////////////////////////////////////////////////////////////////////
+  // The decrement() function decrements the counter for a given entry.
+  // Arguments :
+  // - index   : the index of the entry
+  // - counter : (return argument) value of the counter after decrement
+  // This function returns true if the entry is valid.
+  /////////////////////////////////////////////////////////////////////
+  bool decrement( const size_t index,
+      size_t &counter ) 
+  {
+    assert((index<size_tab) && "Bad Update Tab Entry");
+    if ( tab[index].valid ) {
+      tab[index].count--;
+      counter = tab[index].count;
+      return true;
+    } else {
+      return false;
+    }
+  }
+
+  /////////////////////////////////////////////////////////////////////
+  // The is_full() function returns true if the table is full
+  /////////////////////////////////////////////////////////////////////
+  bool is_full()
+  {
+    for(size_t i = 0 ; i < size_tab ; i++){
+      if(!tab[i].valid){
+        return false;
+      }
+    }
+    return true;
+  }
+
+  /////////////////////////////////////////////////////////////////////
+  // The need_rsp() function returns the need of a response
+  // Arguments :
+  // - index : the index of the entry
+  /////////////////////////////////////////////////////////////////////
+  bool need_rsp(const size_t index)
+  {
+    assert(index<size_tab && "Bad Update Tab Entry");
+    return tab[index].rsp;	
+  }
+
+  /////////////////////////////////////////////////////////////////////
+  // The is_update() function returns the transaction type
+  // Arguments :
+  // - index : the index of the entry
+  /////////////////////////////////////////////////////////////////////
+  bool is_brdcast(const size_t index)
+  {
+    assert(index<size_tab && "Bad Update Tab Entry");
+    return tab[index].brdcast;	
+  }
+
+  /////////////////////////////////////////////////////////////////////
+  // The is_update() function returns the transaction type
+  // Arguments :
+  // - index : the index of the entry
+  /////////////////////////////////////////////////////////////////////
+  bool is_update(const size_t index)
+  {
+    assert(index<size_tab && "Bad Update Tab Entry");
+    return tab[index].update;	
+  }
+
+  /////////////////////////////////////////////////////////////////////
+  // The srcid() function returns the srcid value
+  // Arguments :
+  // - index : the index of the entry
+  /////////////////////////////////////////////////////////////////////
+  size_t srcid(const size_t index)
+  {
+    assert(index<size_tab && "Bad Update Tab Entry");
+    return tab[index].srcid;	
+  }
+
+  /////////////////////////////////////////////////////////////////////
+  // The trdid() function returns the trdid value
+  // Arguments :
+  // - index : the index of the entry
+  /////////////////////////////////////////////////////////////////////
+  size_t trdid(const size_t index)
+  {
+    assert(index<size_tab && "Bad Update Tab Entry");
+    return tab[index].trdid;	
+  }
+
+  /////////////////////////////////////////////////////////////////////
+  // The pktid() function returns the pktid value
+  // Arguments :
+  // - index : the index of the entry
+  /////////////////////////////////////////////////////////////////////
+  size_t pktid(const size_t index)
+  {
+    assert(index<size_tab && "Bad Update Tab Entry");
+    return tab[index].pktid;	
+  }
+
+  /////////////////////////////////////////////////////////////////////
+  // The nline() function returns the nline value
+  // Arguments :
+  // - index : the index of the entry
+  /////////////////////////////////////////////////////////////////////
+  addr_t nline(const size_t index)
+  {
+    assert(index<size_tab && "Bad Update Tab Entry");
+    return tab[index].nline;
+  }
+
+  /////////////////////////////////////////////////////////////////////
+  // The search_inval() function returns the index of the entry in UPT
+  // Arguments :
+  // - nline : the line number of the entry in the directory
+  /////////////////////////////////////////////////////////////////////
+  bool search_inval(const addr_t nline,size_t &index)
+  {
+    size_t i ;
+
+    for (i = 0 ; i < size_tab ; i++){
+      if((tab[i].nline == nline) && tab[i].valid){
+        if(!tab[i].update){
+          index = i ;
+          return true;
+        }
+      }
+    }
+    return false;
+  }
+
+  /////////////////////////////////////////////////////////////////////
+  // The read_nline() function returns the index of the entry in UPT
+  // Arguments :
+  // - nline : the line number of the entry in the directory
+  /////////////////////////////////////////////////////////////////////
+  bool read_nline(const addr_t nline,size_t &index) 
+  {
+    size_t i ;
+
+    for (i = 0 ; i < size_tab ; i++){
+      if((tab[i].nline == nline) && tab[i].valid){
+        index = i ;
+        return true;
+      }
+    }
+    return false;
+  }
+
+  /////////////////////////////////////////////////////////////////////
+  // The clear() function erases an entry of the tab
+  // Arguments :
+  // - index : the index of the entry
+  /////////////////////////////////////////////////////////////////////       
+  void clear(const size_t index)
+  {
+    assert(index<size_tab && "Bad Update Tab Entry");
+    tab[index].valid=false;
+    return;	
+  }
+
+};
+
+#endif
+
+// Local Variables:
+// tab-width: 4
+// c-basic-offset: 4
+// c-file-offsets:((innamespace . 0)(inline-open . 0))
+// indent-tabs-mode: nil
+// End:
+
+// vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4
+
Index: branches/v4/platforms/almos-tsarv3-platforms/common/vci_mem_cache_v3/caba/source/include/vci_mem_cache_v3.h
===================================================================
--- branches/v4/platforms/almos-tsarv3-platforms/common/vci_mem_cache_v3/caba/source/include/vci_mem_cache_v3.h	(revision 371)
+++ branches/v4/platforms/almos-tsarv3-platforms/common/vci_mem_cache_v3/caba/source/include/vci_mem_cache_v3.h	(revision 371)
@@ -0,0 +1,733 @@
+/* -*- c++ -*-
+ * File         : vci_mem_cache_v3.h
+ * Date         : 26/10/2008
+ * Copyright    : UPMC / LIP6
+ * Authors      : Alain Greiner / Eric Guthmuller
+ *
+ * SOCLIB_LGPL_HEADER_BEGIN
+ *
+ * This file is part of SoCLib, GNU LGPLv2.1.
+ *
+ * SoCLib is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU Lesser General Public License as published
+ * by the Free Software Foundation; version 2.1 of the License.
+ *
+ * SoCLib is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with SoCLib; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301 USA
+ *
+ * SOCLIB_LGPL_HEADER_END
+ *
+ * Maintainers: alain eric.guthmuller@polytechnique.edu
+ */
+/*
+ *
+ * Modifications done by Christophe Choichillon on the 7/04/2009:
+ * - Adding new states in the CLEANUP FSM : CLEANUP_UPT_LOCK and CLEANUP_UPT_WRITE
+ * - Adding a new VCI target port for the CLEANUP network
+ * - Adding new state in the ALLOC_UPT_FSM : ALLOC_UPT_CLEANUP
+ * 
+ * Modifications to do :
+ * - Adding new variables used by the CLEANUP FSM
+ *
+ */
+
+#ifndef SOCLIB_CABA_MEM_CACHE_V3_H
+#define SOCLIB_CABA_MEM_CACHE_V3_H
+
+#include <inttypes.h>
+#include <systemc>
+#include <list>
+#include <cassert>
+#include <iostream>
+#include <fstream>
+#include "arithmetics.h"
+#include "alloc_elems.h"
+#include "caba_base_module.h"
+#include "vci_target.h"
+#include "vci_initiator.h"
+#include "generic_fifo.h"
+#include "mapping_table.h"
+#include "int_tab.h"
+#include "mem_cache_directory_v3.h"
+#include "xram_transaction_v3.h"
+#include "update_tab_v3.h"
+#include "atomic_tab_v3.h"
+#include "config.h"
+
+#define TRANSACTION_TAB_LINES   CONFIG_MEMC_TRANSACTION_TAB_LINES     // Number of lines in the transaction tab
+#define UPDATE_TAB_LINES        CONFIG_MEMC_UPDATE_TAB_LINES    // Number of lines in the update tab
+
+namespace soclib {  namespace caba {
+  using namespace sc_core;
+
+  template<typename vci_param>
+    class VciMemCacheV3
+    : public soclib::caba::BaseModule
+    {
+      typedef sc_dt::sc_uint<40> addr_t;
+      typedef typename vci_param::fast_addr_t vci_addr_t;
+      typedef uint32_t data_t;
+      typedef uint32_t tag_t;
+      typedef uint32_t size_t;
+      typedef uint32_t be_t;
+      typedef uint32_t copy_t;
+
+      /* States of the TGT_CMD fsm */
+      enum tgt_cmd_fsm_state_e{
+        TGT_CMD_IDLE,
+        TGT_CMD_READ,
+        TGT_CMD_READ_EOP,
+        TGT_CMD_WRITE,
+        TGT_CMD_ATOMIC,
+      };
+
+      /* States of the TGT_RSP fsm */
+      enum tgt_rsp_fsm_state_e{
+        TGT_RSP_READ_IDLE,
+        TGT_RSP_WRITE_IDLE,
+        TGT_RSP_LLSC_IDLE,
+        TGT_RSP_XRAM_IDLE,
+        TGT_RSP_INIT_IDLE,
+        TGT_RSP_CLEANUP_IDLE,
+        TGT_RSP_READ,
+        TGT_RSP_WRITE,
+        TGT_RSP_LLSC,
+        TGT_RSP_XRAM,
+        TGT_RSP_INIT,
+        TGT_RSP_CLEANUP,
+      };
+
+      /* States of the INIT_CMD fsm */
+      enum init_cmd_fsm_state_e{
+        INIT_CMD_INVAL_IDLE,
+        INIT_CMD_INVAL_NLINE,
+        INIT_CMD_XRAM_BRDCAST,
+        INIT_CMD_UPDT_IDLE,
+        INIT_CMD_WRITE_BRDCAST,
+        INIT_CMD_UPDT_NLINE,
+        INIT_CMD_UPDT_INDEX,
+        INIT_CMD_UPDT_DATA,
+        INIT_CMD_SC_UPDT_IDLE,
+        INIT_CMD_SC_BRDCAST,
+        INIT_CMD_SC_UPDT_NLINE,
+        INIT_CMD_SC_UPDT_INDEX,
+        INIT_CMD_SC_UPDT_DATA,
+      };
+
+      /* States of the INIT_RSP fsm */
+      enum init_rsp_fsm_state_e{
+        INIT_RSP_IDLE,
+        INIT_RSP_UPT_LOCK,
+        INIT_RSP_UPT_CLEAR,
+        INIT_RSP_END,
+      };
+
+      /* States of the READ fsm */
+      enum read_fsm_state_e{
+        READ_IDLE,
+        READ_DIR_LOCK,
+        READ_DIR_HIT,
+        READ_HEAP_LOCK,
+        READ_HEAP_WRITE,
+        READ_HEAP_ERASE,
+        READ_HEAP_LAST,
+        READ_RSP,
+        READ_TRT_LOCK,
+        READ_TRT_SET,
+        READ_XRAM_REQ,
+      };
+
+      /* States of the WRITE fsm */
+      enum write_fsm_state_e{
+        WRITE_IDLE,
+        WRITE_NEXT,
+        WRITE_DIR_LOCK,
+        WRITE_DIR_HIT_READ,
+        WRITE_DIR_HIT,
+        WRITE_DIR_HIT_RSP,
+        WRITE_UPT_LOCK,
+        WRITE_HEAP_LOCK,
+        WRITE_UPT_REQ,
+        WRITE_UPDATE,
+        WRITE_UPT_DEC,
+        WRITE_RSP,
+        WRITE_TRT_LOCK,
+        WRITE_TRT_DATA,
+        WRITE_TRT_SET,
+        WRITE_WAIT,
+        WRITE_XRAM_REQ,
+        WRITE_TRT_WRITE_LOCK,
+        WRITE_INVAL_LOCK,
+        WRITE_DIR_INVAL,
+        WRITE_INVAL,
+        WRITE_XRAM_SEND,
+        WRITE_HEAP_ERASE,
+        WRITE_HEAP_LAST,
+      };
+
+      /* States of the IXR_RSP fsm */
+      enum ixr_rsp_fsm_state_e{
+        IXR_RSP_IDLE,
+        IXR_RSP_ACK,
+        IXR_RSP_TRT_ERASE,
+        IXR_RSP_TRT_READ,
+      };
+
+      /* States of the XRAM_RSP fsm */
+      enum xram_rsp_fsm_state_e{
+        XRAM_RSP_IDLE,
+        XRAM_RSP_TRT_COPY,
+        XRAM_RSP_TRT_DIRTY,
+        XRAM_RSP_DIR_LOCK,
+        XRAM_RSP_DIR_UPDT,
+        XRAM_RSP_DIR_RSP,
+        XRAM_RSP_INVAL_LOCK,
+        XRAM_RSP_INVAL_WAIT,
+        XRAM_RSP_INVAL,
+        XRAM_RSP_WRITE_DIRTY,
+        XRAM_RSP_HEAP_ERASE,
+        XRAM_RSP_HEAP_LAST,
+      };
+
+      /* States of the IXR_CMD fsm */
+      enum ixr_cmd_fsm_state_e{
+        IXR_CMD_READ_IDLE,
+        IXR_CMD_WRITE_IDLE,
+        IXR_CMD_LLSC_IDLE,
+        IXR_CMD_XRAM_IDLE,
+        IXR_CMD_READ_NLINE,
+        IXR_CMD_WRITE_NLINE,
+        IXR_CMD_LLSC_NLINE,
+        IXR_CMD_XRAM_DATA,
+      };
+
+      /* States of the LLSC fsm */
+      enum llsc_fsm_state_e{
+        LLSC_IDLE,
+        LL_DIR_LOCK,
+        LL_DIR_HIT,
+        LL_RSP,
+        SC_DIR_LOCK,
+        SC_DIR_HIT,
+        SC_UPT_LOCK,
+        SC_WAIT,
+        SC_HEAP_LOCK,
+        SC_UPT_REQ,
+        SC_UPDATE,
+        SC_TRT_LOCK,
+        SC_INVAL_LOCK,
+        SC_DIR_INVAL,
+        SC_INVAL,
+        SC_XRAM_SEND,
+        SC_HEAP_ERASE,
+        SC_HEAP_LAST, 
+        SC_RSP_FALSE,
+        SC_RSP_TRUE,
+        LLSC_TRT_LOCK,
+        LLSC_TRT_SET,
+        LLSC_XRAM_REQ,
+      };
+
+      /* States of the CLEANUP fsm */
+      enum cleanup_fsm_state_e{
+        CLEANUP_IDLE,
+        CLEANUP_DIR_LOCK,
+        CLEANUP_DIR_WRITE,
+        CLEANUP_HEAP_LOCK,
+        CLEANUP_HEAP_SEARCH,
+        CLEANUP_HEAP_CLEAN,
+        CLEANUP_HEAP_FREE,
+        CLEANUP_UPT_LOCK,
+        CLEANUP_UPT_WRITE,
+        CLEANUP_WRITE_RSP,
+        CLEANUP_RSP,
+      };
+
+      /* States of the ALLOC_DIR fsm */
+      enum alloc_dir_fsm_state_e{
+        ALLOC_DIR_READ,
+        ALLOC_DIR_WRITE,
+        ALLOC_DIR_LLSC,
+        ALLOC_DIR_CLEANUP,
+        ALLOC_DIR_XRAM_RSP,
+      };
+
+      /* States of the ALLOC_TRT fsm */
+      enum alloc_trt_fsm_state_e{
+        ALLOC_TRT_READ,
+        ALLOC_TRT_WRITE,
+        ALLOC_TRT_LLSC,
+        ALLOC_TRT_XRAM_RSP,
+        ALLOC_TRT_IXR_RSP,
+      };
+
+      /* States of the ALLOC_UPT fsm */
+      enum alloc_upt_fsm_state_e{
+        ALLOC_UPT_WRITE,
+        ALLOC_UPT_XRAM_RSP,
+        ALLOC_UPT_INIT_RSP,
+        ALLOC_UPT_CLEANUP,
+        ALLOC_UPT_LLSC,
+      };
+
+      /* States of the ALLOC_HEAP fsm */
+      enum alloc_heap_fsm_state_e{
+        ALLOC_HEAP_READ,
+        ALLOC_HEAP_WRITE,
+        ALLOC_HEAP_LLSC,
+        ALLOC_HEAP_CLEANUP,
+        ALLOC_HEAP_XRAM_RSP,
+      };
+
+      uint32_t	   m_cpt_cycles;            // Counter of cycles 
+      uint32_t	   m_cpt_read;              // Number of READ transactions
+      uint32_t	   m_cpt_read_miss;         // Number of MISS READ 
+      uint32_t	   m_cpt_write;             // Number of WRITE transactions
+      uint32_t	   m_cpt_write_miss;        // Number of MISS WRITE
+      uint32_t     m_cpt_write_cells;	    // Cumulated length for WRITE transactions
+      uint32_t     m_cpt_write_dirty;	    // Cumulated length for WRITE transactions
+      uint32_t	   m_cpt_update;            // Number of UPDATE transactions
+      uint32_t	   m_cpt_update_mult;       // Number of targets for UPDATE
+      uint32_t	   m_cpt_inval;             // Number of INVAL  transactions
+      uint32_t	   m_cpt_inval_mult;        // Number of targets for INVAL  
+      uint32_t	   m_cpt_inval_brdcast;     // Number of BROADCAST INVAL  
+      uint32_t	   m_cpt_cleanup;           // Number of CLEANUP transactions
+      uint32_t	   m_cpt_ll;                // Number of LL transactions
+      uint32_t	   m_cpt_sc;                // Number of SC transactions
+      uint32_t     m_total_cycles;
+      unsigned long m_waiting_cycles;        // Number of TGT FSM waiting cycles 
+      double        m_wait_threshold;       // Trace threshold upon waiting cycles percentage
+
+      protected:
+
+      SC_HAS_PROCESS(VciMemCacheV3);
+
+      public:
+      sc_in<bool> 			  	p_clk;
+      sc_in<bool> 			  	p_resetn;
+      soclib::caba::VciTarget<vci_param>    	p_vci_tgt;
+      soclib::caba::VciTarget<vci_param>    	p_vci_tgt_cleanup;
+      soclib::caba::VciInitiator<vci_param> 	p_vci_ini;	
+      soclib::caba::VciInitiator<vci_param> 	p_vci_ixr;
+
+      VciMemCacheV3(
+          sc_module_name name,                              // Instance Name 
+          const soclib::common::MappingTable &mtp,          // Mapping table for primary requets
+          const soclib::common::MappingTable &mtc,          // Mapping table for coherence requets
+          const soclib::common::MappingTable &mtx,          // Mapping table for XRAM
+          const soclib::common::IntTab &vci_ixr_index,      // VCI port to XRAM (initiator)
+          const soclib::common::IntTab &vci_ini_index,      // VCI port to PROC (initiator)
+          const soclib::common::IntTab &vci_tgt_index,      // VCI port to PROC (target)
+          const soclib::common::IntTab &vci_tgt_index_cleanup,    // VCI port to PROC (target) for cleanup
+          size_t nways,                                     // Number of ways per set 
+          size_t nsets,                                     // Number of sets
+          size_t nwords,                                    // Number of words per line
+          size_t heap_size=1024);                           // Size of the heap
+
+      ~VciMemCacheV3();
+
+      void transition();
+
+      void genMoore();
+
+      void print_stats();
+      void clear_stats();
+
+      private:
+        
+        void print_log();
+        void print_trace_to_log_file();
+        
+      // Component attributes
+      const size_t              m_initiators;           // Number of initiators
+      const size_t              m_heap_size;            // Size of the heap
+      const size_t              m_ways;                 // Number of ways in a set
+      const size_t              m_sets;                 // Number of cache sets
+      const size_t              m_words;		        // Number of words in a line
+      const size_t              m_srcid_ixr;		    // Srcid for requests to XRAM 
+      const size_t              m_srcid_ini;		    // Srcid for requests to processors
+      std::list<soclib::common::Segment>  m_seglist;    // memory cached into the cache
+      std::list<soclib::common::Segment>  m_cseglist;   // coherence segment for the cache
+      vci_addr_t        		*m_coherence_table; 	// address(srcid)
+      AtomicTab                 m_atomic_tab;           // atomic access table
+      TransactionTab      		m_transaction_tab;	    // xram transaction table
+      UpdateTab                 m_update_tab;		    // pending update & invalidate 
+      CacheDirectory			m_cache_directory;	    // data cache directory
+      HeapDirectory             m_heap_directory;       // heap directory
+
+      data_t	        	       ***m_cache_data;		// data array[set][way][word]
+        std::ofstream             m_log;
+      size_t                    m_tm_start;
+      long long                 m_debug_start;
+      size_t                    m_tm_end;
+      size_t                    m_period;
+
+
+      // adress masks
+      const soclib::common::AddressMaskingTable<vci_addr_t>   m_x;
+      const soclib::common::AddressMaskingTable<vci_addr_t>   m_y;
+      const soclib::common::AddressMaskingTable<vci_addr_t>   m_z;
+      const soclib::common::AddressMaskingTable<vci_addr_t>   m_nline; 
+
+      // broadcast address
+      vci_addr_t broadcast_addr;
+
+      //////////////////////////////////////////////////
+      // Others registers
+      //////////////////////////////////////////////////
+      size_t m_copy_threshold;
+      sc_signal<size_t>   r_copies_limit; // Limit of the number of copies for one line
+
+      //////////////////////////////////////////////////
+      // Registers controlled by the TGT_CMD fsm
+      //////////////////////////////////////////////////
+
+      // Fifo between TGT_CMD fsm and READ fsm
+      GenericFifo<uint64_t>  m_cmd_read_addr_fifo;
+      GenericFifo<size_t>    m_cmd_read_length_fifo;
+      GenericFifo<size_t>    m_cmd_read_srcid_fifo;
+      GenericFifo<size_t>    m_cmd_read_trdid_fifo;
+      GenericFifo<size_t>    m_cmd_read_pktid_fifo;
+
+      // Fifo between TGT_CMD fsm and WRITE fsm    
+      GenericFifo<uint64_t>  m_cmd_write_addr_fifo;
+      GenericFifo<bool>      m_cmd_write_eop_fifo;
+      GenericFifo<size_t>    m_cmd_write_srcid_fifo;
+      GenericFifo<size_t>    m_cmd_write_trdid_fifo;
+      GenericFifo<size_t>    m_cmd_write_pktid_fifo;
+      GenericFifo<data_t>    m_cmd_write_data_fifo;
+      GenericFifo<be_t>	     m_cmd_write_be_fifo;
+
+      // Fifo between TGT_CMD fsm and LLSC fsm
+      GenericFifo<uint64_t>  m_cmd_llsc_addr_fifo;
+      GenericFifo<bool>      m_cmd_llsc_sc_fifo;
+      GenericFifo<size_t>    m_cmd_llsc_srcid_fifo;
+      GenericFifo<size_t>    m_cmd_llsc_trdid_fifo;
+      GenericFifo<size_t>    m_cmd_llsc_pktid_fifo;
+      GenericFifo<data_t>    m_cmd_llsc_wdata_fifo;
+
+      sc_signal<int>         r_tgt_cmd_fsm;
+
+      sc_signal<size_t>	     r_index;
+      size_t nseg;
+      size_t ncseg;
+      soclib::common::Segment  **m_seg;
+      soclib::common::Segment  **m_cseg;
+      ///////////////////////////////////////////////////////
+      // Registers controlled by the READ fsm
+      ///////////////////////////////////////////////////////
+
+      sc_signal<int>         r_read_fsm;        // FSM state 
+      sc_signal<size_t>      r_read_copy;       // Srcid of the first copy
+      sc_signal<bool>        r_read_copy_inst;  // Type of the first copy
+      sc_signal<tag_t>       r_read_tag;	    // cache line tag (in directory)
+      sc_signal<bool>        r_read_is_cnt;	    // is_cnt bit (in directory)
+      sc_signal<bool>        r_read_lock;	    // lock bit (in directory)
+      sc_signal<bool>        r_read_dirty;	    // dirty bit (in directory)
+      sc_signal<bool>        r_read_inst;       // it is an instruction line
+      sc_signal<size_t>      r_read_count;      // number of copies
+      sc_signal<size_t>      r_read_ptr;        // pointer to the heap
+      sc_signal<data_t>     *r_read_data;       // data (one cache line)
+      sc_signal<size_t>      r_read_way;        // associative way (in cache)
+      sc_signal<size_t>      r_read_trt_index;  // Transaction Table index
+      sc_signal<size_t>      r_read_next_ptr;   // Next entry to point to
+      sc_signal<bool>        r_read_last_free;  // Last free entry
+
+      // Buffer between READ fsm and IXR_CMD fsm (ask a missing cache line to XRAM)   
+      sc_signal<bool>        r_read_to_ixr_cmd_req;     // valid request
+      sc_signal<addr_t>      r_read_to_ixr_cmd_nline;   // cache line index
+      sc_signal<size_t>      r_read_to_ixr_cmd_trdid;   // index in Transaction Table
+
+      // Buffer between READ fsm and TGT_RSP fsm (send a hit read response to L1 cache)
+      sc_signal<bool>	   r_read_to_tgt_rsp_req;       // valid request
+      sc_signal<size_t>	   r_read_to_tgt_rsp_srcid;	    // Transaction srcid
+      sc_signal<size_t>	   r_read_to_tgt_rsp_trdid;	    // Transaction trdid
+      sc_signal<size_t>	   r_read_to_tgt_rsp_pktid;	    // Transaction pktid
+      sc_signal<data_t>   *r_read_to_tgt_rsp_data;	    // data (one cache line)
+      sc_signal<size_t>    r_read_to_tgt_rsp_word;      // first word of the response
+      sc_signal<size_t>    r_read_to_tgt_rsp_length;    // length of the response
+
+      ///////////////////////////////////////////////////////////////
+      // Registers controlled by the WRITE fsm
+      ///////////////////////////////////////////////////////////////
+
+      sc_signal<int>       r_write_fsm;             // FSM state
+      sc_signal<addr_t>	   r_write_address;         // first word address
+      sc_signal<size_t>    r_write_word_index;      // first word index in line
+      sc_signal<size_t>    r_write_word_count;      // number of words in line
+      sc_signal<size_t>    r_write_srcid;           // transaction srcid
+      sc_signal<size_t>    r_write_trdid;           // transaction trdid
+      sc_signal<size_t>    r_write_pktid;           // transaction pktid
+      sc_signal<data_t>	  *r_write_data;            // data (one cache line)	
+      sc_signal<be_t>     *r_write_be;              // one byte enable per word
+      sc_signal<bool>      r_write_byte;            // is it a byte write
+      sc_signal<bool>      r_write_is_cnt;          // is_cnt bit (in directory)
+      sc_signal<bool>      r_write_lock;            // lock bit (in directory)
+      sc_signal<bool>      r_write_inst;            // instruction bit
+      sc_signal<tag_t>     r_write_tag;             // cache line tag (in directory)
+      sc_signal<size_t>    r_write_copy;            // first owner of the line
+      sc_signal<bool>      r_write_copy_inst;       // is this owner a ICache ?
+      sc_signal<size_t>	   r_write_count;           // number of copies
+      sc_signal<size_t>    r_write_ptr;             // pointer to the heap
+      sc_signal<size_t>    r_write_next_ptr;        // next pointer to the heap
+      sc_signal<bool>      r_write_to_dec;          // need to decrement update counter
+      sc_signal<size_t>	   r_write_way;		        // way of the line
+      sc_signal<size_t>    r_write_trt_index;	    // index in Transaction Table
+      sc_signal<size_t>    r_write_upt_index;	    // index in Update Table
+
+      // Buffer between WRITE fsm and TGT_RSP fsm (acknowledge a write command from L1)
+      sc_signal<bool>      r_write_to_tgt_rsp_req;		// valid request
+      sc_signal<size_t>    r_write_to_tgt_rsp_srcid;    // transaction srcid
+      sc_signal<size_t>    r_write_to_tgt_rsp_trdid;	// transaction trdid
+      sc_signal<size_t>    r_write_to_tgt_rsp_pktid;	// transaction pktid
+
+      // Buffer between WRITE fsm and IXR_CMD fsm (ask a missing cache line to XRAM) 
+      sc_signal<bool>	   r_write_to_ixr_cmd_req;      // valid request
+      sc_signal<bool>	   r_write_to_ixr_cmd_write;    // write request
+      sc_signal<addr_t>    r_write_to_ixr_cmd_nline; 	// cache line index
+      sc_signal<data_t>	  *r_write_to_ixr_cmd_data;	    // cache line data
+      sc_signal<size_t>    r_write_to_ixr_cmd_trdid;	// index in Transaction Table
+
+      // Buffer between WRITE fsm and INIT_CMD fsm (Update/Invalidate L1 caches)
+      sc_signal<bool>	   r_write_to_init_cmd_multi_req;   // valid multicast request
+      sc_signal<bool>	   r_write_to_init_cmd_brdcast_req; // valid brdcast request
+      sc_signal<addr_t>	   r_write_to_init_cmd_nline;	    // cache line index
+      sc_signal<size_t>	   r_write_to_init_cmd_trdid;	    // index in Update Table
+      sc_signal<data_t>   *r_write_to_init_cmd_data;	    // data (one cache line)
+      sc_signal<bool>     *r_write_to_init_cmd_we;	        // word enable
+      sc_signal<size_t>	   r_write_to_init_cmd_count;	    // number of words in line
+      sc_signal<size_t>	   r_write_to_init_cmd_index;	    // index of first word in line
+      GenericFifo<bool>    m_write_to_init_cmd_inst_fifo;   // fifo for the L1 type
+      GenericFifo<size_t>  m_write_to_init_cmd_srcid_fifo;  // fifo for srcids
+
+      // Buffer between WRITE fsm and INIT_RSP fsm (Decrement UPT entry)
+      sc_signal<bool>      r_write_to_init_rsp_req;         // valid request
+      sc_signal<size_t>    r_write_to_init_rsp_upt_index;   // index in update table
+
+      /////////////////////////////////////////////////////////
+      // Registers controlled by INIT_RSP fsm
+      //////////////////////////////////////////////////////////
+
+      sc_signal<int> 	   r_init_rsp_fsm;        // FSM state
+      sc_signal<size_t>	   r_init_rsp_upt_index;  // index in the Update Table
+      sc_signal<size_t>	   r_init_rsp_srcid;	  // pending write srcid      
+      sc_signal<size_t>	   r_init_rsp_trdid;	  // pending write trdid      
+      sc_signal<size_t>	   r_init_rsp_pktid;	  // pending write pktid      
+      sc_signal<addr_t>	   r_init_rsp_nline;	  // pending write nline      
+
+      // Buffer between INIT_RSP fsm and TGT_RSP fsm (complete write/update transaction)
+      sc_signal<bool>	     r_init_rsp_to_tgt_rsp_req;   	// valid request
+      sc_signal<size_t>	   r_init_rsp_to_tgt_rsp_srcid;		// Transaction srcid
+      sc_signal<size_t>	   r_init_rsp_to_tgt_rsp_trdid;		// Transaction trdid
+      sc_signal<size_t>	   r_init_rsp_to_tgt_rsp_pktid;		// Transaction pktid
+
+      ///////////////////////////////////////////////////////
+      // Registers controlled by CLEANUP fsm
+      ///////////////////////////////////////////////////////
+
+      sc_signal<int> 	     r_cleanup_fsm;         // FSM state
+      sc_signal<size_t>      r_cleanup_srcid;       // transaction srcid
+      sc_signal<size_t>      r_cleanup_trdid;       // transaction trdid
+      sc_signal<size_t>      r_cleanup_pktid;       // transaction pktid
+      sc_signal<addr_t>      r_cleanup_nline;       // cache line index
+
+      sc_signal<copy_t>      r_cleanup_copy;        // first copy
+      sc_signal<size_t>      r_cleanup_copy_inst;   // type of the first copy
+      sc_signal<copy_t>      r_cleanup_count;       // number of copies 
+      sc_signal<size_t>      r_cleanup_ptr;         // pointer to the heap
+      sc_signal<size_t>      r_cleanup_prev_ptr;    // previous pointer to the heap
+      sc_signal<size_t>      r_cleanup_prev_srcid;  // srcid of previous heap entry
+      sc_signal<bool>        r_cleanup_prev_inst;   // inst bit of previous heap entry
+      sc_signal<size_t>      r_cleanup_next_ptr;    // next pointer to the heap
+      sc_signal<tag_t>       r_cleanup_tag;	        // cache line tag (in directory)
+      sc_signal<bool>        r_cleanup_is_cnt;      // inst bit (in directory)
+      sc_signal<bool>        r_cleanup_lock;	    // lock bit (in directory)
+      sc_signal<bool>        r_cleanup_inst;	    // inst bit (in directory)
+      sc_signal<bool>        r_cleanup_dirty;	    // dirty bit (in directory)
+      sc_signal<size_t>      r_cleanup_way;	        // associative way (in cache)
+
+      sc_signal<size_t>      r_cleanup_write_srcid; // srcid of write response
+      sc_signal<size_t>      r_cleanup_write_trdid; // trdid of write rsp
+      sc_signal<size_t>      r_cleanup_write_pktid; // pktid of write rsp
+      sc_signal<bool>        r_cleanup_need_rsp;    // needs a write rsp
+
+      sc_signal<size_t>      r_cleanup_index;	    // index of the INVAL line (in the UPT)
+
+      // Buffer between CLEANUP fsm and TGT_RSP fsm (acknowledge a write command from L1)
+      sc_signal<bool>      r_cleanup_to_tgt_rsp_req;    // valid request
+      sc_signal<size_t>    r_cleanup_to_tgt_rsp_srcid;  // transaction srcid
+      sc_signal<size_t>    r_cleanup_to_tgt_rsp_trdid;	// transaction trdid
+      sc_signal<size_t>    r_cleanup_to_tgt_rsp_pktid;	// transaction pktid
+
+      ///////////////////////////////////////////////////////
+      // Registers controlled by LLSC fsm
+      ///////////////////////////////////////////////////////
+
+      sc_signal<int>       r_llsc_fsm;          // FSM state
+      sc_signal<data_t>	   r_llsc_data;		    // read data word
+      sc_signal<copy_t>    r_llsc_copy; 	    // Srcid of the first copy
+      sc_signal<bool>      r_llsc_copy_inst;	// Type of the first copy
+      sc_signal<size_t>    r_llsc_count;	    // number of copies
+      sc_signal<size_t>    r_llsc_ptr;  	    // pointer to the heap
+      sc_signal<size_t>    r_llsc_next_ptr;  	// next pointer to the heap
+      sc_signal<bool>      r_llsc_is_cnt;	    // is_cnt bit (in directory)
+      sc_signal<bool>      r_llsc_dirty;	    // dirty bit (in directory)
+      sc_signal<bool>      r_llsc_inst;         // inst bit
+      sc_signal<size_t>    r_llsc_way;		    // way in directory
+      sc_signal<size_t>    r_llsc_set;		    // set in directory
+      sc_signal<data_t>    r_llsc_tag;		    // cache line tag (in directory)
+      sc_signal<size_t>    r_llsc_trt_index;    // Transaction Table index
+      sc_signal<size_t>    r_llsc_upt_index;    // Update Table index
+
+      // Buffer between LLSC fsm and INIT_CMD fsm (XRAM read)	
+      sc_signal<bool>	   r_llsc_to_ixr_cmd_req;   // valid request
+      sc_signal<addr_t>	   r_llsc_to_ixr_cmd_nline; // cache line index
+      sc_signal<size_t>	   r_llsc_to_ixr_cmd_trdid; // index in Transaction Table
+      sc_signal<bool>	   r_llsc_to_ixr_cmd_write; // write request
+      sc_signal<data_t>	  *r_llsc_to_ixr_cmd_data;  // cache line data
+
+
+      // Buffer between LLSC fsm and TGT_RSP fsm
+      sc_signal<bool>	   r_llsc_to_tgt_rsp_req;   // valid request
+      sc_signal<data_t>    r_llsc_to_tgt_rsp_data;  // read data word
+      sc_signal<size_t>	   r_llsc_to_tgt_rsp_srcid; // Transaction srcid
+      sc_signal<size_t>	   r_llsc_to_tgt_rsp_trdid; // Transaction trdid
+      sc_signal<size_t>	   r_llsc_to_tgt_rsp_pktid; // Transaction pktid
+
+      // Buffer between LLSC fsm and INIT_CMD fsm (Update/Invalidate L1 caches)
+      sc_signal<bool>	   r_llsc_to_init_cmd_multi_req;    // valid request
+      sc_signal<bool>	   r_llsc_to_init_cmd_brdcast_req;  // brdcast request
+      sc_signal<addr_t>	   r_llsc_to_init_cmd_nline;	    // cache line index
+      sc_signal<size_t>	   r_llsc_to_init_cmd_trdid;	    // index in Update Table
+      sc_signal<data_t>    r_llsc_to_init_cmd_wdata;        // data (one word)
+      sc_signal<size_t>	   r_llsc_to_init_cmd_index;	    // index of the word in line
+      GenericFifo<bool>    m_llsc_to_init_cmd_inst_fifo;    // fifo for the L1 type
+      GenericFifo<size_t>  m_llsc_to_init_cmd_srcid_fifo;   // fifo for srcids
+
+      // Buffer between LLSC fsm and INIT_RSP fsm (Decrement UPT entry)
+      sc_signal<bool>      r_llsc_to_init_rsp_req;          // valid request
+      sc_signal<size_t>    r_llsc_to_init_rsp_upt_index;    // index in update table
+
+      ////////////////////////////////////////////////////
+      // Registers controlled by the IXR_RSP fsm
+      ////////////////////////////////////////////////////
+
+      sc_signal<int> 	   r_ixr_rsp_fsm;       // FSM state
+      sc_signal<size_t>	   r_ixr_rsp_trt_index;	// TRT entry index
+      sc_signal<size_t>    r_ixr_rsp_cpt;	    // word counter
+
+      // Buffer between IXR_RSP fsm and XRAM_RSP fsm  (response from the XRAM)
+      sc_signal<bool>	  *r_ixr_rsp_to_xram_rsp_rok;	// A xram response is ready
+
+      ////////////////////////////////////////////////////
+      // Registers controlled by the XRAM_RSP fsm
+      ////////////////////////////////////////////////////
+
+      sc_signal<int> 	   r_xram_rsp_fsm;		        // FSM state
+      sc_signal<size_t>	   r_xram_rsp_trt_index;	    // TRT entry index
+      TransactionTabEntry  r_xram_rsp_trt_buf;		    // TRT entry local buffer
+      sc_signal<bool>	   r_xram_rsp_victim_inval;	    // victim line invalidate 
+      sc_signal<bool>	   r_xram_rsp_victim_is_cnt;    // victim line inst bit
+      sc_signal<bool>	   r_xram_rsp_victim_dirty;	    // victim line dirty bit
+      sc_signal<size_t>    r_xram_rsp_victim_way;	    // victim line way
+      sc_signal<size_t>    r_xram_rsp_victim_set;	    // victim line set
+      sc_signal<addr_t>    r_xram_rsp_victim_nline;     // victim line index
+      sc_signal<copy_t>    r_xram_rsp_victim_copy;  	// victim line first copy
+      sc_signal<bool>      r_xram_rsp_victim_copy_inst;	// victim line type of first copy
+      sc_signal<size_t>    r_xram_rsp_victim_count;	    // victim line number of copies
+      sc_signal<size_t>    r_xram_rsp_victim_ptr;       // victim line pointer to the heap
+      sc_signal<data_t>	  *r_xram_rsp_victim_data;	    // victim line data
+      sc_signal<size_t>	   r_xram_rsp_upt_index;	    // UPT entry index
+      sc_signal<size_t>    r_xram_rsp_next_ptr;         // Next pointer to the heap
+
+      // Buffer between XRAM_RSP fsm and TGT_RSP fsm  (response to L1 cache)
+      sc_signal<bool>	   r_xram_rsp_to_tgt_rsp_req;	// Valid request
+      sc_signal<size_t>    r_xram_rsp_to_tgt_rsp_srcid;	// Transaction srcid
+      sc_signal<size_t>    r_xram_rsp_to_tgt_rsp_trdid;	// Transaction trdid
+      sc_signal<size_t>    r_xram_rsp_to_tgt_rsp_pktid;	// Transaction pktid
+      sc_signal<data_t>   *r_xram_rsp_to_tgt_rsp_data;	// data (one cache line)
+      sc_signal<size_t>    r_xram_rsp_to_tgt_rsp_word;  // first word index
+      sc_signal<size_t>    r_xram_rsp_to_tgt_rsp_length;// length of the response
+
+      // Buffer between XRAM_RSP fsm and INIT_CMD fsm (Inval L1 Caches) 
+      sc_signal<bool>	    r_xram_rsp_to_init_cmd_multi_req;       // Valid request
+      sc_signal<bool>       r_xram_rsp_to_init_cmd_brdcast_req;     // Broadcast request
+      sc_signal<addr_t>     r_xram_rsp_to_init_cmd_nline;           // cache line index;
+      sc_signal<size_t>	    r_xram_rsp_to_init_cmd_trdid;           // index of UPT entry
+      GenericFifo<bool>     m_xram_rsp_to_init_cmd_inst_fifo;       // fifo for the L1 type
+      GenericFifo<size_t>   m_xram_rsp_to_init_cmd_srcid_fifo;      // fifo for srcids
+
+      // Buffer between XRAM_RSP fsm and IXR_CMD fsm (XRAM write)
+      sc_signal<bool>	   r_xram_rsp_to_ixr_cmd_req;	// Valid request
+      sc_signal<addr_t>	   r_xram_rsp_to_ixr_cmd_nline;	// cache line index
+      sc_signal<data_t>	  *r_xram_rsp_to_ixr_cmd_data;	// cache line data
+      sc_signal<size_t>	   r_xram_rsp_to_ixr_cmd_trdid;	// index in transaction table
+
+      ////////////////////////////////////////////////////
+      // Registers controlled by the IXR_CMD fsm
+      ////////////////////////////////////////////////////
+
+      sc_signal<int> 	   r_ixr_cmd_fsm;
+      sc_signal<size_t>	   r_ixr_cmd_cpt;
+
+      ////////////////////////////////////////////////////
+      // Registers controlled by TGT_RSP fsm
+      ////////////////////////////////////////////////////
+
+      sc_signal<int> 	   r_tgt_rsp_fsm;
+      sc_signal<size_t>    r_tgt_rsp_cpt;
+
+      ////////////////////////////////////////////////////
+      // Registers controlled by INIT_CMD fsm
+      ////////////////////////////////////////////////////
+
+      sc_signal<int> 	  r_init_cmd_fsm;
+      sc_signal<size_t>   r_init_cmd_cpt;
+      sc_signal<bool>     r_init_cmd_inst;
+
+      ////////////////////////////////////////////////////
+      // Registers controlled by ALLOC_DIR fsm
+      ////////////////////////////////////////////////////
+
+      sc_signal<int> 		r_alloc_dir_fsm;
+
+      ////////////////////////////////////////////////////
+      // Registers controlled by ALLOC_TRT fsm
+      ////////////////////////////////////////////////////
+
+      sc_signal<int> 		r_alloc_trt_fsm;
+
+      ////////////////////////////////////////////////////
+      // Registers controlled by ALLOC_UPT fsm
+      ////////////////////////////////////////////////////
+
+      sc_signal<int> 		r_alloc_upt_fsm;
+
+      ////////////////////////////////////////////////////
+      // Registers controlled by ALLOC_HEAP fsm
+      ////////////////////////////////////////////////////
+
+      sc_signal<int> 		r_alloc_heap_fsm;
+
+    }; // end class VciMemCacheV3
+
+}}
+
+#endif
+
+// Local Variables:
+// tab-width: 4
+// c-basic-offset: 4
+// c-file-offsets:((innamespace . 0)(inline-open . 0))
+// indent-tabs-mode: nil
+// End:
+
+// vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4
+
Index: branches/v4/platforms/almos-tsarv3-platforms/common/vci_mem_cache_v3/caba/source/include/xram_transaction_v3.h
===================================================================
--- branches/v4/platforms/almos-tsarv3-platforms/common/vci_mem_cache_v3/caba/source/include/xram_transaction_v3.h	(revision 371)
+++ branches/v4/platforms/almos-tsarv3-platforms/common/vci_mem_cache_v3/caba/source/include/xram_transaction_v3.h	(revision 371)
@@ -0,0 +1,412 @@
+#ifndef XRAM_TRANSACTION_V3_H_
+#define XRAM_TRANSACTION_V3_H_
+ 
+#include <inttypes.h>
+#include <systemc>
+#include <cassert>
+#include <fstream>
+#include <iostream>
+#include "arithmetics.h"
+
+#define DEBUG_XRAM_TRANSACTION 0
+
+////////////////////////////////////////////////////////////////////////
+//                  A transaction tab entry         
+////////////////////////////////////////////////////////////////////////
+
+class TransactionTabEntry {
+  typedef uint32_t size_t;
+  typedef uint32_t data_t;
+  typedef sc_dt::sc_uint<40> addr_t;
+  typedef uint32_t be_t;
+
+ public:
+  bool 		      valid;     	    // entry valid 
+  bool 		      xram_read; 	    // read request to XRAM
+  addr_t   	      nline;    	    // index (zy) of the requested line
+  size_t 	      srcid;     	    // processor requesting the transaction
+  size_t 	      trdid;     	    // processor requesting the transaction
+  size_t 	      pktid;     	    // processor requesting the transaction
+  bool 		      proc_read;	    // read request from processor
+  size_t 		  read_length;      // length of the read (for the response)
+  size_t 	      word_index;    	// index of the first read word (for the response)
+  std::vector<data_t> wdata;        // write buffer (one cache line)
+  std::vector<be_t>   wdata_be;    	// be for each data in the write buffer
+  /////////////////////////////////////////////////////////////////////
+  // The init() function initializes the entry 
+  /////////////////////////////////////////////////////////////////////
+  void init()
+  {
+    valid		= false;
+  }
+
+  /////////////////////////////////////////////////////////////////////
+  // The alloc() function initializes the vectors of an entry
+  // Its arguments are :
+  // - n_words : number of words per line in the cache
+  /////////////////////////////////////////////////////////////////////
+  void alloc(size_t n_words)
+  {
+    wdata_be.reserve( (int)n_words );
+    wdata.reserve( (int)n_words );
+    for(size_t i=0; i<n_words; i++){
+      wdata_be.push_back(false);
+      wdata.push_back(0);
+    }
+  }
+
+  ////////////////////////////////////////////////////////////////////
+  // The copy() function copies an existing entry
+  // Its arguments are :
+  // - source : the transaction tab entry to copy
+  ////////////////////////////////////////////////////////////////////
+  void copy(const TransactionTabEntry &source)
+  {
+    valid	    = source.valid;
+    xram_read 	= source.xram_read;
+    nline	    = source.nline;
+    srcid	    = source.srcid;
+    trdid	    = source.trdid;
+    pktid	    = source.pktid;
+    proc_read 	= source.proc_read;
+    read_length = source.read_length;
+    word_index	= source.word_index;
+    wdata_be.assign(source.wdata_be.begin(),source.wdata_be.end());
+    wdata.assign(source.wdata.begin(),source.wdata.end());	
+  }
+
+  ////////////////////////////////////////////////////////////////////
+  // The print() function prints the entry 
+  ////////////////////////////////////////////////////////////////////
+  void print(std::ostream &m_log){
+    m_log << "valid       = " << valid        << std::endl;
+    m_log << "xram_read   = " << xram_read    << std::endl;
+    m_log << "nline       = " << std::hex << nline << std::endl;
+    m_log << "srcid       = " << srcid        << std::endl;
+    m_log << "trdid       = " << trdid        << std::endl;
+    m_log << "pktid       = " << pktid        << std::endl;
+    m_log << "proc_read   = " << proc_read    << std::endl;
+    m_log << "read_length = " << read_length  << std::endl;
+    m_log << "word_index  = " << word_index   << std::endl; 
+    for(size_t i=0; i<wdata_be.size() ; i++){
+      m_log << "wdata_be [" << i <<"] = " << wdata_be[i] << std::endl;
+    }
+    for(size_t i=0; i<wdata.size() ; i++){
+      m_log << "wdata [" << i <<"] = " << wdata[i] << std::endl;
+    }
+    m_log << std::endl;
+  }
+
+  /////////////////////////////////////////////////////////////////////
+  // 		Constructors
+  /////////////////////////////////////////////////////////////////////
+
+  TransactionTabEntry()
+    {
+      wdata_be.clear();
+      wdata.clear();
+      valid=false;
+    }
+
+  TransactionTabEntry(const TransactionTabEntry &source){
+    valid	    = source.valid;
+    xram_read	= source.xram_read;
+    nline	    = source.nline;
+    srcid	    = source.srcid;
+    trdid	    = source.trdid;
+    pktid	    = source.pktid;
+    proc_read	= source.proc_read;
+    read_length = source.read_length;
+    word_index	= source.word_index;
+    wdata_be.assign(source.wdata_be.begin(),source.wdata_be.end());
+    wdata.assign(source.wdata.begin(),source.wdata.end());
+  }
+
+}; // end class TransactionTabEntry
+
+////////////////////////////////////////////////////////////////////////
+//                  The transaction tab                              
+////////////////////////////////////////////////////////////////////////
+class TransactionTab{
+  typedef uint32_t size_t;
+  typedef uint32_t data_t;
+  typedef sc_dt::sc_uint<40> addr_t;
+  typedef uint32_t be_t;
+
+ private:
+  size_t size_tab;                // The size of the tab
+
+  data_t be_to_mask(be_t be)
+  {
+    data_t ret = 0;
+    if ( be&0x1 ) {
+      ret = ret | 0x000000FF;
+    }
+    if ( be&0x2 ) {
+      ret = ret | 0x0000FF00;
+    }
+    if ( be&0x4 ) {
+      ret = ret | 0x00FF0000;
+    }
+    if ( be&0x8 ) {
+      ret = ret | 0xFF000000;
+    }
+    return ret;
+  }
+
+ public:
+  TransactionTabEntry *tab;       // The transaction tab
+
+  ////////////////////////////////////////////////////////////////////
+  //		Constructors
+  ////////////////////////////////////////////////////////////////////
+  TransactionTab()
+    {
+      size_tab=0;
+      tab=NULL;
+    }
+
+  TransactionTab(size_t n_entries, size_t n_words)
+    {
+      size_tab = n_entries;
+      tab = new TransactionTabEntry[size_tab];
+      for ( size_t i=0; i<size_tab; i++) {
+          tab[i].alloc(n_words);
+      }
+    }
+
+  ~TransactionTab()
+    {
+      delete [] tab;
+    }
+
+  /////////////////////////////////////////////////////////////////////
+  // The size() function returns the size of the tab
+  /////////////////////////////////////////////////////////////////////
+  size_t size()
+  {
+    return size_tab;
+  }
+
+  /////////////////////////////////////////////////////////////////////
+  // The init() function initializes the transaction tab entries
+  /////////////////////////////////////////////////////////////////////
+  void init()
+  {
+    for ( size_t i=0; i<size_tab; i++) {
+      tab[i].init();
+    }
+  }
+
+  /////////////////////////////////////////////////////////////////////
+  // The print() function prints a transaction tab entry
+  // Arguments :
+  // - index : the index of the entry to print
+  /////////////////////////////////////////////////////////////////////
+  void print(const size_t index, std::ostream &output)
+  {
+    assert( (index < size_tab) 
+	    && "Invalid Transaction Tab Entry");
+    tab[index].print(output);
+    return;
+  }
+
+  /////////////////////////////////////////////////////////////////////
+  // The read() function returns a transaction tab entry.
+  // Arguments :
+  // - index : the index of the entry to read
+  /////////////////////////////////////////////////////////////////////
+  TransactionTabEntry read(const size_t index)
+  {
+    assert( (index < size_tab) 
+	    && "Invalid Transaction Tab Entry");
+    return tab[index];
+  }
+
+  /////////////////////////////////////////////////////////////////////
+  // The full() function returns the state of the transaction tab
+  // Arguments :
+  // - index : (return argument) the index of an empty entry 
+  // The function returns true if the transaction tab is full
+  /////////////////////////////////////////////////////////////////////
+  bool full(size_t &index)
+  {
+    for(size_t i=0; i<size_tab; i++){
+      if(!tab[i].valid){
+	    index=i;
+	    return false;	
+      }
+    }
+    return true;
+  }
+
+  /////////////////////////////////////////////////////////////////////
+  // The hit_read() function checks if an XRAM read transaction exists 
+  // for a given cache line.
+  // Arguments :
+  // - index : (return argument) the index of the hit entry, if there is 
+  // - nline : the index (zy) of the requested line
+  // The function returns true if a read request has already been sent
+  //////////////////////////////////////////////////////////////////////
+  bool hit_read(const addr_t nline,size_t &index)
+  {
+    for(size_t i=0; i<size_tab; i++){
+      if((tab[i].valid && (nline==tab[i].nline)) && (tab[i].xram_read)) {
+	    index=i;
+	    return true;	
+      }
+    }
+    return false;
+  }
+
+  ///////////////////////////////////////////////////////////////////////
+  // The hit_write() function looks if an XRAM write transaction exists 
+  // for a given line.
+  // Arguments :
+  // - nline : the index (zy) of the requested line
+  // The function returns true if a write request has already been sent
+  ///////////////////////////////////////////////////////////////////////
+  bool hit_write(const addr_t nline)
+  {
+    for(size_t i=0; i<size_tab; i++){
+      if(tab[i].valid && (nline==tab[i].nline) && !(tab[i].xram_read)) {
+	    return true;	
+      }
+    }
+    return false;
+  }
+
+  /////////////////////////////////////////////////////////////////////
+  // The write_data_mask() function writes a vector of data (a line).
+  // The data is written only if the corresponding bits are set
+  // in the be vector. 
+  // Arguments :
+  // - index : the index of the request in the transaction tab
+  // - be   : vector of be 
+  // - data : vector of data
+  /////////////////////////////////////////////////////////////////////
+  void write_data_mask(const size_t index, 
+		       const std::vector<be_t> &be, 
+		       const std::vector<data_t> &data) 
+  {
+    assert( (index < size_tab) 
+	    && "Invalid Transaction Tab Entry");
+    assert(be.size()==tab[index].wdata_be.size() 
+	   && "Bad data mask in write_data_mask in TransactionTab");
+    assert(data.size()==tab[index].wdata.size() 
+	   && "Bad data in write_data_mask in TransactionTab");
+
+    for(size_t i=0; i<tab[index].wdata_be.size() ; i++) {
+      tab[index].wdata_be[i] = tab[index].wdata_be[i] | be[i];
+      data_t mask = be_to_mask(be[i]);
+      tab[index].wdata[i] = (tab[index].wdata[i] & ~mask) | (data[i] & mask);
+    }
+  }
+
+  /////////////////////////////////////////////////////////////////////
+  // The set() function registers a transaction (read or write)
+  // to the XRAM in the transaction tab.
+  // Arguments :
+  // - index : index in the transaction tab
+  // - xram_read : transaction type (read or write a cache line)
+  // - nline : the index (zy) of the cache line
+  // - srcid : srcid of the initiator that caused the transaction
+  // - trdid : trdid of the initiator that caused the transaction
+  // - pktid : pktid of the initiator that caused the transaction
+  // - proc_read : does the initiator want a copy
+  // - read_length : length of read (in case of processor read)
+  // - word_index : index in the line (in case of single word read)
+  // - data : the data to write (in case of write)
+  // - data_be : the mask of the data to write (in case of write)
+  /////////////////////////////////////////////////////////////////////
+  void set(const size_t index,
+	   const bool xram_read,
+	   const addr_t nline,
+	   const size_t srcid,
+	   const size_t trdid,
+	   const size_t pktid,
+	   const bool proc_read,
+	   const size_t read_length,
+	   const size_t word_index,
+	   const std::vector<be_t> &data_be,
+	   const std::vector<data_t> &data) 
+  {
+    assert( (index < size_tab) 
+	    && "The selected entry is out of range in set() Transaction Tab");
+    assert(data_be.size()==tab[index].wdata_be.size() 
+	   && "Bad data_be argument in set() TransactionTab");
+    assert(data.size()==tab[index].wdata.size() 
+	   && "Bad data argument in set() TransactionTab");
+
+    tab[index].valid	        = true;
+    tab[index].xram_read        = xram_read;
+    tab[index].nline	        = nline;
+    tab[index].srcid	        = srcid;
+    tab[index].trdid	        = trdid;
+    tab[index].pktid	        = pktid;
+    tab[index].proc_read	    = proc_read;
+    tab[index].read_length	    = read_length;
+    tab[index].word_index	    = word_index;
+    for(size_t i=0; i<tab[index].wdata.size(); i++) {
+      tab[index].wdata_be[i]    = data_be[i];
+      tab[index].wdata[i]       = data[i];
+    }
+  }
+
+  /////////////////////////////////////////////////////////////////////
+  // The write_rsp() function writes a word of the response to an 
+  // XRAM read transaction.
+  // The data is only written when the corresponding BE field is Ox0.
+  // Arguments :
+  // - index : the index of the transaction in the transaction tab
+  // - word_index : the index of the data in the line
+  // - data : the data to write
+  /////////////////////////////////////////////////////////////////////
+  void write_rsp(const size_t index,
+		 const size_t word,
+		 const data_t data)
+  {
+    assert( (index < size_tab) 
+	    && "Selected entry  out of range in write_rsp() Transaction Tab");
+    assert( (word <= tab[index].wdata_be.size()) 
+	    && "Bad word_index in write_rsp() in TransactionTab");
+  
+    if(!(tab[index].valid))
+    {        
+        print(index, std::cout);
+    }
+
+    assert( tab[index].valid 
+	    && "Transaction Tab Entry invalid in write_rsp()");
+  
+    assert( tab[index].xram_read 
+                && "Selected entry is not an XRAM read transaction in write_rsp()");
+
+    data_t mask = be_to_mask(tab[index].wdata_be[word]);
+    tab[index].wdata[word] = (tab[index].wdata[word] & mask) | (data & ~mask);
+  }
+
+  /////////////////////////////////////////////////////////////////////
+  // The erase() function erases an entry in the transaction tab.
+  // Arguments :
+  // - index : the index of the request in the transaction tab
+  /////////////////////////////////////////////////////////////////////
+  void erase(const size_t index)
+  {
+    assert( (index < size_tab) 
+	    && "The selected entry is out of range in erase() Transaction Tab");
+    tab[index].valid	= false;
+  }
+}; // end class TransactionTab
+
+#endif
+
+// Local Variables:
+// tab-width: 4
+// c-basic-offset: 4
+// c-file-offsets:((innamespace . 0)(inline-open . 0))
+// indent-tabs-mode: nil
+// End:
+
+// vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4
+
Index: branches/v4/platforms/almos-tsarv3-platforms/common/vci_mem_cache_v3/caba/source/src/TAGS
===================================================================
--- branches/v4/platforms/almos-tsarv3-platforms/common/vci_mem_cache_v3/caba/source/src/TAGS	(revision 371)
+++ branches/v4/platforms/almos-tsarv3-platforms/common/vci_mem_cache_v3/caba/source/src/TAGS	(revision 371)
@@ -0,0 +1,654 @@
+
+
+vci_mem_cache_v3.cpp,678
+#define MEMC_INI_ID 36,1183
+#define TRACE_MSG(38,1211
+namespace soclib 44,1522
+namespace soclib { namespace caba soclib::caba44,1522
+#define tmpl(224,5523
+  using soclib::common::uint32_log2;soclib::caba::soclib::common::uint32_log2226,5596
+  tmpl(soclib::caba::tmpl232,5724
+#define L2 271,7054
+#undef L2276,7306
+  tmpl(soclib::caba::tmpl456,13347
+  tmpl(soclib::caba::tmpl477,13900
+  tmpl(soclib::caba::tmpl500,15551
+  tmpl(soclib::caba::tmpl521,17270
+  tmpl(soclib::caba::tmpl543,18820
+  tmpl(soclib::caba::tmpl572,19526
+#define L2 2586,103429
+#undef L22588,103559
+#define L2 2638,105577
+#undef L22640,105709
+  tmpl(soclib::caba::tmpl4370,180469
+
+
+../include/atomic_tab_v3.h,652
+#define ATOMIC_TAB_V3_H_2,25
+class AtomicTab{AtomicTab17,505
+    typedef uint32_t size_t;AtomicTab::size_t18,522
+    typedef sc_dt::sc_uint<40> addr_t;AtomicTab::addr_t19,551
+    size_t size_tab;AtomicTab::size_tab22,600
+    std::vector<addr_t> addr_tab;AtomicTab::addr_tab23,671
+    std::vector<bool>   valid_tab;AtomicTab::valid_tab24,738
+    AtomicTab(AtomicTab::AtomicTab28,813
+    AtomicTab(AtomicTab::AtomicTab35,888
+    const size_t size(AtomicTab::size46,1214
+    void init(AtomicTab::init54,1487
+    void set(AtomicTab::set69,1923
+    bool isatomic(AtomicTab::isatomic86,2520
+    void reset(AtomicTab::reset100,3016
+
+
+../include/mem_cache_directory_v3.h,3393
+#define SOCLIB_CABA_MEM_CACHE_DIRECTORY_V3_H 2,45
+  class LruEntry 16,430
+      bool recent;20,463
+      void init(22,495
+  class Owner{Owner32,763
+    typedef uint32_t size_t;33,778
+      bool      inst;37,838
+      size_t    srcid;38,894
+      Owner(43,1027
+      Owner(48,1130
+      Owner(53,1221
+  class DirectoryEntry 65,1566
+    typedef uint32_t tag_t;67,1592
+    typedef uint32_t size_t;68,1620
+    bool    valid;72,1663
+    bool    is_cnt;73,1714
+    bool    dirty;74,1788
+    bool    lock;75,1839
+    bool    inst;76,1891
+    tag_t   tag;77,1956
+    size_t  count;78,2012
+    Owner   owner;79,2068
+    size_t  ptr;80,2129
+    DirectoryEntry(82,2195
+    DirectoryEntry(96,2499
+    void init(112,3088
+    void copy(125,3483
+    void print(141,4012
+  class CacheDirectory 159,4749
+    typedef sc_dt::sc_uint<40> addr_t;CacheDirectory::addr_t161,4775
+    typedef uint32_t data_t;CacheDirectory::data_t162,4814
+    typedef uint32_t tag_t;CacheDirectory::tag_t163,4843
+    typedef uint32_t size_t;CacheDirectory::size_t164,4871
+    size_t					m_ways;CacheDirectory::m_ways169,4942
+    size_t					m_sets;CacheDirectory::m_sets170,4965
+    size_t					m_words;CacheDirectory::m_words171,4988
+    size_t					m_width;CacheDirectory::m_width172,5012
+    DirectoryEntry 				**m_dir_tab;CacheDirectory::m_dir_tab175,5071
+    LruEntry	 				**m_lru_tab;CacheDirectory::m_lru_tab176,5107
+    CacheDirectory(CacheDirectory::CacheDirectory183,5229
+    ~CacheDirectory(CacheDirectory::~CacheDirectory205,5909
+    DirectoryEntry read(CacheDirectory::read223,6571
+#define L2 226,6637
+#undef L2229,6833
+    void write(CacheDirectory::write257,7684
+    void print(CacheDirectory::print285,8721
+    DirectoryEntry select(CacheDirectory::select297,9281
+    void init(CacheDirectory::init333,10475
+  class HeapEntry{HeapEntry348,10933
+    typedef uint32_t size_t;HeapEntry::size_t349,10952
+      Owner     owner;HeapEntry::owner353,11021
+      size_t    next;HeapEntry::next354,11044
+      HeapEntry(HeapEntry::HeapEntry359,11144
+      HeapEntry(HeapEntry::HeapEntry368,11315
+      void copy(HeapEntry::copy377,11719
+      void print(HeapEntry::print386,12090
+  class HeapDirectory{HeapDirectory399,12596
+    typedef uint32_t size_t;HeapDirectory::size_t400,12619
+      size_t    ptr_free;HeapDirectory::ptr_free404,12696
+      bool      full;HeapDirectory::full405,12722
+      HeapEntry *m_heap_tab;HeapDirectory::m_heap_tab406,12744
+      size_t    tab_size;HeapDirectory::tab_size409,12813
+      HeapDirectory(HeapDirectory::HeapDirectory415,12929
+      ~HeapDirectory(HeapDirectory::~HeapDirectory426,13264
+      void init(HeapDirectory::init433,13533
+      void print(HeapDirectory::print448,14035
+      void print_list(HeapDirectory::print_list458,14537
+      bool is_full(HeapDirectory::is_full473,15180
+      size_t next_free_ptr(HeapDirectory::next_free_ptr481,15485
+      HeapEntry next_free_entry(HeapDirectory::next_free_entry489,15805
+      void write_free_entry(HeapDirectory::write_free_entry498,16195
+      void write_free_ptr(HeapDirectory::write_free_ptr506,16559
+      void set_full(HeapDirectory::set_full514,16964
+      void unset_full(HeapDirectory::unset_full521,17248
+      HeapEntry read(HeapDirectory::read531,17626
+      void write(HeapDirectory::write542,18139
+
+
+../include/update_tab_v3.h,1996
+#define UPDATE_TAB_V3_H_2,25
+class UpdateTabEntry 12,327
+  typedef uint32_t size_t;UpdateTabEntry::size_t13,350
+  typedef sc_dt::sc_uint<40> addr_t;UpdateTabEntry::addr_t14,377
+  bool 	valid;UpdateTabEntry::valid17,425
+  bool	update;UpdateTabEntry::update18,492
+  bool  brdcast;UpdateTabEntry::brdcast19,552
+  bool  rsp;UpdateTabEntry::rsp20,614
+  size_t 	srcid;UpdateTabEntry::srcid21,684
+  size_t 	trdid;UpdateTabEntry::trdid22,759
+  size_t 	pktid;UpdateTabEntry::pktid23,834
+  addr_t	nline;UpdateTabEntry::nline24,909
+  size_t 	count;UpdateTabEntry::count25,967
+  UpdateTabEntry(UpdateTabEntry::UpdateTabEntry27,1042
+  UpdateTabEntry(UpdateTabEntry::UpdateTabEntry39,1224
+  UpdateTabEntry(UpdateTabEntry::UpdateTabEntry60,1661
+  void init(UpdateTabEntry::init76,2127
+  void copy(UpdateTabEntry::copy94,2572
+  void print(UpdateTabEntry::print110,3054
+class UpdateTab{UpdateTab126,3794
+  typedef uint32_t size_t;UpdateTab::size_t128,3812
+  typedef sc_dt::sc_uint<40> addr_t;UpdateTab::addr_t129,3839
+  size_t size_tab;UpdateTab::size_tab132,3888
+  std::vector<UpdateTabEntry> tab;UpdateTab::tab133,3907
+  UpdateTab(UpdateTab::UpdateTab137,3954
+  UpdateTab(UpdateTab::UpdateTab143,4006
+  const size_t size(UpdateTab::size152,4290
+  void print(UpdateTab::print160,4537
+  void init(UpdateTab::init172,4912
+  UpdateTabEntry read UpdateTab::read185,5285
+  bool set(UpdateTab::set202,5993
+  bool decrement(UpdateTab::decrement237,7135
+  bool is_full(UpdateTab::is_full253,7617
+  bool need_rsp(UpdateTab::need_rsp268,8024
+  bool is_brdcast(UpdateTab::is_brdcast279,8409
+  bool is_update(UpdateTab::is_update290,8800
+  size_t srcid(UpdateTab::srcid301,9180
+  size_t trdid(UpdateTab::trdid312,9557
+  size_t pktid(UpdateTab::pktid323,9934
+  addr_t nline(UpdateTab::nline334,10311
+  bool search_inval(UpdateTab::search_inval345,10731
+  bool read_nline(UpdateTab::read_nline365,11305
+  void clear(UpdateTab::clear383,11804
+
+
+../include/vci_mem_cache_v3.h,38250
+#define SOCLIB_CABA_MEM_CACHE_V3_H42,1409
+#define TRANSACTION_TAB_LINES 64,1909
+#define UPDATE_TAB_LINES 65,2021
+    class VciMemCacheV371,2219
+      typedef sc_dt::sc_uint<40> addr_t;VciMemCacheV3::addr_t74,2287
+      typedef typename vci_param::fast_addr_t vci_addr_t;VciMemCacheV3::vci_addr_t75,2328
+      typedef uint32_t data_t;VciMemCacheV3::data_t76,2386
+      typedef uint32_t tag_t;VciMemCacheV3::tag_t77,2417
+      typedef uint32_t size_t;VciMemCacheV3::size_t78,2447
+      typedef uint32_t be_t;VciMemCacheV3::be_t79,2478
+      typedef uint32_t copy_t;VciMemCacheV3::copy_t80,2507
+      enum tgt_cmd_fsm_state_e{VciMemCacheV3::tgt_cmd_fsm_state_e83,2577
+        TGT_CMD_IDLE,VciMemCacheV3::tgt_cmd_fsm_state_e::TGT_CMD_IDLE84,2609
+        TGT_CMD_READ,VciMemCacheV3::tgt_cmd_fsm_state_e::TGT_CMD_READ85,2631
+        TGT_CMD_READ_EOP,VciMemCacheV3::tgt_cmd_fsm_state_e::TGT_CMD_READ_EOP86,2653
+        TGT_CMD_WRITE,VciMemCacheV3::tgt_cmd_fsm_state_e::TGT_CMD_WRITE87,2679
+        TGT_CMD_ATOMIC,VciMemCacheV3::tgt_cmd_fsm_state_e::TGT_CMD_ATOMIC88,2702
+      enum tgt_rsp_fsm_state_e{VciMemCacheV3::tgt_rsp_fsm_state_e92,2774
+        TGT_RSP_READ_IDLE,VciMemCacheV3::tgt_rsp_fsm_state_e::TGT_RSP_READ_IDLE93,2806
+        TGT_RSP_WRITE_IDLE,VciMemCacheV3::tgt_rsp_fsm_state_e::TGT_RSP_WRITE_IDLE94,2833
+        TGT_RSP_LLSC_IDLE,VciMemCacheV3::tgt_rsp_fsm_state_e::TGT_RSP_LLSC_IDLE95,2861
+        TGT_RSP_XRAM_IDLE,VciMemCacheV3::tgt_rsp_fsm_state_e::TGT_RSP_XRAM_IDLE96,2888
+        TGT_RSP_INIT_IDLE,VciMemCacheV3::tgt_rsp_fsm_state_e::TGT_RSP_INIT_IDLE97,2915
+        TGT_RSP_CLEANUP_IDLE,VciMemCacheV3::tgt_rsp_fsm_state_e::TGT_RSP_CLEANUP_IDLE98,2942
+        TGT_RSP_READ,VciMemCacheV3::tgt_rsp_fsm_state_e::TGT_RSP_READ99,2972
+        TGT_RSP_WRITE,VciMemCacheV3::tgt_rsp_fsm_state_e::TGT_RSP_WRITE100,2994
+        TGT_RSP_LLSC,VciMemCacheV3::tgt_rsp_fsm_state_e::TGT_RSP_LLSC101,3017
+        TGT_RSP_XRAM,VciMemCacheV3::tgt_rsp_fsm_state_e::TGT_RSP_XRAM102,3039
+        TGT_RSP_INIT,VciMemCacheV3::tgt_rsp_fsm_state_e::TGT_RSP_INIT103,3061
+        TGT_RSP_CLEANUP,VciMemCacheV3::tgt_rsp_fsm_state_e::TGT_RSP_CLEANUP104,3083
+      enum init_cmd_fsm_state_e{VciMemCacheV3::init_cmd_fsm_state_e108,3157
+        INIT_CMD_INVAL_IDLE,VciMemCacheV3::init_cmd_fsm_state_e::INIT_CMD_INVAL_IDLE109,3190
+        INIT_CMD_INVAL_NLINE,VciMemCacheV3::init_cmd_fsm_state_e::INIT_CMD_INVAL_NLINE110,3219
+        INIT_CMD_XRAM_BRDCAST,VciMemCacheV3::init_cmd_fsm_state_e::INIT_CMD_XRAM_BRDCAST111,3249
+        INIT_CMD_UPDT_IDLE,VciMemCacheV3::init_cmd_fsm_state_e::INIT_CMD_UPDT_IDLE112,3280
+        INIT_CMD_WRITE_BRDCAST,VciMemCacheV3::init_cmd_fsm_state_e::INIT_CMD_WRITE_BRDCAST113,3308
+        INIT_CMD_UPDT_NLINE,VciMemCacheV3::init_cmd_fsm_state_e::INIT_CMD_UPDT_NLINE114,3340
+        INIT_CMD_UPDT_INDEX,VciMemCacheV3::init_cmd_fsm_state_e::INIT_CMD_UPDT_INDEX115,3369
+        INIT_CMD_UPDT_DATA,VciMemCacheV3::init_cmd_fsm_state_e::INIT_CMD_UPDT_DATA116,3398
+        INIT_CMD_SC_UPDT_IDLE,VciMemCacheV3::init_cmd_fsm_state_e::INIT_CMD_SC_UPDT_IDLE117,3426
+        INIT_CMD_SC_BRDCAST,VciMemCacheV3::init_cmd_fsm_state_e::INIT_CMD_SC_BRDCAST118,3457
+        INIT_CMD_SC_UPDT_NLINE,VciMemCacheV3::init_cmd_fsm_state_e::INIT_CMD_SC_UPDT_NLINE119,3486
+        INIT_CMD_SC_UPDT_INDEX,VciMemCacheV3::init_cmd_fsm_state_e::INIT_CMD_SC_UPDT_INDEX120,3518
+        INIT_CMD_SC_UPDT_DATA,VciMemCacheV3::init_cmd_fsm_state_e::INIT_CMD_SC_UPDT_DATA121,3550
+      enum init_rsp_fsm_state_e{VciMemCacheV3::init_rsp_fsm_state_e125,3630
+        INIT_RSP_IDLE,VciMemCacheV3::init_rsp_fsm_state_e::INIT_RSP_IDLE126,3663
+        INIT_RSP_UPT_LOCK,VciMemCacheV3::init_rsp_fsm_state_e::INIT_RSP_UPT_LOCK127,3686
+        INIT_RSP_UPT_CLEAR,VciMemCacheV3::init_rsp_fsm_state_e::INIT_RSP_UPT_CLEAR128,3713
+        INIT_RSP_END,VciMemCacheV3::init_rsp_fsm_state_e::INIT_RSP_END129,3741
+      enum read_fsm_state_e{VciMemCacheV3::read_fsm_state_e133,3808
+        READ_IDLE,VciMemCacheV3::read_fsm_state_e::READ_IDLE134,3837
+        READ_DIR_LOCK,VciMemCacheV3::read_fsm_state_e::READ_DIR_LOCK135,3856
+        READ_DIR_HIT,VciMemCacheV3::read_fsm_state_e::READ_DIR_HIT136,3879
+        READ_HEAP_LOCK,VciMemCacheV3::read_fsm_state_e::READ_HEAP_LOCK137,3901
+        READ_HEAP_WRITE,VciMemCacheV3::read_fsm_state_e::READ_HEAP_WRITE138,3925
+        READ_HEAP_ERASE,VciMemCacheV3::read_fsm_state_e::READ_HEAP_ERASE139,3950
+        READ_HEAP_LAST,VciMemCacheV3::read_fsm_state_e::READ_HEAP_LAST140,3975
+        READ_RSP,VciMemCacheV3::read_fsm_state_e::READ_RSP141,3999
+        READ_TRT_LOCK,VciMemCacheV3::read_fsm_state_e::READ_TRT_LOCK142,4017
+        READ_TRT_SET,VciMemCacheV3::read_fsm_state_e::READ_TRT_SET143,4040
+        READ_XRAM_REQ,VciMemCacheV3::read_fsm_state_e::READ_XRAM_REQ144,4062
+      enum write_fsm_state_e{VciMemCacheV3::write_fsm_state_e148,4131
+        WRITE_IDLE,VciMemCacheV3::write_fsm_state_e::WRITE_IDLE149,4161
+        WRITE_NEXT,VciMemCacheV3::write_fsm_state_e::WRITE_NEXT150,4181
+        WRITE_DIR_LOCK,VciMemCacheV3::write_fsm_state_e::WRITE_DIR_LOCK151,4201
+        WRITE_DIR_HIT_READ,VciMemCacheV3::write_fsm_state_e::WRITE_DIR_HIT_READ152,4225
+        WRITE_DIR_HIT,VciMemCacheV3::write_fsm_state_e::WRITE_DIR_HIT153,4253
+        WRITE_DIR_HIT_RSP,VciMemCacheV3::write_fsm_state_e::WRITE_DIR_HIT_RSP154,4276
+        WRITE_UPT_LOCK,VciMemCacheV3::write_fsm_state_e::WRITE_UPT_LOCK155,4303
+        WRITE_HEAP_LOCK,VciMemCacheV3::write_fsm_state_e::WRITE_HEAP_LOCK156,4327
+        WRITE_UPT_REQ,VciMemCacheV3::write_fsm_state_e::WRITE_UPT_REQ157,4352
+        WRITE_UPDATE,VciMemCacheV3::write_fsm_state_e::WRITE_UPDATE158,4375
+        WRITE_UPT_DEC,VciMemCacheV3::write_fsm_state_e::WRITE_UPT_DEC159,4397
+        WRITE_RSP,VciMemCacheV3::write_fsm_state_e::WRITE_RSP160,4420
+        WRITE_TRT_LOCK,VciMemCacheV3::write_fsm_state_e::WRITE_TRT_LOCK161,4439
+        WRITE_TRT_DATA,VciMemCacheV3::write_fsm_state_e::WRITE_TRT_DATA162,4463
+        WRITE_TRT_SET,VciMemCacheV3::write_fsm_state_e::WRITE_TRT_SET163,4487
+        WRITE_WAIT,VciMemCacheV3::write_fsm_state_e::WRITE_WAIT164,4510
+        WRITE_XRAM_REQ,VciMemCacheV3::write_fsm_state_e::WRITE_XRAM_REQ165,4530
+        WRITE_TRT_WRITE_LOCK,VciMemCacheV3::write_fsm_state_e::WRITE_TRT_WRITE_LOCK166,4554
+        WRITE_INVAL_LOCK,VciMemCacheV3::write_fsm_state_e::WRITE_INVAL_LOCK167,4584
+        WRITE_DIR_INVAL,VciMemCacheV3::write_fsm_state_e::WRITE_DIR_INVAL168,4610
+        WRITE_INVAL,VciMemCacheV3::write_fsm_state_e::WRITE_INVAL169,4635
+        WRITE_XRAM_SEND,VciMemCacheV3::write_fsm_state_e::WRITE_XRAM_SEND170,4656
+        WRITE_HEAP_ERASE,VciMemCacheV3::write_fsm_state_e::WRITE_HEAP_ERASE171,4681
+        WRITE_HEAP_LAST,VciMemCacheV3::write_fsm_state_e::WRITE_HEAP_LAST172,4707
+      enum ixr_rsp_fsm_state_e{VciMemCacheV3::ixr_rsp_fsm_state_e176,4780
+        IXR_RSP_IDLE,VciMemCacheV3::ixr_rsp_fsm_state_e::IXR_RSP_IDLE177,4812
+        IXR_RSP_ACK,VciMemCacheV3::ixr_rsp_fsm_state_e::IXR_RSP_ACK178,4834
+        IXR_RSP_TRT_ERASE,VciMemCacheV3::ixr_rsp_fsm_state_e::IXR_RSP_TRT_ERASE179,4855
+        IXR_RSP_TRT_READ,VciMemCacheV3::ixr_rsp_fsm_state_e::IXR_RSP_TRT_READ180,4882
+      enum xram_rsp_fsm_state_e{VciMemCacheV3::xram_rsp_fsm_state_e184,4957
+        XRAM_RSP_IDLE,VciMemCacheV3::xram_rsp_fsm_state_e::XRAM_RSP_IDLE185,4990
+        XRAM_RSP_TRT_COPY,VciMemCacheV3::xram_rsp_fsm_state_e::XRAM_RSP_TRT_COPY186,5013
+        XRAM_RSP_TRT_DIRTY,VciMemCacheV3::xram_rsp_fsm_state_e::XRAM_RSP_TRT_DIRTY187,5040
+        XRAM_RSP_DIR_LOCK,VciMemCacheV3::xram_rsp_fsm_state_e::XRAM_RSP_DIR_LOCK188,5068
+        XRAM_RSP_DIR_UPDT,VciMemCacheV3::xram_rsp_fsm_state_e::XRAM_RSP_DIR_UPDT189,5095
+        XRAM_RSP_DIR_RSP,VciMemCacheV3::xram_rsp_fsm_state_e::XRAM_RSP_DIR_RSP190,5122
+        XRAM_RSP_INVAL_LOCK,VciMemCacheV3::xram_rsp_fsm_state_e::XRAM_RSP_INVAL_LOCK191,5148
+        XRAM_RSP_INVAL_WAIT,VciMemCacheV3::xram_rsp_fsm_state_e::XRAM_RSP_INVAL_WAIT192,5177
+        XRAM_RSP_INVAL,VciMemCacheV3::xram_rsp_fsm_state_e::XRAM_RSP_INVAL193,5206
+        XRAM_RSP_WRITE_DIRTY,VciMemCacheV3::xram_rsp_fsm_state_e::XRAM_RSP_WRITE_DIRTY194,5230
+        XRAM_RSP_HEAP_ERASE,VciMemCacheV3::xram_rsp_fsm_state_e::XRAM_RSP_HEAP_ERASE195,5260
+        XRAM_RSP_HEAP_LAST,VciMemCacheV3::xram_rsp_fsm_state_e::XRAM_RSP_HEAP_LAST196,5289
+      enum ixr_cmd_fsm_state_e{VciMemCacheV3::ixr_cmd_fsm_state_e200,5365
+        IXR_CMD_READ_IDLE,VciMemCacheV3::ixr_cmd_fsm_state_e::IXR_CMD_READ_IDLE201,5397
+        IXR_CMD_WRITE_IDLE,VciMemCacheV3::ixr_cmd_fsm_state_e::IXR_CMD_WRITE_IDLE202,5424
+        IXR_CMD_LLSC_IDLE,VciMemCacheV3::ixr_cmd_fsm_state_e::IXR_CMD_LLSC_IDLE203,5452
+        IXR_CMD_XRAM_IDLE,VciMemCacheV3::ixr_cmd_fsm_state_e::IXR_CMD_XRAM_IDLE204,5479
+        IXR_CMD_READ_NLINE,VciMemCacheV3::ixr_cmd_fsm_state_e::IXR_CMD_READ_NLINE205,5506
+        IXR_CMD_WRITE_NLINE,VciMemCacheV3::ixr_cmd_fsm_state_e::IXR_CMD_WRITE_NLINE206,5534
+        IXR_CMD_LLSC_NLINE,VciMemCacheV3::ixr_cmd_fsm_state_e::IXR_CMD_LLSC_NLINE207,5563
+        IXR_CMD_XRAM_DATA,VciMemCacheV3::ixr_cmd_fsm_state_e::IXR_CMD_XRAM_DATA208,5591
+      enum llsc_fsm_state_e{VciMemCacheV3::llsc_fsm_state_e212,5663
+        LLSC_IDLE,VciMemCacheV3::llsc_fsm_state_e::LLSC_IDLE213,5692
+        LL_DIR_LOCK,VciMemCacheV3::llsc_fsm_state_e::LL_DIR_LOCK214,5711
+        LL_DIR_HIT,VciMemCacheV3::llsc_fsm_state_e::LL_DIR_HIT215,5732
+        LL_RSP,VciMemCacheV3::llsc_fsm_state_e::LL_RSP216,5752
+        SC_DIR_LOCK,VciMemCacheV3::llsc_fsm_state_e::SC_DIR_LOCK217,5768
+        SC_DIR_HIT,VciMemCacheV3::llsc_fsm_state_e::SC_DIR_HIT218,5789
+        SC_UPT_LOCK,VciMemCacheV3::llsc_fsm_state_e::SC_UPT_LOCK219,5809
+        SC_WAIT,VciMemCacheV3::llsc_fsm_state_e::SC_WAIT220,5830
+        SC_HEAP_LOCK,VciMemCacheV3::llsc_fsm_state_e::SC_HEAP_LOCK221,5847
+        SC_UPT_REQ,VciMemCacheV3::llsc_fsm_state_e::SC_UPT_REQ222,5869
+        SC_UPDATE,VciMemCacheV3::llsc_fsm_state_e::SC_UPDATE223,5889
+        SC_TRT_LOCK,VciMemCacheV3::llsc_fsm_state_e::SC_TRT_LOCK224,5908
+        SC_INVAL_LOCK,VciMemCacheV3::llsc_fsm_state_e::SC_INVAL_LOCK225,5929
+        SC_DIR_INVAL,VciMemCacheV3::llsc_fsm_state_e::SC_DIR_INVAL226,5952
+        SC_INVAL,VciMemCacheV3::llsc_fsm_state_e::SC_INVAL227,5974
+        SC_XRAM_SEND,VciMemCacheV3::llsc_fsm_state_e::SC_XRAM_SEND228,5992
+        SC_HEAP_ERASE,VciMemCacheV3::llsc_fsm_state_e::SC_HEAP_ERASE229,6014
+        SC_HEAP_LAST,VciMemCacheV3::llsc_fsm_state_e::SC_HEAP_LAST230,6037
+        SC_RSP_FALSE,VciMemCacheV3::llsc_fsm_state_e::SC_RSP_FALSE231,6060
+        SC_RSP_TRUE,VciMemCacheV3::llsc_fsm_state_e::SC_RSP_TRUE232,6082
+        LLSC_TRT_LOCK,VciMemCacheV3::llsc_fsm_state_e::LLSC_TRT_LOCK233,6103
+        LLSC_TRT_SET,VciMemCacheV3::llsc_fsm_state_e::LLSC_TRT_SET234,6126
+        LLSC_XRAM_REQ,VciMemCacheV3::llsc_fsm_state_e::LLSC_XRAM_REQ235,6148
+      enum cleanup_fsm_state_e{VciMemCacheV3::cleanup_fsm_state_e239,6219
+        CLEANUP_IDLE,VciMemCacheV3::cleanup_fsm_state_e::CLEANUP_IDLE240,6251
+        CLEANUP_DIR_LOCK,VciMemCacheV3::cleanup_fsm_state_e::CLEANUP_DIR_LOCK241,6273
+        CLEANUP_DIR_WRITE,VciMemCacheV3::cleanup_fsm_state_e::CLEANUP_DIR_WRITE242,6299
+        CLEANUP_HEAP_LOCK,VciMemCacheV3::cleanup_fsm_state_e::CLEANUP_HEAP_LOCK243,6326
+        CLEANUP_HEAP_SEARCH,VciMemCacheV3::cleanup_fsm_state_e::CLEANUP_HEAP_SEARCH244,6353
+        CLEANUP_HEAP_CLEAN,VciMemCacheV3::cleanup_fsm_state_e::CLEANUP_HEAP_CLEAN245,6382
+        CLEANUP_HEAP_FREE,VciMemCacheV3::cleanup_fsm_state_e::CLEANUP_HEAP_FREE246,6410
+        CLEANUP_UPT_LOCK,VciMemCacheV3::cleanup_fsm_state_e::CLEANUP_UPT_LOCK247,6437
+        CLEANUP_UPT_WRITE,VciMemCacheV3::cleanup_fsm_state_e::CLEANUP_UPT_WRITE248,6463
+        CLEANUP_WRITE_RSP,VciMemCacheV3::cleanup_fsm_state_e::CLEANUP_WRITE_RSP249,6490
+        CLEANUP_RSP,VciMemCacheV3::cleanup_fsm_state_e::CLEANUP_RSP250,6517
+      enum alloc_dir_fsm_state_e{VciMemCacheV3::alloc_dir_fsm_state_e254,6588
+        ALLOC_DIR_READ,VciMemCacheV3::alloc_dir_fsm_state_e::ALLOC_DIR_READ255,6622
+        ALLOC_DIR_WRITE,VciMemCacheV3::alloc_dir_fsm_state_e::ALLOC_DIR_WRITE256,6646
+        ALLOC_DIR_LLSC,VciMemCacheV3::alloc_dir_fsm_state_e::ALLOC_DIR_LLSC257,6671
+        ALLOC_DIR_CLEANUP,VciMemCacheV3::alloc_dir_fsm_state_e::ALLOC_DIR_CLEANUP258,6695
+        ALLOC_DIR_XRAM_RSP,VciMemCacheV3::alloc_dir_fsm_state_e::ALLOC_DIR_XRAM_RSP259,6722
+      enum alloc_trt_fsm_state_e{VciMemCacheV3::alloc_trt_fsm_state_e263,6800
+        ALLOC_TRT_READ,VciMemCacheV3::alloc_trt_fsm_state_e::ALLOC_TRT_READ264,6834
+        ALLOC_TRT_WRITE,VciMemCacheV3::alloc_trt_fsm_state_e::ALLOC_TRT_WRITE265,6858
+        ALLOC_TRT_LLSC,VciMemCacheV3::alloc_trt_fsm_state_e::ALLOC_TRT_LLSC266,6883
+        ALLOC_TRT_XRAM_RSP,VciMemCacheV3::alloc_trt_fsm_state_e::ALLOC_TRT_XRAM_RSP267,6907
+        ALLOC_TRT_IXR_RSP,VciMemCacheV3::alloc_trt_fsm_state_e::ALLOC_TRT_IXR_RSP268,6935
+      enum alloc_upt_fsm_state_e{VciMemCacheV3::alloc_upt_fsm_state_e272,7012
+        ALLOC_UPT_WRITE,VciMemCacheV3::alloc_upt_fsm_state_e::ALLOC_UPT_WRITE273,7046
+        ALLOC_UPT_XRAM_RSP,VciMemCacheV3::alloc_upt_fsm_state_e::ALLOC_UPT_XRAM_RSP274,7071
+        ALLOC_UPT_INIT_RSP,VciMemCacheV3::alloc_upt_fsm_state_e::ALLOC_UPT_INIT_RSP275,7099
+        ALLOC_UPT_CLEANUP,VciMemCacheV3::alloc_upt_fsm_state_e::ALLOC_UPT_CLEANUP276,7127
+        ALLOC_UPT_LLSC,VciMemCacheV3::alloc_upt_fsm_state_e::ALLOC_UPT_LLSC277,7154
+      enum alloc_heap_fsm_state_e{VciMemCacheV3::alloc_heap_fsm_state_e281,7229
+        ALLOC_HEAP_READ,VciMemCacheV3::alloc_heap_fsm_state_e::ALLOC_HEAP_READ282,7264
+        ALLOC_HEAP_WRITE,VciMemCacheV3::alloc_heap_fsm_state_e::ALLOC_HEAP_WRITE283,7289
+        ALLOC_HEAP_LLSC,VciMemCacheV3::alloc_heap_fsm_state_e::ALLOC_HEAP_LLSC284,7315
+        ALLOC_HEAP_CLEANUP,VciMemCacheV3::alloc_heap_fsm_state_e::ALLOC_HEAP_CLEANUP285,7340
+        ALLOC_HEAP_XRAM_RSP,VciMemCacheV3::alloc_heap_fsm_state_e::ALLOC_HEAP_XRAM_RSP286,7368
+      uint32_t	   m_cpt_cycles;VciMemCacheV3::m_cpt_cycles289,7407
+      uint32_t	   m_cpt_read;VciMemCacheV3::m_cpt_read290,7472
+      uint32_t	   m_cpt_read_miss;VciMemCacheV3::m_cpt_read_miss291,7546
+      uint32_t	   m_cpt_write;VciMemCacheV3::m_cpt_write292,7613
+      uint32_t	   m_cpt_write_miss;VciMemCacheV3::m_cpt_write_miss293,7688
+      uint32_t     m_cpt_write_cells;VciMemCacheV3::m_cpt_write_cells294,7755
+      uint32_t     m_cpt_write_dirty;VciMemCacheV3::m_cpt_write_dirty295,7840
+      uint32_t	   m_cpt_update;VciMemCacheV3::m_cpt_update296,7925
+      uint32_t	   m_cpt_update_mult;VciMemCacheV3::m_cpt_update_mult297,8001
+      uint32_t	   m_cpt_inval;VciMemCacheV3::m_cpt_inval298,8076
+      uint32_t	   m_cpt_inval_mult;VciMemCacheV3::m_cpt_inval_mult299,8152
+      uint32_t	   m_cpt_inval_brdcast;VciMemCacheV3::m_cpt_inval_brdcast300,8228
+      uint32_t	   m_cpt_cleanup;VciMemCacheV3::m_cpt_cleanup301,8302
+      uint32_t	   m_cpt_ll;VciMemCacheV3::m_cpt_ll302,8379
+      uint32_t	   m_cpt_sc;VciMemCacheV3::m_cpt_sc303,8451
+      uint32_t     m_total_cycles;VciMemCacheV3::m_total_cycles304,8523
+        unsigned long m_waiting_cycles;VciMemCacheV3::m_waiting_cycles305,8558
+      sc_in<bool> 			  	p_clk;VciMemCacheV3::p_clk312,8713
+      sc_in<bool> 			  	p_resetn;VciMemCacheV3::p_resetn313,8744
+      soclib::caba::VciTarget<vci_param>    	p_vci_tgt;VciMemCacheV3::p_vci_tgt314,8778
+      soclib::caba::VciTarget<vci_param>    	p_vci_tgt_cleanup;VciMemCacheV3::p_vci_tgt_cleanup315,8834
+      soclib::caba::VciInitiator<vci_param> 	p_vci_ini;VciMemCacheV3::p_vci_ini316,8898
+      soclib::caba::VciInitiator<vci_param> 	p_vci_ixr;VciMemCacheV3::p_vci_ixr317,8955
+      const size_t              m_initiators;VciMemCacheV3::m_initiators348,10364
+      const size_t              m_heap_size;VciMemCacheV3::m_heap_size349,10444
+      const size_t              m_ways;VciMemCacheV3::m_ways350,10520
+      const size_t              m_sets;VciMemCacheV3::m_sets351,10603
+      const size_t              m_words;VciMemCacheV3::m_words352,10683
+      const size_t              m_srcid_ixr;VciMemCacheV3::m_srcid_ixr353,10762
+      const size_t              m_srcid_ini;VciMemCacheV3::m_srcid_ini354,10843
+      std::list<soclib::common::Segment>  m_seglist;VciMemCacheV3::m_seglist355,10929
+      std::list<soclib::common::Segment>  m_cseglist;VciMemCacheV3::m_cseglist356,11017
+      vci_addr_t        		*m_coherence_table;VciMemCacheV3::m_coherence_table357,11108
+      AtomicTab                 m_atomic_tab;VciMemCacheV3::m_atomic_tab358,11173
+      TransactionTab      		m_transaction_tab;VciMemCacheV3::m_transaction_tab359,11252
+      UpdateTab                 m_update_tab;VciMemCacheV3::m_update_tab360,11329
+      CacheDirectory			m_cache_directory;VciMemCacheV3::m_cache_directory361,11412
+      HeapDirectory             m_heap_directory;VciMemCacheV3::m_heap_directory362,11482
+      data_t	        	       ***m_cache_data;VciMemCacheV3::m_cache_data364,11557
+        std::ofstream             m_log;VciMemCacheV3::m_log365,11634
+      size_t                    m_tm_start;VciMemCacheV3::m_tm_start366,11675
+      long long                 m_debug_start;VciMemCacheV3::m_debug_start367,11719
+      size_t                    m_tm_end;VciMemCacheV3::m_tm_end368,11766
+      size_t                    m_period;VciMemCacheV3::m_period369,11808
+      const soclib::common::AddressMaskingTable<vci_addr_t>   m_x;VciMemCacheV3::m_x373,11874
+      const soclib::common::AddressMaskingTable<vci_addr_t>   m_y;VciMemCacheV3::m_y374,11941
+      const soclib::common::AddressMaskingTable<vci_addr_t>   m_z;VciMemCacheV3::m_z375,12008
+      const soclib::common::AddressMaskingTable<vci_addr_t>   m_nline;VciMemCacheV3::m_nline376,12075
+      vci_addr_t broadcast_addr;VciMemCacheV3::broadcast_addr379,12175
+      sc_signal<size_t>   r_copies_limit;VciMemCacheV3::r_copies_limit384,12349
+      GenericFifo<uint64_t>  m_cmd_read_addr_fifo;VciMemCacheV3::m_cmd_read_addr_fifo391,12649
+      GenericFifo<size_t>    m_cmd_read_length_fifo;VciMemCacheV3::m_cmd_read_length_fifo392,12700
+      GenericFifo<size_t>    m_cmd_read_srcid_fifo;VciMemCacheV3::m_cmd_read_srcid_fifo393,12753
+      GenericFifo<size_t>    m_cmd_read_trdid_fifo;VciMemCacheV3::m_cmd_read_trdid_fifo394,12805
+      GenericFifo<size_t>    m_cmd_read_pktid_fifo;VciMemCacheV3::m_cmd_read_pktid_fifo395,12857
+      GenericFifo<uint64_t>  m_cmd_write_addr_fifo;VciMemCacheV3::m_cmd_write_addr_fifo398,12962
+      GenericFifo<bool>      m_cmd_write_eop_fifo;VciMemCacheV3::m_cmd_write_eop_fifo399,13014
+      GenericFifo<size_t>    m_cmd_write_srcid_fifo;VciMemCacheV3::m_cmd_write_srcid_fifo400,13065
+      GenericFifo<size_t>    m_cmd_write_trdid_fifo;VciMemCacheV3::m_cmd_write_trdid_fifo401,13118
+      GenericFifo<size_t>    m_cmd_write_pktid_fifo;VciMemCacheV3::m_cmd_write_pktid_fifo402,13171
+      GenericFifo<data_t>    m_cmd_write_data_fifo;VciMemCacheV3::m_cmd_write_data_fifo403,13224
+      GenericFifo<be_t>	     m_cmd_write_be_fifo;VciMemCacheV3::m_cmd_write_be_fifo404,13276
+      GenericFifo<uint64_t>  m_cmd_llsc_addr_fifo;VciMemCacheV3::m_cmd_llsc_addr_fifo407,13374
+      GenericFifo<bool>      m_cmd_llsc_sc_fifo;VciMemCacheV3::m_cmd_llsc_sc_fifo408,13425
+      GenericFifo<size_t>    m_cmd_llsc_srcid_fifo;VciMemCacheV3::m_cmd_llsc_srcid_fifo409,13474
+      GenericFifo<size_t>    m_cmd_llsc_trdid_fifo;VciMemCacheV3::m_cmd_llsc_trdid_fifo410,13526
+      GenericFifo<size_t>    m_cmd_llsc_pktid_fifo;VciMemCacheV3::m_cmd_llsc_pktid_fifo411,13578
+      GenericFifo<data_t>    m_cmd_llsc_wdata_fifo;VciMemCacheV3::m_cmd_llsc_wdata_fifo412,13630
+      sc_signal<int>         r_tgt_cmd_fsm;VciMemCacheV3::r_tgt_cmd_fsm414,13683
+      sc_signal<size_t>	     r_index;VciMemCacheV3::r_index416,13728
+      size_t nseg;VciMemCacheV3::nseg417,13766
+      size_t ncseg;VciMemCacheV3::ncseg418,13785
+      soclib::common::Segment  **m_seg;VciMemCacheV3::m_seg419,13805
+      soclib::common::Segment  **m_cseg;VciMemCacheV3::m_cseg420,13845
+      sc_signal<int>         r_read_fsm;VciMemCacheV3::r_read_fsm425,14057
+      sc_signal<size_t>      r_read_copy;VciMemCacheV3::r_read_copy426,14119
+      sc_signal<bool>        r_read_copy_inst;VciMemCacheV3::r_read_copy_inst427,14194
+      sc_signal<tag_t>       r_read_tag;VciMemCacheV3::r_read_tag428,14268
+      sc_signal<bool>        r_read_is_cnt;VciMemCacheV3::r_read_is_cnt429,14346
+      sc_signal<bool>        r_read_lock;VciMemCacheV3::r_read_lock430,14423
+      sc_signal<bool>        r_read_dirty;VciMemCacheV3::r_read_dirty431,14496
+      sc_signal<bool>        r_read_inst;VciMemCacheV3::r_read_inst432,14571
+      sc_signal<size_t>      r_read_count;VciMemCacheV3::r_read_count433,14648
+      sc_signal<size_t>      r_read_ptr;VciMemCacheV3::r_read_ptr434,14716
+      sc_signal<data_t>     *r_read_data;VciMemCacheV3::r_read_data435,14787
+      sc_signal<size_t>      r_read_way;VciMemCacheV3::r_read_way436,14860
+      sc_signal<size_t>      r_read_trt_index;VciMemCacheV3::r_read_trt_index437,14938
+      sc_signal<size_t>      r_read_next_ptr;VciMemCacheV3::r_read_next_ptr438,15013
+      sc_signal<bool>        r_read_last_free;VciMemCacheV3::r_read_last_free439,15087
+      sc_signal<bool>        r_read_to_ixr_cmd_req;VciMemCacheV3::r_read_to_ixr_cmd_req442,15242
+      sc_signal<addr_t>      r_read_to_ixr_cmd_nline;VciMemCacheV3::r_read_to_ixr_cmd_nline443,15315
+      sc_signal<size_t>      r_read_to_ixr_cmd_trdid;VciMemCacheV3::r_read_to_ixr_cmd_trdid444,15391
+      sc_signal<bool>	   r_read_to_tgt_rsp_req;VciMemCacheV3::r_read_to_tgt_rsp_req447,15566
+      sc_signal<size_t>	   r_read_to_tgt_rsp_srcid;VciMemCacheV3::r_read_to_tgt_rsp_srcid448,15637
+      sc_signal<size_t>	   r_read_to_tgt_rsp_trdid;VciMemCacheV3::r_read_to_tgt_rsp_trdid449,15714
+      sc_signal<size_t>	   r_read_to_tgt_rsp_pktid;VciMemCacheV3::r_read_to_tgt_rsp_pktid450,15791
+      sc_signal<data_t>   *r_read_to_tgt_rsp_data;VciMemCacheV3::r_read_to_tgt_rsp_data451,15868
+      sc_signal<size_t>    r_read_to_tgt_rsp_word;VciMemCacheV3::r_read_to_tgt_rsp_word452,15948
+      sc_signal<size_t>    r_read_to_tgt_rsp_length;VciMemCacheV3::r_read_to_tgt_rsp_length453,16034
+      sc_signal<int>       r_write_fsm;VciMemCacheV3::r_write_fsm459,16305
+      sc_signal<addr_t>	   r_write_address;VciMemCacheV3::r_write_address460,16370
+      sc_signal<size_t>    r_write_word_index;VciMemCacheV3::r_write_word_index461,16444
+      sc_signal<size_t>    r_write_word_count;VciMemCacheV3::r_write_word_count462,16524
+      sc_signal<size_t>    r_write_srcid;VciMemCacheV3::r_write_srcid463,16603
+      sc_signal<size_t>    r_write_trdid;VciMemCacheV3::r_write_trdid464,16676
+      sc_signal<size_t>    r_write_pktid;VciMemCacheV3::r_write_pktid465,16749
+      sc_signal<data_t>	  *r_write_data;VciMemCacheV3::r_write_data466,16822
+      sc_signal<be_t>     *r_write_be;VciMemCacheV3::r_write_be467,16900
+      sc_signal<bool>      r_write_byte;VciMemCacheV3::r_write_byte468,16980
+      sc_signal<bool>      r_write_is_cnt;VciMemCacheV3::r_write_is_cnt469,17054
+      sc_signal<bool>      r_write_lock;VciMemCacheV3::r_write_lock470,17135
+      sc_signal<bool>      r_write_inst;VciMemCacheV3::r_write_inst471,17214
+      sc_signal<tag_t>     r_write_tag;VciMemCacheV3::r_write_tag472,17285
+      sc_signal<size_t>    r_write_copy;VciMemCacheV3::r_write_copy473,17370
+      sc_signal<bool>      r_write_copy_inst;VciMemCacheV3::r_write_copy_inst474,17449
+      sc_signal<size_t>	   r_write_count;VciMemCacheV3::r_write_count475,17529
+      sc_signal<size_t>    r_write_ptr;VciMemCacheV3::r_write_ptr476,17601
+      sc_signal<size_t>    r_write_next_ptr;VciMemCacheV3::r_write_next_ptr477,17676
+      sc_signal<bool>      r_write_to_dec;VciMemCacheV3::r_write_to_dec478,17756
+      sc_signal<size_t>	   r_write_way;VciMemCacheV3::r_write_way479,17844
+      sc_signal<size_t>    r_write_trt_index;VciMemCacheV3::r_write_trt_index480,17912
+      sc_signal<size_t>    r_write_upt_index;VciMemCacheV3::r_write_upt_index481,17992
+      sc_signal<bool>      r_write_to_tgt_rsp_req;VciMemCacheV3::r_write_to_tgt_rsp_req484,18156
+      sc_signal<size_t>    r_write_to_tgt_rsp_srcid;VciMemCacheV3::r_write_to_tgt_rsp_srcid485,18225
+      sc_signal<size_t>    r_write_to_tgt_rsp_trdid;VciMemCacheV3::r_write_to_tgt_rsp_trdid486,18302
+      sc_signal<size_t>    r_write_to_tgt_rsp_pktid;VciMemCacheV3::r_write_to_tgt_rsp_pktid487,18376
+      sc_signal<bool>	   r_write_to_ixr_cmd_req;VciMemCacheV3::r_write_to_ixr_cmd_req490,18537
+      sc_signal<bool>	   r_write_to_ixr_cmd_write;VciMemCacheV3::r_write_to_ixr_cmd_write491,18608
+      sc_signal<addr_t>    r_write_to_ixr_cmd_nline;VciMemCacheV3::r_write_to_ixr_cmd_nline492,18679
+      sc_signal<data_t>	  *r_write_to_ixr_cmd_data;VciMemCacheV3::r_write_to_ixr_cmd_data493,18753
+      sc_signal<size_t>    r_write_to_ixr_cmd_trdid;VciMemCacheV3::r_write_to_ixr_cmd_trdid494,18828
+      sc_signal<bool>	   r_write_to_init_cmd_multi_req;VciMemCacheV3::r_write_to_init_cmd_multi_req497,18993
+      sc_signal<bool>	   r_write_to_init_cmd_brdcast_req;VciMemCacheV3::r_write_to_init_cmd_brdcast_req498,19078
+      sc_signal<addr_t>	   r_write_to_init_cmd_nline;VciMemCacheV3::r_write_to_init_cmd_nline499,19161
+      sc_signal<size_t>	   r_write_to_init_cmd_trdid;VciMemCacheV3::r_write_to_init_cmd_trdid500,19239
+      sc_signal<data_t>   *r_write_to_init_cmd_data;VciMemCacheV3::r_write_to_init_cmd_data501,19322
+      sc_signal<bool>     *r_write_to_init_cmd_we;VciMemCacheV3::r_write_to_init_cmd_we502,19404
+      sc_signal<size_t>	   r_write_to_init_cmd_count;VciMemCacheV3::r_write_to_init_cmd_count503,19478
+      sc_signal<size_t>	   r_write_to_init_cmd_index;VciMemCacheV3::r_write_to_init_cmd_index504,19563
+      GenericFifo<bool>    m_write_to_init_cmd_inst_fifo;VciMemCacheV3::m_write_to_init_cmd_inst_fifo505,19652
+      GenericFifo<size_t>  m_write_to_init_cmd_srcid_fifo;VciMemCacheV3::m_write_to_init_cmd_srcid_fifo506,19736
+      sc_signal<bool>      r_write_to_init_rsp_req;VciMemCacheV3::r_write_to_init_rsp_req509,19889
+      sc_signal<size_t>    r_write_to_init_rsp_upt_index;VciMemCacheV3::r_write_to_init_rsp_upt_index510,19966
+      sc_signal<int> 	   r_init_rsp_fsm;VciMemCacheV3::r_init_rsp_fsm516,20228
+      sc_signal<size_t>	   r_init_rsp_upt_index;VciMemCacheV3::r_init_rsp_upt_index517,20289
+      sc_signal<size_t>	   r_init_rsp_srcid;VciMemCacheV3::r_init_rsp_srcid518,20368
+      sc_signal<size_t>	   r_init_rsp_trdid;VciMemCacheV3::r_init_rsp_trdid519,20444
+      sc_signal<size_t>	   r_init_rsp_pktid;VciMemCacheV3::r_init_rsp_pktid520,20520
+      sc_signal<addr_t>	   r_init_rsp_nline;VciMemCacheV3::r_init_rsp_nline521,20596
+      sc_signal<bool>	     r_init_rsp_to_tgt_rsp_req;VciMemCacheV3::r_init_rsp_to_tgt_rsp_req524,20762
+      sc_signal<size_t>	   r_init_rsp_to_tgt_rsp_srcid;VciMemCacheV3::r_init_rsp_to_tgt_rsp_srcid525,20836
+      sc_signal<size_t>	   r_init_rsp_to_tgt_rsp_trdid;VciMemCacheV3::r_init_rsp_to_tgt_rsp_trdid526,20914
+      sc_signal<size_t>	   r_init_rsp_to_tgt_rsp_pktid;VciMemCacheV3::r_init_rsp_to_tgt_rsp_pktid527,20992
+      sc_signal<int> 	     r_cleanup_fsm;VciMemCacheV3::r_cleanup_fsm533,21241
+      sc_signal<size_t>      r_cleanup_srcid;VciMemCacheV3::r_cleanup_srcid534,21304
+      sc_signal<size_t>      r_cleanup_trdid;VciMemCacheV3::r_cleanup_trdid535,21377
+      sc_signal<size_t>      r_cleanup_pktid;VciMemCacheV3::r_cleanup_pktid536,21450
+      sc_signal<addr_t>      r_cleanup_nline;VciMemCacheV3::r_cleanup_nline537,21523
+      sc_signal<copy_t>      r_cleanup_copy;VciMemCacheV3::r_cleanup_copy539,21596
+      sc_signal<size_t>      r_cleanup_copy_inst;VciMemCacheV3::r_cleanup_copy_inst540,21662
+      sc_signal<copy_t>      r_cleanup_count;VciMemCacheV3::r_cleanup_count541,21740
+      sc_signal<size_t>      r_cleanup_ptr;VciMemCacheV3::r_cleanup_ptr542,21813
+      sc_signal<size_t>      r_cleanup_prev_ptr;VciMemCacheV3::r_cleanup_prev_ptr543,21888
+      sc_signal<size_t>      r_cleanup_prev_srcid;VciMemCacheV3::r_cleanup_prev_srcid544,21972
+      sc_signal<bool>        r_cleanup_prev_inst;VciMemCacheV3::r_cleanup_prev_inst545,22056
+      sc_signal<size_t>      r_cleanup_next_ptr;VciMemCacheV3::r_cleanup_next_ptr546,22143
+      sc_signal<tag_t>       r_cleanup_tag;VciMemCacheV3::r_cleanup_tag547,22223
+      sc_signal<bool>        r_cleanup_is_cnt;VciMemCacheV3::r_cleanup_is_cnt548,22308
+      sc_signal<bool>        r_cleanup_lock;VciMemCacheV3::r_cleanup_lock549,22387
+      sc_signal<bool>        r_cleanup_inst;VciMemCacheV3::r_cleanup_inst550,22463
+      sc_signal<bool>        r_cleanup_dirty;VciMemCacheV3::r_cleanup_dirty551,22539
+      sc_signal<size_t>      r_cleanup_way;VciMemCacheV3::r_cleanup_way552,22617
+      sc_signal<size_t>      r_cleanup_write_srcid;VciMemCacheV3::r_cleanup_write_srcid554,22700
+      sc_signal<size_t>      r_cleanup_write_trdid;VciMemCacheV3::r_cleanup_write_trdid555,22779
+      sc_signal<size_t>      r_cleanup_write_pktid;VciMemCacheV3::r_cleanup_write_pktid556,22853
+      sc_signal<bool>        r_cleanup_need_rsp;VciMemCacheV3::r_cleanup_need_rsp557,22927
+      sc_signal<size_t>      r_cleanup_index;VciMemCacheV3::r_cleanup_index559,23001
+      sc_signal<bool>      r_cleanup_to_tgt_rsp_req;VciMemCacheV3::r_cleanup_to_tgt_rsp_req562,23182
+      sc_signal<size_t>    r_cleanup_to_tgt_rsp_srcid;VciMemCacheV3::r_cleanup_to_tgt_rsp_srcid563,23255
+      sc_signal<size_t>    r_cleanup_to_tgt_rsp_trdid;VciMemCacheV3::r_cleanup_to_tgt_rsp_trdid564,23332
+      sc_signal<size_t>    r_cleanup_to_tgt_rsp_pktid;VciMemCacheV3::r_cleanup_to_tgt_rsp_pktid565,23408
+      sc_signal<int>       r_llsc_fsm;VciMemCacheV3::r_llsc_fsm571,23652
+      sc_signal<data_t>	   r_llsc_data;VciMemCacheV3::r_llsc_data572,23713
+      sc_signal<copy_t>    r_llsc_copy;VciMemCacheV3::r_llsc_copy573,23776
+      sc_signal<bool>      r_llsc_copy_inst;VciMemCacheV3::r_llsc_copy_inst574,23848
+      sc_signal<size_t>    r_llsc_count;VciMemCacheV3::r_llsc_count575,23919
+      sc_signal<size_t>    r_llsc_ptr;VciMemCacheV3::r_llsc_ptr576,23984
+      sc_signal<size_t>    r_llsc_next_ptr;VciMemCacheV3::r_llsc_next_ptr577,24052
+      sc_signal<bool>      r_llsc_is_cnt;VciMemCacheV3::r_llsc_is_cnt578,24126
+      sc_signal<bool>      r_llsc_dirty;VciMemCacheV3::r_llsc_dirty579,24201
+      sc_signal<bool>      r_llsc_inst;VciMemCacheV3::r_llsc_inst580,24274
+      sc_signal<size_t>    r_llsc_way;VciMemCacheV3::r_llsc_way581,24334
+      sc_signal<size_t>    r_llsc_set;VciMemCacheV3::r_llsc_set582,24398
+      sc_signal<data_t>    r_llsc_tag;VciMemCacheV3::r_llsc_tag583,24462
+      sc_signal<size_t>    r_llsc_trt_index;VciMemCacheV3::r_llsc_trt_index584,24539
+      sc_signal<size_t>    r_llsc_upt_index;VciMemCacheV3::r_llsc_upt_index585,24614
+      sc_signal<bool>	   r_llsc_to_ixr_cmd_req;VciMemCacheV3::r_llsc_to_ixr_cmd_req588,24748
+      sc_signal<addr_t>	   r_llsc_to_ixr_cmd_nline;VciMemCacheV3::r_llsc_to_ixr_cmd_nline589,24815
+      sc_signal<size_t>	   r_llsc_to_ixr_cmd_trdid;VciMemCacheV3::r_llsc_to_ixr_cmd_trdid590,24887
+      sc_signal<bool>	   r_llsc_to_ixr_cmd_write;VciMemCacheV3::r_llsc_to_ixr_cmd_write591,24969
+      sc_signal<data_t>	  *r_llsc_to_ixr_cmd_data;VciMemCacheV3::r_llsc_to_ixr_cmd_data592,25036
+      sc_signal<bool>	   r_llsc_to_tgt_rsp_req;VciMemCacheV3::r_llsc_to_tgt_rsp_req596,25158
+      sc_signal<data_t>    r_llsc_to_tgt_rsp_data;VciMemCacheV3::r_llsc_to_tgt_rsp_data597,25225
+      sc_signal<size_t>	   r_llsc_to_tgt_rsp_srcid;VciMemCacheV3::r_llsc_to_tgt_rsp_srcid598,25295
+      sc_signal<size_t>	   r_llsc_to_tgt_rsp_trdid;VciMemCacheV3::r_llsc_to_tgt_rsp_trdid599,25368
+      sc_signal<size_t>	   r_llsc_to_tgt_rsp_pktid;VciMemCacheV3::r_llsc_to_tgt_rsp_pktid600,25441
+      sc_signal<bool>	   r_llsc_to_init_cmd_multi_req;VciMemCacheV3::r_llsc_to_init_cmd_multi_req603,25595
+      sc_signal<bool>	   r_llsc_to_init_cmd_brdcast_req;VciMemCacheV3::r_llsc_to_init_cmd_brdcast_req604,25670
+      sc_signal<addr_t>	   r_llsc_to_init_cmd_nline;VciMemCacheV3::r_llsc_to_init_cmd_nline605,25747
+      sc_signal<size_t>	   r_llsc_to_init_cmd_trdid;VciMemCacheV3::r_llsc_to_init_cmd_trdid606,25824
+      sc_signal<data_t>    r_llsc_to_init_cmd_wdata;VciMemCacheV3::r_llsc_to_init_cmd_wdata607,25906
+      sc_signal<size_t>	   r_llsc_to_init_cmd_index;VciMemCacheV3::r_llsc_to_init_cmd_index608,25985
+      GenericFifo<bool>    m_llsc_to_init_cmd_inst_fifo;VciMemCacheV3::m_llsc_to_init_cmd_inst_fifo609,26071
+      GenericFifo<size_t>  m_llsc_to_init_cmd_srcid_fifo;VciMemCacheV3::m_llsc_to_init_cmd_srcid_fifo610,26155
+      sc_signal<bool>      r_llsc_to_init_rsp_req;VciMemCacheV3::r_llsc_to_init_rsp_req613,26307
+      sc_signal<size_t>    r_llsc_to_init_rsp_upt_index;VciMemCacheV3::r_llsc_to_init_rsp_upt_index614,26384
+      sc_signal<int> 	   r_ixr_rsp_fsm;VciMemCacheV3::r_ixr_rsp_fsm620,26638
+      sc_signal<size_t>	   r_ixr_rsp_trt_index;VciMemCacheV3::r_ixr_rsp_trt_index621,26697
+      sc_signal<size_t>    r_ixr_rsp_cpt;VciMemCacheV3::r_ixr_rsp_cpt622,26764
+      sc_signal<bool>	  *r_ixr_rsp_to_xram_rsp_rok;VciMemCacheV3::r_ixr_rsp_to_xram_rsp_rok625,26906
+      sc_signal<int> 	   r_xram_rsp_fsm;VciMemCacheV3::r_xram_rsp_fsm631,27156
+      sc_signal<size_t>	   r_xram_rsp_trt_index;VciMemCacheV3::r_xram_rsp_trt_index632,27219
+      TransactionTabEntry  r_xram_rsp_trt_buf;VciMemCacheV3::r_xram_rsp_trt_buf633,27291
+      sc_signal<bool>	   r_xram_rsp_victim_inval;VciMemCacheV3::r_xram_rsp_victim_inval634,27369
+      sc_signal<bool>	   r_xram_rsp_victim_is_cnt;VciMemCacheV3::r_xram_rsp_victim_is_cnt635,27450
+      sc_signal<bool>	   r_xram_rsp_victim_dirty;VciMemCacheV3::r_xram_rsp_victim_dirty636,27528
+      sc_signal<size_t>    r_xram_rsp_victim_way;VciMemCacheV3::r_xram_rsp_victim_way637,27607
+      sc_signal<size_t>    r_xram_rsp_victim_set;VciMemCacheV3::r_xram_rsp_victim_set638,27680
+      sc_signal<addr_t>    r_xram_rsp_victim_nline;VciMemCacheV3::r_xram_rsp_victim_nline639,27753
+      sc_signal<copy_t>    r_xram_rsp_victim_copy;VciMemCacheV3::r_xram_rsp_victim_copy640,27830
+      sc_signal<bool>      r_xram_rsp_victim_copy_inst;VciMemCacheV3::r_xram_rsp_victim_copy_inst641,27909
+      sc_signal<size_t>    r_xram_rsp_victim_count;VciMemCacheV3::r_xram_rsp_victim_count642,27999
+      sc_signal<size_t>    r_xram_rsp_victim_ptr;VciMemCacheV3::r_xram_rsp_victim_ptr643,28087
+      sc_signal<data_t>	  *r_xram_rsp_victim_data;VciMemCacheV3::r_xram_rsp_victim_data644,28178
+      sc_signal<size_t>	   r_xram_rsp_upt_index;VciMemCacheV3::r_xram_rsp_upt_index645,28253
+      sc_signal<size_t>    r_xram_rsp_next_ptr;VciMemCacheV3::r_xram_rsp_next_ptr646,28325
+      sc_signal<bool>	   r_xram_rsp_to_tgt_rsp_req;VciMemCacheV3::r_xram_rsp_to_tgt_rsp_req649,28487
+      sc_signal<size_t>    r_xram_rsp_to_tgt_rsp_srcid;VciMemCacheV3::r_xram_rsp_to_tgt_rsp_srcid650,28556
+      sc_signal<size_t>    r_xram_rsp_to_tgt_rsp_trdid;VciMemCacheV3::r_xram_rsp_to_tgt_rsp_trdid651,28633
+      sc_signal<size_t>    r_xram_rsp_to_tgt_rsp_pktid;VciMemCacheV3::r_xram_rsp_to_tgt_rsp_pktid652,28710
+      sc_signal<data_t>   *r_xram_rsp_to_tgt_rsp_data;VciMemCacheV3::r_xram_rsp_to_tgt_rsp_data653,28787
+      sc_signal<size_t>    r_xram_rsp_to_tgt_rsp_word;VciMemCacheV3::r_xram_rsp_to_tgt_rsp_word654,28867
+      sc_signal<size_t>    r_xram_rsp_to_tgt_rsp_length;VciMemCacheV3::r_xram_rsp_to_tgt_rsp_length655,28943
+      sc_signal<bool>	    r_xram_rsp_to_init_cmd_multi_req;VciMemCacheV3::r_xram_rsp_to_init_cmd_multi_req658,29099
+      sc_signal<bool>       r_xram_rsp_to_init_cmd_brdcast_req;VciMemCacheV3::r_xram_rsp_to_init_cmd_brdcast_req659,29182
+      sc_signal<addr_t>     r_xram_rsp_to_init_cmd_nline;VciMemCacheV3::r_xram_rsp_to_init_cmd_nline660,29271
+      sc_signal<size_t>	    r_xram_rsp_to_init_cmd_trdid;VciMemCacheV3::r_xram_rsp_to_init_cmd_trdid661,29360
+      GenericFifo<bool>     m_xram_rsp_to_init_cmd_inst_fifo;VciMemCacheV3::m_xram_rsp_to_init_cmd_inst_fifo662,29450
+      GenericFifo<size_t>   m_xram_rsp_to_init_cmd_srcid_fifo;VciMemCacheV3::m_xram_rsp_to_init_cmd_srcid_fifo663,29542
+      sc_signal<bool>	   r_xram_rsp_to_ixr_cmd_req;VciMemCacheV3::r_xram_rsp_to_ixr_cmd_req666,29696
+      sc_signal<addr_t>	   r_xram_rsp_to_ixr_cmd_nline;VciMemCacheV3::r_xram_rsp_to_ixr_cmd_nline667,29765
+      sc_signal<data_t>	  *r_xram_rsp_to_ixr_cmd_data;VciMemCacheV3::r_xram_rsp_to_ixr_cmd_data668,29841
+      sc_signal<size_t>	   r_xram_rsp_to_ixr_cmd_trdid;VciMemCacheV3::r_xram_rsp_to_ixr_cmd_trdid669,29915
+      sc_signal<int> 	   r_ixr_cmd_fsm;VciMemCacheV3::r_ixr_cmd_fsm675,30170
+      sc_signal<size_t>	   r_ixr_cmd_cpt;VciMemCacheV3::r_ixr_cmd_cpt676,30210
+      sc_signal<int> 	   r_tgt_rsp_fsm;VciMemCacheV3::r_tgt_rsp_fsm682,30417
+      sc_signal<size_t>    r_tgt_rsp_cpt;VciMemCacheV3::r_tgt_rsp_cpt683,30457
+      sc_signal<int> 	  r_init_cmd_fsm;VciMemCacheV3::r_init_cmd_fsm689,30665
+      sc_signal<size_t>   r_init_cmd_cpt;VciMemCacheV3::r_init_cmd_cpt690,30705
+      sc_signal<bool>     r_init_cmd_inst;VciMemCacheV3::r_init_cmd_inst691,30747
+      sc_signal<int> 		r_alloc_dir_fsm;VciMemCacheV3::r_alloc_dir_fsm697,30957
+      sc_signal<int> 		r_alloc_trt_fsm;VciMemCacheV3::r_alloc_trt_fsm703,31164
+      sc_signal<int> 		r_alloc_upt_fsm;VciMemCacheV3::r_alloc_upt_fsm709,31371
+      sc_signal<int> 		r_alloc_heap_fsm;VciMemCacheV3::r_alloc_heap_fsm715,31579
+
+
+../include/xram_transaction_v3.h,2560
+#define XRAM_TRANSACTION_V3_H_2,31
+#define DEBUG_XRAM_TRANSACTION 11,189
+class TransactionTabEntry 17,423
+  typedef uint32_t size_t;TransactionTabEntry::size_t18,451
+  typedef uint32_t data_t;TransactionTabEntry::data_t19,478
+  typedef sc_dt::sc_uint<40> addr_t;TransactionTabEntry::addr_t20,505
+  typedef uint32_t be_t;TransactionTabEntry::be_t21,542
+  bool 		      valid;TransactionTabEntry::valid24,577
+  bool 		      xram_read;TransactionTabEntry::xram_read25,624
+  addr_t   	      nline;TransactionTabEntry::nline26,679
+  size_t 	      srcid;TransactionTabEntry::srcid27,748
+  size_t 	      trdid;TransactionTabEntry::trdid28,820
+  size_t 	      pktid;TransactionTabEntry::pktid29,892
+  bool 		      proc_read;TransactionTabEntry::proc_read30,964
+  size_t 		  read_length;TransactionTabEntry::read_length31,1025
+  size_t 	      word_index;TransactionTabEntry::word_index32,1097
+  std::vector<data_t> wdata;TransactionTabEntry::wdata33,1180
+  std::vector<be_t>   wdata_be;TransactionTabEntry::wdata_be34,1249
+  void init(TransactionTabEntry::init38,1517
+  void alloc(TransactionTabEntry::alloc48,1846
+  void copy(TransactionTabEntry::copy63,2326
+  void print(TransactionTabEntry::print81,2990
+  TransactionTabEntry(TransactionTabEntry::TransactionTabEntry104,4002
+  TransactionTabEntry(TransactionTabEntry::TransactionTabEntry111,4103
+class TransactionTab{TransactionTab130,4838
+  typedef uint32_t size_t;TransactionTab::size_t131,4860
+  typedef uint32_t data_t;TransactionTab::data_t132,4887
+  typedef sc_dt::sc_uint<40> addr_t;TransactionTab::addr_t133,4914
+  typedef uint32_t be_t;TransactionTab::be_t134,4951
+  size_t size_tab;TransactionTab::size_tab137,4987
+  data_t be_to_mask(TransactionTab::be_to_mask139,5045
+  TransactionTabEntry *tab;TransactionTab::tab158,5352
+  TransactionTab(TransactionTab::TransactionTab163,5571
+  TransactionTab(TransactionTab::TransactionTab169,5637
+  ~TransactionTab(TransactionTab::~TransactionTab178,5860
+  size_t size(TransactionTab::size186,6111
+  void init(TransactionTab::init194,6366
+  void print(TransactionTab::print206,6722
+  TransactionTabEntry read(TransactionTab::read219,7167
+  bool full(TransactionTab::full232,7671
+  bool hit_read(TransactionTab::hit_read251,8295
+  bool hit_write(TransactionTab::hit_write269,8916
+  void write_data_mask(TransactionTab::write_data_mask288,9563
+  void set(TransactionTab::set322,11155
+  void write_rsp(TransactionTab::write_rsp365,12790
+  void erase(TransactionTab::erase394,13815
Index: branches/v4/platforms/almos-tsarv3-platforms/common/vci_mem_cache_v3/caba/source/src/vci_mem_cache_v3.cpp
===================================================================
--- branches/v4/platforms/almos-tsarv3-platforms/common/vci_mem_cache_v3/caba/source/src/vci_mem_cache_v3.cpp	(revision 371)
+++ branches/v4/platforms/almos-tsarv3-platforms/common/vci_mem_cache_v3/caba/source/src/vci_mem_cache_v3.cpp	(revision 371)
@@ -0,0 +1,4807 @@
+/* -*- c++ -*-
+ * File 	: vci_mem_cache_v3.cpp
+ * Date 	: 30/10/2008
+ * Copyright 	: UPMC / LIP6
+ * Authors 	: Alain Greiner / Eric Guthmuller
+ *
+ * SOCLIB_LGPL_HEADER_BEGIN
+ *
+ * This file is part of SoCLib, GNU LGPLv2.1.
+ *
+ * SoCLib is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU Lesser General Public License as published
+ * by the Free Software Foundation; version 2.1 of the License.
+ *
+ * SoCLib is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with SoCLib; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301 USA
+ *
+ * SOCLIB_LGPL_HEADER_END
+ *
+ * Maintainers: alain eric.guthmuller@polytechnique.edu
+ */
+#include "../include/vci_mem_cache_v3.h"
+
+//#define TDEBUG // Transaction tab debug
+//#define IDEBUG // Update tab debug
+//#define DDEBUG // Directory debug
+//#define DEBUG_VCI_MEM_CACHE 1
+
+#define MEMC_INI_ID  8196 
+
+#define TRACE_MSG(...)                                                  \
+    do{                                                                 \
+        if((m_total_cycles > m_debug_start) || (current_waiting >= m_wait_threshold)) \
+            __VA_ARGS__;                                                \
+    }while(0)
+
+#define DUMP_UPDATE_TABLE                            \
+    do{                                         \
+        if((m_total_cycles > m_debug_start) || (current_waiting >= m_wait_threshold)) \
+            m_update_tab.print();                                       \
+    }while(0)
+
+
+#define DUMP_TRANSACTION_TABLE                            \
+    do{                                         \
+        if((m_total_cycles > m_debug_start) || (current_waiting >= m_wait_threshold)) { \
+            for(size_t i = 0 ; i < m_transaction_tab.size() ; i++)      \
+                m_transaction_tab.print(i, m_log);                      \
+        }                                                               \
+    }while(0)
+
+
+#define DUMP_ENTRY(x)  \
+    do {                                                                \
+        if((m_total_cycles > m_debug_start) || (current_waiting >= m_wait_threshold)) \
+            entry.print();                                              \
+    }while(0)
+
+namespace soclib { namespace caba {
+
+  const char *tgt_cmd_fsm_str[] = {
+    "TGT_CMD_IDLE",
+    "TGT_CMD_READ",
+    "TGT_CMD_READ_EOP",
+    "TGT_CMD_WRITE",
+    "TGT_CMD_ATOMIC",
+  };
+  const char *tgt_rsp_fsm_str[] = {
+    "TGT_RSP_READ_IDLE",
+    "TGT_RSP_WRITE_IDLE",
+    "TGT_RSP_LLSC_IDLE",
+    "TGT_RSP_XRAM_IDLE",
+    "TGT_RSP_INIT_IDLE",
+    "TGT_RSP_CLEANUP_IDLE",
+    "TGT_RSP_READ",
+    "TGT_RSP_WRITE",
+    "TGT_RSP_LLSC",
+    "TGT_RSP_XRAM",
+    "TGT_RSP_INIT",
+    "TGT_RSP_CLEANUP",
+  };
+  const char *init_cmd_fsm_str[] = {
+    "INIT_CMD_INVAL_IDLE",
+    "INIT_CMD_INVAL_NLINE",
+    "INIT_CMD_XRAM_BRDCAST",
+    "INIT_CMD_UPDT_IDLE",
+    "INIT_CMD_WRITE_BRDCAST",
+    "INIT_CMD_UPDT_NLINE",
+    "INIT_CMD_UPDT_INDEX",
+    "INIT_CMD_UPDT_DATA",
+    "INIT_CMD_SC_UPDT_IDLE",
+    "INIT_CMD_SC_BRDCAST",
+    "INIT_CMD_SC_UPDT_NLINE",
+    "INIT_CMD_SC_UPDT_INDEX",
+    "INIT_CMD_SC_UPDT_DATA",
+  };
+  const char *init_rsp_fsm_str[] = {
+    "INIT_RSP_IDLE",
+    "INIT_RSP_UPT_LOCK",
+    "INIT_RSP_UPT_CLEAR",
+    "INIT_RSP_END",
+  };
+  const char *read_fsm_str[] = {
+    "READ_IDLE",
+    "READ_DIR_LOCK",
+    "READ_DIR_HIT",
+    "READ_HEAP_LOCK",
+    "READ_HEAP_WRITE",
+    "READ_HEAP_ERASE",
+    "READ_HEAP_LAST",
+    "READ_RSP",
+    "READ_TRT_LOCK",
+    "READ_TRT_SET",
+    "READ_XRAM_REQ",
+  };
+  const char *write_fsm_str[] = {
+    "WRITE_IDLE",
+    "WRITE_NEXT",
+    "WRITE_DIR_LOCK",
+    "WRITE_DIR_HIT_READ",
+    "WRITE_DIR_HIT",
+    "WRITE_DIR_HIT_RSP",
+    "WRITE_UPT_LOCK",
+    "WRITE_HEAP_LOCK",
+    "WRITE_UPT_REQ",
+    "WRITE_UPDATE",
+    "WRITE_UPT_DEC",
+    "WRITE_RSP",
+    "WRITE_TRT_LOCK",
+    "WRITE_TRT_DATA",
+    "WRITE_TRT_SET",
+    "WRITE_WAIT",
+    "WRITE_XRAM_REQ",
+    "WRITE_TRT_WRITE_LOCK",
+    "WRITE_INVAL_LOCK",
+    "WRITE_DIR_INVAL",
+    "WRITE_INVAL",
+    "WRITE_XRAM_SEND",
+    "WRITE_HEAP_ERASE",
+    "WRITE_HEAP_LAST",
+  };
+  const char *ixr_rsp_fsm_str[] = {
+    "IXR_RSP_IDLE",
+    "IXR_RSP_ACK",
+    "IXR_RSP_TRT_ERASE",
+    "IXR_RSP_TRT_READ",
+  };
+  const char *xram_rsp_fsm_str[] = {
+    "XRAM_RSP_IDLE",
+    "XRAM_RSP_TRT_COPY",
+    "XRAM_RSP_TRT_DIRTY",
+    "XRAM_RSP_DIR_LOCK",
+    "XRAM_RSP_DIR_UPDT",
+    "XRAM_RSP_DIR_RSP",
+    "XRAM_RSP_INVAL_LOCK",
+    "XRAM_RSP_INVAL_WAIT",
+    "XRAM_RSP_INVAL",
+    "XRAM_RSP_WRITE_DIRTY",
+    "XRAM_RSP_HEAP_ERASE",
+    "XRAM_RSP_HEAP_LAST",
+  };
+  const char *ixr_cmd_fsm_str[] = {
+    "IXR_CMD_READ_IDLE",
+    "IXR_CMD_WRITE_IDLE",
+    "IXR_CMD_LLSC_IDLE",
+    "IXR_CMD_XRAM_IDLE",
+    "IXR_CMD_READ_NLINE",
+    "IXR_CMD_WRITE_NLINE",
+    "IXR_CMD_LLSC_NLINE",
+    "IXR_CMD_XRAM_DATA",
+  };
+  const char *llsc_fsm_str[] = {
+    "LLSC_IDLE",
+    "LL_DIR_LOCK",
+    "LL_DIR_HIT",
+    "LL_RSP",
+    "SC_DIR_LOCK",
+    "SC_DIR_HIT",
+    "SC_UPT_LOCK",
+    "SC_WAIT",
+    "SC_HEAP_LOCK",
+    "SC_UPT_REQ",
+    "SC_UPDATE",
+    "SC_TRT_LOCK",
+    "SC_INVAL_LOCK",
+    "SC_DIR_INVAL",
+    "SC_INVAL",
+    "SC_XRAM_SEND",
+    "SC_HEAP_ERASE",
+    "SC_HEAP_LAST",
+    "SC_RSP_FALSE",
+    "SC_RSP_TRUE",
+    "LLSC_TRT_LOCK",
+    "LLSC_TRT_SET",
+    "LLSC_XRAM_REQ",
+  };
+  const char *cleanup_fsm_str[] = {
+    "CLEANUP_IDLE",
+    "CLEANUP_DIR_LOCK",
+    "CLEANUP_DIR_WRITE",
+    "CLEANUP_HEAP_LOCK",
+    "CLEANUP_HEAP_SEARCH",
+    "CLEANUP_HEAP_CLEAN",
+    "CLEANUP_HEAP_FREE",
+    "CLEANUP_UPT_LOCK",
+    "CLEANUP_UPT_WRITE",
+    "CLEANUP_WRITE_RSP",
+    "CLEANUP_RSP",
+  };
+  const char *alloc_dir_fsm_str[] = {
+    "ALLOC_DIR_READ",
+    "ALLOC_DIR_WRITE",
+    "ALLOC_DIR_LLSC",
+    "ALLOC_DIR_CLEANUP",
+    "ALLOC_DIR_XRAM_RSP",
+  };
+  const char *alloc_trt_fsm_str[] = {
+    "ALLOC_TRT_READ",
+    "ALLOC_TRT_WRITE",
+    "ALLOC_TRT_LLSC",
+    "ALLOC_TRT_XRAM_RSP",
+    "ALLOC_TRT_IXR_RSP",
+  };
+  const char *alloc_upt_fsm_str[] = {
+    "ALLOC_UPT_WRITE",
+    "ALLOC_UPT_XRAM_RSP",
+    "ALLOC_UPT_INIT_RSP",
+    "ALLOC_UPT_CLEANUP",
+  };
+  const char *alloc_heap_fsm_str[] = {
+    "ALLOC_HEAP_READ",
+    "ALLOC_HEAP_WRITE",
+    "ALLOC_HEAP_LLSC",
+    "ALLOC_HEAP_CLEANUP",
+    "ALLOC_HEAP_XRAM_RSP",
+  };
+
+
+#define tmpl(x) template<typename vci_param> x VciMemCacheV3<vci_param>
+
+  using soclib::common::uint32_log2;
+
+  ////////////////////////////////
+  // 	Constructor 
+  ////////////////////////////////
+
+  tmpl(/**/)::VciMemCacheV3( 
+      sc_module_name name,
+      const soclib::common::MappingTable &mtp,
+      const soclib::common::MappingTable &mtc,
+      const soclib::common::MappingTable &mtx,
+      const soclib::common::IntTab &vci_ixr_index,
+      const soclib::common::IntTab &vci_ini_index,
+      const soclib::common::IntTab &vci_tgt_index,
+      const soclib::common::IntTab &vci_tgt_index_cleanup,
+      size_t nways,
+      size_t nsets,
+      size_t nwords,
+      size_t heap_size)
+
+    : soclib::caba::BaseModule(name),
+
+    p_clk("clk"),
+    p_resetn("resetn"),
+    p_vci_tgt("vci_tgt"),
+    p_vci_tgt_cleanup("vci_tgt_cleanup"),
+    p_vci_ini("vci_ini"),
+    p_vci_ixr("vci_ixr"),
+
+    m_initiators( 1 << vci_param::S ),
+    m_heap_size( heap_size ),
+    m_ways( nways ),
+    m_sets( nsets ),
+    m_words( nwords ),
+    m_srcid_ixr( mtx.indexForId(vci_ixr_index) ),
+    m_srcid_ini( mtc.indexForId(vci_ini_index) ),
+    m_seglist(mtp.getSegmentList(vci_tgt_index)),
+    m_cseglist(mtc.getSegmentList(vci_tgt_index_cleanup)),
+    m_coherence_table( mtc.getCoherenceTable<vci_addr_t>() ),
+    m_atomic_tab( m_initiators ),
+    m_transaction_tab( TRANSACTION_TAB_LINES, nwords ),
+    m_update_tab( UPDATE_TAB_LINES ),
+    m_cache_directory( nways, nsets, nwords, vci_param::N ),
+    m_heap_directory( m_heap_size ),
+
+#define L2 soclib::common::uint32_log2
+    m_x( L2(m_words), 2),
+    m_y( L2(m_sets), L2(m_words) + 2),
+    m_z( vci_param::N - L2(m_sets) - L2(m_words) - 2, L2(m_sets) + L2(m_words) + 2),
+    m_nline( vci_param::N - L2(m_words) - 2, L2(m_words) + 2),
+#undef L2
+
+    //  FIFOs 
+    m_cmd_read_addr_fifo("m_cmd_read_addr_fifo", 4),
+    m_cmd_read_length_fifo("m_cmd_read_length_fifo", 4),
+    m_cmd_read_srcid_fifo("m_cmd_read_srcid_fifo", 4),
+    m_cmd_read_trdid_fifo("m_cmd_read_trdid_fifo", 4),
+    m_cmd_read_pktid_fifo("m_cmd_read_pktid_fifo", 4),
+
+    m_cmd_write_addr_fifo("m_cmd_write_addr_fifo",8),
+    m_cmd_write_eop_fifo("m_cmd_write_eop_fifo",8),
+    m_cmd_write_srcid_fifo("m_cmd_write_srcid_fifo",8),
+    m_cmd_write_trdid_fifo("m_cmd_write_trdid_fifo",8),
+    m_cmd_write_pktid_fifo("m_cmd_write_pktid_fifo",8),
+    m_cmd_write_data_fifo("m_cmd_write_data_fifo",8),
+    m_cmd_write_be_fifo("m_cmd_write_be_fifo",8),
+
+    m_cmd_llsc_addr_fifo("m_cmd_llsc_addr_fifo",4),
+    m_cmd_llsc_sc_fifo("m_cmd_llsc_sc_fifo",4),
+    m_cmd_llsc_srcid_fifo("m_cmd_llsc_srcid_fifo",4),
+    m_cmd_llsc_trdid_fifo("m_cmd_llsc_trdid_fifo",4),
+    m_cmd_llsc_pktid_fifo("m_cmd_llsc_pktid_fifo",4),
+    m_cmd_llsc_wdata_fifo("m_cmd_llsc_wdata_fifo",4),
+
+    r_tgt_cmd_fsm("r_tgt_cmd_fsm"),
+    
+    nseg(0),	
+    ncseg(0),	
+
+    r_read_fsm("r_read_fsm"),
+    r_write_fsm("r_write_fsm"),
+    m_write_to_init_cmd_inst_fifo("m_write_to_init_cmd_inst_fifo",8),
+    m_write_to_init_cmd_srcid_fifo("m_write_to_init_cmd_srcid_fifo",8),
+    r_init_rsp_fsm("r_init_rsp_fsm"),
+    r_cleanup_fsm("r_cleanup_fsm"),
+    r_llsc_fsm("r_llsc_fsm"),
+    m_llsc_to_init_cmd_inst_fifo("m_llsc_to_init_cmd_inst_fifo",8),
+    m_llsc_to_init_cmd_srcid_fifo("m_llsc_to_init_cmd_srcid_fifo",8),
+    r_ixr_rsp_fsm("r_ixr_rsp_fsm"),
+    r_xram_rsp_fsm("r_xram_rsp_fsm"),
+    m_xram_rsp_to_init_cmd_inst_fifo("m_xram_rsp_to_init_cmd_inst_fifo",8),
+    m_xram_rsp_to_init_cmd_srcid_fifo("m_xram_rsp_to_init_cmd_srcid_fifo",8),
+    r_ixr_cmd_fsm("r_ixr_cmd_fsm"),
+    r_tgt_rsp_fsm("r_tgt_rsp_fsm"),
+    r_init_cmd_fsm("r_init_cmd_fsm"),
+    r_alloc_dir_fsm("r_alloc_dir_fsm"),
+    r_alloc_trt_fsm("r_alloc_trt_fsm"),
+    r_alloc_upt_fsm("r_alloc_upt_fsm")
+    {
+      assert(IS_POW_OF_2(nsets));
+      assert(IS_POW_OF_2(nwords));
+      assert(IS_POW_OF_2(nways));
+      assert(nsets);
+      assert(nwords);
+      assert(nways);
+      assert(nsets <= 1024);
+      assert(nwords <= 32);
+      assert(nways <= 32);
+
+      // Set the broadcast address with Xmin,Xmax,Ymin,Ymax set to maximum
+      broadcast_addr = 0x3 | (0x7C1F << (vci_param::N-20));
+
+      // Get the segments associated to the MemCache 
+      std::list<soclib::common::Segment>::iterator seg;
+
+      for(seg = m_seglist.begin(); seg != m_seglist.end() ; seg++) {
+        nseg++;
+      }
+      for(seg = m_cseglist.begin(); seg != m_cseglist.end() ; seg++) {
+        ncseg++;
+      }
+
+      m_seg = new soclib::common::Segment*[nseg];
+      size_t i = 0;
+      for ( seg = m_seglist.begin() ; seg != m_seglist.end() ; seg++ ) { 
+        m_seg[i] = &(*seg);
+        i++;
+      }
+      m_cseg = new soclib::common::Segment*[ncseg];
+      i = 0;
+      for ( seg = m_cseglist.begin() ; seg != m_cseglist.end() ; seg++ ) { 
+          m_cseg[i] = &(*seg);
+          i++;
+      }
+
+      // Memory cache allocation & initialisation
+      m_cache_data = new data_t**[nways];
+      for ( size_t i=0 ; i<nways ; ++i ) {
+        m_cache_data[i] = new data_t*[nsets];
+      }
+      for ( size_t i=0; i<nways; ++i ) {
+        for ( size_t j=0; j<nsets; ++j ) {
+          m_cache_data[i][j] = new data_t[nwords];
+          for ( size_t k=0; k<nwords; k++){
+            m_cache_data[i][j][k]=0;
+          }	
+        }
+      }
+
+      // Allocation for IXR_RSP FSM
+      r_ixr_rsp_to_xram_rsp_rok	    = new sc_signal<bool>[TRANSACTION_TAB_LINES];
+
+      // Allocation for XRAM_RSP FSM
+      r_xram_rsp_victim_data        = new sc_signal<data_t>[nwords];
+      r_xram_rsp_to_tgt_rsp_data    = new sc_signal<data_t>[nwords];
+      r_xram_rsp_to_ixr_cmd_data    = new sc_signal<data_t>[nwords];
+
+      // Allocation for READ FSM
+      r_read_data 			        = new sc_signal<data_t>[nwords];
+      r_read_to_tgt_rsp_data 		= new sc_signal<data_t>[nwords];
+
+      // Allocation for WRITE FSM
+      r_write_data 			        = new sc_signal<data_t>[nwords];
+      r_write_be 			        = new sc_signal<be_t>[nwords];
+      r_write_to_init_cmd_data 		= new sc_signal<data_t>[nwords];
+      r_write_to_init_cmd_we		= new sc_signal<bool>[nwords];
+      r_write_to_ixr_cmd_data	    = new sc_signal<data_t>[nwords];
+
+      // Allocation for LLSC FSM
+      r_llsc_to_ixr_cmd_data	    = new sc_signal<data_t>[nwords];
+
+
+      m_tm_start = 0;
+      m_tm_end = 0;
+      m_period = 0;
+      m_debug_start = 499999999LL;
+
+      char *ptr;
+
+      ptr = getenv("TSAR_MEMC_COPY_THRESHOLD");
+
+      if(ptr != NULL)
+          m_copy_threshold = atol(ptr);
+      else
+          m_copy_threshold = 3;
+      
+      ptr = getenv("TSAR_MEMC_TM_START");
+
+      if(ptr != NULL)
+          m_tm_start = (size_t) atol(ptr);
+
+      ptr = getenv("TSAR_MEMC_TM_END");
+
+      if(ptr != NULL)
+          m_tm_end = (size_t) atol(ptr);
+
+      ptr = getenv("TSAR_MEMC_PERIOD");
+
+      if(ptr != NULL)
+          m_period = (size_t) atol(ptr);
+      
+      ptr = getenv("TSAR_MEMC_DEBUG_START");
+
+      if(ptr != NULL)
+          m_debug_start = (long long) atoll(ptr);
+
+      if(m_period != 0)
+          m_log.open(name, std::ios::out);
+
+      ptr = getenv("TSAR_MEMC_WAIT_THRESHOLD");
+
+      if(ptr != NULL)
+          m_wait_threshold = atof(ptr);
+      else
+          m_wait_threshold = 0.95;
+
+
+      //std::cout << name << " srcid " << m_srcid_ini << std::endl;
+
+      if(m_srcid_ini == 4)
+      {
+          std::cout << "TSAR_MEMC_TM_START    =" << m_tm_start << std::endl
+                    << "TSAR_MEMC_TM_END      =" << m_tm_end << std::endl
+                    << "TSAR_MEMC_PERIOD      =" << m_period << std::endl
+                    << "TSAR_MEMC_DEBUG_START =" << m_debug_start << std::endl
+                    << "CPY_TH                =" << m_copy_threshold << std::endl
+                    << "TRT_TBL               =" << TRANSACTION_TAB_LINES << std::endl
+                    << "UPD_TBL               =" << UPDATE_TAB_LINES << std::endl;
+      }
+  
+      // Simulation
+
+      SC_METHOD(transition);
+      dont_initialize();
+      sensitive << p_clk.pos();
+
+      SC_METHOD(genMoore);
+      dont_initialize();
+      sensitive << p_clk.neg();
+
+    } // end constructor
+
+  /////////////////////////////////////////
+  // This function prints the statistics 
+  /////////////////////////////////////////
+
+  tmpl(void)::clear_stats()
+  {
+      // Activity counters
+      m_cpt_cycles		    = 0;
+      m_cpt_read		    = 0;
+      m_cpt_read_miss	    = 0;
+      m_cpt_write		    = 0;
+      m_cpt_write_miss	    = 0;
+      m_cpt_write_cells	    = 0;
+      m_cpt_write_dirty	    = 0;
+      m_cpt_update		    = 0;
+      m_cpt_update_mult     = 0;
+      m_cpt_inval_brdcast 	= 0;
+      m_cpt_inval 		    = 0;
+      m_cpt_inval_mult 		= 0;
+      m_cpt_cleanup		    = 0;
+      m_cpt_ll     		    = 0;
+      m_cpt_sc     		    = 0;
+      m_waiting_cycles      = 0;
+  }
+
+  tmpl(void)::print_log()
+  {
+      m_log << "----------------------------------" << std::dec << std::endl;
+      m_log << "MEM_CACHE " << m_srcid_ini << " / Time = " << m_total_cycles << std::endl
+            << "READ_RATE             = " << (double)m_cpt_read/m_cpt_cycles << std::endl
+            << "READ_MISS_RATE        = " << (double)m_cpt_read_miss/m_cpt_read << std::endl
+            << "WRITE_RATE            = " << (double)m_cpt_write/m_cpt_cycles << std::endl
+            << "WRITE_MISS_RATE       = " << (double)m_cpt_write_miss/m_cpt_write << std::endl
+            << "WRITE_BURST_LENGTH    = " << (double)m_cpt_write_cells/m_cpt_write << std::endl
+            << "UPDATE_RATE           = " << (double)m_cpt_update/m_cpt_cycles << std::endl
+            << "UPDATE_ARITY          = " << (double)m_cpt_update_mult/m_cpt_update << std::endl
+            << "INVAL_MULTICAST_RATE  = " << (double)(m_cpt_inval-m_cpt_inval_brdcast)/m_cpt_cycles << std::endl
+            << "INVAL_MULTICAST_ARITY = " << (double)m_cpt_inval_mult/(m_cpt_inval-m_cpt_inval_brdcast) << std::endl
+            << "INVAL_BROADCAST_RATE  = " << (double)m_cpt_inval_brdcast/m_cpt_cycles << std::endl
+            << "SAVE_DIRTY_RATE       = " << (double)m_cpt_write_dirty/m_cpt_cycles << std::endl
+            << "CLEANUP_RATE          = " << (double)m_cpt_cleanup/m_cpt_cycles << std::endl
+            << "LL_RATE               = " << (double)m_cpt_ll/m_cpt_cycles << std::endl
+            << "SC_RATE               = " << (double)m_cpt_sc/m_cpt_cycles << std::endl
+            << "TGT_WAITING_%         = " << (double)m_waiting_cycles/m_cpt_cycles << std::endl;
+  }
+
+
+
+  tmpl(void)::print_stats()
+  {
+      std::cout << "----------------------------------" << std::dec << std::endl;
+      std::cout << "MEM_CACHE " << m_srcid_ini << " / Time = " << m_total_cycles << std::endl
+                << "READ_RATE             = " << (double)m_cpt_read/m_cpt_cycles << std::endl
+                << "READ_MISS_RATE        = " << (double)m_cpt_read_miss/m_cpt_read << std::endl
+                << "WRITE_RATE            = " << (double)m_cpt_write/m_cpt_cycles << std::endl
+                << "WRITE_MISS_RATE       = " << (double)m_cpt_write_miss/m_cpt_write << std::endl
+                << "WRITE_BURST_LENGTH    = " << (double)m_cpt_write_cells/m_cpt_write << std::endl
+                << "UPDATE_RATE           = " << (double)m_cpt_update/m_cpt_cycles << std::endl
+                << "UPDATE_ARITY          = " << (double)m_cpt_update_mult/m_cpt_update << std::endl
+                << "INVAL_MULTICAST_RATE  = " << (double)(m_cpt_inval-m_cpt_inval_brdcast)/m_cpt_cycles << std::endl
+                << "INVAL_MULTICAST_ARITY = " << (double)m_cpt_inval_mult/(m_cpt_inval-m_cpt_inval_brdcast) << std::endl
+                << "INVAL_BROADCAST_RATE  = " << (double)m_cpt_inval_brdcast/m_cpt_cycles << std::endl
+                << "SAVE_DIRTY_RATE       = " << (double)m_cpt_write_dirty/m_cpt_cycles << std::endl
+                << "CLEANUP_RATE          = " << (double)m_cpt_cleanup/m_cpt_cycles << std::endl
+                << "LL_RATE               = " << (double)m_cpt_ll/m_cpt_cycles << std::endl
+                << "SC_RATE               = " << (double)m_cpt_sc/m_cpt_cycles << std::endl
+                << "TGT_WAITING_%         = " << (double)m_waiting_cycles/m_cpt_cycles << std::endl;
+  }
+
+  tmpl(void)::print_trace_to_log_file()
+  {
+      m_log << "---------------------------------------------" << std::dec << std::endl;
+      m_log << "MEM_CACHE " << m_srcid_ini << " ; Time = " << m_cpt_cycles << std::endl
+            << " - TGT_CMD FSM    = " << tgt_cmd_fsm_str[r_tgt_cmd_fsm] << std::endl
+            << " - TGT_RSP FSM    = " << tgt_rsp_fsm_str[r_tgt_rsp_fsm] << std::endl
+            << " - INIT_CMD FSM   = " << init_cmd_fsm_str[r_init_cmd_fsm] << std::endl
+            << " - INIT_RSP FSM   = " << init_rsp_fsm_str[r_init_rsp_fsm] << std::endl
+            << " - READ FSM       = " << read_fsm_str[r_read_fsm] << std::endl
+            << " - WRITE FSM      = " << write_fsm_str[r_write_fsm] << std::endl
+            << " - LLSC FSM       = " << llsc_fsm_str[r_llsc_fsm] << std::endl
+            << " - CLEANUP FSM    = " << cleanup_fsm_str[r_cleanup_fsm] << std::endl
+            << " - IXR_CMD FSM    = " << ixr_cmd_fsm_str[r_ixr_cmd_fsm] << std::endl
+            << " - IXR_RSP FSM    = " << ixr_rsp_fsm_str[r_ixr_rsp_fsm] << std::endl
+            << " - XRAM_RSP FSM   = " << xram_rsp_fsm_str[r_xram_rsp_fsm] << std::endl
+            << " - ALLOC_DIR FSM  = " << alloc_dir_fsm_str[r_alloc_dir_fsm] << std::endl
+            << " - ALLOC_TRT FSM  = " << alloc_trt_fsm_str[r_alloc_trt_fsm] << std::endl
+            << " - ALLOC_UPT FSM  = " << alloc_upt_fsm_str[r_alloc_upt_fsm] << std::endl
+            << " - ALLOC_HEAP FSM = " << alloc_heap_fsm_str[r_alloc_heap_fsm] << std::endl;
+  }
+    
+  /////////////////////////////////
+  tmpl(/**/)::~VciMemCacheV3()
+    /////////////////////////////////
+  {
+    for(size_t i=0; i<m_ways ; i++){
+      for(size_t j=0; j<m_sets ; j++){
+        delete [] m_cache_data[i][j];
+      }
+    }
+    for(size_t i=0; i<m_ways ; i++){
+      delete [] m_cache_data[i];
+    }
+    delete [] m_cache_data;
+    delete [] m_coherence_table;
+
+    delete [] r_ixr_rsp_to_xram_rsp_rok;
+
+    delete [] r_xram_rsp_victim_data;
+    delete [] r_xram_rsp_to_tgt_rsp_data;
+    delete [] r_xram_rsp_to_ixr_cmd_data;
+
+    delete [] r_read_data;
+    delete [] r_read_to_tgt_rsp_data;
+
+    delete [] r_write_data;
+    delete [] r_write_be;
+    delete [] r_write_to_init_cmd_data;
+  }
+
+  //////////////////////////////////
+  tmpl(void)::transition()
+    //////////////////////////////////
+  {
+    using soclib::common::uint32_log2;
+    //  RESET          
+    if ( ! p_resetn.read() ) {
+
+      //     Initializing FSMs
+      r_tgt_cmd_fsm 	= TGT_CMD_IDLE;
+      r_tgt_rsp_fsm 	= TGT_RSP_READ_IDLE;
+      r_init_cmd_fsm 	= INIT_CMD_INVAL_IDLE;
+      r_init_rsp_fsm 	= INIT_RSP_IDLE;
+      r_read_fsm 	= READ_IDLE;
+      r_write_fsm 	= WRITE_IDLE;
+      r_llsc_fsm 	= LLSC_IDLE;
+      r_cleanup_fsm 	= CLEANUP_IDLE;
+      r_alloc_dir_fsm   = ALLOC_DIR_READ;
+      r_alloc_trt_fsm   = ALLOC_TRT_READ;
+      r_alloc_upt_fsm   = ALLOC_UPT_WRITE;
+      r_ixr_rsp_fsm 	= IXR_RSP_IDLE;
+      r_xram_rsp_fsm 	= XRAM_RSP_IDLE;
+      r_ixr_cmd_fsm 	= IXR_CMD_READ_IDLE;
+
+      //  Initializing Tables
+      m_cache_directory.init();
+      m_atomic_tab.init();	
+      m_transaction_tab.init();
+      m_heap_directory.init();
+
+      // initializing FIFOs and communication Buffers
+
+      m_cmd_read_addr_fifo.init();
+      m_cmd_read_length_fifo.init();
+      m_cmd_read_srcid_fifo.init();
+      m_cmd_read_trdid_fifo.init();
+      m_cmd_read_pktid_fifo.init();
+
+      m_cmd_write_addr_fifo.init();
+      m_cmd_write_eop_fifo.init();
+      m_cmd_write_srcid_fifo.init();
+      m_cmd_write_trdid_fifo.init();
+      m_cmd_write_pktid_fifo.init();
+      m_cmd_write_data_fifo.init();
+
+      m_cmd_llsc_addr_fifo.init();
+      m_cmd_llsc_srcid_fifo.init();
+      m_cmd_llsc_trdid_fifo.init();
+      m_cmd_llsc_pktid_fifo.init();
+      m_cmd_llsc_wdata_fifo.init();
+      m_cmd_llsc_sc_fifo.init();
+
+      r_read_to_tgt_rsp_req	    = false;
+      r_read_to_ixr_cmd_req	    = false;
+
+      r_write_to_tgt_rsp_req	        = false;
+      r_write_to_ixr_cmd_req	        = false;
+      r_write_to_init_cmd_multi_req	    = false;
+      r_write_to_init_cmd_brdcast_req	= false;
+      r_write_to_init_rsp_req           = false;
+      m_write_to_init_cmd_inst_fifo.init();
+      m_write_to_init_cmd_srcid_fifo.init();
+
+      r_cleanup_to_tgt_rsp_req	= false;
+
+      r_init_rsp_to_tgt_rsp_req	= false;
+
+      r_llsc_to_tgt_rsp_req	            = false;
+      r_llsc_to_ixr_cmd_req	            = false;
+      r_llsc_to_init_cmd_multi_req	    = false;
+      r_llsc_to_init_cmd_brdcast_req	= false;
+      m_llsc_to_init_cmd_inst_fifo.init();
+      m_llsc_to_init_cmd_srcid_fifo.init();
+
+      for(size_t i=0; i<TRANSACTION_TAB_LINES ; i++){
+        r_ixr_rsp_to_xram_rsp_rok[i] = false;
+      }
+
+      r_xram_rsp_to_tgt_rsp_req	            = false;
+      r_xram_rsp_to_init_cmd_multi_req      = false;
+      r_xram_rsp_to_init_cmd_brdcast_req    = false;
+      r_xram_rsp_to_ixr_cmd_req	            = false;
+      r_xram_rsp_trt_index	                = 0;
+      m_xram_rsp_to_init_cmd_inst_fifo.init();
+      m_xram_rsp_to_init_cmd_srcid_fifo.init();
+
+      r_ixr_cmd_cpt         = 0;
+
+      r_copies_limit        = m_copy_threshold;
+      m_total_cycles = 0;
+      clear_stats();
+      return;
+    }
+
+    double current_waiting = 0;
+
+    if(m_period != 0)
+    {
+        size_t current_period;
+
+        current_period  = (m_cpt_cycles == 0) ? 1 : m_cpt_cycles;
+        current_waiting = (double)(m_waiting_cycles / current_period);
+        
+        if(current_waiting > m_wait_threshold)
+            print_trace_to_log_file();
+    }
+
+    bool    cmd_read_fifo_put = false;
+    bool    cmd_read_fifo_get = false;
+
+    bool    cmd_write_fifo_put = false;
+    bool    cmd_write_fifo_get = false;
+
+    bool    cmd_llsc_fifo_put = false;
+    bool    cmd_llsc_fifo_get = false;
+
+    bool    write_to_init_cmd_fifo_put   = false;
+    bool    write_to_init_cmd_fifo_get   = false;
+    bool    write_to_init_cmd_fifo_inst  = false;
+    size_t  write_to_init_cmd_fifo_srcid = 0;
+
+    bool    xram_rsp_to_init_cmd_fifo_put   = false;
+    bool    xram_rsp_to_init_cmd_fifo_get   = false;
+    bool    xram_rsp_to_init_cmd_fifo_inst  = false;
+    size_t  xram_rsp_to_init_cmd_fifo_srcid = 0;
+
+    bool    llsc_to_init_cmd_fifo_put   = false;
+    bool    llsc_to_init_cmd_fifo_get   = false;
+    bool    llsc_to_init_cmd_fifo_inst  = false;
+    size_t  llsc_to_init_cmd_fifo_srcid = 0;
+
+
+    ////////////////////////////////////////////////////////////////////////////////////
+    //		TGT_CMD FSM
+    ////////////////////////////////////////////////////////////////////////////////////
+    // The TGT_CMD_FSM controls the incoming VCI command pakets from the processors
+    //
+    // There is 4 types of packets for the m_mem_segment :
+    // - READ    : a READ request has a length of 1 VCI cell. It can be a single word 
+    //             or an entire cache line, depending on the PLEN value.
+    // - WRITE   : a WRITE request has a maximum length of 16 cells, and can only
+    //             concern words in a same line.
+    // - LL      : The LL request has a length of 1 cell.
+    // - SC      : The SC request has a length of 1 cell. 
+    //             The WDATA field contains the data to write.
+    //
+    ////////////////////////////////////////////////////////////////////////////////////
+
+    switch ( r_tgt_cmd_fsm.read() ) {
+
+      //////////////////
+      case TGT_CMD_IDLE:
+        {
+          if ( p_vci_tgt.cmdval ) 
+          {
+              m_waiting_cycles ++;
+
+              assert( (p_vci_tgt.srcid.read() < m_initiators)
+                      && "VCI_MEM_CACHE error in VCI_MEM_CACHE : The received SRCID is larger than the number of initiators");
+              
+              bool reached = false;
+              for ( size_t index = 0 ; index < nseg && !reached ; index++) 
+              {
+                  //              if ( m_seg[index]->contains((addr_t)(p_vci_tgt.address.read())) ) {
+                  if ( m_seg[index]->contains(p_vci_tgt.address.read()) ) {
+                      reached = true;
+                      r_index = index;
+                  }
+              }
+
+
+              if ( !reached ) 
+              { 
+                  std::cout << "VCI_MEM_CACHE Out of segment access in VCI_MEM_CACHE" << std::endl;
+                  std::cout << "Faulty address = " << std::hex << (addr_t)(p_vci_tgt.address.read()) << std::endl;
+                  std::cout << "Faulty initiator = " << std::dec << p_vci_tgt.srcid.read() << std::endl;
+                  exit(0);
+              } 
+              else if ( p_vci_tgt.cmd.read() == vci_param::CMD_READ ) 
+              {
+                  r_tgt_cmd_fsm = TGT_CMD_READ;
+              } 
+              else if ( p_vci_tgt.cmd.read() == vci_param::CMD_WRITE )
+              {  
+                  r_tgt_cmd_fsm = TGT_CMD_WRITE;
+              } 
+              else if ((p_vci_tgt.cmd.read() == vci_param::CMD_LOCKED_READ) || 
+                       (p_vci_tgt.cmd.read() == vci_param::CMD_STORE_COND) ) 
+              {
+                  r_tgt_cmd_fsm = TGT_CMD_ATOMIC;
+              } 
+          }
+          break;
+        }
+        //////////////////
+      case TGT_CMD_READ:
+
+        {
+          assert(((m_x[(vci_addr_t)p_vci_tgt.address.read()]+(p_vci_tgt.plen.read()>>2))<=16)
+              && "VCI_MEM_CACHE All read request to the MemCache must stay within a cache line"); 
+
+          m_waiting_cycles ++;
+
+          if ( p_vci_tgt.cmdval && m_cmd_read_addr_fifo.wok() ) {
+            cmd_read_fifo_put = true;
+            if ( p_vci_tgt.eop )  r_tgt_cmd_fsm = TGT_CMD_IDLE;
+            else                  r_tgt_cmd_fsm = TGT_CMD_READ_EOP;		
+          } 
+          break;
+        }
+        //////////////////////
+      case TGT_CMD_READ_EOP:
+        {
+            m_waiting_cycles ++;
+         
+            if ( p_vci_tgt.cmdval && p_vci_tgt.eop ){
+                r_tgt_cmd_fsm = TGT_CMD_IDLE;
+            }
+            break;
+        }
+        ///////////////////
+      case TGT_CMD_WRITE:
+        {
+
+            m_waiting_cycles ++;
+
+            if ( p_vci_tgt.cmdval && m_cmd_write_addr_fifo.wok() ) {
+                cmd_write_fifo_put = true;
+                if(  p_vci_tgt.eop )  r_tgt_cmd_fsm = TGT_CMD_IDLE;
+                
+            }
+            break;
+        }
+        ////////////////////
+      case TGT_CMD_ATOMIC:
+        {
+          assert(p_vci_tgt.eop && "Memory Cache Error: LL or SC command with length > 1 ");
+
+          m_waiting_cycles ++;
+
+          if ( p_vci_tgt.cmdval && m_cmd_llsc_addr_fifo.wok() ) {
+              cmd_llsc_fifo_put = true;
+              r_tgt_cmd_fsm = TGT_CMD_IDLE;
+          }
+          break;
+        }
+    } // end switch tgt_cmd_fsm
+
+    /////////////////////////////////////////////////////////////////////////
+    //		INIT_RSP FSM
+    /////////////////////////////////////////////////////////////////////////
+    // This FSM controls the response to the update or invalidate requests
+    // sent by the memory cache to the L1 caches :
+    //
+    // - update request initiated by the WRITE FSM.  
+    //   The FSM decrements the proper entry in the Update/Inval Table.
+    //   It sends a request to the TGT_RSP FSM to complete the pending 
+    //   write transaction (acknowledge response to the writer processor), 
+    //   and clear the UPT entry when all responses have been received.  
+    // - invalidate request initiated by the XRAM_RSP FSM.
+    //   The FSM decrements the proper entry in the Update/Inval_Table,
+    //   and clear the entry when all responses have been received.
+    //
+    // All those response packets are one word, compact
+    // packets complying with the VCI advanced format. 
+    // The index in the Table is defined in the RTRDID field, and
+    // the Transaction type is defined in the Update/Inval Table.
+    /////////////////////////////////////////////////////////////////////
+
+    switch ( r_init_rsp_fsm.read() ) {
+
+      ///////////////////
+      case INIT_RSP_IDLE:
+        {
+
+          if ( p_vci_ini.rspval ) {
+
+            assert ( ( p_vci_ini.rtrdid.read() < m_update_tab.size() )
+                && "VCI_MEM_CACHE UPT index too large in VCI response paquet received by memory cache" );
+            assert ( p_vci_ini.reop 
+                && "VCI_MEM_CACHE All response packets to update/invalidate requests must be one cell" );
+            r_init_rsp_upt_index = p_vci_ini.rtrdid.read(); 
+            r_init_rsp_fsm = INIT_RSP_UPT_LOCK;
+          } else if( r_write_to_init_rsp_req.read() ){
+            r_init_rsp_upt_index = r_write_to_init_rsp_upt_index.read();
+            r_write_to_init_rsp_req = false;
+            r_init_rsp_fsm = INIT_RSP_UPT_LOCK;
+          }
+          break;
+        }
+        ///////////////////////
+      case INIT_RSP_UPT_LOCK:	// decrement the number of expected responses
+        {
+
+          if ( r_alloc_upt_fsm.read() == ALLOC_UPT_INIT_RSP ) { 
+            size_t count = 0;
+            bool valid  = m_update_tab.decrement(r_init_rsp_upt_index.read(), count);
+#ifdef IDEBUG
+            TRACE_MSG(m_log
+                      << m_total_cycles 
+                      << " " << name() 
+                      << " INIT_RSP_UPT_LOCK update table : " << std::endl);
+            
+            DUMP_UPDATE_TABLE;
+#endif
+            assert ( valid 
+                && "VCI_MEM_CACHE Invalid UPT entry in VCI response paquet received by memory cache" );
+
+            if ( count == 0 ) r_init_rsp_fsm = INIT_RSP_UPT_CLEAR;
+            else              r_init_rsp_fsm = INIT_RSP_IDLE;
+          }
+          break;
+        }
+        ////////////////////////
+      case INIT_RSP_UPT_CLEAR:	// clear the UPT entry
+        {
+          if ( r_alloc_upt_fsm.read() == ALLOC_UPT_INIT_RSP ) {
+            r_init_rsp_srcid = m_update_tab.srcid(r_init_rsp_upt_index.read());
+            r_init_rsp_trdid = m_update_tab.trdid(r_init_rsp_upt_index.read());
+            r_init_rsp_pktid = m_update_tab.pktid(r_init_rsp_upt_index.read());
+            r_init_rsp_nline = m_update_tab.nline(r_init_rsp_upt_index.read());
+            bool need_rsp = m_update_tab.need_rsp(r_init_rsp_upt_index.read());
+            if ( need_rsp ) r_init_rsp_fsm = INIT_RSP_END;
+            else            r_init_rsp_fsm = INIT_RSP_IDLE;
+            m_update_tab.clear(r_init_rsp_upt_index.read());
+
+#ifdef IDEBUG
+            TRACE_MSG(std::cout << m_total_cycles << " " << name() << " INIT_RSP_UPT_CLEAR update table : " << std::endl);
+            DUMP_UPDATE_TABLE;
+#endif
+          }
+          break;
+        }
+        //////////////////
+      case INIT_RSP_END:
+        {
+
+          if ( !r_init_rsp_to_tgt_rsp_req ) {
+            r_init_rsp_to_tgt_rsp_req = true;
+            r_init_rsp_to_tgt_rsp_srcid = r_init_rsp_srcid.read();
+            r_init_rsp_to_tgt_rsp_trdid = r_init_rsp_trdid.read();
+            r_init_rsp_to_tgt_rsp_pktid = r_init_rsp_pktid.read();
+            r_init_rsp_fsm = INIT_RSP_IDLE;
+          }
+          break;
+        }
+    } // end switch r_init_rsp_fsm
+
+    ////////////////////////////////////////////////////////////////////////////////////
+    //		READ FSM
+    ////////////////////////////////////////////////////////////////////////////////////
+    // The READ FSM controls the read requests sent by processors.
+    // It takes the lock protecting the cache directory to check the cache line status:
+    // - In case of HIT, the fsm copies the data (one line, or one single word)
+    //   in the r_read_to_tgt_rsp buffer. It waits if this buffer is not empty.
+    //   The requesting initiator is registered in the cache directory.
+    // - In case of MISS, the READ fsm takes the lock protecting the transaction tab.
+    //   If a read transaction to the XRAM for this line already exists,
+    //   or if the transaction tab is full, the fsm is stalled.
+    //   If a transaction entry is free, the READ fsm sends a request to the XRAM.
+    ////////////////////////////////////////////////////////////////////////////////////
+
+    switch ( r_read_fsm.read() ) {
+
+      ///////////////
+      case READ_IDLE:
+        {
+          if (m_cmd_read_addr_fifo.rok()) {
+            m_cpt_read++;
+            r_read_fsm = READ_DIR_LOCK;
+          }
+          break;
+        }
+        ///////////////////
+      case READ_DIR_LOCK:	// check directory for hit / miss
+        {
+          if( r_alloc_dir_fsm.read() == ALLOC_DIR_READ ) {
+            size_t way = 0;
+            DirectoryEntry entry = m_cache_directory.read(m_cmd_read_addr_fifo.read(), way);
+#ifdef DDEBUG
+            TRACE_MSG(m_log << "In READ_DIR_LOCK printing the entry of address is : " 
+                      << std::hex << m_cmd_read_addr_fifo.read() 
+                      << std::endl);
+            DUMP_ENTRY(entry);
+            TRACE_MSG(m_log << "done" << std::endl);
+#endif
+
+            r_read_is_cnt   = entry.is_cnt;
+            r_read_dirty    = entry.dirty;
+            r_read_lock	    = entry.lock;
+            r_read_inst     = entry.inst;
+            r_read_tag	    = entry.tag;
+            r_read_way	    = way;
+            r_read_count    = entry.count;
+            r_read_copy     = entry.owner.srcid; 
+            r_read_copy_inst= entry.owner.inst;
+            r_read_ptr      = entry.ptr;
+
+            bool cached_read = (m_cmd_read_trdid_fifo.read() & 0x1);
+            // In case of hit, the read acces must be registered in the copies bit-vector
+            if( entry.valid ) 
+            {
+                if(entry.is_cnt || (entry.count == 0) || !cached_read)  { // No new entry in the heap
+                    r_read_fsm = READ_DIR_HIT;
+                } else {
+                    r_read_fsm = READ_HEAP_LOCK;
+                }
+            } 
+            else 
+            {
+                r_read_fsm = READ_TRT_LOCK;
+                m_cpt_read_miss++;
+            }
+          }
+          break;
+        }
+        //////////////////
+      case READ_DIR_HIT:	// read hit : update the memory cache
+        {
+          if( r_alloc_dir_fsm.read() == ALLOC_DIR_READ ) {
+            // signals generation
+            bool inst_read = (m_cmd_read_trdid_fifo.read() & 0x2);
+            bool cached_read = (m_cmd_read_trdid_fifo.read() & 0x1);
+            bool is_cnt = r_read_is_cnt.read();
+
+            // read data in the cache
+            size_t set = m_y[(vci_addr_t)(m_cmd_read_addr_fifo.read())];
+            size_t way = r_read_way.read();
+            for ( size_t i=0 ; i<m_words ; i++ ) {
+              r_read_data[i] = m_cache_data[way][set][i];
+            }
+
+            // update the cache directory (for the copies)
+            DirectoryEntry entry;
+            entry.valid	  = true;
+            entry.is_cnt  = is_cnt; 
+            entry.dirty	  = r_read_dirty.read();
+            entry.tag	  = r_read_tag.read();
+            entry.lock	  = r_read_lock.read();
+            entry.ptr     = r_read_ptr.read();
+            if(cached_read){  // Cached read, we update the copy
+              if(!is_cnt){ // Not counter mode
+                entry.owner.srcid   = m_cmd_read_srcid_fifo.read();
+                entry.owner.inst    = inst_read;
+                entry.inst          = r_read_inst.read() || inst_read;
+                entry.count         = r_read_count.read() + 1;
+              } else { // Counter mode
+                entry.owner.srcid   = 0;
+                entry.owner.inst    = false;
+                entry.inst          = r_read_inst.read() || inst_read;
+                entry.count         = r_read_count.read() + 1;
+              } 
+            } else { // Uncached read
+              entry.owner.srcid     = r_read_copy.read();
+              entry.owner.inst      = r_read_copy_inst.read();
+              entry.inst            = r_read_inst.read();
+              entry.count           = r_read_count.read();
+            }
+#ifdef DDEBUG
+            TRACE_MSG(m_log << "In READ_DIR_HIT printing the entry of address is : " << std::endl);
+            DUMP_ENTRY(entry);
+            TRACE_MSG(m_log << "done" << std::endl);
+#endif
+
+            m_cache_directory.write(set, way, entry);
+            r_read_fsm    = READ_RSP;
+          }
+          break;
+        }
+        //////////////
+      case READ_HEAP_LOCK:
+        {
+          if( r_alloc_heap_fsm.read() == ALLOC_HEAP_READ ) 
+          {
+              size_t copies_count = r_read_count.read() + 1;
+              bool inst_read = (m_cmd_read_trdid_fifo.read() & 0x2);
+              //bool is_cnt    = (r_read_count.read() >= r_copies_limit.read()) || m_heap_directory.is_full();
+              bool is_cnt    = (r_copies_limit.read() == 2) ? true : ((copies_count >= r_copies_limit.read()) || m_heap_directory.is_full());
+
+              // read data in the cache
+              size_t set     = m_y[(vci_addr_t)(m_cmd_read_addr_fifo.read())];
+              size_t way     = r_read_way.read();
+
+              for ( size_t i=0 ; i<m_words ; i++ ) {
+                  r_read_data[i] = m_cache_data[way][set][i];
+              }
+
+              // update the cache directory (for the copies)
+              DirectoryEntry entry;
+              entry.valid	  = true;
+              entry.is_cnt    = is_cnt; // when we reach the limit of copies or the heap is full
+              entry.dirty	  = r_read_dirty.read();
+              entry.tag	      = r_read_tag.read();
+              entry.lock	  = r_read_lock.read();
+              if(!is_cnt){ // Not counter mode
+                entry.owner.srcid   = r_read_copy.read();
+                entry.owner.inst    = r_read_copy_inst.read();
+                entry.inst          = r_read_inst.read() || inst_read;
+                entry.count         = r_read_count.read() + 1;
+                entry.ptr           = m_heap_directory.next_free_ptr();
+              } else { // Counter mode
+                entry.owner.srcid   = 0;
+                entry.owner.inst    = false;
+                entry.inst          = r_read_inst.read() || inst_read;
+                entry.count         = r_read_count.read() + 1;
+                entry.ptr           = 0;
+              }
+
+#ifdef DDEBUG
+              TRACE_MSG(m_log << "In READ_HEAP_LOCK printing the entry of address is : " << std::endl);
+              DUMP_ENTRY(entry);
+              TRACE_MSG(m_log << "done" << std::endl);
+#endif
+
+              m_cache_directory.write(set, way, entry);
+
+              if(!is_cnt)
+              {
+                  HeapEntry free_heap_entry = m_heap_directory.next_free_entry();
+                  r_read_next_ptr           = free_heap_entry.next;
+
+                  if( free_heap_entry.next == m_heap_directory.next_free_ptr() ) { // Last free heap entry
+                      r_read_last_free = true;
+                  } else {
+                      r_read_last_free = false;
+                  }
+
+                  r_read_fsm = READ_HEAP_WRITE; // we add an entry in the list of copies
+              } 
+              else 
+              {
+                  if(r_read_count.read()>1) 
+                  { // else there is no list of copies...
+                      HeapEntry next_entry = m_heap_directory.read(r_read_ptr.read());
+                      r_read_next_ptr = m_heap_directory.next_free_ptr();
+                      m_heap_directory.write_free_ptr(r_read_ptr.read());
+                      if( next_entry.next == r_read_ptr.read() ) { // The last list member
+                          r_read_fsm = READ_HEAP_LAST; // we erase the list of copies (counter mode)
+                      } else { // Not the end of the list
+                          r_read_ptr = next_entry.next;
+                          r_read_fsm = READ_HEAP_ERASE; // we erase the list of copies (counter mode)
+                      }
+                  } 
+                  else 
+                  {
+                      r_read_fsm = READ_RSP;
+                  }
+              }
+          }
+          break;
+        }
+        //////////////
+      case READ_HEAP_WRITE:
+        {
+          if(r_alloc_heap_fsm.read() == ALLOC_HEAP_READ){
+            bool inst_read = (m_cmd_read_trdid_fifo.read() & 0x2);
+            HeapEntry new_heap_entry;
+            new_heap_entry.owner.srcid  = m_cmd_read_srcid_fifo.read();
+            new_heap_entry.owner.inst   = inst_read;
+            if(r_read_count.read() == 1){ // creation of a new list
+              new_heap_entry.next         = m_heap_directory.next_free_ptr(); 
+            } else {                      // it is an insertion
+              new_heap_entry.next         = r_read_ptr.read();
+            }
+            m_heap_directory.write_free_entry(new_heap_entry);
+            m_heap_directory.write_free_ptr(r_read_next_ptr.read());
+            if(r_read_last_free.read()) {
+              m_heap_directory.set_full();
+            }
+
+            r_read_fsm = READ_RSP;
+          } else {
+            assert(false && "MEMCACHE Error : Bad HEAP allocation");
+          }
+          break;
+        }
+        //////////////
+      case READ_HEAP_ERASE:
+        {
+          if(r_alloc_heap_fsm.read() == ALLOC_HEAP_READ){
+            HeapEntry next_entry = m_heap_directory.read(r_read_ptr.read());
+            if( next_entry.next == r_read_ptr.read() ){
+              r_read_fsm = READ_HEAP_LAST;
+            } else {
+              r_read_ptr = next_entry.next;
+              r_read_fsm = READ_HEAP_ERASE;
+            }
+          } else {
+            assert(false && "MEMCACHE Error : Bad HEAP allocation");
+          }
+          break;
+        }
+        //////////////
+      case READ_HEAP_LAST:
+        {
+          if(r_alloc_heap_fsm.read() == ALLOC_HEAP_READ){
+            HeapEntry last_entry;
+            last_entry.owner.srcid = 0;
+            last_entry.owner.inst  = false;
+            if(m_heap_directory.is_full()){
+              last_entry.next      = r_read_ptr.read();
+              m_heap_directory.unset_full();
+            } else {
+              last_entry.next      = r_read_next_ptr.read();
+            }
+            m_heap_directory.write(r_read_ptr.read(),last_entry);
+            r_read_fsm = READ_RSP;
+          } else {
+            assert(false && "MEMCACHE Error : Bad HEAP allocation");
+          }
+          break;
+        }
+        //////////////
+      case READ_RSP: 		//  request the TGT_RSP FSM to return data
+        {
+          if( !r_read_to_tgt_rsp_req ) {	
+            for ( size_t i=0 ; i<m_words ; i++ ) {
+              r_read_to_tgt_rsp_data[i] = r_read_data[i];
+            }
+            r_read_to_tgt_rsp_word   = m_x[(vci_addr_t)m_cmd_read_addr_fifo.read()];
+            r_read_to_tgt_rsp_length = m_cmd_read_length_fifo.read();
+            cmd_read_fifo_get 		 = true;
+            r_read_to_tgt_rsp_req	 = true;
+            r_read_to_tgt_rsp_srcid	 = m_cmd_read_srcid_fifo.read();
+            r_read_to_tgt_rsp_trdid	 = m_cmd_read_trdid_fifo.read();
+            r_read_to_tgt_rsp_pktid	 = m_cmd_read_pktid_fifo.read();
+            r_read_fsm 			     = READ_IDLE;  
+          }
+          break;
+        }
+        ///////////////////
+      case READ_TRT_LOCK:	// read miss : check the Transaction Table
+        {
+          if ( r_alloc_trt_fsm.read() == ALLOC_TRT_READ ) {
+#ifdef TDEBUG
+              TRACE_MSG(m_log << m_total_cycles << " " << name() << " READ_TRT_LOCK " << std::endl);
+#endif
+            size_t index     = 0;
+            bool   hit_read  = m_transaction_tab.hit_read(m_nline[(vci_addr_t)(m_cmd_read_addr_fifo.read())], index);
+            bool   hit_write = m_transaction_tab.hit_write(m_nline[(vci_addr_t)(m_cmd_read_addr_fifo.read())]);
+            bool   wok       = !m_transaction_tab.full(index);
+
+            if( hit_read || !wok || hit_write )  // missing line already requested or no space
+            {  
+              r_read_fsm = READ_IDLE; 
+              
+              TRACE_MSG(m_log << m_total_cycles 
+                        << " " << name() 
+                        << " READ_TRT_LOCK -> READ_IDLE"
+                        << " address = " << std::hex << m_cmd_read_addr_fifo.read()
+                        << " read hit = " << hit_read
+                        << ", write hit = " << hit_write
+                        << std::endl);
+            }
+            else 		                         // missing line is requested to the XRAM 
+            {	
+              r_read_trt_index = index;
+              r_read_fsm       = READ_TRT_SET;
+            }
+          }
+          break;
+        }
+        //////////////////
+      case READ_TRT_SET:
+        {
+          if ( r_alloc_trt_fsm.read() == ALLOC_TRT_READ ) {
+            m_transaction_tab.set(r_read_trt_index.read(),
+                true,
+                m_nline[(vci_addr_t)(m_cmd_read_addr_fifo.read())],
+                m_cmd_read_srcid_fifo.read(),
+                m_cmd_read_trdid_fifo.read(),
+                m_cmd_read_pktid_fifo.read(),
+                true,
+                m_cmd_read_length_fifo.read(),
+                m_x[(vci_addr_t)(m_cmd_read_addr_fifo.read())],
+                std::vector<be_t>(m_words,0),
+                std::vector<data_t>(m_words,0));
+#ifdef TDEBUG
+            TRACE_MSG(m_log << m_total_cycles << " " << name() 
+                      << " Address = " << std::hex << m_cmd_read_addr_fifo.read()
+                      << " READ_TRT_SET transaction table : " << std::endl);
+
+            DUMP_TRANSACTION_TABLE;
+#endif
+
+            r_read_fsm 	 = READ_XRAM_REQ;
+          }
+          break;
+        }
+        /////////////////////
+      case READ_XRAM_REQ:
+        {
+          if( !r_read_to_ixr_cmd_req ) {
+            cmd_read_fifo_get		= true;
+            r_read_to_ixr_cmd_req  	= true;
+            r_read_to_ixr_cmd_nline 	= m_nline[(vci_addr_t)(m_cmd_read_addr_fifo.read())];
+            r_read_to_ixr_cmd_trdid 	= r_read_trt_index.read();
+            r_read_fsm 			          = READ_IDLE;
+          }
+          break;
+        }
+    } // end switch read_fsm
+
+    ///////////////////////////////////////////////////////////////////////////////////
+    //		WRITE FSM
+    ///////////////////////////////////////////////////////////////////////////////////
+    // The WRITE FSM handles the write bursts sent by the processors.
+    // All addresses in a burst must be in the same cache line.
+    // A complete write burst is consumed in the FIFO & copied to a local buffer.
+    // Then the FSM takes the lock protecting the cache directory, to check
+    // if the line is in the cache.
+    //
+    // - In case of HIT, the cache is updated.
+    //   If there is no other copy, an acknowledge response is immediately
+    //   returned to the writing processor.
+    //   if the data is cached by other processoris, the FSM takes the lock
+    //   protecting the Update Table (UPT) to register this update transaction.
+    //   If the UPT is full, it releases the lock  and waits. Then, it sends 
+    //   a multi-update request to all owners of the line (but the writer), 
+    //   through the INIT_CMD FSM. In case of multi-update transaction, the WRITE FSM 
+    //   does not respond to the writing processor, as this response will be sent by 
+    //   the INIT_RSP FSM when all update responses have been received.
+    //
+    // - In case of MISS, the WRITE FSM takes the lock protecting the transaction
+    //   table (TRT). If a read transaction to the XRAM for this line already exists, 
+    //   it writes in the TRT (write buffer). Otherwise, if a TRT entry is free, 
+    //   the WRITE FSM register a new transaction in TRT, and sends a read line request 
+    //   to the XRAM. If the TRT is full, it releases the lock, and waits.
+    //   Finally, the WRITE FSM returns an aknowledge response to the writing processor.
+    /////////////////////////////////////////////////////////////////////////////////////
+
+    switch ( r_write_fsm.read() ) {
+
+      ////////////////
+      case WRITE_IDLE:	// copy first word of a write burst in local buffer	
+        {
+          if ( m_cmd_write_addr_fifo.rok()) {
+            m_cpt_write++;
+            m_cpt_write_cells++;
+            // consume a word in the FIFO & write it in the local buffer 
+            cmd_write_fifo_get	= true;
+            size_t index 	    = m_x[(vci_addr_t)(m_cmd_write_addr_fifo.read())];
+            r_write_address	    = (addr_t)(m_cmd_write_addr_fifo.read());
+            r_write_word_index	= index;
+            r_write_word_count	= 1;
+            r_write_data[index]	= m_cmd_write_data_fifo.read();
+            r_write_srcid	    = m_cmd_write_srcid_fifo.read();
+            r_write_trdid	    = m_cmd_write_trdid_fifo.read();
+            r_write_pktid	    = m_cmd_write_pktid_fifo.read();
+
+            // the be field must be set for all words 
+            for ( size_t i=0 ; i<m_words ; i++ ) {
+              if ( i == index ) r_write_be[i] = m_cmd_write_be_fifo.read();
+              else		        r_write_be[i] = 0x0;
+            }
+            if( !((m_cmd_write_be_fifo.read() == 0x0)||(m_cmd_write_be_fifo.read() == 0xF)) )
+                    r_write_byte=true;
+            else    r_write_byte=false;
+
+            if( m_cmd_write_eop_fifo.read() )  r_write_fsm = WRITE_DIR_LOCK;
+            else                               r_write_fsm = WRITE_NEXT;
+          }
+          break;
+        }
+        ////////////////
+      case WRITE_NEXT:	// copy next word of a write burst in local buffer
+        {
+          if ( m_cmd_write_addr_fifo.rok() ) {
+            m_cpt_write_cells++;
+
+            // check that the next word is in the same cache line
+            assert( (m_nline[(vci_addr_t)(r_write_address.read())] == m_nline[(vci_addr_t)(m_cmd_write_addr_fifo.read())])  
+                && "VCI_MEM_CACHE write error in vci_mem_cache : write burst over a line" );
+            // consume a word in the FIFO & write it in the local buffer 
+            cmd_write_fifo_get=true;
+            size_t index 	        = r_write_word_index.read() + r_write_word_count.read();
+            r_write_be[index]       = m_cmd_write_be_fifo.read();
+            r_write_data[index]     = m_cmd_write_data_fifo.read();
+            r_write_word_count 	    = r_write_word_count.read() + 1;
+            if( !((m_cmd_write_be_fifo.read() == 0x0)||(m_cmd_write_be_fifo.read() == 0xF)) )
+              r_write_byte=true;
+            if ( m_cmd_write_eop_fifo.read() )  r_write_fsm = WRITE_DIR_LOCK;
+          }
+          break;
+        }
+        ////////////////////
+      case WRITE_DIR_LOCK:	// access directory to check hit/miss
+        {
+          if ( r_alloc_dir_fsm.read() == ALLOC_DIR_WRITE ) {
+            size_t  way = 0;
+            DirectoryEntry entry(m_cache_directory.read(r_write_address.read(), way));
+
+            // copy directory entry in local buffers in case of hit
+            if ( entry.valid )  {	
+              r_write_is_cnt    = entry.is_cnt;
+              r_write_lock	    = entry.lock;
+              r_write_inst      = entry.inst;
+              r_write_tag       = entry.tag;
+              r_write_copy      = entry.owner.srcid;
+              r_write_copy_inst = entry.owner.inst;
+              r_write_count     = entry.count;
+              r_write_ptr       = entry.ptr;
+              r_write_way  	    = way;
+              
+              bool owner = (entry.owner.srcid==r_write_srcid.read()) && !entry.owner.inst;
+              bool no_update = (entry.count==0) || ( owner && (entry.count==1));
+
+              if((entry.is_cnt && entry.count) || entry.inst)
+              {
+                  r_write_fsm      = WRITE_DIR_HIT_READ;
+              } 
+              else 
+              {
+                  if(r_write_byte.read())
+                      r_write_fsm      = WRITE_DIR_HIT_READ;
+                  else
+                  { 
+                      if( no_update) r_write_fsm  = WRITE_DIR_HIT_RSP;
+                      else           r_write_fsm  = WRITE_DIR_HIT;
+                  }
+              }
+            } 
+            else 
+            {
+                r_write_fsm = WRITE_TRT_LOCK;
+                m_cpt_write_miss++;
+            }
+          }
+          break;
+        }
+        ///////////////////
+      case WRITE_DIR_HIT_READ:	// read the cache and complete the buffer (data, when be!=0xF)
+        {
+          // update local buffer
+          size_t set	= m_y[(vci_addr_t)(r_write_address.read())];
+          size_t way	= r_write_way.read();
+          for(size_t i=0 ; i<m_words ; i++) {
+            data_t mask      = 0;
+            if  (r_write_be[i].read() & 0x1) mask = mask | 0x000000FF;
+            if  (r_write_be[i].read() & 0x2) mask = mask | 0x0000FF00;
+            if  (r_write_be[i].read() & 0x4) mask = mask | 0x00FF0000;
+            if  (r_write_be[i].read() & 0x8) mask = mask | 0xFF000000;
+            if(r_write_be[i].read()||r_write_is_cnt.read()||r_write_inst.read()) { // complete only if mask is not null (for energy consumption)
+              r_write_data[i]  = (r_write_data[i].read() & mask) | 
+                (m_cache_data[way][set][i] & ~mask);
+            }
+          } // end for
+
+          bool owner = (r_write_copy.read()==r_write_srcid.read()) && !r_write_copy_inst.read();
+          bool no_update = (r_write_count.read()==0) || ( owner && (r_write_count.read()==1));
+          if((r_write_is_cnt.read() && r_write_count.read()) ||
+              r_write_inst.read()){
+            r_write_fsm            = WRITE_TRT_WRITE_LOCK;
+          } else {
+            if( no_update ) r_write_fsm = WRITE_DIR_HIT_RSP;
+            else            r_write_fsm = WRITE_DIR_HIT;
+          }
+          break;
+        }
+        ///////////////////
+      case WRITE_DIR_HIT:	// update the cache (data & dirty bit)
+        {
+          // update directory with Dirty bit
+          DirectoryEntry entry;
+          entry.valid	    = true;
+          entry.dirty	    = true;
+          entry.tag	        = r_write_tag.read();
+          entry.is_cnt      = r_write_is_cnt.read();
+          entry.lock	    = r_write_lock.read();
+          entry.inst        = r_write_inst.read();
+          entry.owner.srcid = r_write_copy.read();
+          entry.owner.inst  = r_write_copy_inst.read();
+          entry.count       = r_write_count.read();
+          entry.ptr         = r_write_ptr.read();
+          size_t set	    = m_y[(vci_addr_t)(r_write_address.read())];
+          size_t way	    = r_write_way.read();
+          m_cache_directory.write(set, way, entry);
+
+          bool owner = (r_write_copy.read()==r_write_srcid.read()) && !r_write_copy_inst.read();
+
+          size_t count_signal   = r_write_count.read();
+          if(owner){
+            count_signal        = count_signal - 1;
+          }
+          r_write_count         = count_signal;
+          r_write_to_dec        = false;
+
+          if( !r_write_to_init_cmd_multi_req.read() && 
+              !r_write_to_init_cmd_brdcast_req.read()  )
+            r_write_fsm = WRITE_UPT_LOCK;
+          else
+            r_write_fsm = WRITE_WAIT;
+          break;
+        }
+        ///////////////////
+      case WRITE_DIR_HIT_RSP:	// update the cache (data & dirty bit) no update
+        {
+          // update directory with Dirty bit
+          DirectoryEntry entry;
+          entry.valid	    = true;
+          entry.dirty	    = true;
+          entry.tag	        = r_write_tag.read();
+          entry.is_cnt      = r_write_is_cnt.read();
+          entry.lock	    = r_write_lock.read();
+          entry.inst        = r_write_inst.read();
+          entry.owner.srcid = r_write_copy.read();
+          entry.owner.inst  = r_write_copy_inst.read();
+          entry.count       = r_write_count.read();
+          entry.ptr         = r_write_ptr.read();
+          size_t set	    = m_y[(vci_addr_t)(r_write_address.read())];
+          size_t way	    = r_write_way.read();
+          m_cache_directory.write(set, way, entry);
+
+          bool owner = (r_write_copy.read()==r_write_srcid.read()) && !r_write_copy_inst.read();
+
+          // write data in cache
+          for(size_t i=0 ; i<m_words ; i++) {
+              if  ( r_write_be[i].read() ) {
+                  m_cache_data[way][set][i]  = r_write_data[i].read();
+              }
+          } // end for
+
+          if ( !r_write_to_tgt_rsp_req.read() ) {
+            r_write_to_tgt_rsp_req	    = true;
+            r_write_to_tgt_rsp_srcid	= r_write_srcid.read();
+            r_write_to_tgt_rsp_trdid	= r_write_trdid.read();
+            r_write_to_tgt_rsp_pktid	= r_write_pktid.read();
+            r_write_fsm 		        = WRITE_IDLE;
+          } else {
+            r_write_fsm = WRITE_RSP;
+          }
+          break;
+        }
+        /////////////////////
+      case WRITE_UPT_LOCK: 	// Try to register the request in Update Table
+        {
+
+          if ( r_alloc_upt_fsm.read() == ALLOC_UPT_WRITE ) {
+            bool        wok        = false;
+            size_t      index      = 0;
+            size_t      srcid      = r_write_srcid.read();
+            size_t      trdid      = r_write_trdid.read();
+            size_t      pktid      = r_write_pktid.read();
+            addr_t      nline      = m_nline[(vci_addr_t)(r_write_address.read())];
+            size_t      nb_copies  = r_write_count.read();
+            size_t set	    = m_y[(vci_addr_t)(r_write_address.read())];
+            size_t way	    = r_write_way.read();
+
+            wok =m_update_tab.set(true,	// it's an update transaction
+                false,                  // it's not a broadcast
+                true,                   // it needs a response
+                srcid,
+                trdid,
+                pktid,
+                nline,
+                nb_copies,
+                index);
+            if(wok){
+              // write data in cache
+              for(size_t i=0 ; i<m_words ; i++) {
+                if  ( r_write_be[i].read() ) {
+                  m_cache_data[way][set][i]  = r_write_data[i].read();
+                }
+              } // end for
+            }
+#ifdef IDEBUG
+            if((wok) && (m_total_cycles > m_debug_start) && (m_srcid_ini == MEMC_INI_ID)){
+                TRACE_MSG(m_log << 
+                          m_total_cycles 
+                          << " " << name() << " WRITE_UPT_LOCK update table : " 
+                          << std::endl);
+                m_update_tab.print();
+            }
+#endif
+            r_write_upt_index = index;
+            //  releases the lock protecting the Update Table and the Directory if no entry...
+            if ( wok ) r_write_fsm = WRITE_HEAP_LOCK;
+            else       r_write_fsm = WRITE_WAIT;
+          }
+          break;
+        }
+        //////////////////
+      case WRITE_HEAP_LOCK:
+        {
+          if( r_alloc_heap_fsm.read() == ALLOC_HEAP_WRITE ){
+            r_write_fsm = WRITE_UPT_REQ;
+          }
+          break;
+        }
+        //////////////////
+      case WRITE_UPT_REQ:
+        {
+          assert( (r_alloc_heap_fsm.read() == ALLOC_HEAP_WRITE) &&
+                    "MemCache ERROR : bad HEAP allocation");
+          if( !r_write_to_init_cmd_multi_req.read() && 
+              !r_write_to_init_cmd_brdcast_req.read()  ){
+            r_write_to_init_cmd_brdcast_req  = false;
+            r_write_to_init_cmd_trdid        = r_write_upt_index.read();
+            r_write_to_init_cmd_nline        = m_nline[(vci_addr_t)(r_write_address.read())];
+            r_write_to_init_cmd_index        = r_write_word_index.read();
+            r_write_to_init_cmd_count        = r_write_word_count.read();
+
+            for(size_t i=0; i<m_words ; i++){
+              if(r_write_be[i].read())  r_write_to_init_cmd_we[i]=true;
+              else                      r_write_to_init_cmd_we[i]=false;
+            }
+
+            size_t min = r_write_word_index.read();
+            size_t max = r_write_word_index.read() + r_write_word_count.read();
+            for (size_t i=min ; i<max ; i++) {
+              r_write_to_init_cmd_data[i] = r_write_data[i];
+            }
+            
+            if( r_write_copy.read() != r_write_srcid.read() ) {
+              // We put the first copy in the fifo
+              write_to_init_cmd_fifo_put     = true;
+              write_to_init_cmd_fifo_inst    = r_write_copy_inst.read();
+              write_to_init_cmd_fifo_srcid   = r_write_copy.read();
+              if(r_write_count.read() == 1){
+                r_write_fsm = WRITE_IDLE;
+                r_write_to_init_cmd_multi_req = true;
+              } else {
+                r_write_fsm = WRITE_UPDATE;
+              }
+            } else {
+              r_write_fsm = WRITE_UPDATE;
+            }
+          }
+          break;
+        }
+        //////////////////
+      case WRITE_UPDATE:	// send a multi-update request to INIT_CMD fsm
+        {
+          assert( (r_alloc_heap_fsm.read() == ALLOC_HEAP_WRITE) &&
+                    "MemCache ERROR : bad HEAP allocation");
+          HeapEntry entry = m_heap_directory.read(r_write_ptr.read());
+          write_to_init_cmd_fifo_inst  = entry.owner.inst;
+          write_to_init_cmd_fifo_srcid = entry.owner.srcid;
+          bool dec_upt_counter = r_write_to_dec.read();
+          if( (entry.owner.srcid != r_write_srcid.read()) || entry.owner.inst ){
+            write_to_init_cmd_fifo_put = true;
+          } else {
+            dec_upt_counter = true;
+          }
+          r_write_to_dec = dec_upt_counter;
+
+          if( m_write_to_init_cmd_inst_fifo.wok() ){
+            r_write_ptr = entry.next;
+            if( entry.next == r_write_ptr.read() ) { // last copy
+              r_write_to_init_cmd_multi_req = true;
+              if(dec_upt_counter){
+                r_write_fsm = WRITE_UPT_DEC;
+              } else {
+                r_write_fsm = WRITE_IDLE;
+              }
+            } else {
+              r_write_fsm = WRITE_UPDATE;
+            }
+          } else {
+            r_write_fsm = WRITE_UPDATE;
+          }
+          break;
+        }
+        //////////////////
+      case WRITE_UPT_DEC:
+        {
+          if(!r_write_to_init_rsp_req.read()){
+            r_write_to_init_rsp_req = true;
+            r_write_to_init_rsp_upt_index = r_write_upt_index.read();
+            r_write_fsm = WRITE_IDLE;
+          }
+          break;
+        }
+        ///////////////
+      case WRITE_RSP:		// send a request to TGT_RSP FSM to acknowledge the write
+        {
+          if ( !r_write_to_tgt_rsp_req.read() ) {
+            r_write_to_tgt_rsp_req	    = true;
+            r_write_to_tgt_rsp_srcid	= r_write_srcid.read();
+            r_write_to_tgt_rsp_trdid	= r_write_trdid.read();
+            r_write_to_tgt_rsp_pktid	= r_write_pktid.read();
+            r_write_fsm 		        = WRITE_IDLE;
+          }
+          break;
+        }
+        ////////////////////
+      case WRITE_TRT_LOCK:	// Miss : check Transaction Table
+        {
+          if ( r_alloc_trt_fsm.read() == ALLOC_TRT_WRITE ) {
+#ifdef TDEBUG
+              TRACE_MSG(m_log << m_total_cycles << " " << name() << " READ_TRT_LOCK " << std::endl);
+#endif
+            size_t hit_index = 0;
+            size_t wok_index = 0;
+            bool hit_read    = m_transaction_tab.hit_read(m_nline[(vci_addr_t)(r_write_address.read())], hit_index);
+            bool hit_write   = m_transaction_tab.hit_write(m_nline[(vci_addr_t)(r_write_address.read())]);
+            bool wok         = !m_transaction_tab.full(wok_index);
+
+            if ( hit_read ) {	// register the modified data in TRT 
+              r_write_trt_index = hit_index;
+              r_write_fsm       = WRITE_TRT_DATA;
+            } else if ( wok && !hit_write ) {	// set a new entry in TRT
+              r_write_trt_index = wok_index;
+              r_write_fsm       = WRITE_TRT_SET;
+            } else {		    // wait an empty entry in TRT
+              r_write_fsm       = WRITE_WAIT;
+            }
+          }
+          break;
+        }
+        ////////////////////
+      case WRITE_WAIT:	// release the lock protecting TRT
+        { 
+          r_write_fsm = WRITE_DIR_LOCK;
+          break;
+        }
+        ///////////////////
+      case WRITE_TRT_SET:	// register a new transaction in TRT (Write Buffer)
+        {  
+          if ( r_alloc_trt_fsm.read() == ALLOC_TRT_WRITE ) 
+          {
+            std::vector<be_t> be_vector;
+            std::vector<data_t> data_vector;
+            be_vector.clear();
+            data_vector.clear();
+            for ( size_t i=0; i<m_words; i++ ) 
+            {
+              be_vector.push_back(r_write_be[i]);
+              data_vector.push_back(r_write_data[i]);
+            }
+            m_transaction_tab.set(r_write_trt_index.read(),
+                true,				// read request to XRAM
+                m_nline[(vci_addr_t)(r_write_address.read())],
+                r_write_srcid.read(),
+                r_write_trdid.read(),
+                r_write_pktid.read(),
+                false,				// not a processor read
+                0,  				// not a single word 
+                0,		        	// word index
+                be_vector,
+                data_vector);
+#ifdef TDEBUG
+            TRACE_MSG(m_log << m_total_cycles << " " << name() << " WRITE_TRT_SET transaction table : " << std::endl);
+            DUMP_TRANSACTION_TABLE;
+#endif
+
+            r_write_fsm = WRITE_XRAM_REQ;
+          }
+          break;
+        }  
+        ///////////////////
+      case WRITE_TRT_DATA:	// update an entry in TRT (Write Buffer)
+        { 
+          if ( r_alloc_trt_fsm.read() == ALLOC_TRT_WRITE ) {
+            std::vector<be_t> be_vector;
+            std::vector<data_t> data_vector;
+            be_vector.clear();
+            data_vector.clear();
+            for ( size_t i=0; i<m_words; i++ ) {
+              be_vector.push_back(r_write_be[i]);
+              data_vector.push_back(r_write_data[i]);
+            }
+            m_transaction_tab.write_data_mask(r_write_trt_index.read(),
+                be_vector,
+                data_vector);
+            r_write_fsm = WRITE_RSP;
+#ifdef TDEBUG
+            TRACE_MSG(m_log << m_total_cycles << " " << name() << " WRITE_TRT_DATA transaction table : " << std::endl);
+              
+            DUMP_TRANSACTION_TABLE;
+#endif
+
+          }
+          break;
+        }
+        ////////////////////
+      case WRITE_XRAM_REQ:	// send a request to IXR_CMD FSM
+        {  
+
+          if ( !r_write_to_ixr_cmd_req ) {
+            r_write_to_ixr_cmd_req   = true;
+            r_write_to_ixr_cmd_write = false;
+            r_write_to_ixr_cmd_nline = m_nline[(vci_addr_t)(r_write_address.read())];
+            r_write_to_ixr_cmd_trdid = r_write_trt_index.read();
+            r_write_fsm              = WRITE_RSP;
+          }
+          break;
+        }
+        ////////////////////
+      case WRITE_TRT_WRITE_LOCK:
+        {
+          if ( r_alloc_trt_fsm.read() == ALLOC_TRT_WRITE ) {
+            size_t wok_index = 0;
+            bool wok = !m_transaction_tab.full(wok_index);
+            if ( wok ) {	// set a new entry in TRT
+              r_write_trt_index = wok_index;
+              r_write_fsm       = WRITE_INVAL_LOCK;
+            } else {		// wait an empty entry in TRT
+              r_write_fsm       = WRITE_WAIT;
+            }
+          }
+
+          break;
+        }
+        ////////////////////
+      case WRITE_INVAL_LOCK:
+        {
+          if ( r_alloc_upt_fsm.read() == ALLOC_UPT_WRITE ) {
+            bool        wok       = false;
+            size_t      index     = 0;
+            size_t      srcid     = r_write_srcid.read();
+            size_t      trdid     = r_write_trdid.read();
+            size_t      pktid     = r_write_pktid.read();
+            addr_t	    nline     = m_nline[(vci_addr_t)(r_write_address.read())];
+            size_t      nb_copies = r_write_count.read();
+
+            wok =m_update_tab.set(false,	// it's an inval transaction
+                true,                       // it's a broadcast
+                true,                       // it needs a response
+                srcid,
+                trdid,
+                pktid,
+                nline,
+                nb_copies,
+                index);
+#ifdef IDEBUG
+            if(wok){
+       
+                TRACE_MSG(m_log << 
+                          m_total_cycles << " " << name() 
+                          << " WRITE_INVAL_LOCK update table : " 
+                          << std::endl);
+
+                DUMP_UPDATE_TABLE;   
+            }
+#endif
+            r_write_upt_index = index;
+            //  releases the lock protecting Update Table if no entry...
+            if ( wok ) r_write_fsm = WRITE_DIR_INVAL;
+            else       r_write_fsm = WRITE_WAIT;
+          }
+
+          break;
+        }
+        ////////////////////
+      case WRITE_DIR_INVAL:
+        {
+            assert(((r_alloc_trt_fsm.read() == ALLOC_TRT_WRITE ) &&
+                    (r_alloc_upt_fsm.read() == ALLOC_UPT_WRITE ) &&
+                    (r_alloc_dir_fsm.read() == ALLOC_DIR_WRITE ))&&
+                    "MemCache ERROR : bad TRT,DIR or UPT allocation error");
+            m_transaction_tab.set(r_write_trt_index.read(),
+                false,				// write request to XRAM
+                m_nline[(vci_addr_t)(r_write_address.read())],
+                0,
+                0,
+                0,
+                false,				// not a processor read
+                0,  				// not a single word 
+                0,		        	// word index
+                std::vector<be_t>(m_words,0),
+                std::vector<data_t>(m_words,0));
+#ifdef TDEBUG
+            TRACE_MSG(m_log << m_total_cycles 
+                      << " " << name() << " WRITE_DIR_INVAL transaction table : " << std::endl);
+
+            DUMP_TRANSACTION_TABLE;
+#endif
+
+            // invalidate directory entry
+            DirectoryEntry entry;
+            entry.valid	        = false;
+            entry.dirty	        = false;
+            entry.tag	        = 0;
+            entry.is_cnt        = false;
+            entry.lock          = false;
+            entry.inst          = false;
+            entry.owner.srcid   = 0;
+            entry.owner.inst    = false;
+            entry.ptr           = 0;
+            entry.count         = 0;
+            size_t set	        = m_y[(vci_addr_t)(r_write_address.read())];
+            size_t way	        = r_write_way.read();
+            m_cache_directory.write(set, way, entry);
+
+            r_write_fsm = WRITE_INVAL;
+            break;
+        }
+        ////////////////////
+      case WRITE_INVAL:
+        {
+          if (  !r_write_to_init_cmd_multi_req.read() &&
+                !r_write_to_init_cmd_brdcast_req.read() ) {
+            r_write_to_init_cmd_multi_req   = false;
+            r_write_to_init_cmd_brdcast_req = true;
+            r_write_to_init_cmd_trdid       = r_write_upt_index.read();
+            r_write_to_init_cmd_nline       = m_nline[(vci_addr_t)(r_write_address.read())];
+            r_write_to_init_cmd_index       = 0;
+            r_write_to_init_cmd_count       = 0;
+
+            for(size_t i=0; i<m_words ; i++){
+              r_write_to_init_cmd_we[i]=false;
+              r_write_to_init_cmd_data[i] = 0;
+            }
+            r_write_fsm = WRITE_XRAM_SEND;
+            // all inval responses
+          }
+
+          break;
+        }
+        ////////////////////
+      case WRITE_XRAM_SEND:
+        {
+          if ( !r_write_to_ixr_cmd_req ) {
+            r_write_to_ixr_cmd_req     = true;
+            r_write_to_ixr_cmd_write   = true;
+            r_write_to_ixr_cmd_nline   = m_nline[(vci_addr_t)(r_write_address.read())];
+            r_write_to_ixr_cmd_trdid   = r_write_trt_index.read();
+            for(size_t i=0; i<m_words; i++){
+              r_write_to_ixr_cmd_data[i] = r_write_data[i];
+            }
+            if(  r_write_is_cnt.read() ||
+                ((!r_write_is_cnt.read()) && (r_write_count.read()==1)) ){
+              r_write_fsm = WRITE_IDLE;
+            } else {
+              r_write_fsm = WRITE_HEAP_ERASE;
+              r_write_next_ptr = r_write_ptr.read();
+            }
+          }
+          break;
+        }
+        ////////////////////
+      case WRITE_HEAP_ERASE:
+        {
+          if(r_alloc_heap_fsm.read() == ALLOC_HEAP_WRITE){
+            HeapEntry next_entry = m_heap_directory.read(r_write_next_ptr.read());
+            if( next_entry.next == r_write_next_ptr.read()){
+              r_write_fsm = WRITE_HEAP_LAST;
+            } else {
+              r_write_next_ptr = next_entry.next;
+              r_write_fsm = WRITE_HEAP_ERASE;
+            }
+          }
+          break;
+        }
+        ////////////////////
+      case WRITE_HEAP_LAST:
+        {
+          assert((r_alloc_heap_fsm.read() == ALLOC_HEAP_WRITE) &&
+                  "MemCache ERROR : bad HEAP allocation");
+          size_t free_pointer = m_heap_directory.next_free_ptr();
+
+          HeapEntry last_entry;
+          last_entry.owner.srcid = 0;
+          last_entry.owner.inst  = false;
+          if(m_heap_directory.is_full()){
+            last_entry.next     = r_write_next_ptr.read();
+            m_heap_directory.unset_full();
+          } else {
+            last_entry.next     = free_pointer;
+          }
+
+          m_heap_directory.write_free_ptr(r_write_ptr.read());
+          m_heap_directory.write(r_write_next_ptr.read(),last_entry);
+
+          r_write_fsm = WRITE_IDLE;
+          break;
+        }
+    } // end switch r_write_fsm
+
+    ///////////////////////////////////////////////////////////////////////
+    //		IXR_CMD FSM
+    ///////////////////////////////////////////////////////////////////////
+    // The IXR_CMD fsm controls the command packets to the XRAM :
+    // - It sends a single cell VCI read to the XRAM in case of MISS request
+    // posted by the READ, WRITE or LLSC FSMs : the TRDID field contains 
+    // the Transaction Tab index.
+    // The VCI response is a multi-cell packet : the N cells contain
+    // the N data words.
+    // - It sends a multi-cell VCI write when the XRAM_RSP FSM request 
+    // to save a dirty line to the XRAM. 
+    // The VCI response is a single cell packet.
+    // This FSM handles requests from the READ, WRITE, LLSC & XRAM_RSP FSMs 
+    // with a round-robin priority.
+    ////////////////////////////////////////////////////////////////////////
+
+    switch ( r_ixr_cmd_fsm.read() ) {
+      //////////////////////// 
+      case IXR_CMD_READ_IDLE:
+        if      ( r_write_to_ixr_cmd_req )     r_ixr_cmd_fsm = IXR_CMD_WRITE_NLINE;
+        else if ( r_llsc_to_ixr_cmd_req  )     r_ixr_cmd_fsm = IXR_CMD_LLSC_NLINE;
+        else if ( r_xram_rsp_to_ixr_cmd_req  ) r_ixr_cmd_fsm = IXR_CMD_XRAM_DATA;
+        else if ( r_read_to_ixr_cmd_req  )     r_ixr_cmd_fsm = IXR_CMD_READ_NLINE;
+        break;
+        //////////////////////// 
+      case IXR_CMD_WRITE_IDLE:
+        if      ( r_llsc_to_ixr_cmd_req  )     r_ixr_cmd_fsm = IXR_CMD_LLSC_NLINE;
+        else if ( r_xram_rsp_to_ixr_cmd_req  ) r_ixr_cmd_fsm = IXR_CMD_XRAM_DATA;
+        else if ( r_read_to_ixr_cmd_req  )     r_ixr_cmd_fsm = IXR_CMD_READ_NLINE;
+        else if ( r_write_to_ixr_cmd_req )     r_ixr_cmd_fsm = IXR_CMD_WRITE_NLINE;
+        break;
+        //////////////////////// 
+      case IXR_CMD_LLSC_IDLE:
+        if      ( r_xram_rsp_to_ixr_cmd_req  ) r_ixr_cmd_fsm = IXR_CMD_XRAM_DATA;
+        else if ( r_read_to_ixr_cmd_req  )     r_ixr_cmd_fsm = IXR_CMD_READ_NLINE;
+        else if ( r_write_to_ixr_cmd_req )     r_ixr_cmd_fsm = IXR_CMD_WRITE_NLINE;
+        else if ( r_llsc_to_ixr_cmd_req  )     r_ixr_cmd_fsm = IXR_CMD_LLSC_NLINE;
+        break;
+        //////////////////////// 
+      case IXR_CMD_XRAM_IDLE:
+        if      ( r_read_to_ixr_cmd_req  )     r_ixr_cmd_fsm = IXR_CMD_READ_NLINE;
+        else if ( r_write_to_ixr_cmd_req )     r_ixr_cmd_fsm = IXR_CMD_WRITE_NLINE;
+        else if ( r_llsc_to_ixr_cmd_req  )     r_ixr_cmd_fsm = IXR_CMD_LLSC_NLINE;
+        else if ( r_xram_rsp_to_ixr_cmd_req  ) r_ixr_cmd_fsm = IXR_CMD_XRAM_DATA;
+        break;
+        /////////////////////////
+      case IXR_CMD_READ_NLINE:
+        if ( p_vci_ixr.cmdack ) {
+          r_ixr_cmd_fsm = IXR_CMD_READ_IDLE;		
+          r_read_to_ixr_cmd_req = false;
+        }
+        break;
+        //////////////////////////
+      case IXR_CMD_WRITE_NLINE:
+        if ( p_vci_ixr.cmdack ) {
+          if( r_write_to_ixr_cmd_write.read()){
+            if ( r_ixr_cmd_cpt.read() == (m_words - 1) ) {
+              r_ixr_cmd_cpt = 0;
+              r_ixr_cmd_fsm = IXR_CMD_WRITE_IDLE;
+              r_write_to_ixr_cmd_req = false;
+            } else {
+              r_ixr_cmd_cpt = r_ixr_cmd_cpt + 1;
+            }
+          } else {
+            r_ixr_cmd_fsm = IXR_CMD_WRITE_IDLE;		
+            r_write_to_ixr_cmd_req = false;
+          }
+        }
+        break;
+        /////////////////////////
+      case IXR_CMD_LLSC_NLINE:
+        if ( p_vci_ixr.cmdack ) {
+          if( r_llsc_to_ixr_cmd_write.read()){
+            if ( r_ixr_cmd_cpt.read() == (m_words - 1) ) {
+              r_ixr_cmd_cpt = 0;
+              r_ixr_cmd_fsm = IXR_CMD_LLSC_IDLE;
+              r_llsc_to_ixr_cmd_req = false;
+            } else {
+              r_ixr_cmd_cpt = r_ixr_cmd_cpt + 1;
+            }
+          } else {
+            r_ixr_cmd_fsm = IXR_CMD_LLSC_IDLE;		
+            r_llsc_to_ixr_cmd_req = false;
+          }
+        }
+        break;
+        ////////////////////////
+      case IXR_CMD_XRAM_DATA:
+        if ( p_vci_ixr.cmdack ) {
+          if ( r_ixr_cmd_cpt.read() == (m_words - 1) ) {
+            r_ixr_cmd_cpt = 0;
+            r_ixr_cmd_fsm = IXR_CMD_XRAM_IDLE;
+            r_xram_rsp_to_ixr_cmd_req = false;
+          } else {
+            r_ixr_cmd_cpt = r_ixr_cmd_cpt + 1;
+          }
+        }
+        break;
+
+    } // end switch r_ixr_cmd_fsm
+
+    ////////////////////////////////////////////////////////////////////////////
+    //                IXR_RSP FSM
+    ////////////////////////////////////////////////////////////////////////////
+    // The IXR_RSP FSM receives the response packets from the XRAM,
+    // for both write transaction, and read transaction.
+    //
+    // - A response to a write request is a single-cell VCI packet.
+    // The Transaction Tab index is contained in the RTRDID field.
+    // The FSM takes the lock protecting the TRT, and the corresponding
+    // entry is erased.
+    //	
+    // - A response to a read request is a multi-cell VCI packet.
+    // The Transaction Tab index is contained in the RTRDID field.
+    // The N cells contain the N words of the cache line in the RDATA field.
+    // The FSM takes the lock protecting the TRT to store the line in the TRT
+    // (taking into account the write requests already stored in the TRT).
+    // When the line is completely written, the corresponding rok signal is set.
+    ///////////////////////////////////////////////////////////////////////////////
+
+    switch ( r_ixr_rsp_fsm.read() ) {
+
+      ///////////////////
+      case IXR_RSP_IDLE:	// test if it's a read or a write transaction
+        {
+          if ( p_vci_ixr.rspval ) {
+            r_ixr_rsp_cpt   = 0;
+            r_ixr_rsp_trt_index = p_vci_ixr.rtrdid.read();
+            if ( p_vci_ixr.reop )  r_ixr_rsp_fsm = IXR_RSP_ACK;
+            else                   r_ixr_rsp_fsm = IXR_RSP_TRT_READ;
+          }
+          break;  
+        }
+        ////////////////////////
+      case IXR_RSP_ACK:        // Acknowledge the vci response
+        r_ixr_rsp_fsm = IXR_RSP_TRT_ERASE;
+        break;
+        ////////////////////////
+      case IXR_RSP_TRT_ERASE: 	// erase the entry in the TRT
+        {
+          if ( r_alloc_trt_fsm.read() == ALLOC_TRT_IXR_RSP ) {
+            m_transaction_tab.erase(r_ixr_rsp_trt_index.read());
+            r_ixr_rsp_fsm = IXR_RSP_IDLE;
+
+#ifdef TDEBUG            
+            TRACE_MSG(m_log << m_total_cycles << " " << name() << " IXR_RSP_TRT_ERASE transaction table : " << std::endl);
+            DUMP_TRANSACTION_TABLE;
+#endif
+
+          }
+          break;
+        }
+        ///////////////////////
+      case IXR_RSP_TRT_READ:		// write data in the TRT
+        {
+          if ( (r_alloc_trt_fsm.read() == ALLOC_TRT_IXR_RSP) &&  p_vci_ixr.rspval ) {
+            bool   eop  	= p_vci_ixr.reop.read();
+            data_t data 	= p_vci_ixr.rdata.read();
+            size_t index        = r_ixr_rsp_trt_index.read();
+            assert( eop == (r_ixr_rsp_cpt.read() == (m_words-1)) 
+                && "Error in VCI_MEM_CACHE : invalid length for a response from XRAM");
+
+
+            if(m_total_cycles > m_debug_start)
+            {
+                m_log << "[ " << std::dec << m_total_cycles << " ]"
+                      << " " << name() << " m_srcid_ini " << m_srcid_ini
+                      << " IXR_RSP_TRT_READ: calling write_rsp with [i:" 
+                      << index
+                      << ",cntr:"
+                      << r_ixr_rsp_cpt.read()
+                      << ",data:" << std::hex
+                      << data << "]" << std::dec << std::endl;
+            }
+
+            m_transaction_tab.write_rsp(index, r_ixr_rsp_cpt.read(), data);
+
+            if(m_total_cycles > m_debug_start)
+            {
+                m_log << std::dec << m_total_cycles
+                      << " " << name()
+                      << " Done" << std::endl;
+            }
+
+            r_ixr_rsp_cpt = r_ixr_rsp_cpt.read() + 1;
+
+            if ( eop ) {
+#ifdef TDEBUG
+                TRACE_MSG(m_log << m_total_cycles << " " << name() << " IXR_RSP_TRT_READ transaction table : " << std::endl);
+                DUMP_TRANSACTION_TABLE;
+#endif
+
+              r_ixr_rsp_to_xram_rsp_rok[r_ixr_rsp_trt_index.read()]=true;
+              r_ixr_rsp_fsm = IXR_RSP_IDLE;
+            }
+          }
+          break;
+        }
+    } // end swich r_ixr_rsp_fsm
+
+
+    ////////////////////////////////////////////////////////////////////////////
+    //                XRAM_RSP FSM
+    ////////////////////////////////////////////////////////////////////////////
+    // The XRAM_RSP FSM handles the incoming cache lines from the XRAM.
+    // The cache line has been written in the TRT buffer by the IXR_FSM.
+    //
+    // When a response is available, the corresponding TRT entry 
+    // is copied in a local buffer to be written in the cache. 
+    // Then, the FSM releases the lock protecting the TRT, and takes the lock 
+    // protecting the cache directory.
+    // It selects a cache slot and writes the line in the cache.
+    // If it was a read MISS, the XRAM_RSP FSM send a request to the TGT_RSP
+    // FSM to return the cache line to the registered processor.
+    // If there is no empty slot, a victim line is evicted, and
+    // invalidate requests are sent to the L1 caches containing copies.
+    // If this line is dirty, the XRAM_RSP FSM send a request to the IXR_CMD 
+    // FSM to save the victim line to the XRAM, and register the write transaction
+    // in the TRT (using the entry previously used by the read transaction).
+    ///////////////////////////////////////////////////////////////////////////////
+
+    switch ( r_xram_rsp_fsm.read() ) {
+
+      ///////////////////
+      case XRAM_RSP_IDLE:	// test if there is a response with a round robin priority
+        {
+          size_t ptr   = r_xram_rsp_trt_index.read();
+          size_t lines = TRANSACTION_TAB_LINES;
+          for(size_t i=0; i<lines; i++){
+            size_t index=(i+ptr+1)%lines;
+            if(r_ixr_rsp_to_xram_rsp_rok[index]){
+              r_xram_rsp_trt_index=index;
+              r_ixr_rsp_to_xram_rsp_rok[index]=false;
+              r_xram_rsp_fsm           = XRAM_RSP_DIR_LOCK;
+              break;
+
+#ifdef TDEBUG
+              TRACE_MSG(m_log << "XRAM_RSP FSM in XRAM_RSP_IDLE state" << std::endl);
+#endif
+            }
+          }
+          break;  
+        }
+        ///////////////////////
+      case XRAM_RSP_DIR_LOCK: 	// Take the lock on the directory
+        {
+          if( r_alloc_dir_fsm.read() == ALLOC_DIR_XRAM_RSP ) {
+            r_xram_rsp_fsm           = XRAM_RSP_TRT_COPY;
+#ifdef TDEBUG
+            TRACE_MSG(m_log << "XRAM_RSP FSM in XRAM_RSP_DIR_LOCK state" << std::endl);
+#endif
+          }
+          break;
+        }
+        ///////////////////////
+      case XRAM_RSP_TRT_COPY:		// Copy the TRT entry in the local buffer and eviction of a cache line
+        {
+          if ( (r_alloc_trt_fsm.read() == ALLOC_TRT_XRAM_RSP) ) {
+            size_t index = r_xram_rsp_trt_index.read();
+            TransactionTabEntry    trt_entry(m_transaction_tab.read(index));	
+
+            r_xram_rsp_trt_buf.copy(trt_entry);  // TRT entry local buffer
+
+            // selects & extracts a victim line from cache
+            size_t way = 0;
+            size_t set = m_y[(vci_addr_t)(trt_entry.nline * m_words * 4)];
+            DirectoryEntry victim(m_cache_directory.select(set, way));
+
+            for (size_t i=0 ; i<m_words ; i++) r_xram_rsp_victim_data[i] = m_cache_data[way][set][i];
+
+            bool inval = (victim.count && victim.valid) ;
+
+            r_xram_rsp_victim_copy      = victim.owner.srcid;
+            r_xram_rsp_victim_copy_inst = victim.owner.inst;
+            r_xram_rsp_victim_count     = victim.count;
+            r_xram_rsp_victim_ptr       = victim.ptr;
+            r_xram_rsp_victim_way       = way;
+            r_xram_rsp_victim_set       = set;
+            r_xram_rsp_victim_nline     = victim.tag*m_sets + set;
+            r_xram_rsp_victim_is_cnt    = victim.is_cnt;
+            r_xram_rsp_victim_inval     = inval ;
+            r_xram_rsp_victim_dirty     = victim.dirty;
+
+            r_xram_rsp_fsm = XRAM_RSP_INVAL_LOCK;
+
+#ifdef TDEBUG
+            TRACE_MSG(m_log << "XRAM_RSP FSM in XRAM_RSP_TRT_COPY state" << std::endl);
+            TRACE_MSG(m_log << "Victim way : " << std::hex << way << " set " << std::hex << set << std::endl);
+            DUMP_ENTRY(victim);
+#endif
+          }
+          break;
+        }
+        ///////////////////////
+      case XRAM_RSP_INVAL_LOCK:
+        {
+          if ( r_alloc_upt_fsm == ALLOC_UPT_XRAM_RSP ) 
+          {
+
+#ifdef IDEBUG
+              TRACE_MSG(m_log << "XRAM_RSP FSM in XRAM_RSP_INVAL_LOCK state, line = " 
+                        << std::hex << r_xram_rsp_trt_buf.nline
+                        << std::endl);
+#endif
+              size_t index;
+              
+              if(m_update_tab.search_inval(r_xram_rsp_trt_buf.nline, index))
+              {
+                  r_xram_rsp_fsm = XRAM_RSP_INVAL_WAIT;
+                  
+#ifdef IDEBUG
+                  TRACE_MSG(m_log << "XRAM_RSP FSM in XRAM_RSP_INVAL_LOCK state to XRAM_RSP_INVAL_WAIT state" << std::endl);
+                  TRACE_MSG(m_log << "A invalidation is already registered at this address" << std::endl);
+                  
+                  DUMP_UPDATE_TABLE;
+#endif
+              }
+              else if(m_update_tab.is_full() && r_xram_rsp_victim_inval.read())
+              {
+                  r_xram_rsp_fsm = XRAM_RSP_INVAL_WAIT;
+                  
+#ifdef IDEBUG
+                  TRACE_MSG(m_log << "XRAM_RSP FSM in XRAM_RSP_INVAL_LOCK state to XRAM_RSP_INVAL_WAIT state" << std::endl);
+                  TRACE_MSG(m_log << "The inval tab is full" << std::endl);
+
+                  DUMP_UPDATE_TABLE;
+#endif
+              }
+              else 
+              {
+                  r_xram_rsp_fsm = XRAM_RSP_DIR_UPDT;
+#ifdef IDEBUG
+                  TRACE_MSG(m_log << "XRAM_RSP FSM in XRAM_RSP_INVAL_LOCK state to XRAM_RSP_DIR_UPDT state" << std::endl);
+                  DUMP_UPDATE_TABLE;
+#endif
+              }
+          }
+          break;
+        }
+        ///////////////////////
+      case XRAM_RSP_INVAL_WAIT:
+        {
+          r_xram_rsp_fsm = XRAM_RSP_DIR_LOCK;
+#ifdef IDEBUG
+          TRACE_MSG(m_log << "XRAM_RSP FSM in XRAM_RSP_INVAL_WAIT state" << std::endl);
+#endif
+          break;
+        }
+        ///////////////////////
+      case XRAM_RSP_DIR_UPDT:		// updates the cache (both data & directory)
+        {
+          // signals generation
+          bool inst_read = (r_xram_rsp_trt_buf.trdid & 0x2) && r_xram_rsp_trt_buf.proc_read; // It is an instruction read
+          bool cached_read = (r_xram_rsp_trt_buf.trdid & 0x1) && r_xram_rsp_trt_buf.proc_read ;
+          // update data
+          size_t set   = r_xram_rsp_victim_set.read();
+          size_t way   = r_xram_rsp_victim_way.read();
+          for(size_t i=0; i<m_words ; i++){
+            m_cache_data[way][set][i] = r_xram_rsp_trt_buf.wdata[i];
+          }
+          // compute dirty 
+          bool dirty = false;
+          for(size_t i=0; i<m_words;i++){
+            dirty = dirty || (r_xram_rsp_trt_buf.wdata_be[i] != 0);
+          }
+
+          // update directory
+          DirectoryEntry entry;
+          entry.valid	  = true;
+          entry.is_cnt    = false;
+          entry.lock	  = false;
+          entry.dirty	  = dirty;
+          entry.tag	      = r_xram_rsp_trt_buf.nline / m_sets;
+          entry.ptr       = 0;
+          if(cached_read) {
+            if(inst_read) {
+              entry.inst        = true;
+              entry.owner.srcid = r_xram_rsp_trt_buf.srcid;
+              entry.owner.inst  = true;
+              entry.count       = 1;
+            } else {
+              entry.inst        = false;
+              entry.owner.srcid = r_xram_rsp_trt_buf.srcid;
+              entry.owner.inst  = false;
+              entry.count       = 1;
+            }
+          } else {
+            entry.owner.srcid = 0;
+            entry.owner.inst  = 0;
+            entry.inst        = false;
+            entry.count       = 0;
+          }
+          m_cache_directory.write(set, way, entry);
+#ifdef DDEBUG
+          TRACE_MSG(m_log << "printing the entry : " << std::endl);
+          DUMP_ENTRY(entry);
+          TRACE_MSG(m_log << "done" << std::endl);
+#endif
+
+#ifdef TDEBUG
+          TRACE_MSG(m_log << m_total_cycles << " " << name() << " XRAM_RSP_DIR_UPDT transaction table : " << std::endl);
+          DUMP_TRANSACTION_TABLE;
+#endif
+
+          if(r_xram_rsp_victim_inval.read()){
+            bool    brdcast = r_xram_rsp_victim_is_cnt.read();
+            size_t index;
+            size_t count_copies = r_xram_rsp_victim_count.read();
+
+            bool	 wok = m_update_tab.set(false,	// it's an inval transaction
+                                            brdcast,                          // set brdcast bit
+                                            false,  // it does not need a response
+                                            0,
+                                            0,
+                                            0,
+                                            r_xram_rsp_victim_nline.read(),
+                                            count_copies,
+                                            index);
+
+#ifdef IDEBUG
+            TRACE_MSG(m_log << "xram_rsp : record invalidation, time = " << std::dec << m_cpt_cycles << std::endl);
+            
+            DUMP_UPDATE_TABLE;
+#endif
+            r_xram_rsp_upt_index = index;
+            if(!wok) {
+              assert(false && "mem_cache error : xram_rsp_dir_upt, an update_tab entry was free but write unsuccessful");
+            }
+          }
+          // If the victim is not dirty, we erase the entry in the TRT
+          if      (!r_xram_rsp_victim_dirty.read()){
+              m_transaction_tab.erase(r_xram_rsp_trt_index.read());
+
+	  }
+          // Next state
+          if      ( r_xram_rsp_victim_dirty.read())       r_xram_rsp_fsm = XRAM_RSP_TRT_DIRTY;
+          else if ( r_xram_rsp_trt_buf.proc_read  )       r_xram_rsp_fsm = XRAM_RSP_DIR_RSP;
+          else if ( r_xram_rsp_victim_inval.read())       r_xram_rsp_fsm = XRAM_RSP_INVAL;
+          else                                            r_xram_rsp_fsm = XRAM_RSP_IDLE;
+          break;
+        }
+        ////////////////////////
+      case XRAM_RSP_TRT_DIRTY:		// set the TRT entry (write line to XRAM) if the victim is dirty
+        {
+          if ( r_alloc_trt_fsm.read() == ALLOC_TRT_XRAM_RSP ) {
+            m_transaction_tab.set(r_xram_rsp_trt_index.read(),
+                false,				// write to XRAM
+                r_xram_rsp_victim_nline.read(), // line index
+                0,
+                0,
+                0,
+                false,
+                0,
+                0,
+                std::vector<be_t>(m_words,0),
+                std::vector<data_t>(m_words,0) );
+#ifdef TDEBUG
+            TRACE_MSG(m_log << m_total_cycles << " " << name() << " XRAM_RSP_TRT_DIRTY transaction table : " << std::endl);
+            DUMP_TRANSACTION_TABLE;
+#endif
+
+            if      ( r_xram_rsp_trt_buf.proc_read  )       r_xram_rsp_fsm = XRAM_RSP_DIR_RSP;
+            else if ( r_xram_rsp_victim_inval.read())       r_xram_rsp_fsm = XRAM_RSP_INVAL;
+            else                                            r_xram_rsp_fsm = XRAM_RSP_WRITE_DIRTY;
+          }
+          break;
+        }
+        //////////////////////
+      case XRAM_RSP_DIR_RSP:     // send a request to TGT_RSP FSM in case of read
+        {
+          if ( !r_xram_rsp_to_tgt_rsp_req.read() ) {
+            r_xram_rsp_to_tgt_rsp_srcid = r_xram_rsp_trt_buf.srcid;
+            r_xram_rsp_to_tgt_rsp_trdid = r_xram_rsp_trt_buf.trdid;
+            r_xram_rsp_to_tgt_rsp_pktid = r_xram_rsp_trt_buf.pktid;
+            for (size_t i=0; i < m_words; i++) {
+              r_xram_rsp_to_tgt_rsp_data[i] = r_xram_rsp_trt_buf.wdata[i];
+            } 
+            r_xram_rsp_to_tgt_rsp_word   = r_xram_rsp_trt_buf.word_index;
+            r_xram_rsp_to_tgt_rsp_length = r_xram_rsp_trt_buf.read_length;
+            r_xram_rsp_to_tgt_rsp_req    = true;
+
+            if      ( r_xram_rsp_victim_inval ) r_xram_rsp_fsm = XRAM_RSP_INVAL;
+            else if ( r_xram_rsp_victim_dirty ) r_xram_rsp_fsm = XRAM_RSP_WRITE_DIRTY; 
+            else                                r_xram_rsp_fsm = XRAM_RSP_IDLE;
+
+#ifdef DDEBUG
+            TRACE_MSG(m_log << "XRAM_RSP FSM in XRAM_RSP_DIR_RSP state" << std::endl);
+#endif
+          }
+          break;
+        }
+        ////////////////////
+      case XRAM_RSP_INVAL:	// send invalidate request to INIT_CMD FSM
+        {
+          if(   !r_xram_rsp_to_init_cmd_multi_req.read() && 
+                !r_xram_rsp_to_init_cmd_brdcast_req.read() ) {	      
+            
+            bool multi_req = !r_xram_rsp_victim_is_cnt.read();
+            bool last_multi_req  = multi_req && (r_xram_rsp_victim_count.read() == 1);
+            bool not_last_multi_req = multi_req && (r_xram_rsp_victim_count.read() != 1);
+
+            r_xram_rsp_to_init_cmd_multi_req    = last_multi_req; 
+            r_xram_rsp_to_init_cmd_brdcast_req  = r_xram_rsp_victim_is_cnt.read();
+            r_xram_rsp_to_init_cmd_nline        = r_xram_rsp_victim_nline.read();
+            r_xram_rsp_to_init_cmd_trdid        = r_xram_rsp_upt_index;
+            xram_rsp_to_init_cmd_fifo_srcid     = r_xram_rsp_victim_copy.read();
+            xram_rsp_to_init_cmd_fifo_inst      = r_xram_rsp_victim_copy_inst.read();
+            xram_rsp_to_init_cmd_fifo_put       = multi_req;
+            
+            r_xram_rsp_next_ptr                 = r_xram_rsp_victim_ptr.read();
+
+            if ( r_xram_rsp_victim_dirty )  r_xram_rsp_fsm = XRAM_RSP_WRITE_DIRTY;
+            else if (not_last_multi_req)    r_xram_rsp_fsm = XRAM_RSP_HEAP_ERASE;
+            else                            r_xram_rsp_fsm = XRAM_RSP_IDLE;
+#ifdef IDEBUG
+            TRACE_MSG(m_log << "XRAM_RSP FSM in XRAM_RSP_INVAL state" << std::endl);
+#endif
+          }
+          break;
+        }
+        //////////////////////////
+      case XRAM_RSP_WRITE_DIRTY:	// send a write request to IXR_CMD FSM
+        {
+          if ( !r_xram_rsp_to_ixr_cmd_req.read() ) {
+            r_xram_rsp_to_ixr_cmd_req = true;
+            r_xram_rsp_to_ixr_cmd_nline = r_xram_rsp_victim_nline.read();
+            r_xram_rsp_to_ixr_cmd_trdid = r_xram_rsp_trt_index.read();
+            for(size_t i=0; i<m_words ; i++) {
+              r_xram_rsp_to_ixr_cmd_data[i] = r_xram_rsp_victim_data[i];
+            }
+            m_cpt_write_dirty++;
+            bool multi_req = !r_xram_rsp_victim_is_cnt.read() && r_xram_rsp_victim_inval.read();
+            bool not_last_multi_req = multi_req && (r_xram_rsp_victim_count.read() != 1);
+            if ( not_last_multi_req )   r_xram_rsp_fsm = XRAM_RSP_HEAP_ERASE;
+            else                        r_xram_rsp_fsm = XRAM_RSP_IDLE;
+#ifdef TDEBUG
+            TRACE_MSG(m_log << "XRAM_RSP FSM in XRAM_RSP_WRITE_DIRTY state" << std::endl);
+#endif
+          }
+          break;
+        }
+        //////////////////////////
+      case XRAM_RSP_HEAP_ERASE:	// erase the list of copies and sent invalidations
+        {
+          if( r_alloc_heap_fsm.read() == ALLOC_HEAP_XRAM_RSP ) {
+            HeapEntry entry = m_heap_directory.read(r_xram_rsp_next_ptr.read());
+            xram_rsp_to_init_cmd_fifo_srcid = entry.owner.srcid;
+            xram_rsp_to_init_cmd_fifo_inst  = entry.owner.inst;
+            xram_rsp_to_init_cmd_fifo_put   = true;
+            if( m_xram_rsp_to_init_cmd_inst_fifo.wok() ){
+              r_xram_rsp_next_ptr = entry.next;
+              if( entry.next == r_xram_rsp_next_ptr.read() ){ // last copy
+                r_xram_rsp_to_init_cmd_multi_req = true;
+                r_xram_rsp_fsm = XRAM_RSP_HEAP_LAST;
+              } else {
+                r_xram_rsp_fsm = XRAM_RSP_HEAP_ERASE;
+              }
+            } else {
+              r_xram_rsp_fsm = XRAM_RSP_HEAP_ERASE;
+            }
+          }
+          break;
+        }
+        //////////////////////////
+      case XRAM_RSP_HEAP_LAST:	// last member of the list
+        {
+          assert((r_alloc_heap_fsm.read() == ALLOC_HEAP_XRAM_RSP) &&
+                  "MemCache ERROR : bad HEAP allocation");
+          size_t free_pointer = m_heap_directory.next_free_ptr();
+
+          HeapEntry last_entry;
+          last_entry.owner.srcid = 0;
+          last_entry.owner.inst  = false;
+          if(m_heap_directory.is_full()){
+            last_entry.next     = r_xram_rsp_next_ptr.read();
+            m_heap_directory.unset_full();
+          } else {
+            last_entry.next     = free_pointer;
+          }
+
+          m_heap_directory.write_free_ptr(r_xram_rsp_victim_ptr.read());
+          m_heap_directory.write(r_xram_rsp_next_ptr.read(),last_entry);
+
+          r_xram_rsp_fsm = XRAM_RSP_IDLE;
+
+          break;
+        }
+    } // end swich r_xram_rsp_fsm
+
+    ////////////////////////////////////////////////////////////////////////////////////
+    //		CLEANUP FSM
+    ////////////////////////////////////////////////////////////////////////////////////
+    // The CLEANUP FSM handles the cleanup request from L1 caches.
+    // It accesses the cache directory to update the list of copies.
+    //
+    ////////////////////////////////////////////////////////////////////////////////////
+    switch ( r_cleanup_fsm.read() ) {
+
+      ///////////////////
+      case CLEANUP_IDLE:
+        {
+
+          if ( p_vci_tgt_cleanup.cmdval.read() ) {
+            assert( (p_vci_tgt_cleanup.srcid.read() < m_initiators) &&
+                "VCI_MEM_CACHE error in VCI_MEM_CACHE in the CLEANUP network : The received SRCID is larger than the number of initiators");
+            bool reached = false;
+            for ( size_t index = 0 ; index < ncseg && !reached ; index++ ){
+              if ( m_cseg[index]->contains((addr_t)(p_vci_tgt_cleanup.address.read())) ){
+                reached = true;
+              }
+            }
+            if ( (p_vci_tgt_cleanup.cmd.read() == vci_param::CMD_WRITE) &&
+                (((addr_t)(p_vci_tgt_cleanup.address.read())&0x3) != 0x3) &&
+                reached) {
+
+              m_cpt_cleanup++;
+
+              r_cleanup_nline      = (addr_t)(m_nline[(vci_addr_t)(p_vci_tgt_cleanup.address.read())]) ;
+              r_cleanup_srcid      = p_vci_tgt_cleanup.srcid.read();
+              r_cleanup_trdid      = p_vci_tgt_cleanup.trdid.read();
+              r_cleanup_pktid      = p_vci_tgt_cleanup.pktid.read();
+
+              r_cleanup_fsm        = CLEANUP_DIR_LOCK;
+            }
+          }
+          break;
+        }
+        //////////////////////
+      case CLEANUP_DIR_LOCK:
+        {
+          if ( r_alloc_dir_fsm.read() == ALLOC_DIR_CLEANUP ) {
+
+            // Read the directory
+            size_t way = 0;
+	   addr_t cleanup_address = r_cleanup_nline.read() * m_words * 4;
+           DirectoryEntry entry = m_cache_directory.read(cleanup_address , way);
+#ifdef DDEBUG
+           TRACE_MSG(m_log << "In CLEANUP_DIR_LOCK printing the entry of address is : " << std::hex << cleanup_address << std::endl);
+           DUMP_ENTRY(entry);
+           TRACE_MSG(m_log << "done" << std::endl);
+#endif
+            r_cleanup_is_cnt    = entry.is_cnt;
+            r_cleanup_dirty	    = entry.dirty;
+            r_cleanup_tag	    = entry.tag;
+            r_cleanup_lock	    = entry.lock;
+            r_cleanup_inst      = entry.inst;
+            r_cleanup_way	    = way;
+            r_cleanup_copy      = entry.owner.srcid;
+            r_cleanup_copy_inst = entry.owner.inst;
+            r_cleanup_count     = entry.count;
+            r_cleanup_ptr       = entry.ptr;
+
+
+            // In case of hit, the copy must be cleaned in the copies bit-vector
+            if( entry.valid){
+              if ( (entry.count==1) || (entry.is_cnt) )  { // no access to the heap
+                r_cleanup_fsm = CLEANUP_DIR_WRITE;
+              } else {
+                r_cleanup_fsm = CLEANUP_HEAP_LOCK;
+              }
+            } else {
+              r_cleanup_fsm = CLEANUP_UPT_LOCK;
+            }
+          }
+          break;
+        }
+        ///////////////////////
+      case CLEANUP_DIR_WRITE:
+        {
+          assert( (r_alloc_dir_fsm.read() == ALLOC_DIR_CLEANUP ) && 
+                "MemCache ERROR : Bad DIR allocation");
+          size_t way      = r_cleanup_way.read();
+#define L2 soclib::common::uint32_log2
+          size_t set      = m_y[(vci_addr_t)(r_cleanup_nline.read() << (L2(m_words) +2))];
+#undef L2
+          bool cleanup_inst  = r_cleanup_trdid.read() & 0x1; 
+          bool match_srcid   = (r_cleanup_copy.read() == r_cleanup_srcid.read());
+          bool match_inst    = (r_cleanup_copy_inst.read()  == cleanup_inst);
+          bool match         = match_srcid && match_inst;
+
+          // update the cache directory (for the copies)
+          DirectoryEntry entry;
+          entry.valid	= true;
+          entry.is_cnt  = r_cleanup_is_cnt.read();
+          entry.dirty	= r_cleanup_dirty.read();
+          entry.tag	    = r_cleanup_tag.read();
+          entry.lock	= r_cleanup_lock.read();
+          entry.ptr     = r_cleanup_ptr.read();
+          if(r_cleanup_is_cnt.read()) { // Directory is a counter
+            entry.count  = r_cleanup_count.read() -1;
+            if((r_cleanup_count.read()-1) == 0){
+              entry.inst    = false;
+            } else {
+              entry.inst    = r_cleanup_inst.read();
+            }
+            entry.owner.srcid = 0;
+            entry.owner.inst  = 0;
+            // response to the cache 
+            r_cleanup_fsm = CLEANUP_RSP;
+          }
+          else{                         // Directory is a list
+            if(match) { // hit
+              entry.count       = 0; // no more copy
+              entry.owner.srcid = 0;
+              entry.owner.inst  = 0;
+              entry.inst        = false;
+              r_cleanup_fsm     = CLEANUP_RSP; 
+            } else { // miss
+              entry.count       = r_cleanup_count.read();
+              entry.owner.srcid = r_cleanup_copy.read();
+              entry.owner.inst  = r_cleanup_copy_inst.read();
+              entry.inst        = r_cleanup_inst.read();
+              r_cleanup_fsm     = CLEANUP_UPT_LOCK;
+            }
+          }
+          m_cache_directory.write(set, way, entry);  
+
+          break;
+        }
+        /////////////////
+      case CLEANUP_HEAP_LOCK:
+        {
+          if(r_alloc_heap_fsm.read() == ALLOC_HEAP_CLEANUP){
+            size_t way      = r_cleanup_way.read();
+#define L2 soclib::common::uint32_log2
+            size_t set      = m_y[(vci_addr_t)(r_cleanup_nline.read() << (L2(m_words) +2))];
+#undef L2
+            HeapEntry heap_entry = m_heap_directory.read(r_cleanup_ptr.read());
+            bool last = (heap_entry.next == r_cleanup_ptr.read());
+            bool cleanup_inst       = r_cleanup_trdid.read() & 0x1; 
+            bool match_dir_srcid    = (r_cleanup_copy.read() == r_cleanup_srcid.read());
+            bool match_dir_inst     = (r_cleanup_copy_inst.read()  == cleanup_inst);
+            bool match_dir          = match_dir_srcid && match_dir_inst;
+            bool match_heap_srcid   = (heap_entry.owner.srcid == r_cleanup_srcid.read());
+            bool match_heap_inst    = (heap_entry.owner.inst  == cleanup_inst);
+            bool match_heap         = match_heap_srcid && match_heap_inst;
+
+            r_cleanup_prev_ptr = r_cleanup_ptr.read();
+            r_cleanup_prev_srcid = heap_entry.owner.srcid;
+            r_cleanup_prev_inst  = heap_entry.owner.inst;
+
+            if(match_dir){
+              DirectoryEntry dir_entry;
+              dir_entry.valid	    = true;
+              dir_entry.is_cnt      = r_cleanup_is_cnt.read();
+              dir_entry.dirty	    = r_cleanup_dirty.read();
+              dir_entry.tag	        = r_cleanup_tag.read();
+              dir_entry.lock	    = r_cleanup_lock.read();
+              dir_entry.ptr         = heap_entry.next;
+              dir_entry.count       = r_cleanup_count.read()-1;
+              dir_entry.owner.srcid = heap_entry.owner.srcid;
+              dir_entry.owner.inst  = heap_entry.owner.inst;
+              dir_entry.inst        = r_cleanup_inst.read();
+              m_cache_directory.write(set,way,dir_entry);
+              r_cleanup_next_ptr    = r_cleanup_ptr.read();
+              r_cleanup_fsm         = CLEANUP_HEAP_FREE;
+            }
+            else if(match_heap){
+              DirectoryEntry dir_entry;
+              dir_entry.valid	    = true;
+              dir_entry.is_cnt      = r_cleanup_is_cnt.read();
+              dir_entry.dirty	    = r_cleanup_dirty.read();
+              dir_entry.tag	        = r_cleanup_tag.read();
+              dir_entry.lock	    = r_cleanup_lock.read();
+              dir_entry.ptr         = heap_entry.next;
+              dir_entry.count       = r_cleanup_count.read()-1;
+              dir_entry.owner.srcid = r_cleanup_copy.read();
+              dir_entry.owner.inst  = r_cleanup_copy_inst.read();
+              dir_entry.inst        = r_cleanup_inst.read();
+              m_cache_directory.write(set,way,dir_entry);
+              r_cleanup_next_ptr    = r_cleanup_ptr.read();
+              r_cleanup_fsm         = CLEANUP_HEAP_FREE; 
+            }
+            else{
+              if(!last){
+                DirectoryEntry dir_entry;
+                dir_entry.valid	        = true;
+                dir_entry.is_cnt        = r_cleanup_is_cnt.read();
+                dir_entry.dirty	        = r_cleanup_dirty.read();
+                dir_entry.tag	        = r_cleanup_tag.read();
+                dir_entry.lock	        = r_cleanup_lock.read();
+                dir_entry.ptr           = r_cleanup_ptr.read();
+                dir_entry.count         = r_cleanup_count.read()-1;
+                dir_entry.owner.srcid   = r_cleanup_copy.read();
+                dir_entry.owner.inst    = r_cleanup_copy_inst.read();
+                dir_entry.inst          = r_cleanup_inst.read();
+                m_cache_directory.write(set,way,dir_entry);
+
+                r_cleanup_next_ptr = heap_entry.next;
+                r_cleanup_fsm      = CLEANUP_HEAP_SEARCH;
+
+              } else{
+                assert(false && "MemCache ERROR : CLEANUP hit but line not shared");
+              }
+            }
+          }
+          break;
+        }
+        /////////////////
+      case CLEANUP_HEAP_SEARCH:
+        {
+          assert( (r_alloc_heap_fsm.read() == ALLOC_HEAP_CLEANUP) &&
+                    "MemCache ERROR : bad HEAP allocation");
+          HeapEntry heap_entry = m_heap_directory.read(r_cleanup_next_ptr.read());
+          bool last = (heap_entry.next == r_cleanup_next_ptr.read());
+          bool cleanup_inst       = r_cleanup_trdid.read() & 0x1; 
+          bool match_heap_srcid   = (heap_entry.owner.srcid == r_cleanup_srcid.read());
+          bool match_heap_inst    = (heap_entry.owner.inst  == cleanup_inst);
+          bool match_heap         = match_heap_srcid && match_heap_inst;
+
+          if(match_heap){
+            r_cleanup_ptr           = heap_entry.next; // reuse ressources
+            r_cleanup_fsm = CLEANUP_HEAP_CLEAN;
+          }
+          else{
+            if(last) {
+              assert(false && "MemCache ERROR : CLEANUP hit but line not shared");
+            } else {
+              r_cleanup_prev_ptr = r_cleanup_next_ptr.read();
+              r_cleanup_prev_srcid = heap_entry.owner.srcid;
+              r_cleanup_prev_inst  = heap_entry.owner.inst;
+              r_cleanup_next_ptr = heap_entry.next;
+              r_cleanup_fsm      = CLEANUP_HEAP_SEARCH;
+            }
+          }
+
+          break;
+        }
+        /////////////////
+      case CLEANUP_HEAP_CLEAN:
+        {
+          assert( (r_alloc_heap_fsm.read() == ALLOC_HEAP_CLEANUP) &&
+                    "MemCache ERROR : bad HEAP allocation");
+          bool last = (r_cleanup_next_ptr.read() == r_cleanup_ptr.read());
+          HeapEntry heap_entry; 
+          heap_entry.owner.srcid = r_cleanup_prev_srcid.read();
+          heap_entry.owner.inst  = r_cleanup_prev_inst.read();
+          if(last){ // this is the last entry of the list of copies
+            heap_entry.next     = r_cleanup_prev_ptr.read();
+          } else { // this is not the last entry
+            heap_entry.next     = r_cleanup_ptr.read();
+          }
+          m_heap_directory.write(r_cleanup_prev_ptr.read(),heap_entry);
+          r_cleanup_fsm = CLEANUP_HEAP_FREE;
+          break;
+        }
+        /////////////////
+      case CLEANUP_HEAP_FREE:
+        {
+          assert( (r_alloc_heap_fsm.read() == ALLOC_HEAP_CLEANUP) &&
+                    "MemCache ERROR : bad HEAP allocation");
+          HeapEntry heap_entry;
+          heap_entry.owner.srcid = 0;
+          heap_entry.owner.inst  = false;
+          if(m_heap_directory.is_full()){
+            heap_entry.next     = r_cleanup_next_ptr.read();
+          } else {
+            heap_entry.next     = m_heap_directory.next_free_ptr();
+          }
+          m_heap_directory.write(r_cleanup_next_ptr.read(),heap_entry);
+          m_heap_directory.write_free_ptr(r_cleanup_next_ptr.read());
+          m_heap_directory.unset_full();
+          r_cleanup_fsm = CLEANUP_RSP;
+          break;
+        }
+        /////////////////
+      case CLEANUP_UPT_LOCK:
+        {
+          if( r_alloc_upt_fsm.read() == ALLOC_UPT_CLEANUP )
+          {
+            size_t index;
+            bool hit_inval;
+            hit_inval = m_update_tab.search_inval(r_cleanup_nline.read(),index);
+            if(!hit_inval) {
+#ifdef DEBUG_VCI_MEM_CACHE
+                TRACE_MSG(m_log << "MEM_CACHE WARNING: cleanup with no corresponding entry at address : " << std::hex << (r_cleanup_nline.read()*4*m_words) << std::dec << std::endl);
+#endif
+              r_cleanup_fsm = CLEANUP_RSP;
+            } else {
+              r_cleanup_write_srcid = m_update_tab.srcid(index);
+              r_cleanup_write_trdid = m_update_tab.trdid(index);
+              r_cleanup_write_pktid = m_update_tab.pktid(index);
+              r_cleanup_need_rsp    = m_update_tab.need_rsp(index);
+              r_cleanup_fsm = CLEANUP_UPT_WRITE;
+            }
+            r_cleanup_index.write(index) ; 
+          }
+          break;
+        }
+        /////////////////
+      case CLEANUP_UPT_WRITE:
+        {
+          size_t count = 0;
+          m_update_tab.decrement(r_cleanup_index.read(), count); // &count
+          if(count == 0){
+            m_update_tab.clear(r_cleanup_index.read());
+#ifdef IDEBUG
+            TRACE_MSG(m_log << m_total_cycles << " " << name() << " CLEANUP_UPT_WRITE update table : " << std::endl);
+            DUMP_UPDATE_TABLE;
+#endif
+
+            if(r_cleanup_need_rsp.read()){
+              r_cleanup_fsm = CLEANUP_WRITE_RSP ;
+            } else {
+              r_cleanup_fsm = CLEANUP_RSP;
+            }
+          } else {
+            r_cleanup_fsm = CLEANUP_RSP ;
+          }
+          break;
+        }
+        /////////////////
+      case CLEANUP_WRITE_RSP:
+        {
+          if( !r_cleanup_to_tgt_rsp_req.read()) {
+            r_cleanup_to_tgt_rsp_req     = true;
+            r_cleanup_to_tgt_rsp_srcid   = r_cleanup_write_srcid.read();
+            r_cleanup_to_tgt_rsp_trdid   = r_cleanup_write_trdid.read();
+            r_cleanup_to_tgt_rsp_pktid   = r_cleanup_write_pktid.read();
+            r_cleanup_fsm = CLEANUP_RSP;
+          }
+          break;
+        }
+        /////////////////
+      case CLEANUP_RSP:
+        {
+          if(p_vci_tgt_cleanup.rspack)
+            r_cleanup_fsm = CLEANUP_IDLE;
+          break;
+        }
+    } // end switch cleanup fsm
+
+
+    ////////////////////////////////////////////////////////////////////////////////////
+    //		LLSC FSM
+    ////////////////////////////////////////////////////////////////////////////////////
+    // The LLSC FSM handles the LL & SC atomic access.
+    //
+    // For a LL :
+    // It access the directory to check hit / miss.
+    // - In case of hit, the LL request is registered in the Atomic Table and the
+    // response is sent to the requesting processor.
+    // - In case of miss, the LLSC FSM accesses the transaction table. 
+    // If a read transaction to the XRAM for this line already exists, 
+    // or if the transaction table is full, it returns to IDLE state.
+    // Otherwise, a new transaction to the XRAM is initiated.
+    // In both cases, the LL request is not consumed in the FIFO.
+    //
+    // For a SC :
+    // It access the directory to check hit / miss.
+    // - In case of hit, the Atomic Table is checked and the proper response
+    // (true or false is sent to the requesting processor.
+    // - In case of miss, the LLSC FSM accesses the transaction table. 
+    // If a read transaction to the XRAM for this line already exists, 
+    // or if the transaction table is full, it returns to IDLE state. 
+    // Otherwise, a new transaction to the XRAM is initiated.
+    // In both cases, the SC request is not consumed in the FIFO.
+    /////////////////////////////////////////////////////////////////////
+
+    switch ( r_llsc_fsm.read() ) {
+
+      ///////////////
+      case LLSC_IDLE:		// test LL / SC
+        {
+          if( m_cmd_llsc_addr_fifo.rok() ) {
+            if(m_cmd_llsc_sc_fifo.read()){
+              m_cpt_sc++;
+              r_llsc_fsm = SC_DIR_LOCK;
+            }
+            else{
+              m_cpt_ll++;
+              r_llsc_fsm = LL_DIR_LOCK;
+            }
+          }	
+          break;
+        }
+        /////////////////
+      case LL_DIR_LOCK:		// check directory for hit / miss
+        {
+          if( r_alloc_dir_fsm.read() == ALLOC_DIR_LLSC ) {
+            size_t way = 0;
+            DirectoryEntry entry(m_cache_directory.read(m_cmd_llsc_addr_fifo.read(), way));
+            r_llsc_is_cnt     = entry.is_cnt;
+            r_llsc_dirty      = entry.dirty;
+            r_llsc_inst       = entry.inst;
+            r_llsc_tag        = entry.tag;
+            r_llsc_way        = way;
+            r_llsc_copy       = entry.owner.srcid;
+            r_llsc_copy_inst  = entry.owner.inst;
+            r_llsc_count      = entry.count;
+            r_llsc_ptr        = entry.ptr;
+
+            // set Atomic Table
+            m_atomic_tab.set(m_cmd_llsc_srcid_fifo.read(), m_cmd_llsc_addr_fifo.read());
+
+            if ( entry.valid )  r_llsc_fsm = LL_DIR_HIT;
+            else                r_llsc_fsm = LLSC_TRT_LOCK;
+          }
+          break;
+        }
+        ////////////////
+      case LL_DIR_HIT:		// read hit : update the memory cache
+        {
+          size_t way	= r_llsc_way.read();
+          size_t set	= m_y[(vci_addr_t)(m_cmd_llsc_addr_fifo.read())];
+          size_t word	= m_x[(vci_addr_t)(m_cmd_llsc_addr_fifo.read())];
+
+          // update directory (lock bit & copies)
+          DirectoryEntry entry;
+          entry.valid	    = true;
+          entry.is_cnt      = r_llsc_is_cnt.read();
+          entry.dirty	    = r_llsc_dirty.read();
+          entry.lock	    = true;
+          entry.inst        = r_llsc_inst.read();
+          entry.tag	        = r_llsc_tag.read();
+          entry.owner.srcid = r_llsc_copy.read();
+          entry.owner.inst  = r_llsc_copy_inst.read();
+          entry.count       = r_llsc_count.read();
+          entry.ptr         = r_llsc_ptr.read();
+          m_cache_directory.write(set, way, entry);
+
+          // read data in cache
+          r_llsc_data	= m_cache_data[way][set][word];
+
+          r_llsc_fsm 	= LL_RSP;
+          break;
+        }
+        ////////////
+      case LL_RSP:		// request the TGT_RSP FSM to return data
+        {
+          if ( !r_llsc_to_tgt_rsp_req ) {
+            cmd_llsc_fifo_get		= true;
+            r_llsc_to_tgt_rsp_data	= r_llsc_data.read();
+            r_llsc_to_tgt_rsp_srcid	= m_cmd_llsc_srcid_fifo.read();
+            r_llsc_to_tgt_rsp_trdid	= m_cmd_llsc_trdid_fifo.read();
+            r_llsc_to_tgt_rsp_pktid	= m_cmd_llsc_pktid_fifo.read();
+            r_llsc_to_tgt_rsp_req	= true;
+            r_llsc_fsm = LLSC_IDLE;
+          }
+          break;
+        }
+        /////////////////
+      case SC_DIR_LOCK:
+        {
+          if( r_alloc_dir_fsm.read() == ALLOC_DIR_LLSC ) {
+            size_t way = 0;
+            DirectoryEntry entry(m_cache_directory.read(m_cmd_llsc_addr_fifo.read(), way));
+            bool ok = m_atomic_tab.isatomic(m_cmd_llsc_srcid_fifo.read(),m_cmd_llsc_addr_fifo.read());
+            if( ok ) {
+              r_llsc_is_cnt   = entry.is_cnt;
+              r_llsc_dirty    = entry.dirty;
+              r_llsc_tag      = entry.tag;
+              r_llsc_way      = way;
+              r_llsc_copy     = entry.owner.srcid;
+              r_llsc_copy_inst= entry.owner.inst;
+              r_llsc_inst     = entry.inst;
+              r_llsc_ptr      = entry.ptr;
+              r_llsc_count    = entry.count;
+              if ( entry.valid ){
+                if((entry.is_cnt && entry.count) || entry.inst) {
+                  r_llsc_fsm = SC_TRT_LOCK;
+                } else {
+                  r_llsc_fsm = SC_DIR_HIT;
+                }
+              }
+              else r_llsc_fsm = LLSC_TRT_LOCK;
+            } else {
+              r_llsc_fsm = SC_RSP_FALSE;
+            }
+          }
+          break;
+        }
+        ////////////////
+      case SC_DIR_HIT:
+        {
+          size_t way	= r_llsc_way.read();
+          size_t set	= m_y[(vci_addr_t)(m_cmd_llsc_addr_fifo.read())]; 
+          size_t word	= m_x[(vci_addr_t)(m_cmd_llsc_addr_fifo.read())]; 
+
+          // update directory (lock & dirty bits
+          DirectoryEntry entry;
+          entry.valid	    = true;
+          entry.is_cnt      = r_llsc_is_cnt.read();
+          entry.dirty	    = true;
+          entry.lock	    = true;
+          entry.inst        = r_llsc_inst.read();
+          entry.tag	        = r_llsc_tag.read();
+          entry.owner.srcid = r_llsc_copy.read();
+          entry.owner.inst  = r_llsc_copy_inst.read();
+          entry.count       = r_llsc_count.read();
+          entry.ptr         = r_llsc_ptr.read();
+          m_cache_directory.write(set, way, entry);
+
+          if(!r_llsc_count.read()){ // no update
+            // write data in cache
+            m_cache_data[way][set][word] = m_cmd_llsc_wdata_fifo.read();
+            // reset Atomic Table
+            m_atomic_tab.reset(m_cmd_llsc_addr_fifo.read());
+          }
+          
+          if(r_llsc_count.read()) {  // Shared line
+              if( !r_llsc_to_init_cmd_multi_req.read() && 
+                  !r_llsc_to_init_cmd_brdcast_req.read()  )
+                  r_llsc_fsm = SC_UPT_LOCK;
+              else
+                  r_llsc_fsm = SC_WAIT;
+          } else {
+            r_llsc_fsm = SC_RSP_TRUE;
+          }
+          break;
+        }
+        /////////////////////
+      case SC_UPT_LOCK: 	// Try to register the request in Update Table
+        {
+
+          if ( r_alloc_upt_fsm.read() == ALLOC_UPT_LLSC ) {
+            size_t way	= r_llsc_way.read();
+            size_t set	= m_y[(vci_addr_t)(m_cmd_llsc_addr_fifo.read())]; 
+            size_t word	= m_x[(vci_addr_t)(m_cmd_llsc_addr_fifo.read())]; 
+            bool        wok        = false;
+            size_t      index      = 0;
+            size_t      srcid      = m_cmd_llsc_srcid_fifo.read();
+            size_t      trdid      = m_cmd_llsc_trdid_fifo.read();
+            size_t      pktid      = m_cmd_llsc_pktid_fifo.read();
+            addr_t	    nline      = m_nline[(vci_addr_t)(m_cmd_llsc_addr_fifo.read())];
+            size_t      nb_copies  = r_llsc_count.read();
+
+            wok =m_update_tab.set(true,	// it's an update transaction
+                false,                  // it's not a broadcast
+                true,                   // it needs a response
+                srcid,
+                trdid,
+                pktid,
+                nline,
+                nb_copies,
+                index);
+            if(wok){
+              // write data in cache
+              m_cache_data[way][set][word] = m_cmd_llsc_wdata_fifo.read();
+              // reset Atomic Table
+              m_atomic_tab.reset(m_cmd_llsc_addr_fifo.read());
+            }
+#ifdef IDEBUG
+            if(wok){
+                TRACE_MSG(m_log << m_total_cycles << " " << name() << " SC_UPT_LOCK update table : " << std::endl);
+                DUMP_UPDATE_TABLE;
+            }
+#endif
+            r_llsc_upt_index = index;
+            //  releases the lock protecting the Update Table and the Directory if no entry...
+            if ( wok ) r_llsc_fsm = SC_HEAP_LOCK;
+            else       r_llsc_fsm = SC_WAIT;
+          }
+          break;
+        }
+        ////////////////////
+      case SC_WAIT: 	// release all locks
+        {
+          r_llsc_fsm = SC_DIR_LOCK;
+          break;
+        }
+        ////////////////////
+      case SC_HEAP_LOCK: 	// lock the heap
+        {
+          if( r_alloc_heap_fsm.read() == ALLOC_HEAP_LLSC ){
+            r_llsc_fsm = SC_UPT_REQ;
+          }
+          break;
+        }
+        ////////////////////
+      case SC_UPT_REQ: 	// Request the update
+        {
+          assert( (r_alloc_heap_fsm.read() == ALLOC_HEAP_LLSC) &&
+                    "MemCache ERROR : bad HEAP allocation");
+          if( !r_llsc_to_init_cmd_multi_req.read() && 
+              !r_llsc_to_init_cmd_brdcast_req.read()  ){
+            r_llsc_to_init_cmd_brdcast_req  = false;
+            r_llsc_to_init_cmd_trdid        = r_llsc_upt_index.read();
+            r_llsc_to_init_cmd_nline        = m_nline[(vci_addr_t)(m_cmd_llsc_addr_fifo.read())];
+            r_llsc_to_init_cmd_index        = m_x[(vci_addr_t)(m_cmd_llsc_addr_fifo.read())];
+            r_llsc_to_init_cmd_wdata        = m_cmd_llsc_wdata_fifo.read();
+
+            // We put the first copy in the fifo
+            llsc_to_init_cmd_fifo_put     = true;
+            llsc_to_init_cmd_fifo_inst    = r_llsc_copy_inst.read();
+            llsc_to_init_cmd_fifo_srcid   = r_llsc_copy.read();
+            if(r_llsc_count.read() == 1){
+              r_llsc_fsm = LLSC_IDLE;
+              cmd_llsc_fifo_get            = true;
+              r_llsc_to_init_cmd_multi_req = true;
+            } else {
+              r_llsc_fsm = SC_UPDATE;
+            }
+          }
+          break;
+        }
+        //////////////////
+      case SC_UPDATE:   	// send a multi-update request to INIT_CMD fsm
+        {
+          assert( (r_alloc_heap_fsm.read() == ALLOC_HEAP_LLSC) &&
+                    "MemCache ERROR : bad HEAP allocation");
+          HeapEntry entry = m_heap_directory.read(r_llsc_ptr.read());
+          llsc_to_init_cmd_fifo_inst  = entry.owner.inst;
+          llsc_to_init_cmd_fifo_srcid = entry.owner.srcid;
+          llsc_to_init_cmd_fifo_put = true;
+
+          if( m_llsc_to_init_cmd_inst_fifo.wok() ){
+            r_llsc_ptr = entry.next;
+            if( entry.next == r_llsc_ptr.read() ) { // last copy
+              r_llsc_to_init_cmd_multi_req = true;
+              r_llsc_fsm = LLSC_IDLE; // Response will be sent after receiving
+                                      // all update responses
+              cmd_llsc_fifo_get         = true;
+            } else {
+              r_llsc_fsm = SC_UPDATE;
+            }
+          } else {
+            r_llsc_fsm = SC_UPDATE;
+          }
+          
+          break;
+        }
+        //////////////////
+      case SC_TRT_LOCK:
+        {
+          if( r_alloc_trt_fsm.read() == ALLOC_TRT_LLSC ) {
+            if( !r_llsc_to_ixr_cmd_req ) { // we can transfer the data to the buffer
+              size_t way	= r_llsc_way.read();
+              size_t set	= m_y[(vci_addr_t)(m_cmd_llsc_addr_fifo.read())];
+              for(size_t i = 0; i<m_words; i++){
+                if(i==m_x[(vci_addr_t)m_cmd_llsc_addr_fifo.read()]) {
+                  r_llsc_to_ixr_cmd_data[i] = m_cmd_llsc_wdata_fifo.read();
+                } else {
+                  r_llsc_to_ixr_cmd_data[i] = m_cache_data[way][set][i];
+                }
+              }
+              size_t wok_index = 0;
+              bool wok = !m_transaction_tab.full(wok_index);
+              if ( wok ) { // set a new entry in TRT
+                r_llsc_trt_index = wok_index;
+                r_llsc_fsm       = SC_INVAL_LOCK; 
+              } else {
+                r_llsc_fsm       = SC_WAIT;
+              }
+            } else {
+              r_llsc_fsm = SC_WAIT;
+            }
+          }
+          break;
+        }
+        //////////////////
+      case SC_INVAL_LOCK:
+        {
+          if ( r_alloc_upt_fsm.read() == ALLOC_UPT_LLSC ) {
+            bool        wok       = false;
+            size_t      index     = 0;
+            size_t      srcid     = m_cmd_llsc_srcid_fifo.read();
+            size_t      trdid     = m_cmd_llsc_trdid_fifo.read();
+            size_t      pktid     = m_cmd_llsc_pktid_fifo.read();
+            addr_t	    nline     = m_nline[(vci_addr_t)(m_cmd_llsc_addr_fifo.read())];
+            size_t      nb_copies = r_llsc_count.read();
+
+            wok =m_update_tab.set(false,	// it's an inval transaction
+                true,                       // it's a broadcast
+                true,                       // it needs a response
+                srcid,
+                trdid,
+                pktid,
+                nline,
+                nb_copies,
+                index);
+#ifdef IDEBUG
+            if(wok){
+                TRACE_MSG(m_log << m_total_cycles << " " << name() << " LLSC_INVAL_LOCK update table : " << std::endl);
+                DUMP_UPDATE_TABLE;
+            }
+#endif
+            r_llsc_upt_index = index;
+            //  releases the lock protecting Update Table if no entry...
+            if ( wok ) r_llsc_fsm = SC_DIR_INVAL;
+            else       r_llsc_fsm = SC_WAIT;
+          }
+          break;
+        }
+        //////////////////
+      case SC_DIR_INVAL:
+        {
+          if ( (r_alloc_trt_fsm.read() == ALLOC_TRT_LLSC ) &&
+              (r_alloc_upt_fsm.read() == ALLOC_UPT_LLSC )  &&
+              (r_alloc_dir_fsm.read() == ALLOC_DIR_LLSC ))
+          {
+            m_transaction_tab.set(r_llsc_trt_index.read(),
+                false,				// write request to XRAM
+                m_nline[(vci_addr_t)(m_cmd_llsc_addr_fifo.read())],
+                0,
+                0,
+                0,
+                false,				// not a processor read
+                0,  				// not a single word 
+                0,		        	// word index
+                std::vector<be_t>(m_words,0),
+                std::vector<data_t>(m_words,0));
+#ifdef TDEBUG
+            TRACE_MSG(m_log << m_total_cycles << " " << name() << " SC_DIR_INVAL transaction table : " << std::endl);
+            DUMP_TRANSACTION_TABLE;
+#endif
+            // reset Atomic Table
+            m_atomic_tab.reset(m_cmd_llsc_addr_fifo.read());
+
+            // invalidate directory entry
+            DirectoryEntry entry;
+            entry.valid	   = false;
+            entry.dirty	   = false;
+            entry.tag	   = 0;
+            entry.is_cnt   = false;
+            entry.lock	   = false;
+//            entry.d_copies = 0;
+//            entry.i_copies = 0;
+            entry.count    = 0;
+            size_t set	   = m_y[(vci_addr_t)(m_cmd_llsc_addr_fifo.read())];
+            size_t way	   = r_llsc_way.read();
+            m_cache_directory.write(set, way, entry);
+
+            r_llsc_fsm = SC_INVAL;
+          } else {
+            assert(false && "LOCK ERROR in LLSC_FSM, STATE = LLSC_DIR_INVAL");
+          }
+
+          break;
+
+        }
+        //////////////////
+      case SC_INVAL:
+        {
+          if ( !r_llsc_to_init_cmd_multi_req.read() &&
+               !r_llsc_to_init_cmd_brdcast_req.read()) {
+            r_llsc_to_init_cmd_multi_req    = false;
+            r_llsc_to_init_cmd_brdcast_req  = true;
+            r_llsc_to_init_cmd_trdid        = r_llsc_upt_index.read();
+            r_llsc_to_init_cmd_nline        = m_nline[(vci_addr_t)(m_cmd_llsc_addr_fifo.read())];
+            r_llsc_to_init_cmd_index        = 0;
+            r_llsc_to_init_cmd_wdata        = 0;
+
+            r_llsc_fsm = SC_XRAM_SEND;
+            // all update responses
+          }
+
+          break;
+        }
+        //////////////////
+      case SC_XRAM_SEND:
+        {
+          if ( !r_llsc_to_ixr_cmd_req ) {
+            r_llsc_to_ixr_cmd_req     = true;
+            r_llsc_to_ixr_cmd_write   = true;
+            r_llsc_to_ixr_cmd_nline   = m_nline[(vci_addr_t)(m_cmd_llsc_addr_fifo.read())];
+            r_llsc_to_ixr_cmd_trdid   = r_llsc_trt_index.read();
+            if(  r_llsc_is_cnt.read() ||
+                ((!r_llsc_is_cnt.read()) && (r_llsc_count.read()==1)) ){
+              r_llsc_fsm        = LLSC_IDLE;
+              cmd_llsc_fifo_get = true;
+            } else {
+              r_llsc_fsm        = SC_HEAP_ERASE;
+              r_llsc_next_ptr   = r_llsc_ptr.read();
+            }
+          } else {
+            assert( false && "MEM_CACHE, LLSC FSM : SC_XRAM_SEND state : the request should not have been previously set");
+          }
+          break;
+        }
+        //////////////////
+      case SC_HEAP_ERASE:
+        {
+          if(r_alloc_heap_fsm.read() == ALLOC_HEAP_LLSC){
+            HeapEntry next_entry = m_heap_directory.read(r_llsc_next_ptr.read());
+            if( next_entry.next == r_llsc_next_ptr.read()){
+                //r_write_fsm = SC_HEAP_LAST;
+                r_llsc_fsm = SC_HEAP_LAST; // As suggest by Alexendre J.
+            } else {
+              r_llsc_next_ptr = next_entry.next;
+              r_llsc_fsm = SC_HEAP_ERASE;
+            }
+          }
+          break;
+        }
+        //////////////////
+      case SC_HEAP_LAST:
+        {
+          assert((r_alloc_heap_fsm.read() == ALLOC_HEAP_LLSC) &&
+                  "MemCache ERROR : bad HEAP allocation");
+          size_t free_pointer = m_heap_directory.next_free_ptr();
+
+          HeapEntry last_entry;
+          last_entry.owner.srcid = 0;
+          last_entry.owner.inst  = false;
+          if(m_heap_directory.is_full()){
+            last_entry.next     = r_llsc_next_ptr.read();
+            m_heap_directory.unset_full();
+          } else {
+            last_entry.next     = free_pointer;
+          }
+
+          m_heap_directory.write_free_ptr(r_llsc_ptr.read());
+          m_heap_directory.write(r_llsc_next_ptr.read(),last_entry);
+
+          cmd_llsc_fifo_get		= true;
+          r_llsc_fsm = LLSC_IDLE;
+          break;
+        }
+        //////////////////
+      case SC_RSP_FALSE:
+        {
+          if( !r_llsc_to_tgt_rsp_req ) {
+            cmd_llsc_fifo_get		= true;
+            r_llsc_to_tgt_rsp_req	= true;
+            r_llsc_to_tgt_rsp_data	= 1;
+            r_llsc_to_tgt_rsp_srcid	= m_cmd_llsc_srcid_fifo.read();
+            r_llsc_to_tgt_rsp_trdid	= m_cmd_llsc_trdid_fifo.read();
+            r_llsc_to_tgt_rsp_pktid	= m_cmd_llsc_pktid_fifo.read();
+            r_llsc_fsm 			    = LLSC_IDLE;
+          }
+          break;
+        }
+        /////////////////
+      case SC_RSP_TRUE:
+        {
+          if( !r_llsc_to_tgt_rsp_req ) {
+            cmd_llsc_fifo_get	    = true;
+            r_llsc_to_tgt_rsp_req	= true;
+            r_llsc_to_tgt_rsp_data	= 0;
+            r_llsc_to_tgt_rsp_srcid	= m_cmd_llsc_srcid_fifo.read();
+            r_llsc_to_tgt_rsp_trdid	= m_cmd_llsc_trdid_fifo.read();
+            r_llsc_to_tgt_rsp_pktid	= m_cmd_llsc_pktid_fifo.read();
+            r_llsc_fsm 			    = LLSC_IDLE;
+          }
+          break;
+        }
+        ///////////////////
+      case LLSC_TRT_LOCK:         // read or write miss : check the Transaction Table
+        {
+          if( r_alloc_trt_fsm.read() == ALLOC_TRT_LLSC ) {
+            size_t   index = 0;
+            bool hit_read = m_transaction_tab.hit_read(m_nline[(vci_addr_t)m_cmd_llsc_addr_fifo.read()],index);
+            bool hit_write = m_transaction_tab.hit_write(m_nline[(vci_addr_t)m_cmd_llsc_addr_fifo.read()]);
+            bool wok = !m_transaction_tab.full(index);
+
+            if ( hit_read || !wok || hit_write ) {  // missing line already requested or no space in TRT
+              r_llsc_fsm = LLSC_IDLE;
+            } else {
+              r_llsc_trt_index = index;
+              r_llsc_fsm       = LLSC_TRT_SET;
+            }
+          }
+          break;
+        }
+        //////////////////
+      case LLSC_TRT_SET:	// register the XRAM transaction in Transaction Table
+        {
+          if( r_alloc_trt_fsm.read() == ALLOC_TRT_LLSC ) {
+            size_t word	= m_x[(vci_addr_t)(m_cmd_llsc_addr_fifo.read())]; 
+            bool proc_read = !m_cmd_llsc_sc_fifo.read();
+            if(proc_read){
+              m_transaction_tab.set(r_llsc_trt_index.read(),
+                  true,
+                  m_nline[(vci_addr_t)m_cmd_llsc_addr_fifo.read()],
+                  m_cmd_llsc_srcid_fifo.read(),
+                  m_cmd_llsc_trdid_fifo.read(),
+                  m_cmd_llsc_pktid_fifo.read(),
+                  true,
+                  1,
+                  word,
+                  std::vector<be_t>(m_words,0),
+                  std::vector<data_t>(m_words,0));
+            }else{
+              std::vector<be_t> be_vector;
+              std::vector<data_t> data_vector;
+              be_vector.clear();
+              data_vector.clear();
+              // reset Atomic Table
+              m_atomic_tab.reset(m_cmd_llsc_addr_fifo.read());
+              for ( size_t i=0; i<m_words; i++ ) 
+              {   
+                if(i == word){
+                  be_vector.push_back(0xF);
+                  data_vector.push_back(m_cmd_llsc_wdata_fifo.read());
+                } else {
+                  be_vector.push_back(0);
+                  data_vector.push_back(0);
+                }
+              }
+ 
+              m_transaction_tab.set(r_llsc_trt_index.read(),
+                  true,
+                  m_nline[(vci_addr_t)m_cmd_llsc_addr_fifo.read()],
+                  m_cmd_llsc_srcid_fifo.read(),
+                  m_cmd_llsc_trdid_fifo.read(),
+                  m_cmd_llsc_pktid_fifo.read(),
+                  false,
+                  0,
+                  0,
+                  be_vector,
+                  data_vector);
+            }
+#ifdef TDEBUG
+            TRACE_MSG(m_log << m_total_cycles << " " << name() << " LLSC_TRT_SET transaction table : " << std::endl);
+            DUMP_TRANSACTION_TABLE;
+#endif
+
+            r_llsc_fsm = LLSC_XRAM_REQ;
+          }
+          break;
+        }
+        ///////////////////
+      case LLSC_XRAM_REQ:	// request the IXR_CMD FSM to fetch the missing line
+        {
+          if ( !r_llsc_to_ixr_cmd_req ) {
+            r_llsc_to_ixr_cmd_req        = true;
+            r_llsc_to_ixr_cmd_write      = false;
+            r_llsc_to_ixr_cmd_trdid      = r_llsc_trt_index.read();
+            r_llsc_to_ixr_cmd_nline      = m_nline[(vci_addr_t)m_cmd_llsc_addr_fifo.read()];
+            if( m_cmd_llsc_sc_fifo.read() ) {
+              r_llsc_fsm                 = SC_RSP_TRUE;
+            } else {
+              cmd_llsc_fifo_get          = true;
+              r_llsc_fsm                 = LLSC_IDLE;
+            }
+          }
+          break;
+        }
+    } // end switch r_llsc_fsm
+
+
+    //////////////////////////////////////////////////////////////////////////////
+    //		INIT_CMD FSM
+    //////////////////////////////////////////////////////////////////////////////
+    // The INIT_CMD fsm controls the VCI CMD initiator port, used to update
+    // or invalidate cache lines in L1 caches.
+    // It implements a round-robin priority between the two following requests:
+    // - r_write_to_init_cmd_req : update request from WRITE FSM 
+    // - r_xram_rsp_to_init_cmd_req : invalidate request from XRAM_RSP FSM 
+    // The inval request is a single cell VCI write command containing the 
+    // index of the line to be invalidated.
+    // The update request is a multi-cells VCI write command : The first cell 
+    // contains the index of the cache line to be updated. The second cell contains 
+    // the index of the first modified word in the line. The following cells
+    // contain the data.
+    ///////////////////////////////////////////////////////////////////////////////
+
+    switch ( r_init_cmd_fsm.read() ) {
+
+      //////////////////////// 
+      case INIT_CMD_UPDT_IDLE:	// Invalidate requests have highest priority
+        {
+
+          if ( m_xram_rsp_to_init_cmd_inst_fifo.rok() ||
+               r_xram_rsp_to_init_cmd_multi_req.read()  ) {
+            r_init_cmd_fsm = INIT_CMD_INVAL_NLINE;
+            m_cpt_inval++;
+          } else if ( r_xram_rsp_to_init_cmd_brdcast_req.read() ) {
+            r_init_cmd_fsm = INIT_CMD_XRAM_BRDCAST;
+            m_cpt_inval++;
+          } else if ( m_write_to_init_cmd_inst_fifo.rok() ||
+                      r_write_to_init_cmd_multi_req.read() ) {
+            r_init_cmd_fsm = INIT_CMD_UPDT_NLINE;
+            m_cpt_update++;
+          } else if ( r_write_to_init_cmd_brdcast_req.read() ){
+            r_init_cmd_fsm = INIT_CMD_WRITE_BRDCAST;
+            m_cpt_inval++;
+          } else if ( m_llsc_to_init_cmd_inst_fifo.rok() ||
+                      r_llsc_to_init_cmd_multi_req.read()  ) {
+            r_init_cmd_fsm = INIT_CMD_SC_UPDT_NLINE;
+            m_cpt_update++;
+          } else if( r_llsc_to_init_cmd_brdcast_req.read() ){
+            r_init_cmd_fsm = INIT_CMD_SC_BRDCAST;
+            m_cpt_inval++;
+          }
+          break;
+        }
+        /////////////////////////
+      case INIT_CMD_INVAL_IDLE:	// Update requests have highest priority
+        {
+          if ( m_write_to_init_cmd_inst_fifo.rok() ||
+               r_write_to_init_cmd_multi_req.read() ) {
+            r_init_cmd_fsm = INIT_CMD_UPDT_NLINE;
+            m_cpt_update++;
+          } else if ( r_write_to_init_cmd_brdcast_req.read() ){
+            r_init_cmd_fsm = INIT_CMD_WRITE_BRDCAST;
+            m_cpt_inval++;
+          } else if ( m_llsc_to_init_cmd_inst_fifo.rok() ||
+                      r_llsc_to_init_cmd_multi_req.read()  ) {
+            r_init_cmd_fsm = INIT_CMD_SC_UPDT_NLINE;
+            m_cpt_update++;
+          } else if( r_llsc_to_init_cmd_brdcast_req.read() ){
+            r_init_cmd_fsm = INIT_CMD_SC_BRDCAST;
+            m_cpt_inval++;
+          } else if ( m_xram_rsp_to_init_cmd_inst_fifo.rok() ||
+                      r_xram_rsp_to_init_cmd_multi_req.read()  ) {
+            r_init_cmd_fsm = INIT_CMD_INVAL_NLINE;
+            m_cpt_inval++;
+          } else if ( r_xram_rsp_to_init_cmd_brdcast_req.read() ) {
+            r_init_cmd_fsm = INIT_CMD_XRAM_BRDCAST;
+            m_cpt_inval++;
+          }
+          break;
+        }
+        /////////////////////////
+      case INIT_CMD_SC_UPDT_IDLE:	// Update requests for SCs have highest priority
+        {
+          if ( m_llsc_to_init_cmd_inst_fifo.rok() ||
+               r_llsc_to_init_cmd_multi_req.read()  ) {
+            r_init_cmd_fsm = INIT_CMD_SC_UPDT_NLINE;
+            m_cpt_update++;
+          } else if( r_llsc_to_init_cmd_brdcast_req.read() ){
+            r_init_cmd_fsm = INIT_CMD_SC_BRDCAST;
+            m_cpt_inval++;
+          } else if ( m_xram_rsp_to_init_cmd_inst_fifo.rok() ||
+                      r_xram_rsp_to_init_cmd_multi_req.read()  ) {
+            r_init_cmd_fsm = INIT_CMD_INVAL_NLINE;
+            m_cpt_inval++;
+          } else if ( r_xram_rsp_to_init_cmd_brdcast_req.read() ) {
+            r_init_cmd_fsm = INIT_CMD_XRAM_BRDCAST;
+            m_cpt_inval++;
+          } else if ( m_write_to_init_cmd_inst_fifo.rok() ||
+                      r_write_to_init_cmd_multi_req.read() ) {
+            r_init_cmd_fsm = INIT_CMD_UPDT_NLINE;
+            m_cpt_update++;
+          } else if ( r_write_to_init_cmd_brdcast_req.read() ){
+            r_init_cmd_fsm = INIT_CMD_WRITE_BRDCAST;
+            m_cpt_inval++;
+          }
+          break;
+        }
+        ////////////////////////
+      case INIT_CMD_INVAL_NLINE:	// send the cache line index
+        {
+          if ( m_xram_rsp_to_init_cmd_inst_fifo.rok() ){
+            if ( p_vci_ini.cmdack ) {
+              m_cpt_inval_mult++;
+              r_init_cmd_fsm = INIT_CMD_INVAL_NLINE;
+              xram_rsp_to_init_cmd_fifo_get = true;
+            }
+          } else {
+            if( r_xram_rsp_to_init_cmd_multi_req.read() ){
+              r_xram_rsp_to_init_cmd_multi_req = false;
+            } 
+            r_init_cmd_fsm = INIT_CMD_INVAL_IDLE;
+          }
+          break;
+        }
+        ////////////////////////
+      case INIT_CMD_XRAM_BRDCAST:	// send the cache line index
+        {
+          if ( p_vci_ini.cmdack ) {
+            m_cpt_inval_brdcast++;
+            r_init_cmd_fsm = INIT_CMD_INVAL_IDLE;
+            r_xram_rsp_to_init_cmd_brdcast_req = false;
+          }
+          break;
+        }
+        /////////////////////////
+      case INIT_CMD_WRITE_BRDCAST:
+        {
+          if( p_vci_ini.cmdack ) {
+            m_cpt_inval_brdcast++;
+            r_write_to_init_cmd_brdcast_req = false;
+            r_init_cmd_fsm = INIT_CMD_UPDT_IDLE;
+          }
+          break;
+        }
+        /////////////////////////
+      case INIT_CMD_UPDT_NLINE:	// send the cache line index
+        {
+          if ( m_write_to_init_cmd_inst_fifo.rok() ) {
+            if ( p_vci_ini.cmdack ){
+              m_cpt_update_mult++;
+              r_init_cmd_fsm = INIT_CMD_UPDT_INDEX;
+            }
+          } else {
+            if ( r_write_to_init_cmd_multi_req.read() ){
+              r_write_to_init_cmd_multi_req = false;
+            }
+            r_init_cmd_fsm = INIT_CMD_UPDT_IDLE;
+          }
+          break;
+        }
+        /////////////////////////
+      case INIT_CMD_UPDT_INDEX:	// send the first word index
+        {
+          r_init_cmd_cpt    = 0;
+          if ( p_vci_ini.cmdack )  r_init_cmd_fsm = INIT_CMD_UPDT_DATA;
+          break;
+        }
+        ////////////////////////
+      case INIT_CMD_UPDT_DATA:	// send the data
+        {
+          if ( p_vci_ini.cmdack ) {
+            if ( r_init_cmd_cpt.read() == (r_write_to_init_cmd_count.read()-1) ) {
+              r_init_cmd_fsm = INIT_CMD_UPDT_NLINE;
+              write_to_init_cmd_fifo_get = true;
+            } else {
+              r_init_cmd_cpt = r_init_cmd_cpt.read() + 1;
+            }
+          }
+          break;
+        }
+        /////////////////////////
+      case INIT_CMD_SC_BRDCAST:
+        {
+          if( p_vci_ini.cmdack ) {
+            m_cpt_inval_brdcast++;
+            r_llsc_to_init_cmd_brdcast_req = false;
+            r_init_cmd_fsm = INIT_CMD_SC_UPDT_IDLE;
+          }
+          break;
+        }
+        /////////////////////////
+      case INIT_CMD_SC_UPDT_NLINE:	// send the cache line index
+        {
+          if ( m_llsc_to_init_cmd_inst_fifo.rok() ){
+            if ( p_vci_ini.cmdack ){
+              m_cpt_update_mult++;
+              r_init_cmd_fsm = INIT_CMD_SC_UPDT_INDEX;
+            }
+          } else {
+            if( r_llsc_to_init_cmd_multi_req.read() ){
+              r_llsc_to_init_cmd_multi_req = false;
+            }
+            r_init_cmd_fsm = INIT_CMD_SC_UPDT_IDLE;
+          }
+          break;
+        }
+        /////////////////////////
+      case INIT_CMD_SC_UPDT_INDEX:	// send the first word index
+        {
+          if ( p_vci_ini.cmdack )  r_init_cmd_fsm = INIT_CMD_SC_UPDT_DATA;
+          break;
+        }
+        ////////////////////////
+      case INIT_CMD_SC_UPDT_DATA:	// send the data
+        {
+          if ( p_vci_ini.cmdack ) {
+            llsc_to_init_cmd_fifo_get = true;
+            r_init_cmd_fsm = INIT_CMD_SC_UPDT_NLINE;
+          }
+          break;
+        }
+
+    } // end switch r_init_cmd_fsm
+
+    /////////////////////////////////////////////////////////////////////
+    //		TGT_RSP FSM
+    /////////////////////////////////////////////////////////////////////
+    // The TGT_RSP fsm sends the responses on the VCI target port
+    // with a round robin priority between six requests :
+    // - r_read_to_tgt_rsp_req
+    // - r_write_to_tgt_rsp_req
+    // - r_llsc_to_tgt_rsp_req
+    // - r_cleanup_to_tgt_rsp_req
+    // - r_init_rsp_to_tgt_rsp_req
+    // - r_xram_rsp_to_tgt_rsp_req
+    // The  ordering is :  read > write > llsc > cleanup > xram > init
+    /////////////////////////////////////////////////////////////////////
+
+    switch ( r_tgt_rsp_fsm.read() ) {
+
+      ///////////////////////
+      case TGT_RSP_READ_IDLE:		// write requests have the highest priority
+        {
+          if      ( r_write_to_tgt_rsp_req    ) r_tgt_rsp_fsm = TGT_RSP_WRITE;
+          else if ( r_llsc_to_tgt_rsp_req     ) r_tgt_rsp_fsm = TGT_RSP_LLSC;
+          else if ( r_xram_rsp_to_tgt_rsp_req ) {
+            r_tgt_rsp_fsm = TGT_RSP_XRAM;
+            r_tgt_rsp_cpt = r_xram_rsp_to_tgt_rsp_word.read();
+          }
+          else if ( r_init_rsp_to_tgt_rsp_req ) r_tgt_rsp_fsm = TGT_RSP_INIT;
+          else if ( r_cleanup_to_tgt_rsp_req  ) r_tgt_rsp_fsm = TGT_RSP_CLEANUP;
+          else if ( r_read_to_tgt_rsp_req     ) {
+            r_tgt_rsp_fsm = TGT_RSP_READ;
+            r_tgt_rsp_cpt = r_read_to_tgt_rsp_word.read();
+          }
+          break;
+        }
+        ////////////////////////
+      case TGT_RSP_WRITE_IDLE:		// llsc requests have the highest priority
+        {
+          if      ( r_llsc_to_tgt_rsp_req     ) r_tgt_rsp_fsm = TGT_RSP_LLSC;
+          else if ( r_xram_rsp_to_tgt_rsp_req ) {
+            r_tgt_rsp_fsm = TGT_RSP_XRAM;
+            r_tgt_rsp_cpt = r_xram_rsp_to_tgt_rsp_word.read();
+          }
+          else if ( r_init_rsp_to_tgt_rsp_req ) r_tgt_rsp_fsm = TGT_RSP_INIT;
+          else if ( r_cleanup_to_tgt_rsp_req  ) r_tgt_rsp_fsm = TGT_RSP_CLEANUP;
+          else if ( r_read_to_tgt_rsp_req     ) {
+            r_tgt_rsp_fsm = TGT_RSP_READ;
+            r_tgt_rsp_cpt = r_read_to_tgt_rsp_word.read();
+          }
+
+          else if ( r_write_to_tgt_rsp_req    ) r_tgt_rsp_fsm = TGT_RSP_WRITE;
+          break;
+        }
+        ///////////////////////
+      case TGT_RSP_LLSC_IDLE:		// cleanup requests have the highest priority
+        {
+          if ( r_xram_rsp_to_tgt_rsp_req )  {
+            r_tgt_rsp_fsm = TGT_RSP_XRAM;
+            r_tgt_rsp_cpt = r_xram_rsp_to_tgt_rsp_word.read();
+          }
+          else if ( r_init_rsp_to_tgt_rsp_req ) r_tgt_rsp_fsm = TGT_RSP_INIT;
+          else if ( r_cleanup_to_tgt_rsp_req  ) r_tgt_rsp_fsm = TGT_RSP_CLEANUP;
+          else if ( r_read_to_tgt_rsp_req     ) {
+            r_tgt_rsp_fsm = TGT_RSP_READ;
+            r_tgt_rsp_cpt = r_read_to_tgt_rsp_word.read();
+          }
+          else if ( r_write_to_tgt_rsp_req    ) r_tgt_rsp_fsm = TGT_RSP_WRITE;
+          else if ( r_llsc_to_tgt_rsp_req     ) r_tgt_rsp_fsm = TGT_RSP_LLSC;
+          break;
+        }
+      case TGT_RSP_XRAM_IDLE:		// init requests have the highest priority
+        {
+
+          if      ( r_init_rsp_to_tgt_rsp_req ) r_tgt_rsp_fsm = TGT_RSP_INIT;
+          else if ( r_cleanup_to_tgt_rsp_req  ) r_tgt_rsp_fsm = TGT_RSP_CLEANUP;
+          else if ( r_read_to_tgt_rsp_req     ) {
+            r_tgt_rsp_fsm = TGT_RSP_READ;
+            r_tgt_rsp_cpt = r_read_to_tgt_rsp_word.read();
+          }
+          else if ( r_write_to_tgt_rsp_req    ) r_tgt_rsp_fsm = TGT_RSP_WRITE;
+          else if ( r_llsc_to_tgt_rsp_req     ) r_tgt_rsp_fsm = TGT_RSP_LLSC;
+          else if ( r_xram_rsp_to_tgt_rsp_req )  {
+            r_tgt_rsp_fsm = TGT_RSP_XRAM;
+            r_tgt_rsp_cpt = r_xram_rsp_to_tgt_rsp_word.read();
+          }
+          break;
+        }
+        ///////////////////////
+      case TGT_RSP_INIT_IDLE:		// cleanup requests have the highest priority
+        {
+          if      ( r_cleanup_to_tgt_rsp_req  ) r_tgt_rsp_fsm = TGT_RSP_CLEANUP;
+          else if ( r_read_to_tgt_rsp_req     ) {
+            r_tgt_rsp_fsm = TGT_RSP_READ;
+            r_tgt_rsp_cpt = r_read_to_tgt_rsp_word.read();
+          }
+          else if ( r_write_to_tgt_rsp_req    ) r_tgt_rsp_fsm = TGT_RSP_WRITE;
+          else if ( r_llsc_to_tgt_rsp_req     ) r_tgt_rsp_fsm = TGT_RSP_LLSC;
+          else if ( r_xram_rsp_to_tgt_rsp_req ) {
+            r_tgt_rsp_fsm = TGT_RSP_XRAM;
+            r_tgt_rsp_cpt = r_xram_rsp_to_tgt_rsp_word.read();
+          }
+          else if ( r_init_rsp_to_tgt_rsp_req ) r_tgt_rsp_fsm = TGT_RSP_INIT;
+          break;
+        }
+        ///////////////////////
+      case TGT_RSP_CLEANUP_IDLE:		// read requests have the highest priority
+        {
+          if      ( r_read_to_tgt_rsp_req     ) {
+            r_tgt_rsp_fsm = TGT_RSP_READ;
+            r_tgt_rsp_cpt = r_read_to_tgt_rsp_word.read();
+          }
+          else if ( r_write_to_tgt_rsp_req    ) r_tgt_rsp_fsm = TGT_RSP_WRITE;
+          else if ( r_llsc_to_tgt_rsp_req     ) r_tgt_rsp_fsm = TGT_RSP_LLSC;
+          else if ( r_xram_rsp_to_tgt_rsp_req ) {
+            r_tgt_rsp_fsm = TGT_RSP_XRAM;
+            r_tgt_rsp_cpt = r_xram_rsp_to_tgt_rsp_word.read();
+          }
+          else if ( r_init_rsp_to_tgt_rsp_req ) r_tgt_rsp_fsm = TGT_RSP_INIT;
+          else if ( r_cleanup_to_tgt_rsp_req  ) r_tgt_rsp_fsm = TGT_RSP_CLEANUP;
+          break;
+        }
+        ///////////////////////
+      case TGT_RSP_READ:		// send the response
+        {
+          if ( p_vci_tgt.rspack ) {
+            if ( r_tgt_rsp_cpt.read() == (r_read_to_tgt_rsp_word.read()+r_read_to_tgt_rsp_length-1) ) {
+              r_tgt_rsp_fsm = TGT_RSP_READ_IDLE;
+              r_read_to_tgt_rsp_req = false;
+            } else {
+              r_tgt_rsp_cpt = r_tgt_rsp_cpt.read() + 1;
+            }
+          }
+          break;
+        }
+        ///////////////////
+      case TGT_RSP_WRITE:		// send the write acknowledge
+        {
+          if ( p_vci_tgt.rspack ) {
+            r_tgt_rsp_fsm = TGT_RSP_WRITE_IDLE;
+            r_write_to_tgt_rsp_req = false;
+          }
+          break;
+        }
+        ///////////////////
+      case TGT_RSP_CLEANUP:		// send the write acknowledge
+        {
+          if ( p_vci_tgt.rspack ) {
+            r_tgt_rsp_fsm = TGT_RSP_CLEANUP_IDLE;
+            r_cleanup_to_tgt_rsp_req = false;
+          }
+          break;
+        }
+        //////////////////
+      case TGT_RSP_LLSC:		// send one atomic word response
+        {
+          if ( p_vci_tgt.rspack ) {
+            r_tgt_rsp_fsm = TGT_RSP_LLSC_IDLE;
+            r_llsc_to_tgt_rsp_req = false;
+          }
+          break;
+        }
+
+        ///////////////////////
+      case TGT_RSP_XRAM:		// send the response
+        {
+          if ( p_vci_tgt.rspack ) {
+            if ( r_tgt_rsp_cpt.read() == (r_xram_rsp_to_tgt_rsp_word.read()+r_xram_rsp_to_tgt_rsp_length.read()-1)) {
+              r_tgt_rsp_fsm = TGT_RSP_XRAM_IDLE;
+              r_xram_rsp_to_tgt_rsp_req = false;
+            } else {
+              r_tgt_rsp_cpt = r_tgt_rsp_cpt.read() + 1;
+            }
+          }
+          break;
+        }
+        ///////////////////
+      case TGT_RSP_INIT:		// send the pending write acknowledge
+        {
+          if ( p_vci_tgt.rspack ) {
+            r_tgt_rsp_fsm = TGT_RSP_INIT_IDLE;
+            r_init_rsp_to_tgt_rsp_req = false;
+          }
+          break;
+        }
+    } // end switch tgt_rsp_fsm
+    ////////////////////////////////////////////////////////////////////////////////////
+    //		NEW ALLOC_UPT FSM
+    ////////////////////////////////////////////////////////////////////////////////////
+    // The ALLOC_UPT FSM allocates the access to the Update/Inval Table (UPT).
+    // with a round robin priority between three FSMs : INIT_RSP > WRITE > XRAM_RSP > CLEANUP 
+    // - The WRITE FSM initiates update transactions and sets  new entry in UPT.
+    // - The XRAM_RSP FSM initiates inval transactions and sets  new entry in UPT.
+    // - The INIT_RSP FSM complete those trasactions and erase the UPT entry.
+    // - The CLEANUP  FSM decrement an entry in UPT.
+    // The resource is always allocated.
+    /////////////////////////////////////////////////////////////////////////////////////
+
+    switch ( r_alloc_upt_fsm.read() ) {
+
+      ////////////////////////
+      case ALLOC_UPT_INIT_RSP:
+        if ( (r_init_rsp_fsm.read() != INIT_RSP_UPT_LOCK) && 
+             (r_init_rsp_fsm.read() != INIT_RSP_UPT_CLEAR) ) 
+        {
+          if      ((r_write_fsm.read() == WRITE_UPT_LOCK) ||
+                   (r_write_fsm.read() == WRITE_INVAL_LOCK))        r_alloc_upt_fsm = ALLOC_UPT_WRITE;
+          else if (r_xram_rsp_fsm.read() == XRAM_RSP_INVAL_LOCK)    r_alloc_upt_fsm = ALLOC_UPT_XRAM_RSP;
+          else if (r_cleanup_fsm.read() == CLEANUP_UPT_LOCK)        r_alloc_upt_fsm = ALLOC_UPT_CLEANUP;
+          else if ((r_llsc_fsm.read() == SC_UPT_LOCK) ||
+                   (r_llsc_fsm.read() == SC_INVAL_LOCK))            r_alloc_upt_fsm = ALLOC_UPT_LLSC;
+        }
+        break;
+
+        /////////////////////
+      case ALLOC_UPT_WRITE:
+        if ( (r_write_fsm.read() != WRITE_UPT_LOCK) &&
+             (r_write_fsm.read() != WRITE_INVAL_LOCK)) 
+        {
+          if      (r_xram_rsp_fsm.read() == XRAM_RSP_INVAL_LOCK)    r_alloc_upt_fsm = ALLOC_UPT_XRAM_RSP;
+          else if (r_cleanup_fsm.read() == CLEANUP_UPT_LOCK)        r_alloc_upt_fsm = ALLOC_UPT_CLEANUP;
+          else if ((r_llsc_fsm.read() == SC_UPT_LOCK) ||
+                   (r_llsc_fsm.read() == SC_INVAL_LOCK))            r_alloc_upt_fsm = ALLOC_UPT_LLSC;
+          else if (r_init_rsp_fsm.read() == INIT_RSP_UPT_LOCK)      r_alloc_upt_fsm = ALLOC_UPT_INIT_RSP;
+        }
+        break;
+
+        ////////////////////////
+      case ALLOC_UPT_XRAM_RSP:
+        if (r_xram_rsp_fsm.read() != XRAM_RSP_INVAL_LOCK) 
+        { 
+          if       (r_cleanup_fsm.read() == CLEANUP_UPT_LOCK)       r_alloc_upt_fsm = ALLOC_UPT_CLEANUP;
+          else if ((r_llsc_fsm.read() == SC_UPT_LOCK) ||
+                   (r_llsc_fsm.read() == SC_INVAL_LOCK))            r_alloc_upt_fsm = ALLOC_UPT_LLSC;
+          else if  (r_init_rsp_fsm.read() == INIT_RSP_UPT_LOCK)     r_alloc_upt_fsm = ALLOC_UPT_INIT_RSP;
+          else if ((r_write_fsm.read() == WRITE_UPT_LOCK)   ||
+                   (r_write_fsm.read() == WRITE_INVAL_LOCK))        r_alloc_upt_fsm = ALLOC_UPT_WRITE;
+        }
+        break;
+
+        //////////////////////////
+      case ALLOC_UPT_CLEANUP:
+        if(r_cleanup_fsm.read() != CLEANUP_UPT_LOCK )
+        {
+          if      ((r_llsc_fsm.read() == SC_UPT_LOCK) ||
+                   (r_llsc_fsm.read() == SC_INVAL_LOCK))            r_alloc_upt_fsm = ALLOC_UPT_LLSC;
+          else if  (r_init_rsp_fsm.read() == INIT_RSP_UPT_LOCK)     r_alloc_upt_fsm = ALLOC_UPT_INIT_RSP;
+          else if ((r_write_fsm.read() == WRITE_UPT_LOCK) ||
+                   (r_write_fsm.read() == WRITE_INVAL_LOCK))        r_alloc_upt_fsm = ALLOC_UPT_WRITE;
+          else if (r_xram_rsp_fsm.read() == XRAM_RSP_INVAL_LOCK)    r_alloc_upt_fsm = ALLOC_UPT_XRAM_RSP;
+        }
+        break;
+        
+        //////////////////////////
+      case ALLOC_UPT_LLSC:
+        if( (r_llsc_fsm.read() != SC_UPT_LOCK) && 
+            (r_llsc_fsm.read() != SC_INVAL_LOCK))
+        {
+          if      (r_init_rsp_fsm.read() == INIT_RSP_UPT_LOCK)      r_alloc_upt_fsm = ALLOC_UPT_INIT_RSP;
+          else if ((r_write_fsm.read() == WRITE_UPT_LOCK) ||
+                   (r_write_fsm.read() == WRITE_INVAL_LOCK))        r_alloc_upt_fsm = ALLOC_UPT_WRITE;
+          else if (r_xram_rsp_fsm.read() == XRAM_RSP_INVAL_LOCK)    r_alloc_upt_fsm = ALLOC_UPT_XRAM_RSP;
+          else if (r_cleanup_fsm.read() == CLEANUP_UPT_LOCK)        r_alloc_upt_fsm = ALLOC_UPT_CLEANUP;
+        }
+        break;
+
+    } // end switch r_alloc_upt_fsm
+
+    ////////////////////////////////////////////////////////////////////////////////////
+    //		ALLOC_DIR FSM
+    ////////////////////////////////////////////////////////////////////////////////////
+    // The ALLOC_DIR FSM allocates the access to the directory and
+    // the data cache with a round robin priority between 5 user FSMs :
+    // The cyclic ordering is READ > WRITE > LLSC > CLEANUP > XRAM_RSP
+    // The ressource is always allocated.
+    /////////////////////////////////////////////////////////////////////////////////////
+
+    switch ( r_alloc_dir_fsm.read() ) {
+
+      ////////////////////
+      case ALLOC_DIR_READ:
+        if ( ( (r_read_fsm.read() != READ_DIR_LOCK) &&
+              (r_read_fsm.read() != READ_TRT_LOCK)  &&
+              (r_read_fsm.read() != READ_HEAP_LOCK))
+            ||
+            ( (r_read_fsm.read()        == READ_HEAP_LOCK) &&
+              (r_alloc_heap_fsm.read()  == ALLOC_HEAP_READ) )
+            ||
+            ( (r_read_fsm.read()      == READ_TRT_LOCK)  &&
+              (r_alloc_trt_fsm.read() == ALLOC_TRT_READ)    )  ) 
+        {
+          if        (r_write_fsm.read() == WRITE_DIR_LOCK)          r_alloc_dir_fsm = ALLOC_DIR_WRITE;
+          else if   ((r_llsc_fsm.read() == LL_DIR_LOCK) || 
+                    (r_llsc_fsm.read() == SC_DIR_LOCK))             r_alloc_dir_fsm = ALLOC_DIR_LLSC;
+          else if   (r_cleanup_fsm.read() == CLEANUP_DIR_LOCK)      r_alloc_dir_fsm = ALLOC_DIR_CLEANUP;
+          else if   (r_xram_rsp_fsm.read() == XRAM_RSP_DIR_LOCK)    r_alloc_dir_fsm = ALLOC_DIR_XRAM_RSP;
+        }
+        break;
+
+        /////////////////////
+      case ALLOC_DIR_WRITE:
+        if ( ( (r_write_fsm.read() != WRITE_DIR_LOCK)     &&
+              (r_write_fsm.read() != WRITE_TRT_LOCK)     &&
+              (r_write_fsm.read() != WRITE_DIR_HIT_READ) &&
+              (r_write_fsm.read() != WRITE_DIR_HIT) &&
+              (r_write_fsm.read() != WRITE_TRT_WRITE_LOCK) &&
+              (r_write_fsm.read() != WRITE_INVAL_LOCK) &&
+              (r_write_fsm.read() != WRITE_UPT_LOCK) &&
+              (r_write_fsm.read() != WRITE_HEAP_LOCK))
+            ||
+            ( (r_write_fsm.read()       == WRITE_HEAP_LOCK) &&
+              (r_alloc_heap_fsm.read()  == ALLOC_HEAP_WRITE) )
+            ||
+            ( (r_write_fsm.read()     == WRITE_TRT_LOCK) &&
+              (r_alloc_trt_fsm.read() == ALLOC_TRT_WRITE)   )   )
+        {
+          if        ((r_llsc_fsm.read() == LL_DIR_LOCK) || 
+                    (r_llsc_fsm.read() == SC_DIR_LOCK))             r_alloc_dir_fsm = ALLOC_DIR_LLSC;
+          else if   (r_cleanup_fsm.read() == CLEANUP_DIR_LOCK)      r_alloc_dir_fsm = ALLOC_DIR_CLEANUP;
+          else if   (r_xram_rsp_fsm.read() == XRAM_RSP_DIR_LOCK)    r_alloc_dir_fsm = ALLOC_DIR_XRAM_RSP;
+          else if   (r_read_fsm.read() == READ_DIR_LOCK) 	        r_alloc_dir_fsm = ALLOC_DIR_READ;
+        }
+        break;
+
+        ////////////////////
+      case ALLOC_DIR_LLSC:
+        if ( ( (r_llsc_fsm.read() != LL_DIR_LOCK)    &&
+              (r_llsc_fsm.read() != LL_DIR_HIT )    &&
+              (r_llsc_fsm.read() != SC_DIR_LOCK)    &&
+              (r_llsc_fsm.read() != SC_DIR_HIT )    &&
+              (r_llsc_fsm.read() != LLSC_TRT_LOCK ) &&
+              (r_llsc_fsm.read() != SC_TRT_LOCK)    &&
+              (r_llsc_fsm.read() != SC_INVAL_LOCK)  &&
+              (r_llsc_fsm.read() != SC_UPT_LOCK)    &&
+              (r_llsc_fsm.read() != SC_HEAP_LOCK))
+            ||
+            ( (r_llsc_fsm.read()       == SC_HEAP_LOCK) &&
+              (r_alloc_heap_fsm.read() == ALLOC_HEAP_LLSC) )
+            ||
+            ( (r_llsc_fsm.read()      == LLSC_TRT_LOCK ) &&
+              (r_alloc_trt_fsm.read() == ALLOC_TRT_LLSC)    ) )
+        {
+          if      (r_cleanup_fsm.read() == CLEANUP_DIR_LOCK)    r_alloc_dir_fsm = ALLOC_DIR_CLEANUP;
+          else if (r_xram_rsp_fsm.read() == XRAM_RSP_DIR_LOCK)  r_alloc_dir_fsm = ALLOC_DIR_XRAM_RSP;
+          else if (r_read_fsm.read() == READ_DIR_LOCK) 	        r_alloc_dir_fsm = ALLOC_DIR_READ;
+          else if (r_write_fsm.read() == WRITE_DIR_LOCK)        r_alloc_dir_fsm = ALLOC_DIR_WRITE;
+        }
+        break;
+
+        ///////////////////////
+      case ALLOC_DIR_CLEANUP:
+        if ( (r_cleanup_fsm.read() != CLEANUP_DIR_LOCK) &&
+            (r_cleanup_fsm.read() != CLEANUP_HEAP_LOCK) )
+        {
+          if        (r_xram_rsp_fsm.read() == XRAM_RSP_DIR_LOCK)    r_alloc_dir_fsm = ALLOC_DIR_XRAM_RSP;
+          else if   (r_read_fsm.read() == READ_DIR_LOCK)            r_alloc_dir_fsm = ALLOC_DIR_READ;
+          else if   (r_write_fsm.read() == WRITE_DIR_LOCK)          r_alloc_dir_fsm = ALLOC_DIR_WRITE;
+          else if   ((r_llsc_fsm.read() == LL_DIR_LOCK) || 
+                    (r_llsc_fsm.read() == SC_DIR_LOCK))             r_alloc_dir_fsm = ALLOC_DIR_LLSC;
+        }
+        break;
+        ////////////////////////
+      case ALLOC_DIR_XRAM_RSP:
+        if ( (r_xram_rsp_fsm.read() != XRAM_RSP_DIR_LOCK)  &&
+            (r_xram_rsp_fsm.read() != XRAM_RSP_TRT_COPY)   && 
+            (r_xram_rsp_fsm.read() != XRAM_RSP_INVAL_LOCK))
+        {
+          if      (r_read_fsm.read() == READ_DIR_LOCK) 	        r_alloc_dir_fsm = ALLOC_DIR_READ;
+          else if (r_write_fsm.read() == WRITE_DIR_LOCK)        r_alloc_dir_fsm = ALLOC_DIR_WRITE;
+          else if ( (r_llsc_fsm.read() == LL_DIR_LOCK) || 
+                    (r_llsc_fsm.read() == SC_DIR_LOCK))         r_alloc_dir_fsm = ALLOC_DIR_LLSC;
+          else if (r_cleanup_fsm.read() == CLEANUP_DIR_LOCK)    r_alloc_dir_fsm = ALLOC_DIR_CLEANUP;
+        }
+        break;
+
+    } // end switch alloc_dir_fsm
+
+    ////////////////////////////////////////////////////////////////////////////////////
+    //		ALLOC_TRT FSM
+    ////////////////////////////////////////////////////////////////////////////////////
+    // The ALLOC_TRT fsm allocates the access to the Transaction Table (write buffer)
+    // with a round robin priority between 4 user FSMs :
+    // The cyclic priority is READ > WRITE > LLSC > XRAM_RSP
+    // The ressource is always allocated.
+    ///////////////////////////////////////////////////////////////////////////////////
+
+    switch (r_alloc_trt_fsm) {
+
+      ////////////////////
+      case ALLOC_TRT_READ:
+        if ( r_read_fsm.read() != READ_TRT_LOCK ) 
+        {
+          if      ((r_write_fsm.read() == WRITE_TRT_LOCK)   ||
+                   (r_write_fsm.read() == WRITE_TRT_WRITE_LOCK))    r_alloc_trt_fsm = ALLOC_TRT_WRITE;
+          else if ((r_llsc_fsm.read() == LLSC_TRT_LOCK) ||
+                   (r_llsc_fsm.read() == SC_TRT_LOCK))              r_alloc_trt_fsm = ALLOC_TRT_LLSC;
+          else if (r_xram_rsp_fsm.read() == XRAM_RSP_TRT_COPY)      r_alloc_trt_fsm = ALLOC_TRT_XRAM_RSP;
+          else if ( (r_ixr_rsp_fsm.read() == IXR_RSP_TRT_ERASE) ||
+                    (r_ixr_rsp_fsm.read() == IXR_RSP_TRT_READ) )    r_alloc_trt_fsm = ALLOC_TRT_IXR_RSP;
+        }
+        break;
+        /////////////////////
+      case ALLOC_TRT_WRITE:
+        if ( (r_write_fsm.read() != WRITE_TRT_LOCK) &&
+             (r_write_fsm.read() != WRITE_TRT_WRITE_LOCK) &&
+             (r_write_fsm.read() != WRITE_INVAL_LOCK)) 
+        {
+          if      ((r_llsc_fsm.read() == LLSC_TRT_LOCK) ||
+                   (r_llsc_fsm.read() == SC_TRT_LOCK))              r_alloc_trt_fsm = ALLOC_TRT_LLSC;
+          else if (r_xram_rsp_fsm.read() == XRAM_RSP_TRT_COPY)      r_alloc_trt_fsm = ALLOC_TRT_XRAM_RSP;
+          else if ( (r_ixr_rsp_fsm.read() == IXR_RSP_TRT_ERASE) ||
+                    (r_ixr_rsp_fsm.read() == IXR_RSP_TRT_READ))     r_alloc_trt_fsm = ALLOC_TRT_IXR_RSP;
+          else if (r_read_fsm.read() == READ_TRT_LOCK) 	            r_alloc_trt_fsm = ALLOC_TRT_READ;
+        }
+        break;
+        ////////////////////
+      case ALLOC_TRT_LLSC:
+        if ( (r_llsc_fsm.read() != LLSC_TRT_LOCK) &&
+             (r_llsc_fsm.read() != SC_TRT_LOCK) &&
+             (r_llsc_fsm.read() != SC_INVAL_LOCK))
+        { 
+          if      (r_xram_rsp_fsm.read() == XRAM_RSP_TRT_COPY)      r_alloc_trt_fsm = ALLOC_TRT_XRAM_RSP;
+          else if ( (r_ixr_rsp_fsm.read() == IXR_RSP_TRT_ERASE) ||
+                    (r_ixr_rsp_fsm.read() == IXR_RSP_TRT_READ))     r_alloc_trt_fsm = ALLOC_TRT_IXR_RSP;
+          else if (r_read_fsm.read() == READ_TRT_LOCK) 	            r_alloc_trt_fsm = ALLOC_TRT_READ;
+          else if ((r_write_fsm.read() == WRITE_TRT_LOCK)     ||
+                   (r_write_fsm.read() == WRITE_TRT_WRITE_LOCK))    r_alloc_trt_fsm = ALLOC_TRT_WRITE;
+        }
+        break;
+        ////////////////////////
+      case ALLOC_TRT_XRAM_RSP:
+        if ( (r_xram_rsp_fsm.read() != XRAM_RSP_TRT_COPY)  &&
+            (r_xram_rsp_fsm.read() != XRAM_RSP_DIR_UPDT)   &&
+            (r_xram_rsp_fsm.read() != XRAM_RSP_INVAL_LOCK)) {
+          if      ( (r_ixr_rsp_fsm.read() == IXR_RSP_TRT_ERASE) ||
+                    (r_ixr_rsp_fsm.read() == IXR_RSP_TRT_READ))     r_alloc_trt_fsm = ALLOC_TRT_IXR_RSP;
+          else if (r_read_fsm.read() == READ_TRT_LOCK) 	            r_alloc_trt_fsm = ALLOC_TRT_READ;
+          else if ((r_write_fsm.read() == WRITE_TRT_LOCK)    ||
+                   (r_write_fsm.read() == WRITE_TRT_WRITE_LOCK))    r_alloc_trt_fsm = ALLOC_TRT_WRITE;
+          else if ((r_llsc_fsm.read() == LLSC_TRT_LOCK) ||
+                   (r_llsc_fsm.read() == SC_TRT_LOCK))              r_alloc_trt_fsm = ALLOC_TRT_LLSC;
+        }
+        break;
+        ////////////////////////
+      case ALLOC_TRT_IXR_RSP:
+        if ( (r_ixr_rsp_fsm.read() != IXR_RSP_TRT_ERASE) &&
+            (r_ixr_rsp_fsm.read() != IXR_RSP_TRT_READ) ) {
+          if      (r_read_fsm.read() == READ_TRT_LOCK) 	            r_alloc_trt_fsm = ALLOC_TRT_READ;
+          else if ((r_write_fsm.read() == WRITE_TRT_LOCK)   ||
+                   (r_write_fsm.read() == WRITE_TRT_WRITE_LOCK))    r_alloc_trt_fsm = ALLOC_TRT_WRITE;
+          else if ((r_llsc_fsm.read() == LLSC_TRT_LOCK) ||
+                   (r_llsc_fsm.read() == SC_TRT_LOCK))              r_alloc_trt_fsm = ALLOC_TRT_LLSC;
+          else if (r_xram_rsp_fsm.read() == XRAM_RSP_TRT_COPY)      r_alloc_trt_fsm = ALLOC_TRT_XRAM_RSP;
+        }
+        break;
+
+    } // end switch alloc_trt_fsm
+
+    ////////////////////////////////////////////////////////////////////////////////////
+    //		ALLOC_HEAP FSM
+    ////////////////////////////////////////////////////////////////////////////////////
+    // The ALLOC_HEAP FSM allocates the access to the heap
+    // with a round robin priority between 5 user FSMs :
+    // The cyclic ordering is READ > WRITE > LLSC > CLEANUP > XRAM_RSP
+    // The ressource is always allocated.
+    /////////////////////////////////////////////////////////////////////////////////////
+
+    switch ( r_alloc_heap_fsm.read() ) {
+
+      ////////////////////
+      case ALLOC_HEAP_READ:
+        if (  (r_read_fsm.read() != READ_HEAP_LOCK) &&
+              (r_read_fsm.read() != READ_HEAP_ERASE)     ) 
+        {
+          if        ((r_write_fsm.read() == WRITE_HEAP_LOCK) ||         
+                     (r_write_fsm.read() == WRITE_HEAP_ERASE))      r_alloc_heap_fsm = ALLOC_HEAP_WRITE;
+          else if  ((r_llsc_fsm.read() == SC_HEAP_LOCK) || 
+                    (r_llsc_fsm.read() == SC_HEAP_ERASE))           r_alloc_heap_fsm = ALLOC_HEAP_LLSC;
+          else if   (r_cleanup_fsm.read() == CLEANUP_HEAP_LOCK)     r_alloc_heap_fsm = ALLOC_HEAP_CLEANUP;
+          else if   (r_xram_rsp_fsm.read() == XRAM_RSP_HEAP_ERASE)  r_alloc_heap_fsm = ALLOC_HEAP_XRAM_RSP;
+        }
+        break;
+
+        /////////////////////
+      case ALLOC_HEAP_WRITE:
+        if (  (r_write_fsm.read() != WRITE_HEAP_LOCK)   &&
+              (r_write_fsm.read() != WRITE_UPT_REQ)     &&
+              (r_write_fsm.read() != WRITE_UPDATE)      &&
+              (r_write_fsm.read() != WRITE_HEAP_ERASE))
+        {
+          if       ((r_llsc_fsm.read() == SC_HEAP_LOCK) || 
+                    (r_llsc_fsm.read() == SC_HEAP_ERASE))           r_alloc_heap_fsm = ALLOC_HEAP_LLSC;
+          else if   (r_cleanup_fsm.read() == CLEANUP_HEAP_LOCK)     r_alloc_heap_fsm = ALLOC_HEAP_CLEANUP;
+          else if   (r_xram_rsp_fsm.read() == XRAM_RSP_HEAP_ERASE)  r_alloc_heap_fsm = ALLOC_HEAP_XRAM_RSP;
+          else if   (r_read_fsm.read() == READ_HEAP_LOCK) 	        r_alloc_heap_fsm = ALLOC_HEAP_READ;
+        }
+        break;
+
+        ////////////////////
+      case ALLOC_HEAP_LLSC:
+        if (  (r_llsc_fsm.read() != SC_HEAP_LOCK)  &&
+              (r_llsc_fsm.read() != SC_UPT_REQ )    &&
+              (r_llsc_fsm.read() != SC_UPDATE)      &&
+              (r_llsc_fsm.read() != SC_HEAP_ERASE ) )
+        {
+          if      (r_cleanup_fsm.read() == CLEANUP_HEAP_LOCK)     r_alloc_heap_fsm = ALLOC_HEAP_CLEANUP;
+          else if (r_xram_rsp_fsm.read() == XRAM_RSP_HEAP_ERASE)  r_alloc_heap_fsm = ALLOC_HEAP_XRAM_RSP;
+          else if (r_read_fsm.read() == READ_HEAP_LOCK)           r_alloc_heap_fsm = ALLOC_HEAP_READ;
+          else if ((r_write_fsm.read() == WRITE_HEAP_LOCK) ||        
+                   (r_write_fsm.read() == WRITE_HEAP_ERASE))      r_alloc_heap_fsm = ALLOC_HEAP_WRITE;
+        }
+        break;
+
+        ///////////////////////
+      case ALLOC_HEAP_CLEANUP:
+        if ( (r_cleanup_fsm.read() != CLEANUP_HEAP_LOCK) &&
+            (r_cleanup_fsm.read() != CLEANUP_HEAP_SEARCH)&&
+            (r_cleanup_fsm.read() != CLEANUP_HEAP_CLEAN)    )
+        {
+          if        (r_xram_rsp_fsm.read() == XRAM_RSP_HEAP_ERASE)  r_alloc_heap_fsm = ALLOC_HEAP_XRAM_RSP;
+          else if   (r_read_fsm.read() == READ_HEAP_LOCK)           r_alloc_heap_fsm = ALLOC_HEAP_READ;
+          else if   ((r_write_fsm.read() == WRITE_HEAP_LOCK) ||        
+                     (r_write_fsm.read() == WRITE_HEAP_ERASE))      r_alloc_heap_fsm = ALLOC_HEAP_WRITE;
+          else if   ((r_llsc_fsm.read() == SC_HEAP_LOCK) || 
+                    (r_llsc_fsm.read() == SC_HEAP_ERASE))           r_alloc_heap_fsm = ALLOC_HEAP_LLSC;
+        }
+        break;
+        ////////////////////////
+      case ALLOC_HEAP_XRAM_RSP:
+        if ( r_xram_rsp_fsm.read() != XRAM_RSP_HEAP_ERASE )
+        {
+          if        (r_read_fsm.read() == READ_HEAP_LOCK) 	        r_alloc_heap_fsm = ALLOC_HEAP_READ;
+          else if   ((r_write_fsm.read() == WRITE_HEAP_LOCK) ||        
+                     (r_write_fsm.read() == WRITE_HEAP_ERASE))      r_alloc_heap_fsm = ALLOC_HEAP_WRITE;
+          else if   ( (r_llsc_fsm.read() == SC_HEAP_LOCK) || 
+                    (r_llsc_fsm.read() == SC_HEAP_ERASE))           r_alloc_heap_fsm = ALLOC_HEAP_LLSC;
+          else if   (r_cleanup_fsm.read() == CLEANUP_HEAP_LOCK)     r_alloc_heap_fsm = ALLOC_HEAP_CLEANUP;
+        }
+        break;
+
+    } // end switch alloc_heap_fsm
+
+
+    ////////////////////////////////////////////////////////////////////////////////////
+    //		TGT_CMD to READ FIFO
+    ////////////////////////////////////////////////////////////////////////////////////
+
+    if ( cmd_read_fifo_put ) {
+      if ( cmd_read_fifo_get ) {
+        m_cmd_read_addr_fifo.put_and_get((addr_t)(p_vci_tgt.address.read()));
+        m_cmd_read_length_fifo.put_and_get(p_vci_tgt.plen.read()>>2);
+        m_cmd_read_srcid_fifo.put_and_get(p_vci_tgt.srcid.read());
+        m_cmd_read_trdid_fifo.put_and_get(p_vci_tgt.trdid.read());
+        m_cmd_read_pktid_fifo.put_and_get(p_vci_tgt.pktid.read());
+      } else {
+        m_cmd_read_addr_fifo.simple_put((addr_t)(p_vci_tgt.address.read()));
+        m_cmd_read_length_fifo.simple_put(p_vci_tgt.plen.read()>>2);
+        m_cmd_read_srcid_fifo.simple_put(p_vci_tgt.srcid.read());
+        m_cmd_read_trdid_fifo.simple_put(p_vci_tgt.trdid.read());
+        m_cmd_read_pktid_fifo.simple_put(p_vci_tgt.pktid.read());
+      }
+    } else {
+      if ( cmd_read_fifo_get ) {
+        m_cmd_read_addr_fifo.simple_get();
+        m_cmd_read_length_fifo.simple_get();
+        m_cmd_read_srcid_fifo.simple_get();
+        m_cmd_read_trdid_fifo.simple_get();
+        m_cmd_read_pktid_fifo.simple_get();
+      }
+    }
+    /////////////////////////////////////////////////////////////////////
+    //		TGT_CMD to WRITE FIFO
+    /////////////////////////////////////////////////////////////////////
+
+    if ( cmd_write_fifo_put ) {
+      if ( cmd_write_fifo_get ) {
+        m_cmd_write_addr_fifo.put_and_get((addr_t)(p_vci_tgt.address.read()));
+        m_cmd_write_eop_fifo.put_and_get(p_vci_tgt.eop.read());
+        m_cmd_write_srcid_fifo.put_and_get(p_vci_tgt.srcid.read());
+        m_cmd_write_trdid_fifo.put_and_get(p_vci_tgt.trdid.read());
+        m_cmd_write_pktid_fifo.put_and_get(p_vci_tgt.pktid.read());
+        m_cmd_write_data_fifo.put_and_get(p_vci_tgt.wdata.read());
+        m_cmd_write_be_fifo.put_and_get(p_vci_tgt.be.read());
+      } else {
+        m_cmd_write_addr_fifo.simple_put((addr_t)(p_vci_tgt.address.read()));
+        m_cmd_write_eop_fifo.simple_put(p_vci_tgt.eop.read());
+        m_cmd_write_srcid_fifo.simple_put(p_vci_tgt.srcid.read());
+        m_cmd_write_trdid_fifo.simple_put(p_vci_tgt.trdid.read());
+        m_cmd_write_pktid_fifo.simple_put(p_vci_tgt.pktid.read());
+        m_cmd_write_data_fifo.simple_put(p_vci_tgt.wdata.read());
+        m_cmd_write_be_fifo.simple_put(p_vci_tgt.be.read());
+      }
+    } else {
+      if ( cmd_write_fifo_get ) {
+        m_cmd_write_addr_fifo.simple_get();
+        m_cmd_write_eop_fifo.simple_get();
+        m_cmd_write_srcid_fifo.simple_get();
+        m_cmd_write_trdid_fifo.simple_get();
+        m_cmd_write_pktid_fifo.simple_get();
+        m_cmd_write_data_fifo.simple_get();
+        m_cmd_write_be_fifo.simple_get();
+      }
+    }
+    ////////////////////////////////////////////////////////////////////////////////////
+    //		TGT_CMD to LLSC FIFO
+    ////////////////////////////////////////////////////////////////////////////////////
+
+    if ( cmd_llsc_fifo_put ) {
+      if ( cmd_llsc_fifo_get ) {
+        m_cmd_llsc_addr_fifo.put_and_get((addr_t)(p_vci_tgt.address.read()));
+        m_cmd_llsc_sc_fifo.put_and_get(p_vci_tgt.cmd.read() == vci_param::CMD_STORE_COND); 
+        m_cmd_llsc_srcid_fifo.put_and_get(p_vci_tgt.srcid.read());
+        m_cmd_llsc_trdid_fifo.put_and_get(p_vci_tgt.trdid.read());
+        m_cmd_llsc_pktid_fifo.put_and_get(p_vci_tgt.pktid.read());
+        m_cmd_llsc_wdata_fifo.put_and_get(p_vci_tgt.wdata.read());
+      } else {
+        m_cmd_llsc_addr_fifo.simple_put((addr_t)(p_vci_tgt.address.read()));
+        m_cmd_llsc_sc_fifo.simple_put(p_vci_tgt.cmd.read() == vci_param::CMD_STORE_COND); 
+        m_cmd_llsc_srcid_fifo.simple_put(p_vci_tgt.srcid.read());
+        m_cmd_llsc_trdid_fifo.simple_put(p_vci_tgt.trdid.read());
+        m_cmd_llsc_pktid_fifo.simple_put(p_vci_tgt.pktid.read());
+        m_cmd_llsc_wdata_fifo.simple_put(p_vci_tgt.wdata.read());
+      }
+    } else {
+      if ( cmd_llsc_fifo_get ) {
+        m_cmd_llsc_addr_fifo.simple_get();
+        m_cmd_llsc_sc_fifo.simple_get();
+        m_cmd_llsc_srcid_fifo.simple_get();
+        m_cmd_llsc_trdid_fifo.simple_get();
+        m_cmd_llsc_pktid_fifo.simple_get();
+        m_cmd_llsc_wdata_fifo.simple_get();
+      }
+    }
+    ////////////////////////////////////////////////////////////////////////////////////
+    //		WRITE to INIT_CMD FIFO
+    ////////////////////////////////////////////////////////////////////////////////////
+
+    if ( write_to_init_cmd_fifo_put ) {
+      if ( write_to_init_cmd_fifo_get ) {
+        m_write_to_init_cmd_inst_fifo.put_and_get(write_to_init_cmd_fifo_inst);
+        m_write_to_init_cmd_srcid_fifo.put_and_get(write_to_init_cmd_fifo_srcid);
+      } else {
+        m_write_to_init_cmd_inst_fifo.simple_put(write_to_init_cmd_fifo_inst);
+        m_write_to_init_cmd_srcid_fifo.simple_put(write_to_init_cmd_fifo_srcid);
+      }
+    } else {
+      if ( write_to_init_cmd_fifo_get ) {
+        m_write_to_init_cmd_inst_fifo.simple_get();
+        m_write_to_init_cmd_srcid_fifo.simple_get();
+      }
+    }
+    ////////////////////////////////////////////////////////////////////////////////////
+    //		XRAM_RSP to INIT_CMD FIFO
+    ////////////////////////////////////////////////////////////////////////////////////
+
+    if ( xram_rsp_to_init_cmd_fifo_put ) {
+      if ( xram_rsp_to_init_cmd_fifo_get ) {
+        m_xram_rsp_to_init_cmd_inst_fifo.put_and_get(xram_rsp_to_init_cmd_fifo_inst);
+        m_xram_rsp_to_init_cmd_srcid_fifo.put_and_get(xram_rsp_to_init_cmd_fifo_srcid);
+      } else {
+        m_xram_rsp_to_init_cmd_inst_fifo.simple_put(xram_rsp_to_init_cmd_fifo_inst);
+        m_xram_rsp_to_init_cmd_srcid_fifo.simple_put(xram_rsp_to_init_cmd_fifo_srcid);
+      }
+    } else {
+      if ( xram_rsp_to_init_cmd_fifo_get ) {
+        m_xram_rsp_to_init_cmd_inst_fifo.simple_get();
+        m_xram_rsp_to_init_cmd_srcid_fifo.simple_get();
+      }
+    }
+    ////////////////////////////////////////////////////////////////////////////////////
+    //		LLSC to INIT_CMD FIFO
+    ////////////////////////////////////////////////////////////////////////////////////
+
+    if ( llsc_to_init_cmd_fifo_put ) {
+      if ( llsc_to_init_cmd_fifo_get ) {
+        m_llsc_to_init_cmd_inst_fifo.put_and_get(llsc_to_init_cmd_fifo_inst);
+        m_llsc_to_init_cmd_srcid_fifo.put_and_get(llsc_to_init_cmd_fifo_srcid);
+      } else {
+        m_llsc_to_init_cmd_inst_fifo.simple_put(llsc_to_init_cmd_fifo_inst);
+        m_llsc_to_init_cmd_srcid_fifo.simple_put(llsc_to_init_cmd_fifo_srcid);
+      }
+    } else {
+      if ( llsc_to_init_cmd_fifo_get ) {
+        m_llsc_to_init_cmd_inst_fifo.simple_get();
+        m_llsc_to_init_cmd_srcid_fifo.simple_get();
+      }
+    }
+
+
+  //////////////////////////////////////////////////////////////
+    m_cpt_cycles++;
+    m_total_cycles++;
+
+    if((m_period != 0) && ((m_cpt_cycles % m_period) == 0))
+    {
+        print_log();
+        clear_stats();
+    }
+
+  } // end transition()
+
+  /////////////////////////////
+  tmpl(void)::genMoore()
+    /////////////////////////////
+  {
+    ////////////////////////////////////////////////////////////
+    // Command signals on the p_vci_ixr port
+    ////////////////////////////////////////////////////////////
+
+
+    p_vci_ixr.be      = 0xF;
+    p_vci_ixr.pktid   = 0;
+    p_vci_ixr.srcid   = m_srcid_ixr;
+    p_vci_ixr.cons    = false;
+    p_vci_ixr.wrap    = false;
+    p_vci_ixr.contig  = true;
+    p_vci_ixr.clen    = 0;
+    p_vci_ixr.cfixed  = false;
+
+    if ( r_ixr_cmd_fsm.read() == IXR_CMD_READ_NLINE ) {
+      p_vci_ixr.cmd     = vci_param::CMD_READ;
+      p_vci_ixr.cmdval  = true;
+      p_vci_ixr.address = (addr_t)(r_read_to_ixr_cmd_nline.read()*m_words*4);
+      p_vci_ixr.plen    = m_words*4;
+      p_vci_ixr.wdata   = 0x00000000;
+      p_vci_ixr.trdid   = r_read_to_ixr_cmd_trdid.read();
+      p_vci_ixr.eop     = true;
+    } 
+    else if ( r_ixr_cmd_fsm.read() == IXR_CMD_LLSC_NLINE ) {
+      if(r_llsc_to_ixr_cmd_write.read()){
+        p_vci_ixr.cmd     = vci_param::CMD_WRITE;
+        p_vci_ixr.cmdval  = true;
+        p_vci_ixr.address = (addr_t)((r_llsc_to_ixr_cmd_nline.read()*m_words+r_ixr_cmd_cpt.read())*4);
+        p_vci_ixr.plen    = m_words*4;
+        p_vci_ixr.wdata   = r_llsc_to_ixr_cmd_data[r_ixr_cmd_cpt.read()].read();
+        p_vci_ixr.trdid   = r_llsc_to_ixr_cmd_trdid.read();
+        p_vci_ixr.eop     = (r_ixr_cmd_cpt == (m_words-1));
+      } else {
+        p_vci_ixr.cmd     = vci_param::CMD_READ;
+        p_vci_ixr.cmdval  = true;
+        p_vci_ixr.address = (addr_t)(r_llsc_to_ixr_cmd_nline.read()*m_words*4);
+        p_vci_ixr.plen    = m_words*4;
+        p_vci_ixr.wdata   = 0x00000000;
+        p_vci_ixr.trdid   = r_llsc_to_ixr_cmd_trdid.read();
+        p_vci_ixr.eop     = true;
+      }
+    } 
+    else if ( r_ixr_cmd_fsm.read() == IXR_CMD_WRITE_NLINE ) {
+      if(r_write_to_ixr_cmd_write.read()){
+        p_vci_ixr.cmd     = vci_param::CMD_WRITE;
+        p_vci_ixr.cmdval  = true;
+        p_vci_ixr.address = (addr_t)((r_write_to_ixr_cmd_nline.read()*m_words+r_ixr_cmd_cpt.read())*4);
+        p_vci_ixr.plen    = m_words*4;
+        p_vci_ixr.wdata   = r_write_to_ixr_cmd_data[r_ixr_cmd_cpt.read()].read();
+        p_vci_ixr.trdid   = r_write_to_ixr_cmd_trdid.read();
+        p_vci_ixr.eop     = (r_ixr_cmd_cpt == (m_words-1));
+      } else {
+        p_vci_ixr.cmd     = vci_param::CMD_READ;
+        p_vci_ixr.cmdval  = true;
+        p_vci_ixr.address = (addr_t)(r_write_to_ixr_cmd_nline.read()*m_words*4);
+        p_vci_ixr.plen    = m_words*4;
+        p_vci_ixr.wdata   = 0x00000000;
+        p_vci_ixr.trdid   = r_write_to_ixr_cmd_trdid.read();
+        p_vci_ixr.eop     = true;
+      }
+    } 
+    else if ( r_ixr_cmd_fsm.read() == IXR_CMD_XRAM_DATA ) {
+      p_vci_ixr.cmd     = vci_param::CMD_WRITE;
+      p_vci_ixr.cmdval  = true;
+      p_vci_ixr.address = (addr_t)((r_xram_rsp_to_ixr_cmd_nline.read()*m_words+r_ixr_cmd_cpt.read())*4);
+      p_vci_ixr.plen    = m_words*4;
+      p_vci_ixr.wdata   = r_xram_rsp_to_ixr_cmd_data[r_ixr_cmd_cpt.read()].read();
+      p_vci_ixr.trdid   = r_xram_rsp_to_ixr_cmd_trdid.read();
+      p_vci_ixr.eop     = (r_ixr_cmd_cpt == (m_words-1));
+    } else {
+      p_vci_ixr.cmdval  = false;
+      p_vci_ixr.address = 0;
+      p_vci_ixr.plen    = 0;
+      p_vci_ixr.wdata   = 0;
+      p_vci_ixr.trdid   = 0;
+      p_vci_ixr.eop	= false;
+    }
+
+    ////////////////////////////////////////////////////
+    // Response signals on the p_vci_ixr port
+    ////////////////////////////////////////////////////
+
+    if ( ((r_alloc_trt_fsm.read() == ALLOC_TRT_IXR_RSP) &&
+          (r_ixr_rsp_fsm.read() == IXR_RSP_TRT_READ)) || 
+        (r_ixr_rsp_fsm.read() == IXR_RSP_ACK) ) p_vci_ixr.rspack = true;
+    else                                        p_vci_ixr.rspack = false;
+
+    ////////////////////////////////////////////////////
+    // Command signals on the p_vci_tgt port
+    ////////////////////////////////////////////////////
+
+    switch ((tgt_cmd_fsm_state_e)r_tgt_cmd_fsm.read()) {
+      case TGT_CMD_IDLE:
+        p_vci_tgt.cmdack  = false;
+        break;
+      case TGT_CMD_READ:
+        p_vci_tgt.cmdack  = m_cmd_read_addr_fifo.wok();
+        break;
+      case TGT_CMD_READ_EOP:
+        p_vci_tgt.cmdack  = true;
+        break;
+      case TGT_CMD_WRITE:
+        p_vci_tgt.cmdack  = m_cmd_write_addr_fifo.wok();
+        break;
+      case TGT_CMD_ATOMIC:
+        p_vci_tgt.cmdack  = m_cmd_llsc_addr_fifo.wok();
+        break;
+      default:
+        p_vci_tgt.cmdack = false;
+        break;
+    }
+
+    ////////////////////////////////////////////////////
+    // Response signals on the p_vci_tgt port
+    ////////////////////////////////////////////////////
+    switch ( r_tgt_rsp_fsm.read() ) {
+
+      case TGT_RSP_READ_IDLE:
+      case TGT_RSP_WRITE_IDLE:
+      case TGT_RSP_LLSC_IDLE:
+      case TGT_RSP_XRAM_IDLE:
+      case TGT_RSP_INIT_IDLE:
+      case TGT_RSP_CLEANUP_IDLE:
+        p_vci_tgt.rspval  = false;
+        p_vci_tgt.rsrcid  = 0;
+        p_vci_tgt.rdata   = 0;
+        p_vci_tgt.rpktid  = 0;
+        p_vci_tgt.rtrdid  = 0;
+        p_vci_tgt.rerror  = 0;
+        p_vci_tgt.reop    = false;	
+        break;
+      case TGT_RSP_READ:
+        p_vci_tgt.rspval   = true;
+        p_vci_tgt.rdata    = r_read_to_tgt_rsp_data[r_tgt_rsp_cpt.read()].read();
+        p_vci_tgt.rsrcid   = r_read_to_tgt_rsp_srcid.read();
+        p_vci_tgt.rtrdid   = r_read_to_tgt_rsp_trdid.read();
+        p_vci_tgt.rpktid   = r_read_to_tgt_rsp_pktid.read();
+        p_vci_tgt.rerror   = 0;
+        p_vci_tgt.reop     = ( r_tgt_rsp_cpt.read() == (r_read_to_tgt_rsp_word.read()+r_read_to_tgt_rsp_length-1) );
+        break;
+      case TGT_RSP_WRITE:
+        p_vci_tgt.rspval   = true;
+        p_vci_tgt.rdata    = 0;
+        p_vci_tgt.rsrcid   = r_write_to_tgt_rsp_srcid.read();
+        p_vci_tgt.rtrdid   = r_write_to_tgt_rsp_trdid.read();
+        p_vci_tgt.rpktid   = r_write_to_tgt_rsp_pktid.read();
+        p_vci_tgt.rerror   = 0x2 & ( (1 << vci_param::E) - 1); // Write OK
+        p_vci_tgt.reop     = true;
+        break;
+      case TGT_RSP_CLEANUP:
+        p_vci_tgt.rspval   = true;
+        p_vci_tgt.rdata    = 0;
+        p_vci_tgt.rsrcid   = r_cleanup_to_tgt_rsp_srcid.read();
+        p_vci_tgt.rtrdid   = r_cleanup_to_tgt_rsp_trdid.read();
+        p_vci_tgt.rpktid   = r_cleanup_to_tgt_rsp_pktid.read();
+        p_vci_tgt.rerror   = 0;
+        p_vci_tgt.reop     = true;
+        break;
+      case TGT_RSP_LLSC:
+        p_vci_tgt.rspval   = true;
+        p_vci_tgt.rdata    = r_llsc_to_tgt_rsp_data.read();
+        p_vci_tgt.rsrcid   = r_llsc_to_tgt_rsp_srcid.read();
+        p_vci_tgt.rtrdid   = r_llsc_to_tgt_rsp_trdid.read();
+        p_vci_tgt.rpktid   = r_llsc_to_tgt_rsp_pktid.read();
+        p_vci_tgt.rerror   = 0;
+        p_vci_tgt.reop     = true;
+        break;
+      case TGT_RSP_XRAM:
+        p_vci_tgt.rspval   = true;
+        p_vci_tgt.rdata    = r_xram_rsp_to_tgt_rsp_data[r_tgt_rsp_cpt.read()].read();
+        p_vci_tgt.rsrcid   = r_xram_rsp_to_tgt_rsp_srcid.read();
+        p_vci_tgt.rtrdid   = r_xram_rsp_to_tgt_rsp_trdid.read();
+        p_vci_tgt.rpktid   = r_xram_rsp_to_tgt_rsp_pktid.read();
+        p_vci_tgt.rerror   = 0;
+        p_vci_tgt.reop     = ( r_tgt_rsp_cpt.read() == (r_xram_rsp_to_tgt_rsp_word.read()+r_xram_rsp_to_tgt_rsp_length.read()-1));
+        break;
+      case TGT_RSP_INIT:
+        p_vci_tgt.rspval   = true;
+        p_vci_tgt.rdata    = 0;
+        p_vci_tgt.rsrcid   = r_init_rsp_to_tgt_rsp_srcid.read();
+        p_vci_tgt.rtrdid   = r_init_rsp_to_tgt_rsp_trdid.read();
+        p_vci_tgt.rpktid   = r_init_rsp_to_tgt_rsp_pktid.read();
+        p_vci_tgt.rerror   = 0;
+        p_vci_tgt.reop     = true;	
+        break;
+    } // end switch r_tgt_rsp_fsm
+
+    ///////////////////////////////////////////////////
+    // Command signals on the p_vci_ini port
+    ///////////////////////////////////////////////////
+
+    p_vci_ini.cmd     = vci_param::CMD_WRITE;
+    p_vci_ini.srcid   = m_srcid_ini;
+    p_vci_ini.pktid   = 0;
+    p_vci_ini.cons    = true;
+    p_vci_ini.wrap    = false;
+    p_vci_ini.contig  = false;
+    p_vci_ini.clen    = 0;
+    p_vci_ini.cfixed  = false;
+
+    switch ( r_init_cmd_fsm.read() ) {
+
+      case INIT_CMD_UPDT_IDLE:
+      case INIT_CMD_INVAL_IDLE:
+      case INIT_CMD_SC_UPDT_IDLE:
+        p_vci_ini.cmdval  = false;
+        p_vci_ini.address = 0;
+        p_vci_ini.wdata   = 0;
+        p_vci_ini.be      = 0;
+        p_vci_ini.plen    = 0;
+        p_vci_ini.trdid   = 0;
+        p_vci_ini.eop     = false;
+        break;
+      case INIT_CMD_INVAL_NLINE:
+        p_vci_ini.cmdval  = m_xram_rsp_to_init_cmd_inst_fifo.rok();
+        if(m_xram_rsp_to_init_cmd_inst_fifo.rok()){
+          if(m_xram_rsp_to_init_cmd_inst_fifo.read()) {
+            p_vci_ini.address = (addr_t)(m_coherence_table[m_xram_rsp_to_init_cmd_srcid_fifo.read()]+8);
+          } else {
+            p_vci_ini.address = (addr_t)(m_coherence_table[m_xram_rsp_to_init_cmd_srcid_fifo.read()]);
+          }
+        } else p_vci_ini.address = 0; // prevent segmentation faults by reading an empty fifo
+        p_vci_ini.wdata   = (uint32_t)r_xram_rsp_to_init_cmd_nline.read();
+        p_vci_ini.be      = ((r_xram_rsp_to_init_cmd_nline.read() >> 32) & 0x3);
+        p_vci_ini.plen    = 4;
+        p_vci_ini.trdid   = r_xram_rsp_to_init_cmd_trdid.read();
+        p_vci_ini.eop     = true;
+        break;
+      case INIT_CMD_XRAM_BRDCAST:
+        p_vci_ini.cmdval  = true;
+        p_vci_ini.address = broadcast_addr;
+        p_vci_ini.wdata   = (uint32_t)r_xram_rsp_to_init_cmd_nline.read();
+        p_vci_ini.be      = ((r_xram_rsp_to_init_cmd_nline.read() >> 32) & 0x3);
+        p_vci_ini.plen    = 4;
+        p_vci_ini.trdid   = r_xram_rsp_to_init_cmd_trdid.read();
+        p_vci_ini.eop     = true;
+        break;
+
+      case INIT_CMD_WRITE_BRDCAST:
+        p_vci_ini.cmdval  = true;
+        p_vci_ini.address = broadcast_addr;
+        p_vci_ini.wdata   = (addr_t)r_write_to_init_cmd_nline.read();
+        p_vci_ini.be      = ((r_write_to_init_cmd_nline.read() >> 32) & 0x3);
+        p_vci_ini.plen    = 4 ;
+        p_vci_ini.eop     = true;
+        p_vci_ini.trdid   = r_write_to_init_cmd_trdid.read();
+        break;
+      case INIT_CMD_UPDT_NLINE:
+        p_vci_ini.cmdval  = m_write_to_init_cmd_inst_fifo.rok();
+        if(m_write_to_init_cmd_inst_fifo.rok()){
+          p_vci_ini.address = (addr_t)(m_coherence_table[m_write_to_init_cmd_srcid_fifo.read()] + 4);
+        } else {
+          p_vci_ini.address = 0;
+        }
+        p_vci_ini.wdata   = (uint32_t)r_write_to_init_cmd_nline.read();
+        p_vci_ini.be      = ((r_write_to_init_cmd_nline.read() >> 32 ) & 0x3);
+        p_vci_ini.plen    = 4 * (r_write_to_init_cmd_count.read() + 2);
+        p_vci_ini.eop     = false;
+        p_vci_ini.trdid   = r_write_to_init_cmd_trdid.read();
+        break;
+      case INIT_CMD_UPDT_INDEX:
+        p_vci_ini.cmdval  = true;
+        p_vci_ini.address = (addr_t)(m_coherence_table[m_write_to_init_cmd_srcid_fifo.read()] + 4);
+        p_vci_ini.wdata   = r_write_to_init_cmd_index.read();
+        p_vci_ini.be      = 0xF;
+        p_vci_ini.plen    = 4 * (r_write_to_init_cmd_count.read() + 2);
+        p_vci_ini.trdid   = r_write_to_init_cmd_trdid.read();
+        p_vci_ini.eop     = false;
+        break;
+      case INIT_CMD_UPDT_DATA:
+        p_vci_ini.cmdval  = true;
+        p_vci_ini.address = (addr_t)(m_coherence_table[m_write_to_init_cmd_srcid_fifo.read()] + 4);
+        p_vci_ini.wdata   = r_write_to_init_cmd_data[r_init_cmd_cpt.read() +
+          r_write_to_init_cmd_index.read()].read();
+        if(r_write_to_init_cmd_we[r_init_cmd_cpt.read() +
+            r_write_to_init_cmd_index.read()].read())  
+          p_vci_ini.be      = 0xF;
+        else			p_vci_ini.be      = 0x0;
+        p_vci_ini.plen    = 4 * (r_write_to_init_cmd_count.read() + 2);
+        p_vci_ini.trdid   = r_write_to_init_cmd_trdid.read();
+        p_vci_ini.eop     = ( r_init_cmd_cpt.read() == (r_write_to_init_cmd_count.read()-1) );
+        break;
+
+      case INIT_CMD_SC_BRDCAST:
+        p_vci_ini.cmdval  = true;
+        p_vci_ini.address = broadcast_addr;
+        p_vci_ini.wdata   = (addr_t)r_llsc_to_init_cmd_nline.read();
+        p_vci_ini.be      = ((r_llsc_to_init_cmd_nline.read() >> 32) & 0x3);
+        p_vci_ini.plen    = 4 ;
+        p_vci_ini.eop     = true;
+        p_vci_ini.trdid   = r_llsc_to_init_cmd_trdid.read();
+        break;
+      case INIT_CMD_SC_UPDT_NLINE:
+        p_vci_ini.cmdval  = m_llsc_to_init_cmd_inst_fifo.rok();
+        if(m_llsc_to_init_cmd_inst_fifo.rok()){
+          p_vci_ini.address = (addr_t)(m_coherence_table[m_llsc_to_init_cmd_srcid_fifo.read()] + 4);
+        } else {
+          p_vci_ini.address = 0;
+        }
+        p_vci_ini.wdata   = (uint32_t)r_llsc_to_init_cmd_nline.read();
+        p_vci_ini.be      = ((r_llsc_to_init_cmd_nline.read() >> 32 ) & 0x3);
+        p_vci_ini.plen    = 4 * 3;
+        p_vci_ini.eop     = false;
+        p_vci_ini.trdid   = r_llsc_to_init_cmd_trdid.read();
+        break;
+      case INIT_CMD_SC_UPDT_INDEX:
+        p_vci_ini.cmdval  = true;
+        p_vci_ini.address = (addr_t)(m_coherence_table[m_llsc_to_init_cmd_srcid_fifo.read()] + 4);
+        p_vci_ini.wdata   = r_llsc_to_init_cmd_index.read();
+        p_vci_ini.be      = 0xF;
+        p_vci_ini.plen    = 4 * 3;
+        p_vci_ini.trdid   = r_llsc_to_init_cmd_trdid.read();
+        p_vci_ini.eop     = false;
+        break;
+      case INIT_CMD_SC_UPDT_DATA:
+        p_vci_ini.cmdval  = true;
+        p_vci_ini.address = (addr_t)(m_coherence_table[m_llsc_to_init_cmd_srcid_fifo.read()] + 4);
+        p_vci_ini.wdata   = r_llsc_to_init_cmd_wdata.read();
+        p_vci_ini.be      = 0xF;
+        p_vci_ini.plen    = 4 * 3;
+        p_vci_ini.trdid   = r_llsc_to_init_cmd_trdid.read();
+        p_vci_ini.eop     = true;
+        break;
+
+    } // end switch r_init_cmd_fsm
+
+    //////////////////////////////////////////////////////
+    // Response signals on the p_vci_ini port
+    //////////////////////////////////////////////////////
+
+    if ( r_init_rsp_fsm.read() == INIT_RSP_IDLE ) p_vci_ini.rspack  = true;
+    else                                          p_vci_ini.rspack  = false;
+
+    //////////////////////////////////////////////////////
+    // Response signals on the p_vci_tgt_cleanup port
+    //////////////////////////////////////////////////////
+    p_vci_tgt_cleanup.rspval = false;
+    p_vci_tgt_cleanup.rsrcid = 0;
+    p_vci_tgt_cleanup.rdata  = 0;
+    p_vci_tgt_cleanup.rpktid = 0;
+    p_vci_tgt_cleanup.rtrdid = 0;
+    p_vci_tgt_cleanup.rerror = 0;
+    p_vci_tgt_cleanup.reop   = false;
+    p_vci_tgt_cleanup.cmdack = false ;
+
+    switch(r_cleanup_fsm.read()){
+      case CLEANUP_IDLE:
+        {
+          p_vci_tgt_cleanup.cmdack = true ;
+          break;
+        }
+      case CLEANUP_RSP:
+        {
+          p_vci_tgt_cleanup.rspval = true;
+          p_vci_tgt_cleanup.rdata  = 0;
+          p_vci_tgt_cleanup.rsrcid = r_cleanup_srcid.read();
+          p_vci_tgt_cleanup.rpktid = r_cleanup_pktid.read();
+          p_vci_tgt_cleanup.rtrdid = r_cleanup_trdid.read();
+          p_vci_tgt_cleanup.rerror = 0x2 & ( (1 << vci_param::E) - 1);
+          p_vci_tgt_cleanup.reop   = 1;
+          break;
+        }
+
+    }
+
+  } // end genMoore()
+
+}} // end name space
+
+// Local Variables:
+// tab-width: 4
+// c-basic-offset: 4
+// c-file-offsets:((innamespace . 0)(inline-open . 0))
+// indent-tabs-mode: nil
+// End:
+
+// vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4
+
Index: branches/v4/platforms/almos-tsarv3-platforms/common/vci_vdspin_initiator_wrapper/caba/metadata/vci_vdspin_initiator_wrapper.sd
===================================================================
--- branches/v4/platforms/almos-tsarv3-platforms/common/vci_vdspin_initiator_wrapper/caba/metadata/vci_vdspin_initiator_wrapper.sd	(revision 371)
+++ branches/v4/platforms/almos-tsarv3-platforms/common/vci_vdspin_initiator_wrapper/caba/metadata/vci_vdspin_initiator_wrapper.sd	(revision 371)
@@ -0,0 +1,25 @@
+
+# -*- python -*-
+
+Module('caba:vci_vdspin_initiator_wrapper',
+		classname = 'soclib::caba::VciVdspinInitiatorWrapper',
+	tmpl_parameters = [
+		parameter.Module('vci_param',  default = 'caba:vci_param'),
+		parameter.Int('dspin_cmd_width'),
+		parameter.Int('dspin_rsp_width'), ],
+        header_files = ['../source/include/vci_vdspin_initiator_wrapper.h', ],
+        implementation_files = ['../source/src/vci_vdspin_initiator_wrapper.cpp',],
+        ports = [
+		Port('caba:vci_initiator', 'p_vci'),
+                Port('caba:dspin_output', 'p_dspin_out', dspin_data_size = parameter.Reference('dspin_cmd_width')),
+                Port('caba:dspin_input', 'p_dspin_in', dspin_data_size = parameter.Reference('dspin_rsp_width')),
+		Port('caba:bit_in', 'p_resetn', auto = 'resetn'),
+		Port('caba:clock_in', 'p_clk', auto = 'clock'), ],
+	uses = [
+		Uses('caba:base_module'),
+		Uses('caba:generic_fifo'),
+		],
+	instance_parameters = [
+		parameter.Int('cmd_fifo_depth'),
+		parameter.Int('rsp_fifo_depth'), ],
+)
Index: branches/v4/platforms/almos-tsarv3-platforms/common/vci_vdspin_initiator_wrapper/caba/source/include/vci_vdspin_initiator_wrapper.h
===================================================================
--- branches/v4/platforms/almos-tsarv3-platforms/common/vci_vdspin_initiator_wrapper/caba/source/include/vci_vdspin_initiator_wrapper.h	(revision 371)
+++ branches/v4/platforms/almos-tsarv3-platforms/common/vci_vdspin_initiator_wrapper/caba/source/include/vci_vdspin_initiator_wrapper.h	(revision 371)
@@ -0,0 +1,125 @@
+/* -*- c++ -*-
+  * File : vci_vdspin_initiator_wrapper.h
+  * Copyright (c) UPMC, Lip6
+  * Author : Alain Greiner
+  *
+  * SOCLIB_LGPL_HEADER_BEGIN
+  * 
+  * This file is part of SoCLib, GNU LGPLv2.1.
+  * 
+  * SoCLib is free software; you can redistribute it and/or modify it
+  * under the terms of the GNU Lesser General Public License as published
+  * by the Free Software Foundation; version 2.1 of the License.
+  * 
+  * SoCLib is distributed in the hope that it will be useful, but
+  * WITHOUT ANY WARRANTY; without even the implied warranty of
+  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+  * Lesser General Public License for more details.
+  * 
+  * You should have received a copy of the GNU Lesser General Public
+  * License along with SoCLib; if not, write to the Free Software
+  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+  * 02110-1301 USA
+  * 
+  * SOCLIB_LGPL_HEADER_END
+  */
+
+/////////////////////////////////////////////////////////////////////////
+// This component performs the protocol translation between VCI & DSPIN,
+// and can be used to connect a VCI initiator to a DSPIN network.
+// It is implemented as two fully independant sub-components:
+// - translation from a VCI CMD to a DSPIN CMD
+// - translation from a DSPIN RSP to a VCI RSP
+// Each subcomponent contains a FIFO containing DSPIN flits.
+// For the DSPIN interfaces, the widths of the CMD & RSP flits
+// are defined as template parameters for future evolutions,
+// but the VCI to DSPIN translation makes the following assumptions:
+// - DSPIN CMD flit width = 40 bits
+// - DSPIN RSP flit width = 33 bits
+// - VCI address width    <= 40 bits
+// - VCI data             == 32 bits
+// - VCI plen             == 8  bits
+// - VCI srcid            <= 14 bits
+// - VCI trdid            <= 8  bits
+// - VCI pktid field not transmitted
+// - VCI rerror           == 2 bits
+////////////////////////////////////////////////////////////////////////
+
+#ifndef VCI_VDSPIN_INITIATOR_WRAPPER_H_
+#define VCI_VDSPIN_INITIATOR_WRAPPER_H_
+
+#include <systemc>
+#include <assert.h>
+#include "caba_base_module.h"
+#include "vci_target.h"
+#include "generic_fifo.h"
+#include "dspin_interface.h"
+
+namespace soclib { namespace caba {
+
+template<typename vci_param, int dspin_cmd_width, int dspin_rsp_width>
+class VciVdspinInitiatorWrapper
+	: public soclib::caba::BaseModule
+{
+    // Command FSM 
+    enum fsm_state_cmd{
+	CMD_IDLE,
+	CMD_BROADCAST,
+	CMD_READ,
+	CMD_WRITE,
+	CMD_WDATA,
+    };
+
+    // Response FSM
+    enum fsm_state_rsp{
+	RSP_IDLE,
+	RSP_READ,		
+	RSP_WRITE,	
+    };
+
+protected:
+    SC_HAS_PROCESS(VciVdspinInitiatorWrapper);
+
+public:
+    // ports
+    sc_core::sc_in<bool>                             		p_clk;
+    sc_core::sc_in<bool>                             		p_resetn;
+    soclib::caba::DspinOutput<dspin_cmd_width>			p_dspin_out;
+    soclib::caba::DspinInput<dspin_rsp_width>			p_dspin_in;
+    soclib::caba::VciTarget<vci_param>      			p_vci;
+
+    // constructor / destructor
+    VciVdspinInitiatorWrapper(	sc_module_name 			name, 
+				size_t				cmd_fifo_depth,
+				size_t				rsp_fifo_depth);
+private:
+    // internal registers
+    sc_core::sc_signal<int>        				r_cmd_fsm;
+    sc_core::sc_signal<int>        				r_rsp_fsm;
+    sc_core::sc_signal<sc_uint<dspin_rsp_width>	>		r_rsp_buf;
+
+    // fifos cmd and rsp
+    soclib::caba::GenericFifo<sc_uint<dspin_cmd_width> >  	r_fifo_cmd;
+    soclib::caba::GenericFifo<sc_uint<dspin_rsp_width> >  	r_fifo_rsp;
+
+    // methods systemc
+    void transition();
+    void genMoore();
+
+public:
+    void print_trace();
+
+};
+
+}} // end namespace
+               
+#endif // VCI_VDSPIN_INITIATOR_WRAPPER_H_
+
+// Local Variables:
+// tab-width: 4
+// c-basic-offset: 4
+// c-file-offsets:((innamespace . 0)(inline-open . 0))
+// indent-tabs-mode: nil
+// End:
+
+// vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4
Index: branches/v4/platforms/almos-tsarv3-platforms/common/vci_vdspin_initiator_wrapper/caba/source/src/vci_vdspin_initiator_wrapper.cpp
===================================================================
--- branches/v4/platforms/almos-tsarv3-platforms/common/vci_vdspin_initiator_wrapper/caba/source/src/vci_vdspin_initiator_wrapper.cpp	(revision 371)
+++ branches/v4/platforms/almos-tsarv3-platforms/common/vci_vdspin_initiator_wrapper/caba/source/src/vci_vdspin_initiator_wrapper.cpp	(revision 371)
@@ -0,0 +1,351 @@
+/* -*- c++ -*-
+  * File : vci_vdspin_initiator_wrapper.cpp
+  * Copyright (c) UPMC, Lip6
+  * Authors : Alain Greiner
+  *
+  * SOCLIB_LGPL_HEADER_BEGIN
+  * 
+  * This file is part of SoCLib, GNU LGPLv2.1.
+  * 
+  * SoCLib is free software; you can redistribute it and/or modify it
+  * under the terms of the GNU Lesser General Public License as published
+  * by the Free Software Foundation; version 2.1 of the License.
+  * 
+  * SoCLib is distributed in the hope that it will be useful, but
+  * WITHOUT ANY WARRANTY; without even the implied warranty of
+  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+  * Lesser General Public License for more details.
+  * 
+  * You should have received a copy of the GNU Lesser General Public
+  * License along with SoCLib; if not, write to the Free Software
+  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+  * 02110-1301 USA
+  * 
+  * SOCLIB_LGPL_HEADER_END
+  */
+
+#include "../include/vci_vdspin_initiator_wrapper.h"
+
+namespace soclib { namespace caba {
+
+#define tmpl(x) template<typename vci_param, int dspin_cmd_width, int dspin_rsp_width> x VciVdspinInitiatorWrapper<vci_param, dspin_cmd_width, dspin_rsp_width>
+
+//////////////////////////////////////////////////////////:////////////////////////////////
+tmpl(/**/)::VciVdspinInitiatorWrapper(sc_module_name 			name,
+				      size_t				cmd_fifo_depth,
+				      size_t				rsp_fifo_depth)
+	       : soclib::caba::BaseModule(name),
+                 p_clk("p_clk"),
+                 p_resetn("p_resetn"),
+                 p_dspin_out("p_dspin_out"),
+                 p_dspin_in("p_dspin_in"),
+                 p_vci("p_vci"),
+                 r_cmd_fsm("r_cmd_fsm"),
+                 r_rsp_fsm("r_rsp_fsm"),
+	         r_fifo_cmd("r_fifo_cmd", cmd_fifo_depth),
+	         r_fifo_rsp("r_fifo_rsp", rsp_fifo_depth)
+    {
+	SC_METHOD (transition);
+	dont_initialize();
+	sensitive << p_clk.pos();
+	SC_METHOD (genMoore);
+	dont_initialize();
+	sensitive  << p_clk.neg();
+
+        assert( (dspin_cmd_width == 40) && "The DSPIN CMD flit width must have 40 bits");
+        assert( (dspin_rsp_width == 33) && "The DSPIN RSP flit width must have 33 bits");
+        assert( (vci_param::N    <= 40) && "The VCI ADDRESS field cannot have more than 40 bits"); 
+        assert( (vci_param::B    == 4) && "The VCI DATA filds must have 32 bits");
+        assert( (vci_param::K    == 8) && "The VCI PLEN field cannot have more than 8 bits");
+        assert( (vci_param::S    <= 14) && "The VCI SRCID field cannot have more than 8 bits");
+        assert( (vci_param::T    <= 8) && "The VCI TRDID field cannot have more than 8 bits");
+        //assert( (vci_param::E    == 2) && "The VCI RERROR field cannot have more than 2 bits");
+
+    } //  end constructor
+
+/////////////////////////
+tmpl(void)::transition()
+{
+	sc_uint<dspin_cmd_width>	cmd_fifo_data;
+	bool				cmd_fifo_write;
+	bool				cmd_fifo_read;
+
+	sc_uint<dspin_rsp_width>	rsp_fifo_data;
+	bool				rsp_fifo_write;
+	bool				rsp_fifo_read;
+
+	if (p_resetn == false) 
+        {
+	    r_fifo_cmd.init();
+	    r_fifo_rsp.init();
+	    r_cmd_fsm = CMD_IDLE;
+	    r_rsp_fsm = RSP_IDLE;
+	    return;
+	} // end reset
+
+        /////////////////////////////////////////////////////////////
+	// VCI command packet to DSPIN command packet
+	// The VCI packet is analysed, translated,
+	// and the DSPIN packet is stored in the fifo_cmd
+        /////////////////////////////////////////////////////////////
+        // - A N flits VCI write command packet is translated
+        //   to a N+2 flits DSPIN command.
+        // - A single flit VCI read command packet is translated 
+        //   to a 2 flits DSPIN command.
+        // - A single flit VCI broadcast packet is translated to
+        //   a 2 flits DSPIN command.
+        // A DSPIN flit is written in the fifo_cmd in all states
+        // but a VCI flit is consumed only in the CMD_READ,
+        // CMD_BROACAST,  and CMD_WDATA states.
+        //////////////////////////////////////////////////////////////
+
+	// cmd_fifo_read
+	cmd_fifo_read = p_dspin_out.read.read();
+
+	// r_cmd_fsm, cmd_fifo_write and cmd_fifo_data
+        cmd_fifo_write = false;		// default value
+
+	switch(r_cmd_fsm) {
+	    case CMD_IDLE:		// write first DSPIN flit into fifo_cmd
+            {
+		if( p_vci.cmdval && r_fifo_cmd.wok() ) 
+                {
+		    cmd_fifo_write = true;
+                    sc_uint<dspin_cmd_width> address = (sc_uint<dspin_cmd_width>)p_vci.address.read();
+                    sc_uint<dspin_cmd_width> srcid   = (sc_uint<dspin_cmd_width>)p_vci.srcid.read();
+                    sc_uint<dspin_cmd_width> trdid   = (sc_uint<dspin_cmd_width>)p_vci.trdid.read();
+                    sc_uint<dspin_cmd_width> cmd     = (sc_uint<dspin_cmd_width>)p_vci.cmd.read();
+
+                    bool is_broadcast = ( (address & 0x3) != 0);
+                    bool is_read = ((cmd == vci_param::CMD_READ) || (cmd == vci_param::CMD_LOCKED_READ));
+
+                    if ( vci_param::N == 40 ) address = address >> 1;
+                    else                      address = address << (39 - vci_param::N);              
+
+                    if ( is_broadcast )	// VCI broacast command
+                    {
+                        r_cmd_fsm     = CMD_BROADCAST;
+                        cmd_fifo_data = (address      & 0x7FFFF80000ULL) |
+                                        ((srcid << 5) & 0x000007FFE0) | 
+                                        ((trdid << 1) & 0x000000001E) | 
+                                                        0x0000000001;		
+                    }
+                    else if (is_read )			// VCI READ  command
+                    {
+		        r_cmd_fsm     = CMD_READ;
+                        cmd_fifo_data = address & 0x7FFFFFFFFEULL;
+		    }
+                    else 				// VCI WRITE command
+                    {
+		        r_cmd_fsm     = CMD_WRITE;
+                        cmd_fifo_data = address & 0x7FFFFFFFFEULL;
+		    }
+		}
+	 	break;
+            }
+	    case CMD_BROADCAST:		// write second DSPIN flit in case of broadcast
+            {    
+		if( p_vci.cmdval && r_fifo_cmd.wok() ) 
+                {
+                    cmd_fifo_write   = true;
+                    sc_uint<dspin_cmd_width> data = (sc_uint<dspin_cmd_width>)p_vci.wdata.read();
+                    sc_uint<dspin_cmd_width> be   = (sc_uint<dspin_cmd_width>)p_vci.be.read();
+                    cmd_fifo_data    = (data       & 0x00FFFFFFFFUL) | 
+                                       ((be << 32) & 0x0300000000ULL) |
+                                                     0x8000000000ULL; 
+                    r_cmd_fsm = CMD_IDLE;
+                }
+                break;
+            }
+            case CMD_READ:	// write second DSPIN flit in case of read/write
+            case CMD_WRITE:
+            {
+		if( p_vci.cmdval && r_fifo_cmd.wok() ) 
+                {
+		    cmd_fifo_write      = true;
+                    sc_uint<dspin_cmd_width> srcid   = (sc_uint<dspin_cmd_width>)p_vci.srcid.read();
+                    sc_uint<dspin_cmd_width> trdid   = (sc_uint<dspin_cmd_width>)p_vci.trdid.read();
+                    sc_uint<dspin_cmd_width> cmd     = (sc_uint<dspin_cmd_width>)p_vci.cmd.read();
+                    sc_uint<dspin_cmd_width> plen    = (sc_uint<dspin_cmd_width>)p_vci.plen.read();
+                    sc_uint<dspin_cmd_width> be      = (sc_uint<dspin_cmd_width>)p_vci.be.read();
+		    cmd_fifo_data       = ((be    << 1 ) & 0x000000001E) |
+                                          ((trdid << 5 ) & 0x0000001FE0) |
+                                          ((plen  << 13) & 0x00001FE000) |
+                                          ((cmd   << 23) & 0x0001800000) |
+                                          ((srcid << 25) & 0x7FFE000000ULL) ;
+                    if ( p_vci.contig.read() ) cmd_fifo_data = cmd_fifo_data | 0x0000400000 ;
+                    if ( p_vci.cons.read()   ) cmd_fifo_data = cmd_fifo_data | 0x0000200000 ;
+
+                    if( r_cmd_fsm == CMD_READ )  // read command
+                    {
+                        r_cmd_fsm = CMD_IDLE;
+                        cmd_fifo_data = cmd_fifo_data    | 0x8000000000ULL ;
+                    }
+                    else			// write command
+                    {
+                        r_cmd_fsm = CMD_WDATA;
+                    }
+		}
+		break;
+            }
+	    case CMD_WDATA:
+            {
+		if( p_vci.cmdval && r_fifo_cmd.wok() ) 
+                {
+		    cmd_fifo_write = true;
+                    sc_uint<dspin_cmd_width> data = (sc_uint<dspin_cmd_width>)p_vci.wdata.read();
+                    sc_uint<dspin_cmd_width> be   = (sc_uint<dspin_cmd_width>)p_vci.be.read();
+		    cmd_fifo_data    = (data       & 0x00FFFFFFFFUL) | 
+                                       ((be << 32) & 0x0F00000000ULL) ;
+                                       
+                    if ( p_vci.eop.read() )
+                    {
+                        cmd_fifo_data = cmd_fifo_data | 0x8000000000ULL;
+                        r_cmd_fsm = CMD_IDLE;
+                    }
+                }                
+                break;
+            }
+	} // end switch r_cmd_fsm
+	
+	// fifo_cmd
+	if((cmd_fifo_write == true)  && (cmd_fifo_read == false)) { r_fifo_cmd.simple_put(cmd_fifo_data); } 
+	if((cmd_fifo_write == true)  && (cmd_fifo_read == true))  { r_fifo_cmd.put_and_get(cmd_fifo_data); } 
+	if((cmd_fifo_write == false) && (cmd_fifo_read == true))  { r_fifo_cmd.simple_get(); }
+
+        //////////////////////////////////////////////////////////////
+	// DSPIN response packet to VCI response packet
+	// The DSPIN packet is stored in the fifo_rsp
+	// The FIFO output is analysed and translated to a VCI packet
+        //////////////////////////////////////////////////////////////
+        // - A N+1 flits DSPIN read response packet is translated
+        //   to a N flits VCI response.
+        // - A single flit DSPIN write response packet is translated
+        //   to a single flit VCI response.
+        // A valid DSPIN flit in the fifo_rsp is always consumed   
+        // in the CMD_IDLE state, but no VCI flit is transmitted.
+        // The VCI flits are sent in the RSP_READ & RSP_WRITE states.
+        //////////////////////////////////////////////////////////////
+
+	// rsp_fifo_write, rsp_fifo_data
+	rsp_fifo_write = p_dspin_in.write.read();
+	rsp_fifo_data  = p_dspin_in.data.read();
+
+	// r_rsp_fsm, rsp_fifo_read
+        rsp_fifo_read = false;		// default value
+
+	switch(r_rsp_fsm) {
+	    case RSP_IDLE:
+            {
+		if( r_fifo_rsp.rok() )
+                {
+		    rsp_fifo_read = true;
+                    r_rsp_buf = r_fifo_rsp.read();
+                    if ( (r_fifo_rsp.read() & 0x000020000) == 0 )  r_rsp_fsm = RSP_READ;
+                    else 					   r_rsp_fsm = RSP_WRITE;
+		}
+		break;
+            }
+	    case RSP_READ:		
+	    {
+		if( r_fifo_rsp.rok() && p_vci.rspack.read() )
+                {
+		    rsp_fifo_read = true;
+                    if ( (r_fifo_rsp.read() & 0x100000000ULL) ) r_rsp_fsm = RSP_IDLE;
+		}
+		break;
+            }
+            case RSP_WRITE:
+            {
+                if ( p_vci.rspack.read() ) r_rsp_fsm = RSP_IDLE;
+            }
+	} // end switch r_rsp_fsm
+
+	// fifo_rsp
+	if((rsp_fifo_write == true)  && (rsp_fifo_read == false)) { r_fifo_rsp.simple_put(rsp_fifo_data); } 
+	if((rsp_fifo_write == true)  && (rsp_fifo_read == true))  { r_fifo_rsp.put_and_get(rsp_fifo_data); } 
+	if((rsp_fifo_write == false) && (rsp_fifo_read == true))  { r_fifo_rsp.simple_get(); }
+
+}; // end transition
+
+//////////////////////
+tmpl(void)::genMoore()
+{
+	// VCI CMD interface
+        if ( ( r_cmd_fsm.read() == CMD_IDLE ) || ( r_cmd_fsm.read() == CMD_WRITE ) ) 
+        {
+            p_vci.cmdack = false; 
+        }
+	else
+        {
+            p_vci.cmdack = r_fifo_cmd.wok();
+        }
+
+	// VCI RSP interface
+	if ( r_rsp_fsm.read() == RSP_IDLE )
+        {
+            p_vci.rspval = false;
+        }
+        else if ( r_rsp_fsm.read() == RSP_WRITE )
+        {
+            p_vci.rspval = true;
+	    p_vci.rdata  = 0;
+            p_vci.rsrcid = (sc_uint<vci_param::S>)((r_rsp_buf.read() & 0x0FFFC0000ULL) >> 18);
+            p_vci.rtrdid = (sc_uint<vci_param::T>)((r_rsp_buf.read() & 0x00000FF00) >> 8);
+            p_vci.rpktid = 0;
+            p_vci.rerror = (sc_uint<vci_param::E>)((r_rsp_buf.read() & 0x000030000) >> 16);
+            p_vci.reop   = true;
+        }
+        else if ( r_rsp_fsm.read() == RSP_READ )
+        {
+            p_vci.rspval = r_fifo_rsp.rok();
+            p_vci.rdata  = (sc_uint<8*vci_param::B>)(r_fifo_rsp.read() & 0x0FFFFFFFFUL);
+            p_vci.rsrcid = (sc_uint<vci_param::S>)((r_rsp_buf.read()   & 0x0FFFC0000) >> 18);
+            p_vci.rtrdid = (sc_uint<vci_param::T>)((r_rsp_buf.read()   & 0x00000FF00) >> 8);
+            p_vci.rpktid = 0;
+            p_vci.rerror = (sc_uint<vci_param::E>)((r_rsp_buf.read()   & 0x000030000) >> 16);
+            p_vci.reop   = ((r_fifo_rsp.read() & 0x100000000ULL) == 0x100000000ULL); 
+        }
+
+	// DSPIN_OUT interface
+	p_dspin_out.write = r_fifo_cmd.rok();
+	p_dspin_out.data  = r_fifo_cmd.read();
+
+	// DSPIN_IN interface
+	p_dspin_in.read = r_fifo_rsp.wok();
+
+}; // end genMoore
+
+/////////////////////////
+tmpl(void)::print_trace()
+{
+    const char* cmd_str[] = {
+    "CMD_IDLE     ",
+    "CMD_BROADCAST",
+    "CMD_READ     ",
+    "CMD_WRITE    ",
+    "CMD_WDATA    ",
+    };
+    const char* rsp_str[] = {
+    "RSP_IDLE     ",
+    "RSP_READ     ",
+    "RSP_WRITE    ",
+    };
+
+    std::cout << name() << " : " << cmd_str[r_cmd_fsm.read()]
+                        << " | " << rsp_str[r_rsp_fsm.read()] 
+                        << " | fifo_cmd = " << r_fifo_cmd.filled_status()
+                        << " | fifo_rsp = " << r_fifo_rsp.filled_status()
+                        << std::endl;
+}
+
+}} // end namespace
+
+// Local Variables:
+// tab-width: 4
+// c-basic-offset: 4
+// c-file-offsets:((innamespace . 0)(inline-open . 0))
+// indent-tabs-mode: nil
+// End:
+
+// vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4
Index: branches/v4/platforms/almos-tsarv3-platforms/common/vci_vdspin_target_wrapper/caba/metadata/vci_vdspin_target_wrapper.sd
===================================================================
--- branches/v4/platforms/almos-tsarv3-platforms/common/vci_vdspin_target_wrapper/caba/metadata/vci_vdspin_target_wrapper.sd	(revision 371)
+++ branches/v4/platforms/almos-tsarv3-platforms/common/vci_vdspin_target_wrapper/caba/metadata/vci_vdspin_target_wrapper.sd	(revision 371)
@@ -0,0 +1,25 @@
+
+# -*- python -*-
+
+Module('caba:vci_vdspin_target_wrapper',
+	classname = 'soclib::caba::VciVdspinTargetWrapper',
+	tmpl_parameters = [
+		parameter.Module('vci_param',  default = 'caba:vci_param'),
+		parameter.Int('dspin_cmd_width'),
+		parameter.Int('dspin_rsp_width'), ],
+        header_files = ['../source/include/vci_vdspin_target_wrapper.h', ],
+        implementation_files = ['../source/src/vci_vdspin_target_wrapper.cpp',],
+        ports = [
+		Port('caba:vci_initiator', 'p_vci'),
+                Port('caba:dspin_output', 'p_dspin_out', dspin_data_size = parameter.Reference('dspin_rsp_width')),
+                Port('caba:dspin_input', 'p_dspin_in', dspin_data_size = parameter.Reference('dspin_cmd_width')),
+		Port('caba:bit_in', 'p_resetn', auto = 'resetn'),
+		Port('caba:clock_in', 'p_clk', auto = 'clock'), ],
+	uses = [
+		Uses('caba:base_module'),
+		Uses('caba:generic_fifo'),
+		],
+	instance_parameters = [
+		parameter.Int('cmd_fifo_depth'),
+		parameter.Int('rsp_fifo_depth'), ],
+)
Index: branches/v4/platforms/almos-tsarv3-platforms/common/vci_vdspin_target_wrapper/caba/source/include/vci_vdspin_target_wrapper.h
===================================================================
--- branches/v4/platforms/almos-tsarv3-platforms/common/vci_vdspin_target_wrapper/caba/source/include/vci_vdspin_target_wrapper.h	(revision 371)
+++ branches/v4/platforms/almos-tsarv3-platforms/common/vci_vdspin_target_wrapper/caba/source/include/vci_vdspin_target_wrapper.h	(revision 371)
@@ -0,0 +1,129 @@
+/* -*- c++ -*-
+  * File : vci_vdspin_target_wrapper.h
+  * Copyright (c) UPMC, Lip6
+  * Author : Alain Greiner
+  *
+  * SOCLIB_LGPL_HEADER_BEGIN
+  * 
+  * This file is part of SoCLib, GNU LGPLv2.1.
+  * 
+  * SoCLib is free software; you can redistribute it and/or modify it
+  * under the terms of the GNU Lesser General Public License as published
+  * by the Free Software Foundation; version 2.1 of the License.
+  * 
+  * SoCLib is distributed in the hope that it will be useful, but
+  * WITHOUT ANY WARRANTY; without even the implied warranty of
+  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+  * Lesser General Public License for more details.
+  * 
+  * You should have received a copy of the GNU Lesser General Public
+  * License along with SoCLib; if not, write to the Free Software
+  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+  * 02110-1301 USA
+  * 
+  * SOCLIB_LGPL_HEADER_END
+  */
+
+/////////////////////////////////////////////////////////////////////////
+// This component performs the protocol translation between VCI & DSPIN,
+// and can be used to connect a VCI target to a DSPIN netnork.
+// It is implemented as two fully independant sub-components:
+// - translation from a DSPIN CMD to a VCI CMD
+// - translation from a VCI RSP to a DSPIN RSP
+// Each subcomponent contains a FIFO containing DSPIN flits.
+// For the DSPIN interfaces, the widths of the CMD & RSP flits
+// are defined as template parameters for future evolutions,
+// but the VCI to DSPIN translation makes the following assumptions:
+// - DSPIN CMD flit width == 40 bits
+// - DSPIN RSP flit width == 33 bits
+// - VCI address width    <= 40 bits
+// - VCI data             == 32 bits
+// - VCI plen		  == 8  bits
+// - VCI srcid		  <= 14 bits
+// - VCI trdid		  <= 8  bits
+// - VCI pktid field not transmitted
+// - VCI rerror		  == 2 bits
+////////////////////////////////////////////////////////////////////////
+
+#ifndef VCI_VDSPIN_TARGET_WRAPPER_H_
+#define VCI_VDSPIN_TARGET_WRAPPER_H_
+
+#include <systemc>
+#include <assert.h>
+#include "caba_base_module.h"
+#include "vci_initiator.h"
+#include "generic_fifo.h"
+#include "dspin_interface.h"
+
+namespace soclib { namespace caba {
+
+
+template<typename vci_param, int dspin_cmd_width, int dspin_rsp_width>
+class VciVdspinTargetWrapper
+	: public soclib::caba::BaseModule
+{
+
+    // Command FSM 
+    enum fsm_state_cmd{
+    CMD_IDLE,
+    CMD_BROADCAST,
+    CMD_RW,
+    CMD_READ,
+    CMD_WDATA,
+    };
+
+    // Response FSM
+    enum fsm_state_rsp{
+    RSP_IDLE,
+    RSP_READ,
+    RSP_WRITE,
+    };
+
+protected:
+    SC_HAS_PROCESS(VciVdspinTargetWrapper);
+
+public:
+    // ports
+    sc_core::sc_in<bool>                             		p_clk;
+    sc_core::sc_in<bool>                             		p_resetn;
+    soclib::caba::DspinOutput<dspin_rsp_width>			p_dspin_out;
+    soclib::caba::DspinInput<dspin_cmd_width>			p_dspin_in;
+    soclib::caba::VciInitiator<vci_param>      			p_vci;
+
+    // constructor / destructor
+    VciVdspinTargetWrapper(	sc_module_name 			name, 
+				size_t				cmd_fifo_depth,
+				size_t				rsp_fifo_depth);
+private:
+    // internal registers
+    sc_core::sc_signal<int>        				r_cmd_fsm;
+    sc_core::sc_signal<sc_uint<dspin_cmd_width>	>		r_cmd_buf0;
+    sc_core::sc_signal<sc_uint<dspin_cmd_width>	>		r_cmd_buf1;
+    sc_core::sc_signal<int>        				r_rsp_fsm;
+    sc_core::sc_signal<size_t>					r_flit_count;
+
+    // fifos cmd and rsp
+    soclib::caba::GenericFifo<sc_uint<dspin_cmd_width> >  	r_fifo_cmd;
+    soclib::caba::GenericFifo<sc_uint<dspin_rsp_width> >  	r_fifo_rsp;
+
+    // methods systemc
+    void transition();
+    void genMoore();
+
+public:
+    void print_trace();
+
+};
+
+}} // end namespace
+               
+#endif // VCI_VDSPIN_TARGET_WRAPPER_H_
+
+// Local Variables:
+// tab-width: 4
+// c-basic-offset: 4
+// c-file-offsets:((innamespace . 0)(inline-open . 0))
+// indent-tabs-mode: nil
+// End:
+
+// vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4
Index: branches/v4/platforms/almos-tsarv3-platforms/common/vci_vdspin_target_wrapper/caba/source/src/vci_vdspin_target_wrapper.cpp
===================================================================
--- branches/v4/platforms/almos-tsarv3-platforms/common/vci_vdspin_target_wrapper/caba/source/src/vci_vdspin_target_wrapper.cpp	(revision 371)
+++ branches/v4/platforms/almos-tsarv3-platforms/common/vci_vdspin_target_wrapper/caba/source/src/vci_vdspin_target_wrapper.cpp	(revision 371)
@@ -0,0 +1,361 @@
+/* -*- c++ -*-
+  * File : vci_vdspin_target_wrapper.cpp
+  * Copyright (c) UPMC, Lip6
+  * Author : Alain Greiner
+  *
+  * SOCLIB_LGPL_HEADER_BEGIN
+  * 
+  * This file is part of SoCLib, GNU LGPLv2.1.
+  * 
+  * SoCLib is free software; you can redistribute it and/or modify it
+  * under the terms of the GNU Lesser General Public License as published
+  * by the Free Software Foundation; version 2.1 of the License.
+  * 
+  * SoCLib is distributed in the hope that it will be useful, but
+  * WITHOUT ANY WARRANTY; without even the implied warranty of
+  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+  * Lesser General Public License for more details.
+  * 
+  * You should have received a copy of the GNU Lesser General Public
+  * License along with SoCLib; if not, write to the Free Software
+  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+  * 02110-1301 USA
+  * 
+  * SOCLIB_LGPL_HEADER_END
+  */
+
+#include "../include/vci_vdspin_target_wrapper.h"
+
+namespace soclib { namespace caba {
+
+#define tmpl(x) template<typename vci_param, int dspin_cmd_width, int dspin_rsp_width> x VciVdspinTargetWrapper<vci_param, dspin_cmd_width, dspin_rsp_width>
+
+//////////////////////////////////////////////////////////:////////////////////////////////
+tmpl(/**/)::VciVdspinTargetWrapper(sc_module_name 			name,
+			     	   size_t				cmd_fifo_depth,
+				   size_t				rsp_fifo_depth)
+	       : soclib::caba::BaseModule(name),
+                 p_clk("p_clk"),
+                 p_resetn("p_resetn"),
+                 p_dspin_out("p_dspin_out"),
+                 p_dspin_in("p_dspin_in"),
+                 p_vci("p_vci"),
+                 r_cmd_fsm("r_cmd_fsm"),
+                 r_rsp_fsm("r_rsp_fsm"),
+	         r_fifo_cmd("r_fifo_cmd", cmd_fifo_depth),
+	         r_fifo_rsp("r_fifo_rsp", rsp_fifo_depth)
+    {
+	SC_METHOD (transition);
+	dont_initialize();
+	sensitive << p_clk.pos();
+	SC_METHOD (genMoore);
+	dont_initialize();
+	sensitive  << p_clk.neg();
+
+        assert( (dspin_cmd_width == 40) && "The DSPIN CMD flit width must have 40 bits");
+        assert( (dspin_rsp_width == 33) && "The DSPIN RSP flit width must have 33 bits");
+        assert( (vci_param::N    <= 40) && "The VCI ADDRESS field cannot have more than 40 bits"); 
+        assert( (vci_param::B    == 4) && "The VCI DATA filds must have 32 bits");
+        assert( (vci_param::K    == 8) && "The VCI PLEN field cannot have more than 8 bits");
+        assert( (vci_param::S    <= 14) && "The VCI SRCID field cannot have more than 8 bits");
+        assert( (vci_param::T    <= 8) && "The VCI TRDID field cannot have more than 8 bits");
+        //assert( (vci_param::E    == 2) && "The VCI RERROR field cannot have more than 2 bits");
+
+    } //  end constructor
+
+/////////////////////////
+tmpl(void)::transition()
+{
+	sc_uint<dspin_cmd_width>	cmd_fifo_data;
+	bool				cmd_fifo_write;
+	bool				cmd_fifo_read;
+
+	sc_uint<dspin_rsp_width>	rsp_fifo_data;
+	bool				rsp_fifo_write;
+	bool				rsp_fifo_read;
+
+	if (p_resetn == false) 
+        {
+	    r_fifo_cmd.init();
+	    r_fifo_rsp.init();
+	    r_cmd_fsm = CMD_IDLE;
+	    r_rsp_fsm = RSP_IDLE;
+	    return;
+	} // end reset
+
+        /////////////////////////////////////////////////////////////
+	// VCI response packet to DSPIN response packet.
+	// The VCI packet is analysed, translated,
+	// and the DSPIN packet is stored in the fifo_rsp
+        /////////////////////////////////////////////////////////////
+        // - A single flit VCI write response packet is translated
+        //   to a single flit DSPIN response.
+        // - A N flits VCI read response packet is translated 
+        //   to a N+1 flits DSPIN response
+        // In the RSP_IDLE state, the first DSPIN flit is written 
+        // in fifo_rsp , but no VCI flit is consumed. The VCI flits 
+        // are consumed in the RSP_READ or RSP_WRITE states.
+        //////////////////////////////////////////////////////////////
+
+	// rsp_fifo_read
+	rsp_fifo_read = p_dspin_out.read.read();
+
+	// r_rsp_fsm, rsp_fifo_write and rsp_fifo_data
+        rsp_fifo_write = false;		// default value
+
+	switch(r_rsp_fsm) {
+	    case RSP_IDLE:		// write first DSPIN flit into rsp_fifo
+            {
+		if( p_vci.rspval && r_fifo_rsp.wok() ) 
+                {
+                    bool is_read = ( (p_vci.rerror.read() & 0x2) == 0);
+
+		    rsp_fifo_write = true;
+                    rsp_fifo_data = (((sc_uint<dspin_rsp_width>)p_vci.rsrcid.read()) << 18) |
+                                    (((sc_uint<dspin_rsp_width>)p_vci.rerror.read()) << 16) |
+                                    (((sc_uint<dspin_rsp_width>)p_vci.rtrdid.read()) << 8);
+                    if ( is_read ) 
+                    {
+                        r_rsp_fsm = RSP_READ;
+                    }
+                    else
+                    {
+                        rsp_fifo_data = rsp_fifo_data | 0x100000000ULL;
+                        r_rsp_fsm = RSP_WRITE;
+                    }
+		}
+	 	break;
+            }
+	    case RSP_READ:		// write DSPIN data flit in case of read
+            {    
+                if( p_vci.rspval && r_fifo_rsp.wok() )
+                {
+                    rsp_fifo_write   = true;
+                    rsp_fifo_data = ((sc_uint<dspin_rsp_width>)p_vci.rdata.read());
+                    if ( p_vci.reop ) 
+                    {
+                        rsp_fifo_data = rsp_fifo_data | 0x100000000ULL;
+                        r_rsp_fsm = RSP_IDLE;
+                    }
+                }
+                break;
+            }
+            case RSP_WRITE:
+            {
+                rsp_fifo_write = false;
+                if ( r_fifo_rsp.wok() ) r_rsp_fsm = RSP_IDLE;
+                break;
+            }
+	} // end switch r_cmd_fsm
+	
+	// fifo_rsp
+	if((rsp_fifo_write == true)  && (rsp_fifo_read == false)) { r_fifo_rsp.simple_put(rsp_fifo_data); } 
+	if((rsp_fifo_write == true)  && (rsp_fifo_read == true))  { r_fifo_rsp.put_and_get(rsp_fifo_data); } 
+	if((rsp_fifo_write == false) && (rsp_fifo_read == true))  { r_fifo_rsp.simple_get(); }
+
+        //////////////////////////////////////////////////////////////
+	// DSPIN command packet to VCI command packet
+	// The DSPIN packet is stored in the fifo_rsp
+	// The FIFO output is analysed and translated to a VCI packet
+        //////////////////////////////////////////////////////////////
+        // - A 2 flits DSPIN broadcast command is translated
+        //   to a 1 flit VCI broadcast command.
+        // - A 2 flits DSPIN read command is translated
+        //   to a 1 flit VCI read command.
+        // - A N+2 flits DSPIN write command is translated
+        //   to a N flits VCI write command. 
+        // The VCI flits are sent in the CMD_READ, CMD_WDATA 
+        // & CMD_BROADCAST states. 
+        // The r_cmd_buf0 et r_cmd_buf1 buffers are used to store
+        // the two first DSPIN flits (in case of write).
+        //////////////////////////////////////////////////////////////
+
+	// cmd_fifo_write, cmd_fifo_data
+	cmd_fifo_write = p_dspin_in.write.read();
+	cmd_fifo_data  = p_dspin_in.data.read();
+
+	// r_cmd_fsm, cmd_fifo_read
+        cmd_fifo_read = false; 		// default value
+
+	switch(r_cmd_fsm) {
+	    case CMD_IDLE:
+            {
+		if( r_fifo_cmd.rok() )
+                {
+                    bool is_broadcast = ( (r_fifo_cmd.read() & 0x1) == 0x1);
+
+		    cmd_fifo_read = true;
+                    r_cmd_buf0    = r_fifo_cmd.read(); 		// save address
+                    if ( is_broadcast ) r_cmd_fsm = CMD_BROADCAST;
+                    else		r_cmd_fsm = CMD_RW;
+		}
+		break;
+            }
+	    case CMD_BROADCAST:
+	    {
+		if( r_fifo_cmd.rok() && p_vci.cmdack )
+                {
+                    cmd_fifo_read = true;
+                    r_cmd_fsm = CMD_IDLE;
+                }
+                break;
+            }
+            case CMD_RW:
+            {
+		if( r_fifo_cmd.rok() )
+                {
+		    cmd_fifo_read = true;
+                    r_cmd_buf1 = r_fifo_cmd.read();		// save command parameters
+                    // read command if EOP
+                    if ( (r_fifo_cmd.read() & 0x8000000000ULL) )   r_cmd_fsm = CMD_READ;
+                    else					r_cmd_fsm = CMD_WDATA;
+                    r_flit_count = 0;
+		}
+		break;
+            }
+            case CMD_READ:
+            {
+                if ( p_vci.cmdack.read() ) r_cmd_fsm = CMD_IDLE;
+                break;
+            }
+            case CMD_WDATA:
+            {
+		if( r_fifo_cmd.rok() && p_vci.cmdack.read() )
+                {
+                    if ( (r_cmd_buf1.read() & 0x0000200000) == 0 ) r_flit_count = r_flit_count + 1;
+		               cmd_fifo_read = true;
+                    if ( (r_fifo_cmd.read() & 0x8000000000ULL) ) 	r_cmd_fsm = CMD_IDLE;
+		}
+                break;
+            }
+	} // end switch r_cmd_fsm
+
+	// fifo_cmd
+	if((cmd_fifo_write == true)  && (cmd_fifo_read == false)) { r_fifo_cmd.simple_put(cmd_fifo_data); } 
+	if((cmd_fifo_write == true)  && (cmd_fifo_read == true))  { r_fifo_cmd.put_and_get(cmd_fifo_data); } 
+	if((cmd_fifo_write == false) && (cmd_fifo_read == true))  { r_fifo_cmd.simple_get(); }
+
+}; // end transition
+
+//////////////////////
+tmpl(void)::genMoore()
+{
+	// VCI RSP interface
+        if ( r_rsp_fsm.read() == RSP_IDLE )	p_vci.rspack = false;
+	else                                   	p_vci.rspack = r_fifo_rsp.wok();
+
+	// VCI CMD interface
+	if ( (r_cmd_fsm.read() == CMD_IDLE) || (r_cmd_fsm.read() == CMD_RW) )
+        {
+            p_vci.cmdval = false;
+        }
+        else if ( r_cmd_fsm.read() == CMD_BROADCAST )	// VCI CMD broadcast
+        {
+            if ( r_fifo_cmd.rok() )
+            {
+                sc_uint<dspin_cmd_width>  minmax = r_cmd_buf0.read() & 0x7FFFF80000ULL;
+                if ( vci_param::N == 40 ) minmax = (minmax << 1);
+                else			  minmax = (minmax >> (39 - vci_param::N) ); 
+                p_vci.cmdval  = true;
+	        p_vci.address = (sc_uint<vci_param::N>)minmax | 0x3;
+                p_vci.cmd     = vci_param::CMD_WRITE;
+                p_vci.wdata   = (sc_uint<8*vci_param::B>)(r_fifo_cmd.read() & 0x00FFFFFFFFUL);
+                p_vci.be      = (sc_uint<vci_param::B>)((r_fifo_cmd.read() & 0x0F00000000ULL) >> 32);
+                p_vci.srcid   = (sc_uint<vci_param::S>)((r_cmd_buf0.read() & 0x000007FFE0) >> 5);
+                p_vci.trdid   = (sc_uint<vci_param::T>)((r_cmd_buf0.read() & 0x000000001E) >> 1);
+		p_vci.pktid   = 0;
+                p_vci.plen    = vci_param::B;
+                p_vci.contig  = true;
+                p_vci.cons    = false;
+                p_vci.eop     = true;
+            }
+            else
+            {
+            	p_vci.cmdval = false;
+            }
+        }
+        else if ( r_cmd_fsm.read() == CMD_READ )	// VCI CMD read
+        {            
+            sc_uint<vci_param::N> address;
+            if ( vci_param::N == 40 ) address = (r_cmd_buf0.read() << 1);
+            else                      address = (r_cmd_buf0.read() >> (39 - vci_param::N) ); 
+            p_vci.cmdval  = true;
+	    p_vci.address = address;
+            p_vci.cmd     = (sc_uint<2>)((r_cmd_buf1.read()            & 0x0001800000) >> 23);
+	    p_vci.wdata   = 0;
+            p_vci.be      = (sc_uint<vci_param::B>)((r_cmd_buf1.read() & 0x000000001E) >> 1);
+            p_vci.srcid   = (sc_uint<vci_param::S>)((r_cmd_buf1.read() & 0x7FFE000000ULL) >> 25);
+            p_vci.trdid   = (sc_uint<vci_param::T>)((r_cmd_buf1.read() & 0x0000001FE0) >> 5);
+	    p_vci.pktid   = 0;
+            p_vci.plen    = (sc_uint<vci_param::K>)((r_cmd_buf1.read() & 0x00001FE000) >> 13);
+            p_vci.contig  = ((r_cmd_buf1.read() & 0x0000400000) != 0);
+            p_vci.cons    = ((r_cmd_buf1.read() & 0x0000200000) != 0);
+            p_vci.eop     = true;
+	}
+        else if ( r_cmd_fsm.read() == CMD_WDATA )	// VCI write command
+        {
+            if ( r_fifo_cmd.rok() )  
+            {
+                sc_uint<vci_param::N> address;
+                if ( vci_param::N == 40 ) address = (r_cmd_buf0.read() << 1);
+                else                      address = (r_cmd_buf0.read() >> (39 - vci_param::N) ); 
+                p_vci.cmdval  = true;
+	        p_vci.address = address + (r_flit_count.read()*vci_param::B);
+                p_vci.cmd     = (sc_uint<2>)((r_cmd_buf1.read()              & 0x0001800000) >> 23);
+		p_vci.wdata   = (sc_uint<8*vci_param::B>)(r_fifo_cmd.read()  & 0x00FFFFFFFFUL);
+		p_vci.be      = (sc_uint<vci_param::B>)((r_fifo_cmd.read()   & 0x0F00000000ULL) >> 32);
+                p_vci.srcid   = (sc_uint<vci_param::S>)((r_cmd_buf1.read()   & 0x7FFE000000ULL) >> 25);
+                p_vci.trdid   = (sc_uint<vci_param::T>)((r_cmd_buf1.read()   & 0x0000001FE0) >> 5);
+		p_vci.pktid   = 0;
+                p_vci.plen    = (sc_uint<vci_param::K>)((r_cmd_buf1.read() & 0x00001FE000) >> 13);
+                p_vci.contig  = ((r_cmd_buf1.read() & 0x0000400000) != 0);
+                p_vci.cons    = ((r_cmd_buf1.read() & 0x0000200000) != 0);
+		p_vci.eop     = ((r_fifo_cmd.read() & 0x8000000000ULL) == 0x8000000000ULL); 
+            }
+            else
+            {
+            	p_vci.cmdval = false;
+            }
+        }
+
+	// DSPIN_OUT interface
+	p_dspin_out.write = r_fifo_rsp.rok();
+	p_dspin_out.data  = r_fifo_rsp.read();
+
+	// DSPIN_IN interface
+	p_dspin_in.read = r_fifo_cmd.wok();
+
+}; // end genMoore
+
+/////////////////////////
+tmpl(void)::print_trace()
+{
+    const char* cmd_str[] = {
+    "CMD_IDLE     ",
+    "CMD_BROADCAST",
+    "CMD_RW       ",
+    "CMD_READ     ",
+    "CMD_WDATA    ",
+    };
+    const char* rsp_str[] = {
+    "RSP_IDLE     ",
+    "RSP_READ     ",
+    "RSP_WRITE    ",
+    };
+    std::cout << name() << " : " << cmd_str[r_cmd_fsm.read()]
+                        << " | " << rsp_str[r_rsp_fsm.read()] 
+                        << " | fifo_cmd = " << r_fifo_cmd.filled_status()
+                        << " | fifo_rsp = " << r_fifo_rsp.filled_status()
+			<< std::endl;
+}
+
+}} // end namespace
+
+// Local Variables:
+// tab-width: 4
+// c-basic-offset: 4
+// c-file-offsets:((innamespace . 0)(inline-open . 0))
+// indent-tabs-mode: nil
+// End:
+
+// vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4
Index: branches/v4/platforms/almos-tsarv3-platforms/mono-cluster/Makefile
===================================================================
--- branches/v4/platforms/almos-tsarv3-platforms/mono-cluster/Makefile	(revision 371)
+++ branches/v4/platforms/almos-tsarv3-platforms/mono-cluster/Makefile	(revision 371)
@@ -0,0 +1,6 @@
+ARCH=mips32el
+SOCLIB?=$(shell soclib-cc --getpath)
+NO_SOFT=1
+export SOCLIB
+SOCLIB_CC_ADD_ARGS='-v -I. -I../common'
+include $(SOCLIB)/soclib/platform/topcells/all.mk
Index: branches/v4/platforms/almos-tsarv3-platforms/mono-cluster/config.h
===================================================================
--- branches/v4/platforms/almos-tsarv3-platforms/mono-cluster/config.h	(revision 371)
+++ branches/v4/platforms/almos-tsarv3-platforms/mono-cluster/config.h	(revision 371)
@@ -0,0 +1,2 @@
+#define CONFIG_MEMC_TRANSACTION_TAB_LINES 8
+#define CONFIG_MEMC_UPDATE_TAB_LINES      8
Index: branches/v4/platforms/almos-tsarv3-platforms/mono-cluster/config/config.h
===================================================================
--- branches/v4/platforms/almos-tsarv3-platforms/mono-cluster/config/config.h	(revision 371)
+++ branches/v4/platforms/almos-tsarv3-platforms/mono-cluster/config/config.h	(revision 371)
@@ -0,0 +1,3 @@
+namespace config {
+  #include "../config.h"
+}
Index: branches/v4/platforms/almos-tsarv3-platforms/mono-cluster/config/config.sd
===================================================================
--- branches/v4/platforms/almos-tsarv3-platforms/mono-cluster/config/config.sd	(revision 371)
+++ branches/v4/platforms/almos-tsarv3-platforms/mono-cluster/config/config.sd	(revision 371)
@@ -0,0 +1,13 @@
+
+# -*- python -*-
+
+__id__ = "$Id: todo $"
+__version__ = "$vision: 0 $"
+
+Module('config:config',
+	header_files = [
+		'../config.h',
+		]
+)
+
+
Index: branches/v4/platforms/almos-tsarv3-platforms/mono-cluster/platform_desc
===================================================================
--- branches/v4/platforms/almos-tsarv3-platforms/mono-cluster/platform_desc	(revision 371)
+++ branches/v4/platforms/almos-tsarv3-platforms/mono-cluster/platform_desc	(revision 371)
@@ -0,0 +1,37 @@
+
+# -*- python -*-
+
+
+todo = Platform('caba', 'top.cpp',
+                uses = [
+	Uses('caba:vci_cc_vcache_wrapper2_v1', iss_t = 'common:mips32el'),
+	Uses('caba:vci_simple_ram'),
+	Uses('caba:vci_multi_tty'),
+        Uses('caba:vci_xicu'),
+        Uses('caba:vci_dma_tsar_v2'),
+	Uses('caba:vci_block_device_tsar_v2'),
+        Uses('caba:vci_framebuffer'),
+	Uses('caba:vci_vgmn'),
+        Uses('caba:vci_profiler', iss_t = 'common:mips32el'),
+#        Uses('caba:vci_simple_ring_fast',
+#             ring_cmd_data_size = 40,
+#             ring_rsp_data_size =33),
+        Uses('caba:vci_logger'),
+#        Uses('caba:vci_mem_cache_v4'),
+	Uses('caba:vci_mem_cache_v3'),
+#        Uses('caba:vci_mem_cache_v2'),
+	Uses('common:elf_file_loader'),
+	Uses('common:plain_file_loader'),
+	],
+	cell_size = 4,
+	plen_size = 8,
+	addr_size = 32,
+	rerror_size = 1,
+	clen_size = 1,
+	rflag_size = 1,
+	srcid_size = 8,
+	pktid_size = 4,
+	trdid_size = 4,
+	wrplen_size = 1
+)
+
Index: branches/v4/platforms/almos-tsarv3-platforms/mono-cluster/segmentation.h
===================================================================
--- branches/v4/platforms/almos-tsarv3-platforms/mono-cluster/segmentation.h	(revision 371)
+++ branches/v4/platforms/almos-tsarv3-platforms/mono-cluster/segmentation.h	(revision 371)
@@ -0,0 +1,59 @@
+/////////////////////////////////////////
+//   Devices mapped segments 
+/////////////////////////////////////////
+#define     XICU_BASE   0x11800000
+#define     XICU_SIZE   0x00001000
+
+#define	    DMA_BASE	0x32200000
+#define	    DMA_SIZE	0x00000014
+
+#define     TTY_BASE    0x12200000
+#define     TTY_SIZE    0x00000040
+
+#define     BD_BASE     0x15200000
+#define     BD_SIZE     0x20
+
+#define FB_XSIZE 512
+#define FB_YSIZE 512
+#define	FB_BASE	0x13200000
+#define FB_SIZE 0x200000
+////////////////////////////////////////
+
+//////////////////////////////////////////
+//       ROM mapped segments
+//////////////////////////////////////////
+#define ROM_BASE        0xbfc00000
+#define BOOT_BASE       ROM_BASE
+#define BOOT_SIZE       0x00008000
+#define BOOT_INFO_BLOCK 0xbfc08000
+#define KERNEL_BIN_IMG  0xbfc10000
+#define ROM_SIZE        0x00100000
+//////////////////////////////////////////
+
+//////////////////////////////////////////
+//                RAM
+//////////////////////////////////////////
+#define     RAM_BASE    0x00000000
+#define     RAM_SIZE    0x08000000
+//////////////////////////////////////////
+
+
+////////////////////////////////////////
+
+////////////////////////////////////////
+//	Reserved segments
+////////////////////////////////////////
+
+#define PROC0_BASE	0x08200000
+#define PROC0_SIZE	0x00000010
+
+#define PROC1_BASE	0x09200000
+#define PROC1_SIZE	0x00000010
+
+#define PROC2_BASE	0x0a200000
+#define PROC2_SIZE	0x00000010
+
+#define PROC3_BASE	0x0b200000
+#define PROC3_SIZE	0x00000010
+
+////////////////////////////////////////
Index: branches/v4/platforms/almos-tsarv3-platforms/mono-cluster/top.cpp
===================================================================
--- branches/v4/platforms/almos-tsarv3-platforms/mono-cluster/top.cpp	(revision 371)
+++ branches/v4/platforms/almos-tsarv3-platforms/mono-cluster/top.cpp	(revision 371)
@@ -0,0 +1,684 @@
+#define yes 1
+#define no  0
+
+#define USE_RING       no
+#define USE_TSAR_V3    yes
+#define SECTOR_SIZE    4096
+
+#define L1_WAYS        4
+#define L1_SETS        64
+
+#define MEMC_WAYS      16
+#define MEMC_SETS      256
+
+#define MEMC_HEAP      1024 //4096
+
+#define XRAM_LATENCY   0
+
+#define USE_VCI_LOGGER_ON_L1_CPU0  no
+#define USE_VCI_LOGGER_ON_L1_CPU1  no
+#define USE_VCI_LOGGER_ON_L1_CPU2  no
+#define USE_VCI_LOGGER_ON_L1_CPU3  no
+
+#define USE_VCI_LOGGER_ON_ROM      no
+
+#define USE_VCI_PROFILER_ON_CPU0   yes
+#define USE_VCI_PROFILER_ON_CPU1   yes
+#define USE_VCI_PROFILER_ON_CPU2   yes
+#define USE_VCI_PROFILER_ON_CPU3   yes
+
+#define USE_VCI_PROFILER (USE_VCI_PROFILER_ON_CPU0 || USE_VCI_PROFILER_ON_CPU1 || USE_VCI_PROFILER_ON_CPU2 || USE_VCI_PROFILER_ON_CPU3)
+
+#include <systemc>
+#include <sys/time.h>
+#include <iostream>
+#include <cstdlib>
+#include <cstdarg>
+#include <unistd.h>
+#include <getopt.h>
+
+#include "mapping_table.h"
+#include "mips32.h"
+#include "vci_simple_ram.h"
+#include "vci_multi_tty.h"
+
+#if USE_RING
+#include "vci_simple_ring_fast.h"
+#else
+#include "vci_vgmn.h"
+#endif
+
+#if USE_VCI_PROFILER
+#include "vci_profiler.h"
+#endif
+
+
+#if USE_TSAR_V3
+#include "vci_mem_cache_v3.h"
+#else
+#include "vci_mem_cache_v2.h"
+#endif
+
+#include "vci_cc_vcache_wrapper2_v1.h"
+#include "vci_logger.h"
+#include "vci_xicu.h"
+#include "vci_framebuffer.h"
+#include "vci_dma_tsar_v2.h"
+#include "vci_block_device_tsar_v2.h"
+
+#ifdef USE_GDB_SERVER
+#include "iss/gdbserver.h"
+#endif
+
+//#define  VCI_LOGGER_ON_L1
+//#define  VCI_LOGGER_ON_ROM
+//#define VCI_LOGGER_ON_L1_TGT
+
+#define _TO_STR(x) #x
+#define TO_STR(x) _TO_STR(x)
+
+#include "segmentation.h"
+
+#if  !(defined(KERNEL_BIN_IMG) || defined(BOOT_INFO_BLOCK))
+#error KERNEL_BIN_IMG or BOOT_INFO_BLOCK macros definition are missed
+#endif 
+
+#include <config.h>
+
+
+static const struct option opts[] = {{"XFB",    required_argument, NULL, 'x'},
+				     {"YFB",    required_argument, NULL, 'y'},
+				     {"FBMODE", required_argument, NULL, 'm'},
+				     {"SSTEP",  required_argument, NULL, 's'},
+				     {"LOGMC0", required_argument, NULL, 'l'},
+				     {"BLKSZ",  required_argument, NULL, 'b'},
+				     {"HELP",   no_argument,       NULL, 'h'},
+				     {NULL,     no_argument,       NULL,  0}};
+
+int _main(int argc, char *argv[])
+{
+	uint64_t       ms1, ms2;
+	struct timeval t1, t2;
+	uint64_t     sstep    = 10000000000ULL;
+	uint64_t     ncycles  = 10000000000ULL;
+	size_t       xfb      = FB_XSIZE;
+	size_t       yfb      = FB_YSIZE;
+	size_t       fb_mode  = 420;
+	size_t       blksz    = SECTOR_SIZE;
+	int          longIndex;
+	int          c;
+	bool         do_loggerMc0 = false;
+
+	using namespace sc_core;
+	// Avoid repeating these everywhere
+	using soclib::common::IntTab;
+	using soclib::common::Segment;
+
+	// Define VCI parameters
+	typedef soclib::caba::VciParams<4,8,32,1,1,1,8,4,4,1> vci_param;
+	typedef soclib::common::Mips32ElIss proc_iss;
+	// Mapping table
+
+	while ((c = getopt_long(argc, argv, "x:y:s:m:l:b:h", opts, &longIndex)) != -1) 
+	{
+	  switch(c) 
+	  {
+	  case 'x':
+	    xfb = atoi(optarg);
+	    break;
+
+	  case 'y':
+	    yfb = atoi(optarg); 
+	    break;
+
+	  case 'm':
+	    fb_mode = atoi(optarg);
+	    break;
+
+	  case 's':
+	    sstep = atoll(optarg);
+	    break;
+
+	  case 'l':
+	    if(strcmp(optarg, "ON") == 0)
+	      do_loggerMc0 = true;
+	    break;
+
+	  case 'b':
+	    blksz = atoi(optarg);
+	    break;
+      
+	  case 'h':
+	    std::cout << "Usage: "<< argv[0] << " <options>" << std::endl << std::endl;
+	    std::cout << "Options:" << std::endl;
+	    std::cout << "  --XFB     : FrameBuffer XSIZE" << std::endl;
+	    std::cout << "  --YFB     : FrameBuffer YSIZE" << std::endl;
+	    std::cout << "  --FBMODE  : FrameBuffer MODE {YUV:420, YUV:422, RGB:0, RGB:16, RGB:32, RGBPAL:256}" << std::endl;
+	    std::cout << "  --SSTEP   : Statistics period" << std::endl;
+	    std::cout << "  --LOGMC0  : {ON|OFF} Trace the charge of directe network input of MemCache0" << std::endl;
+	    std::cout << "  --BLKSZ   : Sector Size (in bytes)" << std::endl;
+	    std::cout << "  --HELP    : Print out command line options" << std::endl << std::endl;
+	    std::cout << "Default: "  << argv[0] 
+		      << " --XFB "    << xfb 
+		      << " --YFB "    << yfb 
+		      << " --FBMODE " << fb_mode
+		      << " --SSTEP "  << sstep 
+		      << " --LOGMC0 " << "OFF"
+		      << " --BLKSZ "  << blksz
+		      << std::endl;
+	    exit(0);
+	    break;
+	  }
+	}
+
+	std::cout << "CONFIG_MEMC_UPDATE_TAB_LINES = " << CONFIG_MEMC_UPDATE_TAB_LINES << std::endl;
+
+	soclib::common::MappingTable maptabp(32, IntTab(8), IntTab(8), 0xF0000000);
+	
+	maptabp.add(Segment("mc_m" , RAM_BASE , RAM_SIZE , IntTab(0), true));
+	maptabp.add(Segment("rom", ROM_BASE, ROM_SIZE, IntTab(1), true));
+
+	maptabp.add(Segment("bd", BD_BASE, BD_SIZE, IntTab(2), false));
+	maptabp.add(Segment("tty"  , TTY_BASE  , TTY_SIZE  , IntTab(3), false));
+	maptabp.add(Segment("xicu" , XICU_BASE , XICU_SIZE , IntTab(4), false));
+	maptabp.add(Segment("dma", DMA_BASE, DMA_SIZE, IntTab(5), false));
+	maptabp.add(Segment("fb", FB_BASE, FB_SIZE, IntTab(6), false));
+
+	std::cout << maptabp << std::endl;
+
+        soclib::common::MappingTable maptabc(32, IntTab(8), IntTab(8), 0xF0000000);
+	maptabc.add(Segment("c_proc0" , PROC0_BASE , PROC0_SIZE , IntTab(0), false, true, IntTab(0)));
+	maptabc.add(Segment("c_proc1" , PROC1_BASE , PROC1_SIZE , IntTab(1), false, true, IntTab(1)));
+	maptabc.add(Segment("c_proc2" , PROC2_BASE , PROC2_SIZE , IntTab(2), false, true, IntTab(2)));
+	maptabc.add(Segment("c_proc3" , PROC3_BASE , PROC3_SIZE , IntTab(3), false, true, IntTab(3)));
+	maptabc.add(Segment("mc_m" , RAM_BASE , RAM_SIZE , IntTab(4), false ));
+	
+	maptabc.add(Segment("rom", ROM_BASE, ROM_SIZE, IntTab(4), true));
+
+	std::cout << maptabc << std::endl;
+	
+	soclib::common::MappingTable maptabx(32, IntTab(8), IntTab(8), 0xF0000000);
+	maptabx.add(Segment("xram" , RAM_BASE , RAM_SIZE , IntTab(0), false));
+	
+	
+	std::cout << maptabx << std::endl;
+
+	//soclib::caba::VciLogger<vci_param> vci_logger0("vci_logger_mc0", maptabp, do_loggerMc0);
+	
+	// Signals
+
+	sc_clock	signal_clk("clk");
+	sc_signal<bool> signal_resetn("resetn");
+   
+	sc_signal<bool> signal_proc0_it0("mips0_it0"); 
+	sc_signal<bool> signal_proc0_it1("mips0_it1"); 
+	sc_signal<bool> signal_proc0_it2("mips0_it2"); 
+	sc_signal<bool> signal_proc0_it3("mips0_it3"); 
+	sc_signal<bool> signal_proc0_it4("mips0_it4"); 
+	sc_signal<bool> signal_proc0_it5("mips0_it5");
+
+	sc_signal<bool> signal_proc1_it0("mips1_it0"); 
+	sc_signal<bool> signal_proc1_it1("mips1_it1"); 
+	sc_signal<bool> signal_proc1_it2("mips1_it2"); 
+	sc_signal<bool> signal_proc1_it3("mips1_it3"); 
+	sc_signal<bool> signal_proc1_it4("mips1_it4"); 
+	sc_signal<bool> signal_proc1_it5("mips1_it5");
+
+	sc_signal<bool> signal_proc2_it0("mips2_it0"); 
+	sc_signal<bool> signal_proc2_it1("mips2_it1"); 
+	sc_signal<bool> signal_proc2_it2("mips2_it2"); 
+	sc_signal<bool> signal_proc2_it3("mips2_it3"); 
+	sc_signal<bool> signal_proc2_it4("mips2_it4"); 
+	sc_signal<bool> signal_proc2_it5("mips2_it5");
+
+	sc_signal<bool> signal_proc3_it0("mips3_it0"); 
+	sc_signal<bool> signal_proc3_it1("mips3_it1"); 
+	sc_signal<bool> signal_proc3_it2("mips3_it2"); 
+	sc_signal<bool> signal_proc3_it3("mips3_it3"); 
+	sc_signal<bool> signal_proc3_it4("mips3_it4"); 
+	sc_signal<bool> signal_proc3_it5("mips3_it5");
+
+	soclib::caba::VciSignals<vci_param> signal_vci_ini_rw_proc0("vci_ini_rw_proc0");
+	soclib::caba::VciSignals<vci_param> signal_vci_ini_c_proc0("vci_ini_c_proc0");
+	soclib::caba::VciSignals<vci_param> signal_vci_tgt_proc0("vci_tgt_proc0");
+
+	soclib::caba::VciSignals<vci_param> signal_vci_ini_rw_proc1("vci_ini_rw_proc1");
+	soclib::caba::VciSignals<vci_param> signal_vci_ini_c_proc1("vci_ini_c_proc1");
+	soclib::caba::VciSignals<vci_param> signal_vci_tgt_proc1("vci_tgt_proc1");
+
+	soclib::caba::VciSignals<vci_param> signal_vci_ini_rw_proc2("vci_ini_rw_proc2");
+	soclib::caba::VciSignals<vci_param> signal_vci_ini_c_proc2("vci_ini_c_proc2");
+	soclib::caba::VciSignals<vci_param> signal_vci_tgt_proc2("vci_tgt_proc2");
+
+	soclib::caba::VciSignals<vci_param> signal_vci_ini_rw_proc3("vci_ini_rw_proc3");
+	soclib::caba::VciSignals<vci_param> signal_vci_ini_c_proc3("vci_ini_c_proc3");
+	soclib::caba::VciSignals<vci_param> signal_vci_tgt_proc3("vci_tgt_proc3");
+
+	soclib::caba::VciSignals<vci_param> signal_vci_tty("signal_vci_tty");
+
+	
+	soclib::caba::VciSignals<vci_param> signal_vci_xicu("signal_vci_xicu");
+	soclib::caba::VciSignals<vci_param> signal_vci_dmai("signal_vci_dmai");
+	soclib::caba::VciSignals<vci_param> signal_vci_dmat("signal_vci_dmat");
+	soclib::caba::VciSignals<vci_param> signal_vci_vcifb("signal_vci_vcifb");
+	soclib::caba::VciSignals<vci_param> signal_vci_vcibd_i("signal_vci_vcibd_i");
+	soclib::caba::VciSignals<vci_param> signal_vci_vcibd_t("signal_vci_vcibd_t");
+	soclib::caba::VciSignals<vci_param> signal_vci_tgt_rom("vci_tgt_rom");
+
+	soclib::caba::VciSignals<vci_param> signal_vci_tgt_xram("vci_tgt_xram");
+
+	soclib::caba::VciSignals<vci_param> signal_vci_ixr_memc("vci_ixr_memc");
+	soclib::caba::VciSignals<vci_param> signal_vci_ini_memc("vci_ini_memc");
+	soclib::caba::VciSignals<vci_param> signal_vci_tgt_memc("vci_tgt_memc");
+	soclib::caba::VciSignals<vci_param> signal_vci_tgt_cleanup_memc("vci_tgt_cleanup_memc");
+
+	sc_signal<bool> signal_icu_irq0("signal_xicu_irq0");
+	sc_signal<bool> signal_icu_irq1("signal_xicu_irq1");
+	sc_signal<bool> signal_icu_irq2("signal_xicu_irq2");
+	sc_signal<bool> signal_icu_irq3("signal_xicu_irq3");
+	sc_signal<bool> signal_icu_irq4("signal_xicu_irq4");
+	sc_signal<bool> signal_icu_irq5("signal_xicu_irq5");
+	sc_signal<bool> signal_icu_irq6("signal_xicu_irq6");
+
+	
+	soclib::common::Loader loader("bootloader.bin",
+				      "kernel-soclib.bin@"TO_STR(KERNEL_BIN_IMG)":D",
+				      "arch-info.bin@"TO_STR(BOOT_INFO_BLOCK)":D");
+
+
+        //                                  init_rw   init_c   tgt
+	soclib::caba::VciCcVCacheWrapper2V1<vci_param, proc_iss > 
+	proc0("proc_0", 0, maptabp, maptabc, IntTab(0),IntTab(0),IntTab(0),
+	      4,16,4,16,
+	      L1_WAYS,L1_SETS,16,
+	      L1_WAYS,L1_SETS,16,
+	      16);
+
+	soclib::caba::VciCcVCacheWrapper2V1<vci_param, proc_iss > 
+	proc1("proc_1", 1, maptabp, maptabc, IntTab(1),IntTab(1),IntTab(1),
+	      4,16,4,16,
+	      L1_WAYS,L1_SETS,16,
+	      L1_WAYS,L1_SETS,16,
+	      16);
+
+	soclib::caba::VciCcVCacheWrapper2V1<vci_param, proc_iss > 
+	proc2("proc_2", 2, maptabp, maptabc, IntTab(2),IntTab(2),IntTab(2),
+	      4,16,4,16,
+	      L1_WAYS,L1_SETS,16,
+	      L1_WAYS,L1_SETS,16,
+	      16);
+
+	soclib::caba::VciCcVCacheWrapper2V1<vci_param, proc_iss > 
+	proc3("proc_3", 3, maptabp, maptabc, IntTab(3),IntTab(3),IntTab(3),
+	      4,16,4,16,
+	      L1_WAYS,L1_SETS,16,
+	      L1_WAYS,L1_SETS,16,
+	      16);
+
+	soclib::caba::VciSimpleRam<vci_param> 
+	rom("rom", IntTab(1), maptabp, loader);
+
+	soclib::caba::VciSimpleRam<vci_param> 
+	  xram("xram", IntTab(0), maptabx, loader, XRAM_LATENCY);
+
+        //                                  x_init    c_init    p_tgt     c_tgt
+	
+#if USE_TSAR_V3
+	soclib::caba::VciMemCacheV3<vci_param> 
+	  memc("memc",maptabp,maptabc,maptabx,IntTab(0),IntTab(4),IntTab(0), IntTab(4),MEMC_WAYS,MEMC_SETS,16,MEMC_HEAP);
+#else
+	soclib::caba::VciMemCacheV2<vci_param> 
+	memc("memc",maptabp,maptabc,maptabx,IntTab(0),IntTab(4),IntTab(0), IntTab(4),16,256,16);
+#endif
+	//memc("memc",maptabp,maptabc,maptabx,IntTab(0),IntTab(4),IntTab(2), IntTab(4),4,16,16,32);
+       
+	soclib::caba::VciXicu<vci_param> vcixicu("vcixicu", maptabp, IntTab(4), 4 /* npti */, 6 /* nhwi */, 4 /* nwti */, 4 /* nirq */);
+
+	soclib::caba::VciMultiTty<vci_param> vcitty("vcitty",	IntTab(3), maptabp, "tty0" ,"tty1", "tty2", "tty3", NULL);
+	soclib::caba::VciDmaTsarV2<vci_param> vcidma("vcidma", maptabp, IntTab(4), IntTab(5), 64);//(1<<(vci_param::K-1))); 
+
+	soclib::caba::VciBlockDeviceTsarV2<vci_param> vcibd("vcitbd", 
+							    maptabp, 
+							    IntTab(5), 
+							    IntTab(2), 
+							    "hdd-img.bin", 
+							    blksz);
+
+	soclib::caba::VciFrameBuffer<vci_param> vcifb("vcifb", IntTab(6), maptabp, xfb, yfb, fb_mode);
+	
+
+#if USE_VCI_LOGGER_ON_L1_CPU0
+  soclib::caba::VciLogger<vci_param> vci_logger0("vci_logger0",maptabp);
+#endif
+
+#if USE_VCI_LOGGER_ON_CPU1
+  soclib::caba::VciLogger<vci_param> vci_logger1("vci_logger1",maptabp);
+#endif
+
+#if USE_VCI_LOGGER_ON_CPU2
+  soclib::caba::VciLogger<vci_param> vci_logger2("vci_logger2",maptabp);
+#endif
+
+#if USE_VCI_LOGGER_ON_CPU3
+  soclib::caba::VciLogger<vci_param> vci_logger3("vci_logger3",maptabp);
+#endif
+
+#if USE_VCI_LOGGER_ON_ROM
+  soclib::caba::VciLogger<vci_param> vci_logger4("vci_logger4",maptabp);
+#endif
+
+
+#if USE_VCI_PROFILER_ON_CPU0
+  soclib::caba::VciProfiler<vci_param, proc_iss> vci_prof0("vci_prof0", 0, 0, 0, 1, 1, 32);
+#endif
+
+#if USE_VCI_PROFILER_ON_CPU1
+  soclib::caba::VciProfiler<vci_param, proc_iss> vci_prof1("vci_prof1", 0, 0, 0, 1, 1, 32);
+#endif
+
+#if USE_VCI_PROFILER_ON_CPU2
+  soclib::caba::VciProfiler<vci_param, proc_iss> vci_prof2("vci_prof2", 0, 0, 0, 1, 1, 32);
+#endif
+
+#if USE_VCI_PROFILER_ON_CPU3
+  soclib::caba::VciProfiler<vci_param, proc_iss> vci_prof3("vci_prof3", 0, 0, 0, 1, 1, 32);
+#endif
+
+#if USE_RING
+  std::cout << "Local Interconnect Type : RING" << std::endl;
+	//soclib::caba::VciVgmn<vci_param> 
+	soclib::caba::VciSimpleRingFast<vci_param, 40, 33> 
+	  ringp("ringp",maptabp, IntTab(), 4, 6, 7);//, /*3*/1, 8);
+	
+	//soclib::caba::VciVgmn<vci_param> 
+	soclib::caba::VciSimpleRingFast<vci_param, 40, 33> 
+	  ringc("ringc",maptabc, IntTab(), 4, 5, 5);//, /*2*/1, 8);
+
+#else
+	std::cout << "Local Interconnect Type : VGMN" << std::endl;
+	soclib::caba::VciVgmn<vci_param> 
+	  ringp("ringp",maptabp, 6, 7, 1, 8);
+	
+	soclib::caba::VciVgmn<vci_param> 
+	  ringc("ringc",maptabc, 5, 5, 1, 8);
+#endif
+
+	proc0.p_clk(signal_clk);  
+	proc0.p_resetn(signal_resetn);  
+	proc0.p_irq[0](signal_proc0_it0); 
+	proc0.p_irq[1](signal_proc0_it1); 
+	proc0.p_irq[2](signal_proc0_it2); 
+	proc0.p_irq[3](signal_proc0_it3); 
+	proc0.p_irq[4](signal_proc0_it4); 
+	proc0.p_irq[5](signal_proc0_it5); 
+	proc0.p_vci_ini_rw(signal_vci_ini_rw_proc0);
+	proc0.p_vci_ini_c(signal_vci_ini_c_proc0);
+	proc0.p_vci_tgt(signal_vci_tgt_proc0);
+
+	proc1.p_clk(signal_clk);  
+	proc1.p_resetn(signal_resetn);  
+	proc1.p_irq[0](signal_proc1_it0); 
+	proc1.p_irq[1](signal_proc1_it1); 
+	proc1.p_irq[2](signal_proc1_it2); 
+	proc1.p_irq[3](signal_proc1_it3); 
+	proc1.p_irq[4](signal_proc1_it4); 
+	proc1.p_irq[5](signal_proc1_it5); 
+	proc1.p_vci_ini_rw(signal_vci_ini_rw_proc1);
+	proc1.p_vci_ini_c(signal_vci_ini_c_proc1);
+	proc1.p_vci_tgt(signal_vci_tgt_proc1);
+
+	proc2.p_clk(signal_clk);  
+	proc2.p_resetn(signal_resetn);  
+	proc2.p_irq[0](signal_proc2_it0); 
+	proc2.p_irq[1](signal_proc2_it1); 
+	proc2.p_irq[2](signal_proc2_it2); 
+	proc2.p_irq[3](signal_proc2_it3); 
+	proc2.p_irq[4](signal_proc2_it4); 
+	proc2.p_irq[5](signal_proc2_it5); 
+	proc2.p_vci_ini_rw(signal_vci_ini_rw_proc2);
+	proc2.p_vci_ini_c(signal_vci_ini_c_proc2);
+	proc2.p_vci_tgt(signal_vci_tgt_proc2);
+
+	proc3.p_clk(signal_clk);  
+	proc3.p_resetn(signal_resetn);  
+	proc3.p_irq[0](signal_proc3_it0); 
+	proc3.p_irq[1](signal_proc3_it1); 
+	proc3.p_irq[2](signal_proc3_it2); 
+	proc3.p_irq[3](signal_proc3_it3); 
+	proc3.p_irq[4](signal_proc3_it4); 
+	proc3.p_irq[5](signal_proc3_it5); 
+	proc3.p_vci_ini_rw(signal_vci_ini_rw_proc3);
+	proc3.p_vci_ini_c(signal_vci_ini_c_proc3);
+	proc3.p_vci_tgt(signal_vci_tgt_proc3);
+
+	rom.p_clk(signal_clk);
+	rom.p_resetn(signal_resetn);
+	rom.p_vci(signal_vci_tgt_rom);
+
+#if USE_VCI_LOGGER_ON_L1_CPU0
+	vci_logger0.p_clk(signal_clk);
+	vci_logger0.p_resetn(signal_resetn);
+	vci_logger0.p_vci(signal_vci_ini_rw_proc0);
+#endif
+
+
+#if USE_VCI_LOGGER_ON_L1_CPU1
+	vci_logger1.p_clk(signal_clk);
+	vci_logger1.p_resetn(signal_resetn);
+	vci_logger1.p_vci(signal_vci_ini_rw_proc1);
+#endif
+
+#if USE_VCI_LOGGER_ON_L1_CPU2
+	vci_logger2.p_clk(signal_clk);
+	vci_logger2.p_resetn(signal_resetn);
+	vci_logger2.p_vci(signal_vci_ini_rw_proc2);
+#endif
+
+#if USE_VCI_LOGGER_ON_L1_CPU3
+	vci_logger3.p_clk(signal_clk);
+	vci_logger3.p_resetn(signal_resetn);
+	vci_logger3.p_vci(signal_vci_ini_rw_proc3);
+#endif
+
+#if USE_VCI_LOGGER_ON_ROM
+	vci_logger4.p_clk(signal_clk);
+	vci_logger4.p_resetn(signal_resetn);
+	vci_logger4.p_vci(signal_vci_tgt_rom);
+#endif
+
+
+#if USE_VCI_PROFILER_ON_CPU0
+	vci_prof0.p_clk(signal_clk);
+	vci_prof0.p_resetn(signal_resetn);
+	vci_prof0.p_vci(signal_vci_ini_rw_proc0);
+	vci_prof0.set_L1_cache(&proc0);
+#endif
+
+#if USE_VCI_PROFILER_ON_CPU1
+	vci_prof1.p_clk(signal_clk);
+	vci_prof1.p_resetn(signal_resetn);
+	vci_prof1.p_vci(signal_vci_ini_rw_proc1);
+	vci_prof1.set_L1_cache(&proc1);
+#endif
+
+#if USE_VCI_PROFILER_ON_CPU2
+	vci_prof2.p_clk(signal_clk);
+	vci_prof2.p_resetn(signal_resetn);
+	vci_prof2.p_vci(signal_vci_ini_rw_proc2);
+	vci_prof2.set_L1_cache(&proc2);
+#endif
+
+#if USE_VCI_PROFILER_ON_CPU3
+	vci_prof3.p_clk(signal_clk);
+	vci_prof3.p_resetn(signal_resetn);
+	vci_prof3.p_vci(signal_vci_ini_rw_proc3);
+	vci_prof3.set_L1_cache(&proc3);
+#endif
+
+	vcixicu.p_resetn(signal_resetn);
+	vcixicu.p_clk(signal_clk);
+	vcixicu.p_vci(signal_vci_xicu);
+	vcixicu.p_hwi[0](signal_icu_irq0);
+	vcixicu.p_hwi[1](signal_icu_irq1);
+	vcixicu.p_hwi[2](signal_icu_irq2);
+	vcixicu.p_hwi[3](signal_icu_irq3);
+	vcixicu.p_hwi[4](signal_icu_irq4);
+	vcixicu.p_hwi[5](signal_icu_irq5);
+
+	vcixicu.p_irq[0](signal_proc0_it0);
+	vcixicu.p_irq[1](signal_proc1_it0);
+	vcixicu.p_irq[2](signal_proc2_it0);
+	vcixicu.p_irq[3](signal_proc3_it0);
+	vcidma.p_clk(signal_clk);
+	vcidma.p_resetn(signal_resetn);
+	vcidma.p_irq(signal_icu_irq4); 
+
+	vcifb.p_clk(signal_clk);
+	vcifb.p_resetn(signal_resetn);
+	vcifb.p_vci(signal_vci_vcifb);
+
+	vcitty.p_clk(signal_clk);
+	vcitty.p_resetn(signal_resetn);
+	vcitty.p_vci(signal_vci_tty);
+	vcitty.p_irq[0](signal_icu_irq0); 
+	vcitty.p_irq[1](signal_icu_irq1); 
+	vcitty.p_irq[2](signal_icu_irq2); 
+	vcitty.p_irq[3](signal_icu_irq3); 
+
+
+	vcidma.p_vci_target(signal_vci_dmat);
+	vcidma.p_vci_initiator(signal_vci_dmai);
+	
+	memc.p_clk(signal_clk);
+	memc.p_resetn(signal_resetn);
+	memc.p_vci_tgt(signal_vci_tgt_memc);
+	memc.p_vci_tgt_cleanup(signal_vci_tgt_cleanup_memc);
+	memc.p_vci_ini(signal_vci_ini_memc);
+	memc.p_vci_ixr(signal_vci_ixr_memc);
+
+	vcibd.p_clk(signal_clk);
+	vcibd.p_resetn(signal_resetn);
+	vcibd.p_vci_target(signal_vci_vcibd_t);
+	vcibd.p_vci_initiator(signal_vci_vcibd_i);
+	vcibd.p_irq(signal_icu_irq5);
+
+
+	xram.p_clk(signal_clk);
+	xram.p_resetn(signal_resetn);
+	xram.p_vci(signal_vci_ixr_memc);
+	
+
+	ringp.p_clk(signal_clk);
+	ringp.p_resetn(signal_resetn);
+
+	ringc.p_clk(signal_clk);
+	ringc.p_resetn(signal_resetn);
+
+	ringp.p_to_initiator[0](signal_vci_ini_rw_proc0);
+	ringp.p_to_initiator[1](signal_vci_ini_rw_proc1);
+	ringp.p_to_initiator[2](signal_vci_ini_rw_proc2);
+	ringp.p_to_initiator[3](signal_vci_ini_rw_proc3);
+	ringp.p_to_initiator[4](signal_vci_dmai);
+	ringp.p_to_initiator[5](signal_vci_vcibd_i);
+	
+
+	ringc.p_to_initiator[0](signal_vci_ini_c_proc0);
+	ringc.p_to_initiator[1](signal_vci_ini_c_proc1);
+	ringc.p_to_initiator[2](signal_vci_ini_c_proc2);
+	ringc.p_to_initiator[3](signal_vci_ini_c_proc3);
+	ringc.p_to_initiator[4](signal_vci_ini_memc);
+
+
+	ringp.p_to_target[0](signal_vci_tgt_memc);
+	ringp.p_to_target[1](signal_vci_tgt_rom);
+	ringp.p_to_target[2](signal_vci_vcibd_t);
+	ringp.p_to_target[3](signal_vci_tty);
+	ringp.p_to_target[4](signal_vci_xicu);
+	ringp.p_to_target[5](signal_vci_dmat);
+	ringp.p_to_target[6](signal_vci_vcifb);
+
+	ringc.p_to_target[0](signal_vci_tgt_proc0);
+	ringc.p_to_target[1](signal_vci_tgt_proc1);
+	ringc.p_to_target[2](signal_vci_tgt_proc2);
+	ringc.p_to_target[3](signal_vci_tgt_proc3);
+	ringc.p_to_target[4](signal_vci_tgt_cleanup_memc);
+
+
+	sc_start(sc_core::sc_time(0, SC_NS));
+	signal_resetn = false;
+
+	sc_start(sc_core::sc_time(1, SC_NS));
+	signal_resetn = true;
+
+	if (gettimeofday(&t1, NULL) != 0) {
+	      perror("gettimeofday");
+	      return EXIT_FAILURE;
+	}
+	
+	for(uint64_t i=1 ; i<ncycles ; i++)
+	{
+	  sc_start(sc_core::sc_time(1, SC_NS));
+	  
+	  if ( (i % sstep) == 0)
+	  {
+	    memc.print_stats();
+	    proc0.print_trace();
+	    proc0.print_stats();
+	    proc0.clear_stats();
+	   
+#if 1
+	    proc1.print_trace();
+	    proc1.print_stats();
+	    proc1.clear_stats();
+	    
+	    proc2.print_trace();
+	    proc2.print_stats();
+	    proc2.clear_stats();
+	    
+	    proc3.print_trace();
+	    proc3.print_stats();
+	    proc3.clear_stats();
+#endif
+	  }
+
+	  /*
+	   * execute 10 million cycle, compute how many time it took and
+	   * print the clock frequency
+	   */
+	  
+	  if( (i % 10000000) == 0)
+	  {
+
+	    if (gettimeofday(&t2, NULL) != 0) 
+	    {
+	      perror("gettimeofday");
+	      return EXIT_FAILURE;
+	    }
+	    
+	    ms1 = (uint64_t)t1.tv_sec * 1000ULL + (uint64_t)t1.tv_usec / 1000;
+	    ms2 = (uint64_t)t2.tv_sec * 1000ULL + (uint64_t)t2.tv_usec / 1000;
+	    std::cerr << "platform clock frequency " << (double)10000000ULL / (double)(ms2 - ms1) << "Khz" << std::endl;
+	   
+	    if (gettimeofday(&t1, NULL) != 0) 
+	    {
+	      perror("gettimeofday");
+	      return EXIT_FAILURE;
+	    }
+	  }
+	}
+
+	return EXIT_SUCCESS;
+}
+
+int sc_main (int argc, char *argv[])
+{
+	try {
+		return _main(argc, argv);
+	} catch (std::exception &e) {
+		std::cout << e.what() << std::endl;
+	} catch (...) {
+		std::cout << "Unknown exception occured" << std::endl;
+		throw;
+	}
+	return 1;
+}
Index: branches/v4/platforms/almos-tsarv3-platforms/multi-clusters/Makefile
===================================================================
--- branches/v4/platforms/almos-tsarv3-platforms/multi-clusters/Makefile	(revision 371)
+++ branches/v4/platforms/almos-tsarv3-platforms/multi-clusters/Makefile	(revision 371)
@@ -0,0 +1,6 @@
+ARCH=mips32el
+SOCLIB?=$(shell soclib-cc --getpath)
+NO_SOFT=1
+export SOCLIB
+SOCLIB_CC_ADD_ARGS='-v -I../common -I.'
+include $(SOCLIB)/soclib/platform/topcells/all.mk
Index: branches/v4/platforms/almos-tsarv3-platforms/multi-clusters/config.h
===================================================================
--- branches/v4/platforms/almos-tsarv3-platforms/multi-clusters/config.h	(revision 371)
+++ branches/v4/platforms/almos-tsarv3-platforms/multi-clusters/config.h	(revision 371)
@@ -0,0 +1,150 @@
+#ifndef _TSAR_CONFIG_H_
+#define _TSAR_CONFIG_H_
+
+#define yes 1
+#define no  0
+
+///////////////////////////////////////////////////
+//                Memory system          
+///////////////////////////////////////////////////
+
+#define USE_MEMCACHE_V3                       yes
+#define USE_MEMCACHE_V4                       no
+
+#define CONFIG_MEMC_UPDATE_TAB_LINES          4
+#define CONFIG_MEMC_TRANSACTION_TAB_LINES     4
+
+#define MEMC_WAYS                             16
+#define MEMC_SETS                             256
+
+#define L1_IWAYS                              4
+#define L1_ISETS                              64
+
+#define L1_DWAYS                              4
+#define L1_DSETS                              64
+
+#define TLB_IWAYS                             4
+#define TLB_ISETS                             16
+
+#define TLB_DWAYS                             4
+#define TLB_DSETS                             16
+
+#define CONFIG_XRAM_LATENCY                   0
+
+///////////////////////////////////////////////////
+//              Operating System
+///////////////////////////////////////////////////
+
+#define USE_ALMOS                yes
+
+
+///////////////////////////////////////////////////
+//              Peripheral Devices 
+/////////////////////////////////////////////////// 
+
+#define USE_FRAME_BUFFER         no
+
+#define	SECTOR_SIZE	         4096
+#define BDEV_IMAGE_NAME	         "hdd-img.bin"
+#define BDEV_NAME_LEN            128
+
+#define N_TTYS		         4
+
+///////////////////////////////////////////////////
+//               Parallelisation
+///////////////////////////////////////////////////
+#define USE_OPENMP               yes
+
+///////////////////////////////////////////////////
+//               Local-Interconnect
+//////////////////////////////////////////////////
+#define USE_LOCAL_RING           no
+
+///////////////////////////////////////////////////
+//               Global-Interconnect
+///////////////////////////////////////////////////
+#define VDSPIN_CMD_IN_LEN         4
+#define VDSPIN_CMD_OUT_LEN        4
+#define VDSPIN_RSP_IN_LEN         4
+#define VDSPIN_RSP_OUT_LEN        4
+
+///////////////////////////////////////////////////
+//               Profiling & Debug
+///////////////////////////////////////////////////
+
+#define USE_LOGGER_ON_CPUs           no
+#define USE_LOGGER_ON_DMA            no
+#define USE_PROFILER_ON_CPUs         yes
+#define USE_GDBSERVER                no
+
+#define VCI_LOGGER_ON_ROM            no
+#define VCI_LOGGER_ON_MC_IO          no
+#define VCI_LOGGER_ON_MC0_D          no
+#define VCI_LOGGER_ON_MC2_D          no
+#define VCI_LOGGER_ON_BDEV           no
+
+#define CONFIG_LOGGER_START_CYCLE    6000000
+
+#define CONFIG_RING_IDEBUG           no
+#define CONFIG_RING_HIDEBUG          no
+#define CONFIG_RING_TDEBUG           no
+#define CONFIG_RING_HTDEBUG          no
+
+
+///////////////////////////////////////////////////
+//        Physical Address Sapce         
+///////////////////////////////////////////////////
+// segments definition in direct space.
+// There is 16 Mbytes address space per cluster.
+// The 8 MSB bits define the cluster index (x,y),
+// even if the number of clusters is less than 256.
+// Each memory cache contains up to 12 Mbytes.
+// There is one MEMC segment and one XICU segment 
+// per cluster. The peripherals BDEV, FBUF, MTTY, 
+// CDMA and the boot BROM are mapped in cluster 
+// containing address 0xBFC00000
+///////////////////////////////////////////////////
+
+#define MEMC_BASE                0x00000000      
+#define MEMC_SIZE                0x00C00000
+
+#define BROM_BASE                0xBFC00000      
+#define BROM_SIZE                0x00100000
+
+#define FBUF_BASE                0xBFD00000      
+#define FBUF_SIZE                0x00200000
+
+#define XICU_BASE                0x00F00000      
+#define XICU_SIZE                0x00002000
+
+#define BDEV_BASE                0xBFF10000      
+#define BDEV_SIZE                0x00000100
+
+#define MTTY_BASE                0xBFF20000      
+#define MTTY_SIZE                0x00000100
+
+#define CDMA_BASE                0xBFF30000      
+#define CDMA_SIZE                0x00000100
+
+
+////////////////////////////////////////////////////////////////////
+//     TGTID & SRCID definition in direct space
+// For all components:  global TGTID = global SRCID = cluster_index
+// For processors, the local SRCID is between 0 & nprocs-1
+////////////////////////////////////////////////////////////////////
+
+#define MEMC_TGTID               0
+#define XICU_TGTID               1
+#define FBUF_TGTID               2
+#define MTTY_TGTID               3
+#define BROM_TGTID               4
+#define BDEV_TGTID               5
+#define CDMA_TGTID               6
+
+#define PROC_SRCID               0
+#define BDEV_SRCID               nprocs
+#define CDMA_SRCID               (nprocs+1)
+
+#define CONFIG_ADDRESS_WIDTH     32
+
+#endif	/* _TSAR_CONFIG_H_ */
Index: branches/v4/platforms/almos-tsarv3-platforms/multi-clusters/config/config.h
===================================================================
--- branches/v4/platforms/almos-tsarv3-platforms/multi-clusters/config/config.h	(revision 371)
+++ branches/v4/platforms/almos-tsarv3-platforms/multi-clusters/config/config.h	(revision 371)
@@ -0,0 +1,3 @@
+namespace config {
+  #include "../config.h"
+}
Index: branches/v4/platforms/almos-tsarv3-platforms/multi-clusters/config/config.sd
===================================================================
--- branches/v4/platforms/almos-tsarv3-platforms/multi-clusters/config/config.sd	(revision 371)
+++ branches/v4/platforms/almos-tsarv3-platforms/multi-clusters/config/config.sd	(revision 371)
@@ -0,0 +1,13 @@
+
+# -*- python -*-
+
+__id__ = "$Id: todo $"
+__version__ = "$vision: 0 $"
+
+Module('config:config',
+	header_files = [
+		'../config.h',
+		]
+)
+
+
Index: branches/v4/platforms/almos-tsarv3-platforms/multi-clusters/platform_desc
===================================================================
--- branches/v4/platforms/almos-tsarv3-platforms/multi-clusters/platform_desc	(revision 371)
+++ branches/v4/platforms/almos-tsarv3-platforms/multi-clusters/platform_desc	(revision 371)
@@ -0,0 +1,26 @@
+ 
+# -*- python -*-
+
+todo = Platform('caba', 'top.cpp',
+	uses = [
+    
+#           Uses('caba:vci_cc_vcache_wrapper2_v1', iss_t = 'common:mips32el'),
+#           Uses('caba:vci_mem_cache_v3'),
+#           Uses('caba:vci_local_ring_fast', ring_cmd_data_size = 40, ring_rsp_data_size = 33),
+#	    Uses('caba:vci_cluster', iss_t = 'common:gdb_iss', gdb_iss_t = 'common:mips32el', cmd_width = 40, rsp_width = 33),
+
+            Uses('caba:tsarv4_cluster_xbar', iss_t = 'common:mips32el', cmd_width = 40, rsp_width = 33),
+            Uses('common:elf_file_loader'),
+            Uses('common:plain_file_loader'),
+	],
+	cell_size = 4,
+	plen_size = 8,
+	addr_size = 32,
+	rerror_size = 1,
+	clen_size = 1,
+	rflag_size = 1,
+	srcid_size = 14,
+	pktid_size = 4,
+	trdid_size = 4,
+	wrplen_size = 1,
+)
Index: branches/v4/platforms/almos-tsarv3-platforms/multi-clusters/soclib.conf
===================================================================
--- branches/v4/platforms/almos-tsarv3-platforms/multi-clusters/soclib.conf	(revision 371)
+++ branches/v4/platforms/almos-tsarv3-platforms/multi-clusters/soclib.conf	(revision 371)
@@ -0,0 +1,23 @@
+config.lib_systemcass_openmp_mine = Library(
+	parent = config.systemc,
+	dir = "/users/outil/nbsdtsar/systemcass",
+	libdir = "%(dir)s/lib-linux",
+	cflags = config.systemc.cflags+['-fopenmp']+['-O3'],
+	#cflags = config.systemc.cflags,
+	libs = ['-ldl', '-lm', '-lpthread', '-L%(libdir)s', '-lsystemc', '-rdynamic', '-fopenmp'],
+	#libs = ['-ldl', '-lm', '-lpthread', '-L%(libdir)s', '-lsystemc', '-rdynamic'],
+)
+
+config.systemcass_openmp_mine = BuildEnv(
+	parent = config.systemc_64,
+	libraries = [ config.lib_systemcass_openmp_mine ],
+	#base = config.systemc_32,
+	repos = "/dsk/l1/misc/almaless/soclib-cc/head/systemcass-mine",
+	cache_file = "/dsk/l1/misc/almaless/soclib-cc/head/systemcass-mine/soclib_cc.cache",
+	toolchain = config.toolchain_64,
+	#toolchain = config.dist_toolchain,
+)
+
+#config.default = config.systemcass
+#config.default = config.systemcass_openmp
+config.default = config.systemcass_openmp_mine
Index: branches/v4/platforms/almos-tsarv3-platforms/multi-clusters/soclib.conf32
===================================================================
--- branches/v4/platforms/almos-tsarv3-platforms/multi-clusters/soclib.conf32	(revision 371)
+++ branches/v4/platforms/almos-tsarv3-platforms/multi-clusters/soclib.conf32	(revision 371)
@@ -0,0 +1,23 @@
+config.lib_systemcass_openmp_mine = Library(
+	parent = config.systemc,
+	dir = "/users/outil/nbsdtsar/systemcass32",
+	libdir = "%(dir)s/lib-linux",
+	cflags = config.systemc.cflags+['-fopenmp']+['-O3'],
+	#cflags = config.systemc.cflags,
+	libs = ['-ldl', '-lm', '-lpthread', '-L%(libdir)s', '-lsystemc', '-rdynamic', '-fopenmp'],
+	#libs = ['-ldl', '-lm', '-lpthread', '-L%(libdir)s', '-lsystemc', '-rdynamic'],
+)
+
+config.systemcass_openmp_mine = BuildEnv(
+	parent = config.systemc,
+	libraries = [ config.lib_systemcass_openmp_mine ],
+	base = config.systemc_32,
+	repos = "/dsk/l1/misc/almaless/soclib-cc/head/systemcass-mine-32",
+	cache_file = "/dsk/l1/misc/almaless/soclib-cc/head/systemcass-mine-32/soclib_cc.cache",
+	toolchain = config.toolchain,
+	#toolchain = config.dist_toolchain,
+)
+
+#config.default = config.systemcass
+#config.default = config.systemcass_openmp
+config.default = config.systemcass_openmp_mine
Index: branches/v4/platforms/almos-tsarv3-platforms/multi-clusters/soclib.conf64
===================================================================
--- branches/v4/platforms/almos-tsarv3-platforms/multi-clusters/soclib.conf64	(revision 371)
+++ branches/v4/platforms/almos-tsarv3-platforms/multi-clusters/soclib.conf64	(revision 371)
@@ -0,0 +1,23 @@
+config.lib_systemcass_openmp_mine = Library(
+	parent = config.systemc,
+	dir = "/users/outil/nbsdtsar/systemcass",
+	libdir = "%(dir)s/lib-linux",
+	cflags = config.systemc.cflags+['-fopenmp']+['-O3'],
+	#cflags = config.systemc.cflags,
+	libs = ['-ldl', '-lm', '-lpthread', '-L%(libdir)s', '-lsystemc', '-rdynamic', '-fopenmp'],
+	#libs = ['-ldl', '-lm', '-lpthread', '-L%(libdir)s', '-lsystemc', '-rdynamic'],
+)
+
+config.systemcass_openmp_mine = BuildEnv(
+	parent = config.systemc_64,
+	libraries = [ config.lib_systemcass_openmp_mine ],
+	#base = config.systemc_32,
+	repos = "/dsk/l1/misc/almaless/soclib-cc/head/systemcass-mine",
+	cache_file = "/dsk/l1/misc/almaless/soclib-cc/head/systemcass-mine/soclib_cc.cache",
+	toolchain = config.toolchain_64,
+	#toolchain = config.dist_toolchain,
+)
+
+#config.default = config.systemcass
+#config.default = config.systemcass_openmp
+config.default = config.systemcass_openmp_mine
Index: branches/v4/platforms/almos-tsarv3-platforms/multi-clusters/top.cpp
===================================================================
--- branches/v4/platforms/almos-tsarv3-platforms/multi-clusters/top.cpp	(revision 371)
+++ branches/v4/platforms/almos-tsarv3-platforms/multi-clusters/top.cpp	(revision 371)
@@ -0,0 +1,773 @@
+/////////////////////////////////////////////////////////////////////////
+// File: tsarv4_vgmn_generic_32_top.cpp
+// Author: Alain Greiner
+// Copyright: UPMC/LIP6
+// Date : november 5 2010
+// This program is released under the GNU public license
+/////////////////////////////////////////////////////////////////////////
+// This file define a generic TSAR architecture without virtual memory.
+// - It uses the vci_vgmn as global interconnect 
+// - It uses the vci_local_crossbar  as local interconnect 
+// - It uses the vci_cc_xcache (No MMU) 
+// The physical address space is 32 bits.
+// The number of clusters cannot be larger than 256.
+// The three parameters are 
+// - xmax : number of clusters in a row
+// - ymax : number of clusters in a column
+// - nprocs : number of processor per cluster
+//
+// Each cluster contains nprocs processors, one Memory Cache,
+// and one XICU component.
+// The peripherals BDEV, CDMA, FBUF, MTTY and the boot BROM
+// are in the cluster containing address 0xBFC00000.
+// - The bdev_irq is connected to IRQ_IN[0]
+// - The cdma_irq is connected to IRQ_IN[1]
+// - The tty_irq[i] is connected to IRQ_IN[i+2]
+// For all clusters, the XICU component contains nprocs timers.
+// 
+// As we target up to 256 clusters, each cluster can contain 
+// at most 16 Mbytes (in a 4Gbytes address space).
+// There is one MEMC segment and one XICU segment per cluster.
+// - Each memory cache contains 8 Mbytes.
+// - The Frame buffer contains 4 Mbytes.
+// - The Boot ROM contains 1 Mbytes
+//
+// General policy for 32 bits address decoding:
+// To simplifly, all segments base addresses are aligned
+// on 64 Kbytes addresses. Therefore the 16 address MSB bits
+// define the target in the direct address space.
+// In these 16 bits, the (x_width + y_width) MSB bits define
+// the cluster index, and the 8 LSB bits define the local index:
+// 
+//      | X_ID  | Y_ID  |---| L_ID |     OFFSET          |
+//	|x_width|y_width|---|  8   |       16            |
+/////////////////////////////////////////////////////////////////////////
+
+#include <systemc>
+#include <sys/time.h>
+#include <iostream>
+#include <sstream>
+#include <cstdlib>
+#include <cstdarg>
+#include <stdint.h>
+
+#include "mapping_table.h"
+#include "tsarv4_cluster_xbar.h"
+#include "mips32.h"
+#include "vci_simple_ram.h"
+
+#include "alloc_elems.h"
+#include "config.h"
+
+#if USE_OPENMP
+#include <omp.h>
+#endif
+
+#if USE_VCI_PROFILER
+#include "vci_profiler.h"
+#endif
+
+#if USE_GDBSERVER
+#include "gdbserver.h"
+#endif
+
+
+#if USE_ALMOS
+#define BOOT_INFO_BLOCK 0xbfc08000
+#define KERNEL_BIN_IMG  0xbfc10000
+#endif
+
+//  cluster index (computed from x,y coordinates)
+#define cluster(x,y)	(y + ymax*x)
+
+#define _TO_STR(_str) #_str
+#define  TO_STR(_str) _TO_STR(_str)
+
+// flit widths for the DSPIN network
+#define cmd_width	         40
+#define rsp_width	         33
+
+// VCI format
+#define cell_width	         4
+#define address_width	         32
+#define plen_width	         8
+#define error_width	         1
+#define clen_width	         1
+#define rflag_width	         1
+#define srcid_width	         14
+#define pktid_width	         4
+#define trdid_width	         4
+#define wrplen_width	         1
+
+
+/////////////////////////////////
+int _main(int argc, char *argv[])
+{
+    using namespace sc_core;
+    using namespace soclib::caba;
+    using namespace soclib::common;
+    
+    uint64_t       ms1, ms2;
+    struct timeval t1, t2;
+    
+    char    soft_name[BDEV_NAME_LEN] = "to_be_defined";	// pathname to binary code
+    char    disk_name[BDEV_NAME_LEN] = BDEV_IMAGE_NAME;   // pathname to the disk image
+    size_t  ncycles        = 1000000000;       // simulated cycles
+    size_t  xmax           = 2;		       // number of clusters in a row
+    size_t  ymax           = 2;                // number of clusters in a column
+    size_t  nprocs         = 1;		// number of processors per cluster
+    size_t  xfb            = 512;	// frameBuffer column number
+    size_t  yfb            = 512;       // frameBuffer lines number
+    size_t  fb_mode        = 420;
+    #define DEBUG_OK       no
+    size_t  from_cycle     = 0;                // debug start cycle
+    size_t  memc_size      = MEMC_SIZE;
+    size_t  blk_size       = SECTOR_SIZE;
+    size_t  l1_i_ways      = L1_IWAYS;
+    size_t  l1_d_ways      = L1_DWAYS;
+    size_t  l1_i_sets      = L1_ISETS;
+    size_t  l1_d_sets      = L1_DSETS;
+    size_t  memc_sets      = MEMC_SETS;
+    size_t  memc_ways      = MEMC_WAYS;
+    size_t  itlb_ways      = TLB_IWAYS;
+    size_t  itlb_sets      = TLB_ISETS;
+    size_t  dtlb_ways      = TLB_DWAYS;
+    size_t  dtlb_sets      = TLB_DSETS;
+    size_t  xram_latency   = CONFIG_XRAM_LATENCY;
+    size_t  omp_threads    = 1;
+    ////////////// command line arguments //////////////////////
+    if (argc > 1)
+    {
+      for( int n=1 ; n<argc ; n=n+2 )
+      {
+	    if( (strcmp(argv[n],"-NCYCLES") == 0) && (n+1<argc) )
+            {
+                ncycles = atoi(argv[n+1]);
+            }
+            else if( (strcmp(argv[n],"-NPROCS") == 0) && (n+1<argc) )
+            {
+                nprocs = atoi(argv[n+1]);
+                assert( ((nprocs == 1) || (nprocs == 2) || (nprocs == 4)) &&
+                        "NPROCS must be equal to 1, 2, or 4");
+            }
+            else if( (strcmp(argv[n],"-THREADS") == 0) && (n+1<argc) )
+            {
+	        omp_threads = atoi(argv[n+1]);
+            }
+            else if( (strcmp(argv[n],"-XMAX") == 0) && (n+1<argc) )
+            {
+                xmax = atoi(argv[n+1]);
+                assert( ((xmax == 1) || (xmax == 2) || (xmax == 4) || (xmax == 8) || (xmax == 16)) 
+                         && "The XMAX parameter must be 2, 4, 8, or 16" );
+            }
+	    else if( (strcmp(argv[n],"-YMAX") == 0) && (n+1<argc) )
+            {
+                ymax = atoi(argv[n+1]);
+                assert( ((ymax == 1) || (ymax == 2) || (ymax == 4) || (ymax == 8) || (ymax == 16)) 
+                         && "The YMAX parameter must be 2, 4, 8, or 16" );
+            }
+	    else if( (strcmp(argv[n],"-XFB") == 0) && (n+1<argc) )
+            {
+	        xfb = atoi(argv[n+1]);
+            }
+	    else if( (strcmp(argv[n],"-YFB") == 0) && (n+1<argc) )
+            {
+                yfb = atoi(argv[n+1]);
+            }
+	    else if( (strcmp(argv[n], "-FBMODE") == 0) && (n+1 < argc))
+	    {
+	      fb_mode = atoi(argv[n+1]);
+	    }
+            else if( (strcmp(argv[n],"-SOFT") == 0) && (n+1<argc) )
+            {
+                strcpy(soft_name, argv[n+1]);
+            }
+            else if( (strcmp(argv[n],"-DISK") == 0) && (n+1<argc) )
+            {
+                strcpy(disk_name, argv[n+1]);
+            }
+	    else if( (strcmp(argv[n],"-BLKSZ") == 0) && (n+1<argc) )
+            {
+	      blk_size = atoi(argv[n+1]);
+	      assert(((blk_size % 512) == 0) && "BDEV: Block size must be multiple of 512 bytes");
+            }
+            else if( (strcmp(argv[n],"-TRACE") == 0) && (n+1<argc) )
+            {
+                from_cycle = atoi(argv[n+1]);
+            }
+	    else if((strcmp(argv[n], "-MEMSZ") == 0) && (n+1 < argc))
+	    {
+	        memc_size = atoi(argv[n+1]);
+	    }
+	    else if((strcmp(argv[n], "-MCWAYS") == 0) && (n+1 < argc))
+	    {
+	        memc_ways = atoi(argv[n+1]);
+	    }
+	    else if((strcmp(argv[n], "-MCSETS") == 0) && (n+1 < argc))
+	    {
+	        memc_sets = atoi(argv[n+1]);
+	    }
+	    else if((strcmp(argv[n], "-L1_IWAYS") == 0) && (n+1 < argc))
+	    {
+	        l1_i_ways = atoi(argv[n+1]);
+	    }
+	    else if((strcmp(argv[n], "-L1_ISETS") == 0) && (n+1 < argc))
+	    {
+	        l1_i_sets = atoi(argv[n+1]);
+	    }
+	    else if((strcmp(argv[n], "-L1_DWAYS") == 0) && (n+1 < argc))
+	    {
+	        l1_d_ways = atoi(argv[n+1]);
+	    }
+	    else if((strcmp(argv[n], "-L1_DSETS") == 0) && (n+1 < argc))
+	    {
+	        l1_d_sets = atoi(argv[n+1]);
+	    }
+	    else if((strcmp(argv[n], "-ITLB_WAYS") == 0) && (n+1 < argc))
+	    {
+	        itlb_ways = atoi(argv[n+1]);
+	    }
+	    else if((strcmp(argv[n], "-ITLB_SETS") == 0) && (n+1 < argc))
+	    {
+	        itlb_sets = atoi(argv[n+1]);
+	    }
+	    else if((strcmp(argv[n], "-DTLB_WAYS") == 0) && (n+1 < argc))
+	    {
+	        dtlb_ways = atoi(argv[n+1]);
+	    }
+	    else if((strcmp(argv[n], "-DTLB_SETS") == 0) && (n+1 < argc))
+	    {
+	        dtlb_sets = atoi(argv[n+1]);
+	    }
+	    else if((strcmp(argv[n], "-XLATENCY") == 0) && (n+1 < argc))
+	    {
+	        xram_latency = atoi(argv[n+1]);
+	    }
+            else
+            {
+                std::cout << "   Arguments on the command line are (key,value) couples." << std::endl;
+                std::cout << "   The order is not important." << std::endl;
+                std::cout << "   Accepted arguments are :" << std::endl << std::endl;
+                std::cout << "     -SOFT pathname_for_embedded_soft" << std::endl;
+                std::cout << "     -DISK pathname_for_disk_image" << std::endl;
+		std::cout << "     -BLKSZ sector size in bytes ( must be multiple of 512 bytes )" << std::endl;
+                std::cout << "     -NCYCLES number_of_simulated_cycles" << std::endl;
+                std::cout << "     -NPROCS number_of_processors_per_cluster" << std::endl;
+                std::cout << "     -XMAX number_of_clusters_in_a_row" << std::endl;
+                std::cout << "     -YMAX number_of_clusters_in_a_column" << std::endl;
+                std::cout << "     -TRACE debug_start_cycle" << std::endl;
+                std::cout << "     -MCWAYS memory_cache_number_of_ways" << std::endl;
+                std::cout << "     -MCSETS memory_cache_number_of_sets" << std::endl;
+		std::cout << "     -L1_IWAYS L1_instruction_cache_number_of_ways" << std::endl;
+		std::cout << "     -L1_ISETS L1_instruction_cache_number_of_sets" << std::endl;
+		std::cout << "     -L1_DWAYS L1_data_cache_number_of_ways" << std::endl;
+		std::cout << "     -L1_DSETS L1_data_cache_number_of_sets" << std::endl;
+                std::cout << "     -XLATENCY external_ram_latency_value" << std::endl;
+                std::cout << "     -XFB fram_buffer_number_of_pixels" << std::endl;
+                std::cout << "     -YFB fram_buffer_number_of_lines" << std::endl;
+		std::cout << "     -FBMODE fram buffer subsampling integer value (YUV:420,YUV:422,RGB:0,RGB:16,RGB:32,RGBPAL:256)" << std::endl;
+		std::cout << "     -MEMSZ per-cluster memory size ( <= 12 MB )" << std::endl;
+                std::cout << "     -THREADS number_of_cores_for_OpenMP" << std::endl;
+                exit(0);
+            }
+        }
+    }
+
+    
+    std::cout << "Simulation Parameters:" << std::endl;
+    std::cout << "          OMP_THREADS_NR        = " << omp_threads << std::endl;
+    std::cout << "          XFB                   = " << xfb << std::endl;
+    std::cout << "          YFB                   = " << yfb << std::endl;
+    std::cout << "          FB_MODE               = " << fb_mode << std::endl;
+    std::cout << "          SECTOR_SIZE  (Bytes)  = " << blk_size << std::endl;
+    std::cout << "          RAM/CLSTR    (Bytes)  = " << memc_size << std::endl;
+    std::cout << "          XRAM_LATENCY (cycles) = " << xram_latency << std::endl;
+    std::cout << "          MEMC_UPD_TBL          = " << CONFIG_MEMC_UPDATE_TAB_LINES << std::endl;
+    std::cout << "          MEMC_TRN_TLB          = " << CONFIG_MEMC_TRANSACTION_TAB_LINES <<std::endl;
+    std::cout << "          MEMC_WAYS             = " << memc_ways << std::endl;
+    std::cout << "          MEMC_SETS             = " << memc_sets << std::endl;
+    std::cout << "          L1_IWAYS              = " << l1_i_ways << std::endl;
+    std::cout << "          L1_ISETS              = " << l1_i_sets << std::endl;
+    std::cout << "          L1_DWAYS              = " << l1_d_ways << std::endl;
+    std::cout << "          L1_DSETS              = " << l1_d_sets << std::endl;
+    std::cout << "          ITLB_WAYS             = " << itlb_ways << std::endl;
+    std::cout << "          ITLB_SETS             = " << itlb_sets << std::endl;
+    std::cout << "          DTLB_WAYS             = " << dtlb_ways << std::endl;
+    std::cout << "          DTLB_SETS             = " << dtlb_sets << std::endl;
+    
+#define CONFIG_MEMC_TRANSACTION_TAB_LINES     8
+
+#define MEMC_WAYS                             16
+#define MEMC_SETS                             256
+
+#define L1_IWAYS                              4
+#define L1_ISETS                              64
+
+#define L1_DWAYS                              4
+#define L1_DSETS                              64
+
+#define TLB_IWAYS                             4
+#define TLB_ISETS                             16
+
+#define TLB_DWAYS                             4
+#define TLB_DSETS                             16
+
+#define CONFIG_XRAM_LATENCY                   0
+
+
+
+#if USE_OPENMP
+        omp_set_dynamic(false);
+        omp_set_num_threads(omp_threads);
+        std::cerr << "Built with openmp version " << _OPENMP << std::endl;
+#endif
+
+
+    // Define VCI parameters
+    typedef soclib::caba::VciParams<cell_width,
+                                    plen_width,
+                                    address_width,
+                                    error_width,                                   
+                                    clen_width,
+                                    rflag_width,
+                                    srcid_width,
+                                    pktid_width,
+                                    trdid_width,
+                                    wrplen_width> vci_param;
+
+    size_t	cluster_io_index;
+    size_t	x_width;
+    size_t	y_width;
+
+    if      (xmax == 2) x_width = 1;
+    else if (xmax <= 4) x_width = 2;
+    else if (xmax <= 8) x_width = 3;
+    else                x_width = 4;
+
+    if      (ymax == 2) y_width = 1;
+    else if (ymax <= 4) y_width = 2;
+    else if (ymax <= 8) y_width = 3;
+    else                y_width = 4;
+
+    cluster_io_index = 0xBF >> (8 - x_width - y_width);
+    
+    /////////////////////
+    //  Mapping Tables
+    /////////////////////
+
+    // direct network
+    MappingTable maptabd(address_width, 
+                         IntTab(x_width + y_width, 16 - x_width - y_width), 
+                         IntTab(x_width + y_width, srcid_width - x_width - y_width), 
+                         0x00F00000);
+
+    for ( size_t x = 0 ; x < xmax ; x++)
+    {
+        for ( size_t y = 0 ; y < ymax ; y++)
+        {
+            sc_uint<address_width> offset  = cluster(x,y) << (address_width-x_width-y_width);
+            std::ostringstream 	sm;
+            sm << "d_seg_memc_" << x << "_" << y;
+            maptabd.add(Segment(sm.str(), MEMC_BASE+offset, memc_size, IntTab(cluster(x,y),MEMC_TGTID), true));
+            std::ostringstream 	si;
+            si << "d_seg_xicu_" << x << "_" << y;
+            maptabd.add(Segment(si.str(), XICU_BASE+offset, XICU_SIZE, IntTab(cluster(x,y),XICU_TGTID), false));
+            if ( cluster(x,y) == cluster_io_index )
+            {
+	      maptabd.add(Segment("d_seg_fbuf", FBUF_BASE, FBUF_SIZE, IntTab(cluster(x,y),FBUF_TGTID), false));
+	      maptabd.add(Segment("d_seg_bdev", BDEV_BASE, BDEV_SIZE, IntTab(cluster(x,y),BDEV_TGTID), false));
+	      maptabd.add(Segment("d_seg_mtty", MTTY_BASE, MTTY_SIZE, IntTab(cluster(x,y),MTTY_TGTID), false));
+	      maptabd.add(Segment("d_seg_brom", BROM_BASE, BROM_SIZE, IntTab(cluster(x,y),BROM_TGTID), true));
+	      maptabd.add(Segment("d_seg_cdma", CDMA_BASE, CDMA_SIZE, IntTab(cluster(x,y),CDMA_TGTID), false));
+            }
+        }
+    }
+    std::cout << maptabd << std::endl;
+
+    // coherence network
+    MappingTable maptabc(address_width, 
+                         IntTab(x_width + y_width, 12 - x_width - y_width), 
+                         IntTab(x_width + y_width, srcid_width - x_width - y_width), 
+                         0xF0000000);
+
+    for ( size_t x = 0 ; x < xmax ; x++)
+    {
+        for ( size_t y = 0 ; y < ymax ; y++)
+        {
+            sc_uint<address_width> offset  = cluster(x,y) << (address_width-x_width-y_width);
+            
+            std::ostringstream sm;
+            sm << "c_seg_memc_" << x << "_" << y;
+            maptabc.add(Segment(sm.str(), MEMC_BASE+offset, memc_size, IntTab(cluster(x,y), nprocs), false));
+            // the segment base and size will be modified 
+            // when the segmentation of the coherence space will be simplified
+
+            if ( cluster(x,y) == cluster_io_index )
+            {
+                std::ostringstream sr;
+                sr << "c_seg_brom_" << x << "_" << y;
+                maptabc.add(Segment(sr.str(), BROM_BASE, BROM_SIZE, IntTab(cluster(x,y), nprocs), false));
+            }
+
+	    sc_uint<address_width> avoid_collision  = 0;
+	    for ( size_t p = 0 ; p < nprocs ; p++)
+            {
+	        sc_uint<address_width> base = memc_size + (p*0x100000) + offset;
+                // the following test is to avoid a collision between the c_seg_brom segment
+                // and a c_seg_proc segment (all segments base addresses being multiple of 1Mbytes)
+                if ( base == BROM_BASE ) avoid_collision = 0x100000;
+	        std::ostringstream sp;
+	        sp << "c_seg_proc_" << x << "_" << y << "_" << p;
+	        maptabc.add(Segment(sp.str(), base + avoid_collision, 0x20, IntTab(cluster(x,y), p), false, 
+				  true, IntTab(cluster(x,y), p))); 
+                // the two last arguments will be removed 
+                // when the segmentation of the coherence space will be simplified
+            }
+        }
+    }
+    std::cout << maptabc << std::endl;
+
+    // external network
+    MappingTable maptabx(address_width, IntTab(1), IntTab(10), 0xF0000000);
+
+    for ( size_t x = 0 ; x < xmax ; x++)
+    {
+        for ( size_t y = 0 ; y < ymax ; y++)
+        { 
+	  sc_uint<address_width> offset  = cluster(x,y) << (address_width-x_width-y_width);
+	  std::ostringstream sx;
+	  
+	  sx << "seg_xram_" << x << "_" << y;
+	  maptabx.add(Segment(sx.str(), MEMC_BASE + offset, memc_size, IntTab(cluster(x,y)), false));
+        }
+    }
+    std::cout << maptabx << std::endl;
+
+    ////////////////////
+    // Signals
+    ///////////////////
+
+    sc_clock		signal_clk("clk");
+    sc_signal<bool> 	signal_resetn("resetn");
+    sc_signal<bool>	signal_false;
+   
+
+    // Horizontal inter-clusters DSPIN signals
+    DspinSignals<cmd_width>*** signal_dspin_h_cmd_inc =
+      alloc_elems<DspinSignals<cmd_width> >("signal_dspin_h_cmd_inc", xmax-1, ymax, 2);
+    DspinSignals<cmd_width>*** signal_dspin_h_cmd_dec =
+      alloc_elems<DspinSignals<cmd_width> >("signal_dspin_h_cmd_dec", xmax-1, ymax, 2);
+    DspinSignals<rsp_width>*** signal_dspin_h_rsp_inc =
+      alloc_elems<DspinSignals<rsp_width> >("signal_dspin_h_rsp_inc", xmax-1, ymax, 2);
+    DspinSignals<rsp_width>*** signal_dspin_h_rsp_dec =
+      alloc_elems<DspinSignals<rsp_width> >("signal_dspin_h_rsp_dec", xmax-1, ymax, 2);
+
+    // Vertical inter-clusters DSPIN signals
+    DspinSignals<cmd_width>*** signal_dspin_v_cmd_inc =
+      alloc_elems<DspinSignals<cmd_width> >("signal_dspin_v_cmd_inc", xmax, ymax-1, 2);
+    DspinSignals<cmd_width>*** signal_dspin_v_cmd_dec =
+        alloc_elems<DspinSignals<cmd_width> >("signal_dspin_v_cmd_dec", xmax, ymax-1, 2);
+    DspinSignals<rsp_width>*** signal_dspin_v_rsp_inc =
+        alloc_elems<DspinSignals<rsp_width> >("signal_dspin_v_rsp_inc", xmax, ymax-1, 2);
+    DspinSignals<rsp_width>*** signal_dspin_v_rsp_dec =
+        alloc_elems<DspinSignals<rsp_width> >("signal_dspin_v_rsp_dec", xmax, ymax-1, 2);
+
+    // Mesh boundaries DSPIN signals
+    DspinSignals<cmd_width>**** signal_dspin_false_cmd_in =
+        alloc_elems<DspinSignals<cmd_width> >("signal_dspin_false_cmd_in", xmax,  ymax, 2, 4);
+    DspinSignals<cmd_width>**** signal_dspin_false_cmd_out =
+        alloc_elems<DspinSignals<cmd_width> >("signal_dspin_false_cmd_out", xmax, ymax, 2, 4);
+    DspinSignals<rsp_width>**** signal_dspin_false_rsp_in =
+        alloc_elems<DspinSignals<rsp_width> >("signal_dspin_false_rsp_in", xmax, ymax, 2, 4);
+    DspinSignals<rsp_width>**** signal_dspin_false_rsp_out =
+        alloc_elems<DspinSignals<rsp_width> >("signal_dspin_false_rsp_out", xmax, ymax, 2, 4);
+
+    // Xternal network VCI signals
+    VciSignals<vci_param> signal_vci_tgt_x_xram("signal_vci_tgt_x_xram");
+
+    ////////////////////////////
+    //      Components
+    ////////////////////////////
+
+#if USE_ALMOS
+    soclib::common::Loader loader("bootloader.bin",
+				  "arch-info.bin@"TO_STR(BOOT_INFO_BLOCK)":D",
+				  "kernel-soclib.bin@"TO_STR(KERNEL_BIN_IMG)":D");
+#else
+    soclib::common::Loader loader(soft_name);
+#endif
+
+#if USE_GDBSERVER
+    typedef soclib::common::GdbServer<soclib::common::Mips32ElIss> proc_iss;
+    proc_iss::set_loader(loader);
+#else
+    typedef soclib::common::Mips32ElIss proc_iss;
+#endif
+
+
+    TsarV4ClusterXbar<vci_param, proc_iss, cmd_width, rsp_width>* clusters[xmax][ymax];
+
+#if USE_OPENMP
+
+#pragma omp parallel
+    {
+#pragma omp for
+      for( int i = 0 ; i  < (xmax * ymax); i++)
+      {
+	size_t x = i / ymax;
+	size_t y = i % ymax;
+#pragma omp critical
+	{
+	  std::ostringstream sc;
+	  sc << "cluster_" << x << "_" << y;
+	  clusters[x][y] = new TsarV4ClusterXbar<vci_param, proc_iss, cmd_width, rsp_width>
+	    (sc.str().c_str(),
+	   nprocs,
+	     x,
+	     y,
+	     cluster(x,y),
+	     maptabd,
+	     maptabc,
+	     maptabx,
+	     x_width,
+	     y_width,
+	     MEMC_TGTID,
+	     XICU_TGTID,
+	     FBUF_TGTID,
+	     MTTY_TGTID,
+	     BROM_TGTID,
+	     BDEV_TGTID,
+	     CDMA_TGTID,
+	     memc_ways,
+	     memc_sets,
+	     l1_i_ways,
+	     l1_i_sets,
+	     l1_d_ways,
+	     l1_d_sets,
+	     xram_latency,
+	     (cluster(x,y) == cluster_io_index),
+	     xfb,
+	     yfb,
+	     fb_mode,
+	     disk_name,
+	     blk_size,
+	     loader);
+	}
+      }
+    }
+
+#else  // USE_OPENMP
+    for( size_t x = 0 ; x  < xmax ; x++)
+    {
+      for( size_t y = 0 ; y < ymax ; y++ )
+      {
+	std::ostringstream sc;
+	sc << "cluster_" << x << "_" << y;
+	
+	clusters[x][y] = new TsarV4ClusterXbar<vci_param, proc_iss, cmd_width, rsp_width>
+	  (sc.str().c_str(),
+	   nprocs,
+	   x,
+	   y,
+	   cluster(x,y),
+	   maptabd,
+	   maptabc,
+	   maptabx,
+	   x_width,
+	   y_width,
+	   MEMC_TGTID,
+	   XICU_TGTID,
+	   FBUF_TGTID,
+	   MTTY_TGTID,
+	   BROM_TGTID,
+	   BDEV_TGTID,
+	   CDMA_TGTID,
+	   memc_ways,
+	   memc_sets,
+	   l1_i_ways,
+	   l1_i_sets,
+	   l1_d_ways,
+	   l1_d_sets,
+	   xram_latency,
+	   (cluster(x,y) == cluster_io_index),
+	   xfb,
+	   yfb,
+	   fb_mode,
+	   disk_name,
+	   blk_size,
+	   loader);
+	}
+      }
+#endif	// USE_OPENMP
+
+    ///////////////////////////////////////////////////////////////
+    //     Net-list 
+    ///////////////////////////////////////////////////////////////
+
+    // Clock & RESET
+    for ( size_t x = 0 ; x < (xmax) ; x++ )
+    {
+        for ( size_t y = 0 ; y < ymax ; y++ )
+        {
+            clusters[x][y]->p_clk			(signal_clk);
+            clusters[x][y]->p_resetn			(signal_resetn);
+        }
+    }
+
+    // Inter Clusters horizontal connections
+    if ( xmax > 1 )
+    {
+        for ( size_t x = 0 ; x < (xmax-1) ; x++ )
+        {
+            for ( size_t y = 0 ; y < ymax ; y++ )
+            {
+                for ( size_t k = 0 ; k < 2 ; k++ )
+                {
+		clusters[x][y]->p_cmd_out[k][EAST]      (signal_dspin_h_cmd_inc[x][y][k]);
+                clusters[x+1][y]->p_cmd_in[k][WEST]     (signal_dspin_h_cmd_inc[x][y][k]);
+                clusters[x][y]->p_cmd_in[k][EAST]       (signal_dspin_h_cmd_dec[x][y][k]);
+                clusters[x+1][y]->p_cmd_out[k][WEST]    (signal_dspin_h_cmd_dec[x][y][k]);
+                clusters[x][y]->p_rsp_out[k][EAST]      (signal_dspin_h_rsp_inc[x][y][k]);
+                clusters[x+1][y]->p_rsp_in[k][WEST]     (signal_dspin_h_rsp_inc[x][y][k]);
+                clusters[x][y]->p_rsp_in[k][EAST]       (signal_dspin_h_rsp_dec[x][y][k]);
+                clusters[x+1][y]->p_rsp_out[k][WEST]    (signal_dspin_h_rsp_dec[x][y][k]);
+                }
+            }
+        }
+    }
+    std::cout << "Horizontal connections established" << std::endl;	
+
+    // Inter Clusters vertical connections
+    if ( ymax > 1 )
+    {
+        for ( size_t y = 0 ; y < (ymax-1) ; y++ )
+        {
+            for ( size_t x = 0 ; x < xmax ; x++ )
+            {
+                for ( size_t k = 0 ; k < 2 ; k++ )
+                {
+                clusters[x][y]->p_cmd_out[k][NORTH]     (signal_dspin_v_cmd_inc[x][y][k]);
+                clusters[x][y+1]->p_cmd_in[k][SOUTH]    (signal_dspin_v_cmd_inc[x][y][k]);
+                clusters[x][y]->p_cmd_in[k][NORTH]      (signal_dspin_v_cmd_dec[x][y][k]);
+                clusters[x][y+1]->p_cmd_out[k][SOUTH]   (signal_dspin_v_cmd_dec[x][y][k]);
+                clusters[x][y]->p_rsp_out[k][NORTH]     (signal_dspin_v_rsp_inc[x][y][k]);
+                clusters[x][y+1]->p_rsp_in[k][SOUTH]    (signal_dspin_v_rsp_inc[x][y][k]);
+                clusters[x][y]->p_rsp_in[k][NORTH]      (signal_dspin_v_rsp_dec[x][y][k]);
+                clusters[x][y+1]->p_rsp_out[k][SOUTH]   (signal_dspin_v_rsp_dec[x][y][k]);
+                }
+            }
+        }
+    }
+
+   std::cout << "Vertical connections established" << std::endl;
+
+    // East & West boundary cluster connections
+    for ( size_t y = 0 ; y < ymax ; y++ )
+    {
+        for ( size_t k = 0 ; k < 2 ; k++ )
+        {
+	    clusters[0][y]->p_cmd_in[k][WEST]       	(signal_dspin_false_cmd_in[0][y][k][WEST]);
+	    clusters[0][y]->p_cmd_out[k][WEST]      	(signal_dspin_false_cmd_out[0][y][k][WEST]);
+	    clusters[0][y]->p_rsp_in[k][WEST]       	(signal_dspin_false_rsp_in[0][y][k][WEST]);
+	    clusters[0][y]->p_rsp_out[k][WEST]      	(signal_dspin_false_rsp_out[0][y][k][WEST]);
+	  
+	    clusters[xmax-1][y]->p_cmd_in[k][EAST]  	(signal_dspin_false_cmd_in[xmax-1][y][k][EAST]);
+	    clusters[xmax-1][y]->p_cmd_out[k][EAST] 	(signal_dspin_false_cmd_out[xmax-1][y][k][EAST]);
+	    clusters[xmax-1][y]->p_rsp_in[k][EAST]  	(signal_dspin_false_rsp_in[xmax-1][y][k][EAST]);
+	    clusters[xmax-1][y]->p_rsp_out[k][EAST] 	(signal_dspin_false_rsp_out[xmax-1][y][k][EAST]);
+	}
+    }
+    
+    // North & South boundary clusters connections
+    for ( size_t x = 0 ; x < xmax ; x++ )
+    {
+        for ( size_t k = 0 ; k < 2 ; k++ )
+        {
+	    clusters[x][0]->p_cmd_in[k][SOUTH]      	(signal_dspin_false_cmd_in[x][0][k][SOUTH]);
+	    clusters[x][0]->p_cmd_out[k][SOUTH]     	(signal_dspin_false_cmd_out[x][0][k][SOUTH]);
+	    clusters[x][0]->p_rsp_in[k][SOUTH]      	(signal_dspin_false_rsp_in[x][0][k][SOUTH]);
+	    clusters[x][0]->p_rsp_out[k][SOUTH]     	(signal_dspin_false_rsp_out[x][0][k][SOUTH]);
+	    
+	    clusters[x][ymax-1]->p_cmd_in[k][NORTH] 	(signal_dspin_false_cmd_in[x][ymax-1][k][NORTH]);
+	    clusters[x][ymax-1]->p_cmd_out[k][NORTH]	(signal_dspin_false_cmd_out[x][ymax-1][k][NORTH]);
+	    clusters[x][ymax-1]->p_rsp_in[k][NORTH] 	(signal_dspin_false_rsp_in[x][ymax-1][k][NORTH]);
+	    clusters[x][ymax-1]->p_rsp_out[k][NORTH]	(signal_dspin_false_rsp_out[x][ymax-1][k][NORTH]);
+	}
+    }
+      
+    ////////////////////////////////////////////////////////
+    //   Simulation
+    ///////////////////////////////////////////////////////
+
+    sc_start(sc_core::sc_time(0, SC_NS));
+    signal_resetn = false;
+
+    // network boundaries signals
+    for(size_t x=0; x<xmax ; x++)
+    {
+        for(size_t y=0 ; y<ymax ; y++)
+        {
+            for (size_t k=0; k<2; k++)
+            {
+                for(size_t a=0; a<4; a++)
+                {
+		        signal_dspin_false_cmd_in[x][y][k][a].write = false;
+		        signal_dspin_false_cmd_in[x][y][k][a].read = true;
+                        signal_dspin_false_cmd_out[x][y][k][a].write = false;
+                        signal_dspin_false_cmd_out[x][y][k][a].read = true;
+
+                        signal_dspin_false_rsp_in[x][y][k][a].write = false;
+                        signal_dspin_false_rsp_in[x][y][k][a].read = true;
+                        signal_dspin_false_rsp_out[x][y][k][a].write = false;
+                        signal_dspin_false_rsp_out[x][y][k][a].read = true;
+		}
+            }
+        }
+    }
+
+    sc_start(sc_core::sc_time(1, SC_NS));
+    signal_resetn = true;
+
+    if (gettimeofday(&t1, NULL) != 0) 
+    {
+      perror("gettimeofday");
+      return EXIT_FAILURE;
+    }
+
+    while(1)
+    {
+      sc_start(sc_core::sc_time(100000000, SC_NS));
+
+      if (gettimeofday(&t2, NULL) != 0) 
+      {
+	perror("gettimeofday");
+	return EXIT_FAILURE;
+      }
+	    
+      ms1 = (uint64_t)t1.tv_sec * 1000ULL + (uint64_t)t1.tv_usec / 1000;
+      ms2 = (uint64_t)t2.tv_sec * 1000ULL + (uint64_t)t2.tv_usec / 1000;
+      
+      std::cerr << "platform clock frequency " << (double)100000000ULL / (double)(ms2 - ms1) << "Khz" << std::endl;
+	   
+      if (gettimeofday(&t1, NULL) != 0) 
+      {
+	perror("gettimeofday");
+	return EXIT_FAILURE;
+      }
+    }
+
+    return EXIT_SUCCESS;
+}
+
+int sc_main (int argc, char *argv[])
+{
+	try {
+		return _main(argc, argv);
+	} catch (std::exception &e) {
+		std::cout << e.what() << std::endl;
+	} catch (...) {
+		std::cout << "Unknown exception occured" << std::endl;
+		throw;
+	}
+	return 1;
+}
Index: branches/v4/platforms/almos-tsarv3-platforms/multi-clusters/tsarv4_cluster_xbar/caba/metadata/tsarv4_cluster_xbar.sd
===================================================================
--- branches/v4/platforms/almos-tsarv3-platforms/multi-clusters/tsarv4_cluster_xbar/caba/metadata/tsarv4_cluster_xbar.sd	(revision 371)
+++ branches/v4/platforms/almos-tsarv3-platforms/multi-clusters/tsarv4_cluster_xbar/caba/metadata/tsarv4_cluster_xbar.sd	(revision 371)
@@ -0,0 +1,85 @@
+
+# -*- python -*-
+
+Module('caba:tsarv4_cluster_xbar',
+	classname = 'soclib::caba::TsarV4ClusterXbar',
+	tmpl_parameters = [
+		parameter.Module('vci_param', default = 'caba:vci_param'),
+		parameter.Module('iss_t'),
+		parameter.Int('cmd_width'),
+		parameter.Int('rsp_width'),
+		],
+	header_files = [ '../source/include/tsarv4_cluster_xbar.h', ],
+	implementation_files = [ '../source/src/tsarv4_cluster_xbar.cpp', ],
+	uses = [
+		Uses('caba:base_module'),
+		Uses('common:mapping_table'),
+		Uses('common:iss2'),
+                Uses('config:config'),
+                Uses('caba:vci_cc_vcache_wrapper2_v1', iss_t = 'common:mips32el'),
+                #Uses('caba:vci_cc_xcache_wrapper_v4', iss_t = 'common:gdb_iss', gdb_iss_t = 'common:mips32el'),
+                #Uses('caba:vci_mem_cache_v4'),
+                Uses('caba:vci_mem_cache_v3'),
+            	Uses('caba:vci_simple_ram'),
+            	Uses('caba:vci_xicu'),
+            	Uses('caba:vci_local_crossbar'),
+            	Uses('caba:virtual_dspin_router', flit_width = parameter.Reference('cmd_width')),
+            	Uses('caba:virtual_dspin_router', flit_width = parameter.Reference('rsp_width')),
+                
+            	Uses('caba:vci_vdspin_target_wrapper',
+                     dspin_cmd_width = parameter.Reference('cmd_width'), 
+                     dspin_rsp_width = parameter.Reference('rsp_width')),
+
+            	Uses('caba:vci_vdspin_initiator_wrapper',
+                     dspin_cmd_width = parameter.Reference('cmd_width'), 
+                     dspin_rsp_width = parameter.Reference('rsp_width')),
+                
+                Uses('caba:vci_local_ring_fast',
+                     ring_cmd_data_size = parameter.Reference('cmd_width'),
+                     ring_rsp_data_size = parameter.Reference('rsp_width')),
+                
+		Uses('caba:vci_multi_tty'),
+		Uses('caba:vci_framebuffer'),
+                Uses('caba:vci_profiler'),
+                Uses('caba:vci_logger'),
+		Uses('caba:vci_block_device_tsar_v2'),
+		Uses('caba:vci_dma_tsar_v2'),
+		Uses('common:elf_file_loader'),
+		],
+        instance_parameters = [
+                parameter.Int('n_x'),
+                parameter.Int('n_y'),
+		parameter.Int('n_cluster'),
+		parameter.Module('mtd', 'common:mapping_table'),
+                parameter.Module('mtc', 'common:mapping_table'),
+		parameter.Module('mtx', 'common:mapping_table'),
+		parameter.Int('x_width'),
+		parameter.Int('y_width'),
+		parameter.Int('memc_tgtid'),
+		parameter.Int('xicu_tgtid'),
+		parameter.Int('fbuf_tgtid'),
+		parameter.Int('mtty_tgtid'),
+		parameter.Int('brom_tgtid'),
+		parameter.Int('bdev_tgtid'),
+		parameter.Int('cdma_tgtid'),
+		parameter.Int('memc_ways'),
+		parameter.Int('memc_sets'),
+		parameter.Int('l1_i_ways'),
+		parameter.Int('l1_i_sets'),
+		parameter.Int('l1_d_ways'),
+		parameter.Int('l1_d_sets'),
+                parameter.Int('xram_latency'),
+		parameter.Bool('io'),
+                ],
+
+	ports = [
+		Port('caba:bit_in', 'p_resetn', auto = 'resetn'),
+		Port('caba:clock_in', 'p_clk', auto = 'clock'),
+		Port('caba:dspin_output', 'p_cmd_out', [2, 4], dspin_data_size = parameter.Reference('cmd_width')),
+		Port('caba:dspin_input', 'p_cmd_in', [2, 4], dspin_data_size = parameter.Reference('cmd_width')),
+		Port('caba:dspin_output', 'p_rsp_out', [2, 4], dspin_data_size = parameter.Reference('rsp_width')), 
+                Port('caba:dspin_input', 'p_rsp_in', [2, 4], dspin_data_size = parameter.Reference('rsp_width')),
+		],
+)
+
+
Index: branches/v4/platforms/almos-tsarv3-platforms/multi-clusters/tsarv4_cluster_xbar/caba/source/include/tsarv4_cluster_xbar.h
===================================================================
--- branches/v4/platforms/almos-tsarv3-platforms/multi-clusters/tsarv4_cluster_xbar/caba/source/include/tsarv4_cluster_xbar.h	(revision 371)
+++ branches/v4/platforms/almos-tsarv3-platforms/multi-clusters/tsarv4_cluster_xbar/caba/source/include/tsarv4_cluster_xbar.h	(revision 371)
@@ -0,0 +1,233 @@
+//////////////////////////////////////////////////////////////////////////////
+// File: tsarv4_cluster_xbar.h
+// Author: Alain Greiner 
+// Copyright: UPMC/LIP6
+// Date : march 2011
+// This program is released under the GNU public license
+//////////////////////////////////////////////////////////////////////////////
+// This file define a TSAR cluster architecture without virtual memory,
+// - It uses the virtual_dspin_router  as distributed global interconnect 
+// - It uses the vci_local_crossbar as local interconnect 
+// - It uses the vci_cc_xcache_wrapper_v4
+// - It uses the vci_mem_cache_v4
+// - It contains a private RAM a variable latency to emulate the L3 cache
+// - It can contains 1, 2 or 4 processors
+// - Each processor has a private local TTY terminal (vci_multi_tty)
+// - Each processor has a private dma channel (vci_multi_dma)
+// - It uses the vci_xicu interrupt controller
+// - The nprocs tty irq are connected to IRQ_IN[0]...IRQ_IN[3]
+// - The nprocs dma irq are connected to IRQ_IN[4]...IRQ_IN[7]
+// - The peripherals BDEV, FBUF, and the boot BROM are in the cluster 
+//   containing address 0xBFC00000, and the bdev_irq is connected to IRQ_IN[8]
+////////////////////////////////////////////////////////////////////////////////// 
+
+#ifndef SOCLIB_CABA_TSAR_CLUSTER_V4_XBAR_H
+#define SOCLIB_CABA_TSAR_CLUSTER_V4_XBAR_H
+
+#include <systemc>
+#include <sys/time.h>
+#include <iostream>
+#include <sstream>
+#include <cstdlib>
+#include <cstdarg>
+
+//#include "gdbserver.h"
+#include "virtual_dspin_router.h"
+#include "mapping_table.h"
+#include "mips32.h"
+#include "vci_simple_ram.h"
+#include "vci_xicu.h"
+#include "vci_multi_tty.h"
+#include "vci_block_device_tsar_v2.h"
+#include "vci_framebuffer.h"
+#include "vci_dma_tsar_v2.h"
+#include "vci_logger.h"
+#include "config.h"
+
+#if USE_LOCAL_RING
+#include "vci_local_ring_fast.h"
+#else
+#include "vci_local_crossbar.h"
+#include "vci_vdspin_target_wrapper.h"
+#include "vci_vdspin_initiator_wrapper.h"
+#endif
+
+#if USE_MEMCACHE_V3
+#include "vci_mem_cache_v3.h"
+#include "vci_cc_vcache_wrapper2_v1.h"
+#endif
+
+#if USE_MEMCACHE_V4
+#include "vci_mem_cache_v4.h"
+#include "vci_cc_xcache_wrapper_v4.h"
+#endif
+
+
+#if !(USE_MEMCACHE_V3 ^ USE_MEMCACHE_V4)
+#error One version of TSAR memory system must be provieded (V3 or V4)
+#endif
+
+#if (USE_LOGGER_ON_CPUs && USE_PROFILER_ON_CPUs)
+#error Either Logger or Profiler can be used, you have to make a choice !
+#endif
+
+
+#if USE_PROFILER_ON_CPUs
+#include "vci_profiler.h"
+#endif
+
+namespace soclib {
+namespace caba	{
+
+///////////////////////////////////////////////////////////////////////////
+template<typename vci_param, typename iss_t, int cmd_width, int rsp_width>
+class TsarV4ClusterXbar 
+///////////////////////////////////////////////////////////////////////////
+    : public soclib::caba::BaseModule
+{
+
+  public:
+
+	// Ports
+    	sc_in<bool>                             		p_clk;
+    	sc_in<bool>                             		p_resetn;
+	soclib::caba::DspinOutput<cmd_width>   			**p_cmd_out;
+	soclib::caba::DspinInput<cmd_width>    			**p_cmd_in;
+        soclib::caba::DspinOutput<rsp_width>                   	**p_rsp_out;
+        soclib::caba::DspinInput<rsp_width>                   	**p_rsp_in;
+
+        // interrupt signals
+	sc_signal<bool>     		signal_false;
+	sc_signal<bool> 		signal_proc_it[4];
+	//sc_signal<bool> 		signal_irq_mdma[4];
+	sc_signal<bool> 		signal_irq_cdma;
+	sc_signal<bool>*    		signal_irq_mtty;
+	sc_signal<bool> 		signal_irq_bdev;
+	
+	// DSPIN signals between DSPIN routers and VCI/DSPIN wrappers
+	DspinSignals<cmd_width> 	signal_dspin_cmd_l2g_d; 
+	DspinSignals<cmd_width> 	signal_dspin_cmd_g2l_d; 
+	DspinSignals<cmd_width> 	signal_dspin_cmd_l2g_c;
+	DspinSignals<cmd_width> 	signal_dspin_cmd_g2l_c; 
+	DspinSignals<rsp_width> 	signal_dspin_rsp_l2g_d; 
+	DspinSignals<rsp_width> 	signal_dspin_rsp_g2l_d; 
+	DspinSignals<rsp_width> 	signal_dspin_rsp_l2g_c;
+	DspinSignals<rsp_width> 	signal_dspin_rsp_g2l_c;
+
+	// VCI signals between VCI/DSPIN wrappers and local crossbars
+	VciSignals<vci_param>  		signal_vci_l2g_d; 
+	VciSignals<vci_param>  		signal_vci_g2l_d; 
+	VciSignals<vci_param>  		signal_vci_l2g_c; 
+	VciSignals<vci_param>  		signal_vci_g2l_c; 
+
+	// Direct VCI signals
+	VciSignals<vci_param> 		signal_vci_ini_d_proc[4]; 
+	VciSignals<vci_param>  		signal_vci_ini_d_bdev; 
+	VciSignals<vci_param>  		signal_vci_ini_d_cdma; 
+
+	VciSignals<vci_param>		signal_vci_tgt_d_memc;
+	VciSignals<vci_param> 		signal_vci_tgt_d_mtty;
+	VciSignals<vci_param> 		signal_vci_tgt_d_xicu;
+	VciSignals<vci_param> 		signal_vci_tgt_d_bdev;
+	VciSignals<vci_param> 		signal_vci_tgt_d_cdma;
+	VciSignals<vci_param> 		signal_vci_tgt_d_brom;
+	VciSignals<vci_param> 		signal_vci_tgt_d_fbuf;
+
+	// Coherence VCi signals
+	VciSignals<vci_param> 		signal_vci_ini_c_proc[4];
+	VciSignals<vci_param> 		signal_vci_tgt_c_proc[4];
+	VciSignals<vci_param> 		signal_vci_ini_c_memc;
+	VciSignals<vci_param> 		signal_vci_tgt_c_memc;
+
+	// external RAM VCI signal
+	VciSignals<vci_param> 		signal_vci_xram;
+	
+        // Components
+
+#if USE_MEMCACHE_V4
+        VciCcXCacheWrapperV4<vci_param, iss_t>*                 	proc[4];
+        VciMemCacheV4<vci_param>*                               	memc;
+#endif
+
+#if USE_MEMCACHE_V3
+        VciCcVCacheWrapper2V1<vci_param, iss_t>*                        proc[4];
+        VciMemCacheV3<vci_param>*                                       memc;
+#endif
+
+#if USE_PROFILER_ON_CPUs
+	soclib::caba::VciProfiler<vci_param, iss_t> *profiler[4];
+#endif
+
+#if USE_LOGGER_ON_CPUs
+	VciLogger<vci_param> *vci_logger[10];
+#endif
+
+#if USE_LOGGER_ON_DMA
+	VciLogger<vci_param> *vci_dma_logger;
+#endif
+
+	VciXicu<vci_param>*                                     	xicu;
+
+#if USE_LOCAL_RING
+	VciLocalRingFast<vci_param,cmd_width,rsp_width>*                xbard;
+        VciLocalRingFast<vci_param,cmd_width,rsp_width>*                xbarc;
+#else
+        VciLocalCrossbar<vci_param>*        				xbard;
+        VciLocalCrossbar<vci_param>*        				xbarc;
+	VciVdspinTargetWrapper<vci_param,cmd_width,rsp_width>*		tgtwrapperd;
+        VciVdspinInitiatorWrapper<vci_param,cmd_width,rsp_width>*	iniwrapperd;
+        VciVdspinTargetWrapper<vci_param,cmd_width,rsp_width>*		tgtwrapperc;
+        VciVdspinInitiatorWrapper<vci_param,cmd_width,rsp_width>*	iniwrapperc;
+#endif
+	VirtualDspinRouter<cmd_width>*   	                	cmdrouter;
+        VirtualDspinRouter<rsp_width>*	                        	rsprouter;
+        VciSimpleRam<vci_param>*                 			brom;
+        VciMultiTty<vci_param>*                  			mtty;
+
+#if USE_FRAME_BUFFER
+        VciFrameBuffer<vci_param>*               			fbuf;
+#else
+	VciLogger<vci_param>*                   			fbuf;
+#endif
+
+        VciBlockDeviceTsarV2<vci_param>*         			bdev;
+	VciDmaTsarV2<vci_param>*                                        cdma;
+        VciSimpleRam<vci_param>*					xram;
+
+	TsarV4ClusterXbar(	sc_module_name  insname,
+                        size_t		nprocs,					// number of processors 
+			size_t		n_x,					// x coordinate
+			size_t		n_y,					// y coordinate
+			size_t		n_cluster,				// y + ymax*x
+			const 		soclib::common::MappingTable &mtd,	// direct mapping table
+			const		soclib::common::MappingTable &mtc,	// coherence mapping table
+			const		soclib::common::MappingTable &mtx,	// xram mapping table
+			size_t		x_width,				// x field number of bits
+			size_t		y_width,				// y field number of bits
+                        size_t		tgtid_memc,
+                        size_t		tgtid_xicu,
+                        size_t		tgtid_fbuf,
+                        size_t		tgtid_mtty,
+                        size_t		tgtid_brom,
+                        size_t		tgtid_bdev,
+                        size_t		tgtid_mdma,
+                        size_t		memc_ways,				// number of ways for MEMC
+                        size_t		memc_sets,				// number of sets for MEMC
+                        size_t		l1_i_ways,				// number of ways for L1 ICACHE
+                        size_t		l1_i_sets,				// number of sets for L1 ICACHE
+                        size_t		l1_d_ways,				// number of ways for L1 DCACHE
+                        size_t		l1_d_sets,				// number of sets for L1 DCACHE
+                        size_t		xram_latency,				// external ram latency
+			bool		io,					// I/O cluster if true
+                        size_t          xfb,					// frame buffer pixels
+                        size_t          yfb,					// frame buffer lines
+			size_t          fb_mode,                                // frame buffer subsampling mode
+                        char*           disk_name,				// virtual disk name for BDEV
+                        size_t          block_size,				// block size for BDEV
+                        const Loader    &loader);				// loader for BROM
+
+	~TsarV4ClusterXbar();
+};
+}}
+
+#endif
Index: branches/v4/platforms/almos-tsarv3-platforms/multi-clusters/tsarv4_cluster_xbar/caba/source/src/tsarv4_cluster_xbar.cpp
===================================================================
--- branches/v4/platforms/almos-tsarv3-platforms/multi-clusters/tsarv4_cluster_xbar/caba/source/src/tsarv4_cluster_xbar.cpp	(revision 371)
+++ branches/v4/platforms/almos-tsarv3-platforms/multi-clusters/tsarv4_cluster_xbar/caba/source/src/tsarv4_cluster_xbar.cpp	(revision 371)
@@ -0,0 +1,590 @@
+#include "../include/tsarv4_cluster_xbar.h"
+
+namespace soclib {
+namespace caba  {
+
+//////////////////////////////////////////////////////////////////////////
+//                 Constructor
+//////////////////////////////////////////////////////////////////////////
+template<typename vci_param, typename iss_t, int cmd_width, int rsp_width>
+TsarV4ClusterXbar<vci_param, iss_t, cmd_width, rsp_width>::TsarV4ClusterXbar(
+                        sc_module_name  insname,
+                        size_t          nprocs,
+                        size_t          x_id,
+                        size_t          y_id,
+                        size_t          cluster_id,
+                        const   	soclib::common::MappingTable &mtd,
+                        const   	soclib::common::MappingTable &mtc, 
+                        const   	soclib::common::MappingTable &mtx, 
+                        size_t          x_width,
+                        size_t          y_width,
+                        size_t		tgtid_memc,
+                        size_t		tgtid_xicu,
+                        size_t		tgtid_fbuf,
+                        size_t		tgtid_mtty,
+                        size_t		tgtid_brom,
+                        size_t		tgtid_bdev,
+                        size_t		tgtid_mdma,
+                        size_t		memc_ways,
+                        size_t		memc_sets,
+                        size_t		l1_i_ways,
+                        size_t		l1_i_sets,
+                        size_t		l1_d_ways,
+                        size_t		l1_d_sets,
+                        size_t		xram_latency,
+                        bool            io,
+                        size_t		xfb,
+                        size_t		yfb,
+                        size_t          fb_mode,
+                        char*		disk_name,
+                        size_t		block_size,
+                        const Loader	&loader)
+      : soclib::caba::BaseModule(insname),
+        p_clk("clk"),
+        p_resetn("resetn"),
+
+        signal_dspin_cmd_l2g_d("signal_dspin_cmd_l2g_d"),
+        signal_dspin_cmd_g2l_d("signal_dspin_cmd_g2l_d"),
+        signal_dspin_cmd_l2g_c("signal_dspin_cmd_l2g_c"),
+        signal_dspin_cmd_g2l_c("signal_dspin_cmd_g2l_c"),
+        signal_dspin_rsp_l2g_d("signal_dspin_rsp_l2g_d"),
+        signal_dspin_rsp_g2l_d("signal_dspin_rsp_g2l_d"),
+        signal_dspin_rsp_l2g_c("signal_dspin_rsp_l2g_c"),
+        signal_dspin_rsp_g2l_c("signal_dspin_rsp_g2l_c"),
+
+	signal_vci_ini_d_bdev("signal_vci_ini_d_bdev"),
+	signal_vci_ini_d_cdma("signal_vci_ini_d_cdma"),
+
+        signal_vci_tgt_d_memc("signal_vci_tgt_d_memc"),
+        signal_vci_tgt_d_mtty("signal_vci_tgt_d_mtty"),
+        signal_vci_tgt_d_xicu("signal_vci_tgt_d_xicu"),
+        signal_vci_tgt_d_bdev("signal_vci_tgt_d_bdev"),
+        signal_vci_tgt_d_cdma("signal_vci_tgt_d_cdma"),
+        signal_vci_tgt_d_brom("signal_vci_tgt_d_brom"),
+        signal_vci_tgt_d_fbuf("signal_vci_tgt_d_fbuf"),
+
+        signal_vci_ini_c_memc("signal_vci_ini_c_memc"), 
+        signal_vci_tgt_c_memc("signal_vci_tgt_c_memc"),
+
+        signal_vci_xram("signal_vci_xram")
+
+{
+        // Vectors of ports definition
+
+        p_cmd_in        = alloc_elems<DspinInput<cmd_width> >("p_cmd_in", 2, 4);
+        p_cmd_out       = alloc_elems<DspinOutput<cmd_width> >("p_cmd_out", 2, 4);
+        p_rsp_in        = alloc_elems<DspinInput<rsp_width> >("p_rsp_in", 2, 4);
+        p_rsp_out       = alloc_elems<DspinOutput<rsp_width> >("p_rsp_out", 2, 4);
+	
+        // Components definition 
+
+        // on direct network : local srcid[proc] in [0...nprocs-1]
+        // on direct network : local srcid[mdma] = nprocs
+        // on direct network : local srcid[bdev] = nprocs + 1
+
+        // on coherence network : local srcid[proc] in [0...nprocs-1]
+	// on coherence network : local srcid[memc] = nprocs
+
+std::cout << "  - building proc_" << x_id << "_" << y_id << "-*" << std::endl;
+
+        for ( size_t p=0 ; p<nprocs ; p++ )
+        { 
+	  std::ostringstream sproc;
+	  sproc << "proc_" << x_id << "_" << y_id << "_" << p;
+
+#if USE_MEMCACHE_V4
+            proc[p] = new VciCcXCacheWrapperV4<vci_param, iss_t>(
+                sproc.str().c_str(),
+                cluster_id*nprocs + p,
+                mtd,				// Mapping Table Direct
+                mtc,				// Mapping Table Coherence
+                IntTab(cluster_id,p),    	// SRCID_D
+                IntTab(cluster_id,p),    	// SRCID_C
+                IntTab(cluster_id,p),    	// TGTID_C
+                1,				// single core
+                1,				// single dcache
+                l1_i_ways,l1_i_sets,16,  	// ICACHE size
+                l1_d_ways,l1_d_sets,16,      	// DCACHE size
+                4,				// WBUF width
+                8 				// WBUF depth
+                );
+#endif	// USE_MEMCACHE_V4
+
+#if USE_MEMCACHE_V3
+	    proc[p] = new VciCcVCacheWrapper2V1<vci_param, iss_t>(
+								  sproc.str().c_str(),
+								  cluster_id*nprocs + p,
+								  mtd, mtc,
+								  IntTab(cluster_id,p),     // SRCID_D
+								  IntTab(cluster_id,p),     // SRCID_C
+								  IntTab(cluster_id,p),     // TGTID_C
+								  TLB_IWAYS,TLB_ISETS,TLB_DWAYS,TLB_DSETS,
+								  l1_i_ways,l1_i_sets,16,
+								  l1_d_ways,l1_d_sets,16,
+								  16);      // TLB, Icache and Dcache sizes
+#endif	// USE_MEMCACHE_V3
+
+#if USE_PROFILER_ON_CPUs
+	    std::ostringstream sp;
+	    sp << "profiler_" << x_id << "_" << y_id << "-" << p;
+	    
+	    profiler[p] = new VciProfiler <vci_param, iss_t> (sp.str().c_str(), 
+							      cluster_id,
+							      x_id,
+							      y_id,
+							      x_width,
+							      y_width, 
+							      CONFIG_ADDRESS_WIDTH);
+	    profiler[p]->p_clk                  (this->p_clk);
+	    profiler[p]->p_resetn               (this->p_resetn);
+	    profiler[p]->p_vci                  (signal_vci_ini_d_proc[p]);
+	    profiler[p]->set_L1_cache(proc[p]);
+#endif	// USE_PROFILER_ON_CPUs
+
+#if USE_LOGGER_ON_CPUs
+	    std::ostringstream sp2;
+	    sp2 << "logger_" << x_id << "_" << y_id << "-" << p;
+	    vci_logger[p] = new VciLogger <vci_param> (sp2.str().c_str(), mtd);
+	    vci_logger[p]->p_clk    (this->p_clk);
+	    vci_logger[p]->p_resetn (this->p_resetn);
+	    vci_logger[p]->p_vci (signal_vci_ini_d_proc[p]);
+#endif	// USE_LOGGER_ON_CPUs
+
+        } // for on CPUs number
+
+std::cout << "  - building memc_" << x_id << "_" << y_id << std::endl;
+
+        std::ostringstream smemc;
+        smemc << "memc_" << x_id << "_" << y_id;
+
+#if USE_MEMCACHE_V4
+        memc = new VciMemCacheV4<vci_param>(
+                   smemc.str().c_str(),
+                   mtd, mtc, mtx,
+                   IntTab(cluster_id),           	// SRCID_X
+                   IntTab(cluster_id, nprocs),   	// SRCID_C
+                   IntTab(cluster_id, tgtid_memc),	// TGTID_D
+                   IntTab(cluster_id, nprocs),   	// TGTID_C
+                   memc_ways, memc_sets, 16,	 	// CACHE SIZE
+                   4096,     			 	// HEAP SIZE
+                   8,					// TRANSACTION TABLE DEPTH
+                   8);					// UPDATE TABLE DEPTH
+#endif
+
+#if USE_MEMCACHE_V3
+	memc = new VciMemCacheV3<vci_param>(
+					    smemc.str().c_str(),
+					    mtd, mtc, mtx,
+					    IntTab(cluster_id),                   	// SRCID_X
+					    IntTab(cluster_id, nprocs),           	// SRCID_C
+					    IntTab(cluster_id, tgtid_memc),        	// TGTID_D
+					    IntTab(cluster_id, nprocs),           	// TGTID_C
+					    memc_ways, memc_sets, 16,
+					    4096); 
+#endif	// USE_MEMCACHE_V3
+
+        
+std::cout << "  - building xram_" << x_id << "_" << y_id << std::endl;
+
+        std::ostringstream sxram;
+        sxram << "xram_" << x_id << "_" << y_id;
+        xram = new VciSimpleRam<vci_param>(
+                   sxram.str().c_str(),
+                   IntTab(cluster_id),
+                   mtx,
+                   loader,
+                   xram_latency);
+
+std::cout << "  - building xicu_" << x_id << "_" << y_id << std::endl;
+
+        //size_t  nhwi = 8;				// always 8 (or 9) ports, even if 
+        //if( io == true ) nhwi = 9;			// there if less than 4 processors
+
+
+         size_t   nhwi = 0;
+	 if(io == true) nhwi = 6;
+
+        std::ostringstream sicu;
+        sicu << "xicu_" << x_id << "_" << y_id;
+        xicu = new VciXicu<vci_param>(
+                  sicu.str().c_str(),
+                  mtd,				  	// mapping table
+                  IntTab(cluster_id, tgtid_xicu),  	// TGTID_D
+                  nprocs,				// number of timer IRQs
+                  nhwi,                          	// number of hard IRQs
+                  nprocs,				// number of soft IRQs
+                  nprocs);				// number of output IRQs
+
+std::cout << "  - building xbard_" << x_id << "_" << y_id << std::endl;
+
+        // direct local crossbar
+        size_t nb_direct_initiators      = nprocs;
+        size_t nb_direct_targets         = 2;
+
+        if( io == true )
+        {
+            nb_direct_initiators         = nprocs + 2;
+            nb_direct_targets            = 7;
+	}
+
+        std::ostringstream sd;
+        sd << "xbard_" << x_id << "_" << y_id;
+
+#if USE_LOCAL_RING
+	xbard = new VciLocalRingFast<vci_param,cmd_width,rsp_width>(
+		    sd.str().c_str(),
+		    mtd,
+		    IntTab(cluster_id),              // cluster index
+		    4,                               // wrapper fifo depth
+		    18,                              // gateway fifo depth
+		    nb_direct_initiators ,           // number of initiators
+		    nb_direct_targets);              // number of targets			
+#else
+        xbard = new VciLocalCrossbar<vci_param>(
+                    sd.str().c_str(),
+                    mtd,
+                    IntTab(cluster_id),              	// cluster initiator index
+                    IntTab(cluster_id),              	// cluster target index
+                    nb_direct_initiators,           	// number of initiators
+                    nb_direct_targets);             	// number of targets      
+#endif // USE_LOCAL_RING
+
+        
+std::cout << "  - building xbarc_" << x_id << "_" << y_id << std::endl;
+
+        // coherence local crossbar
+        std::ostringstream sc;
+        sc << "xbarc_" << x_id << "_" << y_id;
+
+#if USE_LOCAL_RING
+        xbarc = new VciLocalRingFast<vci_param,cmd_width,rsp_width>(
+		     sc.str().c_str(),
+		     mtc,
+		     IntTab(cluster_id),                   	// cluster index
+		     4,                                      	// wrapper fifo depth
+		     18,                                     	// gateway fifo depth
+		     nprocs + 1,                               	// number of initiators
+		     nprocs + 1);                              	// number of targets
+	
+#else
+        xbarc = new VciLocalCrossbar<vci_param>(
+                    sc.str().c_str(),
+                    mtc,
+                    IntTab(cluster_id),                	// cluster initiator index
+                    IntTab(cluster_id),                	// cluster target index
+                    nprocs + 1,                		// number of initiators
+                    nprocs + 1);               		// number of targets
+#endif  // USE_LOCAL_RING 
+
+#if !(USE_LOCAL_RING)
+std::cout << "  - building wrappers in cluster_" << x_id << "_" << y_id << std::endl;
+
+        // direct initiator wrapper
+        std::ostringstream wid;
+        wid << "iniwrapperd_" << x_id << "_" << y_id;
+        iniwrapperd = new VciVdspinInitiatorWrapper<vci_param,cmd_width,rsp_width>(
+                          wid.str().c_str(),
+                          4,				// cmd fifo depth
+                          4);				// rsp fifo depth
+
+        // direct target wrapper
+        std::ostringstream wtd;
+        wtd << "tgtwrapperd_" << x_id << "_" << y_id;
+        tgtwrapperd = new VciVdspinTargetWrapper<vci_param,cmd_width,rsp_width>(
+                          wtd.str().c_str(),
+                          4,				// cmd fifo depth
+                          4);				// rsp fifo depth
+
+        // coherence initiator wrapper
+        std::ostringstream wic;
+        wic << "iniwrapperc_" << x_id << "_" << y_id;
+        iniwrapperc = new VciVdspinInitiatorWrapper<vci_param,cmd_width,rsp_width>(
+                          wic.str().c_str(),
+                          4,				// cmd fifo depth
+                          4);				// rsp fifo depth
+
+        // coherence target wrapper
+        std::ostringstream wtc;
+        wtc << "tgtwrapperc_" << x_id << "_" << y_id;
+        tgtwrapperc = new VciVdspinTargetWrapper<vci_param,cmd_width,rsp_width>(
+                          wtc.str().c_str(),
+                          4,				// cmd fifo depth
+                          4);				// rsp fifo depth
+#endif	// !(USE_LOCAL_RING)
+
+std::cout << "  - building cmdrouter_" << x_id << "_" << y_id << std::endl;
+
+        // CMD router
+        std::ostringstream scmd;
+        scmd << "cmdrouter_" << x_id << "_" << y_id;
+        cmdrouter = new VirtualDspinRouter<cmd_width>(
+                        scmd.str().c_str(),
+                        x_id,y_id,                    // coordinate in the mesh
+                        x_width, y_width,             // x & y fields width
+                        4,4);                         // input & output fifo depths
+        
+std::cout << "  - building rsprouter_" << x_id << "_" << y_id << std::endl;
+
+        // RSP router
+        std::ostringstream srsp;
+        srsp << "rsprouter_" << x_id << "_" << y_id;
+        rsprouter = new VirtualDspinRouter<rsp_width>(
+                        srsp.str().c_str(),
+                        x_id,y_id,                    // coordinates in mesh
+                        x_width, y_width,             // x & y fields width
+                        4,4);                         // input & output fifo depths
+        
+        // IO cluster components
+        if ( io == true )
+	{
+            brom = new VciSimpleRam<vci_param>(
+                       "brom",
+                       IntTab(cluster_id, tgtid_brom),
+                       mtd,
+                       loader);
+
+#if USE_FRAME_BUFFER
+            fbuf = new VciFrameBuffer<vci_param>(
+                       "fbuf",
+                       IntTab(cluster_id, tgtid_fbuf),
+                       mtd,
+		       xfb, 
+		       yfb,
+		       fb_mode); 
+#else
+	    std::ostringstream sf;
+	    sd << "fb_logger__" << x_id << "_" << y_id;
+	    fbuf = new VciLogger <vci_param> (sd.str().c_str(), mtd);
+#endif
+
+	    cdma = new VciDmaTsarV2<vci_param>(
+		      "cdma", 
+		      mtd, 
+		      IntTab(cluster_id, nprocs),
+		      IntTab(cluster_id, tgtid_mdma),
+		      64);
+
+#if USE_LOGGER_ON_DMA
+	    std::ostringstream sd;
+	    sd << "dma_logger_" << x_id << "_" << y_id;
+	    vci_dma_logger = new VciLogger <vci_param> (sd.str().c_str(), mtd);
+	    vci_dma_logger->p_clk    (this->p_clk);
+	    vci_dma_logger->p_resetn (this->p_resetn);
+	    vci_dma_logger->p_vci (signal_vci_ini_d_cdma);
+#endif	// USE_LOGGER_ON_DMA
+
+	    bdev = new VciBlockDeviceTsarV2<vci_param>(
+                       "bdev",
+                       mtd,
+                       IntTab(cluster_id, nprocs+1),
+                       IntTab(cluster_id, tgtid_bdev),
+                       disk_name,
+                       block_size);
+
+	    // tty
+	    signal_irq_mtty = alloc_elems<sc_signal<bool> >("signal_irq_mtty", 4);
+
+	    std::ostringstream stty;
+	    stty << "tty_" << x_id << "_" << y_id;
+	    mtty = new VciMultiTty<vci_param>(
+					      stty.str().c_str(),
+					      IntTab(cluster_id, tgtid_mtty),
+					      mtd, "tty0", "tty1", "tty2", "tty3", NULL);
+	}
+
+std::cout << "  - all components constructed" << std::endl;
+
+        ////////////////////////////////////
+        // Connections are defined here
+        ////////////////////////////////////
+
+        // CMDROUTER and RSPROUTER
+        cmdrouter->p_clk                	(this->p_clk);
+        cmdrouter->p_resetn             	(this->p_resetn);
+        rsprouter->p_clk                	(this->p_clk);
+        rsprouter->p_resetn             	(this->p_resetn);
+        for(int x = 0; x < 2; x++)
+        {
+          for(int y = 0; y < 4; y++)
+          {
+            cmdrouter->p_out[x][y]              (this->p_cmd_out[x][y]);
+            cmdrouter->p_in[x][y]               (this->p_cmd_in[x][y]);
+            rsprouter->p_out[x][y]              (this->p_rsp_out[x][y]);
+            rsprouter->p_in[x][y]               (this->p_rsp_in[x][y]);
+          }
+        }
+        
+        cmdrouter->p_out[0][4]  		(signal_dspin_cmd_g2l_d);
+        cmdrouter->p_out[1][4]  		(signal_dspin_cmd_g2l_c);
+        cmdrouter->p_in[0][4]   		(signal_dspin_cmd_l2g_d);
+        cmdrouter->p_in[1][4]   		(signal_dspin_cmd_l2g_c);
+
+        rsprouter->p_out[0][4]  		(signal_dspin_rsp_g2l_d);
+        rsprouter->p_out[1][4]  		(signal_dspin_rsp_g2l_c);
+        rsprouter->p_in[0][4]   		(signal_dspin_rsp_l2g_d);
+        rsprouter->p_in[1][4]   		(signal_dspin_rsp_l2g_c);
+
+#if !(USE_LOCAL_RING)
+        // VCI/DSPIN WRAPPERS
+        iniwrapperd->p_clk			(this->p_clk);
+        iniwrapperd->p_resetn			(this->p_resetn);
+	iniwrapperd->p_vci			(signal_vci_l2g_d);
+	iniwrapperd->p_dspin_out		(signal_dspin_cmd_l2g_d);
+	iniwrapperd->p_dspin_in			(signal_dspin_rsp_g2l_d);
+
+        tgtwrapperd->p_clk			(this->p_clk);
+        tgtwrapperd->p_resetn			(this->p_resetn);
+	tgtwrapperd->p_vci			(signal_vci_g2l_d);
+	tgtwrapperd->p_dspin_out		(signal_dspin_rsp_l2g_d);
+	tgtwrapperd->p_dspin_in			(signal_dspin_cmd_g2l_d);
+
+        iniwrapperc->p_clk			(this->p_clk);
+        iniwrapperc->p_resetn			(this->p_resetn);
+	iniwrapperc->p_vci			(signal_vci_l2g_c);
+	iniwrapperc->p_dspin_out		(signal_dspin_cmd_l2g_c);
+	iniwrapperc->p_dspin_in			(signal_dspin_rsp_g2l_c);
+
+        tgtwrapperc->p_clk			(this->p_clk);
+        tgtwrapperc->p_resetn			(this->p_resetn);
+	tgtwrapperc->p_vci			(signal_vci_g2l_c);
+	tgtwrapperc->p_dspin_out		(signal_dspin_rsp_l2g_c);
+	tgtwrapperc->p_dspin_in			(signal_dspin_cmd_g2l_c);
+#endif
+
+        // CROSSBAR direct
+        xbard->p_clk                  		(this->p_clk);
+        xbard->p_resetn                 	(this->p_resetn);
+
+#if USE_LOCAL_RING
+	xbard->p_gate_cmd_out                   (signal_dspin_cmd_l2g_d);
+        xbard->p_gate_cmd_in                    (signal_dspin_cmd_g2l_d);
+        xbard->p_gate_rsp_out                   (signal_dspin_rsp_l2g_d);
+        xbard->p_gate_rsp_in                    (signal_dspin_rsp_g2l_d);
+#else
+        xbard->p_initiator_to_up        	(signal_vci_l2g_d);
+        xbard->p_target_to_up           	(signal_vci_g2l_d);
+#endif     
+        xbard->p_to_target[tgtid_memc]  	(signal_vci_tgt_d_memc);
+        xbard->p_to_target[tgtid_xicu]  	(signal_vci_tgt_d_xicu);          
+        
+        for ( size_t p=0 ; p<nprocs ; p++)
+            xbard->p_to_initiator[p]		(signal_vci_ini_d_proc[p]);
+
+	if ( io == true )
+	{
+            xbard->p_to_target[tgtid_brom]  	(signal_vci_tgt_d_brom);
+            xbard->p_to_target[tgtid_bdev]  	(signal_vci_tgt_d_bdev);
+            xbard->p_to_target[tgtid_fbuf]  	(signal_vci_tgt_d_fbuf);
+	    xbard->p_to_target[tgtid_mtty]  	(signal_vci_tgt_d_mtty);
+	    xbard->p_to_target[tgtid_mdma]  	(signal_vci_tgt_d_cdma);
+
+	    xbard->p_to_initiator[nprocs]  	(signal_vci_ini_d_cdma);
+            xbard->p_to_initiator[nprocs+1]  	(signal_vci_ini_d_bdev);
+	}
+        
+        // CROSSBAR coherence
+        xbarc->p_clk                    	(this->p_clk);
+        xbarc->p_resetn                 	(this->p_resetn);
+
+#if USE_LOCAL_RING
+	xbarc->p_gate_cmd_out                   (signal_dspin_cmd_l2g_c);
+        xbarc->p_gate_cmd_in                    (signal_dspin_cmd_g2l_c);
+        xbarc->p_gate_rsp_out                   (signal_dspin_rsp_l2g_c);
+        xbarc->p_gate_rsp_in                    (signal_dspin_rsp_g2l_c);
+#else
+        xbarc->p_initiator_to_up        	(signal_vci_l2g_c);
+        xbarc->p_target_to_up           	(signal_vci_g2l_c);
+#endif
+        xbarc->p_to_initiator[nprocs]  		(signal_vci_ini_c_memc);
+        xbarc->p_to_target[nprocs]     		(signal_vci_tgt_c_memc);
+
+        for ( size_t p=0 ; p<nprocs ; p++)
+        {
+            xbarc->p_to_target[p]       	(signal_vci_tgt_c_proc[p]);
+            xbarc->p_to_initiator[p]    	(signal_vci_ini_c_proc[p]);
+        }
+
+        // Processors
+        for ( size_t p=0 ; p<nprocs ; p++)
+        {
+            proc[p]->p_clk              	(this->p_clk);
+            proc[p]->p_resetn           	(this->p_resetn);
+            proc[p]->p_vci_ini_rw       	(signal_vci_ini_d_proc[p]);
+            proc[p]->p_vci_ini_c        	(signal_vci_ini_c_proc[p]);
+            proc[p]->p_vci_tgt          	(signal_vci_tgt_c_proc[p]);
+            proc[p]->p_irq[0]           	(signal_proc_it[p]);
+
+            for ( size_t j = 1 ; j < 6 ; j++ )
+                proc[p]->p_irq[j]       	(signal_false);
+        }
+        
+        // XICU
+        xicu->p_clk                     	(this->p_clk);
+        xicu->p_resetn                  	(this->p_resetn);
+        xicu->p_vci                     	(signal_vci_tgt_d_xicu);
+
+        for ( size_t p=0 ; p<nprocs ; p++)
+	  xicu->p_irq[p]              	(signal_proc_it[p]);
+	
+        // MEMC
+        memc->p_clk                     	(this->p_clk);
+        memc->p_resetn                  	(this->p_resetn);
+        memc->p_vci_ixr                 	(signal_vci_xram);
+        memc->p_vci_tgt                 	(signal_vci_tgt_d_memc);
+        memc->p_vci_ini                 	(signal_vci_ini_c_memc);
+        memc->p_vci_tgt_cleanup         	(signal_vci_tgt_c_memc);
+
+        // XRAM
+        xram->p_clk                     	(this->p_clk);
+        xram->p_resetn                  	(this->p_resetn);
+        xram->p_vci                 		(signal_vci_xram);
+
+	// Components in IO cluster
+	if ( io == true )
+	{
+        	// BDEV            
+		bdev->p_clk                      (this->p_clk);
+        	bdev->p_resetn                   (this->p_resetn);
+        	bdev->p_irq                      (signal_irq_bdev);
+        	bdev->p_vci_target               (signal_vci_tgt_d_bdev);
+        	bdev->p_vci_initiator            (signal_vci_ini_d_bdev);
+
+        	// FBUF
+        	fbuf->p_clk                       (this->p_clk);
+        	fbuf->p_resetn                    (this->p_resetn);
+        	fbuf->p_vci                       (signal_vci_tgt_d_fbuf);
+
+        	// BROM
+        	brom->p_clk                       (this->p_clk);
+        	brom->p_resetn                    (this->p_resetn);
+        	brom->p_vci                       (signal_vci_tgt_d_brom);
+		
+		// MTTY
+		mtty->p_clk                       (this->p_clk);
+		mtty->p_resetn                    (this->p_resetn);
+		mtty->p_vci                       (signal_vci_tgt_d_mtty);
+		for(size_t i=0 ; i<4 ; i++)
+		  mtty->p_irq[i]                   (signal_irq_mtty[i]);
+
+		// CDMA
+		cdma->p_clk                       (this->p_clk);
+		cdma->p_resetn                    (this->p_resetn);
+		cdma->p_irq                       (signal_irq_cdma);
+		cdma->p_vci_target                (signal_vci_tgt_d_cdma);
+		cdma->p_vci_initiator             (signal_vci_ini_d_cdma);
+
+		xicu->p_hwi[0]             (signal_irq_bdev);
+		xicu->p_hwi[1]             (signal_irq_cdma);
+		
+		for(size_t i=0 ; i<4 ; i++)
+		  xicu->p_hwi[2+i]        (signal_irq_mtty[i]);
+        }
+} // end constructor
+
+///////////////////////////////////////////////////////////////////////////
+//    destructor
+///////////////////////////////////////////////////////////////////////////
+template<typename vci_param, typename iss_t, int cmd_width, int rsp_width>
+TsarV4ClusterXbar<vci_param, iss_t, cmd_width, rsp_width>::~TsarV4ClusterXbar() {}
+
+}}
Index: branches/v4/platforms/caba-new_vdspin-test/Makefile
===================================================================
--- branches/v4/platforms/caba-new_vdspin-test/Makefile	(revision 371)
+++ branches/v4/platforms/caba-new_vdspin-test/Makefile	(revision 371)
@@ -0,0 +1,6 @@
+ARCH=mips32el
+SIMULATION_ARGS=100000
+SOCLIB_CC_ADD_ARGS=-t systemcass
+SOCLIB?=$(shell soclib-cc --getpath)
+export SOCLIB
+include $(SOCLIB)/soclib/platform/topcells/all.mk
Index: branches/v4/platforms/caba-new_vdspin-test/platform_desc
===================================================================
--- branches/v4/platforms/caba-new_vdspin-test/platform_desc	(revision 371)
+++ branches/v4/platforms/caba-new_vdspin-test/platform_desc	(revision 371)
@@ -0,0 +1,38 @@
+
+# -*- python -*-
+
+
+
+# -*- python -*-
+
+
+todo = Platform('caba', 'top.cpp',
+				uses = [
+	Uses('caba:vci_cc_xcache_wrapper_v1', iss_t = 'common:iss2_simhelper', simhelper_iss_t = 'common:mips32el'),
+	Uses('caba:vci_simple_ram'),
+	Uses('caba:vci_multi_tty'),
+	Uses('caba:vci_mem_cache_v3'),
+        Uses('caba:vci_local_ring_fast',
+        ring_cmd_data_size = 40,
+        ring_rsp_data_size = 33,
+),
+        Uses('caba:vci_simple_ring_fast',
+        ring_cmd_data_size = 40,
+        ring_rsp_data_size = 33,
+),
+	Uses('caba:virtual_dspin_router', flit_width = 40),
+	Uses('caba:virtual_dspin_router', flit_width = 33),
+	Uses('common:elf_file_loader'),
+	],
+	cell_size = 4,
+	plen_size = 8,
+	addr_size = 32,
+	rerror_size = 2,
+	clen_size = 1,
+	rflag_size = 1,
+	srcid_size = 8,
+	pktid_size = 4,
+	trdid_size = 4,
+	wrplen_size = 1
+)
+
Index: branches/v4/platforms/caba-new_vdspin-test/segmentation.h
===================================================================
--- branches/v4/platforms/caba-new_vdspin-test/segmentation.h	(revision 371)
+++ branches/v4/platforms/caba-new_vdspin-test/segmentation.h	(revision 371)
@@ -0,0 +1,117 @@
+
+/////////////////////////////////////////////////////////////////
+//	ADDRESS SPACE SEGMENTATION
+//
+//	This file must be included in the system.cpp file, 
+//	for harware configuration : It is used to build
+//	the SOCLIB_SEGMENT_TABLE.
+//
+//	This file can also be used by the ldscript generator,
+//	for embedded software generation.
+//	
+//	It gives the system integrator the guaranty
+//	that hardware and software have the same
+//	description of the address space segmentation.
+/////////////////////////////////////////////////////////////////
+
+/////////////////////////////////////////////////////////////////
+//	reset, and exception segments
+//      base address required by MIPS processor
+/////////////////////////////////////////////////////////////////
+#define MMU
+
+#define	RESET_BASE	0xBFC00000
+#define	RESET_SIZE	0x00001000      // 4 k
+
+#define	EXCEP_BASE	0x80000080
+#define	EXCEP_SIZE	0x00001000      // 4 k
+
+#define	TEXT_BASE	0x00400000
+#define	TEXT_SIZE       0x00050000	// 20 k 
+///////////////////////////////////////////////////////////////////////////////////
+//	global data segment (initialised)
+///////////////////////////////////////////////////////////////////////////////////
+
+#define DATA0_BASE	0x10000000
+#define DATA0_SIZE	0x00100000     // 256 k
+
+#define DATA1_BASE	0x50000000
+#define DATA1_SIZE	0x00100000
+
+#define DATA2_BASE	0x90000000
+#define DATA2_SIZE	0x00100000
+
+#define DATA3_BASE	0xE0000000
+#define DATA3_SIZE	0x00100000
+
+/////////////////////////////////////////////////////////////////
+//	page table (initialised)
+/////////////////////////////////////////////////////////////////
+#define PTD_ADDR	0x40400000
+#define PTE_ADDR	0x40402000
+#define IPTE_ADDR	0x40403000
+#define	TAB_SIZE	0x00010000      // 64 k
+
+#define V_TTY_BASE 	0x00800000
+#define	V_TIMER_BASE	0x00C00000	// timer virtual address
+//////////////////////////////////////////////////////////
+//	System devices
+///////////////////////////////////////////////////////////
+
+#define	TTY_BASE	0xC0200000  
+#define	TTY_SIZE	0x00000100  // 256
+
+#define	TIMER_BASE	0xD0200000
+#define	TIMER_SIZE	0x00000100
+
+#define	LOCKS_BASE	0xE0200000
+#define	LOCKS_SIZE	0x00000100
+
+#define PROC0_BASE      0x01400000
+#define PROC0_SIZE      0x0000000A
+
+#define PROC1_BASE      0x02400000
+#define PROC1_SIZE      0x0000000A
+
+#define PROC2_BASE      0x03400000
+#define PROC2_SIZE      0x0000000A
+
+#define PROC3_BASE      0x04400000
+#define PROC3_SIZE      0x0000000A
+
+#define PROC4_BASE      0x43400000
+#define PROC4_SIZE      0x0000000A
+
+#define PROC5_BASE      0x44400000
+#define PROC5_SIZE      0x0000000A
+
+#define PROC6_BASE      0x45400000
+#define PROC6_SIZE      0x0000000A
+
+#define PROC7_BASE      0x46400000
+#define PROC7_SIZE      0x0000000A
+
+#define PROC8_BASE      0xA3400000
+#define PROC8_SIZE      0x0000000A
+
+#define PROC9_BASE      0xA4400000
+#define PROC9_SIZE      0x0000000A
+
+#define PROC10_BASE     0xA5400000
+#define PROC10_SIZE     0x0000000A
+
+#define PROC11_BASE     0xA6400000
+#define PROC11_SIZE     0x0000000A
+
+#define PROC12_BASE     0xE2400000
+#define PROC12_SIZE     0x0000000A
+
+#define PROC13_BASE     0xE3400000
+#define PROC13_SIZE     0x0000000A
+
+#define PROC14_BASE     0xE4400000
+#define PROC14_SIZE     0x0000000A
+
+#define PROC15_BASE     0xE5400000
+#define PROC15_SIZE     0x0000000A
+
Index: branches/v4/platforms/caba-new_vdspin-test/soft/Makefile
===================================================================
--- branches/v4/platforms/caba-new_vdspin-test/soft/Makefile	(revision 371)
+++ branches/v4/platforms/caba-new_vdspin-test/soft/Makefile	(revision 371)
@@ -0,0 +1,4 @@
+ADD_OBJS=stdlib.o stdio.o exception.o system.o
+SOCLIB?=$(shell soclib-cc --getpath)
+export SOCLIB
+include $(SOCLIB)/soclib/platform/topcells/soft.mk
Index: branches/v4/platforms/caba-new_vdspin-test/soft/ldscript
===================================================================
--- branches/v4/platforms/caba-new_vdspin-test/soft/ldscript	(revision 371)
+++ branches/v4/platforms/caba-new_vdspin-test/soft/ldscript	(revision 371)
@@ -0,0 +1,124 @@
+/*
+ *
+ * SOCLIB_GPL_HEADER_BEGIN
+ * 
+ * This file is part of SoCLib, GNU GPLv2.
+ * 
+ * SoCLib is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ * 
+ * SoCLib is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * General Public License for more details.
+ * 
+ * You should have received a copy of the GNU General Public License
+ * along with SoCLib; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301, USA.
+ * 
+ * SOCLIB_GPL_HEADER_END
+ *
+ * Copyright (c) UPMC, Lip6, SoC
+ *         Nicolas Pouillon <nipo@ssji.net>, 2006-2007
+ *
+ * Maintainers: nipo
+ */
+
+SECTIONS
+{
+	special_base = 0x00500000;
+	. = special_base;
+    .ppc_special : {
+		. = 0x100;
+		*(.ppc_special.critical_input)
+		. = 0x200;
+		*(.ppc_special.machine_check)
+		. = 0x300;
+		*(.ppc_special.data_storage)
+		. = 0x400;
+		*(.ppc_special.instruction_storage)
+		. = 0x500;
+		*(.ppc_special.external)
+		. = 0x600;
+		*(.ppc_special.alignment)
+		. = 0x700;
+		*(.ppc_special.program)
+		. = 0xc00;
+		*(.ppc_special.syscall)
+		. = 0x1000;
+		*(.ppc_special.programmable_interval_timer)
+		. = 0x1010;
+		*(.ppc_special.fixed_interval_timer)
+		. = 0x1020;
+		*(.ppc_special.watchdog)
+		. = 0x1100;
+		*(.ppc_special.data_tlb_miss)
+		. = 0x1200;
+		*(.ppc_special.instruction_tlb_miss)
+		. = 0x2000;
+		*(.ppc_special.debug)
+    }
+
+    . = 0xfffffffc;
+    .ppc_boot : {
+		*(.ppc_boot)
+		*(.ppc_boot.*)
+    }
+
+   . = 0x80000000;
+   .excep : {
+		*(.excep)
+		*(.excep.*)
+   }
+
+   . = 0xbfc00000;
+   .reset : {
+		*(.reset)
+		*(.reset.*)
+   }
+
+   . = 0x00400000;
+   .text : {
+      *(.text)
+   }
+   . = 0x10000000;
+   .rodata : {
+      *(.rodata)
+      . = ALIGN(4);
+   }
+   .data  : {
+      *(.data)
+   }
+   .sdata : {
+      *(.lit8)
+      *(.lit4)
+      *(.sdata)
+   }
+   _gp = .;
+   . = ALIGN(4);
+   _edata = .;
+   .sbss  : {
+      *(.sbss)
+      *(.scommon)
+   }
+   .bss   : {
+      *(.bss)
+      *(COMMON)
+   }
+   . = ALIGN(4);
+   _end = .;
+   _heap = .;
+   _stack = 0x10020000-16;
+
+   . = 0x50000000;
+   __SortArr1 = .;
+
+   . = 0x90000000;
+   __SortArr2 = .;
+   
+   . = 0xE0000000;
+   __SortArr3 = .;
+
+}
Index: branches/v4/platforms/caba-new_vdspin-test/soft/main.c
===================================================================
--- branches/v4/platforms/caba-new_vdspin-test/soft/main.c	(revision 371)
+++ branches/v4/platforms/caba-new_vdspin-test/soft/main.c	(revision 371)
@@ -0,0 +1,203 @@
+#include "system.h"
+#include "stdio.h"
+#include "stdlib.h"
+#include "matrice.h"
+
+#include "../segmentation.h"
+
+#define NPROCS 16
+#define SIZE 500 //1000
+#define SORT_TYPE 1
+
+extern unsigned int __SortArr1;
+extern unsigned int __SortArr2;
+extern unsigned int __SortArr3;
+
+volatile int compteur=NPROCS;
+volatile int nprocs=NPROCS;
+volatile int mmu=0;
+
+unsigned int SortArr0[4*(SIZE+200)];
+unsigned int *SortArr1 = &__SortArr1;
+unsigned int *SortArr2 = &__SortArr2;
+unsigned int *SortArr3 = &__SortArr3;
+
+void SORT(int *base, int n, int type);
+void insertion_sort(int *base, int n);
+void selection_sort(int *base, int n);
+void bubble_sort(int *base, int n);
+void quick_sort(int *base, int n);
+
+int main()
+{
+
+unsigned int *mappArray[4] = {SortArr0, SortArr1, SortArr2, SortArr3};
+
+register int p; 
+
+p=procnum();
+
+
+  puts("Hello from processor ");
+  puti(p);
+  putchar('\n');
+
+
+  int i;
+  int j;
+
+  if(p+1 <= nprocs){
+        i=1;
+        puts("Memory copy \n");
+        memcpy(&mappArray[p/4][(p % 4)*(SIZE+200)], gQSortNum0 + ( (4*(p+1)*i) % 32) ,SIZE);
+
+        puts("Sort... \n");
+        SORT(&mappArray[(p/4)][(p % 4)*(SIZE+200)], SIZE, SORT_TYPE);
+
+        for (j = 1; j < SIZE; j++)
+        {
+          if (mappArray[p/4][(p % 4)*(SIZE+200)+j] < mappArray[p/4][(p%4)*(SIZE+200) + j - 1])
+                {
+                        puts("ucbqsort: failed\n");
+                        while(1);
+                }
+
+        }
+        puts("ucbqsort: success\n");
+
+  }
+
+  while(1);
+}
+
+//---- insertion sort : non adapté pour tableaux de grande taille (> 100) --
+void insertion_sort(int *base, int n) 
+{
+    /* Spécifications externes : Tri du tableau base par insertion séquentielle */
+    int i,p,j;
+    int x;
+
+    puts("Insertion Sort\n");
+
+    for (i = 1; i < n; i++) 
+    {
+
+        putchar('-'); // added for debug
+
+        /* stockage de la valeur en i */
+        x = base[i]; 
+ 
+        /* recherche du plus petit indice p inférieur à i tel que base[p] >= base[i] */
+        for(p = 0; base[p] < x; p++);
+        /* p pointe une valeur de base supérieure à celle en i */ 
+ 
+        /* décalage avant des valeurs de base entre p et i */         
+        for (j = i-1; j >= p; j--) {
+            base[j+1] = base[j]; 
+        }   
+ 
+        base[p] = x; /* insertion de la valeur stockée à la place vacante */
+
+        putchar('+'); // added for debug
+
+    }
+}
+
+//------ simple_sort -------------------------------
+void selection_sort(int *base, int n)
+{
+     int i, min, j , x;
+     puts("Selection Sort\n");
+
+     for(i = 0 ; i < n - 1 ; i++)
+     {
+
+         putchar('-'); // added for debug
+
+         min = i;
+
+         
+         for(j = i+1 ; j < n ; j++)
+         {
+        
+            if(base[j] < base[min])
+                  min = j;
+            
+         }
+
+         if(min != i)
+         {
+             x = base[i];
+             base[i] = base[min];
+             base[min] = x;
+         }
+
+         putchar('+'); // added for debug
+
+     }
+}
+//-------------------------------
+void bubble_sort(int *base, int n)
+{
+        int i   = 0; /* Indice de répétition du tri */
+ 	int j   = 0; /* Variable de boucle */
+ 	int tmp = 0; /* Variable de stockage temporaire */
+        int en_desordre = 1; /* Booléen marquant l'arrêt du tri si le tableau est ordonné */
+
+        puts("Bubble Sort\n");
+
+	/* Boucle de répétition du tri et le test qui arrête le tri dès que le tableau est ordonné */
+	for(i = 0 ; (i < n) && en_desordre; i++)
+	{
+                putchar('-'); // added for debug
+
+		/* Supposons le tableau ordonné */
+		en_desordre = 0;
+		/* Vérification des éléments des places j et j-1 */
+		for(j = 1 ; j < n - i ; j++)
+		{
+			/* Si les 2 éléments sont mal triés */
+			if(base[j] < base[j-1])
+			{
+				/* Inversion des 2 éléments */
+ 				tmp = base[j-1];
+ 				base[j-1] = base[j];
+ 				base[j] = tmp;
+ 
+ 				/* Le tableau n'est toujours pas trié */
+				en_desordre = 1;
+ 			}
+		}
+
+                putchar('+'); // added for debug
+	}
+
+}
+//-------------------------------
+void quick_sort(int *base, int n)
+{}
+
+//-------------------------------------*/
+void SORT(int *base, int n, int type)
+{
+  switch(type)
+  {
+  case 0:
+    quick_sort(base, n);
+    break;
+  case 1:
+    selection_sort(base, n);
+    break;
+  case 2:
+    insertion_sort(base, n);
+    break;
+  case 3:
+    bubble_sort(base, n);
+    break;
+  default:
+    break;
+  }
+
+}
+
+
Index: branches/v4/platforms/caba-new_vdspin-test/soft/matrice.h
===================================================================
--- branches/v4/platforms/caba-new_vdspin-test/soft/matrice.h	(revision 371)
+++ branches/v4/platforms/caba-new_vdspin-test/soft/matrice.h	(revision 371)
@@ -0,0 +1,713 @@
+unsigned int gQSortNum0[16000] = {
+  251, 24, 113, 170, 215, 60, 83, 30, 115, 48, 169, 210, 49, 92, 101, 58, 21, 184, 225, 6,
+  199, 244, 227, 146, 99, 96, 25, 222, 65, 140, 213, 22, 219, 136, 175, 182, 73, 36, 141, 190, 
+  83, 112, 137, 114, 175, 188, 187, 102, 53, 168, 193, 154, 167, 172, 3, 242, 67, 64,144, 137,
+  142, 175, 188, 69, 102, 53, 168, 193, 102, 89, 172, 253, 242, 67,192, 7, 62, 159, 20, 181,
+  182, 187, 216, 207, 22, 105, 132, 109, 162, 205, 16, 151, 18, 113, 228, 37, 6, 85, 8, 161,
+  58, 135, 76, 35, 174, 35, 224, 39, 158, 127, 180, 149, 86, 155, 200, 239, 118, 119, 28, 77,
+  254, 19, 176, 183, 78, 145, 132, 5, 90, 117, 152, 127, 218, 153, 20, 67, 178, 3, 128, 185,
+  254, 95, 172, 139, 246, 123, 104, 15, 42, 169, 68, 211, 98, 243, 80, 41, 174, 79, 36, 27,
+  186, 149, 86, 155, 200, 239, 118, 119, 28, 77, 254, 19, 176, 183,78, 145, 132, 5, 90, 117,
+  152, 127, 218, 153, 20, 67, 178, 3, 128, 185, 254, 95, 172, 139, 246, 123, 104, 15, 42,169,
+  68, 211, 98, 243, 80, 41, 174, 79, 36, 27, 186, 107, 56, 97, 134, 71, 116, 157, 238, 227,
+  32, 153, 162, 193, 244, 171, 150, 165, 248, 209, 54, 55, 164, 13, 194, 45, 16, 247, 242, 47,
+  60, 59, 26, 75, 40, 65, 230, 217, 44, 131, 142, 195, 192, 121, 190, 225, 108, 203, 202, 197,
+  168, 177, 150, 233, 252, 19, 34, 77, 144, 23, 110, 15, 100, 91, 122, 213, 120, 223, 70, 7, 
+  52, 93, 46, 93, 160, 167, 226, 255, 204, 21, 42, 229, 72, 111, 246, 9, 100, 205, 126, 147,
+  215, 82, 79, 36, 229, 70, 149, 56, 159, 134, 185, 140, 99, 18, 29, 224, 153, 94, 63, 244, 85, 150, 91, 248, 209,
+  202, 55, 92, 243, 194, 211, 240, 247, 242, 209, 196, 197, 26, 75, 40, 191, 26, 39, 44, 131, 142, 195, 64, 121, 190,
+  231, 34, 65, 116, 43, 22, 219, 136, 175, 74, 73, 220, 141, 190, 83, 112, 137, 142, 81, 68, 69, 154, 203, 88, 63,
+  154, 89, 172, 3, 242, 67, 192, 249, 62, 159, 20, 181, 74, 69, 216, 49, 22, 105, 132, 109, 162, 205, 16, 151, 18,
+  37, 136, 175, 74, 183, 36, 115, 66, 173, 144, 137, 142, 175, 188, 69, 102, 53, 168, 193, 102, 89, 172, 253, 242, 67,
+  192, 7, 62, 159, 20, 181, 182, 187, 216, 207, 22, 105, 132, 109, 162, 205, 16, 151, 18, 113, 228, 37, 6, 85, 8,
+  161, 58, 135, 76, 35, 174, 35, 224, 39, 158, 127, 180, 149, 86, 155, 200, 239, 118, 119, 28, 77, 254, 19, 176, 183,
+  78, 145, 132, 5, 90, 117, 152, 127, 218, 153, 20, 67, 178, 3, 128, 185, 254, 95, 172, 139, 246, 123, 104, 15, 42,
+  251, 24, 113, 170, 215, 60, 83, 30, 115, 48, 169, 210, 49, 92, 101, 58, 21, 184, 225, 6,
+  199, 244, 227, 146, 99, 96, 25, 222, 65, 140, 213, 22, 219, 136, 175, 182, 73, 36, 141, 190, 
+  83, 112, 137, 114, 175, 188, 187, 102, 53, 168, 193, 154, 167, 172, 3, 242, 67, 64,144, 137,
+  142, 175, 188, 69, 102, 53, 168, 193, 102, 89, 172, 253, 242, 67,192, 7, 62, 159, 20, 181,
+  182, 187, 216, 207, 22, 105, 132, 109, 162, 205, 16, 151, 18, 113, 228, 37, 6, 85, 8, 161,
+  58, 135, 76, 35, 174, 35, 224, 39, 158, 127, 180, 149, 86, 155, 200, 239, 118, 119, 28, 77,
+  254, 19, 176, 183, 78, 145, 132, 5, 90, 117, 152, 127, 218, 153, 20, 67, 178, 3, 128, 185,
+  254, 95, 172, 139, 246, 123, 104, 15, 42, 169, 68, 211, 98, 243, 80, 41, 174, 79, 36, 27,
+  186, 149, 86, 155, 200, 239, 118, 119, 28, 77, 254, 19, 176, 183,78, 145, 132, 5, 90, 117,
+  152, 127, 218, 153, 20, 67, 178, 3, 128, 185, 254, 95, 172, 139, 246, 123, 104, 15, 42,169,
+  68, 211, 98, 243, 80, 41, 174, 79, 36, 27, 186, 107, 56, 97, 134, 71, 116, 157, 238, 227,
+  32, 153, 162, 193, 244, 171, 150, 165, 248, 209, 54, 55, 164, 13, 194, 45, 16, 247, 242, 47,
+  60, 59, 26, 75, 40, 65, 230, 217, 44, 131, 142, 195, 192, 121, 190, 225, 108, 203, 202, 197,
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+  192, 7, 62, 159, 20, 181, 182, 187, 216, 207, 22, 105, 132, 109, 162, 205, 16, 151, 18, 113, 228, 37, 6, 85, 8,
+  161, 58, 135, 76, 35, 174, 35, 224, 39, 158, 127, 180, 149, 86, 155, 200, 239, 118, 119, 28, 77, 254, 19, 176, 183,
+  78, 145, 132, 5, 90, 117, 152, 127, 218, 153, 20, 67, 178, 3, 128, 185, 254, 95, 172, 139, 246, 123, 104, 15, 42,
+  169, 68, 211, 98, 243, 80, 41, 174, 79, 36, 27, 186, 107, 56, 97, 134, 71, 116, 157, 238, 227, 32, 153, 162, 193,
+  244, 171, 150, 165, 248, 209, 54, 55, 164, 13, 194, 45, 16, 247, 242, 47, 60, 59, 26, 75, 40, 65, 230, 217, 44,
+  131, 142, 195, 192, 121, 190, 225, 108, 203, 202, 197, 168, 177, 150, 233, 252, 19, 34, 77, 144, 23, 110, 15, 100, 91,
+  122, 213, 120, 223, 70, 7, 52, 93, 46, 93, 160, 167, 226, 255, 204, 21, 42, 229, 72, 111, 246, 9, 100, 205, 126,
+  147, 48, 55, 206, 239, 4, 133, 218, 245, 232, 255, 166, 231, 108, 195, 50, 131, 0, 57, 130, 223, 44, 245, 118, 251,
+  232, 113, 86, 215, 196, 83, 30, 141, 48, 87, 46, 207, 92, 155, 198, 235, 72, 31, 250, 57, 244, 29, 110, 99, 160,
+  231, 34, 65, 116, 43, 22, 219, 136, 175, 74, 73, 220, 141, 190, 83, 112, 137, 142, 81, 68, 69, 154, 203, 88, 63,
+  154, 89, 172, 3, 242, 67, 192, 249, 62, 159, 20, 181, 74, 69, 216, 49, 22, 105, 132, 109, 162, 205, 16, 151, 18,
+  113, 228, 219, 
+250, 171, 8, 95, 58, 135, 180, 35, 82, 221, 224, 39, 98, 129, 180, 107, 86, 101, 200, 239, 118, 119,
+  228, 179, 2, 237, 80, 183, 78, 111, 124, 5, 90, 117, 104, 127, 38, 153, 20, 67, 178, 253, 128, 185, 254, 95, 172,
+  117, 10, 123, 152, 241, 42, 87, 188, 211, 98, 243, 80, 215, 82, 79, 36, 27, 186, 107, 200, 159, 122, 71, 140, 157,
+  238, 29, 224, 153, 94, 63, 244, 85, 106, 91, 248, 47, 54, 201, 164, 243, 62, 211, 240, 247, 242, 47, 196, 197, 230,
+  181, 216, 65, 26, 217, 44, 125, 114, 195, 192, 135, 190, 31, 148, 203, 202, 59, 88, 79, 150, 233, 252, 19, 34, 77,
+  144, 233, 146, 15, 100, 165, 122, 213, 136, 223, 70, 249, 204, 93, 46, 93, 96, 167, 30, 1, 204, 21, 42, 27, 72
+};
+
+
Index: branches/v4/platforms/caba-new_vdspin-test/top.cpp
===================================================================
--- branches/v4/platforms/caba-new_vdspin-test/top.cpp	(revision 371)
+++ branches/v4/platforms/caba-new_vdspin-test/top.cpp	(revision 371)
@@ -0,0 +1,1132 @@
+
+#include <systemc>
+#include <sys/time.h>
+#include <iostream>
+#include <cstdlib>
+#include <cstdarg>
+
+#include "mapping_table.h"
+#include "mips32.h"
+#include "iss2_simhelper.h"
+#include "vci_simple_ram.h"
+#include "vci_multi_tty.h"
+#include "vci_mem_cache_v3.h"
+#include "vci_cc_xcache_wrapper_v1.h"
+#include "vci_local_ring_fast.h"
+#include "vci_simple_ring_fast.h"
+#include "virtual_dspin_router.h"
+
+#ifdef USE_GDB_SERVER
+#include "iss/gdbserver.h"
+#endif
+
+#include "segmentation.h"
+
+#define X_MAX           2
+#define Y_MAX           2
+#define N_PROCS         16
+#define N_CLUSTERS      X_MAX*Y_MAX
+// Router ports index
+#define NORTH		0
+#define SOUTH		1
+#define EAST		2
+#define WEST		3
+#define LOCAL		4
+
+// DSPIN flit widths
+#define cmd_width	40
+#define rsp_width	33
+
+// VCI address format
+#define adr_width	32
+#define x_width		1 //4
+#define y_width		1 //4
+#define l_width		4
+
+//  cluster index (from coordinates)
+#define cluster(x,y)	(y + Y_MAX*x)
+int _main(int argc, char *argv[])
+{
+	using namespace sc_core;
+	// Avoid repeating these everywhere
+	using soclib::common::IntTab;
+	using soclib::common::Segment;
+	using namespace soclib::caba;
+
+	// Define VCI parameters
+	typedef soclib::caba::VciParams<4,8,32,2,1,1,8,4,4,1> vci_param;
+        typedef soclib::common::Iss2Simhelper<soclib::common::Mips32ElIss> proc_iss;
+	
+	// Mapping table
+
+	soclib::common::MappingTable maptabp(32, IntTab(2,10), IntTab(2,6), 0x00F00000);
+
+	maptabp.add(Segment("text"   , TEXT_BASE   , TEXT_SIZE   , IntTab(0,0), true));
+	maptabp.add(Segment("data0"  , DATA0_BASE  , DATA0_SIZE  , IntTab(0,0), true));
+	maptabp.add(Segment("data1"  , DATA1_BASE  , DATA1_SIZE  , IntTab(1,0), true));
+	maptabp.add(Segment("data2"  , DATA2_BASE  , DATA2_SIZE  , IntTab(2,0), true));
+	maptabp.add(Segment("data3"  , DATA3_BASE  , DATA3_SIZE  , IntTab(3,0), true));
+	maptabp.add(Segment("reset"  , RESET_BASE  , RESET_SIZE  , IntTab(2,0), true));
+	maptabp.add(Segment("excep"  , EXCEP_BASE  , EXCEP_SIZE  , IntTab(2,0), true));
+	maptabp.add(Segment("tty"    , TTY_BASE    , TTY_SIZE    , IntTab(3,1), false));
+
+	std::cout << maptabp << std::endl;
+
+	soclib::common::MappingTable maptabc(32, IntTab(2,10), IntTab(2,6), 0x00F00000);
+
+	maptabc.add(Segment("proc0"  , PROC0_BASE  , PROC0_SIZE  , IntTab(0,0), false, true, IntTab(0,0)));
+	maptabc.add(Segment("proc1"  , PROC1_BASE  , PROC1_SIZE  , IntTab(0,1), false, true, IntTab(0,1)));
+	maptabc.add(Segment("proc2"  , PROC2_BASE  , PROC2_SIZE  , IntTab(0,2), false, true, IntTab(0,2)));
+	maptabc.add(Segment("proc3"  , PROC3_BASE  , PROC3_SIZE  , IntTab(0,3), false, true, IntTab(0,3)));
+	maptabc.add(Segment("proc4"  , PROC4_BASE  , PROC4_SIZE  , IntTab(1,0), false, true, IntTab(1,0)));
+	maptabc.add(Segment("proc5"  , PROC5_BASE  , PROC5_SIZE  , IntTab(1,1), false, true, IntTab(1,1)));
+	maptabc.add(Segment("proc6"  , PROC6_BASE  , PROC6_SIZE  , IntTab(1,2), false, true, IntTab(1,2)));
+	maptabc.add(Segment("proc7"  , PROC7_BASE  , PROC7_SIZE  , IntTab(1,3), false, true, IntTab(1,3)));
+	maptabc.add(Segment("proc8"  , PROC8_BASE  , PROC8_SIZE  , IntTab(2,0), false, true, IntTab(2,0)));
+	maptabc.add(Segment("proc9"  , PROC9_BASE  , PROC9_SIZE  , IntTab(2,1), false, true, IntTab(2,1)));
+	maptabc.add(Segment("proc10" , PROC10_BASE , PROC10_SIZE , IntTab(2,2), false, true, IntTab(2,2)));
+	maptabc.add(Segment("proc11" , PROC11_BASE , PROC11_SIZE , IntTab(2,3), false, true, IntTab(2,3)));
+	maptabc.add(Segment("proc12" , PROC12_BASE , PROC12_SIZE , IntTab(3,0), false, true, IntTab(3,0)));
+	maptabc.add(Segment("proc13" , PROC13_BASE , PROC13_SIZE , IntTab(3,1), false, true, IntTab(3,1)));
+	maptabc.add(Segment("proc14" , PROC14_BASE , PROC14_SIZE , IntTab(3,2), false, true, IntTab(3,2)));
+	maptabc.add(Segment("proc15" , PROC15_BASE , PROC15_SIZE , IntTab(3,3), false, true, IntTab(3,3)));
+        maptabc.add(Segment("reset"  , RESET_BASE  , RESET_SIZE  , IntTab(2,4), false, false));
+	maptabc.add(Segment("excep"  , EXCEP_BASE  , EXCEP_SIZE  , IntTab(2,4), false, false));
+        maptabc.add(Segment("text"   , TEXT_BASE   , TEXT_SIZE   , IntTab(0,4), false, false));
+	maptabc.add(Segment("data0"  , DATA0_BASE  , DATA0_SIZE  , IntTab(0,4), false,false));
+	maptabc.add(Segment("data1"  , DATA1_BASE  , DATA1_SIZE  , IntTab(1,4), false,false));
+	maptabc.add(Segment("data2"  , DATA2_BASE  , DATA2_SIZE  , IntTab(2,4), false,false));
+	maptabc.add(Segment("data3"  , DATA3_BASE  , DATA3_SIZE  , IntTab(3,4), false,false));
+
+	std::cout << maptabc << std::endl;
+
+	soclib::common::MappingTable maptabx(32, IntTab(8), IntTab(8), 0x00F00000);
+       	maptabx.add(Segment("reset" , RESET_BASE , RESET_SIZE , IntTab(0), false));
+	maptabx.add(Segment("excep" , EXCEP_BASE , EXCEP_SIZE , IntTab(0), false));
+	maptabx.add(Segment("text"  , TEXT_BASE  , TEXT_SIZE  , IntTab(0), false));
+	maptabx.add(Segment("data0"  , DATA0_BASE  , DATA0_SIZE  , IntTab(0), false));
+	maptabx.add(Segment("data1"  , DATA1_BASE  , DATA1_SIZE  , IntTab(0), false));
+	maptabx.add(Segment("data2"  , DATA2_BASE  , DATA2_SIZE  , IntTab(0), false));
+	maptabx.add(Segment("data3"  , DATA3_BASE  , DATA3_SIZE  , IntTab(0), false));
+
+	std::cout << maptabx << std::endl;
+
+	// Signals
+
+	sc_clock	signal_clk("clk");
+	sc_signal<bool> signal_resetn("resetn");
+   
+	sc_signal<bool> signal_proc0_it0("proc0_it0"); 
+	sc_signal<bool> signal_proc0_it1("proc0_it1"); 
+	sc_signal<bool> signal_proc0_it2("proc0_it2"); 
+	sc_signal<bool> signal_proc0_it3("proc0_it3"); 
+	sc_signal<bool> signal_proc0_it4("proc0_it4"); 
+	sc_signal<bool> signal_proc0_it5("proc0_it5");
+
+	sc_signal<bool> signal_proc1_it0("proc1_it0"); 
+	sc_signal<bool> signal_proc1_it1("proc1_it1"); 
+	sc_signal<bool> signal_proc1_it2("proc1_it2"); 
+	sc_signal<bool> signal_proc1_it3("proc1_it3"); 
+	sc_signal<bool> signal_proc1_it4("proc1_it4"); 
+	sc_signal<bool> signal_proc1_it5("proc1_it5");
+
+	sc_signal<bool> signal_proc2_it0("proc2_it0"); 
+	sc_signal<bool> signal_proc2_it1("proc2_it1"); 
+	sc_signal<bool> signal_proc2_it2("proc2_it2"); 
+	sc_signal<bool> signal_proc2_it3("proc2_it3"); 
+	sc_signal<bool> signal_proc2_it4("proc2_it4"); 
+	sc_signal<bool> signal_proc2_it5("proc2_it5");
+
+	sc_signal<bool> signal_proc3_it0("proc3_it0"); 
+	sc_signal<bool> signal_proc3_it1("proc3_it1"); 
+	sc_signal<bool> signal_proc3_it2("proc3_it2"); 
+	sc_signal<bool> signal_proc3_it3("proc3_it3"); 
+	sc_signal<bool> signal_proc3_it4("proc3_it4"); 
+	sc_signal<bool> signal_proc3_it5("proc3_it5");
+
+	sc_signal<bool> signal_proc4_it0("proc4_it0"); 
+	sc_signal<bool> signal_proc4_it1("proc4_it1"); 
+	sc_signal<bool> signal_proc4_it2("proc4_it2"); 
+	sc_signal<bool> signal_proc4_it3("proc4_it3"); 
+	sc_signal<bool> signal_proc4_it4("proc4_it4"); 
+	sc_signal<bool> signal_proc4_it5("proc4_it5");
+
+	sc_signal<bool> signal_proc5_it0("proc5_it0"); 
+	sc_signal<bool> signal_proc5_it1("proc5_it1"); 
+	sc_signal<bool> signal_proc5_it2("proc5_it2"); 
+	sc_signal<bool> signal_proc5_it3("proc5_it3"); 
+	sc_signal<bool> signal_proc5_it4("proc5_it4"); 
+	sc_signal<bool> signal_proc5_it5("proc5_it5");
+
+	sc_signal<bool> signal_proc6_it0("proc6_it0"); 
+	sc_signal<bool> signal_proc6_it1("proc6_it1"); 
+	sc_signal<bool> signal_proc6_it2("proc6_it2"); 
+	sc_signal<bool> signal_proc6_it3("proc6_it3"); 
+	sc_signal<bool> signal_proc6_it4("proc6_it4"); 
+	sc_signal<bool> signal_proc6_it5("proc6_it5");
+
+	sc_signal<bool> signal_proc7_it0("proc7_it0"); 
+	sc_signal<bool> signal_proc7_it1("proc7_it1"); 
+	sc_signal<bool> signal_proc7_it2("proc7_it2"); 
+	sc_signal<bool> signal_proc7_it3("proc7_it3"); 
+	sc_signal<bool> signal_proc7_it4("proc7_it4"); 
+	sc_signal<bool> signal_proc7_it5("proc7_it5");
+
+	sc_signal<bool> signal_proc8_it0("proc8_it0"); 
+	sc_signal<bool> signal_proc8_it1("proc8_it1"); 
+	sc_signal<bool> signal_proc8_it2("proc8_it2"); 
+	sc_signal<bool> signal_proc8_it3("proc8_it3"); 
+	sc_signal<bool> signal_proc8_it4("proc8_it4"); 
+	sc_signal<bool> signal_proc8_it5("proc8_it5");
+
+	sc_signal<bool> signal_proc9_it0("proc9_it0"); 
+	sc_signal<bool> signal_proc9_it1("proc9_it1"); 
+	sc_signal<bool> signal_proc9_it2("proc9_it2"); 
+	sc_signal<bool> signal_proc9_it3("proc9_it3"); 
+	sc_signal<bool> signal_proc9_it4("proc9_it4"); 
+	sc_signal<bool> signal_proc9_it5("proc9_it5");
+
+	sc_signal<bool> signal_proc10_it0("proc10_it0"); 
+	sc_signal<bool> signal_proc10_it1("proc10_it1"); 
+	sc_signal<bool> signal_proc10_it2("proc10_it2"); 
+	sc_signal<bool> signal_proc10_it3("proc10_it3"); 
+	sc_signal<bool> signal_proc10_it4("proc10_it4"); 
+	sc_signal<bool> signal_proc10_it5("proc10_it5");
+
+	sc_signal<bool> signal_proc11_it0("proc11_it0"); 
+	sc_signal<bool> signal_proc11_it1("proc11_it1"); 
+	sc_signal<bool> signal_proc11_it2("proc11_it2"); 
+	sc_signal<bool> signal_proc11_it3("proc11_it3"); 
+	sc_signal<bool> signal_proc11_it4("proc11_it4"); 
+	sc_signal<bool> signal_proc11_it5("proc11_it5");
+
+	sc_signal<bool> signal_proc12_it0("proc12_it0"); 
+	sc_signal<bool> signal_proc12_it1("proc12_it1"); 
+	sc_signal<bool> signal_proc12_it2("proc12_it2"); 
+	sc_signal<bool> signal_proc12_it3("proc12_it3"); 
+	sc_signal<bool> signal_proc12_it4("proc12_it4"); 
+	sc_signal<bool> signal_proc12_it5("proc12_it5");
+
+	sc_signal<bool> signal_proc13_it0("proc13_it0"); 
+	sc_signal<bool> signal_proc13_it1("proc13_it1"); 
+	sc_signal<bool> signal_proc13_it2("proc13_it2"); 
+	sc_signal<bool> signal_proc13_it3("proc13_it3"); 
+	sc_signal<bool> signal_proc13_it4("proc13_it4"); 
+	sc_signal<bool> signal_proc13_it5("proc13_it5");
+
+	sc_signal<bool> signal_proc14_it0("proc14_it0"); 
+	sc_signal<bool> signal_proc14_it1("proc14_it1"); 
+	sc_signal<bool> signal_proc14_it2("proc14_it2"); 
+	sc_signal<bool> signal_proc14_it3("proc14_it3"); 
+	sc_signal<bool> signal_proc14_it4("proc14_it4"); 
+	sc_signal<bool> signal_proc14_it5("proc14_it5");
+
+	sc_signal<bool> signal_proc15_it0("proc15_it0"); 
+	sc_signal<bool> signal_proc15_it1("proc15_it1"); 
+	sc_signal<bool> signal_proc15_it2("proc15_it2"); 
+	sc_signal<bool> signal_proc15_it3("proc15_it3"); 
+	sc_signal<bool> signal_proc15_it4("proc15_it4"); 
+	sc_signal<bool> signal_proc15_it5("proc15_it5");
+
+//--- Dspin router 
+	DspinSignals<cmd_width>*** signal_dspin_false_cmd_in = alloc_elems<DspinSignals<cmd_width> >("signal_dspin_false_cmd_in", (Y_MAX*X_MAX), 2, 2);
+	DspinSignals<cmd_width>*** signal_dspin_false_cmd_out = alloc_elems<DspinSignals<cmd_width> >("signal_dspin_false_cmd_out", (Y_MAX*X_MAX), 2, 2);
+	DspinSignals<rsp_width>*** signal_dspin_false_rsp_in = alloc_elems<DspinSignals<rsp_width> >("signal_dspin_false_rsp_in", (Y_MAX*X_MAX), 2, 2);
+	DspinSignals<rsp_width>*** signal_dspin_false_rsp_out = alloc_elems<DspinSignals<rsp_width> >("signal_dspin_false_rsp_out", (Y_MAX*X_MAX), 2, 2);
+
+
+	// DSPIN signals between local ring & global interconnects
+	DspinSignals<cmd_width>** signal_dspin_cmd_l2g_d =
+	    alloc_elems<DspinSignals<cmd_width> >("signal_dspin_cmd_l2g_d", X_MAX, Y_MAX);
+	DspinSignals<cmd_width>** signal_dspin_cmd_g2l_d =
+	    alloc_elems<DspinSignals<cmd_width> >("signal_dspin_cmd_g2l_d", X_MAX, Y_MAX);
+	
+	DspinSignals<cmd_width>** signal_dspin_cmd_l2g_c =
+	    alloc_elems<DspinSignals<cmd_width> >("signal_dspin_cmd_l2g_c", X_MAX, Y_MAX);
+	DspinSignals<cmd_width>** signal_dspin_cmd_g2l_c =
+	    alloc_elems<DspinSignals<cmd_width> >("signal_dspin_cmd_g2l_c", X_MAX, Y_MAX);
+	
+	DspinSignals<rsp_width>** signal_dspin_rsp_l2g_d =
+	    alloc_elems<DspinSignals<rsp_width> >("signal_dspin_rsp_l2g_d", X_MAX, Y_MAX);
+	DspinSignals<rsp_width>** signal_dspin_rsp_g2l_d =
+	    alloc_elems<DspinSignals<rsp_width> >("signal_dspin_rsp_g2l_d", X_MAX, Y_MAX);
+	
+	DspinSignals<rsp_width>** signal_dspin_rsp_l2g_c =
+	    alloc_elems<DspinSignals<rsp_width> >("signal_dspin_rsp_l2g_c", X_MAX, Y_MAX);
+	DspinSignals<rsp_width>** signal_dspin_rsp_g2l_c =
+	    alloc_elems<DspinSignals<rsp_width> >("signal_dspin_rsp_g2l_c", X_MAX, Y_MAX);
+	
+	// Horizontal inter-clusters DSPIN signals
+	DspinSignals<cmd_width>*** signal_dspin_h_cmd_inc =
+	    alloc_elems<DspinSignals<cmd_width> >("signal_dspin_h_cmd_inc", X_MAX-1, Y_MAX, 2);
+	DspinSignals<cmd_width>*** signal_dspin_h_cmd_dec =
+	    alloc_elems<DspinSignals<cmd_width> >("signal_dspin_h_cmd_dec", X_MAX-1, Y_MAX, 2);
+	DspinSignals<rsp_width>*** signal_dspin_h_rsp_inc =
+	    alloc_elems<DspinSignals<rsp_width> >("signal_dspin_h_rsp_inc", X_MAX-1, Y_MAX, 2);
+	DspinSignals<rsp_width>*** signal_dspin_h_rsp_dec =
+	    alloc_elems<DspinSignals<rsp_width> >("signal_dspin_h_rsp_dec", X_MAX-1, Y_MAX, 2);
+	
+	// Vertical inter-clusters DSPIN signals
+	DspinSignals<cmd_width>*** signal_dspin_v_cmd_inc =
+	    alloc_elems<DspinSignals<cmd_width> >("signal_dspin_v_cmd_inc", X_MAX, Y_MAX-1, 2);
+	DspinSignals<cmd_width>*** signal_dspin_v_cmd_dec =
+	    alloc_elems<DspinSignals<cmd_width> >("signal_dspin_v_cmd_dec", X_MAX, Y_MAX-1, 2);
+	DspinSignals<rsp_width>*** signal_dspin_v_rsp_inc =
+	    alloc_elems<DspinSignals<rsp_width> >("signal_dspin_v_rsp_inc", X_MAX, Y_MAX-1, 2);
+	DspinSignals<rsp_width>*** signal_dspin_v_rsp_dec =
+	    alloc_elems<DspinSignals<rsp_width> >("signal_dspin_v_rsp_dec", X_MAX, Y_MAX-1, 2);
+
+        soclib::caba::VciSignals<vci_param> signal_vci_ini_rw_proc0("vci_ini_rw_proc0");
+	soclib::caba::VciSignals<vci_param> signal_vci_ini_c_proc0("vci_ini_c_proc0");
+
+	soclib::caba::VciSignals<vci_param> signal_vci_tgt_proc0("vci_tgt_proc0");
+
+	soclib::caba::VciSignals<vci_param> signal_vci_ini_rw_proc1("vci_ini_rw_proc1");
+	soclib::caba::VciSignals<vci_param> signal_vci_ini_c_proc1("vci_ini_c_proc1");
+
+	soclib::caba::VciSignals<vci_param> signal_vci_tgt_proc1("vci_tgt_proc1");
+
+	soclib::caba::VciSignals<vci_param> signal_vci_ini_rw_proc2("vci_ini_rw_proc2");
+	soclib::caba::VciSignals<vci_param> signal_vci_ini_c_proc2("vci_ini_c_proc2");
+
+	soclib::caba::VciSignals<vci_param> signal_vci_tgt_proc2("vci_tgt_proc2");
+
+	soclib::caba::VciSignals<vci_param> signal_vci_ini_rw_proc3("vci_ini_rw_proc3");
+	soclib::caba::VciSignals<vci_param> signal_vci_ini_c_proc3("vci_ini_c_proc3");
+
+        soclib::caba::VciSignals<vci_param> signal_vci_tgt_proc3("vci_tgt_proc3");
+
+        soclib::caba::VciSignals<vci_param> signal_vci_ini_rw_proc4("vci_ini_rw_proc4");
+	soclib::caba::VciSignals<vci_param> signal_vci_ini_c_proc4("vci_ini_c_proc4");
+
+	soclib::caba::VciSignals<vci_param> signal_vci_tgt_proc4("vci_tgt_proc4");
+
+	soclib::caba::VciSignals<vci_param> signal_vci_ini_rw_proc5("vci_ini_rw_proc5");
+	soclib::caba::VciSignals<vci_param> signal_vci_ini_c_proc5("vci_ini_c_proc5");
+
+	soclib::caba::VciSignals<vci_param> signal_vci_tgt_proc5("vci_tgt_proc5");
+
+	soclib::caba::VciSignals<vci_param> signal_vci_ini_rw_proc6("vci_ini_rw_proc6");
+	soclib::caba::VciSignals<vci_param> signal_vci_ini_c_proc6("vci_ini_c_proc6");
+
+	soclib::caba::VciSignals<vci_param> signal_vci_tgt_proc6("vci_tgt_proc6");
+
+	soclib::caba::VciSignals<vci_param> signal_vci_ini_rw_proc7("vci_ini_rw_proc7");
+	soclib::caba::VciSignals<vci_param> signal_vci_ini_c_proc7("vci_ini_c_proc7");
+
+        soclib::caba::VciSignals<vci_param> signal_vci_tgt_proc7("vci_tgt_proc7");
+
+	soclib::caba::VciSignals<vci_param> signal_vci_ini_rw_proc8("vci_ini_rw_proc8");
+	soclib::caba::VciSignals<vci_param> signal_vci_ini_c_proc8("vci_ini_c_proc8");
+
+	soclib::caba::VciSignals<vci_param> signal_vci_tgt_proc8("vci_tgt_proc8");
+
+	soclib::caba::VciSignals<vci_param> signal_vci_ini_rw_proc9("vci_ini_rw_proc9");
+	soclib::caba::VciSignals<vci_param> signal_vci_ini_c_proc9("vci_ini_c_proc9");
+
+	soclib::caba::VciSignals<vci_param> signal_vci_tgt_proc9("vci_tgt_proc9");
+
+	soclib::caba::VciSignals<vci_param> signal_vci_ini_rw_proc10("vci_ini_rw_proc10");
+	soclib::caba::VciSignals<vci_param> signal_vci_ini_c_proc10("vci_ini_c_proc10");
+
+	soclib::caba::VciSignals<vci_param> signal_vci_tgt_proc10("vci_tgt_proc10");
+
+	soclib::caba::VciSignals<vci_param> signal_vci_ini_rw_proc11("vci_ini_rw_proc11");
+	soclib::caba::VciSignals<vci_param> signal_vci_ini_c_proc11("vci_ini_c_proc11");
+
+	soclib::caba::VciSignals<vci_param> signal_vci_tgt_proc11("vci_tgt_proc11");
+
+	soclib::caba::VciSignals<vci_param> signal_vci_ini_rw_proc12("vci_ini_rw_proc12");
+	soclib::caba::VciSignals<vci_param> signal_vci_ini_c_proc12("vci_ini_c_proc12");
+
+	soclib::caba::VciSignals<vci_param> signal_vci_tgt_proc12("vci_tgt_proc12");
+
+	soclib::caba::VciSignals<vci_param> signal_vci_ini_rw_proc13("vci_ini_rw_proc13");
+	soclib::caba::VciSignals<vci_param> signal_vci_ini_c_proc13("vci_ini_c_proc13");
+
+	soclib::caba::VciSignals<vci_param> signal_vci_tgt_proc13("vci_tgt_proc13");
+
+	soclib::caba::VciSignals<vci_param> signal_vci_ini_rw_proc14("vci_ini_rw_proc14");
+	soclib::caba::VciSignals<vci_param> signal_vci_ini_c_proc14("vci_ini_c_proc14");
+
+	soclib::caba::VciSignals<vci_param> signal_vci_tgt_proc14("vci_tgt_proc14");
+
+	soclib::caba::VciSignals<vci_param> signal_vci_ini_rw_proc15("vci_ini_rw_proc15");
+	soclib::caba::VciSignals<vci_param> signal_vci_ini_c_proc15("vci_ini_c_proc15");
+
+	soclib::caba::VciSignals<vci_param> signal_vci_tgt_proc15("vci_tgt_proc15");
+
+	soclib::caba::VciSignals<vci_param> signal_vci_tgt_tty("vci_tgt_tty");
+
+
+	soclib::caba::VciSignals<vci_param> signal_vci_tgt_xram("vci_tgt_xram");
+
+	soclib::caba::VciSignals<vci_param> signal_vci_ixr_memc0("vci_ixr_memc0");
+	soclib::caba::VciSignals<vci_param> signal_vci_ini_memc0("vci_ini_memc0");
+	soclib::caba::VciSignals<vci_param> signal_vci_tgt_memc0("vci_tgt_memc0");
+        soclib::caba::VciSignals<vci_param> signal_vci_tgt_cleanup_memc0("vci_tgt_cleanup_memc0");
+
+	soclib::caba::VciSignals<vci_param> signal_vci_ixr_memc1("vci_ixr_memc1");
+	soclib::caba::VciSignals<vci_param> signal_vci_ini_memc1("vci_ini_memc1");
+	soclib::caba::VciSignals<vci_param> signal_vci_tgt_memc1("vci_tgt_memc1");
+        soclib::caba::VciSignals<vci_param> signal_vci_tgt_cleanup_memc1("vci_tgt_cleanup_memc1");
+
+	soclib::caba::VciSignals<vci_param> signal_vci_ixr_memc2("vci_ixr_memc2");
+	soclib::caba::VciSignals<vci_param> signal_vci_ini_memc2("vci_ini_memc2");
+	soclib::caba::VciSignals<vci_param> signal_vci_tgt_memc2("vci_tgt_memc2");
+        soclib::caba::VciSignals<vci_param> signal_vci_tgt_cleanup_memc2("vci_tgt_cleanup_memc2");
+
+	soclib::caba::VciSignals<vci_param> signal_vci_ixr_memc3("vci_ixr_memc3");
+	soclib::caba::VciSignals<vci_param> signal_vci_ini_memc3("vci_ini_memc3");
+	soclib::caba::VciSignals<vci_param> signal_vci_tgt_memc3("vci_tgt_memc3");
+        soclib::caba::VciSignals<vci_param> signal_vci_tgt_cleanup_memc3("vci_tgt_cleanup_memc3");
+
+	sc_signal<bool> signal_tty_irq0("signal_tty_irq0"); 
+	sc_signal<bool> signal_tty_irq1("signal_tty_irq1"); 
+	sc_signal<bool> signal_tty_irq2("signal_tty_irq2"); 
+	sc_signal<bool> signal_tty_irq3("signal_tty_irq3"); 
+	sc_signal<bool> signal_tty_irq4("signal_tty_irq4"); 
+	sc_signal<bool> signal_tty_irq5("signal_tty_irq5"); 
+	sc_signal<bool> signal_tty_irq6("signal_tty_irq6"); 
+	sc_signal<bool> signal_tty_irq7("signal_tty_irq7"); 
+	sc_signal<bool> signal_tty_irq8("signal_tty_irq8"); 
+	sc_signal<bool> signal_tty_irq9("signal_tty_irq9"); 
+	sc_signal<bool> signal_tty_irq10("signal_tty_irq10"); 
+	sc_signal<bool> signal_tty_irq11("signal_tty_irq11"); 
+	sc_signal<bool> signal_tty_irq12("signal_tty_irq12"); 
+	sc_signal<bool> signal_tty_irq13("signal_tty_irq13"); 
+	sc_signal<bool> signal_tty_irq14("signal_tty_irq14"); 
+	sc_signal<bool> signal_tty_irq15("signal_tty_irq15"); 
+
+	soclib::common::Loader loader("soft/bin.soft");
+
+	//                                  init_rw   init_c   tgt
+        soclib::caba::VciCcXCacheWrapperV1<vci_param, proc_iss > 
+        proc0("proc0", 0, maptabp, maptabc, IntTab(0,0),IntTab(0,0),IntTab(0,0),4,4,16,4,4,16);
+
+        soclib::caba::VciCcXCacheWrapperV1<vci_param, proc_iss > 
+        proc1("proc1", 1, maptabp, maptabc, IntTab(0,1),IntTab(0,1),IntTab(0,1),4,4,16,4,4,16);
+
+        soclib::caba::VciCcXCacheWrapperV1<vci_param, proc_iss > 
+        proc2("proc2", 2, maptabp, maptabc, IntTab(0,2),IntTab(0,2),IntTab(0,2),4,4,16,4,4,16);
+
+        soclib::caba::VciCcXCacheWrapperV1<vci_param, proc_iss > 
+        proc3("proc3", 3, maptabp, maptabc, IntTab(0,3),IntTab(0,3),IntTab(0,3),4,4,16,4,4,16);
+
+        soclib::caba::VciCcXCacheWrapperV1<vci_param, proc_iss > 
+        proc4("proc4", 4, maptabp, maptabc, IntTab(1,0),IntTab(1,0),IntTab(1,0),4,4,16,4,4,16);
+
+        soclib::caba::VciCcXCacheWrapperV1<vci_param, proc_iss > 
+        proc5("proc5", 5, maptabp, maptabc, IntTab(1,1),IntTab(1,1),IntTab(1,1),4,4,16,4,4,16);
+
+        soclib::caba::VciCcXCacheWrapperV1<vci_param, proc_iss > 
+        proc6("proc6", 6, maptabp, maptabc, IntTab(1,2),IntTab(1,2),IntTab(1,2),4,4,16,4,4,16);
+
+        soclib::caba::VciCcXCacheWrapperV1<vci_param, proc_iss > 
+        proc7("proc7", 7, maptabp, maptabc, IntTab(1,3),IntTab(1,3),IntTab(1,3),4,4,16,4,4,16);
+
+        soclib::caba::VciCcXCacheWrapperV1<vci_param, proc_iss > 
+        proc8("proc8", 8, maptabp, maptabc, IntTab(2,0),IntTab(2,0),IntTab(2,0),4,4,16,4,4,16);
+
+        soclib::caba::VciCcXCacheWrapperV1<vci_param, proc_iss > 
+        proc9("proc9", 9, maptabp, maptabc, IntTab(2,1),IntTab(2,1),IntTab(2,1),4,4,16,4,4,16);
+
+        soclib::caba::VciCcXCacheWrapperV1<vci_param, proc_iss > 
+        proc10("proc10", 10, maptabp, maptabc, IntTab(2,2),IntTab(2,2),IntTab(2,2),4,4,16,4,4,16);
+
+        soclib::caba::VciCcXCacheWrapperV1<vci_param, proc_iss > 
+        proc11("proc11", 11, maptabp, maptabc, IntTab(2,3),IntTab(2,3),IntTab(2,3),4,4,16,4,4,16);
+
+        soclib::caba::VciCcXCacheWrapperV1<vci_param, proc_iss > 
+        proc12("proc12", 12, maptabp, maptabc, IntTab(3,0),IntTab(3,0),IntTab(3,0),4,4,16,4,4,16);
+
+        soclib::caba::VciCcXCacheWrapperV1<vci_param, proc_iss > 
+        proc13("proc13", 13, maptabp, maptabc, IntTab(3,1),IntTab(3,1),IntTab(3,1),4,4,16,4,4,16);
+
+        soclib::caba::VciCcXCacheWrapperV1<vci_param, proc_iss > 
+        proc14("proc14", 14, maptabp, maptabc, IntTab(3,2),IntTab(3,2),IntTab(3,2),4,4,16,4,4,16);
+
+        soclib::caba::VciCcXCacheWrapperV1<vci_param, proc_iss > 
+        proc15("proc15", 15, maptabp, maptabc, IntTab(3,3),IntTab(3,3),IntTab(3,3),4,4,16,4,4,16);
+
+
+	soclib::caba::VciSimpleRam<vci_param> 
+	xram("xram",IntTab(0),maptabx, loader);
+
+        //                                  x_init    c_init    p_tgt     c_tgt
+	soclib::caba::VciMemCacheV3<vci_param> 
+//	memc0("memc0",maptabp,maptabc,maptabx,IntTab(0),IntTab(0,4),IntTab(0,0), IntTab(0,4), 16,256,16);
+        memc0("memc0",maptabp,maptabc,maptabx,IntTab(0),IntTab(0,4),IntTab(0,0), IntTab(0,4), 4,16,16);
+
+	soclib::caba::VciMemCacheV3<vci_param> 
+	memc1("memc1",maptabp,maptabc,maptabx,IntTab(1),IntTab(1,4),IntTab(1,0), IntTab(1,4), 4,16,16);
+
+	soclib::caba::VciMemCacheV3<vci_param> 
+	memc2("memc2",maptabp,maptabc,maptabx,IntTab(2),IntTab(2,4),IntTab(2,0), IntTab(2,4), 4,16,16);
+
+	soclib::caba::VciMemCacheV3<vci_param> 
+	memc3("memc3",maptabp,maptabc,maptabx,IntTab(3),IntTab(3,4),IntTab(3,0), IntTab(3,4), 4,16,16);
+	
+	soclib::caba::VciMultiTty<vci_param> 
+	tty("tty",IntTab(3,1),maptabp,"tty0","tty1","tty2","tty3","tty4","tty5","tty6","tty7","tty8","tty9","tty10","tty11","tty12","tty13","tty14","tty15",NULL);
+
+    
+	soclib::caba::VciLocalRingFast<vci_param, 40, 33> 
+	clusterPN0("clusterPN0",maptabp, IntTab(0), 2, 18, 4, 1 );
+
+	soclib::caba::VciLocalRingFast<vci_param, 40, 33>
+	clusterPN1("clusterPN1",maptabp, IntTab(1), 2, 18, 4, 1 );
+
+	soclib::caba::VciLocalRingFast<vci_param, 40, 33>
+	clusterPN2("clusterPN2",maptabp, IntTab(2), 2, 18, 4, 1 );
+
+	soclib::caba::VciLocalRingFast<vci_param, 40, 33>
+	clusterPN3("clusterPN3",maptabp, IntTab(3), 2, 18, 4, 2 );
+
+	soclib::caba::VciLocalRingFast<vci_param, 40, 33> 
+	clusterCN0("clusterCN0",maptabc, IntTab(0), 2, 2, 5, 5 );
+
+	soclib::caba::VciLocalRingFast<vci_param, 40, 33> 
+	clusterCN1("clusterCN1",maptabc, IntTab(1), 2, 2, 5, 5 );
+
+	soclib::caba::VciLocalRingFast<vci_param, 40, 33> 
+	clusterCN2("clusterCN2",maptabc, IntTab(2), 2, 2, 5, 5 );
+
+	soclib::caba::VciLocalRingFast<vci_param, 40, 33> 
+	clusterCN3("clusterCN3",maptabc, IntTab(3), 2, 2, 5, 5 );
+
+        soclib::caba::VciSimpleRingFast<vci_param, 40, 33>
+    	xring("xring",maptabx, IntTab(), 2, 4, 1);
+
+	// Distributed Global Interconnect : one cmd router & one rsp router per cluster
+	VirtualDspinRouter<cmd_width>* cmdrouter = (VirtualDspinRouter<cmd_width>*)
+	    malloc(sizeof(VirtualDspinRouter<cmd_width>) * X_MAX * Y_MAX);
+	VirtualDspinRouter<rsp_width>* rsprouter = (VirtualDspinRouter<rsp_width>*)
+	    malloc(sizeof(VirtualDspinRouter<rsp_width>) * X_MAX * Y_MAX);
+
+	for ( size_t x = 0 ; x < X_MAX ; x++ )
+	{
+	    for ( size_t y = 0 ; y < Y_MAX ; y++ )
+	    {
+	
+	        std::ostringstream   str_cmd;
+		std::ostringstream   str_rsp;
+
+	        str_cmd << "cmdrouter_" << x << "_" << y;
+	        str_rsp << "rsprouter_" << x << "_" << y;
+
+	        new(&cmdrouter[cluster(x,y)]) VirtualDspinRouter<cmd_width>(str_cmd.str().c_str(),
+	                                                 x,y,		// coordinate in the mesh
+	                                                 x_width, y_width,	// x & y fields width
+	                                                 4,4);		// input & output fifo depths
+	        new(&rsprouter[cluster(x,y)]) VirtualDspinRouter<rsp_width>(str_rsp.str().c_str(),
+	                                                 x,y,		// coordinates in mesh
+	                                                 x_width, y_width,	// x & y fields width
+	                                                 4,4);		// input & output fifo depths
+	    }
+	}
+
+	proc0.p_clk(signal_clk);
+	proc0.p_resetn(signal_resetn);
+	proc0.p_irq[0](signal_proc0_it0);
+	proc0.p_irq[1](signal_proc0_it1);
+	proc0.p_irq[2](signal_proc0_it2);
+	proc0.p_irq[3](signal_proc0_it3); 
+	proc0.p_irq[4](signal_proc0_it4); 
+	proc0.p_irq[5](signal_proc0_it5); 
+	proc0.p_vci_ini_rw(signal_vci_ini_rw_proc0);
+	proc0.p_vci_ini_c(signal_vci_ini_c_proc0);
+	proc0.p_vci_tgt(signal_vci_tgt_proc0);
+
+	proc1.p_clk(signal_clk);  
+	proc1.p_resetn(signal_resetn);  
+	proc1.p_irq[0](signal_proc1_it0); 
+	proc1.p_irq[1](signal_proc1_it1); 
+	proc1.p_irq[2](signal_proc1_it2); 
+	proc1.p_irq[3](signal_proc1_it3); 
+	proc1.p_irq[4](signal_proc1_it4); 
+	proc1.p_irq[5](signal_proc1_it5); 
+	proc1.p_vci_ini_rw(signal_vci_ini_rw_proc1);
+	proc1.p_vci_ini_c(signal_vci_ini_c_proc1);
+	proc1.p_vci_tgt(signal_vci_tgt_proc1);
+
+	proc2.p_clk(signal_clk);  
+	proc2.p_resetn(signal_resetn);  
+	proc2.p_irq[0](signal_proc2_it0); 
+	proc2.p_irq[1](signal_proc2_it1); 
+	proc2.p_irq[2](signal_proc2_it2); 
+	proc2.p_irq[3](signal_proc2_it3); 
+	proc2.p_irq[4](signal_proc2_it4); 
+	proc2.p_irq[5](signal_proc2_it5); 
+	proc2.p_vci_ini_rw(signal_vci_ini_rw_proc2);
+	proc2.p_vci_ini_c(signal_vci_ini_c_proc2);
+	proc2.p_vci_tgt(signal_vci_tgt_proc2);
+
+	proc3.p_clk(signal_clk);  
+	proc3.p_resetn(signal_resetn);  
+	proc3.p_irq[0](signal_proc3_it0); 
+	proc3.p_irq[1](signal_proc3_it1); 
+	proc3.p_irq[2](signal_proc3_it2); 
+	proc3.p_irq[3](signal_proc3_it3); 
+	proc3.p_irq[4](signal_proc3_it4); 
+	proc3.p_irq[5](signal_proc3_it5); 
+	proc3.p_vci_ini_rw(signal_vci_ini_rw_proc3);
+	proc3.p_vci_ini_c(signal_vci_ini_c_proc3);
+	proc3.p_vci_tgt(signal_vci_tgt_proc3);
+
+	proc4.p_clk(signal_clk);  
+	proc4.p_resetn(signal_resetn);  
+	proc4.p_irq[0](signal_proc4_it0); 
+	proc4.p_irq[1](signal_proc4_it1); 
+	proc4.p_irq[2](signal_proc4_it2); 
+	proc4.p_irq[3](signal_proc4_it3); 
+	proc4.p_irq[4](signal_proc4_it4); 
+	proc4.p_irq[5](signal_proc4_it5); 
+	proc4.p_vci_ini_rw(signal_vci_ini_rw_proc4);
+	proc4.p_vci_ini_c(signal_vci_ini_c_proc4);
+	proc4.p_vci_tgt(signal_vci_tgt_proc4);
+
+	proc5.p_clk(signal_clk);  
+	proc5.p_resetn(signal_resetn);  
+	proc5.p_irq[0](signal_proc5_it0); 
+	proc5.p_irq[1](signal_proc5_it1); 
+	proc5.p_irq[2](signal_proc5_it2); 
+	proc5.p_irq[3](signal_proc5_it3); 
+	proc5.p_irq[4](signal_proc5_it4); 
+	proc5.p_irq[5](signal_proc5_it5); 
+	proc5.p_vci_ini_rw(signal_vci_ini_rw_proc5);
+	proc5.p_vci_ini_c(signal_vci_ini_c_proc5);
+	proc5.p_vci_tgt(signal_vci_tgt_proc5);
+
+	proc6.p_clk(signal_clk);  
+	proc6.p_resetn(signal_resetn);  
+	proc6.p_irq[0](signal_proc6_it0); 
+	proc6.p_irq[1](signal_proc6_it1); 
+	proc6.p_irq[2](signal_proc6_it2); 
+	proc6.p_irq[3](signal_proc6_it3); 
+	proc6.p_irq[4](signal_proc6_it4); 
+	proc6.p_irq[5](signal_proc6_it5); 
+	proc6.p_vci_ini_rw(signal_vci_ini_rw_proc6);
+	proc6.p_vci_ini_c(signal_vci_ini_c_proc6);
+	proc6.p_vci_tgt(signal_vci_tgt_proc6);
+
+	proc7.p_clk(signal_clk);  
+	proc7.p_resetn(signal_resetn);  
+	proc7.p_irq[0](signal_proc7_it0); 
+	proc7.p_irq[1](signal_proc7_it1); 
+	proc7.p_irq[2](signal_proc7_it2); 
+	proc7.p_irq[3](signal_proc7_it3); 
+	proc7.p_irq[4](signal_proc7_it4); 
+	proc7.p_irq[5](signal_proc7_it5); 
+	proc7.p_vci_ini_rw(signal_vci_ini_rw_proc7);
+	proc7.p_vci_ini_c(signal_vci_ini_c_proc7);
+	proc7.p_vci_tgt(signal_vci_tgt_proc7);
+
+	proc8.p_clk(signal_clk);  
+	proc8.p_resetn(signal_resetn);  
+	proc8.p_irq[0](signal_proc8_it0); 
+	proc8.p_irq[1](signal_proc8_it1); 
+	proc8.p_irq[2](signal_proc8_it2); 
+	proc8.p_irq[3](signal_proc8_it3); 
+	proc8.p_irq[4](signal_proc8_it4); 
+	proc8.p_irq[5](signal_proc8_it5); 
+	proc8.p_vci_ini_rw(signal_vci_ini_rw_proc8);
+	proc8.p_vci_ini_c(signal_vci_ini_c_proc8);
+	proc8.p_vci_tgt(signal_vci_tgt_proc8);
+
+	proc9.p_clk(signal_clk);  
+	proc9.p_resetn(signal_resetn);  
+	proc9.p_irq[0](signal_proc9_it0); 
+	proc9.p_irq[1](signal_proc9_it1); 
+	proc9.p_irq[2](signal_proc9_it2); 
+	proc9.p_irq[3](signal_proc9_it3); 
+	proc9.p_irq[4](signal_proc9_it4); 
+	proc9.p_irq[5](signal_proc9_it5); 
+	proc9.p_vci_ini_rw(signal_vci_ini_rw_proc9);
+	proc9.p_vci_ini_c(signal_vci_ini_c_proc9);
+	proc9.p_vci_tgt(signal_vci_tgt_proc9);
+
+	proc10.p_clk(signal_clk);  
+	proc10.p_resetn(signal_resetn);  
+	proc10.p_irq[0](signal_proc10_it0); 
+	proc10.p_irq[1](signal_proc10_it1); 
+	proc10.p_irq[2](signal_proc10_it2); 
+	proc10.p_irq[3](signal_proc10_it3); 
+	proc10.p_irq[4](signal_proc10_it4); 
+	proc10.p_irq[5](signal_proc10_it5); 
+	proc10.p_vci_ini_rw(signal_vci_ini_rw_proc10);
+	proc10.p_vci_ini_c(signal_vci_ini_c_proc10);
+	proc10.p_vci_tgt(signal_vci_tgt_proc10);
+
+	proc11.p_clk(signal_clk);  
+	proc11.p_resetn(signal_resetn);  
+	proc11.p_irq[0](signal_proc11_it0); 
+	proc11.p_irq[1](signal_proc11_it1); 
+	proc11.p_irq[2](signal_proc11_it2); 
+	proc11.p_irq[3](signal_proc11_it3); 
+	proc11.p_irq[4](signal_proc11_it4); 
+	proc11.p_irq[5](signal_proc11_it5); 
+	proc11.p_vci_ini_rw(signal_vci_ini_rw_proc11);
+	proc11.p_vci_ini_c(signal_vci_ini_c_proc11);
+	proc11.p_vci_tgt(signal_vci_tgt_proc11);
+
+	proc12.p_clk(signal_clk);  
+	proc12.p_resetn(signal_resetn);  
+	proc12.p_irq[0](signal_proc12_it0); 
+	proc12.p_irq[1](signal_proc12_it1); 
+	proc12.p_irq[2](signal_proc12_it2); 
+	proc12.p_irq[3](signal_proc12_it3); 
+	proc12.p_irq[4](signal_proc12_it4); 
+	proc12.p_irq[5](signal_proc12_it5); 
+	proc12.p_vci_ini_rw(signal_vci_ini_rw_proc12);
+	proc12.p_vci_ini_c(signal_vci_ini_c_proc12);
+	proc12.p_vci_tgt(signal_vci_tgt_proc12);
+
+	proc13.p_clk(signal_clk);  
+	proc13.p_resetn(signal_resetn);  
+	proc13.p_irq[0](signal_proc13_it0); 
+	proc13.p_irq[1](signal_proc13_it1); 
+	proc13.p_irq[2](signal_proc13_it2); 
+	proc13.p_irq[3](signal_proc13_it3); 
+	proc13.p_irq[4](signal_proc13_it4); 
+	proc13.p_irq[5](signal_proc13_it5); 
+	proc13.p_vci_ini_rw(signal_vci_ini_rw_proc13);
+	proc13.p_vci_ini_c(signal_vci_ini_c_proc13);
+	proc13.p_vci_tgt(signal_vci_tgt_proc13);
+
+	proc14.p_clk(signal_clk);  
+	proc14.p_resetn(signal_resetn);  
+	proc14.p_irq[0](signal_proc14_it0); 
+	proc14.p_irq[1](signal_proc14_it1); 
+	proc14.p_irq[2](signal_proc14_it2); 
+	proc14.p_irq[3](signal_proc14_it3); 
+	proc14.p_irq[4](signal_proc14_it4); 
+	proc14.p_irq[5](signal_proc14_it5); 
+	proc14.p_vci_ini_rw(signal_vci_ini_rw_proc14);
+	proc14.p_vci_ini_c(signal_vci_ini_c_proc14);
+	proc14.p_vci_tgt(signal_vci_tgt_proc14);
+
+	proc15.p_clk(signal_clk);  
+	proc15.p_resetn(signal_resetn);  
+	proc15.p_irq[0](signal_proc15_it0); 
+	proc15.p_irq[1](signal_proc15_it1); 
+	proc15.p_irq[2](signal_proc15_it2); 
+	proc15.p_irq[3](signal_proc15_it3); 
+	proc15.p_irq[4](signal_proc15_it4); 
+	proc15.p_irq[5](signal_proc15_it5); 
+	proc15.p_vci_ini_rw(signal_vci_ini_rw_proc15);
+	proc15.p_vci_ini_c(signal_vci_ini_c_proc15);
+	proc15.p_vci_tgt(signal_vci_tgt_proc15);
+
+	tty.p_clk(signal_clk);
+	tty.p_resetn(signal_resetn);
+	tty.p_vci(signal_vci_tgt_tty);
+	tty.p_irq[0](signal_tty_irq0);
+	tty.p_irq[1](signal_tty_irq1);
+	tty.p_irq[2](signal_tty_irq2);
+	tty.p_irq[3](signal_tty_irq3);
+	tty.p_irq[4](signal_tty_irq4);
+	tty.p_irq[5](signal_tty_irq5);
+	tty.p_irq[6](signal_tty_irq6);
+	tty.p_irq[7](signal_tty_irq7); 
+	tty.p_irq[8](signal_tty_irq8);
+	tty.p_irq[9](signal_tty_irq9);
+	tty.p_irq[10](signal_tty_irq10);
+	tty.p_irq[11](signal_tty_irq11); 
+	tty.p_irq[12](signal_tty_irq12);
+	tty.p_irq[13](signal_tty_irq13);
+	tty.p_irq[14](signal_tty_irq14);
+	tty.p_irq[15](signal_tty_irq15);  
+
+	memc0.p_clk(signal_clk);
+	memc0.p_resetn(signal_resetn);
+	memc0.p_vci_tgt(signal_vci_tgt_memc0);
+	memc0.p_vci_tgt_cleanup(signal_vci_tgt_cleanup_memc0);
+	memc0.p_vci_ini(signal_vci_ini_memc0);
+	memc0.p_vci_ixr(signal_vci_ixr_memc0);
+
+	memc1.p_clk(signal_clk);
+	memc1.p_resetn(signal_resetn);
+	memc1.p_vci_tgt(signal_vci_tgt_memc1);
+	memc1.p_vci_tgt_cleanup(signal_vci_tgt_cleanup_memc1);
+	memc1.p_vci_ini(signal_vci_ini_memc1);
+	memc1.p_vci_ixr(signal_vci_ixr_memc1);
+
+	memc2.p_clk(signal_clk);
+	memc2.p_resetn(signal_resetn);
+	memc2.p_vci_tgt(signal_vci_tgt_memc2);
+	memc2.p_vci_tgt_cleanup(signal_vci_tgt_cleanup_memc2);
+	memc2.p_vci_ini(signal_vci_ini_memc2);
+	memc2.p_vci_ixr(signal_vci_ixr_memc2);
+
+	memc3.p_clk(signal_clk);
+	memc3.p_resetn(signal_resetn);
+	memc3.p_vci_tgt(signal_vci_tgt_memc3);
+	memc3.p_vci_tgt_cleanup(signal_vci_tgt_cleanup_memc3);
+	memc3.p_vci_ini(signal_vci_ini_memc3);
+	memc3.p_vci_ixr(signal_vci_ixr_memc3);
+
+
+	xram.p_clk(signal_clk);
+        xram.p_resetn(signal_resetn);
+	xram.p_vci(signal_vci_tgt_xram);	
+
+	///////////////////////////////////////////////////////
+	// Réseau vers la XRAM
+	///////////////////////////////////////////////////////
+
+	xring.p_clk(signal_clk);
+	xring.p_resetn(signal_resetn);
+
+	xring.p_to_initiator[0](signal_vci_ixr_memc0);
+	xring.p_to_initiator[1](signal_vci_ixr_memc1);
+	xring.p_to_initiator[2](signal_vci_ixr_memc2);
+	xring.p_to_initiator[3](signal_vci_ixr_memc3);
+
+	xring.p_to_target[0](signal_vci_tgt_xram);
+
+	///////////////////////////////////////////////////////
+	// Routers connections
+	///////////////////////////////////////////////////////
+
+	for ( size_t x = 0 ; x < X_MAX ; x++ )
+	{
+	    for ( size_t y = 0 ; y < Y_MAX ; y++ )
+	    {
+	        // cmd DSPIN router
+	        cmdrouter[cluster(x,y)].p_clk			(signal_clk);
+	        cmdrouter[cluster(x,y)].p_resetn		(signal_resetn);
+	        cmdrouter[cluster(x,y)].p_out[0][LOCAL]		(signal_dspin_cmd_g2l_d[x][y]);
+	        cmdrouter[cluster(x,y)].p_out[1][LOCAL]		(signal_dspin_cmd_g2l_c[x][y]);
+	        cmdrouter[cluster(x,y)].p_in[0][LOCAL]		(signal_dspin_cmd_l2g_d[x][y]);
+	        cmdrouter[cluster(x,y)].p_in[1][LOCAL]		(signal_dspin_cmd_l2g_c[x][y]);
+	
+	        // rsp DSPIN router
+	        rsprouter[cluster(x,y)].p_clk			(signal_clk);
+	        rsprouter[cluster(x,y)].p_resetn		(signal_resetn);
+	        rsprouter[cluster(x,y)].p_out[0][LOCAL]		(signal_dspin_rsp_g2l_d[x][y]);
+	        rsprouter[cluster(x,y)].p_out[1][LOCAL]		(signal_dspin_rsp_g2l_c[x][y]);
+	        rsprouter[cluster(x,y)].p_in[0][LOCAL]		(signal_dspin_rsp_l2g_d[x][y]);
+	        rsprouter[cluster(x,y)].p_in[1][LOCAL]		(signal_dspin_rsp_l2g_c[x][y]);
+	    }
+	}
+
+	// Inter Clusters horizontal connections
+	for ( size_t x = 0 ; x < (X_MAX-1) ; x++ )
+	{
+	    for ( size_t y = 0 ; y < Y_MAX ; y++ )
+	    {
+	        for ( size_t k = 0 ; k < 2 ; k++ )
+	        {
+	            cmdrouter[cluster(x,y)].p_out[k][EAST]		(signal_dspin_h_cmd_inc[x][y][k]);		
+	            cmdrouter[cluster((x+1),y)].p_in[k][WEST]	(signal_dspin_h_cmd_inc[x][y][k]);
+	
+	            cmdrouter[cluster(x,y)].p_in[k][EAST]		(signal_dspin_h_cmd_dec[x][y][k]);		
+	            cmdrouter[cluster((x+1),y)].p_out[k][WEST]	(signal_dspin_h_cmd_dec[x][y][k]);
+	
+	            rsprouter[cluster(x,y)].p_out[k][EAST]		(signal_dspin_h_rsp_inc[x][y][k]);		
+	            rsprouter[cluster((x+1),y)].p_in[k][WEST]	(signal_dspin_h_rsp_inc[x][y][k]);
+	
+	            rsprouter[cluster(x,y)].p_in[k][EAST]		(signal_dspin_h_rsp_dec[x][y][k]);		
+	            rsprouter[cluster((x+1),y)].p_out[k][WEST]	(signal_dspin_h_rsp_dec[x][y][k]);
+	       } 
+	    }
+	}
+	
+//	std::cout << "returned after inter cluster are horizontally connected" << std::endl;
+	
+	// East & West boundary clusters connections
+	
+	for ( size_t y = 0 ; y < Y_MAX ; y++ )
+	{
+	    for ( size_t k = 0 ; k < 2 ; k++ )
+	    {
+	            cmdrouter[cluster(0,y)].p_in[k][WEST]           (signal_dspin_false_cmd_in[cluster(0,y)][k][0]);
+	            cmdrouter[cluster(0,y)].p_out[k][WEST]          (signal_dspin_false_cmd_out[cluster(0,y)][k][0]);
+	            rsprouter[cluster(0,y)].p_in[k][WEST]           (signal_dspin_false_rsp_in[cluster(0,y)][k][0]);
+	            rsprouter[cluster(0,y)].p_out[k][WEST]          (signal_dspin_false_rsp_out[cluster(0,y)][k][0]);
+	
+	            cmdrouter[cluster((X_MAX-1),y)].p_in[k][EAST]     (signal_dspin_false_cmd_in[cluster((X_MAX-1),y)][k][0]);
+	            cmdrouter[cluster((X_MAX-1),y)].p_out[k][EAST]    (signal_dspin_false_cmd_out[cluster((X_MAX-1),y)][k][0]);
+	            rsprouter[cluster((X_MAX-1),y)].p_in[k][EAST]     (signal_dspin_false_rsp_in[cluster((X_MAX-1),y)][k][0]);
+	            rsprouter[cluster((X_MAX-1),y)].p_out[k][EAST]    (signal_dspin_false_rsp_out[cluster((X_MAX-1),y)][k][0]);
+	    }
+	 }
+	
+//	std::cout << "returned after boundary clusters are horizontally connected" << std::endl;
+	
+	// Inter Clusters vertical connections
+	for ( size_t y = 0 ; y < (Y_MAX-1) ; y++ )
+	{
+	    for ( size_t x = 0 ; x < X_MAX ; x++ )
+	    {
+	        for ( size_t k = 0 ; k < 2 ; k++ )
+	        {
+	            cmdrouter[cluster(x,y)].p_out[k][NORTH]		(signal_dspin_v_cmd_inc[x][y][k]);		
+	            cmdrouter[cluster(x,(y+1))].p_in[k][SOUTH]	(signal_dspin_v_cmd_inc[x][y][k]);
+	
+	            cmdrouter[cluster(x,y)].p_in[k][NORTH]		(signal_dspin_v_cmd_dec[x][y][k]);		
+	            cmdrouter[cluster(x,(y+1))].p_out[k][SOUTH]	(signal_dspin_v_cmd_dec[x][y][k]);
+	
+	            rsprouter[cluster(x,y)].p_out[k][NORTH]		(signal_dspin_v_rsp_inc[x][y][k]);		
+	            rsprouter[cluster(x,(y+1))].p_in[k][SOUTH]	(signal_dspin_v_rsp_inc[x][y][k]);
+	
+	            rsprouter[cluster(x,y)].p_in[k][NORTH]		(signal_dspin_v_rsp_dec[x][y][k]);		
+	            rsprouter[cluster(x,(y+1))].p_out[k][SOUTH]	(signal_dspin_v_rsp_dec[x][y][k]);
+	        }
+	    }
+	}
+	
+	// North & South boundary clusters connections
+	
+	for ( size_t x = 0 ; x < X_MAX ; x++ )
+	{
+	    for ( size_t k = 0 ; k < 2 ; k++ )
+	    {
+	            cmdrouter[cluster(x,0)].p_in[k][SOUTH]          (signal_dspin_false_cmd_in[cluster(x,0)][k][1]);
+	            cmdrouter[cluster(x,0)].p_out[k][SOUTH]         (signal_dspin_false_cmd_out[cluster(x,0)][k][1]);
+	            rsprouter[cluster(x,0)].p_in[k][SOUTH]          (signal_dspin_false_rsp_in[cluster(x,0)][k][1]);
+	            rsprouter[cluster(x,0)].p_out[k][SOUTH]         (signal_dspin_false_rsp_out[cluster(x,0)][k][1]);
+	
+	            cmdrouter[cluster(x,(Y_MAX-1))].p_out[k][NORTH]   (signal_dspin_false_cmd_out[cluster(x,(Y_MAX-1))][k][1]);
+         	    cmdrouter[cluster(x,(Y_MAX-1))].p_in[k][NORTH]    (signal_dspin_false_cmd_in[cluster(x,(Y_MAX-1))][k][1]);
+	            rsprouter[cluster(x,(Y_MAX-1))].p_out[k][NORTH]   (signal_dspin_false_rsp_out[cluster(x,(Y_MAX-1))][k][1]);
+	            rsprouter[cluster(x,(Y_MAX-1))].p_in[k][NORTH]    (signal_dspin_false_rsp_in[cluster(x,(Y_MAX-1))][k][1]);
+	    }
+	}
+	
+//	std::cout << "returned after boundary clusters are vertically connected" << std::endl;
+
+	///////////////////////////////////////////////////////
+	// Réseau des commandes primaires
+	///////////////////////////////////////////////////////
+
+	clusterPN0.p_clk(signal_clk);
+	clusterPN0.p_resetn(signal_resetn);
+
+	clusterPN0.p_to_initiator[0](signal_vci_ini_rw_proc0);
+	clusterPN0.p_to_initiator[1](signal_vci_ini_rw_proc1);
+	clusterPN0.p_to_initiator[2](signal_vci_ini_rw_proc2);
+	clusterPN0.p_to_initiator[3](signal_vci_ini_rw_proc3);
+
+	clusterPN0.p_to_target[0](signal_vci_tgt_memc0);
+
+        clusterPN0.p_gate_cmd_out(signal_dspin_cmd_l2g_d[0][0]);
+	clusterPN0.p_gate_rsp_in(signal_dspin_rsp_g2l_d[0][0]);
+        clusterPN0.p_gate_cmd_in(signal_dspin_cmd_g2l_d[0][0]);
+	clusterPN0.p_gate_rsp_out(signal_dspin_rsp_l2g_d[0][0]);
+
+	clusterPN1.p_clk(signal_clk);
+	clusterPN1.p_resetn(signal_resetn);
+
+	clusterPN1.p_to_initiator[0](signal_vci_ini_rw_proc4);
+	clusterPN1.p_to_initiator[1](signal_vci_ini_rw_proc5);
+	clusterPN1.p_to_initiator[2](signal_vci_ini_rw_proc6);
+	clusterPN1.p_to_initiator[3](signal_vci_ini_rw_proc7);
+
+	clusterPN1.p_to_target[0](signal_vci_tgt_memc1);
+
+        clusterPN1.p_gate_cmd_out(signal_dspin_cmd_l2g_d[0][1]);
+	clusterPN1.p_gate_rsp_in(signal_dspin_rsp_g2l_d[0][1]);
+        clusterPN1.p_gate_cmd_in(signal_dspin_cmd_g2l_d[0][1]);
+	clusterPN1.p_gate_rsp_out(signal_dspin_rsp_l2g_d[0][1]);
+
+	clusterPN2.p_clk(signal_clk);
+	clusterPN2.p_resetn(signal_resetn);
+
+	clusterPN2.p_to_initiator[0](signal_vci_ini_rw_proc8);
+	clusterPN2.p_to_initiator[1](signal_vci_ini_rw_proc9);
+	clusterPN2.p_to_initiator[2](signal_vci_ini_rw_proc10);
+	clusterPN2.p_to_initiator[3](signal_vci_ini_rw_proc11);
+	
+	clusterPN2.p_to_target[0](signal_vci_tgt_memc2);
+
+        clusterPN2.p_gate_cmd_out(signal_dspin_cmd_l2g_d[1][0]);
+	clusterPN2.p_gate_rsp_in(signal_dspin_rsp_g2l_d[1][0]);
+        clusterPN2.p_gate_cmd_in(signal_dspin_cmd_g2l_d[1][0]);
+	clusterPN2.p_gate_rsp_out(signal_dspin_rsp_l2g_d[1][0]);
+
+	clusterPN3.p_clk(signal_clk);
+	clusterPN3.p_resetn(signal_resetn);
+
+	clusterPN3.p_to_initiator[0](signal_vci_ini_rw_proc12);
+	clusterPN3.p_to_initiator[1](signal_vci_ini_rw_proc13);
+	clusterPN3.p_to_initiator[2](signal_vci_ini_rw_proc14);
+	clusterPN3.p_to_initiator[3](signal_vci_ini_rw_proc15);
+
+	clusterPN3.p_to_target[0](signal_vci_tgt_memc3);
+	clusterPN3.p_to_target[1](signal_vci_tgt_tty);
+
+        clusterPN3.p_gate_cmd_out(signal_dspin_cmd_l2g_d[1][1]);
+	clusterPN3.p_gate_rsp_in(signal_dspin_rsp_g2l_d[1][1]);
+        clusterPN3.p_gate_cmd_in(signal_dspin_cmd_g2l_d[1][1]);
+	clusterPN3.p_gate_rsp_out(signal_dspin_rsp_l2g_d[1][1]);
+
+//	std::cout << "returned after clusterPN3 connected" << std::endl;
+	
+	///////////////////////////////////////////////////////
+	// Réseau des commandes de cohérence
+	///////////////////////////////////////////////////////
+	clusterCN0.p_clk(signal_clk);
+	clusterCN0.p_resetn(signal_resetn);
+
+	clusterCN0.p_to_initiator[4](signal_vci_ini_memc0);
+	clusterCN0.p_to_initiator[0](signal_vci_ini_c_proc0);
+	clusterCN0.p_to_initiator[1](signal_vci_ini_c_proc1);
+	clusterCN0.p_to_initiator[2](signal_vci_ini_c_proc2);
+	clusterCN0.p_to_initiator[3](signal_vci_ini_c_proc3);
+
+	clusterCN0.p_to_target[0](signal_vci_tgt_proc0);
+	clusterCN0.p_to_target[1](signal_vci_tgt_proc1);
+	clusterCN0.p_to_target[2](signal_vci_tgt_proc2);
+	clusterCN0.p_to_target[3](signal_vci_tgt_proc3);
+	clusterCN0.p_to_target[4](signal_vci_tgt_cleanup_memc0);
+
+        clusterCN0.p_gate_cmd_out(signal_dspin_cmd_l2g_c[0][0]);
+	clusterCN0.p_gate_rsp_in(signal_dspin_rsp_g2l_c[0][0]);
+        clusterCN0.p_gate_cmd_in(signal_dspin_cmd_g2l_c[0][0]);
+	clusterCN0.p_gate_rsp_out(signal_dspin_rsp_l2g_c[0][0]);
+
+	clusterCN1.p_clk(signal_clk);
+	clusterCN1.p_resetn(signal_resetn);
+
+        clusterCN1.p_to_initiator[4](signal_vci_ini_memc1);
+	clusterCN1.p_to_initiator[0](signal_vci_ini_c_proc4);
+	clusterCN1.p_to_initiator[1](signal_vci_ini_c_proc5);
+	clusterCN1.p_to_initiator[2](signal_vci_ini_c_proc6);
+	clusterCN1.p_to_initiator[3](signal_vci_ini_c_proc7);
+
+	clusterCN1.p_to_target[0](signal_vci_tgt_proc4);
+	clusterCN1.p_to_target[1](signal_vci_tgt_proc5);
+	clusterCN1.p_to_target[2](signal_vci_tgt_proc6);
+	clusterCN1.p_to_target[3](signal_vci_tgt_proc7);
+	clusterCN1.p_to_target[4](signal_vci_tgt_cleanup_memc1);
+
+        clusterCN1.p_gate_cmd_out(signal_dspin_cmd_l2g_c[0][1]);
+	clusterCN1.p_gate_rsp_in(signal_dspin_rsp_g2l_c[0][1]);
+        clusterCN1.p_gate_cmd_in(signal_dspin_cmd_g2l_c[0][1]);
+	clusterCN1.p_gate_rsp_out(signal_dspin_rsp_l2g_c[0][1]);
+
+	clusterCN2.p_clk(signal_clk);
+	clusterCN2.p_resetn(signal_resetn);
+
+	clusterCN2.p_to_initiator[4](signal_vci_ini_memc2);
+	clusterCN2.p_to_initiator[0](signal_vci_ini_c_proc8);
+	clusterCN2.p_to_initiator[1](signal_vci_ini_c_proc9);
+	clusterCN2.p_to_initiator[2](signal_vci_ini_c_proc10);
+	clusterCN2.p_to_initiator[3](signal_vci_ini_c_proc11);
+
+	clusterCN2.p_to_target[0](signal_vci_tgt_proc8);
+	clusterCN2.p_to_target[1](signal_vci_tgt_proc9);
+	clusterCN2.p_to_target[2](signal_vci_tgt_proc10);
+	clusterCN2.p_to_target[3](signal_vci_tgt_proc11);
+        clusterCN2.p_to_target[4](signal_vci_tgt_cleanup_memc2);
+
+        clusterCN2.p_gate_cmd_out(signal_dspin_cmd_l2g_c[1][0]);
+	clusterCN2.p_gate_rsp_in(signal_dspin_rsp_g2l_c[1][0]);
+        clusterCN2.p_gate_cmd_in(signal_dspin_cmd_g2l_c[1][0]);
+	clusterCN2.p_gate_rsp_out(signal_dspin_rsp_l2g_c[1][0]);
+
+	clusterCN3.p_clk(signal_clk);
+	clusterCN3.p_resetn(signal_resetn);
+
+	clusterCN3.p_to_initiator[4](signal_vci_ini_memc3);
+	clusterCN3.p_to_initiator[0](signal_vci_ini_c_proc12);
+	clusterCN3.p_to_initiator[1](signal_vci_ini_c_proc13);
+	clusterCN3.p_to_initiator[2](signal_vci_ini_c_proc14);
+	clusterCN3.p_to_initiator[3](signal_vci_ini_c_proc15);
+
+	clusterCN3.p_to_target[0](signal_vci_tgt_proc12);
+	clusterCN3.p_to_target[1](signal_vci_tgt_proc13);
+	clusterCN3.p_to_target[2](signal_vci_tgt_proc14);
+	clusterCN3.p_to_target[3](signal_vci_tgt_proc15);
+	clusterCN3.p_to_target[4](signal_vci_tgt_cleanup_memc3);
+
+        clusterCN3.p_gate_cmd_out(signal_dspin_cmd_l2g_c[1][1]);
+	clusterCN3.p_gate_rsp_in(signal_dspin_rsp_g2l_c[1][1]);
+        clusterCN3.p_gate_cmd_in(signal_dspin_cmd_g2l_c[1][1]);
+	clusterCN3.p_gate_rsp_out(signal_dspin_rsp_l2g_c[1][1]);
+
+
+	////////////////////////////////////////////////////////
+	////////////////////////////////////////////////////////
+
+	int ncycles;
+
+#ifndef SOCVIEW
+	if (argc == 2) {
+		ncycles = std::atoi(argv[1]);
+	} else {
+		std::cerr
+			<< std::endl
+			<< "The number of simulation cycles must "
+			   "be defined in the command line"
+			<< std::endl;
+		exit(1);
+	}
+
+	sc_start(sc_core::sc_time(0, SC_NS));
+	signal_resetn = false;
+
+	for(size_t t = 0; t < X_MAX*Y_MAX; t++)
+	{
+	    for (size_t k = 0; k < 2; k++)
+	    {
+	        for(size_t a = 0; a < 2; a ++)
+	        {
+			signal_dspin_false_cmd_in[t][k][a].write = false;
+			signal_dspin_false_cmd_in[t][k][a].read = true;
+			signal_dspin_false_cmd_out[t][k][a].write = false;
+			signal_dspin_false_cmd_out[t][k][a].read = true;
+	
+			signal_dspin_false_rsp_in[t][k][a].write = false;
+			signal_dspin_false_rsp_in[t][k][a].read = true;
+			signal_dspin_false_rsp_out[t][k][a].write = false;
+			signal_dspin_false_rsp_out[t][k][a].read = true;
+	       }
+	    }
+	}
+
+
+	sc_start(sc_core::sc_time(1, SC_NS));
+	signal_resetn = true;
+
+	for (int i = 0; i < ncycles ; i+=1) {
+		sc_start(sc_core::sc_time(1, SC_NS));
+	       //std::cout << " +++++++++ cycle : " << std::dec << i << std::endl;
+               //cmdrouter[0].printTrace(1);   // channel 0 : Direct, channel 1 : Coherence
+               //cmdrouter[1].printTrace(1); 		
+               //cmdrouter[2].printTrace(1); 		
+               //cmdrouter[3].printTrace(1); 		
+	}
+
+        std::cout << "Hit ENTER to end simulation" << std::endl;
+        char buf[1];
+
+	std::cin.getline(buf,1);
+	return EXIT_SUCCESS;
+#else
+	ncycles = 1;
+	sc_start(sc_core::sc_time(0, SC_NS));
+	signal_resetn = false;
+	sc_start(sc_core::sc_time(1, SC_NS));
+	signal_resetn = true;
+
+	debug();
+	return EXIT_SUCCESS;
+#endif
+}
+
+int sc_main (int argc, char *argv[])
+{
+	try {
+		return _main(argc, argv);
+	} catch (std::exception &e) {
+		std::cout << e.what() << std::endl;
+	} catch (...) {
+		std::cout << "Unknown exception occured" << std::endl;
+		throw;
+	}
+	return 1;
+}
+
Index: branches/v4/platforms/caba-ring-ccxcachev1_memcachev1-mipsel/Makefile
===================================================================
--- branches/v4/platforms/caba-ring-ccxcachev1_memcachev1-mipsel/Makefile	(revision 371)
+++ branches/v4/platforms/caba-ring-ccxcachev1_memcachev1-mipsel/Makefile	(revision 371)
@@ -0,0 +1,6 @@
+ARCH=mips32el
+SIMULATION_ARGS=100000
+SOCLIB_CC_ADD_ARGS=-I. -t systemcass
+SOCLIB?=$(shell soclib-cc --getpath)
+export SOCLIB
+include $(SOCLIB)/soclib/platform/topcells/all.mk
Index: branches/v4/platforms/caba-ring-ccxcachev1_memcachev1-mipsel/platform_desc
===================================================================
--- branches/v4/platforms/caba-ring-ccxcachev1_memcachev1-mipsel/platform_desc	(revision 371)
+++ branches/v4/platforms/caba-ring-ccxcachev1_memcachev1-mipsel/platform_desc	(revision 371)
@@ -0,0 +1,27 @@
+
+# -*- python -*-
+
+
+todo = Platform('caba', 'top.cpp',
+				uses = [
+	Uses('caba:vci_cc_xcache_wrapper_v1', iss_t = 'common:iss2_simhelper', simhelper_iss_t = 'common:mips32el'),
+	Uses('caba:vci_simple_ram'),
+        Uses('caba:vci_logger'),
+	Uses('caba:vci_multi_tty'),
+        Uses('caba:vci_simple_ring_fast',
+        ring_cmd_data_size = 40,
+        ring_rsp_data_size = 33),
+	Uses('caba:vci_mem_cache_v1'),
+	Uses('common:elf_file_loader'),
+	],
+	cell_size = 4,
+	plen_size = 8,
+	addr_size = 32,
+	rerror_size = 1,
+	clen_size = 1,
+	rflag_size = 1,
+	srcid_size = 8,
+	pktid_size = 4,
+	trdid_size = 4,
+	wrplen_size = 1
+)
Index: branches/v4/platforms/caba-ring-ccxcachev1_memcachev1-mipsel/segmentation.h
===================================================================
--- branches/v4/platforms/caba-ring-ccxcachev1_memcachev1-mipsel/segmentation.h	(revision 371)
+++ branches/v4/platforms/caba-ring-ccxcachev1_memcachev1-mipsel/segmentation.h	(revision 371)
@@ -0,0 +1,72 @@
+
+/////////////////////////////////////////////////////////////////
+//	ADDRESS SPACE SEGMENTATION
+//
+//	This file must be included in the system.cpp file, 
+//	for harware configuration : It is used to build
+//	the SOCLIB_SEGMENT_TABLE.
+//
+//	This file can also be used by the ldscript generator,
+//	for embedded software generation.
+//	
+//	It gives the system integrator the garanty
+//	that hardware and software have the same
+//	description of the address space segmentation.
+/////////////////////////////////////////////////////////////////
+
+/////////////////////////////////////////////////////////////////
+//	reset, and exception segments
+//      base address required by MIPS processor
+/////////////////////////////////////////////////////////////////
+//#define MMU
+
+#define	RESET_BASE	0xBFC00000
+#define	RESET_SIZE	0x00001000
+
+#define	EXCEP_BASE	0x80000000
+#define	EXCEP_SIZE	0x00001000
+
+#define	TEXT_BASE	0x00400000
+#define	TEXT_SIZE	0x00100000
+/////////////////////////////////////////////////////////////////
+//	global data segment (initialised)
+/////////////////////////////////////////////////////////////////
+
+#define MC_M_BASE	0x10000000
+#define MC_M_SIZE	0x00100000
+
+//////////////////////////////////////////////////////////
+//	System devices
+///////////////////////////////////////////////////////////
+
+#define	TTY_BASE	0xC0200000
+#define	TTY_SIZE	0x00010000
+
+#define	TIMER_BASE	0xD0200000
+#define	TIMER_SIZE	0x00000100
+
+#define	LOCKS_BASE	0xE0200000
+#define	LOCKS_SIZE	0x00000100
+
+#define C_PROC0_BASE	0x01200000
+#define C_PROC0_SIZE	0x00000010
+
+#define C_PROC1_BASE	0x02200000
+#define C_PROC1_SIZE	0x00000010
+
+#define C_PROC2_BASE	0x03200000
+#define C_PROC2_SIZE	0x00000010
+
+#define C_PROC3_BASE	0x04200000
+#define C_PROC3_SIZE	0x00000010
+
+#define C_MC_M_BASE	0x00200000
+#define C_MC_M_SIZE	0x00000008
+
+#define XRAM_BASE	0xB0200000
+#define XRAM_SIZE	0x00000008
+
+#define MC_R_BASE	0x20200000
+#define MC_R_SIZE	0x00000008
+
+#define CLEANUP_OFFSET  0x20200000
Index: branches/v4/platforms/caba-ring-ccxcachev1_memcachev1-mipsel/soft/Makefile
===================================================================
--- branches/v4/platforms/caba-ring-ccxcachev1_memcachev1-mipsel/soft/Makefile	(revision 371)
+++ branches/v4/platforms/caba-ring-ccxcachev1_memcachev1-mipsel/soft/Makefile	(revision 371)
@@ -0,0 +1,4 @@
+ADD_OBJS=stdlib.o stdio.o exception.o system.o
+SOCLIB?=$(shell soclib-cc --getpath)
+export SOCLIB
+include $(SOCLIB)/soclib/platform/topcells/soft.mk
Index: branches/v4/platforms/caba-ring-ccxcachev1_memcachev1-mipsel/soft/main.c
===================================================================
--- branches/v4/platforms/caba-ring-ccxcachev1_memcachev1-mipsel/soft/main.c	(revision 371)
+++ branches/v4/platforms/caba-ring-ccxcachev1_memcachev1-mipsel/soft/main.c	(revision 371)
@@ -0,0 +1,114 @@
+#include "system.h"
+#include "stdio.h"
+#include "stdlib.h"
+//#include "matrice.h"
+
+#include "../segmentation.h"
+
+#define NPROCS 4
+#define SIZE 50 
+#define SORT_TYPE 0 // shellSort
+
+volatile int nprocs=NPROCS;
+
+
+unsigned int gQSortNum0[200] = {
+  251,  24, 113, 170, 215,  60,  83,  30, 115,  48, 169, 210,  49,  92, 101,  58,  21, 184, 225,   6,
+  199, 244, 227, 146,  99,  96,  25, 222,  65, 140, 213,  22, 219, 136, 175, 182,  73,  36, 141, 190, 
+   83, 112, 137, 114, 175, 188, 187, 102,  53, 168, 193, 154, 167, 172,   3, 242,  67,  64, 144, 137,
+  142, 175, 188,  69, 102,  53, 168, 193, 102,  89, 172, 253, 242,  67, 192,   7,  62, 159,  20, 181,
+  182, 187, 216, 207,  22, 105, 132, 109, 162, 205,  16, 151,  18, 113, 228,  37,   6,  85,   8, 161,
+   58, 135,  76,  35, 174,  35, 224,  39, 158, 127, 180, 149,  86, 155, 200, 239, 118, 119,  28,  77,
+  254,  19, 176, 183,  78, 145, 132,   5,  90, 117, 152, 127, 218, 153,  20,  67, 178,   3, 128, 185,
+  254,  95, 172, 139, 246, 123, 104,  15,  42, 169,  68, 211,  98, 243,  80,  41, 174,  79,  36,  27,
+  186, 149,  86, 155, 200, 239, 118, 119,  28,  77, 254,  19, 176, 183,  78, 145, 132,   5,  90, 117,
+  152, 127, 218, 153,  20,  67, 178,   3, 128, 185, 254,  95, 172, 139, 246, 123, 104,  15,  42, 169 };
+
+
+unsigned int SortArr0[NPROCS*(SIZE+50)];
+
+void shellSortPhase(unsigned int a[],unsigned int length, int gap);
+void shellSort(unsigned int *base, unsigned int n);     // type 0
+
+int main()
+{
+  register int p; 
+
+  p=procnum();
+
+  puts("Hello from processor ");
+  putchar(p+'0');
+  putchar('\n');
+
+  int i;
+  int j;
+  unsigned int* SortArray;
+
+  if(p+1 <= nprocs)
+  {
+        i=1;
+  	puts("Memory copy \n");
+        SortArray = SortArr0 + p*(SIZE+50);
+//	memcpy(SortArray, gQSortNum0 + p*SIZE,SIZE*4);
+	memcpy(SortArray, gQSortNum0,SIZE*4);
+
+ 	puts("Sort... \n");
+        shellSort((unsigned int *) (SortArray), (unsigned int) SIZE);
+
+  	for (j = 1; j < SIZE; j++)
+    	{
+	  if (SortArray[j] < SortArray[j-1])
+		{
+	  		puts("ucbqsort: failed\n");
+			while(1);
+		}
+
+    	}
+
+  	puts("ucbqsort: success\n");
+  }
+
+  while(1);
+}
+
+//------------------------------------------------------
+/*
+ * Exécute un tri par insertion avec la séparation donnée
+ * If gap == 1, on fait un tri ordinaire.
+ * If gap >= length, on ne fait rien.
+ */
+void shellSortPhase(unsigned int a[],unsigned int length, int gap) {
+    int i;
+ 
+    puti(gap);
+    for (i = gap; i < length; ++i) {
+        unsigned int value = a[i];
+        int j;
+        for (j = i - gap; j >= 0 && a[j] > value; j -= gap) {
+	    putchar('+');
+            a[j + gap] = a[j];
+	    putchar('-');
+        }
+        a[j + gap] = value;
+    }
+}
+ 
+void shellSort(unsigned int *base, unsigned int n) {
+    /*
+     * gaps[] doit approximer une Série géométrique.
+     * La sequence suivante est la meilleure connue en terme
+     * de nombre moyen de comparaisons. voir:
+     * http://www.research.att.com/~njas/sequences/A102549
+     */
+    static const int gaps[] = {
+        1, 4, 10, 23, 57, 132, 301, 701
+    };
+    int sizeIndex;
+ 
+    puts("Shell Sort\n");
+    for (sizeIndex = sizeof(gaps)/sizeof(gaps[0]) - 1;
+               sizeIndex >= 0;
+               --sizeIndex)
+        shellSortPhase(base, n, gaps[sizeIndex]);
+}
+
Index: branches/v4/platforms/caba-ring-ccxcachev1_memcachev1-mipsel/top.cpp
===================================================================
--- branches/v4/platforms/caba-ring-ccxcachev1_memcachev1-mipsel/top.cpp	(revision 371)
+++ branches/v4/platforms/caba-ring-ccxcachev1_memcachev1-mipsel/top.cpp	(revision 371)
@@ -0,0 +1,346 @@
+
+#include <systemc>
+#include <sys/time.h>
+#include <iostream>
+#include <cstdlib>
+#include <cstdarg>
+
+#include "mapping_table.h"
+#include "mips32.h"
+#include "iss2_simhelper.h"
+#include "vci_simple_ram.h"
+#include "vci_multi_tty.h"
+#include "vci_simple_ring_fast.h"
+#include "vci_mem_cache_v1.h"
+#include "vci_cc_xcache_wrapper_v1.h"
+#include "vci_logger.h"
+
+#ifdef USE_GDB_SERVER
+#include "iss/gdbserver.h"
+#endif
+
+#include "segmentation.h"
+
+int _main(int argc, char *argv[])
+{
+	using namespace sc_core;
+	// Avoid repeating these everywhere
+	using soclib::common::IntTab;
+	using soclib::common::Segment;
+
+	// Define VCI parameters
+	typedef soclib::caba::VciParams<4,8,32,1,1,1,8,4,4,1> vci_param;
+	typedef soclib::common::Iss2Simhelper<soclib::common::Mips32ElIss> proc_iss;
+	// Mapping table
+
+	soclib::common::MappingTable maptabp(32, IntTab(8), IntTab(8), 0x00300000);
+
+	maptabp.add(Segment("reset", RESET_BASE, RESET_SIZE, IntTab(0), true));
+	maptabp.add(Segment("excep", EXCEP_BASE, EXCEP_SIZE, IntTab(0), true));
+	maptabp.add(Segment("text" , TEXT_BASE , TEXT_SIZE , IntTab(0), true));
+	maptabp.add(Segment("tty"  , TTY_BASE  , TTY_SIZE  , IntTab(1), false));
+	maptabp.add(Segment("mc_m" , MC_M_BASE , MC_M_SIZE , IntTab(0), true ));
+ 
+	std::cout << maptabp << std::endl;
+
+        soclib::common::MappingTable maptabc(32, IntTab(8), IntTab(8), 0x00300000);
+	maptabc.add(Segment("c_proc0" , C_PROC0_BASE , C_PROC0_SIZE , IntTab(0), false, true, IntTab(0)));
+	maptabc.add(Segment("c_proc1" , C_PROC1_BASE , C_PROC1_SIZE , IntTab(1), false, true, IntTab(1)));
+	maptabc.add(Segment("c_proc2" , C_PROC2_BASE , C_PROC2_SIZE , IntTab(2), false, true, IntTab(2)));
+	maptabc.add(Segment("c_proc3" , C_PROC3_BASE , C_PROC3_SIZE , IntTab(3), false, true, IntTab(3)));
+	maptabc.add(Segment("mc_m"  , MC_M_BASE , MC_M_SIZE  , IntTab(4), false, false));
+	maptabc.add(Segment("reset", RESET_BASE, RESET_SIZE, IntTab(4), false, false));
+	maptabc.add(Segment("excep", EXCEP_BASE, EXCEP_SIZE, IntTab(4), false, false));
+	maptabc.add(Segment("text" , TEXT_BASE , TEXT_SIZE , IntTab(4), false, false));
+
+	std::cout << maptabc << std::endl;
+	
+	soclib::common::MappingTable maptabx(32, IntTab(8), IntTab(8), 0x00300000);
+	maptabx.add(Segment("xram" , MC_M_BASE , MC_M_SIZE , IntTab(0), false));
+	maptabx.add(Segment("reset", RESET_BASE, RESET_SIZE, IntTab(0), false));
+	maptabx.add(Segment("excep", EXCEP_BASE, EXCEP_SIZE, IntTab(0), false));
+	maptabx.add(Segment("text" , TEXT_BASE , TEXT_SIZE , IntTab(0), false));
+	
+	std::cout << maptabx << std::endl;
+
+	// Signals
+	sc_clock	signal_clk("clk");
+	sc_signal<bool> signal_resetn("resetn");
+   
+	sc_signal<bool> signal_proc0_it0("proc0_it0"); 
+	sc_signal<bool> signal_proc0_it1("proc0_it1"); 
+	sc_signal<bool> signal_proc0_it2("proc0_it2"); 
+	sc_signal<bool> signal_proc0_it3("proc0_it3"); 
+	sc_signal<bool> signal_proc0_it4("proc0_it4"); 
+	sc_signal<bool> signal_proc0_it5("proc0_it5");
+
+	sc_signal<bool> signal_proc1_it0("proc1_it0"); 
+	sc_signal<bool> signal_proc1_it1("proc1_it1"); 
+	sc_signal<bool> signal_proc1_it2("proc1_it2"); 
+	sc_signal<bool> signal_proc1_it3("proc1_it3"); 
+	sc_signal<bool> signal_proc1_it4("proc1_it4"); 
+	sc_signal<bool> signal_proc1_it5("proc1_it5");
+
+	sc_signal<bool> signal_proc2_it0("proc2_it0"); 
+	sc_signal<bool> signal_proc2_it1("proc2_it1"); 
+	sc_signal<bool> signal_proc2_it2("proc2_it2"); 
+	sc_signal<bool> signal_proc2_it3("proc2_it3"); 
+	sc_signal<bool> signal_proc2_it4("proc2_it4"); 
+	sc_signal<bool> signal_proc2_it5("proc2_it5");
+
+	sc_signal<bool> signal_proc3_it0("proc3_it0"); 
+	sc_signal<bool> signal_proc3_it1("proc3_it1"); 
+	sc_signal<bool> signal_proc3_it2("proc3_it2"); 
+	sc_signal<bool> signal_proc3_it3("proc3_it3"); 
+	sc_signal<bool> signal_proc3_it4("proc3_it4"); 
+	sc_signal<bool> signal_proc3_it5("proc3_it5");
+
+	soclib::caba::VciSignals<vci_param> signal_vci_ini_rw_proc0("vci_ini_rw_proc0");
+	soclib::caba::VciSignals<vci_param> signal_vci_ini_c_proc0("vci_ini_c_proc0");
+	soclib::caba::VciSignals<vci_param> signal_vci_tgt_proc0("vci_tgt_proc0");
+
+	soclib::caba::VciSignals<vci_param> signal_vci_ini_rw_proc1("vci_ini_rw_proc1");
+	soclib::caba::VciSignals<vci_param> signal_vci_ini_c_proc1("vci_ini_c_proc1");
+	soclib::caba::VciSignals<vci_param> signal_vci_tgt_proc1("vci_tgt_proc1");
+
+	soclib::caba::VciSignals<vci_param> signal_vci_ini_rw_proc2("vci_ini_rw_proc2");
+	soclib::caba::VciSignals<vci_param> signal_vci_ini_c_proc2("vci_ini_c_proc2");
+	soclib::caba::VciSignals<vci_param> signal_vci_tgt_proc2("vci_tgt_proc2");
+
+	soclib::caba::VciSignals<vci_param> signal_vci_ini_rw_proc3("vci_ini_rw_proc3");
+	soclib::caba::VciSignals<vci_param> signal_vci_ini_c_proc3("vci_ini_c_proc3");
+	soclib::caba::VciSignals<vci_param> signal_vci_tgt_proc3("vci_tgt_proc3");
+
+	soclib::caba::VciSignals<vci_param> signal_vci_tgt_tty("vci_tgt_tty");
+
+	soclib::caba::VciSignals<vci_param> signal_vci_tgt_xram("vci_tgt_xram");
+
+	soclib::caba::VciSignals<vci_param> signal_vci_ixr_memc("vci_ixr_memc");
+	soclib::caba::VciSignals<vci_param> signal_vci_ini_memc("vci_ini_memc");
+	soclib::caba::VciSignals<vci_param> signal_vci_tgt_memc("vci_tgt_memc");
+	soclib::caba::VciSignals<vci_param> signal_vci_tgt_cleanup_memc("vci_tgt_cleanup_memc");
+
+	sc_signal<bool> signal_tty_irq0("signal_tty_irq0"); 
+	sc_signal<bool> signal_tty_irq1("signal_tty_irq1"); 
+	sc_signal<bool> signal_tty_irq2("signal_tty_irq2"); 
+	sc_signal<bool> signal_tty_irq3("signal_tty_irq3"); 
+
+        sc_signal<bool> signal_stuck0("signal_stuck0");
+
+	soclib::common::Loader loader("soft/bin.soft");
+
+        // Components
+	soclib::caba::VciCcXCacheWrapperV1<vci_param, proc_iss > 
+	proc0("proc0", 0, maptabp, maptabc, IntTab(0),IntTab(0),IntTab(0),4,4,16,4,4,16);
+
+	soclib::caba::VciCcXCacheWrapperV1<vci_param, proc_iss > 
+	proc1("proc1", 1, maptabp, maptabc, IntTab(1),IntTab(1),IntTab(1),4,4,16,4,4,16);
+
+	soclib::caba::VciCcXCacheWrapperV1<vci_param, proc_iss > 
+	proc2("proc2", 2, maptabp, maptabc, IntTab(2),IntTab(2),IntTab(2),4,4,16,4,4,16);
+
+	soclib::caba::VciCcXCacheWrapperV1<vci_param, proc_iss > 
+	proc3("proc3", 3, maptabp, maptabc, IntTab(3),IntTab(3),IntTab(3),4,4,16,4,4,16);
+
+	soclib::caba::VciSimpleRam<vci_param> 
+	xram("xram", IntTab(0), maptabx, loader);
+
+	soclib::caba::VciMemCacheV1<vci_param> 
+	memc("memc",maptabp,maptabc,maptabx,IntTab(0),IntTab(4),IntTab(0), IntTab(4),16,16,16);
+	
+	soclib::caba::VciMultiTty<vci_param> 
+	tty("tty",IntTab(1),maptabp,"tty0","tty1","tty2","tty3",NULL);
+
+//      soclib::caba::VciLogger<vci_param> vci_logger_proc0("vci_logger_proc0",maptabp);
+//      soclib::caba::VciLogger<vci_param> vci_logger_proc1("vci_logger_proc1",maptabp);
+//      soclib::caba::VciLogger<vci_param> vci_logger_proc2("vci_logger_proc2",maptabp);
+//      soclib::caba::VciLogger<vci_param> vci_logger_proc3("vci_logger_proc3",maptabp);
+//      soclib::caba::VciLogger<vci_param> vci_logger_memc("vci_logger_memc",maptabp);
+
+	soclib::caba::VciSimpleRingFast<vci_param, 40 , 33> 
+	ringd("ringd",maptabp, IntTab(), 2, 4, 2);
+//    	soclib::caba::VciVgmn<vci_param> 
+//  	ringd("ringd",maptabp, 4, 3, 2, 2);
+
+	soclib::caba::VciSimpleRingFast<vci_param, 40 , 33> 
+	ringc("ringc",maptabc, IntTab(), 2, 5, 5);
+//    	soclib::caba::VciVgmn<vci_param> 
+//  	ringc("ringc",maptabc, 5, 5, 2, 2);
+
+	soclib::caba::VciSimpleRingFast<vci_param, 40 , 33> 
+	ringx("ringx",maptabx, IntTab(), 2, 1, 1);
+//    	soclib::caba::VciVgmn<vci_param> 
+//  	ringx("ringx",maptabx, 1, 1, 2, 2);
+
+	// Net-List
+ 
+	proc0.p_clk(signal_clk);  
+	proc0.p_resetn(signal_resetn);  
+	proc0.p_irq[0](signal_proc0_it0); 
+	proc0.p_irq[1](signal_proc0_it1); 
+	proc0.p_irq[2](signal_proc0_it2); 
+	proc0.p_irq[3](signal_proc0_it3); 
+	proc0.p_irq[4](signal_proc0_it4); 
+	proc0.p_irq[5](signal_proc0_it5); 
+	proc0.p_vci_ini_rw(signal_vci_ini_rw_proc0);
+	proc0.p_vci_ini_c(signal_vci_ini_c_proc0);
+	proc0.p_vci_tgt(signal_vci_tgt_proc0);
+
+	proc1.p_clk(signal_clk);  
+	proc1.p_resetn(signal_resetn);  
+	proc1.p_irq[0](signal_proc1_it0); 
+	proc1.p_irq[1](signal_proc1_it1); 
+	proc1.p_irq[2](signal_proc1_it2); 
+	proc1.p_irq[3](signal_proc1_it3); 
+	proc1.p_irq[4](signal_proc1_it4); 
+	proc1.p_irq[5](signal_proc1_it5); 
+	proc1.p_vci_ini_rw(signal_vci_ini_rw_proc1);
+	proc1.p_vci_ini_c(signal_vci_ini_c_proc1);
+	proc1.p_vci_tgt(signal_vci_tgt_proc1);
+
+	proc2.p_clk(signal_clk);  
+	proc2.p_resetn(signal_resetn);  
+	proc2.p_irq[0](signal_proc2_it0); 
+	proc2.p_irq[1](signal_proc2_it1); 
+	proc2.p_irq[2](signal_proc2_it2); 
+	proc2.p_irq[3](signal_proc2_it3); 
+	proc2.p_irq[4](signal_proc2_it4); 
+	proc2.p_irq[5](signal_proc2_it5); 
+	proc2.p_vci_ini_rw(signal_vci_ini_rw_proc2);
+	proc2.p_vci_ini_c(signal_vci_ini_c_proc2);
+	proc2.p_vci_tgt(signal_vci_tgt_proc2);
+
+	proc3.p_clk(signal_clk);  
+	proc3.p_resetn(signal_resetn);  
+	proc3.p_irq[0](signal_proc3_it0); 
+	proc3.p_irq[1](signal_proc3_it1); 
+	proc3.p_irq[2](signal_proc3_it2); 
+	proc3.p_irq[3](signal_proc3_it3); 
+	proc3.p_irq[4](signal_proc3_it4); 
+	proc3.p_irq[5](signal_proc3_it5); 
+	proc3.p_vci_ini_rw(signal_vci_ini_rw_proc3);
+	proc3.p_vci_ini_c(signal_vci_ini_c_proc3);
+	proc3.p_vci_tgt(signal_vci_tgt_proc3);
+
+//  vci_logger_proc0.p_clk(signal_clk);
+//  vci_logger_proc0.p_resetn(signal_resetn);
+//  vci_logger_proc0.p_vci(signal_vci_ini_rw_proc0);
+
+//  vci_logger_proc1.p_clk(signal_clk);
+//  vci_logger_proc1.p_resetn(signal_resetn);
+//  vci_logger_proc1.p_vci(signal_vci_ini_rw_proc2);
+
+//  vci_logger_proc2.p_clk(signal_clk);
+//  vci_logger_proc2.p_resetn(signal_resetn);
+//  vci_logger_proc2.p_vci(signal_vci_ini_rw_proc2);
+
+//  vci_logger_proc3.p_clk(signal_clk);
+//  vci_logger_proc3.p_resetn(signal_resetn);
+//  vci_logger_proc3.p_vci(signal_vci_ini_rw_proc3);
+
+//  vci_logger_memc.p_clk(signal_clk);
+//  vci_logger_memc.p_resetn(signal_resetn);
+//  vci_logger_memc.p_vci(signal_vci_tgt_memc);
+
+	tty.p_clk(signal_clk);
+	tty.p_resetn(signal_resetn);
+	tty.p_vci(signal_vci_tgt_tty);
+	tty.p_irq[0](signal_tty_irq0); 
+	tty.p_irq[1](signal_tty_irq1); 
+	tty.p_irq[2](signal_tty_irq2); 
+	tty.p_irq[3](signal_tty_irq3); 
+
+	memc.p_clk(signal_clk);
+	memc.p_resetn(signal_resetn);
+	memc.p_vci_tgt(signal_vci_tgt_memc);
+	memc.p_vci_tgt_cleanup(signal_vci_tgt_cleanup_memc);
+	memc.p_vci_ini(signal_vci_ini_memc);
+	memc.p_vci_ixr(signal_vci_ixr_memc);
+
+	xram.p_clk(signal_clk);
+        xram.p_resetn(signal_resetn);
+	xram.p_vci(signal_vci_tgt_xram);
+	
+	ringd.p_clk(signal_clk);
+	ringd.p_resetn(signal_resetn);
+	ringd.p_to_initiator[0](signal_vci_ini_rw_proc0);
+	ringd.p_to_initiator[1](signal_vci_ini_rw_proc1);
+	ringd.p_to_initiator[2](signal_vci_ini_rw_proc2);
+	ringd.p_to_initiator[3](signal_vci_ini_rw_proc3);
+	ringd.p_to_target[0](signal_vci_tgt_memc);
+	ringd.p_to_target[1](signal_vci_tgt_tty);
+
+	ringc.p_clk(signal_clk);
+	ringc.p_resetn(signal_resetn);
+	ringc.p_to_initiator[0](signal_vci_ini_c_proc0);
+	ringc.p_to_initiator[1](signal_vci_ini_c_proc1);
+	ringc.p_to_initiator[2](signal_vci_ini_c_proc2);
+	ringc.p_to_initiator[3](signal_vci_ini_c_proc3);
+	ringc.p_to_initiator[4](signal_vci_ini_memc);
+	ringc.p_to_target[0](signal_vci_tgt_proc0);
+	ringc.p_to_target[1](signal_vci_tgt_proc1);
+	ringc.p_to_target[2](signal_vci_tgt_proc2);
+	ringc.p_to_target[3](signal_vci_tgt_proc3);
+	ringc.p_to_target[4](signal_vci_tgt_cleanup_memc);
+
+	ringx.p_clk(signal_clk);
+	ringx.p_resetn(signal_resetn);
+	ringx.p_to_initiator[0](signal_vci_ixr_memc);
+	ringx.p_to_target[0](signal_vci_tgt_xram);
+
+	int ncycles;
+
+#ifndef SOCVIEW
+	if (argc == 2) {
+		ncycles = std::atoi(argv[1]);
+	} else {
+		std::cerr
+			<< std::endl
+			<< "The number of simulation cycles must "
+			   "be defined in the command line"
+			<< std::endl;
+		exit(1);
+	}
+
+	sc_start(sc_core::sc_time(0, SC_NS));
+	signal_resetn = false;
+        signal_stuck0 = false;
+
+	sc_start(sc_core::sc_time(1, SC_NS));
+	signal_resetn = true;
+
+	for (int i = 0; i < ncycles ; i++) 
+        {
+		sc_start(sc_core::sc_time(1, SC_NS));
+  
+	}
+
+        std::cout << "Hit ENTER to end simulation" << std::endl;
+        char buf[1];
+	std::cin.getline(buf,1);
+
+	return EXIT_SUCCESS;
+#else
+	ncycles = 1;
+	sc_start(sc_core::sc_time(0, SC_NS));
+	signal_resetn = false;
+	sc_start(sc_core::sc_time(1, SC_NS));
+	signal_resetn = true;
+
+	debug();
+	return EXIT_SUCCESS;
+#endif
+}
+
+int sc_main (int argc, char *argv[])
+{
+	try {
+		return _main(argc, argv);
+	} catch (std::exception &e) {
+		std::cout << e.what() << std::endl;
+	} catch (...) {
+		std::cout << "Unknown exception occured" << std::endl;
+		throw;
+	}
+	return 1;
+}
Index: branches/v4/platforms/caba-ring-ccxcachev1_memcachev3-mipsel/Makefile
===================================================================
--- branches/v4/platforms/caba-ring-ccxcachev1_memcachev3-mipsel/Makefile	(revision 371)
+++ branches/v4/platforms/caba-ring-ccxcachev1_memcachev3-mipsel/Makefile	(revision 371)
@@ -0,0 +1,6 @@
+ARCH=mips32el
+SIMULATION_ARGS=100000
+SOCLIB_CC_ADD_ARGS=-t systemcass
+SOCLIB?=$(shell soclib-cc --getpath)
+export SOCLIB
+include $(SOCLIB)/soclib/platform/topcells/all.mk
Index: branches/v4/platforms/caba-ring-ccxcachev1_memcachev3-mipsel/platform_desc
===================================================================
--- branches/v4/platforms/caba-ring-ccxcachev1_memcachev3-mipsel/platform_desc	(revision 371)
+++ branches/v4/platforms/caba-ring-ccxcachev1_memcachev3-mipsel/platform_desc	(revision 371)
@@ -0,0 +1,28 @@
+
+# -*- python -*-
+
+
+todo = Platform('caba', 'top.cpp',
+				uses = [
+	Uses('caba:vci_cc_xcache_wrapper_v1', iss_t = 'common:iss2_simhelper', simhelper_iss_t = 'common:mips32el'),
+	Uses('caba:vci_simple_ram'),
+  Uses('caba:vci_logger'),
+	Uses('caba:vci_multi_tty'),
+	Uses('caba:vci_simple_ring_fast',
+        ring_cmd_data_size=40,
+        ring_rsp_data_size=33
+        ),
+	Uses('caba:vci_mem_cache_v3'),
+	Uses('common:elf_file_loader'),
+	],
+	cell_size = 4,
+	plen_size = 8,
+	addr_size = 32,
+	rerror_size = 2,
+	clen_size = 1,
+	rflag_size = 1,
+	srcid_size = 8,
+	pktid_size = 4,
+	trdid_size = 4,
+	wrplen_size = 1
+)
Index: branches/v4/platforms/caba-ring-ccxcachev1_memcachev3-mipsel/segmentation.h
===================================================================
--- branches/v4/platforms/caba-ring-ccxcachev1_memcachev3-mipsel/segmentation.h	(revision 371)
+++ branches/v4/platforms/caba-ring-ccxcachev1_memcachev3-mipsel/segmentation.h	(revision 371)
@@ -0,0 +1,67 @@
+
+/////////////////////////////////////////////////////////////////
+//	ADDRESS SPACE SEGMENTATION
+//
+//	This file must be included in the system.cpp file, 
+//	for harware configuration : It is used to build
+//	the SOCLIB_SEGMENT_TABLE.
+//
+//	This file can also be used by the ldscript generator,
+//	for embedded software generation.
+//	
+//	It gives the system integrator the garanty
+//	that hardware and software have the same
+//	description of the address space segmentation.
+/////////////////////////////////////////////////////////////////
+
+/////////////////////////////////////////////////////////////////
+//	reset, and exception segments
+//      base address required by MIPS processor
+/////////////////////////////////////////////////////////////////
+
+#define	RESET_BASE	0xBFC00000
+#define	RESET_SIZE	0x00010000
+
+#define	EXCEP_BASE	0x80000000
+#define	EXCEP_SIZE	0x00010000
+
+#define	TEXT_BASE	0x00400000
+#define	TEXT_SIZE	0x00050000
+/////////////////////////////////////////////////////////////////
+//	global data segment (initialised)
+/////////////////////////////////////////////////////////////////
+
+#define MC_M_BASE	0x10000000
+#define MC_M_SIZE	0x00200000
+
+//////////////////////////////////////////////////////////
+//	System devices
+///////////////////////////////////////////////////////////
+
+#define	TTY_BASE	0xC0200000
+#define	TTY_SIZE	0x00000100
+
+#define	TIMER_BASE	0xD0200000
+#define	TIMER_SIZE	0x00000100
+
+#define	LOCKS_BASE	0xE0200000
+#define	LOCKS_SIZE	0x00000100
+
+#define C_PROC0_BASE	0x01200000
+#define C_PROC0_SIZE	0x00000010
+
+#define C_PROC1_BASE	0x02200000
+#define C_PROC1_SIZE	0x00000010
+
+#define C_PROC2_BASE	0x03200000
+#define C_PROC2_SIZE	0x00000010
+
+#define C_PROC3_BASE	0x04200000
+#define C_PROC3_SIZE	0x00000010
+
+#define C_MC_M_BASE	0x00200000
+#define C_MC_M_SIZE	0x00000008
+
+#define XRAM_BASE	0xB0200000
+#define XRAM_SIZE	0x00000008
+
Index: branches/v4/platforms/caba-ring-ccxcachev1_memcachev3-mipsel/soft/Makefile
===================================================================
--- branches/v4/platforms/caba-ring-ccxcachev1_memcachev3-mipsel/soft/Makefile	(revision 371)
+++ branches/v4/platforms/caba-ring-ccxcachev1_memcachev3-mipsel/soft/Makefile	(revision 371)
@@ -0,0 +1,4 @@
+ADD_OBJS= stdio.o stdlib.o exception.o system.o
+SOCLIB?=$(shell soclib-cc --getpath)
+export SOCLIB
+include $(SOCLIB)/soclib/platform/topcells/soft.mk
Index: branches/v4/platforms/caba-ring-ccxcachev1_memcachev3-mipsel/soft/main.c
===================================================================
--- branches/v4/platforms/caba-ring-ccxcachev1_memcachev3-mipsel/soft/main.c	(revision 371)
+++ branches/v4/platforms/caba-ring-ccxcachev1_memcachev3-mipsel/soft/main.c	(revision 371)
@@ -0,0 +1,234 @@
+#include "system.h"
+#include "stdio.h"
+#include "stdlib.h"
+#include "matrice.h"
+
+#include "../segmentation.h"
+
+#define NPROCS 4
+#define SIZE 500 
+#define SORT_TYPE 0
+
+volatile int nprocs=NPROCS;
+
+unsigned int SortArr0[NPROCS*(SIZE+200)];
+
+void SORT(unsigned int *base, unsigned int n, int type);
+void insertion_sort(unsigned int *base, unsigned int n); // type 2
+void selection_sort(unsigned int *base, unsigned int n); // type 1
+void bubble_sort(unsigned int *base, unsigned int n);    // type 3
+void shellSortPhase(unsigned int a[],unsigned int length, int gap);
+void shellSort(unsigned int *base, unsigned int n);     // type 0
+
+int main()
+{
+  register int p; 
+
+  int beg_cycle, end_cycle;
+
+  beg_cycle = cpu_cycles();
+   
+  p=procnum();
+
+  puts("Hello from processor ");
+  putchar(p+'0');
+  putchar('\n');
+
+  int i;
+  int j;
+  unsigned int* SortArray;
+
+  if(p+1 <= nprocs)
+  {
+        i=1;
+  	puts("Memory copy \n");
+        SortArray = SortArr0 + p*(SIZE+200);
+	memcpy(SortArray, gQSortNum0 + p*SIZE,SIZE*4);
+ 	puts("Sort... \n");
+        SORT((unsigned int *) (SortArray), (unsigned int) SIZE, SORT_TYPE);
+
+  	for (j = 1; j < SIZE; j++)
+    	{
+	  if (SortArray[j] < SortArray[j-1])
+		{
+	  		puts("ucbqsort: failed\n");
+			while(1);
+		}
+
+    	}
+
+  	puts("ucbqsort: success\n");
+        end_cycle = cpu_cycles();
+        printf( "nombre cycles cpu : %i\n", end_cycle-beg_cycle);
+  }
+
+  while(1);
+}
+
+
+//---- insertion sort : non adapté pour tableaux de grande taille (> 100) --
+void insertion_sort(unsigned int *base, unsigned int n) 
+{
+    /* Spécifications externes : Tri du tableau base par insertion séquentielle */
+    int i,p,j;
+    int x;
+
+    puts("Insertion Sort\n");
+
+    for (i = 1; i < n; i++) 
+    {
+
+        putchar('-'); // added for debug
+
+        /* stockage de la valeur en i */
+        x = base[i]; 
+ 
+        /* recherche du plus petit indice p inférieur à i tel que base[p] >= base[i] */
+        for(p = 0; base[p] < x; p++);
+        /* p pointe une valeur de base supérieure à celle en i */ 
+ 
+        /* décalage avant des valeurs de base entre p et i */         
+        for (j = i-1; j >= p; j--) {
+            base[j+1] = base[j]; 
+        }   
+ 
+        base[p] = x; /* insertion de la valeur stockée à la place vacante */
+
+        putchar('+'); // added for debug
+
+    }
+}
+
+//------ simple_sort -------------------------------
+void selection_sort(unsigned int *base, unsigned int n)
+{
+     int i, min, j , x;
+     puts("Selection Sort\n");
+
+     for(i = 0 ; i < n - 1 ; i++)
+     {
+
+         putchar('-'); // added for debug
+
+         min = i;
+
+         
+         for(j = i+1 ; j < n ; j++)
+         {
+        
+            if(base[j] < base[min])
+                  min = j;
+            
+         }
+
+         if(min != i)
+         {
+             x = base[i];
+             base[i] = base[min];
+             base[min] = x;
+         }
+
+         putchar('+'); // added for debug
+
+     }
+}
+//-------------------------------
+void bubble_sort(unsigned int *base, unsigned int n)
+{
+        int i   = 0; /* Indice de répétition du tri */
+ 	int j   = 0; /* Variable de boucle */
+ 	int tmp = 0; /* Variable de stockage temporaire */
+        int en_desordre = 1; /* Booléen marquant l'arrêt du tri si le tableau est ordonné */
+
+        puts("Bubble Sort\n");
+
+	/* Boucle de répétition du tri et le test qui arrête le tri dès que le tableau est ordonné */
+	for(i = 0 ; (i < n) && en_desordre; i++)
+	{
+                putchar('-'); // added for debug
+
+		/* Supposons le tableau ordonné */
+		en_desordre = 0;
+		/* Vérification des éléments des places j et j-1 */
+		for(j = 1 ; j < n - i ; j++)
+		{
+			/* Si les 2 éléments sont mal triés */
+			if(base[j] < base[j-1])
+			{
+				/* Inversion des 2 éléments */
+ 				tmp = base[j-1];
+ 				base[j-1] = base[j];
+ 				base[j] = tmp;
+ 
+ 				/* Le tableau n'est toujours pas trié */
+				en_desordre = 1;
+ 			}
+		}
+
+                putchar('+'); // added for debug
+	}
+
+}
+//------------------------------------------------------
+/*
+ * Exécute un tri par insertion avec la séparation donnée
+ * If gap == 1, on fait un tri ordinaire.
+ * If gap >= length, on ne fait rien.
+ */
+void shellSortPhase(unsigned int a[],unsigned int length, int gap) {
+    int i;
+ 
+    puti(gap);
+    for (i = gap; i < length; ++i) {
+        unsigned int value = a[i];
+        int j;
+        for (j = i - gap; j >= 0 && a[j] > value; j -= gap) {
+	    putchar('+');
+            a[j + gap] = a[j];
+	    putchar('-');
+        }
+        a[j + gap] = value;
+    }
+}
+ 
+void shellSort(unsigned int *base, unsigned int n) {
+    /*
+     * gaps[] doit approximer une Série géométrique.
+     * La sequence suivante est la meilleure connue en terme
+     * de nombre moyen de comparaisons. voir:
+     * http://www.research.att.com/~njas/sequences/A102549
+     */
+    static const int gaps[] = {
+        1, 4, 10, 23, 57, 132, 301, 701
+    };
+    int sizeIndex;
+ 
+    puts("Shell Sort\n");
+    for (sizeIndex = sizeof(gaps)/sizeof(gaps[0]) - 1;
+               sizeIndex >= 0;
+               --sizeIndex)
+        shellSortPhase(base, n, gaps[sizeIndex]);
+}
+
+//-------------------------------------*/
+void SORT(unsigned int *base, unsigned int n, int type)
+{
+  switch(type)
+  {
+  case 0:
+    shellSort(base, n);
+    break;
+  case 1:
+    selection_sort(base, n);
+    break;
+  case 2:
+    insertion_sort(base, n);
+    break;
+  case 3:
+    bubble_sort(base, n);
+    break;
+  default:
+    break;
+  }
+}
+
Index: branches/v4/platforms/caba-ring-ccxcachev1_memcachev3-mipsel/soft/matrice.h
===================================================================
--- branches/v4/platforms/caba-ring-ccxcachev1_memcachev3-mipsel/soft/matrice.h	(revision 371)
+++ branches/v4/platforms/caba-ring-ccxcachev1_memcachev3-mipsel/soft/matrice.h	(revision 371)
@@ -0,0 +1,713 @@
+unsigned int gQSortNum0[16000] = {
+  251, 24, 113, 170, 215, 60, 83, 30, 115, 48, 169, 210, 49, 92, 101, 58, 21, 184, 225, 6,
+  199, 244, 227, 146, 99, 96, 25, 222, 65, 140, 213, 22, 219, 136, 175, 182, 73, 36, 141, 190, 
+  83, 112, 137, 114, 175, 188, 187, 102, 53, 168, 193, 154, 167, 172, 3, 242, 67, 64,144, 137,
+  142, 175, 188, 69, 102, 53, 168, 193, 102, 89, 172, 253, 242, 67,192, 7, 62, 159, 20, 181,
+  182, 187, 216, 207, 22, 105, 132, 109, 162, 205, 16, 151, 18, 113, 228, 37, 6, 85, 8, 161,
+  58, 135, 76, 35, 174, 35, 224, 39, 158, 127, 180, 149, 86, 155, 200, 239, 118, 119, 28, 77,
+  254, 19, 176, 183, 78, 145, 132, 5, 90, 117, 152, 127, 218, 153, 20, 67, 178, 3, 128, 185,
+  254, 95, 172, 139, 246, 123, 104, 15, 42, 169, 68, 211, 98, 243, 80, 41, 174, 79, 36, 27,
+  186, 149, 86, 155, 200, 239, 118, 119, 28, 77, 254, 19, 176, 183,78, 145, 132, 5, 90, 117,
+  152, 127, 218, 153, 20, 67, 178, 3, 128, 185, 254, 95, 172, 139, 246, 123, 104, 15, 42,169,
+  68, 211, 98, 243, 80, 41, 174, 79, 36, 27, 186, 107, 56, 97, 134, 71, 116, 157, 238, 227,
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+  6, 57, 12, 227, 110, 157, 96, 25, 34, 191, 140, 43, 22, 37, 136, 175, 182, 183, 220, 115, 66, 173, 144, 137, 114,
+  81, 68, 69, 102, 203, 168, 193, 102, 167, 172, 3, 14, 67, 64, 249, 62, 159, 20, 75, 74, 187, 216, 207, 22, 151,
+  124, 109, 162, 51, 16, 151, 18, 143, 28, 37, 250, 171, 8, 95, 58, 135, 76, 221, 82, 221, 224, 217, 158, 127, 76,
+  107, 170, 155, 200, 239, 138, 119, 228, 77, 2, 237, 176, 183, 178, 111, 132, 5, 166, 139, 104, 129, 218, 103, 20, 189,
+  78, 3, 128, 185, 2, 95, 172, 139, 10, 123, 104, 241, 214, 169, 188, 211, 98, 13, 80, 41, 82, 177, 220, 229, 186,
+  149, 200, 159, 134, 71, 116, 99, 18, 29, 224, 103, 162, 193, 12, 171, 150, 165, 248, 209, 202, 201, 92, 13, 62, 211,
+  16, 247, 14, 209, 60, 59, 26, 181, 40, 191, 230, 39, 44, 125, 114, 195, 64, 135, 190, 225, 148, 53, 202, 197, 168,
+  79, 106, 23, 4, 19, 34, 77, 144, 23, 146, 241, 156, 91, 122, 43, 136, 223, 70, 249, 52, 163, 46, 93, 96, 89,
+  30, 255, 52, 21, 214, 229, 72, 111, 10, 9, 156, 205, 126, 147, 48, 55, 50, 239, 252, 133, 38, 11, 232, 1, 166,
+  25, 108, 61, 206, 125, 0, 199, 126, 223, 44, 11, 118, 251, 24, 113, 170, 215, 60, 83, 30, 115, 48, 169, 210, 49,
+  92, 101, 58, 21, 184, 225, 6, 199, 244, 227, 146, 99, 96, 25, 222, 65, 140, 213, 22, 219, 136, 175, 182, 73, 36,
+  141, 190, 83, 112, 137, 114, 175, 188, 187, 102, 53, 168, 193, 154, 167, 172, 3, 242, 67, 64, 7, 62, 159, 236, 75,
+  182, 187, 40, 49, 234, 105, 124, 109, 162, 205, 16, 105, 238, 143, 28, 37, 6, 85, 248, 161, 58, 121, 180, 221, 174,
+  221, 32, 217, 98, 129, 76, 149, 170, 101, 200, 239, 118, 137, 28, 179, 254, 19, 80, 183, 178, 145, 124, 251, 166, 139,
+  152, 129, 38, 153, 20, 189, 78, 3, 128, 71, 254, 95, 84, 139, 10, 123, 152, 241, 214, 169, 68, 211, 98, 13, 80,
+  215, 82, 79, 36, 229, 70, 149, 56, 159, 134, 185, 140, 99, 18, 29, 224, 153, 94, 63, 244, 85, 150, 91, 248, 209,
+  202, 55, 92, 243, 194, 211, 240, 247, 242, 209, 196, 197, 26, 75, 40, 191, 26, 39, 44, 131, 142, 195, 64, 121, 190,
+  225, 148, 53, 54, 197, 88, 79, 106, 233, 252, 19, 34, 77, 144, 233, 146, 241, 100, 91, 134, 43, 136, 33, 70, 249,
+  204, 163, 210, 163, 96, 89, 226, 1, 52, 235, 214, 27, 72, 111, 246, 247, 156, 51, 130, 109, 208, 55, 50, 17, 252,
+  123, 218, 245, 232, 255, 90, 231, 108, 195, 50, 125, 0, 199, 130, 223, 212, 11, 138, 251, 232, 143, 86, 215, 196, 83,
+  30, 141, 48, 87, 46, 207, 92, 155, 58, 235, 184, 31, 6, 199, 12, 29, 146, 157, 160, 231, 34, 191, 116, 213, 22,
+  37, 136, 175, 74, 183, 36, 115, 66, 173, 144, 137, 142, 175, 188, 69, 102, 53, 168, 193, 102, 89, 172, 253, 242, 67,
+  192, 7, 62, 159, 20, 181, 182, 187, 216, 207, 22, 105, 132, 109, 162, 205, 16, 151, 18, 113, 228, 37, 6, 85, 8,
+  161, 58, 135, 76, 35, 174, 35, 224, 39, 158, 127, 180, 149, 86, 155, 200, 239, 118, 119, 28, 77, 254, 19, 176, 183,
+  78, 145, 132, 5, 90, 117, 152, 127, 218, 153, 20, 67, 178, 3, 128, 185, 254, 95, 172, 139, 246, 123, 104, 15, 42,
+  169, 68, 211, 98, 243, 80, 41, 174, 79, 36, 27, 186, 107, 56, 97, 134, 71, 116, 157, 238, 227, 32, 153, 162, 193,
+  244, 171, 150, 165, 248, 209, 54, 55, 164, 13, 194, 45, 16, 247, 242, 47, 60, 59, 26, 75, 40, 65, 230, 217, 44,
+  131, 142, 195, 192, 121, 190, 225, 108, 203, 202, 197, 168, 177, 150, 233, 252, 19, 34, 77, 144, 23, 110, 15, 100, 91,
+  122, 213, 120, 223, 70, 7, 52, 93, 46, 93, 160, 167, 226, 255, 204, 21, 42, 229, 72, 111, 246, 9, 100, 205, 126,
+  147, 48, 55, 206, 239, 4, 133, 218, 245, 232, 255, 166, 231, 108, 195, 50, 131, 0, 57, 130, 223, 44, 245, 118, 251,
+  232, 113, 86, 215, 196, 83, 30, 141, 48, 87, 46, 207, 92, 155, 198, 235, 72, 31, 250, 57, 244, 29, 110, 99, 160,
+  231, 34, 65, 116, 43, 22, 219, 136, 175, 74, 73, 220, 141, 190, 83, 112, 137, 142, 81, 68, 69, 154, 203, 88, 63,
+  154, 89, 172, 3, 242, 67, 192, 249, 62, 159, 20, 181, 74, 69, 216, 49, 22, 105, 132, 109, 162, 205, 16, 151, 18,
+  113, 228, 219, 
+250, 171, 8, 95, 58, 135, 180, 35, 82, 221, 224, 39, 98, 129, 180, 107, 86, 101, 200, 239, 118, 119,
+  228, 179, 2, 237, 80, 183, 78, 111, 124, 5, 90, 117, 104, 127, 38, 153, 20, 67, 178, 253, 128, 185, 254, 95, 172,
+  117, 10, 123, 152, 241, 42, 87, 188, 211, 98, 243, 80, 215, 82, 79, 36, 27, 186, 107, 200, 159, 122, 71, 140, 157,
+  238, 29, 224, 153, 94, 63, 244, 85, 106, 91, 248, 47, 54, 201, 164, 243, 62, 211, 240, 247, 242, 47, 196, 197, 230,
+  181, 216, 65, 26, 217, 44, 125, 114, 195, 192, 135, 190, 31, 148, 203, 202, 59, 88, 79, 150, 233, 252, 19, 34, 77,
+  144, 233, 146, 15, 100, 165, 122, 213, 136, 223, 70, 249, 204, 93, 46, 93, 96, 167, 30, 1, 204, 21, 42, 27, 72
+};
+
+
Index: branches/v4/platforms/caba-ring-ccxcachev1_memcachev3-mipsel/top.cpp
===================================================================
--- branches/v4/platforms/caba-ring-ccxcachev1_memcachev3-mipsel/top.cpp	(revision 371)
+++ branches/v4/platforms/caba-ring-ccxcachev1_memcachev3-mipsel/top.cpp	(revision 371)
@@ -0,0 +1,348 @@
+
+#include <systemc>
+#include <sys/time.h>
+#include <iostream>
+#include <cstdlib>
+#include <cstdarg>
+
+#include "mapping_table.h"
+#include "mips32.h"
+#include "iss2_simhelper.h"
+#include "vci_simple_ram.h"
+#include "vci_multi_tty.h"
+#include "vci_simple_ring_fast.h"
+#include "vci_mem_cache_v3.h"
+#include "vci_cc_xcache_wrapper_v1.h"
+#include "vci_logger.h"
+
+#ifdef USE_GDB_SERVER
+#include "iss/gdbserver.h"
+#endif
+
+//#define  VCI_LOGGER
+#include "segmentation.h"
+
+int _main(int argc, char *argv[])
+{
+	using namespace sc_core;
+	// Avoid repeating these everywhere
+	using soclib::common::IntTab;
+	using soclib::common::Segment;
+
+	// Define VCI parameters
+	typedef soclib::caba::VciParams<4,8,32,2,1,1,8,4,4,1> vci_param;
+	typedef soclib::common::Iss2Simhelper<soclib::common::Mips32ElIss> proc_iss;
+	// Mapping table
+
+	soclib::common::MappingTable maptabp(32, IntTab(8), IntTab(8), 0x00300000);
+
+	maptabp.add(Segment("reset", RESET_BASE, RESET_SIZE, IntTab(2), true));
+	maptabp.add(Segment("excep", EXCEP_BASE, EXCEP_SIZE, IntTab(2), true));
+	maptabp.add(Segment("text" , TEXT_BASE , TEXT_SIZE , IntTab(2), true));
+	maptabp.add(Segment("tty"  , TTY_BASE  , TTY_SIZE  , IntTab(1), false));
+	maptabp.add(Segment("mc_m" , MC_M_BASE , MC_M_SIZE , IntTab(2), true ));
+ 
+	std::cout << maptabp << std::endl;
+
+        soclib::common::MappingTable maptabc(32, IntTab(8), IntTab(8), 0x00300000);
+	maptabc.add(Segment("c_proc0" , C_PROC0_BASE , C_PROC0_SIZE , IntTab(0), false, true, IntTab(0)));
+	maptabc.add(Segment("c_proc1" , C_PROC1_BASE , C_PROC1_SIZE , IntTab(1), false, true, IntTab(1)));
+	maptabc.add(Segment("c_proc2" , C_PROC2_BASE , C_PROC2_SIZE , IntTab(2), false, true, IntTab(2)));
+	maptabc.add(Segment("c_proc3" , C_PROC3_BASE , C_PROC3_SIZE , IntTab(3), false, true, IntTab(3)));
+	maptabc.add(Segment("mc_m"  , MC_M_BASE , MC_M_SIZE  , IntTab(4), false, false));
+	maptabc.add(Segment("reset", RESET_BASE, RESET_SIZE, IntTab(4), false, false));
+	maptabc.add(Segment("excep", EXCEP_BASE, EXCEP_SIZE, IntTab(4), false, false));
+	maptabc.add(Segment("text" , TEXT_BASE , TEXT_SIZE , IntTab(4), false, false));
+
+	std::cout << maptabc << std::endl;
+	
+	soclib::common::MappingTable maptabx(32, IntTab(8), IntTab(8), 0x00300000);
+	maptabx.add(Segment("xram" , MC_M_BASE , MC_M_SIZE , IntTab(0), false));
+	maptabx.add(Segment("reset", RESET_BASE, RESET_SIZE, IntTab(0), false));
+	maptabx.add(Segment("excep", EXCEP_BASE, EXCEP_SIZE, IntTab(0), false));
+	maptabx.add(Segment("text" , TEXT_BASE , TEXT_SIZE , IntTab(0), false));
+	
+	std::cout << maptabx << std::endl;
+
+	// Signals
+	sc_clock	signal_clk("clk");
+	sc_signal<bool> signal_resetn("resetn");
+   
+	sc_signal<bool> signal_proc0_it0("proc0_it0"); 
+	sc_signal<bool> signal_proc0_it1("proc0_it1"); 
+	sc_signal<bool> signal_proc0_it2("proc0_it2"); 
+	sc_signal<bool> signal_proc0_it3("proc0_it3"); 
+	sc_signal<bool> signal_proc0_it4("proc0_it4"); 
+	sc_signal<bool> signal_proc0_it5("proc0_it5");
+
+	sc_signal<bool> signal_proc1_it0("proc1_it0"); 
+	sc_signal<bool> signal_proc1_it1("proc1_it1"); 
+	sc_signal<bool> signal_proc1_it2("proc1_it2"); 
+	sc_signal<bool> signal_proc1_it3("proc1_it3"); 
+	sc_signal<bool> signal_proc1_it4("proc1_it4"); 
+	sc_signal<bool> signal_proc1_it5("proc1_it5");
+
+	sc_signal<bool> signal_proc2_it0("proc2_it0"); 
+	sc_signal<bool> signal_proc2_it1("proc2_it1"); 
+	sc_signal<bool> signal_proc2_it2("proc2_it2"); 
+	sc_signal<bool> signal_proc2_it3("proc2_it3"); 
+	sc_signal<bool> signal_proc2_it4("proc2_it4"); 
+	sc_signal<bool> signal_proc2_it5("proc2_it5");
+
+	sc_signal<bool> signal_proc3_it0("proc3_it0"); 
+	sc_signal<bool> signal_proc3_it1("proc3_it1"); 
+	sc_signal<bool> signal_proc3_it2("proc3_it2"); 
+	sc_signal<bool> signal_proc3_it3("proc3_it3"); 
+	sc_signal<bool> signal_proc3_it4("proc3_it4"); 
+	sc_signal<bool> signal_proc3_it5("proc3_it5");
+
+	soclib::caba::VciSignals<vci_param> signal_vci_ini_rw_proc0("vci_ini_rw_proc0");
+	soclib::caba::VciSignals<vci_param> signal_vci_ini_c_proc0("vci_ini_c_proc0");
+
+	soclib::caba::VciSignals<vci_param> signal_vci_tgt_proc0("vci_tgt_proc0");
+
+	soclib::caba::VciSignals<vci_param> signal_vci_ini_rw_proc1("vci_ini_rw_proc1");
+	soclib::caba::VciSignals<vci_param> signal_vci_ini_c_proc1("vci_ini_c_proc1");
+
+	soclib::caba::VciSignals<vci_param> signal_vci_tgt_proc1("vci_tgt_proc1");
+
+	soclib::caba::VciSignals<vci_param> signal_vci_ini_rw_proc2("vci_ini_rw_proc2");
+	soclib::caba::VciSignals<vci_param> signal_vci_ini_c_proc2("vci_ini_c_proc2");
+
+	soclib::caba::VciSignals<vci_param> signal_vci_tgt_proc2("vci_tgt_proc2");
+
+	soclib::caba::VciSignals<vci_param> signal_vci_ini_rw_proc3("vci_ini_rw_proc3");
+	soclib::caba::VciSignals<vci_param> signal_vci_ini_c_proc3("vci_ini_c_proc3");
+
+	soclib::caba::VciSignals<vci_param> signal_vci_tgt_proc3("vci_tgt_proc3");
+
+	soclib::caba::VciSignals<vci_param> signal_vci_tgt_tty("vci_tgt_tty");
+
+	soclib::caba::VciSignals<vci_param> signal_vci_tgt_rom("vci_tgt_rom");
+
+	soclib::caba::VciSignals<vci_param> signal_vci_tgt_xram("vci_tgt_xram");
+
+	soclib::caba::VciSignals<vci_param> signal_vci_ixr_memc("vci_ixr_memc");
+	soclib::caba::VciSignals<vci_param> signal_vci_ini_memc("vci_ini_memc");
+	soclib::caba::VciSignals<vci_param> signal_vci_tgt_memc("vci_tgt_memc");
+	soclib::caba::VciSignals<vci_param> signal_vci_tgt_cleanup_memc("vci_tgt_cleanup_memc");
+
+	sc_signal<bool> signal_tty_irq0("signal_tty_irq0"); 
+	sc_signal<bool> signal_tty_irq1("signal_tty_irq1"); 
+	sc_signal<bool> signal_tty_irq2("signal_tty_irq2"); 
+	sc_signal<bool> signal_tty_irq3("signal_tty_irq3"); 
+
+	soclib::common::Loader loader("soft/bin.soft");
+
+        //                                  init_rw   init_c   tgt
+/*	soclib::caba::VciCcXCacheWrapperV1<vci_param, proc_iss > 
+	proc0("proc0", 0, maptabp, maptabc, IntTab(0),IntTab(0),IntTab(0),4,64,16,4,64,16);
+
+	soclib::caba::VciCcXCacheWrapperV1<vci_param, proc_iss > 
+	proc1("proc1", 1, maptabp, maptabc, IntTab(1),IntTab(1),IntTab(1),4,64,16,4,64,16);
+
+	soclib::caba::VciCcXCacheWrapperV1<vci_param, proc_iss > 
+	proc2("proc2", 2, maptabp, maptabc, IntTab(2),IntTab(2),IntTab(2),4,64,16,4,64,16);
+
+	soclib::caba::VciCcXCacheWrapperV1<vci_param, proc_iss > 
+	proc3("proc3", 3, maptabp, maptabc, IntTab(3),IntTab(3),IntTab(3),4,64,16,4,64,16);
+*/
+
+	soclib::caba::VciCcXCacheWrapperV1<vci_param, proc_iss > 
+	proc0("proc0", 0, maptabp, maptabc, IntTab(0),IntTab(0),IntTab(0),1,8,16,1,8,16);
+
+	soclib::caba::VciCcXCacheWrapperV1<vci_param, proc_iss > 
+	proc1("proc1", 1, maptabp, maptabc, IntTab(1),IntTab(1),IntTab(1),1,8,16,1,8,16);
+
+	soclib::caba::VciCcXCacheWrapperV1<vci_param, proc_iss > 
+	proc2("proc2", 2, maptabp, maptabc, IntTab(2),IntTab(2),IntTab(2),1,8,16,1,8,16);
+
+	soclib::caba::VciCcXCacheWrapperV1<vci_param, proc_iss > 
+	proc3("proc3", 3, maptabp, maptabc, IntTab(3),IntTab(3),IntTab(3),1,8,16,1,8,16);
+
+
+	soclib::caba::VciSimpleRam<vci_param> 
+	rom("rom", IntTab(0), maptabp, loader);
+
+	soclib::caba::VciSimpleRam<vci_param> 
+	xram("xram", IntTab(0), maptabx, loader);
+
+        //                                  x_init    c_init    p_tgt     c_tgt
+	soclib::caba::VciMemCacheV3<vci_param> 
+	//memc("memc",maptabp,maptabc,maptabx,IntTab(0),IntTab(4),IntTab(2), IntTab(4),16,256,16);
+	//memc("memc",maptabp,maptabc,maptabx,IntTab(0),IntTab(4),IntTab(2), IntTab(4),4,16,16);
+	memc("memc",maptabp,maptabc,maptabx,IntTab(0),IntTab(4),IntTab(2), IntTab(4),4,4,16);
+	
+	soclib::caba::VciMultiTty<vci_param> 
+	tty("tty",IntTab(1),maptabp,"tty0","tty1","tty2","tty3",NULL);
+
+#ifdef VCI_LOGGER
+  soclib::caba::VciLogger<vci_param> vci_logger0("vci_logger0",maptabp);
+#endif
+
+	soclib::caba::VciSimpleRingFast<vci_param, 40, 33> 
+	ringp("ringp",maptabp, IntTab(), 2, 4, 3);
+
+	soclib::caba::VciSimpleRingFast<vci_param, 40, 33> 
+	ringc("ringc",maptabc, IntTab(), 2, 5, 5);
+
+  	soclib::caba::VciSimpleRingFast<vci_param, 40, 33> 
+  	ringx("ringx",maptabx, IntTab(), 2, 1, 1);
+
+	// Net-List
+ 
+	proc0.p_clk(signal_clk);  
+	proc0.p_resetn(signal_resetn);  
+	proc0.p_irq[0](signal_proc0_it0); 
+	proc0.p_irq[1](signal_proc0_it1); 
+	proc0.p_irq[2](signal_proc0_it2); 
+	proc0.p_irq[3](signal_proc0_it3); 
+	proc0.p_irq[4](signal_proc0_it4); 
+	proc0.p_irq[5](signal_proc0_it5); 
+	proc0.p_vci_ini_rw(signal_vci_ini_rw_proc0);
+	proc0.p_vci_ini_c(signal_vci_ini_c_proc0);
+	proc0.p_vci_tgt(signal_vci_tgt_proc0);
+
+	proc1.p_clk(signal_clk);  
+	proc1.p_resetn(signal_resetn);  
+	proc1.p_irq[0](signal_proc1_it0); 
+	proc1.p_irq[1](signal_proc1_it1); 
+	proc1.p_irq[2](signal_proc1_it2); 
+	proc1.p_irq[3](signal_proc1_it3); 
+	proc1.p_irq[4](signal_proc1_it4); 
+	proc1.p_irq[5](signal_proc1_it5); 
+	proc1.p_vci_ini_rw(signal_vci_ini_rw_proc1);
+	proc1.p_vci_ini_c(signal_vci_ini_c_proc1);
+	proc1.p_vci_tgt(signal_vci_tgt_proc1);
+
+	proc2.p_clk(signal_clk);  
+	proc2.p_resetn(signal_resetn);  
+	proc2.p_irq[0](signal_proc2_it0); 
+	proc2.p_irq[1](signal_proc2_it1); 
+	proc2.p_irq[2](signal_proc2_it2); 
+	proc2.p_irq[3](signal_proc2_it3); 
+	proc2.p_irq[4](signal_proc2_it4); 
+	proc2.p_irq[5](signal_proc2_it5); 
+	proc2.p_vci_ini_rw(signal_vci_ini_rw_proc2);
+	proc2.p_vci_ini_c(signal_vci_ini_c_proc2);
+	proc2.p_vci_tgt(signal_vci_tgt_proc2);
+
+	proc3.p_clk(signal_clk);  
+	proc3.p_resetn(signal_resetn);  
+	proc3.p_irq[0](signal_proc3_it0); 
+	proc3.p_irq[1](signal_proc3_it1); 
+	proc3.p_irq[2](signal_proc3_it2); 
+	proc3.p_irq[3](signal_proc3_it3); 
+	proc3.p_irq[4](signal_proc3_it4); 
+	proc3.p_irq[5](signal_proc3_it5); 
+	proc3.p_vci_ini_rw(signal_vci_ini_rw_proc3);
+	proc3.p_vci_ini_c(signal_vci_ini_c_proc3);
+	proc3.p_vci_tgt(signal_vci_tgt_proc3);
+
+	rom.p_clk(signal_clk);
+	rom.p_resetn(signal_resetn);
+	rom.p_vci(signal_vci_tgt_rom);
+
+#ifdef VCI_LOGGER
+  vci_logger0.p_clk(signal_clk);
+  vci_logger0.p_resetn(signal_resetn);
+  vci_logger0.p_vci(signal_vci_ini_rw_proc2);
+#endif
+
+	tty.p_clk(signal_clk);
+	tty.p_resetn(signal_resetn);
+	tty.p_vci(signal_vci_tgt_tty);
+	tty.p_irq[0](signal_tty_irq0); 
+	tty.p_irq[1](signal_tty_irq1); 
+	tty.p_irq[2](signal_tty_irq2); 
+	tty.p_irq[3](signal_tty_irq3); 
+
+	memc.p_clk(signal_clk);
+	memc.p_resetn(signal_resetn);
+	memc.p_vci_tgt(signal_vci_tgt_memc);
+	memc.p_vci_tgt_cleanup(signal_vci_tgt_cleanup_memc);
+	memc.p_vci_ini(signal_vci_ini_memc);
+	memc.p_vci_ixr(signal_vci_ixr_memc);
+
+	xram.p_clk(signal_clk);
+  xram.p_resetn(signal_resetn);
+	xram.p_vci(signal_vci_tgt_xram);
+	
+	ringp.p_clk(signal_clk);
+	ringp.p_resetn(signal_resetn);
+
+	ringc.p_clk(signal_clk);
+	ringc.p_resetn(signal_resetn);
+
+	ringx.p_clk(signal_clk);
+	ringx.p_resetn(signal_resetn);
+
+	ringp.p_to_initiator[0](signal_vci_ini_rw_proc0);
+	ringp.p_to_initiator[1](signal_vci_ini_rw_proc1);
+	ringp.p_to_initiator[2](signal_vci_ini_rw_proc2);
+	ringp.p_to_initiator[3](signal_vci_ini_rw_proc3);
+
+	ringc.p_to_initiator[4](signal_vci_ini_memc);
+	ringc.p_to_initiator[0](signal_vci_ini_c_proc0);
+	ringc.p_to_initiator[1](signal_vci_ini_c_proc1);
+	ringc.p_to_initiator[2](signal_vci_ini_c_proc2);
+	ringc.p_to_initiator[3](signal_vci_ini_c_proc3);
+
+	ringx.p_to_initiator[0](signal_vci_ixr_memc);
+
+	ringp.p_to_target[0](signal_vci_tgt_rom);
+	ringp.p_to_target[1](signal_vci_tgt_tty);
+	ringp.p_to_target[2](signal_vci_tgt_memc);
+
+	ringc.p_to_target[0](signal_vci_tgt_proc0);
+	ringc.p_to_target[1](signal_vci_tgt_proc1);
+	ringc.p_to_target[2](signal_vci_tgt_proc2);
+	ringc.p_to_target[3](signal_vci_tgt_proc3);
+	ringc.p_to_target[4](signal_vci_tgt_cleanup_memc);
+
+	ringx.p_to_target[0](signal_vci_tgt_xram);
+
+	int ncycles;
+
+	if (argc == 2) {
+		ncycles = std::atoi(argv[1]);
+	} else {
+		std::cerr
+			<< std::endl
+			<< "The number of simulation cycles must "
+			   "be defined in the command line"
+			<< std::endl;
+		exit(1);
+	}
+
+	sc_start(sc_core::sc_time(0, SC_NS));
+	signal_resetn = false;
+
+	sc_start(sc_core::sc_time(1, SC_NS));
+	signal_resetn = true;
+
+
+	for (int i = 0; i < ncycles ; i+=1) {
+		sc_start(sc_core::sc_time(1, SC_NS));
+	}
+
+        std::cout << "Hit ENTER to end simulation" << std::endl;
+        char buf[1];
+
+	std::cin.getline(buf,1);
+
+	return EXIT_SUCCESS;
+}
+
+int sc_main (int argc, char *argv[])
+{
+	try {
+		return _main(argc, argv);
+	} catch (std::exception &e) {
+		std::cout << e.what() << std::endl;
+	} catch (...) {
+		std::cout << "Unknown exception occured" << std::endl;
+		throw;
+	}
+	return 1;
+}
Index: branches/v4/platforms/caba-ring-ccxcachev4_memcachev4-mips32el/Makefile
===================================================================
--- branches/v4/platforms/caba-ring-ccxcachev4_memcachev4-mips32el/Makefile	(revision 371)
+++ branches/v4/platforms/caba-ring-ccxcachev4_memcachev4-mips32el/Makefile	(revision 371)
@@ -0,0 +1,10 @@
+#NO_SOFT		=  1
+ARCH			=  mips32el
+#SIMULATION_ARGS	=  
+#SOCLIB_CC_ADD_ARGS	= -t systemc_32
+SOCLIB_CC_ADD_ARGS	= -t systemcass
+SOCLIB			?= $(shell soclib-cc --getpath)
+export SOCLIB
+SOCLIB_TTY		= FILES;
+export SOCLIB_TTY
+include $(SOCLIB)/soclib/platform/topcells/all.mk
Index: branches/v4/platforms/caba-ring-ccxcachev4_memcachev4-mips32el/configuration/default.cfg
===================================================================
--- branches/v4/platforms/caba-ring-ccxcachev4_memcachev4-mips32el/configuration/default.cfg	(revision 371)
+++ branches/v4/platforms/caba-ring-ccxcachev4_memcachev4-mips32el/configuration/default.cfg	(revision 371)
@@ -0,0 +1,6 @@
+2
+4 4
+4 64 16
+4 64 16
+4 8
+16 256 16 4096
Index: branches/v4/platforms/caba-ring-ccxcachev4_memcachev4-mips32el/configuration/gen_config.sh
===================================================================
--- branches/v4/platforms/caba-ring-ccxcachev4_memcachev4-mips32el/configuration/gen_config.sh	(revision 371)
+++ branches/v4/platforms/caba-ring-ccxcachev4_memcachev4-mips32el/configuration/gen_config.sh	(revision 371)
@@ -0,0 +1,100 @@
+#!/bin/bash
+
+#               archi1  archi2  archi3       archi4  archi5 
+archi_name=(    "min"   "tsar"  "full_assoc" "2k"    "4k"   );
+iways=(         "1"     "4"     "16"         "4"     "4"    );
+isets=(         "8"     "64"    "1"          "8"     "16"   );
+iwords=(        "16"    "16"    "16"         "16"    "16"   );
+dways=(         "1"     "4"     "16"         "4"     "4"    );
+dsets=(         "8"     "64"    "1"          "8"     "16"   );
+dwords=(        "16"    "16"    "16"         "16"    "16"   );
+memc_nways=(    "4"     "16"    "8"          "2"     "16"   );
+memc_nsets=(    "4"     "256"   "64"         "32"    "64"   );
+memc_words=(    "16"    "16"    "16"         "16"    "16"   );
+memc_heap_size=("4096"  "4096"  "4096"       "4096"  "4096" );
+
+nb_proc=(        "1" "15"   "+1" "4");
+nb_cpu_by_cache=("1" "15"   "*2" "1");
+nb_cache=(       "1" "16"   "*2" "1");
+#wnwords=(        "1" "16"   "*2" "4");
+#wnlines=(        "1" "8"    "*2" "8");
+
+wnwords=(        "4"  "4"  "*2" "4");
+wnlines=(        "8"  "8"  "*2" "8");
+
+archi_default="1";
+gen_cfg=0;
+
+function gen_file ()
+{
+        filename=$(printf "archi_%s-x%.2d_%.2d_%.2d-wbuf_%.2d_%.2d_%.4d.cfg" ${archi_name[${4}]} ${1} ${2} ${3} ${5} ${6});
+
+        echo ${filename};
+
+        echo "${1}" >  ${filename};
+        echo "${2} ${3}" >> ${filename};
+        echo "${iways[${4}]} ${isets[${4}]} ${iwords[${4}]}" >> ${filename};
+        echo "${dways[${4}]} ${dsets[${4}]} ${dwords[${4}]}" >> ${filename};
+        echo "${5} ${6}" >> ${filename};
+        echo "${memc_nways[${4}]} ${memc_nsets[${4}]} ${memc_words[${4}]} ${memc_heap_size[${4}]}" >> ${filename};
+}
+
+function gen_default ()
+{
+        filename="default.cfg";
+        archi=${1};
+
+        echo ${filename};
+
+        echo "${nb_proc[3]}"  >  ${filename};
+        echo "${nb_cpu_by_cache[3]} ${nb_cache[3]}" >> ${filename};
+        echo "${iways[${archi}]} ${isets[${archi}]} ${iwords[${archi}]}" >> ${filename};
+        echo "${dways[${archi}]} ${dsets[${archi}]} ${dwords[${archi}]}" >> ${filename};
+        echo "${wnwords[3]} ${wnlines[3]}" >> ${filename};
+        echo "${memc_nways[${archi}]} ${memc_nsets[${archi}]} ${memc_words[${archi}]} ${memc_heap_size[${archi}]}" >> ${filename};
+}
+
+gen_default ${archi_default};
+
+if test ${gen_cfg} -ne 0; then
+    nb_archi=${#iways[*]};
+    
+    num_archi=0;
+    while test ${num_archi} -lt ${nb_archi}; do
+        num_proc=${nb_proc[0]};
+        while test ${num_proc} -le ${nb_proc[1]}; do
+            num_cpu_by_cache=${nb_cpu_by_cache[0]};
+            while test ${num_cpu_by_cache} -le ${nb_cpu_by_cache[1]}; do
+
+                if test $((${num_proc} * ${num_cpu_by_cache})) -le ${nb_cpu_by_cache[1]}; then
+
+                num_cache=${nb_cache[0]};
+                while test ${num_cache} -le ${nb_cache[1]}; do
+                
+                    if test ${num_cache} -ge ${num_cpu_by_cache}; then
+                    if test ${num_cpu_by_cache} -ne 1 -o ${num_cache} -eq 1; then
+
+                    num_words=${wnwords[0]};
+                    while test ${num_words} -le ${wnwords[1]}; do
+                        num_lines=${wnlines[0]};
+                        while test ${num_lines} -le ${wnlines[1]}; do
+                            
+                            gen_file ${num_proc} ${num_cpu_by_cache} ${num_cache} ${num_archi} ${num_words} ${num_lines};
+
+                            num_lines=$((${num_lines} ${wnlines[2]}));
+                        done;
+                        num_words=$((${num_words} ${wnwords[2]}));
+                    done;
+                    fi;
+                    fi;
+                    num_cache=$((${num_cache} ${nb_cache[2]}));
+                done;
+                fi;
+                num_cpu_by_cache=$((${num_cpu_by_cache} ${nb_cpu_by_cache[2]}));
+            done;
+            num_proc=$((${num_proc} ${nb_proc[2]}));
+        done;
+        num_archi=$((${num_archi}+1));
+    done;
+fi;
+
Index: branches/v4/platforms/caba-ring-ccxcachev4_memcachev4-mips32el/platform_desc
===================================================================
--- branches/v4/platforms/caba-ring-ccxcachev4_memcachev4-mips32el/platform_desc	(revision 371)
+++ branches/v4/platforms/caba-ring-ccxcachev4_memcachev4-mips32el/platform_desc	(revision 371)
@@ -0,0 +1,28 @@
+
+# -*- python -*-
+
+
+todo = Platform('caba', 'top.cpp',
+	uses = [
+	Uses('caba:vci_cc_xcache_wrapper_v4', iss_t = 'common:gdb_iss', gdb_iss_t = 'common:mips32el'),
+	Uses('caba:vci_simple_ram'),
+        Uses('caba:vci_simhelper'),
+	Uses('caba:vci_multi_tty'),
+	Uses('caba:vci_simple_ring_fast',
+		ring_cmd_data_size = 40,
+		ring_rsp_data_size = 33),
+	Uses('caba:vci_mem_cache_v4'),
+	Uses('common:elf_file_loader'),
+        Uses('caba:vci_xicu'),
+	],
+	cell_size = 4,
+	plen_size = 8,
+	addr_size = 32,
+	rerror_size = 1,
+	clen_size = 1,
+	rflag_size = 1,
+	srcid_size = 8,
+	pktid_size = 4,
+	trdid_size = 4,
+	wrplen_size = 1
+)
Index: branches/v4/platforms/caba-ring-ccxcachev4_memcachev4-mips32el/segmentation.h
===================================================================
--- branches/v4/platforms/caba-ring-ccxcachev4_memcachev4-mips32el/segmentation.h	(revision 371)
+++ branches/v4/platforms/caba-ring-ccxcachev4_memcachev4-mips32el/segmentation.h	(revision 371)
@@ -0,0 +1,58 @@
+
+/////////////////////////////////////////////////////////////////
+//	ADDRESS SPACE SEGMENTATION
+//
+//	This file must be included in the system.cpp file, 
+//	for harware configuration : It is used to build
+//	the SOCLIB_SEGMENT_TABLE.
+//
+//	This file can also be used by the ldscript generator,
+//	for embedded software generation.
+//	
+//	It gives the system integrator the garanty
+//	that hardware and software have the same
+//	description of the address space segmentation.
+/////////////////////////////////////////////////////////////////
+
+/////////////////////////////////////////////////////////////////
+//	reset, and exception segments
+//      base address required by MIPS processor
+/////////////////////////////////////////////////////////////////
+#define	RESET_BASE	0xBFC00000
+#define	RESET_SIZE	0x00010000
+
+#define	EXCEP_BASE	0x80000000
+#define	EXCEP_SIZE	0x00010000
+
+#define	TEXT_BASE	0x00400000
+#define	TEXT_SIZE	0x00050000
+
+/////////////////////////////////////////////////////////////////
+//	global data segment (initialised)
+/////////////////////////////////////////////////////////////////
+
+#define MC_M_BASE	0x10000000
+#define MC_M_SIZE	0x000F0000
+
+#define MC_R_BASE	0x20200000
+#define MC_R_SIZE	0x00000008
+
+#define MC_U_BASE	0x30000000
+#define MC_U_SIZE	0x000F0000
+
+//////////////////////////////////////////////////////////
+//	System devices
+///////////////////////////////////////////////////////////
+
+#define	TTY_BASE	0xC0200000
+#define	TTY_SIZE	0x00000100
+
+#define	XICU_BASE	0xD0200000
+#define	XICU_SIZE	0x00000100
+
+#define	SIMHELPER_BASE  0xF0200000
+#define	SIMHELPER_SIZE	0x00000100
+
+#define C_PROC_BASE	0x01200000
+#define C_PROC_SIZE	0x00000010
+#define C_PROC_SPAN     0x01000000
Index: branches/v4/platforms/caba-ring-ccxcachev4_memcachev4-mips32el/soft/Makefile
===================================================================
--- branches/v4/platforms/caba-ring-ccxcachev4_memcachev4-mips32el/soft/Makefile	(revision 371)
+++ branches/v4/platforms/caba-ring-ccxcachev4_memcachev4-mips32el/soft/Makefile	(revision 371)
@@ -0,0 +1,18 @@
+ADD_OBJS	= 	\
+			$(patsubst self_code_modifying/%.c,self_code_modifying/%.o,$(wildcard self_code_modifying/*.c))  \
+			$(patsubst matrix_multiplication/%.c,matrix_multiplication/%.o,$(wildcard matrix_multiplication/*.c)) \
+			$(patsubst sort/%.c,sort/%.o,$(wildcard sort/*.c)) \
+			$(patsubst dhrystone/%.c,dhrystone/%.o,$(wildcard dhrystone/*.c)) \
+			$(patsubst benchmark/%.c,benchmark/%.o,$(wildcard benchmark/*.c)) \
+			$(patsubst irq/%.c,irq/%.o,$(wildcard irq/*.c)) \
+			$(patsubst common/%.c,common/%.o,$(wildcard common/*.c)) \
+			$(patsubst %.c,%.o,$(wildcard *.c)) \
+			stdio.o stdlib.o exception.o system.o
+
+
+ADD_CFLAGS	=
+ADD_LDFLAGS	=
+SOCLIB		?=	$(shell soclib-cc --getpath)
+
+export SOCLIB
+include $(SOCLIB)/soclib/platform/topcells/soft.mk
Index: branches/v4/platforms/caba-ring-ccxcachev4_memcachev4-mips32el/soft/benchmark/benchmark.c
===================================================================
--- branches/v4/platforms/caba-ring-ccxcachev4_memcachev4-mips32el/soft/benchmark/benchmark.c	(revision 371)
+++ branches/v4/platforms/caba-ring-ccxcachev4_memcachev4-mips32el/soft/benchmark/benchmark.c	(revision 371)
@@ -0,0 +1,95 @@
+#include "benchmark.h"
+#include "system.h"
+#include "stdio.h"
+#include "../common/common.h"
+
+void benchmark (void)
+{
+  int result      = 0;
+  int num_cpu     = procnum();
+  int cycle_begin = cycle_begin = cpu_cycles();
+  
+  if (num_cpu < BENCHMARK_NB_THREAD)
+   switch (num_cpu)
+     {
+     default :
+        {
+#if BENCHMARK_MATRIX_MULTIPLICATION_MT
+          int result_mm_mt = benchmark_matrix_multiplication_mt();
+          result += result_mm_mt;
+#endif
+#if BENCHMARK_DHRYSTONE
+          int result_dhrystone = benchmark_dhrystone();
+          result += result_dhrystone;
+#endif
+#if BENCHMARK_SORT_ALL
+          int result_sort_all = benchmark_sort_all();
+          result += result_sort_all;
+#endif
+#if BENCHMARK_SORT_BUBBLE
+          int result_sort_bubble = benchmark_sort_bubble();
+          result += result_sort_bubble;
+#endif
+#if BENCHMARK_SORT_INSERTION
+          int result_sort_insertion = benchmark_sort_insertion();
+          result += result_sort_insertion;
+#endif
+#if BENCHMARK_SORT_SELECTION
+          int result_sort_selection = benchmark_sort_selection();
+          result += result_sort_selection;
+#endif
+#if BENCHMARK_SORT_SHELL
+          int result_sort_shell = benchmark_sort_shell();
+          result += result_sort_shell;
+#endif
+#if BENCHMARK_MATRIX_MULTIPLICATION_ST
+          int result_mm_st = benchmark_matrix_multiplication_st();
+          result += result_mm_st;
+#endif
+#if BENCHMARK_SELF_CODE_MODIFYING
+          int result_self_code_modifying = benchmark_self_code_modifying();
+          result += result_self_code_modifying;
+#endif
+          
+          printf("\n");
+          printf("--------------------------------\n");
+          printf( "Partial results :\n");
+#if BENCHMARK_MATRIX_MULTIPLICATION_MT
+          printf(" * MM MT               : %d\n",result_mm_mt);
+#endif
+#if BENCHMARK_DHRYSTONE
+          printf(" * DHRYSTONE           : %d\n",result_dhrystone);
+#endif
+#if BENCHMARK_SORT_ALL
+          printf(" * SORT_ALL            : %d\n",result_sort_all);
+#endif
+#if BENCHMARK_SORT_BUBBLE
+          printf(" * SORT_BUBBLE         : %d\n",result_sort_bubble);
+#endif
+#if BENCHMARK_SORT_INSERTION
+          printf(" * SORT_INSERTION      : %d\n",result_sort_insertion);
+#endif
+#if BENCHMARK_SORT_SELECTION
+          printf(" * SORT_SELECTION      : %d\n",result_sort_selection);
+#endif
+#if BENCHMARK_SORT_SHELL
+          printf(" * SORT_SHELL          : %d\n",result_sort_shell);
+#endif
+#if BENCHMARK_MATRIX_MULTIPLICATION_ST
+          printf(" * MM ST               : %d\n",result_mm_st);
+#endif 
+#if BENCHMARK_SELF_CODE_MODIFYING
+          printf(" * SELF_CODE_MODIFYING : %d\n",result_self_code_modifying);
+#endif
+          printf("--------------------------------\n");
+          break;
+        }
+      }
+
+  printf("\n");
+  printf("================================\n");
+  printf( "Results :\n");
+  printf( " * Score           : %d\n", result);
+  printf( " * Total CPU Cycle : %d\n", cpu_cycles()-cycle_begin);
+  printf("================================\n");
+}
Index: branches/v4/platforms/caba-ring-ccxcachev4_memcachev4-mips32el/soft/benchmark/benchmark.h
===================================================================
--- branches/v4/platforms/caba-ring-ccxcachev4_memcachev4-mips32el/soft/benchmark/benchmark.h	(revision 371)
+++ branches/v4/platforms/caba-ring-ccxcachev4_memcachev4-mips32el/soft/benchmark/benchmark.h	(revision 371)
@@ -0,0 +1,16 @@
+#ifndef benchmark_h
+#define benchmark_h
+
+#include "../define.h"
+
+void benchmark                         (void);
+int  benchmark_sort_all                (void);
+int  benchmark_sort_bubble             (void);
+int  benchmark_sort_insert             (void);
+int  benchmark_sort_selection          (void);
+int  benchmark_sort_shell              (void);
+int  benchmark_dhrystone               (void);
+int  benchmark_matrix_multiplication_st(void);
+int  benchmark_matrix_multiplication_mt(void);
+
+#endif //benchmark_h
Index: branches/v4/platforms/caba-ring-ccxcachev4_memcachev4-mips32el/soft/benchmark/benchmark_dhrystone.c
===================================================================
--- branches/v4/platforms/caba-ring-ccxcachev4_memcachev4-mips32el/soft/benchmark/benchmark_dhrystone.c	(revision 371)
+++ branches/v4/platforms/caba-ring-ccxcachev4_memcachev4-mips32el/soft/benchmark/benchmark_dhrystone.c	(revision 371)
@@ -0,0 +1,31 @@
+#include "benchmark.h"
+#include "system.h"
+#include "stdlib.h"
+#include "stdio.h"
+#include "../dhrystone/dhry21.h"
+
+static uint32_t nb_thread;
+
+int _benchmark_dhrystone (unsigned int nb_runs)
+{
+  printf("\n");
+  printf("================================\n");
+  printf("Benchmark Dhrystone\n");
+  printf("================================\n");
+  printf("\n");
+
+  int result = 0;
+  
+  if (atomic_inc(&nb_thread) == 1)
+    {
+      result = dhry21(nb_runs);
+    }
+  else
+    {
+      printf("The dhrystone benchmark is not multi threaded.\n");
+    }
+    
+  return result;
+}
+
+int benchmark_dhrystone (void) { return _benchmark_dhrystone(DHRYSTONE_NB_RUNS); }
Index: branches/v4/platforms/caba-ring-ccxcachev4_memcachev4-mips32el/soft/benchmark/benchmark_matrix_multiplication.c
===================================================================
--- branches/v4/platforms/caba-ring-ccxcachev4_memcachev4-mips32el/soft/benchmark/benchmark_matrix_multiplication.c	(revision 371)
+++ branches/v4/platforms/caba-ring-ccxcachev4_memcachev4-mips32el/soft/benchmark/benchmark_matrix_multiplication.c	(revision 371)
@@ -0,0 +1,262 @@
+#include "benchmark.h"
+#include "system.h"
+#include "stdlib.h"
+#include "stdio.h"
+#include "stdint.h"
+#include "../matrix_multiplication/matrix_multiplication.h"
+#include "../common/common.h"
+
+static uint32_t matrix_lock;
+
+void benchmark_matrix_malloc (int ** matrix_a,
+                              int ** matrix_b,
+                              int ** matrix_d,
+                              int    size)
+{
+  int i;
+  
+  for (i=0; i<size; ++i)
+    {
+      matrix_a[i] = (int*) malloc(size*sizeof(int));
+      matrix_b[i] = (int*) malloc(size*sizeof(int));
+      matrix_d[i] = (int*) malloc(size*sizeof(int));
+    }
+}
+
+void benchmark_matrix_free (int ** matrix_a,
+                            int ** matrix_b,
+                            int ** matrix_d,
+                            int    size)
+{
+  int i;
+  
+  for (i=0; i<size; ++i)
+    {
+      free(matrix_a[i]);
+      free(matrix_b[i]);
+      free(matrix_d[i]);
+    }
+}
+
+void benchmark_matrix_init (int ** matrix_a,
+                            int ** matrix_b,
+                            int    size)
+{
+  int i,j,x;
+
+  x = 0;
+  for (i=0; i<size; ++i)
+    for (j=0; j<size; ++j)
+      {
+        matrix_a [i][j] = x;
+        matrix_b [j][i] = x;
+        x++;
+      }
+}
+
+void benchmark_matrix_validation (int ** matrix_d,
+                                  int    size)
+{
+  int i,j,x;
+  int error = 0;
+
+  for (i=0; (i<size)&&(error==0); ++i)
+    for (j=0; (j<size)&&(error==0); ++j)
+      {
+        int val = 0;
+        for (x=0; x<size; ++x)
+          val += (i*size+x)*(j*size+x);
+        
+        if (matrix_d[i][j] != val)
+          {
+            error = 1;
+            printf("KO !!! (matrix_d[%d][%d] = %d (!= %d))\n",i,j,matrix_d[i][j],val);
+          }
+      }
+
+  if (error == 0)
+    printf("OK\n");
+}
+
+int _benchmark_matrix_multiplication_st (unsigned int size)
+{
+  printf("\n");
+  printf("================================\n");
+  printf("Benchmark Matrix Multiplication (ST)\n");
+  printf("================================\n");
+  printf("\n");
+
+  printf(" * Size : %d\n",size);
+  
+  int cycle_begin, result;
+
+  result = 0;
+
+  printf(" * Malloc...\n");
+
+  lock_lock(&matrix_lock);
+
+  int ** matrix_local_a = (int**) malloc(size*sizeof(int*));
+  int ** matrix_local_b = (int**) malloc(size*sizeof(int*));
+  int ** matrix_local_d = (int**) malloc(size*sizeof(int*));
+
+  benchmark_matrix_malloc (matrix_local_a,
+                           matrix_local_b,
+                           matrix_local_d,
+                           size);
+  lock_unlock(&matrix_lock);
+  
+  printf(" * Init...\n");
+
+  benchmark_matrix_init (matrix_local_a,
+                         matrix_local_b,
+                         size);
+  
+  /* matrix_multiplication_print(matrix_local_a, size); */
+  /* matrix_multiplication_print(matrix_local_b, size); */
+ 
+  printf(" * Matrix multiplication (size : %d)... \n",size);
+
+  cycle_begin = cpu_cycles();
+  matrix_multiplication_st(matrix_local_a,
+                           matrix_local_b,
+                           matrix_local_d,
+                           size);
+  result += cpu_cycles()-cycle_begin;
+
+  /* matrix_multiplication_print(matrix_local_d, size); */
+  
+#if VERIFICATION_MATRIX_MULTIPLICATION
+  printf(" * Verification... ");
+  
+  benchmark_matrix_validation (matrix_local_d, size);
+#endif
+  
+  printf(" * Free...\n");
+  
+  benchmark_matrix_free (matrix_local_a,
+                         matrix_local_b,
+                         matrix_local_d,
+                         size);
+  
+  free(matrix_local_a);
+  free(matrix_local_b);
+  free(matrix_local_d);
+
+  return result;
+}
+
+static int ** matrix_global_a;
+static int ** matrix_global_b;
+static int ** matrix_global_d;
+
+static int matrix_nb_thread_start;
+static int matrix_nb_thread_stop;
+static int matrix_end;
+
+int _benchmark_matrix_multiplication_mt (int size, int lock_by_line)
+{
+  printf("\n");
+  printf("================================\n");
+  printf("Benchmark Matrix Multiplication (MT)\n");
+  printf("================================\n");
+  printf("\n");
+  
+  printf(" * Size         : %d\n",size);
+  printf(" * Lock by line : %d\n",lock_by_line);
+  
+  int cycle_begin, result;
+
+  result = 0;
+
+  lock_lock(&matrix_lock);
+
+  if (matrix_end != 0)
+    {
+      printf("Benchmark is already finished\n");
+
+      lock_unlock(&matrix_lock);
+      
+      return 0;
+    }
+      
+  printf(" * Start number %d\n",matrix_nb_thread_start);
+  
+  // first thread
+  if (matrix_nb_thread_start==0)
+    {
+      printf(" * Malloc...\n");
+
+      matrix_global_a = (int**) malloc(size*sizeof(int*));
+      matrix_global_b = (int**) malloc(size*sizeof(int*));
+      matrix_global_d = (int**) malloc(size*sizeof(int*));
+
+      benchmark_matrix_malloc (matrix_global_a,
+                               matrix_global_b,
+                               matrix_global_d,
+                               size);
+           
+      printf(" * Init...\n");
+
+      benchmark_matrix_init (matrix_global_a,
+                             matrix_global_b,
+                             size);
+    }
+
+  matrix_nb_thread_start ++;
+
+  lock_unlock(&matrix_lock);
+  
+  /* matrix_multiplication_print(matrix_global_a, size); */
+  /* matrix_multiplication_print(matrix_global_b, size); */
+ 
+  printf(" * Matrix multiplication (size : %d)... \n",size);
+
+  cycle_begin = cpu_cycles();
+  matrix_multiplication_mt(matrix_global_a,
+                           matrix_global_b,
+                           matrix_global_d,
+                           size,
+                           lock_by_line);
+  result += cpu_cycles()-cycle_begin;
+
+  /* matrix_multiplication_print(matrix_global_d, size); */
+
+  lock_lock(&matrix_lock);
+
+  printf(" * Stop number %d\n",matrix_nb_thread_stop);
+  
+  matrix_nb_thread_stop ++;
+    
+  // first thread
+  if (matrix_nb_thread_stop == matrix_nb_thread_start)
+    {
+#if VERIFICATION_MATRIX_MULTIPLICATION
+      printf(" * Verification... ");
+
+      benchmark_matrix_validation (matrix_global_d, size);
+#endif
+      
+      printf(" * Free...\n");
+   
+      benchmark_matrix_free (matrix_global_a,
+                             matrix_global_b,
+                             matrix_global_d,
+                             size);
+      
+      free(matrix_global_a);
+      free(matrix_global_b);
+      free(matrix_global_d);
+
+      matrix_end = 1;
+    }
+
+  lock_unlock(&matrix_lock);
+  
+  return result;
+}
+
+int benchmark_matrix_multiplication_st (void) { return _benchmark_matrix_multiplication_st (MATRIX_MULTIPLICATION_ST_SIZE);}
+int benchmark_matrix_multiplication_mt (void) { return _benchmark_matrix_multiplication_mt (MATRIX_MULTIPLICATION_MT_SIZE,MATRIX_MULTIPLICATION_MT_LOCK_BY_LINE);}
+
+
Index: branches/v4/platforms/caba-ring-ccxcachev4_memcachev4-mips32el/soft/benchmark/benchmark_self_code_modifying.c
===================================================================
--- branches/v4/platforms/caba-ring-ccxcachev4_memcachev4-mips32el/soft/benchmark/benchmark_self_code_modifying.c	(revision 371)
+++ branches/v4/platforms/caba-ring-ccxcachev4_memcachev4-mips32el/soft/benchmark/benchmark_self_code_modifying.c	(revision 371)
@@ -0,0 +1,31 @@
+#include "benchmark.h"
+#include "system.h"
+#include "stdlib.h"
+#include "stdio.h"
+#include "../self_code_modifying/self_code_modifying.h"
+
+static uint32_t nb_thread;
+
+int _benchmark_self_code_modifying (unsigned int nb_runs)
+{
+  printf("\n");
+  printf("================================\n");
+  printf("Benchmark Self_Code_Modifying\n");
+  printf("================================\n");
+  printf("\n");
+
+  int result = 0;
+  
+  if (atomic_inc(&nb_thread) == 1)
+    {
+      result = self_code_modifying(nb_runs);
+    }
+  else
+    {
+      printf("The self_code_modifying benchmark is not multi threaded.\n");
+    }
+    
+  return result;
+}
+
+int benchmark_self_code_modifying (void) { return _benchmark_self_code_modifying(SELF_CODE_MODIFYING_NB_RUNS); }
Index: branches/v4/platforms/caba-ring-ccxcachev4_memcachev4-mips32el/soft/benchmark/benchmark_sort.c
===================================================================
--- branches/v4/platforms/caba-ring-ccxcachev4_memcachev4-mips32el/soft/benchmark/benchmark_sort.c	(revision 371)
+++ branches/v4/platforms/caba-ring-ccxcachev4_memcachev4-mips32el/soft/benchmark/benchmark_sort.c	(revision 371)
@@ -0,0 +1,103 @@
+#include "benchmark.h"
+#include "system.h"
+#include "stdlib.h"
+#include "stdio.h"
+#include "stdint.h"
+#include "../sort/sort.h"
+#include "../common/common.h"
+
+static uint32_t sort_lock;
+
+int _benchmark_sort (sort_t sort_type,
+                     unsigned int size)
+{
+  printf(" * Size : %d\n",size);
+
+  unsigned int* SortArray;
+  
+  int cycle_begin;
+
+  int num_cpu=procnum();
+  
+  printf(" * Algo : %s\n",sort_str(sort_type));
+  
+  printf("   * Init...\n");
+  
+  lock_lock(&sort_lock);
+  SortArray = (unsigned int*) malloc(size*sizeof(unsigned int));
+  lock_unlock(&sort_lock);
+  
+  unsigned int seed = num_cpu;
+  int i;
+  for (i=0; i<size; ++i)
+    {
+      seed = seed * 1103515245 + 12345;
+      SortArray[i] = seed&0xff;
+    }
+  printf("   * Sort... \n");
+  
+  cycle_begin = cpu_cycles();
+  sort((unsigned int *) (SortArray), (unsigned int) size, sort_type);
+  int cycle_exec = cpu_cycles()-cycle_begin;
+  
+  printf("   * Executed in %d cycles\n",cycle_exec);
+  
+  int result = cycle_exec;
+  
+#if VERIFICATION_SORT      
+  printf("   * Verification... ");
+  
+  for (i = 1; i < size; i++)
+    {
+      /* printf("%d ",SortArray[i-1]); */
+      
+      if (SortArray[i] < SortArray[i-1])
+        {
+          printf("KO !!!\n");
+          EXIT(1);
+        }
+    }
+  printf("OK\n");
+#endif
+  
+  free (SortArray);
+
+  return result;
+}
+
+int _benchmark_sort_all (unsigned int size)
+{
+  printf("\n");
+  printf("================================\n");
+  printf("Benchmark Sort (ALL)\n");
+  printf("================================\n");
+  printf("\n");
+
+  int result = 0;
+  int num_cpu=procnum();
+  sort_t _sort_type;
+  const sort_t nb_sort_type = 4;
+  
+  for (_sort_type=0; _sort_type < nb_sort_type; _sort_type++)
+    result += _benchmark_sort((_sort_type+num_cpu)%nb_sort_type,size);
+  
+  return result;
+}
+
+int _benchmark_sort_one (sort_t sort_type,
+                         unsigned int size)
+{
+  printf("\n");
+  printf("================================\n");
+  printf("Benchmark Sort\n");
+  printf("================================\n");
+  printf("\n");
+
+  return _benchmark_sort(sort_type,size);
+}
+
+int benchmark_sort_all       (void) { return _benchmark_sort_all(SORT_ALL_SIZE); }
+int benchmark_sort_bubble    (void) { return _benchmark_sort_one(SORT_BUBBLE   ,SORT_BUBBLE_SIZE   ); }
+int benchmark_sort_insertion (void) { return _benchmark_sort_one(SORT_INSERTION,SORT_INSERTION_SIZE); }
+int benchmark_sort_selection (void) { return _benchmark_sort_one(SORT_SELECTION,SORT_SELECTION_SIZE); }
+int benchmark_sort_shell     (void) { return _benchmark_sort_one(SORT_SHELL    ,SORT_SHELL_SIZE    ); }
Index: branches/v4/platforms/caba-ring-ccxcachev4_memcachev4-mips32el/soft/common/common.c
===================================================================
--- branches/v4/platforms/caba-ring-ccxcachev4_memcachev4-mips32el/soft/common/common.c	(revision 371)
+++ branches/v4/platforms/caba-ring-ccxcachev4_memcachev4-mips32el/soft/common/common.c	(revision 371)
@@ -0,0 +1,47 @@
+#include "common.h"
+#include "stdio.h"
+#include "system.h"
+#include "stdio.h"
+
+#ifdef SIMHELPER_BASE
+#include "soclib/simhelper.h"
+#endif
+
+static uint32_t lock;
+static uint32_t nb_thread;
+
+void system_start (void)
+{
+  lock_lock(&lock);
+  nb_thread ++;
+  lock_unlock(&lock);
+
+  printf("CPU %d\n",procnum());
+}
+
+void system_stop (char* file, int line, int x)
+{
+  printf("Exit(%d) in file \"%s\", line %d\n",x,file,line);
+
+  lock_lock(&lock);
+  uint32_t num_thread = --nb_thread;
+  lock_unlock(&lock);
+
+  // Last thread ?
+  if (num_thread == 0)
+    {
+#ifdef SIMHELPER_BASE
+      soclib_io_set
+        (base(SIMHELPER),
+         SIMHELPER_SC_STOP,
+         0);
+#else
+# warning "No simhelper, exit will do a trap and an infinite loop"
+#endif
+    }
+
+  pause();
+  
+  while(1);
+}
+
Index: branches/v4/platforms/caba-ring-ccxcachev4_memcachev4-mips32el/soft/common/common.h
===================================================================
--- branches/v4/platforms/caba-ring-ccxcachev4_memcachev4-mips32el/soft/common/common.h	(revision 371)
+++ branches/v4/platforms/caba-ring-ccxcachev4_memcachev4-mips32el/soft/common/common.h	(revision 371)
@@ -0,0 +1,9 @@
+#ifndef common_h
+#define common_h
+
+#define EXIT(x) system_stop(__FILE__,__LINE__,x)
+
+void system_start (void);
+void system_stop  (char* file, int line, int x);
+
+#endif // common_h
Index: branches/v4/platforms/caba-ring-ccxcachev4_memcachev4-mips32el/soft/define.h
===================================================================
--- branches/v4/platforms/caba-ring-ccxcachev4_memcachev4-mips32el/soft/define.h	(revision 371)
+++ branches/v4/platforms/caba-ring-ccxcachev4_memcachev4-mips32el/soft/define.h	(revision 371)
@@ -0,0 +1,38 @@
+#ifndef define_h
+#define define_h
+
+// List of benchmark
+#define BENCHMARK_NB_THREAD                   8
+
+#define BENCHMARK_DHRYSTONE                   0
+#define BENCHMARK_SORT_ALL                    0
+#define BENCHMARK_SORT_BUBBLE                 0
+#define BENCHMARK_SORT_INSERTION              0
+#define BENCHMARK_SORT_SELECTION              0
+#define BENCHMARK_SORT_SHELL                  0
+#define BENCHMARK_MATRIX_MULTIPLICATION_ST    0
+#define BENCHMARK_MATRIX_MULTIPLICATION_MT    1
+#define BENCHMARK_SELF_CODE_MODIFYING         0
+
+#define VERBOSE_SORT                          0
+
+#define VERIFICATION_SORT                     0
+#define VERIFICATION_MATRIX_MULTIPLICATION    0
+
+// Benchmark size
+#define DHRYSTONE_NB_RUNS                     5000
+#define SORT_ALL_SIZE                         1000
+#define SORT_BUBBLE_SIZE                      1500
+#define SORT_INSERTION_SIZE                   2300
+#define SORT_SELECTION_SIZE                   1600
+#define SORT_SHELL_SIZE                       5000
+#define MATRIX_MULTIPLICATION_ST_SIZE         50
+#define MATRIX_MULTIPLICATION_MT_SIZE         75
+#define MATRIX_MULTIPLICATION_MT_LOCK_BY_LINE 1
+#define SELF_CODE_MODIFYING_NB_RUNS           10
+
+// Timer configuration
+#define TIMER_INTERRUPT                       0
+#define TIMER_INTERRUPT_PERIOD                100000
+
+#endif // define_h
Index: branches/v4/platforms/caba-ring-ccxcachev4_memcachev4-mips32el/soft/dhrystone/dhry.h
===================================================================
--- branches/v4/platforms/caba-ring-ccxcachev4_memcachev4-mips32el/soft/dhrystone/dhry.h	(revision 371)
+++ branches/v4/platforms/caba-ring-ccxcachev4_memcachev4-mips32el/soft/dhrystone/dhry.h	(revision 371)
@@ -0,0 +1,414 @@
+/*
+ *************************************************************************
+ *
+ *                   "DHRYSTONE" Benchmark Program
+ *                   -----------------------------
+ *
+ *  Version:    C, Version 2.1
+ *
+ *  File:       dhry.h (part 1 of 3)
+ *
+ *  Date:       May 25, 1988
+ *
+ *  Author:     Reinhold P. Weicker
+ *              Siemens Nixdorf Inf. Syst.
+ *              STM OS 32
+ *              Otto-Hahn-Ring 6
+ *              W-8000 Muenchen 83
+ *              Germany
+ *                      Phone:    [+49]-89-636-42436
+ *                                (8-17 Central European Time)
+ *                      UUCP:     weicker@ztivax.uucp@unido.uucp
+ *                      Internet: weicker@ztivax.siemens.com
+ *
+ *              Original Version (in Ada) published in
+ *              "Communications of the ACM" vol. 27., no. 10 (Oct. 1984),
+ *              pp. 1013 - 1030, together with the statistics
+ *              on which the distribution of statements etc. is based.
+ *
+ *              In this C version, the following C library functions are
+ *              used:
+ *              - strcpy, strcmp (inside the measurement loop)
+ *              - printf, scanf (outside the measurement loop)
+ *
+ *  Collection of Results:
+ *              Reinhold Weicker (address see above) and
+ *              
+ *              Rick Richardson
+ *              PC Research. Inc.
+ *              94 Apple Orchard Drive
+ *              Tinton Falls, NJ 07724
+ *                      Phone:  (201) 834-1378 (9-17 EST)
+ *                      UUCP:   ...!uunet!pcrat!rick
+ *
+ *      Please send results to Rick Richardson and/or Reinhold Weicker.
+ *      Complete information should be given on hardware and software
+ *      used. Hardware information includes: Machine type, CPU, type and
+ *      size of caches; for microprocessors: clock frequency, memory speed
+ *      (number of wait states). Software information includes: Compiler
+ *      (and runtime library) manufacturer and version, compilation
+ *      switches, OS version. The Operating System version may give an
+ *      indication about the compiler; Dhrystone itself performs no OS
+ *      calls in the measurement loop.
+ *
+ *      The complete output generated by the program should be mailed
+ *      such that at least some checks for correctness can be made.
+ *
+ *************************************************************************
+ *
+ *  History:    This version C/2.1 has been made for two reasons:
+ *
+ *              1) There is an obvious need for a common C version of
+ *              Dhrystone, since C is at present the most popular system
+ *              programming language for the class of processors
+ *              (microcomputers, minicomputers) where Dhrystone is used
+ *              most. There should be, as far as possible, only one C
+ *              version of Dhrystone such that results can be compared
+ *              without restrictions. In the past, the C versions
+ *              distributed by Rick Richardson (Version 1.1) and by
+ *              Reinhold Weicker had small (though not significant)
+ *              differences.
+ *
+ *              2) As far as it is possible without changes to the
+ *              Dhrystone statistics, optimizing compilers should be
+ *              prevented from removing significant statements.
+ *
+ *              This C version has been developed in cooperation with
+ *              Rick Richardson (Tinton Falls, NJ), it incorporates many
+ *              ideas from the "Version 1.1" distributed previously by
+ *              him over the UNIX network Usenet.
+ *              I also thank Chaim Benedelac (National Semiconductor),
+ *              David Ditzel (SUN), Earl Killian and John Mashey (MIPS),
+ *              Alan Smith and Rafael Saavedra-Barrera (UC at Berkeley)
+ *              for their help with comments on earlier versions of the
+ *              benchmark.
+ *
+ *  Changes:    In the initialization part, this version follows mostly
+ *              Rick Richardson's version distributed via Usenet, not the
+ *              version distributed earlier via floppy disk by Reinhold
+ *              Weicker. As a concession to older compilers, names have
+ *              been made unique within the first 8 characters. Inside the
+ *              measurement loop, this version follows the version
+ *              previously distributed by Reinhold Weicker.
+ *
+ *              At several places in the benchmark, code has been added,
+ *              but within the measurement loop only in branches that
+ *              are not executed. The intention is that optimizing
+ *              compilers should be prevented from moving code out of the
+ *              measurement loop, or from removing code altogether. Since
+ *              the statements that are executed within the measurement
+ *              loop have NOT been changed, the numbers defining the
+ *              "Dhrystone distribution" (distribution of statements,
+ *              operand types and locality) still hold. Except for
+ *              sophisticated optimizing compilers, execution times for
+ *              this version should be the same as for previous versions.
+ *
+ *              Since it has proven difficult to subtract the time for the
+ *              measurement loop overhead in a correct way, the loop check
+ *              has been made a part of the benchmark. This does have
+ *              an impact - though a very minor one - on the distribution
+ *              statistics which have been updated for this version.
+ *
+ *              All changes within the measurement loop are described
+ *              and discussed in the companion paper "Rationale for
+ *              Dhrystone version 2".
+ *
+ *              Because of the self-imposed limitation that the order and
+ *              distribution of the executed statements should not be
+ *              changed, there are still cases where optimizing compilers
+ *              may not generate code for some statements. To a certain
+ *              degree, this is unavoidable for small synthetic
+ *              benchmarks. Users of the benchmark are advised to check
+ *              code listings whether code is generated for all statements
+ *              of Dhrystone.
+ *
+ *              Version 2.1 is identical to version 2.0 distributed via
+ *              the UNIX network Usenet in March 1988 except that it
+ *              corrects some minor deficiencies that were found by users
+ *              of version 2.0. The only change within the measurement
+ *              loop is that a non-executed "else" part was added to the
+ *              "if" statement in Func_3, and a non-executed "else" part
+ *              removed from Proc_3.
+ *
+ *************************************************************************
+ *
+ * Defines:     The following "Defines" are possible:
+ *              -DROPT         (default: Not defined)
+ *                      As an approximation to what an average C
+ *                      programmer might do, the "register" storage class
+ *                      is applied (if enabled by -DROPT)
+ *                      - for local variables, if they are used
+ *                        (dynamically) five or more times
+ *                      - for parameters if they are used (dynamically)
+ *                        six or more times
+ *                      Note that an optimal "register" strategy is
+ *                      compiler-dependent, and that "register"
+ *                      declarations do not necessarily lead to faster
+ *                      execution.
+ *              -DNOSTRUCTASSIGN        (default: Not defined)
+ *                      Define if the C compiler does not support
+ *                      assignment of structures.
+ *              -DNOENUMS               (default: Not defined)
+ *                      Define if the C compiler does not support
+ *                      enumeration types.
+ *
+ *************************************************************************
+ *
+ *  Compilation model and measurement (IMPORTANT):
+ *
+ *  This C version of Dhrystone consists of three files:
+ *  - dhry.h (this file, containing global definitions and comments)
+ *  - dhry_1.c (containing the code corresponding to Ada package Pack_1)
+ *  - dhry_2.c (containing the code corresponding to Ada package Pack_2)
+ *
+ *  The following "ground rules" apply for measurements:
+ *  - Separate compilation
+ *  - No procedure merging
+ *  - Otherwise, compiler optimizations are allowed but should be
+ *    indicated
+ *  - Default results are those without register declarations
+ *  See the companion paper "Rationale for Dhrystone Version 2" for a more
+ *  detailed discussion of these ground rules.
+ *
+ *  For 16-Bit processors (e.g. 80186, 80286), times for all compilation
+ *  models ("small", "medium", "large" etc.) should be given if possible,
+ *  together with a definition of these models for the compiler system
+ *  used.
+ *
+ *************************************************************************
+ *
+ *  Dhrystone (C version) statistics:
+ *
+ *  [Comment from the first distribution, updated for version 2.
+ *   Note that because of language differences, the numbers are slightly
+ *   different from the Ada version.]
+ *
+ *  The following program contains statements of a high level programming
+ *  language (here: C) in a distribution considered representative:
+ *
+ *    assignments                  52 (51.0 %)
+ *    control statements           33 (32.4 %)
+ *    procedure, function calls    17 (16.7 %)
+ *
+ *  103 statements are dynamically executed. The program is balanced with
+ *  respect to the three aspects:
+ *
+ *    - statement type
+ *    - operand type
+ *    - operand locality
+ *         operand global, local, parameter, or constant.
+ *
+ *  The combination of these three aspects is balanced only approximately.
+ *
+ *  1. Statement Type:
+ *  -----------------             number
+ *
+ *     V1 = V2                     9
+ *       (incl. V1 = F(..)
+ *     V = Constant               12
+ *     Assignment,                 7
+ *       with array element
+ *     Assignment,                 6
+ *       with record component
+ *                                --
+ *                                34       34
+ *
+ *     X = Y +|-|"&&"|"|" Z        5
+ *     X = Y +|-|"==" Constant     6
+ *     X = X +|- 1                 3
+ *     X = Y *|/ Z                 2
+ *     X = Expression,             1
+ *           two operators
+ *     X = Expression,             1
+ *           three operators
+ *                                --
+ *                                18       18
+ *
+ *     if ....                    14
+ *       with "else"      7
+ *       without "else"   7
+ *           executed        3
+ *           not executed    4
+ *     for ...                     7  |  counted every time
+ *     while ...                   4  |  the loop condition
+ *     do ... while                1  |  is evaluated
+ *     switch ...                  1
+ *     break                       1
+ *     declaration with            1
+ *       initialization
+ *                                --
+ *                                34       34
+ *
+ *     P (...)  procedure call    11
+ *       user procedure      10
+ *       library procedure    1
+ *     X = F (...)
+ *             function  call      6
+ *       user function        5
+ *       library function     1
+ *                                --
+ *                                17       17
+ *                                        ---
+ *                                        103
+ *
+ *    The average number of parameters in procedure or function calls
+ *    is 1.82 (not counting the function values as implicit parameters).
+ *
+ *
+ *  2. Operators
+ *  ------------
+ *                          number    approximate
+ *                                    percentage
+ *
+ *    Arithmetic             32          50.8
+ *
+ *       +                     21          33.3
+ *       -                      7          11.1
+ *       *                      3           4.8
+ *       / (int div)            1           1.6
+ *
+ *    Comparison             27           42.8
+ *
+ *       ==                     9           14.3
+ *       /=                     4            6.3
+ *       >                      1            1.6
+ *       <                      3            4.8
+ *       >=                     1            1.6
+ *       <=                     9           14.3
+ *
+ *    Logic                   4            6.3
+ *
+ *       && (AND-THEN)          1            1.6
+ *       |  (OR)                1            1.6
+ *       !  (NOT)               2            3.2
+ * 
+ *                           --          -----
+ *                           63          100.1
+ *
+ *
+ *  3. Operand Type (counted once per operand reference):
+ *  ---------------
+ *                          number    approximate
+ *                                    percentage
+ *
+ *     Integer               175        72.3 %
+ *     Character              45        18.6 %
+ *     Pointer                12         5.0 %
+ *     String30                6         2.5 %
+ *     Array                   2         0.8 %
+ *     Record                  2         0.8 %
+ *                           ---       -------
+ *                           242       100.0 %
+ *
+ *  When there is an access path leading to the final operand (e.g. a
+ *  record component), only the final data type on the access path is
+ *  counted.
+ *
+ *
+ *  4. Operand Locality:
+ *  -------------------
+ *                                number    approximate
+ *                                          percentage
+ *
+ *     local variable              114        47.1 %
+ *     global variable              22         9.1 %
+ *     parameter                    45        18.6 %
+ *        value                        23         9.5 %
+ *        reference                    22         9.1 %
+ *     function result               6         2.5 %
+ *     constant                     55        22.7 %
+ *                                 ---       -------
+ *                                 242       100.0 %
+ *
+ *
+ *  The program does not compute anything meaningful, but it is
+ *  syntactically and semantically correct. All variables have a value
+ *  assigned to them before they are used as a source operand.
+ *
+ *  There has been no explicit effort to account for the effects of a
+ *  cache, or to balance the use of long or short displacements for code
+ *  or data.
+ *
+ *************************************************************************
+ */
+
+#ifndef DHRY_H
+#define DHRY_H
+
+/* Compiler and system dependent definitions: */
+
+#define VERBOSE
+//#define HAVE_DOUBLE
+//#define GENERATE_RESULT_FILE
+
+#ifdef HAVE_DOUBLE
+# define DOUBLE float
+# define Mic_secs_Per_Second     1000000.0
+#else
+# define DOUBLE unsigned int
+# define Mic_secs_Per_Second     1000000
+#endif
+
+DOUBLE dtime ();
+
+                /* Berkeley UNIX C returns process times in seconds/HZ */
+
+#ifdef  NOSTRUCTASSIGN
+#define structassign(d, s)      memcpy(&(d), &(s), sizeof(d))
+#else
+#define structassign(d, s)      d = s
+#endif
+
+#ifdef  NOENUM
+#define Ident_1 0
+#define Ident_2 1
+#define Ident_3 2
+#define Ident_4 3
+#define Ident_5 4
+  typedef int   Enumeration;
+#else
+  typedef       enum    {Ident_1, Ident_2, Ident_3, Ident_4, Ident_5}
+                Enumeration;
+#endif
+        /* for boolean and enumeration types in Ada, Pascal */
+
+/* General definitions: */
+
+#include <stdio.h>
+                /* for strcpy, strcmp */
+
+#define Null 0 
+                /* Value of a Null pointer */
+#define true  1
+#define false 0
+
+typedef int     One_Thirty;
+typedef int     One_Fifty;
+typedef char    Capital_Letter;
+typedef int     Boolean;
+typedef char    Str_30 [31];
+typedef int     Arr_1_Dim [50];
+typedef int     Arr_2_Dim [50] [50];
+
+typedef struct record 
+    {
+    struct record *Ptr_Comp;
+    Enumeration    Discr;
+    union {
+          struct {
+                  Enumeration Enum_Comp;
+                  int         Int_Comp;
+                  char        Str_Comp [31];
+                  } var_1;
+          struct {
+                  Enumeration E_Comp_2;
+                  char        Str_2_Comp [31];
+                  } var_2;
+          struct {
+                  char        Ch_1_Comp;
+                  char        Ch_2_Comp;
+                  } var_3;
+          } variant;
+      } Rec_Type, *Rec_Pointer;
+
+#endif //!DHRY_H
Index: branches/v4/platforms/caba-ring-ccxcachev4_memcachev4-mips32el/soft/dhrystone/dhry21.h
===================================================================
--- branches/v4/platforms/caba-ring-ccxcachev4_memcachev4-mips32el/soft/dhrystone/dhry21.h	(revision 371)
+++ branches/v4/platforms/caba-ring-ccxcachev4_memcachev4-mips32el/soft/dhrystone/dhry21.h	(revision 371)
@@ -0,0 +1,20 @@
+#ifndef DHRY21_H
+#define DHRY21_H
+
+#include "dhry.h"
+
+DOUBLE      dhry21 (unsigned int);
+
+void        Proc_1 (Rec_Pointer);
+void        Proc_2 (One_Fifty *);
+void        Proc_3 (Rec_Pointer *);
+void        Proc_4 ();
+void        Proc_5 ();
+void        Proc_6 (Enumeration, Enumeration*);
+void        Proc_7 (One_Fifty,One_Fifty,One_Fifty*);
+void        Proc_8 (Arr_1_Dim,Arr_2_Dim,int,int);
+Enumeration Func_1 (Capital_Letter,Capital_Letter);
+Boolean     Func_2 (Str_30,Str_30);
+Boolean     Func_3 (Enumeration);
+
+#endif
Index: branches/v4/platforms/caba-ring-ccxcachev4_memcachev4-mips32el/soft/dhrystone/dhry21a.c
===================================================================
--- branches/v4/platforms/caba-ring-ccxcachev4_memcachev4-mips32el/soft/dhrystone/dhry21a.c	(revision 371)
+++ branches/v4/platforms/caba-ring-ccxcachev4_memcachev4-mips32el/soft/dhrystone/dhry21a.c	(revision 371)
@@ -0,0 +1,425 @@
+/*
+ *************************************************************************
+ *
+ *                   "DHRYSTONE" Benchmark Program
+ *                   -----------------------------
+ *
+ *  Version:    C, Version 2.1
+ *
+ *  File:       dhry_1.c (part 2 of 3)
+ *
+ *  Date:       May 25, 1988
+ *
+ *  Author:     Reinhold P. Weicker
+ *
+ *************************************************************************
+ */
+
+#include "dhry.h"
+#include "dhry21.h"
+
+#include <stdio.h>
+#ifdef GENERATE_RESULT_FILE
+#include <string.h>
+#endif
+#include <stdlib.h>
+
+/* Global Variables: */
+
+Rec_Pointer     Ptr_Glob,
+                Next_Ptr_Glob;
+int             Int_Glob;
+Boolean         Bool_Glob;
+char            Ch_1_Glob,
+                Ch_2_Glob;
+int             Arr_1_Glob [50];
+int             Arr_2_Glob [50] [50];
+
+char Reg_Define[] = "Register option selected.";
+
+//extern char     *malloc ();
+//Enumeration     Func_1 ();
+  /* 
+  forward declaration necessary since Enumeration may not simply be int
+  */
+
+#ifndef ROPT
+#define REG
+        /* REG becomes defined as empty */
+        /* i.e. no register variables   */
+#else
+#define REG register
+#endif
+
+
+/* variables for time measurement: */
+
+#define Too_Small_Time 2
+                /* Measurements should last at least 2 seconds */
+
+DOUBLE          Begin_Time,
+                End_Time,
+                User_Time;
+
+DOUBLE          Microseconds,
+                Dhrystones_Per_Second,
+                Vax_Mips;
+
+/* end of variables for time measurement */
+
+DOUBLE dhry21 (unsigned int NUMBER_OF_RUNS)
+/*****/
+
+  /* main program, corresponds to procedures        */
+  /* Main and Proc_0 in the Ada version             */
+{
+  DOUBLE   dtime();
+
+        One_Fifty       Int_1_Loc = 0;
+  REG   One_Fifty       Int_2_Loc = 0;
+        One_Fifty       Int_3_Loc;
+  REG   char            Ch_Index;
+        Enumeration     Enum_Loc;
+        Str_30          Str_1_Loc;
+        Str_30          Str_2_Loc;
+  REG   int             Run_Index;
+  REG   int             Number_Of_Runs;
+
+#ifdef GENERATE_RESULT_FILE
+        FILE            *Ap;
+
+  /* Initializations */
+
+  if ((Ap = fopen("dhry.res","a+")) == NULL)
+    {
+       printf("Can not open dhry.res\n\n");
+       EXIT(1);
+    }
+#endif
+
+  Next_Ptr_Glob = (Rec_Pointer) malloc (sizeof (Rec_Type));
+  Ptr_Glob      = (Rec_Pointer) malloc (sizeof (Rec_Type));
+
+  Ptr_Glob->Ptr_Comp                    = Next_Ptr_Glob;
+  Ptr_Glob->Discr                       = Ident_1;
+  Ptr_Glob->variant.var_1.Enum_Comp     = Ident_3;
+  Ptr_Glob->variant.var_1.Int_Comp      = 40;
+  strcpy (Ptr_Glob->variant.var_1.Str_Comp,
+          "DHRYSTONE PROGRAM, SOME STRING");
+  strcpy (Str_1_Loc, "DHRYSTONE PROGRAM, 1'ST STRING");
+
+  Arr_2_Glob [8][7] = 10;
+        /* Was missing in published program. Without this statement,    */
+        /* Arr_2_Glob [8][7] would have an undefined value.             */
+        /* Warning: With 16-Bit processors and Number_Of_Runs > 32000,  */
+        /* overflow may occur for this array element.                   */
+
+  printf ("\n");
+  printf ("Dhrystone Benchmark, Version 2.1 (Language: C)\n");
+  printf ("\n");
+  
+//  if (Reg)
+//  {
+//    printf ("Program compiled with 'register' attribute\n");
+//    printf ("\n");
+//  }
+//  else
+//  {
+//    printf ("Program compiled without 'register' attribute\n");
+//    printf ("\n");
+//  }
+
+//**********************************************************************
+//  printf ("Please give the number of runs through the benchmark: ");
+//  {
+//    int n;
+//    scanf ("%d", &n);
+//    Number_Of_Runs = n;
+//  }
+//  printf ("\n");
+//**********************************************************************
+
+  Number_Of_Runs = NUMBER_OF_RUNS;
+  
+  printf ("Execution starts, %d runs through Dhrystone\n",Number_Of_Runs);
+  
+  /***************/
+  /* Start timer */
+  /***************/
+ 
+  Begin_Time = dtime();
+
+  for (Run_Index = 1; Run_Index <= Number_Of_Runs; ++Run_Index)
+  {
+    Proc_5();
+    Proc_4();
+      /* Ch_1_Glob == 'A', Ch_2_Glob == 'B', Bool_Glob == true */
+    Int_1_Loc = 2;
+    Int_2_Loc = 3;
+    strcpy (Str_2_Loc, "DHRYSTONE PROGRAM, 2'ND STRING");
+    Enum_Loc = Ident_2;
+    Bool_Glob = ! Func_2 (Str_1_Loc, Str_2_Loc);
+      /* Bool_Glob == 1 */
+    while (Int_1_Loc < Int_2_Loc)  /* loop body executed once */
+    {
+      Int_3_Loc = 5 * Int_1_Loc - Int_2_Loc;
+        /* Int_3_Loc == 7 */
+      Proc_7 (Int_1_Loc, Int_2_Loc, &Int_3_Loc);
+        /* Int_3_Loc == 7 */
+      Int_1_Loc += 1;
+    } /* while */
+      /* Int_1_Loc == 3, Int_2_Loc == 3, Int_3_Loc == 7 */
+    Proc_8 (Arr_1_Glob, Arr_2_Glob, Int_1_Loc, Int_3_Loc);
+      /* Int_Glob == 5 */
+    Proc_1 (Ptr_Glob);
+    for (Ch_Index = 'A'; Ch_Index <= Ch_2_Glob; ++Ch_Index)
+                             /* loop body executed twice */
+    {
+      if (Enum_Loc == Func_1 (Ch_Index, 'C'))
+          /* then, not executed */
+        {
+        Proc_6 (Ident_1, &Enum_Loc);
+        strcpy (Str_2_Loc, "DHRYSTONE PROGRAM, 3'RD STRING");
+        Int_2_Loc = Run_Index;
+        Int_Glob = Run_Index;
+        }
+    }
+      /* Int_1_Loc == 3, Int_2_Loc == 3, Int_3_Loc == 7 */
+    Int_2_Loc = Int_2_Loc * Int_1_Loc;
+    Int_1_Loc = Int_2_Loc / Int_3_Loc;
+    Int_2_Loc = 7 * (Int_2_Loc - Int_3_Loc) - Int_1_Loc;
+      /* Int_1_Loc == 1, Int_2_Loc == 13, Int_3_Loc == 7 */
+    Proc_2 (&Int_1_Loc);
+      /* Int_1_Loc == 5 */
+
+  } /* loop "for Run_Index" */
+
+  /**************/
+  /* Stop timer */
+  /**************/
+
+  End_Time = dtime();
+
+  printf ("Execution ends\n");
+
+#ifdef VERBOSE
+  printf ("\n");
+  printf ("Final values of the variables used in the benchmark:\n");
+  printf ("\n");
+  printf ("Int_Glob:            %d\n", Int_Glob);
+  printf ("        should be:   %d\n", 5);
+  printf ("Bool_Glob:           %d\n", Bool_Glob);
+  printf ("        should be:   %d\n", 1);
+  printf ("Ch_1_Glob:           %c\n", Ch_1_Glob);
+  printf ("        should be:   %c\n", 'A');
+  printf ("Ch_2_Glob:           %c\n", Ch_2_Glob);
+  printf ("        should be:   %c\n", 'B');
+  printf ("Arr_1_Glob[8]:       %d\n", Arr_1_Glob[8]);
+  printf ("        should be:   %d\n", 7);
+  printf ("Arr_2_Glob[8][7]:    %d\n", Arr_2_Glob[8][7]);
+  printf ("        should be:   Number_Of_Runs + 10\n");
+  printf ("Ptr_Glob->\n");
+  printf ("  Ptr_Comp:          %d\n", (int) Ptr_Glob->Ptr_Comp);
+  printf ("        should be:   (implementation-dependent)\n");
+  printf ("  Discr:             %d\n", Ptr_Glob->Discr);
+  printf ("        should be:   %d\n", 0);
+  printf ("  Enum_Comp:         %d\n", Ptr_Glob->variant.var_1.Enum_Comp);
+  printf ("        should be:   %d\n", 2);
+  printf ("  Int_Comp:          %d\n", Ptr_Glob->variant.var_1.Int_Comp);
+  printf ("        should be:   %d\n", 17);
+  printf ("  Str_Comp:          %s\n", Ptr_Glob->variant.var_1.Str_Comp);
+  printf ("        should be:   DHRYSTONE PROGRAM, SOME STRING\n");
+  printf ("Next_Ptr_Glob->\n");
+  printf ("  Ptr_Comp:          %d\n", (int) Next_Ptr_Glob->Ptr_Comp);
+  printf ("        should be:   (implementation-dependent), same as above\n");
+  printf ("  Discr:             %d\n", Next_Ptr_Glob->Discr);
+  printf ("        should be:   %d\n", 0);
+  printf ("  Enum_Comp:         %d\n", Next_Ptr_Glob->variant.var_1.Enum_Comp);
+  printf ("        should be:   %d\n", 1);
+  printf ("  Int_Comp:          %d\n", Next_Ptr_Glob->variant.var_1.Int_Comp);
+  printf ("        should be:   %d\n", 18);
+  printf ("  Str_Comp:          %s\n", Next_Ptr_Glob->variant.var_1.Str_Comp);
+  printf ("        should be:   DHRYSTONE PROGRAM, SOME STRING\n");
+  printf ("Int_1_Loc:           %d\n", Int_1_Loc);
+  printf ("        should be:   %d\n", 5);
+  printf ("Int_2_Loc:           %d\n", Int_2_Loc);
+  printf ("        should be:   %d\n", 13);
+  printf ("Int_3_Loc:           %d\n", Int_3_Loc);
+  printf ("        should be:   %d\n", 7);
+  printf ("Enum_Loc:            %d\n", Enum_Loc);
+  printf ("        should be:   %d\n", 1);
+  printf ("Str_1_Loc:           %s\n", Str_1_Loc);
+  printf ("        should be:   DHRYSTONE PROGRAM, 1'ST STRING\n");
+  printf ("Str_2_Loc:           %s\n", Str_2_Loc);
+  printf ("        should be:   DHRYSTONE PROGRAM, 2'ND STRING\n");
+  printf ("\n");
+#endif
+
+  User_Time = End_Time - Begin_Time;
+
+//  if (User_Time < Too_Small_Time)
+//  {
+//#ifdef HAVE_DOUBLE
+//    printf ("Measured time too small to obtain meaningful results : %f\n",User_Time);
+//#else
+//    printf ("Measured time too small to obtain meaningful results : %d\n",User_Time);
+//#endif
+//    printf ("Please increase number of runs\n");
+//    printf ("\n");
+//  }
+//  else
+
+#ifdef HAVE_DOUBLE
+  Microseconds          = User_Time * Mic_secs_Per_Second / (DOUBLE) Number_Of_Runs;
+  Dhrystones_Per_Second = (DOUBLE) Number_Of_Runs / User_Time;
+  Vax_Mips              = Dhrystones_Per_Second / 1757.0;
+#else
+  Microseconds          = User_Time                       / (DOUBLE) Number_Of_Runs;
+#endif
+  
+#ifdef ROPT
+  printf ("Register option selected?  YES\n");
+#else
+  printf ("Register option selected?  NO\n");
+  strcpy(Reg_Define, "Register option not selected.");
+#endif
+  
+#ifdef HAVE_DOUBLE
+  printf ("Microseconds for one run through Dhrystone : %.1lf  \n",Microseconds);
+  printf ("Dhrystones per Second                      : %.1lf \n",Dhrystones_Per_Second);
+  printf ("VAX MIPS rating                            : %.3lf \n",Vax_Mips);
+#else
+  printf ("Begin_Time : %d\n",Begin_Time);
+  printf ("End_Time   : %d\n",End_Time  );
+  printf ("User_Time  : %d\n",User_Time );
+  printf ("Numbers of cycle for one run through Dhrystone : %d  \n",Microseconds);
+#endif
+  printf ("\n");
+  
+#ifdef GENERATE_RESULT_FILE
+  fprintf(Ap,"\n");
+  fprintf(Ap,"Dhrystone Benchmark, Version 2.1 (Language: C)\n");
+  fprintf(Ap,"%s\n",Reg_Define);
+  
+# ifdef HAVE_DOUBLE
+  fprintf(Ap,"Microseconds for one loop : %.1lf\n",Microseconds);
+  fprintf(Ap,"Dhrystones per second     : %.1lf\n",Dhrystones_Per_Second);
+  fprintf(Ap,"VAX MIPS rating           : %.3lf\n",Vax_Mips);
+# else
+  fprintf(Ap,"Numbers of cycle for one loop : %.1d\n",Microseconds);
+# endif
+  fclose(Ap);
+#endif
+  
+#ifdef HAVE_DOUBLE
+  return Vax_Mips;
+#else
+  return User_Time;
+#endif
+}
+
+void
+Proc_1 (Ptr_Val_Par)
+/******************/
+
+REG Rec_Pointer Ptr_Val_Par;
+    /* executed once */
+{
+  REG Rec_Pointer Next_Record = Ptr_Val_Par->Ptr_Comp;  
+                                        /* == Ptr_Glob_Next */
+  /* Local variable, initialized with Ptr_Val_Par->Ptr_Comp,    */
+  /* corresponds to "rename" in Ada, "with" in Pascal           */
+  
+  structassign (*Ptr_Val_Par->Ptr_Comp, *Ptr_Glob);
+  Ptr_Val_Par->variant.var_1.Int_Comp = 5;
+  Next_Record->variant.var_1.Int_Comp 
+        = Ptr_Val_Par->variant.var_1.Int_Comp;
+  Next_Record->Ptr_Comp = Ptr_Val_Par->Ptr_Comp;
+  Proc_3 (&Next_Record->Ptr_Comp);
+    /* Ptr_Val_Par->Ptr_Comp->Ptr_Comp 
+                        == Ptr_Glob->Ptr_Comp */
+  if (Next_Record->Discr == Ident_1)
+    /* then, executed */
+  {
+    Next_Record->variant.var_1.Int_Comp = 6;
+    Proc_6 (Ptr_Val_Par->variant.var_1.Enum_Comp, 
+           &Next_Record->variant.var_1.Enum_Comp);
+    Next_Record->Ptr_Comp = Ptr_Glob->Ptr_Comp;
+    Proc_7 (Next_Record->variant.var_1.Int_Comp, 10, 
+           &Next_Record->variant.var_1.Int_Comp);
+  }
+  else /* not executed */
+    structassign (*Ptr_Val_Par, *Ptr_Val_Par->Ptr_Comp);
+} /* Proc_1 */
+
+void
+Proc_2 (Int_Par_Ref)
+/******************/
+    /* executed once */
+    /* *Int_Par_Ref == 1, becomes 4 */
+
+One_Fifty   *Int_Par_Ref;
+{
+  One_Fifty  Int_Loc;
+  Enumeration   Enum_Loc;
+
+  Int_Loc = *Int_Par_Ref + 10;
+  do /* executed once */
+    if (Ch_1_Glob == 'A')
+      /* then, executed */
+    {
+      Int_Loc -= 1;
+      *Int_Par_Ref = Int_Loc - Int_Glob;
+      Enum_Loc = Ident_1;
+    } /* if */
+  while (Enum_Loc != Ident_1); /* true */
+} /* Proc_2 */
+
+void
+Proc_3 (Ptr_Ref_Par)
+/******************/
+    /* executed once */
+    /* Ptr_Ref_Par becomes Ptr_Glob */
+
+Rec_Pointer *Ptr_Ref_Par;
+
+{
+  if (Ptr_Glob != Null)
+    /* then, executed */
+    *Ptr_Ref_Par = Ptr_Glob->Ptr_Comp;
+  Proc_7 (10, Int_Glob, &Ptr_Glob->variant.var_1.Int_Comp);
+} /* Proc_3 */
+
+void
+Proc_4 () /* without parameters */
+/*******/
+    /* executed once */
+{
+  Boolean Bool_Loc;
+
+  Bool_Loc = Ch_1_Glob == 'A';
+  Bool_Glob = Bool_Loc | Bool_Glob;
+  Ch_2_Glob = 'B';
+} /* Proc_4 */
+
+void
+Proc_5 () /* without parameters */
+/*******/
+    /* executed once */
+{
+  Ch_1_Glob = 'A';
+  Bool_Glob = false;
+} /* Proc_5 */
+
+
+        /* Procedure for the assignment of structures,          */
+        /* if the C compiler doesn't support this feature       */
+#ifdef  NOSTRUCTASSIGN
+memcpy (d, s, l)
+register char   *d;
+register char   *s;
+register int    l;
+{
+        while (l--) *d++ = *s++;
+}
+#endif
Index: branches/v4/platforms/caba-ring-ccxcachev4_memcachev4-mips32el/soft/dhrystone/dhry21b.c
===================================================================
--- branches/v4/platforms/caba-ring-ccxcachev4_memcachev4-mips32el/soft/dhrystone/dhry21b.c	(revision 371)
+++ branches/v4/platforms/caba-ring-ccxcachev4_memcachev4-mips32el/soft/dhrystone/dhry21b.c	(revision 371)
@@ -0,0 +1,195 @@
+/*
+ *************************************************************************
+ *
+ *                   "DHRYSTONE" Benchmark Program
+ *                   -----------------------------
+ *
+ *  Version:    C, Version 2.1
+ *
+ *  File:       dhry_2.c (part 3 of 3)
+ *
+ *  Date:       May 25, 1988
+ *
+ *  Author:     Reinhold P. Weicker
+ *
+ *************************************************************************
+ */
+
+#include "dhry.h"
+#include "dhry21.h"
+//#include <string.h>
+
+#ifndef REG
+#define REG
+        /* REG becomes defined as empty */
+        /* i.e. no register variables   */
+#else
+#define REG register
+#endif
+
+int     Int_Glob;
+char    Ch_1_Glob;
+
+void
+Proc_6 (Enum_Val_Par, Enum_Ref_Par)
+/*********************************/
+    /* executed once */
+    /* Enum_Val_Par == Ident_3, Enum_Ref_Par becomes Ident_2 */
+
+Enumeration  Enum_Val_Par;
+Enumeration *Enum_Ref_Par;
+{
+  *Enum_Ref_Par = Enum_Val_Par;
+  if (! Func_3 (Enum_Val_Par))
+    /* then, not executed */
+    *Enum_Ref_Par = Ident_4;
+  switch (Enum_Val_Par)
+  {
+    case Ident_1: 
+      *Enum_Ref_Par = Ident_1;
+      break;
+    case Ident_2: 
+      if (Int_Glob > 100)
+        /* then */
+      *Enum_Ref_Par = Ident_1;
+      else *Enum_Ref_Par = Ident_4;
+      break;
+    case Ident_3: /* executed */
+      *Enum_Ref_Par = Ident_2;
+      break;
+    case Ident_4: break;
+    case Ident_5: 
+      *Enum_Ref_Par = Ident_3;
+      break;
+  } /* switch */
+} /* Proc_6 */
+
+void
+Proc_7 (Int_1_Par_Val, Int_2_Par_Val, Int_Par_Ref)
+/**********************************************/
+    /* executed three times                                      */
+    /* first call:      Int_1_Par_Val == 2, Int_2_Par_Val == 3,  */
+    /*                  Int_Par_Ref becomes 7                    */
+    /* second call:     Int_1_Par_Val == 10, Int_2_Par_Val == 5, */
+    /*                  Int_Par_Ref becomes 17                   */
+    /* third call:      Int_1_Par_Val == 6, Int_2_Par_Val == 10, */
+    /*                  Int_Par_Ref becomes 18                   */
+One_Fifty       Int_1_Par_Val;
+One_Fifty       Int_2_Par_Val;
+One_Fifty      *Int_Par_Ref;
+{
+  One_Fifty Int_Loc;
+
+  Int_Loc = Int_1_Par_Val + 2;
+  *Int_Par_Ref = Int_2_Par_Val + Int_Loc;
+} /* Proc_7 */
+
+void
+Proc_8 (Arr_1_Par_Ref, Arr_2_Par_Ref, Int_1_Par_Val, Int_2_Par_Val)
+/*********************************************************************/
+    /* executed once      */
+    /* Int_Par_Val_1 == 3 */
+    /* Int_Par_Val_2 == 7 */
+Arr_1_Dim       Arr_1_Par_Ref;
+Arr_2_Dim       Arr_2_Par_Ref;
+int             Int_1_Par_Val;
+int             Int_2_Par_Val;
+{
+  REG One_Fifty Int_Index;
+  REG One_Fifty Int_Loc;
+
+  Int_Loc = Int_1_Par_Val + 5;
+  Arr_1_Par_Ref [Int_Loc] = Int_2_Par_Val;
+  Arr_1_Par_Ref [Int_Loc+1] = Arr_1_Par_Ref [Int_Loc];
+  Arr_1_Par_Ref [Int_Loc+30] = Int_Loc;
+  for (Int_Index = Int_Loc; Int_Index <= Int_Loc+1; ++Int_Index)
+    Arr_2_Par_Ref [Int_Loc] [Int_Index] = Int_Loc;
+  Arr_2_Par_Ref [Int_Loc] [Int_Loc-1] += 1;
+  Arr_2_Par_Ref [Int_Loc+20] [Int_Loc] = Arr_1_Par_Ref [Int_Loc];
+  Int_Glob = 5;
+} /* Proc_8 */
+
+
+Enumeration Func_1 (Ch_1_Par_Val, Ch_2_Par_Val)
+/*************************************************/
+    /* executed three times                                         */
+    /* first call:      Ch_1_Par_Val == 'H', Ch_2_Par_Val == 'R'    */
+    /* second call:     Ch_1_Par_Val == 'A', Ch_2_Par_Val == 'C'    */
+    /* third call:      Ch_1_Par_Val == 'B', Ch_2_Par_Val == 'C'    */
+
+Capital_Letter   Ch_1_Par_Val;
+Capital_Letter   Ch_2_Par_Val;
+{
+  Capital_Letter        Ch_1_Loc;
+  Capital_Letter        Ch_2_Loc;
+
+  Ch_1_Loc = Ch_1_Par_Val;
+  Ch_2_Loc = Ch_1_Loc;
+  if (Ch_2_Loc != Ch_2_Par_Val)
+    /* then, executed */
+    return (Ident_1);
+  else  /* not executed */
+  {
+    Ch_1_Glob = Ch_1_Loc;
+    return (Ident_2);
+   }
+} /* Func_1 */
+
+
+Boolean Func_2 (Str_1_Par_Ref, Str_2_Par_Ref)
+/*************************************************/
+    /* executed once */
+    /* Str_1_Par_Ref == "DHRYSTONE PROGRAM, 1'ST STRING" */
+    /* Str_2_Par_Ref == "DHRYSTONE PROGRAM, 2'ND STRING" */
+
+Str_30  Str_1_Par_Ref;
+Str_30  Str_2_Par_Ref;
+{
+  REG One_Thirty        Int_Loc;
+      Capital_Letter    Ch_Loc ;
+
+  Int_Loc = 2;
+  while (Int_Loc <= 2) /* loop body executed once */
+    if (Func_1 (Str_1_Par_Ref[Int_Loc],
+                Str_2_Par_Ref[Int_Loc+1]) == Ident_1)
+      /* then, executed */
+    {
+      Ch_Loc = 'A';
+      Int_Loc += 1;
+    } /* if, while */
+  if (Ch_Loc >= 'W' && Ch_Loc < 'Z')
+    /* then, not executed */
+    Int_Loc = 7;
+  if (Ch_Loc == 'R')
+    /* then, not executed */
+    return (true);
+  else /* executed */
+  {
+    if (strcmp (Str_1_Par_Ref, Str_2_Par_Ref) > 0)
+      /* then, not executed */
+    {
+      Int_Loc += 7;
+      Int_Glob = Int_Loc;
+      return (true);
+    }
+    else /* executed */
+      return (false);
+  } /* if Ch_Loc */
+} /* Func_2 */
+
+
+Boolean Func_3 (Enum_Par_Val)
+/***************************/
+    /* executed once        */
+    /* Enum_Par_Val == Ident_3 */
+Enumeration Enum_Par_Val;
+{
+  Enumeration Enum_Loc;
+
+  Enum_Loc = Enum_Par_Val;
+  if (Enum_Loc == Ident_3)
+    /* then, executed */
+    return (true);
+  else /* not executed */
+    return (false);
+} /* Func_3 */
Index: branches/v4/platforms/caba-ring-ccxcachev4_memcachev4-mips32el/soft/dhrystone/dtime.c
===================================================================
--- branches/v4/platforms/caba-ring-ccxcachev4_memcachev4-mips32el/soft/dhrystone/dtime.c	(revision 371)
+++ branches/v4/platforms/caba-ring-ccxcachev4_memcachev4-mips32el/soft/dhrystone/dtime.c	(revision 371)
@@ -0,0 +1,58 @@
+/*****************************************************/
+/* Various timer routines.                           */
+/* Al Aburto, aburto@nosc.mil, 18 Feb 1997           */
+/*                                                   */
+/* t = dtime() outputs the current time in seconds.  */
+/* Use CAUTION as some of these routines will mess   */
+/* up when timing across the hour mark!!!            */
+/*                                                   */
+/* For timing I use the 'user' time whenever         */
+/* possible. Using 'user+sys' time is a separate     */
+/* issue.                                            */
+/*                                                   */
+/* Example Usage:                                    */
+/* [timer options added here]                        */
+/* main()                                            */
+/* {                                                 */
+/* double starttime,benchtime,dtime();               */
+/*                                                   */
+/* starttime = dtime();                              */ 
+/* [routine to time]                                 */
+/* benchtime = dtime() - starttime;                  */
+/* }                                                 */
+/*                                                   */
+/* [timer code below added here]                     */
+/*****************************************************/
+
+/*********************************/
+/* Timer code.                   */
+/*********************************/
+
+#include "dhry.h"
+#include "system.h"
+
+/***************************************************/
+/*  dtime().                                       */
+/***************************************************/
+#ifdef HAVE_DOUBLE
+# ifndef MHZ
+# define MHZ (1000000.0)
+# endif //!MHZ
+
+# ifndef FRQ
+# define FRQ (1*MHZ)
+# endif //!FRQ
+#endif
+
+DOUBLE dtime()
+{
+  DOUBLE q;
+
+#ifdef HAVE_DOUBLE
+  q = (DOUBLE)(cpu_cycles())/(DOUBLE)FRQ;
+#else
+  q = (DOUBLE)(cpu_cycles());
+#endif
+
+  return (q);
+}
Index: branches/v4/platforms/caba-ring-ccxcachev4_memcachev4-mips32el/soft/irq/irq.h
===================================================================
--- branches/v4/platforms/caba-ring-ccxcachev4_memcachev4-mips32el/soft/irq/irq.h	(revision 371)
+++ branches/v4/platforms/caba-ring-ccxcachev4_memcachev4-mips32el/soft/irq/irq.h	(revision 371)
@@ -0,0 +1,7 @@
+#ifndef irq_h
+#define irq_h
+
+void irq_init   ();
+void irq_handler(int irq);
+
+#endif // irq_h
Index: branches/v4/platforms/caba-ring-ccxcachev4_memcachev4-mips32el/soft/irq/irq_handler.c
===================================================================
--- branches/v4/platforms/caba-ring-ccxcachev4_memcachev4-mips32el/soft/irq/irq_handler.c	(revision 371)
+++ branches/v4/platforms/caba-ring-ccxcachev4_memcachev4-mips32el/soft/irq/irq_handler.c	(revision 371)
@@ -0,0 +1,17 @@
+#include "irq.h"
+#include "system.h"
+#include "stdio.h"
+
+#include "../../segmentation.h"
+#include "soclib/xicu.h"
+
+void irq_handler (int irq)
+{
+  const int cpu = procnum();
+  
+  printf("Timer wrapped at cycle %d on cpu %d\n", cpu_cycles(), cpu);
+  /* printf("Timer wrapped  on cpu %d\n", cpu); */
+
+  soclib_io_get(base(XICU),
+        	XICU_REG(XICU_PTI_ACK, cpu));
+}
Index: branches/v4/platforms/caba-ring-ccxcachev4_memcachev4-mips32el/soft/irq/irq_init.c
===================================================================
--- branches/v4/platforms/caba-ring-ccxcachev4_memcachev4-mips32el/soft/irq/irq_init.c	(revision 371)
+++ branches/v4/platforms/caba-ring-ccxcachev4_memcachev4-mips32el/soft/irq/irq_init.c	(revision 371)
@@ -0,0 +1,27 @@
+#include "irq.h"
+#include "system.h"
+#include "stdio.h"
+#include "../define.h"
+#include "../../segmentation.h"
+#include "soclib/xicu.h"
+
+void irq_init ()
+{
+  int cpu=procnum();
+  
+  printf("irq_init : %d\n",cpu);
+  
+  set_irq_handler(irq_handler);
+  
+  soclib_io_set(base(XICU),
+                XICU_REG(XICU_PTI_PER, cpu),
+                TIMER_INTERRUPT_PERIOD);
+  
+  soclib_io_set(base(XICU),
+                XICU_REG(XICU_MSK_PTI, cpu),
+                1);
+
+  enable_hw_irq(0);
+  irq_enable();
+}
+
Index: branches/v4/platforms/caba-ring-ccxcachev4_memcachev4-mips32el/soft/main.c
===================================================================
--- branches/v4/platforms/caba-ring-ccxcachev4_memcachev4-mips32el/soft/main.c	(revision 371)
+++ branches/v4/platforms/caba-ring-ccxcachev4_memcachev4-mips32el/soft/main.c	(revision 371)
@@ -0,0 +1,22 @@
+#include "system.h"
+#include "stdio.h"
+
+#include "define.h"
+#include "common/common.h"
+#include "benchmark/benchmark.h"
+#include "irq/irq.h"
+
+int main()
+{
+  system_start();
+  
+#if TIMER_INTERRUPT
+  irq_init();
+#endif
+  
+  benchmark();
+  
+  EXIT(0);
+
+  return 1;
+}
Index: branches/v4/platforms/caba-ring-ccxcachev4_memcachev4-mips32el/soft/matrix_multiplication/matrix_multiplication.c
===================================================================
--- branches/v4/platforms/caba-ring-ccxcachev4_memcachev4-mips32el/soft/matrix_multiplication/matrix_multiplication.c	(revision 371)
+++ branches/v4/platforms/caba-ring-ccxcachev4_memcachev4-mips32el/soft/matrix_multiplication/matrix_multiplication.c	(revision 371)
@@ -0,0 +1,68 @@
+#include "matrix_multiplication.h"
+#include "stdio.h"
+#include "system.h"
+#include "stdint.h"
+
+void matrix_multiplication_st (int ** a,
+                               int ** b,
+                               int ** d,
+                               unsigned int n)
+{
+  uint32_t x, y;
+
+  for (x=0; x<n; ++x)
+    {
+      printf("%d, ",x);
+
+      for (y=0; y<n; ++y)
+        {
+          uint32_t i;
+
+          int tmp = 0;
+          for (i=0; i<n; ++i)
+            tmp += a[x][i] * b[i][y];
+          d[x][y] = tmp;
+        }
+    }
+  
+  printf("finish\n");
+}
+
+static uint32_t lock;
+static uint32_t next;
+
+void matrix_multiplication_mt (int ** a,
+                               int ** b,
+                               int ** d,
+                               unsigned int n,
+                               int lock_by_line)
+{
+  uint32_t x, y;
+
+  while (1)
+    {
+      lock_lock(&lock);
+      
+      x=next++;
+      
+      lock_unlock(&lock);
+
+      if (x >= n)
+        break;
+      
+      printf("%d, ",x);
+      for (y=0; y<n; ++y)
+        {
+          int line  =(lock_by_line)?x:y;
+          int column=(lock_by_line)?y:x;
+          
+          int i;
+          int tmp = 0;
+          for (i=0; i<n; ++i)
+            tmp += a[column][i] * b[i][line];
+          d[column][line] = tmp;
+        }
+    }
+  
+  printf("finish\n");
+}
Index: branches/v4/platforms/caba-ring-ccxcachev4_memcachev4-mips32el/soft/matrix_multiplication/matrix_multiplication.h
===================================================================
--- branches/v4/platforms/caba-ring-ccxcachev4_memcachev4-mips32el/soft/matrix_multiplication/matrix_multiplication.h	(revision 371)
+++ branches/v4/platforms/caba-ring-ccxcachev4_memcachev4-mips32el/soft/matrix_multiplication/matrix_multiplication.h	(revision 371)
@@ -0,0 +1,17 @@
+#ifndef matrix_multiplication_h
+#define matrix_multiplication_h
+
+void matrix_multiplication_st (int ** a,
+                               int ** b,
+                               int ** d,
+                               unsigned int n);
+
+void matrix_multiplication_mt (int ** a,
+                               int ** b,
+                               int ** d,
+                               unsigned int n,
+                               int lock_by_line);
+
+void matrix_multiplication_print (int ** m, unsigned int n);
+
+#endif // matrix_multiplication_h
Index: branches/v4/platforms/caba-ring-ccxcachev4_memcachev4-mips32el/soft/matrix_multiplication/matrix_multiplication_print.c
===================================================================
--- branches/v4/platforms/caba-ring-ccxcachev4_memcachev4-mips32el/soft/matrix_multiplication/matrix_multiplication_print.c	(revision 371)
+++ branches/v4/platforms/caba-ring-ccxcachev4_memcachev4-mips32el/soft/matrix_multiplication/matrix_multiplication_print.c	(revision 371)
@@ -0,0 +1,13 @@
+#include "matrix_multiplication.h"
+#include "stdio.h"
+
+void matrix_multiplication_print (int ** m, unsigned int n)
+{
+  int i,j;
+  for (i=0; i<n; ++i)
+    {
+      for (j=0; j<n; ++j)
+        printf("%d ",m[i][j]);
+      printf("\n");
+    }
+}
Index: branches/v4/platforms/caba-ring-ccxcachev4_memcachev4-mips32el/soft/self_code_modifying/self_code_modifying.c
===================================================================
--- branches/v4/platforms/caba-ring-ccxcachev4_memcachev4-mips32el/soft/self_code_modifying/self_code_modifying.c	(revision 371)
+++ branches/v4/platforms/caba-ring-ccxcachev4_memcachev4-mips32el/soft/self_code_modifying/self_code_modifying.c	(revision 371)
@@ -0,0 +1,130 @@
+#include <stdio.h>
+#include <stdlib.h>
+/* #include <unistd.h> */
+/* #include <sys/mman.h> */
+/* #include <errno.h> */
+/* #include <string.h> */
+
+#define SELF_CODE_MODIFYING      1
+#define SELF_CODE_MODIFYING_ADDR 1
+// 0 : with label in function
+// 1 : fixed
+
+
+#if SELF_CODE_MODIFYING
+static int  self_code_modifying_nb_runs;
+extern char self_code_modifying_function_destination_start;
+extern char self_code_modifying_function_destination_end;
+extern char self_code_modifying_function_source_start;
+extern char self_code_modifying_function_source_end;
+
+int  self_code_modifying_manage              (int nb_runs);
+void self_code_modifying_function_source     (void);
+void self_code_modifying_function_destination(void);
+
+int self_code_modifying(int nb_runs)
+{
+ return self_code_modifying_manage(nb_runs);
+}
+
+int  self_code_modifying_manage(int nb_runs)
+{
+  
+//  // Change the memory protection
+//  unsigned page = (unsigned)&self_code_modifying_function_destination_start & ~( getpagesize() - 1 );
+//  
+//  if( mprotect( (char*)page, getpagesize(), PROT_READ | PROT_WRITE | PROT_EXEC ) )
+//    {
+//      perror( "mprotect failed" );
+//      exit( errno );
+//    }
+
+  // First execution
+  self_code_modifying_function_destination();
+
+
+#if   (SELF_CODE_MODIFYING_ADDR==0)
+  int function_source_start      = (int)&self_code_modifying_function_source_start     ;
+  int function_source_end        = (int)&self_code_modifying_function_source_end       ;
+  int function_destination_start = (int)&self_code_modifying_function_destination_start;
+  int function_destination_end   = (int)&self_code_modifying_function_destination_end  ;
+#elif (SELF_CODE_MODIFYING_ADDR==1)
+  int function_source_start      = 0x00400330;
+  int function_source_end        = 0x00400358;
+  int function_destination_start = 0x0040036c;
+  int function_destination_end   = 0x004004d8;
+#else
+  #error "Invalid SELF_CODE_MODIFYING_ADDR."
+#endif
+
+  int size_source      = function_source_end     -function_source_start;
+  int size_destination = function_destination_end-function_destination_start;
+  
+  printf(" * self_code_modifying_function_destination : %x to %x (%d bytes)\n",function_destination_start,function_destination_end,size_destination);
+  printf(" * self_code_modifying_function_source      : %x to %x (%d bytes)\n",function_source_start     ,function_source_end     ,size_source);
+  
+  if (size_destination<size_source)
+    {
+      printf("Size of destination is too short\n");
+      return 1;
+    }
+  
+  printf(" * memcpy\n");
+  memcpy((void*)function_destination_start, (void*)function_source_start, function_source_end - function_source_start );
+  
+  while (self_code_modifying_nb_runs<nb_runs)
+    {
+      self_code_modifying_function_destination();
+    }
+
+  return 0;
+}
+
+void self_code_modifying_function_source(void)
+{
+  int  (*callPrintf  )(const char *format, ...); 
+ 
+  asm volatile( "self_code_modifying_function_source_start:" );
+  
+  (*(callPrintf=&printf))( " + self_code_modifying_function_source\n" );
+  self_code_modifying_nb_runs++;
+  (*(callPrintf=&printf))( " + Number of call : %d\n",self_code_modifying_nb_runs);
+  
+  asm volatile( "self_code_modifying_function_source_end:");
+}
+
+void self_code_modifying_function_destination(void)
+{
+  int  (*callPrintf  )(const char *format, ...); 
+
+  asm volatile( "self_code_modifying_function_destination_start:");
+
+  (*(callPrintf=&printf))( " + self_code_modifying_function_destination\n" );
+  
+  // Padding
+  asm volatile (//".set push        \n\t"
+                //".set noreorder   \n\t"
+                //".set noat        \n\t"
+                "nop; nop; nop; nop; nop; nop; nop; nop;\n\t"
+                "nop; nop; nop; nop; nop; nop; nop; nop;\n\t"
+                "nop; nop; nop; nop; nop; nop; nop; nop;\n\t"
+                "nop; nop; nop; nop; nop; nop; nop; nop;\n\t"
+                "nop; nop; nop; nop; nop; nop; nop; nop;\n\t"
+                "nop; nop; nop; nop; nop; nop; nop; nop;\n\t"
+                "nop; nop; nop; nop; nop; nop; nop; nop;\n\t"
+                "nop; nop; nop; nop; nop; nop; nop; nop;\n\t"
+                "nop; nop; nop; nop; nop; nop; nop; nop;\n\t"
+                "nop; nop; nop; nop; nop; nop; nop; nop;\n\t"
+                "nop; nop; nop; nop; nop; nop; nop; nop;\n\t");
+    
+  asm volatile( "self_code_modifying_function_destination_end:");
+}
+
+#else
+
+int self_code_modifying(int nb_runs)
+{
+  return 0;
+}
+
+#endif
Index: branches/v4/platforms/caba-ring-ccxcachev4_memcachev4-mips32el/soft/self_code_modifying/self_code_modifying.h
===================================================================
--- branches/v4/platforms/caba-ring-ccxcachev4_memcachev4-mips32el/soft/self_code_modifying/self_code_modifying.h	(revision 371)
+++ branches/v4/platforms/caba-ring-ccxcachev4_memcachev4-mips32el/soft/self_code_modifying/self_code_modifying.h	(revision 371)
@@ -0,0 +1,6 @@
+#ifndef self_code_modifying_h
+#define self_code_modifying_h
+
+int self_code_modifying(int nb_runs);
+
+#endif // self_code_modifying_h
Index: branches/v4/platforms/caba-ring-ccxcachev4_memcachev4-mips32el/soft/sort/sort.c
===================================================================
--- branches/v4/platforms/caba-ring-ccxcachev4_memcachev4-mips32el/soft/sort/sort.c	(revision 371)
+++ branches/v4/platforms/caba-ring-ccxcachev4_memcachev4-mips32el/soft/sort/sort.c	(revision 371)
@@ -0,0 +1,25 @@
+#include "sort.h"
+#include "system.h"
+#include "stdio.h"
+
+//-------------------------------------*/
+void sort(unsigned int *base, unsigned int n, sort_t type)
+{
+  switch(type)
+  {
+  case SORT_SHELL:
+    sort_shell(base, n);
+    break;
+  case SORT_SELECTION:
+    sort_selection(base, n);
+    break;
+  case SORT_INSERTION:
+    sort_insertion(base, n);
+    break;
+  case SORT_BUBBLE:
+    sort_bubble(base, n);
+    break;
+  default:
+    break;
+  }
+}
Index: branches/v4/platforms/caba-ring-ccxcachev4_memcachev4-mips32el/soft/sort/sort.h
===================================================================
--- branches/v4/platforms/caba-ring-ccxcachev4_memcachev4-mips32el/soft/sort/sort.h	(revision 371)
+++ branches/v4/platforms/caba-ring-ccxcachev4_memcachev4-mips32el/soft/sort/sort.h	(revision 371)
@@ -0,0 +1,21 @@
+#ifndef sort_h
+#define sort_h
+
+#include "../define.h"
+
+typedef enum
+  {
+    SORT_INSERTION,
+    SORT_SELECTION,
+    SORT_BUBBLE,
+    SORT_SHELL
+  } sort_t;
+
+void         sort            (unsigned int *base, unsigned int n, sort_t type);
+void         sort_insertion  (unsigned int *base, unsigned int n);
+void         sort_selection  (unsigned int *base, unsigned int n);
+void         sort_bubble     (unsigned int *base, unsigned int n);
+void         sort_shell      (unsigned int *base, unsigned int n);
+const char * sort_str        (sort_t x);
+
+#endif //sort_h
Index: branches/v4/platforms/caba-ring-ccxcachev4_memcachev4-mips32el/soft/sort/sort_bubble.c
===================================================================
--- branches/v4/platforms/caba-ring-ccxcachev4_memcachev4-mips32el/soft/sort/sort_bubble.c	(revision 371)
+++ branches/v4/platforms/caba-ring-ccxcachev4_memcachev4-mips32el/soft/sort/sort_bubble.c	(revision 371)
@@ -0,0 +1,44 @@
+#include "sort.h"
+#include "system.h"
+#include "stdio.h"
+
+void sort_bubble(unsigned int *base, unsigned int n)
+{
+        int i   = 0; /* Indice de rÃ©pÃ©tition du tri */
+ 	int j   = 0; /* Variable de boucle */
+ 	int tmp = 0; /* Variable de stockage temporaire */
+        int en_desordre = 1; /* BoolÃ©en marquant l'arrÃªt du tri si le tableau est ordonnÃ© */
+
+	/* Boucle de rÃ©pÃ©tition du tri et le test qui arrÃªte le tri dÃšs que le tableau est ordonnÃ© */
+	for(i = 0 ; (i < n) && en_desordre; i++)
+	{
+#if VERBOSE_SORT
+                printf("-"); // added for debug
+#endif
+		/* Supposons le tableau ordonnÃ© */
+		en_desordre = 0;
+		/* VÃ©rification des Ã©lÃ©ments des places j et j-1 */
+		for(j = 1 ; j < n - i ; j++)
+		{
+			/* Si les 2 Ã©lÃ©ments sont mal triÃ©s */
+			if(base[j] < base[j-1])
+			{
+				/* Inversion des 2 Ã©lÃ©ments */
+ 				tmp = base[j-1];
+ 				base[j-1] = base[j];
+ 				base[j] = tmp;
+ 
+ 				/* Le tableau n'est toujours pas triÃ© */
+				en_desordre = 1;
+ 			}
+		}
+
+#if VERBOSE_SORT
+                printf("+"); // added for debug
+#endif
+	}
+
+#if VERBOSE_SORT
+    printf("\n");
+#endif
+}
Index: branches/v4/platforms/caba-ring-ccxcachev4_memcachev4-mips32el/soft/sort/sort_insertion.c
===================================================================
--- branches/v4/platforms/caba-ring-ccxcachev4_memcachev4-mips32el/soft/sort/sort_insertion.c	(revision 371)
+++ branches/v4/platforms/caba-ring-ccxcachev4_memcachev4-mips32el/soft/sort/sort_insertion.c	(revision 371)
@@ -0,0 +1,39 @@
+#include "sort.h"
+#include "system.h"
+#include "stdio.h"
+
+//---- insertion sort : non adaptÃ© pour tableaux de grande taille (> 100) --
+void sort_insertion(unsigned int *base, unsigned int n) 
+{
+    /* SpÃ©cifications externes : Tri du tableau base par insertion sÃ©quentielle */
+    int i,p,j;
+    int x;
+
+    for (i = 1; i < n; i++) 
+    {
+
+#if VERBOSE_SORT
+        printf("-"); // added for debug
+#endif
+        /* stockage de la valeur en i */
+        x = base[i]; 
+ 
+        /* recherche du plus petit indice p infÃ©rieur ÃÂ  i tel que base[p] >= base[i] */
+        for(p = 0; base[p] < x; p++);
+        /* p pointe une valeur de base supÃ©rieure ÃÂ  celle en i */ 
+ 
+        /* dÃ©calage avant des valeurs de base entre p et i */         
+        for (j = i-1; j >= p; j--) {
+            base[j+1] = base[j]; 
+        }   
+ 
+        base[p] = x; /* insertion de la valeur stockÃ©e ÃÂ  la place vacante */
+
+#if VERBOSE_SORT
+        printf("+"); // added for debug
+#endif
+    }
+#if VERBOSE_SORT
+    printf("\n");
+#endif
+}
Index: branches/v4/platforms/caba-ring-ccxcachev4_memcachev4-mips32el/soft/sort/sort_selection.c
===================================================================
--- branches/v4/platforms/caba-ring-ccxcachev4_memcachev4-mips32el/soft/sort/sort_selection.c	(revision 371)
+++ branches/v4/platforms/caba-ring-ccxcachev4_memcachev4-mips32el/soft/sort/sort_selection.c	(revision 371)
@@ -0,0 +1,41 @@
+#include "sort.h"
+#include "system.h"
+#include "stdio.h"
+
+//------ simple_sort -------------------------------
+void sort_selection(unsigned int *base, unsigned int n)
+{
+     int i, min, j , x;
+
+     for(i = 0 ; i < n - 1 ; i++)
+     {
+
+#if VERBOSE_SORT
+         printf("-"); // added for debug
+#endif
+
+         min = i;
+         
+         for(j = i+1 ; j < n ; j++)
+         {
+        
+            if(base[j] < base[min])
+                  min = j;
+            
+         }
+
+         if(min != i)
+         {
+             x = base[i];
+             base[i] = base[min];
+             base[min] = x;
+         }
+
+#if VERBOSE_SORT
+         printf("+"); // added for debug
+#endif
+     }
+#if VERBOSE_SORT
+    printf("\n");
+#endif
+}
Index: branches/v4/platforms/caba-ring-ccxcachev4_memcachev4-mips32el/soft/sort/sort_shell.c
===================================================================
--- branches/v4/platforms/caba-ring-ccxcachev4_memcachev4-mips32el/soft/sort/sort_shell.c	(revision 371)
+++ branches/v4/platforms/caba-ring-ccxcachev4_memcachev4-mips32el/soft/sort/sort_shell.c	(revision 371)
@@ -0,0 +1,50 @@
+#include "sort.h"
+#include "system.h"
+#include "stdio.h"
+
+//------------------------------------------------------
+/*
+ * ExÃ©cute un tri par insertion avec la sÃ©paration donnÃ©e
+ * If gap == 1, on fait un tri ordinaire.
+ * If gap >= length, on ne fait rien.
+ */
+void sort_shell_phase(unsigned int a[],unsigned int length, int gap) {
+    int i;
+ 
+    /* puti(gap); */
+    for (i = gap; i < length; ++i) {
+        unsigned int value = a[i];
+        int j;
+        for (j = i - gap; j >= 0 && a[j] > value; j -= gap) {
+#if VERBOSE_SORT
+	    printf("+");
+#endif
+            a[j + gap] = a[j];
+#if VERBOSE_SORT
+	    printf("-");
+#endif
+        }
+        a[j + gap] = value;
+    }
+}
+ 
+void sort_shell(unsigned int *base, unsigned int n) {
+    /*
+     * gaps[] doit approximer une SÃ©rie gÃ©omÃ©trique.
+     * La sequence suivante est la meilleure connue en terme
+     * de nombre moyen de comparaisons. voir:
+     * http://www.research.att.com/~njas/sequences/A102549
+     */
+    static const int gaps[] = {
+        1, 4, 10, 23, 57, 132, 301, 701
+    };
+    int sizeIndex;
+ 
+    for (sizeIndex = sizeof(gaps)/sizeof(gaps[0]) - 1;
+               sizeIndex >= 0;
+               --sizeIndex)
+        sort_shell_phase(base, n, gaps[sizeIndex]);
+#if VERBOSE_SORT
+    printf("\n");
+#endif
+}
Index: branches/v4/platforms/caba-ring-ccxcachev4_memcachev4-mips32el/soft/sort/sort_str.c
===================================================================
--- branches/v4/platforms/caba-ring-ccxcachev4_memcachev4-mips32el/soft/sort/sort_str.c	(revision 371)
+++ branches/v4/platforms/caba-ring-ccxcachev4_memcachev4-mips32el/soft/sort/sort_str.c	(revision 371)
@@ -0,0 +1,16 @@
+#include "sort.h"
+#include "stdio.h"
+
+static const char * sort_type_str [] = 
+  {
+    "insertion sort",
+    "selection sort",
+    "bubble sort",
+    "shell sort"
+  };
+
+const char * sort_str (sort_t x)
+{
+  return sort_type_str[x];
+}
+
Index: branches/v4/platforms/caba-ring-ccxcachev4_memcachev4-mips32el/top.cpp
===================================================================
--- branches/v4/platforms/caba-ring-ccxcachev4_memcachev4-mips32el/top.cpp	(revision 371)
+++ branches/v4/platforms/caba-ring-ccxcachev4_memcachev4-mips32el/top.cpp	(revision 371)
@@ -0,0 +1,506 @@
+#include <systemc>
+#include <sys/time.h>
+#include <iostream>
+#include <sstream>
+#include <cstdlib>
+#include <cstdarg>
+#include <stdint.h>
+#include <fstream>
+
+#include "mapping_table.h"
+#include "mips32.h"
+#include "vci_simhelper.h"
+#include "vci_simple_ram.h"
+#include "vci_multi_tty.h"
+#include "vci_xicu.h"
+#include "vci_simple_ring_fast.h"
+#include "vci_mem_cache_v4.h"
+#include "vci_cc_xcache_wrapper_v4.h"
+#include "alloc_elems.h"
+
+#include "iss/gdbserver.h"
+
+#include "segmentation.h"
+
+//===========================================
+// Define before include
+//===========================================
+
+// Parameters
+// * Platforms
+#  define PARAM_VCI                         4,8,32,1,1,1,8,4,4,1
+
+#  define USE_OLD_XCACHE                    0
+#  define NB_PROC_MIN                       1
+#  define NB_PROC_MAX                       15
+//                                          fifo_depth
+#  define PARAM_RING_P                      2
+#  define PARAM_RING_C                      2
+#  define PARAM_RING_X                      2
+//                                          pti    , hwi    , wti, irq
+#  define PARAM_XICU                        nb_proc*nb_cpu_by_cache, nb_proc*nb_cpu_by_cache, 0  , nb_proc*nb_cpu_by_cache
+//#define PARAM_XICU                        nb_proc, nb_proc, 0  , nb_proc
+
+// * Debug
+#  define DEBUG_TOP                         0
+#  define SOCVIEW                           0
+#  define STOP_SIMULATION_NB_FRZ_CYCLES     100000
+                                            
+// * Simulation                             
+#  define CONFIG_DEFAULT                    "configuration/default.cfg"
+#  define NCYCLES_DEFAULT                   0
+#  define SOFT_DEFAULT                      "soft/bin.soft"
+//===========================================
+
+void usage (char * funcname)
+{
+  std::cout << funcname << " [option] " << std::endl;
+  std::cout << " * -NCYCLES int : number of simulated cycle, if 0 then no stop condition." << std::endl;
+  std::cout << "                  default : " << NCYCLES_DEFAULT << " cycle(s)" << std::endl;
+  std::cout << " * -CFG string  : configuration file" << std::endl;
+  std::cout << "                    - nb_proc," << std::endl;
+  std::cout << "                    - nb_cpu_by_cache, nb_dcache," << std::endl;
+  std::cout << "                    - iways, isets, iwords," << std::endl;
+  std::cout << "                    - dways, dsets, dwords," << std::endl;
+  std::cout << "                    - wnwords, wnlines, " << std::endl;
+  std::cout << "                    - memc_nways, memc_nsets, memc_words, memc_heap_size." << std::endl;
+  std::cout << "                  default : \"" << CONFIG_DEFAULT << "\"" << std::endl;
+  std::cout << " * -SOFT string : software executed by this platform." << std::endl;
+  std::cout << "                  default : \"" << SOFT_DEFAULT << "\"" << std::endl;
+
+  exit(1);
+}
+
+int _main(int argc, char *argv[])
+{
+	int    ncycles = NCYCLES_DEFAULT;
+	char * config  = CONFIG_DEFAULT;
+        char * soft    = SOFT_DEFAULT;
+
+        if (argc > 1)
+          {
+            for( int n=1 ; n<argc ; n=n+2 )
+              {
+                if( (strcmp(argv[n],"-NCYCLES") == 0) && (n+1<argc) )
+                  {
+                    ncycles = atoi(argv[n+1]);
+                  }
+                else if( (strcmp(argv[n],"-CFG") == 0) && (n+1<argc) )
+                  {
+                    // strcpy(config, argv[n+1]);
+                    config = argv[n+1];
+                  }
+                else if( (strcmp(argv[n],"-SOFT") == 0) && (n+1<argc) )
+                  {
+                    // strcpy(soft, argv[n+1]);
+                    soft = argv[n+1];
+                  }
+                else
+                  {
+                    usage(argv[0]);
+                  }
+              }
+          }
+
+        if (ncycles == 0)
+          ncycles = -1;
+
+        uint32_t nb_proc;
+        uint32_t nb_cpu_by_cache;
+        uint32_t nb_dcache;
+        uint32_t iways, isets, iwords;
+        uint32_t dways, dsets, dwords;
+        uint32_t wnwords, wnlines;
+        uint32_t memc_nways, memc_nsets, memc_words, memc_heap_size;
+
+        std::ifstream inFile;
+        const char * filename = config;
+
+        inFile.open(filename);
+        
+        if (!inFile) 
+          {
+            std::cout << "Can't open file : \"" << filename << "\"." << std::endl;
+            usage(argv[0]);
+          }
+
+        std::string str;
+        if (not (inFile >> str)){std::cout << "Invalid parameters number in configuration file." << std::endl; usage(argv[0]);}
+        nb_proc         =std::atoi(str.c_str());
+        if (not (inFile >> str)){std::cout << "Invalid parameters number in configuration file." << std::endl; usage(argv[0]);}
+        nb_cpu_by_cache =std::atoi(str.c_str());
+        if (not (inFile >> str)){std::cout << "Invalid parameters number in configuration file." << std::endl; usage(argv[0]);}
+        nb_dcache       =std::atoi(str.c_str());
+        if (not (inFile >> str)){std::cout << "Invalid parameters number in configuration file." << std::endl; usage(argv[0]);}
+        iways           =std::atoi(str.c_str());
+        if (not (inFile >> str)){std::cout << "Invalid parameters number in configuration file." << std::endl; usage(argv[0]);}
+        isets           =std::atoi(str.c_str());
+        if (not (inFile >> str)){std::cout << "Invalid parameters number in configuration file." << std::endl; usage(argv[0]);}
+        iwords          =std::atoi(str.c_str());
+        if (not (inFile >> str)){std::cout << "Invalid parameters number in configuration file." << std::endl; usage(argv[0]);}
+        dways           =std::atoi(str.c_str());
+        if (not (inFile >> str)){std::cout << "Invalid parameters number in configuration file." << std::endl; usage(argv[0]);}
+        dsets           =std::atoi(str.c_str());
+        if (not (inFile >> str)){std::cout << "Invalid parameters number in configuration file." << std::endl; usage(argv[0]);}
+        dwords          =std::atoi(str.c_str());
+        if (not (inFile >> str)){std::cout << "Invalid parameters number in configuration file." << std::endl; usage(argv[0]);}
+        wnwords         =std::atoi(str.c_str());
+        if (not (inFile >> str)){std::cout << "Invalid parameters number in configuration file." << std::endl; usage(argv[0]);}
+        wnlines         =std::atoi(str.c_str());
+        if (not (inFile >> str)){std::cout << "Invalid parameters number in configuration file." << std::endl; usage(argv[0]);}
+        memc_nways      =std::atoi(str.c_str());
+        if (not (inFile >> str)){std::cout << "Invalid parameters number in configuration file." << std::endl; usage(argv[0]);}
+        memc_nsets      =std::atoi(str.c_str());
+        if (not (inFile >> str)){std::cout << "Invalid parameters number in configuration file." << std::endl; usage(argv[0]);}
+        memc_words      =std::atoi(str.c_str());
+        if (not (inFile >> str)){std::cout << "Invalid parameters number in configuration file." << std::endl; usage(argv[0]);}
+        memc_heap_size  =std::atoi(str.c_str());
+
+        if (((nb_proc*nb_cpu_by_cache)<NB_PROC_MIN) or
+            ((nb_proc*nb_cpu_by_cache)>NB_PROC_MAX))
+          {
+            std::cout << "Parameters nb_proc is out of bound." << std::endl;
+            usage(argv[0]);
+          }
+
+        std::cout << "  * Parameters : " << std::endl;
+        std::cout << "    * nb_proc          : " << nb_proc          << std::endl;
+        std::cout << "    * nb_cpu_by_cache  : " << nb_cpu_by_cache  << std::endl;
+        std::cout << "    * nb_dcache        : " << nb_dcache        << std::endl;
+        std::cout << "    * iways            : " << iways            << std::endl;
+        std::cout << "    * isets            : " << isets            << std::endl;
+        std::cout << "    * iwords           : " << iwords           << std::endl;
+        std::cout << "    * dways            : " << dways            << std::endl;
+        std::cout << "    * dsets            : " << dsets            << std::endl;
+        std::cout << "    * dwords           : " << dwords           << std::endl;
+        std::cout << "    * wnwords          : " << wnwords          << std::endl;
+        std::cout << "    * wnlines          : " << wnlines          << std::endl;
+        std::cout << "    * memc_nways       : " << memc_nways       << std::endl;
+        std::cout << "    * memc_nsets       : " << memc_nsets       << std::endl;
+        std::cout << "    * memc_words       : " << memc_words       << std::endl;
+        std::cout << "    * memc_heap_size   : " << memc_heap_size   << std::endl;
+        std::cout << "  * Simulation : " << std::endl;
+        std::cout << "    * ncycles          : " << ncycles          << std::endl;
+        std::cout << "    * soft             : " << soft             << std::endl;
+
+	using namespace sc_core;
+	// Avoid repeating these everywhere
+	using soclib::common::IntTab;
+	using soclib::common::Segment;
+
+	// Define VCI parameters
+	typedef soclib::caba::VciParams<PARAM_VCI> vci_param;
+	typedef soclib::common::GdbServer<soclib::common::Mips32ElIss> proc_iss;
+	// Mapping table
+
+	soclib::common::MappingTable maptabp(32, IntTab(8), IntTab(8), 0x00300000); // size, level_addr_bits, level_id_bits, cacheability_mask
+
+	maptabp.add(Segment("reset"    , RESET_BASE    , RESET_SIZE    , IntTab(2), true));
+	maptabp.add(Segment("excep"    , EXCEP_BASE    , EXCEP_SIZE    , IntTab(2), true));
+
+	maptabp.add(Segment("tty"      , TTY_BASE      , TTY_SIZE      , IntTab(1), false));
+	maptabp.add(Segment("text"     , TEXT_BASE     , TEXT_SIZE     , IntTab(2), true));
+	maptabp.add(Segment("mc_r"     , MC_R_BASE     , MC_R_SIZE     , IntTab(2), false, true, IntTab(0)));
+	maptabp.add(Segment("mc_m"     , MC_M_BASE     , MC_M_SIZE     , IntTab(2), true));
+      //maptabp.add(Segment("mc_u"     , MC_U_BASE     , MC_U_SIZE     , IntTab(2), false));
+      //maptabp.add(Segment("ptba"     , PTD_ADDR      , TAB_SIZE      , IntTab(2), true));
+	maptabp.add(Segment("xicu"     , XICU_BASE     , XICU_SIZE     , IntTab(3), false));
+	maptabp.add(Segment("simhelper", SIMHELPER_BASE, SIMHELPER_SIZE, IntTab(4), false));
+ 
+	std::cout << maptabp << std::endl;
+
+        soclib::common::MappingTable maptabc(32, IntTab(8), IntTab(8), 0x00300000);
+        // for (uint32_t i=0; i<nb_proc; ++i)
+        //   for (uint32_t j=0; j<nb_cpu_by_cache; ++j)
+        //   {
+        //     std::ostringstream str;
+        //     str << "c_proc_" << i << "_" << j;
+        //     maptabc.add(Segment(str.str().c_str(), C_PROC_BASE+(i*nb_cpu_by_cache+j)*C_PROC_SPAN, C_PROC_SIZE , IntTab(i), false, true, IntTab(i)));
+        //   }
+        for (uint32_t i=0; i<nb_proc; ++i)
+        {
+          std::ostringstream str;
+          str << "c_proc_" << i;
+          maptabc.add(Segment(str.str().c_str(), C_PROC_BASE+i*C_PROC_SPAN, C_PROC_SIZE , IntTab(i), false, true, IntTab(i)));
+        }
+	maptabc.add(Segment("mc_r"    , MC_R_BASE  , MC_R_SIZE   , IntTab(nb_proc), false, false));
+	maptabc.add(Segment("mc_m"    , MC_M_BASE  , MC_M_SIZE   , IntTab(nb_proc), false, false));
+	// maptabc.add(Segment("mc_u"    , MC_U_BASE  , MC_U_SIZE   , IntTab(nb_proc), false, false));
+	maptabc.add(Segment("reset"   , RESET_BASE , RESET_SIZE  , IntTab(nb_proc), false, false));
+	maptabc.add(Segment("excep"   , EXCEP_BASE , EXCEP_SIZE  , IntTab(nb_proc), false, false));
+	maptabc.add(Segment("text"    , TEXT_BASE  , TEXT_SIZE   , IntTab(nb_proc), false, false));
+      //maptabc.add(Segment("ptba"    , PTD_ADDR   , TAB_SIZE    , IntTab(nb_proc), false, false));
+
+	std::cout << maptabc << std::endl;
+	
+	soclib::common::MappingTable maptabx(32, IntTab(8), IntTab(8), 0x00300000);
+	maptabx.add(Segment("xram" , MC_M_BASE , MC_M_SIZE , IntTab(0), false));
+	// maptabx.add(Segment("uram" , MC_U_BASE , MC_U_SIZE , IntTab(0), false));
+	maptabx.add(Segment("reset", RESET_BASE, RESET_SIZE, IntTab(0), false));
+	maptabx.add(Segment("excep", EXCEP_BASE, EXCEP_SIZE, IntTab(0), false));
+	maptabx.add(Segment("text" , TEXT_BASE , TEXT_SIZE , IntTab(0), false));
+	// maptabx.add(Segment("ptba" , PTD_ADDR  , TAB_SIZE  , IntTab(0), false));
+	
+	std::cout << maptabx << std::endl;
+
+	// Signals
+	sc_clock	signal_clk("clk");
+	sc_signal<bool> signal_resetn("resetn");
+   
+	sc_signal<bool> *** signal_proc_it = soclib::common::alloc_elems<sc_signal<bool> >("proc_it", nb_proc, nb_cpu_by_cache, 6);
+
+	soclib::caba::VciSignals<vci_param> * signal_vci_ini_rw_proc = soclib::common::alloc_elems<soclib::caba::VciSignals<vci_param> >("vci_ini_rw_proc", nb_proc);
+	soclib::caba::VciSignals<vci_param> * signal_vci_ini_c_proc  = soclib::common::alloc_elems<soclib::caba::VciSignals<vci_param> >("vci_ini_c_proc" , nb_proc);
+	soclib::caba::VciSignals<vci_param> * signal_vci_tgt_proc    = soclib::common::alloc_elems<soclib::caba::VciSignals<vci_param> >("vci_tgt_proc"   , nb_proc);
+
+	soclib::caba::VciSignals<vci_param> signal_vci_tgt_tty("vci_tgt_tty");
+
+	soclib::caba::VciSignals<vci_param> signal_vci_tgt_simhelper("signal_vci_tgt_simhelper");
+
+	soclib::caba::VciSignals<vci_param> signal_vci_tgt_rom("vci_tgt_rom");
+
+	soclib::caba::VciSignals<vci_param> signal_vci_tgt_xram("vci_tgt_xram");
+
+	soclib::caba::VciSignals<vci_param> signal_vci_tgt_xicu("vci_tgt_xicu");
+
+	soclib::caba::VciSignals<vci_param> signal_vci_ixr_memc("vci_ixr_memc");
+	soclib::caba::VciSignals<vci_param> signal_vci_ini_memc("vci_ini_memc");
+	soclib::caba::VciSignals<vci_param> signal_vci_tgt_memc("vci_tgt_memc");
+	soclib::caba::VciSignals<vci_param> signal_vci_tgt_cleanup_memc("vci_tgt_cleanup_memc");
+
+	sc_signal<bool> ** signal_tty_irq = soclib::common::alloc_elems<sc_signal<bool> >("signal_tty_irq", nb_proc, nb_cpu_by_cache);
+
+	soclib::common::Loader loader(soft);
+
+        soclib::common::GdbServer<soclib::common::Mips32ElIss>::set_loader(loader);
+
+	soclib::caba::VciCcXCacheWrapperV4<vci_param, proc_iss > * proc [nb_proc];
+        for (uint32_t i=0; i<nb_proc; ++i)
+          {
+            uint32_t num_cpu = i*nb_cpu_by_cache;
+
+            std::ostringstream str;
+            str << "proc_" << num_cpu;
+
+            proc[i] = new soclib::caba::VciCcXCacheWrapperV4<vci_param, proc_iss > (str.str().c_str(), num_cpu, maptabp, maptabc, IntTab(i),IntTab(i),IntTab(i)
+#if USE_OLD_XCACHE
+                                                                                    ,iways, isets, iwords
+                                                                                    ,dways, dsets, dwords
+#else
+                                                                                    ,nb_cpu_by_cache   
+                                                                                    ,nb_dcache
+                                                                                    ,iways*nb_cpu_by_cache, isets, iwords
+                                                                                    ,dways*nb_cpu_by_cache, dsets, dwords
+                                                                                    ,wnwords, wnlines*nb_cpu_by_cache
+#endif
+                                                                                    );
+
+#if not USE_OLD_XCACHE
+            proc[i]->stop_simulation(STOP_SIMULATION_NB_FRZ_CYCLES);
+#endif
+          }
+
+	soclib::caba::VciSimpleRam<vci_param> 
+	rom ("rom", IntTab(0), maptabp, loader);
+
+	soclib::caba::VciSimpleRam<vci_param> 
+	xram("xram", IntTab(0), maptabx, loader);
+
+        //                                  x_init    c_init          p_tgt     c_tgt
+	soclib::caba::VciMemCacheV4<vci_param> 
+        memc("memc",maptabp,maptabc,maptabx,IntTab(0),IntTab(nb_proc),IntTab(2),IntTab(nb_proc), memc_nways, memc_nsets, memc_words, memc_heap_size);
+
+        std::vector<std::string> tty_name;
+        for (uint32_t i=0; i<nb_proc*nb_cpu_by_cache; ++i)
+          {
+            std::ostringstream str;
+            str << "tty_" << i;
+
+            tty_name.push_back(str.str());
+          }
+	
+	soclib::caba::VciMultiTty<vci_param> 
+	tty("tty",IntTab(1),maptabp,tty_name);
+
+        soclib::caba::VciXicu<vci_param> 
+        xicu("xicu", maptabp, IntTab(3), PARAM_XICU);
+
+	// soclib::caba::VciTimer<vci_param> 
+        // timer("timer", IntTab(3), maptabp, nb_proc);
+
+	soclib::caba::VciSimhelper<vci_param> 
+        simhelper("simhelper", IntTab(4), maptabp);
+
+        //                  initiatior | target 
+        // interconnect_p : proc       | rom, tty, memc, xicu, simhelper
+        // interconnect_c : proc, memc | proc, memc
+        // interconnect_x : memc       | xram
+
+	soclib::caba::VciSimpleRingFast<vci_param,40,33> 
+	interconnect_p("interconnect_p",maptabp, IntTab(), PARAM_RING_P,nb_proc  , 5        );
+
+	soclib::caba::VciSimpleRingFast<vci_param,40,33>
+	interconnect_c("interconnect_c",maptabc, IntTab(), PARAM_RING_C,nb_proc+1, nb_proc+1);
+
+	soclib::caba::VciSimpleRingFast<vci_param,40,33>
+	interconnect_x("interconnect_x",maptabx, IntTab(), PARAM_RING_X,1        , 1        );
+
+	// Net-List
+        for (uint32_t i=0; i<nb_proc; ++i)
+          {
+            proc[i]->p_clk(signal_clk);  
+            proc[i]->p_resetn(signal_resetn);
+            for (uint32_t j=0; j<nb_cpu_by_cache; ++j)
+              {
+                proc[i]->p_irq[j][0](signal_proc_it[i][j][0]);
+                proc[i]->p_irq[j][1](signal_proc_it[i][j][1]);
+                proc[i]->p_irq[j][2](signal_proc_it[i][j][2]);
+                proc[i]->p_irq[j][3](signal_proc_it[i][j][3]);
+                proc[i]->p_irq[j][4](signal_proc_it[i][j][4]);
+                proc[i]->p_irq[j][5](signal_proc_it[i][j][5]);
+              }
+            proc[i]->p_vci_ini_rw(signal_vci_ini_rw_proc[i]);
+            proc[i]->p_vci_ini_c(signal_vci_ini_c_proc[i]);
+            proc[i]->p_vci_tgt(signal_vci_tgt_proc[i]);
+          }
+
+	rom.p_clk(signal_clk);
+	rom.p_resetn(signal_resetn);
+	rom.p_vci(signal_vci_tgt_rom);
+
+	tty.p_clk(signal_clk);
+	tty.p_resetn(signal_resetn);
+	tty.p_vci(signal_vci_tgt_tty);
+        for (uint32_t i=0; i<nb_proc; ++i)
+          for (uint32_t j=0; j<nb_cpu_by_cache; ++j)
+            tty.p_irq[i*nb_cpu_by_cache+j](signal_tty_irq[i][j]); 
+
+        xicu.p_clk(signal_clk);
+        xicu.p_resetn(signal_resetn);
+        xicu.p_vci(signal_vci_tgt_xicu);
+        for (uint32_t i=0; i<nb_proc; ++i)
+          for (uint32_t j=0; j<nb_cpu_by_cache; ++j)
+          {
+            xicu.p_hwi[i*nb_cpu_by_cache+j](signal_tty_irq[i][j]);
+            xicu.p_irq[i*nb_cpu_by_cache+j](signal_proc_it[i][j][0]);
+          }
+
+        simhelper.p_clk(signal_clk);
+        simhelper.p_resetn(signal_resetn);
+        simhelper.p_vci(signal_vci_tgt_simhelper);
+
+	memc.p_clk(signal_clk);
+	memc.p_resetn(signal_resetn);
+	memc.p_vci_tgt(signal_vci_tgt_memc);
+	memc.p_vci_tgt_cleanup(signal_vci_tgt_cleanup_memc);
+	memc.p_vci_ini(signal_vci_ini_memc);
+	memc.p_vci_ixr(signal_vci_ixr_memc);
+
+	xram.p_clk(signal_clk);
+	xram.p_resetn(signal_resetn);
+	xram.p_vci(signal_vci_tgt_xram);
+        
+	interconnect_p.p_clk(signal_clk);
+	interconnect_p.p_resetn(signal_resetn);
+
+        for (uint32_t i=0; i<nb_proc; ++i)
+        interconnect_p.p_to_initiator[i](signal_vci_ini_rw_proc[i]);
+
+	interconnect_p.p_to_target[0](signal_vci_tgt_rom);
+	interconnect_p.p_to_target[1](signal_vci_tgt_tty);
+	interconnect_p.p_to_target[2](signal_vci_tgt_memc);
+	interconnect_p.p_to_target[3](signal_vci_tgt_xicu);
+	interconnect_p.p_to_target[4](signal_vci_tgt_simhelper);
+
+	interconnect_c.p_clk(signal_clk);
+	interconnect_c.p_resetn(signal_resetn);
+
+        for (uint32_t i=0; i<nb_proc; ++i)
+	interconnect_c.p_to_initiator[i](signal_vci_ini_c_proc[i]);
+	interconnect_c.p_to_initiator[nb_proc](signal_vci_ini_memc);
+
+        for (uint32_t i=0; i<nb_proc; ++i)
+	interconnect_c.p_to_target[i](signal_vci_tgt_proc[i]);
+	interconnect_c.p_to_target[nb_proc](signal_vci_tgt_cleanup_memc);
+
+	interconnect_x.p_clk(signal_clk);
+	interconnect_x.p_resetn(signal_resetn);
+
+	interconnect_x.p_to_initiator[0](signal_vci_ixr_memc);
+
+	interconnect_x.p_to_target[0](signal_vci_tgt_xram);
+
+	sc_start(sc_core::sc_time(0, SC_NS));
+	signal_resetn = false;
+	sc_start(sc_core::sc_time(1, SC_NS));
+	signal_resetn = true;
+
+#if SOCVIEW
+	debug();
+#elif DEBUG_TOP
+
+        uint32_t num_cycle=0;
+        while(1)
+          {
+            std::cout << std::endl
+                      << std::dec << "===== [ cycle " << num_cycle << " ]======" << std::endl
+                      << std::endl;
+            
+            sc_start(sc_core::sc_time(1, SC_NS));
+            
+            // for (uint32_t i=0; i<nb_proc; ++i)
+            //   proc[i]->print_trace(1);
+            num_cycle ++;
+          }
+#else
+        if (ncycles==-1)
+          sc_start();
+        else
+          sc_start(sc_core::sc_time(ncycles, SC_NS));
+
+        // sc_start(sc_core::sc_time(1013000, SC_NS));
+        // uint32_t num_cycle=1013000 ;
+
+        // for (uint32_t i=0; i<600; ++i)
+        //   {
+        //     std::cout << std::endl
+        //               << std::dec << "===== [ cycle " << num_cycle << " ]======" << std::endl
+        //               << std::endl;
+        //     sc_start(sc_core::sc_time(1, SC_NS));
+        //     interconnect_p.print_trace();
+        //     num_cycle ++;
+        //   }
+
+        // std::cout << "Hit ENTER to end simulation" << std::endl;
+        // char buf[1];
+	// std::cin.getline(buf,1);
+#endif
+        for (uint32_t i=0; i<nb_proc; ++i)
+          proc[i]->print_cpi();
+        for (uint32_t i=0; i<nb_proc; ++i)
+          proc[i]->print_stats();
+
+        soclib::common::dealloc_elems<sc_signal<bool>                     >(signal_tty_irq         , nb_proc, nb_cpu_by_cache);
+	soclib::common::dealloc_elems<soclib::caba::VciSignals<vci_param> >(signal_vci_tgt_proc    , nb_proc);
+	soclib::common::dealloc_elems<soclib::caba::VciSignals<vci_param> >(signal_vci_ini_c_proc  , nb_proc);
+	soclib::common::dealloc_elems<soclib::caba::VciSignals<vci_param> >(signal_vci_ini_rw_proc , nb_proc);
+	soclib::common::dealloc_elems<sc_signal<bool>                     >(signal_proc_it         , nb_proc, nb_cpu_by_cache, 6);
+
+        for (uint32_t i=0; i<nb_proc; ++i)
+          delete proc[i];
+
+	return EXIT_SUCCESS;
+}
+
+int sc_main (int argc, char *argv[])
+{
+  try {
+    return _main(argc, argv);
+  } catch (std::exception &e) {
+    std::cout << e.what() << std::endl;
+  } catch (...) {
+    std::cout << "Unknown exception occured" << std::endl;
+    throw;
+  }
+  return 1;
+}
Index: branches/v4/platforms/caba-ring-vcache2_memcache-mipsel/Makefile
===================================================================
--- branches/v4/platforms/caba-ring-vcache2_memcache-mipsel/Makefile	(revision 371)
+++ branches/v4/platforms/caba-ring-vcache2_memcache-mipsel/Makefile	(revision 371)
@@ -0,0 +1,6 @@
+ARCH=mips32el
+SIMULATION_ARGS=100000
+SOCLIB_CC_ADD_ARGS=-t systemcass
+SOCLIB?=$(shell soclib-cc --getpath)
+export SOCLIB
+include $(SOCLIB)/soclib/platform/topcells/all.mk
Index: branches/v4/platforms/caba-ring-vcache2_memcache-mipsel/platform_desc
===================================================================
--- branches/v4/platforms/caba-ring-vcache2_memcache-mipsel/platform_desc	(revision 371)
+++ branches/v4/platforms/caba-ring-vcache2_memcache-mipsel/platform_desc	(revision 371)
@@ -0,0 +1,27 @@
+
+# -*- python -*-
+
+
+todo = Platform('caba', 'top.cpp',
+				uses = [
+	Uses('caba:vci_cc_vcache_wrapper2_ring', iss_t = 'common:iss2_simhelper', simhelper_iss_t = 'common:mips32el'),
+	Uses('caba:vci_simple_ram'),
+	Uses('caba:vci_multi_tty'),
+	Uses('caba:vci_simple_ring_fast',
+        ring_cmd_data_size = 40,
+        ring_rsp_data_size = 33,
+),
+	Uses('caba:vci_mem_cache2'),
+	Uses('common:elf_file_loader'),
+	],
+	cell_size = 4,
+	plen_size = 8,
+	addr_size = 32,
+	rerror_size = 1,
+	clen_size = 1,
+	rflag_size = 1,
+	srcid_size = 14,
+	pktid_size = 4,
+	trdid_size = 4,
+	wrplen_size = 1
+)
Index: branches/v4/platforms/caba-ring-vcache2_memcache-mipsel/segmentation.h
===================================================================
--- branches/v4/platforms/caba-ring-vcache2_memcache-mipsel/segmentation.h	(revision 371)
+++ branches/v4/platforms/caba-ring-vcache2_memcache-mipsel/segmentation.h	(revision 371)
@@ -0,0 +1,82 @@
+
+/////////////////////////////////////////////////////////////////
+//	ADDRESS SPACE SEGMENTATION
+//
+//	This file must be included in the system.cpp file, 
+//	for harware configuration : It is used to build
+//	the SOCLIB_SEGMENT_TABLE.
+//
+//	This file can also be used by the ldscript generator,
+//	for embedded software generation.
+//	
+//	It gives the system integrator the garanty
+//	that hardware and software have the same
+//	description of the address space segmentation.
+/////////////////////////////////////////////////////////////////
+
+/////////////////////////////////////////////////////////////////
+//	reset, and exception segments
+//      base address required by MIPS processor
+/////////////////////////////////////////////////////////////////
+#define MMU
+
+#define	RESET_BASE	0xBFC00000
+#define	RESET_SIZE	0x00010000
+
+#define	EXCEP_BASE	0x80000080
+#define	EXCEP_SIZE	0x00010000
+
+#define	TEXT_BASE	0x00400000
+#define	TEXT_SIZE	0x00050000
+/////////////////////////////////////////////////////////////////
+//	global data segment (initialised)
+/////////////////////////////////////////////////////////////////
+
+#define MC_M_BASE	0x10000000
+#define MC_M_SIZE	0x00100000
+
+/////////////////////////////////////////////////////////////////
+//	page table (initialised)
+/////////////////////////////////////////////////////////////////
+#define PTD_ADDR	0x40400000
+#define PTE_ADDR	0x40402000
+#define IPTE_ADDR	0x40403000
+#define	TAB_SIZE	0x00010000
+
+#define V_TTY_BASE 	0x00800000
+#define	V_TIMER_BASE	0x00C00000	// timer virtual address
+//////////////////////////////////////////////////////////
+//	System devices
+///////////////////////////////////////////////////////////
+
+#define	TTY_BASE	0xC0200000
+#define	TTY_SIZE	0x00000100
+
+#define	TIMER_BASE	0xD0200000
+#define	TIMER_SIZE	0x00000100
+
+#define	LOCKS_BASE	0xE0200000
+#define	LOCKS_SIZE	0x00000100
+
+#define C_PROC0_BASE	0x01200000
+#define C_PROC0_SIZE	0x00000008
+
+#define C_PROC1_BASE	0x02200000
+#define C_PROC1_SIZE	0x00000008
+
+#define C_PROC2_BASE	0x03200000
+#define C_PROC2_SIZE	0x00000008
+
+#define C_PROC3_BASE	0x04200000
+#define C_PROC3_SIZE	0x00000008
+
+#define C_MC_M_BASE	0x00200000
+#define C_MC_M_SIZE	0x00000008
+
+#define XRAM_BASE	0xB0200000
+#define XRAM_SIZE	0x00000008
+
+#define MC_R_BASE	0x20200000
+#define MC_R_SIZE	0x00000008
+
+#define CLEANUP_OFFSET  0x20200000
Index: branches/v4/platforms/caba-ring-vcache2_memcache-mipsel/soft/Makefile
===================================================================
--- branches/v4/platforms/caba-ring-vcache2_memcache-mipsel/soft/Makefile	(revision 371)
+++ branches/v4/platforms/caba-ring-vcache2_memcache-mipsel/soft/Makefile	(revision 371)
@@ -0,0 +1,4 @@
+ADD_OBJS=stdlib.o stdio.o exception.o system.o
+SOCLIB?=$(shell soclib-cc --getpath)
+export SOCLIB
+include $(SOCLIB)/soclib/platform/topcells/soft.mk
Index: branches/v4/platforms/caba-ring-vcache2_memcache-mipsel/soft/main.c
===================================================================
--- branches/v4/platforms/caba-ring-vcache2_memcache-mipsel/soft/main.c	(revision 371)
+++ branches/v4/platforms/caba-ring-vcache2_memcache-mipsel/soft/main.c	(revision 371)
@@ -0,0 +1,415 @@
+#include "system.h"
+#include "stdio.h"
+#include "stdlib.h"
+
+
+#include "../segmentation.h"
+
+#define NPROCS 4
+#define SIZE 100
+#define SORT_TYPE 1
+
+volatile int lock=0;
+volatile int compteur=NPROCS;
+volatile int nprocs=NPROCS;
+
+// 100 elements
+unsigned int gQSortNum0[100] = {
+  251,  24, 113, 170, 215,  60,  83,  30, 115,  48, 169, 210,  49,  92, 101,  58,  21, 184, 225,   6,
+  199, 244, 227, 146,  99,  96,  25, 222,  65, 140, 213,  22, 219, 136, 175, 182,  73,  36, 141, 190, 
+   83, 112, 137, 114, 175, 188, 187, 102,  53, 168, 193, 154, 167, 172,   3, 242,  67,  64, 144, 137,
+  142, 175, 188,  69, 102,  53, 168, 193, 102,  89, 172, 253, 242,  67, 192,   7,  62, 159,  20, 181,
+  182, 187, 216, 207,  22, 105, 132, 109, 162, 205,  16, 151,  18, 113, 228,  37,   6,  85,   8, 161
+};
+
+unsigned int SortArr0[2*(SIZE)];
+
+void SORT(int *base, int n, int size, int (*compar) (),int type);
+void QSORT(int *base, int n, int size, int (*compar) ());
+void simple_sort(int *base, int n, int size, int (*compar) ());
+void insertion_sort(int *base, int n, int size, int (*compar) ());
+void bubble_sort(int *base, int n, int size, int (*compar) ());
+int compare(int *n1, int *n2)
+{
+  return (*((unsigned int *) n1) - *((unsigned int *) n2));
+}
+
+int main()
+{
+/* -------------------------------------------------- */
+	// define the page table entry
+        uint32_t * ptd_table;
+        ptd_table = (uint32_t *)PTD_ADDR;
+
+        ptd_table[2] = 0xC0040403; 	// PTD for instruction 	 
+        ptd_table[4] = 0xC0040402; 	// PTD for tty
+
+        ptd_table[128] = 0x8D000080; 	// PTE for data ram
+        ptd_table[1024] = 0x8D800400; 	// PTE for exception
+	
+	// tty pte
+        uint32_t * pte_table;
+        pte_table = (uint32_t *)PTE_ADDR;
+        pte_table[0] = 0x85000000;	//tty no global
+        pte_table[1] = 0x000C0200;	//tty no global
+
+	// instruction pte
+        uint32_t * ipte_table;
+        ipte_table = (uint32_t *)IPTE_ADDR;
+	ipte_table[0] = 0x8B000000;
+	ipte_table[1] = 0x00000400;
+
+	puts("Page table are defined! \n");
+
+	// context switch and tlb mode change
+	set_cp2(0, 0, 0x00020200);	// context switch
+	set_cp2(1, 0, 0xf);		// TLB enable
+	puts("Context switch(TLB flush) and TLB enable!\n");
+
+	set_cp2(2, 0, 0);
+	puts("icache flush done!\n");
+
+	set_cp2(3, 0, 0);
+	puts("dcache flush done!\n");
+
+	// cache inval
+	//set_cp2(6, 0, 0x004000a4);
+	set_cp2(6, 0, 0x004000c4);
+	puts("icache invalidation test good :-)\n");
+	set_cp2(7, 0, 0x00800000);
+	puts("dcache invalidation test good :-) \n");
+
+	// tlb inval
+	puts("TLB invalidation test begin: \n");
+	set_cp2(4, 0, 0x00400000);
+	puts("itlb invalidation test good :-) \n");
+	set_cp2(5, 0, 0x00800000);
+	puts("dtlb invalidation test good :-) \n");
+
+/* -------------------------------------------------- */
+  register int p; 
+
+  p=procnum();
+
+  puts("Hello from processor ");
+  putchar(p+'0');
+  putchar('\n');
+
+
+  int i;
+  int j;
+  int temp;
+
+  if(p+1 <= nprocs){
+	for(i=1 ; i <= 8 ; i++ ){
+  	puts("Memory copy \n");
+	memcpy(SortArr0+p*(SIZE), gQSortNum0 + ( (4*(p+1)*i) % 32) ,SIZE);
+	
+  	puts("Sort... \n");
+  	SORT((int *) (SortArr0+p*(SIZE)), (int) SIZE, sizeof(unsigned int), compare,SORT_TYPE);
+  	for (j = 1; j < SIZE; j++)
+    	{
+      		if (SortArr0[p*(SIZE)+j] < SortArr0[p*(SIZE) + j - 1])
+		{
+	  		puts("ucbqsort: failed\n");
+			while(1);
+		}
+
+    	}
+  	puts("ucbqsort: success\n");
+	}
+  }
+  
+
+  if(p+1 <= nprocs){
+	lock_lock(&lock);
+	compteur--;
+	if(!compteur){
+  		putchar('\n');
+  		puti(temp);
+  		putchar('\n');
+	}
+	lock_unlock(&lock);
+  }
+
+  while(1);
+}
+
+static int (*qcmp) ();
+static int qsz;
+static int thresh;
+static int mthresh;
+static void qst(int *, int *);
+void QSORT(base, n, size, compar)
+     int *base;
+     int n;
+     int size;
+     int (*compar) ();
+{
+  register int c, *i, *j, *lo, *hi;
+  int *min, *max;
+  if (n <= 1)
+    return;
+  qsz = size;
+  qcmp = compar;
+  thresh = 4;
+  mthresh = 6;
+  max = base + n;
+  if (n >= 4)
+    {
+      qst(base, max);
+      hi = base + thresh;
+    } 
+  else
+    {
+      hi = max;
+    }
+
+  puts("Quick sort done... \n");
+
+  for (j = lo = base; (lo ++) < hi;)
+    if ((*qcmp) (j, lo) > 0)
+      j = lo;
+  if (j != base)
+    {
+      for (i = base, hi = base + 1; i < hi;)
+	{
+	  c = *j;
+	  *j++ = *i;
+	  *i++ = c;
+	}
+
+    }
+  for (min = base; (hi = min ++) < max;)
+    {
+      while ((*qcmp) (hi --, min) > 0)
+	;
+      if ((hi ++) != min)
+	{
+	  for (lo = min + 1; --lo >= min;)
+	    {
+	      c = *lo;
+	      for (i = j = lo; (j --) >= hi; i = j)
+		*i = *j;
+	      *i = c;
+	    }
+
+	}
+    }
+
+}
+
+
+void simple_sort(base, n, size, compar)
+     int *base;
+     int n;
+     int size;
+     int (*compar) ();
+{
+  register int c, *i, *j, *lo, p, *k;
+  int *max;
+  if (n <= 1)
+    return;
+  qsz = size;
+  qcmp = compar;
+  max = base + n;
+  puts("Selection Sort\n");
+  p=procnum();
+//  k=4;
+  for(j = base; j < max ; j++){
+    lo=j;
+    c=(*lo);
+    for(i = j; i < max ; i++){
+	asm("	nop		\n"); //1
+      if( c-(*i) > 0){
+ 	lo=i;
+        c=(*lo);
+      }
+      asm("	nop		\n"); // 1
+    }
+    *lo = *j;
+    *j = c;
+  }
+}
+
+void insertion_sort(base, n, size, compar)
+     int *base;
+     int n;
+     int size;
+     int (*compar) ();
+{
+  register int c, *i, *j,p;
+  int *max;
+  if (n <= 1)
+    return;
+  qsz = size;
+  qcmp = compar;
+  max = base + n;
+  puts("Insertion Sort\n");
+  p=procnum();
+  for(j = base; j < max-1 ; j++){
+    for(i = j; i < max-1 ; i++){
+      if( (*i)-(*(i+1)) > 0){
+ 	c = *i;
+	*i = *(i+1);
+	*(i+1)=c;
+      }
+    }
+  }
+}
+
+
+void bubble_sort(base, n, size, compar)
+     int *base;
+     int n;
+     int size;
+     int (*compar) ();
+{
+  register int c, *i;
+  register int b_swap=1;
+  int *max;
+  if (n <= 1)
+    return;
+  qsz = size;
+  qcmp = compar;
+  max = base + n;
+  puts("Bubble Sort\n");
+  while(b_swap){
+    b_swap=0;
+    for(i = base; i < max-1 ; i++){
+      if( (*i)-(*(i+1)) > 0){
+	b_swap=1;
+ 	c = *i;
+	*i = *(i+1);
+	*(i+1)=c;
+      }
+    }
+  }
+}
+
+static
+void qst(base, max)
+     int *base, *max;
+{
+  register int c, *i, *j, *jj;
+  register int ii;
+  int *mid, *tmp;
+  int lo, hi;
+  lo = max - base;
+  do
+    {
+      mid = i = base + 1 * ((lo / qsz) >> 1);
+      if (lo >= mthresh)
+	{
+	  j = ((*qcmp) ((jj = base), i) > 0 ? jj : i);
+	  if ((*qcmp) (j, (tmp = max - 1)) > 0)
+	    {
+	      j = (j == jj ? i : jj);
+	      if ((*qcmp) (j, tmp) < 0)
+		j = tmp;
+	    }
+
+	  if (j != i)
+	    {
+	      ii = 1;
+	      do
+		{
+		  c = *i;
+		  *i++ = *j;
+		  *j++ = c;
+		}
+
+	      while (--ii);
+	    }
+
+	}
+      for (i = base, j = max - 1;;)
+	{
+	  while (i < mid && (*qcmp) (i, mid) <= 0)
+            i ++;
+	  while (j > mid)
+	    {
+	      if ((*qcmp) (mid, j) <= 0)
+		{
+		  j --;
+		  continue;
+		}
+
+	      tmp = i + 1;
+	      if (i == mid)
+		{
+		  mid = jj = j;
+		} 
+	      else
+		{
+		  jj = j;
+		  j --;
+		}
+
+	      goto swap;
+	    }
+
+	  if (i == mid)
+	    {
+	      break;
+	    } 
+	  else
+	    {
+	      jj = mid;
+	      tmp = mid = i;
+	      j --;
+	    }
+
+	swap:
+	  ii = 1;
+	  do
+	    {
+	      c = *i;
+	      *i++ = *jj;
+	      *jj++ = c;
+	    }
+
+	  while (--ii);
+	  i = tmp;
+	}
+
+      i = (j = mid) + 1;
+      if ((lo = j - base) <= (hi = max - i))
+	{
+	  if (lo >= thresh)
+            qst(base, j);
+	  base = i;
+	  lo = hi;
+	} 
+      else
+	{
+	  if (hi >= thresh)
+            qst(i, max);
+	  max = j;
+	}
+
+    }
+  while (lo >= thresh);
+}
+
+void SORT(int *base, int n, int size, int (*compar) (),int type){
+  switch(type){
+  case 0:
+    QSORT(base, n, size, compar);
+    break;
+  case 1:
+    simple_sort(base, n, size, compar);
+    break;
+  case 2:
+    insertion_sort(base, n, size, compar);
+    break;
+  case 3:
+    bubble_sort(base, n, size, compar);
+    break;
+  default:
+    break;
+  }
+
+}
+
+
Index: branches/v4/platforms/caba-ring-vcache2_memcache-mipsel/top.cpp
===================================================================
--- branches/v4/platforms/caba-ring-vcache2_memcache-mipsel/top.cpp	(revision 371)
+++ branches/v4/platforms/caba-ring-vcache2_memcache-mipsel/top.cpp	(revision 371)
@@ -0,0 +1,338 @@
+
+#include <systemc>
+#include <sys/time.h>
+#include <iostream>
+#include <cstdlib>
+#include <cstdarg>
+
+#include "mapping_table.h"
+#include "mips32.h"
+#include "iss2_simhelper.h"
+#include "vci_simple_ram.h"
+#include "vci_multi_tty.h"
+#include "vci_simple_ring_fast.h"
+#include "vci_mem_cache2.h"
+#include "vci_cc_vcache_wrapper2_ring.h"
+
+#ifdef USE_GDB_SERVER
+#include "iss/gdbserver.h"
+#endif
+
+#include "segmentation.h"
+
+int _main(int argc, char *argv[])
+{
+	using namespace sc_core;
+	// Avoid repeating these everywhere
+	using soclib::common::IntTab;
+	using soclib::common::Segment;
+
+	// Define VCI parameters
+	typedef soclib::caba::VciParams<4,8,32,1,1,1,14,4,4,1> vci_param;
+	typedef soclib::common::Iss2Simhelper<soclib::common::Mips32ElIss> proc_iss;
+	// Mapping table
+
+	soclib::common::MappingTable maptabp(32, IntTab(8), IntTab(8), 0x00300000);
+
+	maptabp.add(Segment("reset", RESET_BASE, RESET_SIZE, IntTab(2), true));
+	maptabp.add(Segment("excep", EXCEP_BASE, EXCEP_SIZE, IntTab(2), true));
+	maptabp.add(Segment("text" , TEXT_BASE , TEXT_SIZE , IntTab(2), true));
+	maptabp.add(Segment("tty"  , TTY_BASE  , TTY_SIZE  , IntTab(1), false));
+	maptabp.add(Segment("mc_r" , MC_R_BASE , MC_R_SIZE , IntTab(2), false, true, IntTab(0)));
+	maptabp.add(Segment("mc_m" , MC_M_BASE , MC_M_SIZE , IntTab(2), true ));
+	maptabp.add(Segment("ptba" , PTD_ADDR , TAB_SIZE   , IntTab(2), true));
+ 
+//	std::cout << maptabp << std::endl;
+
+        soclib::common::MappingTable maptabc(32, IntTab(8), IntTab(8), 0x00300000);
+	maptabc.add(Segment("c_proc0" , C_PROC0_BASE , C_PROC0_SIZE , IntTab(0), false, true, IntTab(0)));
+	maptabc.add(Segment("c_proc1" , C_PROC1_BASE , C_PROC1_SIZE , IntTab(1), false, true, IntTab(1)));
+	maptabc.add(Segment("c_proc2" , C_PROC2_BASE , C_PROC2_SIZE , IntTab(2), false, true, IntTab(2)));
+	maptabc.add(Segment("c_proc3" , C_PROC3_BASE , C_PROC3_SIZE , IntTab(3), false, true, IntTab(3)));
+	maptabc.add(Segment("mc_r"    , MC_R_BASE , MC_R_SIZE , IntTab(4), false, false));
+	maptabc.add(Segment("mc_m"  , MC_M_BASE , MC_M_SIZE  , IntTab(4), false, false));
+	maptabc.add(Segment("reset", RESET_BASE, RESET_SIZE, IntTab(4), false, false));
+	maptabc.add(Segment("excep", EXCEP_BASE, EXCEP_SIZE, IntTab(4), false, false));
+	maptabc.add(Segment("text" , TEXT_BASE , TEXT_SIZE , IntTab(4), false, false));
+	maptabc.add(Segment("ptba" , PTD_ADDR  , TAB_SIZE  , IntTab(4), false, false));
+
+//	std::cout << maptabc << std::endl;
+	
+	soclib::common::MappingTable maptabx(32, IntTab(8), IntTab(8), 0x00300000);
+	maptabx.add(Segment("xram" , MC_M_BASE , MC_M_SIZE , IntTab(0), false));
+	maptabx.add(Segment("reset", RESET_BASE, RESET_SIZE, IntTab(0), false));
+	maptabx.add(Segment("excep", EXCEP_BASE, EXCEP_SIZE, IntTab(0), false));
+	maptabx.add(Segment("text" , TEXT_BASE , TEXT_SIZE , IntTab(0), false));
+	maptabx.add(Segment("ptba" , PTD_ADDR  , TAB_SIZE  , IntTab(0), false));
+	
+//	std::cout << maptabx << std::endl;
+
+	// Signals
+	sc_clock	signal_clk("clk");
+	sc_signal<bool> signal_resetn("resetn");
+   
+	sc_signal<bool> signal_proc0_it0("proc0_it0"); 
+	sc_signal<bool> signal_proc0_it1("proc0_it1"); 
+	sc_signal<bool> signal_proc0_it2("proc0_it2"); 
+	sc_signal<bool> signal_proc0_it3("proc0_it3"); 
+	sc_signal<bool> signal_proc0_it4("proc0_it4"); 
+	sc_signal<bool> signal_proc0_it5("proc0_it5");
+
+	sc_signal<bool> signal_proc1_it0("proc1_it0"); 
+	sc_signal<bool> signal_proc1_it1("proc1_it1"); 
+	sc_signal<bool> signal_proc1_it2("proc1_it2"); 
+	sc_signal<bool> signal_proc1_it3("proc1_it3"); 
+	sc_signal<bool> signal_proc1_it4("proc1_it4"); 
+	sc_signal<bool> signal_proc1_it5("proc1_it5");
+
+	sc_signal<bool> signal_proc2_it0("proc2_it0"); 
+	sc_signal<bool> signal_proc2_it1("proc2_it1"); 
+	sc_signal<bool> signal_proc2_it2("proc2_it2"); 
+	sc_signal<bool> signal_proc2_it3("proc2_it3"); 
+	sc_signal<bool> signal_proc2_it4("proc2_it4"); 
+	sc_signal<bool> signal_proc2_it5("proc2_it5");
+
+	sc_signal<bool> signal_proc3_it0("proc3_it0"); 
+	sc_signal<bool> signal_proc3_it1("proc3_it1"); 
+	sc_signal<bool> signal_proc3_it2("proc3_it2"); 
+	sc_signal<bool> signal_proc3_it3("proc3_it3"); 
+	sc_signal<bool> signal_proc3_it4("proc3_it4"); 
+	sc_signal<bool> signal_proc3_it5("proc3_it5");
+
+	soclib::caba::VciSignals<vci_param> signal_vci_ini_rw_proc0("vci_ini_rw_proc0");
+	soclib::caba::VciSignals<vci_param> signal_vci_ini_c_proc0("vci_ini_c_proc0");
+
+	soclib::caba::VciSignals<vci_param> signal_vci_tgt_proc0("vci_tgt_proc0");
+
+	soclib::caba::VciSignals<vci_param> signal_vci_ini_rw_proc1("vci_ini_rw_proc1");
+	soclib::caba::VciSignals<vci_param> signal_vci_ini_c_proc1("vci_ini_c_proc1");
+
+	soclib::caba::VciSignals<vci_param> signal_vci_tgt_proc1("vci_tgt_proc1");
+
+	soclib::caba::VciSignals<vci_param> signal_vci_ini_rw_proc2("vci_ini_rw_proc2");
+	soclib::caba::VciSignals<vci_param> signal_vci_ini_c_proc2("vci_ini_c_proc2");
+
+	soclib::caba::VciSignals<vci_param> signal_vci_tgt_proc2("vci_tgt_proc2");
+
+	soclib::caba::VciSignals<vci_param> signal_vci_ini_rw_proc3("vci_ini_rw_proc3");
+	soclib::caba::VciSignals<vci_param> signal_vci_ini_c_proc3("vci_ini_c_proc3");
+
+	soclib::caba::VciSignals<vci_param> signal_vci_tgt_proc3("vci_tgt_proc3");
+
+	soclib::caba::VciSignals<vci_param> signal_vci_tgt_tty("vci_tgt_tty");
+
+	soclib::caba::VciSignals<vci_param> signal_vci_tgt_rom("vci_tgt_rom");
+
+	soclib::caba::VciSignals<vci_param> signal_vci_tgt_xram("vci_tgt_xram");
+
+	soclib::caba::VciSignals<vci_param> signal_vci_ixr_memc("vci_ixr_memc");
+	soclib::caba::VciSignals<vci_param> signal_vci_ini_memc("vci_ini_memc");
+	soclib::caba::VciSignals<vci_param> signal_vci_tgt_memc("vci_tgt_memc");
+	soclib::caba::VciSignals<vci_param> signal_vci_tgt_cleanup_memc("vci_tgt_cleanup_memc");
+
+	sc_signal<bool> signal_tty_irq0("signal_tty_irq0"); 
+	sc_signal<bool> signal_tty_irq1("signal_tty_irq1"); 
+	sc_signal<bool> signal_tty_irq2("signal_tty_irq2"); 
+	sc_signal<bool> signal_tty_irq3("signal_tty_irq3"); 
+
+	soclib::common::Loader loader("soft/bin.soft");
+
+        //                                  init_rw   init_c   tgt
+	soclib::caba::VciCcVCacheWrapper2Ring<vci_param, proc_iss > 
+	proc0("proc0", 0, maptabp, maptabc, IntTab(0),IntTab(0),IntTab(0),4,16,4,16,4,64,16,4,64,16,16);
+	
+	soclib::caba::VciCcVCacheWrapper2Ring<vci_param, proc_iss > 
+	proc1("proc1", 1, maptabp, maptabc, IntTab(1),IntTab(1),IntTab(1),4,16,4,16,4,64,16,4,64,16,16);
+
+	soclib::caba::VciCcVCacheWrapper2Ring<vci_param, proc_iss > 
+	proc2("proc2", 2, maptabp, maptabc, IntTab(2),IntTab(2),IntTab(2),4,16,4,16,4,64,16,4,64,16,16);
+	
+	soclib::caba::VciCcVCacheWrapper2Ring<vci_param, proc_iss > 
+	proc3("proc3", 3, maptabp, maptabc, IntTab(3),IntTab(3),IntTab(3),4,16,4,16,4,64,16,4,64,16,16);
+
+	soclib::caba::VciSimpleRam<vci_param> 
+	rom("rom", IntTab(0), maptabp, loader);
+
+	soclib::caba::VciSimpleRam<vci_param> 
+	xram("xram", IntTab(0), maptabx, loader);
+
+        //                                  x_init    c_init    p_tgt     c_tgt
+	soclib::caba::VciMemCache2<vci_param> 
+	memc("memc",maptabp,maptabc,maptabx,IntTab(0),IntTab(4),IntTab(2), IntTab(4),16,256,16);
+	//memc("memc",maptabp,maptabc,maptabx,IntTab(0),IntTab(4),IntTab(2), IntTab(4),4,16,16);
+	
+	soclib::caba::VciMultiTty<vci_param> 
+	tty("tty",IntTab(1),maptabp,"tty0","tty1","tty2","tty3",NULL);
+
+	soclib::caba::VciSimpleRingFast<vci_param, 40, 33> 
+	ringp("ringp",maptabp, IntTFast, 4, 3);
+
+	soclib::caba::VciSimpleRingFast<vci_param, 40, 33> 
+	ringc("ringc",maptabc, IntTFast, 5, 5);
+
+	soclib::caba::VciSimpleRingFast<vci_param, 40, 33> 
+	ringx("ringx",maptabx, IntTab(), 2, 1, 1);
+
+	// Net-List
+ 
+	proc0.p_clk(signal_clk);  
+	proc0.p_resetn(signal_resetn);  
+	proc0.p_irq[0](signal_proc0_it0); 
+	proc0.p_irq[1](signal_proc0_it1); 
+	proc0.p_irq[2](signal_proc0_it2); 
+	proc0.p_irq[3](signal_proc0_it3); 
+	proc0.p_irq[4](signal_proc0_it4); 
+	proc0.p_irq[5](signal_proc0_it5); 
+	proc0.p_vci_ini_rw(signal_vci_ini_rw_proc0);
+	proc0.p_vci_ini_c(signal_vci_ini_c_proc0);
+	proc0.p_vci_tgt(signal_vci_tgt_proc0);
+
+	proc1.p_clk(signal_clk);  
+	proc1.p_resetn(signal_resetn);  
+	proc1.p_irq[0](signal_proc1_it0); 
+	proc1.p_irq[1](signal_proc1_it1); 
+	proc1.p_irq[2](signal_proc1_it2); 
+	proc1.p_irq[3](signal_proc1_it3); 
+	proc1.p_irq[4](signal_proc1_it4); 
+	proc1.p_irq[5](signal_proc1_it5); 
+	proc1.p_vci_ini_rw(signal_vci_ini_rw_proc1);
+	proc1.p_vci_ini_c(signal_vci_ini_c_proc1);
+	proc1.p_vci_tgt(signal_vci_tgt_proc1);
+
+	proc2.p_clk(signal_clk);  
+	proc2.p_resetn(signal_resetn);  
+	proc2.p_irq[0](signal_proc2_it0); 
+	proc2.p_irq[1](signal_proc2_it1); 
+	proc2.p_irq[2](signal_proc2_it2); 
+	proc2.p_irq[3](signal_proc2_it3); 
+	proc2.p_irq[4](signal_proc2_it4); 
+	proc2.p_irq[5](signal_proc2_it5); 
+	proc2.p_vci_ini_rw(signal_vci_ini_rw_proc2);
+	proc2.p_vci_ini_c(signal_vci_ini_c_proc2);
+	proc2.p_vci_tgt(signal_vci_tgt_proc2);
+
+	proc3.p_clk(signal_clk);  
+	proc3.p_resetn(signal_resetn);  
+	proc3.p_irq[0](signal_proc3_it0); 
+	proc3.p_irq[1](signal_proc3_it1); 
+	proc3.p_irq[2](signal_proc3_it2); 
+	proc3.p_irq[3](signal_proc3_it3); 
+	proc3.p_irq[4](signal_proc3_it4); 
+	proc3.p_irq[5](signal_proc3_it5); 
+	proc3.p_vci_ini_rw(signal_vci_ini_rw_proc3);
+	proc3.p_vci_ini_c(signal_vci_ini_c_proc3);
+	proc3.p_vci_tgt(signal_vci_tgt_proc3);
+
+	rom.p_clk(signal_clk);
+	rom.p_resetn(signal_resetn);
+	rom.p_vci(signal_vci_tgt_rom);
+
+	tty.p_clk(signal_clk);
+	tty.p_resetn(signal_resetn);
+	tty.p_vci(signal_vci_tgt_tty);
+	tty.p_irq[0](signal_tty_irq0); 
+	tty.p_irq[1](signal_tty_irq1); 
+	tty.p_irq[2](signal_tty_irq2); 
+	tty.p_irq[3](signal_tty_irq3); 
+
+	memc.p_clk(signal_clk);
+	memc.p_resetn(signal_resetn);
+	memc.p_vci_tgt(signal_vci_tgt_memc);
+	memc.p_vci_tgt_cleanup(signal_vci_tgt_cleanup_memc);
+	memc.p_vci_ini(signal_vci_ini_memc);
+	memc.p_vci_ixr(signal_vci_ixr_memc);
+
+	xram.p_clk(signal_clk);
+  xram.p_resetn(signal_resetn);
+	xram.p_vci(signal_vci_tgt_xram);
+	
+	ringp.p_clk(signal_clk);
+	ringp.p_resetn(signal_resetn);
+
+	ringc.p_clk(signal_clk);
+	ringc.p_resetn(signal_resetn);
+
+	ringx.p_clk(signal_clk);
+	ringx.p_resetn(signal_resetn);
+
+	ringp.p_to_initiator[0](signal_vci_ini_rw_proc0);
+	ringp.p_to_initiator[1](signal_vci_ini_rw_proc1);
+	ringp.p_to_initiator[2](signal_vci_ini_rw_proc2);
+	ringp.p_to_initiator[3](signal_vci_ini_rw_proc3);
+
+	ringc.p_to_initiator[4](signal_vci_ini_memc);
+	ringc.p_to_initiator[0](signal_vci_ini_c_proc0);
+	ringc.p_to_initiator[1](signal_vci_ini_c_proc1);
+	ringc.p_to_initiator[2](signal_vci_ini_c_proc2);
+	ringc.p_to_initiator[3](signal_vci_ini_c_proc3);
+
+	ringx.p_to_initiator[0](signal_vci_ixr_memc);
+
+	ringp.p_to_target[0](signal_vci_tgt_rom);
+	ringp.p_to_target[1](signal_vci_tgt_tty);
+	ringp.p_to_target[2](signal_vci_tgt_memc);
+
+	ringc.p_to_target[0](signal_vci_tgt_proc0);
+	ringc.p_to_target[1](signal_vci_tgt_proc1);
+	ringc.p_to_target[2](signal_vci_tgt_proc2);
+	ringc.p_to_target[3](signal_vci_tgt_proc3);
+	ringc.p_to_target[4](signal_vci_tgt_cleanup_memc);
+
+	ringx.p_to_target[0](signal_vci_tgt_xram);
+
+	int ncycles;
+
+#ifndef SOCVIEW
+	if (argc == 2) {
+		ncycles = std::atoi(argv[1]);
+	} else {
+		std::cerr
+			<< std::endl
+			<< "The number of simulation cycles must "
+			   "be defined in the command line"
+			<< std::endl;
+		exit(1);
+	}
+
+	sc_start(sc_core::sc_time(0, SC_NS));
+	signal_resetn = false;
+
+	sc_start(sc_core::sc_time(1, SC_NS));
+	signal_resetn = true;
+
+	for (int i = 0; i < ncycles ; i+=1000) {
+		sc_start(sc_core::sc_time(1000, SC_NS));
+		//proc.print_stats();
+		//memc.print_stats();
+	}
+
+        std::cout << "Hit ENTER to end simulation" << std::endl;
+        char buf[1];
+
+	std::cin.getline(buf,1);
+
+	return EXIT_SUCCESS;
+#else
+	ncycles = 1;
+	sc_start(sc_core::sc_time(0, SC_NS));
+	signal_resetn = false;
+	sc_start(sc_core::sc_time(1, SC_NS));
+	signal_resetn = true;
+
+	debug();
+	return EXIT_SUCCESS;
+#endif
+}
+
+int sc_main (int argc, char *argv[])
+{
+	try {
+		return _main(argc, argv);
+	} catch (std::exception &e) {
+		std::cout << e.what() << std::endl;
+	} catch (...) {
+		std::cout << "Unknown exception occured" << std::endl;
+		throw;
+	}
+	return 1;
+}
Index: branches/v4/platforms/caba-tsar-v0/Makefile
===================================================================
--- branches/v4/platforms/caba-tsar-v0/Makefile	(revision 371)
+++ branches/v4/platforms/caba-tsar-v0/Makefile	(revision 371)
@@ -0,0 +1,5 @@
+ARCH=mipsel
+SIMULATION_ARGS=100000
+SOCLIB?=$(shell soclib-cc --getpath)
+export SOCLIB
+include $(SOCLIB)/soclib/platform/topcells/all.mk
Index: branches/v4/platforms/caba-tsar-v0/platform_desc
===================================================================
--- branches/v4/platforms/caba-tsar-v0/platform_desc	(revision 371)
+++ branches/v4/platforms/caba-tsar-v0/platform_desc	(revision 371)
@@ -0,0 +1,26 @@
+
+# -*- python -*-
+
+
+todo = Platform('caba', 'top.cpp',
+				uses = [
+        Uses('caba:vci_cc_xcache_wrapper', iss_t = 'common:ississ2', iss2_t = 'common:iss_simhelper', simhelper_iss_t = 'common:mipsel'),
+	Uses('caba:vci_simple_ram'),
+	Uses('caba:vci_multi_tty'),
+	Uses('caba:vci_local_crossbar'),
+	Uses('caba:vci_mem_cache'),
+	Uses('caba:vci_vgmn'),
+	Uses('caba:vci_dspinplus_network',dspin_fifo_size = 4, dspin_yx_size = 1),
+		Uses('common:elf_file_loader'),
+	],
+	cell_size = 4,
+	plen_size = 8,
+	addr_size = 32,
+	rerror_size = 1,
+	clen_size = 1,
+	rflag_size = 1,
+	srcid_size = 8,
+	pktid_size = 4,
+	trdid_size = 4,
+	wrplen_size = 1
+)
Index: branches/v4/platforms/caba-tsar-v0/segmentation.h
===================================================================
--- branches/v4/platforms/caba-tsar-v0/segmentation.h	(revision 371)
+++ branches/v4/platforms/caba-tsar-v0/segmentation.h	(revision 371)
@@ -0,0 +1,121 @@
+
+/////////////////////////////////////////////////////////////////
+//	ADDRESS SPACE SEGMENTATION
+//
+//	This file must be included in the system.cpp file, 
+//	for harware configuration : It is used to build
+//	the SOCLIB_SEGMENT_TABLE.
+//
+//	This file can also be used by the ldscript generator,
+//	for embedded software generation.
+//	
+//	It gives the system integrator the garanty
+//	that hardware and software have the same
+//	description of the address space segmentation.
+/////////////////////////////////////////////////////////////////
+
+///////////////////////////////////////////////////////////////////////////////////
+//	reset, and exception segments
+//      base address required by MIPS processor
+///////////////////////////////////////////////////////////////////////////////////
+
+#define	RESET_BASE	0xBFC00000
+#define	RESET_SIZE	0x00010000
+
+#define	EXCEP_BASE	0x80000000
+#define	EXCEP_SIZE	0x00010000
+
+///////////////////////////////////////////////////////////////////////////////////
+//	global data segment (initialised)
+///////////////////////////////////////////////////////////////////////////////////
+
+#define MC0_M_BASE	0x10000000
+#define MC0_M_SIZE	0x00400000
+
+#define MC1_M_BASE	0x50000000
+#define MC1_M_SIZE	0x00400000
+
+#define MC2_M_BASE	0x91000000
+#define MC2_M_SIZE	0x00400000
+
+#define MC3_M_BASE	0xD0000000
+#define MC3_M_SIZE	0x00400000
+
+////////////////////////////////////////////////////////////////////////////////
+//	System devices (seen by the software)
+////////////////////////////////////////////////////////////////////////////////
+
+#define	TTY_BASE	0xC1400000
+#define	TTY_SIZE	0x00000100
+
+#define	TIMER_BASE	0xD1400000
+#define	TIMER_SIZE	0x00000100
+
+#define	LOCKS_BASE	0xE1400000
+#define	LOCKS_SIZE	0x00000100
+
+#define MC0_R_BASE	0x1F400000
+#define MC0_R_SIZE	0x00000008
+
+#define MC1_R_BASE	0x5F400000
+#define MC1_R_SIZE	0x00000008
+
+#define MC2_R_BASE	0x9F400000
+#define MC2_R_SIZE	0x00000008
+
+#define MC3_R_BASE	0xDF400000
+#define MC3_R_SIZE	0x00000008
+
+////////////////////////////////////////////////////////////////////////////////
+//	System devices (NOT seen by the software)
+////////////////////////////////////////////////////////////////////////////////
+
+#define PROC0_BASE	0x01400000
+#define PROC0_SIZE	0x00000008
+
+#define PROC1_BASE	0x02400000
+#define PROC1_SIZE	0x00000008
+
+#define PROC2_BASE	0x03400000
+#define PROC2_SIZE	0x00000008
+
+#define PROC3_BASE	0x04400000
+#define PROC3_SIZE	0x00000008
+
+#define PROC4_BASE	0x43400000
+#define PROC4_SIZE	0x00000008
+
+#define PROC5_BASE	0x44400000
+#define PROC5_SIZE	0x00000008
+
+#define PROC6_BASE	0x45400000
+#define PROC6_SIZE	0x00000008
+
+#define PROC7_BASE	0x46400000
+#define PROC7_SIZE	0x00000008
+
+#define PROC8_BASE	0xA3400000
+#define PROC8_SIZE	0x00000008
+
+#define PROC9_BASE	0xA4400000
+#define PROC9_SIZE	0x00000008
+
+#define PROC10_BASE	0xA5400000
+#define PROC10_SIZE	0x00000008
+
+#define PROC11_BASE	0xA6400000
+#define PROC11_SIZE	0x00000008
+
+#define PROC12_BASE	0xE2400000
+#define PROC12_SIZE	0x00000008
+
+#define PROC13_BASE	0xE3400000
+#define PROC13_SIZE	0x00000008
+
+#define PROC14_BASE	0xE4400000
+#define PROC14_SIZE	0x00000008
+
+#define PROC15_BASE	0xE5400000
+#define PROC15_SIZE	0x00000008
+
+#define CLEANUP_OFFSET  0x1F400000
Index: branches/v4/platforms/caba-tsar-v0/soft/Makefile
===================================================================
--- branches/v4/platforms/caba-tsar-v0/soft/Makefile	(revision 371)
+++ branches/v4/platforms/caba-tsar-v0/soft/Makefile	(revision 371)
@@ -0,0 +1,4 @@
+ADD_OBJS=stdlib.o stdio.o
+SOCLIB?=$(shell soclib-cc --getpath)
+export SOCLIB
+include $(SOCLIB)/soclib/platform/topcells/soft.mk
Index: branches/v4/platforms/caba-tsar-v0/soft/ldscript
===================================================================
--- branches/v4/platforms/caba-tsar-v0/soft/ldscript	(revision 371)
+++ branches/v4/platforms/caba-tsar-v0/soft/ldscript	(revision 371)
@@ -0,0 +1,114 @@
+/*
+ *
+ * SOCLIB_GPL_HEADER_BEGIN
+ * 
+ * This file is part of SoCLib, GNU GPLv2.
+ * 
+ * SoCLib is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ * 
+ * SoCLib is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * General Public License for more details.
+ * 
+ * You should have received a copy of the GNU General Public License
+ * along with SoCLib; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301, USA.
+ * 
+ * SOCLIB_GPL_HEADER_END
+ *
+ * Copyright (c) UPMC, Lip6, SoC
+ *         Nicolas Pouillon <nipo@ssji.net>, 2006-2007
+ *
+ * Maintainers: nipo
+ */
+
+SECTIONS
+{
+	special_base = 0x00500000;
+	. = special_base;
+    .ppc_special : {
+		. = 0x100;
+		*(.ppc_special.critical_input)
+		. = 0x200;
+		*(.ppc_special.machine_check)
+		. = 0x300;
+		*(.ppc_special.data_storage)
+		. = 0x400;
+		*(.ppc_special.instruction_storage)
+		. = 0x500;
+		*(.ppc_special.external)
+		. = 0x600;
+		*(.ppc_special.alignment)
+		. = 0x700;
+		*(.ppc_special.program)
+		. = 0xc00;
+		*(.ppc_special.syscall)
+		. = 0x1000;
+		*(.ppc_special.programmable_interval_timer)
+		. = 0x1010;
+		*(.ppc_special.fixed_interval_timer)
+		. = 0x1020;
+		*(.ppc_special.watchdog)
+		. = 0x1100;
+		*(.ppc_special.data_tlb_miss)
+		. = 0x1200;
+		*(.ppc_special.instruction_tlb_miss)
+		. = 0x2000;
+		*(.ppc_special.debug)
+    }
+
+    . = 0xfffffffc;
+    .ppc_boot : {
+		*(.ppc_boot)
+		*(.ppc_boot.*)
+    }
+
+   . = 0x80000000;
+   .excep : {
+		*(.excep)
+		*(.excep.*)
+   }
+
+   . = 0xbfc00000;
+   .reset : {
+		*(.reset)
+		*(.reset.*)
+   }
+
+   . = 0x10020000;
+   .text : {
+      *(.text)
+   }
+   . = 0x10070000;
+   .rodata : {
+      *(.rodata)
+      . = ALIGN(4);
+   }
+   .data  : {
+      *(.data)
+   }
+   .sdata : {
+      *(.lit8)
+      *(.lit4)
+      *(.sdata)
+   }
+   _gp = .;
+   . = ALIGN(4);
+   _edata = .;
+   .sbss  : {
+      *(.sbss)
+      *(.scommon)
+   }
+   .bss   : {
+      *(.bss)
+      *(COMMON)
+   }
+   . = ALIGN(4);
+   _end = .;
+   _heap = .;
+   _stack = 0x10070000-16;
+}
Index: branches/v4/platforms/caba-tsar-v0/soft/main.c
===================================================================
--- branches/v4/platforms/caba-tsar-v0/soft/main.c	(revision 371)
+++ branches/v4/platforms/caba-tsar-v0/soft/main.c	(revision 371)
@@ -0,0 +1,1113 @@
+#include "system.h"
+#include "stdio.h"
+#include "stdlib.h"
+
+
+#include "../segmentation.h"
+
+#define NPROCS 16
+#define SIZE 8000
+#define SORT_TYPE 2
+
+volatile int lock=0;
+volatile int compteur=NPROCS;
+volatile int nprocs=NPROCS;
+
+volatile int write_boost[16*120];
+
+unsigned int gQSortNum0[16000] = {
+  251, 24, 113, 170, 215, 60, 83, 30, 115, 48, 169, 210, 49, 92, 101, 58, 21, 184, 225, 6,
+  199, 244, 227, 146, 99, 96, 25, 222, 65, 140, 213, 22, 219, 136, 175, 182, 73, 36, 141, 190, 
+  83, 112, 137, 114, 175, 188, 187, 102, 53, 168, 193, 154, 167, 172, 3, 242, 67, 64,144, 137,
+  142, 175, 188, 69, 102, 53, 168, 193, 102, 89, 172, 253, 242, 67,192, 7, 62, 159, 20, 181,
+  182, 187, 216, 207, 22, 105, 132, 109, 162, 205, 16, 151, 18, 113, 228, 37, 6, 85, 8, 161,
+  58, 135, 76, 35, 174, 35, 224, 39, 158, 127, 180, 149, 86, 155, 200, 239, 118, 119, 28, 77,
+  254, 19, 176, 183, 78, 145, 132, 5, 90, 117, 152, 127, 218, 153, 20, 67, 178, 3, 128, 185,
+  254, 95, 172, 139, 246, 123, 104, 15, 42, 169, 68, 211, 98, 243, 80, 41, 174, 79, 36, 27,
+  186, 149, 86, 155, 200, 239, 118, 119, 28, 77, 254, 19, 176, 183,78, 145, 132, 5, 90, 117,
+  152, 127, 218, 153, 20, 67, 178, 3, 128, 185, 254, 95, 172, 139, 246, 123, 104, 15, 42,169,
+  68, 211, 98, 243, 80, 41, 174, 79, 36, 27, 186, 107, 56, 97, 134, 71, 116, 157, 238, 227,
+  32, 153, 162, 193, 244, 171, 150, 165, 248, 209, 54, 55, 164, 13, 194, 45, 16, 247, 242, 47,
+  60, 59, 26, 75, 40, 65, 230, 217, 44, 131, 142, 195, 192, 121, 190, 225, 108, 203, 202, 197,
+  168, 177, 150, 233, 252, 19, 34, 77, 144, 23, 110, 15, 100, 91, 122, 213, 120, 223, 70, 7, 
+  52, 93, 46, 93, 160, 167, 226, 255, 204, 21, 42, 229, 72, 111, 246, 9, 100, 205, 126, 147,
+  215, 82, 79, 36, 229, 70, 149, 56, 159, 134, 185, 140, 99, 18, 29, 224, 153, 94, 63, 244, 85, 150, 91, 248, 209,
+  202, 55, 92, 243, 194, 211, 240, 247, 242, 209, 196, 197, 26, 75, 40, 191, 26, 39, 44, 131, 142, 195, 64, 121, 190,
+  231, 34, 65, 116, 43, 22, 219, 136, 175, 74, 73, 220, 141, 190, 83, 112, 137, 142, 81, 68, 69, 154, 203, 88, 63,
+  154, 89, 172, 3, 242, 67, 192, 249, 62, 159, 20, 181, 74, 69, 216, 49, 22, 105, 132, 109, 162, 205, 16, 151, 18,
+  37, 136, 175, 74, 183, 36, 115, 66, 173, 144, 137, 142, 175, 188, 69, 102, 53, 168, 193, 102, 89, 172, 253, 242, 67,
+  192, 7, 62, 159, 20, 181, 182, 187, 216, 207, 22, 105, 132, 109, 162, 205, 16, 151, 18, 113, 228, 37, 6, 85, 8,
+  161, 58, 135, 76, 35, 174, 35, 224, 39, 158, 127, 180, 149, 86, 155, 200, 239, 118, 119, 28, 77, 254, 19, 176, 183,
+  78, 145, 132, 5, 90, 117, 152, 127, 218, 153, 20, 67, 178, 3, 128, 185, 254, 95, 172, 139, 246, 123, 104, 15, 42,
+  251, 24, 113, 170, 215, 60, 83, 30, 115, 48, 169, 210, 49, 92, 101, 58, 21, 184, 225, 6,
+  199, 244, 227, 146, 99, 96, 25, 222, 65, 140, 213, 22, 219, 136, 175, 182, 73, 36, 141, 190, 
+  83, 112, 137, 114, 175, 188, 187, 102, 53, 168, 193, 154, 167, 172, 3, 242, 67, 64,144, 137,
+  142, 175, 188, 69, 102, 53, 168, 193, 102, 89, 172, 253, 242, 67,192, 7, 62, 159, 20, 181,
+  182, 187, 216, 207, 22, 105, 132, 109, 162, 205, 16, 151, 18, 113, 228, 37, 6, 85, 8, 161,
+  58, 135, 76, 35, 174, 35, 224, 39, 158, 127, 180, 149, 86, 155, 200, 239, 118, 119, 28, 77,
+  254, 19, 176, 183, 78, 145, 132, 5, 90, 117, 152, 127, 218, 153, 20, 67, 178, 3, 128, 185,
+  254, 95, 172, 139, 246, 123, 104, 15, 42, 169, 68, 211, 98, 243, 80, 41, 174, 79, 36, 27,
+  186, 149, 86, 155, 200, 239, 118, 119, 28, 77, 254, 19, 176, 183,78, 145, 132, 5, 90, 117,
+  152, 127, 218, 153, 20, 67, 178, 3, 128, 185, 254, 95, 172, 139, 246, 123, 104, 15, 42,169,
+  68, 211, 98, 243, 80, 41, 174, 79, 36, 27, 186, 107, 56, 97, 134, 71, 116, 157, 238, 227,
+  32, 153, 162, 193, 244, 171, 150, 165, 248, 209, 54, 55, 164, 13, 194, 45, 16, 247, 242, 47,
+  60, 59, 26, 75, 40, 65, 230, 217, 44, 131, 142, 195, 192, 121, 190, 225, 108, 203, 202, 197,
+  168, 177, 150, 233, 252, 19, 34, 77, 144, 23, 110, 15, 100, 91, 122, 213, 120, 223, 70, 7, 
+  52, 93, 46, 93, 160, 167, 226, 255, 204, 21, 42, 229, 72, 111, 246, 9, 100, 205, 126, 147,
+  215, 82, 79, 36, 229, 70, 149, 56, 159, 134, 185, 140, 99, 18, 29, 224, 153, 94, 63, 244, 85, 150, 91, 248, 209,
+  202, 55, 92, 243, 194, 211, 240, 247, 242, 209, 196, 197, 26, 75, 40, 191, 26, 39, 44, 131, 142, 195, 64, 121, 190,
+  231, 34, 65, 116, 43, 22, 219, 136, 175, 74, 73, 220, 141, 190, 83, 112, 137, 142, 81, 68, 69, 154, 203, 88, 63,
+  154, 89, 172, 3, 242, 67, 192, 249, 62, 159, 20, 181, 74, 69, 216, 49, 22, 105, 132, 109, 162, 205, 16, 151, 18,
+  37, 136, 175, 74, 183, 36, 115, 66, 173, 144, 137, 142, 175, 188, 69, 102, 53, 168, 193, 102, 89, 172, 253, 242, 67,
+  192, 7, 62, 159, 20, 181, 182, 187, 216, 207, 22, 105, 132, 109, 162, 205, 16, 151, 18, 113, 228, 37, 6, 85, 8,
+  161, 58, 135, 76, 35, 174, 35, 224, 39, 158, 127, 180, 149, 86, 155, 200, 239, 118, 119, 28, 77, 254, 19, 176, 183,
+  78, 145, 132, 5, 90, 117, 152, 127, 218, 153, 20, 67, 178, 3, 128, 185, 254, 95, 172, 139, 246, 123, 104, 15, 42,
+
+  251, 24, 113, 170, 215, 60, 83, 30, 115, 48, 169, 210, 49, 92, 101, 58, 21, 184, 225, 6,
+  199, 244, 227, 146, 99, 96, 25, 222, 65, 140, 213, 22, 219, 136, 175, 182, 73, 36, 141, 190, 
+  83, 112, 137, 114, 175, 188, 187, 102, 53, 168, 193, 154, 167, 172, 3, 242, 67, 64,144, 137,
+  142, 175, 188, 69, 102, 53, 168, 193, 102, 89, 172, 253, 242, 67,192, 7, 62, 159, 20, 181,
+  182, 187, 216, 207, 22, 105, 132, 109, 162, 205, 16, 151, 18, 113, 228, 37, 6, 85, 8, 161,
+  58, 135, 76, 35, 174, 35, 224, 39, 158, 127, 180, 149, 86, 155, 200, 239, 118, 119, 28, 77,
+  254, 19, 176, 183, 78, 145, 132, 5, 90, 117, 152, 127, 218, 153, 20, 67, 178, 3, 128, 185,
+  254, 95, 172, 139, 246, 123, 104, 15, 42, 169, 68, 211, 98, 243, 80, 41, 174, 79, 36, 27,
+  186, 149, 86, 155, 200, 239, 118, 119, 28, 77, 254, 19, 176, 183,78, 145, 132, 5, 90, 117,
+  152, 127, 218, 153, 20, 67, 178, 3, 128, 185, 254, 95, 172, 139, 246, 123, 104, 15, 42,169,
+  68, 211, 98, 243, 80, 41, 174, 79, 36, 27, 186, 107, 56, 97, 134, 71, 116, 157, 238, 227,
+  32, 153, 162, 193, 244, 171, 150, 165, 248, 209, 54, 55, 164, 13, 194, 45, 16, 247, 242, 47,
+  60, 59, 26, 75, 40, 65, 230, 217, 44, 131, 142, 195, 192, 121, 190, 225, 108, 203, 202, 197,
+  168, 177, 150, 233, 252, 19, 34, 77, 144, 23, 110, 15, 100, 91, 122, 213, 120, 223, 70, 7, 
+  52, 93, 46, 93, 160, 167, 226, 255, 204, 21, 42, 229, 72, 111, 246, 9, 100, 205, 126, 147,
+  215, 82, 79, 36, 229, 70, 149, 56, 159, 134, 185, 140, 99, 18, 29, 224, 153, 94, 63, 244, 85, 150, 91, 248, 209,
+  202, 55, 92, 243, 194, 211, 240, 247, 242, 209, 196, 197, 26, 75, 40, 191, 26, 39, 44, 131, 142, 195, 64, 121, 190,
+  231, 34, 65, 116, 43, 22, 219, 136, 175, 74, 73, 220, 141, 190, 83, 112, 137, 142, 81, 68, 69, 154, 203, 88, 63,
+  154, 89, 172, 3, 242, 67, 192, 249, 62, 159, 20, 181, 74, 69, 216, 49, 22, 105, 132, 109, 162, 205, 16, 151, 18,
+  37, 136, 175, 74, 183, 36, 115, 66, 173, 144, 137, 142, 175, 188, 69, 102, 53, 168, 193, 102, 89, 172, 253, 242, 67,
+  192, 7, 62, 159, 20, 181, 182, 187, 216, 207, 22, 105, 132, 109, 162, 205, 16, 151, 18, 113, 228, 37, 6, 85, 8,
+  161, 58, 135, 76, 35, 174, 35, 224, 39, 158, 127, 180, 149, 86, 155, 200, 239, 118, 119, 28, 77, 254, 19, 176, 183,
+  78, 145, 132, 5, 90, 117, 152, 127, 218, 153, 20, 67, 178, 3, 128, 185, 254, 95, 172, 139, 246, 123, 104, 15, 42,
+  251, 24, 113, 170, 215, 60, 83, 30, 115, 48, 169, 210, 49, 92, 101, 58, 21, 184, 225, 6,
+  199, 244, 227, 146, 99, 96, 25, 222, 65, 140, 213, 22, 219, 136, 175, 182, 73, 36, 141, 190, 
+  83, 112, 137, 114, 175, 188, 187, 102, 53, 168, 193, 154, 167, 172, 3, 242, 67, 64,144, 137,
+  142, 175, 188, 69, 102, 53, 168, 193, 102, 89, 172, 253, 242, 67,192, 7, 62, 159, 20, 181,
+  182, 187, 216, 207, 22, 105, 132, 109, 162, 205, 16, 151, 18, 113, 228, 37, 6, 85, 8, 161,
+  58, 135, 76, 35, 174, 35, 224, 39, 158, 127, 180, 149, 86, 155, 200, 239, 118, 119, 28, 77,
+  254, 19, 176, 183, 78, 145, 132, 5, 90, 117, 152, 127, 218, 153, 20, 67, 178, 3, 128, 185,
+  254, 95, 172, 139, 246, 123, 104, 15, 42, 169, 68, 211, 98, 243, 80, 41, 174, 79, 36, 27,
+  186, 149, 86, 155, 200, 239, 118, 119, 28, 77, 254, 19, 176, 183,78, 145, 132, 5, 90, 117,
+  152, 127, 218, 153, 20, 67, 178, 3, 128, 185, 254, 95, 172, 139, 246, 123, 104, 15, 42,169,
+  68, 211, 98, 243, 80, 41, 174, 79, 36, 27, 186, 107, 56, 97, 134, 71, 116, 157, 238, 227,
+  32, 153, 162, 193, 244, 171, 150, 165, 248, 209, 54, 55, 164, 13, 194, 45, 16, 247, 242, 47,
+  60, 59, 26, 75, 40, 65, 230, 217, 44, 131, 142, 195, 192, 121, 190, 225, 108, 203, 202, 197,
+  168, 177, 150, 233, 252, 19, 34, 77, 144, 23, 110, 15, 100, 91, 122, 213, 120, 223, 70, 7, 
+  52, 93, 46, 93, 160, 167, 226, 255, 204, 21, 42, 229, 72, 111, 246, 9, 100, 205, 126, 147,
+  215, 82, 79, 36, 229, 70, 149, 56, 159, 134, 185, 140, 99, 18, 29, 224, 153, 94, 63, 244, 85, 150, 91, 248, 209,
+  202, 55, 92, 243, 194, 211, 240, 247, 242, 209, 196, 197, 26, 75, 40, 191, 26, 39, 44, 131, 142, 195, 64, 121, 190,
+  231, 34, 65, 116, 43, 22, 219, 136, 175, 74, 73, 220, 141, 190, 83, 112, 137, 142, 81, 68, 69, 154, 203, 88, 63,
+  154, 89, 172, 3, 242, 67, 192, 249, 62, 159, 20, 181, 74, 69, 216, 49, 22, 105, 132, 109, 162, 205, 16, 151, 18,
+  37, 136, 175, 74, 183, 36, 115, 66, 173, 144, 137, 142, 175, 188, 69, 102, 53, 168, 193, 102, 89, 172, 253, 242, 67,
+  192, 7, 62, 159, 20, 181, 182, 187, 216, 207, 22, 105, 132, 109, 162, 205, 16, 151, 18, 113, 228, 37, 6, 85, 8,
+  161, 58, 135, 76, 35, 174, 35, 224, 39, 158, 127, 180, 149, 86, 155, 200, 239, 118, 119, 28, 77, 254, 19, 176, 183,
+  78, 145, 132, 5, 90, 117, 152, 127, 218, 153, 20, 67, 178, 3, 128, 185, 254, 95, 172, 139, 246, 123, 104, 15, 42,
+
+  251, 24, 113, 170, 215, 60, 83, 30, 115, 48, 169, 210, 49, 92, 101, 58, 21, 184, 225, 6,
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+  78, 3, 128, 185, 2, 95, 172, 139, 10, 123, 104, 241, 214, 169, 188, 211, 98, 13, 80, 41, 82, 177, 220, 229, 186,
+  149, 200, 159, 134, 71, 116, 99, 18, 29, 224, 103, 162, 193, 12, 171, 150, 165, 248, 209, 202, 201, 92, 13, 62, 211,
+  16, 247, 14, 209, 60, 59, 26, 181, 40, 191, 230, 39, 44, 125, 114, 195, 64, 135, 190, 225, 148, 53, 202, 197, 168,
+  79, 106, 23, 4, 19, 34, 77, 144, 23, 146, 241, 156, 91, 122, 43, 136, 223, 70, 249, 52, 163, 46, 93, 96, 89,
+  30, 255, 52, 21, 214, 229, 72, 111, 10, 9, 156, 205, 126, 147, 48, 55, 50, 239, 252, 133, 38, 11, 232, 1, 166,
+  25, 108, 61, 206, 125, 0, 199, 126, 223, 44, 11, 118, 251, 24, 113, 170, 215, 60, 83, 30, 115, 48, 169, 210, 49,
+  92, 101, 58, 21, 184, 225, 6, 199, 244, 227, 146, 99, 96, 25, 222, 65, 140, 213, 22, 219, 136, 175, 182, 73, 36,
+  141, 190, 83, 112, 137, 114, 175, 188, 187, 102, 53, 168, 193, 154, 167, 172, 3, 242, 67, 64, 7, 62, 159, 236, 75,
+  182, 187, 40, 49, 234, 105, 124, 109, 162, 205, 16, 105, 238, 143, 28, 37, 6, 85, 248, 161, 58, 121, 180, 221, 174,
+  221, 32, 217, 98, 129, 76, 149, 170, 101, 200, 239, 118, 137, 28, 179, 254, 19, 80, 183, 178, 145, 124, 251, 166, 139,
+  152, 129, 38, 153, 20, 189, 78, 3, 128, 71, 254, 95, 84, 139, 10, 123, 152, 241, 214, 169, 68, 211, 98, 13, 80,
+  215, 82, 79, 36, 229, 70, 149, 56, 159, 134, 185, 140, 99, 18, 29, 224, 153, 94, 63, 244, 85, 150, 91, 248, 209,
+  202, 55, 92, 243, 194, 211, 240, 247, 242, 209, 196, 197, 26, 75, 40, 191, 26, 39, 44, 131, 142, 195, 64, 121, 190,
+  225, 148, 53, 54, 197, 88, 79, 106, 233, 252, 19, 34, 77, 144, 233, 146, 241, 100, 91, 134, 43, 136, 33, 70, 249,
+  204, 163, 210, 163, 96, 89, 226, 1, 52, 235, 214, 27, 72, 111, 246, 247, 156, 51, 130, 109, 208, 55, 50, 17, 252,
+  123, 218, 245, 232, 255, 90, 231, 108, 195, 50, 125, 0, 199, 130, 223, 212, 11, 138, 251, 232, 143, 86, 215, 196, 83,
+  30, 141, 48, 87, 46, 207, 92, 155, 58, 235, 184, 31, 6, 199, 12, 29, 146, 157, 160, 231, 34, 191, 116, 213, 22,
+  37, 136, 175, 74, 183, 36, 115, 66, 173, 144, 137, 142, 175, 188, 69, 102, 53, 168, 193, 102, 89, 172, 253, 242, 67,
+  192, 7, 62, 159, 20, 181, 182, 187, 216, 207, 22, 105, 132, 109, 162, 205, 16, 151, 18, 113, 228, 37, 6, 85, 8,
+  161, 58, 135, 76, 35, 174, 35, 224, 39, 158, 127, 180, 149, 86, 155, 200, 239, 118, 119, 28, 77, 254, 19, 176, 183,
+  78, 145, 132, 5, 90, 117, 152, 127, 218, 153, 20, 67, 178, 3, 128, 185, 254, 95, 172, 139, 246, 123, 104, 15, 42,
+  169, 68, 211, 98, 243, 80, 41, 174, 79, 36, 27, 186, 107, 56, 97, 134, 71, 116, 157, 238, 227, 32, 153, 162, 193,
+  244, 171, 150, 165, 248, 209, 54, 55, 164, 13, 194, 45, 16, 247, 242, 47, 60, 59, 26, 75, 40, 65, 230, 217, 44,
+  131, 142, 195, 192, 121, 190, 225, 108, 203, 202, 197, 168, 177, 150, 233, 252, 19, 34, 77, 144, 23, 110, 15, 100, 91,
+  122, 213, 120, 223, 70, 7, 52, 93, 46, 93, 160, 167, 226, 255, 204, 21, 42, 229, 72, 111, 246, 9, 100, 205, 126,
+  147, 48, 55, 206, 239, 4, 133, 218, 245, 232, 255, 166, 231, 108, 195, 50, 131, 0, 57, 130, 223, 44, 245, 118, 251,
+  232, 113, 86, 215, 196, 83, 30, 141, 48, 87, 46, 207, 92, 155, 198, 235, 72, 31, 250, 57, 244, 29, 110, 99, 160,
+  231, 34, 65, 116, 43, 22, 219, 136, 175, 74, 73, 220, 141, 190, 83, 112, 137, 142, 81, 68, 69, 154, 203, 88, 63,
+  154, 89, 172, 3, 242, 67, 192, 249, 62, 159, 20, 181, 74, 69, 216, 49, 22, 105, 132, 109, 162, 205, 16, 151, 18,
+  113, 228, 219, 
+250, 171, 8, 95, 58, 135, 180, 35, 82, 221, 224, 39, 98, 129, 180, 107, 86, 101, 200, 239, 118, 119,
+  228, 179, 2, 237, 80, 183, 78, 111, 124, 5, 90, 117, 104, 127, 38, 153, 20, 67, 178, 253, 128, 185, 254, 95, 172,
+  117, 10, 123, 152, 241, 42, 87, 188, 211, 98, 243, 80, 215, 82, 79, 36, 27, 186, 107, 200, 159, 122, 71, 140, 157,
+  238, 29, 224, 153, 94, 63, 244, 85, 106, 91, 248, 47, 54, 201, 164, 243, 62, 211, 240, 247, 242, 47, 196, 197, 230,
+  181, 216, 65, 26, 217, 44, 125, 114, 195, 192, 135, 190, 31, 148, 203, 202, 59, 88, 79, 150, 233, 252, 19, 34, 77,
+  144, 233, 146, 15, 100, 165, 122, 213, 136, 223, 70, 249, 204, 93, 46, 93, 96, 167, 30, 1, 204, 21, 42, 27, 72,
+
+  57, 126, 223, 44, 11, 138, 251, 232, 143, 86, 215, 60, 83, 30, 115, 48, 87, 46, 49, 164, 101, 198, 235, 72, 31,
+  6, 57, 12, 227, 110, 157, 96, 25, 34, 191, 140, 43, 22, 37, 136, 175, 182, 183, 220, 115, 66, 173, 144, 137, 114,
+  81, 68, 69, 102, 203, 168, 193, 102, 167, 172, 3, 14, 67, 64, 249, 62, 159, 20, 75, 74, 187, 216, 207, 22, 151,
+  124, 109, 162, 51, 16, 151, 18, 143, 28, 37, 250, 171, 8, 95, 58, 135, 76, 221, 82, 221, 224, 217, 158, 127, 76,
+  107, 170, 155, 200, 239, 138, 119, 228, 77, 2, 237, 176, 183, 178, 111, 132, 5, 166, 139, 104, 129, 218, 103, 20, 189,
+  78, 3, 128, 185, 2, 95, 172, 139, 10, 123, 104, 241, 214, 169, 188, 211, 98, 13, 80, 41, 82, 177, 220, 229, 186,
+  149, 200, 159, 134, 71, 116, 99, 18, 29, 224, 103, 162, 193, 12, 171, 150, 165, 248, 209, 202, 201, 92, 13, 62, 211,
+  16, 247, 14, 209, 60, 59, 26, 181, 40, 191, 230, 39, 44, 125, 114, 195, 64, 135, 190, 225, 148, 53, 202, 197, 168,
+  79, 106, 23, 4, 19, 34, 77, 144, 23, 146, 241, 156, 91, 122, 43, 136, 223, 70, 249, 52, 163, 46, 93, 96, 89,
+  30, 255, 52, 21, 214, 229, 72, 111, 10, 9, 156, 205, 126, 147, 48, 55, 50, 239, 252, 133, 38, 11, 232, 1, 166,
+  25, 108, 61, 206, 125, 0, 199, 126, 223, 44, 11, 118, 251, 24, 113, 170, 215, 60, 83, 30, 115, 48, 169, 210, 49,
+  92, 101, 58, 21, 184, 225, 6, 199, 244, 227, 146, 99, 96, 25, 222, 65, 140, 213, 22, 219, 136, 175, 182, 73, 36,
+  141, 190, 83, 112, 137, 114, 175, 188, 187, 102, 53, 168, 193, 154, 167, 172, 3, 242, 67, 64, 7, 62, 159, 236, 75,
+  182, 187, 40, 49, 234, 105, 124, 109, 162, 205, 16, 105, 238, 143, 28, 37, 6, 85, 248, 161, 58, 121, 180, 221, 174,
+  221, 32, 217, 98, 129, 76, 149, 170, 101, 200, 239, 118, 137, 28, 179, 254, 19, 80, 183, 178, 145, 124, 251, 166, 139,
+  152, 129, 38, 153, 20, 189, 78, 3, 128, 71, 254, 95, 84, 139, 10, 123, 152, 241, 214, 169, 68, 211, 98, 13, 80,
+  215, 82, 79, 36, 229, 70, 149, 56, 159, 134, 185, 140, 99, 18, 29, 224, 153, 94, 63, 244, 85, 150, 91, 248, 209,
+  202, 55, 92, 243, 194, 211, 240, 247, 242, 209, 196, 197, 26, 75, 40, 191, 26, 39, 44, 131, 142, 195, 64, 121, 190,
+  225, 148, 53, 54, 197, 88, 79, 106, 233, 252, 19, 34, 77, 144, 233, 146, 241, 100, 91, 134, 43, 136, 33, 70, 249,
+  204, 163, 210, 163, 96, 89, 226, 1, 52, 235, 214, 27, 72, 111, 246, 247, 156, 51, 130, 109, 208, 55, 50, 17, 252,
+  123, 218, 245, 232, 255, 90, 231, 108, 195, 50, 125, 0, 199, 130, 223, 212, 11, 138, 251, 232, 143, 86, 215, 196, 83,
+  30, 141, 48, 87, 46, 207, 92, 155, 58, 235, 184, 31, 6, 199, 12, 29, 146, 157, 160, 231, 34, 191, 116, 213, 22,
+  37, 136, 175, 74, 183, 36, 115, 66, 173, 144, 137, 142, 175, 188, 69, 102, 53, 168, 193, 102, 89, 172, 253, 242, 67,
+  192, 7, 62, 159, 20, 181, 182, 187, 216, 207, 22, 105, 132, 109, 162, 205, 16, 151, 18, 113, 228, 37, 6, 85, 8,
+  161, 58, 135, 76, 35, 174, 35, 224, 39, 158, 127, 180, 149, 86, 155, 200, 239, 118, 119, 28, 77, 254, 19, 176, 183,
+  78, 145, 132, 5, 90, 117, 152, 127, 218, 153, 20, 67, 178, 3, 128, 185, 254, 95, 172, 139, 246, 123, 104, 15, 42,
+  169, 68, 211, 98, 243, 80, 41, 174, 79, 36, 27, 186, 107, 56, 97, 134, 71, 116, 157, 238, 227, 32, 153, 162, 193,
+  244, 171, 150, 165, 248, 209, 54, 55, 164, 13, 194, 45, 16, 247, 242, 47, 60, 59, 26, 75, 40, 65, 230, 217, 44,
+  131, 142, 195, 192, 121, 190, 225, 108, 203, 202, 197, 168, 177, 150, 233, 252, 19, 34, 77, 144, 23, 110, 15, 100, 91,
+  122, 213, 120, 223, 70, 7, 52, 93, 46, 93, 160, 167, 226, 255, 204, 21, 42, 229, 72, 111, 246, 9, 100, 205, 126,
+  147, 48, 55, 206, 239, 4, 133, 218, 245, 232, 255, 166, 231, 108, 195, 50, 131, 0, 57, 130, 223, 44, 245, 118, 251,
+  232, 113, 86, 215, 196, 83, 30, 141, 48, 87, 46, 207, 92, 155, 198, 235, 72, 31, 250, 57, 244, 29, 110, 99, 160,
+  231, 34, 65, 116, 43, 22, 219, 136, 175, 74, 73, 220, 141, 190, 83, 112, 137, 142, 81, 68, 69, 154, 203, 88, 63,
+  154, 89, 172, 3, 242, 67, 192, 249, 62, 159, 20, 181, 74, 69, 216, 49, 22, 105, 132, 109, 162, 205, 16, 151, 18,
+  113, 228, 219, 
+250, 171, 8, 95, 58, 135, 180, 35, 82, 221, 224, 39, 98, 129, 180, 107, 86, 101, 200, 239, 118, 119,
+  228, 179, 2, 237, 80, 183, 78, 111, 124, 5, 90, 117, 104, 127, 38, 153, 20, 67, 178, 253, 128, 185, 254, 95, 172,
+  117, 10, 123, 152, 241, 42, 87, 188, 211, 98, 243, 80, 215, 82, 79, 36, 27, 186, 107, 200, 159, 122, 71, 140, 157,
+  238, 29, 224, 153, 94, 63, 244, 85, 106, 91, 248, 47, 54, 201, 164, 243, 62, 211, 240, 247, 242, 47, 196, 197, 230,
+  181, 216, 65, 26, 217, 44, 125, 114, 195, 192, 135, 190, 31, 148, 203, 202, 59, 88, 79, 150, 233, 252, 19, 34, 77,
+  144, 233, 146, 15, 100, 165, 122, 213, 136, 223, 70, 249, 204, 93, 46, 93, 96, 167, 30, 1, 204, 21, 42, 27, 72,
+
+  57, 126, 223, 44, 11, 138, 251, 232, 143, 86, 215, 60, 83, 30, 115, 48, 87, 46, 49, 164, 101, 198, 235, 72, 31,
+  6, 57, 12, 227, 110, 157, 96, 25, 34, 191, 140, 43, 22, 37, 136, 175, 182, 183, 220, 115, 66, 173, 144, 137, 114,
+  81, 68, 69, 102, 203, 168, 193, 102, 167, 172, 3, 14, 67, 64, 249, 62, 159, 20, 75, 74, 187, 216, 207, 22, 151,
+  124, 109, 162, 51, 16, 151, 18, 143, 28, 37, 250, 171, 8, 95, 58, 135, 76, 221, 82, 221, 224, 217, 158, 127, 76,
+  107, 170, 155, 200, 239, 138, 119, 228, 77, 2, 237, 176, 183, 178, 111, 132, 5, 166, 139, 104, 129, 218, 103, 20, 189,
+  78, 3, 128, 185, 2, 95, 172, 139, 10, 123, 104, 241, 214, 169, 188, 211, 98, 13, 80, 41, 82, 177, 220, 229, 186,
+  149, 200, 159, 134, 71, 116, 99, 18, 29, 224, 103, 162, 193, 12, 171, 150, 165, 248, 209, 202, 201, 92, 13, 62, 211,
+  16, 247, 14, 209, 60, 59, 26, 181, 40, 191, 230, 39, 44, 125, 114, 195, 64, 135, 190, 225, 148, 53, 202, 197, 168,
+  79, 106, 23, 4, 19, 34, 77, 144, 23, 146, 241, 156, 91, 122, 43, 136, 223, 70, 249, 52, 163, 46, 93, 96, 89,
+  30, 255, 52, 21, 214, 229, 72, 111, 10, 9, 156, 205, 126, 147, 48, 55, 50, 239, 252, 133, 38, 11, 232, 1, 166,
+  25, 108, 61, 206, 125, 0, 199, 126, 223, 44, 11, 118, 251, 24, 113, 170, 215, 60, 83, 30, 115, 48, 169, 210, 49,
+  92, 101, 58, 21, 184, 225, 6, 199, 244, 227, 146, 99, 96, 25, 222, 65, 140, 213, 22, 219, 136, 175, 182, 73, 36,
+  141, 190, 83, 112, 137, 114, 175, 188, 187, 102, 53, 168, 193, 154, 167, 172, 3, 242, 67, 64, 7, 62, 159, 236, 75,
+  182, 187, 40, 49, 234, 105, 124, 109, 162, 205, 16, 105, 238, 143, 28, 37, 6, 85, 248, 161, 58, 121, 180, 221, 174,
+  221, 32, 217, 98, 129, 76, 149, 170, 101, 200, 239, 118, 137, 28, 179, 254, 19, 80, 183, 178, 145, 124, 251, 166, 139,
+  152, 129, 38, 153, 20, 189, 78, 3, 128, 71, 254, 95, 84, 139, 10, 123, 152, 241, 214, 169, 68, 211, 98, 13, 80,
+  215, 82, 79, 36, 229, 70, 149, 56, 159, 134, 185, 140, 99, 18, 29, 224, 153, 94, 63, 244, 85, 150, 91, 248, 209,
+  202, 55, 92, 243, 194, 211, 240, 247, 242, 209, 196, 197, 26, 75, 40, 191, 26, 39, 44, 131, 142, 195, 64, 121, 190,
+  225, 148, 53, 54, 197, 88, 79, 106, 233, 252, 19, 34, 77, 144, 233, 146, 241, 100, 91, 134, 43, 136, 33, 70, 249,
+  204, 163, 210, 163, 96, 89, 226, 1, 52, 235, 214, 27, 72, 111, 246, 247, 156, 51, 130, 109, 208, 55, 50, 17, 252,
+  123, 218, 245, 232, 255, 90, 231, 108, 195, 50, 125, 0, 199, 130, 223, 212, 11, 138, 251, 232, 143, 86, 215, 196, 83,
+  30, 141, 48, 87, 46, 207, 92, 155, 58, 235, 184, 31, 6, 199, 12, 29, 146, 157, 160, 231, 34, 191, 116, 213, 22,
+  37, 136, 175, 74, 183, 36, 115, 66, 173, 144, 137, 142, 175, 188, 69, 102, 53, 168, 193, 102, 89, 172, 253, 242, 67,
+  192, 7, 62, 159, 20, 181, 182, 187, 216, 207, 22, 105, 132, 109, 162, 205, 16, 151, 18, 113, 228, 37, 6, 85, 8,
+  161, 58, 135, 76, 35, 174, 35, 224, 39, 158, 127, 180, 149, 86, 155, 200, 239, 118, 119, 28, 77, 254, 19, 176, 183,
+  78, 145, 132, 5, 90, 117, 152, 127, 218, 153, 20, 67, 178, 3, 128, 185, 254, 95, 172, 139, 246, 123, 104, 15, 42,
+  169, 68, 211, 98, 243, 80, 41, 174, 79, 36, 27, 186, 107, 56, 97, 134, 71, 116, 157, 238, 227, 32, 153, 162, 193,
+  244, 171, 150, 165, 248, 209, 54, 55, 164, 13, 194, 45, 16, 247, 242, 47, 60, 59, 26, 75, 40, 65, 230, 217, 44,
+  131, 142, 195, 192, 121, 190, 225, 108, 203, 202, 197, 168, 177, 150, 233, 252, 19, 34, 77, 144, 23, 110, 15, 100, 91,
+  122, 213, 120, 223, 70, 7, 52, 93, 46, 93, 160, 167, 226, 255, 204, 21, 42, 229, 72, 111, 246, 9, 100, 205, 126,
+  147, 48, 55, 206, 239, 4, 133, 218, 245, 232, 255, 166, 231, 108, 195, 50, 131, 0, 57, 130, 223, 44, 245, 118, 251,
+  232, 113, 86, 215, 196, 83, 30, 141, 48, 87, 46, 207, 92, 155, 198, 235, 72, 31, 250, 57, 244, 29, 110, 99, 160,
+  231, 34, 65, 116, 43, 22, 219, 136, 175, 74, 73, 220, 141, 190, 83, 112, 137, 142, 81, 68, 69, 154, 203, 88, 63,
+  154, 89, 172, 3, 242, 67, 192, 249, 62, 159, 20, 181, 74, 69, 216, 49, 22, 105, 132, 109, 162, 205, 16, 151, 18,
+  113, 228, 219, 
+250, 171, 8, 95, 58, 135, 180, 35, 82, 221, 224, 39, 98, 129, 180, 107, 86, 101, 200, 239, 118, 119,
+  228, 179, 2, 237, 80, 183, 78, 111, 124, 5, 90, 117, 104, 127, 38, 153, 20, 67, 178, 253, 128, 185, 254, 95, 172,
+  117, 10, 123, 152, 241, 42, 87, 188, 211, 98, 243, 80, 215, 82, 79, 36, 27, 186, 107, 200, 159, 122, 71, 140, 157,
+  238, 29, 224, 153, 94, 63, 244, 85, 106, 91, 248, 47, 54, 201, 164, 243, 62, 211, 240, 247, 242, 47, 196, 197, 230,
+  181, 216, 65, 26, 217, 44, 125, 114, 195, 192, 135, 190, 31, 148, 203, 202, 59, 88, 79, 150, 233, 252, 19, 34, 77,
+  144, 233, 146, 15, 100, 165, 122, 213, 136, 223, 70, 249, 204, 93, 46, 93, 96, 167, 30, 1, 204, 21, 42, 27, 72
+};
+
+
+
+  unsigned int SortArr0[16*(SIZE+200)];
+
+void SORT(int *base, int n, int size, int (*compar) (),int type);
+void QSORT(int *base, int n, int size, int (*compar) ());
+void simple_sort(int *base, int n, int size, int (*compar) ());
+void insertion_sort(int *base, int n, int size, int (*compar) ());
+void bubble_sort(int *base, int n, int size, int (*compar) ());
+int compare(int *n1, int *n2)
+{
+  return (*((unsigned int *) n1) - *((unsigned int *) n2));
+}
+
+int main()
+{
+  register int p; 
+
+  p=procnum();
+
+  puts("Hello from processor ");
+  putchar(p+'0');
+  putchar('\n');
+
+
+  int i;
+  int j;
+  int temp;
+
+  if(p+1 <= nprocs){
+	for(i=1 ; i <= 8 ; i++ ){
+  	puts("Memory copy \n");
+	memcpy(SortArr0+p*(SIZE+200), gQSortNum0 + ( (4*(p+1)*i) % 32) ,SIZE);
+
+/*
+  	uputs("Cache erase ... \n");
+
+  	for(j = 0; j < SIZE+200; j++){
+		temp=gQSortNum0[j];
+  	}
+*/
+ 
+	
+  	puts("Sort... \n");
+  	SORT((int *) (SortArr0+p*(SIZE+200)), (int) SIZE, sizeof(unsigned int), compare,SORT_TYPE);
+  	for (j = 1; j < SIZE; j++)
+    	{
+      		if (SortArr0[p*(SIZE+200)+j] < SortArr0[p*(SIZE+200) + j - 1])
+		{
+	  		puts("ucbqsort: failed\n");
+			while(1);
+		}
+
+    	}
+  	puts("ucbqsort: success\n");
+	}
+  }
+  
+
+  if(p+1 <= nprocs){
+	lock_lock(&lock);
+	compteur--;
+	if(!compteur){
+  		putchar('\n');
+  		puti(temp);
+  		putchar('\n');
+	}
+	lock_unlock(&lock);
+  }
+
+  while(1);
+}
+
+static int (*qcmp) ();
+static int qsz;
+static int thresh;
+static int mthresh;
+static void qst(int *, int *);
+void QSORT(base, n, size, compar)
+     int *base;
+     int n;
+     int size;
+     int (*compar) ();
+{
+  register int c, *i, *j, *lo, *hi;
+  int *min, *max;
+  if (n <= 1)
+    return;
+  qsz = size;
+  qcmp = compar;
+  thresh = 4;
+  mthresh = 6;
+  max = base + n;
+  if (n >= 4)
+    {
+      qst(base, max);
+      hi = base + thresh;
+    } 
+  else
+    {
+      hi = max;
+    }
+
+  puts("Quick sort done... \n");
+
+  for (j = lo = base; (lo ++) < hi;)
+    if ((*qcmp) (j, lo) > 0)
+      j = lo;
+  if (j != base)
+    {
+      for (i = base, hi = base + 1; i < hi;)
+	{
+	  c = *j;
+	  *j++ = *i;
+	  *i++ = c;
+	}
+
+    }
+  for (min = base; (hi = min ++) < max;)
+    {
+      while ((*qcmp) (hi --, min) > 0)
+	;
+      if ((hi ++) != min)
+	{
+	  for (lo = min + 1; --lo >= min;)
+	    {
+	      c = *lo;
+	      for (i = j = lo; (j --) >= hi; i = j)
+		*i = *j;
+	      *i = c;
+	    }
+
+	}
+    }
+
+}
+
+
+void simple_sort(base, n, size, compar)
+     int *base;
+     int n;
+     int size;
+     int (*compar) ();
+{
+  register int c, *i, *j, *lo, p, *k;
+  int *max;
+  k=write_boost;
+  if (n <= 1)
+    return;
+  qsz = size;
+  qcmp = compar;
+  max = base + n;
+  puts("Selection Sort\n");
+  p=procnum();
+//  k=4;
+  for(j = base; j < max ; j++){
+    lo=j;
+    c=(*lo);
+    for(i = j; i < max ; i++){
+      *(k+(p * 70)+20)=p; // 1
+
+	asm("	nop		\n"); //1
+	//asm("	nop		\n");
+
+
+      if( c-(*i) > 0){
+//	if( (*qcmp) (lo,i) > 0){
+ 	lo=i;
+        c=(*lo);
+/*	write_boost[p][((int)i) & mask1]=(*(lo+3));
+	write_boost[p][((int)i) & mask2]=(*(lo+4));
+	write_boost[p][((int)j) & mask1]=(*(lo+2));
+	write_boost[p][((int)j) & mask2]=(*(lo+1));
+	write_boost[p][((int)i) & mask3]=(*(lo));
+*/
+      }
+
+/*
+      if(!k){
+	write_boost[p][((int)i) & 0x00000010]=(int)max;
+	k=4;
+      }
+      else{
+	if((k%2)){
+	  write_boost[p][((int)i) & 0x00000010]=(int)max;
+	}
+	else{
+	  write_boost[p][((int)j) & 0x00000111]=(int)i;
+	}
+	k--;
+//	write_boost[p][((int)i) & 0x00000001]=(int)i;
+      }
+*/
+      asm("	nop		\n"); // 1
+	//asm("	nop		\n");
+    }
+    *lo = *j;
+    *j = c;
+  }
+}
+
+void insertion_sort(base, n, size, compar)
+     int *base;
+     int n;
+     int size;
+     int (*compar) ();
+{
+  register int c, *i, *j,p;
+  int *max;
+  if (n <= 1)
+    return;
+  qsz = size;
+  qcmp = compar;
+  max = base + n;
+  puts("Insertion Sort\n");
+  p=procnum();
+  for(j = base; j < max-1 ; j++){
+    for(i = j; i < max-1 ; i++){
+      if( (*i)-(*(i+1)) > 0){
+//	if( (*qcmp) (i,i+1) > 0){
+ 	c = *i;
+	*i = *(i+1);
+	*(i+1)=c;
+      }
+    }
+  }
+}
+
+
+void bubble_sort(base, n, size, compar)
+     int *base;
+     int n;
+     int size;
+     int (*compar) ();
+{
+  register int c, *i;
+  register int b_swap=1;
+  int *max;
+  if (n <= 1)
+    return;
+  qsz = size;
+  qcmp = compar;
+  max = base + n;
+  puts("Bubble Sort\n");
+  while(b_swap){
+    b_swap=0;
+    for(i = base; i < max-1 ; i++){
+      if( (*i)-(*(i+1)) > 0){
+//	if( (*qcmp) (i,i+1) > 0){
+	b_swap=1;
+ 	c = *i;
+	*i = *(i+1);
+	*(i+1)=c;
+      }
+    }
+  }
+}
+
+static
+void qst(base, max)
+     int *base, *max;
+{
+  register int c, *i, *j, *jj;
+  register int ii;
+  int *mid, *tmp;
+  int lo, hi;
+  lo = max - base;
+  do
+    {
+      mid = i = base + 1 * ((lo / qsz) >> 1);
+      if (lo >= mthresh)
+	{
+	  j = ((*qcmp) ((jj = base), i) > 0 ? jj : i);
+	  if ((*qcmp) (j, (tmp = max - 1)) > 0)
+	    {
+	      j = (j == jj ? i : jj);
+	      if ((*qcmp) (j, tmp) < 0)
+		j = tmp;
+	    }
+
+	  if (j != i)
+	    {
+	      ii = 1;
+	      do
+		{
+		  c = *i;
+		  *i++ = *j;
+		  *j++ = c;
+		}
+
+	      while (--ii);
+	    }
+
+	}
+      for (i = base, j = max - 1;;)
+	{
+	  while (i < mid && (*qcmp) (i, mid) <= 0)
+            i ++;
+	  while (j > mid)
+	    {
+	      if ((*qcmp) (mid, j) <= 0)
+		{
+		  j --;
+		  continue;
+		}
+
+	      tmp = i + 1;
+	      if (i == mid)
+		{
+		  mid = jj = j;
+		} 
+	      else
+		{
+		  jj = j;
+		  j --;
+		}
+
+	      goto swap;
+	    }
+
+	  if (i == mid)
+	    {
+	      break;
+	    } 
+	  else
+	    {
+	      jj = mid;
+	      tmp = mid = i;
+	      j --;
+	    }
+
+	swap:
+	  ii = 1;
+	  do
+	    {
+	      c = *i;
+	      *i++ = *jj;
+	      *jj++ = c;
+	    }
+
+	  while (--ii);
+	  i = tmp;
+	}
+
+      i = (j = mid) + 1;
+      if ((lo = j - base) <= (hi = max - i))
+	{
+	  if (lo >= thresh)
+            qst(base, j);
+	  base = i;
+	  lo = hi;
+	} 
+      else
+	{
+	  if (hi >= thresh)
+            qst(i, max);
+	  max = j;
+	}
+
+    }
+  while (lo >= thresh);
+}
+
+void SORT(int *base, int n, int size, int (*compar) (),int type){
+  switch(type){
+  case 0:
+    QSORT(base, n, size, compar);
+    break;
+  case 1:
+    simple_sort(base, n, size, compar);
+    break;
+  case 2:
+    insertion_sort(base, n, size, compar);
+    break;
+  case 3:
+    bubble_sort(base, n, size, compar);
+    break;
+  default:
+    break;
+  }
+
+}
+
+
Index: branches/v4/platforms/caba-tsar-v0/top.cpp
===================================================================
--- branches/v4/platforms/caba-tsar-v0/top.cpp	(revision 371)
+++ branches/v4/platforms/caba-tsar-v0/top.cpp	(revision 371)
@@ -0,0 +1,889 @@
+#include <systemc>
+#include <sys/time.h>
+#include <iostream>
+#include <cstdlib>
+#include <cstdarg>
+
+#include "mapping_table.h"
+#include "mips.h"
+#include "ississ2.h"
+#include "iss_simhelper.h"
+#include "vci_simple_ram.h"
+#include "vci_multi_tty.h"
+#include "vci_vgmn.h"
+#include "vci_mem_cache.h"
+#include "vci_local_crossbar.h"
+#include "vci_dspinplus_network.h"
+#include "vci_cc_xcache_wrapper.h"
+
+#ifdef USE_GDB_SERVER
+#include "iss/gdbserver.h"
+#endif
+
+#include "segmentation.h"
+
+int _main(int argc, char *argv[])
+{
+	using namespace sc_core;
+	// Avoid repeating these everywhere
+	using soclib::common::IntTab;
+	using soclib::common::Segment;
+
+	// Define VCI parameters
+	typedef soclib::caba::VciParams<4,8,32,1,1,1,8,4,4,1> vci_param;
+	typedef soclib::common::IssIss2<soclib::common::IssSimhelper<soclib::common::MipsElIss> > proc_iss;
+
+	// Mapping table
+
+	soclib::common::MappingTable maptabp(32, IntTab(2,10), IntTab(2,3), 0x00C00000);
+
+	maptabp.add(Segment("reset", RESET_BASE, RESET_SIZE, IntTab(2,1), true));
+	maptabp.add(Segment("excep", EXCEP_BASE, EXCEP_SIZE, IntTab(2,1), true));
+	maptabp.add(Segment("tty"  , TTY_BASE  , TTY_SIZE  , IntTab(3,1), false));
+
+	maptabp.add(Segment("mc_r0" , MC0_R_BASE , MC0_R_SIZE , IntTab(0,0), false, true, IntTab(0,0)));
+	maptabp.add(Segment("mc_m0" , MC0_M_BASE , MC0_M_SIZE , IntTab(0,0), true ));
+	maptabp.add(Segment("mc_r1" , MC1_R_BASE , MC1_R_SIZE , IntTab(1,0), false, true, IntTab(1,0)));
+	maptabp.add(Segment("mc_m1" , MC1_M_BASE , MC1_M_SIZE , IntTab(1,0), true ));
+	maptabp.add(Segment("mc_r2" , MC2_R_BASE , MC2_R_SIZE , IntTab(2,0), false, true, IntTab(2,0)));
+	maptabp.add(Segment("mc_m2" , MC2_M_BASE , MC2_M_SIZE , IntTab(2,0), true ));
+	maptabp.add(Segment("mc_r3" , MC3_R_BASE , MC3_R_SIZE , IntTab(3,0), false, true, IntTab(3,0)));
+	maptabp.add(Segment("mc_m3" , MC3_M_BASE , MC3_M_SIZE , IntTab(3,0), true ));
+
+	std::cout << maptabp << std::endl;
+
+	soclib::common::MappingTable maptabc(32, IntTab(2,10), IntTab(2,3), 0x00C00000);
+
+	maptabc.add(Segment("proc0" , PROC0_BASE , PROC0_SIZE , IntTab(0,0), false, true, IntTab(0,0)));
+	maptabc.add(Segment("proc1" , PROC1_BASE , PROC1_SIZE , IntTab(0,1), false, true, IntTab(0,1)));
+	maptabc.add(Segment("proc2" , PROC2_BASE , PROC2_SIZE , IntTab(0,2), false, true, IntTab(0,2)));
+	maptabc.add(Segment("proc3" , PROC3_BASE , PROC3_SIZE , IntTab(0,3), false, true, IntTab(0,3)));
+	maptabc.add(Segment("proc4" , PROC4_BASE , PROC4_SIZE , IntTab(1,0), false, true, IntTab(1,0)));
+	maptabc.add(Segment("proc5" , PROC5_BASE , PROC5_SIZE , IntTab(1,1), false, true, IntTab(1,1)));
+	maptabc.add(Segment("proc6" , PROC6_BASE , PROC6_SIZE , IntTab(1,2), false, true, IntTab(1,2)));
+	maptabc.add(Segment("proc7" , PROC7_BASE , PROC7_SIZE , IntTab(1,3), false, true, IntTab(1,3)));
+	maptabc.add(Segment("proc8" , PROC8_BASE , PROC8_SIZE , IntTab(2,0), false, true, IntTab(2,0)));
+	maptabc.add(Segment("proc9" , PROC9_BASE , PROC9_SIZE , IntTab(2,1), false, true, IntTab(2,1)));
+	maptabc.add(Segment("proc10" , PROC10_BASE , PROC10_SIZE , IntTab(2,2), false, true, IntTab(2,2)));
+	maptabc.add(Segment("proc11" , PROC11_BASE , PROC11_SIZE , IntTab(2,3), false, true, IntTab(2,3)));
+	maptabc.add(Segment("proc12" , PROC12_BASE , PROC12_SIZE , IntTab(3,0), false, true, IntTab(3,0)));
+	maptabc.add(Segment("proc13" , PROC13_BASE , PROC13_SIZE , IntTab(3,1), false, true, IntTab(3,1)));
+	maptabc.add(Segment("proc14" , PROC14_BASE , PROC14_SIZE , IntTab(3,2), false, true, IntTab(3,2)));
+	maptabc.add(Segment("proc15" , PROC15_BASE , PROC15_SIZE , IntTab(3,3), false, true, IntTab(3,3)));
+
+	std::cout << maptabc << std::endl;
+
+	soclib::common::MappingTable maptabx(32, IntTab(8,4), IntTab(4,4), 0x00C00000);
+	maptabx.add(Segment("xram0" , MC0_M_BASE , MC0_M_SIZE , IntTab(0,0), false));
+	maptabx.add(Segment("xram1" , MC1_M_BASE , MC1_M_SIZE , IntTab(0,0), false));
+	maptabx.add(Segment("xram2" , MC2_M_BASE , MC2_M_SIZE , IntTab(0,0), false));
+	maptabx.add(Segment("xram3" , MC3_M_BASE , MC3_M_SIZE , IntTab(0,0), false));
+	std::cout << maptabx << std::endl;
+
+
+	// Signals
+
+	sc_clock	signal_clk("clk");
+	sc_signal<bool> signal_resetn("resetn");
+   
+	sc_signal<bool> signal_proc0_it0("proc0_it0"); 
+	sc_signal<bool> signal_proc0_it1("proc0_it1"); 
+	sc_signal<bool> signal_proc0_it2("proc0_it2"); 
+	sc_signal<bool> signal_proc0_it3("proc0_it3"); 
+	sc_signal<bool> signal_proc0_it4("proc0_it4"); 
+	sc_signal<bool> signal_proc0_it5("proc0_it5");
+
+	sc_signal<bool> signal_proc1_it0("proc1_it0"); 
+	sc_signal<bool> signal_proc1_it1("proc1_it1"); 
+	sc_signal<bool> signal_proc1_it2("proc1_it2"); 
+	sc_signal<bool> signal_proc1_it3("proc1_it3"); 
+	sc_signal<bool> signal_proc1_it4("proc1_it4"); 
+	sc_signal<bool> signal_proc1_it5("proc1_it5");
+
+	sc_signal<bool> signal_proc2_it0("proc2_it0"); 
+	sc_signal<bool> signal_proc2_it1("proc2_it1"); 
+	sc_signal<bool> signal_proc2_it2("proc2_it2"); 
+	sc_signal<bool> signal_proc2_it3("proc2_it3"); 
+	sc_signal<bool> signal_proc2_it4("proc2_it4"); 
+	sc_signal<bool> signal_proc2_it5("proc2_it5");
+
+	sc_signal<bool> signal_proc3_it0("proc3_it0"); 
+	sc_signal<bool> signal_proc3_it1("proc3_it1"); 
+	sc_signal<bool> signal_proc3_it2("proc3_it2"); 
+	sc_signal<bool> signal_proc3_it3("proc3_it3"); 
+	sc_signal<bool> signal_proc3_it4("proc3_it4"); 
+	sc_signal<bool> signal_proc3_it5("proc3_it5");
+
+	sc_signal<bool> signal_proc4_it0("proc4_it0"); 
+	sc_signal<bool> signal_proc4_it1("proc4_it1"); 
+	sc_signal<bool> signal_proc4_it2("proc4_it2"); 
+	sc_signal<bool> signal_proc4_it3("proc4_it3"); 
+	sc_signal<bool> signal_proc4_it4("proc4_it4"); 
+	sc_signal<bool> signal_proc4_it5("proc4_it5");
+
+	sc_signal<bool> signal_proc5_it0("proc5_it0"); 
+	sc_signal<bool> signal_proc5_it1("proc5_it1"); 
+	sc_signal<bool> signal_proc5_it2("proc5_it2"); 
+	sc_signal<bool> signal_proc5_it3("proc5_it3"); 
+	sc_signal<bool> signal_proc5_it4("proc5_it4"); 
+	sc_signal<bool> signal_proc5_it5("proc5_it5");
+
+	sc_signal<bool> signal_proc6_it0("proc6_it0"); 
+	sc_signal<bool> signal_proc6_it1("proc6_it1"); 
+	sc_signal<bool> signal_proc6_it2("proc6_it2"); 
+	sc_signal<bool> signal_proc6_it3("proc6_it3"); 
+	sc_signal<bool> signal_proc6_it4("proc6_it4"); 
+	sc_signal<bool> signal_proc6_it5("proc6_it5");
+
+	sc_signal<bool> signal_proc7_it0("proc7_it0"); 
+	sc_signal<bool> signal_proc7_it1("proc7_it1"); 
+	sc_signal<bool> signal_proc7_it2("proc7_it2"); 
+	sc_signal<bool> signal_proc7_it3("proc7_it3"); 
+	sc_signal<bool> signal_proc7_it4("proc7_it4"); 
+	sc_signal<bool> signal_proc7_it5("proc7_it5");
+
+	sc_signal<bool> signal_proc8_it0("proc8_it0"); 
+	sc_signal<bool> signal_proc8_it1("proc8_it1"); 
+	sc_signal<bool> signal_proc8_it2("proc8_it2"); 
+	sc_signal<bool> signal_proc8_it3("proc8_it3"); 
+	sc_signal<bool> signal_proc8_it4("proc8_it4"); 
+	sc_signal<bool> signal_proc8_it5("proc8_it5");
+
+	sc_signal<bool> signal_proc9_it0("proc9_it0"); 
+	sc_signal<bool> signal_proc9_it1("proc9_it1"); 
+	sc_signal<bool> signal_proc9_it2("proc9_it2"); 
+	sc_signal<bool> signal_proc9_it3("proc9_it3"); 
+	sc_signal<bool> signal_proc9_it4("proc9_it4"); 
+	sc_signal<bool> signal_proc9_it5("proc9_it5");
+
+	sc_signal<bool> signal_proc10_it0("proc10_it0"); 
+	sc_signal<bool> signal_proc10_it1("proc10_it1"); 
+	sc_signal<bool> signal_proc10_it2("proc10_it2"); 
+	sc_signal<bool> signal_proc10_it3("proc10_it3"); 
+	sc_signal<bool> signal_proc10_it4("proc10_it4"); 
+	sc_signal<bool> signal_proc10_it5("proc10_it5");
+
+	sc_signal<bool> signal_proc11_it0("proc11_it0"); 
+	sc_signal<bool> signal_proc11_it1("proc11_it1"); 
+	sc_signal<bool> signal_proc11_it2("proc11_it2"); 
+	sc_signal<bool> signal_proc11_it3("proc11_it3"); 
+	sc_signal<bool> signal_proc11_it4("proc11_it4"); 
+	sc_signal<bool> signal_proc11_it5("proc11_it5");
+
+	sc_signal<bool> signal_proc12_it0("proc12_it0"); 
+	sc_signal<bool> signal_proc12_it1("proc12_it1"); 
+	sc_signal<bool> signal_proc12_it2("proc12_it2"); 
+	sc_signal<bool> signal_proc12_it3("proc12_it3"); 
+	sc_signal<bool> signal_proc12_it4("proc12_it4"); 
+	sc_signal<bool> signal_proc12_it5("proc12_it5");
+
+	sc_signal<bool> signal_proc13_it0("proc13_it0"); 
+	sc_signal<bool> signal_proc13_it1("proc13_it1"); 
+	sc_signal<bool> signal_proc13_it2("proc13_it2"); 
+	sc_signal<bool> signal_proc13_it3("proc13_it3"); 
+	sc_signal<bool> signal_proc13_it4("proc13_it4"); 
+	sc_signal<bool> signal_proc13_it5("proc13_it5");
+
+	sc_signal<bool> signal_proc14_it0("proc14_it0"); 
+	sc_signal<bool> signal_proc14_it1("proc14_it1"); 
+	sc_signal<bool> signal_proc14_it2("proc14_it2"); 
+	sc_signal<bool> signal_proc14_it3("proc14_it3"); 
+	sc_signal<bool> signal_proc14_it4("proc14_it4"); 
+	sc_signal<bool> signal_proc14_it5("proc14_it5");
+
+	sc_signal<bool> signal_proc15_it0("proc15_it0"); 
+	sc_signal<bool> signal_proc15_it1("proc15_it1"); 
+	sc_signal<bool> signal_proc15_it2("proc15_it2"); 
+	sc_signal<bool> signal_proc15_it3("proc15_it3"); 
+	sc_signal<bool> signal_proc15_it4("proc15_it4"); 
+	sc_signal<bool> signal_proc15_it5("proc15_it5");
+
+
+	soclib::caba::VciSignals<vci_param> signal_vci_ini_proc0("vci_ini_proc0");
+	soclib::caba::VciSignals<vci_param> signal_vci_tgt_proc0("vci_tgt_proc0");
+
+	soclib::caba::VciSignals<vci_param> signal_vci_ini_proc1("vci_ini_proc1");
+	soclib::caba::VciSignals<vci_param> signal_vci_tgt_proc1("vci_tgt_proc1");
+
+	soclib::caba::VciSignals<vci_param> signal_vci_ini_proc2("vci_ini_proc2");
+	soclib::caba::VciSignals<vci_param> signal_vci_tgt_proc2("vci_tgt_proc2");
+
+	soclib::caba::VciSignals<vci_param> signal_vci_ini_proc3("vci_ini_proc3");
+	soclib::caba::VciSignals<vci_param> signal_vci_tgt_proc3("vci_tgt_proc3");
+
+	soclib::caba::VciSignals<vci_param> signal_vci_ini_proc4("vci_ini_proc4");
+	soclib::caba::VciSignals<vci_param> signal_vci_tgt_proc4("vci_tgt_proc4");
+
+	soclib::caba::VciSignals<vci_param> signal_vci_ini_proc5("vci_ini_proc5");
+	soclib::caba::VciSignals<vci_param> signal_vci_tgt_proc5("vci_tgt_proc5");
+
+	soclib::caba::VciSignals<vci_param> signal_vci_ini_proc6("vci_ini_proc6");
+	soclib::caba::VciSignals<vci_param> signal_vci_tgt_proc6("vci_tgt_proc6");
+
+	soclib::caba::VciSignals<vci_param> signal_vci_ini_proc7("vci_ini_proc7");
+	soclib::caba::VciSignals<vci_param> signal_vci_tgt_proc7("vci_tgt_proc7");
+
+	soclib::caba::VciSignals<vci_param> signal_vci_ini_proc8("vci_ini_proc8");
+	soclib::caba::VciSignals<vci_param> signal_vci_tgt_proc8("vci_tgt_proc8");
+
+	soclib::caba::VciSignals<vci_param> signal_vci_ini_proc9("vci_ini_proc9");
+	soclib::caba::VciSignals<vci_param> signal_vci_tgt_proc9("vci_tgt_proc9");
+
+	soclib::caba::VciSignals<vci_param> signal_vci_ini_proc10("vci_ini_proc10");
+	soclib::caba::VciSignals<vci_param> signal_vci_tgt_proc10("vci_tgt_proc10");
+
+	soclib::caba::VciSignals<vci_param> signal_vci_ini_proc11("vci_ini_proc11");
+	soclib::caba::VciSignals<vci_param> signal_vci_tgt_proc11("vci_tgt_proc11");
+
+	soclib::caba::VciSignals<vci_param> signal_vci_ini_proc12("vci_ini_proc12");
+	soclib::caba::VciSignals<vci_param> signal_vci_tgt_proc12("vci_tgt_proc12");
+
+	soclib::caba::VciSignals<vci_param> signal_vci_ini_proc13("vci_ini_proc13");
+	soclib::caba::VciSignals<vci_param> signal_vci_tgt_proc13("vci_tgt_proc13");
+
+	soclib::caba::VciSignals<vci_param> signal_vci_ini_proc14("vci_ini_proc14");
+	soclib::caba::VciSignals<vci_param> signal_vci_tgt_proc14("vci_tgt_proc14");
+
+	soclib::caba::VciSignals<vci_param> signal_vci_ini_proc15("vci_ini_proc15");
+	soclib::caba::VciSignals<vci_param> signal_vci_tgt_proc15("vci_tgt_proc15");
+
+	soclib::caba::VciSignals<vci_param> signal_vci_tgt_tty("vci_tgt_tty");
+
+	soclib::caba::VciSignals<vci_param> signal_vci_tgt_rom("vci_tgt_rom");
+
+	soclib::caba::VciSignals<vci_param> signal_vci_tgt_xram("vci_tgt_xram");
+
+	soclib::caba::VciSignals<vci_param> signal_vci_ixr_memc0("vci_ixr_memc0");
+	soclib::caba::VciSignals<vci_param> signal_vci_ini_memc0("vci_ini_memc0");
+	soclib::caba::VciSignals<vci_param> signal_vci_tgt_memc0("vci_tgt_memc0");
+
+	soclib::caba::VciSignals<vci_param> signal_vci_ixr_memc1("vci_ixr_memc1");
+	soclib::caba::VciSignals<vci_param> signal_vci_ini_memc1("vci_ini_memc1");
+	soclib::caba::VciSignals<vci_param> signal_vci_tgt_memc1("vci_tgt_memc1");
+
+	soclib::caba::VciSignals<vci_param> signal_vci_ixr_memc2("vci_ixr_memc2");
+	soclib::caba::VciSignals<vci_param> signal_vci_ini_memc2("vci_ini_memc2");
+	soclib::caba::VciSignals<vci_param> signal_vci_tgt_memc2("vci_tgt_memc2");
+
+	soclib::caba::VciSignals<vci_param> signal_vci_ixr_memc3("vci_ixr_memc3");
+	soclib::caba::VciSignals<vci_param> signal_vci_ini_memc3("vci_ini_memc3");
+	soclib::caba::VciSignals<vci_param> signal_vci_tgt_memc3("vci_tgt_memc3");
+
+	soclib::caba::VciSignals<vci_param> signal_vci_ini_pdspin0("vci_ini_pdspin0");
+	soclib::caba::VciSignals<vci_param> signal_vci_tgt_pdspin0("vci_tgt_pdspin0");
+
+	soclib::caba::VciSignals<vci_param> signal_vci_ini_pdspin1("vci_ini_pdspin1");
+	soclib::caba::VciSignals<vci_param> signal_vci_tgt_pdspin1("vci_tgt_pdspin1");
+
+	soclib::caba::VciSignals<vci_param> signal_vci_ini_pdspin2("vci_ini_pdspin2");
+	soclib::caba::VciSignals<vci_param> signal_vci_tgt_pdspin2("vci_tgt_pdspin2");
+
+	soclib::caba::VciSignals<vci_param> signal_vci_ini_pdspin3("vci_ini_pdspin3");
+	soclib::caba::VciSignals<vci_param> signal_vci_tgt_pdspin3("vci_tgt_pdspin3");
+
+	soclib::caba::VciSignals<vci_param> signal_vci_ini_cdspin0("vci_ini_cdspin0");
+	soclib::caba::VciSignals<vci_param> signal_vci_tgt_cdspin0("vci_tgt_cdspin0");
+
+	soclib::caba::VciSignals<vci_param> signal_vci_ini_cdspin1("vci_ini_cdspin1");
+	soclib::caba::VciSignals<vci_param> signal_vci_tgt_cdspin1("vci_tgt_cdspin1");
+
+	soclib::caba::VciSignals<vci_param> signal_vci_ini_cdspin2("vci_ini_cdspin2");
+	soclib::caba::VciSignals<vci_param> signal_vci_tgt_cdspin2("vci_tgt_cdspin2");
+
+	soclib::caba::VciSignals<vci_param> signal_vci_ini_cdspin3("vci_ini_cdspin3");
+	soclib::caba::VciSignals<vci_param> signal_vci_tgt_cdspin3("vci_tgt_cdspin3");
+
+
+
+	sc_signal<bool> signal_tty_irq0("signal_tty_irq0"); 
+	sc_signal<bool> signal_tty_irq1("signal_tty_irq1"); 
+	sc_signal<bool> signal_tty_irq2("signal_tty_irq2"); 
+	sc_signal<bool> signal_tty_irq3("signal_tty_irq3"); 
+	sc_signal<bool> signal_tty_irq4("signal_tty_irq4"); 
+	sc_signal<bool> signal_tty_irq5("signal_tty_irq5"); 
+	sc_signal<bool> signal_tty_irq6("signal_tty_irq6"); 
+	sc_signal<bool> signal_tty_irq7("signal_tty_irq7"); 
+	sc_signal<bool> signal_tty_irq8("signal_tty_irq8"); 
+	sc_signal<bool> signal_tty_irq9("signal_tty_irq9"); 
+	sc_signal<bool> signal_tty_irq10("signal_tty_irq10"); 
+	sc_signal<bool> signal_tty_irq11("signal_tty_irq11"); 
+	sc_signal<bool> signal_tty_irq12("signal_tty_irq12"); 
+	sc_signal<bool> signal_tty_irq13("signal_tty_irq13"); 
+	sc_signal<bool> signal_tty_irq14("signal_tty_irq14"); 
+	sc_signal<bool> signal_tty_irq15("signal_tty_irq15"); 
+
+	// Components
+	// VCI ports indexation : 3 initiateurs et 5 cibles
+
+        // INIT0 : proc0_ini
+        // INIT1 : memc_ini
+        // INIT2 : memc_ixr
+
+	// TGT 0 : rom_tgt
+	// TGT 1 : tty_tgt
+        // TGT 2 : xram_tgt
+	// TGT 3 : memc_tgt
+	// TGT 4 : proc0_tgt
+
+	soclib::common::Loader loader("soft/bin.soft");
+
+	soclib::caba::VciCcXcacheWrapper<vci_param, proc_iss > 
+	proc0("proc0", 0, maptabp,maptabc,IntTab(0,0),IntTab(0,0),4,64,16,4,64,16,CLEANUP_OFFSET);
+
+	soclib::caba::VciCcXcacheWrapper<vci_param, proc_iss > 
+	proc1("proc1", 1, maptabp,maptabc,IntTab(0,1),IntTab(0,1),4,64,16,4,64,16,CLEANUP_OFFSET);
+
+	soclib::caba::VciCcXcacheWrapper<vci_param, proc_iss > 
+	proc2("proc2", 2, maptabp,maptabc,IntTab(0,2),IntTab(0,2),4,64,16,4,64,16,CLEANUP_OFFSET);
+
+	soclib::caba::VciCcXcacheWrapper<vci_param, proc_iss > 
+	proc3("proc3", 3, maptabp,maptabc,IntTab(0,3),IntTab(0,3),4,64,16,4,64,16,CLEANUP_OFFSET);
+
+	soclib::caba::VciCcXcacheWrapper<vci_param, proc_iss > 
+	proc4("proc4", 4, maptabp,maptabc,IntTab(1,0),IntTab(1,0),4,64,16,4,64,16,CLEANUP_OFFSET);
+
+	soclib::caba::VciCcXcacheWrapper<vci_param, proc_iss > 
+	proc5("proc5", 5, maptabp,maptabc,IntTab(1,1),IntTab(1,1),4,64,16,4,64,16,CLEANUP_OFFSET);
+
+	soclib::caba::VciCcXcacheWrapper<vci_param, proc_iss > 
+	proc6("proc6", 6, maptabp,maptabc,IntTab(1,2),IntTab(1,2),4,64,16,4,64,16,CLEANUP_OFFSET);
+
+	soclib::caba::VciCcXcacheWrapper<vci_param, proc_iss > 
+	proc7("proc7", 7, maptabp,maptabc,IntTab(1,3),IntTab(1,3),4,64,16,4,64,16,CLEANUP_OFFSET);
+
+	soclib::caba::VciCcXcacheWrapper<vci_param, proc_iss > 
+	proc8("proc8", 8, maptabp,maptabc,IntTab(2,0),IntTab(2,0),4,64,16,4,64,16,CLEANUP_OFFSET);
+
+	soclib::caba::VciCcXcacheWrapper<vci_param, proc_iss > 
+	proc9("proc9", 9, maptabp,maptabc,IntTab(2,1),IntTab(2,1),4,64,16,4,64,16,CLEANUP_OFFSET);
+
+	soclib::caba::VciCcXcacheWrapper<vci_param, proc_iss > 
+	proc10("proc10", 10, maptabp,maptabc,IntTab(2,2),IntTab(2,2),4,64,16,4,64,16,CLEANUP_OFFSET);
+
+	soclib::caba::VciCcXcacheWrapper<vci_param, proc_iss > 
+	proc11("proc11", 11, maptabp,maptabc,IntTab(2,3),IntTab(2,3),4,64,16,4,64,16,CLEANUP_OFFSET);
+
+	soclib::caba::VciCcXcacheWrapper<vci_param, proc_iss > 
+	proc12("proc12", 12, maptabp,maptabc,IntTab(3,0),IntTab(3,0),4,64,16,4,64,16,CLEANUP_OFFSET);
+
+	soclib::caba::VciCcXcacheWrapper<vci_param, proc_iss > 
+	proc13("proc13", 13, maptabp,maptabc,IntTab(3,1),IntTab(3,1),4,64,16,4,64,16,CLEANUP_OFFSET);
+
+	soclib::caba::VciCcXcacheWrapper<vci_param, proc_iss > 
+	proc14("proc14", 14, maptabp,maptabc,IntTab(3,2),IntTab(3,2),4,64,16,4,64,16,CLEANUP_OFFSET);
+
+	soclib::caba::VciCcXcacheWrapper<vci_param, proc_iss > 
+	proc15("proc15", 15, maptabp,maptabc,IntTab(3,3),IntTab(3,3),4,64,16,4,64,16,CLEANUP_OFFSET);
+
+	soclib::caba::VciSimpleRam<vci_param> 
+	rom("rom", IntTab(2,1), maptabp, loader);
+
+	soclib::caba::VciSimpleRam<vci_param> 
+	xram("xram",IntTab(0,0),maptabx, loader);
+
+	soclib::caba::VciMemCache<vci_param> 
+	memc0("memc0",maptabp,maptabc,maptabx,IntTab(0,0),IntTab(0,0),IntTab(0,0),16,256,16);
+
+	soclib::caba::VciMemCache<vci_param> 
+	memc1("memc1",maptabp,maptabc,maptabx,IntTab(1,0),IntTab(1,0),IntTab(1,0),16,256,16);
+
+	soclib::caba::VciMemCache<vci_param> 
+	memc2("memc2",maptabp,maptabc,maptabx,IntTab(2,0),IntTab(2,0),IntTab(2,0),16,256,16);
+
+	soclib::caba::VciMemCache<vci_param> 
+	memc3("memc3",maptabp,maptabc,maptabx,IntTab(3,0),IntTab(3,0),IntTab(3,0),16,256,16);
+	
+	soclib::caba::VciMultiTty<vci_param> 
+	tty("tty",IntTab(3,1),maptabp,"tty0","tty1","tty2","tty3","tty4","tty5","tty6","tty7","tty8","tty9","tty10","tty11","tty12","tty13","tty14","tty15",NULL);
+
+	soclib::caba::VciLocalCrossbar<vci_param> 
+	clusterPN0("clusterPN0",maptabp, IntTab(0), IntTab(0), 4, 1 );
+
+	soclib::caba::VciLocalCrossbar<vci_param> 
+	clusterPN1("clusterPN1",maptabp, IntTab(1), IntTab(1), 4, 1 );
+
+	soclib::caba::VciLocalCrossbar<vci_param> 
+	clusterPN2("clusterPN2",maptabp, IntTab(2), IntTab(2), 4, 2 );
+
+	soclib::caba::VciLocalCrossbar<vci_param> 
+	clusterPN3("clusterPN3",maptabp, IntTab(3), IntTab(3), 4, 2 );
+
+	soclib::caba::VciLocalCrossbar<vci_param> 
+	clusterCN0("clusterCN0",maptabc, IntTab(0), IntTab(0), 1, 4 );
+
+	soclib::caba::VciLocalCrossbar<vci_param> 
+	clusterCN1("clusterCN1",maptabc, IntTab(1), IntTab(1), 1, 4 );
+
+	soclib::caba::VciLocalCrossbar<vci_param> 
+	clusterCN2("clusterCN2",maptabc, IntTab(2), IntTab(2), 1, 4 );
+
+	soclib::caba::VciLocalCrossbar<vci_param> 
+	clusterCN3("clusterCN3",maptabc, IntTab(3), IntTab(3), 1, 4 );
+
+	soclib::caba::VciDspinPlusNetwork<vci_param, 4, 1> vciDspinCNetwork("vciDspinCNetwork", maptabc, 2, 2);
+
+	soclib::caba::VciDspinPlusNetwork<vci_param, 4, 1> vciDspinPNetwork("vciDspinPNetwork", maptabp, 2, 2);
+
+	soclib::caba::VciVgmn<vci_param> 
+	vgmn("vgmn",maptabx, 4, 1, 1, 4);
+
+	// Net-List
+ 
+	proc0.p_clk(signal_clk);  
+	proc0.p_resetn(signal_resetn);  
+	proc0.p_irq[0](signal_proc0_it0); 
+	proc0.p_irq[1](signal_proc0_it1); 
+	proc0.p_irq[2](signal_proc0_it2); 
+	proc0.p_irq[3](signal_proc0_it3); 
+	proc0.p_irq[4](signal_proc0_it4); 
+	proc0.p_irq[5](signal_proc0_it5); 
+	proc0.p_vci_ini(signal_vci_ini_proc0);
+	proc0.p_vci_tgt(signal_vci_tgt_proc0);
+
+	proc1.p_clk(signal_clk);  
+	proc1.p_resetn(signal_resetn);  
+	proc1.p_irq[0](signal_proc1_it0); 
+	proc1.p_irq[1](signal_proc1_it1); 
+	proc1.p_irq[2](signal_proc1_it2); 
+	proc1.p_irq[3](signal_proc1_it3); 
+	proc1.p_irq[4](signal_proc1_it4); 
+	proc1.p_irq[5](signal_proc1_it5); 
+	proc1.p_vci_ini(signal_vci_ini_proc1);
+	proc1.p_vci_tgt(signal_vci_tgt_proc1);
+
+	proc2.p_clk(signal_clk);  
+	proc2.p_resetn(signal_resetn);  
+	proc2.p_irq[0](signal_proc2_it0); 
+	proc2.p_irq[1](signal_proc2_it1); 
+	proc2.p_irq[2](signal_proc2_it2); 
+	proc2.p_irq[3](signal_proc2_it3); 
+	proc2.p_irq[4](signal_proc2_it4); 
+	proc2.p_irq[5](signal_proc2_it5); 
+	proc2.p_vci_ini(signal_vci_ini_proc2);
+	proc2.p_vci_tgt(signal_vci_tgt_proc2);
+
+	proc3.p_clk(signal_clk);  
+	proc3.p_resetn(signal_resetn);  
+	proc3.p_irq[0](signal_proc3_it0); 
+	proc3.p_irq[1](signal_proc3_it1); 
+	proc3.p_irq[2](signal_proc3_it2); 
+	proc3.p_irq[3](signal_proc3_it3); 
+	proc3.p_irq[4](signal_proc3_it4); 
+	proc3.p_irq[5](signal_proc3_it5); 
+	proc3.p_vci_ini(signal_vci_ini_proc3);
+	proc3.p_vci_tgt(signal_vci_tgt_proc3);
+
+	proc4.p_clk(signal_clk);  
+	proc4.p_resetn(signal_resetn);  
+	proc4.p_irq[0](signal_proc4_it0); 
+	proc4.p_irq[1](signal_proc4_it1); 
+	proc4.p_irq[2](signal_proc4_it2); 
+	proc4.p_irq[3](signal_proc4_it3); 
+	proc4.p_irq[4](signal_proc4_it4); 
+	proc4.p_irq[5](signal_proc4_it5); 
+	proc4.p_vci_ini(signal_vci_ini_proc4);
+	proc4.p_vci_tgt(signal_vci_tgt_proc4);
+
+	proc5.p_clk(signal_clk);  
+	proc5.p_resetn(signal_resetn);  
+	proc5.p_irq[0](signal_proc5_it0); 
+	proc5.p_irq[1](signal_proc5_it1); 
+	proc5.p_irq[2](signal_proc5_it2); 
+	proc5.p_irq[3](signal_proc5_it3); 
+	proc5.p_irq[4](signal_proc5_it4); 
+	proc5.p_irq[5](signal_proc5_it5); 
+	proc5.p_vci_ini(signal_vci_ini_proc5);
+	proc5.p_vci_tgt(signal_vci_tgt_proc5);
+
+	proc6.p_clk(signal_clk);  
+	proc6.p_resetn(signal_resetn);  
+	proc6.p_irq[0](signal_proc6_it0); 
+	proc6.p_irq[1](signal_proc6_it1); 
+	proc6.p_irq[2](signal_proc6_it2); 
+	proc6.p_irq[3](signal_proc6_it3); 
+	proc6.p_irq[4](signal_proc6_it4); 
+	proc6.p_irq[5](signal_proc6_it5); 
+	proc6.p_vci_ini(signal_vci_ini_proc6);
+	proc6.p_vci_tgt(signal_vci_tgt_proc6);
+
+	proc7.p_clk(signal_clk);  
+	proc7.p_resetn(signal_resetn);  
+	proc7.p_irq[0](signal_proc7_it0); 
+	proc7.p_irq[1](signal_proc7_it1); 
+	proc7.p_irq[2](signal_proc7_it2); 
+	proc7.p_irq[3](signal_proc7_it3); 
+	proc7.p_irq[4](signal_proc7_it4); 
+	proc7.p_irq[5](signal_proc7_it5); 
+	proc7.p_vci_ini(signal_vci_ini_proc7);
+	proc7.p_vci_tgt(signal_vci_tgt_proc7);
+
+	proc8.p_clk(signal_clk);  
+	proc8.p_resetn(signal_resetn);  
+	proc8.p_irq[0](signal_proc8_it0); 
+	proc8.p_irq[1](signal_proc8_it1); 
+	proc8.p_irq[2](signal_proc8_it2); 
+	proc8.p_irq[3](signal_proc8_it3); 
+	proc8.p_irq[4](signal_proc8_it4); 
+	proc8.p_irq[5](signal_proc8_it5); 
+	proc8.p_vci_ini(signal_vci_ini_proc8);
+	proc8.p_vci_tgt(signal_vci_tgt_proc8);
+
+	proc9.p_clk(signal_clk);  
+	proc9.p_resetn(signal_resetn);  
+	proc9.p_irq[0](signal_proc9_it0); 
+	proc9.p_irq[1](signal_proc9_it1); 
+	proc9.p_irq[2](signal_proc9_it2); 
+	proc9.p_irq[3](signal_proc9_it3); 
+	proc9.p_irq[4](signal_proc9_it4); 
+	proc9.p_irq[5](signal_proc9_it5); 
+	proc9.p_vci_ini(signal_vci_ini_proc9);
+	proc9.p_vci_tgt(signal_vci_tgt_proc9);
+
+	proc10.p_clk(signal_clk);  
+	proc10.p_resetn(signal_resetn);  
+	proc10.p_irq[0](signal_proc10_it0); 
+	proc10.p_irq[1](signal_proc10_it1); 
+	proc10.p_irq[2](signal_proc10_it2); 
+	proc10.p_irq[3](signal_proc10_it3); 
+	proc10.p_irq[4](signal_proc10_it4); 
+	proc10.p_irq[5](signal_proc10_it5); 
+	proc10.p_vci_ini(signal_vci_ini_proc10);
+	proc10.p_vci_tgt(signal_vci_tgt_proc10);
+
+	proc11.p_clk(signal_clk);  
+	proc11.p_resetn(signal_resetn);  
+	proc11.p_irq[0](signal_proc11_it0); 
+	proc11.p_irq[1](signal_proc11_it1); 
+	proc11.p_irq[2](signal_proc11_it2); 
+	proc11.p_irq[3](signal_proc11_it3); 
+	proc11.p_irq[4](signal_proc11_it4); 
+	proc11.p_irq[5](signal_proc11_it5); 
+	proc11.p_vci_ini(signal_vci_ini_proc11);
+	proc11.p_vci_tgt(signal_vci_tgt_proc11);
+
+	proc12.p_clk(signal_clk);  
+	proc12.p_resetn(signal_resetn);  
+	proc12.p_irq[0](signal_proc12_it0); 
+	proc12.p_irq[1](signal_proc12_it1); 
+	proc12.p_irq[2](signal_proc12_it2); 
+	proc12.p_irq[3](signal_proc12_it3); 
+	proc12.p_irq[4](signal_proc12_it4); 
+	proc12.p_irq[5](signal_proc12_it5); 
+	proc12.p_vci_ini(signal_vci_ini_proc12);
+	proc12.p_vci_tgt(signal_vci_tgt_proc12);
+
+	proc13.p_clk(signal_clk);  
+	proc13.p_resetn(signal_resetn);  
+	proc13.p_irq[0](signal_proc13_it0); 
+	proc13.p_irq[1](signal_proc13_it1); 
+	proc13.p_irq[2](signal_proc13_it2); 
+	proc13.p_irq[3](signal_proc13_it3); 
+	proc13.p_irq[4](signal_proc13_it4); 
+	proc13.p_irq[5](signal_proc13_it5); 
+	proc13.p_vci_ini(signal_vci_ini_proc13);
+	proc13.p_vci_tgt(signal_vci_tgt_proc13);
+
+	proc14.p_clk(signal_clk);  
+	proc14.p_resetn(signal_resetn);  
+	proc14.p_irq[0](signal_proc14_it0); 
+	proc14.p_irq[1](signal_proc14_it1); 
+	proc14.p_irq[2](signal_proc14_it2); 
+	proc14.p_irq[3](signal_proc14_it3); 
+	proc14.p_irq[4](signal_proc14_it4); 
+	proc14.p_irq[5](signal_proc14_it5); 
+	proc14.p_vci_ini(signal_vci_ini_proc14);
+	proc14.p_vci_tgt(signal_vci_tgt_proc14);
+
+	proc15.p_clk(signal_clk);  
+	proc15.p_resetn(signal_resetn);  
+	proc15.p_irq[0](signal_proc15_it0); 
+	proc15.p_irq[1](signal_proc15_it1); 
+	proc15.p_irq[2](signal_proc15_it2); 
+	proc15.p_irq[3](signal_proc15_it3); 
+	proc15.p_irq[4](signal_proc15_it4); 
+	proc15.p_irq[5](signal_proc15_it5); 
+	proc15.p_vci_ini(signal_vci_ini_proc15);
+	proc15.p_vci_tgt(signal_vci_tgt_proc15);
+
+
+
+	rom.p_clk(signal_clk);
+	rom.p_resetn(signal_resetn);
+	rom.p_vci(signal_vci_tgt_rom);
+
+	tty.p_clk(signal_clk);
+	tty.p_resetn(signal_resetn);
+	tty.p_vci(signal_vci_tgt_tty);
+	tty.p_irq[0](signal_tty_irq0);
+	tty.p_irq[1](signal_tty_irq1);
+	tty.p_irq[2](signal_tty_irq2);
+	tty.p_irq[3](signal_tty_irq3);
+	tty.p_irq[4](signal_tty_irq4);
+	tty.p_irq[5](signal_tty_irq5);
+	tty.p_irq[6](signal_tty_irq6);
+	tty.p_irq[7](signal_tty_irq7); 
+	tty.p_irq[8](signal_tty_irq8);
+	tty.p_irq[9](signal_tty_irq9);
+	tty.p_irq[10](signal_tty_irq10);
+	tty.p_irq[11](signal_tty_irq11); 
+	tty.p_irq[12](signal_tty_irq12);
+	tty.p_irq[13](signal_tty_irq13);
+	tty.p_irq[14](signal_tty_irq14);
+	tty.p_irq[15](signal_tty_irq15);  
+
+	memc0.p_clk(signal_clk);
+	memc0.p_resetn(signal_resetn);
+	memc0.p_vci_tgt(signal_vci_tgt_memc0);	
+	memc0.p_vci_ini(signal_vci_ini_memc0);
+	memc0.p_vci_ixr(signal_vci_ixr_memc0);
+
+	memc1.p_clk(signal_clk);
+	memc1.p_resetn(signal_resetn);
+	memc1.p_vci_tgt(signal_vci_tgt_memc1);	
+	memc1.p_vci_ini(signal_vci_ini_memc1);
+	memc1.p_vci_ixr(signal_vci_ixr_memc1);
+
+	memc2.p_clk(signal_clk);
+	memc2.p_resetn(signal_resetn);
+	memc2.p_vci_tgt(signal_vci_tgt_memc2);	
+	memc2.p_vci_ini(signal_vci_ini_memc2);
+	memc2.p_vci_ixr(signal_vci_ixr_memc2);
+
+	memc3.p_clk(signal_clk);
+	memc3.p_resetn(signal_resetn);
+	memc3.p_vci_tgt(signal_vci_tgt_memc3);	
+	memc3.p_vci_ini(signal_vci_ini_memc3);
+	memc3.p_vci_ixr(signal_vci_ixr_memc3);
+
+	xram.p_clk(signal_clk);
+        xram.p_resetn(signal_resetn);
+	xram.p_vci(signal_vci_tgt_xram);	
+
+	///////////////////////////////////////////////////////
+	// Rï¿œseau vers la XRAM
+	///////////////////////////////////////////////////////
+
+	vgmn.p_clk(signal_clk);
+	vgmn.p_resetn(signal_resetn);
+
+	vgmn.p_to_initiator[0](signal_vci_ixr_memc0);
+	vgmn.p_to_initiator[1](signal_vci_ixr_memc1);
+	vgmn.p_to_initiator[2](signal_vci_ixr_memc2);
+	vgmn.p_to_initiator[3](signal_vci_ixr_memc3);
+
+	vgmn.p_to_target[0](signal_vci_tgt_xram);
+
+	///////////////////////////////////////////////////////
+	// Rï¿œseau des commandes primaires
+	///////////////////////////////////////////////////////
+
+	clusterPN0.p_clk(signal_clk);
+	clusterPN0.p_resetn(signal_resetn);
+
+	clusterPN0.p_to_initiator[0](signal_vci_ini_proc0);
+	clusterPN0.p_to_initiator[1](signal_vci_ini_proc1);
+	clusterPN0.p_to_initiator[2](signal_vci_ini_proc2);
+	clusterPN0.p_to_initiator[3](signal_vci_ini_proc3);
+
+	clusterPN0.p_to_target[0](signal_vci_tgt_memc0);
+
+	clusterPN0.p_initiator_to_up(signal_vci_ini_pdspin0);
+	clusterPN0.p_target_to_up(signal_vci_tgt_pdspin0);
+
+	clusterPN1.p_clk(signal_clk);
+	clusterPN1.p_resetn(signal_resetn);
+
+	clusterPN1.p_to_initiator[0](signal_vci_ini_proc4);
+	clusterPN1.p_to_initiator[1](signal_vci_ini_proc5);
+	clusterPN1.p_to_initiator[2](signal_vci_ini_proc6);
+	clusterPN1.p_to_initiator[3](signal_vci_ini_proc7);
+
+	clusterPN1.p_to_target[0](signal_vci_tgt_memc1);
+
+	clusterPN1.p_initiator_to_up(signal_vci_ini_pdspin1);
+	clusterPN1.p_target_to_up(signal_vci_tgt_pdspin1);
+
+	clusterPN2.p_clk(signal_clk);
+	clusterPN2.p_resetn(signal_resetn);
+
+	clusterPN2.p_to_initiator[0](signal_vci_ini_proc8);
+	clusterPN2.p_to_initiator[1](signal_vci_ini_proc9);
+	clusterPN2.p_to_initiator[2](signal_vci_ini_proc10);
+	clusterPN2.p_to_initiator[3](signal_vci_ini_proc11);
+	
+
+	clusterPN2.p_to_target[0](signal_vci_tgt_memc2);
+	clusterPN2.p_to_target[1](signal_vci_tgt_rom);
+
+	clusterPN2.p_initiator_to_up(signal_vci_ini_pdspin2);
+	clusterPN2.p_target_to_up(signal_vci_tgt_pdspin2);
+
+	clusterPN3.p_clk(signal_clk);
+	clusterPN3.p_resetn(signal_resetn);
+
+	clusterPN3.p_to_initiator[0](signal_vci_ini_proc12);
+	clusterPN3.p_to_initiator[1](signal_vci_ini_proc13);
+	clusterPN3.p_to_initiator[2](signal_vci_ini_proc14);
+	clusterPN3.p_to_initiator[3](signal_vci_ini_proc15);
+
+	clusterPN3.p_to_target[0](signal_vci_tgt_memc3);
+	clusterPN3.p_to_target[1](signal_vci_tgt_tty);
+
+	clusterPN3.p_initiator_to_up(signal_vci_ini_pdspin3);
+	clusterPN3.p_target_to_up(signal_vci_tgt_pdspin3);
+
+
+	vciDspinPNetwork.p_clk(signal_clk);
+	vciDspinPNetwork.p_resetn(signal_resetn);
+
+	vciDspinPNetwork.p_to_initiator[0][0](signal_vci_ini_pdspin0);
+	vciDspinPNetwork.p_to_initiator[0][1](signal_vci_ini_pdspin1);
+	vciDspinPNetwork.p_to_initiator[1][0](signal_vci_ini_pdspin2);
+	vciDspinPNetwork.p_to_initiator[1][1](signal_vci_ini_pdspin3);
+
+	vciDspinPNetwork.p_to_target[0][0](signal_vci_tgt_pdspin0);
+	vciDspinPNetwork.p_to_target[0][1](signal_vci_tgt_pdspin1);
+	vciDspinPNetwork.p_to_target[1][0](signal_vci_tgt_pdspin2);
+	vciDspinPNetwork.p_to_target[1][1](signal_vci_tgt_pdspin3);
+
+	///////////////////////////////////////////////////////
+	// Rï¿œseau des commandes de cohï¿œrence
+	///////////////////////////////////////////////////////
+	clusterCN0.p_clk(signal_clk);
+	clusterCN0.p_resetn(signal_resetn);
+
+	clusterCN0.p_to_initiator[0](signal_vci_ini_memc0);
+
+	clusterCN0.p_to_target[0](signal_vci_tgt_proc0);
+	clusterCN0.p_to_target[1](signal_vci_tgt_proc1);
+	clusterCN0.p_to_target[2](signal_vci_tgt_proc2);
+	clusterCN0.p_to_target[3](signal_vci_tgt_proc3);
+
+	clusterCN0.p_initiator_to_up(signal_vci_ini_cdspin0);
+	clusterCN0.p_target_to_up(signal_vci_tgt_cdspin0);
+
+	clusterCN1.p_clk(signal_clk);
+	clusterCN1.p_resetn(signal_resetn);
+
+	clusterCN1.p_to_initiator[0](signal_vci_ini_memc1);
+
+	clusterCN1.p_to_target[0](signal_vci_tgt_proc4);
+	clusterCN1.p_to_target[1](signal_vci_tgt_proc5);
+	clusterCN1.p_to_target[2](signal_vci_tgt_proc6);
+	clusterCN1.p_to_target[3](signal_vci_tgt_proc7);
+
+
+	clusterCN1.p_initiator_to_up(signal_vci_ini_cdspin1);
+	clusterCN1.p_target_to_up(signal_vci_tgt_cdspin1);
+
+	clusterCN2.p_clk(signal_clk);
+	clusterCN2.p_resetn(signal_resetn);
+
+	clusterCN2.p_to_initiator[0](signal_vci_ini_memc2);
+
+	clusterCN2.p_to_target[0](signal_vci_tgt_proc8);
+	clusterCN2.p_to_target[1](signal_vci_tgt_proc9);
+	clusterCN2.p_to_target[2](signal_vci_tgt_proc10);
+	clusterCN2.p_to_target[3](signal_vci_tgt_proc11);
+
+	clusterCN2.p_initiator_to_up(signal_vci_ini_cdspin2);
+	clusterCN2.p_target_to_up(signal_vci_tgt_cdspin2);
+
+	clusterCN3.p_clk(signal_clk);
+	clusterCN3.p_resetn(signal_resetn);
+
+	clusterCN3.p_to_initiator[0](signal_vci_ini_memc3);
+
+	clusterCN3.p_to_target[0](signal_vci_tgt_proc12);
+	clusterCN3.p_to_target[1](signal_vci_tgt_proc13);
+	clusterCN3.p_to_target[2](signal_vci_tgt_proc14);
+	clusterCN3.p_to_target[3](signal_vci_tgt_proc15);
+
+	clusterCN3.p_initiator_to_up(signal_vci_ini_cdspin3);
+	clusterCN3.p_target_to_up(signal_vci_tgt_cdspin3);
+
+	vciDspinCNetwork.p_clk(signal_clk);
+	vciDspinCNetwork.p_resetn(signal_resetn);
+
+	vciDspinCNetwork.p_to_initiator[0][0](signal_vci_ini_cdspin0);
+	vciDspinCNetwork.p_to_initiator[0][1](signal_vci_ini_cdspin1);
+	vciDspinCNetwork.p_to_initiator[1][0](signal_vci_ini_cdspin2);
+	vciDspinCNetwork.p_to_initiator[1][1](signal_vci_ini_cdspin3);
+
+	vciDspinCNetwork.p_to_target[0][0](signal_vci_tgt_cdspin0);
+	vciDspinCNetwork.p_to_target[0][1](signal_vci_tgt_cdspin1);
+	vciDspinCNetwork.p_to_target[1][0](signal_vci_tgt_cdspin2);
+	vciDspinCNetwork.p_to_target[1][1](signal_vci_tgt_cdspin3);
+
+
+	////////////////////////////////////////////////////////
+	////////////////////////////////////////////////////////
+
+	int ncycles;
+
+#ifndef SOCVIEW
+	if (argc == 2) {
+		ncycles = std::atoi(argv[1]);
+	} else {
+		std::cerr
+			<< std::endl
+			<< "The number of simulation cycles must "
+			   "be defined in the command line"
+			<< std::endl;
+		exit(1);
+	}
+
+	sc_start(sc_core::sc_time(0, SC_NS));
+	signal_resetn = false;
+
+	sc_start(sc_core::sc_time(1, SC_NS));
+	signal_resetn = true;
+
+	for (int i = 0; i < ncycles ; i+=100000) {
+		sc_start(sc_core::sc_time(100000, SC_NS));
+		memc0.print_stats();
+		proc0.print_stats();
+		proc1.print_stats();
+		proc2.print_stats();
+		proc3.print_stats();
+		memc1.print_stats();
+		proc4.print_stats();
+		proc5.print_stats();
+		proc6.print_stats();
+		proc7.print_stats();
+		memc2.print_stats();
+		proc8.print_stats();
+		proc9.print_stats();
+		proc10.print_stats();
+		proc11.print_stats();
+		memc3.print_stats();
+		proc12.print_stats();
+		proc13.print_stats();
+		proc14.print_stats();
+		proc15.print_stats();
+	}
+	return EXIT_SUCCESS;
+#else
+	ncycles = 1;
+	sc_start(sc_core::sc_time(0, SC_NS));
+	signal_resetn = false;
+	sc_start(sc_core::sc_time(1, SC_NS));
+	signal_resetn = true;
+
+	debug();
+	return EXIT_SUCCESS;
+#endif
+}
+
+int sc_main (int argc, char *argv[])
+{
+	try {
+		return _main(argc, argv);
+	} catch (std::exception &e) {
+		std::cout << e.what() << std::endl;
+	} catch (...) {
+		std::cout << "Unknown exception occured" << std::endl;
+		throw;
+	}
+	return 1;
+}
Index: branches/v4/platforms/caba-vdspin-vci_synthetic_initiator/Makefile
===================================================================
--- branches/v4/platforms/caba-vdspin-vci_synthetic_initiator/Makefile	(revision 371)
+++ branches/v4/platforms/caba-vdspin-vci_synthetic_initiator/Makefile	(revision 371)
@@ -0,0 +1,8 @@
+ARCH=mips32el
+SIMULATION_ARGS=100000
+#SOCLIB_CC_ADD_ARGS=-t systemcass -I.
+SOCLIB_CC_ADD_ARGS=-I.
+SOCLIB?=$(shell soclib-cc --getpath)
+export SOCLIB
+NO_SOFT=1
+include $(SOCLIB)/soclib/platform/topcells/all.mk
Index: branches/v4/platforms/caba-vdspin-vci_synthetic_initiator/platform_desc
===================================================================
--- branches/v4/platforms/caba-vdspin-vci_synthetic_initiator/platform_desc	(revision 371)
+++ branches/v4/platforms/caba-vdspin-vci_synthetic_initiator/platform_desc	(revision 371)
@@ -0,0 +1,27 @@
+# -*- python -*-
+
+
+todo = Platform('caba', 'top.cpp',
+		uses = [
+		  Uses('caba:vci_synthetic_initiator'),
+		  Uses('caba:vci_local_ring_fast',
+		       ring_cmd_data_size = 40,
+		       ring_rsp_data_size = 33,
+		  ),
+		  Uses('caba:vci_synthetic_target'),
+		  Uses('caba:virtual_dspin_router', flit_width = 40),
+		  Uses('caba:virtual_dspin_router', flit_width = 33),
+		  Uses('common:loader'),
+	        ],
+		  cell_size = 4,
+		  plen_size = 8,
+		  addr_size = 32,
+		  rerror_size = 1,
+		  clen_size = 1,
+		  rflag_size = 1,
+		  srcid_size = 11,
+		  pktid_size = 4,
+		  trdid_size = 4,
+		  wrplen_size = 1
+	       )
+
Index: branches/v4/platforms/caba-vdspin-vci_synthetic_initiator/top.cpp
===================================================================
--- branches/v4/platforms/caba-vdspin-vci_synthetic_initiator/top.cpp	(revision 371)
+++ branches/v4/platforms/caba-vdspin-vci_synthetic_initiator/top.cpp	(revision 371)
@@ -0,0 +1,573 @@
+
+#include <stdint.h>
+#include <systemc>
+#include <sys/time.h>
+#include <iostream>
+#include <cstdlib>
+#include <cstdarg>
+
+#include "arithmetics.h"
+#include "mapping_table.h"
+#include "alloc_elems.h"
+#include "vci_synthetic_target.h"
+#include "vci_local_ring_fast.h"
+#include "virtual_dspin_router.h"
+#include "vci_synthetic_initiator.h"
+
+// MESH SIZE
+#define X_MAX           2
+#define Y_MAX           2
+#define N_CLUSTERS      X_MAX*Y_MAX
+// FLIT_WIDTH
+#define WIDTH_CMD	40
+#define WIDTH_RSP	33
+// Face of each DSPIN Router
+#define NORTH		0
+#define SOUTH		1
+#define EAST		2
+#define WEST		3
+#define LOCAL		4
+// VCI parameters
+#define cell_width      4
+#define plen_width      8
+#define address_width   32
+#define error_width     1
+#define clen_width      1
+#define rflag_width     1
+#define srcid_width     11
+#define pktid_width     4
+#define trdid_width     4
+#define wrplen_width    1
+// Adress of targets
+#define TARGET_ADDR	0x00000000
+#define TARGET_SIZE	0x400
+// FIFO depth in the gateways
+#define DEPTH		4
+// LENGTH of packets
+#define PACKET_LENGTH	2
+// FIFO depth in the routers
+#define DSPIN_FIFO      4
+// DEBUG MODE : 0 OFF, 1 only the initiators and the targets, 2 only network
+#define DEBUG		0
+// LOAD wanted
+#define LOAD		450
+
+#define STAGE		0
+
+int _main(int argc, char *argv[])
+{
+	using namespace sc_core;
+	// Avoid repeating these everywhere
+	using soclib::common::IntTab;
+	using soclib::common::Segment;
+
+	using soclib::common::uint32_log2;
+
+	int ncycles;
+	uint32_t rho_a;
+	uint32_t rho_b;
+
+	if(argc == 4){
+	  ncycles = std::atoi(argv[1]);
+	  rho_a = std::atoi(argv[2]);
+	  rho_b = std::atoi(argv[3]);
+	} else {
+	  std::cout << "Usage : simulation_cycles packet_rate broadcast_period" << std::endl;
+	  exit(1);
+	}
+	// Define VCI parameters
+	typedef soclib::caba::VciParams<cell_width,
+					plen_width,
+					address_width,
+					error_width,
+					clen_width,
+					rflag_width,
+					srcid_width,
+					pktid_width,
+					trdid_width,
+					wrplen_width> vci_param;
+
+	// Mapping table primary network
+	soclib::common::MappingTable maptab0(address_width, IntTab(soclib::common::uint32_log2(X_MAX)+soclib::common::uint32_log2(Y_MAX) ,srcid_width-soclib::common::uint32_log2(X_MAX)-soclib::common::uint32_log2(Y_MAX)),
+							    IntTab(soclib::common::uint32_log2(X_MAX)+soclib::common::uint32_log2(Y_MAX) ,srcid_width-soclib::common::uint32_log2(X_MAX)-soclib::common::uint32_log2(Y_MAX)), 0xFFC0000);
+	soclib::common::MappingTable maptab1(address_width, IntTab(soclib::common::uint32_log2(X_MAX)+soclib::common::uint32_log2(Y_MAX) ,srcid_width-soclib::common::uint32_log2(X_MAX)-soclib::common::uint32_log2(Y_MAX)),
+							    IntTab(soclib::common::uint32_log2(X_MAX)+soclib::common::uint32_log2(Y_MAX) ,srcid_width-soclib::common::uint32_log2(X_MAX)-soclib::common::uint32_log2(Y_MAX)), 0xFFC0000);
+	for(int i = 0 ; i < Y_MAX ; i++){
+		for(int j = 0 ; j < X_MAX ; j++){
+			std::ostringstream	str0;
+			std::ostringstream	str1;
+			str0 << "Target_c0_" << (i*Y_MAX+j) ;
+			str1 << "Target_c1_" << (i*Y_MAX+j) ;
+			maptab0.add(Segment(str0.str(), TARGET_ADDR + ((i*Y_MAX+j) << (address_width-soclib::common::uint32_log2(X_MAX)-soclib::common::uint32_log2(Y_MAX))), TARGET_SIZE, IntTab((i*X_MAX+j),0), false));
+			maptab1.add(Segment(str1.str(), TARGET_ADDR + ((i*Y_MAX+j) << (address_width-soclib::common::uint32_log2(X_MAX)-soclib::common::uint32_log2(Y_MAX))), TARGET_SIZE, IntTab((i*X_MAX+j),0), false));
+		}
+	}
+
+
+	sc_clock	signal_clk("clk");
+	sc_signal<bool> signal_resetn("resetn");
+   
+	soclib::caba::VciSignals<vci_param> ** signal_vci_ini_synth_c0 = soclib::common::alloc_elems<soclib::caba::VciSignals<vci_param> >("signal_vci_ini_synth_c0", 2, N_CLUSTERS);
+	soclib::caba::VciSignals<vci_param> ** signal_vci_ini_synth_c1 = soclib::common::alloc_elems<soclib::caba::VciSignals<vci_param> >("signal_vci_ini_synth_c1", 2, N_CLUSTERS);
+	///////////////////////////////////////////////////////////////
+	// VDSPIN Signals : one level for in and out, one level for X length in the mesh, 
+	//                  one level for Y length in the mesh, last level for each port of the router
+	///////////////////////////////////////////////////////////////
+	soclib::caba::DspinSignals<WIDTH_CMD> **** dspin_signals_cmd_c0 = soclib::common::alloc_elems<soclib::caba::DspinSignals<WIDTH_CMD> >("Dspin_cmd_signals_channel_0", 2, X_MAX, Y_MAX, 5 );
+	soclib::caba::DspinSignals<WIDTH_CMD> **** dspin_signals_cmd_c1 = soclib::common::alloc_elems<soclib::caba::DspinSignals<WIDTH_CMD> >("Dspin_cmd_signals_channel_1", 2, X_MAX, Y_MAX, 5 );
+	soclib::caba::DspinSignals<WIDTH_RSP> **** dspin_signals_rsp_c0 = soclib::common::alloc_elems<soclib::caba::DspinSignals<WIDTH_RSP> >("Dspin_rsp_signals_channel_0", 2, X_MAX, Y_MAX, 5 );
+	soclib::caba::DspinSignals<WIDTH_RSP> **** dspin_signals_rsp_c1 = soclib::common::alloc_elems<soclib::caba::DspinSignals<WIDTH_RSP> >("Dspin_rsp_signals_channel_2", 2, X_MAX, Y_MAX, 5 );
+
+
+	// N_CLUSTERS ring.
+	soclib::caba::VciLocalRingFast<vci_param, WIDTH_CMD, WIDTH_RSP> * local_ring_c0 = (soclib::caba::VciLocalRingFast<vci_param, WIDTH_CMD, WIDTH_RSP> *) malloc(sizeof(soclib::caba::VciLocalRingFast<vci_param, WIDTH_CMD, WIDTH_RSP> ) * N_CLUSTERS) ;
+	soclib::caba::VciLocalRingFast<vci_param, WIDTH_CMD, WIDTH_RSP> * local_ring_c1 = (soclib::caba::VciLocalRingFast<vci_param, WIDTH_CMD, WIDTH_RSP> *) malloc(sizeof(soclib::caba::VciLocalRingFast<vci_param, WIDTH_CMD, WIDTH_RSP> ) * N_CLUSTERS) ;
+	for(int i = 0 ; i < N_CLUSTERS ; i++){                                                            // ringid, fifo, fifo, nb_init, nb_tgt
+		std::ostringstream	str0;
+		std::ostringstream	str1;
+		str0 << "cluster_c0_" << i ;
+		str1 << "cluster_c1_" << i ;
+		new(&local_ring_c0[i]) soclib::caba::VciLocalRingFast<vci_param, WIDTH_CMD, WIDTH_RSP> (str0.str().c_str(),
+													maptab0, 
+													IntTab(i), 
+													2, 
+													DEPTH, 
+													1, 
+													1);
+		new(&local_ring_c1[i]) soclib::caba::VciLocalRingFast<vci_param, WIDTH_CMD, WIDTH_RSP> (str1.str().c_str(), 
+													maptab1, 
+													IntTab(i), 
+													2, 
+													DEPTH,
+													1,
+													1);
+	}
+
+	// Virtual dspin routers
+	soclib::caba::VirtualDspinRouter<WIDTH_CMD> ** routers_cmd = (soclib::caba::VirtualDspinRouter<WIDTH_CMD> **) malloc(sizeof(soclib::caba::VirtualDspinRouter<WIDTH_CMD> *) * X_MAX);
+	soclib::caba::VirtualDspinRouter<WIDTH_RSP> ** routers_rsp = (soclib::caba::VirtualDspinRouter<WIDTH_RSP> **) malloc(sizeof(soclib::caba::VirtualDspinRouter<WIDTH_RSP> *) * X_MAX);
+
+	for(int i = 0; i < X_MAX; i++ ){
+	  routers_cmd[i] = (soclib::caba::VirtualDspinRouter<WIDTH_CMD> * ) malloc(sizeof(soclib::caba::VirtualDspinRouter<WIDTH_CMD>) * Y_MAX);
+	  routers_rsp[i] = (soclib::caba::VirtualDspinRouter<WIDTH_RSP> * ) malloc(sizeof(soclib::caba::VirtualDspinRouter<WIDTH_RSP>) * Y_MAX);
+	  for(int j = 0; j < Y_MAX; j++){
+		  std::ostringstream	str0;
+		  std::ostringstream	str1;
+		  str0 << "VDspinRouterCMD" << i << j;
+		  str1 << "VDspinRouterRSP" << i << j;
+		  new(&routers_cmd[i][j]) soclib::caba::VirtualDspinRouter<WIDTH_CMD> (str0.str().c_str(), i, j, soclib::common::uint32_log2(X_MAX), soclib::common::uint32_log2(Y_MAX), DSPIN_FIFO, DSPIN_FIFO);
+		  new(&routers_rsp[i][j]) soclib::caba::VirtualDspinRouter<WIDTH_RSP> (str1.str().c_str(), i, j, soclib::common::uint32_log2(X_MAX), soclib::common::uint32_log2(Y_MAX), DSPIN_FIFO, DSPIN_FIFO);
+	  }
+	}
+
+
+	///////////////////////////////////////////////////////////////
+	// Components
+	///////////////////////////////////////////////////////////////
+
+	// N_CLUSTERS VCI Synthetic Initiator (1 initiator per cluster/network)
+	soclib::caba::VciSyntheticInitiator<vci_param> * initiator_c0 = (soclib::caba::VciSyntheticInitiator<vci_param> *) malloc(sizeof(soclib::caba::VciSyntheticInitiator<vci_param> )* N_CLUSTERS);
+	soclib::caba::VciSyntheticInitiator<vci_param> * initiator_c1 = (soclib::caba::VciSyntheticInitiator<vci_param> *) malloc(sizeof(soclib::caba::VciSyntheticInitiator<vci_param> )* N_CLUSTERS);
+	for(int i = 0 ; i < X_MAX; i++)
+		for(int j = 0 ; j < Y_MAX ; j++){
+			std::ostringstream	str0;
+			std::ostringstream	str1;
+			str0 << "Initiator_c0_" << i << "_" << j ;
+			str1 << "Initiator_c1_" << i << "_" << j ;
+			new(&initiator_c0[Y_MAX*i+j]) soclib::caba::VciSyntheticInitiator<vci_param> (str0.str().c_str() , maptab0, IntTab((i*Y_MAX+j) ,0), PACKET_LENGTH, 0, 100, X_MAX, Y_MAX); 
+#if STAGE==1
+			if( (i + 1 == X_MAX) && (j + 1 == Y_MAX ) )
+#endif
+			    new(&initiator_c1[Y_MAX*i+j]) soclib::caba::VciSyntheticInitiator<vci_param> (str1.str().c_str() , maptab1, IntTab((i*Y_MAX+j) ,0), PACKET_LENGTH, rho_a, 100, X_MAX, Y_MAX, rho_b, 0, X_MAX, 0, Y_MAX); 
+
+#if STAGE==1
+			else
+			    new(&initiator_c1[Y_MAX*i+j]) soclib::caba::VciSyntheticInitiator<vci_param> (str1.str().c_str() , maptab1, IntTab((i*Y_MAX+j) ,0), PACKET_LENGTH, rho_a, 100, X_MAX, Y_MAX, 0, 0, X_MAX, 0, Y_MAX); 
+#endif
+		}
+
+	soclib::caba::VciSyntheticTarget<vci_param> * target_c0 = (soclib::caba::VciSyntheticTarget<vci_param> *) malloc(sizeof(soclib::caba::VciSyntheticTarget<vci_param>) * N_CLUSTERS);
+	soclib::caba::VciSyntheticTarget<vci_param> * target_c1 = (soclib::caba::VciSyntheticTarget<vci_param> *) malloc(sizeof(soclib::caba::VciSyntheticTarget<vci_param>) * N_CLUSTERS);
+	for(int i = 0 ; i < X_MAX ; i++)
+		for(int j = 0 ; j < Y_MAX ; j++){
+			std::ostringstream	str0;
+			std::ostringstream	str1;
+			str0 << "Ram_c0_" << (i*Y_MAX+j) ;
+			str1 << "Ram_c1_" << (i*Y_MAX+j) ;
+			new(&target_c0[Y_MAX*i+j]) soclib::caba::VciSyntheticTarget<vci_param> (str0.str().c_str() , IntTab(i*Y_MAX+j,0), maptab0, soclib::common::Loader(), 0);
+			new(&target_c1[Y_MAX*i+j]) soclib::caba::VciSyntheticTarget<vci_param> (str1.str().c_str() , IntTab(i*Y_MAX+j,0), maptab1, soclib::common::Loader(), 0);
+		}
+
+	///////////////////////////////////////////////////////////////
+	// Connection of Synthetic Initiator to each local ring per cluster
+	///////////////////////////////////////////////////////////////
+	for(int i = 0 ; i < N_CLUSTERS ; i++){
+	  local_ring_c0[i].p_clk(signal_clk);
+	  local_ring_c0[i].p_resetn(signal_resetn);
+	  local_ring_c0[i].p_to_initiator[0](signal_vci_ini_synth_c0[0][i]);
+	  local_ring_c0[i].p_to_target[0](signal_vci_ini_synth_c0[1][i]);
+	  initiator_c0[i].p_clk(signal_clk);
+	  initiator_c0[i].p_resetn(signal_resetn);
+	  initiator_c0[i].p_vci(signal_vci_ini_synth_c0[0][i]);
+	  target_c0[i].p_clk(signal_clk);
+	  target_c0[i].p_resetn(signal_resetn);
+	  target_c0[i].p_vci(signal_vci_ini_synth_c0[1][i]);
+	  local_ring_c1[i].p_clk(signal_clk);
+	  local_ring_c1[i].p_resetn(signal_resetn);
+	  local_ring_c1[i].p_to_initiator[0](signal_vci_ini_synth_c1[0][i]);
+	  local_ring_c1[i].p_to_target[0](signal_vci_ini_synth_c1[1][i]);
+	  initiator_c1[i].p_clk(signal_clk);
+	  initiator_c1[i].p_resetn(signal_resetn);
+	  initiator_c1[i].p_vci(signal_vci_ini_synth_c1[0][i]);
+	  target_c1[i].p_clk(signal_clk);
+	  target_c1[i].p_resetn(signal_resetn);
+	  target_c1[i].p_vci(signal_vci_ini_synth_c1[1][i]);
+	}
+	
+	///////////////////////////////////////////////////////////////
+	// Connection of each VDspin Router to each local ring and 
+	// neighbors VDspin Router
+	///////////////////////////////////////////////////////////////
+	for(int i = 0; i < X_MAX ; i++){
+	  for(int j = 0; j < Y_MAX ; j++){
+	    routers_cmd[i][j].p_clk(signal_clk);
+	    routers_cmd[i][j].p_resetn(signal_resetn);
+	    routers_rsp[i][j].p_clk(signal_clk);
+	    routers_rsp[i][j].p_resetn(signal_resetn);
+	    local_ring_c0[i*Y_MAX+j].p_gate_cmd_in( dspin_signals_cmd_c0[0][i][j][LOCAL]);
+	    local_ring_c1[i*Y_MAX+j].p_gate_cmd_in( dspin_signals_cmd_c1[0][i][j][LOCAL]);
+	    local_ring_c0[i*Y_MAX+j].p_gate_cmd_out(dspin_signals_cmd_c0[1][i][j][LOCAL]);
+	    local_ring_c1[i*Y_MAX+j].p_gate_cmd_out(dspin_signals_cmd_c1[1][i][j][LOCAL]);
+	    local_ring_c0[i*Y_MAX+j].p_gate_rsp_in( dspin_signals_rsp_c0[0][i][j][LOCAL]);
+	    local_ring_c1[i*Y_MAX+j].p_gate_rsp_in( dspin_signals_rsp_c1[0][i][j][LOCAL]);
+	    local_ring_c0[i*Y_MAX+j].p_gate_rsp_out(dspin_signals_rsp_c0[1][i][j][LOCAL]);
+	    local_ring_c1[i*Y_MAX+j].p_gate_rsp_out(dspin_signals_rsp_c1[1][i][j][LOCAL]);
+	    for(int k = 0; k < 5; k++){
+	     	if(j == 0){
+	     	  if(i == 0){
+	     	    routers_cmd[i][j].p_out[0][k](dspin_signals_cmd_c0[0][i][j][k]);
+	     	    routers_cmd[i][j].p_out[1][k](dspin_signals_cmd_c1[0][i][j][k]);
+	     	    routers_cmd[i][j].p_in[0][k](dspin_signals_cmd_c0[1][i][j][k]);
+	     	    routers_cmd[i][j].p_in[1][k](dspin_signals_cmd_c1[1][i][j][k]);
+	     	    routers_rsp[i][j].p_out[0][k](dspin_signals_rsp_c0[0][i][j][k]);
+	     	    routers_rsp[i][j].p_out[1][k](dspin_signals_rsp_c1[0][i][j][k]);
+	     	    routers_rsp[i][j].p_in[0][k](dspin_signals_rsp_c0[1][i][j][k]);
+	     	    routers_rsp[i][j].p_in[1][k](dspin_signals_rsp_c1[1][i][j][k]);
+	     	  } else {
+	     	    if(k == WEST){
+	     	   	routers_cmd[i][j].p_out[0][k](dspin_signals_cmd_c0[1][i-1][j][EAST]);
+	     	   	routers_cmd[i][j].p_out[1][k](dspin_signals_cmd_c1[1][i-1][j][EAST]);
+	     	   	routers_cmd[i][j].p_in[0][k](dspin_signals_cmd_c0[0][i-1][j][EAST]);
+	     	   	routers_cmd[i][j].p_in[1][k](dspin_signals_cmd_c1[0][i-1][j][EAST]);
+	     	   	routers_rsp[i][j].p_out[0][k](dspin_signals_rsp_c0[1][i-1][j][EAST]);
+	     	   	routers_rsp[i][j].p_out[1][k](dspin_signals_rsp_c1[1][i-1][j][EAST]);
+	     	   	routers_rsp[i][j].p_in[0][k](dspin_signals_rsp_c0[0][i-1][j][EAST]);
+	     	   	routers_rsp[i][j].p_in[1][k](dspin_signals_rsp_c1[0][i-1][j][EAST]);
+	     	    } else {
+	     	   	routers_cmd[i][j].p_out[0][k](dspin_signals_cmd_c0[0][i][j][k]);
+	     	   	routers_cmd[i][j].p_out[1][k](dspin_signals_cmd_c1[0][i][j][k]);
+	     	   	routers_cmd[i][j].p_in[0][k](dspin_signals_cmd_c0[1][i][j][k]);
+	     	   	routers_cmd[i][j].p_in[1][k](dspin_signals_cmd_c1[1][i][j][k]);
+	     	   	routers_rsp[i][j].p_out[0][k](dspin_signals_rsp_c0[0][i][j][k]);
+	     	   	routers_rsp[i][j].p_out[1][k](dspin_signals_rsp_c1[0][i][j][k]);
+	     	   	routers_rsp[i][j].p_in[0][k](dspin_signals_rsp_c0[1][i][j][k]);
+	     	   	routers_rsp[i][j].p_in[1][k](dspin_signals_rsp_c1[1][i][j][k]);
+	     	    }
+	     	  }
+	     	} else {
+	     	  if(k == SOUTH){
+	     	   	routers_cmd[i][j].p_out[0][k](dspin_signals_cmd_c0[1][i][j-1][NORTH]);
+	     	   	routers_cmd[i][j].p_out[1][k](dspin_signals_cmd_c1[1][i][j-1][NORTH]);
+	     	   	routers_cmd[i][j].p_in[0][k](dspin_signals_cmd_c0[0][i][j-1][NORTH]);
+	     	   	routers_cmd[i][j].p_in[1][k](dspin_signals_cmd_c1[0][i][j-1][NORTH]);
+	     	   	routers_rsp[i][j].p_out[0][k](dspin_signals_rsp_c0[1][i][j-1][NORTH]);
+	     	   	routers_rsp[i][j].p_out[1][k](dspin_signals_rsp_c1[1][i][j-1][NORTH]);
+	     	   	routers_rsp[i][j].p_in[0][k](dspin_signals_rsp_c0[0][i][j-1][NORTH]);
+	     	   	routers_rsp[i][j].p_in[1][k](dspin_signals_rsp_c1[0][i][j-1][NORTH]);
+	     	  } else if(k == WEST){
+	     	     if(i == 0){
+	     	   	routers_cmd[i][j].p_out[0][k](dspin_signals_cmd_c0[0][i][j][k]);
+	     	   	routers_cmd[i][j].p_out[1][k](dspin_signals_cmd_c1[0][i][j][k]);
+	     	   	routers_cmd[i][j].p_in[0][k](dspin_signals_cmd_c0[1][i][j][k]);
+	     	   	routers_cmd[i][j].p_in[1][k](dspin_signals_cmd_c1[1][i][j][k]);
+	     	   	routers_rsp[i][j].p_out[0][k](dspin_signals_rsp_c0[0][i][j][k]);
+	     	   	routers_rsp[i][j].p_out[1][k](dspin_signals_rsp_c1[0][i][j][k]);
+	     	   	routers_rsp[i][j].p_in[0][k](dspin_signals_rsp_c0[1][i][j][k]);
+	     	   	routers_rsp[i][j].p_in[1][k](dspin_signals_rsp_c1[1][i][j][k]);
+	     	     } else {
+	     	   	routers_cmd[i][j].p_out[0][k](dspin_signals_cmd_c0[1][i-1][j][EAST]);
+	     	   	routers_cmd[i][j].p_out[1][k](dspin_signals_cmd_c1[1][i-1][j][EAST]);
+	     	   	routers_cmd[i][j].p_in[0][k](dspin_signals_cmd_c0[0][i-1][j][EAST]);
+	     	   	routers_cmd[i][j].p_in[1][k](dspin_signals_cmd_c1[0][i-1][j][EAST]);
+	     	   	routers_rsp[i][j].p_out[0][k](dspin_signals_rsp_c0[1][i-1][j][EAST]);
+	     	   	routers_rsp[i][j].p_out[1][k](dspin_signals_rsp_c1[1][i-1][j][EAST]);
+	     	   	routers_rsp[i][j].p_in[0][k](dspin_signals_rsp_c0[0][i-1][j][EAST]);
+	     	   	routers_rsp[i][j].p_in[1][k](dspin_signals_rsp_c1[0][i-1][j][EAST]);
+	     	     }
+	     	  } else {
+	     	   	routers_cmd[i][j].p_out[0][k](dspin_signals_cmd_c0[0][i][j][k]);
+	     	   	routers_cmd[i][j].p_out[1][k](dspin_signals_cmd_c1[0][i][j][k]);
+	     	   	routers_cmd[i][j].p_in[0][k](dspin_signals_cmd_c0[1][i][j][k]);
+	     	   	routers_cmd[i][j].p_in[1][k](dspin_signals_cmd_c1[1][i][j][k]);
+	     	   	routers_rsp[i][j].p_out[0][k](dspin_signals_rsp_c0[0][i][j][k]);
+	     	   	routers_rsp[i][j].p_out[1][k](dspin_signals_rsp_c1[0][i][j][k]);
+	     	   	routers_rsp[i][j].p_in[0][k](dspin_signals_rsp_c0[1][i][j][k]);
+	     	   	routers_rsp[i][j].p_in[1][k](dspin_signals_rsp_c1[1][i][j][k]);
+	     	  }
+	     	}
+	    }
+	  }
+	}
+
+	////////////////////////////////////////////////
+	//             Simulation Loop                //
+	////////////////////////////////////////////////
+
+
+	sc_start(sc_core::sc_time(0, SC_NS));
+	signal_resetn = false;
+
+	for(int i = 0; i < X_MAX ; i++){
+		for(int j = 0; j < Y_MAX ; j++){
+			if(j == 0){
+			  	dspin_signals_cmd_c0[0][i][j][SOUTH].read = true   ;
+			  	dspin_signals_cmd_c0[1][i][j][SOUTH].write = false ;
+			  	dspin_signals_cmd_c1[0][i][j][SOUTH].read = true   ;
+			  	dspin_signals_cmd_c1[1][i][j][SOUTH].write = false ;
+			  	dspin_signals_rsp_c0[0][i][j][SOUTH].read = true   ;
+			  	dspin_signals_rsp_c0[1][i][j][SOUTH].write = false ;
+			  	dspin_signals_rsp_c1[0][i][j][SOUTH].read = true   ;
+			  	dspin_signals_rsp_c1[1][i][j][SOUTH].write = false ;
+			} 
+			if(j == Y_MAX-1){
+			  	dspin_signals_cmd_c0[0][i][j][NORTH].read = true   ;
+			  	dspin_signals_cmd_c0[1][i][j][NORTH].write = false ;
+			  	dspin_signals_cmd_c1[0][i][j][NORTH].read = true   ;
+			  	dspin_signals_cmd_c1[1][i][j][NORTH].write = false ;
+			  	dspin_signals_rsp_c0[0][i][j][NORTH].read = true   ;
+			  	dspin_signals_rsp_c0[1][i][j][NORTH].write = false ;
+			  	dspin_signals_rsp_c1[0][i][j][NORTH].read = true   ;
+			  	dspin_signals_rsp_c1[1][i][j][NORTH].write = false ;
+			} 
+			if(i == 0){
+				dspin_signals_cmd_c0[0][i][j][WEST].read = true   ;
+				dspin_signals_cmd_c0[1][i][j][WEST].write = false ;
+				dspin_signals_cmd_c1[0][i][j][WEST].read = true   ;
+				dspin_signals_cmd_c1[1][i][j][WEST].write = false ;
+				dspin_signals_rsp_c0[0][i][j][WEST].read = true   ;
+				dspin_signals_rsp_c0[1][i][j][WEST].write = false ;
+				dspin_signals_rsp_c1[0][i][j][WEST].read = true   ;
+				dspin_signals_rsp_c1[1][i][j][WEST].write = false ;
+			} 
+			if(i == X_MAX-1){
+				dspin_signals_cmd_c0[0][i][j][EAST].read = true   ;
+				dspin_signals_cmd_c0[1][i][j][EAST].write = false ;
+				dspin_signals_cmd_c1[0][i][j][EAST].read = true   ;
+				dspin_signals_cmd_c1[1][i][j][EAST].write = false ;
+				dspin_signals_rsp_c0[0][i][j][EAST].read = true   ;
+				dspin_signals_rsp_c0[1][i][j][EAST].write = false ;
+				dspin_signals_rsp_c1[0][i][j][EAST].read = true   ;
+				dspin_signals_rsp_c1[1][i][j][EAST].write = false ;
+			}
+		}
+	} 
+
+	sc_start(sc_core::sc_time(1, SC_NS));
+	signal_resetn = true;
+
+	for(int t = 0; t < ncycles; t++){
+		sc_start(sc_time(1, SC_NS));
+		//initiator_c1[4].print_trace();
+		//local_ring_c1[4].print_trace();
+		//target_c1[4].print_trace();
+#if defined(DEBUG) 
+		for(int i = 0 ; i < Y_MAX ; i++){
+			for(int j = 0 ; j < X_MAX ; j++){
+#endif
+#if DEBUG==1
+				//initiator_c0[i*Y_MAX+j].print_trace();
+				//std::cout << std::hex;
+				//std::cout << "synt_cmdval  = " << signal_vci_ini_synth_c0[0][i*Y_MAX+j].cmdval.read() << std::endl;
+				//std::cout << "synt_cmdack  = " << signal_vci_ini_synth_c0[0][i*Y_MAX+j].cmdack.read() << std::endl;
+				//std::cout << "synt_address = " << signal_vci_ini_synth_c0[0][i*Y_MAX+j].address.read() << std::endl;
+				//std::cout << "synt_cmd     = " << signal_vci_ini_synth_c0[0][i*Y_MAX+j].cmd.read() << std::endl;
+				//std::cout << "synt_srcid   = " << signal_vci_ini_synth_c0[0][i*Y_MAX+j].srcid.read() << std::endl;
+				//std::cout << "synt_trdid   = " << signal_vci_ini_synth_c0[0][i*Y_MAX+j].trdid.read() << std::endl;
+				//std::cout << "synt_plen    = " << signal_vci_ini_synth_c0[0][i*Y_MAX+j].plen.read() << std::endl;
+				//std::cout << "synt_eop     = " << signal_vci_ini_synth_c0[0][i*Y_MAX+j].eop.read() << std::endl;
+				//std::cout << "synt_rspval  = " << signal_vci_ini_synth_c0[0][i*Y_MAX+j].rspval.read() << std::endl;
+				//std::cout << "synt_rspack  = " << signal_vci_ini_synth_c0[0][i*Y_MAX+j].rspack.read() << std::endl;
+				//std::cout << "synt_rsrcid  = " << signal_vci_ini_synth_c0[0][i*Y_MAX+j].rsrcid.read() << std::endl;
+				//std::cout << "synt_rtrdid  = " << signal_vci_ini_synth_c0[0][i*Y_MAX+j].rtrdid.read() << std::endl;
+				//std::cout << "synt_rpktid  = " << signal_vci_ini_synth_c1[0][i*Y_MAX+j].rpktid.read() << std::endl;
+				//std::cout << "synt_rerror  = " << signal_vci_ini_synth_c0[0][i*Y_MAX+j].rerror.read() << std::endl;
+				//std::cout << "synt_reop    = " << signal_vci_ini_synth_c0[0][i*Y_MAX+j].reop.read() << std::endl;
+				//target_c0[i*Y_MAX+j].print_trace();
+				//std::cout << std::hex;
+				//std::cout << "target_cmdval  = " << signal_vci_ini_synth_c0[1][i*Y_MAX+j].cmdval.read() << std::endl;
+				//std::cout << "target_address = " << signal_vci_ini_synth_c0[1][i*Y_MAX+j].address.read() << std::endl;
+				//std::cout << "target_cmd     = " << signal_vci_ini_synth_c0[1][i*Y_MAX+j].cmd.read() << std::endl;
+				//std::cout << "target_srcid   = " << signal_vci_ini_synth_c0[1][i*Y_MAX+j].srcid.read() << std::endl;
+				//std::cout << "target_trdid   = " << signal_vci_ini_synth_c0[1][i*Y_MAX+j].trdid.read() << std::endl;
+				//std::cout << "target_plen    = " << signal_vci_ini_synth_c0[1][i*Y_MAX+j].plen.read() << std::endl;
+				//std::cout << "target_eop     = " << signal_vci_ini_synth_c0[1][i*Y_MAX+j].eop.read() << std::endl;
+				//std::cout << "target_rspval  = " << signal_vci_ini_synth_c0[1][i*Y_MAX+j].rspval.read() << std::endl;
+				//std::cout << "target_rspack  = " << signal_vci_ini_synth_c0[1][i*Y_MAX+j].rspack.read() << std::endl;
+				//std::cout << "target_rsrcid  = " << signal_vci_ini_synth_c0[1][i*Y_MAX+j].rsrcid.read() << std::endl;
+				//std::cout << "target_rtrdid  = " << signal_vci_ini_synth_c0[1][i*Y_MAX+j].rtrdid.read() << std::endl;
+				//std::cout << "target_rerror  = " << signal_vci_ini_synth_c0[1][i*Y_MAX+j].rerror.read() << std::endl;
+				//std::cout << "target_reop    = " << signal_vci_ini_synth_c0[1][i*Y_MAX+j].reop.read() << std::endl;
+				//initiator_c1[i*Y_MAX+j].print_trace();
+				//std::cout << std::hex;
+				//std::cout << "synt_cmdval  = " << signal_vci_ini_synth_c1[0][i*Y_MAX+j].cmdval.read() << std::endl;
+				//std::cout << "synt_cmdack  = " << signal_vci_ini_synth_c1[0][i*Y_MAX+j].cmdack.read() << std::endl;
+				//std::cout << "synt_address = " << signal_vci_ini_synth_c1[0][i*Y_MAX+j].address.read() << std::endl;
+				//std::cout << "synt_cmd     = " << signal_vci_ini_synth_c1[0][i*Y_MAX+j].cmd.read() << std::endl;
+				//std::cout << "synt_srcid   = " << signal_vci_ini_synth_c1[0][i*Y_MAX+j].srcid.read() << std::endl;
+				//std::cout << "synt_trdid   = " << signal_vci_ini_synth_c1[0][i*Y_MAX+j].trdid.read() << std::endl;
+				//std::cout << "synt_pktid   = " << signal_vci_ini_synth_c1[0][i*Y_MAX+j].pktid.read() << std::endl;
+				//std::cout << "synt_plen    = " << signal_vci_ini_synth_c1[0][i*Y_MAX+j].plen.read() << std::endl;
+				//std::cout << "synt_eop     = " << signal_vci_ini_synth_c1[0][i*Y_MAX+j].eop.read() << std::endl;
+				//std::cout << "synt_rspval  = " << signal_vci_ini_synth_c1[0][i*Y_MAX+j].rspval.read() << std::endl;
+				//std::cout << "synt_rspack  = " << signal_vci_ini_synth_c1[0][i*Y_MAX+j].rspack.read() << std::endl;
+				//std::cout << "synt_rsrcid  = " << signal_vci_ini_synth_c1[0][i*Y_MAX+j].rsrcid.read() << std::endl;
+				//std::cout << "synt_rtrdid  = " << signal_vci_ini_synth_c1[0][i*Y_MAX+j].rtrdid.read() << std::endl;
+				//std::cout << "synt_rpktid  = " << signal_vci_ini_synth_c1[0][i*Y_MAX+j].rpktid.read() << std::endl;
+				//std::cout << "synt_rerror  = " << signal_vci_ini_synth_c1[0][i*Y_MAX+j].rerror.read() << std::endl;
+				//std::cout << "synt_reop    = " << signal_vci_ini_synth_c1[0][i*Y_MAX+j].reop.read() << std::endl;
+				target_c1[i*Y_MAX+j].print_trace();
+				std::cout << std::hex;
+				std::cout << "target_cmdval  = " << signal_vci_ini_synth_c1[1][i*Y_MAX+j].cmdval.read() << std::endl;
+				std::cout << "target_address = " << signal_vci_ini_synth_c1[1][i*Y_MAX+j].address.read() << std::endl;
+				std::cout << "target_cmd     = " << signal_vci_ini_synth_c1[1][i*Y_MAX+j].cmd.read() << std::endl;
+				std::cout << "target_srcid   = " << signal_vci_ini_synth_c1[1][i*Y_MAX+j].srcid.read() << std::endl;
+				std::cout << "target_trdid   = " << signal_vci_ini_synth_c1[1][i*Y_MAX+j].trdid.read() << std::endl;
+				std::cout << "target_pktid   = " << signal_vci_ini_synth_c1[1][i*Y_MAX+j].pktid.read() << std::endl;
+				std::cout << "target_plen    = " << signal_vci_ini_synth_c1[1][i*Y_MAX+j].plen.read() << std::endl;
+				std::cout << "target_eop     = " << signal_vci_ini_synth_c1[1][i*Y_MAX+j].eop.read() << std::endl;
+				std::cout << "target_rspval  = " << signal_vci_ini_synth_c1[1][i*Y_MAX+j].rspval.read() << std::endl;
+				std::cout << "target_rspack  = " << signal_vci_ini_synth_c1[1][i*Y_MAX+j].rspack.read() << std::endl;
+				std::cout << "target_rsrcid  = " << signal_vci_ini_synth_c1[1][i*Y_MAX+j].rsrcid.read() << std::endl;
+				std::cout << "target_rtrdid  = " << signal_vci_ini_synth_c1[1][i*Y_MAX+j].rtrdid.read() << std::endl;
+				std::cout << "target_rpktid  = " << signal_vci_ini_synth_c1[1][i*Y_MAX+j].rpktid.read() << std::endl;
+				std::cout << "target_rerror  = " << signal_vci_ini_synth_c1[1][i*Y_MAX+j].rerror.read() << std::endl;
+				std::cout << "target_reop    = " << signal_vci_ini_synth_c1[1][i*Y_MAX+j].reop.read() << std::endl;
+#endif
+#if DEBUG==2
+				local_ring_c0[i*Y_MAX+j].print_trace();
+				routers_cmd[i][j].print_trace(0);
+				std::cout << std::dec << t << " ns" << std::endl;
+				routers_rsp[i][j].print_trace(0);
+#endif
+#ifdef DEBUG
+			}
+		}
+#endif
+				//initiator_c1[4].print_trace();
+				//std::cout << std::hex;
+				//std::cout << "synt_cmdval  = " << signal_vci_ini_synth_c1[0][255].cmdval.read() << std::endl;
+				//std::cout << "synt_cmdack  = " << signal_vci_ini_synth_c1[0][255].cmdack.read() << std::endl;
+				//std::cout << "synt_address = " << signal_vci_ini_synth_c1[0][255].address.read() << std::endl;
+				//std::cout << "synt_cmd     = " << signal_vci_ini_synth_c1[0][255].cmd.read() << std::endl;
+				//std::cout << "synt_srcid   = " << signal_vci_ini_synth_c1[0][255].srcid.read() << std::endl;
+				//std::cout << "synt_trdid   = " << signal_vci_ini_synth_c1[0][255].trdid.read() << std::endl;
+				//std::cout << "synt_pktid   = " << signal_vci_ini_synth_c1[0][255].pktid.read() << std::endl;
+				//std::cout << "synt_plen    = " << signal_vci_ini_synth_c1[0][255].plen.read() << std::endl;
+				//std::cout << "synt_eop     = " << signal_vci_ini_synth_c1[0][255].eop.read() << std::endl;
+				//std::cout << "synt_rspval  = " << signal_vci_ini_synth_c1[0][255].rspval.read() << std::endl;
+				//std::cout << "synt_rspack  = " << signal_vci_ini_synth_c1[0][255].rspack.read() << std::endl;
+				//std::cout << "synt_rsrcid  = " << signal_vci_ini_synth_c1[0][255].rsrcid.read() << std::endl;
+				//std::cout << "synt_rtrdid  = " << signal_vci_ini_synth_c1[0][255].rtrdid.read() << std::endl;
+				//std::cout << "synt_rpktid  = " << signal_vci_ini_synth_c1[0][255].rpktid.read() << std::endl;
+				//std::cout << "synt_rerror  = " << signal_vci_ini_synth_c1[0][255].rerror.read() << std::endl;
+				//std::cout << "synt_reop    = " << signal_vci_ini_synth_c1[0][255].reop.read() << std::endl;
+				//target_c1[4].print_trace();
+				//std::cout << std::hex;
+				//std::cout << "target_cmdval  = " << signal_vci_ini_synth_c1[1][4].cmdval.read() << std::endl;
+				//std::cout << "target_address = " << signal_vci_ini_synth_c1[1][4].address.read() << std::endl;
+				//std::cout << "target_cmd     = " << signal_vci_ini_synth_c1[1][4].cmd.read() << std::endl;
+				//std::cout << "target_srcid   = " << signal_vci_ini_synth_c1[1][4].srcid.read() << std::endl;
+				//std::cout << "target_trdid   = " << signal_vci_ini_synth_c1[1][4].trdid.read() << std::endl;
+				//std::cout << "target_pktid   = " << signal_vci_ini_synth_c1[1][4].pktid.read() << std::endl;
+				//std::cout << "target_plen    = " << signal_vci_ini_synth_c1[1][4].plen.read() << std::endl;
+				//std::cout << "target_eop     = " << signal_vci_ini_synth_c1[1][4].eop.read() << std::endl;
+				//std::cout << "target_rspval  = " << signal_vci_ini_synth_c1[1][4].rspval.read() << std::endl;
+				//std::cout << "target_rspack  = " << signal_vci_ini_synth_c1[1][4].rspack.read() << std::endl;
+				//std::cout << "target_rsrcid  = " << signal_vci_ini_synth_c1[1][4].rsrcid.read() << std::endl;
+				//std::cout << "target_rtrdid  = " << signal_vci_ini_synth_c1[1][4].rtrdid.read() << std::endl;
+				//std::cout << "target_rpktid  = " << signal_vci_ini_synth_c1[1][4].rpktid.read() << std::endl;
+				//std::cout << "target_rerror  = " << signal_vci_ini_synth_c1[1][4].rerror.read() << std::endl;
+				//std::cout << "target_reop    = " << signal_vci_ini_synth_c1[1][4].reop.read() << std::endl;
+			
+			//for(int i = 0 ; i < Y_MAX ; i++){
+			//	for(int j = 0 ; j < X_MAX ; j++){
+			//		std::cout << std::dec << t << " cycles " << std::endl;
+			//		local_ring_c1[i*Y_MAX+j].print_trace();
+			//		//initiator_c1[i*Y_MAX+j].print_trace();
+			//	}
+			//}
+			//initiator_c1[4].print_trace();
+			//std::cout << std::hex;
+			//std::cout << "synt_cmdval  = " << signal_vci_ini_synth_c1[0][4].cmdval.read() << std::endl;
+			//std::cout << "synt_cmdack  = " << signal_vci_ini_synth_c1[0][4].cmdack.read() << std::endl;
+			//std::cout << "synt_address = " << signal_vci_ini_synth_c1[0][4].address.read() << std::endl;
+			//std::cout << "synt_cmd     = " << signal_vci_ini_synth_c1[0][4].cmd.read() << std::endl;
+			//std::cout << "synt_srcid   = " << signal_vci_ini_synth_c1[0][4].srcid.read() << std::endl;
+			//std::cout << "synt_trdid   = " << signal_vci_ini_synth_c1[0][4].trdid.read() << std::endl;
+			//std::cout << "synt_pktid   = " << signal_vci_ini_synth_c1[0][4].pktid.read() << std::endl;
+			//std::cout << "synt_plen    = " << signal_vci_ini_synth_c1[0][4].plen.read() << std::endl;
+			//std::cout << "synt_eop     = " << signal_vci_ini_synth_c1[0][4].eop.read() << std::endl;
+			//std::cout << "synt_rspval  = " << signal_vci_ini_synth_c1[0][4].rspval.read() << std::endl;
+			//std::cout << "synt_rspack  = " << signal_vci_ini_synth_c1[0][4].rspack.read() << std::endl;
+			//std::cout << "synt_rsrcid  = " << signal_vci_ini_synth_c1[0][4].rsrcid.read() << std::endl;
+			//std::cout << "synt_rtrdid  = " << signal_vci_ini_synth_c1[0][4].rtrdid.read() << std::endl;
+			//std::cout << "synt_rpktid  = " << signal_vci_ini_synth_c1[0][4].rpktid.read() << std::endl;
+			//std::cout << "synt_rerror  = " << signal_vci_ini_synth_c1[0][4].rerror.read() << std::endl;
+			//std::cout << "synt_reop    = " << signal_vci_ini_synth_c1[0][4].reop.read() << std::endl;
+			//local_ring_c1[4].print_trace();
+			//initiator_c1[27].print_fifo_state();
+			//if (!(t%1000000))
+			//	std::cout <<std::dec << t << " 1000000 cycles passed" << std::endl;
+
+
+	}
+
+	//double latency_c0 = 0;
+	double latency_c1 = 0;
+	double latency_bc = 0;
+	std::cout << "Results : " << std::endl;
+	for(int i = 0 ; i < Y_MAX ; i++){
+		for(int j = 0 ; j < X_MAX ; j++){
+			//initiator_c0[i*Y_MAX+j].printStats();
+			//latency_c0 += initiator_c0[i*Y_MAX+j].getLatencySingle() ;
+			initiator_c1[i*Y_MAX+j].printStats();
+			latency_c1 += initiator_c1[i*Y_MAX+j].getLatencySingle() ;
+			latency_bc += initiator_c1[i*Y_MAX+j].getLatencyBC();
+			std::cout << "bc latency " << latency_bc << std::endl;
+		}
+	}
+
+		
+	//std::cout << "Latency_c0 : " << latency_c0 << std::endl;
+	std::cout << "Latency_c1 : " << latency_c1 << std::endl;
+	std::cout << "BC latency : " << latency_bc << std::endl;
+
+	std::cout << "Simulation Ends" << std::endl;
+
+
+	return EXIT_SUCCESS;
+}
+
+int sc_main (int argc, char *argv[])
+{
+	try {
+		return _main(argc, argv);
+	} catch (std::exception &e) {
+		std::cout << e.what() << std::endl;
+	} catch (...) {
+		std::cout << "Unknown exception occured" << std::endl;
+		throw;
+	}
+	return 1;
+}
+
Index: branches/v4/platforms/caba-vgmn-ccxcachev1_memcachev3-mipsel/Makefile
===================================================================
--- branches/v4/platforms/caba-vgmn-ccxcachev1_memcachev3-mipsel/Makefile	(revision 371)
+++ branches/v4/platforms/caba-vgmn-ccxcachev1_memcachev3-mipsel/Makefile	(revision 371)
@@ -0,0 +1,5 @@
+ARCH=mips32el
+SIMULATION_ARGS=100000
+SOCLIB?=$(shell soclib-cc --getpath)
+export SOCLIB
+include $(SOCLIB)/soclib/platform/topcells/all.mk
Index: branches/v4/platforms/caba-vgmn-ccxcachev1_memcachev3-mipsel/platform_desc
===================================================================
--- branches/v4/platforms/caba-vgmn-ccxcachev1_memcachev3-mipsel/platform_desc	(revision 371)
+++ branches/v4/platforms/caba-vgmn-ccxcachev1_memcachev3-mipsel/platform_desc	(revision 371)
@@ -0,0 +1,25 @@
+
+# -*- python -*-
+
+
+todo = Platform('caba', 'top.cpp',
+				uses = [
+	Uses('caba:vci_cc_xcache_wrapper_v1', iss_t = 'common:iss2_simhelper', simhelper_iss_t = 'common:mips32el'),
+	Uses('caba:vci_simple_ram'),
+  Uses('caba:vci_logger'),
+	Uses('caba:vci_multi_tty'),
+	Uses('caba:vci_vgmn'),
+	Uses('caba:vci_mem_cache_v3'),
+	Uses('common:elf_file_loader'),
+	],
+	cell_size = 4,
+	plen_size = 8,
+	addr_size = 32,
+	rerror_size = 1,
+	clen_size = 1,
+	rflag_size = 1,
+	srcid_size = 8,
+	pktid_size = 4,
+	trdid_size = 4,
+	wrplen_size = 1
+)
Index: branches/v4/platforms/caba-vgmn-ccxcachev1_memcachev3-mipsel/segmentation.h
===================================================================
--- branches/v4/platforms/caba-vgmn-ccxcachev1_memcachev3-mipsel/segmentation.h	(revision 371)
+++ branches/v4/platforms/caba-vgmn-ccxcachev1_memcachev3-mipsel/segmentation.h	(revision 371)
@@ -0,0 +1,82 @@
+
+/////////////////////////////////////////////////////////////////
+//	ADDRESS SPACE SEGMENTATION
+//
+//	This file must be included in the system.cpp file, 
+//	for harware configuration : It is used to build
+//	the SOCLIB_SEGMENT_TABLE.
+//
+//	This file can also be used by the ldscript generator,
+//	for embedded software generation.
+//	
+//	It gives the system integrator the garanty
+//	that hardware and software have the same
+//	description of the address space segmentation.
+/////////////////////////////////////////////////////////////////
+
+/////////////////////////////////////////////////////////////////
+//	reset, and exception segments
+//      base address required by MIPS processor
+/////////////////////////////////////////////////////////////////
+#define MMU
+
+#define	RESET_BASE	0xBFC00000
+#define	RESET_SIZE	0x00010000
+
+#define	EXCEP_BASE	0x80000000
+#define	EXCEP_SIZE	0x00010000
+
+#define	TEXT_BASE	0x00400000
+#define	TEXT_SIZE	0x00050000
+/////////////////////////////////////////////////////////////////
+//	global data segment (initialised)
+/////////////////////////////////////////////////////////////////
+
+#define MC_M_BASE	0x10000000
+#define MC_M_SIZE	0x00100000
+
+/////////////////////////////////////////////////////////////////
+//	page table (initialised)
+/////////////////////////////////////////////////////////////////
+#define PTD_ADDR	0x40400000
+#define PTE_ADDR	0x40402000
+#define IPTE_ADDR	0x40403000
+#define	TAB_SIZE	0x00010000
+
+#define V_TTY_BASE 	0x00800000
+#define	V_TIMER_BASE	0x00C00000	// timer virtual address
+//////////////////////////////////////////////////////////
+//	System devices
+///////////////////////////////////////////////////////////
+
+#define	TTY_BASE	0xC0200000
+#define	TTY_SIZE	0x00000100
+
+#define	TIMER_BASE	0xD0200000
+#define	TIMER_SIZE	0x00000100
+
+#define	LOCKS_BASE	0xE0200000
+#define	LOCKS_SIZE	0x00000100
+
+#define C_PROC0_BASE	0x01200000
+#define C_PROC0_SIZE	0x00000010
+
+#define C_PROC1_BASE	0x02200000
+#define C_PROC1_SIZE	0x00000010
+
+#define C_PROC2_BASE	0x03200000
+#define C_PROC2_SIZE	0x00000010
+
+#define C_PROC3_BASE	0x04200000
+#define C_PROC3_SIZE	0x00000010
+
+#define C_MC_M_BASE	0x00200000
+#define C_MC_M_SIZE	0x00000008
+
+#define XRAM_BASE	0xB0200000
+#define XRAM_SIZE	0x00000008
+
+#define MC_R_BASE	0x20200000
+#define MC_R_SIZE	0x00000008
+
+#define CLEANUP_OFFSET  0x20200000
Index: branches/v4/platforms/caba-vgmn-ccxcachev1_memcachev3-mipsel/soft/Makefile
===================================================================
--- branches/v4/platforms/caba-vgmn-ccxcachev1_memcachev3-mipsel/soft/Makefile	(revision 371)
+++ branches/v4/platforms/caba-vgmn-ccxcachev1_memcachev3-mipsel/soft/Makefile	(revision 371)
@@ -0,0 +1,4 @@
+ADD_OBJS= stdio.o stdlib.o exception.o system.o
+SOCLIB?=$(shell soclib-cc --getpath)
+export SOCLIB
+include $(SOCLIB)/soclib/platform/topcells/soft.mk
Index: branches/v4/platforms/caba-vgmn-ccxcachev1_memcachev3-mipsel/soft/main.c
===================================================================
--- branches/v4/platforms/caba-vgmn-ccxcachev1_memcachev3-mipsel/soft/main.c	(revision 371)
+++ branches/v4/platforms/caba-vgmn-ccxcachev1_memcachev3-mipsel/soft/main.c	(revision 371)
@@ -0,0 +1,961 @@
+#include "system.h"
+#include "stdio.h"
+#include "stdlib.h"
+//#include "matrice.h"
+
+#include "../segmentation.h"
+
+#define NPROCS 4
+#define SIZE 500 
+#define SORT_TYPE 2
+
+volatile int nprocs=NPROCS;
+unsigned int gQSortNum0[16000] = {
+  251, 24, 113, 170, 215, 60, 83, 30, 115, 48, 169, 210, 49, 92, 101, 58, 21, 184, 225, 6,
+  199, 244, 227, 146, 99, 96, 25, 222, 65, 140, 213, 22, 219, 136, 175, 182, 73, 36, 141, 190, 
+  83, 112, 137, 114, 175, 188, 187, 102, 53, 168, 193, 154, 167, 172, 3, 242, 67, 64,144, 137,
+  142, 175, 188, 69, 102, 53, 168, 193, 102, 89, 172, 253, 242, 67,192, 7, 62, 159, 20, 181,
+  182, 187, 216, 207, 22, 105, 132, 109, 162, 205, 16, 151, 18, 113, 228, 37, 6, 85, 8, 161,
+  58, 135, 76, 35, 174, 35, 224, 39, 158, 127, 180, 149, 86, 155, 200, 239, 118, 119, 28, 77,
+  254, 19, 176, 183, 78, 145, 132, 5, 90, 117, 152, 127, 218, 153, 20, 67, 178, 3, 128, 185,
+  254, 95, 172, 139, 246, 123, 104, 15, 42, 169, 68, 211, 98, 243, 80, 41, 174, 79, 36, 27,
+  186, 149, 86, 155, 200, 239, 118, 119, 28, 77, 254, 19, 176, 183,78, 145, 132, 5, 90, 117,
+  152, 127, 218, 153, 20, 67, 178, 3, 128, 185, 254, 95, 172, 139, 246, 123, 104, 15, 42,169,
+  68, 211, 98, 243, 80, 41, 174, 79, 36, 27, 186, 107, 56, 97, 134, 71, 116, 157, 238, 227,
+  32, 153, 162, 193, 244, 171, 150, 165, 248, 209, 54, 55, 164, 13, 194, 45, 16, 247, 242, 47,
+  60, 59, 26, 75, 40, 65, 230, 217, 44, 131, 142, 195, 192, 121, 190, 225, 108, 203, 202, 197,
+  168, 177, 150, 233, 252, 19, 34, 77, 144, 23, 110, 15, 100, 91, 122, 213, 120, 223, 70, 7, 
+  52, 93, 46, 93, 160, 167, 226, 255, 204, 21, 42, 229, 72, 111, 246, 9, 100, 205, 126, 147,
+  215, 82, 79, 36, 229, 70, 149, 56, 159, 134, 185, 140, 99, 18, 29, 224, 153, 94, 63, 244, 85, 150, 91, 248, 209,
+  202, 55, 92, 243, 194, 211, 240, 247, 242, 209, 196, 197, 26, 75, 40, 191, 26, 39, 44, 131, 142, 195, 64, 121, 190,
+  231, 34, 65, 116, 43, 22, 219, 136, 175, 74, 73, 220, 141, 190, 83, 112, 137, 142, 81, 68, 69, 154, 203, 88, 63,
+  154, 89, 172, 3, 242, 67, 192, 249, 62, 159, 20, 181, 74, 69, 216, 49, 22, 105, 132, 109, 162, 205, 16, 151, 18,
+  37, 136, 175, 74, 183, 36, 115, 66, 173, 144, 137, 142, 175, 188, 69, 102, 53, 168, 193, 102, 89, 172, 253, 242, 67,
+  192, 7, 62, 159, 20, 181, 182, 187, 216, 207, 22, 105, 132, 109, 162, 205, 16, 151, 18, 113, 228, 37, 6, 85, 8,
+  161, 58, 135, 76, 35, 174, 35, 224, 39, 158, 127, 180, 149, 86, 155, 200, 239, 118, 119, 28, 77, 254, 19, 176, 183,
+  78, 145, 132, 5, 90, 117, 152, 127, 218, 153, 20, 67, 178, 3, 128, 185, 254, 95, 172, 139, 246, 123, 104, 15, 42,
+  251, 24, 113, 170, 215, 60, 83, 30, 115, 48, 169, 210, 49, 92, 101, 58, 21, 184, 225, 6,
+  199, 244, 227, 146, 99, 96, 25, 222, 65, 140, 213, 22, 219, 136, 175, 182, 73, 36, 141, 190, 
+  83, 112, 137, 114, 175, 188, 187, 102, 53, 168, 193, 154, 167, 172, 3, 242, 67, 64,144, 137,
+  142, 175, 188, 69, 102, 53, 168, 193, 102, 89, 172, 253, 242, 67,192, 7, 62, 159, 20, 181,
+  182, 187, 216, 207, 22, 105, 132, 109, 162, 205, 16, 151, 18, 113, 228, 37, 6, 85, 8, 161,
+  58, 135, 76, 35, 174, 35, 224, 39, 158, 127, 180, 149, 86, 155, 200, 239, 118, 119, 28, 77,
+  254, 19, 176, 183, 78, 145, 132, 5, 90, 117, 152, 127, 218, 153, 20, 67, 178, 3, 128, 185,
+  254, 95, 172, 139, 246, 123, 104, 15, 42, 169, 68, 211, 98, 243, 80, 41, 174, 79, 36, 27,
+  186, 149, 86, 155, 200, 239, 118, 119, 28, 77, 254, 19, 176, 183,78, 145, 132, 5, 90, 117,
+  152, 127, 218, 153, 20, 67, 178, 3, 128, 185, 254, 95, 172, 139, 246, 123, 104, 15, 42,169,
+  68, 211, 98, 243, 80, 41, 174, 79, 36, 27, 186, 107, 56, 97, 134, 71, 116, 157, 238, 227,
+  32, 153, 162, 193, 244, 171, 150, 165, 248, 209, 54, 55, 164, 13, 194, 45, 16, 247, 242, 47,
+  60, 59, 26, 75, 40, 65, 230, 217, 44, 131, 142, 195, 192, 121, 190, 225, 108, 203, 202, 197,
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+  192, 7, 62, 159, 20, 181, 182, 187, 216, 207, 22, 105, 132, 109, 162, 205, 16, 151, 18, 113, 228, 37, 6, 85, 8,
+  161, 58, 135, 76, 35, 174, 35, 224, 39, 158, 127, 180, 149, 86, 155, 200, 239, 118, 119, 28, 77, 254, 19, 176, 183,
+  78, 145, 132, 5, 90, 117, 152, 127, 218, 153, 20, 67, 178, 3, 128, 185, 254, 95, 172, 139, 246, 123, 104, 15, 42,
+  169, 68, 211, 98, 243, 80, 41, 174, 79, 36, 27, 186, 107, 56, 97, 134, 71, 116, 157, 238, 227, 32, 153, 162, 193,
+  244, 171, 150, 165, 248, 209, 54, 55, 164, 13, 194, 45, 16, 247, 242, 47, 60, 59, 26, 75, 40, 65, 230, 217, 44,
+  131, 142, 195, 192, 121, 190, 225, 108, 203, 202, 197, 168, 177, 150, 233, 252, 19, 34, 77, 144, 23, 110, 15, 100, 91,
+  122, 213, 120, 223, 70, 7, 52, 93, 46, 93, 160, 167, 226, 255, 204, 21, 42, 229, 72, 111, 246, 9, 100, 205, 126,
+  147, 48, 55, 206, 239, 4, 133, 218, 245, 232, 255, 166, 231, 108, 195, 50, 131, 0, 57, 130, 223, 44, 245, 118, 251,
+  232, 113, 86, 215, 196, 83, 30, 141, 48, 87, 46, 207, 92, 155, 198, 235, 72, 31, 250, 57, 244, 29, 110, 99, 160,
+  231, 34, 65, 116, 43, 22, 219, 136, 175, 74, 73, 220, 141, 190, 83, 112, 137, 142, 81, 68, 69, 154, 203, 88, 63,
+  154, 89, 172, 3, 242, 67, 192, 249, 62, 159, 20, 181, 74, 69, 216, 49, 22, 105, 132, 109, 162, 205, 16, 151, 18,
+  113, 228, 219, 
+250, 171, 8, 95, 58, 135, 180, 35, 82, 221, 224, 39, 98, 129, 180, 107, 86, 101, 200, 239, 118, 119,
+  228, 179, 2, 237, 80, 183, 78, 111, 124, 5, 90, 117, 104, 127, 38, 153, 20, 67, 178, 253, 128, 185, 254, 95, 172,
+  117, 10, 123, 152, 241, 42, 87, 188, 211, 98, 243, 80, 215, 82, 79, 36, 27, 186, 107, 200, 159, 122, 71, 140, 157,
+  238, 29, 224, 153, 94, 63, 244, 85, 106, 91, 248, 47, 54, 201, 164, 243, 62, 211, 240, 247, 242, 47, 196, 197, 230,
+  181, 216, 65, 26, 217, 44, 125, 114, 195, 192, 135, 190, 31, 148, 203, 202, 59, 88, 79, 150, 233, 252, 19, 34, 77,
+  144, 233, 146, 15, 100, 165, 122, 213, 136, 223, 70, 249, 204, 93, 46, 93, 96, 167, 30, 1, 204, 21, 42, 27, 72
+};
+
+
+
+unsigned int SortArr0[NPROCS*(SIZE+200)];
+//unsigned int SortArr0[4*4*SIZE];
+
+void SORT(unsigned int *base, unsigned int n, int type);
+void insertion_sort(unsigned int *base, unsigned int n); // type 2
+void selection_sort(unsigned int *base, unsigned int n); // type 1
+void bubble_sort(unsigned int *base, unsigned int n);    // type 3
+void shellSortPhase(unsigned int a[],unsigned int length, int gap);
+void shellSort(unsigned int *base, unsigned int n);     // type 0
+
+int main()
+{
+  register int p; 
+
+  int beg_cycle, end_cycle;
+
+  beg_cycle = cpu_cycles();
+   
+  p=procnum();
+
+  puts("Hello from processor ");
+  putchar(p+'0');
+  putchar('\n');
+
+  int i;
+  int j;
+  unsigned int* SortArray;
+
+  if(p+1 <= nprocs)
+  {
+        i=1;
+  	puts("Memory copy \n");
+        SortArray = SortArr0 + p*(SIZE+200);
+	memcpy(SortArray, gQSortNum0 + p*SIZE,SIZE*4);
+ 	puts("Sort... \n");
+        SORT((unsigned int *) (SortArray), (unsigned int) SIZE, SORT_TYPE);
+
+  	for (j = 1; j < SIZE; j++)
+    	{
+	  if (SortArray[j] < SortArray[j-1])
+		{
+	  		puts("ucbqsort: failed\n");
+			while(1);
+		}
+
+    	}
+
+  	puts("ucbqsort: success\n");
+        end_cycle = cpu_cycles();
+        printf( "nombre cycles cpu : %i\n", end_cycle-beg_cycle);
+  }
+
+  
+// puts("Display the sorted array : \n");
+// for(j = 0; j < SIZE; j++)
+// {
+//   puti(SortArray[j]);
+//   putchar('\n');
+// }
+
+//  printf( "------------------------------ \n");
+//  printf( "nombre cycles cpu : %i\n", end_cycle-beg_cycle);
+//  printf( "------------------------------ \n");
+
+
+  while(1);
+}
+
+
+//---- insertion sort : non adapté pour tableaux de grande taille (> 100) --
+void insertion_sort(unsigned int *base, unsigned int n) 
+{
+    /* Spécifications externes : Tri du tableau base par insertion séquentielle */
+    int i,p,j;
+    int x;
+
+    puts("Insertion Sort\n");
+
+    for (i = 1; i < n; i++) 
+    {
+
+        putchar('-'); // added for debug
+
+        /* stockage de la valeur en i */
+        x = base[i]; 
+ 
+        /* recherche du plus petit indice p inférieur à i tel que base[p] >= base[i] */
+        for(p = 0; base[p] < x; p++);
+        /* p pointe une valeur de base supérieure à celle en i */ 
+ 
+        /* décalage avant des valeurs de base entre p et i */         
+        for (j = i-1; j >= p; j--) {
+            base[j+1] = base[j]; 
+        }   
+ 
+        base[p] = x; /* insertion de la valeur stockée à la place vacante */
+
+        putchar('+'); // added for debug
+
+    }
+}
+
+//------ simple_sort -------------------------------
+void selection_sort(unsigned int *base, unsigned int n)
+{
+     int i, min, j , x;
+     puts("Selection Sort\n");
+
+     for(i = 0 ; i < n - 1 ; i++)
+     {
+
+         putchar('-'); // added for debug
+
+         min = i;
+
+         
+         for(j = i+1 ; j < n ; j++)
+         {
+        
+            if(base[j] < base[min])
+                  min = j;
+            
+         }
+
+         if(min != i)
+         {
+             x = base[i];
+             base[i] = base[min];
+             base[min] = x;
+         }
+
+         putchar('+'); // added for debug
+
+     }
+}
+//-------------------------------
+void bubble_sort(unsigned int *base, unsigned int n)
+{
+        int i   = 0; /* Indice de répétition du tri */
+ 	int j   = 0; /* Variable de boucle */
+ 	int tmp = 0; /* Variable de stockage temporaire */
+        int en_desordre = 1; /* Booléen marquant l'arrêt du tri si le tableau est ordonné */
+
+        puts("Bubble Sort\n");
+
+	/* Boucle de répétition du tri et le test qui arrête le tri dès que le tableau est ordonné */
+	for(i = 0 ; (i < n) && en_desordre; i++)
+	{
+                putchar('-'); // added for debug
+
+		/* Supposons le tableau ordonné */
+		en_desordre = 0;
+		/* Vérification des éléments des places j et j-1 */
+		for(j = 1 ; j < n - i ; j++)
+		{
+			/* Si les 2 éléments sont mal triés */
+			if(base[j] < base[j-1])
+			{
+				/* Inversion des 2 éléments */
+ 				tmp = base[j-1];
+ 				base[j-1] = base[j];
+ 				base[j] = tmp;
+ 
+ 				/* Le tableau n'est toujours pas trié */
+				en_desordre = 1;
+ 			}
+		}
+
+                putchar('+'); // added for debug
+	}
+
+}
+//------------------------------------------------------
+/*
+ * Exécute un tri par insertion avec la séparation donnée
+ * If gap == 1, on fait un tri ordinaire.
+ * If gap >= length, on ne fait rien.
+ */
+void shellSortPhase(unsigned int a[],unsigned int length, int gap) {
+    int i;
+ 
+    puti(gap);
+    for (i = gap; i < length; ++i) {
+        unsigned int value = a[i];
+        int j;
+        for (j = i - gap; j >= 0 && a[j] > value; j -= gap) {
+	    putchar('+');
+            a[j + gap] = a[j];
+	    putchar('-');
+        }
+        a[j + gap] = value;
+    }
+}
+ 
+void shellSort(unsigned int *base, unsigned int n) {
+    /*
+     * gaps[] doit approximer une Série géométrique.
+     * La sequence suivante est la meilleure connue en terme
+     * de nombre moyen de comparaisons. voir:
+     * http://www.research.att.com/~njas/sequences/A102549
+     */
+    static const int gaps[] = {
+        1, 4, 10, 23, 57, 132, 301, 701
+    };
+    int sizeIndex;
+ 
+    puts("Shell Sort\n");
+    for (sizeIndex = sizeof(gaps)/sizeof(gaps[0]) - 1;
+               sizeIndex >= 0;
+               --sizeIndex)
+        shellSortPhase(base, n, gaps[sizeIndex]);
+}
+
+//-------------------------------------*/
+void SORT(unsigned int *base, unsigned int n, int type)
+{
+  switch(type)
+  {
+  case 0:
+    shellSort(base, n);
+    break;
+  case 1:
+    selection_sort(base, n);
+    break;
+  case 2:
+    insertion_sort(base, n);
+    break;
+  case 3:
+    bubble_sort(base, n);
+    break;
+  default:
+    break;
+  }
+}
+
Index: branches/v4/platforms/caba-vgmn-ccxcachev1_memcachev3-mipsel/top.cpp
===================================================================
--- branches/v4/platforms/caba-vgmn-ccxcachev1_memcachev3-mipsel/top.cpp	(revision 371)
+++ branches/v4/platforms/caba-vgmn-ccxcachev1_memcachev3-mipsel/top.cpp	(revision 371)
@@ -0,0 +1,373 @@
+
+#include <systemc>
+#include <sys/time.h>
+#include <iostream>
+#include <cstdlib>
+#include <cstdarg>
+
+#include "mapping_table.h"
+#include "mips32.h"
+#include "iss2_simhelper.h"
+#include "vci_simple_ram.h"
+#include "vci_multi_tty.h"
+#include "vci_vgmn.h"
+#include "vci_mem_cache_v3.h"
+#include "vci_cc_xcache_wrapper_v1.h"
+#include "vci_logger.h"
+
+#ifdef USE_GDB_SERVER
+#include "iss/gdbserver.h"
+#endif
+
+//#define  VCI_LOGGER
+#include "segmentation.h"
+
+int _main(int argc, char *argv[])
+{
+	using namespace sc_core;
+	// Avoid repeating these everywhere
+	using soclib::common::IntTab;
+	using soclib::common::Segment;
+
+	// Define VCI parameters
+	typedef soclib::caba::VciParams<4,8,32,1,1,1,8,4,4,1> vci_param;
+	typedef soclib::common::Iss2Simhelper<soclib::common::Mips32ElIss> proc_iss;
+	// Mapping table
+
+	soclib::common::MappingTable maptabp(32, IntTab(8), IntTab(8), 0x00300000);
+
+	maptabp.add(Segment("reset", RESET_BASE, RESET_SIZE, IntTab(2), true));
+	maptabp.add(Segment("excep", EXCEP_BASE, EXCEP_SIZE, IntTab(2), true));
+	maptabp.add(Segment("text" , TEXT_BASE , TEXT_SIZE , IntTab(2), true));
+	maptabp.add(Segment("tty"  , TTY_BASE  , TTY_SIZE  , IntTab(1), false));
+	maptabp.add(Segment("mc_r" , MC_R_BASE , MC_R_SIZE , IntTab(2), false, true, IntTab(0)));
+	maptabp.add(Segment("mc_m" , MC_M_BASE , MC_M_SIZE , IntTab(2), true ));
+	maptabp.add(Segment("ptba" , PTD_ADDR , TAB_SIZE   , IntTab(2), true));
+ 
+	std::cout << maptabp << std::endl;
+
+        soclib::common::MappingTable maptabc(32, IntTab(8), IntTab(8), 0x00300000);
+	maptabc.add(Segment("c_proc0" , C_PROC0_BASE , C_PROC0_SIZE , IntTab(0), false, true, IntTab(0)));
+	maptabc.add(Segment("c_proc1" , C_PROC1_BASE , C_PROC1_SIZE , IntTab(1), false, true, IntTab(1)));
+	maptabc.add(Segment("c_proc2" , C_PROC2_BASE , C_PROC2_SIZE , IntTab(2), false, true, IntTab(2)));
+	maptabc.add(Segment("c_proc3" , C_PROC3_BASE , C_PROC3_SIZE , IntTab(3), false, true, IntTab(3)));
+	maptabc.add(Segment("mc_r"    , MC_R_BASE , MC_R_SIZE , IntTab(4), false, false));
+	maptabc.add(Segment("mc_m"  , MC_M_BASE , MC_M_SIZE  , IntTab(4), false, false));
+	maptabc.add(Segment("reset", RESET_BASE, RESET_SIZE, IntTab(4), false, false));
+	maptabc.add(Segment("excep", EXCEP_BASE, EXCEP_SIZE, IntTab(4), false, false));
+	maptabc.add(Segment("text" , TEXT_BASE , TEXT_SIZE , IntTab(4), false, false));
+	maptabc.add(Segment("ptba" , PTD_ADDR  , TAB_SIZE  , IntTab(4), false, false));
+
+	std::cout << maptabc << std::endl;
+	
+	soclib::common::MappingTable maptabx(32, IntTab(8), IntTab(8), 0x00300000);
+	maptabx.add(Segment("xram" , MC_M_BASE , MC_M_SIZE , IntTab(0), false));
+	maptabx.add(Segment("reset", RESET_BASE, RESET_SIZE, IntTab(0), false));
+	maptabx.add(Segment("excep", EXCEP_BASE, EXCEP_SIZE, IntTab(0), false));
+	maptabx.add(Segment("text" , TEXT_BASE , TEXT_SIZE , IntTab(0), false));
+	maptabx.add(Segment("ptba" , PTD_ADDR  , TAB_SIZE  , IntTab(0), false));
+	
+	std::cout << maptabx << std::endl;
+
+	// Signals
+	sc_clock	signal_clk("clk");
+	sc_signal<bool> signal_resetn("resetn");
+   
+	sc_signal<bool> signal_proc0_it0("proc0_it0"); 
+	sc_signal<bool> signal_proc0_it1("proc0_it1"); 
+	sc_signal<bool> signal_proc0_it2("proc0_it2"); 
+	sc_signal<bool> signal_proc0_it3("proc0_it3"); 
+	sc_signal<bool> signal_proc0_it4("proc0_it4"); 
+	sc_signal<bool> signal_proc0_it5("proc0_it5");
+
+	sc_signal<bool> signal_proc1_it0("proc1_it0"); 
+	sc_signal<bool> signal_proc1_it1("proc1_it1"); 
+	sc_signal<bool> signal_proc1_it2("proc1_it2"); 
+	sc_signal<bool> signal_proc1_it3("proc1_it3"); 
+	sc_signal<bool> signal_proc1_it4("proc1_it4"); 
+	sc_signal<bool> signal_proc1_it5("proc1_it5");
+
+	sc_signal<bool> signal_proc2_it0("proc2_it0"); 
+	sc_signal<bool> signal_proc2_it1("proc2_it1"); 
+	sc_signal<bool> signal_proc2_it2("proc2_it2"); 
+	sc_signal<bool> signal_proc2_it3("proc2_it3"); 
+	sc_signal<bool> signal_proc2_it4("proc2_it4"); 
+	sc_signal<bool> signal_proc2_it5("proc2_it5");
+
+	sc_signal<bool> signal_proc3_it0("proc3_it0"); 
+	sc_signal<bool> signal_proc3_it1("proc3_it1"); 
+	sc_signal<bool> signal_proc3_it2("proc3_it2"); 
+	sc_signal<bool> signal_proc3_it3("proc3_it3"); 
+	sc_signal<bool> signal_proc3_it4("proc3_it4"); 
+	sc_signal<bool> signal_proc3_it5("proc3_it5");
+
+	soclib::caba::VciSignals<vci_param> signal_vci_ini_rw_proc0("vci_ini_rw_proc0");
+	soclib::caba::VciSignals<vci_param> signal_vci_ini_c_proc0("vci_ini_c_proc0");
+
+	soclib::caba::VciSignals<vci_param> signal_vci_tgt_proc0("vci_tgt_proc0");
+
+	soclib::caba::VciSignals<vci_param> signal_vci_ini_rw_proc1("vci_ini_rw_proc1");
+	soclib::caba::VciSignals<vci_param> signal_vci_ini_c_proc1("vci_ini_c_proc1");
+
+	soclib::caba::VciSignals<vci_param> signal_vci_tgt_proc1("vci_tgt_proc1");
+
+	soclib::caba::VciSignals<vci_param> signal_vci_ini_rw_proc2("vci_ini_rw_proc2");
+	soclib::caba::VciSignals<vci_param> signal_vci_ini_c_proc2("vci_ini_c_proc2");
+
+	soclib::caba::VciSignals<vci_param> signal_vci_tgt_proc2("vci_tgt_proc2");
+
+	soclib::caba::VciSignals<vci_param> signal_vci_ini_rw_proc3("vci_ini_rw_proc3");
+	soclib::caba::VciSignals<vci_param> signal_vci_ini_c_proc3("vci_ini_c_proc3");
+
+	soclib::caba::VciSignals<vci_param> signal_vci_tgt_proc3("vci_tgt_proc3");
+
+	soclib::caba::VciSignals<vci_param> signal_vci_tgt_tty("vci_tgt_tty");
+
+	soclib::caba::VciSignals<vci_param> signal_vci_tgt_rom("vci_tgt_rom");
+
+	soclib::caba::VciSignals<vci_param> signal_vci_tgt_xram("vci_tgt_xram");
+
+	soclib::caba::VciSignals<vci_param> signal_vci_ixr_memc("vci_ixr_memc");
+	soclib::caba::VciSignals<vci_param> signal_vci_ini_memc("vci_ini_memc");
+	soclib::caba::VciSignals<vci_param> signal_vci_tgt_memc("vci_tgt_memc");
+	soclib::caba::VciSignals<vci_param> signal_vci_tgt_cleanup_memc("vci_tgt_cleanup_memc");
+
+	sc_signal<bool> signal_tty_irq0("signal_tty_irq0"); 
+	sc_signal<bool> signal_tty_irq1("signal_tty_irq1"); 
+	sc_signal<bool> signal_tty_irq2("signal_tty_irq2"); 
+	sc_signal<bool> signal_tty_irq3("signal_tty_irq3"); 
+
+	soclib::common::Loader loader("soft/bin.soft");
+
+        //                                  init_rw   init_c   tgt
+/*	soclib::caba::VciCcXCacheWrapperV1<vci_param, proc_iss > 
+	proc0("proc0", 0, maptabp, maptabc, IntTab(0),IntTab(0),IntTab(0),4,64,16,4,64,16);
+
+	soclib::caba::VciCcXCacheWrapperV1<vci_param, proc_iss > 
+	proc1("proc1", 1, maptabp, maptabc, IntTab(1),IntTab(1),IntTab(1),4,64,16,4,64,16);
+
+	soclib::caba::VciCcXCacheWrapperV1<vci_param, proc_iss > 
+	proc2("proc2", 2, maptabp, maptabc, IntTab(2),IntTab(2),IntTab(2),4,64,16,4,64,16);
+
+	soclib::caba::VciCcXCacheWrapperV1<vci_param, proc_iss > 
+	proc3("proc3", 3, maptabp, maptabc, IntTab(3),IntTab(3),IntTab(3),4,64,16,4,64,16);
+*/
+
+	soclib::caba::VciCcXCacheWrapperV1<vci_param, proc_iss > 
+	proc0("proc0", 0, maptabp, maptabc, IntTab(0),IntTab(0),IntTab(0),1,8,16,1,8,16);
+
+	soclib::caba::VciCcXCacheWrapperV1<vci_param, proc_iss > 
+	proc1("proc1", 1, maptabp, maptabc, IntTab(1),IntTab(1),IntTab(1),1,8,16,1,8,16);
+
+	soclib::caba::VciCcXCacheWrapperV1<vci_param, proc_iss > 
+	proc2("proc2", 2, maptabp, maptabc, IntTab(2),IntTab(2),IntTab(2),1,8,16,1,8,16);
+
+	soclib::caba::VciCcXCacheWrapperV1<vci_param, proc_iss > 
+	proc3("proc3", 3, maptabp, maptabc, IntTab(3),IntTab(3),IntTab(3),1,8,16,1,8,16);
+
+
+	soclib::caba::VciSimpleRam<vci_param> 
+	rom("rom", IntTab(0), maptabp, loader);
+
+	soclib::caba::VciSimpleRam<vci_param> 
+	xram("xram", IntTab(0), maptabx, loader);
+
+        //                                  x_init    c_init    p_tgt     c_tgt
+	soclib::caba::VciMemCacheV3<vci_param> 
+	//memc("memc",maptabp,maptabc,maptabx,IntTab(0),IntTab(4),IntTab(2), IntTab(4),16,256,16);
+	//memc("memc",maptabp,maptabc,maptabx,IntTab(0),IntTab(4),IntTab(2), IntTab(4),4,16,16);
+	memc("memc",maptabp,maptabc,maptabx,IntTab(0),IntTab(4),IntTab(2), IntTab(4),4,4,16);
+	
+	soclib::caba::VciMultiTty<vci_param> 
+	tty("tty",IntTab(1),maptabp,"tty0","tty1","tty2","tty3",NULL);
+
+#ifdef VCI_LOGGER
+  soclib::caba::VciLogger<vci_param> vci_logger0("vci_logger0",maptabp);
+#endif
+
+	soclib::caba::VciVgmn<vci_param> 
+	vgmnp("vgmnp",maptabp, 4, 3, 2, 8);
+
+	soclib::caba::VciVgmn<vci_param> 
+	vgmnc("vgmnc",maptabc, 5, 5, 2, 8);
+
+	soclib::caba::VciVgmn<vci_param> 
+	vgmnx("vgmnx",maptabx, 1, 1, 2, 8);
+
+	// Net-List
+ 
+	proc0.p_clk(signal_clk);  
+	proc0.p_resetn(signal_resetn);  
+	proc0.p_irq[0](signal_proc0_it0); 
+	proc0.p_irq[1](signal_proc0_it1); 
+	proc0.p_irq[2](signal_proc0_it2); 
+	proc0.p_irq[3](signal_proc0_it3); 
+	proc0.p_irq[4](signal_proc0_it4); 
+	proc0.p_irq[5](signal_proc0_it5); 
+	proc0.p_vci_ini_rw(signal_vci_ini_rw_proc0);
+	proc0.p_vci_ini_c(signal_vci_ini_c_proc0);
+	proc0.p_vci_tgt(signal_vci_tgt_proc0);
+
+	proc1.p_clk(signal_clk);  
+	proc1.p_resetn(signal_resetn);  
+	proc1.p_irq[0](signal_proc1_it0); 
+	proc1.p_irq[1](signal_proc1_it1); 
+	proc1.p_irq[2](signal_proc1_it2); 
+	proc1.p_irq[3](signal_proc1_it3); 
+	proc1.p_irq[4](signal_proc1_it4); 
+	proc1.p_irq[5](signal_proc1_it5); 
+	proc1.p_vci_ini_rw(signal_vci_ini_rw_proc1);
+	proc1.p_vci_ini_c(signal_vci_ini_c_proc1);
+	proc1.p_vci_tgt(signal_vci_tgt_proc1);
+
+	proc2.p_clk(signal_clk);  
+	proc2.p_resetn(signal_resetn);  
+	proc2.p_irq[0](signal_proc2_it0); 
+	proc2.p_irq[1](signal_proc2_it1); 
+	proc2.p_irq[2](signal_proc2_it2); 
+	proc2.p_irq[3](signal_proc2_it3); 
+	proc2.p_irq[4](signal_proc2_it4); 
+	proc2.p_irq[5](signal_proc2_it5); 
+	proc2.p_vci_ini_rw(signal_vci_ini_rw_proc2);
+	proc2.p_vci_ini_c(signal_vci_ini_c_proc2);
+	proc2.p_vci_tgt(signal_vci_tgt_proc2);
+
+	proc3.p_clk(signal_clk);  
+	proc3.p_resetn(signal_resetn);  
+	proc3.p_irq[0](signal_proc3_it0); 
+	proc3.p_irq[1](signal_proc3_it1); 
+	proc3.p_irq[2](signal_proc3_it2); 
+	proc3.p_irq[3](signal_proc3_it3); 
+	proc3.p_irq[4](signal_proc3_it4); 
+	proc3.p_irq[5](signal_proc3_it5); 
+	proc3.p_vci_ini_rw(signal_vci_ini_rw_proc3);
+	proc3.p_vci_ini_c(signal_vci_ini_c_proc3);
+	proc3.p_vci_tgt(signal_vci_tgt_proc3);
+
+	rom.p_clk(signal_clk);
+	rom.p_resetn(signal_resetn);
+	rom.p_vci(signal_vci_tgt_rom);
+
+#ifdef VCI_LOGGER
+  vci_logger0.p_clk(signal_clk);
+  vci_logger0.p_resetn(signal_resetn);
+  vci_logger0.p_vci(signal_vci_ini_rw_proc2);
+#endif
+
+	tty.p_clk(signal_clk);
+	tty.p_resetn(signal_resetn);
+	tty.p_vci(signal_vci_tgt_tty);
+	tty.p_irq[0](signal_tty_irq0); 
+	tty.p_irq[1](signal_tty_irq1); 
+	tty.p_irq[2](signal_tty_irq2); 
+	tty.p_irq[3](signal_tty_irq3); 
+
+	memc.p_clk(signal_clk);
+	memc.p_resetn(signal_resetn);
+	memc.p_vci_tgt(signal_vci_tgt_memc);
+	memc.p_vci_tgt_cleanup(signal_vci_tgt_cleanup_memc);
+	memc.p_vci_ini(signal_vci_ini_memc);
+	memc.p_vci_ixr(signal_vci_ixr_memc);
+
+	xram.p_clk(signal_clk);
+  xram.p_resetn(signal_resetn);
+	xram.p_vci(signal_vci_tgt_xram);
+	
+	vgmnp.p_clk(signal_clk);
+	vgmnp.p_resetn(signal_resetn);
+
+	vgmnc.p_clk(signal_clk);
+	vgmnc.p_resetn(signal_resetn);
+
+	vgmnx.p_clk(signal_clk);
+	vgmnx.p_resetn(signal_resetn);
+
+	vgmnp.p_to_initiator[0](signal_vci_ini_rw_proc0);
+	vgmnp.p_to_initiator[1](signal_vci_ini_rw_proc1);
+	vgmnp.p_to_initiator[2](signal_vci_ini_rw_proc2);
+	vgmnp.p_to_initiator[3](signal_vci_ini_rw_proc3);
+
+	vgmnc.p_to_initiator[4](signal_vci_ini_memc);
+	vgmnc.p_to_initiator[0](signal_vci_ini_c_proc0);
+	vgmnc.p_to_initiator[1](signal_vci_ini_c_proc1);
+	vgmnc.p_to_initiator[2](signal_vci_ini_c_proc2);
+	vgmnc.p_to_initiator[3](signal_vci_ini_c_proc3);
+
+	vgmnx.p_to_initiator[0](signal_vci_ixr_memc);
+
+	vgmnp.p_to_target[0](signal_vci_tgt_rom);
+	vgmnp.p_to_target[1](signal_vci_tgt_tty);
+	vgmnp.p_to_target[2](signal_vci_tgt_memc);
+
+	vgmnc.p_to_target[0](signal_vci_tgt_proc0);
+	vgmnc.p_to_target[1](signal_vci_tgt_proc1);
+	vgmnc.p_to_target[2](signal_vci_tgt_proc2);
+	vgmnc.p_to_target[3](signal_vci_tgt_proc3);
+	vgmnc.p_to_target[4](signal_vci_tgt_cleanup_memc);
+
+	vgmnx.p_to_target[0](signal_vci_tgt_xram);
+
+	int ncycles;
+
+#ifndef SOCVIEW
+	if (argc == 2) {
+		ncycles = std::atoi(argv[1]);
+	} else {
+		std::cerr
+			<< std::endl
+			<< "The number of simulation cycles must "
+			   "be defined in the command line"
+			<< std::endl;
+		exit(1);
+	}
+
+	sc_start(sc_core::sc_time(0, SC_NS));
+	signal_resetn = false;
+
+	sc_start(sc_core::sc_time(1, SC_NS));
+	signal_resetn = true;
+
+/*
+  while(1){
+    char buf[2];
+	  std::cin.getline(buf,1);
+		sc_start(sc_core::sc_time(1, SC_NS));
+  }
+*/
+
+	for (int i = 0; i < ncycles ; i+=10000) {
+		sc_start(sc_core::sc_time(10000, SC_NS));
+//		proc0.print_stats();
+//		memc.print_stats();
+	}
+
+        std::cout << "Hit ENTER to end simulation" << std::endl;
+        char buf[1];
+
+	std::cin.getline(buf,1);
+
+	return EXIT_SUCCESS;
+#else
+	ncycles = 1;
+	sc_start(sc_core::sc_time(0, SC_NS));
+	signal_resetn = false;
+	sc_start(sc_core::sc_time(1, SC_NS));
+	signal_resetn = true;
+
+	debug();
+	return EXIT_SUCCESS;
+#endif
+}
+
+int sc_main (int argc, char *argv[])
+{
+	try {
+		return _main(argc, argv);
+	} catch (std::exception &e) {
+		std::cout << e.what() << std::endl;
+	} catch (...) {
+		std::cout << "Unknown exception occured" << std::endl;
+		throw;
+	}
+	return 1;
+}
Index: branches/v4/platforms/caba-vgmn-memcache-mipsel/Makefile
===================================================================
--- branches/v4/platforms/caba-vgmn-memcache-mipsel/Makefile	(revision 371)
+++ branches/v4/platforms/caba-vgmn-memcache-mipsel/Makefile	(revision 371)
@@ -0,0 +1,5 @@
+ARCH=mipsel
+SIMULATION_ARGS=100000
+SOCLIB?=$(shell soclib-cc --getpath)
+export SOCLIB
+include $(SOCLIB)/soclib/platform/topcells/all.mk
Index: branches/v4/platforms/caba-vgmn-memcache-mipsel/platform_desc
===================================================================
--- branches/v4/platforms/caba-vgmn-memcache-mipsel/platform_desc	(revision 371)
+++ branches/v4/platforms/caba-vgmn-memcache-mipsel/platform_desc	(revision 371)
@@ -0,0 +1,24 @@
+
+# -*- python -*-
+
+
+todo = Platform('caba', 'top.cpp',
+				uses = [
+        Uses('caba:vci_cc_xcache_wrapper', iss_t = 'common:ississ2', iss2_t = 'common:iss_simhelper', simhelper_iss_t = 'common:mipsel'),
+	Uses('caba:vci_simple_ram'),
+	Uses('caba:vci_multi_tty'),
+	Uses('caba:vci_vgmn'),
+	Uses('caba:vci_mem_cache'),
+		Uses('common:elf_file_loader'),
+	],
+	cell_size = 4,
+	plen_size = 8,
+	addr_size = 32,
+	rerror_size = 1,
+	clen_size = 1,
+	rflag_size = 1,
+	srcid_size = 8,
+	pktid_size = 4,
+	trdid_size = 4,
+	wrplen_size = 1
+)
Index: branches/v4/platforms/caba-vgmn-memcache-mipsel/segmentation.h
===================================================================
--- branches/v4/platforms/caba-vgmn-memcache-mipsel/segmentation.h	(revision 371)
+++ branches/v4/platforms/caba-vgmn-memcache-mipsel/segmentation.h	(revision 371)
@@ -0,0 +1,57 @@
+
+/////////////////////////////////////////////////////////////////
+//	ADDRESS SPACE SEGMENTATION
+//
+//	This file must be included in the system.cpp file, 
+//	for harware configuration : It is used to build
+//	the SOCLIB_SEGMENT_TABLE.
+//
+//	This file can also be used by the ldscript generator,
+//	for embedded software generation.
+//	
+//	It gives the system integrator the garanty
+//	that hardware and software have the same
+//	description of the address space segmentation.
+/////////////////////////////////////////////////////////////////
+
+/////////////////////////////////////////////////////////////////
+//	reset, and exception segments
+//      base address required by MIPS processor
+/////////////////////////////////////////////////////////////////
+
+#define	RESET_BASE	0xBFC00000
+#define	RESET_SIZE	0x00010000
+
+#define	EXCEP_BASE	0x80000000
+#define	EXCEP_SIZE	0x00010000
+
+/////////////////////////////////////////////////////////////////
+//	global data segment (initialised)
+/////////////////////////////////////////////////////////////////
+
+#define MC_M_BASE	0x10000000
+#define MC_M_SIZE	0x00400000
+
+//////////////////////////////////////////////////////////
+//	System devices (seen by the software)
+///////////////////////////////////////////////////////////
+
+#define	TTY_BASE	0xC0400000
+#define	TTY_SIZE	0x00000100
+
+#define	TIMER_BASE	0xD0400000
+#define	TIMER_SIZE	0x00000100
+
+#define	LOCKS_BASE	0xE0400000
+#define	LOCKS_SIZE	0x00000100
+
+#define PROC_BASE	0xF0400000
+#define PROC_SIZE	0x00000008
+
+#define XRAM_BASE	0xB0400000
+#define XRAM_SIZE	0x00000008
+
+#define MC_R_BASE	0x20400000
+#define MC_R_SIZE	0x00000008
+
+#define CLEANUP_OFFSET  0x20400000
Index: branches/v4/platforms/caba-vgmn-memcache-mipsel/soft/Makefile
===================================================================
--- branches/v4/platforms/caba-vgmn-memcache-mipsel/soft/Makefile	(revision 371)
+++ branches/v4/platforms/caba-vgmn-memcache-mipsel/soft/Makefile	(revision 371)
@@ -0,0 +1,4 @@
+ADD_OBJS=stdlib.o stdio.o
+SOCLIB?=$(shell soclib-cc --getpath)
+export SOCLIB
+include $(SOCLIB)/soclib/platform/topcells/soft.mk
Index: branches/v4/platforms/caba-vgmn-memcache-mipsel/soft/ldscript
===================================================================
--- branches/v4/platforms/caba-vgmn-memcache-mipsel/soft/ldscript	(revision 371)
+++ branches/v4/platforms/caba-vgmn-memcache-mipsel/soft/ldscript	(revision 371)
@@ -0,0 +1,114 @@
+/*
+ *
+ * SOCLIB_GPL_HEADER_BEGIN
+ * 
+ * This file is part of SoCLib, GNU GPLv2.
+ * 
+ * SoCLib is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ * 
+ * SoCLib is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * General Public License for more details.
+ * 
+ * You should have received a copy of the GNU General Public License
+ * along with SoCLib; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301, USA.
+ * 
+ * SOCLIB_GPL_HEADER_END
+ *
+ * Copyright (c) UPMC, Lip6, SoC
+ *         Nicolas Pouillon <nipo@ssji.net>, 2006-2007
+ *
+ * Maintainers: nipo
+ */
+
+SECTIONS
+{
+	special_base = 0x00500000;
+	. = special_base;
+    .ppc_special : {
+		. = 0x100;
+		*(.ppc_special.critical_input)
+		. = 0x200;
+		*(.ppc_special.machine_check)
+		. = 0x300;
+		*(.ppc_special.data_storage)
+		. = 0x400;
+		*(.ppc_special.instruction_storage)
+		. = 0x500;
+		*(.ppc_special.external)
+		. = 0x600;
+		*(.ppc_special.alignment)
+		. = 0x700;
+		*(.ppc_special.program)
+		. = 0xc00;
+		*(.ppc_special.syscall)
+		. = 0x1000;
+		*(.ppc_special.programmable_interval_timer)
+		. = 0x1010;
+		*(.ppc_special.fixed_interval_timer)
+		. = 0x1020;
+		*(.ppc_special.watchdog)
+		. = 0x1100;
+		*(.ppc_special.data_tlb_miss)
+		. = 0x1200;
+		*(.ppc_special.instruction_tlb_miss)
+		. = 0x2000;
+		*(.ppc_special.debug)
+    }
+
+    . = 0xfffffffc;
+    .ppc_boot : {
+		*(.ppc_boot)
+		*(.ppc_boot.*)
+    }
+
+   . = 0x80000000;
+   .excep : {
+		*(.excep)
+		*(.excep.*)
+   }
+
+   . = 0xbfc00000;
+   .reset : {
+		*(.reset)
+		*(.reset.*)
+   }
+
+   . = 0x10020000;
+   .text : {
+      *(.text)
+   }
+   . = 0x10070000;
+   .rodata : {
+      *(.rodata)
+      . = ALIGN(4);
+   }
+   .data  : {
+      *(.data)
+   }
+   .sdata : {
+      *(.lit8)
+      *(.lit4)
+      *(.sdata)
+   }
+   _gp = .;
+   . = ALIGN(4);
+   _edata = .;
+   .sbss  : {
+      *(.sbss)
+      *(.scommon)
+   }
+   .bss   : {
+      *(.bss)
+      *(COMMON)
+   }
+   . = ALIGN(4);
+   _end = .;
+   _heap = .;
+   _stack = 0x10070000-16;
+}
Index: branches/v4/platforms/caba-vgmn-memcache-mipsel/soft/main.c
===================================================================
--- branches/v4/platforms/caba-vgmn-memcache-mipsel/soft/main.c	(revision 371)
+++ branches/v4/platforms/caba-vgmn-memcache-mipsel/soft/main.c	(revision 371)
@@ -0,0 +1,1119 @@
+#include "system.h"
+#include "stdio.h"
+#include "stdlib.h"
+
+
+#include "../segmentation.h"
+
+#define NPROCS 4
+#define SIZE 2000
+#define SORT_TYPE 1
+
+volatile int lock=0;
+volatile int compteur=NPROCS;
+volatile int nprocs=NPROCS;
+
+volatile int write_boost[8*120];
+
+unsigned int gQSortNum0[8000] = {
+  251, 24, 113, 170, 215, 60, 83, 30, 115, 48, 169, 210, 49, 92, 101, 58, 21, 184, 225, 6,
+  199, 244, 227, 146, 99, 96, 25, 222, 65, 140, 213, 22, 219, 136, 175, 182, 73, 36, 141, 190, 
+  83, 112, 137, 114, 175, 188, 187, 102, 53, 168, 193, 154, 167, 172, 3, 242, 67, 64,144, 137,
+  142, 175, 188, 69, 102, 53, 168, 193, 102, 89, 172, 253, 242, 67,192, 7, 62, 159, 20, 181,
+  182, 187, 216, 207, 22, 105, 132, 109, 162, 205, 16, 151, 18, 113, 228, 37, 6, 85, 8, 161,
+  58, 135, 76, 35, 174, 35, 224, 39, 158, 127, 180, 149, 86, 155, 200, 239, 118, 119, 28, 77,
+  254, 19, 176, 183, 78, 145, 132, 5, 90, 117, 152, 127, 218, 153, 20, 67, 178, 3, 128, 185,
+  254, 95, 172, 139, 246, 123, 104, 15, 42, 169, 68, 211, 98, 243, 80, 41, 174, 79, 36, 27,
+  186, 149, 86, 155, 200, 239, 118, 119, 28, 77, 254, 19, 176, 183,78, 145, 132, 5, 90, 117,
+  152, 127, 218, 153, 20, 67, 178, 3, 128, 185, 254, 95, 172, 139, 246, 123, 104, 15, 42,169,
+  68, 211, 98, 243, 80, 41, 174, 79, 36, 27, 186, 107, 56, 97, 134, 71, 116, 157, 238, 227,
+  32, 153, 162, 193, 244, 171, 150, 165, 248, 209, 54, 55, 164, 13, 194, 45, 16, 247, 242, 47,
+  60, 59, 26, 75, 40, 65, 230, 217, 44, 131, 142, 195, 192, 121, 190, 225, 108, 203, 202, 197,
+  168, 177, 150, 233, 252, 19, 34, 77, 144, 23, 110, 15, 100, 91, 122, 213, 120, 223, 70, 7, 
+  52, 93, 46, 93, 160, 167, 226, 255, 204, 21, 42, 229, 72, 111, 246, 9, 100, 205, 126, 147,
+  215, 82, 79, 36, 229, 70, 149, 56, 159, 134, 185, 140, 99, 18, 29, 224, 153, 94, 63, 244, 85, 150, 91, 248, 209,
+  202, 55, 92, 243, 194, 211, 240, 247, 242, 209, 196, 197, 26, 75, 40, 191, 26, 39, 44, 131, 142, 195, 64, 121, 190,
+  231, 34, 65, 116, 43, 22, 219, 136, 175, 74, 73, 220, 141, 190, 83, 112, 137, 142, 81, 68, 69, 154, 203, 88, 63,
+  154, 89, 172, 3, 242, 67, 192, 249, 62, 159, 20, 181, 74, 69, 216, 49, 22, 105, 132, 109, 162, 205, 16, 151, 18,
+  37, 136, 175, 74, 183, 36, 115, 66, 173, 144, 137, 142, 175, 188, 69, 102, 53, 168, 193, 102, 89, 172, 253, 242, 67,
+  192, 7, 62, 159, 20, 181, 182, 187, 216, 207, 22, 105, 132, 109, 162, 205, 16, 151, 18, 113, 228, 37, 6, 85, 8,
+  161, 58, 135, 76, 35, 174, 35, 224, 39, 158, 127, 180, 149, 86, 155, 200, 239, 118, 119, 28, 77, 254, 19, 176, 183,
+  78, 145, 132, 5, 90, 117, 152, 127, 218, 153, 20, 67, 178, 3, 128, 185, 254, 95, 172, 139, 246, 123, 104, 15, 42,
+  251, 24, 113, 170, 215, 60, 83, 30, 115, 48, 169, 210, 49, 92, 101, 58, 21, 184, 225, 6,
+  199, 244, 227, 146, 99, 96, 25, 222, 65, 140, 213, 22, 219, 136, 175, 182, 73, 36, 141, 190, 
+  83, 112, 137, 114, 175, 188, 187, 102, 53, 168, 193, 154, 167, 172, 3, 242, 67, 64,144, 137,
+  142, 175, 188, 69, 102, 53, 168, 193, 102, 89, 172, 253, 242, 67,192, 7, 62, 159, 20, 181,
+  182, 187, 216, 207, 22, 105, 132, 109, 162, 205, 16, 151, 18, 113, 228, 37, 6, 85, 8, 161,
+  58, 135, 76, 35, 174, 35, 224, 39, 158, 127, 180, 149, 86, 155, 200, 239, 118, 119, 28, 77,
+  254, 19, 176, 183, 78, 145, 132, 5, 90, 117, 152, 127, 218, 153, 20, 67, 178, 3, 128, 185,
+  254, 95, 172, 139, 246, 123, 104, 15, 42, 169, 68, 211, 98, 243, 80, 41, 174, 79, 36, 27,
+  186, 149, 86, 155, 200, 239, 118, 119, 28, 77, 254, 19, 176, 183,78, 145, 132, 5, 90, 117,
+  152, 127, 218, 153, 20, 67, 178, 3, 128, 185, 254, 95, 172, 139, 246, 123, 104, 15, 42,169,
+  68, 211, 98, 243, 80, 41, 174, 79, 36, 27, 186, 107, 56, 97, 134, 71, 116, 157, 238, 227,
+  32, 153, 162, 193, 244, 171, 150, 165, 248, 209, 54, 55, 164, 13, 194, 45, 16, 247, 242, 47,
+  60, 59, 26, 75, 40, 65, 230, 217, 44, 131, 142, 195, 192, 121, 190, 225, 108, 203, 202, 197,
+  168, 177, 150, 233, 252, 19, 34, 77, 144, 23, 110, 15, 100, 91, 122, 213, 120, 223, 70, 7, 
+  52, 93, 46, 93, 160, 167, 226, 255, 204, 21, 42, 229, 72, 111, 246, 9, 100, 205, 126, 147,
+  215, 82, 79, 36, 229, 70, 149, 56, 159, 134, 185, 140, 99, 18, 29, 224, 153, 94, 63, 244, 85, 150, 91, 248, 209,
+  202, 55, 92, 243, 194, 211, 240, 247, 242, 209, 196, 197, 26, 75, 40, 191, 26, 39, 44, 131, 142, 195, 64, 121, 190,
+  231, 34, 65, 116, 43, 22, 219, 136, 175, 74, 73, 220, 141, 190, 83, 112, 137, 142, 81, 68, 69, 154, 203, 88, 63,
+  154, 89, 172, 3, 242, 67, 192, 249, 62, 159, 20, 181, 74, 69, 216, 49, 22, 105, 132, 109, 162, 205, 16, 151, 18,
+  37, 136, 175, 74, 183, 36, 115, 66, 173, 144, 137, 142, 175, 188, 69, 102, 53, 168, 193, 102, 89, 172, 253, 242, 67,
+  192, 7, 62, 159, 20, 181, 182, 187, 216, 207, 22, 105, 132, 109, 162, 205, 16, 151, 18, 113, 228, 37, 6, 85, 8,
+  161, 58, 135, 76, 35, 174, 35, 224, 39, 158, 127, 180, 149, 86, 155, 200, 239, 118, 119, 28, 77, 254, 19, 176, 183,
+  78, 145, 132, 5, 90, 117, 152, 127, 218, 153, 20, 67, 178, 3, 128, 185, 254, 95, 172, 139, 246, 123, 104, 15, 42,
+
+  251, 24, 113, 170, 215, 60, 83, 30, 115, 48, 169, 210, 49, 92, 101, 58, 21, 184, 225, 6,
+  199, 244, 227, 146, 99, 96, 25, 222, 65, 140, 213, 22, 219, 136, 175, 182, 73, 36, 141, 190, 
+  83, 112, 137, 114, 175, 188, 187, 102, 53, 168, 193, 154, 167, 172, 3, 242, 67, 64,144, 137,
+  142, 175, 188, 69, 102, 53, 168, 193, 102, 89, 172, 253, 242, 67,192, 7, 62, 159, 20, 181,
+  182, 187, 216, 207, 22, 105, 132, 109, 162, 205, 16, 151, 18, 113, 228, 37, 6, 85, 8, 161,
+  58, 135, 76, 35, 174, 35, 224, 39, 158, 127, 180, 149, 86, 155, 200, 239, 118, 119, 28, 77,
+  254, 19, 176, 183, 78, 145, 132, 5, 90, 117, 152, 127, 218, 153, 20, 67, 178, 3, 128, 185,
+  254, 95, 172, 139, 246, 123, 104, 15, 42, 169, 68, 211, 98, 243, 80, 41, 174, 79, 36, 27,
+  186, 149, 86, 155, 200, 239, 118, 119, 28, 77, 254, 19, 176, 183,78, 145, 132, 5, 90, 117,
+  152, 127, 218, 153, 20, 67, 178, 3, 128, 185, 254, 95, 172, 139, 246, 123, 104, 15, 42,169,
+  68, 211, 98, 243, 80, 41, 174, 79, 36, 27, 186, 107, 56, 97, 134, 71, 116, 157, 238, 227,
+  32, 153, 162, 193, 244, 171, 150, 165, 248, 209, 54, 55, 164, 13, 194, 45, 16, 247, 242, 47,
+  60, 59, 26, 75, 40, 65, 230, 217, 44, 131, 142, 195, 192, 121, 190, 225, 108, 203, 202, 197,
+  168, 177, 150, 233, 252, 19, 34, 77, 144, 23, 110, 15, 100, 91, 122, 213, 120, 223, 70, 7, 
+  52, 93, 46, 93, 160, 167, 226, 255, 204, 21, 42, 229, 72, 111, 246, 9, 100, 205, 126, 147,
+  215, 82, 79, 36, 229, 70, 149, 56, 159, 134, 185, 140, 99, 18, 29, 224, 153, 94, 63, 244, 85, 150, 91, 248, 209,
+  202, 55, 92, 243, 194, 211, 240, 247, 242, 209, 196, 197, 26, 75, 40, 191, 26, 39, 44, 131, 142, 195, 64, 121, 190,
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+  251, 24, 113, 170, 215, 60, 83, 30, 115, 48, 169, 210, 49, 92, 101, 58, 21, 184, 225, 6,
+  199, 244, 227, 146, 99, 96, 25, 222, 65, 140, 213, 22, 219, 136, 175, 182, 73, 36, 141, 190, 
+  83, 112, 137, 114, 175, 188, 187, 102, 53, 168, 193, 154, 167, 172, 3, 242, 67, 64,144, 137,
+  142, 175, 188, 69, 102, 53, 168, 193, 102, 89, 172, 253, 242, 67,192, 7, 62, 159, 20, 181,
+  182, 187, 216, 207, 22, 105, 132, 109, 162, 205, 16, 151, 18, 113, 228, 37, 6, 85, 8, 161,
+  58, 135, 76, 35, 174, 35, 224, 39, 158, 127, 180, 149, 86, 155, 200, 239, 118, 119, 28, 77,
+  254, 19, 176, 183, 78, 145, 132, 5, 90, 117, 152, 127, 218, 153, 20, 67, 178, 3, 128, 185,
+  254, 95, 172, 139, 246, 123, 104, 15, 42, 169, 68, 211, 98, 243, 80, 41, 174, 79, 36, 27,
+  186, 149, 86, 155, 200, 239, 118, 119, 28, 77, 254, 19, 176, 183,78, 145, 132, 5, 90, 117,
+  152, 127, 218, 153, 20, 67, 178, 3, 128, 185, 254, 95, 172, 139, 246, 123, 104, 15, 42,169,
+  68, 211, 98, 243, 80, 41, 174, 79, 36, 27, 186, 107, 56, 97, 134, 71, 116, 157, 238, 227,
+  32, 153, 162, 193, 244, 171, 150, 165, 248, 209, 54, 55, 164, 13, 194, 45, 16, 247, 242, 47,
+  60, 59, 26, 75, 40, 65, 230, 217, 44, 131, 142, 195, 192, 121, 190, 225, 108, 203, 202, 197,
+  168, 177, 150, 233, 252, 19, 34, 77, 144, 23, 110, 15, 100, 91, 122, 213, 120, 223, 70, 7, 
+  52, 93, 46, 93, 160, 167, 226, 255, 204, 21, 42, 229, 72, 111, 246, 9, 100, 205, 126, 147,
+  215, 82, 79, 36, 229, 70, 149, 56, 159, 134, 185, 140, 99, 18, 29, 224, 153, 94, 63, 244, 85, 150, 91, 248, 209,
+  202, 55, 92, 243, 194, 211, 240, 247, 242, 209, 196, 197, 26, 75, 40, 191, 26, 39, 44, 131, 142, 195, 64, 121, 190,
+  231, 34, 65, 116, 43, 22, 219, 136, 175, 74, 73, 220, 141, 190, 83, 112, 137, 142, 81, 68, 69, 154, 203, 88, 63,
+  154, 89, 172, 3, 242, 67, 192, 249, 62, 159, 20, 181, 74, 69, 216, 49, 22, 105, 132, 109, 162, 205, 16, 151, 18,
+  37, 136, 175, 74, 183, 36, 115, 66, 173, 144, 137, 142, 175, 188, 69, 102, 53, 168, 193, 102, 89, 172, 253, 242, 67,
+  192, 7, 62, 159, 20, 181, 182, 187, 216, 207, 22, 105, 132, 109, 162, 205, 16, 151, 18, 113, 228, 37, 6, 85, 8,
+  161, 58, 135, 76, 35, 174, 35, 224, 39, 158, 127, 180, 149, 86, 155, 200, 239, 118, 119, 28, 77, 254, 19, 176, 183,
+  78, 145, 132, 5, 90, 117, 152, 127, 218, 153, 20, 67, 178, 3, 128, 185, 254, 95, 172, 139, 246, 123, 104, 15, 42,
+  251, 24, 113, 170, 215, 60, 83, 30, 115, 48, 169, 210, 49, 92, 101, 58, 21, 184, 225, 6,
+  199, 244, 227, 146, 99, 96, 25, 222, 65, 140, 213, 22, 219, 136, 175, 182, 73, 36, 141, 190, 
+  83, 112, 137, 114, 175, 188, 187, 102, 53, 168, 193, 154, 167, 172, 3, 242, 67, 64,144, 137,
+  142, 175, 188, 69, 102, 53, 168, 193, 102, 89, 172, 253, 242, 67,192, 7, 62, 159, 20, 181,
+  182, 187, 216, 207, 22, 105, 132, 109, 162, 205, 16, 151, 18, 113, 228, 37, 6, 85, 8, 161,
+  58, 135, 76, 35, 174, 35, 224, 39, 158, 127, 180, 149, 86, 155, 200, 239, 118, 119, 28, 77,
+  254, 19, 176, 183, 78, 145, 132, 5, 90, 117, 152, 127, 218, 153, 20, 67, 178, 3, 128, 185,
+  254, 95, 172, 139, 246, 123, 104, 15, 42, 169, 68, 211, 98, 243, 80, 41, 174, 79, 36, 27,
+  186, 149, 86, 155, 200, 239, 118, 119, 28, 77, 254, 19, 176, 183,78, 145, 132, 5, 90, 117,
+  152, 127, 218, 153, 20, 67, 178, 3, 128, 185, 254, 95, 172, 139, 246, 123, 104, 15, 42,169,
+  68, 211, 98, 243, 80, 41, 174, 79, 36, 27, 186, 107, 56, 97, 134, 71, 116, 157, 238, 227,
+  32, 153, 162, 193, 244, 171, 150, 165, 248, 209, 54, 55, 164, 13, 194, 45, 16, 247, 242, 47,
+  60, 59, 26, 75, 40, 65, 230, 217, 44, 131, 142, 195, 192, 121, 190, 225, 108, 203, 202, 197,
+  168, 177, 150, 233, 252, 19, 34, 77, 144, 23, 110, 15, 100, 91, 122, 213, 120, 223, 70, 7, 
+  52, 93, 46, 93, 160, 167, 226, 255, 204, 21, 42, 229, 72, 111, 246, 9, 100, 205, 126, 147,
+  215, 82, 79, 36, 229, 70, 149, 56, 159, 134, 185, 140, 99, 18, 29, 224, 153, 94, 63, 244, 85, 150, 91, 248, 209,
+  202, 55, 92, 243, 194, 211, 240, 247, 242, 209, 196, 197, 26, 75, 40, 191, 26, 39, 44, 131, 142, 195, 64, 121, 190,
+  231, 34, 65, 116, 43, 22, 219, 136, 175, 74, 73, 220, 141, 190, 83, 112, 137, 142, 81, 68, 69, 154, 203, 88, 63,
+  154, 89, 172, 3, 242, 67, 192, 249, 62, 159, 20, 181, 74, 69, 216, 49, 22, 105, 132, 109, 162, 205, 16, 151, 18,
+  37, 136, 175, 74, 183, 36, 115, 66, 173, 144, 137, 142, 175, 188, 69, 102, 53, 168, 193, 102, 89, 172, 253, 242, 67,
+  192, 7, 62, 159, 20, 181, 182, 187, 216, 207, 22, 105, 132, 109, 162, 205, 16, 151, 18, 113, 228, 37, 6, 85, 8,
+  161, 58, 135, 76, 35, 174, 35, 224, 39, 158, 127, 180, 149, 86, 155, 200, 239, 118, 119, 28, 77, 254, 19, 176, 183,
+  78, 145, 132, 5, 90, 117, 152, 127, 218, 153, 20, 67, 178, 3, 128, 185, 254, 95, 172, 139, 246, 123, 104, 15, 42,
+
+  251, 24, 113, 170, 215, 60, 83, 30, 115, 48, 169, 210, 49, 92, 101, 58, 21, 184, 225, 6,
+  199, 244, 227, 146, 99, 96, 25, 222, 65, 140, 213, 22, 219, 136, 175, 182, 73, 36, 141, 190, 
+  83, 112, 137, 114, 175, 188, 187, 102, 53, 168, 193, 154, 167, 172, 3, 242, 67, 64,144, 137,
+  142, 175, 188, 69, 102, 53, 168, 193, 102, 89, 172, 253, 242, 67,192, 7, 62, 159, 20, 181,
+  182, 187, 216, 207, 22, 105, 132, 109, 162, 205, 16, 151, 18, 113, 228, 37, 6, 85, 8, 161,
+  58, 135, 76, 35, 174, 35, 224, 39, 158, 127, 180, 149, 86, 155, 200, 239, 118, 119, 28, 77,
+  254, 19, 176, 183, 78, 145, 132, 5, 90, 117, 152, 127, 218, 153, 20, 67, 178, 3, 128, 185,
+  254, 95, 172, 139, 246, 123, 104, 15, 42, 169, 68, 211, 98, 243, 80, 41, 174, 79, 36, 27,
+  186, 149, 86, 155, 200, 239, 118, 119, 28, 77, 254, 19, 176, 183,78, 145, 132, 5, 90, 117,
+  152, 127, 218, 153, 20, 67, 178, 3, 128, 185, 254, 95, 172, 139, 246, 123, 104, 15, 42,169,
+  68, 211, 98, 243, 80, 41, 174, 79, 36, 27, 186, 107, 56, 97, 134, 71, 116, 157, 238, 227,
+  32, 153, 162, 193, 244, 171, 150, 165, 248, 209, 54, 55, 164, 13, 194, 45, 16, 247, 242, 47,
+  60, 59, 26, 75, 40, 65, 230, 217, 44, 131, 142, 195, 192, 121, 190, 225, 108, 203, 202, 197,
+  168, 177, 150, 233, 252, 19, 34, 77, 144, 23, 110, 15, 100, 91, 122, 213, 120, 223, 70, 7, 
+  52, 93, 46, 93, 160, 167, 226, 255, 204, 21, 42, 229, 72, 111, 246, 9, 100, 205, 126, 147,
+  215, 82, 79, 36, 229, 70, 149, 56, 159, 134, 185, 140, 99, 18, 29, 224, 153, 94, 63, 244, 85, 150, 91, 248, 209,
+  202, 55, 92, 243, 194, 211, 240, 247, 242, 209, 196, 197, 26, 75, 40, 191, 26, 39, 44, 131, 142, 195, 64, 121, 190,
+  231, 34, 65, 116, 43, 22, 219, 136, 175, 74, 73, 220, 141, 190, 83, 112, 137, 142, 81, 68, 69, 154, 203, 88, 63,
+  154, 89, 172, 3, 242, 67, 192, 249, 62, 159, 20, 181, 74, 69, 216, 49, 22, 105, 132, 109, 162, 205, 16, 151, 18,
+  37, 136, 175, 74, 183, 36, 115, 66, 173, 144, 137, 142, 175, 188, 69, 102, 53, 168, 193, 102, 89, 172, 253, 242, 67,
+  192, 7, 62, 159, 20, 181, 182, 187, 216, 207, 22, 105, 132, 109, 162, 205, 16, 151, 18, 113, 228, 37, 6, 85, 8,
+  161, 58, 135, 76, 35, 174, 35, 224, 39, 158, 127, 180, 149, 86, 155, 200, 239, 118, 119, 28, 77, 254, 19, 176, 183,
+  78, 145, 132, 5, 90, 117, 152, 127, 218, 153, 20, 67, 178, 3, 128, 185, 254, 95, 172, 139, 246, 123, 104, 15, 42,
+  251, 24, 113, 170, 215, 60, 83, 30, 115, 48, 169, 210, 49, 92, 101, 58, 21, 184, 225, 6,
+  199, 244, 227, 146, 99, 96, 25, 222, 65, 140, 213, 22, 219, 136, 175, 182, 73, 36, 141, 190, 
+  83, 112, 137, 114, 175, 188, 187, 102, 53, 168, 193, 154, 167, 172, 3, 242, 67, 64,144, 137,
+  142, 175, 188, 69, 102, 53, 168, 193, 102, 89, 172, 253, 242, 67,192, 7, 62, 159, 20, 181,
+  182, 187, 216, 207, 22, 105, 132, 109, 162, 205, 16, 151, 18, 113, 228, 37, 6, 85, 8, 161,
+  58, 135, 76, 35, 174, 35, 224, 39, 158, 127, 180, 149, 86, 155, 200, 239, 118, 119, 28, 77,
+  254, 19, 176, 183, 78, 145, 132, 5, 90, 117, 152, 127, 218, 153, 20, 67, 178, 3, 128, 185,
+  254, 95, 172, 139, 246, 123, 104, 15, 42, 169, 68, 211, 98, 243, 80, 41, 174, 79, 36, 27,
+  186, 149, 86, 155, 200, 239, 118, 119, 28, 77, 254, 19, 176, 183,78, 145, 132, 5, 90, 117,
+  152, 127, 218, 153, 20, 67, 178, 3, 128, 185, 254, 95, 172, 139, 246, 123, 104, 15, 42,169,
+  68, 211, 98, 243, 80, 41, 174, 79, 36, 27, 186, 107, 56, 97, 134, 71, 116, 157, 238, 227,
+  32, 153, 162, 193, 244, 171, 150, 165, 248, 209, 54, 55, 164, 13, 194, 45, 16, 247, 242, 47,
+  60, 59, 26, 75, 40, 65, 230, 217, 44, 131, 142, 195, 192, 121, 190, 225, 108, 203, 202, 197,
+  168, 177, 150, 233, 252, 19, 34, 77, 144, 23, 110, 15, 100, 91, 122, 213, 120, 223, 70, 7, 
+  52, 93, 46, 93, 160, 167, 226, 255, 204, 21, 42, 229, 72, 111, 246, 9, 100, 205, 126, 147,
+  215, 82, 79, 36, 229, 70, 149, 56, 159, 134, 185, 140, 99, 18, 29, 224, 153, 94, 63, 244, 85, 150, 91, 248, 209,
+  202, 55, 92, 243, 194, 211, 240, 247, 242, 209, 196, 197, 26, 75, 40, 191, 26, 39, 44, 131, 142, 195, 64, 121, 190,
+  231, 34, 65, 116, 43, 22, 219, 136, 175, 74, 73, 220, 141, 190, 83, 112, 137, 142, 81, 68, 69, 154, 203, 88, 63,
+  154, 89, 172, 3, 242, 67, 192, 249, 62, 159, 20, 181, 74, 69, 216, 49, 22, 105, 132, 109, 162, 205, 16, 151, 18,
+  37, 136, 175, 74, 183, 36, 115, 66, 173, 144, 137, 142, 175, 188, 69, 102, 53, 168, 193, 102, 89, 172, 253, 242, 67,
+  192, 7, 62, 159, 20, 181, 182, 187, 216, 207, 22, 105, 132, 109, 162, 205, 16, 151, 18, 113, 228, 37, 6, 85, 8,
+  161, 58, 135, 76, 35, 174, 35, 224, 39, 158, 127, 180, 149, 86, 155, 200, 239, 118, 119, 28, 77, 254, 19, 176, 183,
+  78, 145, 132, 5, 90, 117, 152, 127, 218, 153, 20, 67, 178, 3, 128, 185, 254, 95, 172, 139, 246, 123, 104, 15, 42,
+  251, 24, 113, 170, 215, 60, 83, 30, 115, 48, 169, 210, 49, 92, 101, 58, 21, 184, 225, 6,
+  199, 244, 227, 146, 99, 96, 25, 222, 65, 140, 213, 22, 219, 136, 175, 182, 73, 36, 141, 190, 
+  83, 112, 137, 114, 175, 188, 187, 102, 53, 168, 193, 154, 167, 172, 3, 242, 67, 64,144, 137,
+  142, 175, 188, 69, 102, 53, 168, 193, 102, 89, 172, 253, 242, 67,192, 7, 62, 159, 20, 181,
+  182, 187, 216, 207, 22, 105, 132, 109, 162, 205, 16, 151, 18, 113, 228, 37, 6, 85, 8, 161,
+  58, 135, 76, 35, 174, 35, 224, 39, 158, 127, 180, 149, 86, 155, 200, 239, 118, 119, 28, 77,
+  254, 19, 176, 183, 78, 145, 132, 5, 90, 117, 152, 127, 218, 153, 20, 67, 178, 3, 128, 185,
+  254, 95, 172, 139, 246, 123, 104, 15, 42, 169, 68, 211, 98, 243, 80, 41, 174, 79, 36, 27,
+  186, 149, 86, 155, 200, 239, 118, 119, 28, 77, 254, 19, 176, 183,78, 145, 132, 5, 90, 117,
+  152, 127, 218, 153, 20, 67, 178, 3, 128, 185, 254, 95, 172, 139, 246, 123, 104, 15, 42,169,
+  68, 211, 98, 243, 80, 41, 174, 79, 36, 27, 186, 107, 56, 97, 134, 71, 116, 157, 238, 227,
+  32, 153, 162, 193, 244, 171, 150, 165, 248, 209, 54, 55, 164, 13, 194, 45, 16, 247, 242, 47,
+  60, 59, 26, 75, 40, 65, 230, 217, 44, 131, 142, 195, 192, 121, 190, 225, 108, 203, 202, 197,
+  168, 177, 150, 233, 252, 19, 34, 77, 144, 23, 110, 15, 100, 91, 122, 213, 120, 223, 70, 7, 
+  52, 93, 46, 93, 160, 167, 226, 255, 204, 21, 42, 229, 72, 111, 246, 9, 100, 205, 126, 147,
+  215, 82, 79, 36, 229, 70, 149, 56, 159, 134, 185, 140, 99, 18, 29, 224, 153, 94, 63, 244, 85, 150, 91, 248, 209,
+  202, 55, 92, 243, 194, 211, 240, 247, 242, 209, 196, 197, 26, 75, 40, 191, 26, 39, 44, 131, 142, 195, 64, 121, 190,
+  231, 34, 65, 116, 43, 22, 219, 136, 175, 74, 73, 220, 141, 190, 83, 112, 137, 142, 81, 68, 69, 154, 203, 88, 63,
+  154, 89, 172, 3, 242, 67, 192, 249, 62, 159, 20, 181, 74, 69, 216, 49, 22, 105, 132, 109, 162, 205, 16, 151, 18,
+  37, 136, 175, 74, 183, 36, 115, 66, 173, 144, 137, 142, 175, 188, 69, 102, 53, 168, 193, 102, 89, 172, 253, 242, 67,
+  192, 7, 62, 159, 20, 181, 182, 187, 216, 207, 22, 105, 132, 109, 162, 205, 16, 151, 18, 113, 228, 37, 6, 85, 8,
+  161, 58, 135, 76, 35, 174, 35, 224, 39, 158, 127, 180, 149, 86, 155, 200, 239, 118, 119, 28, 77, 254, 19, 176, 183,
+  78, 145, 132, 5, 90, 117, 152, 127, 218, 153, 20, 67, 178, 3, 128, 185, 254, 95, 172, 139, 246, 123, 104, 15, 42,
+  251, 24, 113, 170, 215, 60, 83, 30, 115, 48, 169, 210, 49, 92, 101, 58, 21, 184, 225, 6,
+  199, 244, 227, 146, 99, 96, 25, 222, 65, 140, 213, 22, 219, 136, 175, 182, 73, 36, 141, 190, 
+  83, 112, 137, 114, 175, 188, 187, 102, 53, 168, 193, 154, 167, 172, 3, 242, 67, 64,144, 137,
+  142, 175, 188, 69, 102, 53, 168, 193, 102, 89, 172, 253, 242, 67,192, 7, 62, 159, 20, 181,
+  182, 187, 216, 207, 22, 105, 132, 109, 162, 205, 16, 151, 18, 113, 228, 37, 6, 85, 8, 161,
+  58, 135, 76, 35, 174, 35, 224, 39, 158, 127, 180, 149, 86, 155, 200, 239, 118, 119, 28, 77,
+  254, 19, 176, 183, 78, 145, 132, 5, 90, 117, 152, 127, 218, 153, 20, 67, 178, 3, 128, 185,
+  254, 95, 172, 139, 246, 123, 104, 15, 42, 169, 68, 211, 98, 243, 80, 41, 174, 79, 36, 27,
+  186, 149, 86, 155, 200, 239, 118, 119, 28, 77, 254, 19, 176, 183,78, 145, 132, 5, 90, 117,
+  152, 127, 218, 153, 20, 67, 178, 3, 128, 185, 254, 95, 172, 139, 246, 123, 104, 15, 42,169,
+  68, 211, 98, 243, 80, 41, 174, 79, 36, 27, 186, 107, 56, 97, 134, 71, 116, 157, 238, 227,
+  32, 153, 162, 193, 244, 171, 150, 165, 248, 209, 54, 55, 164, 13, 194, 45, 16, 247, 242, 47,
+  60, 59, 26, 75, 40, 65, 230, 217, 44, 131, 142, 195, 192, 121, 190, 225, 108, 203, 202, 197,
+  168, 177, 150, 233, 252, 19, 34, 77, 144, 23, 110, 15, 100, 91, 122, 213, 120, 223, 70, 7, 
+  52, 93, 46, 93, 160, 167, 226, 255, 204, 21, 42, 229, 72, 111, 246, 9, 100, 205, 126, 147,
+  215, 82, 79, 36, 229, 70, 149, 56, 159, 134, 185, 140, 99, 18, 29, 224, 153, 94, 63, 244, 85, 150, 91, 248, 209,
+  202, 55, 92, 243, 194, 211, 240, 247, 242, 209, 196, 197, 26, 75, 40, 191, 26, 39, 44, 131, 142, 195, 64, 121, 190,
+  231, 34, 65, 116, 43, 22, 219, 136, 175, 74, 73, 220, 141, 190, 83, 112, 137, 142, 81, 68, 69, 154, 203, 88, 63,
+  154, 89, 172, 3, 242, 67, 192, 249, 62, 159, 20, 181, 74, 69, 216, 49, 22, 105, 132, 109, 162, 205, 16, 151, 18,
+  37, 136, 175, 74, 183, 36, 115, 66, 173, 144, 137, 142, 175, 188, 69, 102, 53, 168, 193, 102, 89, 172, 253, 242, 67,
+  192, 7, 62, 159, 20, 181, 182, 187, 216, 207, 22, 105, 132, 109, 162, 205, 16, 151, 18, 113, 228, 37, 6, 85, 8,
+  161, 58, 135, 76, 35, 174, 35, 224, 39, 158, 127, 180, 149, 86, 155, 200, 239, 118, 119, 28, 77, 254, 19, 176, 183,
+  78, 145, 132, 5, 90, 117, 152, 127, 218, 153, 20, 67, 178, 3, 128, 185, 254, 95, 172, 139, 246, 123, 104, 15, 42
+  
+};
+
+/*
+
+unsigned int gQSortNum1[8000] = {
+  57, 126, 223, 44, 11, 138, 251, 232, 143, 86, 215, 60, 83, 30, 115, 48, 87, 46, 49, 164, 101, 198, 235, 72, 31,
+  6, 57, 12, 227, 110, 157, 96, 25, 34, 191, 140, 43, 22, 37, 136, 175, 182, 183, 220, 115, 66, 173, 144, 137, 114,
+  81, 68, 69, 102, 203, 168, 193, 102, 167, 172, 3, 14, 67, 64, 249, 62, 159, 20, 75, 74, 187, 216, 207, 22, 151,
+  124, 109, 162, 51, 16, 151, 18, 143, 28, 37, 250, 171, 8, 95, 58, 135, 76, 221, 82, 221, 224, 217, 158, 127, 76,
+  107, 170, 155, 200, 239, 138, 119, 228, 77, 2, 237, 176, 183, 178, 111, 132, 5, 166, 139, 104, 129, 218, 103, 20, 189,
+  78, 3, 128, 185, 2, 95, 172, 139, 10, 123, 104, 241, 214, 169, 188, 211, 98, 13, 80, 41, 82, 177, 220, 229, 186,
+  149, 200, 159, 134, 71, 116, 99, 18, 29, 224, 103, 162, 193, 12, 171, 150, 165, 248, 209, 202, 201, 92, 13, 62, 211,
+  16, 247, 14, 209, 60, 59, 26, 181, 40, 191, 230, 39, 44, 125, 114, 195, 64, 135, 190, 225, 148, 53, 202, 197, 168,
+  79, 106, 23, 4, 19, 34, 77, 144, 23, 146, 241, 156, 91, 122, 43, 136, 223, 70, 249, 52, 163, 46, 93, 96, 89,
+  30, 255, 52, 21, 214, 229, 72, 111, 10, 9, 156, 205, 126, 147, 48, 55, 50, 239, 252, 133, 38, 11, 232, 1, 166,
+  25, 108, 61, 206, 125, 0, 199, 126, 223, 44, 11, 118, 251, 24, 113, 170, 215, 60, 83, 30, 115, 48, 169, 210, 49,
+  92, 101, 58, 21, 184, 225, 6, 199, 244, 227, 146, 99, 96, 25, 222, 65, 140, 213, 22, 219, 136, 175, 182, 73, 36,
+  141, 190, 83, 112, 137, 114, 175, 188, 187, 102, 53, 168, 193, 154, 167, 172, 3, 242, 67, 64, 7, 62, 159, 236, 75,
+  182, 187, 40, 49, 234, 105, 124, 109, 162, 205, 16, 105, 238, 143, 28, 37, 6, 85, 248, 161, 58, 121, 180, 221, 174,
+  221, 32, 217, 98, 129, 76, 149, 170, 101, 200, 239, 118, 137, 28, 179, 254, 19, 80, 183, 178, 145, 124, 251, 166, 139,
+  152, 129, 38, 153, 20, 189, 78, 3, 128, 71, 254, 95, 84, 139, 10, 123, 152, 241, 214, 169, 68, 211, 98, 13, 80,
+  215, 82, 79, 36, 229, 70, 149, 56, 159, 134, 185, 140, 99, 18, 29, 224, 153, 94, 63, 244, 85, 150, 91, 248, 209,
+  202, 55, 92, 243, 194, 211, 240, 247, 242, 209, 196, 197, 26, 75, 40, 191, 26, 39, 44, 131, 142, 195, 64, 121, 190,
+  225, 148, 53, 54, 197, 88, 79, 106, 233, 252, 19, 34, 77, 144, 233, 146, 241, 100, 91, 134, 43, 136, 33, 70, 249,
+  204, 163, 210, 163, 96, 89, 226, 1, 52, 235, 214, 27, 72, 111, 246, 247, 156, 51, 130, 109, 208, 55, 50, 17, 252,
+  123, 218, 245, 232, 255, 90, 231, 108, 195, 50, 125, 0, 199, 130, 223, 212, 11, 138, 251, 232, 143, 86, 215, 196, 83,
+  30, 141, 48, 87, 46, 207, 92, 155, 58, 235, 184, 31, 6, 199, 12, 29, 146, 157, 160, 231, 34, 191, 116, 213, 22,
+  37, 136, 175, 74, 183, 36, 115, 66, 173, 144, 137, 142, 175, 188, 69, 102, 53, 168, 193, 102, 89, 172, 253, 242, 67,
+  192, 7, 62, 159, 20, 181, 182, 187, 216, 207, 22, 105, 132, 109, 162, 205, 16, 151, 18, 113, 228, 37, 6, 85, 8,
+  161, 58, 135, 76, 35, 174, 35, 224, 39, 158, 127, 180, 149, 86, 155, 200, 239, 118, 119, 28, 77, 254, 19, 176, 183,
+  78, 145, 132, 5, 90, 117, 152, 127, 218, 153, 20, 67, 178, 3, 128, 185, 254, 95, 172, 139, 246, 123, 104, 15, 42,
+  169, 68, 211, 98, 243, 80, 41, 174, 79, 36, 27, 186, 107, 56, 97, 134, 71, 116, 157, 238, 227, 32, 153, 162, 193,
+  244, 171, 150, 165, 248, 209, 54, 55, 164, 13, 194, 45, 16, 247, 242, 47, 60, 59, 26, 75, 40, 65, 230, 217, 44,
+  131, 142, 195, 192, 121, 190, 225, 108, 203, 202, 197, 168, 177, 150, 233, 252, 19, 34, 77, 144, 23, 110, 15, 100, 91,
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+  215, 82, 79, 36, 229, 70, 149, 56, 159, 134, 185, 140, 99, 18, 29, 224, 153, 94, 63, 244, 85, 150, 91, 248, 209,
+  202, 55, 92, 243, 194, 211, 240, 247, 242, 209, 196, 197, 26, 75, 40, 191, 26, 39, 44, 131, 142, 195, 64, 121, 190,
+  225, 148, 53, 54, 197, 88, 79, 106, 233, 252, 19, 34, 77, 144, 233, 146, 241, 100, 91, 134, 43, 136, 33, 70, 249,
+  204, 163, 210, 163, 96, 89, 226, 1, 52, 235, 214, 27, 72, 111, 246, 247, 156, 51, 130, 109, 208, 55, 50, 17, 252,
+  123, 218, 245, 232, 255, 90, 231, 108, 195, 50, 125, 0, 199, 130, 223, 212, 11, 138, 251, 232, 143, 86, 215, 196, 83,
+  30, 141, 48, 87, 46, 207, 92, 155, 58, 235, 184, 31, 6, 199, 12, 29, 146, 157, 160, 231, 34, 191, 116, 213, 22,
+  37, 136, 175, 74, 183, 36, 115, 66, 173, 144, 137, 142, 175, 188, 69, 102, 53, 168, 193, 102, 89, 172, 253, 242, 67,
+  192, 7, 62, 159, 20, 181, 182, 187, 216, 207, 22, 105, 132, 109, 162, 205, 16, 151, 18, 113, 228, 37, 6, 85, 8,
+  161, 58, 135, 76, 35, 174, 35, 224, 39, 158, 127, 180, 149, 86, 155, 200, 239, 118, 119, 28, 77, 254, 19, 176, 183,
+  78, 145, 132, 5, 90, 117, 152, 127, 218, 153, 20, 67, 178, 3, 128, 185, 254, 95, 172, 139, 246, 123, 104, 15, 42,
+  169, 68, 211, 98, 243, 80, 41, 174, 79, 36, 27, 186, 107, 56, 97, 134, 71, 116, 157, 238, 227, 32, 153, 162, 193,
+  244, 171, 150, 165, 248, 209, 54, 55, 164, 13, 194, 45, 16, 247, 242, 47, 60, 59, 26, 75, 40, 65, 230, 217, 44,
+  131, 142, 195, 192, 121, 190, 225, 108, 203, 202, 197, 168, 177, 150, 233, 252, 19, 34, 77, 144, 23, 110, 15, 100, 91,
+  122, 213, 120, 223, 70, 7, 52, 93, 46, 93, 160, 167, 226, 255, 204, 21, 42, 229, 72, 111, 246, 9, 100, 205, 126,
+  147, 48, 55, 206, 239, 4, 133, 218, 245, 232, 255, 166, 231, 108, 195, 50, 131, 0, 57, 130, 223, 44, 245, 118, 251,
+  232, 113, 86, 215, 196, 83, 30, 141, 48, 87, 46, 207, 92, 155, 198, 235, 72, 31, 250, 57, 244, 29, 110, 99, 160,
+  231, 34, 65, 116, 43, 22, 219, 136, 175, 74, 73, 220, 141, 190, 83, 112, 137, 142, 81, 68, 69, 154, 203, 88, 63,
+  154, 89, 172, 3, 242, 67, 192, 249, 62, 159, 20, 181, 74, 69, 216, 49, 22, 105, 132, 109, 162, 205, 16, 151, 18,
+  113, 228, 219, 
+250, 171, 8, 95, 58, 135, 180, 35, 82, 221, 224, 39, 98, 129, 180, 107, 86, 101, 200, 239, 118, 119,
+  228, 179, 2, 237, 80, 183, 78, 111, 124, 5, 90, 117, 104, 127, 38, 153, 20, 67, 178, 253, 128, 185, 254, 95, 172,
+  117, 10, 123, 152, 241, 42, 87, 188, 211, 98, 243, 80, 215, 82, 79, 36, 27, 186, 107, 200, 159, 122, 71, 140, 157,
+  238, 29, 224, 153, 94, 63, 244, 85, 106, 91, 248, 47, 54, 201, 164, 243, 62, 211, 240, 247, 242, 47, 196, 197, 230,
+  181, 216, 65, 26, 217, 44, 125, 114, 195, 192, 135, 190, 31, 148, 203, 202, 59, 88, 79, 150, 233, 252, 19, 34, 77,
+  144, 233, 146, 15, 100, 165, 122, 213, 136, 223, 70, 249, 204, 93, 46, 93, 96, 167, 30, 1, 204, 21, 42, 27, 72,
+
+  57, 126, 223, 44, 11, 138, 251, 232, 143, 86, 215, 60, 83, 30, 115, 48, 87, 46, 49, 164, 101, 198, 235, 72, 31,
+  6, 57, 12, 227, 110, 157, 96, 25, 34, 191, 140, 43, 22, 37, 136, 175, 182, 183, 220, 115, 66, 173, 144, 137, 114,
+  81, 68, 69, 102, 203, 168, 193, 102, 167, 172, 3, 14, 67, 64, 249, 62, 159, 20, 75, 74, 187, 216, 207, 22, 151,
+  124, 109, 162, 51, 16, 151, 18, 143, 28, 37, 250, 171, 8, 95, 58, 135, 76, 221, 82, 221, 224, 217, 158, 127, 76,
+  107, 170, 155, 200, 239, 138, 119, 228, 77, 2, 237, 176, 183, 178, 111, 132, 5, 166, 139, 104, 129, 218, 103, 20, 189,
+  78, 3, 128, 185, 2, 95, 172, 139, 10, 123, 104, 241, 214, 169, 188, 211, 98, 13, 80, 41, 82, 177, 220, 229, 186,
+  149, 200, 159, 134, 71, 116, 99, 18, 29, 224, 103, 162, 193, 12, 171, 150, 165, 248, 209, 202, 201, 92, 13, 62, 211,
+  16, 247, 14, 209, 60, 59, 26, 181, 40, 191, 230, 39, 44, 125, 114, 195, 64, 135, 190, 225, 148, 53, 202, 197, 168,
+  79, 106, 23, 4, 19, 34, 77, 144, 23, 146, 241, 156, 91, 122, 43, 136, 223, 70, 249, 52, 163, 46, 93, 96, 89,
+  30, 255, 52, 21, 214, 229, 72, 111, 10, 9, 156, 205, 126, 147, 48, 55, 50, 239, 252, 133, 38, 11, 232, 1, 166,
+  25, 108, 61, 206, 125, 0, 199, 126, 223, 44, 11, 118, 251, 24, 113, 170, 215, 60, 83, 30, 115, 48, 169, 210, 49,
+  92, 101, 58, 21, 184, 225, 6, 199, 244, 227, 146, 99, 96, 25, 222, 65, 140, 213, 22, 219, 136, 175, 182, 73, 36,
+  141, 190, 83, 112, 137, 114, 175, 188, 187, 102, 53, 168, 193, 154, 167, 172, 3, 242, 67, 64, 7, 62, 159, 236, 75,
+  182, 187, 40, 49, 234, 105, 124, 109, 162, 205, 16, 105, 238, 143, 28, 37, 6, 85, 248, 161, 58, 121, 180, 221, 174,
+  221, 32, 217, 98, 129, 76, 149, 170, 101, 200, 239, 118, 137, 28, 179, 254, 19, 80, 183, 178, 145, 124, 251, 166, 139,
+  152, 129, 38, 153, 20, 189, 78, 3, 128, 71, 254, 95, 84, 139, 10, 123, 152, 241, 214, 169, 68, 211, 98, 13, 80,
+  215, 82, 79, 36, 229, 70, 149, 56, 159, 134, 185, 140, 99, 18, 29, 224, 153, 94, 63, 244, 85, 150, 91, 248, 209,
+  202, 55, 92, 243, 194, 211, 240, 247, 242, 209, 196, 197, 26, 75, 40, 191, 26, 39, 44, 131, 142, 195, 64, 121, 190,
+  225, 148, 53, 54, 197, 88, 79, 106, 233, 252, 19, 34, 77, 144, 233, 146, 241, 100, 91, 134, 43, 136, 33, 70, 249,
+  204, 163, 210, 163, 96, 89, 226, 1, 52, 235, 214, 27, 72, 111, 246, 247, 156, 51, 130, 109, 208, 55, 50, 17, 252,
+  123, 218, 245, 232, 255, 90, 231, 108, 195, 50, 125, 0, 199, 130, 223, 212, 11, 138, 251, 232, 143, 86, 215, 196, 83,
+  30, 141, 48, 87, 46, 207, 92, 155, 58, 235, 184, 31, 6, 199, 12, 29, 146, 157, 160, 231, 34, 191, 116, 213, 22,
+  37, 136, 175, 74, 183, 36, 115, 66, 173, 144, 137, 142, 175, 188, 69, 102, 53, 168, 193, 102, 89, 172, 253, 242, 67,
+  192, 7, 62, 159, 20, 181, 182, 187, 216, 207, 22, 105, 132, 109, 162, 205, 16, 151, 18, 113, 228, 37, 6, 85, 8,
+  161, 58, 135, 76, 35, 174, 35, 224, 39, 158, 127, 180, 149, 86, 155, 200, 239, 118, 119, 28, 77, 254, 19, 176, 183,
+  78, 145, 132, 5, 90, 117, 152, 127, 218, 153, 20, 67, 178, 3, 128, 185, 254, 95, 172, 139, 246, 123, 104, 15, 42,
+  169, 68, 211, 98, 243, 80, 41, 174, 79, 36, 27, 186, 107, 56, 97, 134, 71, 116, 157, 238, 227, 32, 153, 162, 193,
+  244, 171, 150, 165, 248, 209, 54, 55, 164, 13, 194, 45, 16, 247, 242, 47, 60, 59, 26, 75, 40, 65, 230, 217, 44,
+  131, 142, 195, 192, 121, 190, 225, 108, 203, 202, 197, 168, 177, 150, 233, 252, 19, 34, 77, 144, 23, 110, 15, 100, 91,
+  122, 213, 120, 223, 70, 7, 52, 93, 46, 93, 160, 167, 226, 255, 204, 21, 42, 229, 72, 111, 246, 9, 100, 205, 126,
+  147, 48, 55, 206, 239, 4, 133, 218, 245, 232, 255, 166, 231, 108, 195, 50, 131, 0, 57, 130, 223, 44, 245, 118, 251,
+  232, 113, 86, 215, 196, 83, 30, 141, 48, 87, 46, 207, 92, 155, 198, 235, 72, 31, 250, 57, 244, 29, 110, 99, 160,
+  231, 34, 65, 116, 43, 22, 219, 136, 175, 74, 73, 220, 141, 190, 83, 112, 137, 142, 81, 68, 69, 154, 203, 88, 63,
+  154, 89, 172, 3, 242, 67, 192, 249, 62, 159, 20, 181, 74, 69, 216, 49, 22, 105, 132, 109, 162, 205, 16, 151, 18,
+  113, 228, 219, 
+250, 171, 8, 95, 58, 135, 180, 35, 82, 221, 224, 39, 98, 129, 180, 107, 86, 101, 200, 239, 118, 119,
+  228, 179, 2, 237, 80, 183, 78, 111, 124, 5, 90, 117, 104, 127, 38, 153, 20, 67, 178, 253, 128, 185, 254, 95, 172,
+  117, 10, 123, 152, 241, 42, 87, 188, 211, 98, 243, 80, 215, 82, 79, 36, 27, 186, 107, 200, 159, 122, 71, 140, 157,
+  238, 29, 224, 153, 94, 63, 244, 85, 106, 91, 248, 47, 54, 201, 164, 243, 62, 211, 240, 247, 242, 47, 196, 197, 230,
+  181, 216, 65, 26, 217, 44, 125, 114, 195, 192, 135, 190, 31, 148, 203, 202, 59, 88, 79, 150, 233, 252, 19, 34, 77,
+  144, 233, 146, 15, 100, 165, 122, 213, 136, 223, 70, 249, 204, 93, 46, 93, 96, 167, 30, 1, 204, 21, 42, 27, 72,
+
+  57, 126, 223, 44, 11, 138, 251, 232, 143, 86, 215, 60, 83, 30, 115, 48, 87, 46, 49, 164, 101, 198, 235, 72, 31,
+  6, 57, 12, 227, 110, 157, 96, 25, 34, 191, 140, 43, 22, 37, 136, 175, 182, 183, 220, 115, 66, 173, 144, 137, 114,
+  81, 68, 69, 102, 203, 168, 193, 102, 167, 172, 3, 14, 67, 64, 249, 62, 159, 20, 75, 74, 187, 216, 207, 22, 151,
+  124, 109, 162, 51, 16, 151, 18, 143, 28, 37, 250, 171, 8, 95, 58, 135, 76, 221, 82, 221, 224, 217, 158, 127, 76,
+  107, 170, 155, 200, 239, 138, 119, 228, 77, 2, 237, 176, 183, 178, 111, 132, 5, 166, 139, 104, 129, 218, 103, 20, 189,
+  78, 3, 128, 185, 2, 95, 172, 139, 10, 123, 104, 241, 214, 169, 188, 211, 98, 13, 80, 41, 82, 177, 220, 229, 186,
+  149, 200, 159, 134, 71, 116, 99, 18, 29, 224, 103, 162, 193, 12, 171, 150, 165, 248, 209, 202, 201, 92, 13, 62, 211,
+  16, 247, 14, 209, 60, 59, 26, 181, 40, 191, 230, 39, 44, 125, 114, 195, 64, 135, 190, 225, 148, 53, 202, 197, 168,
+  79, 106, 23, 4, 19, 34, 77, 144, 23, 146, 241, 156, 91, 122, 43, 136, 223, 70, 249, 52, 163, 46, 93, 96, 89,
+  30, 255, 52, 21, 214, 229, 72, 111, 10, 9, 156, 205, 126, 147, 48, 55, 50, 239, 252, 133, 38, 11, 232, 1, 166,
+  25, 108, 61, 206, 125, 0, 199, 126, 223, 44, 11, 118, 251, 24, 113, 170, 215, 60, 83, 30, 115, 48, 169, 210, 49,
+  92, 101, 58, 21, 184, 225, 6, 199, 244, 227, 146, 99, 96, 25, 222, 65, 140, 213, 22, 219, 136, 175, 182, 73, 36,
+  141, 190, 83, 112, 137, 114, 175, 188, 187, 102, 53, 168, 193, 154, 167, 172, 3, 242, 67, 64, 7, 62, 159, 236, 75,
+  182, 187, 40, 49, 234, 105, 124, 109, 162, 205, 16, 105, 238, 143, 28, 37, 6, 85, 248, 161, 58, 121, 180, 221, 174,
+  221, 32, 217, 98, 129, 76, 149, 170, 101, 200, 239, 118, 137, 28, 179, 254, 19, 80, 183, 178, 145, 124, 251, 166, 139,
+  152, 129, 38, 153, 20, 189, 78, 3, 128, 71, 254, 95, 84, 139, 10, 123, 152, 241, 214, 169, 68, 211, 98, 13, 80,
+  215, 82, 79, 36, 229, 70, 149, 56, 159, 134, 185, 140, 99, 18, 29, 224, 153, 94, 63, 244, 85, 150, 91, 248, 209,
+  202, 55, 92, 243, 194, 211, 240, 247, 242, 209, 196, 197, 26, 75, 40, 191, 26, 39, 44, 131, 142, 195, 64, 121, 190,
+  225, 148, 53, 54, 197, 88, 79, 106, 233, 252, 19, 34, 77, 144, 233, 146, 241, 100, 91, 134, 43, 136, 33, 70, 249,
+  204, 163, 210, 163, 96, 89, 226, 1, 52, 235, 214, 27, 72, 111, 246, 247, 156, 51, 130, 109, 208, 55, 50, 17, 252,
+  123, 218, 245, 232, 255, 90, 231, 108, 195, 50, 125, 0, 199, 130, 223, 212, 11, 138, 251, 232, 143, 86, 215, 196, 83,
+  30, 141, 48, 87, 46, 207, 92, 155, 58, 235, 184, 31, 6, 199, 12, 29, 146, 157, 160, 231, 34, 191, 116, 213, 22,
+  37, 136, 175, 74, 183, 36, 115, 66, 173, 144, 137, 142, 175, 188, 69, 102, 53, 168, 193, 102, 89, 172, 253, 242, 67,
+  192, 7, 62, 159, 20, 181, 182, 187, 216, 207, 22, 105, 132, 109, 162, 205, 16, 151, 18, 113, 228, 37, 6, 85, 8,
+  161, 58, 135, 76, 35, 174, 35, 224, 39, 158, 127, 180, 149, 86, 155, 200, 239, 118, 119, 28, 77, 254, 19, 176, 183,
+  78, 145, 132, 5, 90, 117, 152, 127, 218, 153, 20, 67, 178, 3, 128, 185, 254, 95, 172, 139, 246, 123, 104, 15, 42,
+  169, 68, 211, 98, 243, 80, 41, 174, 79, 36, 27, 186, 107, 56, 97, 134, 71, 116, 157, 238, 227, 32, 153, 162, 193,
+  244, 171, 150, 165, 248, 209, 54, 55, 164, 13, 194, 45, 16, 247, 242, 47, 60, 59, 26, 75, 40, 65, 230, 217, 44,
+  131, 142, 195, 192, 121, 190, 225, 108, 203, 202, 197, 168, 177, 150, 233, 252, 19, 34, 77, 144, 23, 110, 15, 100, 91,
+  122, 213, 120, 223, 70, 7, 52, 93, 46, 93, 160, 167, 226, 255, 204, 21, 42, 229, 72, 111, 246, 9, 100, 205, 126,
+  147, 48, 55, 206, 239, 4, 133, 218, 245, 232, 255, 166, 231, 108, 195, 50, 131, 0, 57, 130, 223, 44, 245, 118, 251,
+  232, 113, 86, 215, 196, 83, 30, 141, 48, 87, 46, 207, 92, 155, 198, 235, 72, 31, 250, 57, 244, 29, 110, 99, 160,
+  231, 34, 65, 116, 43, 22, 219, 136, 175, 74, 73, 220, 141, 190, 83, 112, 137, 142, 81, 68, 69, 154, 203, 88, 63,
+  154, 89, 172, 3, 242, 67, 192, 249, 62, 159, 20, 181, 74, 69, 216, 49, 22, 105, 132, 109, 162, 205, 16, 151, 18,
+  113, 228, 219, 
+250, 171, 8, 95, 58, 135, 180, 35, 82, 221, 224, 39, 98, 129, 180, 107, 86, 101, 200, 239, 118, 119,
+  228, 179, 2, 237, 80, 183, 78, 111, 124, 5, 90, 117, 104, 127, 38, 153, 20, 67, 178, 253, 128, 185, 254, 95, 172,
+  117, 10, 123, 152, 241, 42, 87, 188, 211, 98, 243, 80, 215, 82, 79, 36, 27, 186, 107, 200, 159, 122, 71, 140, 157,
+  238, 29, 224, 153, 94, 63, 244, 85, 106, 91, 248, 47, 54, 201, 164, 243, 62, 211, 240, 247, 242, 47, 196, 197, 230,
+  181, 216, 65, 26, 217, 44, 125, 114, 195, 192, 135, 190, 31, 148, 203, 202, 59, 88, 79, 150, 233, 252, 19, 34, 77,
+  144, 233, 146, 15, 100, 165, 122, 213, 136, 223, 70, 249, 204, 93, 46, 93, 96, 167, 30, 1, 204, 21, 42, 27, 72,
+
+  57, 126, 223, 44, 11, 138, 251, 232, 143, 86, 215, 60, 83, 30, 115, 48, 87, 46, 49, 164, 101, 198, 235, 72, 31,
+  6, 57, 12, 227, 110, 157, 96, 25, 34, 191, 140, 43, 22, 37, 136, 175, 182, 183, 220, 115, 66, 173, 144, 137, 114,
+  81, 68, 69, 102, 203, 168, 193, 102, 167, 172, 3, 14, 67, 64, 249, 62, 159, 20, 75, 74, 187, 216, 207, 22, 151,
+  124, 109, 162, 51, 16, 151, 18, 143, 28, 37, 250, 171, 8, 95, 58, 135, 76, 221, 82, 221, 224, 217, 158, 127, 76,
+  107, 170, 155, 200, 239, 138, 119, 228, 77, 2, 237, 176, 183, 178, 111, 132, 5, 166, 139, 104, 129, 218, 103, 20, 189,
+  78, 3, 128, 185, 2, 95, 172, 139, 10, 123, 104, 241, 214, 169, 188, 211, 98, 13, 80, 41, 82, 177, 220, 229, 186,
+  149, 200, 159, 134, 71, 116, 99, 18, 29, 224, 103, 162, 193, 12, 171, 150, 165, 248, 209, 202, 201, 92, 13, 62, 211,
+  16, 247, 14, 209, 60, 59, 26, 181, 40, 191, 230, 39, 44, 125, 114, 195, 64, 135, 190, 225, 148, 53, 202, 197, 168,
+  79, 106, 23, 4, 19, 34, 77, 144, 23, 146, 241, 156, 91, 122, 43, 136, 223, 70, 249, 52, 163, 46, 93, 96, 89,
+  30, 255, 52, 21, 214, 229, 72, 111, 10, 9, 156, 205, 126, 147, 48, 55, 50, 239, 252, 133, 38, 11, 232, 1, 166,
+  25, 108, 61, 206, 125, 0, 199, 126, 223, 44, 11, 118, 251, 24, 113, 170, 215, 60, 83, 30, 115, 48, 169, 210, 49,
+  92, 101, 58, 21, 184, 225, 6, 199, 244, 227, 146, 99, 96, 25, 222, 65, 140, 213, 22, 219, 136, 175, 182, 73, 36,
+  141, 190, 83, 112, 137, 114, 175, 188, 187, 102, 53, 168, 193, 154, 167, 172, 3, 242, 67, 64, 7, 62, 159, 236, 75,
+  182, 187, 40, 49, 234, 105, 124, 109, 162, 205, 16, 105, 238, 143, 28, 37, 6, 85, 248, 161, 58, 121, 180, 221, 174,
+  221, 32, 217, 98, 129, 76, 149, 170, 101, 200, 239, 118, 137, 28, 179, 254, 19, 80, 183, 178, 145, 124, 251, 166, 139,
+  152, 129, 38, 153, 20, 189, 78, 3, 128, 71, 254, 95, 84, 139, 10, 123, 152, 241, 214, 169, 68, 211, 98, 13, 80,
+  215, 82, 79, 36, 229, 70, 149, 56, 159, 134, 185, 140, 99, 18, 29, 224, 153, 94, 63, 244, 85, 150, 91, 248, 209,
+  202, 55, 92, 243, 194, 211, 240, 247, 242, 209, 196, 197, 26, 75, 40, 191, 26, 39, 44, 131, 142, 195, 64, 121, 190,
+  225, 148, 53, 54, 197, 88, 79, 106, 233, 252, 19, 34, 77, 144, 233, 146, 241, 100, 91, 134, 43, 136, 33, 70, 249,
+  204, 163, 210, 163, 96, 89, 226, 1, 52, 235, 214, 27, 72, 111, 246, 247, 156, 51, 130, 109, 208, 55, 50, 17, 252,
+  123, 218, 245, 232, 255, 90, 231, 108, 195, 50, 125, 0, 199, 130, 223, 212, 11, 138, 251, 232, 143, 86, 215, 196, 83,
+  30, 141, 48, 87, 46, 207, 92, 155, 58, 235, 184, 31, 6, 199, 12, 29, 146, 157, 160, 231, 34, 191, 116, 213, 22,
+  37, 136, 175, 74, 183, 36, 115, 66, 173, 144, 137, 142, 175, 188, 69, 102, 53, 168, 193, 102, 89, 172, 253, 242, 67,
+  192, 7, 62, 159, 20, 181, 182, 187, 216, 207, 22, 105, 132, 109, 162, 205, 16, 151, 18, 113, 228, 37, 6, 85, 8,
+  161, 58, 135, 76, 35, 174, 35, 224, 39, 158, 127, 180, 149, 86, 155, 200, 239, 118, 119, 28, 77, 254, 19, 176, 183,
+  78, 145, 132, 5, 90, 117, 152, 127, 218, 153, 20, 67, 178, 3, 128, 185, 254, 95, 172, 139, 246, 123, 104, 15, 42,
+  169, 68, 211, 98, 243, 80, 41, 174, 79, 36, 27, 186, 107, 56, 97, 134, 71, 116, 157, 238, 227, 32, 153, 162, 193,
+  244, 171, 150, 165, 248, 209, 54, 55, 164, 13, 194, 45, 16, 247, 242, 47, 60, 59, 26, 75, 40, 65, 230, 217, 44,
+  131, 142, 195, 192, 121, 190, 225, 108, 203, 202, 197, 168, 177, 150, 233, 252, 19, 34, 77, 144, 23, 110, 15, 100, 91,
+  122, 213, 120, 223, 70, 7, 52, 93, 46, 93, 160, 167, 226, 255, 204, 21, 42, 229, 72, 111, 246, 9, 100, 205, 126,
+  147, 48, 55, 206, 239, 4, 133, 218, 245, 232, 255, 166, 231, 108, 195, 50, 131, 0, 57, 130, 223, 44, 245, 118, 251,
+  232, 113, 86, 215, 196, 83, 30, 141, 48, 87, 46, 207, 92, 155, 198, 235, 72, 31, 250, 57, 244, 29, 110, 99, 160,
+  231, 34, 65, 116, 43, 22, 219, 136, 175, 74, 73, 220, 141, 190, 83, 112, 137, 142, 81, 68, 69, 154, 203, 88, 63,
+  154, 89, 172, 3, 242, 67, 192, 249, 62, 159, 20, 181, 74, 69, 216, 49, 22, 105, 132, 109, 162, 205, 16, 151, 18,
+  113, 228, 219, 
+250, 171, 8, 95, 58, 135, 180, 35, 82, 221, 224, 39, 98, 129, 180, 107, 86, 101, 200, 239, 118, 119,
+  228, 179, 2, 237, 80, 183, 78, 111, 124, 5, 90, 117, 104, 127, 38, 153, 20, 67, 178, 253, 128, 185, 254, 95, 172,
+  117, 10, 123, 152, 241, 42, 87, 188, 211, 98, 243, 80, 215, 82, 79, 36, 27, 186, 107, 200, 159, 122, 71, 140, 157,
+  238, 29, 224, 153, 94, 63, 244, 85, 106, 91, 248, 47, 54, 201, 164, 243, 62, 211, 240, 247, 242, 47, 196, 197, 230,
+  181, 216, 65, 26, 217, 44, 125, 114, 195, 192, 135, 190, 31, 148, 203, 202, 59, 88, 79, 150, 233, 252, 19, 34, 77,
+  144, 233, 146, 15, 100, 165, 122, 213, 136, 223, 70, 249, 204, 93, 46, 93, 96, 167, 30, 1, 204, 21, 42, 27, 72
+};
+
+*/
+
+  unsigned int SortArr0[8*(SIZE+200)];
+
+void SORT(int *base, int n, int size, int (*compar) (),int type);
+void QSORT(int *base, int n, int size, int (*compar) ());
+void simple_sort(int *base, int n, int size, int (*compar) ());
+void insertion_sort(int *base, int n, int size, int (*compar) ());
+void bubble_sort(int *base, int n, int size, int (*compar) ());
+int compare(int *n1, int *n2)
+{
+  return (*((unsigned int *) n1) - *((unsigned int *) n2));
+}
+
+int main()
+{
+  register int p; 
+
+  p=procnum();
+
+  puts("Hello from processor ");
+  putchar(p+'0');
+  putchar('\n');
+
+
+  int i;
+  int j;
+  int temp;
+
+  if(p+1 <= nprocs){
+	for(i=1 ; i <= 8 ; i++ ){
+  	puts("Memory copy \n");
+	memcpy(SortArr0+p*(SIZE+200), gQSortNum0 + ( (4*(p+1)*i) % 32) ,SIZE);
+
+/*
+  	uputs("Cache erase ... \n");
+
+  	for(j = 0; j < SIZE+200; j++){
+		temp=gQSortNum0[j];
+  	}
+*/
+ 
+	
+  	puts("Sort... \n");
+  	SORT((int *) (SortArr0+p*(SIZE+200)), (int) SIZE, sizeof(unsigned int), compare,SORT_TYPE);
+  	for (j = 1; j < SIZE; j++)
+    	{
+      		if (SortArr0[p*(SIZE+200)+j] < SortArr0[p*(SIZE+200) + j - 1])
+		{
+	  		puts("ucbqsort: failed\n");
+			while(1);
+		}
+
+    	}
+  	puts("ucbqsort: success\n");
+	}
+  }
+  
+
+  if(p+1 <= nprocs){
+	lock_lock(&lock);
+	compteur--;
+	if(!compteur){
+  		putchar('\n');
+  		puti(temp);
+  		putchar('\n');
+	}
+	lock_unlock(&lock);
+  }
+
+  while(1);
+}
+
+static int (*qcmp) ();
+static int qsz;
+static int thresh;
+static int mthresh;
+static void qst(int *, int *);
+void QSORT(base, n, size, compar)
+     int *base;
+     int n;
+     int size;
+     int (*compar) ();
+{
+  register int c, *i, *j, *lo, *hi;
+  int *min, *max;
+  if (n <= 1)
+    return;
+  qsz = size;
+  qcmp = compar;
+  thresh = 4;
+  mthresh = 6;
+  max = base + n;
+  if (n >= 4)
+    {
+      qst(base, max);
+      hi = base + thresh;
+    } 
+  else
+    {
+      hi = max;
+    }
+
+  puts("Quick sort done... \n");
+
+  for (j = lo = base; (lo ++) < hi;)
+    if ((*qcmp) (j, lo) > 0)
+      j = lo;
+  if (j != base)
+    {
+      for (i = base, hi = base + 1; i < hi;)
+	{
+	  c = *j;
+	  *j++ = *i;
+	  *i++ = c;
+	}
+
+    }
+  for (min = base; (hi = min ++) < max;)
+    {
+      while ((*qcmp) (hi --, min) > 0)
+	;
+      if ((hi ++) != min)
+	{
+	  for (lo = min + 1; --lo >= min;)
+	    {
+	      c = *lo;
+	      for (i = j = lo; (j --) >= hi; i = j)
+		*i = *j;
+	      *i = c;
+	    }
+
+	}
+    }
+
+}
+
+
+void simple_sort(base, n, size, compar)
+     int *base;
+     int n;
+     int size;
+     int (*compar) ();
+{
+  register int c, *i, *j, *lo, p, *k;
+  int *max;
+  k=write_boost;
+  if (n <= 1)
+    return;
+  qsz = size;
+  qcmp = compar;
+  max = base + n;
+  puts("Selection Sort\n");
+  p=procnum();
+//  k=4;
+  for(j = base; j < max ; j++){
+    lo=j;
+    c=(*lo);
+    for(i = j; i < max ; i++){
+      *(k+(p * 70)+20)=p; // 1
+
+	asm("	nop		\n"); //1
+	//asm("	nop		\n");
+
+
+      if( c-(*i) > 0){
+//	if( (*qcmp) (lo,i) > 0){
+ 	lo=i;
+        c=(*lo);
+/*	write_boost[p][((int)i) & mask1]=(*(lo+3));
+	write_boost[p][((int)i) & mask2]=(*(lo+4));
+	write_boost[p][((int)j) & mask1]=(*(lo+2));
+	write_boost[p][((int)j) & mask2]=(*(lo+1));
+	write_boost[p][((int)i) & mask3]=(*(lo));
+*/
+      }
+
+/*
+      if(!k){
+	write_boost[p][((int)i) & 0x00000010]=(int)max;
+	k=4;
+      }
+      else{
+	if((k%2)){
+	  write_boost[p][((int)i) & 0x00000010]=(int)max;
+	}
+	else{
+	  write_boost[p][((int)j) & 0x00000111]=(int)i;
+	}
+	k--;
+//	write_boost[p][((int)i) & 0x00000001]=(int)i;
+      }
+*/
+      asm("	nop		\n"); // 1
+	//asm("	nop		\n");
+    }
+    *lo = *j;
+    *j = c;
+  }
+}
+
+void insertion_sort(base, n, size, compar)
+     int *base;
+     int n;
+     int size;
+     int (*compar) ();
+{
+  register int c, *i, *j,p;
+  int *max;
+  if (n <= 1)
+    return;
+  qsz = size;
+  qcmp = compar;
+  max = base + n;
+  puts("Insertion Sort\n");
+  p=procnum();
+  for(j = base; j < max-1 ; j++){
+    for(i = j; i < max-1 ; i++){
+      if( (*i)-(*(i+1)) > 0){
+//	if( (*qcmp) (i,i+1) > 0){
+ 	c = *i;
+	*i = *(i+1);
+	*(i+1)=c;
+      }
+    }
+  }
+}
+
+
+void bubble_sort(base, n, size, compar)
+     int *base;
+     int n;
+     int size;
+     int (*compar) ();
+{
+  register int c, *i;
+  register int b_swap=1;
+  int *max;
+  if (n <= 1)
+    return;
+  qsz = size;
+  qcmp = compar;
+  max = base + n;
+  puts("Bubble Sort\n");
+  while(b_swap){
+    b_swap=0;
+    for(i = base; i < max-1 ; i++){
+      if( (*i)-(*(i+1)) > 0){
+//	if( (*qcmp) (i,i+1) > 0){
+	b_swap=1;
+ 	c = *i;
+	*i = *(i+1);
+	*(i+1)=c;
+      }
+    }
+  }
+}
+
+static
+void qst(base, max)
+     int *base, *max;
+{
+  register int c, *i, *j, *jj;
+  register int ii;
+  int *mid, *tmp;
+  int lo, hi;
+  lo = max - base;
+  do
+    {
+      mid = i = base + 1 * ((lo / qsz) >> 1);
+      if (lo >= mthresh)
+	{
+	  j = ((*qcmp) ((jj = base), i) > 0 ? jj : i);
+	  if ((*qcmp) (j, (tmp = max - 1)) > 0)
+	    {
+	      j = (j == jj ? i : jj);
+	      if ((*qcmp) (j, tmp) < 0)
+		j = tmp;
+	    }
+
+	  if (j != i)
+	    {
+	      ii = 1;
+	      do
+		{
+		  c = *i;
+		  *i++ = *j;
+		  *j++ = c;
+		}
+
+	      while (--ii);
+	    }
+
+	}
+      for (i = base, j = max - 1;;)
+	{
+	  while (i < mid && (*qcmp) (i, mid) <= 0)
+            i ++;
+	  while (j > mid)
+	    {
+	      if ((*qcmp) (mid, j) <= 0)
+		{
+		  j --;
+		  continue;
+		}
+
+	      tmp = i + 1;
+	      if (i == mid)
+		{
+		  mid = jj = j;
+		} 
+	      else
+		{
+		  jj = j;
+		  j --;
+		}
+
+	      goto swap;
+	    }
+
+	  if (i == mid)
+	    {
+	      break;
+	    } 
+	  else
+	    {
+	      jj = mid;
+	      tmp = mid = i;
+	      j --;
+	    }
+
+	swap:
+	  ii = 1;
+	  do
+	    {
+	      c = *i;
+	      *i++ = *jj;
+	      *jj++ = c;
+	    }
+
+	  while (--ii);
+	  i = tmp;
+	}
+
+      i = (j = mid) + 1;
+      if ((lo = j - base) <= (hi = max - i))
+	{
+	  if (lo >= thresh)
+            qst(base, j);
+	  base = i;
+	  lo = hi;
+	} 
+      else
+	{
+	  if (hi >= thresh)
+            qst(i, max);
+	  max = j;
+	}
+
+    }
+  while (lo >= thresh);
+}
+
+void SORT(int *base, int n, int size, int (*compar) (),int type){
+  switch(type){
+  case 0:
+    QSORT(base, n, size, compar);
+    break;
+  case 1:
+    simple_sort(base, n, size, compar);
+    break;
+  case 2:
+    insertion_sort(base, n, size, compar);
+    break;
+  case 3:
+    bubble_sort(base, n, size, compar);
+    break;
+  default:
+    break;
+  }
+
+}
+
+
Index: branches/v4/platforms/caba-vgmn-memcache-mipsel/top.cpp
===================================================================
--- branches/v4/platforms/caba-vgmn-memcache-mipsel/top.cpp	(revision 371)
+++ branches/v4/platforms/caba-vgmn-memcache-mipsel/top.cpp	(revision 371)
@@ -0,0 +1,228 @@
+
+#include <systemc>
+#include <sys/time.h>
+#include <iostream>
+#include <cstdlib>
+#include <cstdarg>
+
+#include "mapping_table.h"
+#include "mips.h"
+#include "ississ2.h"
+#include "iss_simhelper.h"
+#include "vci_simple_ram.h"
+#include "vci_multi_tty.h"
+#include "vci_vgmn.h"
+#include "vci_mem_cache.h"
+#include "vci_cc_xcache_wrapper.h"
+
+
+#ifdef USE_GDB_SERVER
+#include "iss/gdbserver.h"
+#endif
+
+#include "segmentation.h"
+
+int _main(int argc, char *argv[])
+{
+	using namespace sc_core;
+	// Avoid repeating these everywhere
+	using soclib::common::IntTab;
+	using soclib::common::Segment;
+
+	// Define VCI parameters
+	typedef soclib::caba::VciParams<4,8,32,1,1,1,8,4,4,1> vci_param;
+	typedef soclib::common::IssIss2<soclib::common::IssSimhelper<soclib::common::MipsElIss> > proc_iss;
+
+	// Mapping table
+
+	soclib::common::MappingTable maptabp(32, IntTab(8), IntTab(8), 0x00C00000);
+
+	maptabp.add(Segment("reset", RESET_BASE, RESET_SIZE, IntTab(0), true));
+	maptabp.add(Segment("excep", EXCEP_BASE, EXCEP_SIZE, IntTab(0), true));
+	maptabp.add(Segment("tty"  , TTY_BASE  , TTY_SIZE  , IntTab(1), false));
+	maptabp.add(Segment("mc_r" , MC_R_BASE , MC_R_SIZE , IntTab(2), false, true, IntTab(0)));
+	maptabp.add(Segment("mc_m" , MC_M_BASE , MC_M_SIZE , IntTab(2), true ));
+
+	std::cout << maptabp << std::endl;
+
+	soclib::common::MappingTable maptabc(32, IntTab(8), IntTab(8), 0x00C00000);
+	maptabc.add(Segment("proc" , PROC_BASE , PROC_SIZE , IntTab(0), false, true, IntTab(0)));
+	std::cout << maptabc << std::endl;
+
+	soclib::common::MappingTable maptabx(32, IntTab(8), IntTab(8), 0x00C00000);
+	maptabx.add(Segment("xram" , MC_M_BASE , MC_M_SIZE , IntTab(0), false));
+
+	std::cout << maptabx << std::endl;
+
+	// Signals
+
+	sc_clock	signal_clk("clk");
+	sc_signal<bool> signal_resetn("resetn");
+   
+	sc_signal<bool> signal_proc_it0("proc_it0"); 
+	sc_signal<bool> signal_proc_it1("proc_it1"); 
+	sc_signal<bool> signal_proc_it2("proc_it2"); 
+	sc_signal<bool> signal_proc_it3("proc_it3"); 
+	sc_signal<bool> signal_proc_it4("proc_it4"); 
+	sc_signal<bool> signal_proc_it5("proc_it5");
+
+	soclib::caba::VciSignals<vci_param> signal_vci_ini_proc("vci_ini_proc");
+	soclib::caba::VciSignals<vci_param> signal_vci_tgt_proc("vci_tgt_proc");
+
+	soclib::caba::VciSignals<vci_param> signal_vci_tgt_tty("vci_tgt_tty");
+
+	soclib::caba::VciSignals<vci_param> signal_vci_tgt_rom("vci_tgt_rom");
+
+	soclib::caba::VciSignals<vci_param> signal_vci_tgt_xram("vci_tgt_xram");
+
+	soclib::caba::VciSignals<vci_param> signal_vci_ixr_memc("vci_ixr_memc");
+	soclib::caba::VciSignals<vci_param> signal_vci_ini_memc("vci_ini_memc");
+	soclib::caba::VciSignals<vci_param> signal_vci_tgt_memc("vci_tgt_memc");
+
+	sc_signal<bool> signal_tty_irq("signal_tty_irq"); 
+
+	// Components
+	// VCI ports indexation : 3 intiateurs et 5 cibles
+
+        // INIT0 : proc_ini
+        // INIT1 : memc_ini
+        // INIT2 : memc_ixr
+
+	// TGT 0 : rom_tgt
+	// TGT 1 : tty_tgt
+        // TGT 2 : xram_tgt
+	// TGT 3 : memc_tgt
+	// TGT 4 : proc_tgt
+
+	soclib::common::Loader loader("soft/bin.soft");
+
+	soclib::caba::VciCcXcacheWrapper<vci_param, proc_iss > 
+	proc("proc", 0, maptabp,maptabc,IntTab(0),IntTab(0),4,64,16,4,64,16,CLEANUP_OFFSET);
+
+	soclib::caba::VciSimpleRam<vci_param> 
+	rom("rom", IntTab(0), maptabp, loader);
+
+	soclib::caba::VciSimpleRam<vci_param> 
+	xram("xram",IntTab(0),maptabx, loader);
+
+	soclib::caba::VciMemCache<vci_param> 
+	memc("memc",maptabp,maptabc,maptabx,IntTab(0),IntTab(0),IntTab(2),16,256,16);
+	
+	soclib::caba::VciMultiTty<vci_param> 
+	tty("tty",IntTab(1),maptabp,"tty",NULL);
+
+	soclib::caba::VciVgmn<vci_param> 
+	vgmnp("vgmnp",maptabp, 1, 3, 1, 8);
+
+	soclib::caba::VciVgmn<vci_param> 
+	vgmnc("vgmnc",maptabc, 1, 1, 1, 8);
+
+	soclib::caba::VciVgmn<vci_param> 
+	vgmnx("vgmnx",maptabx, 1, 1, 1, 8);
+
+	// Net-List
+ 
+	proc.p_clk(signal_clk);  
+	proc.p_resetn(signal_resetn);  
+	proc.p_irq[0](signal_proc_it0); 
+	proc.p_irq[1](signal_proc_it1); 
+	proc.p_irq[2](signal_proc_it2); 
+	proc.p_irq[3](signal_proc_it3); 
+	proc.p_irq[4](signal_proc_it4); 
+	proc.p_irq[5](signal_proc_it5); 
+	proc.p_vci_ini(signal_vci_ini_proc);
+	proc.p_vci_tgt(signal_vci_tgt_proc);
+
+	rom.p_clk(signal_clk);
+	rom.p_resetn(signal_resetn);
+	rom.p_vci(signal_vci_tgt_rom);
+
+	tty.p_clk(signal_clk);
+	tty.p_resetn(signal_resetn);
+	tty.p_vci(signal_vci_tgt_tty);
+	tty.p_irq[0](signal_tty_irq); 
+
+	memc.p_clk(signal_clk);
+	memc.p_resetn(signal_resetn);
+	memc.p_vci_tgt(signal_vci_tgt_memc);	
+	memc.p_vci_ini(signal_vci_ini_memc);
+	memc.p_vci_ixr(signal_vci_ixr_memc);
+
+	xram.p_clk(signal_clk);
+        xram.p_resetn(signal_resetn);
+	xram.p_vci(signal_vci_tgt_xram);	
+
+	vgmnp.p_clk(signal_clk);
+	vgmnp.p_resetn(signal_resetn);
+
+	vgmnc.p_clk(signal_clk);
+	vgmnc.p_resetn(signal_resetn);
+
+	vgmnx.p_clk(signal_clk);
+	vgmnx.p_resetn(signal_resetn);
+
+	vgmnp.p_to_initiator[0](signal_vci_ini_proc);
+
+	vgmnc.p_to_initiator[0](signal_vci_ini_memc);
+
+	vgmnx.p_to_initiator[0](signal_vci_ixr_memc);
+
+
+	vgmnp.p_to_target[0](signal_vci_tgt_rom);
+	vgmnp.p_to_target[1](signal_vci_tgt_tty);
+	vgmnp.p_to_target[2](signal_vci_tgt_memc);
+
+	vgmnc.p_to_target[0](signal_vci_tgt_proc);
+
+	vgmnx.p_to_target[0](signal_vci_tgt_xram);
+
+	int ncycles;
+
+#ifndef SOCVIEW
+	if (argc == 2) {
+		ncycles = std::atoi(argv[1]);
+	} else {
+		std::cerr
+			<< std::endl
+			<< "The number of simulation cycles must "
+			   "be defined in the command line"
+			<< std::endl;
+		exit(1);
+	}
+
+	sc_start(sc_core::sc_time(0, SC_NS));
+	signal_resetn = false;
+
+	sc_start(sc_core::sc_time(1, SC_NS));
+	signal_resetn = true;
+
+	for (int i = 0; i < ncycles ; i+=1000) {
+		sc_start(sc_core::sc_time(1000, SC_NS));
+		proc.print_stats();
+		memc.print_stats();
+	}
+	return EXIT_SUCCESS;
+#else
+	ncycles = 1;
+	sc_start(sc_core::sc_time(0, SC_NS));
+	signal_resetn = false;
+	sc_start(sc_core::sc_time(1, SC_NS));
+	signal_resetn = true;
+
+	debug();
+	return EXIT_SUCCESS;
+#endif
+}
+
+int sc_main (int argc, char *argv[])
+{
+	try {
+		return _main(argc, argv);
+	} catch (std::exception &e) {
+		std::cout << e.what() << std::endl;
+	} catch (...) {
+		std::cout << "Unknown exception occured" << std::endl;
+		throw;
+	}
+	return 1;
+}
Index: branches/v4/platforms/caba-vgmn-memcache-mipsel/top_8_procs.cpp
===================================================================
--- branches/v4/platforms/caba-vgmn-memcache-mipsel/top_8_procs.cpp	(revision 371)
+++ branches/v4/platforms/caba-vgmn-memcache-mipsel/top_8_procs.cpp	(revision 371)
@@ -0,0 +1,442 @@
+/*
+ *
+ * SOCLIB_LGPL_HEADER_BEGIN
+ * 
+ * This file is part of SoCLib, GNU LGPLv2.1.
+ * 
+ * SoCLib is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU Lesser General Public License as published
+ * by the Free Software Foundation; version 2.1 of the License.
+ * 
+ * SoCLib is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * Lesser General Public License for more details.
+ * 
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with SoCLib; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301 USA
+ * 
+ * SOCLIB_LGPL_HEADER_END
+ *
+ * Copyright (c) UPMC, Lip6, SoC
+ *         Nicolas Pouillon <nipo@ssji.net>, 2006-2007
+ *
+ * Maintainers: nipo
+ */
+
+#include <systemc>
+#include <sys/time.h>
+#include <iostream>
+#include <cstdlib>
+#include <cstdarg>
+
+#include "mapping_table.h"
+#include "mips.h"
+#include "ississ2.h"
+#include "iss_simhelper.h"
+#include "vci_simple_ram.h"
+#include "vci_multi_tty.h"
+#include "vci_vgmn.h"
+#include "vci_mem_cache.h"
+#include "vci_xram.h"
+#include "vci_cc_xcache_wrapper.h"
+
+
+//#define USE_GDB_SERVER
+
+#ifdef USE_GDB_SERVER
+#include "iss/gdbserver.h"
+#endif
+
+#include "segmentation.h"
+
+int _main(int argc, char *argv[])
+{
+	using namespace sc_core;
+	// Avoid repeating these everywhere
+	using soclib::common::IntTab;
+	using soclib::common::Segment;
+
+	// Define our VCI parameters
+	typedef soclib::caba::VciParams<4,8,32,1,1,1,8,4,4,1> vci_param;
+	typedef soclib::common::IssIss2<soclib::common::IssSimhelper<soclib::common::MipsElIss> > proc_iss;
+
+	// Mapping table
+
+	soclib::common::MappingTable maptab(32, IntTab(8), IntTab(8), 0x00300000);
+
+	maptab.add(Segment("reset", RESET_BASE, RESET_SIZE, IntTab(8), true));
+	maptab.add(Segment("excep", EXCEP_BASE, EXCEP_SIZE, IntTab(8), true));
+
+	//maptab.add(Segment("text" , TEXT_BASE , TEXT_SIZE , IntTab(0), true));  
+	//maptab.add(Segment("data" , DATA_BASE , DATA_SIZE , IntTab(0), true));
+
+	maptab.add(Segment("tty"  , TTY_BASE  , TTY_SIZE  , IntTab(11), false));
+
+	maptab.add(Segment("ccache0", CC_XCACHE0_BASE, CC_XCACHE0_SIZE, IntTab(0), false, true, IntTab(0)));
+/*
+	maptab.add(Segment("ccache1", CC_XCACHE1_BASE, CC_XCACHE1_SIZE, IntTab(1), false, true, IntTab(1)));
+	maptab.add(Segment("ccache2", CC_XCACHE2_BASE, CC_XCACHE2_SIZE, IntTab(2), false, true, IntTab(2)));
+	maptab.add(Segment("ccache3", CC_XCACHE3_BASE, CC_XCACHE3_SIZE, IntTab(3), false, true, IntTab(3)));
+	maptab.add(Segment("ccache4", CC_XCACHE4_BASE, CC_XCACHE4_SIZE, IntTab(4), false, true, IntTab(4)));
+	maptab.add(Segment("ccache5", CC_XCACHE5_BASE, CC_XCACHE5_SIZE, IntTab(5), false, true, IntTab(5)));
+	maptab.add(Segment("ccache6", CC_XCACHE6_BASE, CC_XCACHE6_SIZE, IntTab(6), false, true, IntTab(6)));
+	maptab.add(Segment("ccache7", CC_XCACHE7_BASE, CC_XCACHE7_SIZE, IntTab(7), false, true, IntTab(7)));
+*/
+	maptab.add(Segment("xram", XRAM_BASE, XRAM_SIZE, IntTab(9), false, true, IntTab(8)));
+	maptab.add(Segment("memc_reg", MEMC_REG_BASE, MEMC_REG_SIZE, IntTab(10), false, true, IntTab(9)));
+	maptab.add(Segment("memc_mem", MEMC_MEM_BASE, MEMC_MEM_SIZE, IntTab(10), true ));
+
+	// Signals
+
+	sc_clock	signal_clk("clk");
+	sc_signal<bool> signal_resetn("resetn");
+   
+	sc_signal<bool> signal_proc0_it0("proc0_it0"); 
+	sc_signal<bool> signal_proc0_it1("proc0_it1"); 
+	sc_signal<bool> signal_proc0_it2("proc0_it2"); 
+	sc_signal<bool> signal_proc0_it3("proc0_it3"); 
+	sc_signal<bool> signal_proc0_it4("proc0_it4"); 
+	sc_signal<bool> signal_proc0_it5("proc0_it5");
+/* 
+	sc_signal<bool> signal_proc1_it0("proc1_it0"); 
+	sc_signal<bool> signal_proc1_it1("proc1_it1"); 
+	sc_signal<bool> signal_proc1_it2("proc1_it2"); 
+	sc_signal<bool> signal_proc1_it3("proc1_it3"); 
+	sc_signal<bool> signal_proc1_it4("proc1_it4"); 
+	sc_signal<bool> signal_proc1_it5("proc1_it5");
+  
+	sc_signal<bool> signal_proc2_it0("proc2_it0"); 
+	sc_signal<bool> signal_proc2_it1("proc2_it1"); 
+	sc_signal<bool> signal_proc2_it2("proc2_it2"); 
+	sc_signal<bool> signal_proc2_it3("proc2_it3"); 
+	sc_signal<bool> signal_proc2_it4("proc2_it4"); 
+	sc_signal<bool> signal_proc2_it5("proc2_it5");
+  
+	sc_signal<bool> signal_proc3_it0("proc3_it0"); 
+	sc_signal<bool> signal_proc3_it1("proc3_it1"); 
+	sc_signal<bool> signal_proc3_it2("proc3_it2"); 
+	sc_signal<bool> signal_proc3_it3("proc3_it3"); 
+	sc_signal<bool> signal_proc3_it4("proc3_it4"); 
+	sc_signal<bool> signal_proc3_it5("proc3_it5");
+
+	sc_signal<bool> signal_proc4_it0("proc4_it0"); 
+	sc_signal<bool> signal_proc4_it1("proc4_it1"); 
+	sc_signal<bool> signal_proc4_it2("proc4_it2"); 
+	sc_signal<bool> signal_proc4_it3("proc4_it3"); 
+	sc_signal<bool> signal_proc4_it4("proc4_it4"); 
+	sc_signal<bool> signal_proc4_it5("proc4_it5");
+
+	sc_signal<bool> signal_proc5_it0("proc5_it0"); 
+	sc_signal<bool> signal_proc5_it1("proc5_it1"); 
+	sc_signal<bool> signal_proc5_it2("proc5_it2"); 
+	sc_signal<bool> signal_proc5_it3("proc5_it3"); 
+	sc_signal<bool> signal_proc5_it4("proc5_it4"); 
+	sc_signal<bool> signal_proc5_it5("proc5_it5");
+
+	sc_signal<bool> signal_proc6_it0("proc6_it0"); 
+	sc_signal<bool> signal_proc6_it1("proc6_it1"); 
+	sc_signal<bool> signal_proc6_it2("proc6_it2"); 
+	sc_signal<bool> signal_proc6_it3("proc6_it3"); 
+	sc_signal<bool> signal_proc6_it4("proc6_it4"); 
+	sc_signal<bool> signal_proc6_it5("proc6_it5");
+
+	sc_signal<bool> signal_proc7_it0("proc7_it0"); 
+	sc_signal<bool> signal_proc7_it1("proc7_it1"); 
+	sc_signal<bool> signal_proc7_it2("proc7_it2"); 
+	sc_signal<bool> signal_proc7_it3("proc7_it3"); 
+	sc_signal<bool> signal_proc7_it4("proc7_it4"); 
+	sc_signal<bool> signal_proc7_it5("proc7_it5");
+*/
+	soclib::caba::VciSignals<vci_param> signal_vci_ini_proc0("vci_ini_proc0");
+	soclib::caba::VciSignals<vci_param> signal_vci_tgt_proc0("vci_tgt_proc0");
+/*
+	soclib::caba::VciSignals<vci_param> signal_vci_ini_proc1("vci_ini_proc1");
+	soclib::caba::VciSignals<vci_param> signal_vci_tgt_proc1("vci_tgt_proc1");
+
+	soclib::caba::VciSignals<vci_param> signal_vci_ini_proc2("vci_ini_proc2");
+	soclib::caba::VciSignals<vci_param> signal_vci_tgt_proc2("vci_tgt_proc2");
+
+	soclib::caba::VciSignals<vci_param> signal_vci_ini_proc3("vci_ini_proc3");
+	soclib::caba::VciSignals<vci_param> signal_vci_tgt_proc3("vci_tgt_proc3");
+
+	soclib::caba::VciSignals<vci_param> signal_vci_ini_proc4("vci_ini_proc4");
+	soclib::caba::VciSignals<vci_param> signal_vci_tgt_proc4("vci_tgt_proc4");
+
+	soclib::caba::VciSignals<vci_param> signal_vci_ini_proc5("vci_ini_proc5");
+	soclib::caba::VciSignals<vci_param> signal_vci_tgt_proc5("vci_tgt_proc5");
+
+	soclib::caba::VciSignals<vci_param> signal_vci_ini_proc6("vci_ini_proc6");
+	soclib::caba::VciSignals<vci_param> signal_vci_tgt_proc6("vci_tgt_proc6");
+
+	soclib::caba::VciSignals<vci_param> signal_vci_ini_proc7("vci_ini_proc7");
+	soclib::caba::VciSignals<vci_param> signal_vci_tgt_proc7("vci_tgt_proc7");
+*/
+	soclib::caba::VciSignals<vci_param> signal_vci_tgt_tty("vci_tgt_tty");
+
+	soclib::caba::VciSignals<vci_param> signal_vci_tgt_ram("vci_tgt_ram");
+
+	soclib::caba::VciSignals<vci_param> signal_vci_ini_xram("vci_ini_xram");
+	soclib::caba::VciSignals<vci_param> signal_vci_tgt_xram("vci_tgt_xram");
+
+	soclib::caba::VciSignals<vci_param> signal_vci_ixr_memc("vci_ixr_memc");
+	soclib::caba::VciSignals<vci_param> signal_vci_ini_memc("vci_ini_memc");
+	soclib::caba::VciSignals<vci_param> signal_vci_tgt_memc("vci_tgt_memc");
+
+	sc_signal<bool> signal_tty_irq0("signal_tty_irq0"); 
+	sc_signal<bool> signal_tty_irq1("signal_tty_irq1"); 
+	sc_signal<bool> signal_tty_irq2("signal_tty_irq2"); 
+	sc_signal<bool> signal_tty_irq3("signal_tty_irq3");
+	sc_signal<bool> signal_tty_irq4("signal_tty_irq4"); 
+	sc_signal<bool> signal_tty_irq5("signal_tty_irq5"); 
+	sc_signal<bool> signal_tty_irq6("signal_tty_irq6"); 
+	sc_signal<bool> signal_tty_irq7("signal_tty_irq7");
+
+	// Components
+
+	soclib::caba::VciCcXcacheWrapper<vci_param, proc_iss > 
+	proc0("proc0", 0, maptab,IntTab(0),IntTab(0),16,4,16,16,4,16);
+/*
+	soclib::caba::VciCcXcacheWrapper<vci_param, proc_iss > 
+	proc1("proc1", 1, maptab,IntTab(1),IntTab(1),16,4,16,16,4,16);
+	soclib::caba::VciCcXcacheWrapper<vci_param, proc_iss > 
+	proc2("proc2", 2, maptab,IntTab(2),IntTab(2),16,4,16,16,4,16);
+	soclib::caba::VciCcXcacheWrapper<vci_param, proc_iss > 
+	proc3("proc3", 3, maptab,IntTab(3),IntTab(3),16,4,16,16,4,16);
+	soclib::caba::VciCcXcacheWrapper<vci_param, proc_iss > 
+	proc4("proc4", 4, maptab,IntTab(4),IntTab(4),16,4,16,16,4,16);
+	soclib::caba::VciCcXcacheWrapper<vci_param, proc_iss > 
+	proc5("proc5", 5, maptab,IntTab(5),IntTab(5),16,4,16,16,4,16);
+	soclib::caba::VciCcXcacheWrapper<vci_param, proc_iss > 
+	proc6("proc6", 6, maptab,IntTab(6),IntTab(6),16,4,16,16,4,16); 
+	soclib::caba::VciCcXcacheWrapper<vci_param, proc_iss > 
+	proc7("proc7", 7, maptab,IntTab(7),IntTab(7),16,4,16,16,4,16);
+*/
+	soclib::common::Loader loader("soft/bin.soft");
+
+	soclib::caba::VciSimpleRam<vci_param> 
+	ram("vciram", IntTab(8), maptab, loader);
+
+	soclib::caba::VciXRam<vci_param> 
+	xram("xram",maptab,IntTab(8),IntTab(9),loader,16,MEMC_MEM_SIZE,2);
+
+	soclib::caba::VciMemCache<vci_param> 
+	memc("memc",maptab,IntTab(9),IntTab(10),256,16,16,MEMC_MEM_BASE,IntTab(9));
+/*
+	soclib::caba::VciMultiTty<vci_param> 
+	tty("tty",IntTab(11),maptab,"tty0","tty1","tty2","tty3","tty4","tty5","tty6","tty7",NULL);
+*/	
+	soclib::caba::VciMultiTty<vci_param> 
+	tty("tty",IntTab(11),maptab,"tty0",NULL);
+
+	soclib::caba::VciVgmn<vci_param> 
+	vgmn("vgmn",maptab, 10, 12, 2, 8);
+
+	// Net-List
+ 
+	proc0.p_clk(signal_clk);  
+	proc0.p_resetn(signal_resetn);  
+	proc0.p_irq[0](signal_proc0_it0); 
+	proc0.p_irq[1](signal_proc0_it1); 
+	proc0.p_irq[2](signal_proc0_it2); 
+	proc0.p_irq[3](signal_proc0_it3); 
+	proc0.p_irq[4](signal_proc0_it4); 
+	proc0.p_irq[5](signal_proc0_it5); 
+	proc0.p_vci_ini(signal_vci_ini_proc0);
+	proc0.p_vci_tgt(signal_vci_tgt_proc0);
+ /* 
+	proc1.p_clk(signal_clk);  
+	proc1.p_resetn(signal_resetn);  
+	proc1.p_irq[0](signal_proc1_it0); 
+	proc1.p_irq[1](signal_proc1_it1); 
+	proc1.p_irq[2](signal_proc1_it2); 
+	proc1.p_irq[3](signal_proc1_it3); 
+	proc1.p_irq[4](signal_proc1_it4); 
+	proc1.p_irq[5](signal_proc1_it5); 
+	proc1.p_vci_ini(signal_vci_ini_proc1);
+	proc1.p_vci_tgt(signal_vci_tgt_proc1);
+  
+	proc2.p_clk(signal_clk);  
+	proc2.p_resetn(signal_resetn);  
+	proc2.p_irq[0](signal_proc2_it0); 
+	proc2.p_irq[1](signal_proc2_it1); 
+	proc2.p_irq[2](signal_proc2_it2); 
+	proc2.p_irq[3](signal_proc2_it3); 
+	proc2.p_irq[4](signal_proc2_it4); 
+	proc2.p_irq[5](signal_proc2_it5); 
+	proc2.p_vci_ini(signal_vci_ini_proc2);
+	proc2.p_vci_tgt(signal_vci_tgt_proc2);
+  
+	proc3.p_clk(signal_clk);  
+	proc3.p_resetn(signal_resetn);  
+	proc3.p_irq[0](signal_proc3_it0); 
+	proc3.p_irq[1](signal_proc3_it1); 
+	proc3.p_irq[2](signal_proc3_it2); 
+	proc3.p_irq[3](signal_proc3_it3); 
+	proc3.p_irq[4](signal_proc3_it4); 
+	proc3.p_irq[5](signal_proc3_it5); 
+	proc3.p_vci_ini(signal_vci_ini_proc3);
+	proc3.p_vci_tgt(signal_vci_tgt_proc3);
+        
+	proc4.p_clk(signal_clk);  
+	proc4.p_resetn(signal_resetn);  
+	proc4.p_irq[0](signal_proc4_it0); 
+	proc4.p_irq[1](signal_proc4_it1); 
+	proc4.p_irq[2](signal_proc4_it2); 
+	proc4.p_irq[3](signal_proc4_it3); 
+	proc4.p_irq[4](signal_proc4_it4); 
+	proc4.p_irq[5](signal_proc4_it5); 
+	proc4.p_vci_ini(signal_vci_ini_proc4);
+	proc4.p_vci_tgt(signal_vci_tgt_proc4);
+  
+	proc5.p_clk(signal_clk);  
+	proc5.p_resetn(signal_resetn);  
+	proc5.p_irq[0](signal_proc5_it0); 
+	proc5.p_irq[1](signal_proc5_it1); 
+	proc5.p_irq[2](signal_proc5_it2); 
+	proc5.p_irq[3](signal_proc5_it3); 
+	proc5.p_irq[4](signal_proc5_it4); 
+	proc5.p_irq[5](signal_proc5_it5); 
+	proc5.p_vci_ini(signal_vci_ini_proc5);
+	proc5.p_vci_tgt(signal_vci_tgt_proc5);
+  
+	proc6.p_clk(signal_clk);  
+	proc6.p_resetn(signal_resetn);  
+	proc6.p_irq[0](signal_proc6_it0); 
+	proc6.p_irq[1](signal_proc6_it1); 
+	proc6.p_irq[2](signal_proc6_it2); 
+	proc6.p_irq[3](signal_proc6_it3); 
+	proc6.p_irq[4](signal_proc6_it4); 
+	proc6.p_irq[5](signal_proc6_it5); 
+	proc6.p_vci_ini(signal_vci_ini_proc6);
+	proc6.p_vci_tgt(signal_vci_tgt_proc6);
+  
+	proc7.p_clk(signal_clk);  
+	proc7.p_resetn(signal_resetn);  
+	proc7.p_irq[0](signal_proc7_it0); 
+	proc7.p_irq[1](signal_proc7_it1); 
+	proc7.p_irq[2](signal_proc7_it2); 
+	proc7.p_irq[3](signal_proc7_it3); 
+	proc7.p_irq[4](signal_proc7_it4); 
+	proc7.p_irq[5](signal_proc7_it5); 
+	proc7.p_vci_ini(signal_vci_ini_proc7);
+	proc7.p_vci_tgt(signal_vci_tgt_proc7);
+*/
+	ram.p_clk(signal_clk);
+	ram.p_resetn(signal_resetn);
+	ram.p_vci(signal_vci_tgt_ram);
+
+	tty.p_clk(signal_clk);
+	tty.p_resetn(signal_resetn);
+	tty.p_vci(signal_vci_tgt_tty);
+	tty.p_irq[0](signal_tty_irq0); 
+	tty.p_irq[1](signal_tty_irq1); 
+	tty.p_irq[2](signal_tty_irq2); 
+	tty.p_irq[3](signal_tty_irq3);
+	tty.p_irq[4](signal_tty_irq4); 
+	tty.p_irq[5](signal_tty_irq5); 
+	tty.p_irq[6](signal_tty_irq6); 
+	tty.p_irq[7](signal_tty_irq7); 
+
+	memc.p_clk(signal_clk);
+	memc.p_resetn(signal_resetn);
+	memc.p_vci_tgt(signal_vci_tgt_memc);	
+	memc.p_vci_ini(signal_vci_ini_memc);
+	memc.p_vci_ixr(signal_vci_ixr_memc);
+
+	xram.p_clk(signal_clk);
+        xram.p_resetn(signal_resetn);
+	xram.p_vci_tgt(signal_vci_tgt_xram);	
+	xram.p_vci_ini(signal_vci_ini_xram);
+
+	vgmn.p_clk(signal_clk);
+	vgmn.p_resetn(signal_resetn);
+
+	vgmn.p_to_initiator[0](signal_vci_ini_xram);
+	vgmn.p_to_initiator[1](signal_vci_ini_memc);
+	vgmn.p_to_initiator[2](signal_vci_ini_proc0);
+/*
+	vgmn.p_to_initiator[3](signal_vci_ini_proc1);
+	vgmn.p_to_initiator[4](signal_vci_ini_proc2);
+	vgmn.p_to_initiator[5](signal_vci_ini_proc3);
+	vgmn.p_to_initiator[6](signal_vci_ini_proc4);
+	vgmn.p_to_initiator[7](signal_vci_ini_proc5);
+	vgmn.p_to_initiator[8](signal_vci_ini_proc6);
+	vgmn.p_to_initiator[9](signal_vci_ini_proc7);
+*/
+	vgmn.p_to_target[0](signal_vci_tgt_xram);
+	vgmn.p_to_target[1](signal_vci_tgt_memc);
+	vgmn.p_to_target[2](signal_vci_tgt_ram);
+	vgmn.p_to_target[3](signal_vci_tgt_tty);
+	vgmn.p_to_target[4](signal_vci_tgt_proc0);
+/*
+	vgmn.p_to_target[5](signal_vci_tgt_proc1);
+	vgmn.p_to_target[6](signal_vci_tgt_proc2);
+	vgmn.p_to_target[7](signal_vci_tgt_proc3);
+	vgmn.p_to_target[8](signal_vci_tgt_proc4);	
+	vgmn.p_to_target[9](signal_vci_tgt_proc5);
+	vgmn.p_to_target[10](signal_vci_tgt_proc6);
+	vgmn.p_to_target[11](signal_vci_tgt_proc7);
+*/
+	int ncycles;
+
+#ifndef SOCVIEW
+	if (argc == 2) {
+		ncycles = std::atoi(argv[1]);
+	} else {
+		std::cerr
+			<< std::endl
+			<< "The number of simulation cycles must "
+			   "be defined in the command line"
+			<< std::endl;
+		exit(1);
+	}
+
+	sc_start(sc_core::sc_time(0, SC_NS));
+	signal_resetn = false;
+
+	sc_start(sc_core::sc_time(1, SC_NS));
+	signal_resetn = true;
+
+	for (int i = 0; i < ncycles ; i+=1000000) {
+		sc_start(sc_core::sc_time(1000000, SC_NS));
+		std::cout << "Time elapsed: "<<i<<" cycles." << std::endl;
+		proc0.print_stats();
+/*
+		proc1.print_stats();
+		proc2.print_stats();
+		proc3.print_stats();
+		proc4.print_stats();
+		proc5.print_stats();
+		proc6.print_stats();
+		proc7.print_stats();
+*/
+		memc.print_stats();
+	}
+	return EXIT_SUCCESS;
+#else
+	ncycles = 1;
+	sc_start(sc_core::sc_time(0, SC_NS));
+	signal_resetn = false;
+	sc_start(sc_core::sc_time(1, SC_NS));
+	signal_resetn = true;
+
+	debug();
+	return EXIT_SUCCESS;
+#endif
+}
+
+int sc_main (int argc, char *argv[])
+{
+	try {
+		return _main(argc, argv);
+	} catch (std::exception &e) {
+		std::cout << e.what() << std::endl;
+	} catch (...) {
+		std::cout << "Unknown exception occured" << std::endl;
+		throw;
+	}
+	return 1;
+}
Index: branches/v4/platforms/caba-vgmn-vcache2_memcache-mipsel/Makefile
===================================================================
--- branches/v4/platforms/caba-vgmn-vcache2_memcache-mipsel/Makefile	(revision 371)
+++ branches/v4/platforms/caba-vgmn-vcache2_memcache-mipsel/Makefile	(revision 371)
@@ -0,0 +1,5 @@
+ARCH=mips32el
+SIMULATION_ARGS=100000
+SOCLIB?=$(shell soclib-cc --getpath)
+export SOCLIB
+include $(SOCLIB)/soclib/platform/topcells/all.mk
Index: branches/v4/platforms/caba-vgmn-vcache2_memcache-mipsel/platform_desc
===================================================================
--- branches/v4/platforms/caba-vgmn-vcache2_memcache-mipsel/platform_desc	(revision 371)
+++ branches/v4/platforms/caba-vgmn-vcache2_memcache-mipsel/platform_desc	(revision 371)
@@ -0,0 +1,25 @@
+
+# -*- python -*-
+
+
+todo = Platform('caba', 'top.cpp',
+				uses = [
+#	Uses('caba:vci_cc_vcache_wrapper', iss_t = 'common:iss2_simhelper', simhelper_iss_t = 'common:mips32el'),
+	Uses('caba:vci_cc_vcache_wrapper2', iss_t = 'common:iss2_simhelper', simhelper_iss_t = 'common:mips32el'),
+	Uses('caba:vci_simple_ram'),
+	Uses('caba:vci_multi_tty'),
+	Uses('caba:vci_vgmn'),
+	Uses('caba:vci_mem_cache'),
+	Uses('common:elf_file_loader'),
+	],
+	cell_size = 4,
+	plen_size = 8,
+	addr_size = 32,
+	rerror_size = 1,
+	clen_size = 1,
+	rflag_size = 1,
+	srcid_size = 14,
+	pktid_size = 4,
+	trdid_size = 4,
+	wrplen_size = 1
+)
Index: branches/v4/platforms/caba-vgmn-vcache2_memcache-mipsel/segmentation.h
===================================================================
--- branches/v4/platforms/caba-vgmn-vcache2_memcache-mipsel/segmentation.h	(revision 371)
+++ branches/v4/platforms/caba-vgmn-vcache2_memcache-mipsel/segmentation.h	(revision 371)
@@ -0,0 +1,68 @@
+
+/////////////////////////////////////////////////////////////////
+//	ADDRESS SPACE SEGMENTATION
+//
+//	This file must be included in the system.cpp file, 
+//	for harware configuration : It is used to build
+//	the SOCLIB_SEGMENT_TABLE.
+//
+//	This file can also be used by the ldscript generator,
+//	for embedded software generation.
+//	
+//	It gives the system integrator the garanty
+//	that hardware and software have the same
+//	description of the address space segmentation.
+/////////////////////////////////////////////////////////////////
+
+/////////////////////////////////////////////////////////////////
+//	reset, and exception segments
+//      base address required by MIPS processor
+/////////////////////////////////////////////////////////////////
+#define MMU
+
+#define	RESET_BASE	0xBFC00000
+#define	RESET_SIZE	0x00010000
+
+#define	EXCEP_BASE	0x80000080
+#define	EXCEP_SIZE	0x00010000
+
+#define	TEXT_BASE	0x00400000
+#define	TEXT_SIZE	0x00050000
+/////////////////////////////////////////////////////////////////
+//	global data segment (initialised)
+/////////////////////////////////////////////////////////////////
+
+#define MC_M_BASE	0x10000000
+#define MC_M_SIZE	0x00100000
+
+/////////////////////////////////////////////////////////////////
+//	page table (initialised)
+/////////////////////////////////////////////////////////////////
+#define PTD_ADDR	0x40400000
+#define PTE_ADDR	0x40402000
+#define IPTE_ADDR	0x40403000
+#define	TAB_SIZE	0x00010000
+
+#define V_TTY_BASE 	0x00800000
+#define	V_TIMER_BASE	0x00C00000	// timer virtual address
+//////////////////////////////////////////////////////////
+//	System devices
+///////////////////////////////////////////////////////////
+
+#define	TTY_BASE	0xC0200000
+#define	TTY_SIZE	0x00000100
+
+#define	TIMER_BASE	0xD0200000
+#define	TIMER_SIZE	0x00000100
+
+#define	LOCKS_BASE	0xE0200000
+#define	LOCKS_SIZE	0x00000100
+
+#define PROC0_BASE	0x01200000
+#define PROC0_SIZE	0x00000008
+
+#define PROC1_BASE	0x02200000
+#define PROC1_SIZE	0x00000008
+
+#define MC_R_BASE	0x20200000
+#define MC_R_SIZE	0x00000008
Index: branches/v4/platforms/caba-vgmn-vcache2_memcache-mipsel/soft/Makefile
===================================================================
--- branches/v4/platforms/caba-vgmn-vcache2_memcache-mipsel/soft/Makefile	(revision 371)
+++ branches/v4/platforms/caba-vgmn-vcache2_memcache-mipsel/soft/Makefile	(revision 371)
@@ -0,0 +1,4 @@
+ADD_OBJS=stdlib.o stdio.o exception.o system.o
+SOCLIB?=$(shell soclib-cc --getpath)
+export SOCLIB
+include $(SOCLIB)/soclib/platform/topcells/soft.mk
Index: branches/v4/platforms/caba-vgmn-vcache2_memcache-mipsel/soft/main.c
===================================================================
--- branches/v4/platforms/caba-vgmn-vcache2_memcache-mipsel/soft/main.c	(revision 371)
+++ branches/v4/platforms/caba-vgmn-vcache2_memcache-mipsel/soft/main.c	(revision 371)
@@ -0,0 +1,798 @@
+#include "system.h"
+#include "stdio.h"
+#include "stdlib.h"
+
+
+#include "../segmentation.h"
+
+#define NPROCS 2
+#define SIZE 50
+#define SORT_TYPE 1
+
+volatile int lock=0;
+volatile int compteur=NPROCS;
+volatile int nprocs=NPROCS;
+
+// 100 elements
+unsigned int gQSortNum0[100] = {
+  251,  24, 113, 170, 215,  60,  83,  30, 115,  48, 169, 210,  49,  92, 101,  58,  21, 184, 225,   6,
+  199, 244, 227, 146,  99,  96,  25, 222,  65, 140, 213,  22, 219, 136, 175, 182,  73,  36, 141, 190, 
+   83, 112, 137, 114, 175, 188, 187, 102,  53, 168, 193, 154, 167, 172,   3, 242,  67,  64, 144, 137,
+  142, 175, 188,  69, 102,  53, 168, 193, 102,  89, 172, 253, 242,  67, 192,   7,  62, 159,  20, 181,
+  182, 187, 216, 207,  22, 105, 132, 109, 162, 205,  16, 151,  18, 113, 228,  37,   6,  85,   8, 161
+};
+
+/*
+unsigned int gQSortNum0[8000] = {
+  251, 24, 113, 170, 215, 60, 83, 30, 115, 48, 169, 210, 49, 92, 101, 58, 21, 184, 225, 6,
+  199, 244, 227, 146, 99, 96, 25, 222, 65, 140, 213, 22, 219, 136, 175, 182, 73, 36, 141, 190, 
+  83, 112, 137, 114, 175, 188, 187, 102, 53, 168, 193, 154, 167, 172, 3, 242, 67, 64,144, 137,
+  142, 175, 188, 69, 102, 53, 168, 193, 102, 89, 172, 253, 242, 67,192, 7, 62, 159, 20, 181,
+  182, 187, 216, 207, 22, 105, 132, 109, 162, 205, 16, 151, 18, 113, 228, 37, 6, 85, 8, 161,
+  58, 135, 76, 35, 174, 35, 224, 39, 158, 127, 180, 149, 86, 155, 200, 239, 118, 119, 28, 77,
+  254, 19, 176, 183, 78, 145, 132, 5, 90, 117, 152, 127, 218, 153, 20, 67, 178, 3, 128, 185,
+  254, 95, 172, 139, 246, 123, 104, 15, 42, 169, 68, 211, 98, 243, 80, 41, 174, 79, 36, 27,
+  186, 149, 86, 155, 200, 239, 118, 119, 28, 77, 254, 19, 176, 183,78, 145, 132, 5, 90, 117,
+  152, 127, 218, 153, 20, 67, 178, 3, 128, 185, 254, 95, 172, 139, 246, 123, 104, 15, 42,169,
+  68, 211, 98, 243, 80, 41, 174, 79, 36, 27, 186, 107, 56, 97, 134, 71, 116, 157, 238, 227,
+  32, 153, 162, 193, 244, 171, 150, 165, 248, 209, 54, 55, 164, 13, 194, 45, 16, 247, 242, 47,
+  60, 59, 26, 75, 40, 65, 230, 217, 44, 131, 142, 195, 192, 121, 190, 225, 108, 203, 202, 197,
+  168, 177, 150, 233, 252, 19, 34, 77, 144, 23, 110, 15, 100, 91, 122, 213, 120, 223, 70, 7, 
+  52, 93, 46, 93, 160, 167, 226, 255, 204, 21, 42, 229, 72, 111, 246, 9, 100, 205, 126, 147,
+  215, 82, 79, 36, 229, 70, 149, 56, 159, 134, 185, 140, 99, 18, 29, 224, 153, 94, 63, 244, 85, 150, 91, 248, 209,
+  202, 55, 92, 243, 194, 211, 240, 247, 242, 209, 196, 197, 26, 75, 40, 191, 26, 39, 44, 131, 142, 195, 64, 121, 190,
+  231, 34, 65, 116, 43, 22, 219, 136, 175, 74, 73, 220, 141, 190, 83, 112, 137, 142, 81, 68, 69, 154, 203, 88, 63,
+  154, 89, 172, 3, 242, 67, 192, 249, 62, 159, 20, 181, 74, 69, 216, 49, 22, 105, 132, 109, 162, 205, 16, 151, 18,
+  37, 136, 175, 74, 183, 36, 115, 66, 173, 144, 137, 142, 175, 188, 69, 102, 53, 168, 193, 102, 89, 172, 253, 242, 67,
+  192, 7, 62, 159, 20, 181, 182, 187, 216, 207, 22, 105, 132, 109, 162, 205, 16, 151, 18, 113, 228, 37, 6, 85, 8,
+  161, 58, 135, 76, 35, 174, 35, 224, 39, 158, 127, 180, 149, 86, 155, 200, 239, 118, 119, 28, 77, 254, 19, 176, 183,
+  78, 145, 132, 5, 90, 117, 152, 127, 218, 153, 20, 67, 178, 3, 128, 185, 254, 95, 172, 139, 246, 123, 104, 15, 42,
+  251, 24, 113, 170, 215, 60, 83, 30, 115, 48, 169, 210, 49, 92, 101, 58, 21, 184, 225, 6,
+  199, 244, 227, 146, 99, 96, 25, 222, 65, 140, 213, 22, 219, 136, 175, 182, 73, 36, 141, 190, 
+  83, 112, 137, 114, 175, 188, 187, 102, 53, 168, 193, 154, 167, 172, 3, 242, 67, 64,144, 137,
+  142, 175, 188, 69, 102, 53, 168, 193, 102, 89, 172, 253, 242, 67,192, 7, 62, 159, 20, 181,
+  182, 187, 216, 207, 22, 105, 132, 109, 162, 205, 16, 151, 18, 113, 228, 37, 6, 85, 8, 161,
+  58, 135, 76, 35, 174, 35, 224, 39, 158, 127, 180, 149, 86, 155, 200, 239, 118, 119, 28, 77,
+  254, 19, 176, 183, 78, 145, 132, 5, 90, 117, 152, 127, 218, 153, 20, 67, 178, 3, 128, 185,
+  254, 95, 172, 139, 246, 123, 104, 15, 42, 169, 68, 211, 98, 243, 80, 41, 174, 79, 36, 27,
+  186, 149, 86, 155, 200, 239, 118, 119, 28, 77, 254, 19, 176, 183,78, 145, 132, 5, 90, 117,
+  152, 127, 218, 153, 20, 67, 178, 3, 128, 185, 254, 95, 172, 139, 246, 123, 104, 15, 42,169,
+  68, 211, 98, 243, 80, 41, 174, 79, 36, 27, 186, 107, 56, 97, 134, 71, 116, 157, 238, 227,
+  32, 153, 162, 193, 244, 171, 150, 165, 248, 209, 54, 55, 164, 13, 194, 45, 16, 247, 242, 47,
+  60, 59, 26, 75, 40, 65, 230, 217, 44, 131, 142, 195, 192, 121, 190, 225, 108, 203, 202, 197,
+  168, 177, 150, 233, 252, 19, 34, 77, 144, 23, 110, 15, 100, 91, 122, 213, 120, 223, 70, 7, 
+  52, 93, 46, 93, 160, 167, 226, 255, 204, 21, 42, 229, 72, 111, 246, 9, 100, 205, 126, 147,
+  215, 82, 79, 36, 229, 70, 149, 56, 159, 134, 185, 140, 99, 18, 29, 224, 153, 94, 63, 244, 85, 150, 91, 248, 209,
+  202, 55, 92, 243, 194, 211, 240, 247, 242, 209, 196, 197, 26, 75, 40, 191, 26, 39, 44, 131, 142, 195, 64, 121, 190,
+  231, 34, 65, 116, 43, 22, 219, 136, 175, 74, 73, 220, 141, 190, 83, 112, 137, 142, 81, 68, 69, 154, 203, 88, 63,
+  154, 89, 172, 3, 242, 67, 192, 249, 62, 159, 20, 181, 74, 69, 216, 49, 22, 105, 132, 109, 162, 205, 16, 151, 18,
+  37, 136, 175, 74, 183, 36, 115, 66, 173, 144, 137, 142, 175, 188, 69, 102, 53, 168, 193, 102, 89, 172, 253, 242, 67,
+  192, 7, 62, 159, 20, 181, 182, 187, 216, 207, 22, 105, 132, 109, 162, 205, 16, 151, 18, 113, 228, 37, 6, 85, 8,
+  161, 58, 135, 76, 35, 174, 35, 224, 39, 158, 127, 180, 149, 86, 155, 200, 239, 118, 119, 28, 77, 254, 19, 176, 183,
+  78, 145, 132, 5, 90, 117, 152, 127, 218, 153, 20, 67, 178, 3, 128, 185, 254, 95, 172, 139, 246, 123, 104, 15, 42,
+
+  251, 24, 113, 170, 215, 60, 83, 30, 115, 48, 169, 210, 49, 92, 101, 58, 21, 184, 225, 6,
+  199, 244, 227, 146, 99, 96, 25, 222, 65, 140, 213, 22, 219, 136, 175, 182, 73, 36, 141, 190, 
+  83, 112, 137, 114, 175, 188, 187, 102, 53, 168, 193, 154, 167, 172, 3, 242, 67, 64,144, 137,
+  142, 175, 188, 69, 102, 53, 168, 193, 102, 89, 172, 253, 242, 67,192, 7, 62, 159, 20, 181,
+  182, 187, 216, 207, 22, 105, 132, 109, 162, 205, 16, 151, 18, 113, 228, 37, 6, 85, 8, 161,
+  58, 135, 76, 35, 174, 35, 224, 39, 158, 127, 180, 149, 86, 155, 200, 239, 118, 119, 28, 77,
+  254, 19, 176, 183, 78, 145, 132, 5, 90, 117, 152, 127, 218, 153, 20, 67, 178, 3, 128, 185,
+  254, 95, 172, 139, 246, 123, 104, 15, 42, 169, 68, 211, 98, 243, 80, 41, 174, 79, 36, 27,
+  186, 149, 86, 155, 200, 239, 118, 119, 28, 77, 254, 19, 176, 183,78, 145, 132, 5, 90, 117,
+  152, 127, 218, 153, 20, 67, 178, 3, 128, 185, 254, 95, 172, 139, 246, 123, 104, 15, 42,169,
+  68, 211, 98, 243, 80, 41, 174, 79, 36, 27, 186, 107, 56, 97, 134, 71, 116, 157, 238, 227,
+  32, 153, 162, 193, 244, 171, 150, 165, 248, 209, 54, 55, 164, 13, 194, 45, 16, 247, 242, 47,
+  60, 59, 26, 75, 40, 65, 230, 217, 44, 131, 142, 195, 192, 121, 190, 225, 108, 203, 202, 197,
+  168, 177, 150, 233, 252, 19, 34, 77, 144, 23, 110, 15, 100, 91, 122, 213, 120, 223, 70, 7, 
+  52, 93, 46, 93, 160, 167, 226, 255, 204, 21, 42, 229, 72, 111, 246, 9, 100, 205, 126, 147,
+  215, 82, 79, 36, 229, 70, 149, 56, 159, 134, 185, 140, 99, 18, 29, 224, 153, 94, 63, 244, 85, 150, 91, 248, 209,
+  202, 55, 92, 243, 194, 211, 240, 247, 242, 209, 196, 197, 26, 75, 40, 191, 26, 39, 44, 131, 142, 195, 64, 121, 190,
+  231, 34, 65, 116, 43, 22, 219, 136, 175, 74, 73, 220, 141, 190, 83, 112, 137, 142, 81, 68, 69, 154, 203, 88, 63,
+  154, 89, 172, 3, 242, 67, 192, 249, 62, 159, 20, 181, 74, 69, 216, 49, 22, 105, 132, 109, 162, 205, 16, 151, 18,
+  37, 136, 175, 74, 183, 36, 115, 66, 173, 144, 137, 142, 175, 188, 69, 102, 53, 168, 193, 102, 89, 172, 253, 242, 67,
+  192, 7, 62, 159, 20, 181, 182, 187, 216, 207, 22, 105, 132, 109, 162, 205, 16, 151, 18, 113, 228, 37, 6, 85, 8,
+  161, 58, 135, 76, 35, 174, 35, 224, 39, 158, 127, 180, 149, 86, 155, 200, 239, 118, 119, 28, 77, 254, 19, 176, 183,
+  78, 145, 132, 5, 90, 117, 152, 127, 218, 153, 20, 67, 178, 3, 128, 185, 254, 95, 172, 139, 246, 123, 104, 15, 42,
+  251, 24, 113, 170, 215, 60, 83, 30, 115, 48, 169, 210, 49, 92, 101, 58, 21, 184, 225, 6,
+  199, 244, 227, 146, 99, 96, 25, 222, 65, 140, 213, 22, 219, 136, 175, 182, 73, 36, 141, 190, 
+  83, 112, 137, 114, 175, 188, 187, 102, 53, 168, 193, 154, 167, 172, 3, 242, 67, 64,144, 137,
+  142, 175, 188, 69, 102, 53, 168, 193, 102, 89, 172, 253, 242, 67,192, 7, 62, 159, 20, 181,
+  182, 187, 216, 207, 22, 105, 132, 109, 162, 205, 16, 151, 18, 113, 228, 37, 6, 85, 8, 161,
+  58, 135, 76, 35, 174, 35, 224, 39, 158, 127, 180, 149, 86, 155, 200, 239, 118, 119, 28, 77,
+  254, 19, 176, 183, 78, 145, 132, 5, 90, 117, 152, 127, 218, 153, 20, 67, 178, 3, 128, 185,
+  254, 95, 172, 139, 246, 123, 104, 15, 42, 169, 68, 211, 98, 243, 80, 41, 174, 79, 36, 27,
+  186, 149, 86, 155, 200, 239, 118, 119, 28, 77, 254, 19, 176, 183,78, 145, 132, 5, 90, 117,
+  152, 127, 218, 153, 20, 67, 178, 3, 128, 185, 254, 95, 172, 139, 246, 123, 104, 15, 42,169,
+  68, 211, 98, 243, 80, 41, 174, 79, 36, 27, 186, 107, 56, 97, 134, 71, 116, 157, 238, 227,
+  32, 153, 162, 193, 244, 171, 150, 165, 248, 209, 54, 55, 164, 13, 194, 45, 16, 247, 242, 47,
+  60, 59, 26, 75, 40, 65, 230, 217, 44, 131, 142, 195, 192, 121, 190, 225, 108, 203, 202, 197,
+  168, 177, 150, 233, 252, 19, 34, 77, 144, 23, 110, 15, 100, 91, 122, 213, 120, 223, 70, 7, 
+  52, 93, 46, 93, 160, 167, 226, 255, 204, 21, 42, 229, 72, 111, 246, 9, 100, 205, 126, 147,
+  215, 82, 79, 36, 229, 70, 149, 56, 159, 134, 185, 140, 99, 18, 29, 224, 153, 94, 63, 244, 85, 150, 91, 248, 209,
+  202, 55, 92, 243, 194, 211, 240, 247, 242, 209, 196, 197, 26, 75, 40, 191, 26, 39, 44, 131, 142, 195, 64, 121, 190,
+  231, 34, 65, 116, 43, 22, 219, 136, 175, 74, 73, 220, 141, 190, 83, 112, 137, 142, 81, 68, 69, 154, 203, 88, 63,
+  154, 89, 172, 3, 242, 67, 192, 249, 62, 159, 20, 181, 74, 69, 216, 49, 22, 105, 132, 109, 162, 205, 16, 151, 18,
+  37, 136, 175, 74, 183, 36, 115, 66, 173, 144, 137, 142, 175, 188, 69, 102, 53, 168, 193, 102, 89, 172, 253, 242, 67,
+  192, 7, 62, 159, 20, 181, 182, 187, 216, 207, 22, 105, 132, 109, 162, 205, 16, 151, 18, 113, 228, 37, 6, 85, 8,
+  161, 58, 135, 76, 35, 174, 35, 224, 39, 158, 127, 180, 149, 86, 155, 200, 239, 118, 119, 28, 77, 254, 19, 176, 183,
+  78, 145, 132, 5, 90, 117, 152, 127, 218, 153, 20, 67, 178, 3, 128, 185, 254, 95, 172, 139, 246, 123, 104, 15, 42,
+
+  251, 24, 113, 170, 215, 60, 83, 30, 115, 48, 169, 210, 49, 92, 101, 58, 21, 184, 225, 6,
+  199, 244, 227, 146, 99, 96, 25, 222, 65, 140, 213, 22, 219, 136, 175, 182, 73, 36, 141, 190, 
+  83, 112, 137, 114, 175, 188, 187, 102, 53, 168, 193, 154, 167, 172, 3, 242, 67, 64,144, 137,
+  142, 175, 188, 69, 102, 53, 168, 193, 102, 89, 172, 253, 242, 67,192, 7, 62, 159, 20, 181,
+  182, 187, 216, 207, 22, 105, 132, 109, 162, 205, 16, 151, 18, 113, 228, 37, 6, 85, 8, 161,
+  58, 135, 76, 35, 174, 35, 224, 39, 158, 127, 180, 149, 86, 155, 200, 239, 118, 119, 28, 77,
+  254, 19, 176, 183, 78, 145, 132, 5, 90, 117, 152, 127, 218, 153, 20, 67, 178, 3, 128, 185,
+  254, 95, 172, 139, 246, 123, 104, 15, 42, 169, 68, 211, 98, 243, 80, 41, 174, 79, 36, 27,
+  186, 149, 86, 155, 200, 239, 118, 119, 28, 77, 254, 19, 176, 183,78, 145, 132, 5, 90, 117,
+  152, 127, 218, 153, 20, 67, 178, 3, 128, 185, 254, 95, 172, 139, 246, 123, 104, 15, 42,169,
+  68, 211, 98, 243, 80, 41, 174, 79, 36, 27, 186, 107, 56, 97, 134, 71, 116, 157, 238, 227,
+  32, 153, 162, 193, 244, 171, 150, 165, 248, 209, 54, 55, 164, 13, 194, 45, 16, 247, 242, 47,
+  60, 59, 26, 75, 40, 65, 230, 217, 44, 131, 142, 195, 192, 121, 190, 225, 108, 203, 202, 197,
+  168, 177, 150, 233, 252, 19, 34, 77, 144, 23, 110, 15, 100, 91, 122, 213, 120, 223, 70, 7, 
+  52, 93, 46, 93, 160, 167, 226, 255, 204, 21, 42, 229, 72, 111, 246, 9, 100, 205, 126, 147,
+  215, 82, 79, 36, 229, 70, 149, 56, 159, 134, 185, 140, 99, 18, 29, 224, 153, 94, 63, 244, 85, 150, 91, 248, 209,
+  202, 55, 92, 243, 194, 211, 240, 247, 242, 209, 196, 197, 26, 75, 40, 191, 26, 39, 44, 131, 142, 195, 64, 121, 190,
+  231, 34, 65, 116, 43, 22, 219, 136, 175, 74, 73, 220, 141, 190, 83, 112, 137, 142, 81, 68, 69, 154, 203, 88, 63,
+  154, 89, 172, 3, 242, 67, 192, 249, 62, 159, 20, 181, 74, 69, 216, 49, 22, 105, 132, 109, 162, 205, 16, 151, 18,
+  37, 136, 175, 74, 183, 36, 115, 66, 173, 144, 137, 142, 175, 188, 69, 102, 53, 168, 193, 102, 89, 172, 253, 242, 67,
+  192, 7, 62, 159, 20, 181, 182, 187, 216, 207, 22, 105, 132, 109, 162, 205, 16, 151, 18, 113, 228, 37, 6, 85, 8,
+  161, 58, 135, 76, 35, 174, 35, 224, 39, 158, 127, 180, 149, 86, 155, 200, 239, 118, 119, 28, 77, 254, 19, 176, 183,
+  78, 145, 132, 5, 90, 117, 152, 127, 218, 153, 20, 67, 178, 3, 128, 185, 254, 95, 172, 139, 246, 123, 104, 15, 42,
+  251, 24, 113, 170, 215, 60, 83, 30, 115, 48, 169, 210, 49, 92, 101, 58, 21, 184, 225, 6,
+  199, 244, 227, 146, 99, 96, 25, 222, 65, 140, 213, 22, 219, 136, 175, 182, 73, 36, 141, 190, 
+  83, 112, 137, 114, 175, 188, 187, 102, 53, 168, 193, 154, 167, 172, 3, 242, 67, 64,144, 137,
+  142, 175, 188, 69, 102, 53, 168, 193, 102, 89, 172, 253, 242, 67,192, 7, 62, 159, 20, 181,
+  182, 187, 216, 207, 22, 105, 132, 109, 162, 205, 16, 151, 18, 113, 228, 37, 6, 85, 8, 161,
+  58, 135, 76, 35, 174, 35, 224, 39, 158, 127, 180, 149, 86, 155, 200, 239, 118, 119, 28, 77,
+  254, 19, 176, 183, 78, 145, 132, 5, 90, 117, 152, 127, 218, 153, 20, 67, 178, 3, 128, 185,
+  254, 95, 172, 139, 246, 123, 104, 15, 42, 169, 68, 211, 98, 243, 80, 41, 174, 79, 36, 27,
+  186, 149, 86, 155, 200, 239, 118, 119, 28, 77, 254, 19, 176, 183,78, 145, 132, 5, 90, 117,
+  152, 127, 218, 153, 20, 67, 178, 3, 128, 185, 254, 95, 172, 139, 246, 123, 104, 15, 42,169,
+  68, 211, 98, 243, 80, 41, 174, 79, 36, 27, 186, 107, 56, 97, 134, 71, 116, 157, 238, 227,
+  32, 153, 162, 193, 244, 171, 150, 165, 248, 209, 54, 55, 164, 13, 194, 45, 16, 247, 242, 47,
+  60, 59, 26, 75, 40, 65, 230, 217, 44, 131, 142, 195, 192, 121, 190, 225, 108, 203, 202, 197,
+  168, 177, 150, 233, 252, 19, 34, 77, 144, 23, 110, 15, 100, 91, 122, 213, 120, 223, 70, 7, 
+  52, 93, 46, 93, 160, 167, 226, 255, 204, 21, 42, 229, 72, 111, 246, 9, 100, 205, 126, 147,
+  215, 82, 79, 36, 229, 70, 149, 56, 159, 134, 185, 140, 99, 18, 29, 224, 153, 94, 63, 244, 85, 150, 91, 248, 209,
+  202, 55, 92, 243, 194, 211, 240, 247, 242, 209, 196, 197, 26, 75, 40, 191, 26, 39, 44, 131, 142, 195, 64, 121, 190,
+  231, 34, 65, 116, 43, 22, 219, 136, 175, 74, 73, 220, 141, 190, 83, 112, 137, 142, 81, 68, 69, 154, 203, 88, 63,
+  154, 89, 172, 3, 242, 67, 192, 249, 62, 159, 20, 181, 74, 69, 216, 49, 22, 105, 132, 109, 162, 205, 16, 151, 18,
+  37, 136, 175, 74, 183, 36, 115, 66, 173, 144, 137, 142, 175, 188, 69, 102, 53, 168, 193, 102, 89, 172, 253, 242, 67,
+  192, 7, 62, 159, 20, 181, 182, 187, 216, 207, 22, 105, 132, 109, 162, 205, 16, 151, 18, 113, 228, 37, 6, 85, 8,
+  161, 58, 135, 76, 35, 174, 35, 224, 39, 158, 127, 180, 149, 86, 155, 200, 239, 118, 119, 28, 77, 254, 19, 176, 183,
+  78, 145, 132, 5, 90, 117, 152, 127, 218, 153, 20, 67, 178, 3, 128, 185, 254, 95, 172, 139, 246, 123, 104, 15, 42,
+
+  251, 24, 113, 170, 215, 60, 83, 30, 115, 48, 169, 210, 49, 92, 101, 58, 21, 184, 225, 6,
+  199, 244, 227, 146, 99, 96, 25, 222, 65, 140, 213, 22, 219, 136, 175, 182, 73, 36, 141, 190, 
+  83, 112, 137, 114, 175, 188, 187, 102, 53, 168, 193, 154, 167, 172, 3, 242, 67, 64,144, 137,
+  142, 175, 188, 69, 102, 53, 168, 193, 102, 89, 172, 253, 242, 67,192, 7, 62, 159, 20, 181,
+  182, 187, 216, 207, 22, 105, 132, 109, 162, 205, 16, 151, 18, 113, 228, 37, 6, 85, 8, 161,
+  58, 135, 76, 35, 174, 35, 224, 39, 158, 127, 180, 149, 86, 155, 200, 239, 118, 119, 28, 77,
+  254, 19, 176, 183, 78, 145, 132, 5, 90, 117, 152, 127, 218, 153, 20, 67, 178, 3, 128, 185,
+  254, 95, 172, 139, 246, 123, 104, 15, 42, 169, 68, 211, 98, 243, 80, 41, 174, 79, 36, 27,
+  186, 149, 86, 155, 200, 239, 118, 119, 28, 77, 254, 19, 176, 183,78, 145, 132, 5, 90, 117,
+  152, 127, 218, 153, 20, 67, 178, 3, 128, 185, 254, 95, 172, 139, 246, 123, 104, 15, 42,169,
+  68, 211, 98, 243, 80, 41, 174, 79, 36, 27, 186, 107, 56, 97, 134, 71, 116, 157, 238, 227,
+  32, 153, 162, 193, 244, 171, 150, 165, 248, 209, 54, 55, 164, 13, 194, 45, 16, 247, 242, 47,
+  60, 59, 26, 75, 40, 65, 230, 217, 44, 131, 142, 195, 192, 121, 190, 225, 108, 203, 202, 197,
+  168, 177, 150, 233, 252, 19, 34, 77, 144, 23, 110, 15, 100, 91, 122, 213, 120, 223, 70, 7, 
+  52, 93, 46, 93, 160, 167, 226, 255, 204, 21, 42, 229, 72, 111, 246, 9, 100, 205, 126, 147,
+  215, 82, 79, 36, 229, 70, 149, 56, 159, 134, 185, 140, 99, 18, 29, 224, 153, 94, 63, 244, 85, 150, 91, 248, 209,
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+  78, 145, 132, 5, 90, 117, 152, 127, 218, 153, 20, 67, 178, 3, 128, 185, 254, 95, 172, 139, 246, 123, 104, 15, 42,
+  251, 24, 113, 170, 215, 60, 83, 30, 115, 48, 169, 210, 49, 92, 101, 58, 21, 184, 225, 6,
+  199, 244, 227, 146, 99, 96, 25, 222, 65, 140, 213, 22, 219, 136, 175, 182, 73, 36, 141, 190, 
+  83, 112, 137, 114, 175, 188, 187, 102, 53, 168, 193, 154, 167, 172, 3, 242, 67, 64,144, 137,
+  142, 175, 188, 69, 102, 53, 168, 193, 102, 89, 172, 253, 242, 67,192, 7, 62, 159, 20, 181,
+  182, 187, 216, 207, 22, 105, 132, 109, 162, 205, 16, 151, 18, 113, 228, 37, 6, 85, 8, 161,
+  58, 135, 76, 35, 174, 35, 224, 39, 158, 127, 180, 149, 86, 155, 200, 239, 118, 119, 28, 77,
+  254, 19, 176, 183, 78, 145, 132, 5, 90, 117, 152, 127, 218, 153, 20, 67, 178, 3, 128, 185,
+  254, 95, 172, 139, 246, 123, 104, 15, 42, 169, 68, 211, 98, 243, 80, 41, 174, 79, 36, 27,
+  186, 149, 86, 155, 200, 239, 118, 119, 28, 77, 254, 19, 176, 183,78, 145, 132, 5, 90, 117,
+  152, 127, 218, 153, 20, 67, 178, 3, 128, 185, 254, 95, 172, 139, 246, 123, 104, 15, 42,169,
+  68, 211, 98, 243, 80, 41, 174, 79, 36, 27, 186, 107, 56, 97, 134, 71, 116, 157, 238, 227,
+  32, 153, 162, 193, 244, 171, 150, 165, 248, 209, 54, 55, 164, 13, 194, 45, 16, 247, 242, 47,
+  60, 59, 26, 75, 40, 65, 230, 217, 44, 131, 142, 195, 192, 121, 190, 225, 108, 203, 202, 197,
+  168, 177, 150, 233, 252, 19, 34, 77, 144, 23, 110, 15, 100, 91, 122, 213, 120, 223, 70, 7, 
+  52, 93, 46, 93, 160, 167, 226, 255, 204, 21, 42, 229, 72, 111, 246, 9, 100, 205, 126, 147,
+  215, 82, 79, 36, 229, 70, 149, 56, 159, 134, 185, 140, 99, 18, 29, 224, 153, 94, 63, 244, 85, 150, 91, 248, 209,
+  202, 55, 92, 243, 194, 211, 240, 247, 242, 209, 196, 197, 26, 75, 40, 191, 26, 39, 44, 131, 142, 195, 64, 121, 190,
+  231, 34, 65, 116, 43, 22, 219, 136, 175, 74, 73, 220, 141, 190, 83, 112, 137, 142, 81, 68, 69, 154, 203, 88, 63,
+  154, 89, 172, 3, 242, 67, 192, 249, 62, 159, 20, 181, 74, 69, 216, 49, 22, 105, 132, 109, 162, 205, 16, 151, 18,
+  37, 136, 175, 74, 183, 36, 115, 66, 173, 144, 137, 142, 175, 188, 69, 102, 53, 168, 193, 102, 89, 172, 253, 242, 67,
+  192, 7, 62, 159, 20, 181, 182, 187, 216, 207, 22, 105, 132, 109, 162, 205, 16, 151, 18, 113, 228, 37, 6, 85, 8,
+  161, 58, 135, 76, 35, 174, 35, 224, 39, 158, 127, 180, 149, 86, 155, 200, 239, 118, 119, 28, 77, 254, 19, 176, 183,
+  78, 145, 132, 5, 90, 117, 152, 127, 218, 153, 20, 67, 178, 3, 128, 185, 254, 95, 172, 139, 246, 123, 104, 15, 42,
+  251, 24, 113, 170, 215, 60, 83, 30, 115, 48, 169, 210, 49, 92, 101, 58, 21, 184, 225, 6,
+  199, 244, 227, 146, 99, 96, 25, 222, 65, 140, 213, 22, 219, 136, 175, 182, 73, 36, 141, 190, 
+  83, 112, 137, 114, 175, 188, 187, 102, 53, 168, 193, 154, 167, 172, 3, 242, 67, 64,144, 137,
+  142, 175, 188, 69, 102, 53, 168, 193, 102, 89, 172, 253, 242, 67,192, 7, 62, 159, 20, 181,
+  182, 187, 216, 207, 22, 105, 132, 109, 162, 205, 16, 151, 18, 113, 228, 37, 6, 85, 8, 161,
+  58, 135, 76, 35, 174, 35, 224, 39, 158, 127, 180, 149, 86, 155, 200, 239, 118, 119, 28, 77,
+  254, 19, 176, 183, 78, 145, 132, 5, 90, 117, 152, 127, 218, 153, 20, 67, 178, 3, 128, 185,
+  254, 95, 172, 139, 246, 123, 104, 15, 42, 169, 68, 211, 98, 243, 80, 41, 174, 79, 36, 27,
+  186, 149, 86, 155, 200, 239, 118, 119, 28, 77, 254, 19, 176, 183,78, 145, 132, 5, 90, 117,
+  152, 127, 218, 153, 20, 67, 178, 3, 128, 185, 254, 95, 172, 139, 246, 123, 104, 15, 42,169,
+  68, 211, 98, 243, 80, 41, 174, 79, 36, 27, 186, 107, 56, 97, 134, 71, 116, 157, 238, 227,
+  32, 153, 162, 193, 244, 171, 150, 165, 248, 209, 54, 55, 164, 13, 194, 45, 16, 247, 242, 47,
+  60, 59, 26, 75, 40, 65, 230, 217, 44, 131, 142, 195, 192, 121, 190, 225, 108, 203, 202, 197,
+  168, 177, 150, 233, 252, 19, 34, 77, 144, 23, 110, 15, 100, 91, 122, 213, 120, 223, 70, 7, 
+  52, 93, 46, 93, 160, 167, 226, 255, 204, 21, 42, 229, 72, 111, 246, 9, 100, 205, 126, 147,
+  215, 82, 79, 36, 229, 70, 149, 56, 159, 134, 185, 140, 99, 18, 29, 224, 153, 94, 63, 244, 85, 150, 91, 248, 209,
+  202, 55, 92, 243, 194, 211, 240, 247, 242, 209, 196, 197, 26, 75, 40, 191, 26, 39, 44, 131, 142, 195, 64, 121, 190,
+  231, 34, 65, 116, 43, 22, 219, 136, 175, 74, 73, 220, 141, 190, 83, 112, 137, 142, 81, 68, 69, 154, 203, 88, 63,
+  154, 89, 172, 3, 242, 67, 192, 249, 62, 159, 20, 181, 74, 69, 216, 49, 22, 105, 132, 109, 162, 205, 16, 151, 18,
+  37, 136, 175, 74, 183, 36, 115, 66, 173, 144, 137, 142, 175, 188, 69, 102, 53, 168, 193, 102, 89, 172, 253, 242, 67,
+  192, 7, 62, 159, 20, 181, 182, 187, 216, 207, 22, 105, 132, 109, 162, 205, 16, 151, 18, 113, 228, 37, 6, 85, 8,
+  161, 58, 135, 76, 35, 174, 35, 224, 39, 158, 127, 180, 149, 86, 155, 200, 239, 118, 119, 28, 77, 254, 19, 176, 183,
+  78, 145, 132, 5, 90, 117, 152, 127, 218, 153, 20, 67, 178, 3, 128, 185, 254, 95, 172, 139, 246, 123, 104, 15, 42
+  
+};
+*/
+
+  unsigned int SortArr0[2*(SIZE)];
+
+void SORT(int *base, int n, int size, int (*compar) (),int type);
+void QSORT(int *base, int n, int size, int (*compar) ());
+void simple_sort(int *base, int n, int size, int (*compar) ());
+void insertion_sort(int *base, int n, int size, int (*compar) ());
+void bubble_sort(int *base, int n, int size, int (*compar) ());
+int compare(int *n1, int *n2)
+{
+  return (*((unsigned int *) n1) - *((unsigned int *) n2));
+}
+
+int main()
+{
+/* -------------------------------------------------- */
+	// define the page table entry
+        uint32_t * ptd_table;
+        ptd_table = (uint32_t *)PTD_ADDR;
+
+        ptd_table[2] = 0xC0040403; 	// PTD for instruction 	 
+        ptd_table[4] = 0xC0040402; 	// PTD for tty
+
+        ptd_table[128] = 0x8D000080; 	// PTE for data ram
+        ptd_table[1024] = 0x8D800400; 	// PTE for exception
+	
+	// tty pte
+        uint32_t * pte_table;
+        pte_table = (uint32_t *)PTE_ADDR;
+        pte_table[0] = 0x85000000;	//tty no global
+        pte_table[1] = 0x000C0200;	//tty no global
+
+	// instruction pte
+        uint32_t * ipte_table;
+        ipte_table = (uint32_t *)IPTE_ADDR;
+	ipte_table[0] = 0x8B000000;
+	ipte_table[1] = 0x00000400;
+
+	puts("Page table are defined! \n");
+
+	// context switch and tlb mode change
+	//set_cp2(0, 0, 0x04040000);	// context switch
+	set_cp2(0, 0, 0x00020200);	// context switch
+	set_cp2(1, 0, 0xf);		// TLB enable
+	puts("Context switch(TLB flush) and TLB enable!\n");
+
+	set_cp2(2, 0, 0);
+	puts("icache flush done!\n");
+
+	set_cp2(3, 0, 0);
+	puts("dcache flush done!\n");
+
+	// cache inval
+	//set_cp2(6, 0, 0x004000a4);
+	set_cp2(6, 0, 0x004000c4);
+	puts("icache invalidation test good :-)\n");
+	set_cp2(7, 0, 0x00800000);
+	puts("dcache invalidation test good :-) \n");
+
+	// tlb inval
+	puts("TLB invalidation test begin: \n");
+	set_cp2(4, 0, 0x00400000);
+	puts("itlb invalidation test good :-) \n");
+	set_cp2(5, 0, 0x00800000);
+	puts("dtlb invalidation test good :-) \n");
+
+/* -------------------------------------------------- */
+
+  register int p; 
+
+  p=procnum();
+
+  puts("Hello from processor ");
+  putchar(p+'0');
+  putchar('\n');
+
+
+  int i;
+  int j;
+  int temp;
+
+  if(p+1 <= nprocs){
+	for(i=1 ; i <= 8 ; i++ ){
+  	puts("Memory copy \n");
+	memcpy(SortArr0+p*(SIZE), gQSortNum0 + ( (4*(p+1)*i) % 32) ,SIZE);
+	
+  	puts("Sort... \n");
+  	SORT((int *) (SortArr0+p*(SIZE)), (int) SIZE, sizeof(unsigned int), compare,SORT_TYPE);
+  	for (j = 1; j < SIZE; j++)
+    	{
+      		if (SortArr0[p*(SIZE)+j] < SortArr0[p*(SIZE) + j - 1])
+		{
+	  		puts("ucbqsort: failed\n");
+			while(1);
+		}
+
+    	}
+  	puts("ucbqsort: success\n");
+	}
+  }
+  
+
+  if(p+1 <= nprocs){
+	lock_lock(&lock);
+	compteur--;
+	if(!compteur){
+  		putchar('\n');
+  		puti(temp);
+  		putchar('\n');
+	}
+	lock_unlock(&lock);
+  }
+
+  while(1);
+}
+
+static int (*qcmp) ();
+static int qsz;
+static int thresh;
+static int mthresh;
+static void qst(int *, int *);
+void QSORT(base, n, size, compar)
+     int *base;
+     int n;
+     int size;
+     int (*compar) ();
+{
+  register int c, *i, *j, *lo, *hi;
+  int *min, *max;
+  if (n <= 1)
+    return;
+  qsz = size;
+  qcmp = compar;
+  thresh = 4;
+  mthresh = 6;
+  max = base + n;
+  if (n >= 4)
+    {
+      qst(base, max);
+      hi = base + thresh;
+    } 
+  else
+    {
+      hi = max;
+    }
+
+  puts("Quick sort done... \n");
+
+  for (j = lo = base; (lo ++) < hi;)
+    if ((*qcmp) (j, lo) > 0)
+      j = lo;
+  if (j != base)
+    {
+      for (i = base, hi = base + 1; i < hi;)
+	{
+	  c = *j;
+	  *j++ = *i;
+	  *i++ = c;
+	}
+
+    }
+  for (min = base; (hi = min ++) < max;)
+    {
+      while ((*qcmp) (hi --, min) > 0)
+	;
+      if ((hi ++) != min)
+	{
+	  for (lo = min + 1; --lo >= min;)
+	    {
+	      c = *lo;
+	      for (i = j = lo; (j --) >= hi; i = j)
+		*i = *j;
+	      *i = c;
+	    }
+
+	}
+    }
+
+}
+
+
+void simple_sort(base, n, size, compar)
+     int *base;
+     int n;
+     int size;
+     int (*compar) ();
+{
+  register int c, *i, *j, *lo, p, *k;
+  int *max;
+  if (n <= 1)
+    return;
+  qsz = size;
+  qcmp = compar;
+  max = base + n;
+  puts("Selection Sort\n");
+  p=procnum();
+//  k=4;
+  for(j = base; j < max ; j++){
+    lo=j;
+    c=(*lo);
+    for(i = j; i < max ; i++){
+	asm("	nop		\n"); //1
+      if( c-(*i) > 0){
+ 	lo=i;
+        c=(*lo);
+      }
+      asm("	nop		\n"); // 1
+    }
+    *lo = *j;
+    *j = c;
+  }
+}
+
+void insertion_sort(base, n, size, compar)
+     int *base;
+     int n;
+     int size;
+     int (*compar) ();
+{
+  register int c, *i, *j,p;
+  int *max;
+  if (n <= 1)
+    return;
+  qsz = size;
+  qcmp = compar;
+  max = base + n;
+  puts("Insertion Sort\n");
+  p=procnum();
+  for(j = base; j < max-1 ; j++){
+    for(i = j; i < max-1 ; i++){
+      if( (*i)-(*(i+1)) > 0){
+ 	c = *i;
+	*i = *(i+1);
+	*(i+1)=c;
+      }
+    }
+  }
+}
+
+
+void bubble_sort(base, n, size, compar)
+     int *base;
+     int n;
+     int size;
+     int (*compar) ();
+{
+  register int c, *i;
+  register int b_swap=1;
+  int *max;
+  if (n <= 1)
+    return;
+  qsz = size;
+  qcmp = compar;
+  max = base + n;
+  puts("Bubble Sort\n");
+  while(b_swap){
+    b_swap=0;
+    for(i = base; i < max-1 ; i++){
+      if( (*i)-(*(i+1)) > 0){
+	b_swap=1;
+ 	c = *i;
+	*i = *(i+1);
+	*(i+1)=c;
+      }
+    }
+  }
+}
+
+static
+void qst(base, max)
+     int *base, *max;
+{
+  register int c, *i, *j, *jj;
+  register int ii;
+  int *mid, *tmp;
+  int lo, hi;
+  lo = max - base;
+  do
+    {
+      mid = i = base + 1 * ((lo / qsz) >> 1);
+      if (lo >= mthresh)
+	{
+	  j = ((*qcmp) ((jj = base), i) > 0 ? jj : i);
+	  if ((*qcmp) (j, (tmp = max - 1)) > 0)
+	    {
+	      j = (j == jj ? i : jj);
+	      if ((*qcmp) (j, tmp) < 0)
+		j = tmp;
+	    }
+
+	  if (j != i)
+	    {
+	      ii = 1;
+	      do
+		{
+		  c = *i;
+		  *i++ = *j;
+		  *j++ = c;
+		}
+
+	      while (--ii);
+	    }
+
+	}
+      for (i = base, j = max - 1;;)
+	{
+	  while (i < mid && (*qcmp) (i, mid) <= 0)
+            i ++;
+	  while (j > mid)
+	    {
+	      if ((*qcmp) (mid, j) <= 0)
+		{
+		  j --;
+		  continue;
+		}
+
+	      tmp = i + 1;
+	      if (i == mid)
+		{
+		  mid = jj = j;
+		} 
+	      else
+		{
+		  jj = j;
+		  j --;
+		}
+
+	      goto swap;
+	    }
+
+	  if (i == mid)
+	    {
+	      break;
+	    } 
+	  else
+	    {
+	      jj = mid;
+	      tmp = mid = i;
+	      j --;
+	    }
+
+	swap:
+	  ii = 1;
+	  do
+	    {
+	      c = *i;
+	      *i++ = *jj;
+	      *jj++ = c;
+	    }
+
+	  while (--ii);
+	  i = tmp;
+	}
+
+      i = (j = mid) + 1;
+      if ((lo = j - base) <= (hi = max - i))
+	{
+	  if (lo >= thresh)
+            qst(base, j);
+	  base = i;
+	  lo = hi;
+	} 
+      else
+	{
+	  if (hi >= thresh)
+            qst(i, max);
+	  max = j;
+	}
+
+    }
+  while (lo >= thresh);
+}
+
+void SORT(int *base, int n, int size, int (*compar) (),int type){
+  switch(type){
+  case 0:
+    QSORT(base, n, size, compar);
+    break;
+  case 1:
+    simple_sort(base, n, size, compar);
+    break;
+  case 2:
+    insertion_sort(base, n, size, compar);
+    break;
+  case 3:
+    bubble_sort(base, n, size, compar);
+    break;
+  default:
+    break;
+  }
+
+}
+
+
+
Index: branches/v4/platforms/caba-vgmn-vcache2_memcache-mipsel/top.cpp
===================================================================
--- branches/v4/platforms/caba-vgmn-vcache2_memcache-mipsel/top.cpp	(revision 371)
+++ branches/v4/platforms/caba-vgmn-vcache2_memcache-mipsel/top.cpp	(revision 371)
@@ -0,0 +1,265 @@
+
+#include <systemc>
+#include <sys/time.h>
+#include <iostream>
+#include <cstdlib>
+#include <cstdarg>
+
+#include "mapping_table.h"
+#include "mips32.h"
+#include "iss2_simhelper.h"
+#include "vci_simple_ram.h"
+#include "vci_multi_tty.h"
+#include "vci_vgmn.h"
+#include "vci_mem_cache.h"
+//#include "vci_cc_vcache_wrapper.h"
+#include "vci_cc_vcache_wrapper2.h"
+
+
+#ifdef USE_GDB_SERVER
+#include "iss/gdbserver.h"
+#endif
+
+#include "segmentation.h"
+
+int _main(int argc, char *argv[])
+{
+	using namespace sc_core;
+	// Avoid repeating these everywhere
+	using soclib::common::IntTab;
+	using soclib::common::Segment;
+
+	// Define VCI parameters
+	typedef soclib::caba::VciParams<4,8,32,1,1,1,14,4,4,1> vci_param;
+	typedef soclib::common::Iss2Simhelper<soclib::common::Mips32ElIss> proc_iss;
+	// Mapping table
+
+	soclib::common::MappingTable maptabp(32, IntTab(8), IntTab(8), 0x00300000);
+
+	maptabp.add(Segment("reset", RESET_BASE, RESET_SIZE, IntTab(2), true));
+	maptabp.add(Segment("excep", EXCEP_BASE, EXCEP_SIZE, IntTab(2), true));
+	maptabp.add(Segment("text" , TEXT_BASE , TEXT_SIZE , IntTab(2), true));
+	maptabp.add(Segment("tty"  , TTY_BASE  , TTY_SIZE  , IntTab(1), false));
+	maptabp.add(Segment("mc_r" , MC_R_BASE , MC_R_SIZE , IntTab(2), false, true, IntTab(0)));
+	maptabp.add(Segment("mc_m" , MC_M_BASE , MC_M_SIZE , IntTab(2), true ));
+	//maptabp.add(Segment("ptba" ,  PTD_ADDR , TAB_SIZE  , IntTab(0), false));
+	maptabp.add(Segment("ptba" ,  PTD_ADDR , TAB_SIZE  , IntTab(2), true));
+
+	std::cout << maptabp << std::endl;
+
+        soclib::common::MappingTable maptabc(32, IntTab(8), IntTab(8), 0x00300000);
+	maptabc.add(Segment("proc0" , PROC0_BASE , PROC0_SIZE , IntTab(0), false, true, IntTab(0)));
+	maptabc.add(Segment("proc1" , PROC1_BASE , PROC1_SIZE , IntTab(1), false, true, IntTab(1)));
+	std::cout << maptabc << std::endl;
+	
+	soclib::common::MappingTable maptabx(32, IntTab(8), IntTab(8), 0x00300000);
+	maptabx.add(Segment("xram" , MC_M_BASE , MC_M_SIZE , IntTab(0), true));
+	maptabx.add(Segment("ptba" , PTD_ADDR  , TAB_SIZE  , IntTab(0), true));
+	maptabx.add(Segment("reset", RESET_BASE, RESET_SIZE, IntTab(0), true));
+	maptabx.add(Segment("excep", EXCEP_BASE, EXCEP_SIZE, IntTab(0), true));
+	maptabx.add(Segment("text" , TEXT_BASE , TEXT_SIZE , IntTab(0), true));
+
+	std::cout << maptabx << std::endl;
+
+	// Signals
+	sc_clock	signal_clk("clk");
+	sc_signal<bool> signal_resetn("resetn");
+   
+	sc_signal<bool> signal_proc0_it0("proc0_it0"); 
+	sc_signal<bool> signal_proc0_it1("proc0_it1"); 
+	sc_signal<bool> signal_proc0_it2("proc0_it2"); 
+	sc_signal<bool> signal_proc0_it3("proc0_it3"); 
+	sc_signal<bool> signal_proc0_it4("proc0_it4"); 
+	sc_signal<bool> signal_proc0_it5("proc0_it5");
+
+	sc_signal<bool> signal_proc1_it0("proc1_it0"); 
+	sc_signal<bool> signal_proc1_it1("proc1_it1"); 
+	sc_signal<bool> signal_proc1_it2("proc1_it2"); 
+	sc_signal<bool> signal_proc1_it3("proc1_it3"); 
+	sc_signal<bool> signal_proc1_it4("proc1_it4"); 
+	sc_signal<bool> signal_proc1_it5("proc1_it5");
+
+	soclib::caba::VciSignals<vci_param> signal_vci_ini_proc0("vci_ini_proc0");
+	soclib::caba::VciSignals<vci_param> signal_vci_tgt_proc0("vci_tgt_proc0");
+
+	soclib::caba::VciSignals<vci_param> signal_vci_ini_proc1("vci_ini_proc1");
+	soclib::caba::VciSignals<vci_param> signal_vci_tgt_proc1("vci_tgt_proc1");
+
+	soclib::caba::VciSignals<vci_param> signal_vci_tgt_tty("vci_tgt_tty");
+
+	soclib::caba::VciSignals<vci_param> signal_vci_tgt_rom("vci_tgt_rom");
+
+	soclib::caba::VciSignals<vci_param> signal_vci_tgt_xram("vci_tgt_xram");
+
+	soclib::caba::VciSignals<vci_param> signal_vci_ixr_memc("vci_ixr_memc");
+	soclib::caba::VciSignals<vci_param> signal_vci_ini_memc("vci_ini_memc");
+	soclib::caba::VciSignals<vci_param> signal_vci_tgt_memc("vci_tgt_memc");
+
+	sc_signal<bool> signal_tty_irq0("signal_tty_irq0"); 
+	sc_signal<bool> signal_tty_irq1("signal_tty_irq1"); 
+
+	// Components
+	// VCI ports indexation : 3 intiateurs et 5 cibles
+
+        // INIT0 : proc_ini
+        // INIT1 : memc_ini
+        // INIT2 : memc_ixr
+
+	// TGT 0 : rom_tgt
+	// TGT 1 : tty_tgt
+        // TGT 2 : xram_tgt
+	// TGT 3 : memc_tgt
+	// TGT 4 : proc_tgt
+
+	soclib::common::Loader loader("soft/bin.soft");
+/*
+	soclib::caba::VciCcVCacheWrapper<vci_param, proc_iss > 
+	proc0("proc0", 0, maptabp, maptabc, IntTab(0),IntTab(0),4,16,4,16,4,64,16,4,64,16,16);
+	
+	soclib::caba::VciCcVCacheWrapper<vci_param, proc_iss > 
+	proc1("proc1", 1, maptabp, maptabc, IntTab(1),IntTab(1),4,16,4,16,4,64,16,4,64,16,16);
+*/
+	soclib::caba::VciCcVCacheWrapper2<vci_param, proc_iss > 
+	proc0("proc0", 0, maptabp, maptabc, IntTab(0),IntTab(0),4,16,4,16,4,64,16,4,64,16,16);
+
+	soclib::caba::VciCcVCacheWrapper2<vci_param, proc_iss > 
+	proc1("proc1", 1, maptabp, maptabc, IntTab(1),IntTab(1),4,16,4,16,4,64,16,4,64,16,16);
+
+	soclib::caba::VciSimpleRam<vci_param> 
+	rom("rom", IntTab(0), maptabp, loader);
+
+	soclib::caba::VciSimpleRam<vci_param> 
+	xram("xram", IntTab(0), maptabx, loader);
+
+	soclib::caba::VciMemCache<vci_param> 
+	memc("memc",maptabp,maptabc,maptabx,IntTab(0),IntTab(0),IntTab(2),16,256,16);
+	
+	soclib::caba::VciMultiTty<vci_param> 
+	tty("tty",IntTab(1),maptabp,"tty0","tty1",NULL);
+
+	soclib::caba::VciVgmn<vci_param> 
+	vgmnp("vgmnp",maptabp, 2, 3, 1, 8);
+
+	soclib::caba::VciVgmn<vci_param> 
+	vgmnc("vgmnc",maptabc, 1, 2, 1, 8);
+
+	soclib::caba::VciVgmn<vci_param> 
+	vgmnx("vgmnx",maptabx, 1, 1, 1, 8);
+
+	// Net-List
+ 
+	proc0.p_clk(signal_clk);  
+	proc0.p_resetn(signal_resetn);  
+	proc0.p_irq[0](signal_proc0_it0); 
+	proc0.p_irq[1](signal_proc0_it1); 
+	proc0.p_irq[2](signal_proc0_it2); 
+	proc0.p_irq[3](signal_proc0_it3); 
+	proc0.p_irq[4](signal_proc0_it4); 
+	proc0.p_irq[5](signal_proc0_it5); 
+	proc0.p_vci_ini(signal_vci_ini_proc0);
+	proc0.p_vci_tgt(signal_vci_tgt_proc0);
+
+	proc1.p_clk(signal_clk);  
+	proc1.p_resetn(signal_resetn);  
+	proc1.p_irq[0](signal_proc1_it0); 
+	proc1.p_irq[1](signal_proc1_it1); 
+	proc1.p_irq[2](signal_proc1_it2); 
+	proc1.p_irq[3](signal_proc1_it3); 
+	proc1.p_irq[4](signal_proc1_it4); 
+	proc1.p_irq[5](signal_proc1_it5); 
+	proc1.p_vci_ini(signal_vci_ini_proc1);
+	proc1.p_vci_tgt(signal_vci_tgt_proc1);
+
+	rom.p_clk(signal_clk);
+	rom.p_resetn(signal_resetn);
+	rom.p_vci(signal_vci_tgt_rom);
+
+	tty.p_clk(signal_clk);
+	tty.p_resetn(signal_resetn);
+	tty.p_vci(signal_vci_tgt_tty);
+	tty.p_irq[0](signal_tty_irq0); 
+	tty.p_irq[1](signal_tty_irq1); 
+
+	memc.p_clk(signal_clk);
+	memc.p_resetn(signal_resetn);
+	memc.p_vci_tgt(signal_vci_tgt_memc);	
+	memc.p_vci_ini(signal_vci_ini_memc);
+	memc.p_vci_ixr(signal_vci_ixr_memc);
+
+	xram.p_clk(signal_clk);
+        xram.p_resetn(signal_resetn);
+	xram.p_vci(signal_vci_tgt_xram);
+	
+	vgmnp.p_clk(signal_clk);
+	vgmnp.p_resetn(signal_resetn);
+
+	vgmnc.p_clk(signal_clk);
+	vgmnc.p_resetn(signal_resetn);
+
+	vgmnx.p_clk(signal_clk);
+	vgmnx.p_resetn(signal_resetn);
+
+	vgmnp.p_to_initiator[0](signal_vci_ini_proc0);
+	vgmnp.p_to_initiator[1](signal_vci_ini_proc1);
+	vgmnc.p_to_initiator[0](signal_vci_ini_memc);
+	vgmnx.p_to_initiator[0](signal_vci_ixr_memc);
+
+	vgmnp.p_to_target[0](signal_vci_tgt_rom);
+	vgmnp.p_to_target[1](signal_vci_tgt_tty);
+	vgmnp.p_to_target[2](signal_vci_tgt_memc);
+
+	vgmnc.p_to_target[0](signal_vci_tgt_proc0);
+	vgmnc.p_to_target[1](signal_vci_tgt_proc1);
+	vgmnx.p_to_target[0](signal_vci_tgt_xram);
+
+	int ncycles;
+
+#ifndef SOCVIEW
+	if (argc == 2) {
+		ncycles = std::atoi(argv[1]);
+	} else {
+		std::cerr
+			<< std::endl
+			<< "The number of simulation cycles must "
+			   "be defined in the command line"
+			<< std::endl;
+		exit(1);
+	}
+
+	sc_start(sc_core::sc_time(0, SC_NS));
+	signal_resetn = false;
+
+	sc_start(sc_core::sc_time(1, SC_NS));
+	signal_resetn = true;
+
+	for (int i = 0; i < ncycles ; i+=1000) {
+		sc_start(sc_core::sc_time(1000, SC_NS));
+		//proc.print_stats();
+		//memc.print_stats();
+	}
+	return EXIT_SUCCESS;
+#else
+	ncycles = 1;
+	sc_start(sc_core::sc_time(0, SC_NS));
+	signal_resetn = false;
+	sc_start(sc_core::sc_time(1, SC_NS));
+	signal_resetn = true;
+
+	debug();
+	return EXIT_SUCCESS;
+#endif
+}
+
+int sc_main (int argc, char *argv[])
+{
+	try {
+		return _main(argc, argv);
+	} catch (std::exception &e) {
+		std::cout << e.what() << std::endl;
+	} catch (...) {
+		std::cout << "Unknown exception occured" << std::endl;
+		throw;
+	}
+	return 1;
+}
+
Index: branches/v4/platforms/caba-xxx-ccxcachemulti-mipsel/Makefile
===================================================================
--- branches/v4/platforms/caba-xxx-ccxcachemulti-mipsel/Makefile	(revision 371)
+++ branches/v4/platforms/caba-xxx-ccxcachemulti-mipsel/Makefile	(revision 371)
@@ -0,0 +1,5 @@
+ARCH=mips32el
+SIMULATION_ARGS=100000
+SOCLIB?=$(shell soclib-cc --getpath)
+export SOCLIB
+include $(SOCLIB)/soclib/platform/topcells/all.mk
Index: branches/v4/platforms/caba-xxx-ccxcachemulti-mipsel/platform_desc
===================================================================
--- branches/v4/platforms/caba-xxx-ccxcachemulti-mipsel/platform_desc	(revision 371)
+++ branches/v4/platforms/caba-xxx-ccxcachemulti-mipsel/platform_desc	(revision 371)
@@ -0,0 +1,27 @@
+
+# -*- python -*-
+
+
+todo = Platform('caba', 'top.cpp',
+				uses = [
+	Uses('caba:vci_cc_xcache_wrapper_multi', iss_t = 'common:iss2_simhelper', simhelper_iss_t = 'common:mips32el'),
+	Uses('caba:vci_simple_ram'),
+        Uses('caba:vci_logger'),
+	Uses('caba:vci_multi_tty'),
+ 	Uses('caba:vci_simple_ring_network'),
+	Uses('caba:vci_vgsb'),
+ 	Uses('caba:vci_vgmn'),
+	Uses('caba:vci_mem_cache_v1'),
+	Uses('common:elf_file_loader'),
+	],
+	cell_size = 4,
+	plen_size = 8,
+	addr_size = 64,
+	rerror_size = 1,
+	clen_size = 1,
+	rflag_size = 1,
+	srcid_size = 14,
+	pktid_size = 4,
+	trdid_size = 4,
+	wrplen_size = 1
+)
Index: branches/v4/platforms/caba-xxx-ccxcachemulti-mipsel/segmentation.h
===================================================================
--- branches/v4/platforms/caba-xxx-ccxcachemulti-mipsel/segmentation.h	(revision 371)
+++ branches/v4/platforms/caba-xxx-ccxcachemulti-mipsel/segmentation.h	(revision 371)
@@ -0,0 +1,64 @@
+
+/////////////////////////////////////////////////////////////////
+//	ADDRESS SPACE SEGMENTATION
+//
+//	This file must be included in the system.cpp file, 
+//	for harware configuration : It is used to build
+//	the SOCLIB_SEGMENT_TABLE.
+//
+//	This file can also be used by the ldscript generator,
+//	for embedded software generation.
+//	
+//	It gives the system integrator the garanty
+//	that hardware and software have the same
+//	description of the address space segmentation.
+/////////////////////////////////////////////////////////////////
+
+/////////////////////////////////////////////////////////////////
+//	reset, and exception segments
+//      base address required by MIPS processor
+/////////////////////////////////////////////////////////////////
+#define MMU
+
+#define	RESET_BASE	0x00BFC00000
+#define	RESET_SIZE	0x00010000
+
+#define	EXCEP_BASE	0x0080000080
+#define	EXCEP_SIZE	0x00010000
+
+#define	TEXT_BASE	0x0000400000
+#define	TEXT_SIZE	0x00050000
+/////////////////////////////////////////////////////////////////
+//	global data segment (initialised)
+/////////////////////////////////////////////////////////////////
+
+#define MC_M_BASE	0x0010000000
+#define MC_M_SIZE	0x00100000
+
+//////////////////////////////////////////////////////////
+//	System devices
+///////////////////////////////////////////////////////////
+
+#define	TTY_BASE	0x00C0200000
+#define	TTY_SIZE	0x00000100
+
+#define	TIMER_BASE	0x00D0200000
+#define	TIMER_SIZE	0x00000100
+
+#define	LOCKS_BASE	0x00E0200000
+#define	LOCKS_SIZE	0x00000100
+
+#define C_PROC0_BASE	0x0001200000
+#define C_PROC0_SIZE	0x00000010
+
+#define C_PROC1_BASE	0x0002200000
+#define C_PROC1_SIZE	0x00000010
+
+#define C_PROC2_BASE	0x0003200000
+#define C_PROC2_SIZE	0x00000010
+
+#define C_PROC3_BASE	0x0004200000
+#define C_PROC3_SIZE	0x00000010
+
+
+#define CLEANUP_OFFSET  0x20200000
Index: branches/v4/platforms/caba-xxx-ccxcachemulti-mipsel/soft/Makefile
===================================================================
--- branches/v4/platforms/caba-xxx-ccxcachemulti-mipsel/soft/Makefile	(revision 371)
+++ branches/v4/platforms/caba-xxx-ccxcachemulti-mipsel/soft/Makefile	(revision 371)
@@ -0,0 +1,4 @@
+ADD_OBJS=stdlib.o stdio.o exception.o system.o
+SOCLIB?=$(shell soclib-cc --getpath)
+export SOCLIB
+include $(SOCLIB)/soclib/platform/topcells/soft.mk
Index: branches/v4/platforms/caba-xxx-ccxcachemulti-mipsel/soft/main.c
===================================================================
--- branches/v4/platforms/caba-xxx-ccxcachemulti-mipsel/soft/main.c	(revision 371)
+++ branches/v4/platforms/caba-xxx-ccxcachemulti-mipsel/soft/main.c	(revision 371)
@@ -0,0 +1,122 @@
+#include "system.h"
+#include "stdio.h"
+#include "stdlib.h"
+//#include "matrice.h"
+
+#include "../segmentation.h"
+
+#define NPROCS 1
+#define SIZE 50 
+#define SORT_TYPE 0 // shellSort
+
+volatile int nprocs=NPROCS;
+
+
+unsigned int gQSortNum0[200] = {
+  251,  24, 113, 170, 215,  60,  83,  30, 115,  48, 169, 210,  49,  92, 101,  58,  21, 184, 225,   6,
+  199, 244, 227, 146,  99,  96,  25, 222,  65, 140, 213,  22, 219, 136, 175, 182,  73,  36, 141, 190, 
+   83, 112, 137, 114, 175, 188, 187, 102,  53, 168, 193, 154, 167, 172,   3, 242,  67,  64, 144, 137,
+  142, 175, 188,  69, 102,  53, 168, 193, 102,  89, 172, 253, 242,  67, 192,   7,  62, 159,  20, 181,
+  182, 187, 216, 207,  22, 105, 132, 109, 162, 205,  16, 151,  18, 113, 228,  37,   6,  85,   8, 161,
+   58, 135,  76,  35, 174,  35, 224,  39, 158, 127, 180, 149,  86, 155, 200, 239, 118, 119,  28,  77,
+  254,  19, 176, 183,  78, 145, 132,   5,  90, 117, 152, 127, 218, 153,  20,  67, 178,   3, 128, 185,
+  254,  95, 172, 139, 246, 123, 104,  15,  42, 169,  68, 211,  98, 243,  80,  41, 174,  79,  36,  27,
+  186, 149,  86, 155, 200, 239, 118, 119,  28,  77, 254,  19, 176, 183,  78, 145, 132,   5,  90, 117,
+  152, 127, 218, 153,  20,  67, 178,   3, 128, 185, 254,  95, 172, 139, 246, 123, 104,  15,  42, 169 };
+
+
+unsigned int SortArr0[NPROCS*(SIZE+50)];
+
+void shellSortPhase(unsigned int a[],unsigned int length, int gap);
+void shellSort(unsigned int *base, unsigned int n);     // type 0
+
+int main()
+{
+  register int p; 
+
+  int beg_cycle, end_cycle;
+
+  beg_cycle = cpu_cycles();
+
+  p=procnum();
+
+  puts("Hello from processor ");
+  putchar(p+'0');
+  putchar('\n');
+
+  int i;
+  int j;
+  unsigned int* SortArray;
+
+  if(p+1 <= nprocs)
+  {
+        i=1;
+  	puts("Memory copy \n");
+        SortArray = SortArr0 + p*(SIZE+50);
+	memcpy(SortArray, gQSortNum0 + p*SIZE,SIZE*4);
+
+ 	puts("Sort... \n");
+        shellSort((unsigned int *) (SortArray), (unsigned int) SIZE);
+
+  	for (j = 1; j < SIZE; j++)
+    	{
+	  if (SortArray[j] < SortArray[j-1])
+		{
+	  		puts("ucbqsort: failed\n");
+			while(1);
+		}
+
+    	}
+
+  	puts("ucbqsort: success\n");
+        end_cycle = cpu_cycles();
+//      printf( "nombre cycles cpu : %i\n", end_cycle-beg_cycle);
+        printf( "begin time        : %i\n", beg_cycle);
+        printf( "end time          : %i\n", end_cycle);
+  }
+
+
+  while(1);
+}
+
+//------------------------------------------------------
+/*
+ * Exécute un tri par insertion avec la séparation donnée
+ * If gap == 1, on fait un tri ordinaire.
+ * If gap >= length, on ne fait rien.
+ */
+void shellSortPhase(unsigned int a[],unsigned int length, int gap) {
+    int i;
+ 
+    puti(gap);
+    for (i = gap; i < length; ++i) {
+        unsigned int value = a[i];
+        int j;
+        for (j = i - gap; j >= 0 && a[j] > value; j -= gap) {
+	    putchar('+');
+            a[j + gap] = a[j];
+	    putchar('-');
+        }
+        a[j + gap] = value;
+    }
+}
+ 
+void shellSort(unsigned int *base, unsigned int n) {
+    /*
+     * gaps[] doit approximer une Série géométrique.
+     * La sequence suivante est la meilleure connue en terme
+     * de nombre moyen de comparaisons. voir:
+     * http://www.research.att.com/~njas/sequences/A102549
+     */
+    static const int gaps[] = {
+        1, 4, 10, 23, 57, 132, 301, 701
+    };
+    int sizeIndex;
+ 
+    puts("Shell Sort\n");
+    for (sizeIndex = sizeof(gaps)/sizeof(gaps[0]) - 1;
+               sizeIndex >= 0;
+               --sizeIndex)
+        shellSortPhase(base, n, gaps[sizeIndex]);
+}
+
Index: branches/v4/platforms/caba-xxx-ccxcachemulti-mipsel/soft/matrice.h
===================================================================
--- branches/v4/platforms/caba-xxx-ccxcachemulti-mipsel/soft/matrice.h	(revision 371)
+++ branches/v4/platforms/caba-xxx-ccxcachemulti-mipsel/soft/matrice.h	(revision 371)
@@ -0,0 +1,713 @@
+unsigned int gQSortNum0[16000] = {
+  251, 24, 113, 170, 215, 60, 83, 30, 115, 48, 169, 210, 49, 92, 101, 58, 21, 184, 225, 6,
+  199, 244, 227, 146, 99, 96, 25, 222, 65, 140, 213, 22, 219, 136, 175, 182, 73, 36, 141, 190, 
+  83, 112, 137, 114, 175, 188, 187, 102, 53, 168, 193, 154, 167, 172, 3, 242, 67, 64,144, 137,
+  142, 175, 188, 69, 102, 53, 168, 193, 102, 89, 172, 253, 242, 67,192, 7, 62, 159, 20, 181,
+  182, 187, 216, 207, 22, 105, 132, 109, 162, 205, 16, 151, 18, 113, 228, 37, 6, 85, 8, 161,
+  58, 135, 76, 35, 174, 35, 224, 39, 158, 127, 180, 149, 86, 155, 200, 239, 118, 119, 28, 77,
+  254, 19, 176, 183, 78, 145, 132, 5, 90, 117, 152, 127, 218, 153, 20, 67, 178, 3, 128, 185,
+  254, 95, 172, 139, 246, 123, 104, 15, 42, 169, 68, 211, 98, 243, 80, 41, 174, 79, 36, 27,
+  186, 149, 86, 155, 200, 239, 118, 119, 28, 77, 254, 19, 176, 183,78, 145, 132, 5, 90, 117,
+  152, 127, 218, 153, 20, 67, 178, 3, 128, 185, 254, 95, 172, 139, 246, 123, 104, 15, 42,169,
+  68, 211, 98, 243, 80, 41, 174, 79, 36, 27, 186, 107, 56, 97, 134, 71, 116, 157, 238, 227,
+  32, 153, 162, 193, 244, 171, 150, 165, 248, 209, 54, 55, 164, 13, 194, 45, 16, 247, 242, 47,
+  60, 59, 26, 75, 40, 65, 230, 217, 44, 131, 142, 195, 192, 121, 190, 225, 108, 203, 202, 197,
+  168, 177, 150, 233, 252, 19, 34, 77, 144, 23, 110, 15, 100, 91, 122, 213, 120, 223, 70, 7, 
+  52, 93, 46, 93, 160, 167, 226, 255, 204, 21, 42, 229, 72, 111, 246, 9, 100, 205, 126, 147,
+  215, 82, 79, 36, 229, 70, 149, 56, 159, 134, 185, 140, 99, 18, 29, 224, 153, 94, 63, 244, 85, 150, 91, 248, 209,
+  202, 55, 92, 243, 194, 211, 240, 247, 242, 209, 196, 197, 26, 75, 40, 191, 26, 39, 44, 131, 142, 195, 64, 121, 190,
+  231, 34, 65, 116, 43, 22, 219, 136, 175, 74, 73, 220, 141, 190, 83, 112, 137, 142, 81, 68, 69, 154, 203, 88, 63,
+  154, 89, 172, 3, 242, 67, 192, 249, 62, 159, 20, 181, 74, 69, 216, 49, 22, 105, 132, 109, 162, 205, 16, 151, 18,
+  37, 136, 175, 74, 183, 36, 115, 66, 173, 144, 137, 142, 175, 188, 69, 102, 53, 168, 193, 102, 89, 172, 253, 242, 67,
+  192, 7, 62, 159, 20, 181, 182, 187, 216, 207, 22, 105, 132, 109, 162, 205, 16, 151, 18, 113, 228, 37, 6, 85, 8,
+  161, 58, 135, 76, 35, 174, 35, 224, 39, 158, 127, 180, 149, 86, 155, 200, 239, 118, 119, 28, 77, 254, 19, 176, 183,
+  78, 145, 132, 5, 90, 117, 152, 127, 218, 153, 20, 67, 178, 3, 128, 185, 254, 95, 172, 139, 246, 123, 104, 15, 42,
+  251, 24, 113, 170, 215, 60, 83, 30, 115, 48, 169, 210, 49, 92, 101, 58, 21, 184, 225, 6,
+  199, 244, 227, 146, 99, 96, 25, 222, 65, 140, 213, 22, 219, 136, 175, 182, 73, 36, 141, 190, 
+  83, 112, 137, 114, 175, 188, 187, 102, 53, 168, 193, 154, 167, 172, 3, 242, 67, 64,144, 137,
+  142, 175, 188, 69, 102, 53, 168, 193, 102, 89, 172, 253, 242, 67,192, 7, 62, 159, 20, 181,
+  182, 187, 216, 207, 22, 105, 132, 109, 162, 205, 16, 151, 18, 113, 228, 37, 6, 85, 8, 161,
+  58, 135, 76, 35, 174, 35, 224, 39, 158, 127, 180, 149, 86, 155, 200, 239, 118, 119, 28, 77,
+  254, 19, 176, 183, 78, 145, 132, 5, 90, 117, 152, 127, 218, 153, 20, 67, 178, 3, 128, 185,
+  254, 95, 172, 139, 246, 123, 104, 15, 42, 169, 68, 211, 98, 243, 80, 41, 174, 79, 36, 27,
+  186, 149, 86, 155, 200, 239, 118, 119, 28, 77, 254, 19, 176, 183,78, 145, 132, 5, 90, 117,
+  152, 127, 218, 153, 20, 67, 178, 3, 128, 185, 254, 95, 172, 139, 246, 123, 104, 15, 42,169,
+  68, 211, 98, 243, 80, 41, 174, 79, 36, 27, 186, 107, 56, 97, 134, 71, 116, 157, 238, 227,
+  32, 153, 162, 193, 244, 171, 150, 165, 248, 209, 54, 55, 164, 13, 194, 45, 16, 247, 242, 47,
+  60, 59, 26, 75, 40, 65, 230, 217, 44, 131, 142, 195, 192, 121, 190, 225, 108, 203, 202, 197,
+  168, 177, 150, 233, 252, 19, 34, 77, 144, 23, 110, 15, 100, 91, 122, 213, 120, 223, 70, 7, 
+  52, 93, 46, 93, 160, 167, 226, 255, 204, 21, 42, 229, 72, 111, 246, 9, 100, 205, 126, 147,
+  215, 82, 79, 36, 229, 70, 149, 56, 159, 134, 185, 140, 99, 18, 29, 224, 153, 94, 63, 244, 85, 150, 91, 248, 209,
+  202, 55, 92, 243, 194, 211, 240, 247, 242, 209, 196, 197, 26, 75, 40, 191, 26, 39, 44, 131, 142, 195, 64, 121, 190,
+  231, 34, 65, 116, 43, 22, 219, 136, 175, 74, 73, 220, 141, 190, 83, 112, 137, 142, 81, 68, 69, 154, 203, 88, 63,
+  154, 89, 172, 3, 242, 67, 192, 249, 62, 159, 20, 181, 74, 69, 216, 49, 22, 105, 132, 109, 162, 205, 16, 151, 18,
+  37, 136, 175, 74, 183, 36, 115, 66, 173, 144, 137, 142, 175, 188, 69, 102, 53, 168, 193, 102, 89, 172, 253, 242, 67,
+  192, 7, 62, 159, 20, 181, 182, 187, 216, 207, 22, 105, 132, 109, 162, 205, 16, 151, 18, 113, 228, 37, 6, 85, 8,
+  161, 58, 135, 76, 35, 174, 35, 224, 39, 158, 127, 180, 149, 86, 155, 200, 239, 118, 119, 28, 77, 254, 19, 176, 183,
+  78, 145, 132, 5, 90, 117, 152, 127, 218, 153, 20, 67, 178, 3, 128, 185, 254, 95, 172, 139, 246, 123, 104, 15, 42,
+
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+  154, 89, 172, 3, 242, 67, 192, 249, 62, 159, 20, 181, 74, 69, 216, 49, 22, 105, 132, 109, 162, 205, 16, 151, 18,
+  113, 228, 219, 
+250, 171, 8, 95, 58, 135, 180, 35, 82, 221, 224, 39, 98, 129, 180, 107, 86, 101, 200, 239, 118, 119,
+  228, 179, 2, 237, 80, 183, 78, 111, 124, 5, 90, 117, 104, 127, 38, 153, 20, 67, 178, 253, 128, 185, 254, 95, 172,
+  117, 10, 123, 152, 241, 42, 87, 188, 211, 98, 243, 80, 215, 82, 79, 36, 27, 186, 107, 200, 159, 122, 71, 140, 157,
+  238, 29, 224, 153, 94, 63, 244, 85, 106, 91, 248, 47, 54, 201, 164, 243, 62, 211, 240, 247, 242, 47, 196, 197, 230,
+  181, 216, 65, 26, 217, 44, 125, 114, 195, 192, 135, 190, 31, 148, 203, 202, 59, 88, 79, 150, 233, 252, 19, 34, 77,
+  144, 233, 146, 15, 100, 165, 122, 213, 136, 223, 70, 249, 204, 93, 46, 93, 96, 167, 30, 1, 204, 21, 42, 27, 72
+};
+
+
Index: branches/v4/platforms/caba-xxx-ccxcachemulti-mipsel/top.cpp
===================================================================
--- branches/v4/platforms/caba-xxx-ccxcachemulti-mipsel/top.cpp	(revision 371)
+++ branches/v4/platforms/caba-xxx-ccxcachemulti-mipsel/top.cpp	(revision 371)
@@ -0,0 +1,337 @@
+
+#include <systemc>
+#include <sys/time.h>
+#include <iostream>
+#include <cstdlib>
+#include <cstdarg>
+
+#include "mapping_table.h"
+#include "mips32.h"
+#include "iss2_simhelper.h"
+#include "vci_simple_ram.h"
+#include "vci_multi_tty.h"
+#include "vci_vgmn.h"
+#include "vci_mem_cache_v1.h"
+#include "vci_cc_xcache_wrapper_multi.h"
+
+#ifdef USE_GDB_SERVER
+#include "iss/gdbserver.h"
+#endif
+
+#include "segmentation.h"
+
+int _main(int argc, char *argv[])
+{
+	using namespace sc_core;
+	// Avoid repeating these everywhere
+	using soclib::common::IntTab;
+	using soclib::common::Segment;
+
+	// Define VCI parameters
+	typedef soclib::caba::VciParams<4,8,64,1,1,1,14,4,4,1> vci_param;
+	typedef soclib::common::Iss2Simhelper<soclib::common::Mips32ElIss> proc_iss;
+	// Mapping table
+
+	soclib::common::MappingTable maptabp(40, IntTab(16), IntTab(8), 0x00300000);
+
+	maptabp.add(Segment("reset", RESET_BASE, RESET_SIZE, IntTab(0), true));
+	maptabp.add(Segment("excep", EXCEP_BASE, EXCEP_SIZE, IntTab(0), true));
+	maptabp.add(Segment("text" , TEXT_BASE , TEXT_SIZE , IntTab(0), true));
+	maptabp.add(Segment("tty"  , TTY_BASE  , TTY_SIZE  , IntTab(1), false));
+	maptabp.add(Segment("mc_m" , MC_M_BASE , MC_M_SIZE , IntTab(0), true ));
+ 
+	std::cout << maptabp << std::endl;
+
+        soclib::common::MappingTable maptabc(40, IntTab(16), IntTab(8), 0x00300000);
+	maptabc.add(Segment("c_proc0" , C_PROC0_BASE , C_PROC0_SIZE , IntTab(0), false, true, IntTab(0)));
+	maptabc.add(Segment("mc_m" , MC_M_BASE , MC_M_SIZE , IntTab(1), false, false));
+	maptabc.add(Segment("reset", RESET_BASE, RESET_SIZE, IntTab(1), false, false));
+	maptabc.add(Segment("excep", EXCEP_BASE, EXCEP_SIZE, IntTab(1), false, false));
+	maptabc.add(Segment("text" , TEXT_BASE , TEXT_SIZE , IntTab(1), false, false));
+
+	std::cout << maptabc << std::endl;
+	
+	soclib::common::MappingTable maptabx(40, IntTab(16), IntTab(8), 0x00300000);
+	maptabx.add(Segment("xram" , MC_M_BASE , MC_M_SIZE , IntTab(0), false));
+	maptabx.add(Segment("reset", RESET_BASE, RESET_SIZE, IntTab(0), false));
+	maptabx.add(Segment("excep", EXCEP_BASE, EXCEP_SIZE, IntTab(0), false));
+	maptabx.add(Segment("text" , TEXT_BASE , TEXT_SIZE , IntTab(0), false));
+	
+	std::cout << maptabx << std::endl;
+
+	// Signals
+	sc_clock	signal_clk("clk");
+	sc_signal<bool> signal_resetn("resetn");
+   
+	sc_signal<bool> signal_proc0_it0("proc0_it0"); 
+	sc_signal<bool> signal_proc0_it1("proc0_it1"); 
+	sc_signal<bool> signal_proc0_it2("proc0_it2"); 
+	sc_signal<bool> signal_proc0_it3("proc0_it3"); 
+	sc_signal<bool> signal_proc0_it4("proc0_it4"); 
+	sc_signal<bool> signal_proc0_it5("proc0_it5");
+/*
+	sc_signal<bool> signal_proc1_it0("proc1_it0"); 
+	sc_signal<bool> signal_proc1_it1("proc1_it1"); 
+	sc_signal<bool> signal_proc1_it2("proc1_it2"); 
+	sc_signal<bool> signal_proc1_it3("proc1_it3"); 
+	sc_signal<bool> signal_proc1_it4("proc1_it4"); 
+	sc_signal<bool> signal_proc1_it5("proc1_it5");
+
+	sc_signal<bool> signal_proc2_it0("proc2_it0"); 
+	sc_signal<bool> signal_proc2_it1("proc2_it1"); 
+	sc_signal<bool> signal_proc2_it2("proc2_it2"); 
+	sc_signal<bool> signal_proc2_it3("proc2_it3"); 
+	sc_signal<bool> signal_proc2_it4("proc2_it4"); 
+	sc_signal<bool> signal_proc2_it5("proc2_it5");
+
+	sc_signal<bool> signal_proc3_it0("proc3_it0"); 
+	sc_signal<bool> signal_proc3_it1("proc3_it1"); 
+	sc_signal<bool> signal_proc3_it2("proc3_it2"); 
+	sc_signal<bool> signal_proc3_it3("proc3_it3"); 
+	sc_signal<bool> signal_proc3_it4("proc3_it4"); 
+	sc_signal<bool> signal_proc3_it5("proc3_it5");
+*/
+	soclib::caba::VciSignals<vci_param> signal_vci_ini_d_proc0("vci_ini_d_proc0");
+	soclib::caba::VciSignals<vci_param> signal_vci_ini_c_proc0("vci_ini_c_proc0");
+	soclib::caba::VciSignals<vci_param> signal_vci_tgt_c_proc0("vci_tgt_proc0");
+/*
+	soclib::caba::VciSignals<vci_param> signal_vci_ini_d_proc1("vci_ini_d_proc1");
+	soclib::caba::VciSignals<vci_param> signal_vci_ini_c_proc1("vci_ini_c_proc1");
+	soclib::caba::VciSignals<vci_param> signal_vci_tgt_c_proc1("vci_tgt_proc1");
+
+	soclib::caba::VciSignals<vci_param> signal_vci_ini_d_proc2("vci_ini_d_proc2");
+	soclib::caba::VciSignals<vci_param> signal_vci_ini_c_proc2("vci_ini_c_proc2");
+	soclib::caba::VciSignals<vci_param> signal_vci_tgt_c_proc2("vci_tgt_proc2");
+
+	soclib::caba::VciSignals<vci_param> signal_vci_ini_d_proc3("vci_ini_d_proc3");
+	soclib::caba::VciSignals<vci_param> signal_vci_ini_c_proc3("vci_ini_c_proc3");
+	soclib::caba::VciSignals<vci_param> signal_vci_tgt_c_proc3("vci_tgt_proc3");
+*/
+	soclib::caba::VciSignals<vci_param> signal_vci_tgt_tty("vci_tgt_tty");
+
+	soclib::caba::VciSignals<vci_param> signal_vci_tgt_xram("vci_tgt_xram");
+
+	soclib::caba::VciSignals<vci_param> signal_vci_ixr_memc("vci_ixr_memc");
+	soclib::caba::VciSignals<vci_param> signal_vci_ini_memc("vci_ini_memc");
+	soclib::caba::VciSignals<vci_param> signal_vci_tgt_d_memc("vci_tgt_memc");
+	soclib::caba::VciSignals<vci_param> signal_vci_tgt_c_memc("vci_tgt_cleanup_memc");
+
+	sc_signal<bool> signal_tty_irq0("signal_tty_irq0");
+/* 
+	sc_signal<bool> signal_tty_irq1("signal_tty_irq1"); 
+	sc_signal<bool> signal_tty_irq2("signal_tty_irq2"); 
+	sc_signal<bool> signal_tty_irq3("signal_tty_irq3"); 
+*/
+        sc_signal<bool> signal_stuck0("signal_stuck0");
+
+	soclib::common::Loader loader("soft/bin.soft");
+
+        // Components
+	soclib::caba::VciCcXCacheWrapperMulti<vci_param, proc_iss > 
+	proc0("proc0", 0, maptabp, maptabc, IntTab(0),IntTab(0),IntTab(0),1,8,16,1,8,16,4,8,16);
+/*
+	soclib::caba::VciCcXCacheWrapperMulti<vci_param, proc_iss > 
+	proc1("proc1", 1, maptabp, maptabc, IntTab(1),IntTab(1),IntTab(1),1,8,16,1,8,16,4,8,16);
+
+	soclib::caba::VciCcXCacheWrapperMulti<vci_param, proc_iss > 
+	proc2("proc2", 2, maptabp, maptabc, IntTab(2),IntTab(2),IntTab(2),1,8,16,1,8,16,4,8,16);
+
+	soclib::caba::VciCcXCacheWrapperMulti<vci_param, proc_iss > 
+	proc3("proc3", 3, maptabp, maptabc, IntTab(3),IntTab(3),IntTab(3),1,8,16,1,8,16,4,8,16);
+*/
+
+	soclib::caba::VciSimpleRam<vci_param> 
+	xram("xram", IntTab(0), maptabx, loader);
+
+	soclib::caba::VciMemCacheV1<vci_param> 
+	memc("memc",maptabp,maptabc,maptabx,IntTab(0),IntTab(1),IntTab(0), IntTab(1),4,16,16);
+	
+	soclib::caba::VciMultiTty<vci_param> 
+	tty("tty",IntTab(1),maptabp,"tty0", NULL);
+
+  	soclib::caba::VciVgmn<vci_param> 
+	ringd("ringd",maptabp, 1, 2, 2, 2);
+
+  	soclib::caba::VciVgmn<vci_param> 
+	ringc("ringc",maptabc, 2, 2, 2, 2);
+
+  	soclib::caba::VciVgmn<vci_param> 
+	ringx("ringx",maptabx, 1, 1, 2, 2);
+
+	// Net-List
+ 
+	proc0.p_clk(signal_clk);  
+	proc0.p_resetn(signal_resetn);  
+	proc0.p_irq[0](signal_proc0_it0); 
+	proc0.p_irq[1](signal_proc0_it1); 
+	proc0.p_irq[2](signal_proc0_it2); 
+	proc0.p_irq[3](signal_proc0_it3); 
+	proc0.p_irq[4](signal_proc0_it4); 
+	proc0.p_irq[5](signal_proc0_it5); 
+	proc0.p_vci_ini_d(signal_vci_ini_d_proc0);
+	proc0.p_vci_ini_c(signal_vci_ini_c_proc0);
+	proc0.p_vci_tgt_c(signal_vci_tgt_c_proc0);
+/*
+	proc1.p_clk(signal_clk);  
+	proc1.p_resetn(signal_resetn);  
+	proc1.p_irq[0](signal_proc1_it0); 
+	proc1.p_irq[1](signal_proc1_it1); 
+	proc1.p_irq[2](signal_proc1_it2); 
+	proc1.p_irq[3](signal_proc1_it3); 
+	proc1.p_irq[4](signal_proc1_it4); 
+	proc1.p_irq[5](signal_proc1_it5); 
+	proc1.p_vci_ini_d(signal_vci_ini_d_proc1);
+	proc1.p_vci_ini_c(signal_vci_ini_c_proc1);
+	proc1.p_vci_tgt_c(signal_vci_tgt_c_proc1);
+
+	proc2.p_clk(signal_clk);  
+	proc2.p_resetn(signal_resetn);  
+	proc2.p_irq[0](signal_proc2_it0); 
+	proc2.p_irq[1](signal_proc2_it1); 
+	proc2.p_irq[2](signal_proc2_it2); 
+	proc2.p_irq[3](signal_proc2_it3); 
+	proc2.p_irq[4](signal_proc2_it4); 
+	proc2.p_irq[5](signal_proc2_it5); 
+	proc2.p_vci_ini_d(signal_vci_ini_d_proc2);
+	proc2.p_vci_ini_c(signal_vci_ini_c_proc2);
+	proc2.p_vci_tgt_c(signal_vci_tgt_c_proc2);
+
+	proc3.p_clk(signal_clk);  
+	proc3.p_resetn(signal_resetn);  
+	proc3.p_irq[0](signal_proc3_it0); 
+	proc3.p_irq[1](signal_proc3_it1); 
+	proc3.p_irq[2](signal_proc3_it2); 
+	proc3.p_irq[3](signal_proc3_it3); 
+	proc3.p_irq[4](signal_proc3_it4); 
+	proc3.p_irq[5](signal_proc3_it5); 
+	proc3.p_vci_ini_d(signal_vci_ini_d_proc3);
+	proc3.p_vci_ini_c(signal_vci_ini_c_proc3);
+	proc3.p_vci_tgt_c(signal_vci_tgt_c_proc3);
+*/
+
+	tty.p_clk(signal_clk);
+	tty.p_resetn(signal_resetn);
+	tty.p_vci(signal_vci_tgt_tty);
+	tty.p_irq[0](signal_tty_irq0);
+/* 
+	tty.p_irq[1](signal_tty_irq1); 
+	tty.p_irq[2](signal_tty_irq2); 
+	tty.p_irq[3](signal_tty_irq3); 
+*/
+	memc.p_clk(signal_clk);
+	memc.p_resetn(signal_resetn);
+	memc.p_vci_tgt(signal_vci_tgt_d_memc);
+	memc.p_vci_tgt_cleanup(signal_vci_tgt_c_memc);
+	memc.p_vci_ini(signal_vci_ini_memc);
+	memc.p_vci_ixr(signal_vci_ixr_memc);
+
+	xram.p_clk(signal_clk);
+        xram.p_resetn(signal_resetn);
+	xram.p_vci(signal_vci_tgt_xram);
+	
+	ringd.p_clk(signal_clk);
+	ringd.p_resetn(signal_resetn);
+	ringd.p_to_initiator[0](signal_vci_ini_d_proc0);
+/*
+	ringd.p_to_initiator[1](signal_vci_ini_d_proc1);
+	ringd.p_to_initiator[2](signal_vci_ini_d_proc2);
+	ringd.p_to_initiator[3](signal_vci_ini_d_proc3);
+*/
+	ringd.p_to_target[1](signal_vci_tgt_tty);
+	ringd.p_to_target[0](signal_vci_tgt_d_memc);
+
+	ringc.p_clk(signal_clk);
+	ringc.p_resetn(signal_resetn);
+	ringc.p_to_initiator[0](signal_vci_ini_c_proc0);
+/*
+	ringc.p_to_initiator[1](signal_vci_ini_c_proc1);
+	ringc.p_to_initiator[2](signal_vci_ini_c_proc2);
+	ringc.p_to_initiator[3](signal_vci_ini_c_proc3);
+*/
+	ringc.p_to_initiator[1](signal_vci_ini_memc);
+	ringc.p_to_target[0](signal_vci_tgt_c_proc0);
+/*
+	ringc.p_to_target[1](signal_vci_tgt_c_proc1);
+	ringc.p_to_target[2](signal_vci_tgt_c_proc2);
+	ringc.p_to_target[3](signal_vci_tgt_c_proc3);
+*/
+	ringc.p_to_target[1](signal_vci_tgt_c_memc);
+
+	ringx.p_clk(signal_clk);
+	ringx.p_resetn(signal_resetn);
+	ringx.p_to_initiator[0](signal_vci_ixr_memc);
+	ringx.p_to_target[0](signal_vci_tgt_xram);
+
+	int ncycles = 1000000000;
+
+	if (argc == 2) {
+		ncycles = std::atoi(argv[1]);
+	}
+
+	sc_start(sc_core::sc_time(0, SC_NS));
+	signal_resetn = false;
+        signal_stuck0 = false;
+
+	sc_start(sc_core::sc_time(1, SC_NS));
+	signal_resetn = true;
+
+	for (int i = 0; i < ncycles ; i++) 
+        {
+                if ( i%10000 == 0 ) 
+                {
+			proc0.printStatistics();
+			proc1.printStatistics();
+			proc2.printStatistics();
+			proc3.printStatistics();
+			memc.print_stats();
+		}
+/*
+
+		std::cout << "***************************************** cycle = " << std::dec << i 
+                          << " *************************************************" << std::endl;  
+		proc0.printTrace(0);
+		proc1.printTrace(0);
+		proc2.printTrace(0);
+		proc3.printTrace(0);
+            std::cout << " proc0.cmdval  = " << signal_vci_ini_c_proc0.cmdval << std::endl;
+            std::cout << " proc0.cmdack  = " << signal_vci_ini_c_proc0.cmdack << std::endl;
+            std::cout << " proc0.address = " << signal_vci_ini_c_proc0.address << std::endl;
+            std::cout << " proc0.wdata   = " << signal_vci_ini_c_proc0.wdata << std::endl;
+            std::cout << " proc0.eop     = " << signal_vci_ini_c_proc0.eop << std::endl;
+            std::cout << " proc0.len     = " << signal_vci_ini_c_proc0.plen << std::endl;
+            std::cout << " proc0.rspval  = " << signal_vci_ini_c_proc0.rspval << std::endl;
+            std::cout << " proc0.rspack  = " << signal_vci_ini_c_proc0.rspack << std::endl;
+            std::cout << " proc0.reop    = " << signal_vci_ini_c_proc0.reop << std::endl;
+            std::cout << " proc0.rdata   = " << signal_vci_ini_c_proc0.rdata << std::endl;
+            std::cout << " proc0.rerror  = " << signal_vci_ini_c_proc0.rerror << std::endl;
+            std::cout << " memc.cmdval   = " << signal_vci_tgt_c_memc.cmdval << std::endl;
+            std::cout << " memc.cmdack   = " << signal_vci_tgt_c_memc.cmdack << std::endl;
+            std::cout << " memc.address  = " << signal_vci_tgt_c_memc.address << std::endl;
+            std::cout << " memc.wdata    = " << signal_vci_tgt_c_memc.wdata << std::endl;
+            std::cout << " memc.eop      = " << signal_vci_tgt_c_memc.eop << std::endl;
+            std::cout << " memc.len      = " << signal_vci_tgt_c_memc.plen << std::endl;
+            std::cout << " memc.rspval   = " << signal_vci_tgt_c_memc.rspval << std::endl;
+            std::cout << " memc.rspack   = " << signal_vci_tgt_c_memc.rspack << std::endl;
+            std::cout << " memc.reop     = " << signal_vci_tgt_c_memc.reop << std::endl;
+            std::cout << " memc.rdata    = " << signal_vci_tgt_c_memc.rdata << std::endl;
+            std::cout << " memc.rerror   = " << signal_vci_tgt_c_memc.rerror << std::endl;
+*/
+
+		sc_start(sc_core::sc_time(1, SC_NS));
+	}
+
+	return EXIT_SUCCESS;
+}
+
+int sc_main (int argc, char *argv[])
+{
+	try {
+		return _main(argc, argv);
+	} catch (std::exception &e) {
+		std::cout << e.what() << std::endl;
+	} catch (...) {
+		std::cout << "Unknown exception occured" << std::endl;
+		throw;
+	}
+	return 1;
+}
Index: branches/v4/platforms/dsx/nc_1cluster_virt/cnc_cluster.py
===================================================================
--- branches/v4/platforms/dsx/nc_1cluster_virt/cnc_cluster.py	(revision 371)
+++ branches/v4/platforms/dsx/nc_1cluster_virt/cnc_cluster.py	(revision 371)
@@ -0,0 +1,109 @@
+
+__doc__ = '''
+This file is a Cluster library. It contains classes implementing the
+netlist of a cluster, for different tsar versions.
+'''
+
+class Cluster:
+    '''
+    A generic netlist of a cluster, which must be subclassed to
+    implement caches&dma instanciation
+    '''
+    
+    def __init__(self, pf, ringp, mtp, proc_count, cluster_no, cluster_base):
+        self.pf = pf
+        self.ringp = ringp
+        self.mtp = mtp
+        self.cluster_no = cluster_no
+
+        self.generate(proc_count, cluster_base)
+
+    def generate(self, proc_count, cluster_base):
+        '''
+        The core netlist, where caches and components are created
+        '''
+        self.cpu = []
+        for i in range(proc_count):
+            c = self.create_cpu(i,
+                                cluster_base
+                                + 0x10200000
+                                + 0x01000000 * (i+1)
+                                )
+            self.cpu.append(c)
+
+        xram = self.create_ram( segments = [(cluster_base, 0x02000000)] )
+        rom  = self.create_rom( segments = [(0xbfc00000, 0x00400000)] )
+        tty  = self.create_tty( addr = 0xd0200000 )
+        dma  = self.create_dma( addr = 0xd1200000 )
+        xicu = self.create_xicu( addr = 0xd2200000, hwi_count = 3, cpu_count = proc_count )
+
+        xicu.hwi[0] // tty.irq[0]
+        xicu.hwi[1] // dma.irq
+
+        for p, cpu in enumerate(self.cpu):
+            for i in range(6):
+                xicu.irq[i+p*6] // cpu.irq[i]
+
+    def create_rom(self, segments):
+        name = 'rom%d'%self.cluster_no
+        rom = self.pf.create('caba:vci_simple_ram', name, latency = 1)
+        self.ringp.to_target.new() // rom.vci
+        for addr, size in segments:
+            rom.addSegment(name, address = addr, size = size, cacheable = True)
+        return rom
+
+    def create_ram(self, segments):
+        name = 'ram%d'%self.cluster_no
+        ram = self.pf.create('caba:vci_simple_ram', name, latency = 1)
+        self.ringp.to_target.new() // ram.vci
+        for addr, size in segments:
+            ram.addSegment(name, address = addr, size = size, cacheable = True)
+        return ram
+
+    def create_tty(self, addr):
+        name = 'tty%d'%self.cluster_no
+        tty = self.pf.create('caba:vci_multi_tty', name, names = ['tty0'])
+        self.ringp.to_target.new() // tty.vci
+        tty.addSegment(name, address = addr, size = 0x10, cacheable = False)
+        return tty
+
+    def create_xicu(self, addr, hwi_count, cpu_count):
+        name = 'xicu%d'%self.cluster_no
+        xicu = self.pf.create('caba:vci_xicu', name,
+                              pti_count = cpu_count,
+                              hwi_count = hwi_count,
+                              wti_count = cpu_count,
+                              irq_count = 6*cpu_count,
+                              )
+        self.ringp.to_target.new() // xicu.vci
+        xicu.addSegment(name, address = addr, size = 0x1000, cacheable = False)
+        return xicu
+
+    def create_cpu(self, cpuid, addr):
+            c = self.pf.create(
+                'caba:vci_vcache_wrapper2',
+                'proc_%d_%d' % (self.cluster_no, cpuid),
+                iss_t = "common:mips32el",
+                proc_id = cpuid,
+                icache_ways = 4,
+                icache_sets = 64,
+                icache_words = 16,
+                itlb_ways = 4,
+                itlb_sets = 16,
+                dcache_ways = 4,
+                dcache_sets = 64,
+                dcache_words = 16,
+                dtlb_ways = 4,
+                dtlb_sets = 16,
+                write_buf_size = 16,
+                )
+            self.ringp.to_initiator.new() // c.vci
+            return c
+
+    def create_dma(self, addr):
+        name = 'dma%d'%self.cluster_no
+        dma = self.pf.create('caba:vci_dma', name, burst_size = 64)
+        self.ringp.to_target.new() // dma.vci_target
+        self.ringp.to_initiator.new() // dma.vci_initiator
+        dma.addSegment(name, address = addr, size = 0x14, cacheable = False)
+        return dma
Index: branches/v4/platforms/dsx/nc_1cluster_virt/nc_1cluster_virt.py
===================================================================
--- branches/v4/platforms/dsx/nc_1cluster_virt/nc_1cluster_virt.py	(revision 371)
+++ branches/v4/platforms/dsx/nc_1cluster_virt/nc_1cluster_virt.py	(revision 371)
@@ -0,0 +1,91 @@
+#!/usr/bin/env python
+
+import dsx
+import soclib
+import soclib.component
+import os
+
+class Platform:
+    def __init__(self, cluster_ctor, proc_count, binaries):
+        self.pf = soclib.Architecture(cell_size = 4,
+                                      plen_size = 8,
+                                      addr_size = 32,
+                                      rerror_size = 1,
+                                      clen_size = 1,
+                                      rflag_size = 1,
+                                      srcid_size = 14,
+                                      pktid_size = 4,
+                                      trdid_size = 4,
+                                      wrplen_size = 1
+                                      )
+        mt = self.pf.create('common:mapping_table', 'mtp',
+                            addr_size = 32,
+                            addr_bits = [8], srcid_bits = [8],
+                            cacheability_mask = 0xff000000)
+        self.mtp = mt
+
+        # create a dictionary containing
+        # loader = x, loader2 = y, ...
+        bins = {}
+        for i, bin in enumerate(binaries):
+            k = 'binary'
+            if i:
+                k += str(i+1)
+            bins[k] = bin
+        self.loader = self.pf.create('common:loader', 'loader', **bins)
+
+        self.ringp = self.pf.create('caba:vci_vgmn', 'ringp', 
+                       mt = self.mtp,
+                       min_latency = 1,
+                       fifo_depth = 8, )
+
+        self.cluster = cluster_ctor(self.pf,
+                                    self.ringp,
+                                    self.mtp,
+                                    proc_count = proc_count,
+                                    cluster_no = 0,
+                                    cluster_base = 0x00000000,
+                                    )
+
+        self.proc_count = proc_count
+
+    def simulator(self):
+        self.pf.generate(soclib.PfDriver(outdir = 'cnc%d'%self.proc_count))
+
+    def device_tree(self):
+        from dsx.contrib.dts_platform.platform_to_dts import PlatformToDts
+        import dsx.contrib.dts_platform.platform_handlers
+        dtsgen = PlatformToDts(self.pf, self.mtp)
+        return dtsgen.create_device_tree()
+
+    def dts(self, output):
+        from dsx.device_tree.dts import Driver
+        dt = self.device_tree()
+        dt.generate(Driver(
+            outdir = '.',
+            parent = None,
+            output_file = output,
+            ),)
+
+    def dtb(self, output):
+        from dsx.device_tree.dtb import Driver
+        dt = self.device_tree()
+        dt.generate(Driver(
+            outdir = '.',
+            parent = None,
+            output_file = output,
+            ),)
+
+def main(cpus):
+    from cnc_cluster import Cluster
+    hard = Platform(Cluster, cpus, binaries = ["boot.bin", "kernel@0x00a00000:D"])
+    hard.simulator()
+    hard.dts(os.path.basename(__file__)[:-2]+'dts')
+    hard.dtb(os.path.basename(__file__)[:-2]+'dtb')
+
+if __name__ == '__main__':
+    import sys
+    cpus = 1
+    if len(sys.argv) > 1:
+        cpus = int(sys.argv[1])
+    main(cpus)
Index: branches/v4/platforms/dsx/v1_1cluster_phys/cluster.py
===================================================================
--- branches/v4/platforms/dsx/v1_1cluster_phys/cluster.py	(revision 371)
+++ branches/v4/platforms/dsx/v1_1cluster_phys/cluster.py	(revision 371)
@@ -0,0 +1,131 @@
+
+__doc__ = '''
+This file is a Cluster library. It contains classes implementing the
+netlist of a cluster, for different tsar versions.
+'''
+
+class Cluster:
+    '''
+    A generic netlist of a cluster, which must be subclassed to
+    implement caches&dma instanciation
+    '''
+    
+    def __init__(self, pf, ringp, ringc, mtp, mtc, mtx, proc_count, cluster_no, cluster_base):
+        self.pf = pf
+        self.ringp = ringp
+        self.ringc = ringc
+        self.mtp = mtp
+        self.mtc = mtc
+        self.mtx = mtx
+        self.cluster_no = cluster_no
+
+        self.generate(proc_count, cluster_base)
+
+    def generate(self, proc_count, cluster_base):
+        '''
+        The core netlist, where caches and components are created
+        '''
+        self.cpu = []
+        for i in range(proc_count):
+            c = self.create_cpu(i,
+                                cluster_base
+                                + 0x01200000
+                                + 0x01000000 * i
+                                )
+            self.cpu.append(c)
+
+        memc, xram = self.create_memcache( segments = [
+            ('reset', 0xbfc00000, 0x00010000),
+            ('excep', 0x80000000, 0x00010000),
+            ('text', 0x00400000, 0x00050000),
+            ('data', 0x10000000, 0x00100000),
+            ] )
+        tty  = self.create_tty( addr = 0xc0200000, tty_count = 1 )
+	xicu = self.create_xicu( addr = 0xd2200000, pti_count = 1, 
+						    hwi_count = 1,
+						    wti_count = 4, 
+						    irq_count = 4)
+	tty.irq[0] // xicu.hwi[0]
+	for i in range(proc_count):
+	    self.cpu[i].irq[0] // xicu.irq[i]
+
+    def create_tty(self, addr, tty_count = 1):
+        names = map(lambda x:'tty%d'%x, range(tty_count))
+        name = 'tty%d'%self.cluster_no
+        tty = self.pf.create('caba:vci_multi_tty', name, names = names)
+        self.ringp.to_target.new() // tty.vci
+        tty.addSegment(name, address = addr, size = 0x40, cacheable = False)
+        return tty
+    
+    def create_xicu(self, addr, pti_count, hwi_count, wti_count, irq_count):
+        name = 'xicu'
+        xicu = self.pf.create('caba:vci_xicu_vhdl', name, pti_count = pti_count,
+				          		  hwi_count = hwi_count,
+							  wti_count = wti_count,
+							  irq_count = irq_count)
+        self.ringp.to_target.new() // xicu.vci
+        xicu.addSegment(name, address = addr, size = 0x1000, cacheable = False)
+        return xicu
+
+
+class ClusterV3(Cluster):
+    '''
+    A TsarV3 implementation, using vci_cc_vcache_wrapper2_v1,
+    vci_mem_cache_v3 and vci_dma_tsar_v2.
+    '''
+
+    def create_cpu(self, cpuid, addr):
+            c = self.pf.create(
+                'caba:vci_cc_xcache_wrapper_v1',
+                'proc_%d_%d' % (self.cluster_no, cpuid),
+                iss_t = "common:mips32el",
+                proc_id = cpuid,
+                icache_ways = 4,
+                icache_sets = 64,
+                icache_words = 16,
+                dcache_ways = 4,
+                dcache_sets = 64,
+                dcache_words = 16,
+                write_buf_size = 16,
+                )
+            self.ringc.to_initiator.new() // c.vci_ini_c
+            self.ringc.to_target.new() // c.vci_tgt
+            self.ringp.to_initiator.new() // c.vci_ini_rw
+
+            c.addSegment('proc_%d_%d' % (self.cluster_no, cpuid),
+                         address = addr,
+                         size = 0x10,
+                         cacheable = False,
+                         )
+
+            return c
+
+    def create_memcache(self, segments):
+        memc = self.pf.create('caba:vci_mem_cache_v1', 'memc',
+                              mtx = self.mtx,
+                              vci_ixr_index = (self.cluster_no,),
+                              nways = 16,
+                              nsets = 256,
+                              nwords = 16,
+                              )
+        self.ringc.to_target.new() // memc.vci_tgt_cleanup
+        self.ringp.to_target.new() // memc.vci_tgt
+        self.ringc.to_initiator.new() // memc.vci_ini
+
+        xram = self.pf.create('caba:vci_simple_ram', 'xram',
+                              mt = self.mtx,
+                              ident = (self.cluster_no,),
+                              latency = 1,
+                 )
+        memc.vci_ixr // xram.vci
+
+        for name, addr, size in segments:
+            # Here DSX knows the only way to address xram is through its
+            # vci port. It also knows the only associated mapping_table.
+            xram.addSegment('ram_x_'+name, address = addr, size = size, cacheable = True)
+
+            # For these segments, there is ambiguity for the mapping_table
+            # we are talking about, so we specify mt = ...
+            memc.addSegment('ram_p_'+name, address = addr, size = size, cacheable = True, mt = self.mtp)
+            memc.addSegment('ram_c_'+name, address = addr, size = size, cacheable = True, mt = self.mtc)
+        return memc, xram
Index: branches/v4/platforms/dsx/v1_1cluster_phys/dsx.conf
===================================================================
--- branches/v4/platforms/dsx/v1_1cluster_phys/dsx.conf	(revision 371)
+++ branches/v4/platforms/dsx/v1_1cluster_phys/dsx.conf	(revision 371)
@@ -0,0 +1,1 @@
+soclib_type = "modelsim"
Index: branches/v4/platforms/dsx/v1_1cluster_phys/v1_1cluster_phys.py
===================================================================
--- branches/v4/platforms/dsx/v1_1cluster_phys/v1_1cluster_phys.py	(revision 371)
+++ branches/v4/platforms/dsx/v1_1cluster_phys/v1_1cluster_phys.py	(revision 371)
@@ -0,0 +1,107 @@
+#!/usr/bin/env python
+
+import dsx
+import soclib
+import soclib.component
+import os
+
+import platform_handlers
+
+class Platform:
+    def __init__(self, cluster_ctor, proc_count, binaries):
+        self.pf = soclib.Architecture(cell_size = 4,
+                                      plen_size = 8,
+                                      addr_size = 64,
+                                      rerror_size = 1,
+                                      clen_size = 1,
+                                      rflag_size = 1,
+                                      srcid_size = 14,
+                                      pktid_size = 4,
+                                      trdid_size = 4,
+                                      wrplen_size = 1
+                                      )
+        for name in ['mtp', 'mtc', 'mtx']:
+            mt = self.pf.create('common:mapping_table', name,
+                                addr_size = 40,
+                                addr_bits = [16], srcid_bits = [14],
+                                cacheability_mask = 0x0000300000)
+            # create self.mt[pcx]
+            setattr(self, name, mt)
+
+        # create a dictionary containing
+        # loader = x, loader2 = y, ...
+        bins = {}
+        for i, bin in enumerate(binaries):
+            k = 'binary'
+            if i:
+                k += str(i+1)
+            bins[k] = bin
+        self.loader = self.pf.create('common:loader', 'loader', **bins)
+
+        # self.ringc = self.pf.create(
+        #     'caba:vci_simple_ring_network', 'ringc', 
+        #     mt = mtc,
+        #     ringid = (),
+        #     wrapper_fifo_depth = 2, )
+        # self.ringp = self.pf.create(
+        #     'caba:vci_simple_ring_network', 'ringp', 
+        #     mt = mtp,
+        #     ringid = (),
+        #     wrapper_fifo_depth = 2, )
+        self.ringc = self.pf.create('caba:vci_simple_ring_network', 'ringc', 
+                                    mt = self.mtc,
+                                    ringid = (),
+                                    wrapper_fifo_depth = 2)
+        self.ringp = self.pf.create('caba:vci_simple_ring_network', 'ringp', 
+                                    mt = self.mtp,
+                                    ringid = (),
+                                    wrapper_fifo_depth = 2)
+
+        self.cluster = cluster_ctor(self.pf,
+                                    self.ringp, self.ringc,
+                                    self.mtp, self.mtc, self.mtx,
+                                    proc_count = proc_count,
+                                    cluster_no = 0,
+                                    cluster_base = 0x00000000,
+                                    )
+
+    def simulator(self, outdir = 'hard'):
+        self.pf.generate(soclib.PfDriver(outdir = outdir))
+
+    def device_tree(self):
+        from dsx.contrib.dts_platform.platform_to_dts import PlatformToDts
+        import dsx.contrib.dts_platform.platform_handlers
+        dtsgen = PlatformToDts(self.pf, self.mtp)
+        return dtsgen.create_device_tree()
+
+    def dts(self, output):
+        from dsx.device_tree.dts import Driver
+        dt = self.device_tree()
+        dt.generate(Driver(
+            outdir = '.',
+            parent = None,
+            output_file = output,
+            ),)
+
+    def dtb(self, output):
+        from dsx.device_tree.dtb import Driver
+        dt = self.device_tree()
+        dt.generate(Driver(
+            outdir = '.',
+            parent = None,
+            output_file = output,
+            ),)
+
+def main(cpus):
+    from cluster import ClusterV3
+    hard = Platform(ClusterV3, cpus, binaries = ["bin.soft"])
+    hard.simulator('.')
+    hard.dts(os.path.basename(__file__)[:-2]+'dts')
+    hard.dtb(os.path.basename(__file__)[:-2]+'dtb')
+
+if __name__ == '__main__':
+    import sys
+    cpus = 4
+    if len(sys.argv) > 1:
+        cpus = int(sys.argv[1])
+    main(cpus)
Index: branches/v4/platforms/dsx/v1_1cluster_phys_dma/cluster.py
===================================================================
--- branches/v4/platforms/dsx/v1_1cluster_phys_dma/cluster.py	(revision 371)
+++ branches/v4/platforms/dsx/v1_1cluster_phys_dma/cluster.py	(revision 371)
@@ -0,0 +1,155 @@
+
+__doc__ = '''
+This file is a Cluster library. It contains classes implementing the
+netlist of a cluster, for different tsar versions.
+'''
+
+class Cluster:
+    '''
+    A generic netlist of a cluster, which must be subclassed to
+    implement caches&dma instanciation
+    '''
+    
+    def __init__(self, pf, ringp, ringc, mtp, mtc, mtx, proc_count, cluster_no, cluster_base):
+        self.pf = pf
+        self.ringp = ringp
+        self.ringc = ringc
+        self.mtp = mtp
+        self.mtc = mtc
+        self.mtx = mtx
+        self.cluster_no = cluster_no
+
+        self.generate(proc_count, cluster_base)
+
+    def generate(self, proc_count, cluster_base):
+        '''
+        The core netlist, where caches and components are created
+        '''
+        self.cpu = []
+        for i in range(proc_count):
+            c = self.create_cpu(i,
+                                cluster_base
+                                + 0x01200000
+                                + 0x01000000 * i
+                                )
+            self.cpu.append(c)
+
+        memc, xram = self.create_memcache( segments = [
+            ('reset', 0xbfc00000, 0x00010000),
+            ('excep', 0x80000000, 0x00010000),
+            ('text', 0x00400000, 0x00050000),
+            ('data', 0x10000000, 0x00100000),
+            ] )
+        tty  = self.create_tty( addr = 0xc0200000, tty_count = 1 )
+	xicu = self.create_xicu( addr = 0xd2200000, pti_count = 1, 
+						    hwi_count = 3,
+						    wti_count = 4, 
+						    irq_count = 4)
+	dma = self.create_dma( addr = 0xd1200000, burst_size = 64)
+	fb  = self.create_fb( addr = 0xe2200000, width = 320,
+						 height = 200,
+						 subsampling = 422)
+
+	tty.irq[0] // xicu.hwi[0]
+	for i in range(proc_count):
+	    self.cpu[i].irq[0] // xicu.irq[i]
+	dma.irq // xicu.hwi[1]
+	
+
+    def create_dma(self, addr, burst_size):
+        name = 'dma%d'%self.cluster_no
+        dma = self.pf.create('caba:vci_dma_vhdl', name, burst_size = burst_size)
+        self.ringp.to_target.new() // dma.vci_target
+        self.ringp.to_initiator.new() // dma.vci_initiator
+        dma.addSegment(name, address = addr, size = 0x1000, cacheable = False)
+        return dma
+
+    def create_fb(self, addr, width, height, subsampling):
+        name = 'fb%d'%self.cluster_no
+        fb = self.pf.create('caba:vci_framebuffer', name, width = width,
+						       height = height,
+						       subsampling = subsampling)
+        self.ringp.to_target.new() // fb.vci
+        fb.addSegment(name, address = addr, size = width * height * 2, cacheable = False)
+        return fb
+
+    def create_tty(self, addr, tty_count = 1):
+        names = map(lambda x:'tty%d'%x, range(tty_count))
+        name = 'tty%d'%self.cluster_no
+        tty = self.pf.create('caba:vci_multi_tty', name, names = names)
+        self.ringp.to_target.new() // tty.vci
+        tty.addSegment(name, address = addr, size = 0x1000, cacheable = False)
+        return tty
+    
+    def create_xicu(self, addr, pti_count, hwi_count, wti_count, irq_count):
+        name = 'xicu'
+        xicu = self.pf.create('caba:vci_xicu', name, pti_count = pti_count,
+				          		  hwi_count = hwi_count,
+							  wti_count = wti_count,
+							  irq_count = irq_count)
+        self.ringp.to_target.new() // xicu.vci
+        xicu.addSegment(name, address = addr, size = 0x1000, cacheable = False)
+        return xicu
+
+
+class ClusterV3(Cluster):
+    '''
+    A TsarV3 implementation, using vci_cc_vcache_wrapper2_v1,
+    vci_mem_cache_v3 and vci_dma_tsar_v2.
+    '''
+
+    def create_cpu(self, cpuid, addr):
+            c = self.pf.create(
+                'caba:vci_cc_xcache_wrapper_v1',
+                'proc_%d_%d' % (self.cluster_no, cpuid),
+                iss_t = "common:mips32el",
+                proc_id = cpuid,
+                icache_ways = 4,
+                icache_sets = 64,
+                icache_words = 16,
+                dcache_ways = 4,
+                dcache_sets = 64,
+                dcache_words = 16,
+                write_buf_size = 16,
+                )
+            self.ringc.to_initiator.new() // c.vci_ini_c
+            self.ringc.to_target.new() // c.vci_tgt
+            self.ringp.to_initiator.new() // c.vci_ini_rw
+
+            c.addSegment('proc_%d_%d' % (self.cluster_no, cpuid),
+                         address = addr,
+                         size = 0x10,
+                         cacheable = False,
+                         )
+
+            return c
+
+    def create_memcache(self, segments):
+        memc = self.pf.create('caba:vci_mem_cache_v1', 'memc',
+                              mtx = self.mtx,
+                              vci_ixr_index = (self.cluster_no,),
+                              nways = 16,
+                              nsets = 256,
+                              nwords = 16,
+                              )
+        self.ringc.to_target.new() // memc.vci_tgt_cleanup
+        self.ringp.to_target.new() // memc.vci_tgt
+        self.ringc.to_initiator.new() // memc.vci_ini
+
+        xram = self.pf.create('caba:vci_simple_ram', 'xram',
+                              mt = self.mtx,
+                              ident = (self.cluster_no,),
+                              latency = 1,
+                 )
+        memc.vci_ixr // xram.vci
+
+        for name, addr, size in segments:
+            # Here DSX knows the only way to address xram is through its
+            # vci port. It also knows the only associated mapping_table.
+            xram.addSegment('ram_x_'+name, address = addr, size = size, cacheable = True)
+
+            # For these segments, there is ambiguity for the mapping_table
+            # we are talking about, so we specify mt = ...
+            memc.addSegment('ram_p_'+name, address = addr, size = size, cacheable = True, mt = self.mtp)
+            memc.addSegment('ram_c_'+name, address = addr, size = size, cacheable = True, mt = self.mtc)
+        return memc, xram
Index: branches/v4/platforms/dsx/v1_1cluster_phys_dma/dsx.conf
===================================================================
--- branches/v4/platforms/dsx/v1_1cluster_phys_dma/dsx.conf	(revision 371)
+++ branches/v4/platforms/dsx/v1_1cluster_phys_dma/dsx.conf	(revision 371)
@@ -0,0 +1,1 @@
+soclib_type = "modelsim"
Index: branches/v4/platforms/dsx/v1_1cluster_phys_dma/main.cpp
===================================================================
--- branches/v4/platforms/dsx/v1_1cluster_phys_dma/main.cpp	(revision 371)
+++ branches/v4/platforms/dsx/v1_1cluster_phys_dma/main.cpp	(revision 371)
@@ -0,0 +1,86 @@
+#include <systemc>
+#include <signal.h>
+#include <sys/time.h>
+#include <cstdlib>
+#include <cstdarg>
+
+#include "topcell_.h"
+
+bool stop;
+void run(sc_core::sc_signal<bool> &resetn)
+{
+#ifdef SYSTEMCASS
+	sc_core::sc_start(0);
+	resetn = false;
+	sc_core::sc_start(1);
+	resetn = true;
+#else
+	sc_core::sc_start(sc_core::sc_time(0, sc_core::SC_NS));
+	resetn = false;
+	sc_core::sc_start(sc_core::sc_time(1, sc_core::SC_NS));
+	resetn = true;
+#endif
+
+#ifdef SOCVIEW
+	debug();
+#else
+	const char *t = getenv("STATS_EVERY");
+	if ( t ) {
+		int delta = atoi(t);
+		while (!stop) {
+			struct timezone tz;
+			struct timeval end, begin, tp;
+			gettimeofday( &begin, &tz );
+#ifdef SYSTEMCASS
+			sc_core::sc_start(delta);
+#else
+			sc_core::sc_start(sc_core::sc_time(delta, sc_core::SC_NS));
+#endif
+			gettimeofday( &end, &tz );
+			timersub( &end, &begin, &tp );
+			long ms = (tp.tv_sec*1000+tp.tv_usec/1000);
+			std::cout << std::dec << delta << " cycles in " << ms << " ms: " << ((double)delta*1000/ms) << " Hz" << std::endl;
+		}
+	} else {
+		sc_core::sc_start();
+	}
+#endif
+}
+
+int _main(int argc, char **argv)
+{
+	sc_core::sc_signal<bool> resetn;
+	sc_core::sc_clock clock;
+
+	topcell_ top0("top0");
+
+	top0.p_resetn(resetn);
+	top0.p_clock(clock);
+
+	run(resetn);
+
+	return 0;
+}
+
+void quit(int)
+{
+	sc_core::sc_stop();
+    stop = true;
+}
+
+int sc_main (int argc, char *argv[])
+{
+	signal(SIGINT, quit);
+	atexit(sc_core::sc_stop);
+    stop = false;
+
+	try {
+		return _main(argc, argv);
+	} catch (std::exception &e) {
+		std::cout << e.what() << std::endl;
+	} catch (...) {
+		std::cout << "Unknown exception occured" << std::endl;
+		throw;
+	}
+	return 1;
+}
Index: branches/v4/platforms/dsx/v1_1cluster_phys_dma/modelsim.ini
===================================================================
--- branches/v4/platforms/dsx/v1_1cluster_phys_dma/modelsim.ini	(revision 371)
+++ branches/v4/platforms/dsx/v1_1cluster_phys_dma/modelsim.ini	(revision 371)
@@ -0,0 +1,1310 @@
+; Copyright 1991-2009 Mentor Graphics Corporation
+;
+; All Rights Reserved.
+;
+; THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION WHICH IS THE PROPERTY OF 
+; MENTOR GRAPHICS CORPORATION OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS.
+;   
+
+[Library]
+others = $MODEL_TECH/../modelsim.ini
+;vhdl_psl_checkers = $MODEL_TECH/../vhdl_psl_checkers       // Source files only for this release
+;verilog_psl_checkers = $MODEL_TECH/../verilog_psl_checkers // Source files only for this release
+;mvc_lib = $MODEL_TECH/../mvc_lib
+
+work = work
+[vcom]
+; VHDL93 variable selects language version as the default. 
+; Default is VHDL-2002.
+; Value of 0 or 1987 for VHDL-1987.
+; Value of 1 or 1993 for VHDL-1993.
+; Default or value of 2 or 2002 for VHDL-2002.
+; Value of 3 or 2008 for VHDL-2008
+VHDL93 = 2002
+
+; Show source line containing error. Default is off.
+; Show_source = 1
+
+; Turn off unbound-component warnings. Default is on.
+; Show_Warning1 = 0
+
+; Turn off process-without-a-wait-statement warnings. Default is on.
+; Show_Warning2 = 0
+
+; Turn off null-range warnings. Default is on.
+; Show_Warning3 = 0
+
+; Turn off no-space-in-time-literal warnings. Default is on.
+; Show_Warning4 = 0
+
+; Turn off multiple-drivers-on-unresolved-signal warnings. Default is on.
+; Show_Warning5 = 0
+
+; Turn off optimization for IEEE std_logic_1164 package. Default is on.
+; Optimize_1164 = 0
+
+; Turn on resolving of ambiguous function overloading in favor of the
+; "explicit" function declaration (not the one automatically created by
+; the compiler for each type declaration). Default is off.
+; The .ini file has Explicit enabled so that std_logic_signed/unsigned
+; will match the behavior of synthesis tools.
+Explicit = 1
+
+; Turn off acceleration of the VITAL packages. Default is to accelerate.
+; NoVital = 1
+
+; Turn off VITAL compliance checking. Default is checking on.
+; NoVitalCheck = 1
+
+; Ignore VITAL compliance checking errors. Default is to not ignore.
+; IgnoreVitalErrors = 1
+
+; Turn off VITAL compliance checking warnings. Default is to show warnings.
+; Show_VitalChecksWarnings = 0
+
+; Turn off PSL assertion warning messages. Default is to show warnings.
+; Show_PslChecksWarnings = 0
+
+; Enable parsing of embedded PSL assertions. Default is enabled.
+; EmbeddedPsl = 0
+
+; Keep silent about case statement static warnings.
+; Default is to give a warning.
+; NoCaseStaticError = 1
+
+; Keep silent about warnings caused by aggregates that are not locally static.
+; Default is to give a warning.
+; NoOthersStaticError = 1
+
+; Treat as errors:
+;   case statement static warnings
+;   warnings caused by aggregates that are not locally static
+; Overrides NoCaseStaticError, NoOthersStaticError settings.
+; PedanticErrors = 1
+
+; Turn off inclusion of debugging info within design units.
+; Default is to include debugging info.
+; NoDebug = 1
+
+; Turn off "Loading..." messages. Default is messages on.
+; Quiet = 1
+
+; Turn on some limited synthesis rule compliance checking. Checks only:
+;    -- signals used (read) by a process must be in the sensitivity list
+; CheckSynthesis = 1
+
+; Activate optimizations on expressions that do not involve signals,
+; waits, or function/procedure/task invocations. Default is off.
+; ScalarOpts = 1
+
+; Turns on lint-style checking.
+; Show_Lint = 1
+
+; Require the user to specify a configuration for all bindings,
+; and do not generate a compile time default binding for the
+; component. This will result in an elaboration error of
+; 'component not bound' if the user fails to do so. Avoids the rare
+; issue of a false dependency upon the unused default binding.
+; RequireConfigForAllDefaultBinding = 1
+
+; Perform default binding at compile time.
+; Default is to do default binding at load time.
+; BindAtCompile = 1;
+
+; Inhibit range checking on subscripts of arrays. Range checking on
+; scalars defined with subtypes is inhibited by default.
+; NoIndexCheck = 1
+
+; Inhibit range checks on all (implicit and explicit) assignments to
+; scalar objects defined with subtypes.
+; NoRangeCheck = 1
+
+; Run the 0-in compiler on the VHDL source files
+; Default is off.
+; ZeroIn = 1
+
+; Set the options to be passed to the 0-in compiler.
+; Default is "".
+; ZeroInOptions = ""
+
+; Turn on code coverage in VHDL design units. Default is off.
+; Coverage = sbceft
+
+; Turn off code coverage in VHDL subprograms. Default is on.
+; CoverageSub = 0
+
+; Automatically exclude VHDL case statement default branches. 
+; Default is to not exclude.
+; CoverExcludeDefault = 1
+
+; Control compiler and VOPT optimizations that are allowed when
+; code coverage is on.  Refer to the comment for this in the [vlog] area. 
+; CoverOpt = 3
+
+; Inform code coverage optimizations to respect VHDL 'H' and 'L'
+; values on signals in conditions and expressions, and to not automatically
+; convert them to '1' and '0'. Default is to not convert.
+; CoverRespectHandL = 0
+
+; Increase or decrease the maximum number of rows allowed in a UDP table
+; implementing a VHDL condition coverage or expression coverage expression.
+; More rows leads to a longer compile time, but more expressions covered.
+; CoverMaxUDPRows = 192
+
+; Increase or decrease the maximum number of input patterns that are present
+; in FEC table. This leads to a longer compile time with more expressions
+; covered with FEC metric.
+; CoverMaxFECRows = 192
+
+; Enable or disable Focused Expression Coverage analysis for conditions and
+; expressions. Focused Expression Coverage data is provided by default when
+; expression and/or condition coverage is active.
+; CoverFEC = 0
+
+; Enable or disable short circuit evaluation of conditions and expressions when
+; condition or expression coverage is active. Short circuit evaluation is enabled
+; by default.
+; CoverShortCircuit = 0
+
+; Use this directory for compiler temporary files instead of "work/_temp"
+; CompilerTempDir = /tmp
+
+; Set this to cause the compilers to force data to be committed to disk
+; when the files are closed.
+; SyncCompilerFiles = 1
+
+; Add VHDL-AMS declarations to package STANDARD
+; Default is not to add
+; AmsStandard = 1
+
+; Range and length checking will be performed on array indices and discrete
+; ranges, and when violations are found within subprograms, errors will be
+; reported. Default is to issue warnings for violations, because subprograms
+; may not be invoked.
+; NoDeferSubpgmCheck = 0
+
+; Turn off detection of FSMs having single bit current state variable.
+; FsmSingle = 0
+
+; Turn off reset state transitions in FSM.
+; FsmResetTrans = 0
+
+; Do not show immediate assertions with constant expressions in 
+; GUI/report/UCDB etc. By default immediate assertions with constant 
+; expressions are shown in GUI/report/UCDB etc. This does not affect ;
+; evaluation of immediate assertions.
+; ShowConstantImmediateAsserts = 0 
+
+[vlog]
+; Turn off inclusion of debugging info within design units.
+; Default is to include debugging info.
+; NoDebug = 1
+
+; Turn on `protect compiler directive processing.
+; Default is to ignore `protect directives.
+; Protect = 1
+
+; Turn off "Loading..." messages. Default is messages on.
+; Quiet = 1
+
+; Turn on Verilog hazard checking (order-dependent accessing of global vars).
+; Default is off.
+; Hazard = 1
+
+; Turn on converting regular Verilog identifiers to uppercase. Allows case
+; insensitivity for module names. Default is no conversion.
+; UpCase = 1
+
+; Activate optimizations on expressions that do not involve signals,
+; waits, or function/procedure/task invocations. Default is off.
+; ScalarOpts = 1
+
+; Turns on lint-style checking.
+; Show_Lint = 1
+
+; Show source line containing error. Default is off.
+; Show_source = 1
+
+; Turn on bad option warning. Default is off.
+; Show_BadOptionWarning = 1
+
+; Revert back to IEEE 1364-1995 syntax, default is 0 (off).
+; vlog95compat = 1
+
+; Turn off PSL warning messages. Default is to show warnings.
+; Show_PslChecksWarnings = 0
+
+; Enable parsing of embedded PSL assertions. Default is enabled.
+; EmbeddedPsl = 0
+
+; Set the threshold for automatically identifying sparse Verilog memories.
+; A memory with depth equal to or more than the sparse memory threshold gets
+; marked as sparse automatically, unless specified otherwise in source code
+; or by +nosparse commandline option of vlog or vopt.
+; The default is 1M.  (i.e. memories with depth equal
+; to or greater than 1M are marked as sparse)
+; SparseMemThreshold = 1048576 
+
+; Run the 0-in compiler on the Verilog source files
+; Default is off.
+; ZeroIn = 1
+
+; Set the options to be passed to the 0-in compiler.
+; Default is "".
+; ZeroInOptions = ""
+
+; Set the option to treat all files specified in a vlog invocation as a
+; single compilation unit. The default value is set to 0 which will treat
+; each file as a separate compilation unit as specified in the P1800 draft standard.
+; MultiFileCompilationUnit = 1
+
+; Turn on code coverage in Verilog design units. Default is off.
+; Coverage = sbceft
+
+; Automatically exclude Verilog case statement default branches. 
+; Default is to not automatically exclude defaults.
+; CoverExcludeDefault = 1
+
+; Increase or decrease the maximum number of rows allowed in a UDP table
+; implementing a Verilog condition coverage or expression coverage expression.
+; More rows leads to a longer compile time, but more expressions covered.
+; CoverMaxUDPRows = 192
+
+; Increase or decrease the maximum number of input patterns that are present
+; in FEC table. This leads to a longer compile time with more expressions
+; covered with FEC metric.
+; CoverMaxFECRows = 192
+
+; Enable or disable Focused Expression Coverage analysis for conditions and
+; expressions. Focused Expression Coverage data is provided by default when
+; expression and/or condition coverage is active.
+; CoverFEC = 0
+
+; Enable or disable short circuit evaluation of conditions and expressions when
+; condition or expression coverage is active. Short circuit evaluation is enabled
+; by default.
+; CoverShortCircuit = 0
+
+
+; Turn on code coverage in VLOG `celldefine modules and modules included
+; using vlog -v and -y. Default is off.
+; CoverCells = 1
+
+; Control compiler and VOPT optimizations that are allowed when
+; code coverage is on. This is a number from 1 to 4, with the following
+; meanings (the default is 3):
+;    1 -- Turn off all optimizations that affect coverage reports.
+;    2 -- Allow optimizations that allow large performance improvements 
+;         by invoking sequential processes only when the data changes. 
+;         This may make major reductions in coverage counts.
+;    3 -- In addition, allow optimizations that may change expressions or 
+;         remove some statements. Allow constant propagation. Allow VHDL
+;         subprogram inlining and VHDL FF recognition. 
+;    4 -- In addition, allow optimizations that may remove major regions of 
+;         code by changing assignments to built-ins or removing unused
+;         signals. Change Verilog gates to continuous assignments.
+; CoverOpt = 3
+
+; Specify the override for the default value of "cross_num_print_missing"
+; option for the Cross in Covergroups. If not specified then LRM default
+; value of 0 (zero) is used. This is a compile time option.
+; SVCrossNumPrintMissingDefault = 0
+
+; Setting following to 1 would cause creation of variables which
+; would represent the value of Coverpoint expressions. This is used
+; in conjunction with "SVCoverpointExprVariablePrefix" option
+; in the modelsim.ini
+; EnableSVCoverpointExprVariable = 0
+
+; Specify the override for the prefix used in forming the variable names
+; which represent the Coverpoint expressions. This is used in conjunction with 
+; "EnableSVCoverpointExprVariable" option of the modelsim.ini
+; The default prefix is "expr".
+; The variable name is
+;    variable name => <prefix>_<coverpoint name>
+; SVCoverpointExprVariablePrefix = expr
+
+; Override for the default value of the SystemVerilog covergroup,
+; coverpoint, and cross option.goal (defined to be 100 in the LRM).
+; NOTE: It does not override specific assignments in SystemVerilog
+; source code. NOTE: The modelsim.ini variable "SVCovergroupGoal"
+; in the [vsim] section can override this value.
+; SVCovergroupGoalDefault = 100
+
+; Override for the default value of the SystemVerilog covergroup,
+; coverpoint, and cross type_option.goal (defined to be 100 in the LRM)
+; NOTE: It does not override specific assignments in SystemVerilog
+; source code. NOTE: The modelsim.ini variable "SVCovergroupTypeGoal"
+; in the [vsim] section can override this value.
+; SVCovergroupTypeGoalDefault = 100
+
+; Specify the override for the default value of "strobe" option for the
+; Covergroup Type. This is a compile time option which forces "strobe" to
+; a user specified default value and supersedes SystemVerilog specified
+; default value of '0'(zero). NOTE: This can be overriden by a runtime
+; modelsim.ini variable "SVCovergroupStrobe" in the [vsim] section.
+; SVCovergroupStrobeDefault = 0
+
+; Specify the override for the default value of "merge_instances" option for
+; the Covergroup Type. This is a compile time option which forces 
+; "merge_instances" to a user specified default value and supersedes 
+; SystemVerilog specified default value of '0'(zero).
+; SVCovergroupMergeInstancesDefault = 0
+
+; Specify the override for the default value of "per_instance" option for the
+; Covergroup variables. This is a compile time option which forces "per_instance"
+; to a user specified default value and supersedes SystemVerilog specified
+; default value of '0'(zero).
+; SVCovergroupPerInstanceDefault = 0
+
+; Specify the override for the default value of "get_inst_coverage" option for the
+; Covergroup variables. This is a compile time option which forces 
+; "get_inst_coverage" to a user specified default value and supersedes 
+; SystemVerilog specified default value of '0'(zero).
+; SVCovergroupGetInstCoverageDefault = 0
+
+;
+; A space separated list of resource libraries that contain precompiled
+; packages.  The behavior is identical to using the "-L" switch.
+; 
+; LibrarySearchPath = <path/lib> [<path/lib> ...]
+LibrarySearchPath = mtiAvm mtiOvm mtiUPF
+
+; The behavior is identical to the "-mixedansiports" switch.  Default is off.
+; MixedAnsiPorts = 1
+
+; Enable SystemVerilog 3.1a $typeof() function. Default is off.
+; EnableTypeOf = 1
+
+; Only allow lower case pragmas. Default is disabled.
+; AcceptLowerCasePragmaOnly = 1
+
+; Set the maximum depth permitted for a recursive include file nesting.
+; IncludeRecursionDepthMax = 5
+
+; Turn off detection of FSMs having single bit current state variable.
+; FsmSingle = 0
+
+; Turn off reset state transitions in FSM.
+; FsmResetTrans = 0
+
+; Turn off detections of FSMs having x-assignment.
+; FsmXAssign = 0
+
+; List of file suffixes which will be read as SystemVerilog.  White space
+; in extensions can be specified with a back-slash: "\ ".  Back-slashes
+; can be specified with two consecutive back-slashes: "\\";
+; SVFileExtensions = sv svp svh
+
+; This setting is the same as the vlog -sv command line switch.
+; Enables SystemVerilog features and keywords when true (1).
+; When false (0), the rules of IEEE Std 1364-2001 are followed and 
+; SystemVerilog keywords are ignored. 
+; Svlog = 0
+
+; Prints attribute placed upon SV packages during package import
+; when true (1).  The attribute will be ignored when this
+; entry is false (0). The attribute name is "package_load_message".
+; The value of this attribute is a string literal.
+; Default is true (1).
+; PrintSVPackageLoadingAttribute = 1
+
+; Do not show immediate assertions with constant expressions in 
+; GUI/reports/UCDB etc. By default immediate assertions with constant 
+; expressions are shown in GUI/reports/UCDB etc. This does not affect 
+; evaluation of immediate assertions.
+; ShowConstantImmediateAsserts = 0
+
+[sccom]
+; Enable use of SCV include files and library.  Default is off.
+; UseScv = 1
+
+; Add C++ compiler options to the sccom command line by using this variable.
+; CppOptions = -g
+
+; Use custom C++ compiler located at this path rather than the default path.
+; The path should point directly at a compiler executable.
+; CppPath = /usr/bin/g++
+
+; Enable verbose messages from sccom.  Default is off.
+; SccomVerbose = 1
+
+; sccom logfile.  Default is no logfile.
+; SccomLogfile = sccom.log
+
+; Enable use of SC_MS include files and library.  Default is off.
+; UseScMs = 1
+
+[vopt]
+; Turn on code coverage in vopt.  Default is off. 
+; Coverage = sbceft
+
+; Control compiler optimizations that are allowed when
+; code coverage is on.  Refer to the comment for this in the [vlog] area. 
+; CoverOpt = 3
+
+; Increase or decrease the maximum number of rows allowed in a UDP table
+; implementing a vopt condition coverage or expression coverage expression.
+; More rows leads to a longer compile time, but more expressions covered.
+; CoverMaxUDPRows = 192
+
+; Increase or decrease the maximum number of input patterns that are present
+; in FEC table. This leads to a longer compile time with more expressions
+; covered with FEC metric.
+; CoverMaxFECRows = 192
+
+; Do not show immediate assertions with constant expressions in 
+; GUI/reports/UCDB etc. By default immediate assertions with constant 
+; expressions are shown in GUI/reports/UCDB etc. This does not affect 
+; evaluation of immediate assertions.
+; ShowConstantImmediateAsserts = 0
+
+; Set the maximum number of iterations permitted for a generate loop.
+; Restricting this permits the implementation to recognize infinite
+; generate loops.
+; GenerateLoopIterationMax = 100000
+
+; Set the maximum depth permitted for a recursive generate instantiation.
+; Restricting this permits the implementation to recognize infinite
+; recursions.
+; GenerateRecursionDepthMax = 200
+
+
+[vsim]
+; vopt flow
+; Set to turn on automatic optimization of a design.
+; Default is on
+VoptFlow = 1
+
+; vopt automatic SDF
+; If automatic design optimization is on, enables automatic compilation
+; of SDF files.
+; Default is on, uncomment to turn off.
+; VoptAutoSDFCompile = 0
+
+; Automatic SDF compilation
+; Disables automatic compilation of SDF files in flows that support it.
+; Default is on, uncomment to turn off.
+; NoAutoSDFCompile = 1
+
+; Simulator resolution
+; Set to fs, ps, ns, us, ms, or sec with optional prefix of 1, 10, or 100.
+Resolution = ns
+
+; Disable certain code coverage exclusions automatically. 
+; Assertions and FSM are exluded from the code coverage by default
+; Set AutoExclusionsDisable = fsm to enable code coverage for fsm
+; Set AutoExclusionsDisable = assertions to enable code coverage for assertions
+; Set AutoExclusionsDisable = all to enable code coverage for all the automatic exclusions
+; Or specify comma or space separated list
+;AutoExclusionsDisable = fsm,assertions
+
+; User time unit for run commands
+; Set to default, fs, ps, ns, us, ms, or sec. The default is to use the
+; unit specified for Resolution. For example, if Resolution is 100ps,
+; then UserTimeUnit defaults to ps.
+; Should generally be set to default.
+UserTimeUnit = default
+
+; Default run length
+RunLength = 100
+
+; Maximum iterations that can be run without advancing simulation time
+IterationLimit = 5000
+
+; Control PSL and Verilog Assume directives during simulation
+; Set SimulateAssumeDirectives = 0 to disable assume being simulated as asserts
+; Set SimulateAssumeDirectives = 1 to enable assume simulation as asserts
+; SimulateAssumeDirectives = 1 
+
+; Control the simulation of PSL and SVA
+; These switches can be overridden by the vsim command line switches:
+;    -psl, -nopsl, -sva, -nosva.
+; Set SimulatePSL = 0 to disable PSL simulation
+; Set SimulatePSL = 1 to enable PSL simulation (default)
+; SimulatePSL = 1 
+; Set SimulateSVA = 0 to disable SVA simulation
+; Set SimulateSVA = 1 to enable concurrent SVA simulation (default)
+; SimulateSVA = 1 
+
+; Directives to license manager can be set either as single value or as
+; space separated multi-values:
+; vhdl          Immediately reserve a VHDL license
+; vlog          Immediately reserve a Verilog license
+; plus          Immediately reserve a VHDL and Verilog license
+; nomgc         Do not look for Mentor Graphics Licenses
+; nomti         Do not look for Model Technology Licenses
+; noqueue       Do not wait in the license queue when a license is not available
+; viewsim       Try for viewer license but accept simulator license(s) instead
+;               of queuing for viewer license (PE ONLY)
+; noviewer	Disable checkout of msimviewer and vsim-viewer license 
+;		features (PE ONLY)
+; noslvhdl	Disable checkout of qhsimvh and vsim license features
+; noslvlog	Disable checkout of qhsimvl and vsimvlog license features
+; nomix		Disable checkout of msimhdlmix and hdlmix license features
+; nolnl		Disable checkout of msimhdlsim and hdlsim license features
+; mixedonly	Disable checkout of qhsimvh,qhsimvl,vsim,vsimvlog license 
+;		features
+; lnlonly	Disable checkout of qhsimvh,qhsimvl,vsim,vsimvlog,msimhdlmix,
+;		hdlmix license features
+; Single value:
+; License = plus
+; Multi-value:
+; License = noqueue plus
+
+; Stop the simulator after a VHDL/Verilog immediate assertion message
+; 0 = Note  1 = Warning  2 = Error  3 = Failure  4 = Fatal
+BreakOnAssertion = 3
+
+; VHDL assertion Message Format
+; %S - Severity Level 
+; %R - Report Message
+; %T - Time of assertion
+; %D - Delta
+; %I - Instance or Region pathname (if available)
+; %i - Instance pathname with process
+; %O - Process name
+; %K - Kind of object path is to return: Instance, Signal, Process or Unknown
+; %P - Instance or Region path without leaf process
+; %F - File
+; %L - Line number of assertion or, if assertion is in a subprogram, line
+;      from which the call is made
+; %% - Print '%' character
+; If specific format for assertion level is defined, use its format.
+; If specific format is not defined for assertion level:
+; - and if failure occurs during elaboration, use MessageFormatBreakLine;
+; - and if assertion triggers a breakpoint (controlled by BreakOnAssertion
+;   level), use MessageFormatBreak;
+; - otherwise, use MessageFormat.
+; MessageFormatBreakLine = "** %S: %R\n   Time: %T  Iteration: %D  %K: %i File: %F Line: %L\n"
+; MessageFormatBreak     = "** %S: %R\n   Time: %T  Iteration: %D  %K: %i File: %F\n"
+; MessageFormat          = "** %S: %R\n   Time: %T  Iteration: %D%I\n"
+; MessageFormatNote      = "** %S: %R\n   Time: %T  Iteration: %D%I\n"
+; MessageFormatWarning   = "** %S: %R\n   Time: %T  Iteration: %D%I\n"
+; MessageFormatError     = "** %S: %R\n   Time: %T  Iteration: %D  %K: %i File: %F\n"
+; MessageFormatFail      = "** %S: %R\n   Time: %T  Iteration: %D  %K: %i File: %F\n"
+; MessageFormatFatal     = "** %S: %R\n   Time: %T  Iteration: %D  %K: %i File: %F\n"
+
+; Error File - alternate file for storing error messages
+; ErrorFile = error.log
+
+
+; Simulation Breakpoint messages
+; This flag controls the display of function names when reporting the location
+; where the simulator stops do to a breakpoint or fatal error.
+; Example w/function name:  # Break in Process ctr at counter.vhd line 44
+; Example wo/function name: # Break at counter.vhd line 44
+ShowFunctions = 1
+
+; Default radix for all windows and commands.
+; Set to symbolic, ascii, binary, octal, decimal, hex, unsigned
+DefaultRadix = symbolic
+
+; VSIM Startup command
+; Startup = do startup.do
+
+; VSIM Shutdown file
+; Filename to save u/i formats and configurations.
+; ShutdownFile = restart.do
+; To explicitly disable auto save:
+; ShutdownFile = --disable-auto-save
+
+; File for saving command transcript
+TranscriptFile = transcript
+
+; File for saving command history
+; CommandHistory = cmdhist.log
+
+; Specify whether paths in simulator commands should be described
+; in VHDL or Verilog format.
+; For VHDL, PathSeparator = /
+; For Verilog, PathSeparator = .
+; Must not be the same character as DatasetSeparator.
+PathSeparator = /
+
+; Specify the dataset separator for fully rooted contexts.
+; The default is ':'. For example: sim:/top
+; Must not be the same character as PathSeparator.
+DatasetSeparator = :
+
+; Specify a unique path separator for the Signal Spy set of functions. 
+; The default will be to use the PathSeparator variable.
+; Must not be the same character as DatasetSeparator.
+; SignalSpyPathSeparator = /
+
+; Used to control parsing of HDL identifiers input to the tool.
+; This includes CLI commands, vsim/vopt/vlog/vcom options,
+; string arguments to FLI/VPI/DPI calls, etc.
+; If set to 1, accept either Verilog escaped Id syntax or
+; VHDL extended id syntax, regardless of source language.
+; If set to 0, the syntax of the source language must be used.
+; Each identifier in a hierarchical name may need different syntax,
+; e.g. "/top/\vhdl*ext*id\/middle/\vlog*ext*id /bottom" or
+;       "top.\vhdl*ext*id\.middle.\vlog*ext*id .bottom"
+; GenerousIdentifierParsing = 1
+
+; Disable VHDL assertion messages
+; IgnoreNote = 1
+; IgnoreWarning = 1
+; IgnoreError = 1
+; IgnoreFailure = 1
+
+; Disable System Verilog assertion messages
+; IgnoreSVAInfo = 1 
+; IgnoreSVAWarning = 1
+; IgnoreSVAError = 1
+; IgnoreSVAFatal = 1
+
+; Do not print any additional information from Severity System tasks.
+; Only the message provided by the user is printed along with severity
+; information.
+; SVAPrintOnlyUserMessage = 1;
+
+; Default force kind. May be freeze, drive, deposit, or default
+; or in other terms, fixed, wired, or charged.
+; A value of "default" will use the signal kind to determine the
+; force kind, drive for resolved signals, freeze for unresolved signals
+; DefaultForceKind = freeze
+
+; If zero, open files when elaborated; otherwise, open files on
+; first read or write.  Default is 0.
+; DelayFileOpen = 1
+
+; Control VHDL files opened for write.
+;   0 = Buffered, 1 = Unbuffered
+UnbufferedOutput = 0
+
+; Control the number of VHDL files open concurrently.
+; This number should always be less than the current ulimit
+; setting for max file descriptors.
+;   0 = unlimited
+ConcurrentFileLimit = 40
+
+; Control the number of hierarchical regions displayed as
+; part of a signal name shown in the Wave window.
+; A value of zero tells VSIM to display the full name.
+; The default is 0.
+; WaveSignalNameWidth = 0
+
+; Turn off warnings when changing VHDL constants and generics
+; Default is 1 to generate warning messages
+; WarnConstantChange = 0
+
+; Turn off warnings from the std_logic_arith, std_logic_unsigned
+; and std_logic_signed packages.
+; StdArithNoWarnings = 1
+
+; Turn off warnings from the IEEE numeric_std and numeric_bit packages.
+; NumericStdNoWarnings = 1
+
+; Control the format of the (VHDL) FOR generate statement label
+; for each iteration.  Do not quote it.
+; The format string here must contain the conversion codes %s and %d,
+; in that order, and no other conversion codes.  The %s represents
+; the generate_label; the %d represents the generate parameter value
+; at a particular generate iteration (this is the position number if
+; the generate parameter is of an enumeration type).  Embedded whitespace
+; is allowed (but discouraged); leading and trailing whitespace is ignored.
+; Application of the format must result in a unique scope name over all
+; such names in the design so that name lookup can function properly.
+; GenerateFormat = %s__%d
+
+; Specify whether checkpoint files should be compressed.
+; The default is 1 (compressed).
+; CheckpointCompressMode = 0
+
+; Specify whether to enable SystemVerilog DPI "out-of-the-blue" calls.
+; The term "out-of-the-blue" refers to SystemVerilog export function calls
+; made from C functions that don't have the proper context setup
+; (as is the case when running under "DPI-C" import functions).
+; When this is enabled, one can call a DPI export function
+; (but not task) from any C code.
+; the setting of this variable can be one of the following values:
+; 0 : dpioutoftheblue call is disabled (default)
+; 1 : dpioutoftheblue call is enabled, but export call debug support is not available.
+; 2 : dpioutoftheblue call is enabled, and limited export call debug support is available.
+; DpiOutOfTheBlue = 1
+
+; Specify whether continuous assignments are run before other normal priority
+; processes scheduled in the same iteration. This event ordering minimizes race
+; differences between optimized and non-optimized designs, and is the default
+; behavior beginning with the 6.5 release. For pre-6.5 event ordering, set
+; ImmediateContinuousAssign to 0.
+; The default is 1 (enabled).
+; ImmediateContinuousAssign = 0
+
+; List of dynamically loaded objects for Verilog PLI applications
+; Veriuser = veriuser.sl
+
+; Which default VPI object model should the tool conform to?
+; The 1364 modes are Verilog-only, for backwards compatibility with older
+; libraries, and SystemVerilog objects are not available in these modes.
+; 
+; In the absence of a user-specified default, the tool default is the
+; latest available LRM behavior.
+; Options for PliCompatDefault are:
+;  VPI_COMPATIBILITY_VERSION_1364v1995
+;  VPI_COMPATIBILITY_VERSION_1364v2001
+;  VPI_COMPATIBILITY_VERSION_1364v2005
+;  VPI_COMPATIBILITY_VERSION_1800v2005
+;  VPI_COMPATIBILITY_VERSION_1800v2008
+;
+; Synonyms for each string are also recognized:
+;  VPI_COMPATIBILITY_VERSION_1364v1995 (1995, 95, 1364v1995, 1364V1995, VL1995)
+;  VPI_COMPATIBILITY_VERSION_1364v2001 (2001, 01, 1364v2001, 1364V2001, VL2001)
+;  VPI_COMPATIBILITY_VERSION_1364v2005 (1364v2005, 1364V2005, VL2005)
+;  VPI_COMPATIBILITY_VERSION_1800v2005 (2005, 05, 1800v2005, 1800V2005, SV2005)
+;  VPI_COMPATIBILITY_VERSION_1800v2008 (2008, 08, 1800v2008, 1800V2008, SV2008)
+
+
+; PliCompatDefault = VPI_COMPATIBILITY_VERSION_1800v2005
+
+; Specify default options for the restart command. Options can be one
+; or more of: -force -nobreakpoint -nolist -nolog -nowave -noassertions
+; DefaultRestartOptions = -force
+
+; Turn on (1) or off (0) WLF file compression.
+; The default is 1 (compress WLF file).
+; WLFCompress = 0
+
+; Specify whether to save all design hierarchy (1) in the WLF file
+; or only regions containing logged signals (0).
+; The default is 0 (save only regions with logged signals).
+; WLFSaveAllRegions = 1
+
+; WLF file time limit.  Limit WLF file by time, as closely as possible,
+; to the specified amount of simulation time.  When the limit is exceeded
+; the earliest times get truncated from the file.
+; If both time and size limits are specified the most restrictive is used.
+; UserTimeUnits are used if time units are not specified.
+; The default is 0 (no limit).  Example: WLFTimeLimit = {100 ms}
+; WLFTimeLimit = 0
+
+; WLF file size limit.  Limit WLF file size, as closely as possible,
+; to the specified number of megabytes.  If both time and size limits
+; are specified then the most restrictive is used.
+; The default is 0 (no limit).
+; WLFSizeLimit = 1000
+
+; Specify whether or not a WLF file should be deleted when the
+; simulation ends.  A value of 1 will cause the WLF file to be deleted.
+; The default is 0 (do not delete WLF file when simulation ends).
+; WLFDeleteOnQuit = 1
+
+; Specify whether or not a WLF file should be indexed during 
+; simulation.  If set to 0, the WLF file will not be indexed.
+; The default is 1, indexed the WLF file.
+; WLFIndex = 0
+
+; Specify whether or not a WLF file should be optimized during 
+; simulation.  If set to 0, the WLF file will not be optimized.
+; The default is 1, optimize the WLF file.
+; WLFOptimize = 0
+
+; Specify the name of the WLF file.
+; The default is vsim.wlf
+; WLFFilename = vsim.wlf
+
+; Specify the WLF reader cache size limit for each open WLF file.  
+; The size is giving in megabytes.  A value of 0 turns off the
+; WLF cache. 
+; WLFSimCacheSize allows a different cache size to be set for 
+; simulation WLF file independent of post-simulation WLF file 
+; viewing.  If WLFSimCacheSize is not set it defaults to the
+; WLFCacheSize setting.
+; The default WLFCacheSize setting is enabled to 256M per open WLF file.
+; WLFCacheSize = 2000
+; WLFSimCacheSize = 500
+
+; Specify the WLF file event collapse mode.
+; 0 = Preserve all events and event order. (same as -wlfnocollapse)
+; 1 = Only record values of logged objects at the end of a simulator iteration. 
+;     (same as -wlfcollapsedelta)
+; 2 = Only record values of logged objects at the end of a simulator time step. 
+;     (same as -wlfcollapsetime)
+; The default is 1.
+; WLFCollapseMode = 0
+
+; Specify whether WLF file logging can use threads on multi-processor machines
+; if 0, no threads will be used, if 1, threads will be used if the system has
+; more than one processor
+; WLFUseThreads = 1
+
+; Turn on/off undebuggable SystemC type warnings. Default is on.
+; ShowUndebuggableScTypeWarning = 0
+
+; Turn on/off unassociated SystemC name warnings. Default is off.
+; ShowUnassociatedScNameWarning = 1
+
+; Turn on/off SystemC IEEE 1666 deprecation warnings. Default is off.
+; ScShowIeeeDeprecationWarnings = 1
+
+; Turn on/off the check for multiple drivers on a SystemC sc_signal. Default is off.
+; ScEnableScSignalWriteCheck = 1
+
+; Set SystemC default time unit.
+; Set to fs, ps, ns, us, ms, or sec with optional 
+; prefix of 1, 10, or 100.  The default is 1 ns.
+; The ScTimeUnit value is honored if it is coarser than Resolution.
+; If ScTimeUnit is finer than Resolution, it is set to the value
+; of Resolution. For example, if Resolution is 100ps and ScTimeUnit is ns,
+; then the default time unit will be 1 ns.  However if Resolution 
+; is 10 ns and ScTimeUnit is ns, then the default time unit will be 10 ns.
+ScTimeUnit = ns
+
+; Set SystemC sc_main stack size. The stack size is set as an integer
+; number followed by the unit which can be Kb(Kilo-byte), Mb(Mega-byte) or
+; Gb(Giga-byte). Default is 10 Mb. The stack size for sc_main depends
+; on the amount of data on the sc_main() stack and the memory required
+; to succesfully execute the longest function call chain of sc_main().
+ScMainStackSize = 10 Mb
+
+; Turn on/off execution of remainder of sc_main upon quitting the current
+; simulation session. If the cumulative length of sc_main() in terms of 
+; simulation time units is less than the length of the current simulation
+; run upon quit or restart, sc_main() will be in the middle of execution.
+; This switch gives the option to execute the remainder of sc_main upon
+; quitting simulation. The drawback of not running sc_main till the end
+; is memory leaks for objects created by sc_main. If on, the remainder of
+; sc_main will be executed ignoring all delays. This may cause the simulator
+; to crash if the code in sc_main is dependent on some simulation state.
+; Default is on.
+ScMainFinishOnQuit = 1
+
+; Set the SCV relationship name that will be used to identify phase
+; relations.  If the name given to a transactor relation matches this
+; name, the transactions involved will be treated as phase transactions
+ScvPhaseRelationName = mti_phase
+
+; Customize the vsim kernel shutdown behavior at the end of the simulation.
+; Some common causes of the end of simulation are $finish (implicit or explicit), 
+; sc_stop(), tf_dofinish(), and assertion failures. 
+; This should be set to "ask", "exit", or "stop". The default is "ask".
+; "ask"   -- In batch mode, the vsim kernel will abruptly exit.  
+;            In GUI mode, a dialog box will pop up and ask for user confirmation 
+;            whether or not to quit the simulation.
+; "stop"  -- Cause the simulation to stay loaded in memory. This can make some 
+;            post-simulation tasks easier.
+; "exit"  -- The simulation will abruptly exit without asking for any confirmation.
+; "final" -- Run SystemVerilog final blocks then behave as "stop".
+; Note: these ini variables can be overriden by the vsim command 
+;       line switch "-onfinish <ask|stop|exit>".
+OnFinish = ask
+
+; Print pending deferred assertion messages. 
+; Deferred assertion messages may be scheduled after the $finish in the same 
+; time step. Deferred assertions scheduled to print after the $finish are 
+; printed before exiting with severity level NOTE since it's not known whether
+; the assertion is still valid due to being printed in the active region
+; instead of the reactive region where they are normally printed.
+; OnFinishPendingAssert = 1;
+
+; Print "simstats" result at the end of simulation before shutdown.
+; If this is enabled, the simstats result will be printed out before shutdown.
+; The default is off.
+; PrintSimStats = 1
+
+; Assertion File - alternate file for storing VHDL/PSL/Verilog assertion messages
+; AssertFile = assert.log
+
+; Run simulator in assertion debug mode. Default is off.
+; AssertionDebug = 1
+
+; Turn on/off PSL/SVA concurrent assertion pass enable. 
+; For SVA, Default is on when the assertion has a pass action block, or
+; the vsim -assertdebug option is used and the vopt "+acc=a" flag is active.
+; For PSL, Default is on only when vsim switch "-assertdebug" is used
+; and the vopt "+acc=a" flag is active.
+; AssertionPassEnable = 0 
+
+; Turn on/off PSL/SVA concurrent assertion fail enable. Default is on.
+; AssertionFailEnable = 0
+
+; Set PSL/SVA concurrent assertion pass limit. Default is -1.
+; Any positive integer, -1 for infinity.
+; AssertionPassLimit = 1
+
+; Set PSL/SVA concurrent assertion fail limit. Default is -1.
+; Any positive integer, -1 for infinity.
+; AssertionFailLimit = 1
+
+; Turn on/off PSL concurrent assertion pass log. Default is off.
+; The flag does not affect SVA
+; AssertionPassLog = 1
+
+; Turn on/off PSL concurrent assertion fail log. Default is on.
+; The flag does not affect SVA
+; AssertionFailLog = 0
+
+; Turn on/off SVA concurrent assertion local var printing in -assertdebug mode.  Default is on.
+; AssertionFailLocalVarLog = 0
+
+; Set action type for PSL/SVA concurrent assertion fail action. Default is continue.
+; 0 = Continue  1 = Break  2 = Exit
+; AssertionFailAction = 1
+
+; Enable the active thread monitor in the waveform display when assertion debug is enabled.
+; AssertionActiveThreadMonitor = 1
+
+; Control how many waveform rows will be used for displaying the active threads.  Default is 5.
+; AssertionActiveThreadMonitorLimit = 5
+
+
+; As per strict 1850-2005 PSL LRM, an always property can either pass
+; or fail. However, by default, Questa reports multiple passes and
+; multiple fails on top always/never property (always/never operator
+; is the top operator under Verification Directive). The reason
+; being that Questa reports passes and fails on per attempt of the
+; top always/never property. Use the following flag to instruct
+; Questa to strictly follow LRM. With this flag, all assert/never
+; directives will start an attempt once at start of simulation.
+; The attempt can either fail, match or match vacuously.
+; For e.g. if always is the top operator under assert, the always will
+; keep on checking the property at every clock. If the property under
+; always fails, the directive will be considered failed and no more 
+; checking will be done for that directive. A top always property,
+; if it does not fail, will show a pass at end of simulation.
+; The default value is '0' (i.e. zero is off). For example:
+; PslOneAttempt = 1
+
+; Specify the number of clock ticks to represent infinite clock ticks.
+; This affects eventually!, until! and until_!. If at End of Simulation
+; (EOS) an active strong-property has not clocked this number of
+; clock ticks then neither pass or fail (vacuous match) is returned
+; else respective fail/pass is returned. The default value is '0' (zero)
+; which effectively does not check for clock tick condition. For example:
+; PslInfinityThreshold = 5000
+
+; Control how many thread start times will be preserved for ATV viewing for a given assertion
+; instance.  Default is -1 (ALL).
+; ATVStartTimeKeepCount = -1
+
+; Turn on/off code coverage
+; CodeCoverage = 0
+
+; Count all code coverage condition and expression truth table rows that match.
+; CoverCountAll = 1
+
+; Turn off automatic inclusion of VHDL integers in toggle coverage. Default
+; is to include them.
+; ToggleNoIntegers = 1
+
+; Set the maximum number of values that are collected for toggle coverage of
+; VHDL integers. Default is 100;
+; ToggleMaxIntValues = 100
+
+; Set the maximum number of values that are collected for toggle coverage of
+; Verilog real. Default is 100;
+; ToggleMaxRealValues = 100
+
+; Turn on automatic inclusion of Verilog integers in toggle coverage, except
+; for enumeration types. Default is to include them.
+; ToggleVlogIntegers = 0
+
+; Turn on automatic inclusion of Verilog real type in toggle coverage, except
+; for shortreal types. Default is to not include them.
+; ToggleVlogReal = 1
+
+; Turn on automatic inclusion of Verilog fixed-size unpacked arrays in toggle coverage.
+; Default is to not include them.
+; ToggleFixedSizeArray = 1
+
+; Increase or decrease the maximum size of Verilog unpacked fixed-size arrays that
+; are included for toggle coverage. This leads to a longer simulation time with bigger
+; arrays covered with toggle coverage. Default is 1024.
+; ToggleMaxFixedSizeArray = 1024
+
+; Treat packed vectors and structures as reg-vectors in toggle coverage. Default is 0.
+; TogglePackedAsVec = 0
+
+; Treat Verilog enumerated types as reg-vectors in toggle coverage. Default is 0.
+; ToggleVlogEnumBits = 0
+
+; Limit the widths of registers automatically tracked for toggle coverage. Default is 128.
+; For unlimited width, set to 0.
+; ToggleWidthLimit = 128
+
+; Limit the counts that are tracked for toggle coverage. When all edges for a bit have
+; reached this count, further activity on the bit is ignored. Default is 1.
+; For unlimited counts, set to 0.
+; ToggleCountLimit = 1
+
+; Turn on/off all PSL/SVA cover directive enables.  Default is on.
+; CoverEnable = 0
+
+; Turn on/off PSL/SVA cover log.  Default is off "0".
+; CoverLog = 1
+
+; Set "at_least" value for all PSL/SVA cover directives.  Default is 1.
+; CoverAtLeast = 2
+
+; Set "limit" value for all PSL/SVA cover directives.  Default is -1.
+; Any positive integer, -1 for infinity.
+; CoverLimit = 1
+
+; Specify the coverage database filename.
+; Default is "" (i.e. database is NOT automatically saved on close). 
+; UCDBFilename = vsim.ucdb
+
+; Specify the maximum limit for the number of Cross (bin) products reported
+; in XML and UCDB report against a Cross. A warning is issued if the limit
+; is crossed.
+; MaxReportRhsSVCrossProducts = 1000
+
+; Specify the override for the "auto_bin_max" option for the Covergroups.
+; If not specified then value from Covergroup "option" is used.
+; SVCoverpointAutoBinMax = 64
+
+; Specify the override for the value of "cross_num_print_missing"
+; option for the Cross in Covergroups. If not specified then value
+; specified in the "option.cross_num_print_missing" is used. This
+; is a runtime option. NOTE: This overrides any "cross_num_print_missing"
+; value specified by user in source file and any SVCrossNumPrintMissingDefault
+; specified in modelsim.ini.
+; SVCrossNumPrintMissing = 0
+
+; Specify whether to use the value of "cross_num_print_missing"
+; option in report and GUI for the Cross in Covergroups. If not specified then 
+; cross_num_print_missing is ignored for creating reports and displaying 
+; covergroups in GUI. Default is 0, which means ignore "cross_num_print_missing".
+; UseSVCrossNumPrintMissing = 0
+
+; Specify the override for the value of "strobe" option for the
+; Covergroup Type. If not specified then value in "type_option.strobe"
+; will be used. This is runtime option which forces "strobe" to
+; user specified value and supersedes user specified values in the
+; SystemVerilog Code. NOTE: This also overrides the compile time
+; default value override specified using "SVCovergroupStrobeDefault"
+; SVCovergroupStrobe = 0
+
+; Override for explicit assignments in source code to "option.goal" of
+; SystemVerilog covergroup, coverpoint, and cross. It also overrides the
+; default value of "option.goal" (defined to be 100 in the SystemVerilog
+; LRM) and the value of modelsim.ini variable "SVCovergroupGoalDefault".
+; SVCovergroupGoal = 100
+
+; Override for explicit assignments in source code to "type_option.goal" of
+; SystemVerilog covergroup, coverpoint, and cross. It also overrides the
+; default value of "type_option.goal" (defined to be 100 in the SystemVerilog
+; LRM) and the value of modelsim.ini variable "SVCovergroupTypeGoalDefault".
+; SVCovergroupTypeGoal = 100
+
+; Enforce the 6.3 behavior of covergroup get_coverage() and get_inst_coverage()
+; builtin functions, and report. This setting changes the default values of
+; option.get_inst_coverage and type_option.merge_instances to ensure the 6.3
+; behavior if explicit assignments are not made on option.get_inst_coverage and
+; type_option.merge_instances by the user. There are two vsim command line
+; options, -cvg63 and -nocvg63 to override this setting from vsim command line.
+; The default value of this variable is 1
+; SVCovergroup63Compatibility = 1
+
+; Enable or disable generation of more detailed information about the sampling
+; of covergroup, cross, and coverpoints. It provides the details of the number
+; of times the covergroup instance and type were sampled, as well as details
+; about why covergroup, cross and coverpoint were not covered. A non-zero value
+; is to enable this feature. 0 is to disable this feature. Default is 0
+; SVCovergroupSampleInfo = 0
+
+; Specify the maximum number of Coverpoint bins in whole design for
+; all Covergroups.
+; MaxSVCoverpointBinsDesign = 2147483648 
+
+; Specify maximum number of Coverpoint bins in any instance of a Covergroup
+; MaxSVCoverpointBinsInst = 2147483648
+
+; Specify the maximum number of Cross bins in whole design for
+; all Covergroups.
+; MaxSVCrossBinsDesign = 2147483648 
+
+; Specify maximum number of Cross bins in any instance of a Covergroup
+; MaxSVCrossBinsInst = 2147483648
+
+; Set weight for all PSL/SVA cover directives.  Default is 1.
+; CoverWeight = 2
+
+; Check vsim plusargs.  Default is 0 (off).
+; 0 = Don't check plusargs
+; 1 = Warning on unrecognized plusarg
+; 2 = Error and exit on unrecognized plusarg
+; CheckPlusargs = 1
+
+; Load the specified shared objects with the RTLD_GLOBAL flag.
+; This gives global visibility to all symbols in the shared objects,
+; meaning that subsequently loaded shared objects can bind to symbols
+; in the global shared objects.  The list of shared objects should
+; be whitespace delimited.  This option is not supported on the
+; Windows or AIX platforms.
+; GlobalSharedObjectList = example1.so example2.so example3.so
+
+; Run the 0in tools from within the simulator. 
+; Default is off.
+; ZeroIn = 1
+
+; Set the options to be passed to the 0in runtime tool.
+; Default value set to "".
+; ZeroInOptions = ""
+
+; Initial seed for the Random Number Generator (RNG) of the root thread (SystemVerilog).
+; Sv_Seed = 0
+
+; Maximum size of dynamic arrays that are resized during randomize().
+; The default is 1000. A value of 0 indicates no limit.
+; SolveArrayResizeMax = 1000
+
+; Error message severity when randomize() failure is detected (SystemVerilog).
+; The default is 0 (no error).
+; 0 = No error  1 = Warning  2 = Error  3 = Failure  4 = Fatal
+; SolveFailSeverity = 0
+
+; Enable/disable debug information for randomize() failures (SystemVerilog).
+; The default is 0 (disabled). Set to 1 to enable.
+; SolveFailDebug = 0
+
+; When SolveFailDebug is enabled, this value specifies the algorithm used to
+; discover conflicts between constraints for randomize() failures.
+; The default is "many".
+;
+; Valid schemes are:
+;    "many" = best for determining conflicts due to many related constraints
+;    "few"  = best for determining conflicts due to few related constraints
+;
+; SolveFailDebugScheme = many
+
+; When SolveFailDebug is enabled and SolveFailDebugScheme is "few", this value
+; specifies the maximum number of constraint subsets that will be tested for
+; conflicts.
+; The default is 0 (no limit).
+; SolveFailDebugLimit = 0
+
+; When SolveFailDebug is enabled and SolveFailDebugScheme is "few", this value
+; specifies the maximum size of constraint subsets that will be tested for
+; conflicts.
+; The default value is 0 (no limit).
+; SolveFailDebugMaxSet = 0
+
+; Maximum size of the solution graph that may be generated during randomize().
+; This value can be used to force randomize() to abort if the memory
+; requirements of the constraint scenario exceeds the specified limit. This
+; value is specified in 1000s of nodes.
+; The default is 10000. A value of 0 indicates no limit.
+; SolveGraphMaxSize = 10000
+
+; Maximum number of evaluations that may be performed on the solution graph
+; generated during randomize(). This value can be used to force randomize() to
+; abort if the complexity of the constraint scenario (in time) exceeds the
+; specified limit. This value is specified in 10000s of evaluations.
+; The default is 10000. A value of 0 indicates no limit.
+; SolveGraphMaxEval = 10000
+
+; Use SolveFlags to specify options that will guide the behavior of the
+; constraint solver. These options may improve the performance of the
+; constraint solver for some testcases, and decrease the performance of
+; the constraint solver for others.
+; The default value is "" (no options).
+;
+; Valid flags are:
+;    i = disable bit interleaving for >, >=, <, <= constraints
+;    n = disable bit interleaving for all constraints
+;    r = reverse bit interleaving
+;
+; SolveFlags =
+
+; Specify random sequence compatiblity with a prior letter release. This 
+; option is used to get the same random sequences during simulation as
+; as a prior letter release. Only prior letter releases (of the current
+; number release) are allowed.
+; Note: To achieve the same random sequences, solver optimizations and/or
+; bug fixes introduced since the specified release may be disabled - 
+; yielding the performance / behavior of the prior release.
+; Default value set to "" (random compatibility not required).
+; SolveRev =
+
+; Environment variable expansion of command line arguments has been depricated 
+; in favor shell level expansion.  Universal environment variable expansion 
+; inside -f files is support and continued support for MGC Location Maps provide
+; alternative methods for handling flexible pathnames.
+; The following line may be uncommented and the value set to 1 to re-enable this 
+; deprecated behavior.  The default value is 0.
+; DeprecatedEnvironmentVariableExpansion = 0
+
+; Turn on/off collapsing of bus ports in VCD dumpports output
+DumpportsCollapse = 1
+
+; Location of Multi-Level Verification Component (MVC) installation. 
+; The default location is the product installation directory.
+; MvcHome = $MODEL_TECH/...
+
+[lmc]
+; The simulator's interface to Logic Modeling's SmartModel SWIFT software
+libsm = $MODEL_TECH/libsm.sl
+; The simulator's interface to Logic Modeling's SmartModel SWIFT software (Windows NT)
+; libsm = $MODEL_TECH/libsm.dll
+;  Logic Modeling's SmartModel SWIFT software (HP 9000 Series 700)
+; libswift = $LMC_HOME/lib/hp700.lib/libswift.sl
+;  Logic Modeling's SmartModel SWIFT software (IBM RISC System/6000)
+; libswift = $LMC_HOME/lib/ibmrs.lib/swift.o
+;  Logic Modeling's SmartModel SWIFT software (Sun4 Solaris)
+; libswift = $LMC_HOME/lib/sun4Solaris.lib/libswift.so
+;  Logic Modeling's SmartModel SWIFT software (Windows NT)
+; libswift = $LMC_HOME/lib/pcnt.lib/libswift.dll
+;  Logic Modeling's SmartModel SWIFT software (non-Enterprise versions of Linux)
+; libswift = $LMC_HOME/lib/x86_linux.lib/libswift.so
+;  Logic Modeling's SmartModel SWIFT software (Enterprise versions of Linux)
+; libswift = $LMC_HOME/lib/linux.lib/libswift.so
+
+; The simulator's interface to Logic Modeling's hardware modeler SFI software
+libhm = $MODEL_TECH/libhm.sl
+; The simulator's interface to Logic Modeling's hardware modeler SFI software (Windows NT)
+; libhm = $MODEL_TECH/libhm.dll
+;  Logic Modeling's hardware modeler SFI software (HP 9000 Series 700)
+; libsfi = <sfi_dir>/lib/hp700/libsfi.sl
+;  Logic Modeling's hardware modeler SFI software (IBM RISC System/6000)
+; libsfi = <sfi_dir>/lib/rs6000/libsfi.a
+;  Logic Modeling's hardware modeler SFI software (Sun4 Solaris)
+; libsfi = <sfi_dir>/lib/sun4.solaris/libsfi.so
+;  Logic Modeling's hardware modeler SFI software (Windows NT)
+; libsfi = <sfi_dir>/lib/pcnt/lm_sfi.dll
+;  Logic Modeling's hardware modeler SFI software (Linux)
+; libsfi = <sfi_dir>/lib/linux/libsfi.so
+
+[msg_system]
+; Change a message severity or suppress a message.
+; The format is: <msg directive> = <msg number>[,<msg number>...]
+; suppress can be used to achieve +nowarn<CODE> functionality
+; The format is: suppress = <CODE>,<msg number>,[<CODE>,<msg number>,...]
+; Examples:
+;   note = 3009
+;   warning = 3033
+;   error = 3010,3016
+;   fatal = 3016,3033
+;   suppress = 3009,3016,3043
+;   suppress = 3009,CNNODP,3043,TFMPC
+; The command verror <msg number> can be used to get the complete
+; description of a message.
+
+; Control transcripting of Verilog display system task messages and
+; PLI/FLI print function call messages.  The system tasks include
+; $display[bho], $strobe[bho], Smonitor{bho], and $write[bho].  They
+; also include the analogous file I/O tasks that write to STDOUT 
+; (i.e. $fwrite or $fdisplay).  The PLI/FLI calls include io_printf,
+; vpi_printf, mti_PrintMessage, and mti_PrintFormatted.  The default
+; is to have messages appear only in the transcript.  The other 
+; settings are to send messages to the wlf file only (messages that
+; are recorded in the wlf file can be viewed in the MsgViewer) or 
+; to both the transcript and the wlf file.  The valid values are
+;    tran  {transcript only (default)}
+;    wlf   {wlf file only}
+;    both  {transcript and wlf file}
+; displaymsgmode = tran
+
+; Control transcripting of elaboration/runtime messages not
+; addressed by the displaymsgmode setting.  The default is to 
+; have messages appear in the transcript and recorded in the wlf
+; file (messages that are recorded in the wlf file can be viewed
+; in the MsgViewer).  The other settings are to send messages 
+; only to the transcript or only to the wlf file.  The valid 
+; values are
+;    both  {default}
+;    tran  {transcript only}
+;    wlf   {wlf file only}
+; msgmode = both
Index: branches/v4/platforms/dsx/v1_1cluster_phys_dma/platform_desc
===================================================================
--- branches/v4/platforms/dsx/v1_1cluster_phys_dma/platform_desc	(revision 371)
+++ branches/v4/platforms/dsx/v1_1cluster_phys_dma/platform_desc	(revision 371)
@@ -0,0 +1,16 @@
+
+#
+## MARKER_BEGIN
+# Auto-generated file, dont modify directly
+# your changes will be lost !
+#
+## Generated by DSX on 2010-05-19 13:32:04.700114
+## by choichil@tchaikovsky
+## MARKER_END
+#
+todo = Platform('', 'main.cpp',
+    [Uses('caba:topcell_')],
+    {},
+'/users/cao/choichil/tsar/trunk/platforms/dsx/v1_1cluster_phys/system.x'
+)
+
Index: branches/v4/platforms/dsx/v1_1cluster_phys_dma/v1_1cluster_phys.py
===================================================================
--- branches/v4/platforms/dsx/v1_1cluster_phys_dma/v1_1cluster_phys.py	(revision 371)
+++ branches/v4/platforms/dsx/v1_1cluster_phys_dma/v1_1cluster_phys.py	(revision 371)
@@ -0,0 +1,107 @@
+#!/usr/bin/env python
+
+import dsx
+import soclib
+import soclib.component
+import os
+
+#import platform_handlers
+
+class Platform:
+    def __init__(self, cluster_ctor, proc_count, binaries):
+        self.pf = soclib.Architecture(cell_size = 4,
+                                      plen_size = 8,
+                                      addr_size = 32,
+                                      rerror_size = 1,
+                                      clen_size = 1,
+                                      rflag_size = 1,
+                                      srcid_size = 14,
+                                      pktid_size = 4,
+                                      trdid_size = 4,
+                                      wrplen_size = 1
+                                      )
+        for name in ['mtp', 'mtc', 'mtx']:
+            mt = self.pf.create('common:mapping_table', name,
+                                addr_size = 40,
+                                addr_bits = [16], srcid_bits = [14],
+                                cacheability_mask = 0x0000300000)
+            # create self.mt[pcx]
+            setattr(self, name, mt)
+
+        # create a dictionary containing
+        # loader = x, loader2 = y, ...
+        bins = {}
+        for i, bin in enumerate(binaries):
+            k = 'binary'
+            if i:
+                k += str(i+1)
+            bins[k] = bin
+        self.loader = self.pf.create('common:loader', 'loader', **bins)
+
+        # self.ringc = self.pf.create(
+        #     'caba:vci_simple_ring_network', 'ringc', 
+        #     mt = mtc,
+        #     ringid = (),
+        #     wrapper_fifo_depth = 2, )
+        # self.ringp = self.pf.create(
+        #     'caba:vci_simple_ring_network', 'ringp', 
+        #     mt = mtp,
+        #     ringid = (),
+        #     wrapper_fifo_depth = 2, )
+        self.ringc = self.pf.create('caba:vci_simple_ring_network', 'ringc', 
+                                    mt = self.mtc,
+                                    ringid = (),
+                                    wrapper_fifo_depth = 2)
+        self.ringp = self.pf.create('caba:vci_simple_ring_network', 'ringp', 
+                                    mt = self.mtp,
+                                    ringid = (),
+                                    wrapper_fifo_depth = 2)
+
+        self.cluster = cluster_ctor(self.pf,
+                                    self.ringp, self.ringc,
+                                    self.mtp, self.mtc, self.mtx,
+                                    proc_count = proc_count,
+                                    cluster_no = 0,
+                                    cluster_base = 0x00000000,
+                                    )
+
+    def simulator(self, outdir = 'hard'):
+        self.pf.generate(soclib.PfDriver(outdir = outdir))
+
+    def device_tree(self):
+        from dsx.contrib.dts_platform.platform_to_dts import PlatformToDts
+        import dsx.contrib.dts_platform.platform_handlers
+        dtsgen = PlatformToDts(self.pf, self.mtp)
+        return dtsgen.create_device_tree()
+
+    def dts(self, output):
+        from dsx.device_tree.dts import Driver
+        dt = self.device_tree()
+        dt.generate(Driver(
+            outdir = '.',
+            parent = None,
+            output_file = output,
+            ),)
+
+    def dtb(self, output):
+        from dsx.device_tree.dtb import Driver
+        dt = self.device_tree()
+        dt.generate(Driver(
+            outdir = '.',
+            parent = None,
+            output_file = output,
+            ),)
+
+def main(cpus):
+    from cluster import ClusterV3
+    hard = Platform(ClusterV3, cpus, binaries = ["bin.soft"])
+    hard.simulator('.')
+    hard.dts(os.path.basename(__file__)[:-2]+'dts')
+    hard.dtb(os.path.basename(__file__)[:-2]+'dtb')
+
+if __name__ == '__main__':
+    import sys
+    cpus = 1
+    if len(sys.argv) > 1:
+        cpus = int(sys.argv[1])
+    main(cpus)
Index: branches/v4/platforms/dsx/v1_1cluster_phys_dma/vsim_stacktrace.vstf
===================================================================
--- branches/v4/platforms/dsx/v1_1cluster_phys_dma/vsim_stacktrace.vstf	(revision 371)
+++ branches/v4/platforms/dsx/v1_1cluster_phys_dma/vsim_stacktrace.vstf	(revision 371)
@@ -0,0 +1,244 @@
+# Current time Tue Sep 14 13:34:15 2010
+# ModelSim Stack Trace
+# Program = vsim
+# Id = "6.5c"
+# Version = "2009.08"
+# Date = "Aug 27 2009"
+# Platform = linux
+# 0    0xb7f27410: '<unknown (@0xb7f27410)>'
+# 1    0x00b556fc: 'abort + 0xfc' in '/lib/libc.so.6'
+# --> START OF USERCODE
+# 2    0xb699526f: '__gnu_cxx::__verbose_terminate_handler() + 0x14f' in '/users/soft/mentor/modelsim-6.5c/modeltech/gcc-4.1.2-linux/lib/libstdc++.so.6'
+# 3    0xb6992c90: '__cxxabiv1::__terminate(void (*)()) + 0x10' in '/users/soft/mentor/modelsim-6.5c/modeltech/gcc-4.1.2-linux/lib/libstdc++.so.6'
+# 4    0xb6991e45: '_cxa_call_terminate + 0x45' in '/users/soft/mentor/modelsim-6.5c/modeltech/gcc-4.1.2-linux/lib/libstdc++.so.6'
+# 5    0xb6992aec: '_gxx_personality_v0 + 0x29c' in '/users/soft/mentor/modelsim-6.5c/modeltech/gcc-4.1.2-linux/lib/libstdc++.so.6'
+# 6    0xb7f151e1: 'Unwind_RaiseException_Phase2 + 0x61' in '/users/soft/mentor/modelsim-6.5c/modeltech/gcc-4.1.2-linux/lib/libgcc_s.so.1'
+# 7    0xb7f15494: 'Unwind_Resume + 0x74' in '/users/soft/mentor/modelsim-6.5c/modeltech/gcc-4.1.2-linux/lib/libgcc_s.so.1'
+# 8    0xb6bdc975: 'sc_core::sc_module::~sc_module() + 0x345' in '/users/cao/choichil/tsar/trunk/platforms/dsx/v1_1cluster_phys_dma/work/_sc/linux_gcc-4.1.2/systemc.so'
+# 9    0xb6b458d9: 'topcell_::topcell_(sc_core::sc_module_name) + 0x3cf9' in '/users/cao/choichil/tsar/trunk/platforms/dsx/v1_1cluster_phys_dma/work/_sc/linux_gcc-4.1.2/systemc.so'
+# 10   0xb6b2946d: 'system_driver::system_driver(sc_core::sc_module_name) + 0x23d' in '/users/cao/choichil/tsar/trunk/platforms/dsx/v1_1cluster_phys_dma/work/_sc/linux_gcc-4.1.2/systemc.so'
+# 11   0xb6b298bc: 'mti__system_driver + 0x4c' in '/users/cao/choichil/tsar/trunk/platforms/dsx/v1_1cluster_phys_dma/work/_sc/linux_gcc-4.1.2/systemc.so'
+# <-- END OF USERCODE
+# 12   0x0830e834: '<unknown (@0x830e834)>'
+# 13   0x0828c97c: '<unknown (@0x828c97c)>'
+# 14   0x0828dac1: '<unknown (@0x828dac1)>'
+# 15   0x084b7bb0: '<unknown (@0x84b7bb0)>'
+# 16   0x086c2ad7: '<unknown (@0x86c2ad7)>'
+# 17   0x086c4289: '<unknown (@0x86c4289)>'
+# 18   0x086e9bbb: '<unknown (@0x86e9bbb)>'
+# 19   0x086eeca3: '<unknown (@0x86eeca3)>'
+# 20   0x086c621c: '<unknown (@0x86c621c)>'
+# 21   0x086c92cd: '<unknown (@0x86c92cd)>'
+# 22   0x086c4289: '<unknown (@0x86c4289)>'
+# 23   0x086e9bbb: '<unknown (@0x86e9bbb)>'
+# 24   0x086eef03: '<unknown (@0x86eef03)>'
+# 25   0x086c499c: '<unknown (@0x86c499c)>'
+# 26   0x086cc09d: '<unknown (@0x86cc09d)>'
+# 27   0x086c4289: '<unknown (@0x86c4289)>'
+# 28   0x086c571d: '<unknown (@0x86c571d)>'
+# 29   0x086c5b60: '<unknown (@0x86c5b60)>'
+# 30   0x086c654a: '<unknown (@0x86c654a)>'
+# 31   0x08597b1a: '<unknown (@0x8597b1a)>'
+# 32   0x086fc8bb: '<unknown (@0x86fc8bb)>'
+# 33   0x0872b3ee: '<unknown (@0x872b3ee)>'
+# 34   0x0870bd20: '<unknown (@0x870bd20)>'
+# 35   0x0870c01e: '<unknown (@0x870c01e)>'
+# 36   0x08683820: '<unknown (@0x8683820)>'
+# 37   0x08361250: '<unknown (@0x8361250)>'
+# 38   0x082c507a: '<unknown (@0x82c507a)>'
+# 39   0x0805d329: '<unknown (@0x805d329)>'
+# End of Stack Trace
+
+
+# Current time Tue Sep 14 13:34:15 2010
+# ModelSim Stack Trace
+# Program = vsim
+# Id = "6.5c"
+# Version = "2009.08"
+# Date = "Aug 27 2009"
+# Platform = linux
+# 0    0x00000000: '<unknown (@0x0)>'
+# --> START OF USERCODE
+# 1    0xb6bdf8ce: 'sc_core::sc_module_registry::simulation_done() + 0x5e' in '/users/cao/choichil/tsar/trunk/platforms/dsx/v1_1cluster_phys_dma/work/_sc/linux_gcc-4.1.2/systemc.so'
+# 2    0xb6be7fd5: 'sc_core::sc_simcontext::end() + 0x45' in '/users/cao/choichil/tsar/trunk/platforms/dsx/v1_1cluster_phys_dma/work/_sc/linux_gcc-4.1.2/systemc.so'
+# 3    0xb6b7157b: 'sc_core::scmti_call_end_of_simulation() + 0x2b' in '/users/cao/choichil/tsar/trunk/platforms/dsx/v1_1cluster_phys_dma/work/_sc/linux_gcc-4.1.2/systemc.so'
+# <-- END OF USERCODE
+# 4    0x0830b206: '<unknown (@0x830b206)>'
+# 5    0x082c33fe: '<unknown (@0x82c33fe)>'
+# 6    0x082c3628: '<unknown (@0x82c3628)>'
+# 7    0x00b56da4: 'exit + 0xe4' in '/lib/libc.so.6'
+# 8    0x082c1eea: '<unknown (@0x82c1eea)>'
+# 9    0x082c1ffa: '<unknown (@0x82c1ffa)>'
+# 10   0xb7f2743b: '<unknown (@0xb7f2743b)>'
+# 11   0x00b556fc: 'abort + 0xfc' in '/lib/libc.so.6'
+# --> START OF USERCODE
+# 12   0xb699526f: '__gnu_cxx::__verbose_terminate_handler() + 0x14f' in '/users/soft/mentor/modelsim-6.5c/modeltech/gcc-4.1.2-linux/lib/libstdc++.so.6'
+# 13   0xb6992c90: '__cxxabiv1::__terminate(void (*)()) + 0x10' in '/users/soft/mentor/modelsim-6.5c/modeltech/gcc-4.1.2-linux/lib/libstdc++.so.6'
+# 14   0xb6991e45: '_cxa_call_terminate + 0x45' in '/users/soft/mentor/modelsim-6.5c/modeltech/gcc-4.1.2-linux/lib/libstdc++.so.6'
+# 15   0xb6992aec: '_gxx_personality_v0 + 0x29c' in '/users/soft/mentor/modelsim-6.5c/modeltech/gcc-4.1.2-linux/lib/libstdc++.so.6'
+# 16   0xb7f151e1: 'Unwind_RaiseException_Phase2 + 0x61' in '/users/soft/mentor/modelsim-6.5c/modeltech/gcc-4.1.2-linux/lib/libgcc_s.so.1'
+# 17   0xb7f15494: 'Unwind_Resume + 0x74' in '/users/soft/mentor/modelsim-6.5c/modeltech/gcc-4.1.2-linux/lib/libgcc_s.so.1'
+# 18   0xb6bdc975: 'sc_core::sc_module::~sc_module() + 0x345' in '/users/cao/choichil/tsar/trunk/platforms/dsx/v1_1cluster_phys_dma/work/_sc/linux_gcc-4.1.2/systemc.so'
+# 19   0xb6b458d9: 'topcell_::topcell_(sc_core::sc_module_name) + 0x3cf9' in '/users/cao/choichil/tsar/trunk/platforms/dsx/v1_1cluster_phys_dma/work/_sc/linux_gcc-4.1.2/systemc.so'
+# 20   0xb6b2946d: 'system_driver::system_driver(sc_core::sc_module_name) + 0x23d' in '/users/cao/choichil/tsar/trunk/platforms/dsx/v1_1cluster_phys_dma/work/_sc/linux_gcc-4.1.2/systemc.so'
+# 21   0xb6b298bc: 'mti__system_driver + 0x4c' in '/users/cao/choichil/tsar/trunk/platforms/dsx/v1_1cluster_phys_dma/work/_sc/linux_gcc-4.1.2/systemc.so'
+# <-- END OF USERCODE
+# 22   0x0830e834: '<unknown (@0x830e834)>'
+# 23   0x0828c97c: '<unknown (@0x828c97c)>'
+# 24   0x0828dac1: '<unknown (@0x828dac1)>'
+# 25   0x084b7bb0: '<unknown (@0x84b7bb0)>'
+# 26   0x086c2ad7: '<unknown (@0x86c2ad7)>'
+# 27   0x086c4289: '<unknown (@0x86c4289)>'
+# 28   0x086e9bbb: '<unknown (@0x86e9bbb)>'
+# 29   0x086eeca3: '<unknown (@0x86eeca3)>'
+# 30   0x086c621c: '<unknown (@0x86c621c)>'
+# 31   0x086c92cd: '<unknown (@0x86c92cd)>'
+# 32   0x086c4289: '<unknown (@0x86c4289)>'
+# 33   0x086e9bbb: '<unknown (@0x86e9bbb)>'
+# 34   0x086eef03: '<unknown (@0x86eef03)>'
+# 35   0x086c499c: '<unknown (@0x86c499c)>'
+# 36   0x086cc09d: '<unknown (@0x86cc09d)>'
+# 37   0x086c4289: '<unknown (@0x86c4289)>'
+# 38   0x086c571d: '<unknown (@0x86c571d)>'
+# 39   0x086c5b60: '<unknown (@0x86c5b60)>'
+# 40   0x086c654a: '<unknown (@0x86c654a)>'
+# 41   0x08597b1a: '<unknown (@0x8597b1a)>'
+# 42   0x086fc8bb: '<unknown (@0x86fc8bb)>'
+# 43   0x0872b3ee: '<unknown (@0x872b3ee)>'
+# 44   0x0870bd20: '<unknown (@0x870bd20)>'
+# 45   0x0870c01e: '<unknown (@0x870c01e)>'
+# 46   0x08683820: '<unknown (@0x8683820)>'
+# 47   0x08361250: '<unknown (@0x8361250)>'
+# 48   0x082c507a: '<unknown (@0x82c507a)>'
+# 49   0x0805d329: '<unknown (@0x805d329)>'
+# End of Stack Trace
+
+
+# Current time Tue Sep 14 13:34:15 2010
+# ModelSim Stack Trace
+# Program = vsim
+# Id = "6.5c"
+# Version = "2009.08"
+# Date = "Aug 27 2009"
+# Platform = linux
+# 0    0x00000000: '<unknown (@0x0)>'
+# --> START OF USERCODE
+# 1    0xb6bdf8ce: 'sc_core::sc_module_registry::simulation_done() + 0x5e' in '/users/cao/choichil/tsar/trunk/platforms/dsx/v1_1cluster_phys_dma/work/_sc/linux_gcc-4.1.2/systemc.so'
+# 2    0xb6be7fd5: 'sc_core::sc_simcontext::end() + 0x45' in '/users/cao/choichil/tsar/trunk/platforms/dsx/v1_1cluster_phys_dma/work/_sc/linux_gcc-4.1.2/systemc.so'
+# 3    0xb6b7157b: 'sc_core::scmti_call_end_of_simulation() + 0x2b' in '/users/cao/choichil/tsar/trunk/platforms/dsx/v1_1cluster_phys_dma/work/_sc/linux_gcc-4.1.2/systemc.so'
+# <-- END OF USERCODE
+# 4    0x0830b206: '<unknown (@0x830b206)>'
+# 5    0x082c33fe: '<unknown (@0x82c33fe)>'
+# 6    0x082c3628: '<unknown (@0x82c3628)>'
+# 7    0x00b56da4: 'exit + 0xe4' in '/lib/libc.so.6'
+# 8    0x082c1eea: '<unknown (@0x82c1eea)>'
+# 9    0x082c1ffa: '<unknown (@0x82c1ffa)>'
+# 10   0xb7f2743b: '<unknown (@0xb7f2743b)>'
+# 11   0x00b556fc: 'abort + 0xfc' in '/lib/libc.so.6'
+# --> START OF USERCODE
+# 12   0xb699526f: '__gnu_cxx::__verbose_terminate_handler() + 0x14f' in '/users/soft/mentor/modelsim-6.5c/modeltech/gcc-4.1.2-linux/lib/libstdc++.so.6'
+# 13   0xb6992c90: '__cxxabiv1::__terminate(void (*)()) + 0x10' in '/users/soft/mentor/modelsim-6.5c/modeltech/gcc-4.1.2-linux/lib/libstdc++.so.6'
+# 14   0xb6991e45: '_cxa_call_terminate + 0x45' in '/users/soft/mentor/modelsim-6.5c/modeltech/gcc-4.1.2-linux/lib/libstdc++.so.6'
+# 15   0xb6992aec: '_gxx_personality_v0 + 0x29c' in '/users/soft/mentor/modelsim-6.5c/modeltech/gcc-4.1.2-linux/lib/libstdc++.so.6'
+# 16   0xb7f151e1: 'Unwind_RaiseException_Phase2 + 0x61' in '/users/soft/mentor/modelsim-6.5c/modeltech/gcc-4.1.2-linux/lib/libgcc_s.so.1'
+# 17   0xb7f15494: 'Unwind_Resume + 0x74' in '/users/soft/mentor/modelsim-6.5c/modeltech/gcc-4.1.2-linux/lib/libgcc_s.so.1'
+# 18   0xb6bdc975: 'sc_core::sc_module::~sc_module() + 0x345' in '/users/cao/choichil/tsar/trunk/platforms/dsx/v1_1cluster_phys_dma/work/_sc/linux_gcc-4.1.2/systemc.so'
+# 19   0xb6b458d9: 'topcell_::topcell_(sc_core::sc_module_name) + 0x3cf9' in '/users/cao/choichil/tsar/trunk/platforms/dsx/v1_1cluster_phys_dma/work/_sc/linux_gcc-4.1.2/systemc.so'
+# 20   0xb6b2946d: 'system_driver::system_driver(sc_core::sc_module_name) + 0x23d' in '/users/cao/choichil/tsar/trunk/platforms/dsx/v1_1cluster_phys_dma/work/_sc/linux_gcc-4.1.2/systemc.so'
+# 21   0xb6b298bc: 'mti__system_driver + 0x4c' in '/users/cao/choichil/tsar/trunk/platforms/dsx/v1_1cluster_phys_dma/work/_sc/linux_gcc-4.1.2/systemc.so'
+# <-- END OF USERCODE
+# 22   0x0830e834: '<unknown (@0x830e834)>'
+# 23   0x0828c97c: '<unknown (@0x828c97c)>'
+# 24   0x0828dac1: '<unknown (@0x828dac1)>'
+# 25   0x084b7bb0: '<unknown (@0x84b7bb0)>'
+# 26   0x086c2ad7: '<unknown (@0x86c2ad7)>'
+# 27   0x086c4289: '<unknown (@0x86c4289)>'
+# 28   0x086e9bbb: '<unknown (@0x86e9bbb)>'
+# 29   0x086eeca3: '<unknown (@0x86eeca3)>'
+# 30   0x086c621c: '<unknown (@0x86c621c)>'
+# 31   0x086c92cd: '<unknown (@0x86c92cd)>'
+# 32   0x086c4289: '<unknown (@0x86c4289)>'
+# 33   0x086e9bbb: '<unknown (@0x86e9bbb)>'
+# 34   0x086eef03: '<unknown (@0x86eef03)>'
+# 35   0x086c499c: '<unknown (@0x86c499c)>'
+# 36   0x086cc09d: '<unknown (@0x86cc09d)>'
+# 37   0x086c4289: '<unknown (@0x86c4289)>'
+# 38   0x086c571d: '<unknown (@0x86c571d)>'
+# 39   0x086c5b60: '<unknown (@0x86c5b60)>'
+# 40   0x086c654a: '<unknown (@0x86c654a)>'
+# 41   0x08597b1a: '<unknown (@0x8597b1a)>'
+# 42   0x086fc8bb: '<unknown (@0x86fc8bb)>'
+# 43   0x0872b3ee: '<unknown (@0x872b3ee)>'
+# 44   0x0870bd20: '<unknown (@0x870bd20)>'
+# 45   0x0870c01e: '<unknown (@0x870c01e)>'
+# 46   0x08683820: '<unknown (@0x8683820)>'
+# 47   0x08361250: '<unknown (@0x8361250)>'
+# 48   0x082c507a: '<unknown (@0x82c507a)>'
+# 49   0x0805d329: '<unknown (@0x805d329)>'
+# End of Stack Trace
+
+
+# Current time Tue Sep 14 13:34:16 2010
+# ModelSim Stack Trace
+# Program = vsim
+# Id = "6.5c"
+# Version = "2009.08"
+# Date = "Aug 27 2009"
+# Platform = linux
+# 0    0x00000000: '<unknown (@0x0)>'
+# --> START OF USERCODE
+# 1    0xb6bdf8ce: 'sc_core::sc_module_registry::simulation_done() + 0x5e' in '/users/cao/choichil/tsar/trunk/platforms/dsx/v1_1cluster_phys_dma/work/_sc/linux_gcc-4.1.2/systemc.so'
+# 2    0xb6be7fd5: 'sc_core::sc_simcontext::end() + 0x45' in '/users/cao/choichil/tsar/trunk/platforms/dsx/v1_1cluster_phys_dma/work/_sc/linux_gcc-4.1.2/systemc.so'
+# 3    0xb6b7157b: 'sc_core::scmti_call_end_of_simulation() + 0x2b' in '/users/cao/choichil/tsar/trunk/platforms/dsx/v1_1cluster_phys_dma/work/_sc/linux_gcc-4.1.2/systemc.so'
+# <-- END OF USERCODE
+# 4    0x0830b206: '<unknown (@0x830b206)>'
+# 5    0x082c33fe: '<unknown (@0x82c33fe)>'
+# 6    0x082c3628: '<unknown (@0x82c3628)>'
+# 7    0x00b56da4: 'exit + 0xe4' in '/lib/libc.so.6'
+# 8    0x082c1eea: '<unknown (@0x82c1eea)>'
+# 9    0x082c1ffa: '<unknown (@0x82c1ffa)>'
+# 10   0xb7f2743b: '<unknown (@0xb7f2743b)>'
+# 11   0x00b556fc: 'abort + 0xfc' in '/lib/libc.so.6'
+# --> START OF USERCODE
+# 12   0xb699526f: '__gnu_cxx::__verbose_terminate_handler() + 0x14f' in '/users/soft/mentor/modelsim-6.5c/modeltech/gcc-4.1.2-linux/lib/libstdc++.so.6'
+# 13   0xb6992c90: '__cxxabiv1::__terminate(void (*)()) + 0x10' in '/users/soft/mentor/modelsim-6.5c/modeltech/gcc-4.1.2-linux/lib/libstdc++.so.6'
+# 14   0xb6991e45: '_cxa_call_terminate + 0x45' in '/users/soft/mentor/modelsim-6.5c/modeltech/gcc-4.1.2-linux/lib/libstdc++.so.6'
+# 15   0xb6992aec: '_gxx_personality_v0 + 0x29c' in '/users/soft/mentor/modelsim-6.5c/modeltech/gcc-4.1.2-linux/lib/libstdc++.so.6'
+# 16   0xb7f151e1: 'Unwind_RaiseException_Phase2 + 0x61' in '/users/soft/mentor/modelsim-6.5c/modeltech/gcc-4.1.2-linux/lib/libgcc_s.so.1'
+# 17   0xb7f15494: 'Unwind_Resume + 0x74' in '/users/soft/mentor/modelsim-6.5c/modeltech/gcc-4.1.2-linux/lib/libgcc_s.so.1'
+# 18   0xb6bdc975: 'sc_core::sc_module::~sc_module() + 0x345' in '/users/cao/choichil/tsar/trunk/platforms/dsx/v1_1cluster_phys_dma/work/_sc/linux_gcc-4.1.2/systemc.so'
+# 19   0xb6b458d9: 'topcell_::topcell_(sc_core::sc_module_name) + 0x3cf9' in '/users/cao/choichil/tsar/trunk/platforms/dsx/v1_1cluster_phys_dma/work/_sc/linux_gcc-4.1.2/systemc.so'
+# 20   0xb6b2946d: 'system_driver::system_driver(sc_core::sc_module_name) + 0x23d' in '/users/cao/choichil/tsar/trunk/platforms/dsx/v1_1cluster_phys_dma/work/_sc/linux_gcc-4.1.2/systemc.so'
+# 21   0xb6b298bc: 'mti__system_driver + 0x4c' in '/users/cao/choichil/tsar/trunk/platforms/dsx/v1_1cluster_phys_dma/work/_sc/linux_gcc-4.1.2/systemc.so'
+# <-- END OF USERCODE
+# 22   0x0830e834: '<unknown (@0x830e834)>'
+# 23   0x0828c97c: '<unknown (@0x828c97c)>'
+# 24   0x0828dac1: '<unknown (@0x828dac1)>'
+# 25   0x084b7bb0: '<unknown (@0x84b7bb0)>'
+# 26   0x086c2ad7: '<unknown (@0x86c2ad7)>'
+# 27   0x086c4289: '<unknown (@0x86c4289)>'
+# 28   0x086e9bbb: '<unknown (@0x86e9bbb)>'
+# 29   0x086eeca3: '<unknown (@0x86eeca3)>'
+# 30   0x086c621c: '<unknown (@0x86c621c)>'
+# 31   0x086c92cd: '<unknown (@0x86c92cd)>'
+# 32   0x086c4289: '<unknown (@0x86c4289)>'
+# 33   0x086e9bbb: '<unknown (@0x86e9bbb)>'
+# 34   0x086eef03: '<unknown (@0x86eef03)>'
+# 35   0x086c499c: '<unknown (@0x86c499c)>'
+# 36   0x086cc09d: '<unknown (@0x86cc09d)>'
+# 37   0x086c4289: '<unknown (@0x86c4289)>'
+# 38   0x086c571d: '<unknown (@0x86c571d)>'
+# 39   0x086c5b60: '<unknown (@0x86c5b60)>'
+# 40   0x086c654a: '<unknown (@0x86c654a)>'
+# 41   0x08597b1a: '<unknown (@0x8597b1a)>'
+# 42   0x086fc8bb: '<unknown (@0x86fc8bb)>'
+# 43   0x0872b3ee: '<unknown (@0x872b3ee)>'
+# 44   0x0870bd20: '<unknown (@0x870bd20)>'
+# 45   0x0870c01e: '<unknown (@0x870c01e)>'
+# 46   0x08683820: '<unknown (@0x8683820)>'
+# 47   0x08361250: '<unknown (@0x8361250)>'
+# 48   0x082c507a: '<unknown (@0x82c507a)>'
+# 49   0x0805d329: '<unknown (@0x805d329)>'
+# End of Stack Trace
+
+
Index: branches/v4/platforms/dsx/v3_1cluster_virt/cluster.py
===================================================================
--- branches/v4/platforms/dsx/v3_1cluster_virt/cluster.py	(revision 371)
+++ branches/v4/platforms/dsx/v3_1cluster_virt/cluster.py	(revision 371)
@@ -0,0 +1,163 @@
+
+__doc__ = '''
+This file is a Cluster library. It contains classes implementing the
+netlist of a cluster, for different tsar versions.
+'''
+
+class Cluster:
+    '''
+    A generic netlist of a cluster, which must be subclassed to
+    implement caches&dma instanciation
+    '''
+    
+    def __init__(self, pf, ringp, ringc, mtp, mtc, mtx, proc_count, cluster_no, cluster_base):
+        self.pf = pf
+        self.ringp = ringp
+        self.ringc = ringc
+        self.mtp = mtp
+        self.mtc = mtc
+        self.mtx = mtx
+        self.cluster_no = cluster_no
+
+        self.generate(proc_count, cluster_base)
+
+    def generate(self, proc_count, cluster_base):
+        '''
+        The core netlist, where caches and components are created
+        '''
+        self.cpu = []
+        for i in range(proc_count):
+            c = self.create_cpu(i,
+                                cluster_base
+                                + 0x10200000
+                                + 0x01000000 * (i+1)
+                                )
+            self.cpu.append(c)
+
+        memc, xram = self.create_memcache( segments = [(cluster_base, 0x02000000)] )
+        rom  = self.create_rom( segments = [(0xbfc00000, 0x00400000)], memc = memc )
+        tty  = self.create_tty( addr = 0xd0200000 )
+        dma  = self.create_dma( addr = 0xd1200000 )
+        xicu = self.create_xicu( addr = 0xd2200000, hwi_count = 3, cpu_count = proc_count )
+
+        xicu.hwi[0] // tty.irq[0]
+        xicu.hwi[1] // dma.irq
+
+        for p, cpu in enumerate(self.cpu):
+            for i in range(6):
+                xicu.irq[i+p*6] // cpu.irq[i]
+
+    def create_rom(self, segments, memc):
+        name = 'rom%d'%self.cluster_no
+        rom = self.pf.create('caba:vci_simple_ram', name, latency = 1)
+        self.ringp.to_target.new() // rom.vci
+        for addr, size in segments:
+            rom.addSegment(name, address = addr, size = size, cacheable = True)
+        return rom
+
+    def create_tty(self, addr):
+        name = 'tty%d'%self.cluster_no
+        tty = self.pf.create('caba:vci_multi_tty', name, names = ['tty0'])
+        self.ringp.to_target.new() // tty.vci
+        tty.addSegment(name, address = addr, size = 0x10, cacheable = False)
+        return tty
+
+    def create_xicu(self, addr, hwi_count, cpu_count):
+        name = 'xicu%d'%self.cluster_no
+        xicu = self.pf.create('caba:vci_xicu', name,
+                              pti_count = cpu_count,
+                              hwi_count = hwi_count,
+                              wti_count = cpu_count,
+                              irq_count = 6*cpu_count,
+                              )
+        self.ringp.to_target.new() // xicu.vci
+        xicu.addSegment(name, address = addr, size = 0x1000, cacheable = False)
+        return xicu
+    
+
+class ClusterV3(Cluster):
+    '''
+    A TsarV3 implementation, using vci_cc_vcache_wrapper2_v1,
+    vci_mem_cache_v3 and vci_dma_tsar_v2.
+    '''
+    
+    def create_rom(self, segments, memc):
+        # Here is a hack needed for TsarV3:
+        #
+        # memcache must have segments corresponding to the rom in
+        # order to handle cleanup messages emitted by the L1 caches on
+        # the coherency network (else, they could be routed to wrong
+        # places)
+        name = 'rom%d'%self.cluster_no
+        for addr, size in segments:
+            memc.addSegment(name+'_c', address = addr, size = size, cacheable = True, mt = self.mtc)
+        return Cluster.create_rom(self, segments, memc)
+
+    def create_cpu(self, cpuid, addr):
+            c = self.pf.create(
+                'caba:vci_cc_vcache_wrapper2_v1',
+                'proc_%d_%d' % (self.cluster_no, cpuid),
+                iss_t = "common:mips32el",
+                proc_id = cpuid,
+                icache_ways = 4,
+                icache_sets = 64,
+                icache_words = 16,
+                itlb_ways = 4,
+                itlb_sets = 16,
+                dcache_ways = 4,
+                dcache_sets = 64,
+                dcache_words = 16,
+                dtlb_ways = 4,
+                dtlb_sets = 16,
+                write_buf_size = 16,
+                )
+            self.ringc.to_initiator.new() // c.vci_ini_c
+            self.ringc.to_target.new() // c.vci_tgt
+            self.ringp.to_initiator.new() // c.vci_ini_rw
+
+            c.addSegment('proc_%d_%d' % (self.cluster_no, cpuid),
+                         address = addr,
+                         size = 0x10,
+                         cacheable = False,
+                         )
+
+            return c
+
+    def create_memcache(self, segments):
+        memc = self.pf.create('caba:vci_mem_cache_v3', 'memc',
+                              mtx = self.mtx,
+                              vci_ixr_index = (self.cluster_no,),
+                              nways = 16,
+                              nsets = 256,
+                              nwords = 16,
+                              heap_size = 1024
+                              )
+        self.ringc.to_target.new() // memc.vci_tgt_cleanup
+        self.ringp.to_target.new() // memc.vci_tgt
+        self.ringc.to_initiator.new() // memc.vci_ini
+
+        xram = self.pf.create('caba:vci_simple_ram', 'xram',
+                              mt = self.mtx,
+                              ident = (self.cluster_no,),
+                              latency = 1,
+                 )
+        memc.vci_ixr // xram.vci
+
+        for addr, size in segments:
+            # Here DSX knows the only way to address xram is through its
+            # vci port. It also knows the only associated mapping_table.
+            xram.addSegment('ram_x', address = addr, size = size, cacheable = True)
+
+            # For these segments, there is ambiguity for the mapping_table
+            # we are talking about, so we specify mt = ...
+            memc.addSegment('ram_p', address = addr, size = size, cacheable = True, mt = self.mtp)
+            memc.addSegment('ram_c', address = addr, size = size, cacheable = True, mt = self.mtc)
+        return memc, xram
+
+    def create_dma(self, addr):
+        name = 'dma%d'%self.cluster_no
+        dma = self.pf.create('caba:vci_dma_tsar_v2', name, burst_size = 64)
+        self.ringp.to_target.new() // dma.vci_target
+        self.ringp.to_initiator.new() // dma.vci_initiator
+        dma.addSegment(name, address = addr, size = 0x14, cacheable = False)
+        return dma
Index: branches/v4/platforms/dsx/v3_1cluster_virt/v3_1cluster_virt.py
===================================================================
--- branches/v4/platforms/dsx/v3_1cluster_virt/v3_1cluster_virt.py	(revision 371)
+++ branches/v4/platforms/dsx/v3_1cluster_virt/v3_1cluster_virt.py	(revision 371)
@@ -0,0 +1,104 @@
+#!/usr/bin/env python
+
+import dsx
+import soclib
+import soclib.component
+import os
+
+class Platform:
+    def __init__(self, cluster_ctor, proc_count, binaries):
+        self.pf = soclib.Architecture(cell_size = 4,
+                                      plen_size = 8,
+                                      addr_size = 32,
+                                      rerror_size = 1,
+                                      clen_size = 1,
+                                      rflag_size = 1,
+                                      srcid_size = 14,
+                                      pktid_size = 4,
+                                      trdid_size = 4,
+                                      wrplen_size = 1
+                                      )
+        for name in ['mtp', 'mtc', 'mtx']:
+            mt = self.pf.create('common:mapping_table', name,
+                                addr_bits = [8], srcid_bits = [14],
+                                cacheability_mask = 0x00F0000000)
+            # create self.mt[pcx]
+            setattr(self, name, mt)
+
+        # create a dictionary containing
+        # loader = x, loader2 = y, ...
+        bins = {}
+        for i, bin in enumerate(binaries):
+            k = 'binary'
+            if i:
+                k += str(i+1)
+            bins[k] = bin
+        self.loader = self.pf.create('common:loader', 'loader', **bins)
+
+        # self.ringc = self.pf.create(
+        #     'caba:vci_simple_ring_network', 'ringc', 
+        #     mt = mtc,
+        #     ringid = (),
+        #     wrapper_fifo_depth = 2, )
+        # self.ringp = self.pf.create(
+        #     'caba:vci_simple_ring_network', 'ringp', 
+        #     mt = mtp,
+        #     ringid = (),
+        #     wrapper_fifo_depth = 2, )
+        self.ringc = self.pf.create('caba:vci_vgmn', 'ringc', 
+                       mt = self.mtc,
+                       min_latency = 1,
+                       fifo_depth = 8, )
+        self.ringp = self.pf.create('caba:vci_vgmn', 'ringp', 
+                       mt = self.mtp,
+                       min_latency = 1,
+                       fifo_depth = 8, )
+
+        self.cluster = cluster_ctor(self.pf,
+                                    self.ringp, self.ringc,
+                                    self.mtp, self.mtc, self.mtx,
+                                    proc_count = proc_count,
+                                    cluster_no = 0,
+                                    cluster_base = 0x00000000,
+                                    )
+
+    def simulator(self):
+        self.pf.generate(soclib.PfDriver())
+
+    def device_tree(self):
+        from dsx.contrib.dts_platform.platform_to_dts import PlatformToDts
+        import dsx.contrib.dts_platform.platform_handlers
+        dtsgen = PlatformToDts(self.pf, self.mtp)
+        return dtsgen.create_device_tree()
+
+    def dts(self, output):
+        from dsx.device_tree.dts import Driver
+        dt = self.device_tree()
+        dt.generate(Driver(
+            outdir = '.',
+            parent = None,
+            output_file = output,
+            ),)
+
+    def dtb(self, output):
+        from dsx.device_tree.dtb import Driver
+        dt = self.device_tree()
+        dt.generate(Driver(
+            outdir = '.',
+            parent = None,
+            output_file = output,
+            ),)
+
+def main(cpus):
+    from cluster import ClusterV3
+    hard = Platform(ClusterV3, cpus, binaries = ["boot.bin", "kernel@0x00a00000:D"])
+    hard.simulator()
+    hard.dts(os.path.basename(__file__)[:-2]+'dts')
+    hard.dtb(os.path.basename(__file__)[:-2]+'dtb')
+
+if __name__ == '__main__':
+    import sys
+    cpus = 1
+    if len(sys.argv) > 1:
+        cpus = int(sys.argv[1])
+    main(cpus)
Index: branches/v4/platforms/fpga_3_tsar_v1/Makefile
===================================================================
--- branches/v4/platforms/fpga_3_tsar_v1/Makefile	(revision 371)
+++ branches/v4/platforms/fpga_3_tsar_v1/Makefile	(revision 371)
@@ -0,0 +1,7 @@
+ARCH=mips32el
+SIMULATION_ARGS=100000
+SOCLIB?=$(shell soclib-cc --getpath)
+NO_SOFT=1
+#SOCLIB_CC_ADD_ARGS= -t systemcass
+export SOCLIB
+include $(SOCLIB)/soclib/platform/topcells/all.mk
Index: branches/v4/platforms/fpga_3_tsar_v1/platform_desc
===================================================================
--- branches/v4/platforms/fpga_3_tsar_v1/platform_desc	(revision 371)
+++ branches/v4/platforms/fpga_3_tsar_v1/platform_desc	(revision 371)
@@ -0,0 +1,30 @@
+
+# -*- python -*-
+
+
+todo = Platform('caba', 'top.cpp',
+				uses = [
+	Uses('caba:vci_cc_xcache_wrapper_v1', iss_t = 'common:gdb_iss', gdb_iss_t = 'common:mips32el'),
+	Uses('caba:vci_cc_xcache_wrapper_v1', iss_t = 'common:iss_memchecker', iss_memchecker_t = 'common:mips32el'),
+	Uses('caba:vci_cc_xcache_wrapper_v1', iss_t = 'common:gdb_iss', gdb_iss_t = 'common:iss_memchecker', iss_memchecker_t = 'common:mips32el'),
+	Uses('caba:vci_simple_ram'),
+  Uses('caba:vci_logger'),
+	Uses('caba:vci_multi_tty'),
+	Uses('caba:vci_vgmn'),
+	Uses('caba:vci_simple_ring_fast',
+		ring_cmd_data_size = 40,
+		ring_rsp_data_size = 33),
+	Uses('caba:vci_mem_cache_v2'),
+	Uses('common:elf_file_loader'),
+	],
+	cell_size = 4,
+	plen_size = 8,
+	addr_size = 32,
+	rerror_size = 1,
+	clen_size = 1,
+	rflag_size = 1,
+	srcid_size = 8,
+	pktid_size = 4,
+	trdid_size = 4,
+	wrplen_size = 1
+)
Index: branches/v4/platforms/fpga_3_tsar_v1/segmentation.h
===================================================================
--- branches/v4/platforms/fpga_3_tsar_v1/segmentation.h	(revision 371)
+++ branches/v4/platforms/fpga_3_tsar_v1/segmentation.h	(revision 371)
@@ -0,0 +1,85 @@
+
+/////////////////////////////////////////////////////////////////
+//	ADDRESS SPACE SEGMENTATION
+//
+//	This file must be included in the system.cpp file, 
+//	for harware configuration : It is used to build
+//	the SOCLIB_SEGMENT_TABLE.
+//
+//	This file can also be used by the ldscript generator,
+//	for embedded software generation.
+//	
+//	It gives the system integrator the garanty
+//	that hardware and software have the same
+//	description of the address space segmentation.
+/////////////////////////////////////////////////////////////////
+
+/////////////////////////////////////////////////////////////////
+//	reset, and exception segments
+//      base address required by MIPS processor
+/////////////////////////////////////////////////////////////////
+#define MMU
+
+#define	RESET_BASE	0xBFC00000
+#define	RESET_SIZE	0x00010000
+
+#define	EXCEP_BASE	0x80000080
+#define	EXCEP_SIZE	0x00000080
+
+#define	TEXT_BASE	0x00400000
+#define	TEXT_SIZE	0x00001F80
+
+#define DATA_BASE	0xBE000000
+#define DATA_SIZE	0x00001F80
+/////////////////////////////////////////////////////////////////
+//	global data segment (initialised)
+/////////////////////////////////////////////////////////////////
+
+#define MC_M_BASE	0xC0000000
+#define MC_M_SIZE	0x3FFFFFFC
+
+/////////////////////////////////////////////////////////////////
+//	page table (initialised)
+/////////////////////////////////////////////////////////////////
+#define PTD_ADDR	0x40400000
+#define PTE_ADDR	0x40402000
+#define IPTE_ADDR	0x40403000
+#define	TAB_SIZE	0x00010000
+
+#define V_TTY_BASE 	0x00800000
+#define	V_TIMER_BASE	0x00C00000	// timer virtual address
+//////////////////////////////////////////////////////////
+//	System devices
+///////////////////////////////////////////////////////////
+
+#define	TTY_BASE	0x10200000
+#define	TTY_SIZE	0x00000040
+
+#define	TIMER_BASE	0xD0200000
+#define	TIMER_SIZE	0x00000100
+
+#define	LOCKS_BASE	0xE0200000
+#define	LOCKS_SIZE	0x00000100
+
+#define C_PROC0_BASE	0x01200000
+#define C_PROC0_SIZE	0x00000010
+
+#define C_PROC1_BASE	0x02200000
+#define C_PROC1_SIZE	0x00000010
+
+#define C_PROC2_BASE	0x03200000
+#define C_PROC2_SIZE	0x00000010
+
+#define C_PROC3_BASE	0x04200000
+#define C_PROC3_SIZE	0x00000010
+
+#define C_MC_M_BASE	0x00200000
+#define C_MC_M_SIZE	0x00000008
+
+#define XRAM_BASE	0xB0200000
+#define XRAM_SIZE	0x00000008
+
+#define MC_R_BASE	0x20200000
+#define MC_R_SIZE	0x00000008
+
+#define CLEANUP_OFFSET  0x20200000
Index: branches/v4/platforms/fpga_3_tsar_v1/top.cpp
===================================================================
--- branches/v4/platforms/fpga_3_tsar_v1/top.cpp	(revision 371)
+++ branches/v4/platforms/fpga_3_tsar_v1/top.cpp	(revision 371)
@@ -0,0 +1,386 @@
+
+#include <systemc>
+#include <sys/time.h>
+#include <iostream>
+#include <cstdlib>
+#include <cstdarg>
+
+#include "mapping_table.h"
+#include "mips32.h"
+#include "vci_simple_ram.h"
+#include "vci_multi_tty.h"
+#include "vci_simple_ring_fast.h"
+#include "vci_vgmn.h"
+#include "vci_mem_cache_v2.h"
+#include "vci_cc_xcache_wrapper_v1.h"
+#include "vci_logger.h"
+
+#include "iss/gdbserver.h"
+#include "iss_memchecker.h"
+
+//#define  VCI_LOGGER
+#include "segmentation.h"
+//#define USE_VGMN
+
+int _main(int argc, char *argv[])
+{
+	using namespace sc_core;
+	// Avoid repeating these everywhere
+	using soclib::common::IntTab;
+	using soclib::common::Segment;
+	typedef soclib::common::Mips32ElIss ProcessorIss;
+
+	// Define VCI parameters
+	typedef soclib::caba::VciParams<4,8,32,1,1,1,8,4,4,1> vci_param;
+//	typedef soclib::common::GdbServer<soclib::common::Mips32ElIss> proc_iss;
+	typedef soclib::common::GdbServer< soclib::common::IssMemchecker<ProcessorIss> > proc_iss;
+	// Mapping table
+
+	soclib::common::MappingTable maptabp(32, IntTab(8), IntTab(8), 0xFF000000);
+
+	maptabp.add(Segment("reset", RESET_BASE, RESET_SIZE, IntTab(0), true));
+	maptabp.add(Segment("tty"  , TTY_BASE  , TTY_SIZE  , IntTab(1), false));
+	maptabp.add(Segment("mc_m" , MC_M_BASE , MC_M_SIZE , IntTab(2), true ));
+ 
+	std::cout << maptabp << std::endl;
+
+        soclib::common::MappingTable maptabc(32, IntTab(8), IntTab(8), 0xFF000000);
+	maptabc.add(Segment("c_proc0" , C_PROC0_BASE , C_PROC0_SIZE , IntTab(0), false, true, IntTab(0)));
+	maptabc.add(Segment("c_proc1" , C_PROC1_BASE , C_PROC1_SIZE , IntTab(1), false, true, IntTab(1)));
+	maptabc.add(Segment("c_proc2" , C_PROC2_BASE , C_PROC2_SIZE , IntTab(2), false, true, IntTab(2)));
+	maptabc.add(Segment("c_proc3" , C_PROC3_BASE , C_PROC3_SIZE , IntTab(3), false, true, IntTab(3)));
+	maptabc.add(Segment("mc_m"  , MC_M_BASE , MC_M_SIZE  , IntTab(4), false, false));
+	maptabc.add(Segment("reset", RESET_BASE, RESET_SIZE, IntTab(4), false, false));
+	maptabc.add(Segment("excep", EXCEP_BASE, EXCEP_SIZE, IntTab(4), false, false));
+	maptabc.add(Segment("text" , TEXT_BASE , TEXT_SIZE , IntTab(4), false, false));
+	maptabc.add(Segment("data" , DATA_BASE , DATA_SIZE , IntTab(4), false, false));
+
+	std::cout << maptabc << std::endl;
+	
+	soclib::common::MappingTable maptabx(32, IntTab(8), IntTab(8), 0xFF000000);
+	maptabx.add(Segment("xram" , MC_M_BASE , MC_M_SIZE , IntTab(0), false));
+	
+	std::cout << maptabx << std::endl;
+
+	// Signals
+	sc_clock	signal_clk("clk");
+	sc_signal<bool> signal_resetn("resetn");
+   
+	sc_signal<bool> signal_proc0_it0("proc0_it0"); 
+	sc_signal<bool> signal_proc0_it1("proc0_it1"); 
+	sc_signal<bool> signal_proc0_it2("proc0_it2"); 
+	sc_signal<bool> signal_proc0_it3("proc0_it3"); 
+	sc_signal<bool> signal_proc0_it4("proc0_it4"); 
+	sc_signal<bool> signal_proc0_it5("proc0_it5");
+
+	sc_signal<bool> signal_proc1_it0("proc1_it0"); 
+	sc_signal<bool> signal_proc1_it1("proc1_it1"); 
+	sc_signal<bool> signal_proc1_it2("proc1_it2"); 
+	sc_signal<bool> signal_proc1_it3("proc1_it3"); 
+	sc_signal<bool> signal_proc1_it4("proc1_it4"); 
+	sc_signal<bool> signal_proc1_it5("proc1_it5");
+
+	sc_signal<bool> signal_proc2_it0("proc2_it0"); 
+	sc_signal<bool> signal_proc2_it1("proc2_it1"); 
+	sc_signal<bool> signal_proc2_it2("proc2_it2"); 
+	sc_signal<bool> signal_proc2_it3("proc2_it3"); 
+	sc_signal<bool> signal_proc2_it4("proc2_it4"); 
+	sc_signal<bool> signal_proc2_it5("proc2_it5");
+
+	sc_signal<bool> signal_proc3_it0("proc3_it0"); 
+	sc_signal<bool> signal_proc3_it1("proc3_it1"); 
+	sc_signal<bool> signal_proc3_it2("proc3_it2"); 
+	sc_signal<bool> signal_proc3_it3("proc3_it3"); 
+	sc_signal<bool> signal_proc3_it4("proc3_it4"); 
+	sc_signal<bool> signal_proc3_it5("proc3_it5");
+
+	soclib::caba::VciSignals<vci_param> signal_vci_ini_rw_proc0("vci_ini_rw_proc0");
+	soclib::caba::VciSignals<vci_param> signal_vci_ini_c_proc0("vci_ini_c_proc0");
+
+	soclib::caba::VciSignals<vci_param> signal_vci_tgt_proc0("vci_tgt_proc0");
+
+	soclib::caba::VciSignals<vci_param> signal_vci_ini_rw_proc1("vci_ini_rw_proc1");
+	soclib::caba::VciSignals<vci_param> signal_vci_ini_c_proc1("vci_ini_c_proc1");
+
+	soclib::caba::VciSignals<vci_param> signal_vci_tgt_proc1("vci_tgt_proc1");
+
+	soclib::caba::VciSignals<vci_param> signal_vci_ini_rw_proc2("vci_ini_rw_proc2");
+	soclib::caba::VciSignals<vci_param> signal_vci_ini_c_proc2("vci_ini_c_proc2");
+
+	soclib::caba::VciSignals<vci_param> signal_vci_tgt_proc2("vci_tgt_proc2");
+
+	soclib::caba::VciSignals<vci_param> signal_vci_ini_rw_proc3("vci_ini_rw_proc3");
+	soclib::caba::VciSignals<vci_param> signal_vci_ini_c_proc3("vci_ini_c_proc3");
+
+	soclib::caba::VciSignals<vci_param> signal_vci_tgt_proc3("vci_tgt_proc3");
+
+	soclib::caba::VciSignals<vci_param> signal_vci_tgt_tty("vci_tgt_tty");
+
+	soclib::caba::VciSignals<vci_param> signal_vci_tgt_rom("vci_tgt_rom");
+
+	soclib::caba::VciSignals<vci_param> signal_vci_tgt_xram("vci_tgt_xram");
+
+	soclib::caba::VciSignals<vci_param> signal_vci_ixr_memc("vci_ixr_memc");
+	soclib::caba::VciSignals<vci_param> signal_vci_ini_memc("vci_ini_memc");
+	soclib::caba::VciSignals<vci_param> signal_vci_tgt_memc("vci_tgt_memc");
+	soclib::caba::VciSignals<vci_param> signal_vci_tgt_cleanup_memc("vci_tgt_cleanup_memc");
+
+	sc_signal<bool> signal_tty_irq0("signal_tty_irq0"); 
+	sc_signal<bool> signal_tty_irq1("signal_tty_irq1"); 
+	sc_signal<bool> signal_tty_irq2("signal_tty_irq2"); 
+	sc_signal<bool> signal_tty_irq3("signal_tty_irq3"); 
+
+	soclib::common::Loader loader("soft/bin.soft");
+
+//    soclib::common::GdbServer<
+//        ProcessorIss >::set_loader(loader);
+    soclib::common::GdbServer<
+        soclib::common::IssMemchecker<
+        ProcessorIss> >::set_loader(loader);
+    soclib::common::IssMemchecker<
+        ProcessorIss>::init(maptabp, loader, "tty");
+
+        //                                  init_rw   init_c   tgt
+	soclib::caba::VciCcXCacheWrapperV1<vci_param, proc_iss > 
+	proc0("proc0", 0, maptabp, maptabc, IntTab(0),IntTab(0),IntTab(0),4,64,16,4,64,16);
+
+	soclib::caba::VciCcXCacheWrapperV1<vci_param, proc_iss > 
+	proc1("proc1", 1, maptabp, maptabc, IntTab(1),IntTab(1),IntTab(1),4,64,16,4,64,16);
+
+	soclib::caba::VciCcXCacheWrapperV1<vci_param, proc_iss > 
+	proc2("proc2", 2, maptabp, maptabc, IntTab(2),IntTab(2),IntTab(2),4,64,16,4,64,16);
+
+	soclib::caba::VciCcXCacheWrapperV1<vci_param, proc_iss > 
+	proc3("proc3", 3, maptabp, maptabc, IntTab(3),IntTab(3),IntTab(3),4,64,16,4,64,16);
+
+
+/*
+	soclib::caba::VciCcXCacheWrapperV1<vci_param, proc_iss > 
+	proc0("proc0", 0, maptabp, maptabc, IntTab(0),IntTab(0),IntTab(0),1,8,16,1,8,16);
+
+	soclib::caba::VciCcXCacheWrapperV1<vci_param, proc_iss > 
+	proc1("proc1", 1, maptabp, maptabc, IntTab(1),IntTab(1),IntTab(1),1,8,16,1,8,16);
+
+	soclib::caba::VciCcXCacheWrapperV1<vci_param, proc_iss > 
+	proc2("proc2", 2, maptabp, maptabc, IntTab(2),IntTab(2),IntTab(2),1,8,16,1,8,16);
+
+	soclib::caba::VciCcXCacheWrapperV1<vci_param, proc_iss > 
+	proc3("proc3", 3, maptabp, maptabc, IntTab(3),IntTab(3),IntTab(3),1,8,16,1,8,16);
+*/
+
+	soclib::caba::VciSimpleRam<vci_param> 
+	rom("rom", IntTab(0), maptabp, loader);
+
+	soclib::caba::VciSimpleRam<vci_param> 
+	xram("xram", IntTab(0), maptabx, loader);
+
+        //                                  x_init    c_init    p_tgt     c_tgt
+	soclib::caba::VciMemCacheV2<vci_param> 
+	memc("memc",maptabp,maptabc,maptabx,IntTab(0),IntTab(4),IntTab(2), IntTab(4),16,256,16);
+	//memc("memc",maptabp,maptabc,maptabx,IntTab(0),IntTab(4),IntTab(2), IntTab(4),4,16,16);
+	//memc("memc",maptabp,maptabc,maptabx,IntTab(0),IntTab(4),IntTab(2), IntTab(4),4,32,16);
+	
+	soclib::caba::VciMultiTty<vci_param> 
+	tty("tty",IntTab(1),maptabp,"tty0","tty1","tty2","tty3",NULL);
+
+#ifdef VCI_LOGGER
+  soclib::caba::VciLogger<vci_param> vci_logger0("vci_logger0",maptabp);
+#endif
+#ifdef USE_VGMN
+	soclib::caba::VciVgmn<vci_param> 
+	ringp("ringp",maptabp, 4, 3, 1, 8);
+
+	soclib::caba::VciVgmn<vci_param> 
+	ringc("ringc",maptabc, 5, 5, 1, 8);
+
+	soclib::caba::VciVgmn<vci_param> 
+	ringx("ringx",maptabx, 1, 1, 1, 8);
+#else
+
+	soclib::caba::VciSimpleRingFast<vci_param,40,33> 
+	ringp("ringp",maptabp, IntTab(), 2, 4, 3);
+
+	soclib::caba::VciSimpleRingFast<vci_param,40,33> 
+	ringc("ringc",maptabc, IntTab(), 2, 5, 5);
+
+	soclib::caba::VciSimpleRingFast<vci_param,40,33> 
+	ringx("ringx",maptabx, IntTab(), 2, 1, 1);
+#endif
+	// Net-List
+ 
+	proc0.p_clk(signal_clk);  
+	proc0.p_resetn(signal_resetn);  
+	proc0.p_irq[0](signal_proc0_it0); 
+	proc0.p_irq[1](signal_proc0_it1); 
+	proc0.p_irq[2](signal_proc0_it2); 
+	proc0.p_irq[3](signal_proc0_it3); 
+	proc0.p_irq[4](signal_proc0_it4); 
+	proc0.p_irq[5](signal_proc0_it5); 
+	proc0.p_vci_ini_rw(signal_vci_ini_rw_proc0);
+	proc0.p_vci_ini_c(signal_vci_ini_c_proc0);
+	proc0.p_vci_tgt(signal_vci_tgt_proc0);
+
+	proc1.p_clk(signal_clk);  
+	proc1.p_resetn(signal_resetn);  
+	proc1.p_irq[0](signal_proc1_it0); 
+	proc1.p_irq[1](signal_proc1_it1); 
+	proc1.p_irq[2](signal_proc1_it2); 
+	proc1.p_irq[3](signal_proc1_it3); 
+	proc1.p_irq[4](signal_proc1_it4); 
+	proc1.p_irq[5](signal_proc1_it5); 
+	proc1.p_vci_ini_rw(signal_vci_ini_rw_proc1);
+	proc1.p_vci_ini_c(signal_vci_ini_c_proc1);
+	proc1.p_vci_tgt(signal_vci_tgt_proc1);
+
+	proc2.p_clk(signal_clk);  
+	proc2.p_resetn(signal_resetn);  
+	proc2.p_irq[0](signal_proc2_it0); 
+	proc2.p_irq[1](signal_proc2_it1); 
+	proc2.p_irq[2](signal_proc2_it2); 
+	proc2.p_irq[3](signal_proc2_it3); 
+	proc2.p_irq[4](signal_proc2_it4); 
+	proc2.p_irq[5](signal_proc2_it5); 
+	proc2.p_vci_ini_rw(signal_vci_ini_rw_proc2);
+	proc2.p_vci_ini_c(signal_vci_ini_c_proc2);
+	proc2.p_vci_tgt(signal_vci_tgt_proc2);
+
+	proc3.p_clk(signal_clk);  
+	proc3.p_resetn(signal_resetn);  
+	proc3.p_irq[0](signal_proc3_it0); 
+	proc3.p_irq[1](signal_proc3_it1); 
+	proc3.p_irq[2](signal_proc3_it2); 
+	proc3.p_irq[3](signal_proc3_it3); 
+	proc3.p_irq[4](signal_proc3_it4); 
+	proc3.p_irq[5](signal_proc3_it5); 
+	proc3.p_vci_ini_rw(signal_vci_ini_rw_proc3);
+	proc3.p_vci_ini_c(signal_vci_ini_c_proc3);
+	proc3.p_vci_tgt(signal_vci_tgt_proc3);
+
+	rom.p_clk(signal_clk);
+	rom.p_resetn(signal_resetn);
+	rom.p_vci(signal_vci_tgt_rom);
+
+#ifdef VCI_LOGGER
+  vci_logger0.p_clk(signal_clk);
+  vci_logger0.p_resetn(signal_resetn);
+  vci_logger0.p_vci(signal_vci_ini_rw_proc2);
+#endif
+
+	tty.p_clk(signal_clk);
+	tty.p_resetn(signal_resetn);
+	tty.p_vci(signal_vci_tgt_tty);
+	tty.p_irq[0](signal_tty_irq0); 
+	tty.p_irq[1](signal_tty_irq1); 
+	tty.p_irq[2](signal_tty_irq2); 
+	tty.p_irq[3](signal_tty_irq3); 
+
+	memc.p_clk(signal_clk);
+	memc.p_resetn(signal_resetn);
+	memc.p_vci_tgt(signal_vci_tgt_memc);
+	memc.p_vci_tgt_cleanup(signal_vci_tgt_cleanup_memc);
+	memc.p_vci_ini(signal_vci_ini_memc);
+	memc.p_vci_ixr(signal_vci_ixr_memc);
+
+	xram.p_clk(signal_clk);
+  xram.p_resetn(signal_resetn);
+	xram.p_vci(signal_vci_tgt_xram);
+	
+	ringp.p_clk(signal_clk);
+	ringp.p_resetn(signal_resetn);
+
+	ringc.p_clk(signal_clk);
+	ringc.p_resetn(signal_resetn);
+
+	ringx.p_clk(signal_clk);
+	ringx.p_resetn(signal_resetn);
+
+	ringp.p_to_initiator[0](signal_vci_ini_rw_proc0);
+	ringp.p_to_initiator[1](signal_vci_ini_rw_proc1);
+	ringp.p_to_initiator[2](signal_vci_ini_rw_proc2);
+	ringp.p_to_initiator[3](signal_vci_ini_rw_proc3);
+
+	ringc.p_to_initiator[4](signal_vci_ini_memc);
+	ringc.p_to_initiator[0](signal_vci_ini_c_proc0);
+	ringc.p_to_initiator[1](signal_vci_ini_c_proc1);
+	ringc.p_to_initiator[2](signal_vci_ini_c_proc2);
+	ringc.p_to_initiator[3](signal_vci_ini_c_proc3);
+
+	ringx.p_to_initiator[0](signal_vci_ixr_memc);
+
+	ringp.p_to_target[0](signal_vci_tgt_rom);
+	ringp.p_to_target[1](signal_vci_tgt_tty);
+	ringp.p_to_target[2](signal_vci_tgt_memc);
+
+	ringc.p_to_target[0](signal_vci_tgt_proc0);
+	ringc.p_to_target[1](signal_vci_tgt_proc1);
+	ringc.p_to_target[2](signal_vci_tgt_proc2);
+	ringc.p_to_target[3](signal_vci_tgt_proc3);
+	ringc.p_to_target[4](signal_vci_tgt_cleanup_memc);
+
+	ringx.p_to_target[0](signal_vci_tgt_xram);
+
+	int ncycles;
+
+#ifndef SOCVIEW
+/*	if (argc == 2) {
+		ncycles = std::atoi(argv[1]);
+	} else {
+		std::cerr
+			<< std::endl
+			<< "The number of simulation cycles must "
+			   "be defined in the command line"
+			<< std::endl;
+		exit(1);
+	}
+*/
+	sc_start(sc_core::sc_time(0, SC_NS));
+	signal_resetn = false;
+
+	sc_start(sc_core::sc_time(1, SC_NS));
+	signal_resetn = true;
+
+/*
+  while(1){
+    char buf[2];
+	  std::cin.getline(buf,1);
+		sc_start(sc_core::sc_time(1, SC_NS));
+  }
+*/
+
+	for (int i = 0; ; i+=10000) {
+		sc_start(sc_core::sc_time(100000, SC_NS));
+		std::cout << "Time : " << sc_core::sc_simulation_time() << std::endl;
+//		proc0.print_stats();
+//		memc.print_stats();
+	}
+
+        std::cout << "Hit ENTER to end simulation" << std::endl;
+        char buf[1];
+
+	std::cin.getline(buf,1);
+
+	return EXIT_SUCCESS;
+#else
+	ncycles = 1;
+	sc_start(sc_core::sc_time(0, SC_NS));
+	signal_resetn = false;
+	sc_start(sc_core::sc_time(1, SC_NS));
+	signal_resetn = true;
+
+	debug();
+	return EXIT_SUCCESS;
+#endif
+}
+
+int sc_main (int argc, char *argv[])
+{
+	try {
+		return _main(argc, argv);
+	} catch (std::exception &e) {
+		std::cout << e.what() << std::endl;
+	} catch (...) {
+		std::cout << "Unknown exception occured" << std::endl;
+		throw;
+	}
+	return 1;
+}
Index: branches/v4/platforms/platform_fpga_de2-115/Makefile
===================================================================
--- branches/v4/platforms/platform_fpga_de2-115/Makefile	(revision 371)
+++ branches/v4/platforms/platform_fpga_de2-115/Makefile	(revision 371)
@@ -0,0 +1,9 @@
+ARCH=mips32el
+SIMULATION_ARGS=100000
+SOCLIB?=$(shell soclib-cc --getpath)
+NO_SOFT=1
+export SOCLIB
+#SOCLIB_CC_ADD_ARGS='-v -j8 -I. -m debug'
+SOCLIB_CC_ADD_ARGS='-v -j8 -I. -b common:mips32 -b common:mips32el '
+#SOCLIB_CC_ADD_ARGS='-v -j8 -I. '
+include $(SOCLIB)/soclib/platform/topcells/all.mk
Index: branches/v4/platforms/platform_fpga_de2-115/platform_desc
===================================================================
--- branches/v4/platforms/platform_fpga_de2-115/platform_desc	(revision 371)
+++ branches/v4/platforms/platform_fpga_de2-115/platform_desc	(revision 371)
@@ -0,0 +1,33 @@
+
+# -*- python -*-
+
+
+todo = Platform('caba', 'top.cpp',
+                uses = [
+	Uses('caba:vci_cc_vcache_wrapper_v4', iss_t = 'common:mips32el'),
+	Uses('caba:vci_simple_ram'),
+	Uses('caba:vci_multi_tty'),
+        Uses('caba:vci_xicu'),
+	Uses('caba:vci_block_device_tsar_v4'),
+	Uses('caba:vci_simhelper'),
+        Uses('caba:vci_framebuffer'),
+	Uses('caba:vci_simple_ring_fast',
+	      ring_cmd_data_size=40,
+	      ring_rsp_data_size=33
+	),
+        Uses('caba:vci_logger'),
+	Uses('caba:vci_mem_cache_v4'),
+	Uses('common:elf_file_loader'),
+	],
+	cell_size = 4,
+	plen_size = 8,
+	addr_size = 32,
+	rerror_size = 2,
+	clen_size = 1,
+	rflag_size = 1,
+	srcid_size = 5,
+	pktid_size = 4,
+	trdid_size = 4,
+	wrplen_size = 1
+)
+
Index: branches/v4/platforms/platform_fpga_de2-115/segmentation.h
===================================================================
--- branches/v4/platforms/platform_fpga_de2-115/segmentation.h	(revision 371)
+++ branches/v4/platforms/platform_fpga_de2-115/segmentation.h	(revision 371)
@@ -0,0 +1,99 @@
+/*
+   This file is part of MutekP.
+  
+   MutekP is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 2 of the License, or
+   (at your option) any later version.
+  
+   MutekP is distributed in the hope that it will be useful, but
+   WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+   General Public License for more details.
+  
+   You should have received a copy of the GNU General Public License
+   along with MutekP; if not, write to the Free Software Foundation,
+   Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+  
+   UPMC / LIP6 / SOC (c) 2009
+   Copyright Ghassan Almaless <ghassan.almaless@gmail.com>
+*/
+
+
+/////////////////////////////////////////
+//   Devices mapped segments 
+/////////////////////////////////////////
+#define     SIMH_BASE	0xf1000000
+#define     SIMH_SIZE	0x00010000
+
+#define     XICU_BASE   0xfd000000
+#define     XICU_SIZE   0x00001000
+
+#define	    DMA_BASE	0xf2000000
+#define	    DMA_SIZE	0x00000014
+
+#define     TTY_BASE    0xfc000000
+#define     TTY_SIZE    0x00000010
+
+#define     BD_BASE     0xfb000000
+#define     BD_SIZE     0x20
+
+#define FB_XSIZE 640
+#define FB_YSIZE 480
+#define	     FB_BASE	0xf0000000
+#define      FB_SIZE	FB_XSIZE*FB_YSIZE*4
+////////////////////////////////////////
+
+
+//////////////////////////////////////////
+//       ROM mapped segments
+//////////////////////////////////////////
+
+#define    BOOT_BASE       0xbfc00000
+#define    BOOT_SIZE       0x00400000
+
+#define    DTB_BASE	   0xbfd00000
+#define    DTB_SIZE	   0x00002000
+
+#define    ROM_BASE        BOOT_BASE
+#define    ROM_SIZE        (DTB_BASE+DTB_SIZE-ROM_BASE)
+//////////////////////////////////////////
+
+//////////////////////////////////////////
+//                RAM
+//////////////////////////////////////////
+
+#define     RAM_BASE    0x00000000
+#define     RAM_SIZE    0x10000000
+//////////////////////////////////////////
+
+//////////////////////////////////////////
+//    Application mapped segments
+//////////////////////////////////////////
+
+#define  KTEXT_BASE       0x80000000
+#define  KDATA_BASE       0x80020000
+#define  KDATA_SIZE       0x003E0000
+
+#define     USR_TEXT_BASE    0x7F400000
+#define     USR_DATA_BASE    0x7F402000
+#define     USR_DATA_SIZE    0X00BFD000
+////////////////////////////////////////
+
+////////////////////////////////////////
+//	Reserved segments
+////////////////////////////////////////
+
+#define PROC0_BASE	0x11200000
+#define PROC0_SIZE	0x00000020
+
+#define PROC1_BASE	0x12200000
+#define PROC1_SIZE	0x00000020
+
+#define PROC2_BASE	0x13200000
+#define PROC2_SIZE	0x00000020
+
+#define PROC3_BASE	0x14200000
+#define PROC3_SIZE	0x00000020
+
+////////////////////////////////////////
Index: branches/v4/platforms/platform_fpga_de2-115/top.cpp
===================================================================
--- branches/v4/platforms/platform_fpga_de2-115/top.cpp	(revision 371)
+++ branches/v4/platforms/platform_fpga_de2-115/top.cpp	(revision 371)
@@ -0,0 +1,625 @@
+#define DEBUG_CYCLE (0)
+#define DEBUG_END (DEBUG_CYCLE + 330000)
+#define DEBUG
+#define DEBUG_CYCLE (-1)
+#define DEBUG_END (DEBUG_CYCLE + 33000)
+#undef DEBUG
+#include <systemc>
+#include <sys/time.h>
+#include <iostream>
+#include <cstdlib>
+#include <cstdarg>
+#ifdef _OPENMP
+#include <omp.h>
+#endif
+
+#include "mapping_table.h"
+#include "mips32.h"
+#include "vci_simple_ram.h"
+#include "vci_multi_tty.h"
+#include "vci_simple_ring_fast.h"
+#include "vci_mem_cache_v4.h"
+#include "vci_cc_vcache_wrapper_v4.h"
+#include "vci_logger.h"
+#include "vci_xicu.h"
+#include "vci_block_device_tsar_v4.h"
+#include "vci_simhelper.h"
+#include "vci_framebuffer.h"
+
+#ifdef USE_GDB_SERVER
+#include "iss/gdbserver.h"
+#endif
+
+// #define  VCI_LOGGER_ON_L1
+//#define  VCI_LOGGER_ON_ROM
+//#define VCI_LOGGER_ON_L1_TGT
+
+#include "segmentation.h"
+
+bool do_debug;
+
+int _main(int argc, char *argv[])
+{
+	uint64_t       ms1, ms2;
+	struct timeval t1, t2;
+	using namespace sc_core;
+	// Avoid repeating these everywhere
+	using soclib::common::IntTab;
+	using soclib::common::Segment;
+
+	// set requested parallelims
+#ifdef _OPENMP
+	omp_set_dynamic(false);
+	omp_set_num_threads(5);
+	//omp_set_num_threads(1);
+	std::cerr << "Built with openmp version " << _OPENMP << std::endl;
+#endif
+
+	if (argc < 3) {
+		std::cerr << "usage: " << argv[0] << " <ELF boot image> <disk image>" << std::endl;
+		exit(1);
+	}
+
+	// Define VCI parameters
+#define    cell_width            4
+#define    address_width         32
+#define    plen_width            8
+#define    error_width           2
+#define    clen_width            1
+#define    rflag_width           1
+#define    srcid_width           5
+#define    pktid_width           4
+#define    trdid_width           4
+#define    wrplen_width          1
+
+	typedef soclib::caba::VciParams<cell_width,
+					plen_width,
+					address_width,
+					error_width,
+					clen_width,
+					rflag_width,
+					srcid_width,
+					pktid_width,
+					trdid_width,
+					wrplen_width> vci_param;
+	typedef soclib::common::Mips32ElIss proc_iss;
+	// Mapping table
+
+	soclib::common::MappingTable maptabp(32, IntTab(8), IntTab(8), 0xF0000000);
+	
+	maptabp.add(Segment("mc_m" , RAM_BASE , RAM_SIZE , IntTab(0), true));
+	maptabp.add(Segment("boot", ROM_BASE, ROM_SIZE, IntTab(1), true));
+	maptabp.add(Segment("bd", BD_BASE, BD_SIZE, IntTab(2), false));
+	maptabp.add(Segment("tty"  , TTY_BASE  , TTY_SIZE  , IntTab(3), false));
+	maptabp.add(Segment("xicu" , XICU_BASE , XICU_SIZE , IntTab(4), false));
+	maptabp.add(Segment("simh", SIMH_BASE, SIMH_SIZE, IntTab(5), false));
+	maptabp.add(Segment("fb", FB_BASE, FB_SIZE, IntTab(6), false));
+
+	std::cout << maptabp << std::endl;
+
+	soclib::common::MappingTable maptabc(32, IntTab(srcid_width), IntTab(srcid_width), 0xF0000000);
+	maptabc.add(Segment("c_proc0" , 0 << (address_width - srcid_width) , 0x10 , IntTab(0), false));
+	maptabc.add(Segment("c_proc1" , 1 << (address_width - srcid_width) , 0x10 , IntTab(1), false));
+	maptabc.add(Segment("c_proc2" , 2 << (address_width - srcid_width) , 0x10 , IntTab(2), false));
+	maptabc.add(Segment("c_proc3" , 3 << (address_width - srcid_width) , 0x10 , IntTab(3), false));
+	maptabc.add(Segment("mc_m" , 4 << (address_width - srcid_width) , 0x10 , IntTab(4), false ));
+
+	std::cout << maptabc << std::endl;
+	
+	soclib::common::MappingTable maptabx(32, IntTab(8), IntTab(8), 0x30000000);
+	maptabx.add(Segment("xram" , RAM_BASE , RAM_SIZE , IntTab(0), false));
+	
+	
+	std::cout << maptabx << std::endl;
+
+	// Signals
+
+	sc_clock	signal_clk ("clk");
+	sc_signal<bool> *signal_resetn;
+	signal_resetn = new sc_signal<bool>("resetn");
+
+	sc_signal<bool> *signal_proc0_it0;
+	sc_signal<bool> *signal_proc0_it1;
+	sc_signal<bool> *signal_proc0_it2;
+	sc_signal<bool> *signal_proc0_it3;
+	sc_signal<bool> *signal_proc0_it4;
+	sc_signal<bool> *signal_proc0_it5;
+
+	sc_signal<bool> *signal_proc1_it0;
+	sc_signal<bool> *signal_proc1_it1;
+	sc_signal<bool> *signal_proc1_it2;
+	sc_signal<bool> *signal_proc1_it3;
+	sc_signal<bool> *signal_proc1_it4;
+	sc_signal<bool> *signal_proc1_it5;
+
+	sc_signal<bool> *signal_proc2_it0;
+	sc_signal<bool> *signal_proc2_it1;
+	sc_signal<bool> *signal_proc2_it2;
+	sc_signal<bool> *signal_proc2_it3;
+	sc_signal<bool> *signal_proc2_it4;
+	sc_signal<bool> *signal_proc2_it5;
+
+	sc_signal<bool> *signal_proc3_it0;
+	sc_signal<bool> *signal_proc3_it1;
+	sc_signal<bool> *signal_proc3_it2;
+	sc_signal<bool> *signal_proc3_it3;
+	sc_signal<bool> *signal_proc3_it4;
+	sc_signal<bool> *signal_proc3_it5;
+
+	soclib::caba::VciSignals<vci_param> *signal_vci_ini_rw_proc0;
+	signal_vci_ini_rw_proc0 = new soclib::caba::VciSignals<vci_param>("vci_ini_rw_proc0");
+	std::cerr << "signal_vci_ini_rw_proc0 " << sizeof(*signal_vci_ini_rw_proc0) << "@" << signal_vci_ini_rw_proc0 << std::endl;
+	soclib::caba::VciSignals<vci_param> *signal_vci_ini_c_proc0;
+	signal_vci_ini_c_proc0 = new soclib::caba::VciSignals<vci_param>("vci_ini_c_proc0");
+	soclib::caba::VciSignals<vci_param> *signal_vci_tgt_proc0;
+	signal_vci_tgt_proc0 = new soclib::caba::VciSignals<vci_param>("vci_tgt_proc0");
+
+	soclib::caba::VciSignals<vci_param> *signal_vci_ini_rw_proc1;
+	signal_vci_ini_rw_proc1 = new soclib::caba::VciSignals<vci_param>("vci_ini_rw_proc1");
+	std::cerr << "signal_vci_ini_rw_proc1 " << sizeof(*signal_vci_ini_rw_proc1) << "@" << signal_vci_ini_rw_proc1 << std::endl;
+	soclib::caba::VciSignals<vci_param> *signal_vci_ini_c_proc1;
+	signal_vci_ini_c_proc1 = new soclib::caba::VciSignals<vci_param>("vci_ini_c_proc1");
+	soclib::caba::VciSignals<vci_param> *signal_vci_tgt_proc1;
+	signal_vci_tgt_proc1 = new soclib::caba::VciSignals<vci_param>("vci_tgt_proc1");
+
+	soclib::caba::VciSignals<vci_param> *signal_vci_ini_rw_proc2;
+	signal_vci_ini_rw_proc2 = new soclib::caba::VciSignals<vci_param>("vci_ini_rw_proc2");
+	std::cerr << "signal_vci_ini_rw_proc2 " << sizeof(*signal_vci_ini_rw_proc2) << "@" << signal_vci_ini_rw_proc2 << std::endl;
+	soclib::caba::VciSignals<vci_param> *signal_vci_ini_c_proc2;
+	signal_vci_ini_c_proc2 = new soclib::caba::VciSignals<vci_param>("vci_ini_c_proc2");
+	soclib::caba::VciSignals<vci_param> *signal_vci_tgt_proc2;
+	signal_vci_tgt_proc2 = new soclib::caba::VciSignals<vci_param>("vci_tgt_proc2");
+
+	soclib::caba::VciSignals<vci_param> *signal_vci_ini_rw_proc3;
+	signal_vci_ini_rw_proc3 = new soclib::caba::VciSignals<vci_param>("vci_ini_rw_proc3");
+	std::cerr << "signal_vci_ini_rw_proc3 " << sizeof(*signal_vci_ini_rw_proc3) << "@" << signal_vci_ini_rw_proc3 << std::endl;
+	soclib::caba::VciSignals<vci_param> *signal_vci_ini_c_proc3;
+	signal_vci_ini_c_proc3 = new soclib::caba::VciSignals<vci_param>("vci_ini_c_proc3");
+	soclib::caba::VciSignals<vci_param> *signal_vci_tgt_proc3;
+	signal_vci_tgt_proc3 = new soclib::caba::VciSignals<vci_param>("vci_tgt_proc3");
+
+	soclib::caba::VciSignals<vci_param> *signal_vci_tty;
+	signal_vci_tty = new soclib::caba::VciSignals<vci_param>("signal_vci_tty");
+	soclib::caba::VciSignals<vci_param> *signal_vci_fb;
+	signal_vci_fb = new soclib::caba::VciSignals<vci_param>("signal_vci_fb");
+	soclib::caba::VciSignals<vci_param> *signal_vci_simh;
+	signal_vci_simh = new soclib::caba::VciSignals<vci_param>("signal_vci_simh");
+
+	
+	soclib::caba::VciSignals<vci_param> *signal_vci_xicu;
+	signal_vci_xicu = new soclib::caba::VciSignals<vci_param>("signal_vci_xicu");
+	soclib::caba::VciSignals<vci_param> *signal_vci_vcibd_i;
+	signal_vci_vcibd_i = new soclib::caba::VciSignals<vci_param>("signal_vci_vcibd_i");
+	soclib::caba::VciSignals<vci_param> *signal_vci_vcibd_t;
+	signal_vci_vcibd_t = new soclib::caba::VciSignals<vci_param>("signal_vci_vcibd_t");
+	soclib::caba::VciSignals<vci_param> *signal_vci_tgt_rom;
+	signal_vci_tgt_rom = new soclib::caba::VciSignals<vci_param>("vci_tgt_rom");
+
+	soclib::caba::VciSignals<vci_param> *signal_vci_ixr_memc;
+	soclib::caba::VciSignals<vci_param> *signal_vci_ini_memc;
+	signal_vci_ini_memc = new soclib::caba::VciSignals<vci_param>("vci_ini_memc");
+	soclib::caba::VciSignals<vci_param> *signal_vci_tgt_memc;
+	signal_vci_tgt_memc = new soclib::caba::VciSignals<vci_param>("vci_tgt_memc");
+	soclib::caba::VciSignals<vci_param> *signal_vci_tgt_cleanup_memc;
+	signal_vci_tgt_cleanup_memc = new soclib::caba::VciSignals<vci_param>("vci_tgt_cleanup_memc");
+
+	sc_signal<bool> *signal_icu_irq0;
+	sc_signal<bool> *signal_icu_irq1;
+
+	soclib::common::Loader loader(argv[1]);
+
+        //                                  init_rw   init_c   tgt
+	soclib::caba::VciCcVCacheWrapperV4<vci_param, proc_iss > *proc0;
+	soclib::caba::VciSimpleRam<vci_param> *rom;
+	soclib::caba::VciSimpleRam<vci_param> *xram;
+	soclib::caba::VciMemCacheV4<vci_param> *memc;
+	soclib::caba::VciCcVCacheWrapperV4<vci_param, proc_iss > *proc1;
+	soclib::caba::VciXicu<vci_param> *vcixicu;
+	soclib::caba::VciMultiTty<vci_param> *vcitty;
+	soclib::caba::VciFrameBuffer<vci_param> *vcifb;
+	soclib::caba::VciSimhelper<vci_param> *vcisimh;
+	soclib::caba::VciCcVCacheWrapperV4<vci_param, proc_iss > *proc2;
+	soclib::caba::VciBlockDeviceTsarV4<vci_param> *vcibd;
+	soclib::caba::VciCcVCacheWrapperV4<vci_param, proc_iss > *proc3;
+	soclib::caba::VciSimpleRingFast<vci_param, 40, 33> *ringp;
+	soclib::caba::VciSimpleRingFast<vci_param, 40, 33> *ringc;
+#pragma omp parallel sections
+  {
+#pragma omp section
+    {
+#pragma omp critical
+      {
+	proc0 = new soclib::caba::VciCcVCacheWrapperV4<vci_param, proc_iss >
+	  ("proc0", 0, maptabp, maptabc, IntTab(0),IntTab(0),IntTab(0),
+	    8,8,8,8,4,64,16,4,64,16,4, 4, 0, 0, 4, 50000, DEBUG_CYCLE, true);
+	signal_proc0_it0 = new sc_signal<bool>("mips0_it0");
+	signal_proc0_it1 = new sc_signal<bool>("mips0_it1");
+	signal_proc0_it2 = new sc_signal<bool>("mips0_it2");
+	signal_proc0_it3 = new sc_signal<bool>("mips0_it3");
+	signal_proc0_it4 = new sc_signal<bool>("mips0_it4");
+	signal_proc0_it5 = new sc_signal<bool>("mips0_it5");
+	vcisimh = new soclib::caba::VciSimhelper<vci_param>
+	  ("vcisimh",	IntTab(5), maptabp);
+	proc1 = new soclib::caba::VciCcVCacheWrapperV4<vci_param, proc_iss >
+	  ("proc1", 1, maptabp, maptabc, IntTab(1),IntTab(1),IntTab(1),
+	    8,8,8,8,4,64,16,4,64,16,4, 4, 0, 0, 4, 50000, DEBUG_CYCLE, true);
+	signal_proc1_it0 = new sc_signal<bool>("mips1_it0");
+	signal_proc1_it1 = new sc_signal<bool>("mips1_it1");
+	signal_proc1_it2 = new sc_signal<bool>("mips1_it2");
+	signal_proc1_it3 = new sc_signal<bool>("mips1_it3");
+	signal_proc1_it4 = new sc_signal<bool>("mips1_it4");
+	signal_proc1_it5 = new sc_signal<bool>("mips1_it5");
+	vcitty = new soclib::caba::VciMultiTty<vci_param>
+	  ("vcitty",	IntTab(3), maptabp, "vcitty0", NULL);
+	vcifb = new soclib::caba::VciFrameBuffer<vci_param>
+	  ("vcifb", IntTab(6), maptabp, FB_XSIZE, FB_YSIZE, soclib::common::FbController::RGB_32);
+
+	rom = new soclib::caba::VciSimpleRam<vci_param>
+	  ("rom", IntTab(1), maptabp, loader);
+	vcibd = new soclib::caba::VciBlockDeviceTsarV4<vci_param>
+	  ("vcitbd", maptabp, IntTab(4), IntTab(2), argv[2]);
+
+#if 1
+      }
+    }
+#pragma omp section
+    {
+#pragma omp critical
+      {
+#endif
+	proc2 = new soclib::caba::VciCcVCacheWrapperV4<vci_param, proc_iss >
+	  ("proc2", 2, maptabp, maptabc, IntTab(2),IntTab(2),IntTab(2),
+	    8,8,8,8,4,64,16,4,64,16,4, 4, 0, 0, 4, 50000, DEBUG_CYCLE, true);
+	signal_proc2_it0 = new sc_signal<bool>("mips2_it0");
+	signal_proc2_it1 = new sc_signal<bool>("mips2_it1");
+	signal_proc2_it2 = new sc_signal<bool>("mips2_it2");
+	signal_proc2_it3 = new sc_signal<bool>("mips2_it3");
+	signal_proc2_it4 = new sc_signal<bool>("mips2_it4");
+	signal_proc2_it5 = new sc_signal<bool>("mips2_it5");
+	vcixicu = new soclib::caba::VciXicu<vci_param>
+	  ("vcixicu", maptabp, IntTab(4), 4 /* npti */, 2 /* nhwi */, 4 /* nwti */, 12 /* nirq */);
+	signal_icu_irq0 = new sc_signal<bool>("signal_xicu_irq0");
+	signal_icu_irq1 = new sc_signal<bool>("signal_xicu_irq1");
+#if 1
+      }
+    }
+#pragma omp section
+    {
+#pragma omp critical
+      {
+#endif
+	ringc = new soclib::caba::VciSimpleRingFast<vci_param, 40, 33>
+	  ("ringc",maptabc, IntTab(), 4, 5, 5);
+#if 1
+      }
+    }
+#pragma omp section
+    {
+#pragma omp critical
+      {
+#endif
+	ringp = new soclib::caba::VciSimpleRingFast<vci_param, 40, 33> 
+	  ("ringp",maptabp, IntTab(), 4, 5, 7);
+#if 1
+      }
+    }
+#pragma omp section
+    {
+#pragma omp critical
+      {
+#endif
+	proc3 = new soclib::caba::VciCcVCacheWrapperV4<vci_param, proc_iss >
+	  ("proc3", 3, maptabp, maptabc, IntTab(3),IntTab(3),IntTab(3),
+	    8,8,8,8,4,64,16,4,64,16,4, 4, 0, 0, 4, 50000, DEBUG_CYCLE, true);
+	signal_proc3_it0 = new sc_signal<bool>("mips3_it0");
+	signal_proc3_it1 = new sc_signal<bool>("mips3_it1");
+	signal_proc3_it2 = new sc_signal<bool>("mips3_it2");
+	signal_proc3_it3 = new sc_signal<bool>("mips3_it3");
+	signal_proc3_it4 = new sc_signal<bool>("mips3_it4");
+	signal_proc3_it5 = new sc_signal<bool>("mips3_it5");
+	xram = new soclib::caba::VciSimpleRam<vci_param>
+	  ("xram", IntTab(0), maptabx, loader);
+	memc = new soclib::caba::VciMemCacheV4<vci_param>
+	  ("memc",maptabp,maptabc,maptabx,IntTab(0),IntTab(4),IntTab(0), IntTab(4),16,256,16, 1024, 4, 4, DEBUG_CYCLE, true);
+	signal_vci_ixr_memc = new soclib::caba::VciSignals<vci_param>("vci_ixr_memc");
+#ifdef VCI_LOGGER_ON_L1
+	soclib::caba::VciLogger<vci_param> vci_logger0("vci_logger0",maptabp);
+#endif
+#ifdef VCI_LOGGER_ON_ROM
+	soclib::caba::VciLogger<vci_param> vci_logger1("vci_logger1",maptabp);
+#endif
+#ifdef VCI_LOGGER_ON_L1_TGT
+	soclib::caba::VciLogger<vci_param> vci_logger2("vci_logger2",maptabp);
+#endif
+      }
+    }
+  }
+
+	proc0->p_clk(signal_clk);
+	proc0->p_resetn(*signal_resetn);
+	proc0->p_irq[0](*signal_proc0_it0);
+	proc0->p_irq[1](*signal_proc0_it1);
+	proc0->p_irq[2](*signal_proc0_it2);
+	proc0->p_irq[3](*signal_proc0_it3);
+	proc0->p_irq[4](*signal_proc0_it4);
+	proc0->p_irq[5](*signal_proc0_it5);
+	proc0->p_vci_ini_d(*signal_vci_ini_rw_proc0);
+	proc0->p_vci_ini_c(*signal_vci_ini_c_proc0);
+	proc0->p_vci_tgt_c(*signal_vci_tgt_proc0);
+
+	proc1->p_clk(signal_clk);
+	proc1->p_resetn(*signal_resetn);
+	proc1->p_irq[0](*signal_proc1_it0);
+	proc1->p_irq[1](*signal_proc1_it1);
+	proc1->p_irq[2](*signal_proc1_it2);
+	proc1->p_irq[3](*signal_proc1_it3);
+	proc1->p_irq[4](*signal_proc1_it4);
+	proc1->p_irq[5](*signal_proc1_it5);
+	proc1->p_vci_ini_d(*signal_vci_ini_rw_proc1);
+	proc1->p_vci_ini_c(*signal_vci_ini_c_proc1);
+	proc1->p_vci_tgt_c(*signal_vci_tgt_proc1);
+
+	proc2->p_clk(signal_clk);
+	proc2->p_resetn(*signal_resetn);
+	proc2->p_irq[0](*signal_proc2_it0);
+	proc2->p_irq[1](*signal_proc2_it1);
+	proc2->p_irq[2](*signal_proc2_it2);
+	proc2->p_irq[3](*signal_proc2_it3);
+	proc2->p_irq[4](*signal_proc2_it4);
+	proc2->p_irq[5](*signal_proc2_it5);
+	proc2->p_vci_ini_d(*signal_vci_ini_rw_proc2);
+	proc2->p_vci_ini_c(*signal_vci_ini_c_proc2);
+	proc2->p_vci_tgt_c(*signal_vci_tgt_proc2);
+
+	proc3->p_clk(signal_clk);
+	proc3->p_resetn(*signal_resetn);
+	proc3->p_irq[0](*signal_proc3_it0);
+	proc3->p_irq[1](*signal_proc3_it1);
+	proc3->p_irq[2](*signal_proc3_it2);
+	proc3->p_irq[3](*signal_proc3_it3);
+	proc3->p_irq[4](*signal_proc3_it4);
+	proc3->p_irq[5](*signal_proc3_it5);
+	proc3->p_vci_ini_d(*signal_vci_ini_rw_proc3);
+	proc3->p_vci_ini_c(*signal_vci_ini_c_proc3);
+	proc3->p_vci_tgt_c(*signal_vci_tgt_proc3);
+
+	rom->p_clk(signal_clk);
+	rom->p_resetn(*signal_resetn);
+	rom->p_vci(*signal_vci_tgt_rom);
+
+	vcixicu->p_resetn(*signal_resetn);
+	vcixicu->p_clk(signal_clk);
+	vcixicu->p_vci(*signal_vci_xicu);
+	vcixicu->p_hwi[0](*signal_icu_irq0);
+	vcixicu->p_hwi[1](*signal_icu_irq1);
+	vcixicu->p_irq[0](*signal_proc0_it0);
+	vcixicu->p_irq[1](*signal_proc0_it1);
+	vcixicu->p_irq[2](*signal_proc0_it2);
+	vcixicu->p_irq[3](*signal_proc1_it0);
+	vcixicu->p_irq[4](*signal_proc1_it1);
+	vcixicu->p_irq[5](*signal_proc1_it2);
+	vcixicu->p_irq[6](*signal_proc2_it0);
+	vcixicu->p_irq[7](*signal_proc2_it1);
+	vcixicu->p_irq[8](*signal_proc2_it2);
+	vcixicu->p_irq[9](*signal_proc3_it0);
+	vcixicu->p_irq[10](*signal_proc3_it1);
+	vcixicu->p_irq[11](*signal_proc3_it2);
+
+#ifdef VCI_LOGGER_ON_L1
+  vci_logger0.p_clk(signal_clk);
+  vci_logger0.p_resetn(*signal_resetn);
+  vci_logger0.p_vci(*signal_vci_ini_rw_proc0);
+#endif
+
+#ifdef VCI_LOGGER_ON_ROM
+  vci_logger1.p_clk(signal_clk);
+  vci_logger1.p_resetn(*signal_resetn);
+  vci_logger1.p_vci(*signal_vci_tgt_rom);
+#endif
+
+#ifdef VCI_LOGGER_ON_L1_TGT
+  vci_logger2.p_clk(signal_clk);
+  vci_logger2.p_resetn(*signal_resetn);
+  vci_logger2.p_vci(*signal_vci_tgt_proc1);
+#endif
+
+	vcitty->p_clk(signal_clk);
+	vcitty->p_resetn(*signal_resetn);
+	vcitty->p_vci(*signal_vci_tty);
+	vcitty->p_irq[0](*signal_icu_irq0);
+
+	vcisimh->p_clk(signal_clk);
+	vcisimh->p_resetn(*signal_resetn);
+	vcisimh->p_vci(*signal_vci_simh);
+
+	memc->p_clk(signal_clk);
+	memc->p_resetn(*signal_resetn);
+	memc->p_vci_tgt(*signal_vci_tgt_memc);
+	memc->p_vci_tgt_cleanup(*signal_vci_tgt_cleanup_memc);
+	memc->p_vci_ini(*signal_vci_ini_memc);
+	memc->p_vci_ixr(*signal_vci_ixr_memc);
+
+	vcibd->p_clk(signal_clk);
+	vcibd->p_resetn(*signal_resetn);
+	vcibd->p_vci_target(*signal_vci_vcibd_t);
+	vcibd->p_vci_initiator(*signal_vci_vcibd_i);
+	vcibd->p_irq(*signal_icu_irq1);
+
+	vcifb->p_clk(signal_clk);
+	vcifb->p_resetn(*signal_resetn);
+	vcifb->p_vci(*signal_vci_fb);
+
+	xram->p_clk(signal_clk);
+	xram->p_resetn(*signal_resetn);
+	xram->p_vci(*signal_vci_ixr_memc);
+	
+	ringp->p_clk(signal_clk);
+	ringp->p_resetn(*signal_resetn);
+
+	ringc->p_clk(signal_clk);
+	ringc->p_resetn(*signal_resetn);
+
+	ringp->p_to_initiator[0](*signal_vci_ini_rw_proc0);
+	ringp->p_to_initiator[1](*signal_vci_ini_rw_proc1);
+	ringp->p_to_initiator[2](*signal_vci_ini_rw_proc2);
+	ringp->p_to_initiator[3](*signal_vci_ini_rw_proc3);
+	ringp->p_to_initiator[4](*signal_vci_vcibd_i);
+
+	ringc->p_to_initiator[0](*signal_vci_ini_c_proc0);
+	ringc->p_to_initiator[1](*signal_vci_ini_c_proc1);
+	ringc->p_to_initiator[2](*signal_vci_ini_c_proc2);
+	ringc->p_to_initiator[3](*signal_vci_ini_c_proc3);
+	ringc->p_to_initiator[4](*signal_vci_ini_memc);
+
+	ringp->p_to_target[0](*signal_vci_tgt_memc);
+	ringp->p_to_target[1](*signal_vci_tgt_rom);
+	ringp->p_to_target[2](*signal_vci_vcibd_t);
+	ringp->p_to_target[3](*signal_vci_tty);
+	ringp->p_to_target[4](*signal_vci_xicu);
+	ringp->p_to_target[5](*signal_vci_simh);
+	ringp->p_to_target[6](*signal_vci_fb);
+	
+	ringc->p_to_target[0](*signal_vci_tgt_proc0);
+	ringc->p_to_target[1](*signal_vci_tgt_proc1);
+	ringc->p_to_target[2](*signal_vci_tgt_proc2);
+	ringc->p_to_target[3](*signal_vci_tgt_proc3);
+	ringc->p_to_target[4](*signal_vci_tgt_cleanup_memc);
+
+
+	sc_start(sc_core::sc_time(0, SC_NS));
+	*signal_resetn = false;
+
+	sc_start(sc_core::sc_time(1, SC_NS));
+	*signal_resetn = true;
+	/*
+	 * execute 10 million cycle, compute how many time it took and
+	 * print the clock frequency
+	 */
+#ifndef DEBUG
+//#define  	STATS_CYCLES 100000000ULL
+#define  	STATS_CYCLES 1000000ULL
+	int n = 0;
+	do_debug = 0;
+no_debug:
+	proc0->iss_set_debug_mask(0);
+	proc1->iss_set_debug_mask(0);
+	proc2->iss_set_debug_mask(0);
+	proc3->iss_set_debug_mask(0);
+	while (do_debug == 0) {
+		if (gettimeofday(&t1, NULL) != 0) {
+			perror("gettimeofday");
+			return EXIT_FAILURE;
+		}
+		sc_start(STATS_CYCLES);
+		n += STATS_CYCLES;
+		if (gettimeofday(&t2, NULL) != 0) {
+			perror("gettimeofday");
+			return EXIT_FAILURE;
+		}
+		ms1 = (uint64_t)t1.tv_sec * 1000ULL + (uint64_t)t1.tv_usec / 1000;
+		ms2 = (uint64_t)t2.tv_sec * 1000ULL + (uint64_t)t2.tv_usec / 1000;
+		std::cerr << "cycle " << n << " platform clock frequency " << (double)STATS_CYCLES / (double)(ms2 - ms1) << "Khz" << std::endl;
+	}
+	proc0->iss_set_debug_mask(MIPS32_DEBUG_CPU|MIPS32_DEBUG_DATA);
+	proc1->iss_set_debug_mask(MIPS32_DEBUG_CPU|MIPS32_DEBUG_DATA);
+	proc2->iss_set_debug_mask(MIPS32_DEBUG_CPU|MIPS32_DEBUG_DATA);
+	proc3->iss_set_debug_mask(MIPS32_DEBUG_CPU|MIPS32_DEBUG_DATA);
+	while (do_debug) {
+		proc0->print_trace();
+	        signal_vci_ini_rw_proc0->print_trace("proc_ini_d");
+		signal_vci_tgt_proc0->print_trace("proc_tgt_c");
+	        signal_vci_ini_c_proc0->print_trace("proc_ini_c");
+
+		proc1->print_trace();
+	        signal_vci_ini_rw_proc1->print_trace("proc_ini_d");
+		signal_vci_tgt_proc1->print_trace("proc_tgt_c");
+	        signal_vci_ini_c_proc1->print_trace("proc_ini_c");
+
+		proc2->print_trace();
+	        signal_vci_ini_rw_proc2->print_trace("proc_ini_d");
+		signal_vci_tgt_proc2->print_trace("proc_tgt_c");
+	        signal_vci_ini_c_proc2->print_trace("proc_ini_c");
+
+		proc3->print_trace();
+	        signal_vci_ini_rw_proc3->print_trace("proc_ini_d");
+		signal_vci_tgt_proc3->print_trace("proc_tgt_c");
+	        signal_vci_ini_c_proc3->print_trace("proc_ini_c");
+
+		memc->print_trace();
+		signal_vci_tgt_memc->print_trace("memc_tgt_d");
+		signal_vci_tgt_cleanup_memc->print_trace("memc_tgt_c");
+		signal_vci_ini_memc->print_trace("memc_ini_c");
+		n++;
+		sc_start(sc_core::sc_time(1, SC_NS));
+	}
+	goto no_debug;
+	//sc_start(250000000);
+#else
+	memc->start_monitor(0x12fc, 4);
+	proc0->iss_set_debug_mask(0);
+	proc1->iss_set_debug_mask(0);
+	proc2->iss_set_debug_mask(0);
+	proc3->iss_set_debug_mask(0);
+	sc_start(DEBUG_CYCLE);
+	int n = DEBUG_CYCLE;
+	proc0->iss_set_debug_mask(MIPS32_DEBUG_CPU|MIPS32_DEBUG_DATA);
+	proc1->iss_set_debug_mask(MIPS32_DEBUG_CPU|MIPS32_DEBUG_DATA);
+	proc2->iss_set_debug_mask(MIPS32_DEBUG_CPU|MIPS32_DEBUG_DATA);
+	proc3->iss_set_debug_mask(MIPS32_DEBUG_CPU|MIPS32_DEBUG_DATA);
+#if 0
+	while (n < DEBUG_END) {
+		std::cout << "cycle " << std::dec << n << std::endl;
+		sc_start(10000);
+		n+= 10000;
+	}
+#endif
+	while (n < DEBUG_END) {
+		std::cout << "****************** cycle " << std::dec << n
+		    		<< std::endl;
+		proc0->cache_monitor(0x12fc);
+		proc0->print_trace();
+	        signal_vci_ini_rw_proc0->print_trace("proc_ini_d");
+		signal_vci_tgt_proc0->print_trace("proc_tgt_c");
+	        signal_vci_ini_c_proc0->print_trace("proc_ini_c");
+
+		proc1->print_trace();
+	        signal_vci_ini_rw_proc1->print_trace("proc_ini_d");
+		signal_vci_tgt_proc1->print_trace("proc_tgt_c");
+	        signal_vci_ini_c_proc1->print_trace("proc_ini_c");
+
+		proc2->print_trace();
+	        signal_vci_ini_rw_proc2->print_trace("proc_ini_d");
+		signal_vci_tgt_proc2->print_trace("proc_tgt_c");
+	        signal_vci_ini_c_proc2->print_trace("proc_ini_c");
+
+		proc3->print_trace();
+	        signal_vci_ini_rw_proc3->print_trace("proc_ini_d");
+		signal_vci_tgt_proc3->print_trace("proc_tgt_c");
+	        signal_vci_ini_c_proc3->print_trace("proc_ini_c");
+
+		memc->print_trace();
+		signal_vci_tgt_memc->print_trace("memc_tgt_d");
+		signal_vci_tgt_cleanup_memc->print_trace("memc_tgt_c");
+		signal_vci_ini_memc->print_trace("memc_ini_c");
+		n++;
+		sc_start(sc_core::sc_time(1, SC_NS));
+	}
+#endif
+
+	return EXIT_FAILURE;
+
+}
+
+int sc_main (int argc, char *argv[])
+{
+	try {
+		return _main(argc, argv);
+	} catch (std::exception &e) {
+		std::cout << e.what() << std::endl;
+	} catch (...) {
+		std::cout << "Unknown exception occured" << std::endl;
+		throw;
+	}
+	return 1;
+}
+
Index: branches/v4/platforms/tsarv1_mono_ring/Makefile
===================================================================
--- branches/v4/platforms/tsarv1_mono_ring/Makefile	(revision 371)
+++ branches/v4/platforms/tsarv1_mono_ring/Makefile	(revision 371)
@@ -0,0 +1,8 @@
+
+simulator.x: tsarv1_mono_ring_top.cpp tsarv1_mono_ring_desc
+	soclib-cc -P -p tsarv1_mono_ring_desc -I. -o simulator.x
+
+clean:
+	soclib-cc -x -p tsarv1_mono_ring_desc -I.
+	rm -rf *.o *.x tty*
+
Index: branches/v4/platforms/tsarv1_mono_ring/segmentation.h
===================================================================
--- branches/v4/platforms/tsarv1_mono_ring/segmentation.h	(revision 371)
+++ branches/v4/platforms/tsarv1_mono_ring/segmentation.h	(revision 371)
@@ -0,0 +1,44 @@
+/////////////////////////////////////////////////////////////////
+//	ADDRESS SPACE SEGMENTATION
+//	Author: Cesar Fuguet
+/////////////////////////////////////////////////////////////////
+
+/////////////////////////////////////////////////////////////////
+//	RESET and EXCEPTION segments
+//      Base addresses required by MIPS processor
+
+#define	KCODE_BASE	0x80000000
+#define	KCODE_SIZE	0x00004000
+
+#define	KDATA_BASE	0x80100000
+#define	KDATA_SIZE	0x00004000
+
+#define	KUNC_BASE	0x80200000
+#define	KUNC_SIZE	0x00004000
+
+#define	RESET_BASE	0xBFC00000
+#define	RESET_SIZE	0x00004000
+
+/////////////////////////////////////////////////////////////////
+//	CODE and DATA and STACK segments
+
+#define	CODE_BASE	0x00000000
+#define	CODE_SIZE	0x00004000
+
+#define DATA_BASE	0x00100000
+#define DATA_SIZE	0x00004000
+
+#define STAK_BASE	0x00800000
+#define STAK_SIZE	0x00004000
+
+#define HEAP_BASE	0x00300000
+#define HEAP_SIZE	0x00004000
+
+//////////////////////////////////////////////////////////
+//	System devices
+
+#define	TTY_BASE	0x00F10000
+#define	TTY_SIZE	0x00000010
+
+#define	XICU_BASE	0x00F00000	
+#define XICU_SIZE	0x00001000
Index: branches/v4/platforms/tsarv1_mono_ring/tsar_cluster_v1/caba/metadata/tsar_cluster_v1.sd
===================================================================
--- branches/v4/platforms/tsarv1_mono_ring/tsar_cluster_v1/caba/metadata/tsar_cluster_v1.sd	(revision 371)
+++ branches/v4/platforms/tsarv1_mono_ring/tsar_cluster_v1/caba/metadata/tsar_cluster_v1.sd	(revision 371)
@@ -0,0 +1,74 @@
+
+# -*- python -*-
+
+Module('caba:tsar_cluster_v1',
+  classname = 'soclib::caba::TsarClusterV1',
+  
+  tmpl_parameters = [
+    parameter.Module('vci_param', default = 'caba:vci_param'),
+    parameter.Int('cmd_width'),
+    parameter.Int('rsp_width'),
+  ],
+
+  header_files = [
+    '../source/include/tsar_cluster_v1.h'
+  ],
+
+  implementation_files = [
+    '../source/src/tsar_cluster_v1.cpp'
+  ],
+ 
+  uses = [
+    Uses('caba:base_module'),
+    Uses('common:loader'),
+    Uses('common:elf_file_loader'),
+    Uses('common:mapping_table'),
+    Uses(
+      'caba:vci_cc_xcache_wrapper_v1',
+      iss_t = 'common:gdb_iss',
+      gdb_iss_t = 'common:mips32el'
+    ),
+    Uses('caba:vci_mem_cache_v1'),
+    Uses('caba:vci_multi_tty'),
+    Uses('caba:vci_xicu'),
+    Uses(
+      'caba:vci_simple_ring_fast',
+      ring_cmd_data_size = parameter.Reference('cmd_width'),
+      ring_rsp_data_size = parameter.Reference('rsp_width')
+    )
+  ],
+
+  instance_parameters = [
+    parameter.Int('cluster_idx'),
+    parameter.Int('infifo_depth'),
+    parameter.Int('outfifo_depth'),
+    parameter.Int('x_local'),
+    parameter.Int('y_local'),
+    parameter.Int('x_width'),
+    parameter.Int('y_width'),
+    parameter.Module('md', 'common:mapping_table'),
+    parameter.Module('mc', 'common:mapping_table'),
+    parameter.Module('mx', 'common:mapping_table'),
+    parameter.Int('nprocs'),
+    parameter.Int('max_nprocs'),
+    parameter.Int('iwords'),
+    parameter.Int('iways'),
+    parameter.Int('isets'),
+    parameter.Int('dwords'),
+    parameter.Int('dways'),
+    parameter.Int('dsets'),
+    parameter.Int('mcwords'),
+    parameter.Int('mcways'),
+    parameter.Int('mcsets'),
+    parameter.Int('is_io'),
+  ], 
+
+  ports = [
+    Port('caba:clock_in'    , 'p_clk'           , auto = 'clock'  ),
+    Port('caba:bit_in'      , 'p_resetn'        , auto = 'resetn' ),
+
+    Port('caba:vci_initiator', 'p_vci_ixr')
+  ]
+)
+
+# vim: filetype=python : tabstop=2 : shiftwidth=2 : expandtab
Index: branches/v4/platforms/tsarv1_mono_ring/tsar_cluster_v1/caba/source/include/tsar_cluster_v1.h
===================================================================
--- branches/v4/platforms/tsarv1_mono_ring/tsar_cluster_v1/caba/source/include/tsar_cluster_v1.h	(revision 371)
+++ branches/v4/platforms/tsarv1_mono_ring/tsar_cluster_v1/caba/source/include/tsar_cluster_v1.h	(revision 371)
@@ -0,0 +1,129 @@
+#ifndef TSAR_CLUSTER_V1_H
+#define TSAR_CLUSTER_V1_H
+
+#include <systemc.h>
+#include <iostream>
+
+#include "mapping_table.h"
+#include "mips32.h"
+#include "vci_multi_tty.h"
+#include "vci_mem_cache_v1.h"
+#include "vci_cc_xcache_wrapper_v1.h"
+#include "vci_xicu.h"
+#include "vci_simple_ring_fast.h"
+#include "gdbserver.h"
+#include "vci_initiator.h"
+
+///////////////////////////////////////////////////////////
+//     TGTID & SRCID definition in direct space
+// For all components:  global TGTID = global SRCID = cluster_index
+// For processors, the local SRCID is between 0 & nprocs-1
+
+#define MEMC_TGTID	  0
+#define XICU_TGTID	  1
+#define MTTY_TGTID	  2
+
+#define PROC_SRCID    0
+
+namespace soclib { 
+  namespace caba {
+
+    template <typename vci_param, size_t cmd_width, size_t rsp_width>
+    class TsarClusterV1 : public soclib::caba::BaseModule {
+      public:
+        TsarClusterV1(
+          sc_module_name nm,
+
+          // Cluster Index
+          int cluster_idx,
+
+          // Dspin Routers parameters
+          int infifo_depth,
+          int outfifo_depth,
+          int x_local,
+          int y_local,
+
+          // Bits for global routing
+          size_t x_width,
+          size_t y_width,
+
+          // Mapping tables
+          const MappingTable & md,
+          const MappingTable & mc,
+          const MappingTable & mx,
+
+          // Processor Number
+          size_t nprocs,
+          size_t max_nprocs,
+         
+          // Cache L1 sizes
+          size_t iways,
+          size_t isets,
+          size_t iwords,
+          size_t dways,
+          size_t dsets,
+          size_t dwords,
+
+          // MemCache sizes
+          size_t mcways,
+          size_t mcsets,
+          size_t mcwords,
+
+          int    is_io,
+
+          Loader & loader
+        );
+
+        void print_trace();
+
+        ~TsarClusterV1();
+
+      private:
+        typedef soclib::common::GdbServer<soclib::common::Mips32ElIss> proc_iss;
+
+        ///////////////////////////////////////////////////////////
+        // Components
+
+        VciSimpleRingFast<vci_param,cmd_width,rsp_width> * ringd;
+        VciSimpleRingFast<vci_param,cmd_width,rsp_width> * ringc;
+
+        VciCcXCacheWrapperV1<vci_param, proc_iss> ** procs;
+        VciMemCacheV1<vci_param>                  *  memc;
+        VciXicu<vci_param>                        *  xicu;
+        VciMultiTty<vci_param>                    *  mtty;
+
+        ////////////////////////////////////////////////////////////
+        // Signals
+
+        // Direct VCI Signals
+        VciSignals<vci_param> * signal_vci_ini_d;
+        VciSignals<vci_param> * signal_vci_tgt_d;
+
+        // Coherence VCI Signals
+        VciSignals<vci_param> * signal_vci_ini_c;
+        VciSignals<vci_param> * signal_vci_tgt_c;
+
+        // Interruptions
+        sc_signal<bool> * signal_proc_irq;
+        sc_signal<bool>   signal_mtty_irq;
+
+        sc_signal<bool>   signal_false;
+
+        size_t m_nprocs;
+
+      public:
+
+        ////////////////////////////////////////////////////////////
+        // Ports
+
+        sc_in<bool> p_clk;
+        sc_in<bool> p_resetn;
+
+        soclib::caba::VciInitiator<vci_param>   p_vci_ixr;
+    };
+  }
+}
+
+#endif
+
+// vim: tabstop=2 : shiftwidth=2 : expandtab
Index: branches/v4/platforms/tsarv1_mono_ring/tsar_cluster_v1/caba/source/src/tsar_cluster_v1.cpp
===================================================================
--- branches/v4/platforms/tsarv1_mono_ring/tsar_cluster_v1/caba/source/src/tsar_cluster_v1.cpp	(revision 371)
+++ branches/v4/platforms/tsarv1_mono_ring/tsar_cluster_v1/caba/source/src/tsar_cluster_v1.cpp	(revision 371)
@@ -0,0 +1,265 @@
+#include "tsar_cluster_v1.h"
+
+#define DIRECT_TRACE
+#define COHERENCE_TRACE
+
+namespace soclib {
+  namespace caba {
+
+    template<typename vci_param, size_t cmd_width, size_t rsp_width>
+    TsarClusterV1<vci_param, cmd_width, rsp_width>::TsarClusterV1(
+      sc_module_name nm,
+
+      // Cluster Index
+      int cluster_idx,
+
+      // Dspin Routers parameters
+      int infifo_depth,
+      int outfifo_depth,
+      int x_local,
+      int y_local,
+
+      // Bits for global routing
+      size_t x_width,
+      size_t y_width,
+
+      // Mapping tables
+      const MappingTable & md,
+      const MappingTable & mc,
+      const MappingTable & mx,
+
+      // Processor Number
+      size_t nprocs,
+      size_t max_nprocs,
+     
+      // Cache L1 sizes
+      size_t iways,
+      size_t isets,
+      size_t iwords,
+      size_t dways,
+      size_t dsets,
+      size_t dwords,
+
+      // MemCache sizes
+      size_t mcways,
+      size_t mcsets,
+      size_t mcwords,
+
+      int    is_io,
+
+      Loader & loader
+    ) : soclib::caba::BaseModule(nm),
+        m_nprocs(nprocs)
+    {
+      std::ostringstream sd;
+      sd << "ringd_" << x_local << "_" << y_local;
+      ringd = new VciSimpleRingFast<vci_param, cmd_width, rsp_width> (
+        sd.str().c_str(),
+        md,                               // Direct Mapping Table
+        IntTab(),                         // Cluster index
+        2,                                // Wrapper fifo depth
+        nprocs,                           // Number of initiators
+        2 + is_io                         // Number of targets
+      );
+
+#ifdef DEBUG_TSAR_CLUSTER_V1
+      std::cout << ringd->name() << " instantiated" << std::endl;
+#endif
+
+      std::ostringstream sc;
+      sc << "ringc_" << x_local << "_" << y_local;
+      ringc = new VciSimpleRingFast<vci_param, cmd_width, rsp_width> (
+        sc.str().c_str(),
+        mc,                               // Direct Mapping Table
+        IntTab(),                         // Cluster index
+        2,                                // Wrapper fifo depth
+        nprocs + 1,                       // Number of initiators
+        max_nprocs + 1                    // Number of targets
+      );
+
+#ifdef DEBUG_TSAR_CLUSTER_V1
+      std::cout << ringc->name() << " instantiated" << std::endl;
+#endif
+
+      proc_iss::set_loader(loader);
+      procs = new VciCcXCacheWrapperV1<vci_param, proc_iss> * [nprocs];
+      for(size_t p=0; p < nprocs; p++) {
+        std::ostringstream sp;
+        sp << "proc_" << x_local << "_" << y_local << "_" << p;
+
+        procs[p] = new VciCcXCacheWrapperV1<vci_param, proc_iss> (
+          sp.str().c_str(),
+          p + nprocs*cluster_idx,         // Processor Id
+          md, mc,                         // Mapping Tables
+          IntTab(p),                      // SRCID_D
+          IntTab(p),                      // SRCID_C
+          IntTab(p),                      // TGTID_C
+          iways, isets, iwords,           // ICache Size
+          dways, dsets, dwords,           // DCache Size
+          x_width, y_width, max_nprocs    // Coherence Parameters
+        );
+    
+#ifdef DEBUG_TSAR_CLUSTER_V1
+        std::cout << procs[p]->name() << " instantiated" << std::endl;
+#endif
+      }
+
+      std::ostringstream sm;
+      sm << "memc_" << x_local << "_" << y_local;
+      memc = new VciMemCacheV1<vci_param> (
+        sm.str().c_str(),
+        md, mc, mx,                       // Mapping Tables
+        IntTab(0),                        // SRCID_X
+        IntTab(max_nprocs),               // SRCID_C
+        IntTab(0),                        // TGTID_D
+        IntTab(max_nprocs),               // TGTID_C
+        mcways, mcsets, mcwords           // MemCache Size  
+      );
+      
+#ifdef DEBUG_TSAR_CLUSTER_V1
+      std::cout << memc->name() << " instantiated" << std::endl;
+#endif
+
+      std::ostringstream sx;
+      sx << "xicu_" << x_local << "_" << y_local;
+      xicu = new VciXicu<vci_param> (
+        sx.str().c_str(),
+        md,
+        IntTab(1),                        // TGTID_D
+        nprocs,                           // number of TIMERS
+        is_io,                            // number of hard IRQs
+        nprocs,                           // number of soft IRQs
+        nprocs                            // number of output IRQ lines
+      );
+      
+#ifdef DEBUG_TSAR_CLUSTER_V1
+      std::cout << xicu->name() << " instantiated" << std::endl;
+#endif
+
+      std::ostringstream stty;
+      mtty = NULL;
+      if (is_io == 1) {
+        stty << "mtty_" << x_local << "_" << y_local;
+
+        mtty = new VciMultiTty<vci_param> (
+          stty.str().c_str(),
+          IntTab(2),
+          md,
+          "tty0", NULL
+        );
+
+#ifdef DEBUG_TSAR_CLUSTER_V1
+        std::cout << mtty->name() << " instantiated" << std::endl;
+#endif
+      }
+
+      //////////////////////////////////////////////////////////////
+      // Netlist
+
+      signal_vci_ini_d = alloc_elems<VciSignals<vci_param> >("s_vci_ini_d", nprocs);
+      signal_vci_tgt_d = alloc_elems<VciSignals<vci_param> >("s_vci_tgt_d", 2 + is_io);
+      signal_vci_ini_c = alloc_elems<VciSignals<vci_param> >("s_vci_ini_c", nprocs + 1);
+      signal_vci_tgt_c = alloc_elems<VciSignals<vci_param> >("s_vci_tgt_c", nprocs + 1);
+
+      signal_proc_irq  = new sc_signal<bool>[nprocs];
+
+      memc->p_clk               (p_clk);
+      memc->p_resetn            (p_resetn);
+      memc->p_vci_tgt           (signal_vci_tgt_d[0]);
+      memc->p_vci_ini           (signal_vci_ini_c[nprocs]);
+      memc->p_vci_tgt_cleanup   (signal_vci_tgt_c[max_nprocs]);
+      memc->p_vci_ixr           (p_vci_ixr);
+
+      for ( size_t p = 0 ; p < nprocs ; p++ ) {
+        procs[p]->p_clk        (p_clk);  
+        procs[p]->p_resetn     (p_resetn);  
+        procs[p]->p_vci_ini_rw (signal_vci_ini_d[p]);
+        procs[p]->p_vci_ini_c  (signal_vci_ini_c[p]);
+        procs[p]->p_vci_tgt    (signal_vci_tgt_c[p]);
+        procs[p]->p_irq[0]     (signal_proc_irq[p]);
+
+        for ( size_t j = 1 ; j < 6 ; j++ ) {
+          procs[p]->p_irq[j]   (signal_false); 
+        }
+      }
+
+      // XICU
+      xicu->p_clk       (p_clk);
+      xicu->p_resetn    (p_resetn);
+      xicu->p_vci       (signal_vci_tgt_d[1]);
+
+      if(is_io == 1) {
+        xicu->p_hwi[0]  (signal_mtty_irq);
+
+        mtty->p_clk     (p_clk);
+        mtty->p_resetn  (p_resetn);
+        mtty->p_vci     (signal_vci_tgt_d[2]);
+        mtty->p_irq[0]  (signal_mtty_irq);
+      }
+
+      for ( size_t p = 0 ; p < nprocs ; p++ ) {
+        xicu->p_irq[p]  (signal_proc_irq[p]);
+      }
+
+      // Direct ring
+      ringd->p_clk                    (p_clk);
+      ringd->p_resetn                 (p_resetn);
+
+      for ( size_t p = 0 ; p < nprocs ; p++ ) {
+        ringd->p_to_initiator[p]      (signal_vci_ini_d[p]);
+      }
+
+      for ( int t = 0 ; t < (2 + is_io) ; t++ ) {
+        ringd->p_to_target[t]         (signal_vci_tgt_d[t]);
+      }
+
+      // Coherence ring
+      ringc->p_clk                    (p_clk);
+      ringc->p_resetn                 (p_resetn);
+
+      for ( size_t i = 0 ; i < (nprocs + 1) ; i++ ) {
+        ringc->p_to_initiator[i]      (signal_vci_ini_c[i]);
+      }
+
+      for ( size_t t = 0 ; t < (max_nprocs + 1) ; t++ ) {
+        ringc->p_to_target[t]         (signal_vci_tgt_c[t]);
+      }
+    } // End TsarClusterV1
+
+    template<typename vci_param, size_t cmd_width, size_t rsp_width>
+    void TsarClusterV1<vci_param, cmd_width, rsp_width>::print_trace() {
+      #ifdef DIRECT_TRACE
+      ringd->print_trace();
+      #endif
+      #ifdef COHERENCE_TRACE
+      ringc->print_trace();
+      #endif
+    }
+
+    template<typename vci_param, size_t cmd_width, size_t rsp_width>
+    TsarClusterV1<vci_param, cmd_width, rsp_width>::~TsarClusterV1() {
+      for(size_t p=0; p < m_nprocs; p++) {
+        delete procs[p];
+      }
+      delete [] procs;
+      delete ringd;
+      delete ringc;
+      delete memc;
+      delete xicu;
+
+      if(mtty) {
+        delete mtty;
+        dealloc_elems<VciSignals<vci_param> >(signal_vci_tgt_d, 3);
+      } else {
+        dealloc_elems<VciSignals<vci_param> >(signal_vci_tgt_d, 2);
+      }
+
+      dealloc_elems<VciSignals<vci_param> >(signal_vci_ini_d, m_nprocs);
+      dealloc_elems<VciSignals<vci_param> >(signal_vci_ini_c, m_nprocs + 1);
+      dealloc_elems<VciSignals<vci_param> >(signal_vci_tgt_c, m_nprocs + 1);
+      delete [] signal_proc_irq;
+    }
+  }
+}
+
+// vim: tabstop=2 : shiftwidth=2 : expandtab
Index: branches/v4/platforms/tsarv1_mono_ring/tsarv1_mono_ring_desc
===================================================================
--- branches/v4/platforms/tsarv1_mono_ring/tsarv1_mono_ring_desc	(revision 371)
+++ branches/v4/platforms/tsarv1_mono_ring/tsarv1_mono_ring_desc	(revision 371)
@@ -0,0 +1,24 @@
+
+# -*- python -*-
+
+todo = Platform(
+  'caba', 'tsarv1_mono_ring_top.cpp',
+  uses = [
+      Uses('caba:tsar_cluster_v1', cmd_width = 40, rsp_width = 33),
+      Uses('caba:vci_simple_ram'),
+      Uses('common:elf_file_loader'),
+  ],
+
+  cell_size = 4,
+  plen_size = 8,
+  addr_size = 32,
+  rerror_size = 1,
+  clen_size = 1,
+  rflag_size = 1,
+  srcid_size = 5,
+  pktid_size = 4,
+  trdid_size = 4,
+  wrplen_size = 1,
+)
+
+# vim: tabstop=2 : shiftwidth=2 : expandtab
Index: branches/v4/platforms/tsarv1_mono_ring/tsarv1_mono_ring_top.cpp
===================================================================
--- branches/v4/platforms/tsarv1_mono_ring/tsarv1_mono_ring_top.cpp	(revision 371)
+++ branches/v4/platforms/tsarv1_mono_ring/tsarv1_mono_ring_top.cpp	(revision 371)
@@ -0,0 +1,421 @@
+/////////////////////////////////////////////////////////////////////////
+// File:      tsarv1_mono_ring_top.cpp
+// Author:    Cesar Fuguet / Abdelmalek Simerabe
+// Copyright: UPMC/LIP6
+// Date :     2012
+//
+// This program is released under the GNU public license
+/////////////////////////////////////////////////////////////////////////
+
+#include <systemc>
+#include <sys/time.h>
+#include <iostream>
+#include <sstream>
+#include <cstdlib>
+#include <cstdarg>
+
+#include "tsar_cluster_v1.h"
+#include "mapping_table.h"
+#include "vci_simple_ring_fast.h"
+#include "vci_simple_ram.h"
+#include "segmentation.h"
+
+///////////////////////////////////
+// flit widths for the ring network
+
+#define cmd_width	    40
+#define rsp_width	    33
+
+//////////////////
+// VCI format
+
+#define cell_width	  4
+#define address_width	32
+#define plen_width	  8
+#define error_width	  1
+#define clen_width	  1
+#define rflag_width	  1
+#define srcid_width	  5
+#define pktid_width	  4
+#define trdid_width	  4
+#define wrplen_width  1
+
+/////////////////////////////////
+int _main(int argc, char *argv[])
+{
+    using namespace sc_core;
+    using namespace soclib::caba;
+    using namespace soclib::common;
+
+    char    soft_name[128]  = "undefined_binary_file";  // pathname to binary code
+    size_t  ncycles         = 200000;           	      // simulated cycles
+    size_t  xmax            = 1;         		            // number of clusters in a row
+    size_t  ymax            = 1;                	      // number of clusters in a column
+    size_t  nprocs          = 1;         		            // number of processors per cluster
+    bool    debug_ok        = false;            	      // debug activated
+    size_t  from_cycle      = 0;                      	// debug start cycle
+    size_t  to_cycle        = 200000;           	      // debug end cycle
+
+    ////////////// command line arguments //////////////////////
+    if (argc > 1)
+    {
+        for( int n=1 ; n<argc ; n=n+2 )
+        {
+            if( (strcmp(argv[n],"-NCYCLES") == 0) && (n+1<argc) )
+            {
+                ncycles = atoi(argv[n+1]);
+            }
+            else if( (strcmp(argv[n],"-NPROCS") == 0) && (n+1<argc) )
+            {
+                nprocs = atoi(argv[n+1]);
+                assert( (nprocs <= 8) 
+                    && "The number of processors per cluster cannot be larger than 8");
+            }
+            else if( (strcmp(argv[n],"-SOFT") == 0) && (n+1<argc) )
+            {
+                strcpy(soft_name, argv[n+1]);
+            }
+            else if( (strcmp(argv[n],"-DEBUG") == 0) && (n+1<argc) )
+            {
+                debug_ok = true;
+                from_cycle = atoi(argv[n+1]);
+            }
+            else if( (strcmp(argv[n],"-TOCYCLE") == 0) && (n+1<argc) )
+            {
+                to_cycle = atoi(argv[n+1]);
+            }
+            else
+            {
+                std::cout << "   Arguments on the command line are (key,value) ";
+                std::cout << "couples." << std::endl;
+                std::cout << "   The order is not important." << std::endl;
+                std::cout << "   Accepted arguments are :" << std::endl << std::endl;
+                std::cout << "     -SOFT elf_file_name" << std::endl;
+                std::cout << "     -NCYCLES number_of_simulated_cycles" << std::endl;
+                std::cout << "     -NPROCS number_of_processors_per_cluster" << std::endl;
+                std::cout << "     -DEBUG debug_start_cycle" << std::endl;
+                std::cout << "     -TOCYCLE debug_end_cycle" << std::endl;
+                exit(0);
+            }
+        }
+    }
+
+    std::cout << std::endl << "***********  TSAR ARCHITECTURE  **************" << std::endl
+              << " - Interconnect = DSPIN & RING" << std::endl
+              << " - Number of clusters = " << xmax << " * " << ymax << std::endl
+              << " - Number of processors per cluster = " << nprocs << std::endl
+              << "**********************************************" << std::endl
+              << std::endl;
+
+    // Define VCI parameters
+    typedef soclib::caba::VciParams<cell_width,
+                                    plen_width,
+                                    address_width,
+                                    error_width,                                   
+                                    clen_width,
+                                    rflag_width,
+                                    srcid_width,
+                                    pktid_width,
+                                    trdid_width,
+                                    wrplen_width> vci_param;
+
+    size_t x_width = 0;
+    size_t y_width = 0;
+
+    /////////////////////
+    //  Mapping Tables
+    /////////////////////
+
+    // direct network
+    MappingTable maptabd(address_width, 
+                         IntTab(16 - x_width - y_width), 
+                         IntTab(srcid_width - x_width - y_width), 
+                         0x00FF0000);
+
+    maptabd.add(
+        Segment("d_seg_xicu", 
+          XICU_BASE,
+          XICU_SIZE, 
+          IntTab(XICU_TGTID), 
+          false
+          )
+        );
+
+    maptabd.add(
+        Segment("d_seg_stak",
+          STAK_BASE,
+          STAK_SIZE,
+          IntTab(MEMC_TGTID),
+          true
+          )
+        );
+
+    maptabd.add(
+        Segment("d_seg_mtty",
+          TTY_BASE,
+          TTY_SIZE,
+          IntTab(MTTY_TGTID),
+          false
+          )
+        );
+
+    maptabd.add(
+        Segment("d_seg_reset",
+          RESET_BASE,
+          RESET_SIZE,
+          IntTab(MEMC_TGTID),
+          true
+          )
+        );
+
+    maptabd.add(
+        Segment("d_seg_kcode",
+          KCODE_BASE,
+          KCODE_SIZE,
+          IntTab(MEMC_TGTID),
+          true
+          )
+        );
+
+    maptabd.add(
+        Segment("d_seg_kdata",
+          KDATA_BASE,
+          KDATA_SIZE,
+          IntTab(MEMC_TGTID),
+          true
+          )
+        );
+
+    maptabd.add(
+        Segment("d_seg_kunc",
+          KUNC_BASE,
+          KUNC_SIZE,
+          IntTab(MEMC_TGTID),
+          false
+          )
+        );
+
+    maptabd.add(
+        Segment("d_seg_code",
+          CODE_BASE,
+          CODE_SIZE,
+          IntTab(MEMC_TGTID),
+          true
+          )
+        );
+
+    maptabd.add(
+        Segment("d_seg_data",
+          DATA_BASE,
+          DATA_SIZE,
+          IntTab(MEMC_TGTID),
+          true
+          )
+        );
+    std::cout << maptabd << std::endl;
+
+    // coherence network
+    MappingTable maptabc(address_width,
+        IntTab(srcid_width - x_width - y_width),
+        IntTab(srcid_width - x_width - y_width),
+        0xFF000000);
+
+    std::ostringstream sm;
+    sm << "c_seg_memc_" << 0 << "_" << 0;
+    maptabc.add(
+        Segment(sm.str(),
+          (nprocs << (address_width - srcid_width)),
+          0xC,
+          IntTab(nprocs),
+          false
+          )
+        );
+
+    for ( size_t p = 0 ; p < nprocs ; p++)
+    {
+      std::ostringstream sp;
+      sp << "c_seg_proc_" << 0 << "_" << 0 << "_" << p;
+      maptabc.add(
+          Segment(sp.str(),
+            (p << (address_width - srcid_width)),
+            0xC,
+            IntTab(p),
+            false
+            )
+          );
+    }
+    std::cout << maptabc << std::endl;
+
+    // external network
+    MappingTable maptabx(
+      address_width,
+      IntTab(x_width + y_width),
+      IntTab(x_width + y_width),
+      0x00FF0000
+    );
+
+    maptabx.add(
+      Segment("x_seg_kcode",
+        KCODE_BASE,
+        KCODE_SIZE,
+        IntTab(0),
+        false
+      )
+    );
+
+    maptabx.add(
+      Segment("x_seg_kdata",
+        KDATA_BASE,
+        KDATA_SIZE,
+        IntTab(0),
+        false
+      )
+    );
+
+    maptabx.add(
+      Segment("x_seg_kunc",
+        KUNC_BASE,
+        KUNC_SIZE,
+        IntTab(0),
+        false
+      )
+    );
+
+    maptabx.add(
+      Segment("x_seg_code",
+        CODE_BASE,
+        CODE_SIZE,
+        IntTab(0),
+        false
+      )
+    );
+
+    maptabx.add(
+      Segment("x_seg_reset",
+        RESET_BASE,
+        RESET_SIZE,
+        IntTab(0),
+        false
+      )
+    );
+
+    maptabx.add(
+      Segment("x_seg_data",
+        DATA_BASE,
+        DATA_SIZE,
+        IntTab(0),
+        false
+      )
+    );
+    
+    maptabx.add(
+        Segment("x_seg_stak",
+          STAK_BASE,
+          STAK_SIZE,
+          IntTab(0),
+          false
+          )
+        );
+    std::cout << maptabx << std::endl;
+
+    ////////////////////
+    // Signals
+    ///////////////////
+
+    sc_clock		    signal_clk("clk");
+    sc_signal<bool> signal_resetn("resetn");
+
+    // Xternal network VCI signals
+    VciSignals<vci_param> signal_vci_tgt_x_xram("signal_vci_tgt_x_xram");
+
+    ////////////////////////////
+    //      Components
+    ////////////////////////////
+
+    soclib::common::Loader loader(soft_name);
+
+    cout << loader << endl;
+
+    // TSAR Clusters
+    TsarClusterV1<vci_param, cmd_width, rsp_width> * cluster;
+    std::ostringstream scluster;
+    scluster << "cluster_" << 0 << "_" << 0;
+
+    cluster = new TsarClusterV1<vci_param, cmd_width, rsp_width> (
+        scluster.str().c_str(),
+        0,                          // Cluster index
+        4,4,                        // Router fifo's depth
+        0,0,                        // X, Y coordinates
+        x_width, y_width,           // Global routing bits
+        maptabd, maptabc, maptabx,  // Mapping Tables
+        nprocs,                     // Number of processors in the cluster
+        nprocs,                     // Maximum number of processors per cluster
+        4,32,16,/**/4,32,16,  		  // Icache and Dcache sizes
+        4,32,16,				            // MemCache size
+        1,                          // Is IO cluster
+        loader                      // Program Loader
+        ); 
+
+    // External RAM
+    VciSimpleRam<vci_param> xram(
+        "xram", 
+        IntTab(0), 
+        maptabx, 
+        loader);
+
+    ///////////////////////////////////////////////////////////////
+    //     Net-list 
+    ///////////////////////////////////////////////////////////////
+
+    // External Ram (one instance)
+    xram.p_clk						(signal_clk);
+    xram.p_resetn					(signal_resetn);
+    xram.p_vci						(signal_vci_tgt_x_xram);	
+
+    // Connection with the external network
+    cluster->p_vci_ixr(signal_vci_tgt_x_xram);
+
+    // Clock and Reset
+    cluster->p_clk(signal_clk);
+    cluster->p_resetn(signal_resetn);
+
+    ////////////////////////////////////////////////////////
+    //   Simulation
+    ///////////////////////////////////////////////////////
+
+    sc_start(sc_core::sc_time(0, SC_NS));
+    signal_resetn = false;
+
+    sc_start(sc_core::sc_time(1, SC_NS));
+    signal_resetn = true;
+
+    for(size_t i=1 ; i<ncycles ; i++)
+    {
+        sc_start(sc_core::sc_time(1, SC_NS));
+
+        if(debug_ok) {
+          cluster->print_trace();
+        }
+    }
+
+    std::cout << "Hit ENTER to end simulation" << std::endl;
+    char buf[1];
+    std::cin.getline(buf,1);
+
+    return EXIT_SUCCESS;
+}
+
+int sc_main (int argc, char *argv[])
+{
+	try {
+		return _main(argc, argv);
+	} catch (std::exception &e) {
+		std::cout << e.what() << std::endl;
+	} catch (...) {
+		std::cout << "Unknown exception occured" << std::endl;
+		throw;
+	}
+	return 1;
+}
+
+// vim: tabstop=2 shiftwidth=2 expandtab softtabstop=2
Index: branches/v4/platforms/tsarv2_mutekh/Makefile
===================================================================
--- branches/v4/platforms/tsarv2_mutekh/Makefile	(revision 371)
+++ branches/v4/platforms/tsarv2_mutekh/Makefile	(revision 371)
@@ -0,0 +1,11 @@
+ARCH=mips32el
+SIMULATION_ARGS=mutekh/kernel-soclib-mips.out
+SOCLIB_CC_ADD_ARGS=-t systemcass
+SOCLIB?=$(shell soclib-cc --getpath)
+NO_SOFT=1
+SIMULATOR_BINARY=tsarv2_platform.x
+export SOCLIB
+SOCLIB_CC_ARGS=-p $(PLATFORM_DESC) 
+include $(SOCLIB)/soclib/platform/topcells/all.mk
+
+
Index: branches/v4/platforms/tsarv2_mutekh/mutekh/.config.deps
===================================================================
--- branches/v4/platforms/tsarv2_mutekh/mutekh/.config.deps	(revision 371)
+++ branches/v4/platforms/tsarv2_mutekh/mutekh/.config.deps	(revision 371)
@@ -0,0 +1,95 @@
+##
+## This file has been generated by the configuration script.
+##
+
+/tmp/mutekh_config.17716.23609.h \
+/tmp/mutekh_config.17716.23609.mk \
+/tmp/mutekh_config.17716.23609.m4 \
+/tmp/mutekh_config.17716.23609.py \
+: \
+	/home/guthmuller/dev/mutekh/arch/arch.config \
+	/home/guthmuller/dev/mutekh/arch/emu/emu.config \
+	/home/guthmuller/dev/mutekh/arch/ibmpc/ibmpc.config \
+	/home/guthmuller/dev/mutekh/arch/simple/atmega/atmega.config \
+	/home/guthmuller/dev/mutekh/arch/simple/sam7/sam7.config \
+	/home/guthmuller/dev/mutekh/arch/simple/simple.config \
+	/home/guthmuller/dev/mutekh/arch/soclib/soclib.config \
+	/home/guthmuller/dev/mutekh/cpu/arm/arm.config \
+	/home/guthmuller/dev/mutekh/cpu/avr/avr.config \
+	/home/guthmuller/dev/mutekh/cpu/cpu.config \
+	/home/guthmuller/dev/mutekh/cpu/mips/mips.config \
+	/home/guthmuller/dev/mutekh/cpu/ppc/ppc.config \
+	/home/guthmuller/dev/mutekh/cpu/x86/x86.config \
+	/home/guthmuller/dev/mutekh/cpu/x86-64-emu/emu.config \
+	/home/guthmuller/dev/mutekh/cpu/x86-emu/emu.config \
+	/home/guthmuller/dev/mutekh/drivers/device/block/ata/block-ata.config \
+	/home/guthmuller/dev/mutekh/drivers/device/block/cache/block-cache.config \
+	/home/guthmuller/dev/mutekh/drivers/device/block/file-emu/block-file-emu.config \
+	/home/guthmuller/dev/mutekh/drivers/device/block/partition/block-partition.config \
+	/home/guthmuller/dev/mutekh/drivers/device/block/ramdisk/block-ramdisk.config \
+	/home/guthmuller/dev/mutekh/drivers/device/block/sd-mmc/sd-mmc.config \
+	/home/guthmuller/dev/mutekh/drivers/device/block/soclib/block-soclib.config \
+	/home/guthmuller/dev/mutekh/drivers/device/char/dbgu-sam7/dbgu-sam7.config \
+	/home/guthmuller/dev/mutekh/drivers/device/char/null/null.config \
+	/home/guthmuller/dev/mutekh/drivers/device/char/random/random.config \
+	/home/guthmuller/dev/mutekh/drivers/device/char/tty-emu/tty-emu.config \
+	/home/guthmuller/dev/mutekh/drivers/device/char/tty-soclib/tty-soclib.config \
+	/home/guthmuller/dev/mutekh/drivers/device/char/tty-vga/tty-vga.config \
+	/home/guthmuller/dev/mutekh/drivers/device/char/uart-8250/uart-8250.config \
+	/home/guthmuller/dev/mutekh/drivers/device/char/uart-us6089c/uart-us6089c.config \
+	/home/guthmuller/dev/mutekh/drivers/device/char/zero/zero.config \
+	/home/guthmuller/dev/mutekh/drivers/device/drivers.config \
+	/home/guthmuller/dev/mutekh/drivers/device/enum/fdt/enum-fdt.config \
+	/home/guthmuller/dev/mutekh/drivers/device/enum/isapnp/enum-isapnp.config \
+	/home/guthmuller/dev/mutekh/drivers/device/enum/pci/enum-pci.config \
+	/home/guthmuller/dev/mutekh/drivers/device/enum/root/enum-root.config \
+	/home/guthmuller/dev/mutekh/drivers/device/fb/soclib/fb-soclib.config \
+	/home/guthmuller/dev/mutekh/drivers/device/fb/vga/fb-vga.config \
+	/home/guthmuller/dev/mutekh/drivers/device/gpio/sam7/gpio-sam7.config \
+	/home/guthmuller/dev/mutekh/drivers/device/i2c/twi6061a/i2c-twi6061a.config \
+	/home/guthmuller/dev/mutekh/drivers/device/icu/8259/icu-8259.config \
+	/home/guthmuller/dev/mutekh/drivers/device/icu/arm/icu-arm.config \
+	/home/guthmuller/dev/mutekh/drivers/device/icu/mips/icu-mips.config \
+	/home/guthmuller/dev/mutekh/drivers/device/icu/ppc/icu-ppc.config \
+	/home/guthmuller/dev/mutekh/drivers/device/icu/sam7/icu-sam7.config \
+	/home/guthmuller/dev/mutekh/drivers/device/icu/soclib-icu/icu-soclib.config \
+	/home/guthmuller/dev/mutekh/drivers/device/icu/soclib-xicu/xicu.config \
+	/home/guthmuller/dev/mutekh/drivers/device/input/8042/input-8042.config \
+	/home/guthmuller/dev/mutekh/drivers/device/input/mt5-f/mt5-f.config \
+	/home/guthmuller/dev/mutekh/drivers/device/lcd/pcf8833/pcf8833.config \
+	/home/guthmuller/dev/mutekh/drivers/device/lcd/s1d15g00/s1d15g00.config \
+	/home/guthmuller/dev/mutekh/drivers/device/mem/memory/memory.config \
+	/home/guthmuller/dev/mutekh/drivers/device/net/ne2000/net-ne2000.config \
+	/home/guthmuller/dev/mutekh/drivers/device/net/tuntap/net-tuntap.config \
+	/home/guthmuller/dev/mutekh/drivers/device/spi/spi6088d/spi-spi6088d.config \
+	/home/guthmuller/dev/mutekh/drivers/device/timer/8253/timer-8253.config \
+	/home/guthmuller/dev/mutekh/drivers/device/timer/emu/timer-emu.config \
+	/home/guthmuller/dev/mutekh/drivers/device/timer/pitc_6079a/pitc_6079a.config \
+	/home/guthmuller/dev/mutekh/drivers/device/timer/soclib/timer-soclib.config \
+	/home/guthmuller/dev/mutekh/drivers/fs/devfs/devfs.config \
+	/home/guthmuller/dev/mutekh/drivers/fs/fat/fat.config \
+	/home/guthmuller/dev/mutekh/drivers/fs/iso9660/iso9660.config \
+	/home/guthmuller/dev/mutekh/drivers/fs/ramfs/ramfs.config \
+	/home/guthmuller/dev/mutekh/hexo/hexo.config \
+	/home/guthmuller/dev/mutekh/libc/libc.config \
+	/home/guthmuller/dev/mutekh/libcrypto/crypto.config \
+	/home/guthmuller/dev/mutekh/libdsrl/dsrl.config \
+	/home/guthmuller/dev/mutekh/libelf/libelf.config \
+	/home/guthmuller/dev/mutekh/libfdt/fdt.config \
+	/home/guthmuller/dev/mutekh/liblua/liblua.config \
+	/home/guthmuller/dev/mutekh/libm/libm.config \
+	/home/guthmuller/dev/mutekh/libmwmr/mwmr.config \
+	/home/guthmuller/dev/mutekh/libnetwork/dhclient/dhclient.config \
+	/home/guthmuller/dev/mutekh/libnetwork/libsocket/socket.config \
+	/home/guthmuller/dev/mutekh/libnetwork/lwnfs/lwnfs.config \
+	/home/guthmuller/dev/mutekh/libnetwork/network.config \
+	/home/guthmuller/dev/mutekh/libnetwork/ping/ping.config \
+	/home/guthmuller/dev/mutekh/libnetwork/rarp/rarp.config \
+	/home/guthmuller/dev/mutekh/libpthread/pthread.config \
+	/home/guthmuller/dev/mutekh/libsrl/srl.config \
+	/home/guthmuller/dev/mutekh/libtermui/termui.config \
+	/home/guthmuller/dev/mutekh/libunix/unix.config \
+	/home/guthmuller/dev/mutekh/libvfs/vfs.config \
+	/home/guthmuller/dev/mutekh/mutek/mutek.config \
+	/home/guthmuller/dev/mutekh/scripts/global.config \
+	/home/guthmuller/dev/mutekh/scripts/license.config
Index: branches/v4/platforms/tsarv2_mutekh/mutekh/.config.h
===================================================================
--- branches/v4/platforms/tsarv2_mutekh/mutekh/.config.h	(revision 371)
+++ branches/v4/platforms/tsarv2_mutekh/mutekh/.config.h	(revision 371)
@@ -0,0 +1,292 @@
+/*
+ * This file has been generated by the configuration script.
+ */
+
+#define CONFIG_MUTEK_MEMALLOC_ALGO_FIRSTFIT
+#undef  CONFIG_VFS_STATS
+#undef  CONFIG_NETWORK_SOCKET_PACKET
+#undef  CONFIG_DRIVER_FS_FAT_RW
+#undef  CONFIG_DRIVER_BLOCK_EMU_BLOCKSIZE
+#undef  CONFIG_SRL_SOCLIB
+#undef  CONFIG_DRIVER_BLOCK_EMU
+#define CONFIG_CPU_RESET_ADDR 0xbfc00000
+#undef  CONFIG_ARCH_SIMPLE_HW_INIT
+#undef  CONFIG_DRIVER_SPI
+#undef  CONFIG_LICENSE_APP_PROPRIETARY
+#undef  CONFIG_HET_BUILD
+#undef  CONFIG_DEBUG
+#undef  CONFIG_DRIVER_BLOCK_RAMDISK_SIZE
+#undef  CONFIG_LIBCRYPTO_MD5
+#undef  CONFIG_DRIVER_FS_FAT
+#undef  CONFIG_DRIVER_I2C_TWI6061A
+#undef  CONFIG_HEXO_INTTYPES_DEPRECATED
+#undef  CONFIG_DRIVER_BLOCK_SOCLIB
+#undef  CONFIG_VFS_VERBOSE
+#undef  CONFIG_CPU_X86_64_EMU
+#define CONFIG_ARCH_NAME soclib
+#undef  CONFIG_DRIVER_NET_NE2000
+#undef  CONFIG_CPU_MIPS_ABI_N32
+#undef  CONFIG_ARCH_SIMPLE_SAM7
+#undef  CONFIG_DRIVER_FS_RAMFS
+#define CONFIG_MUTEK_PRINTK
+#define CONFIG_DRIVER_ICU_MIPS
+#define CONFIG_MUTEK_SCHEDULER_IDLE_STACK_SIZE 2048
+#undef  CONFIG_DRIVER_ICU_8259
+#define CONFIG_PTHREAD_JOIN
+#undef  CONFIG_MUTEK_MEMALLOC_GUARD_SIZE
+#define CONFIG_ROM_SIZE 0x01000000
+#undef  CONFIG_LICENSE_USE_GPL
+#undef  CONFIG_NETWORK_AUTOALIGN
+#undef  CONFIG_DRIVER_LCD_S1D15G00
+#undef  CONFIG_VMEM_KERNEL_ALLOC
+#undef  CONFIG_ARCH_SIMPLE_OLIMEX_SAM7_EX256
+#undef  CONFIG_ARCH_HW_INIT
+#undef  CONFIG_VMEM
+#define CONFIG_LICENSE_APP_LGPL
+#undef  CONFIG_CPU_ARM_FPU
+#define CONFIG_CPU_RESET_HANDLER
+#undef  CONFIG_DRIVER_BLOCK
+#undef  CONFIG_CPU_USER
+#undef  CONFIG_NETWORK_NFS
+#undef  CONFIG_VMEM_PHYS_ALLOC
+#undef  CONFIG_MUTEK_MEMALLOC_GUARD_INSTRUMENT
+#undef  CONFIG_MWMR_USE_RAMLOCKS
+#undef  CONFIG_DRIVER_NET_NE2000_FRAGMENT
+#define CONFIG_CPU_CACHE_LINE 4
+#undef  CONFIG_HEXO_ARCH_MMU
+#undef  CONFIG_DRIVER_BLOCK_CACHE_SIZE
+#undef  CONFIG_NETWORK_SOCKET
+#define CONFIG_DRIVER_CHAR_SOCLIBTTY
+#undef  CONFIG_LIBCRYPTO_CRC32_SMALL
+#undef  CONFIG_DRIVER_BLOCK_RAMDISK_BLOCKSIZE
+#undef  CONFIG_CPU_CACHE_COHERENCY
+#undef  CONFIG_MUTEK_MEMALLOC_SIGNED
+#undef  CONFIG_DRIVER_FS_DEVFS
+#undef  CONFIG_NETWORK_PACKET_ASM
+#define CONFIG_COMPILE_SIZEOF_INT 4
+#undef  CONFIG_NETWORK_FORWARDING
+#undef  CONFIG_CLUSTER
+#define CONFIG_MUTEK_MAIN
+#undef  CONFIG_UNIX_STACK_VADDR
+#undef  CONFIG_NETWORK_SOCKET_RAW
+#undef  CONFIG_LIBELF_DEBUG
+#undef  CONFIG_DRIVER_FS_ISO9660
+#undef  CONFIG_DRIVER_I2C
+#undef  CONFIG_ARCH_IBMPC_DMA
+#define CONFIG_CPU_ENDIAN_LITTLE
+#define CONFIG_LIBC_SEMAPHORE
+#undef  CONFIG_UNIX_START_VADDR
+#undef  CONFIG_ARCH_EMU
+#undef  CONFIG_SOCLIB_MEMCHECK
+#undef  CONFIG_DRIVER_FB
+#define CONFIG_CPU_MIPS_ABI_O32
+#define CONFIG_DRIVER_MEM_MEMORY
+#undef  CONFIG_DRIVER_FB_SOCLIB
+#undef  CONFIG_ARCH_EMU_DARWIN
+#define CONFIG_ROM_ADDR 0x61100000
+#define CONFIG_DRIVER_ENUM_ROOT
+#undef  CONFIG_DRIVER_TIMER_SOCLIB
+#define CONFIG_COMPILE_FRAMEPTR
+#undef  CONFIG_LIBDSRL_DEBUG
+#undef  CONFIG_DRIVER_CHAR_NULL
+#undef  CONFIG_MWMR_PTHREAD
+#undef  CONFIG_MWMR_LOCKFREE
+#undef  CONFIG_DRIVER_FS_FAT32
+#undef  CONFIG_DRIVER_BLOCK_SD_MMC
+#undef  CONFIG_NETWORK_UDP
+#undef  CONFIG_NETWORK_IPV4
+#undef  CONFIG_HEXO_MMU_PAGESIZE
+#undef  CONFIG_CPU_X86_EMU
+#undef  CONFIG_NETWORK_DHCLIENT
+#define CONFIG_CPU_CACHE
+#undef  CONFIG_LICENSE_APP_PUBLIC
+#undef  CONFIG_LIBTERMUI
+#undef  CONFIG_MUTEK_MEMALLOC_DEBUG
+#undef  CONFIG_CPU_AVR_GCCMCU
+#undef  CONFIG_ARCH_SOCLIB_RAMLOCK
+#undef  CONFIG_VFS_NAMELEN
+#undef  CONFIG_ARCH_SIMPLE_SAM7X256
+#undef  CONFIG_DRIVER_CHAR_UART8250
+#undef  CONFIG_CPU_ARM_7TDMI
+#define CONFIG_CPU_NAME mips
+#undef  CONFIG_DRIVER_CHAR_VGATTY_KEYBOARD
+#undef  CONFIG_DRIVER_BLOCK_ATA
+#define CONFIG_MUTEK_CONSOLE
+#undef  CONFIG_LIBELF
+#undef  CONFIG_DRIVER_LCD
+#undef  CONFIG_DRIVER_CHAR_SAM7DBGU
+#undef  CONFIG_LICENSE_USE_PUBLIC
+#undef  CONFIG_DRIVER_ENUM_PCI
+#undef  CONFIG_DRIVER_GPIO
+#define CONFIG_CPU_RESET_SIZE 0x2000
+#undef  CONFIG_SRL_STD
+#define CONFIG_LIBC_STREAM
+#undef  CONFIG_ARCH_EMU_LINUX
+#undef  CONFIG_CPU_AVR
+#undef  CONFIG_LICENSE_APP_BSD
+#undef  CONFIG_NETWORK_TCP
+#undef  CONFIG_CPU_PPC
+#undef  CONFIG_ARCH_SIMPLE_RESET_ADDR
+#undef  CONFIG_ARCH_IBMPC
+#undef  CONFIG_CPU_NONALIGNED_ACCESS
+#define CONFIG_CPU_EXCEPTION_ALIGN 0x00001000
+#undef  CONFIG_MUTEK_NUMA
+#undef  CONFIG_DRIVER_ICU_SOCLIB
+#define CONFIG_DRIVER_ENUM_FDT
+#undef  CONFIG_MUTEK_SCHEDULER_CANDIDATE_FCN
+#undef  CONFIG_DRIVER_BLOCK_CACHE
+#define CONFIG_COMPILE_SAVETEMPS
+#undef  CONFIG_HEXO_MMU_VADDR
+#undef  CONFIG_HETROM_SIZE
+#undef  CONFIG_DRIVER_ICU_ARM
+#define CONFIG_PRINTF_ARG_EXT
+#undef  CONFIG_LIBELF_DYNAMIC
+#undef  CONFIG_DRIVER_FS_FAT16
+#undef  CONFIG_DRIVER_CHAR_US6089C_UART
+#define CONFIG_DRIVER_ICU
+#undef  CONFIG_SRL_MULTI_TTY
+#undef  CONFIG_COMPILE_INSTRUMENT
+#undef  CONFIG_CPU_MIPS_ABI_O64
+#undef  CONFIG_DRIVER_CHAR_VGATTY_ANSI
+#define CONFIG_FDT
+#undef  CONFIG_CPU_EXCEPTION_FIXED_ADDRESS
+#undef  CONFIG_ARCH_SIMPLE
+#define CONFIG_SOCLIB_VMEM_MALLOC_REGION_SIZE 0x8000
+#undef  CONFIG_HEXO_CPU_MMU
+#define CONFIG_CPU_MAXCOUNT 4
+#undef  CONFIG_DRIVER_NET
+#define CONFIG_DRIVER_BLOCK_PARTITION_MAXCOUNT 32
+#define CONFIG_DRIVER_ICU_SOCLIB_XICU
+#define CONFIG_ARCH_DEVICE_TREE
+#undef  CONFIG_CPU_AVR_IRQ_COUNT
+#define CONFIG_PTHREAD
+#undef  CONFIG_VFS_GLOBAL_CWD
+#define CONFIG_CPU_MIPS
+#define CONFIG_COMPILE_SOFTFLOAT
+#undef  CONFIG_NETWORK_RARP
+#define CONFIG_PTHREAD_CANCEL
+#undef  CONFIG_CPU_ARM_M_PROFILE
+#undef  CONFIG_MUTEK_MEMALLOC_SIMPLE
+#define CONFIG_LIBCRYPTO
+#define CONFIG_DRIVER_TTY
+#define CONFIG_LIBC_ASSERT
+#undef  CONFIG_CPU_ARM_TLS_IN_C15
+#undef  CONFIG_CPU_AVR_ENHANCED
+#undef  CONFIG_DRIVER_TIMER_PITC_6079A
+#undef  CONFIG_DRIVER_ENUM_ISAPNP
+#undef  CONFIG_CPU_ENDIAN_BIG
+#undef  CONFIG_CPU_X86
+#undef  CONFIG_MWMR
+#undef  CONFIG_MUTEK_MEMALLOC_GUARD
+#undef  CONFIG_LICENSE_USE_PROPRIETARY
+#undef  CONFIG_DRIVER_FB_VGA
+#undef  CONFIG_PTHREAD_CHECK
+#undef  CONFIG_ARCH_SOCLIB_VCACHE_40
+#undef  CONFIG_CPU_MIPS_ABI_EABI
+#define CONFIG_ARCH_SOCLIB
+#define CONFIG_CPU_MIPS_VERSION 32
+#undef  CONFIG_DRIVER_NET_TUNTAP
+#undef  CONFIG_CPU_ARM_THUMB
+#undef  CONFIG_ARCH_SOCLIB_VCACHE_32
+#define CONFIG_HEXO_IRQ
+#undef  CONFIG_CPU_X86_ALIGNCHECK
+#undef  CONFIG_DRIVER_ICU_SAM7
+#undef  CONFIG_ARCH_IBMPC_MEMORY
+#define CONFIG_LICENSE_APP_META
+#undef  CONFIG_HEXO_MMU_PADDR
+#undef  CONFIG_ARCH_EMU_MEMORY
+#undef  CONFIG_UNIX
+#undef  CONFIG_MUTEK_MEMALLOC_ALGO_BESTFIT
+#undef  CONFIG_ARCH_SIMPLE_ATMEGA
+#define CONFIG_RAM_ADDR 0x71600000
+#undef  CONFIG_PRINTF_ARG_SIMPLE
+#define CONFIG_MUTEK_MEMALLOC_ALIGN 0x20
+#undef  CONFIG_NETWORK_FILTER
+#undef  CONFIG_LIBLUA
+#undef  CONFIG_LICENSE_APP_GPL
+#undef  CONFIG_LICENSE_USE_MIT
+#define CONFIG_MUTEK_MEMALLOC_SMART
+#undef  CONFIG_LIBELF_RTLD
+#define CONFIG_SOCLIB_EARLY_CONSOLE 0x90600000
+#define CONFIG_COMPILE_PIC
+#undef  CONFIG_DRIVER_SPI_SPI6088D
+#undef  CONFIG_DRIVER_FS_FAT_LFN
+#undef  CONFIG_MUTEK_MEMALLOC_STATS
+#undef  CONFIG_NETWORK_PROFILING
+#undef  CONFIG_CPU_ARM_SOCLIB
+#undef  CONFIG_DRIVER_BLOCK_RAMDISK
+#undef  CONFIG_MUTEK_SCHEDULER_PREEMPT
+#define CONFIG_DRIVER_ENUM
+#undef  CONFIG_DRIVER_CHAR_EMUTTY
+#define CONFIG_LICENSE_USE_LGPL
+#undef  CONFIG_DRIVER_SOUND
+#undef  CONFIG_ARCH_EMU_PAGESIZE
+#define CONFIG_MUTEK_SCHEDULER
+#undef  CONFIG_SRL
+#undef  CONFIG_DRIVER_CHAR_ZERO
+#undef  CONFIG_MWMR_INSTRUMENTATION
+#define CONFIG_PTHREAD_MUTEX_ATTR
+#undef  CONFIG_DRIVER_ICU_PPC
+#define CONFIG_LIBC_STREAM_BUFFER_SIZE 256
+#undef  CONFIG_LICENSE_USE_BSD
+#define CONFIG_PTHREAD_ATTRIBUTES
+#undef  CONFIG_CPU_X86_SYSENTER
+#undef  CONFIG_SOCLIB_MEMCHECK_ADDRESS
+#undef  CONFIG_DRIVER_INPUT_8042
+#define CONFIG_MODULES splash_radix:/home/share/dcis_scme/THESES/GUTHMULLER/tsar/platforms/tsarv3_mutekh/splash_radix libfdt:/home/guthmuller/dev/mutekh/libfdt libpthread:/home/guthmuller/dev/mutekh/libpthread cpu:/home/guthmuller/dev/mutekh/cpu/mips libcrypto:/home/guthmuller/dev/mutekh/libcrypto arch:/home/guthmuller/dev/mutekh/arch/soclib
+#undef  CONFIG_HEXO_MMU
+#undef  CONFIG_DEBUG_SPINLOCK_LIMIT
+#undef  CONFIG_DRIVER_FS_ISO9660_ROCKRIDGE
+#undef  CONFIG_COMPILE_COLLECT
+#undef  CONFIG_LIBC_STRING_ASM
+#undef  CONFIG_LIBCRYPTO_ARC4
+#undef  CONFIG_MUTEK_TIMERMS
+#undef  CONFIG_DRIVER_BLOCK_PARTITION
+#undef  CONFIG_MWMR_SOCLIB
+#undef  CONFIG_DRIVER_KEYBOARD
+#define CONFIG_SMP
+#undef  CONFIG_LICENSE_APP_MIT
+#define CONFIG_COMPILE_DEBUG
+#define CONFIG_HEXO_IPI
+#undef  CONFIG_DRIVER_TIMER
+#undef  CONFIG_NETWORK
+#undef  CONFIG_DRIVER_UART
+#undef  CONFIG_SRL_VERBOSITY
+#undef  CONFIG_UNIX_DEBUG
+#define CONFIG_DRIVER_MEM
+#undef  CONFIG_DRIVER_CHAR_RANDOM
+#undef  CONFIG_LIBELF_RTLD_KERNEL
+#undef  CONFIG_MUTEK_LOGO
+#undef  CONFIG_CPU_ARM_ARCH
+#define CONFIG_MUTEK_SMP_APP_START
+#undef  CONFIG_MUTEK_SCHEDULER_STATIC
+#undef  CONFIG_DRIVER_LCD_PCF8833
+#undef  CONFIG_ARCH_SIMPLE_ATMEGA128
+#undef  CONFIG_ARCH_HW_INIT_USER
+#undef  CONFIG_HETROM_ADDR
+#undef  CONFIG_DRIVER_FS_FAT_TYPE_FROM_STRING
+#undef  CONFIG_LIBCRYPTO_CRC32
+#define CONFIG_COMPILE_OPTIMIZE 2
+#define CONFIG_MUTEK_RWLOCK
+#define CONFIG_DATA_FROM_ROM
+#undef  CONFIG_MUTEK_SCHEDULER_MIGRATION_AFFINITY
+#undef  CONFIG_DRIVER_GPIO_SAM7
+#undef  CONFIG_MUTEK_MEM_REGION
+#undef  CONFIG_DRIVER_TIMER_8253
+#undef  CONFIG_DRIVER_TIMER_EMU
+#undef  CONFIG_CPU_ARM_CPU
+#undef  CONFIG_DRIVER_INPUT_MT5F
+#undef  CONFIG_DRIVER_CHAR_VGATTY
+#define CONFIG_DEVICE_TREE
+#undef  CONFIG_NETWORK_PING
+#define CONFIG_RAM_SIZE 0x01000000
+#undef  CONFIG_VFS_GLOBAL_ROOT
+#undef  CONFIG_LIBC_STREAM_STD
+#undef  CONFIG_LIBELF_RTLD_TLS
+#undef  CONFIG_UNIX_KSTACK_SIZE
+#undef  CONFIG_LIBM
+#undef  CONFIG_CPU_ARM
+#define CONFIG_MUTEK_SCHEDULER_MIGRATION
+#undef  CONFIG_VFS
+#define CONFIG_PTHREAD_STACK_SIZE 4096
+#undef  CONFIG_LIBDSRL
Index: branches/v4/platforms/tsarv2_mutekh/mutekh/.config.m4
===================================================================
--- branches/v4/platforms/tsarv2_mutekh/mutekh/.config.m4	(revision 371)
+++ branches/v4/platforms/tsarv2_mutekh/mutekh/.config.m4	(revision 371)
@@ -0,0 +1,288 @@
+m4_define(CONFIG_MUTEK_MEMALLOC_ALGO_FIRSTFIT, `defined')
+m4_define(CONFIG_VFS_STATS, `undefined')
+m4_define(CONFIG_NETWORK_SOCKET_PACKET, `undefined')
+m4_define(CONFIG_DRIVER_FS_FAT_RW, `undefined')
+m4_define(CONFIG_DRIVER_BLOCK_EMU_BLOCKSIZE, `undefined')
+m4_define(CONFIG_SRL_SOCLIB, `undefined')
+m4_define(CONFIG_DRIVER_BLOCK_EMU, `undefined')
+m4_define(CONFIG_CPU_RESET_ADDR, `0xbfc00000')
+m4_define(CONFIG_ARCH_SIMPLE_HW_INIT, `undefined')
+m4_define(CONFIG_DRIVER_SPI, `undefined')
+m4_define(CONFIG_LICENSE_APP_PROPRIETARY, `undefined')
+m4_define(CONFIG_HET_BUILD, `undefined')
+m4_define(CONFIG_DEBUG, `undefined')
+m4_define(CONFIG_DRIVER_BLOCK_RAMDISK_SIZE, `undefined')
+m4_define(CONFIG_LIBCRYPTO_MD5, `undefined')
+m4_define(CONFIG_DRIVER_FS_FAT, `undefined')
+m4_define(CONFIG_DRIVER_I2C_TWI6061A, `undefined')
+m4_define(CONFIG_HEXO_INTTYPES_DEPRECATED, `undefined')
+m4_define(CONFIG_DRIVER_BLOCK_SOCLIB, `undefined')
+m4_define(CONFIG_VFS_VERBOSE, `undefined')
+m4_define(CONFIG_CPU_X86_64_EMU, `undefined')
+m4_define(CONFIG_ARCH_NAME, `soclib')
+m4_define(CONFIG_DRIVER_NET_NE2000, `undefined')
+m4_define(CONFIG_CPU_MIPS_ABI_N32, `undefined')
+m4_define(CONFIG_ARCH_SIMPLE_SAM7, `undefined')
+m4_define(CONFIG_DRIVER_FS_RAMFS, `undefined')
+m4_define(CONFIG_MUTEK_PRINTK, `defined')
+m4_define(CONFIG_DRIVER_ICU_MIPS, `defined')
+m4_define(CONFIG_MUTEK_SCHEDULER_IDLE_STACK_SIZE, `2048')
+m4_define(CONFIG_DRIVER_ICU_8259, `undefined')
+m4_define(CONFIG_PTHREAD_JOIN, `defined')
+m4_define(CONFIG_MUTEK_MEMALLOC_GUARD_SIZE, `undefined')
+m4_define(CONFIG_ROM_SIZE, `0x01000000')
+m4_define(CONFIG_LICENSE_USE_GPL, `undefined')
+m4_define(CONFIG_NETWORK_AUTOALIGN, `undefined')
+m4_define(CONFIG_DRIVER_LCD_S1D15G00, `undefined')
+m4_define(CONFIG_VMEM_KERNEL_ALLOC, `undefined')
+m4_define(CONFIG_ARCH_SIMPLE_OLIMEX_SAM7_EX256, `undefined')
+m4_define(CONFIG_ARCH_HW_INIT, `undefined')
+m4_define(CONFIG_VMEM, `undefined')
+m4_define(CONFIG_LICENSE_APP_LGPL, `defined')
+m4_define(CONFIG_CPU_ARM_FPU, `undefined')
+m4_define(CONFIG_CPU_RESET_HANDLER, `defined')
+m4_define(CONFIG_DRIVER_BLOCK, `undefined')
+m4_define(CONFIG_CPU_USER, `undefined')
+m4_define(CONFIG_NETWORK_NFS, `undefined')
+m4_define(CONFIG_VMEM_PHYS_ALLOC, `undefined')
+m4_define(CONFIG_MUTEK_MEMALLOC_GUARD_INSTRUMENT, `undefined')
+m4_define(CONFIG_MWMR_USE_RAMLOCKS, `undefined')
+m4_define(CONFIG_DRIVER_NET_NE2000_FRAGMENT, `undefined')
+m4_define(CONFIG_CPU_CACHE_LINE, `4')
+m4_define(CONFIG_HEXO_ARCH_MMU, `undefined')
+m4_define(CONFIG_DRIVER_BLOCK_CACHE_SIZE, `undefined')
+m4_define(CONFIG_NETWORK_SOCKET, `undefined')
+m4_define(CONFIG_DRIVER_CHAR_SOCLIBTTY, `defined')
+m4_define(CONFIG_LIBCRYPTO_CRC32_SMALL, `undefined')
+m4_define(CONFIG_DRIVER_BLOCK_RAMDISK_BLOCKSIZE, `undefined')
+m4_define(CONFIG_CPU_CACHE_COHERENCY, `undefined')
+m4_define(CONFIG_MUTEK_MEMALLOC_SIGNED, `undefined')
+m4_define(CONFIG_DRIVER_FS_DEVFS, `undefined')
+m4_define(CONFIG_NETWORK_PACKET_ASM, `undefined')
+m4_define(CONFIG_COMPILE_SIZEOF_INT, `4')
+m4_define(CONFIG_NETWORK_FORWARDING, `undefined')
+m4_define(CONFIG_CLUSTER, `undefined')
+m4_define(CONFIG_MUTEK_MAIN, `defined')
+m4_define(CONFIG_UNIX_STACK_VADDR, `undefined')
+m4_define(CONFIG_NETWORK_SOCKET_RAW, `undefined')
+m4_define(CONFIG_LIBELF_DEBUG, `undefined')
+m4_define(CONFIG_DRIVER_FS_ISO9660, `undefined')
+m4_define(CONFIG_DRIVER_I2C, `undefined')
+m4_define(CONFIG_ARCH_IBMPC_DMA, `undefined')
+m4_define(CONFIG_CPU_ENDIAN_LITTLE, `defined')
+m4_define(CONFIG_LIBC_SEMAPHORE, `defined')
+m4_define(CONFIG_UNIX_START_VADDR, `undefined')
+m4_define(CONFIG_ARCH_EMU, `undefined')
+m4_define(CONFIG_SOCLIB_MEMCHECK, `undefined')
+m4_define(CONFIG_DRIVER_FB, `undefined')
+m4_define(CONFIG_CPU_MIPS_ABI_O32, `defined')
+m4_define(CONFIG_DRIVER_MEM_MEMORY, `defined')
+m4_define(CONFIG_DRIVER_FB_SOCLIB, `undefined')
+m4_define(CONFIG_ARCH_EMU_DARWIN, `undefined')
+m4_define(CONFIG_ROM_ADDR, `0x61100000')
+m4_define(CONFIG_DRIVER_ENUM_ROOT, `defined')
+m4_define(CONFIG_DRIVER_TIMER_SOCLIB, `undefined')
+m4_define(CONFIG_COMPILE_FRAMEPTR, `defined')
+m4_define(CONFIG_LIBDSRL_DEBUG, `undefined')
+m4_define(CONFIG_DRIVER_CHAR_NULL, `undefined')
+m4_define(CONFIG_MWMR_PTHREAD, `undefined')
+m4_define(CONFIG_MWMR_LOCKFREE, `undefined')
+m4_define(CONFIG_DRIVER_FS_FAT32, `undefined')
+m4_define(CONFIG_DRIVER_BLOCK_SD_MMC, `undefined')
+m4_define(CONFIG_NETWORK_UDP, `undefined')
+m4_define(CONFIG_NETWORK_IPV4, `undefined')
+m4_define(CONFIG_HEXO_MMU_PAGESIZE, `undefined')
+m4_define(CONFIG_CPU_X86_EMU, `undefined')
+m4_define(CONFIG_NETWORK_DHCLIENT, `undefined')
+m4_define(CONFIG_CPU_CACHE, `defined')
+m4_define(CONFIG_LICENSE_APP_PUBLIC, `undefined')
+m4_define(CONFIG_LIBTERMUI, `undefined')
+m4_define(CONFIG_MUTEK_MEMALLOC_DEBUG, `undefined')
+m4_define(CONFIG_CPU_AVR_GCCMCU, `undefined')
+m4_define(CONFIG_ARCH_SOCLIB_RAMLOCK, `undefined')
+m4_define(CONFIG_VFS_NAMELEN, `undefined')
+m4_define(CONFIG_ARCH_SIMPLE_SAM7X256, `undefined')
+m4_define(CONFIG_DRIVER_CHAR_UART8250, `undefined')
+m4_define(CONFIG_CPU_ARM_7TDMI, `undefined')
+m4_define(CONFIG_CPU_NAME, `mips')
+m4_define(CONFIG_DRIVER_CHAR_VGATTY_KEYBOARD, `undefined')
+m4_define(CONFIG_DRIVER_BLOCK_ATA, `undefined')
+m4_define(CONFIG_MUTEK_CONSOLE, `defined')
+m4_define(CONFIG_LIBELF, `undefined')
+m4_define(CONFIG_DRIVER_LCD, `undefined')
+m4_define(CONFIG_DRIVER_CHAR_SAM7DBGU, `undefined')
+m4_define(CONFIG_LICENSE_USE_PUBLIC, `undefined')
+m4_define(CONFIG_DRIVER_ENUM_PCI, `undefined')
+m4_define(CONFIG_DRIVER_GPIO, `undefined')
+m4_define(CONFIG_CPU_RESET_SIZE, `0x2000')
+m4_define(CONFIG_SRL_STD, `undefined')
+m4_define(CONFIG_LIBC_STREAM, `defined')
+m4_define(CONFIG_ARCH_EMU_LINUX, `undefined')
+m4_define(CONFIG_CPU_AVR, `undefined')
+m4_define(CONFIG_LICENSE_APP_BSD, `undefined')
+m4_define(CONFIG_NETWORK_TCP, `undefined')
+m4_define(CONFIG_CPU_PPC, `undefined')
+m4_define(CONFIG_ARCH_SIMPLE_RESET_ADDR, `undefined')
+m4_define(CONFIG_ARCH_IBMPC, `undefined')
+m4_define(CONFIG_CPU_NONALIGNED_ACCESS, `undefined')
+m4_define(CONFIG_CPU_EXCEPTION_ALIGN, `0x00001000')
+m4_define(CONFIG_MUTEK_NUMA, `undefined')
+m4_define(CONFIG_DRIVER_ICU_SOCLIB, `undefined')
+m4_define(CONFIG_DRIVER_ENUM_FDT, `defined')
+m4_define(CONFIG_MUTEK_SCHEDULER_CANDIDATE_FCN, `undefined')
+m4_define(CONFIG_DRIVER_BLOCK_CACHE, `undefined')
+m4_define(CONFIG_COMPILE_SAVETEMPS, `defined')
+m4_define(CONFIG_HEXO_MMU_VADDR, `undefined')
+m4_define(CONFIG_HETROM_SIZE, `undefined')
+m4_define(CONFIG_DRIVER_ICU_ARM, `undefined')
+m4_define(CONFIG_PRINTF_ARG_EXT, `defined')
+m4_define(CONFIG_LIBELF_DYNAMIC, `undefined')
+m4_define(CONFIG_DRIVER_FS_FAT16, `undefined')
+m4_define(CONFIG_DRIVER_CHAR_US6089C_UART, `undefined')
+m4_define(CONFIG_DRIVER_ICU, `defined')
+m4_define(CONFIG_SRL_MULTI_TTY, `undefined')
+m4_define(CONFIG_COMPILE_INSTRUMENT, `undefined')
+m4_define(CONFIG_CPU_MIPS_ABI_O64, `undefined')
+m4_define(CONFIG_DRIVER_CHAR_VGATTY_ANSI, `undefined')
+m4_define(CONFIG_FDT, `defined')
+m4_define(CONFIG_CPU_EXCEPTION_FIXED_ADDRESS, `undefined')
+m4_define(CONFIG_ARCH_SIMPLE, `undefined')
+m4_define(CONFIG_SOCLIB_VMEM_MALLOC_REGION_SIZE, `0x8000')
+m4_define(CONFIG_HEXO_CPU_MMU, `undefined')
+m4_define(CONFIG_CPU_MAXCOUNT, `4')
+m4_define(CONFIG_DRIVER_NET, `undefined')
+m4_define(CONFIG_DRIVER_BLOCK_PARTITION_MAXCOUNT, `32')
+m4_define(CONFIG_DRIVER_ICU_SOCLIB_XICU, `defined')
+m4_define(CONFIG_ARCH_DEVICE_TREE, `defined')
+m4_define(CONFIG_CPU_AVR_IRQ_COUNT, `undefined')
+m4_define(CONFIG_PTHREAD, `defined')
+m4_define(CONFIG_VFS_GLOBAL_CWD, `undefined')
+m4_define(CONFIG_CPU_MIPS, `defined')
+m4_define(CONFIG_COMPILE_SOFTFLOAT, `defined')
+m4_define(CONFIG_NETWORK_RARP, `undefined')
+m4_define(CONFIG_PTHREAD_CANCEL, `defined')
+m4_define(CONFIG_CPU_ARM_M_PROFILE, `undefined')
+m4_define(CONFIG_MUTEK_MEMALLOC_SIMPLE, `undefined')
+m4_define(CONFIG_LIBCRYPTO, `defined')
+m4_define(CONFIG_DRIVER_TTY, `defined')
+m4_define(CONFIG_LIBC_ASSERT, `defined')
+m4_define(CONFIG_CPU_ARM_TLS_IN_C15, `undefined')
+m4_define(CONFIG_CPU_AVR_ENHANCED, `undefined')
+m4_define(CONFIG_DRIVER_TIMER_PITC_6079A, `undefined')
+m4_define(CONFIG_DRIVER_ENUM_ISAPNP, `undefined')
+m4_define(CONFIG_CPU_ENDIAN_BIG, `undefined')
+m4_define(CONFIG_CPU_X86, `undefined')
+m4_define(CONFIG_MWMR, `undefined')
+m4_define(CONFIG_MUTEK_MEMALLOC_GUARD, `undefined')
+m4_define(CONFIG_LICENSE_USE_PROPRIETARY, `undefined')
+m4_define(CONFIG_DRIVER_FB_VGA, `undefined')
+m4_define(CONFIG_PTHREAD_CHECK, `undefined')
+m4_define(CONFIG_ARCH_SOCLIB_VCACHE_40, `undefined')
+m4_define(CONFIG_CPU_MIPS_ABI_EABI, `undefined')
+m4_define(CONFIG_ARCH_SOCLIB, `defined')
+m4_define(CONFIG_CPU_MIPS_VERSION, `32')
+m4_define(CONFIG_DRIVER_NET_TUNTAP, `undefined')
+m4_define(CONFIG_CPU_ARM_THUMB, `undefined')
+m4_define(CONFIG_ARCH_SOCLIB_VCACHE_32, `undefined')
+m4_define(CONFIG_HEXO_IRQ, `defined')
+m4_define(CONFIG_CPU_X86_ALIGNCHECK, `undefined')
+m4_define(CONFIG_DRIVER_ICU_SAM7, `undefined')
+m4_define(CONFIG_ARCH_IBMPC_MEMORY, `undefined')
+m4_define(CONFIG_LICENSE_APP_META, `defined')
+m4_define(CONFIG_HEXO_MMU_PADDR, `undefined')
+m4_define(CONFIG_ARCH_EMU_MEMORY, `undefined')
+m4_define(CONFIG_UNIX, `undefined')
+m4_define(CONFIG_MUTEK_MEMALLOC_ALGO_BESTFIT, `undefined')
+m4_define(CONFIG_ARCH_SIMPLE_ATMEGA, `undefined')
+m4_define(CONFIG_RAM_ADDR, `0x71600000')
+m4_define(CONFIG_PRINTF_ARG_SIMPLE, `undefined')
+m4_define(CONFIG_MUTEK_MEMALLOC_ALIGN, `0x20')
+m4_define(CONFIG_NETWORK_FILTER, `undefined')
+m4_define(CONFIG_LIBLUA, `undefined')
+m4_define(CONFIG_LICENSE_APP_GPL, `undefined')
+m4_define(CONFIG_LICENSE_USE_MIT, `undefined')
+m4_define(CONFIG_MUTEK_MEMALLOC_SMART, `defined')
+m4_define(CONFIG_LIBELF_RTLD, `undefined')
+m4_define(CONFIG_SOCLIB_EARLY_CONSOLE, `0x90600000')
+m4_define(CONFIG_COMPILE_PIC, `defined')
+m4_define(CONFIG_DRIVER_SPI_SPI6088D, `undefined')
+m4_define(CONFIG_DRIVER_FS_FAT_LFN, `undefined')
+m4_define(CONFIG_MUTEK_MEMALLOC_STATS, `undefined')
+m4_define(CONFIG_NETWORK_PROFILING, `undefined')
+m4_define(CONFIG_CPU_ARM_SOCLIB, `undefined')
+m4_define(CONFIG_DRIVER_BLOCK_RAMDISK, `undefined')
+m4_define(CONFIG_MUTEK_SCHEDULER_PREEMPT, `undefined')
+m4_define(CONFIG_DRIVER_ENUM, `defined')
+m4_define(CONFIG_DRIVER_CHAR_EMUTTY, `undefined')
+m4_define(CONFIG_LICENSE_USE_LGPL, `defined')
+m4_define(CONFIG_DRIVER_SOUND, `undefined')
+m4_define(CONFIG_ARCH_EMU_PAGESIZE, `undefined')
+m4_define(CONFIG_MUTEK_SCHEDULER, `defined')
+m4_define(CONFIG_SRL, `undefined')
+m4_define(CONFIG_DRIVER_CHAR_ZERO, `undefined')
+m4_define(CONFIG_MWMR_INSTRUMENTATION, `undefined')
+m4_define(CONFIG_PTHREAD_MUTEX_ATTR, `defined')
+m4_define(CONFIG_DRIVER_ICU_PPC, `undefined')
+m4_define(CONFIG_LIBC_STREAM_BUFFER_SIZE, `256')
+m4_define(CONFIG_LICENSE_USE_BSD, `undefined')
+m4_define(CONFIG_PTHREAD_ATTRIBUTES, `defined')
+m4_define(CONFIG_CPU_X86_SYSENTER, `undefined')
+m4_define(CONFIG_SOCLIB_MEMCHECK_ADDRESS, `undefined')
+m4_define(CONFIG_DRIVER_INPUT_8042, `undefined')
+m4_define(CONFIG_MODULES, `splash_radix:/home/share/dcis_scme/THESES/GUTHMULLER/tsar/platforms/tsarv3_mutekh/splash_radix libfdt:/home/guthmuller/dev/mutekh/libfdt libpthread:/home/guthmuller/dev/mutekh/libpthread cpu:/home/guthmuller/dev/mutekh/cpu/mips libcrypto:/home/guthmuller/dev/mutekh/libcrypto arch:/home/guthmuller/dev/mutekh/arch/soclib')
+m4_define(CONFIG_HEXO_MMU, `undefined')
+m4_define(CONFIG_DEBUG_SPINLOCK_LIMIT, `undefined')
+m4_define(CONFIG_DRIVER_FS_ISO9660_ROCKRIDGE, `undefined')
+m4_define(CONFIG_COMPILE_COLLECT, `undefined')
+m4_define(CONFIG_LIBC_STRING_ASM, `undefined')
+m4_define(CONFIG_LIBCRYPTO_ARC4, `undefined')
+m4_define(CONFIG_MUTEK_TIMERMS, `undefined')
+m4_define(CONFIG_DRIVER_BLOCK_PARTITION, `undefined')
+m4_define(CONFIG_MWMR_SOCLIB, `undefined')
+m4_define(CONFIG_DRIVER_KEYBOARD, `undefined')
+m4_define(CONFIG_SMP, `defined')
+m4_define(CONFIG_LICENSE_APP_MIT, `undefined')
+m4_define(CONFIG_COMPILE_DEBUG, `defined')
+m4_define(CONFIG_HEXO_IPI, `defined')
+m4_define(CONFIG_DRIVER_TIMER, `undefined')
+m4_define(CONFIG_NETWORK, `undefined')
+m4_define(CONFIG_DRIVER_UART, `undefined')
+m4_define(CONFIG_SRL_VERBOSITY, `undefined')
+m4_define(CONFIG_UNIX_DEBUG, `undefined')
+m4_define(CONFIG_DRIVER_MEM, `defined')
+m4_define(CONFIG_DRIVER_CHAR_RANDOM, `undefined')
+m4_define(CONFIG_LIBELF_RTLD_KERNEL, `undefined')
+m4_define(CONFIG_MUTEK_LOGO, `undefined')
+m4_define(CONFIG_CPU_ARM_ARCH, `undefined')
+m4_define(CONFIG_MUTEK_SMP_APP_START, `defined')
+m4_define(CONFIG_MUTEK_SCHEDULER_STATIC, `undefined')
+m4_define(CONFIG_DRIVER_LCD_PCF8833, `undefined')
+m4_define(CONFIG_ARCH_SIMPLE_ATMEGA128, `undefined')
+m4_define(CONFIG_ARCH_HW_INIT_USER, `undefined')
+m4_define(CONFIG_HETROM_ADDR, `undefined')
+m4_define(CONFIG_DRIVER_FS_FAT_TYPE_FROM_STRING, `undefined')
+m4_define(CONFIG_LIBCRYPTO_CRC32, `undefined')
+m4_define(CONFIG_COMPILE_OPTIMIZE, `2')
+m4_define(CONFIG_MUTEK_RWLOCK, `defined')
+m4_define(CONFIG_DATA_FROM_ROM, `defined')
+m4_define(CONFIG_MUTEK_SCHEDULER_MIGRATION_AFFINITY, `undefined')
+m4_define(CONFIG_DRIVER_GPIO_SAM7, `undefined')
+m4_define(CONFIG_MUTEK_MEM_REGION, `undefined')
+m4_define(CONFIG_DRIVER_TIMER_8253, `undefined')
+m4_define(CONFIG_DRIVER_TIMER_EMU, `undefined')
+m4_define(CONFIG_CPU_ARM_CPU, `undefined')
+m4_define(CONFIG_DRIVER_INPUT_MT5F, `undefined')
+m4_define(CONFIG_DRIVER_CHAR_VGATTY, `undefined')
+m4_define(CONFIG_DEVICE_TREE, `defined')
+m4_define(CONFIG_NETWORK_PING, `undefined')
+m4_define(CONFIG_RAM_SIZE, `0x01000000')
+m4_define(CONFIG_VFS_GLOBAL_ROOT, `undefined')
+m4_define(CONFIG_LIBC_STREAM_STD, `undefined')
+m4_define(CONFIG_LIBELF_RTLD_TLS, `undefined')
+m4_define(CONFIG_UNIX_KSTACK_SIZE, `undefined')
+m4_define(CONFIG_LIBM, `undefined')
+m4_define(CONFIG_CPU_ARM, `undefined')
+m4_define(CONFIG_MUTEK_SCHEDULER_MIGRATION, `defined')
+m4_define(CONFIG_VFS, `undefined')
+m4_define(CONFIG_PTHREAD_STACK_SIZE, `4096')
+m4_define(CONFIG_LIBDSRL, `undefined')
Index: branches/v4/platforms/tsarv2_mutekh/mutekh/.config.mk
===================================================================
--- branches/v4/platforms/tsarv2_mutekh/mutekh/.config.mk	(revision 371)
+++ branches/v4/platforms/tsarv2_mutekh/mutekh/.config.mk	(revision 371)
@@ -0,0 +1,297 @@
+##
+## This file has been generated by the configuration script.
+##
+
+# configuration options
+
+CONFIG_MUTEK_MEMALLOC_ALGO_FIRSTFIT=defined
+CONFIG_VFS_STATS=undefined
+CONFIG_NETWORK_SOCKET_PACKET=undefined
+CONFIG_DRIVER_FS_FAT_RW=undefined
+CONFIG_DRIVER_BLOCK_EMU_BLOCKSIZE=undefined
+CONFIG_SRL_SOCLIB=undefined
+CONFIG_DRIVER_BLOCK_EMU=undefined
+CONFIG_CPU_RESET_ADDR=0xbfc00000
+CONFIG_ARCH_SIMPLE_HW_INIT=undefined
+CONFIG_DRIVER_SPI=undefined
+CONFIG_LICENSE_APP_PROPRIETARY=undefined
+CONFIG_HET_BUILD=undefined
+CONFIG_DEBUG=undefined
+CONFIG_DRIVER_BLOCK_RAMDISK_SIZE=undefined
+CONFIG_LIBCRYPTO_MD5=undefined
+CONFIG_DRIVER_FS_FAT=undefined
+CONFIG_DRIVER_I2C_TWI6061A=undefined
+CONFIG_HEXO_INTTYPES_DEPRECATED=undefined
+CONFIG_DRIVER_BLOCK_SOCLIB=undefined
+CONFIG_VFS_VERBOSE=undefined
+CONFIG_CPU_X86_64_EMU=undefined
+CONFIG_ARCH_NAME=soclib
+CONFIG_DRIVER_NET_NE2000=undefined
+CONFIG_CPU_MIPS_ABI_N32=undefined
+CONFIG_ARCH_SIMPLE_SAM7=undefined
+CONFIG_DRIVER_FS_RAMFS=undefined
+CONFIG_MUTEK_PRINTK=defined
+CONFIG_DRIVER_ICU_MIPS=defined
+CONFIG_MUTEK_SCHEDULER_IDLE_STACK_SIZE=2048
+CONFIG_DRIVER_ICU_8259=undefined
+CONFIG_PTHREAD_JOIN=defined
+CONFIG_MUTEK_MEMALLOC_GUARD_SIZE=undefined
+CONFIG_ROM_SIZE=0x01000000
+CONFIG_LICENSE_USE_GPL=undefined
+CONFIG_NETWORK_AUTOALIGN=undefined
+CONFIG_DRIVER_LCD_S1D15G00=undefined
+CONFIG_VMEM_KERNEL_ALLOC=undefined
+CONFIG_ARCH_SIMPLE_OLIMEX_SAM7_EX256=undefined
+CONFIG_ARCH_HW_INIT=undefined
+CONFIG_VMEM=undefined
+CONFIG_LICENSE_APP_LGPL=defined
+CONFIG_CPU_ARM_FPU=undefined
+CONFIG_CPU_RESET_HANDLER=defined
+CONFIG_DRIVER_BLOCK=undefined
+CONFIG_CPU_USER=undefined
+CONFIG_NETWORK_NFS=undefined
+CONFIG_VMEM_PHYS_ALLOC=undefined
+CONFIG_MUTEK_MEMALLOC_GUARD_INSTRUMENT=undefined
+CONFIG_MWMR_USE_RAMLOCKS=undefined
+CONFIG_DRIVER_NET_NE2000_FRAGMENT=undefined
+CONFIG_CPU_CACHE_LINE=4
+CONFIG_HEXO_ARCH_MMU=undefined
+CONFIG_DRIVER_BLOCK_CACHE_SIZE=undefined
+CONFIG_NETWORK_SOCKET=undefined
+CONFIG_DRIVER_CHAR_SOCLIBTTY=defined
+CONFIG_LIBCRYPTO_CRC32_SMALL=undefined
+CONFIG_DRIVER_BLOCK_RAMDISK_BLOCKSIZE=undefined
+CONFIG_CPU_CACHE_COHERENCY=undefined
+CONFIG_MUTEK_MEMALLOC_SIGNED=undefined
+CONFIG_DRIVER_FS_DEVFS=undefined
+CONFIG_NETWORK_PACKET_ASM=undefined
+CONFIG_COMPILE_SIZEOF_INT=4
+CONFIG_NETWORK_FORWARDING=undefined
+CONFIG_CLUSTER=undefined
+CONFIG_MUTEK_MAIN=defined
+CONFIG_UNIX_STACK_VADDR=undefined
+CONFIG_NETWORK_SOCKET_RAW=undefined
+CONFIG_LIBELF_DEBUG=undefined
+CONFIG_DRIVER_FS_ISO9660=undefined
+CONFIG_DRIVER_I2C=undefined
+CONFIG_ARCH_IBMPC_DMA=undefined
+CONFIG_CPU_ENDIAN_LITTLE=defined
+CONFIG_LIBC_SEMAPHORE=defined
+CONFIG_UNIX_START_VADDR=undefined
+CONFIG_ARCH_EMU=undefined
+CONFIG_SOCLIB_MEMCHECK=undefined
+CONFIG_DRIVER_FB=undefined
+CONFIG_CPU_MIPS_ABI_O32=defined
+CONFIG_DRIVER_MEM_MEMORY=defined
+CONFIG_DRIVER_FB_SOCLIB=undefined
+CONFIG_ARCH_EMU_DARWIN=undefined
+CONFIG_ROM_ADDR=0x61100000
+CONFIG_DRIVER_ENUM_ROOT=defined
+CONFIG_DRIVER_TIMER_SOCLIB=undefined
+CONFIG_COMPILE_FRAMEPTR=defined
+CONFIG_LIBDSRL_DEBUG=undefined
+CONFIG_DRIVER_CHAR_NULL=undefined
+CONFIG_MWMR_PTHREAD=undefined
+CONFIG_MWMR_LOCKFREE=undefined
+CONFIG_DRIVER_FS_FAT32=undefined
+CONFIG_DRIVER_BLOCK_SD_MMC=undefined
+CONFIG_NETWORK_UDP=undefined
+CONFIG_NETWORK_IPV4=undefined
+CONFIG_HEXO_MMU_PAGESIZE=undefined
+CONFIG_CPU_X86_EMU=undefined
+CONFIG_NETWORK_DHCLIENT=undefined
+CONFIG_CPU_CACHE=defined
+CONFIG_LICENSE_APP_PUBLIC=undefined
+CONFIG_LIBTERMUI=undefined
+CONFIG_MUTEK_MEMALLOC_DEBUG=undefined
+CONFIG_CPU_AVR_GCCMCU=undefined
+CONFIG_ARCH_SOCLIB_RAMLOCK=undefined
+CONFIG_VFS_NAMELEN=undefined
+CONFIG_ARCH_SIMPLE_SAM7X256=undefined
+CONFIG_DRIVER_CHAR_UART8250=undefined
+CONFIG_CPU_ARM_7TDMI=undefined
+CONFIG_CPU_NAME=mips
+CONFIG_DRIVER_CHAR_VGATTY_KEYBOARD=undefined
+CONFIG_DRIVER_BLOCK_ATA=undefined
+CONFIG_MUTEK_CONSOLE=defined
+CONFIG_LIBELF=undefined
+CONFIG_DRIVER_LCD=undefined
+CONFIG_DRIVER_CHAR_SAM7DBGU=undefined
+CONFIG_LICENSE_USE_PUBLIC=undefined
+CONFIG_DRIVER_ENUM_PCI=undefined
+CONFIG_DRIVER_GPIO=undefined
+CONFIG_CPU_RESET_SIZE=0x2000
+CONFIG_SRL_STD=undefined
+CONFIG_LIBC_STREAM=defined
+CONFIG_ARCH_EMU_LINUX=undefined
+CONFIG_CPU_AVR=undefined
+CONFIG_LICENSE_APP_BSD=undefined
+CONFIG_NETWORK_TCP=undefined
+CONFIG_CPU_PPC=undefined
+CONFIG_ARCH_SIMPLE_RESET_ADDR=undefined
+CONFIG_ARCH_IBMPC=undefined
+CONFIG_CPU_NONALIGNED_ACCESS=undefined
+CONFIG_CPU_EXCEPTION_ALIGN=0x00001000
+CONFIG_MUTEK_NUMA=undefined
+CONFIG_DRIVER_ICU_SOCLIB=undefined
+CONFIG_DRIVER_ENUM_FDT=defined
+CONFIG_MUTEK_SCHEDULER_CANDIDATE_FCN=undefined
+CONFIG_DRIVER_BLOCK_CACHE=undefined
+CONFIG_COMPILE_SAVETEMPS=defined
+CONFIG_HEXO_MMU_VADDR=undefined
+CONFIG_HETROM_SIZE=undefined
+CONFIG_DRIVER_ICU_ARM=undefined
+CONFIG_PRINTF_ARG_EXT=defined
+CONFIG_LIBELF_DYNAMIC=undefined
+CONFIG_DRIVER_FS_FAT16=undefined
+CONFIG_DRIVER_CHAR_US6089C_UART=undefined
+CONFIG_DRIVER_ICU=defined
+CONFIG_SRL_MULTI_TTY=undefined
+CONFIG_COMPILE_INSTRUMENT=undefined
+CONFIG_CPU_MIPS_ABI_O64=undefined
+CONFIG_DRIVER_CHAR_VGATTY_ANSI=undefined
+CONFIG_FDT=defined
+CONFIG_CPU_EXCEPTION_FIXED_ADDRESS=undefined
+CONFIG_ARCH_SIMPLE=undefined
+CONFIG_SOCLIB_VMEM_MALLOC_REGION_SIZE=0x8000
+CONFIG_HEXO_CPU_MMU=undefined
+CONFIG_CPU_MAXCOUNT=4
+CONFIG_DRIVER_NET=undefined
+CONFIG_DRIVER_BLOCK_PARTITION_MAXCOUNT=32
+CONFIG_DRIVER_ICU_SOCLIB_XICU=defined
+CONFIG_ARCH_DEVICE_TREE=defined
+CONFIG_CPU_AVR_IRQ_COUNT=undefined
+CONFIG_PTHREAD=defined
+CONFIG_VFS_GLOBAL_CWD=undefined
+CONFIG_CPU_MIPS=defined
+CONFIG_COMPILE_SOFTFLOAT=defined
+CONFIG_NETWORK_RARP=undefined
+CONFIG_PTHREAD_CANCEL=defined
+CONFIG_CPU_ARM_M_PROFILE=undefined
+CONFIG_MUTEK_MEMALLOC_SIMPLE=undefined
+CONFIG_LIBCRYPTO=defined
+CONFIG_DRIVER_TTY=defined
+CONFIG_LIBC_ASSERT=defined
+CONFIG_CPU_ARM_TLS_IN_C15=undefined
+CONFIG_CPU_AVR_ENHANCED=undefined
+CONFIG_DRIVER_TIMER_PITC_6079A=undefined
+CONFIG_DRIVER_ENUM_ISAPNP=undefined
+CONFIG_CPU_ENDIAN_BIG=undefined
+CONFIG_CPU_X86=undefined
+CONFIG_MWMR=undefined
+CONFIG_MUTEK_MEMALLOC_GUARD=undefined
+CONFIG_LICENSE_USE_PROPRIETARY=undefined
+CONFIG_DRIVER_FB_VGA=undefined
+CONFIG_PTHREAD_CHECK=undefined
+CONFIG_ARCH_SOCLIB_VCACHE_40=undefined
+CONFIG_CPU_MIPS_ABI_EABI=undefined
+CONFIG_ARCH_SOCLIB=defined
+CONFIG_CPU_MIPS_VERSION=32
+CONFIG_DRIVER_NET_TUNTAP=undefined
+CONFIG_CPU_ARM_THUMB=undefined
+CONFIG_ARCH_SOCLIB_VCACHE_32=undefined
+CONFIG_HEXO_IRQ=defined
+CONFIG_CPU_X86_ALIGNCHECK=undefined
+CONFIG_DRIVER_ICU_SAM7=undefined
+CONFIG_ARCH_IBMPC_MEMORY=undefined
+CONFIG_LICENSE_APP_META=defined
+CONFIG_HEXO_MMU_PADDR=undefined
+CONFIG_ARCH_EMU_MEMORY=undefined
+CONFIG_UNIX=undefined
+CONFIG_MUTEK_MEMALLOC_ALGO_BESTFIT=undefined
+CONFIG_ARCH_SIMPLE_ATMEGA=undefined
+CONFIG_RAM_ADDR=0x71600000
+CONFIG_PRINTF_ARG_SIMPLE=undefined
+CONFIG_MUTEK_MEMALLOC_ALIGN=0x20
+CONFIG_NETWORK_FILTER=undefined
+CONFIG_LIBLUA=undefined
+CONFIG_LICENSE_APP_GPL=undefined
+CONFIG_LICENSE_USE_MIT=undefined
+CONFIG_MUTEK_MEMALLOC_SMART=defined
+CONFIG_LIBELF_RTLD=undefined
+CONFIG_SOCLIB_EARLY_CONSOLE=0x90600000
+CONFIG_COMPILE_PIC=defined
+CONFIG_DRIVER_SPI_SPI6088D=undefined
+CONFIG_DRIVER_FS_FAT_LFN=undefined
+CONFIG_MUTEK_MEMALLOC_STATS=undefined
+CONFIG_NETWORK_PROFILING=undefined
+CONFIG_CPU_ARM_SOCLIB=undefined
+CONFIG_DRIVER_BLOCK_RAMDISK=undefined
+CONFIG_MUTEK_SCHEDULER_PREEMPT=undefined
+CONFIG_DRIVER_ENUM=defined
+CONFIG_DRIVER_CHAR_EMUTTY=undefined
+CONFIG_LICENSE_USE_LGPL=defined
+CONFIG_DRIVER_SOUND=undefined
+CONFIG_ARCH_EMU_PAGESIZE=undefined
+CONFIG_MUTEK_SCHEDULER=defined
+CONFIG_SRL=undefined
+CONFIG_DRIVER_CHAR_ZERO=undefined
+CONFIG_MWMR_INSTRUMENTATION=undefined
+CONFIG_PTHREAD_MUTEX_ATTR=defined
+CONFIG_DRIVER_ICU_PPC=undefined
+CONFIG_LIBC_STREAM_BUFFER_SIZE=256
+CONFIG_LICENSE_USE_BSD=undefined
+CONFIG_PTHREAD_ATTRIBUTES=defined
+CONFIG_CPU_X86_SYSENTER=undefined
+CONFIG_SOCLIB_MEMCHECK_ADDRESS=undefined
+CONFIG_DRIVER_INPUT_8042=undefined
+CONFIG_MODULES=splash_radix:/home/share/dcis_scme/THESES/GUTHMULLER/tsar/platforms/tsarv3_mutekh/splash_radix libfdt:/home/guthmuller/dev/mutekh/libfdt libpthread:/home/guthmuller/dev/mutekh/libpthread cpu:/home/guthmuller/dev/mutekh/cpu/mips libcrypto:/home/guthmuller/dev/mutekh/libcrypto arch:/home/guthmuller/dev/mutekh/arch/soclib
+CONFIG_HEXO_MMU=undefined
+CONFIG_DEBUG_SPINLOCK_LIMIT=undefined
+CONFIG_DRIVER_FS_ISO9660_ROCKRIDGE=undefined
+CONFIG_COMPILE_COLLECT=undefined
+CONFIG_LIBC_STRING_ASM=undefined
+CONFIG_LIBCRYPTO_ARC4=undefined
+CONFIG_MUTEK_TIMERMS=undefined
+CONFIG_DRIVER_BLOCK_PARTITION=undefined
+CONFIG_MWMR_SOCLIB=undefined
+CONFIG_DRIVER_KEYBOARD=undefined
+CONFIG_SMP=defined
+CONFIG_LICENSE_APP_MIT=undefined
+CONFIG_COMPILE_DEBUG=defined
+CONFIG_HEXO_IPI=defined
+CONFIG_DRIVER_TIMER=undefined
+CONFIG_NETWORK=undefined
+CONFIG_DRIVER_UART=undefined
+CONFIG_SRL_VERBOSITY=undefined
+CONFIG_UNIX_DEBUG=undefined
+CONFIG_DRIVER_MEM=defined
+CONFIG_DRIVER_CHAR_RANDOM=undefined
+CONFIG_LIBELF_RTLD_KERNEL=undefined
+CONFIG_MUTEK_LOGO=undefined
+CONFIG_CPU_ARM_ARCH=undefined
+CONFIG_MUTEK_SMP_APP_START=defined
+CONFIG_MUTEK_SCHEDULER_STATIC=undefined
+CONFIG_DRIVER_LCD_PCF8833=undefined
+CONFIG_ARCH_SIMPLE_ATMEGA128=undefined
+CONFIG_ARCH_HW_INIT_USER=undefined
+CONFIG_HETROM_ADDR=undefined
+CONFIG_DRIVER_FS_FAT_TYPE_FROM_STRING=undefined
+CONFIG_LIBCRYPTO_CRC32=undefined
+CONFIG_COMPILE_OPTIMIZE=2
+CONFIG_MUTEK_RWLOCK=defined
+CONFIG_DATA_FROM_ROM=defined
+CONFIG_MUTEK_SCHEDULER_MIGRATION_AFFINITY=undefined
+CONFIG_DRIVER_GPIO_SAM7=undefined
+CONFIG_MUTEK_MEM_REGION=undefined
+CONFIG_DRIVER_TIMER_8253=undefined
+CONFIG_DRIVER_TIMER_EMU=undefined
+CONFIG_CPU_ARM_CPU=undefined
+CONFIG_DRIVER_INPUT_MT5F=undefined
+CONFIG_DRIVER_CHAR_VGATTY=undefined
+CONFIG_DEVICE_TREE=defined
+CONFIG_NETWORK_PING=undefined
+CONFIG_RAM_SIZE=0x01000000
+CONFIG_VFS_GLOBAL_ROOT=undefined
+CONFIG_LIBC_STREAM_STD=undefined
+CONFIG_LIBELF_RTLD_TLS=undefined
+CONFIG_UNIX_KSTACK_SIZE=undefined
+CONFIG_LIBM=undefined
+CONFIG_CPU_ARM=undefined
+CONFIG_MUTEK_SCHEDULER_MIGRATION=defined
+CONFIG_VFS=undefined
+CONFIG_PTHREAD_STACK_SIZE=4096
+CONFIG_LIBDSRL=undefined
+
+# configuration variables
+
Index: branches/v4/platforms/tsarv2_mutekh/mutekh/.config.py
===================================================================
--- branches/v4/platforms/tsarv2_mutekh/mutekh/.config.py	(revision 371)
+++ branches/v4/platforms/tsarv2_mutekh/mutekh/.config.py	(revision 371)
@@ -0,0 +1,288 @@
+CONFIG_MUTEK_MEMALLOC_ALGO_FIRSTFIT = 'defined'
+CONFIG_VFS_STATS = 'undefined'
+CONFIG_NETWORK_SOCKET_PACKET = 'undefined'
+CONFIG_DRIVER_FS_FAT_RW = 'undefined'
+CONFIG_DRIVER_BLOCK_EMU_BLOCKSIZE = 'undefined'
+CONFIG_SRL_SOCLIB = 'undefined'
+CONFIG_DRIVER_BLOCK_EMU = 'undefined'
+CONFIG_CPU_RESET_ADDR = '0xbfc00000'
+CONFIG_ARCH_SIMPLE_HW_INIT = 'undefined'
+CONFIG_DRIVER_SPI = 'undefined'
+CONFIG_LICENSE_APP_PROPRIETARY = 'undefined'
+CONFIG_HET_BUILD = 'undefined'
+CONFIG_DEBUG = 'undefined'
+CONFIG_DRIVER_BLOCK_RAMDISK_SIZE = 'undefined'
+CONFIG_LIBCRYPTO_MD5 = 'undefined'
+CONFIG_DRIVER_FS_FAT = 'undefined'
+CONFIG_DRIVER_I2C_TWI6061A = 'undefined'
+CONFIG_HEXO_INTTYPES_DEPRECATED = 'undefined'
+CONFIG_DRIVER_BLOCK_SOCLIB = 'undefined'
+CONFIG_VFS_VERBOSE = 'undefined'
+CONFIG_CPU_X86_64_EMU = 'undefined'
+CONFIG_ARCH_NAME = 'soclib'
+CONFIG_DRIVER_NET_NE2000 = 'undefined'
+CONFIG_CPU_MIPS_ABI_N32 = 'undefined'
+CONFIG_ARCH_SIMPLE_SAM7 = 'undefined'
+CONFIG_DRIVER_FS_RAMFS = 'undefined'
+CONFIG_MUTEK_PRINTK = 'defined'
+CONFIG_DRIVER_ICU_MIPS = 'defined'
+CONFIG_MUTEK_SCHEDULER_IDLE_STACK_SIZE = '2048'
+CONFIG_DRIVER_ICU_8259 = 'undefined'
+CONFIG_PTHREAD_JOIN = 'defined'
+CONFIG_MUTEK_MEMALLOC_GUARD_SIZE = 'undefined'
+CONFIG_ROM_SIZE = '0x01000000'
+CONFIG_LICENSE_USE_GPL = 'undefined'
+CONFIG_NETWORK_AUTOALIGN = 'undefined'
+CONFIG_DRIVER_LCD_S1D15G00 = 'undefined'
+CONFIG_VMEM_KERNEL_ALLOC = 'undefined'
+CONFIG_ARCH_SIMPLE_OLIMEX_SAM7_EX256 = 'undefined'
+CONFIG_ARCH_HW_INIT = 'undefined'
+CONFIG_VMEM = 'undefined'
+CONFIG_LICENSE_APP_LGPL = 'defined'
+CONFIG_CPU_ARM_FPU = 'undefined'
+CONFIG_CPU_RESET_HANDLER = 'defined'
+CONFIG_DRIVER_BLOCK = 'undefined'
+CONFIG_CPU_USER = 'undefined'
+CONFIG_NETWORK_NFS = 'undefined'
+CONFIG_VMEM_PHYS_ALLOC = 'undefined'
+CONFIG_MUTEK_MEMALLOC_GUARD_INSTRUMENT = 'undefined'
+CONFIG_MWMR_USE_RAMLOCKS = 'undefined'
+CONFIG_DRIVER_NET_NE2000_FRAGMENT = 'undefined'
+CONFIG_CPU_CACHE_LINE = '4'
+CONFIG_HEXO_ARCH_MMU = 'undefined'
+CONFIG_DRIVER_BLOCK_CACHE_SIZE = 'undefined'
+CONFIG_NETWORK_SOCKET = 'undefined'
+CONFIG_DRIVER_CHAR_SOCLIBTTY = 'defined'
+CONFIG_LIBCRYPTO_CRC32_SMALL = 'undefined'
+CONFIG_DRIVER_BLOCK_RAMDISK_BLOCKSIZE = 'undefined'
+CONFIG_CPU_CACHE_COHERENCY = 'undefined'
+CONFIG_MUTEK_MEMALLOC_SIGNED = 'undefined'
+CONFIG_DRIVER_FS_DEVFS = 'undefined'
+CONFIG_NETWORK_PACKET_ASM = 'undefined'
+CONFIG_COMPILE_SIZEOF_INT = '4'
+CONFIG_NETWORK_FORWARDING = 'undefined'
+CONFIG_CLUSTER = 'undefined'
+CONFIG_MUTEK_MAIN = 'defined'
+CONFIG_UNIX_STACK_VADDR = 'undefined'
+CONFIG_NETWORK_SOCKET_RAW = 'undefined'
+CONFIG_LIBELF_DEBUG = 'undefined'
+CONFIG_DRIVER_FS_ISO9660 = 'undefined'
+CONFIG_DRIVER_I2C = 'undefined'
+CONFIG_ARCH_IBMPC_DMA = 'undefined'
+CONFIG_CPU_ENDIAN_LITTLE = 'defined'
+CONFIG_LIBC_SEMAPHORE = 'defined'
+CONFIG_UNIX_START_VADDR = 'undefined'
+CONFIG_ARCH_EMU = 'undefined'
+CONFIG_SOCLIB_MEMCHECK = 'undefined'
+CONFIG_DRIVER_FB = 'undefined'
+CONFIG_CPU_MIPS_ABI_O32 = 'defined'
+CONFIG_DRIVER_MEM_MEMORY = 'defined'
+CONFIG_DRIVER_FB_SOCLIB = 'undefined'
+CONFIG_ARCH_EMU_DARWIN = 'undefined'
+CONFIG_ROM_ADDR = '0x61100000'
+CONFIG_DRIVER_ENUM_ROOT = 'defined'
+CONFIG_DRIVER_TIMER_SOCLIB = 'undefined'
+CONFIG_COMPILE_FRAMEPTR = 'defined'
+CONFIG_LIBDSRL_DEBUG = 'undefined'
+CONFIG_DRIVER_CHAR_NULL = 'undefined'
+CONFIG_MWMR_PTHREAD = 'undefined'
+CONFIG_MWMR_LOCKFREE = 'undefined'
+CONFIG_DRIVER_FS_FAT32 = 'undefined'
+CONFIG_DRIVER_BLOCK_SD_MMC = 'undefined'
+CONFIG_NETWORK_UDP = 'undefined'
+CONFIG_NETWORK_IPV4 = 'undefined'
+CONFIG_HEXO_MMU_PAGESIZE = 'undefined'
+CONFIG_CPU_X86_EMU = 'undefined'
+CONFIG_NETWORK_DHCLIENT = 'undefined'
+CONFIG_CPU_CACHE = 'defined'
+CONFIG_LICENSE_APP_PUBLIC = 'undefined'
+CONFIG_LIBTERMUI = 'undefined'
+CONFIG_MUTEK_MEMALLOC_DEBUG = 'undefined'
+CONFIG_CPU_AVR_GCCMCU = 'undefined'
+CONFIG_ARCH_SOCLIB_RAMLOCK = 'undefined'
+CONFIG_VFS_NAMELEN = 'undefined'
+CONFIG_ARCH_SIMPLE_SAM7X256 = 'undefined'
+CONFIG_DRIVER_CHAR_UART8250 = 'undefined'
+CONFIG_CPU_ARM_7TDMI = 'undefined'
+CONFIG_CPU_NAME = 'mips'
+CONFIG_DRIVER_CHAR_VGATTY_KEYBOARD = 'undefined'
+CONFIG_DRIVER_BLOCK_ATA = 'undefined'
+CONFIG_MUTEK_CONSOLE = 'defined'
+CONFIG_LIBELF = 'undefined'
+CONFIG_DRIVER_LCD = 'undefined'
+CONFIG_DRIVER_CHAR_SAM7DBGU = 'undefined'
+CONFIG_LICENSE_USE_PUBLIC = 'undefined'
+CONFIG_DRIVER_ENUM_PCI = 'undefined'
+CONFIG_DRIVER_GPIO = 'undefined'
+CONFIG_CPU_RESET_SIZE = '0x2000'
+CONFIG_SRL_STD = 'undefined'
+CONFIG_LIBC_STREAM = 'defined'
+CONFIG_ARCH_EMU_LINUX = 'undefined'
+CONFIG_CPU_AVR = 'undefined'
+CONFIG_LICENSE_APP_BSD = 'undefined'
+CONFIG_NETWORK_TCP = 'undefined'
+CONFIG_CPU_PPC = 'undefined'
+CONFIG_ARCH_SIMPLE_RESET_ADDR = 'undefined'
+CONFIG_ARCH_IBMPC = 'undefined'
+CONFIG_CPU_NONALIGNED_ACCESS = 'undefined'
+CONFIG_CPU_EXCEPTION_ALIGN = '0x00001000'
+CONFIG_MUTEK_NUMA = 'undefined'
+CONFIG_DRIVER_ICU_SOCLIB = 'undefined'
+CONFIG_DRIVER_ENUM_FDT = 'defined'
+CONFIG_MUTEK_SCHEDULER_CANDIDATE_FCN = 'undefined'
+CONFIG_DRIVER_BLOCK_CACHE = 'undefined'
+CONFIG_COMPILE_SAVETEMPS = 'defined'
+CONFIG_HEXO_MMU_VADDR = 'undefined'
+CONFIG_HETROM_SIZE = 'undefined'
+CONFIG_DRIVER_ICU_ARM = 'undefined'
+CONFIG_PRINTF_ARG_EXT = 'defined'
+CONFIG_LIBELF_DYNAMIC = 'undefined'
+CONFIG_DRIVER_FS_FAT16 = 'undefined'
+CONFIG_DRIVER_CHAR_US6089C_UART = 'undefined'
+CONFIG_DRIVER_ICU = 'defined'
+CONFIG_SRL_MULTI_TTY = 'undefined'
+CONFIG_COMPILE_INSTRUMENT = 'undefined'
+CONFIG_CPU_MIPS_ABI_O64 = 'undefined'
+CONFIG_DRIVER_CHAR_VGATTY_ANSI = 'undefined'
+CONFIG_FDT = 'defined'
+CONFIG_CPU_EXCEPTION_FIXED_ADDRESS = 'undefined'
+CONFIG_ARCH_SIMPLE = 'undefined'
+CONFIG_SOCLIB_VMEM_MALLOC_REGION_SIZE = '0x8000'
+CONFIG_HEXO_CPU_MMU = 'undefined'
+CONFIG_CPU_MAXCOUNT = '4'
+CONFIG_DRIVER_NET = 'undefined'
+CONFIG_DRIVER_BLOCK_PARTITION_MAXCOUNT = '32'
+CONFIG_DRIVER_ICU_SOCLIB_XICU = 'defined'
+CONFIG_ARCH_DEVICE_TREE = 'defined'
+CONFIG_CPU_AVR_IRQ_COUNT = 'undefined'
+CONFIG_PTHREAD = 'defined'
+CONFIG_VFS_GLOBAL_CWD = 'undefined'
+CONFIG_CPU_MIPS = 'defined'
+CONFIG_COMPILE_SOFTFLOAT = 'defined'
+CONFIG_NETWORK_RARP = 'undefined'
+CONFIG_PTHREAD_CANCEL = 'defined'
+CONFIG_CPU_ARM_M_PROFILE = 'undefined'
+CONFIG_MUTEK_MEMALLOC_SIMPLE = 'undefined'
+CONFIG_LIBCRYPTO = 'defined'
+CONFIG_DRIVER_TTY = 'defined'
+CONFIG_LIBC_ASSERT = 'defined'
+CONFIG_CPU_ARM_TLS_IN_C15 = 'undefined'
+CONFIG_CPU_AVR_ENHANCED = 'undefined'
+CONFIG_DRIVER_TIMER_PITC_6079A = 'undefined'
+CONFIG_DRIVER_ENUM_ISAPNP = 'undefined'
+CONFIG_CPU_ENDIAN_BIG = 'undefined'
+CONFIG_CPU_X86 = 'undefined'
+CONFIG_MWMR = 'undefined'
+CONFIG_MUTEK_MEMALLOC_GUARD = 'undefined'
+CONFIG_LICENSE_USE_PROPRIETARY = 'undefined'
+CONFIG_DRIVER_FB_VGA = 'undefined'
+CONFIG_PTHREAD_CHECK = 'undefined'
+CONFIG_ARCH_SOCLIB_VCACHE_40 = 'undefined'
+CONFIG_CPU_MIPS_ABI_EABI = 'undefined'
+CONFIG_ARCH_SOCLIB = 'defined'
+CONFIG_CPU_MIPS_VERSION = '32'
+CONFIG_DRIVER_NET_TUNTAP = 'undefined'
+CONFIG_CPU_ARM_THUMB = 'undefined'
+CONFIG_ARCH_SOCLIB_VCACHE_32 = 'undefined'
+CONFIG_HEXO_IRQ = 'defined'
+CONFIG_CPU_X86_ALIGNCHECK = 'undefined'
+CONFIG_DRIVER_ICU_SAM7 = 'undefined'
+CONFIG_ARCH_IBMPC_MEMORY = 'undefined'
+CONFIG_LICENSE_APP_META = 'defined'
+CONFIG_HEXO_MMU_PADDR = 'undefined'
+CONFIG_ARCH_EMU_MEMORY = 'undefined'
+CONFIG_UNIX = 'undefined'
+CONFIG_MUTEK_MEMALLOC_ALGO_BESTFIT = 'undefined'
+CONFIG_ARCH_SIMPLE_ATMEGA = 'undefined'
+CONFIG_RAM_ADDR = '0x71600000'
+CONFIG_PRINTF_ARG_SIMPLE = 'undefined'
+CONFIG_MUTEK_MEMALLOC_ALIGN = '0x20'
+CONFIG_NETWORK_FILTER = 'undefined'
+CONFIG_LIBLUA = 'undefined'
+CONFIG_LICENSE_APP_GPL = 'undefined'
+CONFIG_LICENSE_USE_MIT = 'undefined'
+CONFIG_MUTEK_MEMALLOC_SMART = 'defined'
+CONFIG_LIBELF_RTLD = 'undefined'
+CONFIG_SOCLIB_EARLY_CONSOLE = '0x90600000'
+CONFIG_COMPILE_PIC = 'defined'
+CONFIG_DRIVER_SPI_SPI6088D = 'undefined'
+CONFIG_DRIVER_FS_FAT_LFN = 'undefined'
+CONFIG_MUTEK_MEMALLOC_STATS = 'undefined'
+CONFIG_NETWORK_PROFILING = 'undefined'
+CONFIG_CPU_ARM_SOCLIB = 'undefined'
+CONFIG_DRIVER_BLOCK_RAMDISK = 'undefined'
+CONFIG_MUTEK_SCHEDULER_PREEMPT = 'undefined'
+CONFIG_DRIVER_ENUM = 'defined'
+CONFIG_DRIVER_CHAR_EMUTTY = 'undefined'
+CONFIG_LICENSE_USE_LGPL = 'defined'
+CONFIG_DRIVER_SOUND = 'undefined'
+CONFIG_ARCH_EMU_PAGESIZE = 'undefined'
+CONFIG_MUTEK_SCHEDULER = 'defined'
+CONFIG_SRL = 'undefined'
+CONFIG_DRIVER_CHAR_ZERO = 'undefined'
+CONFIG_MWMR_INSTRUMENTATION = 'undefined'
+CONFIG_PTHREAD_MUTEX_ATTR = 'defined'
+CONFIG_DRIVER_ICU_PPC = 'undefined'
+CONFIG_LIBC_STREAM_BUFFER_SIZE = '256'
+CONFIG_LICENSE_USE_BSD = 'undefined'
+CONFIG_PTHREAD_ATTRIBUTES = 'defined'
+CONFIG_CPU_X86_SYSENTER = 'undefined'
+CONFIG_SOCLIB_MEMCHECK_ADDRESS = 'undefined'
+CONFIG_DRIVER_INPUT_8042 = 'undefined'
+CONFIG_MODULES = 'splash_radix:/home/share/dcis_scme/THESES/GUTHMULLER/tsar/platforms/tsarv3_mutekh/splash_radix libfdt:/home/guthmuller/dev/mutekh/libfdt libpthread:/home/guthmuller/dev/mutekh/libpthread cpu:/home/guthmuller/dev/mutekh/cpu/mips libcrypto:/home/guthmuller/dev/mutekh/libcrypto arch:/home/guthmuller/dev/mutekh/arch/soclib'
+CONFIG_HEXO_MMU = 'undefined'
+CONFIG_DEBUG_SPINLOCK_LIMIT = 'undefined'
+CONFIG_DRIVER_FS_ISO9660_ROCKRIDGE = 'undefined'
+CONFIG_COMPILE_COLLECT = 'undefined'
+CONFIG_LIBC_STRING_ASM = 'undefined'
+CONFIG_LIBCRYPTO_ARC4 = 'undefined'
+CONFIG_MUTEK_TIMERMS = 'undefined'
+CONFIG_DRIVER_BLOCK_PARTITION = 'undefined'
+CONFIG_MWMR_SOCLIB = 'undefined'
+CONFIG_DRIVER_KEYBOARD = 'undefined'
+CONFIG_SMP = 'defined'
+CONFIG_LICENSE_APP_MIT = 'undefined'
+CONFIG_COMPILE_DEBUG = 'defined'
+CONFIG_HEXO_IPI = 'defined'
+CONFIG_DRIVER_TIMER = 'undefined'
+CONFIG_NETWORK = 'undefined'
+CONFIG_DRIVER_UART = 'undefined'
+CONFIG_SRL_VERBOSITY = 'undefined'
+CONFIG_UNIX_DEBUG = 'undefined'
+CONFIG_DRIVER_MEM = 'defined'
+CONFIG_DRIVER_CHAR_RANDOM = 'undefined'
+CONFIG_LIBELF_RTLD_KERNEL = 'undefined'
+CONFIG_MUTEK_LOGO = 'undefined'
+CONFIG_CPU_ARM_ARCH = 'undefined'
+CONFIG_MUTEK_SMP_APP_START = 'defined'
+CONFIG_MUTEK_SCHEDULER_STATIC = 'undefined'
+CONFIG_DRIVER_LCD_PCF8833 = 'undefined'
+CONFIG_ARCH_SIMPLE_ATMEGA128 = 'undefined'
+CONFIG_ARCH_HW_INIT_USER = 'undefined'
+CONFIG_HETROM_ADDR = 'undefined'
+CONFIG_DRIVER_FS_FAT_TYPE_FROM_STRING = 'undefined'
+CONFIG_LIBCRYPTO_CRC32 = 'undefined'
+CONFIG_COMPILE_OPTIMIZE = '2'
+CONFIG_MUTEK_RWLOCK = 'defined'
+CONFIG_DATA_FROM_ROM = 'defined'
+CONFIG_MUTEK_SCHEDULER_MIGRATION_AFFINITY = 'undefined'
+CONFIG_DRIVER_GPIO_SAM7 = 'undefined'
+CONFIG_MUTEK_MEM_REGION = 'undefined'
+CONFIG_DRIVER_TIMER_8253 = 'undefined'
+CONFIG_DRIVER_TIMER_EMU = 'undefined'
+CONFIG_CPU_ARM_CPU = 'undefined'
+CONFIG_DRIVER_INPUT_MT5F = 'undefined'
+CONFIG_DRIVER_CHAR_VGATTY = 'undefined'
+CONFIG_DEVICE_TREE = 'defined'
+CONFIG_NETWORK_PING = 'undefined'
+CONFIG_RAM_SIZE = '0x01000000'
+CONFIG_VFS_GLOBAL_ROOT = 'undefined'
+CONFIG_LIBC_STREAM_STD = 'undefined'
+CONFIG_LIBELF_RTLD_TLS = 'undefined'
+CONFIG_UNIX_KSTACK_SIZE = 'undefined'
+CONFIG_LIBM = 'undefined'
+CONFIG_CPU_ARM = 'undefined'
+CONFIG_MUTEK_SCHEDULER_MIGRATION = 'defined'
+CONFIG_VFS = 'undefined'
+CONFIG_PTHREAD_STACK_SIZE = '4096'
+CONFIG_LIBDSRL = 'undefined'
Index: branches/v4/platforms/tsarv2_mutekh/segmentation.h
===================================================================
--- branches/v4/platforms/tsarv2_mutekh/segmentation.h	(revision 371)
+++ branches/v4/platforms/tsarv2_mutekh/segmentation.h	(revision 371)
@@ -0,0 +1,86 @@
+/*
+   This file is part of MutekP.
+  
+   MutekP is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 2 of the License, or
+   (at your option) any later version.
+  
+   MutekP is distributed in the hope that it will be useful, but
+   WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+   General Public License for more details.
+  
+   You should have received a copy of the GNU General Public License
+   along with MutekP; if not, write to the Free Software Foundation,
+   Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+  
+   UPMC / LIP6 / SOC (c) 2009
+   Copyright Ghassan Almaless <ghassan.almaless@gmail.com>
+*/
+
+
+/////////////////////////////////////////
+//   Devices mapped segments 
+/////////////////////////////////////////
+#define     LOCKS_BASE  0xd4200000
+#define     LOCKS_SIZE  0x00010000
+
+#define     TIMER_BASE  0xd3200000
+#define     TIMER_SIZE  0x00000080
+
+#define     ICU_BASE    0xd2200000
+#define     ICU_SIZE    0x00000020
+
+#define	    DMA_BASE	0xd1200000
+#define	    DMA_SIZE	0x00000014
+
+#define     TTY_BASE    0xd0200000
+#define     TTY_SIZE    0x00000040
+
+#define     SIMH_BASE     0xd5200000
+#define     SIMH_SIZE     0x20
+
+////////////////////////////////////////
+
+
+//////////////////////////////////////////
+//       ROM mapped segments
+//////////////////////////////////////////
+
+
+#define    BOOT_BASE       0xbfc00000
+#define    BOOT_SIZE       0x00010000
+//////////////////////////////////////////
+
+//////////////////////////////////////////
+//                RAM
+//////////////////////////////////////////
+#define	TEXT_BASE	0x00400000
+#define	TEXT_SIZE	0x00050000
+
+#define	EXCEP_BASE	0x80000000
+#define	EXCEP_SIZE	0x00010000
+
+#define     RAM_BASE    0x10000000
+#define     RAM_SIZE    0x01000000
+//////////////////////////////////////////
+
+
+////////////////////////////////////////
+//	Reserved segments
+////////////////////////////////////////
+
+#define PROC0_BASE	0x01200000
+#define PROC0_SIZE	0x0000000F
+
+#define PROC1_BASE	0x02200000
+#define PROC1_SIZE	0x0000000F
+
+#define PROC2_BASE	0x03200000
+#define PROC2_SIZE	0x0000000F
+
+#define PROC3_BASE	0x04200000
+#define PROC3_SIZE	0x0000000F
+
+////////////////////////////////////////
Index: branches/v4/platforms/tsarv2_mutekh/top.cpp
===================================================================
--- branches/v4/platforms/tsarv2_mutekh/top.cpp	(revision 371)
+++ branches/v4/platforms/tsarv2_mutekh/top.cpp	(revision 371)
@@ -0,0 +1,383 @@
+
+#include <systemc>
+#include <sys/time.h>
+#include <iostream>
+#include <cstdlib>
+#include <cstdarg>
+
+#include "mapping_table.h"
+#include "mips32.h"
+#include "vci_simple_ram.h"
+#include "vci_multi_tty.h"
+#include "vci_simple_ring_fast.h"
+#include "vci_vgmn.h"
+#include "vci_mem_cache_v2.h"
+#include "vci_cc_xcache_wrapper_v1.h"
+#include "vci_logger.h"
+#include "vci_xicu.h"
+
+#define USE_GDB_SERVER
+
+#ifdef USE_GDB_SERVER
+#include "gdbserver.h"
+#endif
+
+//#define  VCI_LOGGER_ON_L1
+//#define  VCI_LOGGER_ON_ROM
+//#define VCI_LOGGER_ON_DMA
+
+// If you want to use the VGMN or the RING
+//#define USE_VGMN
+
+#define CYCLES 100000
+
+#include "segmentation.h"
+
+int _main(int argc, char *argv[])
+{
+	using namespace sc_core;
+	// Avoid repeating these everywhere
+	using soclib::common::IntTab;
+	using soclib::common::Segment;
+
+	// Define VCI parameters
+	typedef soclib::caba::VciParams<4,8,32,1,1,1,8,4,4,1> vci_param;
+	typedef soclib::common::Mips32ElIss ProcessorIss;
+#ifdef USE_GDB_SERVER
+        typedef soclib::common::GdbServer<ProcessorIss> proc_iss;
+#else
+	typedef ProcessorIss proc_iss;
+#endif
+	// Mapping table
+        soclib::common::MappingTable maptabp(32, IntTab(8), IntTab(8), 0xFF000000);
+        maptabp.add(Segment("resetmips", 0xbfc00000, 0x2000, IntTab(0), true));
+        maptabp.add(Segment("excep", 0x80000000, 0x100000, IntTab(0), true));
+
+        maptabp.add(Segment("text" ,     0x60100000, 0x00100000, IntTab(1), true));
+        maptabp.add(Segment("data",      0x71600000, 0x01000000, IntTab(1), true));
+        maptabp.add(Segment("rodata" ,   0x61100000, 0x01000000, IntTab(1), true));
+
+        maptabp.add(Segment("tty"  ,     0x90600000, 0x00000010, IntTab(2), false));
+        maptabp.add(Segment("xicu",      0x20600000, 0x00001000, IntTab(3), false));
+
+ 
+	std::cout << maptabp << std::endl;
+
+        soclib::common::MappingTable maptabc(32, IntTab(8), IntTab(8), 0xFF000000);
+	maptabc.add(Segment("c_proc0" , PROC0_BASE , PROC0_SIZE , IntTab(0), false, true, IntTab(0)));
+	maptabc.add(Segment("c_proc1" , PROC1_BASE , PROC1_SIZE , IntTab(1), false, true, IntTab(1)));
+	maptabc.add(Segment("c_proc2" , PROC2_BASE , PROC2_SIZE , IntTab(2), false, true, IntTab(2)));
+	maptabc.add(Segment("c_proc3" , PROC3_BASE , PROC3_SIZE , IntTab(3), false, true, IntTab(3)));
+
+        maptabc.add(Segment("resetmips", 0xbfc00000, 0x2000, IntTab(4), false));
+        maptabc.add(Segment("excep", 0x80000000, 0x100000, IntTab(4), true));
+
+        maptabc.add(Segment("text" ,     0x60100000, 0x00100000, IntTab(4), false));
+        maptabc.add(Segment("data",      0x71600000, 0x01000000, IntTab(4), false));
+        maptabc.add(Segment("rodata" ,   0x61100000, 0x01000000, IntTab(4), false));
+
+
+
+	std::cout << maptabc << std::endl;
+	
+	soclib::common::MappingTable maptabx(32, IntTab(8), IntTab(8), 0x30000000);
+	maptabx.add(Segment("data" , 0x71600000 , 0x01000000 , IntTab(0), false));
+	maptabx.add(Segment("text" , 0x60100000 , 0x00100000 , IntTab(0), false));
+	maptabx.add(Segment("rodata" , 0x61100000 , 0x01000000 , IntTab(0), false));
+	
+	
+	std::cout << maptabx << std::endl;
+
+	// Signals
+
+	sc_clock	signal_clk("clk");
+	sc_signal<bool> signal_resetn("resetn");
+   
+	sc_signal<bool> signal_proc0_it0("proc0_it0"); 
+	sc_signal<bool> signal_proc0_it1("proc0_it1"); 
+	sc_signal<bool> signal_proc0_it2("proc0_it2"); 
+	sc_signal<bool> signal_proc0_it3("proc0_it3"); 
+	sc_signal<bool> signal_proc0_it4("proc0_it4"); 
+	sc_signal<bool> signal_proc0_it5("proc0_it5");
+
+	sc_signal<bool> signal_proc1_it0("proc1_it0"); 
+	sc_signal<bool> signal_proc1_it1("proc1_it1"); 
+	sc_signal<bool> signal_proc1_it2("proc1_it2"); 
+	sc_signal<bool> signal_proc1_it3("proc1_it3"); 
+	sc_signal<bool> signal_proc1_it4("proc1_it4"); 
+	sc_signal<bool> signal_proc1_it5("proc1_it5");
+
+	sc_signal<bool> signal_proc2_it0("proc2_it0"); 
+	sc_signal<bool> signal_proc2_it1("proc2_it1"); 
+	sc_signal<bool> signal_proc2_it2("proc2_it2"); 
+	sc_signal<bool> signal_proc2_it3("proc2_it3"); 
+	sc_signal<bool> signal_proc2_it4("proc2_it4"); 
+	sc_signal<bool> signal_proc2_it5("proc2_it5");
+
+	sc_signal<bool> signal_proc3_it0("proc3_it0"); 
+	sc_signal<bool> signal_proc3_it1("proc3_it1"); 
+	sc_signal<bool> signal_proc3_it2("proc3_it2"); 
+	sc_signal<bool> signal_proc3_it3("proc3_it3"); 
+	sc_signal<bool> signal_proc3_it4("proc3_it4"); 
+	sc_signal<bool> signal_proc3_it5("proc3_it5");
+
+
+	soclib::caba::VciSignals<vci_param> signal_vci_ini_rw_proc0("vci_ini_rw_proc0");
+	soclib::caba::VciSignals<vci_param> signal_vci_ini_c_proc0("vci_ini_c_proc0");
+
+	soclib::caba::VciSignals<vci_param> signal_vci_tgt_proc0("vci_tgt_proc0");
+
+	soclib::caba::VciSignals<vci_param> signal_vci_ini_rw_proc1("vci_ini_rw_proc1");
+	soclib::caba::VciSignals<vci_param> signal_vci_ini_c_proc1("vci_ini_c_proc1");
+
+	soclib::caba::VciSignals<vci_param> signal_vci_tgt_proc1("vci_tgt_proc1");
+
+	soclib::caba::VciSignals<vci_param> signal_vci_ini_rw_proc2("vci_ini_rw_proc2");
+	soclib::caba::VciSignals<vci_param> signal_vci_ini_c_proc2("vci_ini_c_proc2");
+
+	soclib::caba::VciSignals<vci_param> signal_vci_tgt_proc2("vci_tgt_proc2");
+
+	soclib::caba::VciSignals<vci_param> signal_vci_ini_rw_proc3("vci_ini_rw_proc3");
+	soclib::caba::VciSignals<vci_param> signal_vci_ini_c_proc3("vci_ini_c_proc3");
+	soclib::caba::VciSignals<vci_param> signal_vci_tgt_proc3("vci_tgt_proc3");
+
+
+	soclib::caba::VciSignals<vci_param> signal_vci_tty("signal_vci_tty");
+	soclib::caba::VciSignals<vci_param> signal_vci_vcitimer("signal_vci_vcitimer");
+	
+	soclib::caba::VciSignals<vci_param> signal_vci_icu("signal_vci_icu");
+	soclib::caba::VciSignals<vci_param> signal_vci_dmai("signal_vci_dmai");
+	soclib::caba::VciSignals<vci_param> signal_vci_dmat("signal_vci_dmat");
+	soclib::caba::VciSignals<vci_param> signal_vci_simhelper("signal_vci_simhelper");
+	soclib::caba::VciSignals<vci_param> signal_vci_tgt_rom("vci_tgt_rom");
+
+	soclib::caba::VciSignals<vci_param> signal_vci_tgt_xram("vci_tgt_xram");
+
+	soclib::caba::VciSignals<vci_param> signal_vci_ini_memc("vci_ini_memc");
+	soclib::caba::VciSignals<vci_param> signal_vci_tgt_memc("vci_tgt_memc");
+	soclib::caba::VciSignals<vci_param> signal_vci_tgt_cleanup_memc("vci_tgt_cleanup_memc");
+
+	sc_signal<bool> signal_icu_irq0("signal_icu_irq0");
+	sc_signal<bool> signal_icu_irq1("signal_icu_irq1");
+	sc_signal<bool> signal_icu_irq2("signal_icu_irq2");
+	sc_signal<bool> signal_icu_irq3("signal_icu_irq3");
+	sc_signal<bool> signal_icu_irq4("signal_icu_irq4");
+	sc_signal<bool> signal_icu_irq5("signal_icu_irq5");
+	sc_signal<bool> signal_icu_irq6("signal_icu_irq6");
+
+	soclib::common::Loader loader("mutekh/kernel-soclib-mips.out");
+
+        //                                  init_rw   init_c   tgt
+	soclib::caba::VciCcXCacheWrapperV1<vci_param, proc_iss > 
+	proc0("proc0", 0, maptabp, maptabc, IntTab(0),IntTab(0),IntTab(0),4,64,16,4,64,16);
+
+	soclib::caba::VciCcXCacheWrapperV1<vci_param, proc_iss > 
+	proc1("proc1", 1, maptabp, maptabc, IntTab(1),IntTab(1),IntTab(1),4,64,16,4,64,16);
+
+	soclib::caba::VciCcXCacheWrapperV1<vci_param, proc_iss > 
+	proc2("proc2", 2, maptabp, maptabc, IntTab(2),IntTab(2),IntTab(2),4,64,16,4,64,16);
+
+	soclib::caba::VciCcXCacheWrapperV1<vci_param, proc_iss > 
+	proc3("proc3", 3, maptabp, maptabc, IntTab(3),IntTab(3),IntTab(3),4,64,16,4,64,16);
+
+	soclib::caba::VciSimpleRam<vci_param> 
+	rom("rom", IntTab(0), maptabp, loader);
+
+	soclib::caba::VciSimpleRam<vci_param> 
+	xram("xram", IntTab(0), maptabx, loader);
+
+        //                                  x_init    c_init    p_tgt     c_tgt
+	//soclib::caba::VciMemCacheV3<vci_param> 
+	//memc("memc",maptabp,maptabc,maptabx,IntTab(0),IntTab(4),IntTab(1), IntTab(4),16,256,16,1024);
+	//memc("memc",maptabp,maptabc,maptabx,IntTab(0),IntTab(4),IntTab(1), IntTab(4),4,16,16,32);
+	soclib::caba::VciMemCacheV2<vci_param> 
+	memc("memc",maptabp,maptabc,maptabx,IntTab(0),IntTab(4),IntTab(1), IntTab(4),16,256,16);
+       
+
+	soclib::caba::VciMultiTty<vci_param> vcitty("vcitty",	IntTab(2), maptabp, "vcitty", NULL);
+        soclib::caba::VciXicu<vci_param> vcixicu("vcixicu", maptabp, IntTab(3), 4, 1, 4, 4);
+	
+
+#ifdef VCI_LOGGER_ON_L1
+  soclib::caba::VciLogger<vci_param> vci_logger0("vci_logger0",maptabp);
+#endif
+
+#ifdef VCI_LOGGER_ON_ROM
+  soclib::caba::VciLogger<vci_param> vci_logger1("vci_logger1",maptabp);
+#endif
+#ifdef VCI_LOGGER_ON_DMA
+  soclib::caba::VciLogger<vci_param> vci_logger2("vci_logger2",maptabp);
+#endif
+
+#ifdef USE_VGMN
+	soclib::caba::VciVgmn<vci_param> 
+	ringp("ringp",maptabp, 4, 4, 2, 8);
+
+	soclib::caba::VciVgmn<vci_param> 
+	ringc("ringc",maptabc, 5, 5, 2, 8);
+
+#else
+	soclib::caba::VciSimpleRingFast<vci_param, 40, 33> 
+	ringp("ringp",maptabp, IntTab(), 2, 4, 4);
+
+	soclib::caba::VciSimpleRingFast<vci_param, 40, 33> 
+	ringc("ringc",maptabc, IntTab(), 2, 5, 5);
+
+#endif
+
+	proc0.p_clk(signal_clk);  
+	proc0.p_resetn(signal_resetn);  
+	proc0.p_irq[0](signal_proc0_it0); 
+	proc0.p_irq[1](signal_proc0_it1); 
+	proc0.p_irq[2](signal_proc0_it2); 
+	proc0.p_irq[3](signal_proc0_it3); 
+	proc0.p_irq[4](signal_proc0_it4); 
+	proc0.p_irq[5](signal_proc0_it5); 
+	proc0.p_vci_ini_rw(signal_vci_ini_rw_proc0);
+	proc0.p_vci_ini_c(signal_vci_ini_c_proc0);
+	proc0.p_vci_tgt(signal_vci_tgt_proc0);
+
+
+	proc1.p_clk(signal_clk);  
+	proc1.p_resetn(signal_resetn);  
+	proc1.p_irq[0](signal_proc1_it0); 
+	proc1.p_irq[1](signal_proc1_it1); 
+	proc1.p_irq[2](signal_proc1_it2); 
+	proc1.p_irq[3](signal_proc1_it3); 
+	proc1.p_irq[4](signal_proc1_it4); 
+	proc1.p_irq[5](signal_proc1_it5); 
+	proc1.p_vci_ini_rw(signal_vci_ini_rw_proc1);
+	proc1.p_vci_ini_c(signal_vci_ini_c_proc1);
+	proc1.p_vci_tgt(signal_vci_tgt_proc1);
+
+	proc2.p_clk(signal_clk);  
+	proc2.p_resetn(signal_resetn);  
+	proc2.p_irq[0](signal_proc2_it0); 
+	proc2.p_irq[1](signal_proc2_it1); 
+	proc2.p_irq[2](signal_proc2_it2); 
+	proc2.p_irq[3](signal_proc2_it3); 
+	proc2.p_irq[4](signal_proc2_it4); 
+	proc2.p_irq[5](signal_proc2_it5); 
+	proc2.p_vci_ini_rw(signal_vci_ini_rw_proc2);
+	proc2.p_vci_ini_c(signal_vci_ini_c_proc2);
+	proc2.p_vci_tgt(signal_vci_tgt_proc2);
+
+	proc3.p_clk(signal_clk);  
+	proc3.p_resetn(signal_resetn);  
+	proc3.p_irq[0](signal_proc3_it0); 
+	proc3.p_irq[1](signal_proc3_it1); 
+	proc3.p_irq[2](signal_proc3_it2); 
+	proc3.p_irq[3](signal_proc3_it3); 
+	proc3.p_irq[4](signal_proc3_it4); 
+	proc3.p_irq[5](signal_proc3_it5); 
+	proc3.p_vci_ini_rw(signal_vci_ini_rw_proc3);
+	proc3.p_vci_ini_c(signal_vci_ini_c_proc3);
+	proc3.p_vci_tgt(signal_vci_tgt_proc3);
+
+	rom.p_clk(signal_clk);
+	rom.p_resetn(signal_resetn);
+	rom.p_vci(signal_vci_tgt_rom);
+
+
+	vcixicu.p_clk(signal_clk);
+	vcixicu.p_vci(signal_vci_icu);
+	vcixicu.p_hwi[0](signal_icu_irq0);
+	vcixicu.p_irq[0](signal_proc0_it0);
+	vcixicu.p_irq[1](signal_proc1_it0);
+	vcixicu.p_irq[2](signal_proc2_it0);
+	vcixicu.p_irq[3](signal_proc3_it0);
+	vcixicu.p_resetn(signal_resetn);
+
+
+#ifdef VCI_LOGGER_ON_L1
+  vci_logger0.p_clk(signal_clk);
+  vci_logger0.p_resetn(signal_resetn);
+  vci_logger0.p_vci(signal_vci_ini_rw_proc0);
+#endif
+
+#ifdef VCI_LOGGER_ON_ROM
+  vci_logger1.p_clk(signal_clk);
+  vci_logger1.p_resetn(signal_resetn);
+  vci_logger1.p_vci(signal_vci_tgt_rom);
+#endif
+
+	vcitty.p_clk(signal_clk);
+	vcitty.p_resetn(signal_resetn);
+	vcitty.p_vci(signal_vci_tty);
+	vcitty.p_irq[0](signal_icu_irq0); 
+	
+
+	memc.p_clk(signal_clk);
+	memc.p_resetn(signal_resetn);
+	memc.p_vci_tgt(signal_vci_tgt_memc);
+	memc.p_vci_tgt_cleanup(signal_vci_tgt_cleanup_memc);
+	memc.p_vci_ini(signal_vci_ini_memc);
+	memc.p_vci_ixr(signal_vci_tgt_xram);
+
+	xram.p_clk(signal_clk);
+	xram.p_resetn(signal_resetn);
+	xram.p_vci(signal_vci_tgt_xram);
+	
+	ringp.p_clk(signal_clk);
+	ringp.p_resetn(signal_resetn);
+
+	ringc.p_clk(signal_clk);
+	ringc.p_resetn(signal_resetn);
+
+
+	ringp.p_to_initiator[0](signal_vci_ini_rw_proc0);
+	ringp.p_to_initiator[1](signal_vci_ini_rw_proc1);
+	ringp.p_to_initiator[2](signal_vci_ini_rw_proc2);
+	ringp.p_to_initiator[3](signal_vci_ini_rw_proc3);
+
+	ringc.p_to_initiator[4](signal_vci_ini_memc);
+	ringc.p_to_initiator[0](signal_vci_ini_c_proc0);
+	ringc.p_to_initiator[1](signal_vci_ini_c_proc1);
+	ringc.p_to_initiator[2](signal_vci_ini_c_proc2);
+	ringc.p_to_initiator[3](signal_vci_ini_c_proc3);
+
+	ringp.p_to_target[0](signal_vci_tgt_rom);
+	ringp.p_to_target[1](signal_vci_tgt_memc);
+	ringp.p_to_target[2](signal_vci_tty);
+	ringp.p_to_target[3](signal_vci_icu);
+	
+	ringc.p_to_target[0](signal_vci_tgt_proc0);
+	ringc.p_to_target[1](signal_vci_tgt_proc1);
+	ringc.p_to_target[2](signal_vci_tgt_proc2);
+	ringc.p_to_target[3](signal_vci_tgt_proc3);
+	ringc.p_to_target[4](signal_vci_tgt_cleanup_memc);
+
+
+	int ncycles;
+
+	sc_start(sc_core::sc_time(0, SC_NS));
+	signal_resetn = false;
+
+	sc_start(sc_core::sc_time(1, SC_NS));
+	signal_resetn = true;
+
+	while(1)
+	{
+	  sc_start(sc_core::sc_time(CYCLES, SC_NS));
+	}
+
+        std::cout << "Hit ENTER to end simulation" << std::endl;
+        char buf[1];
+
+	std::cin.getline(buf,1);
+
+	return EXIT_SUCCESS;
+}
+
+int sc_main (int argc, char *argv[])
+{
+	try {
+		return _main(argc, argv);
+	} catch (std::exception &e) {
+		std::cout << e.what() << std::endl;
+	} catch (...) {
+		std::cout << "Unknown exception occured" << std::endl;
+		throw;
+	}
+	return 1;
+}
Index: branches/v4/platforms/tsarv4_dspin_generic_32/Makefile
===================================================================
--- branches/v4/platforms/tsarv4_dspin_generic_32/Makefile	(revision 371)
+++ branches/v4/platforms/tsarv4_dspin_generic_32/Makefile	(revision 371)
@@ -0,0 +1,6 @@
+
+simulator.x: tsarv4_dspin_generic_32_top.cpp tsarv4_dspin_generic_32_desc
+	soclib-cc -p tsarv4_dspin_generic_32_desc -o simulator.x
+
+clean:
+	rm -rf *o simulator.x temp tty*
Index: branches/v4/platforms/tsarv4_dspin_generic_32/tsarv4_dspin_generic_32_desc
===================================================================
--- branches/v4/platforms/tsarv4_dspin_generic_32/tsarv4_dspin_generic_32_desc	(revision 371)
+++ branches/v4/platforms/tsarv4_dspin_generic_32/tsarv4_dspin_generic_32_desc	(revision 371)
@@ -0,0 +1,31 @@
+
+# -*- python -*-
+
+todo = Platform('caba', 'tsarv4_dspin_generic_32_top.cpp',
+	uses = [
+            Uses('caba:vci_cc_xcache_wrapper_v4', iss_t = 'common:mips32el'),
+            Uses('caba:vci_cc_xcache_wrapper_v4', iss_t = 'common:gdb_iss', gdb_iss_t = 'common:mips32el'),
+            Uses('caba:vci_mem_cache_v4'),
+	    Uses('caba:vci_simple_ram'),
+	    Uses('caba:vci_multi_tty'),
+	    Uses('caba:vci_xicu'),
+	    Uses('caba:vci_vgmn'),
+	    Uses('caba:vci_framebuffer'),
+	    Uses('caba:vci_block_device_tsar_v2'),
+	    Uses('caba:vci_dma_tsar_v2'),
+	    Uses('caba:virtual_dspin_router', flit_width = 40),
+ 	    Uses('caba:virtual_dspin_router', flit_width = 33),
+ 	    Uses('caba:vci_local_ring_fast', ring_cmd_data_size = 40, ring_rsp_data_size = 33),
+	    Uses('common:elf_file_loader'),
+	],
+	cell_size = 4,
+	plen_size = 8,
+	addr_size = 32,
+	rerror_size = 1,
+	clen_size = 1,
+	rflag_size = 1,
+	srcid_size = 14,
+	pktid_size = 4,
+	trdid_size = 4,
+	wrplen_size = 1,
+)
Index: branches/v4/platforms/tsarv4_dspin_generic_32/tsarv4_dspin_generic_32_top.cpp
===================================================================
--- branches/v4/platforms/tsarv4_dspin_generic_32/tsarv4_dspin_generic_32_top.cpp	(revision 371)
+++ branches/v4/platforms/tsarv4_dspin_generic_32/tsarv4_dspin_generic_32_top.cpp	(revision 371)
@@ -0,0 +1,990 @@
+/////////////////////////////////////////////////////////////////////////
+// File: tsarv4_dspin_generic_32_top.cpp
+// Author: Alain Greiner
+// Copyright: UPMC/LIP6
+// Date : november 5 2010
+// This program is released under the GNU public license
+/////////////////////////////////////////////////////////////////////////
+// This file define a generic TSAR architecture without virtual memory.
+// - It uses the virtual_dspin network as global interconnect 
+// - It uses the vci_local_ring_fast as local interconnect 
+// - It uses the vci_cc_xcache (No MMU)  
+// The physical address space is 32 bits.
+// The number of clusters cannot be larger than 256.
+// The three parameters are 
+// - xmax : number of clusters in a row
+// - ymax : number of clusters in a column
+// - nprocs : number of processor per cluster
+//
+// Each cluster contains nprocs processors, one Memory Cache,
+// and one XICU component.
+// The peripherals BDEV, CDMA, FBUF, MTTY and the boot BROM
+// are in the cluster containing address 0xBFC00000.
+// - The bdev_irq is connected to IRQ_IN[0]
+// - The cdma_irq is connected to IRQ_IN[1]
+// - The tty_irq[i] is connected to IRQ_IN[i+2]
+// For all clusters, the XICU component contains nprocs timers.
+//
+// As we target up to 256 clusters, each cluster can contain 
+// at most 16 Mbytes (in a 4Gbytes address space).
+// - Each memory cache contains 9 Mbytes.
+// - The Frame buffer contains 2 Mbytes.
+// - The Boot ROM contains 1 Mbytes.
+//
+// General policy for 32 bits address decoding:
+// To simplifly, all segments base addresses are aligned
+// on 1 Mbyte adresses. Therefore the 12 address MSB bits
+// define the target in the direct address space.
+// In these 12 bits, the (x_width + y_width) MSB bits define
+// the cluster index, and the 4 LSB bits define the local index:
+// 
+//      | X_ID  | Y_ID  |---| L_ID |     OFFSET          |
+//	|x_width|y_width|---|  4   |       20            |
+/////////////////////////////////////////////////////////////////////////
+
+#include <systemc>
+#include <sys/time.h>
+#include <iostream>
+#include <sstream>
+#include <cstdlib>
+#include <cstdarg>
+
+#include "mapping_table.h"
+#include "mips32.h"
+#include "vci_simple_ram.h"
+#include "vci_multi_tty.h"
+#include "vci_mem_cache_v4.h"
+#include "vci_cc_xcache_wrapper_v4.h"
+#include "vci_xicu.h"
+#include "vci_vgmn.h"
+#include "vci_local_ring_fast.h"
+#include "virtual_dspin_router.h"
+#include "vci_framebuffer.h"
+#include "vci_dma_tsar_v2.h"
+#include "vci_block_device_tsar_v2.h"
+#include "gdbserver.h"
+
+#define SECTOR_SIZE     2048
+
+#define FBUF_XSIZE      960
+#define FBUF_YSIZE      960
+
+#define N_TTYS		4
+
+//////////////////////////////////////////////
+// segments definition in direct space.
+// There is 16 Mbytes address space per cluster.
+// The 8 MSB bits define the cluster index (x,y),
+// even if the number of clusters is less than 256.
+// Each memory cache contains up to 9 Mbytes.
+// There is one MEMC segment and one XICU segment per cluster
+// The peripherals BDEV, FBUF, MTTY, CDMA and the boot BROM
+// are mapped in cluster containing address 0xBFC00000
+
+#define	MEMC_BASE	0x00000000	
+#define MEMC_SIZE	0x00900000
+
+#define	XICU_BASE	0x00900000	
+#define XICU_SIZE	0x00001000
+
+#define	FBUF_BASE	0xBFA00000	
+#define FBUF_SIZE	0x00200000
+
+#define	BROM_BASE	0xBFC00000	
+#define BROM_SIZE	0x00100000
+
+#define	BDEV_BASE	0xBFD00000	
+#define BDEV_SIZE	0x00000100
+
+#define	MTTY_BASE	0xBFE00000	
+#define MTTY_SIZE	0x00000100
+
+#define	CDMA_BASE	0xBFF00000	
+#define CDMA_SIZE	0x00000100
+
+///////////////////////////////////////////////////////////
+//     TGTID & SRCID definition in direct space
+// For all components:  global TGTID = global SRCID = cluster_index
+// For processors, the local SRCID is between 0 & nprocs-1
+
+#define MEMC_TGTID	0
+#define XICU_TGTID	1
+#define FBUF_TGTID	2
+#define MTTY_TGTID	3
+#define BROM_TGTID	4
+#define BDEV_TGTID	5
+#define CDMA_TGTID	6
+
+#define PROC_SRCID      0
+#define BDEV_SRCID      nprocs
+#define CDMA_SRCID      (nprocs+1)
+
+////////////////////////////////////////////////////////
+// Local TGTID & SRCID definition in coherence space
+// (The global TGTID & SRCID is the cluster index)
+// For MEMC, the local SRCID is 0
+// For processors, the local SRCID is between 1 & nprocs
+
+/////////////////////////
+// Router ports index
+
+#define NORTH		0
+#define SOUTH		1
+#define EAST		2
+#define WEST		3
+#define LOCAL		4
+
+///////////////////////////////////
+// flit widths for the DSPIN network
+
+#define cmd_width	40
+#define rsp_width	33
+
+//////////////////
+// VCI format
+
+#define cell_width	4
+#define address_width	32
+#define plen_width	8
+#define error_width	1
+#define clen_width	1
+#define rflag_width	1
+#define srcid_width	14
+#define pktid_width	4
+#define trdid_width	4
+#define wrplen_width	1
+
+//  cluster index (computed from x,y coordinates)
+#define cluster(x,y)	(y + ymax*x)
+
+/////////////////////////////////
+int _main(int argc, char *argv[])
+{
+    using namespace sc_core;
+    using namespace soclib::caba;
+    using namespace soclib::common;
+
+    char    soft_name[128]  = "undefined_binary_file";  // pathname to binary code
+    char    disk_name[128]  = "undefined_disk_image";   // pathname to the disk image
+    size_t  ncycles         = 1000000000;       	// simulated cycles
+    size_t  xmax            = 2;         		// number of clusters in a row
+    size_t  ymax            = 2;                	// number of clusters in a column
+    size_t  nprocs          = 1;         		// number of processors per cluster
+    bool    debug_ok        = false;            	// debug activated
+    size_t  from_cycle      = 0;                	// debug start cycle
+    size_t  to_cycle        = 1000000000;       	// debug end cycle
+
+    ////////////// command line arguments //////////////////////
+    if (argc > 1)
+    {
+        for( int n=1 ; n<argc ; n=n+2 )
+        {
+            if( (strcmp(argv[n],"-NCYCLES") == 0) && (n+1<argc) )
+            {
+                ncycles = atoi(argv[n+1]);
+            }
+            else if( (strcmp(argv[n],"-NPROCS") == 0) && (n+1<argc) )
+            {
+                nprocs = atoi(argv[n+1]);
+                assert( (nprocs <= 8) && "The number of processors per cluster cannot be larger than 8");
+            }
+            else if( (strcmp(argv[n],"-XMAX") == 0) && (n+1<argc) )
+            {
+                xmax = atoi(argv[n+1]);
+                assert( ((xmax >= 2) && (xmax <= 16))
+                     && "The XMAX parameter (number of clusters in a row) must be in the range [2,16]" );
+            }
+            else if( (strcmp(argv[n],"-YMAX") == 0) && (n+1<argc) )
+            {
+                ymax = atoi(argv[n+1]);
+                assert( ((ymax >= 2) && (ymax <= 16))
+                     && "The YMAX parameter (number of clusters in a column) must be in the range [2,16]" );
+            }
+            else if( (strcmp(argv[n],"-SOFT") == 0) && (n+1<argc) )
+            {
+                strcpy(soft_name, argv[n+1]);
+            }
+            else if( (strcmp(argv[n],"-DISK") == 0) && (n+1<argc) )
+            {
+                strcpy(disk_name, argv[n+1]);
+            }
+            else if( (strcmp(argv[n],"-DEBUG") == 0) && (n+1<argc) )
+            {
+                debug_ok = true;
+                from_cycle = atoi(argv[n+1]);
+            }
+            else if( (strcmp(argv[n],"-TOCYCLE") == 0) && (n+1<argc) )
+            {
+                to_cycle = atoi(argv[n+1]);
+            }
+            else
+            {
+                std::cout << "   Arguments on the command line are (key,value) couples." << std::endl;
+                std::cout << "   The order is not important." << std::endl;
+                std::cout << "   Accepted arguments are :" << std::endl << std::endl;
+                std::cout << "     -SOFT elf_file_name" << std::endl;
+                std::cout << "     -DISK disk_image_file_name" << std::endl;
+                std::cout << "     -NCYCLES number_of_simulated_cycles" << std::endl;
+                std::cout << "     -NPROCS number_of_processors_per_cluster" << std::endl;
+                std::cout << "     -XMAX number_of_clusters_in_a_row" << std::endl;
+                std::cout << "     -YMAX number_of_clusters_in_a_column" << std::endl;
+                std::cout << "     -DEBUG debug_start_cycle" << std::endl;
+                std::cout << "     -TOCYCLE debug_end_cycle" << std::endl;
+                exit(0);
+            }
+        }
+    }
+
+    std::cout << std::endl << "***********  TSAR ARCHITECTURE  **************" << std::endl
+              << " - Interconnect = DSPIN & RING" << std::endl
+              << " - Number of clusters = " << xmax << " * " << ymax << std::endl
+              << " - Number of processors per cluster = " << nprocs << std::endl
+              << "**********************************************" << std::endl
+              << std::endl;
+
+    // Define VCI parameters
+    typedef soclib::caba::VciParams<cell_width,
+                                    plen_width,
+                                    address_width,
+                                    error_width,                                   
+                                    clen_width,
+                                    rflag_width,
+                                    srcid_width,
+                                    pktid_width,
+                                    trdid_width,
+                                    wrplen_width> vci_param;
+
+    size_t			cluster_io_index;
+    size_t			x_width;
+    size_t			y_width;
+
+    if      (xmax == 2) x_width = 1;
+    else if (xmax <= 4) x_width = 2;
+    else if (xmax <= 8) x_width = 3;
+    else                x_width = 4;
+
+    if      (ymax == 2) y_width = 1;
+    else if (ymax <= 4) y_width = 2;
+    else if (ymax <= 8) y_width = 3;
+    else                y_width = 4;
+
+    cluster_io_index = 0xBF >> (8 - x_width - y_width);
+
+    /////////////////////
+    //  Mapping Tables
+    /////////////////////
+
+    // direct network
+    MappingTable maptabd(address_width, 
+                         IntTab(x_width + y_width, 12 - x_width - y_width), 
+                         IntTab(x_width + y_width, srcid_width - x_width - y_width), 
+                         0x00F00000);
+    for ( size_t x = 0 ; x < xmax ; x++)
+    {
+        for ( size_t y = 0 ; y < ymax ; y++)
+        {
+            sc_uint<address_width> offset  = cluster(x,y) << (address_width-x_width-y_width);
+            std::ostringstream 	sm;
+            sm << "d_seg_memc_" << x << "_" << y;
+            maptabd.add(Segment(sm.str(), MEMC_BASE+offset, MEMC_SIZE, IntTab(cluster(x,y),MEMC_TGTID), true));
+            std::ostringstream 	si;
+            si << "d_seg_xicu_" << x << "_" << y;
+            maptabd.add(Segment(si.str(), XICU_BASE+offset, XICU_SIZE, IntTab(cluster(x,y),XICU_TGTID), false));
+            if ( cluster(x,y) == cluster_io_index )
+            {
+            maptabd.add(Segment("d_seg_fbuf", FBUF_BASE, FBUF_SIZE, IntTab(cluster(x,y),FBUF_TGTID), false));
+            maptabd.add(Segment("d_seg_bdev", BDEV_BASE, BDEV_SIZE, IntTab(cluster(x,y),BDEV_TGTID), false));
+            maptabd.add(Segment("d_seg_mtty", MTTY_BASE, MTTY_SIZE, IntTab(cluster(x,y),MTTY_TGTID), false));
+            maptabd.add(Segment("d_seg_brom", BROM_BASE, BROM_SIZE, IntTab(cluster(x,y),BROM_TGTID), true));
+            maptabd.add(Segment("d_seg_cdma", CDMA_BASE, CDMA_SIZE, IntTab(cluster(x,y),CDMA_TGTID), false));
+            }
+        }
+    }
+    std::cout << maptabd << std::endl;
+
+    // coherence network
+    MappingTable maptabc(address_width,
+                         IntTab(x_width + y_width, 12 - x_width - y_width),
+                         IntTab(x_width + y_width, srcid_width - x_width - y_width),
+                         0xF0000000);
+
+    for ( size_t x = 0 ; x < xmax ; x++)
+    {
+        for ( size_t y = 0 ; y < ymax ; y++)
+        {
+            sc_uint<address_width> offset  = cluster(x,y) << (address_width-x_width-y_width);
+
+            std::ostringstream sm;
+            sm << "c_seg_memc_" << x << "_" << y;
+            maptabc.add(Segment(sm.str(), MEMC_BASE+offset, MEMC_SIZE, IntTab(cluster(x,y), nprocs), false));
+            // the segment base and size will be modified 
+            // when the segmentation of the coherence space will be simplified
+
+            if ( cluster(x,y) == cluster_io_index )
+            {
+                std::ostringstream sr;
+                sr << "c_seg_brom_" << x << "_" << y;
+                maptabc.add(Segment(sr.str(), BROM_BASE, BROM_SIZE, IntTab(cluster(x,y), nprocs), false));
+            }
+
+            sc_uint<address_width> avoid_collision  = 0;
+            for ( size_t p = 0 ; p < nprocs ; p++)
+            {
+                sc_uint<address_width> base = MEMC_SIZE + (p*0x100000) + offset;
+                // the following test is to avoid a collision between the c_seg_brom segment
+                // and a c_seg_proc segment (all segments base addresses being multiple of 1Mbytes)
+                if ( base == BROM_BASE ) avoid_collision = 0x100000;
+                std::ostringstream sp;
+                sp << "c_seg_proc_" << x << "_" << y << "_" << p;
+                maptabc.add(Segment(sp.str(), base + avoid_collision, 0x20, IntTab(cluster(x,y), p), false,
+                                  true, IntTab(cluster(x,y), p)));
+                // the two last arguments will be removed 
+                // when the segmentation of the coherence space will be simplified
+            }
+        }
+    }
+    std::cout << maptabc << std::endl;
+
+    // external network
+    MappingTable maptabx(address_width, IntTab(1), IntTab(10), 0xF0000000);
+    for ( size_t x = 0 ; x < xmax ; x++)
+    {
+        for ( size_t y = 0 ; y < ymax ; y++)
+        {
+            sc_uint<address_width> offset  = cluster(x,y) << (address_width-x_width-y_width);
+            std::ostringstream sx;
+            sx << "seg_xram_" << x << "_" << y;
+            maptabx.add(Segment(sx.str(), MEMC_BASE + offset, MEMC_SIZE, IntTab(0), false));
+        }
+    }
+    std::cout << maptabx << std::endl;
+
+    ////////////////////
+    // Signals
+    ///////////////////
+
+    sc_clock		signal_clk("clk");
+    sc_signal<bool> 	signal_resetn("resetn");
+    sc_signal<bool>	signal_false;
+   
+    // IRQ signals (one signal per proc)
+
+    sc_signal<bool>****	signal_proc_it =
+      alloc_elems<sc_signal<bool> >("signal_proc_it", 1,xmax, ymax, nprocs);
+
+    sc_signal<bool>*    signal_irq_mtty =
+        alloc_elems<sc_signal<bool> >("signal_irq_mtty", N_TTYS);
+
+    sc_signal<bool>     signal_irq_bdev;
+    sc_signal<bool>     signal_irq_cdma;
+
+    // Direct VCI signals
+
+    VciSignals<vci_param>*** signal_vci_ini_d_proc = 
+        alloc_elems<VciSignals<vci_param> >("signal_vci_ini_d_proc", xmax, ymax, nprocs);
+
+    VciSignals<vci_param>** signal_vci_tgt_d_memc = 
+        alloc_elems<VciSignals<vci_param> >("signal_vci_tgt_d_memc", xmax, ymax);
+
+    VciSignals<vci_param>** signal_vci_tgt_d_xicu = 
+        alloc_elems<VciSignals<vci_param> >("signal_vci_tgt_d_xicu", xmax, ymax);
+
+    VciSignals<vci_param> signal_vci_tgt_d_mtty("signal_vci_tgt_d_mtty");
+    VciSignals<vci_param> signal_vci_tgt_d_brom("signal_vci_tgt_d_brom");
+    VciSignals<vci_param> signal_vci_tgt_d_bdev("signal_vci_tgt_d_bdev");
+    VciSignals<vci_param> signal_vci_tgt_d_cdma("signal_vci_tgt_d_cdma");
+    VciSignals<vci_param> signal_vci_tgt_d_fbuf("signal_vci_tgt_d_fbuf");
+
+    VciSignals<vci_param> signal_vci_ini_d_bdev("signal_vci_ini_d_bdev");
+    VciSignals<vci_param> signal_vci_ini_d_cdma("signal_vci_ini_d_cdma");
+
+    // Coherence VCI signals
+
+    VciSignals<vci_param>*** signal_vci_ini_c_proc = 
+        alloc_elems<VciSignals<vci_param> >("signal_vci_ini_c_proc", xmax, ymax, nprocs);
+
+    VciSignals<vci_param>*** signal_vci_tgt_c_proc = 
+        alloc_elems<VciSignals<vci_param> >("signal_vci_tgt_c_proc", xmax, ymax, nprocs);
+
+    VciSignals<vci_param>** signal_vci_ini_c_memc = 
+        alloc_elems<VciSignals<vci_param> >("signal_vci_ini_c_memc", xmax, ymax);
+
+    VciSignals<vci_param>** signal_vci_tgt_c_memc = 
+        alloc_elems<VciSignals<vci_param> >("signal_vci_tgt_c_memc", xmax, ymax);
+
+    // DSPIN signals between local ring & global interconnects
+
+    DspinSignals<cmd_width>** signal_dspin_cmd_l2g_d =
+        alloc_elems<DspinSignals<cmd_width> >("signal_dspin_cmd_l2g_d", xmax, ymax);
+    DspinSignals<cmd_width>** signal_dspin_cmd_g2l_d =
+        alloc_elems<DspinSignals<cmd_width> >("signal_dspin_cmd_g2l_d", xmax, ymax);
+
+    DspinSignals<cmd_width>** signal_dspin_cmd_l2g_c =
+        alloc_elems<DspinSignals<cmd_width> >("signal_dspin_cmd_l2g_c", xmax, ymax);
+    DspinSignals<cmd_width>** signal_dspin_cmd_g2l_c =
+        alloc_elems<DspinSignals<cmd_width> >("signal_dspin_cmd_g2l_c", xmax, ymax);
+
+    DspinSignals<rsp_width>** signal_dspin_rsp_l2g_d =
+        alloc_elems<DspinSignals<rsp_width> >("signal_dspin_rsp_l2g_d", xmax, ymax);
+    DspinSignals<rsp_width>** signal_dspin_rsp_g2l_d =
+        alloc_elems<DspinSignals<rsp_width> >("signal_dspin_rsp_g2l_d", xmax, ymax);
+
+    DspinSignals<rsp_width>** signal_dspin_rsp_l2g_c =
+        alloc_elems<DspinSignals<rsp_width> >("signal_dspin_rsp_l2g_c", xmax, ymax);
+    DspinSignals<rsp_width>** signal_dspin_rsp_g2l_c =
+        alloc_elems<DspinSignals<rsp_width> >("signal_dspin_rsp_g2l_c", xmax, ymax);
+
+    // Horizontal inter-clusters DSPIN signals
+    DspinSignals<cmd_width>*** signal_dspin_h_cmd_inc =
+        alloc_elems<DspinSignals<cmd_width> >("signal_dspin_h_cmd_inc", xmax-1, ymax, 2);
+    DspinSignals<cmd_width>*** signal_dspin_h_cmd_dec =
+        alloc_elems<DspinSignals<cmd_width> >("signal_dspin_h_cmd_dec", xmax-1, ymax, 2);
+    DspinSignals<rsp_width>*** signal_dspin_h_rsp_inc =
+        alloc_elems<DspinSignals<rsp_width> >("signal_dspin_h_rsp_inc", xmax-1, ymax, 2);
+    DspinSignals<rsp_width>*** signal_dspin_h_rsp_dec =
+        alloc_elems<DspinSignals<rsp_width> >("signal_dspin_h_rsp_dec", xmax-1, ymax, 2);
+
+    // Vertical inter-clusters DSPIN signals
+    DspinSignals<cmd_width>*** signal_dspin_v_cmd_inc =
+        alloc_elems<DspinSignals<cmd_width> >("signal_dspin_v_cmd_inc", xmax, ymax-1, 2);
+    DspinSignals<cmd_width>*** signal_dspin_v_cmd_dec =
+        alloc_elems<DspinSignals<cmd_width> >("signal_dspin_v_cmd_dec", xmax, ymax-1, 2);
+    DspinSignals<rsp_width>*** signal_dspin_v_rsp_inc =
+        alloc_elems<DspinSignals<rsp_width> >("signal_dspin_v_rsp_inc", xmax, ymax-1, 2);
+    DspinSignals<rsp_width>*** signal_dspin_v_rsp_dec =
+        alloc_elems<DspinSignals<rsp_width> >("signal_dspin_v_rsp_dec", xmax, ymax-1, 2);
+
+    // Mesh boundaries DSPIN signals
+    DspinSignals<cmd_width>**** signal_dspin_false_cmd_in =
+        alloc_elems<DspinSignals<cmd_width> >("signal_dspin_false_cmd_in", xmax,  ymax, 2, 2);
+    DspinSignals<cmd_width>**** signal_dspin_false_cmd_out =
+        alloc_elems<DspinSignals<cmd_width> >("signal_dspin_false_cmd_out", xmax, ymax, 2, 2);
+    DspinSignals<rsp_width>**** signal_dspin_false_rsp_in =
+        alloc_elems<DspinSignals<rsp_width> >("signal_dspin_false_rsp_in", xmax, ymax, 2, 2);
+    DspinSignals<rsp_width>**** signal_dspin_false_rsp_out =
+        alloc_elems<DspinSignals<rsp_width> >("signal_dspin_false_rsp_out", xmax, ymax, 2, 2);
+
+    // Xternal network VCI signals
+    VciSignals<vci_param> signal_vci_tgt_x_xram("signal_vci_tgt_x_xram");
+    VciSignals<vci_param>** signal_vci_ini_x_memc = 
+        alloc_elems<VciSignals<vci_param> >("signal_vci_ini_x_memc", xmax, ymax);
+
+    ////////////////////////////
+    //      Components
+    ////////////////////////////
+
+    typedef soclib::common::GdbServer<soclib::common::Mips32ElIss> proc_iss;
+
+    soclib::common::Loader loader(soft_name);
+    proc_iss::set_loader(loader);
+
+    // External RAM
+    VciSimpleRam<vci_param> xram(
+        "xram", 
+        IntTab(0), 
+        maptabx, 
+        loader);
+
+    // External network
+    VciVgmn<vci_param> xnoc(
+        "xnoc",
+        maptabx, 
+        xmax*ymax,
+        1, 
+        2, 2);
+
+    // Peripherals : TTY, Frame Buffer, Block Device, DMA & Boot ROM 
+    VciSimpleRam<vci_param> brom(
+        "brom", 
+        IntTab(cluster_io_index, BROM_TGTID), 
+        maptabd, 
+        loader);
+
+    VciMultiTty<vci_param> mtty(
+        "mtty",
+        IntTab(cluster_io_index, MTTY_TGTID),
+        maptabd,
+        "tty0","tty1","tty2","tty3",NULL);
+
+    VciFrameBuffer<vci_param> fbuf(
+        "fbuf", 
+        IntTab(cluster_io_index, FBUF_TGTID),
+        maptabd, 
+        FBUF_XSIZE,
+        FBUF_YSIZE);
+
+    VciBlockDeviceTsarV2<vci_param> bdev(
+        "bdev", 
+        maptabd, 
+        IntTab(cluster_io_index, BDEV_SRCID),	// SRCID_D
+        IntTab(cluster_io_index, BDEV_TGTID),	// TGTID_D
+        disk_name,
+        SECTOR_SIZE); 
+
+    VciDmaTsarV2<vci_param> cdma(
+        "cdma",
+        maptabd,
+        IntTab(cluster_io_index,CDMA_SRCID),    // SRCID_D
+        IntTab(cluster_io_index,CDMA_TGTID),    // TGTID_D
+        64);
+
+    // processors (nprocs per cluster)    
+    VciCcXCacheWrapperV4<vci_param, proc_iss> *proc[xmax][ymax][nprocs];
+
+    for( size_t x = 0 ; x < xmax ; x++ )
+    {
+        for( size_t y = 0 ; y < ymax ; y++ )
+        {
+            for ( size_t p = 0 ; p < nprocs ; p++ ) 
+            {
+                std::ostringstream sp;
+                sp << "proc_" << x << "_" << y << "_" << p;
+
+                proc[x][y][p] = new VciCcXCacheWrapperV4<vci_param, proc_iss>(
+                    sp.str().c_str(),
+                    p+nprocs*cluster(x,y), 
+                    maptabd, maptabc,
+                    IntTab(cluster(x,y),PROC_SRCID+p),	// SRCID_D
+                    IntTab(cluster(x,y),PROC_SRCID+p),	// SRCID_C
+                    IntTab(cluster(x,y),PROC_SRCID+p),	// TGTID_C
+                    1,1,
+                    4,64,16,4,64,16, 			// Icache and Dcache sizes
+                    4,8);
+            }
+        }
+    }
+
+    //  memory caches (one per cluster)
+    VciMemCacheV4<vci_param>* memc[xmax][ymax];
+
+    for( size_t x = 0 ; x < xmax ; x++ )
+    {
+        for( size_t y = 0 ; y < ymax ; y++ )
+        {
+            std::ostringstream sm;
+            sm << "memc_" << x << "_" << y;
+	    memc[x][y] = new VciMemCacheV4<vci_param>(
+                sm.str().c_str(),
+                maptabd, maptabc, maptabx,
+                IntTab(cluster(x,y)),			// SRCID_X
+                IntTab(cluster(x,y), nprocs),		// SRCID_C
+                IntTab(cluster(x,y),MEMC_TGTID),	// TGTID_D
+                IntTab(cluster(x,y), nprocs), 	        // TGTID_C
+                16,256,16,				// CACHE SIZE
+                4096);					// HEAP SIZE
+        }
+    }
+
+    // XICU (one per cluster)
+    VciXicu<vci_param>* xicu[xmax][ymax];
+
+    for( size_t x = 0 ; x < xmax ; x++ )
+    {
+        for( size_t y = 0 ; y < ymax ; y++ )
+        {
+            std::ostringstream si;
+            si << "xicu_" << x << "_" << y;
+            size_t	nhwi;
+            if ( cluster(x,y) == cluster_io_index )	nhwi = 2 + N_TTYS;
+            else					nhwi = 0;
+	    xicu[x][y] = new VciXicu<vci_param>(
+                si.str().c_str(),
+                maptabd,
+                IntTab(cluster(x,y), XICU_TGTID),	// TGTID_D
+               	nprocs,					// number of TIMERS
+		nhwi,					// number of hard IRQs
+		nprocs,					// number of soft IRQs
+		nprocs);				// number of output IRQ lines
+        }
+    }
+                                                
+    // Local interconnects : one direct ring & one coherence ring per cluster
+    VciLocalRingFast<vci_param,cmd_width,rsp_width>* ringd[xmax][ymax];
+    VciLocalRingFast<vci_param,cmd_width,rsp_width>* ringc[xmax][ymax];
+
+    for( size_t x = 0 ; x < xmax ; x++ )
+    {
+        for( size_t y = 0 ; y < ymax ; y++ )
+        {
+            std::ostringstream sd;
+            sd << "ringd_" << x << "_" << y;
+            size_t nb_direct_initiators 	= nprocs;
+            size_t nb_direct_targets	        = 2;
+            if ( cluster(x,y) == cluster_io_index ) 
+            {
+                nb_direct_initiators		= nprocs + 2;
+                nb_direct_targets		= 7;
+            }
+	    ringd[x][y] = new VciLocalRingFast<vci_param,cmd_width,rsp_width>(
+                sd.str().c_str(),
+                maptabd,
+                IntTab(cluster(x,y)),			// cluster index
+                4,					// wrapper fifo depth
+                18,					// gateway fifo depth
+                nb_direct_initiators,			// number of initiators
+                nb_direct_targets);			// number of targets
+
+            std::ostringstream sc;
+            sc << "ringc_" << x << "_" << y;
+	    ringc[x][y] = new VciLocalRingFast<vci_param,cmd_width,rsp_width>(
+                sc.str().c_str(),
+                maptabc,
+                IntTab(cluster(x,y)),			// cluster index
+                4,					// wrapper fifo depth
+                18,					// gateway fifo depth
+                nprocs+1,				// number of initiators
+		nprocs+1);				// number of targets
+        }
+    }
+
+    // Distributed Global Interconnect : one cmd router & one rsp router per cluster
+    VirtualDspinRouter<cmd_width>* cmdrouter[xmax][ymax];
+    VirtualDspinRouter<rsp_width>* rsprouter[xmax][ymax];
+
+    for ( size_t x = 0 ; x < xmax ; x++ )
+    {
+        for ( size_t y = 0 ; y < ymax ; y++ )
+        {
+            std::ostringstream scmd;
+            scmd << "cmdrouter_" << x << "_" << y;
+            cmdrouter[x][y] = new VirtualDspinRouter<cmd_width>(
+                scmd.str().c_str(),
+                x,y,					// coordinate in the mesh
+                x_width, y_width,			// x & y fields width
+                4,4);					// input & output fifo depths
+
+            std::ostringstream srsp;
+            srsp << "rsprouter_" << x << "_" << y;
+            rsprouter[x][y] = new VirtualDspinRouter<rsp_width>(
+                srsp.str().c_str(),
+                x,y,					// coordinates in mesh
+                x_width, y_width,			// x & y fields width
+                4,4);					// input & output fifo depths
+        }
+    }
+
+    ///////////////////////////////////////////////////////////////
+    //     Net-list 
+    ///////////////////////////////////////////////////////////////
+
+    // External Ram (one instance)
+    xram.p_clk						(signal_clk);
+    xram.p_resetn					(signal_resetn);
+    xram.p_vci						(signal_vci_tgt_x_xram);	
+
+    // External Network (one instance)
+    xnoc.p_clk						(signal_clk);
+    xnoc.p_resetn					(signal_resetn);
+    xnoc.p_to_target[0]					(signal_vci_tgt_x_xram);
+    for ( size_t x = 0 ; x < xmax ; x++ )
+    {
+        for ( size_t y = 0 ; y < ymax ; y++ )
+        {
+            xnoc.p_to_initiator[cluster(x,y)]           (signal_vci_ini_x_memc[x][y]);
+        }
+    }
+
+    // Distributed components (in clusters)
+
+    for ( size_t x = 0 ; x < xmax ; x++ )
+    {
+        for ( size_t y = 0 ; y < ymax ; y++ )
+        {
+            // cmd DSPIN router
+            cmdrouter[x][y]->p_clk			(signal_clk);
+            cmdrouter[x][y]->p_resetn			(signal_resetn);
+            cmdrouter[x][y]->p_out[0][LOCAL]		(signal_dspin_cmd_g2l_d[x][y]);
+            cmdrouter[x][y]->p_out[1][LOCAL]		(signal_dspin_cmd_g2l_c[x][y]);
+            cmdrouter[x][y]->p_in[0][LOCAL]		(signal_dspin_cmd_l2g_d[x][y]);
+            cmdrouter[x][y]->p_in[1][LOCAL]		(signal_dspin_cmd_l2g_c[x][y]);
+
+            // rsp DSPIN router
+            rsprouter[x][y]->p_clk			(signal_clk);
+            rsprouter[x][y]->p_resetn			(signal_resetn);
+            rsprouter[x][y]->p_out[0][LOCAL]		(signal_dspin_rsp_g2l_d[x][y]);
+            rsprouter[x][y]->p_out[1][LOCAL]		(signal_dspin_rsp_g2l_c[x][y]);
+            rsprouter[x][y]->p_in[0][LOCAL]		(signal_dspin_rsp_l2g_d[x][y]);
+            rsprouter[x][y]->p_in[1][LOCAL]		(signal_dspin_rsp_l2g_c[x][y]);
+
+            // direct ring
+            ringd[x][y]->p_clk				(signal_clk);
+            ringd[x][y]->p_resetn			(signal_resetn);
+            ringd[x][y]->p_gate_cmd_out			(signal_dspin_cmd_l2g_d[x][y]);
+	    ringd[x][y]->p_gate_cmd_in 			(signal_dspin_cmd_g2l_d[x][y]);
+            ringd[x][y]->p_gate_rsp_out   		(signal_dspin_rsp_l2g_d[x][y]);
+	    ringd[x][y]->p_gate_rsp_in 			(signal_dspin_rsp_g2l_d[x][y]);
+            ringd[x][y]->p_to_target[MEMC_TGTID]	(signal_vci_tgt_d_memc[x][y]);
+            ringd[x][y]->p_to_target[XICU_TGTID]	(signal_vci_tgt_d_xicu[x][y]);
+	    for ( size_t p = 0 ; p < nprocs ; p++ )
+            {
+	        ringd[x][y]->p_to_initiator[p]		(signal_vci_ini_d_proc[x][y][p]);
+	    }
+
+            // coherence ring
+            ringc[x][y]->p_clk				(signal_clk);
+            ringc[x][y]->p_resetn			(signal_resetn);
+            ringc[x][y]->p_gate_cmd_out			(signal_dspin_cmd_l2g_c[x][y]);
+	    ringc[x][y]->p_gate_cmd_in 			(signal_dspin_cmd_g2l_c[x][y]);
+            ringc[x][y]->p_gate_rsp_out   		(signal_dspin_rsp_l2g_c[x][y]);
+	    ringc[x][y]->p_gate_rsp_in 			(signal_dspin_rsp_g2l_c[x][y]);
+            ringc[x][y]->p_to_initiator[nprocs]		(signal_vci_ini_c_memc[x][y]);
+            ringc[x][y]->p_to_target[nprocs]		(signal_vci_tgt_c_memc[x][y]);
+            for ( size_t p = 0 ; p < nprocs ; p++ )
+            {
+                ringc[x][y]->p_to_target[p]		(signal_vci_tgt_c_proc[x][y][p]);
+                ringc[x][y]->p_to_initiator[p]		(signal_vci_ini_c_proc[x][y][p]);
+            }
+
+	    // Processors
+	    for ( size_t p = 0 ; p < nprocs ; p++ )
+            {
+                proc[x][y][p]->p_clk			(signal_clk);  
+                proc[x][y][p]->p_resetn			(signal_resetn);  
+                proc[x][y][p]->p_vci_ini_rw		(signal_vci_ini_d_proc[x][y][p]);
+                proc[x][y][p]->p_vci_ini_c		(signal_vci_ini_c_proc[x][y][p]);
+                proc[x][y][p]->p_vci_tgt		(signal_vci_tgt_c_proc[x][y][p]);
+                proc[x][y][p]->p_irq[0][0]		        (signal_proc_it[0][x][y][p]);
+                for ( size_t j = 1 ; j < 6 ; j++ )
+                {
+                    proc[x][y][p]->p_irq[0][j]		(signal_false); 
+                }
+	    }
+
+            // XICU
+	    xicu[x][y]->p_clk				(signal_clk);
+            xicu[x][y]->p_resetn			(signal_resetn);
+	    xicu[x][y]->p_vci				(signal_vci_tgt_d_xicu[x][y]);
+	    for ( size_t p = 0 ; p < nprocs ; p++ )
+            {
+                xicu[x][y]->p_irq[p]			(signal_proc_it[0][x][y][p]);
+            }
+
+            // MEMC
+            memc[x][y]->p_clk				(signal_clk);
+            memc[x][y]->p_resetn			(signal_resetn);
+            memc[x][y]->p_vci_tgt			(signal_vci_tgt_d_memc[x][y]);	
+            memc[x][y]->p_vci_ini			(signal_vci_ini_c_memc[x][y]);
+            memc[x][y]->p_vci_tgt_cleanup		(signal_vci_tgt_c_memc[x][y]);
+            memc[x][y]->p_vci_ixr			(signal_vci_ini_x_memc[x][y]);
+
+            // I/O peripherals
+            if ( cluster(x,y) == cluster_io_index )
+            {
+	        bdev.p_clk				(signal_clk);
+	        bdev.p_resetn				(signal_resetn);
+	        bdev.p_irq				(signal_irq_bdev); 
+	        bdev.p_vci_target			(signal_vci_tgt_d_bdev);
+	        bdev.p_vci_initiator			(signal_vci_ini_d_bdev);
+
+                cdma.p_clk                              (signal_clk);
+                cdma.p_resetn                           (signal_resetn);
+                cdma.p_irq                              (signal_irq_cdma);
+                cdma.p_vci_target                       (signal_vci_tgt_d_cdma);
+                cdma.p_vci_initiator                    (signal_vci_ini_d_cdma);
+
+	        fbuf.p_clk				(signal_clk); 
+	        fbuf.p_resetn				(signal_resetn); 
+	        fbuf.p_vci				(signal_vci_tgt_d_fbuf); 
+
+	        brom.p_clk				(signal_clk);
+	        brom.p_resetn				(signal_resetn);
+	        brom.p_vci				(signal_vci_tgt_d_brom);
+
+	        mtty.p_clk				(signal_clk);
+	        mtty.p_resetn				(signal_resetn);
+	        mtty.p_vci				(signal_vci_tgt_d_mtty);
+                for(size_t i=0 ; i<N_TTYS ; i++)
+                {
+                    mtty.p_irq[i]                       (signal_irq_mtty[i]);
+                }
+
+                ringd[x][y]->p_to_target[BROM_TGTID]	(signal_vci_tgt_d_brom);
+                ringd[x][y]->p_to_target[MTTY_TGTID]	(signal_vci_tgt_d_mtty);
+	        ringd[x][y]->p_to_target[BDEV_TGTID]	(signal_vci_tgt_d_bdev);
+	        ringd[x][y]->p_to_target[FBUF_TGTID]	(signal_vci_tgt_d_fbuf);
+	        ringd[x][y]->p_to_target[CDMA_TGTID]	(signal_vci_tgt_d_cdma);
+
+	        ringd[x][y]->p_to_initiator[BDEV_SRCID]	(signal_vci_ini_d_bdev);
+	        ringd[x][y]->p_to_initiator[CDMA_SRCID]	(signal_vci_ini_d_cdma);
+
+                xicu[x][y]->p_hwi[0]			(signal_irq_bdev);
+                xicu[x][y]->p_hwi[1]			(signal_irq_cdma);
+                for(size_t i=0 ; i<N_TTYS ; i++)
+                {
+                    xicu[x][y]->p_hwi[2+i]              (signal_irq_mtty[i]);
+                }
+            }
+        } // end for y
+    } // end for x
+
+    // Inter Clusters horizontal connections
+    for ( size_t x = 0 ; x < (xmax-1) ; x++ )
+    {
+        for ( size_t y = 0 ; y < ymax ; y++ )
+        {
+            for ( size_t k = 0 ; k < 2 ; k++ )
+            {
+                cmdrouter[x][y]->p_out[k][EAST]		(signal_dspin_h_cmd_inc[x][y][k]);		
+                cmdrouter[x+1][y]->p_in[k][WEST]		(signal_dspin_h_cmd_inc[x][y][k]);
+
+                cmdrouter[x][y]->p_in[k][EAST]		(signal_dspin_h_cmd_dec[x][y][k]);		
+                cmdrouter[x+1][y]->p_out[k][WEST]	(signal_dspin_h_cmd_dec[x][y][k]);
+
+                rsprouter[x][y]->p_out[k][EAST]		(signal_dspin_h_rsp_inc[x][y][k]);		
+                rsprouter[x+1][y]->p_in[k][WEST]		(signal_dspin_h_rsp_inc[x][y][k]);
+
+                rsprouter[x][y]->p_in[k][EAST]		(signal_dspin_h_rsp_dec[x][y][k]);		
+                rsprouter[x+1][y]->p_out[k][WEST]	(signal_dspin_h_rsp_dec[x][y][k]);
+            }
+        }
+    }
+
+    // Inter Clusters vertical connections
+    for ( size_t y = 0 ; y < (ymax-1) ; y++ )
+    {
+        for ( size_t x = 0 ; x < xmax ; x++ )
+        {
+            for ( size_t k = 0 ; k < 2 ; k++ )
+            {
+                cmdrouter[x][y]->p_out[k][NORTH]		(signal_dspin_v_cmd_inc[x][y][k]);		
+                cmdrouter[x][y+1]->p_in[k][SOUTH]	(signal_dspin_v_cmd_inc[x][y][k]);
+
+                cmdrouter[x][y]->p_in[k][NORTH]		(signal_dspin_v_cmd_dec[x][y][k]);		
+                cmdrouter[x][y+1]->p_out[k][SOUTH]	(signal_dspin_v_cmd_dec[x][y][k]);
+
+                rsprouter[x][y]->p_out[k][NORTH]		(signal_dspin_v_rsp_inc[x][y][k]);		
+                rsprouter[x][y+1]->p_in[k][SOUTH]	(signal_dspin_v_rsp_inc[x][y][k]);
+
+                rsprouter[x][y]->p_in[k][NORTH]		(signal_dspin_v_rsp_dec[x][y][k]);		
+                rsprouter[x][y+1]->p_out[k][SOUTH]	(signal_dspin_v_rsp_dec[x][y][k]);
+            }
+        }
+    }
+
+    // East & West boundary cluster connections
+    for ( size_t y = 0 ; y < ymax ; y++ )
+    {
+        for ( size_t k = 0 ; k < 2 ; k++ )
+        {
+            cmdrouter[0][y]->p_in[k][WEST]          	(signal_dspin_false_cmd_in[0][y][k][0]);
+            cmdrouter[0][y]->p_out[k][WEST]         	(signal_dspin_false_cmd_out[0][y][k][0]);
+            rsprouter[0][y]->p_in[k][WEST]          	(signal_dspin_false_rsp_in[0][y][k][0]);
+            rsprouter[0][y]->p_out[k][WEST]         	(signal_dspin_false_rsp_out[0][y][k][0]);
+
+            cmdrouter[xmax-1][y]->p_in[k][EAST]  	(signal_dspin_false_cmd_in[xmax-1][y][k][0]);
+            cmdrouter[xmax-1][y]->p_out[k][EAST] 	(signal_dspin_false_cmd_out[xmax-1][y][k][0]);
+            rsprouter[xmax-1][y]->p_in[k][EAST]  	(signal_dspin_false_rsp_in[xmax-1][y][k][0]);
+            rsprouter[xmax-1][y]->p_out[k][EAST] 	(signal_dspin_false_rsp_out[xmax-1][y][k][0]);
+        }
+    }
+
+    // North & South boundary clusters connections
+    for ( size_t x = 0 ; x < xmax ; x++ )
+    {
+        for ( size_t k = 0 ; k < 2 ; k++ )
+        {
+            cmdrouter[x][0]->p_in[k][SOUTH]          	(signal_dspin_false_cmd_in[x][0][k][1]);
+            cmdrouter[x][0]->p_out[k][SOUTH]         	(signal_dspin_false_cmd_out[x][0][k][1]);
+            rsprouter[x][0]->p_in[k][SOUTH]          	(signal_dspin_false_rsp_in[x][0][k][1]);
+            rsprouter[x][0]->p_out[k][SOUTH]         	(signal_dspin_false_rsp_out[x][0][k][1]);
+
+            cmdrouter[x][ymax-1]->p_in[k][NORTH]  	(signal_dspin_false_cmd_in[x][ymax-1][k][1]);
+            cmdrouter[x][ymax-1]->p_out[k][NORTH] 	(signal_dspin_false_cmd_out[x][xmax-1][k][1]);
+            rsprouter[x][ymax-1]->p_in[k][NORTH]  	(signal_dspin_false_rsp_in[x][ymax-1][k][1]);
+            rsprouter[x][ymax-1]->p_out[k][NORTH] 	(signal_dspin_false_rsp_out[x][ymax-1][k][1]);
+        }
+    }
+
+    ////////////////////////////////////////////////////////
+    //   Simulation
+    ///////////////////////////////////////////////////////
+
+    sc_start(sc_core::sc_time(0, SC_NS));
+    signal_resetn = false;
+
+    // network boundaries signals
+    for(size_t x=0; x<xmax ; x++)
+    {
+        for(size_t y=0 ; y<ymax ; y++)
+        {
+            for (size_t k=0; k<2; k++)
+            {
+                for(size_t a=0; a<2; a++)
+                {
+                        signal_dspin_false_cmd_in[x][y][k][a].write = false;
+                        signal_dspin_false_cmd_in[x][y][k][a].read = true;
+                        signal_dspin_false_cmd_out[x][y][k][a].write = false;
+                        signal_dspin_false_cmd_out[x][y][k][a].read = true;
+
+                        signal_dspin_false_rsp_in[x][y][k][a].write = false;
+                        signal_dspin_false_rsp_in[x][y][k][a].read = true;
+                        signal_dspin_false_rsp_out[x][y][k][a].write = false;
+                        signal_dspin_false_rsp_out[x][y][k][a].read = true;
+               }
+            }
+        }
+    }
+
+
+    sc_start(sc_core::sc_time(1, SC_NS));
+    signal_resetn = true;
+
+    for(size_t i=1 ; i<ncycles ; i++)
+    {
+        sc_start(sc_core::sc_time(1, SC_NS));
+
+        if( debug_ok && (i > from_cycle) && (i < to_cycle) )
+        {
+        std::cout << std::dec << "*************** cycle " << i 
+                  << "    *******************************************************" << std::endl;
+        proc[0][0][0]->print_trace();
+        proc[0][1][0]->print_trace();
+        proc[1][0][0]->print_trace();
+        proc[1][1][0]->print_trace();
+        std::cout << std::endl;
+        ringd[0][0]->print_trace();
+        ringd[0][1]->print_trace();
+        ringd[1][0]->print_trace();
+        ringd[1][1]->print_trace();
+        ringc[0][0]->print_trace();
+        ringc[0][1]->print_trace();
+        ringc[1][0]->print_trace();
+        ringc[1][1]->print_trace();
+        std::cout << std::endl;
+        cmdrouter[0][0]->print_trace(0);
+        cmdrouter[0][1]->print_trace(0);
+        cmdrouter[1][0]->print_trace(0);
+        cmdrouter[1][1]->print_trace(0);
+        std::cout << std::endl;
+        cmdrouter[0][0]->print_trace(1);
+        cmdrouter[0][1]->print_trace(1);
+        cmdrouter[1][0]->print_trace(1);
+        cmdrouter[1][1]->print_trace(1);
+        std::cout << std::endl;
+        memc[0][0]->print_trace();
+        memc[0][1]->print_trace();
+        memc[1][0]->print_trace();
+        memc[1][1]->print_trace();
+//        if ( i%5 == 0) getchar();
+        }
+    }
+
+    std::cout << "Hit ENTER to end simulation" << std::endl;
+    char buf[1];
+    std::cin.getline(buf,1);
+
+    return EXIT_SUCCESS;
+}
+
+int sc_main (int argc, char *argv[])
+{
+	try {
+		return _main(argc, argv);
+	} catch (std::exception &e) {
+		std::cout << e.what() << std::endl;
+	} catch (...) {
+		std::cout << "Unknown exception occured" << std::endl;
+		throw;
+	}
+	return 1;
+}
Index: branches/v4/platforms/tsarv4_generic_mmu/Makefile
===================================================================
--- branches/v4/platforms/tsarv4_generic_mmu/Makefile	(revision 371)
+++ branches/v4/platforms/tsarv4_generic_mmu/Makefile	(revision 371)
@@ -0,0 +1,8 @@
+
+simulator.x: top.cpp top.desc
+	soclib-cc -P -p top.desc -I. -o simul.x
+
+clean:
+	soclib-cc -x -p top.desc -I.
+	rm -rf *.o *.x tty*
+
Index: branches/v4/platforms/tsarv4_generic_mmu/soclib.conf
===================================================================
--- branches/v4/platforms/tsarv4_generic_mmu/soclib.conf	(revision 371)
+++ branches/v4/platforms/tsarv4_generic_mmu/soclib.conf	(revision 371)
@@ -0,0 +1,2 @@
+config.default.toolchain.set("cflags", config.default.toolchain.cflags + ['-DI_WANT_ILLEGAL_VCI'])
+
Index: branches/v4/platforms/tsarv4_generic_mmu/top.cpp
===================================================================
--- branches/v4/platforms/tsarv4_generic_mmu/top.cpp	(revision 371)
+++ branches/v4/platforms/tsarv4_generic_mmu/top.cpp	(revision 371)
@@ -0,0 +1,796 @@
+/////////////////////////////////////////////////////////////////////////
+// File: top.cpp 
+// Author: Alain Greiner 
+// Copyright: UPMC/LIP6
+// Date : august 2012
+// This program is released under the GNU public license
+/////////////////////////////////////////////////////////////////////////
+// This file define a generic TSAR architecture with virtual memory.
+// The physical address space is 32 bits.
+// The number of clusters cannot be larger than 256.
+// The number of processors per cluster cannot be larger than 8.
+// 
+// - It uses vci_local_crossbar as local interconnect 
+// - It uses virtual_dspin as global interconnect
+// - It uses the vci_cc_vcache_wrapper_v4 
+// - It uses the vci_mem_cache_v4
+// - It contains one vci_xicu and one vci_multi_dma per cluster.
+//
+// All clusters are identical, but the cluster containing address
+// 0xBFC00000 (called io_cluster), that contains 5 extra components:
+// - the boot rom (BROM)
+// - the disk controller (BDEV)
+// - the multi-channel network controller (MNIC)
+// - the multi-channel tty controller (MTTY)
+// - the frame buffer controller (FBUF)
+//
+// It is build with one single component implementing a cluster:
+// The Tsarv4ClusterMmu component is defined in files
+// tsarv4_cluster_mmu.* (with * = cpp, h, sd)
+//
+// The IRQs are connected to XICUs as follow:
+// - The IRQ_IN[0] to IRQ_IN[7] ports are not used in all clusters.
+// - The DMA IRQs are connected to IRQ_IN[8] to IRQ_IN[15] in all clusters.
+// - The TTY IRQs are connected to IRQ_IN[16] to IRQ_IN[30] in I/O cluster.
+// - The BDEV IRQ is connected to IRQ_IN[31] in I/O cluster.
+// 
+// The main hardware parameters must be defined in the hard_config.h file :
+// - CLUSTER_X     : number of clusters in a row (power of 2)
+// - CLUSTER_Y     : number of clusters in a column (power of 2)
+// - CLUSTER_SIZE     : size of the segment allocated to a cluster
+// - NB_PROCS_MAX     : number of processors per cluster (power of 2)
+// - NB_DMAS_MAX      : number of DMA channels per cluster (< 9)
+// - NB_TTYS          : number of TTY channels in I/O cluster (< 16)
+// - NB_NICS          : number of NIC channels in I/O cluster (< 9)
+// 
+// Some secondary hardware parameters must be defined in this top.cpp file:
+// - XRAM_LATENCY     : external ram latency 
+// - MEMC_WAYS        : L2 cache number of ways
+// - MEMC_SETS        : L2 cache number of sets
+// - L1_IWAYS     
+// - L1_ISETS    
+// - L1_DWAYS   
+// - L1_DSETS  
+// - FBUF_X_SIZE      : width of frame buffer (pixels)
+// - FBUF_Y_SIZE      : heigth of frame buffer (lines)
+// - BDEV_SECTOR_SIZE : block size for block drvice
+// - BDEV_IMAGE_NAME  : file pathname for block device 
+// - NIC_RX_NAME      : file pathname for NIC received packets
+// - NIC_TX_NAME      : file pathname for NIC transmited packets
+// - NIC_TIMEOUT      : max number of cycles before closing a container
+//
+// General policy for 32 bits physical address decoding:
+// All segments base addresses are multiple of 64 Kbytes
+// Therefore the 16 address MSB bits completely define the target: 
+// The (x_width + y_width) MSB bits (left aligned) define
+// the cluster index, and the 8 LSB bits define the local index:
+//      | X_ID  | Y_ID  |---| LADR |     OFFSET          |
+//      |x_width|y_width|---|  8   |       16            |
+/////////////////////////////////////////////////////////////////////////
+
+#include <systemc>
+#include <sys/time.h>
+#include <iostream>
+#include <sstream>
+#include <cstdlib>
+#include <cstdarg>
+#include <stdint.h>
+
+#include "gdbserver.h"
+#include "mapping_table.h"
+#include "tsarv4_cluster_mmu.h"
+#include "alloc_elems.h"
+
+///////////////////////////////////////////////////
+//      OS
+///////////////////////////////////////////////////
+#define USE_ALMOS 0
+
+#define almos_bootloader_pathname "bootloader.bin"
+#define almos_kernel_pathname     "kernel-soclib.bin@0xbfc10000:D"
+#define almos_archinfo_pathname   "arch-info.bin@0xBFC08000:D"
+
+///////////////////////////////////////////////////
+//               Parallelisation
+///////////////////////////////////////////////////
+#define USE_OPENMP               0
+
+#if USE_OPENMP
+#include <omp.h>
+#endif
+
+//  cluster index (computed from x,y coordinates)
+#define cluster(x,y)   (y + CLUSTER_Y*x)
+
+// flit widths for the DSPIN network
+#define cmd_width            40
+#define rsp_width            33
+
+// VCI format
+#define cell_width            4
+#define address_width         32
+#define plen_width            8
+#define error_width           2
+#define clen_width            1
+#define rflag_width           1
+#define srcid_width           14
+#define pktid_width           4
+#define trdid_width           4
+#define wrplen_width          1
+
+////////////////////////////////////////////////////////////
+//    Main Hardware Parameters values         
+//////////////////////i/////////////////////////////////////
+
+#include "/Users/alain/Documents/licence/almo_svn_2011/soft/giet_vm/hard_config.h"
+
+////////////////////////////////////////////////////////////
+//    Secondary Hardware Parameters values         
+//////////////////////i/////////////////////////////////////
+
+#define XRAM_LATENCY          0
+
+#define MEMC_WAYS             16
+#define MEMC_SETS             256
+
+#define L1_IWAYS              4
+#define L1_ISETS              64
+
+#define L1_DWAYS              4
+#define L1_DSETS              64
+
+#define FBUF_X_SIZE           128
+#define FBUF_Y_SIZE           128
+
+#define BDEV_SECTOR_SIZE      512
+#define BDEV_IMAGE_NAME       "/Users/alain/Documents/licence/almo_svn_2011/soft/giet_vm/display/images.raw"
+
+#define NIC_RX_NAME           "/Users/alain/Documents/licence/almo_svn_2011/soft/giet_vm/nic/rx_data.txt"
+#define NIC_TX_NAME           "/Users/alain/Documents/licence/almo_svn_2011/soft/giet_vm/nic/tx_data.txt"
+#define NIC_TIMEOUT           10000
+
+////////////////////////////////////////////////////////////
+//    Software to be loaded in ROM & RAM         
+//////////////////////i/////////////////////////////////////
+
+#define BOOT_SOFT_NAME        "/Users/alain/Documents/licence/almo_svn_2011/soft/giet_vm/soft.elf"
+
+////////////////////////////////////////////////////////////
+//     DEBUG Parameters default values         
+//////////////////////i/////////////////////////////////////
+
+#define MAX_FROZEN_CYCLES     10000
+
+#define TRACE_MEMC_ID         1000000
+#define TRACE_PROC_ID         1000000
+
+/////////////////////////////////////////////////////////
+//    Physical segments definition
+/////////////////////////////////////////////////////////
+// There is 3 segments replicated in all clusters
+// and 5 specific segments in the "IO" cluster 
+// (containing address 0xBF000000)
+/////////////////////////////////////////////////////////
+
+// specific segments in "IO" cluster : absolute physical address
+
+#define BROM_BASE               0xBFC00000      
+#define BROM_SIZE               0x00100000   // 1 Mbytes
+
+#define FBUF_BASE               0xBFD00000      
+#define FBUF_SIZE               0x00200000   // 2 Mbytes
+
+#define BDEV_BASE               0xBFF10000      
+#define BDEV_SIZE               0x00001000   // 4 Kbytes
+
+#define MTTY_BASE               0xBFF20000      
+#define MTTY_SIZE               0x00001000   // 4 Kbytes
+
+#define MNIC_BASE               0xBFF80000      
+#define MNIC_SIZE               0x00002000 * (NB_NICS + 1)  // 8 Kbytes per channel + 8 Kbytes
+
+// replicated segments : address is incremented by a cluster offset 
+//     offset  = cluster(x,y) << (address_width-x_width-y_width);
+
+#define MEMC_BASE               0x00000000      
+#define MEMC_SIZE               0x00C00000   // 12 Mbytes
+
+#define XICU_BASE               0x00F00000      
+#define XICU_SIZE               0x00001000   // 4 Kbytes
+
+#define CDMA_BASE               0x00F30000      
+#define CDMA_SIZE               0x00001000 * NB_DMAS_MAX  // 4 Kbytes per channel  
+
+////////////////////////////////////////////////////////////////////
+//     TGTID definition in direct space
+// For all components:  global TGTID = global SRCID = cluster_index
+////////////////////////////////////////////////////////////////////
+
+#define MEMC_TGTID               0
+#define XICU_TGTID               1
+#define CDMA_TGTID               2
+#define MTTY_TGTID               3
+#define FBUF_TGTID               4
+#define BROM_TGTID               5
+#define BDEV_TGTID               6
+#define MNIC_TGTID               7
+
+/////////////////////////////////
+int _main(int argc, char *argv[])
+{
+   using namespace sc_core;
+   using namespace soclib::caba;
+   using namespace soclib::common;
+
+
+   char     soft_name[256]   = BOOT_SOFT_NAME;     // pathname to binary code
+   size_t   ncycles          = 1000000000;         // simulated cycles
+   char     disk_name[256]   = BDEV_IMAGE_NAME;    // pathname to the disk image
+   char     nic_rx_name[256] = NIC_RX_NAME;        // pathname to the rx packets file
+   char     nic_tx_name[256] = NIC_TX_NAME;        // pathname to the tx packets file
+   ssize_t  threads_nr       = 1;                  // simulator's threads number
+   bool     debug_ok         = false;              // trace activated
+   size_t   debug_period     = 1;                  // trace period
+   size_t   debug_memc_id    = TRACE_MEMC_ID;      // index of memc to be traced (cluster_id)  
+   size_t   debug_proc_id    = TRACE_PROC_ID;      // index of proc to be traced
+   uint32_t debug_from       = 0;                  // trace start cycle
+   uint32_t frozen_cycles    = MAX_FROZEN_CYCLES;  // monitoring frozen processor
+
+   ////////////// command line arguments //////////////////////
+   if (argc > 1)
+   {
+      for (int n = 1; n < argc; n = n + 2)
+      {
+         if ((strcmp(argv[n],"-NCYCLES") == 0) && (n+1<argc))
+         {
+            ncycles = atoi(argv[n+1]);
+         }
+         else if ((strcmp(argv[n],"-SOFT") == 0) && (n+1<argc) )
+         {
+            strcpy(soft_name, argv[n+1]);
+         }
+         else if ((strcmp(argv[n],"-DISK") == 0) && (n+1<argc) )
+         {
+            strcpy(disk_name, argv[n+1]);
+         }
+         else if ((strcmp(argv[n],"-DEBUG") == 0) && (n+1<argc) )
+         {
+            debug_ok = true;
+            debug_from = atoi(argv[n+1]);
+         }
+         else if ((strcmp(argv[n],"-MEMCID") == 0) && (n+1<argc) )
+         {
+            debug_memc_id = atoi(argv[n+1]);
+            assert( (debug_memc_id < (CLUSTER_X*CLUSTER_Y) ) && 
+                   "debug_memc_id larger than XMAX * YMAX" );
+         }
+         else if ((strcmp(argv[n],"-PROCID") == 0) && (n+1<argc) )
+         {
+            debug_proc_id = atoi(argv[n+1]);
+            assert( (debug_proc_id < (CLUSTER_X * CLUSTER_Y * NB_PROCS_MAX) ) && 
+                   "debug_proc_id larger than XMAX * YMAX * NB_PROCS" );
+         }
+         else if ((strcmp(argv[n], "-THREADS") == 0) && ((n+1) < argc))
+         {
+            threads_nr = atoi(argv[n+1]);
+            threads_nr = (threads_nr < 1) ? 1 : threads_nr;
+         }
+         else if ((strcmp(argv[n], "-FROZEN") == 0) && (n+1 < argc))
+         {
+            frozen_cycles = atoi(argv[n+1]);
+         }
+         else if ((strcmp(argv[n], "-PERIOD") == 0) && (n+1 < argc))
+         {
+            debug_period = atoi(argv[n+1]);
+         }
+         else
+         {
+            std::cout << "   Arguments on the command line are (key,value) couples." << std::endl;
+            std::cout << "   The order is not important." << std::endl;
+            std::cout << "   Accepted arguments are :" << std::endl << std::endl;
+            std::cout << "     -SOFT pathname_for_embedded_soft" << std::endl;
+            std::cout << "     -DISK pathname_for_disk_image" << std::endl;
+            std::cout << "     -NCYCLES number_of_simulated_cycles" << std::endl;
+            std::cout << "     -DEBUG debug_start_cycle" << std::endl;
+            std::cout << "     -THREADS simulator's threads number" << std::endl;
+            std::cout << "     -FROZEN max_number_of_lines" << std::endl;
+            std::cout << "     -PERIOD number_of_cycles between trace" << std::endl;
+            std::cout << "     -MEMCID index_memc_to_be_traced" << std::endl;
+            std::cout << "     -PROCID index_proc_to_be_traced" << std::endl;
+            exit(0);
+         }
+      }
+   }
+
+   // checking hardware parameters
+   assert( ( (CLUSTER_X == 1) or (CLUSTER_X == 2) or (CLUSTER_X == 4) or
+             (CLUSTER_X == 8) or (CLUSTER_X == 16) ) and
+           "The CLUSTER_X parameter must be 1, 2, 4, 8 or 16" );
+
+   assert( ( (CLUSTER_Y == 1) or (CLUSTER_Y == 2) or (CLUSTER_Y == 4) or
+             (CLUSTER_Y == 8) or (CLUSTER_Y == 16) ) and
+           "The CLUSTER_Y parameter must be 1, 2, 4, 8 or 16" );
+
+   assert( ( (NB_PROCS_MAX == 1) or (NB_PROCS_MAX == 2) or
+             (NB_PROCS_MAX == 4) or (NB_PROCS_MAX == 8) ) and
+           "The NB_PROCS_MAX parameter must be 1, 2, 4 or 8" );
+
+   assert( (NB_DMAS_MAX < 9) and
+           "The NB_DMAS_MAX parameter must be smaller than 9" );
+
+   assert( (NB_TTYS < 15) and
+           "The NB_TTYS parameter must be smaller than 15" );
+
+   assert( (NB_NICS < 9) and
+           "The NB_NICS parameter must be smaller than 9" );
+
+   std::cout << std::endl;
+   std::cout << " - CLUSTER_X    = " << CLUSTER_X << std::endl;
+   std::cout << " - CLUSTER_Y    = " << CLUSTER_Y << std::endl;
+   std::cout << " - NB_PROCS_MAX = " << NB_PROCS_MAX <<  std::endl;
+   std::cout << " - NB_DMAS_MAX  = " << NB_DMAS_MAX <<  std::endl;
+   std::cout << " - NB_TTYS      = " << NB_TTYS <<  std::endl;
+   std::cout << " - NB_NICS      = " << NB_NICS <<  std::endl;
+   std::cout << " - MEMC_WAYS    = " << MEMC_WAYS << std::endl;
+   std::cout << " - MEMC_SETS    = " << MEMC_SETS << std::endl;
+   std::cout << " - RAM_LATENCY  = " << XRAM_LATENCY << std::endl;
+   std::cout << " - MAX_FROZEN   = " << frozen_cycles << std::endl;
+
+   std::cout << std::endl;
+
+#if USE_OPENMP
+   omp_set_dynamic(false);
+   omp_set_num_threads(threads_nr);
+   std::cerr << "Built with openmp version " << _OPENMP << std::endl;
+#endif
+
+   // Define VCI parameters
+   typedef soclib::caba::VciParams<cell_width,
+           plen_width,
+           address_width,
+           error_width,                                   
+           clen_width,
+           rflag_width,
+           srcid_width,
+           pktid_width,
+           trdid_width,
+           wrplen_width> vci_param;
+
+   // Define parameters depending on mesh size
+   size_t   cluster_io_id;
+   size_t   x_width;
+   size_t   y_width;
+
+   if      (CLUSTER_X == 1) x_width = 0;
+   else if (CLUSTER_X == 2) x_width = 1;
+   else if (CLUSTER_X <= 4) x_width = 2;
+   else if (CLUSTER_X <= 8) x_width = 3;
+   else                        x_width = 4;
+
+   if      (CLUSTER_Y == 1) y_width = 0;
+   else if (CLUSTER_Y == 2) y_width = 1;
+   else if (CLUSTER_Y <= 4) y_width = 2;
+   else if (CLUSTER_Y <= 8) y_width = 3;
+   else                        y_width = 4;
+
+   cluster_io_id = 0xBF >> (8 - x_width - y_width);
+
+   /////////////////////
+   //  Mapping Tables
+   /////////////////////
+
+   // direct network
+   MappingTable maptabd(address_width, 
+         IntTab(x_width + y_width, 16 - x_width - y_width), 
+         IntTab(x_width + y_width, srcid_width - x_width - y_width), 
+         0x00FF0000);
+
+   for (size_t x = 0; x < CLUSTER_X; x++)
+   {
+      for (size_t y = 0; y < CLUSTER_Y; y++)
+      {
+         sc_uint<address_width> offset  = cluster(x,y) << (address_width-x_width-y_width);
+
+         std::ostringstream    sh;
+         sh << "d_seg_memc_" << x << "_" << y;
+         maptabd.add(Segment(sh.str(), MEMC_BASE+offset, MEMC_SIZE, IntTab(cluster(x,y),MEMC_TGTID), true));
+
+         std::ostringstream    si;
+         si << "d_seg_xicu_" << x << "_" << y;
+         maptabd.add(Segment(si.str(), XICU_BASE+offset, XICU_SIZE, IntTab(cluster(x,y),XICU_TGTID), false));
+
+         std::ostringstream    sd;
+         sd << "d_seg_mdma_" << x << "_" << y;
+         maptabd.add(Segment(sd.str(), CDMA_BASE+offset, CDMA_SIZE, IntTab(cluster(x,y),CDMA_TGTID), false));
+
+         if ( cluster(x,y) == cluster_io_id )
+         {
+            maptabd.add(Segment("d_seg_mtty", MTTY_BASE, MTTY_SIZE, IntTab(cluster(x,y),MTTY_TGTID), false));
+            maptabd.add(Segment("d_seg_fbuf", FBUF_BASE, FBUF_SIZE, IntTab(cluster(x,y),FBUF_TGTID), false));
+            maptabd.add(Segment("d_seg_bdev", BDEV_BASE, BDEV_SIZE, IntTab(cluster(x,y),BDEV_TGTID), false));
+            maptabd.add(Segment("d_seg_mnic", MNIC_BASE, MNIC_SIZE, IntTab(cluster(x,y),MNIC_TGTID), false));
+            maptabd.add(Segment("d_seg_brom", BROM_BASE, BROM_SIZE, IntTab(cluster(x,y),BROM_TGTID), true));
+         }
+      }
+   }
+   std::cout << maptabd << std::endl;
+
+   // coherence network
+   // - tgtid_c_proc = srcid_c_proc = local procid
+   // - tgtid_c_memc = srcid_c_memc = NB_PROCS_MAX
+   MappingTable maptabc(address_width, 
+         IntTab(x_width + y_width, srcid_width - x_width - y_width), 
+         IntTab(x_width + y_width, srcid_width - x_width - y_width), 
+         0x00FF0000);
+
+   for (size_t x = 0; x < CLUSTER_X; x++)
+   {
+      for (size_t y = 0; y < CLUSTER_Y; y++)
+      {
+         sc_uint<address_width> offset  = cluster(x,y) << (address_width-x_width-y_width);
+
+         // cleanup requests must be routed to the memory cache
+         std::ostringstream sh;
+         sh << "c_seg_memc_" << x << "_" << y;
+         maptabc.add(Segment(sh.str(), (NB_PROCS_MAX << (address_width - srcid_width)) + offset, 
+                     0x10, IntTab(cluster(x,y), NB_PROCS_MAX), false));
+
+         // update & invalidate requests must be routed to the proper processor
+         for ( size_t p = 0 ; p < NB_PROCS_MAX ; p++) 
+         {
+            std::ostringstream sp;
+            sp << "c_seg_proc_" << x << "_" << y << "_" << p;
+            maptabc.add( Segment( sp.str() , (p << (address_width - srcid_width)) + offset , 
+                         0x10 , IntTab(cluster(x,y), p) , false)); 
+         }
+      }
+   }
+   std::cout << maptabc << std::endl;
+
+   // external network
+   MappingTable maptabx(address_width, IntTab(1), IntTab(x_width+y_width), 0xF0000000);
+
+   for (size_t x = 0; x < CLUSTER_X; x++)
+   {
+      for (size_t y = 0; y < CLUSTER_Y ; y++)
+      { 
+         sc_uint<address_width> offset  = cluster(x,y) << (address_width-x_width-y_width);
+         std::ostringstream sh;
+         sh << "x_seg_memc_" << x << "_" << y;
+         maptabx.add(Segment(sh.str(), MEMC_BASE+offset, 
+                     MEMC_SIZE, IntTab(cluster(x,y)), false));
+      }
+   }
+   std::cout << maptabx << std::endl;
+
+   ////////////////////
+   // Signals
+   ///////////////////
+
+   sc_clock      signal_clk("clk");
+   sc_signal<bool>    signal_resetn("resetn");
+
+   // Horizontal inter-clusters DSPIN signals
+   DspinSignals<cmd_width>*** signal_dspin_h_cmd_inc =
+      alloc_elems<DspinSignals<cmd_width> >("signal_dspin_h_cmd_inc", CLUSTER_X-1, CLUSTER_Y, 2);
+   DspinSignals<cmd_width>*** signal_dspin_h_cmd_dec =
+      alloc_elems<DspinSignals<cmd_width> >("signal_dspin_h_cmd_dec", CLUSTER_X-1, CLUSTER_Y, 2);
+   DspinSignals<rsp_width>*** signal_dspin_h_rsp_inc =
+      alloc_elems<DspinSignals<rsp_width> >("signal_dspin_h_rsp_inc", CLUSTER_X-1, CLUSTER_Y, 2);
+   DspinSignals<rsp_width>*** signal_dspin_h_rsp_dec =
+      alloc_elems<DspinSignals<rsp_width> >("signal_dspin_h_rsp_dec", CLUSTER_X-1, CLUSTER_Y, 2);
+
+   // Vertical inter-clusters DSPIN signals
+   DspinSignals<cmd_width>*** signal_dspin_v_cmd_inc =
+      alloc_elems<DspinSignals<cmd_width> >("signal_dspin_v_cmd_inc", CLUSTER_X, CLUSTER_Y-1, 2);
+   DspinSignals<cmd_width>*** signal_dspin_v_cmd_dec =
+      alloc_elems<DspinSignals<cmd_width> >("signal_dspin_v_cmd_dec", CLUSTER_X, CLUSTER_Y-1, 2);
+   DspinSignals<rsp_width>*** signal_dspin_v_rsp_inc =
+      alloc_elems<DspinSignals<rsp_width> >("signal_dspin_v_rsp_inc", CLUSTER_X, CLUSTER_Y-1, 2);
+   DspinSignals<rsp_width>*** signal_dspin_v_rsp_dec =
+      alloc_elems<DspinSignals<rsp_width> >("signal_dspin_v_rsp_dec", CLUSTER_X, CLUSTER_Y-1, 2);
+
+   // Mesh boundaries DSPIN signals
+   DspinSignals<cmd_width>**** signal_dspin_false_cmd_in =
+      alloc_elems<DspinSignals<cmd_width> >("signal_dspin_false_cmd_in", CLUSTER_X, CLUSTER_Y, 2, 4);
+   DspinSignals<cmd_width>**** signal_dspin_false_cmd_out =
+      alloc_elems<DspinSignals<cmd_width> >("signal_dspin_false_cmd_out", CLUSTER_X, CLUSTER_Y, 2, 4);
+   DspinSignals<rsp_width>**** signal_dspin_false_rsp_in =
+      alloc_elems<DspinSignals<rsp_width> >("signal_dspin_false_rsp_in", CLUSTER_X, CLUSTER_Y, 2, 4);
+   DspinSignals<rsp_width>**** signal_dspin_false_rsp_out =
+      alloc_elems<DspinSignals<rsp_width> >("signal_dspin_false_rsp_out", CLUSTER_X, CLUSTER_Y, 2, 4);
+
+
+   ////////////////////////////
+   //      Loader    
+   ////////////////////////////
+
+#if USE_ALMOS
+   soclib::common::Loader loader(almos_bootloader_pathname,
+                                 almos_archinfo_pathname,
+                                 almos_kernel_pathname);
+#else
+   soclib::common::Loader loader(soft_name);
+#endif
+
+   typedef soclib::common::GdbServer<soclib::common::Mips32ElIss> proc_iss;
+   proc_iss::set_loader(loader);
+
+   ////////////////////////////
+   // Clusters construction
+   ////////////////////////////
+
+   TsarV4ClusterMmu<vci_param, proc_iss, cmd_width, rsp_width>* clusters[CLUSTER_X][CLUSTER_Y];
+
+#if USE_OPENMP
+#pragma omp parallel
+    {
+#pragma omp for
+#endif
+        for(size_t i = 0; i  < (CLUSTER_X * CLUSTER_Y); i++)
+        {
+            size_t x = i / CLUSTER_Y;
+            size_t y = i % CLUSTER_Y;
+
+#if USE_OPENMP
+#pragma omp critical
+            {
+#endif
+            std::ostringstream sc;
+            sc << "cluster_" << x << "_" << y;
+            clusters[x][y] = new TsarV4ClusterMmu<vci_param, proc_iss, cmd_width, rsp_width>
+            (
+                sc.str().c_str(),
+                NB_PROCS_MAX,
+                NB_TTYS,  
+                NB_DMAS_MAX, 
+                x,
+                y,
+                cluster(x,y),
+                maptabd,
+                maptabc,
+                maptabx,
+                x_width,
+                y_width,
+                MEMC_TGTID,
+                XICU_TGTID,
+                CDMA_TGTID,
+                FBUF_TGTID,
+                MTTY_TGTID,
+                BROM_TGTID,
+                MNIC_TGTID,
+                BDEV_TGTID,
+                MEMC_WAYS,
+                MEMC_SETS,
+                L1_IWAYS,
+                L1_ISETS,
+                L1_DWAYS,
+                L1_DSETS,
+                XRAM_LATENCY,
+                (cluster(x,y) == cluster_io_id),
+                FBUF_X_SIZE,
+                FBUF_Y_SIZE,
+                disk_name,
+                BDEV_SECTOR_SIZE,
+                NB_NICS,
+                nic_rx_name,
+                nic_tx_name,
+                NIC_TIMEOUT,
+                loader,
+                frozen_cycles,
+                debug_from,
+                debug_ok and (cluster(x,y) == debug_memc_id),
+                debug_ok and (cluster(x,y) == debug_proc_id) 
+            );
+
+            std::cout << "cluster_" << x << "_" << y << " constructed" << std::endl;
+#if USE_OPENMP
+            } // end critical
+#endif
+        } // end for
+#if USE_OPENMP
+    }
+#endif
+
+   ///////////////////////////////////////////////////////////////
+   //     Net-list 
+   ///////////////////////////////////////////////////////////////
+
+   // Clock & RESET
+   for (size_t x = 0; x < (CLUSTER_X); x++){
+      for (size_t y = 0; y < CLUSTER_Y; y++){
+         clusters[x][y]->p_clk     (signal_clk);
+         clusters[x][y]->p_resetn  (signal_resetn);
+      }
+   }
+
+   // Inter Clusters horizontal connections
+   if (CLUSTER_X > 1){
+      for (size_t x = 0; x < (CLUSTER_X-1); x++){
+         for (size_t y = 0; y < CLUSTER_Y; y++){
+            for (size_t k = 0; k < 2; k++){
+               clusters[x][y]->p_cmd_out[k][EAST]      (signal_dspin_h_cmd_inc[x][y][k]);
+               clusters[x+1][y]->p_cmd_in[k][WEST]     (signal_dspin_h_cmd_inc[x][y][k]);
+               clusters[x][y]->p_cmd_in[k][EAST]       (signal_dspin_h_cmd_dec[x][y][k]);
+               clusters[x+1][y]->p_cmd_out[k][WEST]    (signal_dspin_h_cmd_dec[x][y][k]);
+               clusters[x][y]->p_rsp_out[k][EAST]      (signal_dspin_h_rsp_inc[x][y][k]);
+               clusters[x+1][y]->p_rsp_in[k][WEST]     (signal_dspin_h_rsp_inc[x][y][k]);
+               clusters[x][y]->p_rsp_in[k][EAST]       (signal_dspin_h_rsp_dec[x][y][k]);
+               clusters[x+1][y]->p_rsp_out[k][WEST]    (signal_dspin_h_rsp_dec[x][y][k]);
+            }
+         }
+      }
+   }
+   std::cout << std::endl << "Horizontal connections established" << std::endl;   
+
+   // Inter Clusters vertical connections
+   if (CLUSTER_Y > 1) {
+      for (size_t y = 0; y < (CLUSTER_Y-1); y++){
+         for (size_t x = 0; x < CLUSTER_X; x++){
+            for (size_t k = 0; k < 2; k++){
+               clusters[x][y]->p_cmd_out[k][NORTH]     (signal_dspin_v_cmd_inc[x][y][k]);
+               clusters[x][y+1]->p_cmd_in[k][SOUTH]    (signal_dspin_v_cmd_inc[x][y][k]);
+               clusters[x][y]->p_cmd_in[k][NORTH]      (signal_dspin_v_cmd_dec[x][y][k]);
+               clusters[x][y+1]->p_cmd_out[k][SOUTH]   (signal_dspin_v_cmd_dec[x][y][k]);
+               clusters[x][y]->p_rsp_out[k][NORTH]     (signal_dspin_v_rsp_inc[x][y][k]);
+               clusters[x][y+1]->p_rsp_in[k][SOUTH]    (signal_dspin_v_rsp_inc[x][y][k]);
+               clusters[x][y]->p_rsp_in[k][NORTH]      (signal_dspin_v_rsp_dec[x][y][k]);
+               clusters[x][y+1]->p_rsp_out[k][SOUTH]   (signal_dspin_v_rsp_dec[x][y][k]);
+            }
+         }
+      }
+   }
+   std::cout << "Vertical connections established" << std::endl;
+
+   // East & West boundary cluster connections
+   for (size_t y = 0; y < CLUSTER_Y; y++)
+   {
+      for (size_t k = 0; k < 2; k++)
+      {
+         clusters[0][y]->p_cmd_in[k][WEST]          (signal_dspin_false_cmd_in[0][y][k][WEST]);
+         clusters[0][y]->p_cmd_out[k][WEST]         (signal_dspin_false_cmd_out[0][y][k][WEST]);
+         clusters[0][y]->p_rsp_in[k][WEST]          (signal_dspin_false_rsp_in[0][y][k][WEST]);
+         clusters[0][y]->p_rsp_out[k][WEST]         (signal_dspin_false_rsp_out[0][y][k][WEST]);
+
+         clusters[CLUSTER_X-1][y]->p_cmd_in[k][EAST]     (signal_dspin_false_cmd_in[CLUSTER_X-1][y][k][EAST]);
+         clusters[CLUSTER_X-1][y]->p_cmd_out[k][EAST]    (signal_dspin_false_cmd_out[CLUSTER_X-1][y][k][EAST]);
+         clusters[CLUSTER_X-1][y]->p_rsp_in[k][EAST]     (signal_dspin_false_rsp_in[CLUSTER_X-1][y][k][EAST]);
+         clusters[CLUSTER_X-1][y]->p_rsp_out[k][EAST]    (signal_dspin_false_rsp_out[CLUSTER_X-1][y][k][EAST]);
+      }
+   }
+
+   // North & South boundary clusters connections
+   for (size_t x = 0; x < CLUSTER_X; x++)
+   {
+      for (size_t k = 0; k < 2; k++)
+      {
+         clusters[x][0]->p_cmd_in[k][SOUTH]         (signal_dspin_false_cmd_in[x][0][k][SOUTH]);
+         clusters[x][0]->p_cmd_out[k][SOUTH]        (signal_dspin_false_cmd_out[x][0][k][SOUTH]);
+         clusters[x][0]->p_rsp_in[k][SOUTH]         (signal_dspin_false_rsp_in[x][0][k][SOUTH]);
+         clusters[x][0]->p_rsp_out[k][SOUTH]        (signal_dspin_false_rsp_out[x][0][k][SOUTH]);
+
+         clusters[x][CLUSTER_Y-1]->p_cmd_in[k][NORTH]    (signal_dspin_false_cmd_in[x][CLUSTER_Y-1][k][NORTH]);
+         clusters[x][CLUSTER_Y-1]->p_cmd_out[k][NORTH]   (signal_dspin_false_cmd_out[x][CLUSTER_Y-1][k][NORTH]);
+         clusters[x][CLUSTER_Y-1]->p_rsp_in[k][NORTH]    (signal_dspin_false_rsp_in[x][CLUSTER_Y-1][k][NORTH]);
+         clusters[x][CLUSTER_Y-1]->p_rsp_out[k][NORTH]   (signal_dspin_false_rsp_out[x][CLUSTER_Y-1][k][NORTH]);
+      }
+   }
+
+
+   ////////////////////////////////////////////////////////
+   //   Simulation
+   ///////////////////////////////////////////////////////
+
+   sc_start(sc_core::sc_time(0, SC_NS));
+   signal_resetn = false;
+
+   // network boundaries signals
+   for (size_t x = 0; x < CLUSTER_X ; x++){
+      for (size_t y = 0; y < CLUSTER_Y ; y++){
+         for (size_t k = 0; k < 2; k++){
+            for (size_t a = 0; a < 4; a++){
+               signal_dspin_false_cmd_in[x][y][k][a].write = false;
+               signal_dspin_false_cmd_in[x][y][k][a].read = true;
+               signal_dspin_false_cmd_out[x][y][k][a].write = false;
+               signal_dspin_false_cmd_out[x][y][k][a].read = true;
+
+               signal_dspin_false_rsp_in[x][y][k][a].write = false;
+               signal_dspin_false_rsp_in[x][y][k][a].read = true;
+               signal_dspin_false_rsp_out[x][y][k][a].write = false;
+               signal_dspin_false_rsp_out[x][y][k][a].read = true;
+            }
+         }
+      }
+   }
+
+   sc_start(sc_core::sc_time(1, SC_NS));
+   signal_resetn = true;
+
+   for (size_t n = 1; n < ncycles; n++)
+   {
+
+      if (debug_ok and (n > debug_from) and (n % debug_period == 0))
+      {
+         std::cout << "****************** cycle " << std::dec << n ;
+         std::cout << " ************************************************" << std::endl;
+
+         // trace proc[debug_proc_id] 
+         if ( debug_proc_id < (CLUSTER_X * CLUSTER_Y * NB_PROCS_MAX) )
+         {
+             size_t proc_x = debug_proc_id / CLUSTER_Y;
+             size_t proc_y = debug_proc_id % CLUSTER_Y;
+
+             clusters[proc_x][proc_y]->proc[0]->print_trace();
+
+             clusters[proc_x][proc_y]->signal_vci_ini_d_proc[0].print_trace("proc_ini_d");
+             clusters[proc_x][proc_y]->signal_vci_ini_c_proc[0].print_trace("proc_ini_c");
+             clusters[proc_x][proc_y]->signal_vci_tgt_c_proc[0].print_trace("proc_tgt_c");
+         }
+
+         // trace memc[debug_memc_id] 
+         if ( debug_memc_id < (CLUSTER_X * CLUSTER_Y) )
+         {
+             size_t memc_x = debug_memc_id / CLUSTER_Y;
+             size_t memc_y = debug_memc_id % CLUSTER_Y;
+
+             clusters[memc_x][memc_y]->memc->print_trace();
+
+             clusters[memc_x][memc_y]->signal_vci_tgt_d_memc.print_trace("memc_tgt_d");
+             clusters[memc_x][memc_y]->signal_vci_ini_c_memc.print_trace("memc_ini_c");
+             clusters[memc_x][memc_y]->signal_vci_tgt_c_memc.print_trace("memc_tgt_c");
+         }
+
+// clusters[0][0]->signal_vci_tgt_d_xicu.print_trace("xicu_0_0");
+// clusters[0][1]->signal_vci_tgt_d_xicu.print_trace("xicu_0_1");
+// clusters[1][0]->signal_vci_tgt_d_xicu.print_trace("xicu_1_0");
+// clusters[1][1]->signal_vci_tgt_d_xicu.print_trace("xicu_1_1");
+
+// if ( clusters[1][1]->signal_irq_mdma[0].read() ) 
+//    std::cout << std::endl << " IRQ_DMA_1_1 activated" << std::endl;
+// if ( clusters[1][1]->signal_proc_it[0].read() )
+//    std::cout <<  " IRQ_PROC_1_1 activated" << std::endl << std::endl;
+
+// trace ioc component 
+// size_t io_x   = cluster_io_id / CLUSTER_Y;
+// size_t io_y   = cluster_io_id % CLUSTER_Y;
+// clusters[io_x][io_y]->bdev->print_trace();
+// clusters[io_x][io_y]->signal_vci_tgt_d_bdev.print_trace("bdev_1_0_tgt_d  ");
+// clusters[io_x][io_y]->signal_vci_ini_d_bdev.print_trace("bdev_1_0_ini_d  ");
+
+// clusters[1][1]->mdma->print_trace();
+// clusters[1][1]->signal_vci_tgt_d_mdma.print_trace("mdma_1_1_tgt_d  ");
+// clusters[1][1]->signal_vci_ini_d_mdma.print_trace("mdma_1_1_ini_d  ");
+
+      }
+
+      sc_start(sc_core::sc_time(1, SC_NS));
+   }
+   return EXIT_SUCCESS;
+}
+
+int sc_main (int argc, char *argv[])
+{
+   try {
+      return _main(argc, argv);
+   } catch (std::exception &e) {
+      std::cout << e.what() << std::endl;
+   } catch (...) {
+      std::cout << "Unknown exception occured" << std::endl;
+      throw;
+   }
+   return 1;
+}
+
+
+// Local Variables:
+// tab-width: 3
+// c-basic-offset: 3
+// c-file-offsets:((innamespace . 0)(inline-open . 0))
+// indent-tabs-mode: nil
+// End:
+
+// vim: filetype=cpp:expandtab:shiftwidth=3:tabstop=3:softtabstop=3
+
+
+
+
Index: branches/v4/platforms/tsarv4_generic_mmu/top.desc
===================================================================
--- branches/v4/platforms/tsarv4_generic_mmu/top.desc	(revision 371)
+++ branches/v4/platforms/tsarv4_generic_mmu/top.desc	(revision 371)
@@ -0,0 +1,24 @@
+
+# -*- python -*-
+
+todo = Platform('caba', 'top.cpp',
+	uses = [
+            Uses('caba:tsarv4_cluster_mmu', 
+                 iss_t = 'common:gdb_iss', 
+                 gdb_iss_t = 'common:mips32el', 
+                 cmd_width = 40, 
+                 rsp_width = 33),
+	    Uses('common:elf_file_loader'),
+            Uses('common:plain_file_loader'),
+	],
+	cell_size = 4,
+	plen_size = 8,
+	addr_size = 32,
+	rerror_size = 2,
+	clen_size = 1,
+	rflag_size = 1,
+	srcid_size = 14,
+	pktid_size = 4,
+	trdid_size = 4,
+	wrplen_size = 1,
+)
Index: branches/v4/platforms/tsarv4_generic_mmu/tsarv4_cluster_mmu/caba/metadata/tsarv4_cluster_mmu.sd
===================================================================
--- branches/v4/platforms/tsarv4_generic_mmu/tsarv4_cluster_mmu/caba/metadata/tsarv4_cluster_mmu.sd	(revision 371)
+++ branches/v4/platforms/tsarv4_generic_mmu/tsarv4_cluster_mmu/caba/metadata/tsarv4_cluster_mmu.sd	(revision 371)
@@ -0,0 +1,52 @@
+
+# -*- python -*-
+
+Module('caba:tsarv4_cluster_mmu',
+	classname = 'soclib::caba::TsarV4ClusterMmu',
+	tmpl_parameters = [
+		parameter.Module('vci_param', default = 'caba:vci_param'),
+		parameter.Module('iss_t'),
+		parameter.Int('cmd_width'),
+		parameter.Int('rsp_width'),
+		],
+	header_files = [ '../source/include/tsarv4_cluster_mmu.h', ],
+	implementation_files = [ '../source/src/tsarv4_cluster_mmu.cpp', ],
+	uses = [
+		Uses('caba:base_module'),
+		Uses('common:mapping_table'),
+		Uses('common:iss2'),
+		Uses('caba:vci_cc_vcache_wrapper_v4', 
+                     iss_t = 'common:gdb_iss', 
+                     gdb_iss_t = 'common:mips32el'),
+		Uses('caba:vci_mem_cache_v4'),
+		Uses('caba:vci_simple_ram'),
+        Uses('caba:vci_xicu'),
+        Uses('caba:vci_local_crossbar'),
+        Uses('caba:virtual_dspin_router', 
+                     flit_width = parameter.Reference('cmd_width')),
+        Uses('caba:virtual_dspin_router', 
+                     flit_width = parameter.Reference('rsp_width')),
+        Uses('caba:vci_vdspin_target_wrapper', 
+                     dspin_cmd_width = parameter.Reference('cmd_width'), 
+                     dspin_rsp_width = parameter.Reference('rsp_width')),
+        Uses('caba:vci_vdspin_initiator_wrapper', 
+                     dspin_cmd_width = parameter.Reference('cmd_width'), 
+                     dspin_rsp_width = parameter.Reference('rsp_width')),
+		Uses('caba:vci_multi_tty'),
+		Uses('caba:vci_framebuffer'),
+		Uses('caba:vci_multi_nic'),
+		Uses('caba:vci_block_device_tsar_v4'),
+		Uses('caba:vci_multi_dma'),
+		Uses('common:elf_file_loader'),
+		],
+	ports = [
+		Port('caba:bit_in', 'p_resetn', auto = 'resetn'),
+		Port('caba:clock_in', 'p_clk', auto = 'clock'),
+		Port('caba:dspin_output', 'p_cmd_out', [2, 4], dspin_data_size = parameter.Reference('cmd_width')),
+		Port('caba:dspin_input', 'p_cmd_in', [2, 4], dspin_data_size = parameter.Reference('cmd_width')),
+		Port('caba:dspin_output', 'p_rsp_out', [2, 4], dspin_data_size = parameter.Reference('rsp_width')), 
+		Port('caba:dspin_input', 'p_rsp_in', [2, 4], dspin_data_size = parameter.Reference('rsp_width')),
+		],
+)
+
+
Index: branches/v4/platforms/tsarv4_generic_mmu/tsarv4_cluster_mmu/caba/source/include/tsarv4_cluster_mmu.h
===================================================================
--- branches/v4/platforms/tsarv4_generic_mmu/tsarv4_cluster_mmu/caba/source/include/tsarv4_cluster_mmu.h	(revision 371)
+++ branches/v4/platforms/tsarv4_generic_mmu/tsarv4_cluster_mmu/caba/source/include/tsarv4_cluster_mmu.h	(revision 371)
@@ -0,0 +1,171 @@
+//////////////////////////////////////////////////////////////////////////////
+// File: tsarv4_cluster_mmu.h
+// Author: Alain Greiner 
+// Copyright: UPMC/LIP6
+// Date : march 2011
+// This program is released under the GNU public license
+//////////////////////////////////////////////////////////////////////////////
+
+#ifndef SOCLIB_CABA_TSAR_CLUSTER_V4_MMU_H
+#define SOCLIB_CABA_TSAR_CLUSTER_V4_MMU_H
+
+#include <systemc>
+#include <sys/time.h>
+#include <iostream>
+#include <sstream>
+#include <cstdlib>
+#include <cstdarg>
+
+#include "gdbserver.h"
+#include "mapping_table.h"
+#include "mips32.h"
+#include "vci_simple_ram.h"
+#include "vci_xicu.h"
+#include "vci_local_crossbar.h"
+#include "virtual_dspin_router.h"
+#include "vci_vdspin_target_wrapper.h"
+#include "vci_vdspin_initiator_wrapper.h"
+#include "vci_multi_tty.h"
+#include "vci_multi_nic.h"
+#include "vci_block_device_tsar_v4.h"
+#include "vci_framebuffer.h"
+#include "vci_multi_dma.h"
+#include "vci_mem_cache_v4.h"
+#include "vci_cc_vcache_wrapper_v4.h"
+
+namespace soclib {
+namespace caba	{
+
+///////////////////////////////////////////////////////////////////////////
+template<typename vci_param, typename iss_t, int cmd_width, int rsp_width>
+class TsarV4ClusterMmu 
+///////////////////////////////////////////////////////////////////////////
+    : public soclib::caba::BaseModule
+{
+
+  public:
+
+	// Ports
+    sc_in<bool>                             		p_clk;
+    sc_in<bool>                             		p_resetn;
+	soclib::caba::DspinOutput<cmd_width>   			**p_cmd_out;
+	soclib::caba::DspinInput<cmd_width>    			**p_cmd_in;
+    soclib::caba::DspinOutput<rsp_width>           	**p_rsp_out;
+    soclib::caba::DspinInput<rsp_width>            	**p_rsp_in;
+
+    // interrupt signals
+	sc_signal<bool>     	signal_false;
+	sc_signal<bool> 		signal_proc_it[8];
+	sc_signal<bool> 		signal_irq_mdma[8];
+	sc_signal<bool>			signal_irq_mtty[23];
+	sc_signal<bool> 		signal_irq_mnic_rx[8];	// unused
+	sc_signal<bool> 		signal_irq_mnic_tx[8];	// unused
+	sc_signal<bool> 		signal_irq_bdev;
+	
+	// DSPIN signals between DSPIN routers and VCI/DSPIN wrappers
+	DspinSignals<cmd_width> 	signal_dspin_cmd_l2g_d; 
+	DspinSignals<cmd_width> 	signal_dspin_cmd_g2l_d; 
+	DspinSignals<cmd_width> 	signal_dspin_cmd_l2g_c;
+	DspinSignals<cmd_width> 	signal_dspin_cmd_g2l_c; 
+	DspinSignals<rsp_width> 	signal_dspin_rsp_l2g_d; 
+	DspinSignals<rsp_width> 	signal_dspin_rsp_g2l_d; 
+	DspinSignals<rsp_width> 	signal_dspin_rsp_l2g_c;
+	DspinSignals<rsp_width> 	signal_dspin_rsp_g2l_c;
+
+	// VCI signals between VCI/DSPIN wrappers and local crossbars
+	VciSignals<vci_param>  		signal_vci_l2g_d; 
+	VciSignals<vci_param>  		signal_vci_g2l_d; 
+	VciSignals<vci_param>  		signal_vci_l2g_c; 
+	VciSignals<vci_param>  		signal_vci_g2l_c; 
+
+	// Direct VCI signals
+	VciSignals<vci_param> 		signal_vci_ini_d_proc[4]; 
+	VciSignals<vci_param>  		signal_vci_ini_d_bdev; 
+	VciSignals<vci_param>  		signal_vci_ini_d_mdma; 
+
+	VciSignals<vci_param>		signal_vci_tgt_d_memc;
+	VciSignals<vci_param> 		signal_vci_tgt_d_mtty;
+	VciSignals<vci_param> 		signal_vci_tgt_d_xicu;
+	VciSignals<vci_param> 		signal_vci_tgt_d_bdev;
+	VciSignals<vci_param> 		signal_vci_tgt_d_mdma;
+	VciSignals<vci_param> 		signal_vci_tgt_d_brom;
+	VciSignals<vci_param> 		signal_vci_tgt_d_fbuf;
+	VciSignals<vci_param> 		signal_vci_tgt_d_mnic;
+
+	// Coherence VCi signals
+	VciSignals<vci_param> 		signal_vci_ini_c_proc[4];
+	VciSignals<vci_param> 		signal_vci_tgt_c_proc[4];
+	VciSignals<vci_param> 		signal_vci_ini_c_memc;
+	VciSignals<vci_param> 		signal_vci_tgt_c_memc;
+
+	// external RAM VCI signal
+	VciSignals<vci_param> 		signal_vci_xram;
+	
+    // Components
+
+    VciCcVCacheWrapperV4<vci_param, iss_t>*                 	proc[8];
+    VciMemCacheV4<vci_param>*                               	memc;
+    VciXicu<vci_param>*                                     	xicu;
+    VciLocalCrossbar<vci_param>*                                xbard;
+    VciLocalCrossbar<vci_param>*                                xbarc;
+    VciVdspinTargetWrapper<vci_param,cmd_width,rsp_width>*      tgtwrapperd;
+    VciVdspinInitiatorWrapper<vci_param,cmd_width,rsp_width>*   iniwrapperd;
+    VciVdspinTargetWrapper<vci_param,cmd_width,rsp_width>*      tgtwrapperc;
+    VciVdspinInitiatorWrapper<vci_param,cmd_width,rsp_width>*   iniwrapperc;
+    VirtualDspinRouter<cmd_width>*                              cmdrouter;
+    VirtualDspinRouter<rsp_width>*	                        	rsprouter;
+    VciSimpleRam<vci_param>*                                    brom;
+    VciMultiTty<vci_param>*                                     mtty;
+    VciFrameBuffer<vci_param>*                                  fbuf;
+    VciMultiNic<vci_param>*                                     mnic;
+    VciBlockDeviceTsarV4<vci_param>*                            bdev;
+    VciMultiDma<vci_param>*                                     mdma;
+    VciSimpleRam<vci_param>*                                    xram;
+
+	TsarV4ClusterMmu(sc_module_name                     insname,
+                     size_t                             nb_procs,      // number of processors 
+                     size_t                             nb_ttys,       // number of TTY terminals 
+                     size_t                             nb_dmas,       // number of DMA channels 
+                     size_t                             x,             // x coordinate
+                     size_t                             y,             // y coordinate
+                     size_t                             cluster,       // y + ymax*x
+                     const soclib::common::MappingTable &mtd,          // direct mapping table
+                     const soclib::common::MappingTable &mtc,          // coherence mapping table
+                     const soclib::common::MappingTable &mtx,          // xram mapping table
+                     size_t	                            x_width,       // x field number of bits
+                     size_t	                            y_width,       // y field number of bits
+                     size_t	                            tgtid_memc,
+                     size_t	                            tgtid_xicu,
+                     size_t                             tgtid_mdma,
+                     size_t	                            tgtid_fbuf,
+                     size_t                             tgtid_mtty,
+                     size_t                             tgtid_brom,
+                     size_t                             tgtid_mnic,
+                     size_t                             tgtid_bdev,
+                     size_t                             memc_ways,
+                     size_t                             memc_sets,
+                     size_t                             l1_i_ways,
+                     size_t                             l1_i_sets, 
+                     size_t                             l1_d_ways,
+                     size_t                             l1_d_sets,	
+                     size_t                             xram_latency,  // external ram latency
+                     bool                               io,	           // I/O cluster if true
+                     size_t                             xfb,           // frame buffer pixels
+                     size_t                             yfb,           // frame buffer lines
+                     char*                              disk_name,     // virtual disk name for BDEV
+                     size_t                             block_size,    // block size for BDEV
+                     size_t                             nic_channels,  // number of channels
+                     char*                              nic_rx_name,   // file name rx packets
+                     char*                              nic_tx_name,   // file name tx packets
+                     uint32_t							nic_timeout,   // number of cycles
+			         const Loader                       &loader,       // loader for BROM
+                     uint32_t                           frozen_cycles, // max frozen cycles
+                     uint32_t                           start_debug_cycle,
+                     bool                               memc_debug_ok, 
+                     bool                               proc_debug_ok); 
+
+	~TsarV4ClusterMmu();
+};
+}}
+
+#endif
Index: branches/v4/platforms/tsarv4_generic_mmu/tsarv4_cluster_mmu/caba/source/src/tsarv4_cluster_mmu.cpp
===================================================================
--- branches/v4/platforms/tsarv4_generic_mmu/tsarv4_cluster_mmu/caba/source/src/tsarv4_cluster_mmu.cpp	(revision 371)
+++ branches/v4/platforms/tsarv4_generic_mmu/tsarv4_cluster_mmu/caba/source/src/tsarv4_cluster_mmu.cpp	(revision 371)
@@ -0,0 +1,574 @@
+//////////////////////////////////////////////////////////////////////////////
+// File: tsarv4_cluster_mmu.c
+// Author: Alain Greiner 
+// Copyright: UPMC/LIP6
+// Date : march 2011
+// This program is released under the GNU public license
+//////////////////////////////////////////////////////////////////////////////
+// This file define a TSAR cluster architecture with virtual memory:
+// - It uses the virtual_dspin_router as distributed global interconnect 
+// - It uses the vci_local_crossbar as local interconnect 
+// - It uses the vci_cc_vcache_wrapper_v4
+// - It uses the vci_mem_cache_v4
+// - It contains a private RAM with a variable latency to emulate the L3 cache
+// - It can contains 1, 2 or 4 processors
+// - Each processor has a private dma channel (vci_multi_dma)
+// - It uses the vci_xicu interrupt controller
+// - The peripherals MTTY, BDEV, FBUF, and the boot BROM are in the cluster 
+//   containing address 0xBFC00000.
+// - The Multi-TTY component controls up to 15 terminals. 
+// - Each Multi-DMA component controls up to 8 DMA channels.
+// - The DMA IRQs are connected to IRQ_IN[8]...IRQ_IN[15]
+// - The TTY IRQs are connected to IRQ_IN[16]...IRQ_IN[30]
+// - The BDEV IRQ is connected to IRQ_IN[31]
+////////////////////////////////////////////////////////////////////////////////// 
+
+#include "../include/tsarv4_cluster_mmu.h"
+
+namespace soclib {
+namespace caba  {
+
+//////////////////////////////////////////////////////////////////////////
+//                 Constructor
+//////////////////////////////////////////////////////////////////////////
+template<typename vci_param, typename iss_t, int cmd_width, int rsp_width>
+TsarV4ClusterMmu<vci_param, iss_t, cmd_width, rsp_width>::TsarV4ClusterMmu(
+         sc_module_name                     insname,
+         size_t                             nb_procs,
+         size_t                             nb_ttys,
+         size_t                             nb_dmas,
+         size_t                             x_id,
+         size_t                             y_id,
+         size_t                             cluster_id,
+         const soclib::common::MappingTable &mtd,
+         const soclib::common::MappingTable &mtc, 
+         const soclib::common::MappingTable &mtx, 
+         size_t                             x_width,
+         size_t                             y_width,
+         size_t                             tgtid_memc,
+         size_t                             tgtid_xicu,
+         size_t                             tgtid_mdma,
+         size_t                             tgtid_fbuf,
+         size_t                             tgtid_mtty,
+         size_t                             tgtid_brom,
+         size_t                             tgtid_mnic,
+         size_t                             tgtid_bdev,
+         size_t                             memc_ways,
+         size_t                             memc_sets,
+         size_t                             l1_i_ways,
+         size_t                             l1_i_sets,
+         size_t                             l1_d_ways,
+         size_t                             l1_d_sets,
+         size_t                             xram_latency,
+         bool                               io,
+         size_t                             xfb,
+         size_t                             yfb,
+         char*                              disk_name,
+         size_t                             block_size,
+         size_t                             nic_channels,
+         char*                              nic_rx_name,
+         char*                              nic_tx_name,
+         uint32_t                           nic_timeout,
+         const Loader                      &loader,
+         uint32_t                           frozen_cycles,
+         uint32_t                           debug_start_cycle,
+         bool                               memc_debug_ok,
+         bool                               proc_debug_ok)
+            : soclib::caba::BaseModule(insname),
+            p_clk("clk"),
+            p_resetn("resetn")
+
+{
+    // Vectors of ports definition
+
+    p_cmd_in        = alloc_elems<DspinInput<cmd_width> >("p_cmd_in", 2, 4);
+    p_cmd_out       = alloc_elems<DspinOutput<cmd_width> >("p_cmd_out", 2, 4);
+    p_rsp_in        = alloc_elems<DspinInput<rsp_width> >("p_rsp_in", 2, 4);
+    p_rsp_out       = alloc_elems<DspinOutput<rsp_width> >("p_rsp_out", 2, 4);
+
+    // Components definition 
+
+    // on direct network : local srcid[proc] in [0..nb_procs-1]
+    // on direct network : local srcid[mdma] = nb_procs
+    // on direct network : local srcid[bdev] = nb_procs + 1
+
+    // on coherence network : local srcid[proc] in [0...nb_procs-1]
+    // on coherence network : local srcid[memc] = nb_procs
+
+    std::cout << "  - building proc_" << x_id << "_" << y_id << "-*" << std::endl;
+
+    for (size_t p = 0; p < nb_procs; p++)
+    { 
+        std::ostringstream sproc;
+        sproc << "proc_" << x_id << "_" << y_id << "_" << p;
+        proc[p] = new VciCcVCacheWrapperV4<vci_param, iss_t>(
+                      sproc.str().c_str(),
+                      cluster_id*nb_procs + p,
+                      mtd,                            // Mapping Table Direct
+                      mtc,                            // Mapping Table Coherence
+                      IntTab(cluster_id,p),           // SRCID_D
+                      IntTab(cluster_id,p),           // SRCID_C
+                      IntTab(cluster_id,p),           // TGTID_C
+                      8,                              // ITLB ways
+                      8,                              // ITLB sets
+                      8,                              // DTLB ways
+                      8,                              // DTLB sets
+                      l1_i_ways,l1_i_sets,16,         // ICACHE size
+                      l1_d_ways,l1_d_sets,16,         // DCACHE size
+                      4,                              // WBUF nlines
+                      4,                              // WBUF nwords
+                      x_width,
+                      y_width,
+                      nb_procs,                       // MEMC local index
+                      frozen_cycles,                  // max frozen cycles
+                      debug_start_cycle,
+                      proc_debug_ok);
+    }
+
+    std::cout << "  - building memc_" << x_id << "_" << y_id << std::endl;
+
+    std::ostringstream smemc;
+    smemc << "memc_" << x_id << "_" << y_id;
+    memc = new VciMemCacheV4<vci_param>(
+                     smemc.str().c_str(),
+                     mtd, mtc, mtx,
+                     IntTab(cluster_id),              // SRCID_X
+                     IntTab(cluster_id, nb_procs),    // SRCID_C
+                     IntTab(cluster_id, tgtid_memc),  // TGTID_D
+                     IntTab(cluster_id, nb_procs),    // TGTID_C
+                     memc_ways, memc_sets, 16,        // CACHE SIZE
+                     4096,                            // HEAP SIZE
+                     8,                               // TRANSACTION TABLE DEPTH
+                     8,                               // UPDATE TABLE DEPTH
+                     debug_start_cycle,
+                     memc_debug_ok);
+
+    std::cout << "  - building xram_" << x_id << "_" << y_id << std::endl;
+
+    std::ostringstream sxram;
+    sxram << "xram_" << x_id << "_" << y_id;
+    xram = new VciSimpleRam<vci_param>(
+                     sxram.str().c_str(),
+                     IntTab(cluster_id),
+                     mtx,
+                     loader,
+                     xram_latency);
+
+    std::cout << "  - building xicu_" << x_id << "_" << y_id << std::endl;
+
+    std::ostringstream sicu;
+    sicu << "xicu_" << x_id << "_" << y_id;
+    xicu = new VciXicu<vci_param>(
+                     sicu.str().c_str(),
+                     mtd,                               // mapping table
+                     IntTab(cluster_id, tgtid_xicu),    // TGTID_D
+                     nb_procs,                          // number of timer IRQs
+                     32,                                // number of hard IRQs
+                     0,                                 // number of soft IRQs
+                     nb_procs);                         // number of output IRQs
+
+    std::cout << "  - building dma_" << x_id << "_" << y_id << std::endl;
+
+    std::ostringstream sdma;
+    sdma << "dma_" << x_id << "_" << y_id;
+    mdma = new VciMultiDma<vci_param>(
+                     sdma.str().c_str(),
+                     mtd,
+                     IntTab(cluster_id, nb_procs),        // SRCID
+                     IntTab(cluster_id, tgtid_mdma),      // TGTID
+                     64,                                  // burst size
+                     nb_procs);                           // number of IRQs
+
+    std::cout << "  - building xbard_" << x_id << "_" << y_id << std::endl;
+
+    size_t nb_direct_initiators      = nb_procs + 1;
+    size_t nb_direct_targets         = 3;
+    if ( io )
+    {
+        nb_direct_initiators         = nb_procs + 2;
+        nb_direct_targets            = 8;
+    }
+    std::ostringstream sd;
+    sd << "xbard_" << x_id << "_" << y_id;
+    xbard = new VciLocalCrossbar<vci_param>(
+                     sd.str().c_str(),
+                     mtd,
+                     IntTab(cluster_id),           // cluster initiator index
+                     IntTab(cluster_id),           // cluster target index
+                     nb_direct_initiators,         // number of initiators
+                     nb_direct_targets);           // number of targets      
+
+    std::cout << "  - building xbarc_" << x_id << "_" << y_id << std::endl;
+
+    std::ostringstream sc;
+    sc << "xbarc_" << x_id << "_" << y_id;
+    xbarc = new VciLocalCrossbar<vci_param>(
+                     sc.str().c_str(),
+                     mtc,
+                     IntTab(cluster_id),           // cluster initiator index
+                     IntTab(cluster_id),           // cluster target index
+                     nb_procs + 1,                 // number of initiators
+                     nb_procs + 1);                // number of targets
+
+    std::cout << "  - building wrappers in cluster_" << x_id << "_" << y_id << std::endl;
+
+    std::ostringstream wid;
+    wid << "iniwrapperd_" << x_id << "_" << y_id;
+    iniwrapperd = new VciVdspinInitiatorWrapper<vci_param,cmd_width,rsp_width>(
+                     wid.str().c_str(),
+                     4,                            // cmd fifo depth
+                     4);                           // rsp fifo depth
+
+    std::ostringstream wtd;
+    wtd << "tgtwrapperd_" << x_id << "_" << y_id;
+    tgtwrapperd = new VciVdspinTargetWrapper<vci_param,cmd_width,rsp_width>(
+                     wtd.str().c_str(),
+                     4,                            // cmd fifo depth
+                     4);                           // rsp fifo depth
+
+    std::ostringstream wic;
+    wic << "iniwrapperc_" << x_id << "_" << y_id;
+    iniwrapperc = new VciVdspinInitiatorWrapper<vci_param,cmd_width,rsp_width>(
+                     wic.str().c_str(),
+                     4,                            // cmd fifo depth
+                     4);                           // rsp fifo depth
+
+    std::ostringstream wtc;
+    wtc << "tgtwrapperc_" << x_id << "_" << y_id;
+    tgtwrapperc = new VciVdspinTargetWrapper<vci_param,cmd_width,rsp_width>(
+    wtc.str().c_str(),
+                     4,                            // cmd fifo depth
+                     4);                           // rsp fifo depth
+
+    std::cout << "  - building cmdrouter_" << x_id << "_" << y_id << std::endl;
+
+    std::ostringstream scmd;
+    scmd << "cmdrouter_" << x_id << "_" << y_id;
+    cmdrouter = new VirtualDspinRouter<cmd_width>(
+                     scmd.str().c_str(),
+                     x_id,y_id,                    // coordinate in the mesh
+                     x_width, y_width,             // x & y fields width
+                     4,4);                         // input & output fifo depths
+
+    std::cout << "  - building rsprouter_" << x_id << "_" << y_id << std::endl;
+
+    std::ostringstream srsp;
+    srsp << "rsprouter_" << x_id << "_" << y_id;
+    rsprouter = new VirtualDspinRouter<rsp_width>(
+                     srsp.str().c_str(),
+                     x_id,y_id,                    // coordinates in mesh
+                     x_width, y_width,             // x & y fields width
+                     4,4);                         // input & output fifo depths
+
+    // IO cluster components
+    if ( io )
+    {
+        std::cout << "  - building brom" << std::endl;
+
+        brom = new VciSimpleRam<vci_param>(
+                        "brom",
+                        IntTab(cluster_id, tgtid_brom),
+                        mtd,
+                        loader);
+
+        std::cout << "  - building fbuf" << std::endl;
+
+        fbuf = new VciFrameBuffer<vci_param>(
+                        "fbuf",
+                        IntTab(cluster_id, tgtid_fbuf),
+                        mtd,
+                        xfb, yfb); 
+
+        std::cout << "  - building fbuf" << std::endl;
+
+        bdev = new VciBlockDeviceTsarV4<vci_param>(
+                        "bdev",
+                        mtd,
+                        IntTab(cluster_id, nb_procs+1),
+                        IntTab(cluster_id, tgtid_bdev),
+                        disk_name,
+                        block_size,
+                        64);            // burst size
+
+        std::cout << "  - building mnic" << std::endl;
+
+        mnic = new VciMultiNic<vci_param>(
+                        "mnic",
+                        IntTab(cluster_id, tgtid_mnic),
+                        mtd,
+                        nic_channels,
+                        nic_rx_name,
+                        nic_tx_name,
+                        0,   // default mac address MAC4
+                        0 ); // default mac address MAC2
+
+        std::cout << "  - building mtty" << std::endl;
+
+        std::vector<std::string> vect_names;
+        for( size_t tid = 0 ; tid < (nb_ttys) ; tid++ )
+        {
+            std::ostringstream term_name;
+            term_name <<  "term" << tid;
+            vect_names.push_back(term_name.str().c_str());
+        }
+        mtty = new VciMultiTty<vci_param>(
+                        "mtty",
+                        IntTab(cluster_id, tgtid_mtty),
+                        mtd, 
+                        vect_names);
+    }
+
+    std::cout << std::endl;
+
+    ////////////////////////////////////
+    // Connections are defined here
+    ////////////////////////////////////
+
+    // CMDROUTER and RSPROUTER
+    cmdrouter->p_clk                        (this->p_clk);
+    cmdrouter->p_resetn                     (this->p_resetn);
+    rsprouter->p_clk                        (this->p_clk);
+    rsprouter->p_resetn                     (this->p_resetn);
+    for (int x = 0; x < 2; x++)
+    {
+        for(int y = 0; y < 4; y++)
+        {
+            cmdrouter->p_out[x][y]          (this->p_cmd_out[x][y]);
+            cmdrouter->p_in[x][y]           (this->p_cmd_in[x][y]);
+            rsprouter->p_out[x][y]          (this->p_rsp_out[x][y]);
+            rsprouter->p_in[x][y]           (this->p_rsp_in[x][y]);
+        }
+    }
+
+    cmdrouter->p_out[0][4]                  (signal_dspin_cmd_g2l_d);
+    cmdrouter->p_out[1][4]                  (signal_dspin_cmd_g2l_c);
+    cmdrouter->p_in[0][4]                   (signal_dspin_cmd_l2g_d);
+    cmdrouter->p_in[1][4]                   (signal_dspin_cmd_l2g_c);
+
+    rsprouter->p_out[0][4]                  (signal_dspin_rsp_g2l_d);
+    rsprouter->p_out[1][4]                  (signal_dspin_rsp_g2l_c);
+    rsprouter->p_in[0][4]                   (signal_dspin_rsp_l2g_d);
+    rsprouter->p_in[1][4]                   (signal_dspin_rsp_l2g_c);
+
+    std::cout << "  - CMD & RSP routers connected" << std::endl;
+
+    // VCI/DSPIN WRAPPERS
+    iniwrapperd->p_clk                      (this->p_clk);
+    iniwrapperd->p_resetn                   (this->p_resetn);
+    iniwrapperd->p_vci                      (signal_vci_l2g_d);
+    iniwrapperd->p_dspin_out                (signal_dspin_cmd_l2g_d);
+    iniwrapperd->p_dspin_in                 (signal_dspin_rsp_g2l_d);
+
+    tgtwrapperd->p_clk                      (this->p_clk);
+    tgtwrapperd->p_resetn                   (this->p_resetn);
+    tgtwrapperd->p_vci                      (signal_vci_g2l_d);
+    tgtwrapperd->p_dspin_out                (signal_dspin_rsp_l2g_d);
+    tgtwrapperd->p_dspin_in                 (signal_dspin_cmd_g2l_d);
+
+    iniwrapperc->p_clk                      (this->p_clk);
+    iniwrapperc->p_resetn                   (this->p_resetn);
+    iniwrapperc->p_vci                      (signal_vci_l2g_c);
+    iniwrapperc->p_dspin_out                (signal_dspin_cmd_l2g_c);
+    iniwrapperc->p_dspin_in                 (signal_dspin_rsp_g2l_c);
+
+    tgtwrapperc->p_clk                      (this->p_clk);
+    tgtwrapperc->p_resetn                   (this->p_resetn);
+    tgtwrapperc->p_vci                      (signal_vci_g2l_c);
+    tgtwrapperc->p_dspin_out                (signal_dspin_rsp_l2g_c);
+    tgtwrapperc->p_dspin_in                 (signal_dspin_cmd_g2l_c);
+
+    std::cout << "  - VCI/DSPIN wrappers connected" << std::endl;
+
+    // CROSSBAR direct
+    xbard->p_clk                            (this->p_clk);
+    xbard->p_resetn                         (this->p_resetn);
+    xbard->p_initiator_to_up                (signal_vci_l2g_d);
+    xbard->p_target_to_up                   (signal_vci_g2l_d);
+
+    xbard->p_to_target[tgtid_memc]          (signal_vci_tgt_d_memc);
+    xbard->p_to_target[tgtid_xicu]          (signal_vci_tgt_d_xicu);
+    xbard->p_to_target[tgtid_mdma]          (signal_vci_tgt_d_mdma);
+
+    xbard->p_to_initiator[nb_procs]         (signal_vci_ini_d_mdma);
+
+    for (size_t p = 0; p < nb_procs; p++)
+    {
+        xbard->p_to_initiator[p]            (signal_vci_ini_d_proc[p]);
+    }
+
+    if ( io )
+    {
+        xbard->p_to_target[tgtid_mtty]      (signal_vci_tgt_d_mtty);
+        xbard->p_to_target[tgtid_brom]      (signal_vci_tgt_d_brom);
+        xbard->p_to_target[tgtid_bdev]      (signal_vci_tgt_d_bdev);
+        xbard->p_to_target[tgtid_fbuf]      (signal_vci_tgt_d_fbuf);
+        xbard->p_to_target[tgtid_mnic]      (signal_vci_tgt_d_mnic);
+
+        xbard->p_to_initiator[nb_procs+1]   (signal_vci_ini_d_bdev);
+    }
+
+    std::cout << "  - Direct crossbar connected" << std::endl;
+
+    // CROSSBAR coherence
+    xbarc->p_clk                            (this->p_clk);
+    xbarc->p_resetn                         (this->p_resetn);
+    xbarc->p_initiator_to_up                (signal_vci_l2g_c);
+    xbarc->p_target_to_up                   (signal_vci_g2l_c);
+    xbarc->p_to_initiator[nb_procs]         (signal_vci_ini_c_memc);
+    xbarc->p_to_target[nb_procs]            (signal_vci_tgt_c_memc);
+    for (size_t p = 0; p < nb_procs; p++) 
+    {
+        xbarc->p_to_target[p]               (signal_vci_tgt_c_proc[p]);
+        xbarc->p_to_initiator[p]            (signal_vci_ini_c_proc[p]);
+    }
+
+    std::cout << "  - Coherence crossbar connected" << std::endl;
+
+    // Processors
+    for (size_t p = 0; p < nb_procs; p++)
+    {
+        proc[p]->p_clk                      (this->p_clk);
+        proc[p]->p_resetn                   (this->p_resetn);
+        proc[p]->p_vci_ini_d                (signal_vci_ini_d_proc[p]);
+        proc[p]->p_vci_ini_c                (signal_vci_ini_c_proc[p]);
+        proc[p]->p_vci_tgt_c                (signal_vci_tgt_c_proc[p]);
+        proc[p]->p_irq[0]                   (signal_proc_it[p]);
+        for ( size_t j = 1 ; j < 6 ; j++)
+        {
+            proc[p]->p_irq[j]               (signal_false);
+        }
+    }
+
+    std::cout << "  - Processors connected" << std::endl;
+
+    // XICU
+    xicu->p_clk                     	(this->p_clk);
+    xicu->p_resetn                  	(this->p_resetn);
+    xicu->p_vci                     	(signal_vci_tgt_d_xicu);
+    for ( size_t p=0 ; p<nb_procs ; p++)
+    {
+        xicu->p_irq[p]              	(signal_proc_it[p]);
+    }
+    for ( size_t i=0 ; i<32 ; i++)
+    {
+        if ( io ) // I/O cluster
+        {
+            if      (i < 8)                  xicu->p_hwi[i] (signal_false);
+            else if (i < (8 + nb_dmas))      xicu->p_hwi[i]	(signal_irq_mdma[i-8]);
+            else if (i < 16)                 xicu->p_hwi[i] (signal_false);
+            else if (i < (16 + nb_ttys))     xicu->p_hwi[i] (signal_irq_mtty[i-16]);
+            else if (i < 31)                 xicu->p_hwi[i]	(signal_false);
+            else                             xicu->p_hwi[i] (signal_irq_bdev);
+        }
+        else      // other clusters
+        {
+            if      (i < 8)                  xicu->p_hwi[i] (signal_false);
+            else if (i < (8 + nb_dmas))      xicu->p_hwi[i]	(signal_irq_mdma[i-8]);
+            else                             xicu->p_hwi[i]	(signal_false);
+        }
+    }
+
+    std::cout << "  - XICU connected" << std::endl;
+
+    // MEMC
+    memc->p_clk                     	(this->p_clk);
+    memc->p_resetn                  	(this->p_resetn);
+    memc->p_vci_ixr                 	(signal_vci_xram);
+    memc->p_vci_tgt                 	(signal_vci_tgt_d_memc);
+    memc->p_vci_ini                 	(signal_vci_ini_c_memc);
+    memc->p_vci_tgt_cleanup         	(signal_vci_tgt_c_memc);
+
+    std::cout << "  - MEMC connected" << std::endl;
+
+    // XRAM
+    xram->p_clk                     	(this->p_clk);
+    xram->p_resetn                  	(this->p_resetn);
+    xram->p_vci                 	      (signal_vci_xram);
+
+    std::cout << "  - XRAM connected" << std::endl;
+
+    // CDMA
+    mdma->p_clk                       	(this->p_clk);
+    mdma->p_resetn                    	(this->p_resetn);
+    mdma->p_vci_target                	(signal_vci_tgt_d_mdma);
+    mdma->p_vci_initiator             	(signal_vci_ini_d_mdma);
+    for (size_t i=0 ; i<nb_dmas ; i++)
+    {
+        mdma->p_irq[i]                  (signal_irq_mdma[i]);
+    }
+
+    std::cout << "  - MDMA connected" << std::endl;
+
+	 // Components in I/O cluster
+
+	 if ( io )
+	 {
+        // BDEV            
+	     bdev->p_clk                    (this->p_clk);
+        bdev->p_resetn                 (this->p_resetn);
+        bdev->p_irq                    (signal_irq_bdev);
+        bdev->p_vci_target             (signal_vci_tgt_d_bdev);
+        bdev->p_vci_initiator          (signal_vci_ini_d_bdev);
+
+        std::cout << "  - BDEV connected" << std::endl;
+
+        // FBUF
+        fbuf->p_clk                    (this->p_clk);
+        fbuf->p_resetn                 (this->p_resetn);
+        fbuf->p_vci                    (signal_vci_tgt_d_fbuf);
+
+        std::cout << "  - FBUF connected" << std::endl;
+
+        // MNIC
+        mnic->p_clk                    (this->p_clk);
+        mnic->p_resetn                 (this->p_resetn);
+        mnic->p_vci                    (signal_vci_tgt_d_mnic);
+        for ( size_t i=0 ; i<nic_channels ; i++ )
+        {
+            mnic->p_rx_irq[i]          (signal_irq_mnic_rx[i]);
+            mnic->p_tx_irq[i]          (signal_irq_mnic_tx[i]);
+        }
+
+        std::cout << "  - MNIC connected" << std::endl;
+
+        // BROM
+        brom->p_clk                    (this->p_clk);
+        brom->p_resetn                 (this->p_resetn);
+        brom->p_vci                    (signal_vci_tgt_d_brom);
+
+        std::cout << "  - BROM connected" << std::endl;
+
+        // MTTY
+        mtty->p_clk                    (this->p_clk);
+        mtty->p_resetn                 (this->p_resetn);
+        mtty->p_vci                    (signal_vci_tgt_d_mtty);
+        for ( size_t i=0 ; i<nb_ttys ; i++ )
+        {
+            mtty->p_irq[i]           	(signal_irq_mtty[i]);
+        }
+
+        std::cout << "  - MTTY connected" << std::endl;
+   }
+} // end constructor
+
+///////////////////////////////////////////////////////////////////////////
+//    destructor
+///////////////////////////////////////////////////////////////////////////
+template<typename vci_param, typename iss_t, int cmd_width, int rsp_width>
+TsarV4ClusterMmu<vci_param, iss_t, cmd_width, rsp_width>::~TsarV4ClusterMmu() {}
+
+}
+}
+
+
+// Local Variables:
+// tab-width: 3
+// c-basic-offset: 3
+// c-file-offsets:((innamespace . 0)(inline-open . 0))
+// indent-tabs-mode: nil
+// End:
+
+// vim: filetype=cpp:expandtab:shiftwidth=3:tabstop=3:softtabstop=3
+
+
+
Index: branches/v4/platforms/tsarv4_generic_ring/Makefile
===================================================================
--- branches/v4/platforms/tsarv4_generic_ring/Makefile	(revision 371)
+++ branches/v4/platforms/tsarv4_generic_ring/Makefile	(revision 371)
@@ -0,0 +1,8 @@
+
+simulator.x: top.cpp top.desc
+	soclib-cc -P -p top.desc -I. -o simul.x
+
+clean:
+	soclib-cc -x -p top.desc -I.
+	rm -rf *.o *.x tty*
+
Index: branches/v4/platforms/tsarv4_generic_ring/soclib.conf
===================================================================
--- branches/v4/platforms/tsarv4_generic_ring/soclib.conf	(revision 371)
+++ branches/v4/platforms/tsarv4_generic_ring/soclib.conf	(revision 371)
@@ -0,0 +1,2 @@
+config.default.toolchain.set("cflags", config.default.toolchain.cflags + ['-DI_WANT_ILLEGAL_VCI'])
+
Index: branches/v4/platforms/tsarv4_generic_ring/top.cpp
===================================================================
--- branches/v4/platforms/tsarv4_generic_ring/top.cpp	(revision 371)
+++ branches/v4/platforms/tsarv4_generic_ring/top.cpp	(revision 371)
@@ -0,0 +1,880 @@
+/////////////////////////////////////////////////////////////////////////
+// File: tsarv4_generic_ring.cpp
+// Author: Alain Greiner 
+// Copyright: UPMC/LIP6
+// Date : april 2011
+// This program is released under the GNU public license
+/////////////////////////////////////////////////////////////////////////
+// This file define a generic TSAR architecture without virtual memory,
+// that can be supported by the GIET.
+// - It uses vci_local_ring_fast  as local interconnect 
+// - It uses the vci_cc_xcache_wrapper_v4 
+// - It uses the vci_mem_cache_v4
+// - It uses the vci_xicu, with one vci_multi_tty, and one
+//   vci_multi_dma controlers per cluster.
+// The physical address space is 32 bits.
+// The number of clusters cannot be larger than 256.
+// The number of processors per cluster cannot be larger than 4.
+// The parameters mut be power of 2.
+// - xmax   : number of clusters in a row
+// - ymax   : number of clusters in a column
+// - nprocs : number of processors per cluster
+//
+// The peripherals BDEV, FBUF, and the boot BROM
+// are in the cluster containing address 0xBFC00000.
+// - The nprocs TTY IRQs are connected to IRQ_IN[0] to IRQ_IN[3]
+// - The nprocs DMA IRQs are connected to IRQ_IN[4] to IRQ_IN[7]
+// - The IOC IRQ is connected to IRQ_IN[8]
+// 
+// General policy for 32 bits address decoding in direct space:
+// All segments base addresses are multiple of 64 Kbytes
+// Therefore the 16 address MSB bits completely define the target: 
+// The (x_width + y_width) MSB bits (left aligned) define
+// the cluster index, and the 8 LSB bits define the local index:
+// 
+//      | X_ID  | Y_ID  |---| LADR |     OFFSET          |
+//      |x_width|y_width|---|  8   |       16            |
+//
+// Half of all clusters being in the protected address space domain 
+// (addresses larger than 0x8000000), software must execute in
+// kernel mode to access memory if we want to exploit locality,
+// because some stacks and heaps will be in the protected domain.
+/////////////////////////////////////////////////////////////////////////
+
+#include <systemc>
+#include <sys/time.h>
+#include <iostream>
+#include <sstream>
+#include <cstdlib>
+#include <cstdarg>
+#include <stdint.h>
+
+#include "gdbserver.h"
+#include "mapping_table.h"
+#include "tsarv4_cluster_ring.h"
+#include "alloc_elems.h"
+
+///////////////////////////////////////////////////
+//               Parallelisation
+///////////////////////////////////////////////////
+
+#define USE_OPENMP               0
+#define OPENMP_THREADS_NR        8
+
+#if USE_OPENMP
+#include <omp.h>
+#endif
+
+
+//  cluster index (computed from x,y coordinates)
+#define cluster(x,y)	(y + ymax*x)
+
+// flit widths for the DSPIN network
+#define cmd_width	         40
+#define rsp_width	         33
+
+// VCI format
+#define cell_width	         4
+#define address_width	         32
+#define plen_width	         8
+#define error_width	         2
+#define clen_width	         1
+#define rflag_width	         1
+#define srcid_width	         14
+#define pktid_width	         4
+#define trdid_width	         4
+#define wrplen_width	         1
+
+///////////////////////////////////////////////////
+//     Parameters default values         
+///////////////////////////////////////////////////
+
+#define MESH_XMAX		2
+#define MESH_YMAX		2
+
+#define NPROCS			4
+#define XRAM_LATENCY            0
+
+#define MEMC_WAYS               16
+#define MEMC_SETS               256
+
+#define L1_IWAYS                4
+#define L1_ISETS                64
+
+#define L1_DWAYS                4
+#define L1_DSETS                64
+
+#define FBUF_X_SIZE             128 
+#define FBUF_Y_SIZE             128 
+
+#define	BDEV_SECTOR_SIZE 	128 
+#define BDEV_IMAGE_NAME	        "../../softs/soft_transpose_giet/images.raw"
+
+#define BOOT_SOFT_NAME	 	"../../softs/soft_transpose_giet/bin.soft"
+
+/////////////////////////////////////////////////////////
+// Segments definition 
+/////////////////////////////////////////////////////////
+// There is 5 segments replicated in all clusters:
+// - seg_icu 	-> ICU  / LADR = 0xF0
+// - seg_tty 	-> MTTY / LADR = 0xF1
+// - seg_dma 	-> CDMA / LADR = 0xF2
+// - seg_stack	-> RAM  / LADR = 0x80 to 0x8F
+// - seg_heap	-> RAM  / LADR = 0x30 to 0x7F
+//
+// There is 3 specific segments in the "IO" cluster 
+// (containing address 0xBF000000)
+// - seg_reset	-> BROM / LADR = 0xC0 to 0xCF
+// - seg_fbuf	-> FBUF / LADR = 0xD0 to OxEF
+// - seg_bdev	-> BDEV / LADR = 0xF3
+//
+// There is 3 specific segments in the "kcode" cluster
+// (containing address 0x80000000)
+// - seg_kcode	-> RAM  / LADR = 0x00 to 0x0F
+// - seg_kdata	-> RAM  / LADR = 0x10 to 0x1F
+// - seg_kunc 	-> RAM  / LADR = 0x20 to 0x2F
+//
+// There is 2 specific segments in the "code" cluster
+// (containing address 0x00000000)
+// - seg_code	-> RAM  / LADR = 0x00 to Ox0F
+// - seg_data 	-> RAM  / LADR = 0x10 to 0x1F
+//
+// There is one special segment corresponding to
+// the processors in the coherence address space
+// - seg_proc	-> PROCS / LADR = 0xB0 to 0xBF
+///////////////////////////////////////////////////
+
+// specific segments in "kcode" cluster
+
+#define KCOD_BASE               0x80000000      
+#define KCOD_SIZE               0x00010000
+
+#define KDAT_BASE               0x80100000      
+#define KDAT_SIZE               0x00010000
+
+#define KUNC_BASE               0x80200000      
+#define KUNC_SIZE               0x00010000
+
+// specific segments in "code" cluster
+
+#define CODE_BASE               0x00000000      
+#define CODE_SIZE               0x00010000
+
+#define DATA_BASE               0x00100000      
+#define DATA_SIZE               0x00010000
+
+// specific segments in "IO" cluster
+
+#define BROM_BASE               0xBFC00000      
+#define BROM_SIZE               0x00010000
+
+#define FBUF_BASE               0xBFD00000      
+#define FBUF_SIZE               0x00200000
+
+#define BDEV_BASE               0xBFF30000      
+#define BDEV_SIZE               0x00010000
+
+// replicated segments
+
+#define HEAP_BASE               0x00300000      
+#define HEAP_SIZE               0x00500000
+
+#define STAK_BASE               0x00800000      
+#define STAK_SIZE               0x00100000
+
+#define XICU_BASE               0x00F00000      
+#define XICU_SIZE               0x00010000
+
+#define MTTY_BASE               0x00F10000      
+#define MTTY_SIZE               0x00010000
+
+#define CDMA_BASE               0x00F20000      
+#define CDMA_SIZE               0x00000400
+
+#define PROC_BASE               0x00B00000      
+#define PROC_SIZE               0x00000010
+
+////////////////////////////////////////////////////////////////////
+//     TGTID definition in direct space
+// For all components:  global TGTID = global SRCID = cluster_index
+////////////////////////////////////////////////////////////////////
+
+#define MEMC_TGTID               0
+#define XICU_TGTID               1
+#define MTTY_TGTID               2
+#define CDMA_TGTID               3
+#define FBUF_TGTID               4
+#define BROM_TGTID               5
+#define BDEV_TGTID               6
+
+///////////////////////////////////////
+// service function for signal trace
+///////////////////////////////////////
+
+template <typename T>
+void  print_vci_signal(std::string name, T &sig) 
+{
+    if ( sig.cmdval )
+    {
+        std::cout << name << std::hex << " CMD : "; 
+        if ( sig.cmd.read() == 1 ) std::cout << "READ ";
+        if ( sig.cmd.read() == 2 ) std::cout << "WRITE ";
+        if ( sig.cmd.read() == 3 ) std::cout << "LL ";
+        if ( sig.cmd.read() == 4 ) std::cout << "SC ";
+        std::cout  << " address = " << sig.address 
+                   << " | wdata = " << sig.wdata  
+                   << " | srcid = " << sig.srcid 
+                   << " | trdid = " << sig.trdid 
+                   << " | eop = " << sig.eop << std::endl;
+    }
+    if ( sig.rspval )
+    std::cout << name << std::hex 
+              << " RSP : rerror = " << sig.rerror
+              << " | rdata = " << sig.rdata 
+              << " | rsrcid = " << sig.rsrcid 
+              << " | rtrdid = " << sig.rtrdid 
+              << " | reop = " << sig.reop << std::endl;
+}
+
+/////////////////////////////////
+int _main(int argc, char *argv[])
+{
+    using namespace sc_core;
+    using namespace soclib::caba;
+    using namespace soclib::common;
+    
+    
+    char    soft_name[256] = BOOT_SOFT_NAME;  	// pathname to binary code
+    size_t  ncycles        = 1000000000;       	// simulated cycles
+    size_t  xmax           = MESH_XMAX;  	// number of clusters in a row
+    size_t  ymax           = MESH_YMAX;         // number of clusters in a column
+    size_t  nprocs         = NPROCS;    	// number of processors per cluster
+    size_t  xfb            = FBUF_X_SIZE;	// frameBuffer column number
+    size_t  yfb            = FBUF_Y_SIZE;      	// frameBuffer lines number
+    size_t  memc_ways      = MEMC_WAYS;
+    size_t  memc_sets      = MEMC_SETS;
+    size_t  l1_d_ways      = L1_DWAYS;
+    size_t  l1_d_sets      = L1_DSETS;
+    size_t  l1_i_ways      = L1_IWAYS;
+    size_t  l1_i_sets      = L1_ISETS;
+    char    disk_name[256] = BDEV_IMAGE_NAME;  	// pathname to the disk image
+    size_t  blk_size       = BDEV_SECTOR_SIZE;  // block size (in bytes)
+    size_t  xram_latency   = XRAM_LATENCY;	// external RAM latency
+    bool    trace_ok       = false;            	// debug activated
+    size_t  from_cycle     = 0;                	// debug start cycle
+
+    ////////////// command line arguments //////////////////////
+    if (argc > 1)
+    {
+        for( int n=1 ; n<argc ; n=n+2 )
+        {
+            if( (strcmp(argv[n],"-NCYCLES") == 0) && (n+1<argc) )
+            {
+                ncycles = atoi(argv[n+1]);
+            }
+            else if( (strcmp(argv[n],"-NPROCS") == 0) && (n+1<argc) )
+            {
+                nprocs = atoi(argv[n+1]);
+                assert( ((nprocs == 1) || (nprocs == 2) || (nprocs == 4)) &&
+                        "NPROCS must be equal to 1, 2, or 4");
+            }
+            else if( (strcmp(argv[n],"-XMAX") == 0) && (n+1<argc) )
+            {
+                xmax = atoi(argv[n+1]);
+                assert( ((xmax == 1) || (xmax == 2) || (xmax == 4) || (xmax == 8) || (xmax == 16)) 
+                         && "The XMAX parameter must be 2, 4, 8, or 16" );
+            }
+            
+	    else if( (strcmp(argv[n],"-YMAX") == 0) && (n+1<argc) )
+            {
+                ymax = atoi(argv[n+1]);
+                assert( ((ymax == 1) || (ymax == 2) || (ymax == 4) || (ymax == 8) || (ymax == 16)) 
+                         && "The YMAX parameter must be 2, 4, 8, or 16" );
+            }
+	    else if( (strcmp(argv[n],"-XFB") == 0) && (n+1<argc) )
+            {
+	        xfb = atoi(argv[n+1]);
+            }
+	    else if( (strcmp(argv[n],"-YFB") == 0) && (n+1<argc) )
+            {
+                yfb = atoi(argv[n+1]);
+            }
+            else if( (strcmp(argv[n],"-SOFT") == 0) && (n+1<argc) )
+            {
+                strcpy(soft_name, argv[n+1]);
+            }
+            else if( (strcmp(argv[n],"-DISK") == 0) && (n+1<argc) )
+            {
+                strcpy(disk_name, argv[n+1]);
+            }
+            else if( (strcmp(argv[n],"-TRACE") == 0) && (n+1<argc) )
+            {
+                trace_ok = true;
+                from_cycle = atoi(argv[n+1]);
+            }
+	    else if((strcmp(argv[n], "-MCWAYS") == 0) && (n+1 < argc))
+	    {
+	        memc_ways = atoi(argv[n+1]);
+	    }
+	    else if((strcmp(argv[n], "-MCSETS") == 0) && (n+1 < argc))
+	    {
+	        memc_sets = atoi(argv[n+1]);
+	    }
+	    else if((strcmp(argv[n], "-XLATENCY") == 0) && (n+1 < argc))
+	    {
+	        xram_latency = atoi(argv[n+1]);
+	    }
+            else
+            {
+                std::cout << "   Arguments on the command line are (key,value) couples." << std::endl;
+                std::cout << "   The order is not important." << std::endl;
+                std::cout << "   Accepted arguments are :" << std::endl << std::endl;
+                std::cout << "     -SOFT pathname_for_embedded_soft" << std::endl;
+                std::cout << "     -DISK pathname_for_disk_image" << std::endl;
+                std::cout << "     -NCYCLES number_of_simulated_cycles" << std::endl;
+                std::cout << "     -NPROCS number_of_processors_per_cluster" << std::endl;
+                std::cout << "     -XMAX number_of_clusters_in_a_row" << std::endl;
+                std::cout << "     -YMAX number_of_clusters_in_a_column" << std::endl;
+                std::cout << "     -TRACE debug_start_cycle" << std::endl;
+                std::cout << "     -MCWAYS memory_cache_number_of_ways" << std::endl;
+                std::cout << "     -MCSETS memory_cache_number_of_sets" << std::endl;
+                std::cout << "     -XLATENCY external_ram_latency_value" << std::endl;
+                std::cout << "     -XFB fram_buffer_number_of_pixels" << std::endl;
+                std::cout << "     -YFB fram_buffer_number_of_lines" << std::endl;
+                exit(0);
+            }
+        }
+    }
+
+std::cout << std::endl;
+std::cout << " - NB_CLUSTERS = " << std::dec << xmax*ymax <<std::endl;
+std::cout << " - NB_PROCS    = " << std::dec << nprocs <<std::endl;
+std::cout << " - SOFT        = " << soft_name << std::endl;
+std::cout << std::endl;
+
+#if USE_OPENMP
+        omp_set_dynamic(false);
+        omp_set_num_threads(threads_nr);
+        std::cerr << "Built with openmp version " << _OPENMP << std::endl;
+#endif
+
+    // Define VCI parameters
+    typedef soclib::caba::VciParams<cell_width,
+                                    plen_width,
+                                    address_width,
+                                    error_width,                                   
+                                    clen_width,
+                                    rflag_width,
+                                    srcid_width,
+                                    pktid_width,
+                                    trdid_width,
+                                    wrplen_width> vci_param;
+
+    size_t	cluster_io_index;
+    size_t	cluster_code_index;
+    size_t	cluster_kcode_index;
+    size_t	x_width;
+    size_t	y_width;
+
+    if      (xmax == 1) x_width = 0;
+    else if (xmax == 2) x_width = 1;
+    else if (xmax <= 4) x_width = 2;
+    else if (xmax <= 8) x_width = 3;
+    else                x_width = 4;
+
+    if      (ymax == 1) y_width = 0;
+    else if (ymax == 2) y_width = 1;
+    else if (ymax <= 4) y_width = 2;
+    else if (ymax <= 8) y_width = 3;
+    else                y_width = 4;
+
+    cluster_io_index = 0xBF >> (8 - x_width - y_width);
+    cluster_kcode_index = 0x80 >> (8 - x_width - y_width);
+    cluster_code_index = 0;
+    
+    /////////////////////
+    //  Mapping Tables
+    /////////////////////
+
+    // direct network
+    MappingTable maptabd(address_width, 
+                         IntTab(x_width + y_width, 16 - x_width - y_width), 
+                         IntTab(x_width + y_width, srcid_width - x_width - y_width), 
+                         0x00FF0000);
+
+    for ( size_t x = 0 ; x < xmax ; x++)
+    {
+        for ( size_t y = 0 ; y < ymax ; y++)
+        {
+            sc_uint<address_width> offset  = cluster(x,y) << (address_width-x_width-y_width);
+
+            std::ostringstream 	sh;
+            sh << "d_seg_heap_" << x << "_" << y;
+            maptabd.add(Segment(sh.str(), HEAP_BASE+offset, HEAP_SIZE, IntTab(cluster(x,y),MEMC_TGTID), true));
+
+            std::ostringstream 	ss;
+            ss << "d_seg_stak_" << x << "_" << y;
+            maptabd.add(Segment(ss.str(), STAK_BASE+offset, STAK_SIZE, IntTab(cluster(x,y),MEMC_TGTID), true));
+
+            std::ostringstream 	si;
+            si << "d_seg_xicu_" << x << "_" << y;
+            maptabd.add(Segment(si.str(), XICU_BASE+offset, XICU_SIZE, IntTab(cluster(x,y),XICU_TGTID), false));
+
+            std::ostringstream 	st;
+            st << "d_seg_mtty_" << x << "_" << y;
+            maptabd.add(Segment(st.str(), MTTY_BASE+offset, MTTY_SIZE, IntTab(cluster(x,y),MTTY_TGTID), false));
+
+            std::ostringstream 	sd;
+            sd << "d_seg_cdma_" << x << "_" << y;
+            maptabd.add(Segment(sd.str(), CDMA_BASE+offset, CDMA_SIZE, IntTab(cluster(x,y),CDMA_TGTID), false));
+
+            if ( cluster(x,y) == cluster_io_index )
+            {
+	      maptabd.add(Segment("d_seg_fbuf    ", FBUF_BASE, FBUF_SIZE, IntTab(cluster(x,y),FBUF_TGTID), false));
+	      maptabd.add(Segment("d_seg_bdev    ", BDEV_BASE, BDEV_SIZE, IntTab(cluster(x,y),BDEV_TGTID), false));
+	      maptabd.add(Segment("d_seg_brom    ", BROM_BASE, BROM_SIZE, IntTab(cluster(x,y),BROM_TGTID), true));
+            }
+            if ( cluster(x,y) == cluster_code_index )
+            {
+	      maptabd.add(Segment("d_seg_code    ", CODE_BASE, CODE_SIZE, IntTab(cluster(x,y),MEMC_TGTID), true));
+	      maptabd.add(Segment("d_seg_data    ", DATA_BASE, DATA_SIZE, IntTab(cluster(x,y),MEMC_TGTID), true));
+            }
+            if ( cluster(x,y) == cluster_kcode_index )
+            {
+	      maptabd.add(Segment("d_seg_kcod    ", KCOD_BASE, KCOD_SIZE, IntTab(cluster(x,y),MEMC_TGTID), true));
+	      maptabd.add(Segment("d_seg_kdat    ", KDAT_BASE, KDAT_SIZE, IntTab(cluster(x,y),MEMC_TGTID), true));
+	      maptabd.add(Segment("d_seg_kunc    ", KUNC_BASE, KUNC_SIZE, IntTab(cluster(x,y),MEMC_TGTID), true));
+            }
+        }
+    }
+    std::cout << maptabd << std::endl;
+
+    // coherence network
+    // - tgtid_c_proc = srcid_c_proc = local procid
+    // - tgtid_c_memc = srcid_c_memc = nprocs
+    MappingTable maptabc(address_width, 
+                         IntTab(x_width + y_width, 16 - x_width - y_width), 
+                         IntTab(x_width + y_width, srcid_width - x_width - y_width), 
+                         0x00FF0000);
+
+    for ( size_t x = 0 ; x < xmax ; x++)
+    {
+        for ( size_t y = 0 ; y < ymax ; y++)
+        {
+            sc_uint<address_width> offset  = cluster(x,y) << (address_width-x_width-y_width);
+
+            // cleanup requests regarding the heap segment must be routed to the memory cache
+            std::ostringstream sh;
+            sh << "c_seg_heap_" << x << "_" << y;
+            maptabc.add(Segment(sh.str(), HEAP_BASE+offset, HEAP_SIZE, IntTab(cluster(x,y), nprocs), false));
+
+            // cleanup requests regarding the stack segmentmust be routed to the memory cache
+            std::ostringstream ss;
+            ss << "c_seg_stak_" << x << "_" << y;
+            maptabc.add(Segment(ss.str(), STAK_BASE+offset, STAK_SIZE, IntTab(cluster(x,y), nprocs), false));
+
+            // cleanup requests regarding the BROM segment are also be routed to the memory cache
+            if ( cluster(x,y) == cluster_io_index )
+            {
+                maptabc.add(Segment("c_seg_brom    ", BROM_BASE, BROM_SIZE, IntTab(cluster(x,y), nprocs), false));
+            }
+
+            // cleanup requests regarding the code and data segment musts be send to the memory cache
+            if ( cluster(x,y) == cluster_code_index )
+            {
+                maptabc.add(Segment("c_seg_code    ", CODE_BASE, CODE_SIZE, IntTab(cluster(x,y), nprocs), false));
+                maptabc.add(Segment("c_seg_data    ", DATA_BASE, DATA_SIZE, IntTab(cluster(x,y), nprocs), false));
+            }
+            // cleanup requests regarding the kcode, kunc, and kdata segments must be send to the memory cache
+            if ( cluster(x,y) == cluster_kcode_index )
+            {
+                maptabc.add(Segment("c_seg_kcod    ", KCOD_BASE, KCOD_SIZE, IntTab(cluster(x,y), nprocs), false));
+                maptabc.add(Segment("c_seg_kdat    ", KDAT_BASE, KDAT_SIZE, IntTab(cluster(x,y), nprocs), false));
+                maptabc.add(Segment("c_seg_kunc    ", KUNC_BASE, KUNC_SIZE, IntTab(cluster(x,y), nprocs), false));
+            }
+
+            // update & invalidate requests must be routed to the proper processor
+	    for ( size_t p = 0 ; p < nprocs ; p++)
+            {
+                std::ostringstream sp;
+	        sp << "c_seg_proc_" << x << "_" << y << "_" << p;
+	        maptabc.add(Segment(sp.str(), PROC_BASE+offset+(p*0x10000), PROC_SIZE, 
+                            IntTab(cluster(x,y), p), false, true, IntTab(cluster(x,y), p))); 
+            }
+        }
+    }
+    std::cout << maptabc << std::endl;
+
+    // external network
+    MappingTable maptabx(address_width, IntTab(1), IntTab(x_width+y_width), 0xF0000000);
+
+    for ( size_t x = 0 ; x < xmax ; x++)
+    {
+        for ( size_t y = 0 ; y < ymax ; y++)
+        { 
+
+            sc_uint<address_width> offset  = cluster(x,y) << (address_width-x_width-y_width);
+
+            std::ostringstream sh;
+            sh << "x_seg_heap_" << x << "_" << y;
+            maptabx.add(Segment(sh.str(), HEAP_BASE+offset, HEAP_SIZE, IntTab(cluster(x,y)), false));
+
+            std::ostringstream ss;
+            ss << "x_seg_stak_" << x << "_" << y;
+            maptabx.add(Segment(ss.str(), STAK_BASE+offset, STAK_SIZE, IntTab(cluster(x,y)), false));
+
+            if ( cluster(x,y) == cluster_code_index )
+            {
+                maptabx.add(Segment("x_seg_code    ", CODE_BASE, CODE_SIZE, IntTab(cluster(x,y)), false));
+                maptabx.add(Segment("x_seg_data    ", DATA_BASE, DATA_SIZE, IntTab(cluster(x,y)), false));
+            }
+            if ( cluster(x,y) == cluster_kcode_index )
+            {
+                maptabx.add(Segment("x_seg_kcod    ", KCOD_BASE, KCOD_SIZE, IntTab(cluster(x,y)), false));
+                maptabx.add(Segment("x_seg_kdat    ", KDAT_BASE, KDAT_SIZE, IntTab(cluster(x,y)), false));
+                maptabx.add(Segment("x_seg_kunc    ", KUNC_BASE, KUNC_SIZE, IntTab(cluster(x,y)), false));
+            }
+        }
+    }
+    std::cout << maptabx << std::endl;
+
+    ////////////////////
+    // Signals
+    ///////////////////
+
+    sc_clock		signal_clk("clk");
+    sc_signal<bool> 	signal_resetn("resetn");
+
+    // Horizontal inter-clusters DSPIN signals
+    DspinSignals<cmd_width>*** signal_dspin_h_cmd_inc =
+      alloc_elems<DspinSignals<cmd_width> >("signal_dspin_h_cmd_inc", xmax-1, ymax, 2);
+    DspinSignals<cmd_width>*** signal_dspin_h_cmd_dec =
+      alloc_elems<DspinSignals<cmd_width> >("signal_dspin_h_cmd_dec", xmax-1, ymax, 2);
+    DspinSignals<rsp_width>*** signal_dspin_h_rsp_inc =
+      alloc_elems<DspinSignals<rsp_width> >("signal_dspin_h_rsp_inc", xmax-1, ymax, 2);
+    DspinSignals<rsp_width>*** signal_dspin_h_rsp_dec =
+      alloc_elems<DspinSignals<rsp_width> >("signal_dspin_h_rsp_dec", xmax-1, ymax, 2);
+
+    // Vertical inter-clusters DSPIN signals
+    DspinSignals<cmd_width>*** signal_dspin_v_cmd_inc =
+        alloc_elems<DspinSignals<cmd_width> >("signal_dspin_v_cmd_inc", xmax, ymax-1, 2);
+    DspinSignals<cmd_width>*** signal_dspin_v_cmd_dec =
+        alloc_elems<DspinSignals<cmd_width> >("signal_dspin_v_cmd_dec", xmax, ymax-1, 2);
+    DspinSignals<rsp_width>*** signal_dspin_v_rsp_inc =
+        alloc_elems<DspinSignals<rsp_width> >("signal_dspin_v_rsp_inc", xmax, ymax-1, 2);
+    DspinSignals<rsp_width>*** signal_dspin_v_rsp_dec =
+        alloc_elems<DspinSignals<rsp_width> >("signal_dspin_v_rsp_dec", xmax, ymax-1, 2);
+
+    // Mesh boundaries DSPIN signals
+    DspinSignals<cmd_width>**** signal_dspin_false_cmd_in =
+        alloc_elems<DspinSignals<cmd_width> >("signal_dspin_false_cmd_in", xmax, ymax, 2, 4);
+    DspinSignals<cmd_width>**** signal_dspin_false_cmd_out =
+        alloc_elems<DspinSignals<cmd_width> >("signal_dspin_false_cmd_out", xmax, ymax, 2, 4);
+    DspinSignals<rsp_width>**** signal_dspin_false_rsp_in =
+        alloc_elems<DspinSignals<rsp_width> >("signal_dspin_false_rsp_in", xmax, ymax, 2, 4);
+    DspinSignals<rsp_width>**** signal_dspin_false_rsp_out =
+        alloc_elems<DspinSignals<rsp_width> >("signal_dspin_false_rsp_out", xmax, ymax, 2, 4);
+
+
+    ////////////////////////////
+    //      Components
+    ////////////////////////////
+
+#if USE_ALMOS
+    soclib::common::Loader loader("bootloader.bin",
+				  "arch-info.bin@"TO_STR(BOOT_INFO_BLOCK)":D",
+				  "kernel-soclib.bin@"TO_STR(KERNEL_BIN_IMG)":D");
+#else
+    soclib::common::Loader loader(soft_name);
+#endif
+
+    typedef soclib::common::GdbServer<soclib::common::Mips32ElIss> proc_iss;
+    proc_iss::set_loader(loader);
+
+    TsarV4ClusterRing<vci_param, proc_iss, cmd_width, rsp_width>*	clusters[xmax][ymax];
+
+#if USE_OPENMP
+
+#pragma omp parallel
+{
+#pragma omp for
+    for( size_t i = 0 ; i  < (xmax * ymax); i++)
+    {
+        size_t x = i / ymax;
+        size_t y = i % ymax;
+
+#pragma omp critical
+	std::ostringstream sc;
+	sc << "cluster_" << x << "_" << y;
+	clusters[x][y] = new TsarV4ClusterRing<vci_param, proc_iss, cmd_width, rsp_width>
+	    (sc.str().c_str(),
+             nprocs,
+	     x,
+	     y,
+	     cluster(x,y),
+	     maptabd,
+	     maptabc,
+	     maptabx,
+	     x_width,
+	     y_width,
+	     MEMC_TGTID,
+	     XICU_TGTID,
+	     FBUF_TGTID,
+	     MTTY_TGTID,
+	     BROM_TGTID,
+	     BDEV_TGTID,
+	     CDMA_TGTID,
+             memc_ways,
+             memc_sets,
+             l1_i_ways,
+             l1_i_sets,
+             l1_d_ways,
+             l1_d_sets,
+             xram_latency,
+	     (cluster(x,y) == cluster_io_index),
+	     xfb,
+	     yfb,
+	     disk_name,
+	     blk_size,
+	     loader);
+	}
+
+#else  // USE_OPENMP
+
+    for( size_t x = 0 ; x  < xmax ; x++)
+    {
+        for( size_t y = 0 ; y < ymax ; y++ )
+        {
+
+std::cout << "building cluster_" << x << "_" << y << std::endl;
+
+	    std::ostringstream sc;
+	    sc << "cluster_" << x << "_" << y;
+	    clusters[x][y] = new TsarV4ClusterRing<vci_param, proc_iss, cmd_width, rsp_width>
+	    (sc.str().c_str(),
+             nprocs,
+	     x,
+	     y,
+	     cluster(x,y),
+	     maptabd,
+	     maptabc,
+	     maptabx,
+	     x_width,
+	     y_width,
+	     MEMC_TGTID,
+	     XICU_TGTID,
+	     FBUF_TGTID,
+	     MTTY_TGTID,
+	     BROM_TGTID,
+	     BDEV_TGTID,
+	     CDMA_TGTID,
+             memc_ways,
+             memc_sets,
+             l1_i_ways,
+             l1_i_sets,
+             l1_d_ways,
+             l1_d_sets,
+             xram_latency,
+	     (cluster(x,y) == cluster_io_index),
+	     xfb,
+	     yfb,
+	     disk_name,
+	     blk_size,
+	     loader);
+
+std::cout << "cluster_" << x << "_" << y << " constructed" << std::endl;
+
+	}
+    }
+    
+#endif	// USE_OPENMP
+
+    ///////////////////////////////////////////////////////////////
+    //     Net-list 
+    ///////////////////////////////////////////////////////////////
+
+    // Clock & RESET
+    for ( size_t x = 0 ; x < (xmax) ; x++ )
+    {
+        for ( size_t y = 0 ; y < ymax ; y++ )
+        {
+            clusters[x][y]->p_clk			(signal_clk);
+            clusters[x][y]->p_resetn			(signal_resetn);
+        }
+    }
+
+    // Inter Clusters horizontal connections
+    if ( xmax > 1 )
+    {
+        for ( size_t x = 0 ; x < (xmax-1) ; x++ )
+        {
+            for ( size_t y = 0 ; y < ymax ; y++ )
+            {
+                for ( size_t k = 0 ; k < 2 ; k++ )
+                {
+		clusters[x][y]->p_cmd_out[k][EAST]      (signal_dspin_h_cmd_inc[x][y][k]);
+                clusters[x+1][y]->p_cmd_in[k][WEST]     (signal_dspin_h_cmd_inc[x][y][k]);
+                clusters[x][y]->p_cmd_in[k][EAST]       (signal_dspin_h_cmd_dec[x][y][k]);
+                clusters[x+1][y]->p_cmd_out[k][WEST]    (signal_dspin_h_cmd_dec[x][y][k]);
+                clusters[x][y]->p_rsp_out[k][EAST]      (signal_dspin_h_rsp_inc[x][y][k]);
+                clusters[x+1][y]->p_rsp_in[k][WEST]     (signal_dspin_h_rsp_inc[x][y][k]);
+                clusters[x][y]->p_rsp_in[k][EAST]       (signal_dspin_h_rsp_dec[x][y][k]);
+                clusters[x+1][y]->p_rsp_out[k][WEST]    (signal_dspin_h_rsp_dec[x][y][k]);
+                }
+            }
+        }
+    }
+    std::cout << "Horizontal connections established" << std::endl;	
+
+    // Inter Clusters vertical connections
+    if ( ymax > 1 )
+    {
+        for ( size_t y = 0 ; y < (ymax-1) ; y++ )
+        {
+            for ( size_t x = 0 ; x < xmax ; x++ )
+            {
+                for ( size_t k = 0 ; k < 2 ; k++ )
+                {
+                clusters[x][y]->p_cmd_out[k][NORTH]     (signal_dspin_v_cmd_inc[x][y][k]);
+                clusters[x][y+1]->p_cmd_in[k][SOUTH]    (signal_dspin_v_cmd_inc[x][y][k]);
+                clusters[x][y]->p_cmd_in[k][NORTH]      (signal_dspin_v_cmd_dec[x][y][k]);
+                clusters[x][y+1]->p_cmd_out[k][SOUTH]   (signal_dspin_v_cmd_dec[x][y][k]);
+                clusters[x][y]->p_rsp_out[k][NORTH]     (signal_dspin_v_rsp_inc[x][y][k]);
+                clusters[x][y+1]->p_rsp_in[k][SOUTH]    (signal_dspin_v_rsp_inc[x][y][k]);
+                clusters[x][y]->p_rsp_in[k][NORTH]      (signal_dspin_v_rsp_dec[x][y][k]);
+                clusters[x][y+1]->p_rsp_out[k][SOUTH]   (signal_dspin_v_rsp_dec[x][y][k]);
+                }
+            }
+        }
+    }
+    std::cout << "Vertical connections established" << std::endl;
+
+    // East & West boundary cluster connections
+    for ( size_t y = 0 ; y < ymax ; y++ )
+    {
+        for ( size_t k = 0 ; k < 2 ; k++ )
+        {
+	    clusters[0][y]->p_cmd_in[k][WEST]       	(signal_dspin_false_cmd_in[0][y][k][WEST]);
+	    clusters[0][y]->p_cmd_out[k][WEST]      	(signal_dspin_false_cmd_out[0][y][k][WEST]);
+	    clusters[0][y]->p_rsp_in[k][WEST]       	(signal_dspin_false_rsp_in[0][y][k][WEST]);
+	    clusters[0][y]->p_rsp_out[k][WEST]      	(signal_dspin_false_rsp_out[0][y][k][WEST]);
+	  
+	    clusters[xmax-1][y]->p_cmd_in[k][EAST]  	(signal_dspin_false_cmd_in[xmax-1][y][k][EAST]);
+	    clusters[xmax-1][y]->p_cmd_out[k][EAST] 	(signal_dspin_false_cmd_out[xmax-1][y][k][EAST]);
+	    clusters[xmax-1][y]->p_rsp_in[k][EAST]  	(signal_dspin_false_rsp_in[xmax-1][y][k][EAST]);
+	    clusters[xmax-1][y]->p_rsp_out[k][EAST] 	(signal_dspin_false_rsp_out[xmax-1][y][k][EAST]);
+	}
+    }
+    
+    // North & South boundary clusters connections
+    for ( size_t x = 0 ; x < xmax ; x++ )
+    {
+        for ( size_t k = 0 ; k < 2 ; k++ )
+        {
+	    clusters[x][0]->p_cmd_in[k][SOUTH]      	(signal_dspin_false_cmd_in[x][0][k][SOUTH]);
+	    clusters[x][0]->p_cmd_out[k][SOUTH]     	(signal_dspin_false_cmd_out[x][0][k][SOUTH]);
+	    clusters[x][0]->p_rsp_in[k][SOUTH]      	(signal_dspin_false_rsp_in[x][0][k][SOUTH]);
+	    clusters[x][0]->p_rsp_out[k][SOUTH]     	(signal_dspin_false_rsp_out[x][0][k][SOUTH]);
+	    
+	    clusters[x][ymax-1]->p_cmd_in[k][NORTH] 	(signal_dspin_false_cmd_in[x][ymax-1][k][NORTH]);
+	    clusters[x][ymax-1]->p_cmd_out[k][NORTH]	(signal_dspin_false_cmd_out[x][ymax-1][k][NORTH]);
+	    clusters[x][ymax-1]->p_rsp_in[k][NORTH] 	(signal_dspin_false_rsp_in[x][ymax-1][k][NORTH]);
+	    clusters[x][ymax-1]->p_rsp_out[k][NORTH]	(signal_dspin_false_rsp_out[x][ymax-1][k][NORTH]);
+	}
+    }
+      
+
+    ////////////////////////////////////////////////////////
+    //   Simulation
+    ///////////////////////////////////////////////////////
+
+    sc_start(sc_core::sc_time(0, SC_NS));
+    signal_resetn = false;
+
+    // network boundaries signals
+    for(size_t x=0; x<xmax ; x++)
+    {
+        for(size_t y=0 ; y<ymax ; y++)
+        {
+            for (size_t k=0; k<2; k++)
+            {
+                for(size_t a=0; a<4; a++)
+                {
+		        signal_dspin_false_cmd_in[x][y][k][a].write = false;
+		        signal_dspin_false_cmd_in[x][y][k][a].read = true;
+                        signal_dspin_false_cmd_out[x][y][k][a].write = false;
+                        signal_dspin_false_cmd_out[x][y][k][a].read = true;
+
+                        signal_dspin_false_rsp_in[x][y][k][a].write = false;
+                        signal_dspin_false_rsp_in[x][y][k][a].read = true;
+                        signal_dspin_false_rsp_out[x][y][k][a].write = false;
+                        signal_dspin_false_rsp_out[x][y][k][a].read = true;
+		}
+            }
+        }
+    }
+
+    sc_start(sc_core::sc_time(1, SC_NS));
+    signal_resetn = true;
+
+    for ( size_t n=0 ; n<ncycles ; n++)
+    {
+        sc_start(sc_core::sc_time(1, SC_NS));
+        if ( trace_ok && (n > from_cycle) )
+        {
+            std::cout << "****************** cycle " << std::dec << n ;
+            std::cout << " ***********************************" << std::endl;
+
+            clusters[0][0]->proc[0]->print_trace();
+            clusters[0][0]->bdev->print_trace();
+            std::cout << std::endl;
+            print_vci_signal("proc_0_0_0_ini_d", clusters[0][0]->signal_vci_ini_d_proc[0]);
+            print_vci_signal("bdev_tgt", clusters[0][0]->signal_vci_tgt_d_bdev);
+            print_vci_signal("bdev_ini", clusters[0][0]->signal_vci_ini_d_bdev);
+            print_vci_signal("memc_0_0_tgt_d", clusters[0][0]->signal_vci_tgt_d_memc);
+            if ( clusters[0][0]->signal_irq_bdev.read() != 0) std::cout << " IRQ_BDEV" << std::endl;
+            if ( clusters[0][0]->signal_proc_it[0].read() != 0) std::cout << " IRQ_PROC" << std::endl;
+
+/*
+            clusters[0][0]->memc->print_trace();
+
+
+            print_vci_signal("memc_0_0_ini_c", clusters[0][0]->signal_vci_ini_c_memc);
+
+            print_vci_signal("proc_0_0_0_tgt_c", clusters[0][0]->signal_vci_tgt_c_proc[0]);
+            print_vci_signal("proc_0_0_1_tgt_c", clusters[0][0]->signal_vci_tgt_c_proc[1]);
+            print_vci_signal("proc_1_0_0_tgt_c", clusters[1][0]->signal_vci_tgt_c_proc[0]);
+            print_vci_signal("proc_1_0_1_tgt_c", clusters[1][0]->signal_vci_tgt_c_proc[1]);
+
+            print_vci_signal("memc_0_0_tgt_c", clusters[0][0]->signal_vci_tgt_c_memc);
+
+            print_vci_signal("proc_0_0_0_ini_d", clusters[0][0]->signal_vci_ini_d_proc[0]);
+            print_vci_signal("proc_0_0_1_ini_d", clusters[0][0]->signal_vci_ini_d_proc[1]);
+            print_vci_signal("proc_1_0_0_ini_d", clusters[1][0]->signal_vci_ini_d_proc[0]);
+            print_vci_signal("proc_1_0_1_ini_d", clusters[1][0]->signal_vci_ini_d_proc[1]);
+            print_vci_signal("memc_1_0_tgt_d", clusters[1][0]->signal_vci_tgt_d_memc);
+            print_vci_signal("bdev_tgt", clusters[1][0]->signal_vci_tgt_d_bdev);
+            print_vci_signal("bdev_ini", clusters[1][0]->signal_vci_ini_d_bdev);
+
+            if ( clusters[0][0]->signal_irq_mdma[0].read() != 0) std::cout << " IRQ_DMA_0_0" << std::endl;
+            if ( clusters[0][0]->signal_irq_mdma[1].read() != 0) std::cout << " IRQ_DMA_0_1" << std::endl;
+            if ( clusters[1][0]->signal_irq_mdma[0].read() != 0) std::cout << " IRQ_DMA_1_0" << std::endl;
+            if ( clusters[1][0]->signal_irq_mdma[1].read() != 0) std::cout << " IRQ_DMA_1_1" << std::endl;
+*/
+        }
+    }
+    return EXIT_SUCCESS;
+}
+
+int sc_main (int argc, char *argv[])
+{
+	try {
+		return _main(argc, argv);
+	} catch (std::exception &e) {
+		std::cout << e.what() << std::endl;
+	} catch (...) {
+		std::cout << "Unknown exception occured" << std::endl;
+		throw;
+	}
+	return 1;
+}
Index: branches/v4/platforms/tsarv4_generic_ring/top.desc
===================================================================
--- branches/v4/platforms/tsarv4_generic_ring/top.desc	(revision 371)
+++ branches/v4/platforms/tsarv4_generic_ring/top.desc	(revision 371)
@@ -0,0 +1,22 @@
+
+# -*- python -*-
+
+todo = Platform('caba', 'top.cpp',
+	uses = [
+            Uses('caba:tsarv4_cluster_ring', iss_t = 'common:gdb_iss', 
+                                              gdb_iss_t = 'common:mips32el', 
+                                              cmd_width = 40, rsp_width = 33),
+	    Uses('common:elf_file_loader'),
+            Uses('common:plain_file_loader'),
+	],
+	cell_size = 4,
+	plen_size = 8,
+	addr_size = 32,
+	rerror_size = 2,
+	clen_size = 1,
+	rflag_size = 1,
+	srcid_size = 14,
+	pktid_size = 4,
+	trdid_size = 4,
+	wrplen_size = 1,
+)
Index: branches/v4/platforms/tsarv4_generic_ring/tsarv4_cluster_ring/caba/metadata/tsarv4_cluster_ring.sd
===================================================================
--- branches/v4/platforms/tsarv4_generic_ring/tsarv4_cluster_ring/caba/metadata/tsarv4_cluster_ring.sd	(revision 371)
+++ branches/v4/platforms/tsarv4_generic_ring/tsarv4_cluster_ring/caba/metadata/tsarv4_cluster_ring.sd	(revision 371)
@@ -0,0 +1,68 @@
+
+# -*- python -*-
+
+Module('caba:tsarv4_cluster_ring',
+	classname = 'soclib::caba::TsarV4ClusterRing',
+	tmpl_parameters = [
+		parameter.Module('vci_param', default = 'caba:vci_param'),
+		parameter.Module('iss_t'),
+		parameter.Int('cmd_width'),
+		parameter.Int('rsp_width'),
+		],
+	header_files = [ '../source/include/tsarv4_cluster_ring.h', ],
+	implementation_files = [ '../source/src/tsarv4_cluster_ring.cpp', ],
+	uses = [
+		Uses('caba:base_module'),
+		Uses('common:mapping_table'),
+		Uses('common:iss2'),
+                Uses('caba:vci_cc_xcache_wrapper_v4', iss_t = 'common:gdb_iss', gdb_iss_t = 'common:mips32el'),
+                Uses('caba:vci_mem_cache_v4'),
+            	Uses('caba:vci_simple_ram'),
+            	Uses('caba:vci_xicu'),
+            	Uses('caba:virtual_dspin_router', flit_width = parameter.Reference('cmd_width')),
+            	Uses('caba:virtual_dspin_router', flit_width = parameter.Reference('rsp_width')),
+            	Uses('caba:vci_local_ring_fast', ring_cmd_data_size = parameter.Reference('cmd_width'), 
+                                                 ring_rsp_data_size = parameter.Reference('rsp_width')),
+		Uses('caba:vci_multi_tty'),
+		Uses('caba:vci_framebuffer'),
+		Uses('caba:vci_block_device_tsar_v4'),
+		Uses('caba:vci_multi_dma'),
+		Uses('common:elf_file_loader'),
+		],
+        instance_parameters = [
+                parameter.Int('n_x'),
+                parameter.Int('n_y'),
+		parameter.Int('n_cluster'),
+		parameter.Module('mtd', 'common:mapping_table'),
+                parameter.Module('mtc', 'common:mapping_table'),
+		parameter.Module('mtx', 'common:mapping_table'),
+		parameter.Int('x_width'),
+		parameter.Int('y_width'),
+		parameter.Int('memc_tgtid'),
+		parameter.Int('xicu_tgtid'),
+		parameter.Int('fbuf_tgtid'),
+		parameter.Int('mtty_tgtid'),
+		parameter.Int('brom_tgtid'),
+		parameter.Int('bdev_tgtid'),
+		parameter.Int('cdma_tgtid'),
+		parameter.Int('memc_ways'),
+		parameter.Int('memc_sets'),
+		parameter.Int('l1_i_ways'),
+		parameter.Int('l1_i_sets'),
+		parameter.Int('l1_d_ways'),
+		parameter.Int('l1_d_sets'),
+                parameter.Int('xram_latency'),
+		parameter.Bool('io'),
+                ],
+
+	ports = [
+		Port('caba:bit_in', 'p_resetn', auto = 'resetn'),
+		Port('caba:clock_in', 'p_clk', auto = 'clock'),
+		Port('caba:dspin_output', 'p_cmd_out', [2, 4], dspin_data_size = parameter.Reference('cmd_width')),
+		Port('caba:dspin_input', 'p_cmd_in', [2, 4], dspin_data_size = parameter.Reference('cmd_width')),
+		Port('caba:dspin_output', 'p_rsp_out', [2, 4], dspin_data_size = parameter.Reference('rsp_width')), 
+                Port('caba:dspin_input', 'p_rsp_in', [2, 4], dspin_data_size = parameter.Reference('rsp_width')),
+		],
+)
+
+
Index: branches/v4/platforms/tsarv4_generic_ring/tsarv4_cluster_ring/caba/source/include/tsarv4_cluster_ring.h
===================================================================
--- branches/v4/platforms/tsarv4_generic_ring/tsarv4_cluster_ring/caba/source/include/tsarv4_cluster_ring.h	(revision 371)
+++ branches/v4/platforms/tsarv4_generic_ring/tsarv4_cluster_ring/caba/source/include/tsarv4_cluster_ring.h	(revision 371)
@@ -0,0 +1,158 @@
+//////////////////////////////////////////////////////////////////////////////
+// File: tsarv4_cluster_ring.h  
+// Author: Alain Greiner 
+// Copyright: UPMC/LIP6
+// Date : march 2011
+// This program is released under the GNU public license
+//////////////////////////////////////////////////////////////////////////////
+// This file define a TSAR cluster architecture without virtual memory,
+// - It uses virtual_dspin as distributed global interconnect 
+// - It uses vci_local_ring_fast as local interconnect 
+// - It uses the vci_cc_xcache_wrapper_v4
+// - It uses the vci_mem_cache_v4
+// - It contains a private RAM a variable latency to emulate the L3 cache
+// - It can contains 1, 2 or 4 processors
+// - Each processor has a private local TTY terminal (vci_multi_tty)
+// - Each processor has a private dma channel (vci_multi_dma)
+// - It uses the vci_xicu interrupt controller
+// - The nprocs tty irq are connected to IRQ_IN[0]...IRQ_IN[3]
+// - The nprocs dma irq are connected to IRQ_IN[4]...IRQ_IN[7]
+// - The peripherals BDEV, FBUF, and the boot BROM are in the cluster 
+//   containing address 0xBFC00000, and the bdev_irq is connected to IRQ_IN[8]
+////////////////////////////////////////////////////////////////////////////////// 
+
+#ifndef SOCLIB_CABA_TSAR_CLUSTER_V4_RING_H
+#define SOCLIB_CABA_TSAR_CLUSTER_V4_RING_H
+
+#include <systemc>
+#include <sys/time.h>
+#include <iostream>
+#include <sstream>
+#include <cstdlib>
+#include <cstdarg>
+
+#include "gdbserver.h"
+#include "mapping_table.h"
+#include "mips32.h"
+#include "vci_mem_cache_v4.h"
+#include "vci_cc_xcache_wrapper_v4.h"
+#include "vci_simple_ram.h"
+#include "vci_xicu.h"
+#include "vci_local_ring_fast.h"
+#include "virtual_dspin_router.h"
+#include "vci_multi_tty.h"
+#include "vci_block_device_tsar_v4.h"
+#include "vci_framebuffer.h"
+#include "vci_multi_dma.h"
+
+namespace soclib {
+namespace caba	{
+
+///////////////////////////////////////////////////////////////////////////
+template<typename vci_param, typename iss_t, int cmd_width, int rsp_width>
+class TsarV4ClusterRing 
+///////////////////////////////////////////////////////////////////////////
+    : public soclib::caba::BaseModule
+{
+
+  public:
+
+	// Ports
+    	sc_in<bool>                             		p_clk;
+    	sc_in<bool>                             		p_resetn;
+	soclib::caba::DspinOutput<cmd_width>   			**p_cmd_out;
+	soclib::caba::DspinInput<cmd_width>    			**p_cmd_in;
+        soclib::caba::DspinOutput<rsp_width>                   	**p_rsp_out;
+        soclib::caba::DspinInput<rsp_width>                   	**p_rsp_in;
+
+        // interrupt signals
+	sc_signal<bool>     		signal_false;
+	sc_signal<bool> 		signal_proc_it[4];
+	sc_signal<bool> 		signal_irq_mdma[4];
+	sc_signal<bool>			signal_irq_mtty;
+	sc_signal<bool> 		signal_irq_bdev;
+	
+	// DSPIN signals between local ring & global interconnects
+	DspinSignals<cmd_width> 	signal_dspin_cmd_l2g_d; 
+	DspinSignals<cmd_width> 	signal_dspin_cmd_g2l_d; 
+	DspinSignals<cmd_width> 	signal_dspin_cmd_l2g_c;
+	DspinSignals<cmd_width> 	signal_dspin_cmd_g2l_c; 
+	DspinSignals<rsp_width> 	signal_dspin_rsp_l2g_d; 
+	DspinSignals<rsp_width> 	signal_dspin_rsp_g2l_d; 
+	DspinSignals<rsp_width> 	signal_dspin_rsp_l2g_c;
+	DspinSignals<rsp_width> 	signal_dspin_rsp_g2l_c;
+
+	// Direct VCI signals
+	VciSignals<vci_param> 		signal_vci_ini_d_proc[4]; 
+	VciSignals<vci_param>  		signal_vci_ini_d_bdev; 
+	VciSignals<vci_param>  		signal_vci_ini_d_mdma; 
+
+	VciSignals<vci_param>		signal_vci_tgt_d_memc;
+	VciSignals<vci_param> 		signal_vci_tgt_d_mtty;
+	VciSignals<vci_param> 		signal_vci_tgt_d_xicu;
+	VciSignals<vci_param> 		signal_vci_tgt_d_bdev;
+	VciSignals<vci_param> 		signal_vci_tgt_d_mdma;
+	VciSignals<vci_param> 		signal_vci_tgt_d_brom;
+	VciSignals<vci_param> 		signal_vci_tgt_d_fbuf;
+
+	// Coherence VCi signals
+	VciSignals<vci_param> 		signal_vci_ini_c_proc[4];
+	VciSignals<vci_param> 		signal_vci_tgt_c_proc[4];
+	VciSignals<vci_param> 		signal_vci_ini_c_memc;
+	VciSignals<vci_param> 		signal_vci_tgt_c_memc;
+
+	// external RAM VCI signal
+	VciSignals<vci_param> 		signal_vci_xram;
+	
+        // Components
+
+        VciCcXCacheWrapperV4<vci_param, iss_t>*                 proc[4];
+        VciMemCacheV4<vci_param>*                               memc;
+        VciXicu<vci_param>*                                     xicu;
+        VciLocalRingFast<vci_param,cmd_width,rsp_width>*        ringd;
+        VciLocalRingFast<vci_param,cmd_width,rsp_width>*        ringc;
+        VirtualDspinRouter<cmd_width>*   	                cmdrouter;
+        VirtualDspinRouter<rsp_width>*	                        rsprouter;
+        VciSimpleRam<vci_param>*                 		brom;
+        VciMultiTty<vci_param>*                  		mtty;
+        VciFrameBuffer<vci_param>*               		fbuf;
+        VciBlockDeviceTsarV4<vci_param>*         		bdev;
+        VciMultiDma<vci_param>*                 		mdma;
+        VciSimpleRam<vci_param>*				xram;
+
+	TsarV4ClusterRing(	sc_module_name  insname,
+                        size_t		nprocs,					// number of processors 
+			size_t		n_x,					// x coordinate
+			size_t		n_y,					// y coordinate
+			size_t		n_cluster,				// y + ymax*x
+			const 		soclib::common::MappingTable &mtd,	// direct mapping table
+			const		soclib::common::MappingTable &mtc,	// coherence mapping table
+			const		soclib::common::MappingTable &mtx,	// xram mapping table
+			size_t		x_width,				// x field number of bits
+			size_t		y_width,				// y field number of bits
+                        size_t		tgtid_memc,
+                        size_t		tgtid_xicu,
+                        size_t		tgtid_fbuf,
+                        size_t		tgtid_mtty,
+                        size_t		tgtid_brom,
+                        size_t		tgtid_bdev,
+                        size_t		tgtid_mdma,
+                        size_t		memc_ways,				// number of ways for MEMC
+                        size_t		memc_sets,				// number of sets for MEMC
+                        size_t		l1_i_ways,				// number of ways for L1 ICACHE
+                        size_t		l1_i_sets,				// number of sets for L1 ICACHE
+                        size_t		l1_d_ways,				// number of ways for L1 DCACHE
+                        size_t		l1_d_sets,				// number of sets for L1 DCACHE
+                        size_t		xram_latency,				// external ram latency
+			bool		io,					// I/O cluster if true
+                        size_t          xfb,					// frame buffer pixels
+                        size_t          yfb,					// frame buffer lines
+                        char*           disk_name,				// virtual disk name for BDEV
+                        size_t          block_size,				// block size for BDEV
+                        Loader          loader);				// loader for BROM
+
+	~TsarV4ClusterRing();
+};
+}}
+
+#endif
Index: branches/v4/platforms/tsarv4_generic_ring/tsarv4_cluster_ring/caba/source/src/tsarv4_cluster_ring.cpp
===================================================================
--- branches/v4/platforms/tsarv4_generic_ring/tsarv4_cluster_ring/caba/source/src/tsarv4_cluster_ring.cpp	(revision 371)
+++ branches/v4/platforms/tsarv4_generic_ring/tsarv4_cluster_ring/caba/source/src/tsarv4_cluster_ring.cpp	(revision 371)
@@ -0,0 +1,429 @@
+#include "../include/tsarv4_cluster_ring.h"
+
+namespace soclib {
+namespace caba  {
+
+//////////////////////////////////////////////////////////////////////////
+//                 Constructor
+//////////////////////////////////////////////////////////////////////////
+template<typename vci_param, typename iss_t, int cmd_width, int rsp_width>
+TsarV4ClusterRing<vci_param, iss_t, cmd_width, rsp_width>::TsarV4ClusterRing(
+                        sc_module_name  insname,
+                        size_t          nprocs,
+                        size_t          x_id,
+                        size_t          y_id,
+                        size_t          cluster_id,
+                        const   	soclib::common::MappingTable &mtd,
+                        const   	soclib::common::MappingTable &mtc, 
+                        const   	soclib::common::MappingTable &mtx, 
+                        size_t          x_width,
+                        size_t          y_width,
+                        size_t		tgtid_memc,
+                        size_t		tgtid_xicu,
+                        size_t		tgtid_fbuf,
+                        size_t		tgtid_mtty,
+                        size_t		tgtid_brom,
+                        size_t		tgtid_bdev,
+                        size_t		tgtid_mdma,
+                        size_t		memc_ways,
+                        size_t		memc_sets,
+                        size_t		l1_i_ways,
+                        size_t		l1_i_sets,
+                        size_t		l1_d_ways,
+                        size_t		l1_d_sets,
+                        size_t		xram_latency,
+                        bool            io,
+                        size_t		xfb,
+                        size_t		yfb,
+                        char*		disk_name,
+                        size_t		block_size,
+                        Loader		loader)
+      : soclib::caba::BaseModule(insname),
+        p_clk("clk"),
+        p_resetn("resetn"),
+
+        signal_dspin_cmd_l2g_d("signal_dspin_cmd_l2g_d"),
+        signal_dspin_cmd_g2l_d("signal_dspin_cmd_g2l_d"),
+        signal_dspin_cmd_l2g_c("signal_dspin_cmd_l2g_c"),
+        signal_dspin_cmd_g2l_c("signal_dspin_cmd_g2l_c"),
+        signal_dspin_rsp_l2g_d("signal_dspin_rsp_l2g_d"),
+        signal_dspin_rsp_g2l_d("signal_dspin_rsp_g2l_d"),
+        signal_dspin_rsp_l2g_c("signal_dspin_rsp_l2g_c"),
+        signal_dspin_rsp_g2l_c("signal_dspin_rsp_g2l_c"),
+
+	signal_vci_ini_d_bdev("signal_vci_ini_d_bdev"),
+	signal_vci_ini_d_mdma("signal_vci_ini_d_mdma"),
+
+        signal_vci_tgt_d_memc("signal_vci_tgt_d_memc"),
+        signal_vci_tgt_d_mtty("signal_vci_tgt_d_mtty"),
+        signal_vci_tgt_d_xicu("signal_vci_tgt_d_xicu"),
+        signal_vci_tgt_d_bdev("signal_vci_tgt_d_bdev"),
+        signal_vci_tgt_d_mdma("signal_vci_tgt_d_mdma"),
+        signal_vci_tgt_d_brom("signal_vci_tgt_d_brom"),
+        signal_vci_tgt_d_fbuf("signal_vci_tgt_d_fbuf"),
+
+        signal_vci_ini_c_memc("signal_vci_ini_c_memc"), 
+        signal_vci_tgt_c_memc("signal_vci_tgt_c_memc"),
+
+        signal_vci_xram("signal_vci_xram")
+
+{
+        // Vectors of ports definition
+
+        p_cmd_in        = alloc_elems<DspinInput<cmd_width> >("p_cmd_in", 2, 4);
+        p_cmd_out       = alloc_elems<DspinOutput<cmd_width> >("p_cmd_out", 2, 4);
+        p_rsp_in        = alloc_elems<DspinInput<rsp_width> >("p_rsp_in", 2, 4);
+        p_rsp_out       = alloc_elems<DspinOutput<rsp_width> >("p_rsp_out", 2, 4);
+
+        // Components definition 
+
+        // on direct network : local srcid[proc] in [0...nprocs-1]
+        // on direct network : local srcid[mdma] = nprocs
+        // on direct network : local srcid[bdev] = nprocs + 1
+
+        // on coherence network : local srcid[proc] in [0...nprocs-1]
+	// on coherence network : local srcid[memc] = nprocs
+
+std::cout << "  - building proc_" << x_id << "_" << y_id << "-*" << std::endl;
+
+        for ( size_t p=0 ; p<nprocs ; p++ )
+        { 
+            std::ostringstream sproc;
+            sproc << "proc_" << x_id << "_" << y_id << "_" << p;
+            proc[p] = new VciCcXCacheWrapperV4<vci_param, iss_t>(
+                sproc.str().c_str(),
+                cluster_id*nprocs + p,
+                mtd, mtc,
+                IntTab(cluster_id,p),    	// SRCID_D
+                IntTab(cluster_id,p),    	// SRCID_C
+                IntTab(cluster_id,p),    	// TGTID_C
+		1,1,
+                l1_i_ways,l1_i_sets,16,  	// ICACHE size
+                l1_d_ways,l1_d_sets,16,      	// DCACHE size
+                16,				// WBUF width
+                1				// WBUF depth
+                );
+        }
+
+std::cout << "  - building memc_" << x_id << "_" << y_id << std::endl;
+
+        std::ostringstream smemc;
+        smemc << "memc_" << x_id << "_" << y_id;
+        memc = new VciMemCacheV4<vci_param>(
+                   smemc.str().c_str(),
+                   mtd, mtc, mtx,
+                   IntTab(cluster_id),           	// SRCID_X
+                   IntTab(cluster_id, nprocs),   	// SRCID_C
+                   IntTab(cluster_id, tgtid_memc),	// TGTID_D
+                   IntTab(cluster_id, nprocs),   	// TGTID_C
+                   memc_ways, memc_sets, 16,	 	// CACHE SIZE
+                   4096,     			 	// HEAP SIZE
+                   8,					// TRANSACTION TABLE DEPTH
+                   8);					// UPDATE TABLE DEPTH
+
+        
+std::cout << "  - building xram_" << x_id << "_" << y_id << std::endl;
+
+        std::ostringstream sxram;
+        sxram << "xram_" << x_id << "_" << y_id;
+        xram = new VciSimpleRam<vci_param>(
+                   sxram.str().c_str(),
+                   IntTab(cluster_id),
+                   mtx,
+                   loader,
+                   xram_latency);
+
+std::cout << "  - building xicu_" << x_id << "_" << y_id << std::endl;
+
+        size_t  nhwi = 8;				// always 8 (or 9) ports, even if 
+        if( io == true ) nhwi = 9;			// there if less than 4 processors
+        std::ostringstream sicu;
+        sicu << "xicu_" << x_id << "_" << y_id;
+        xicu = new VciXicu<vci_param>(
+                  sicu.str().c_str(),
+                  mtd,				  	// mapping table
+                  IntTab(cluster_id, tgtid_xicu),  	// TGTID_D
+                  0,					// number of timer IRQs
+                  nhwi,                          	// number of hard IRQs
+                  0,					// number of soft IRQs
+                  nprocs);				// number of output IRQs
+
+std::cout << "  - building tty_" << x_id << "_" << y_id << std::endl;
+
+        // tty
+        std::ostringstream stty;
+        stty << "tty_" << x_id << "_" << y_id;
+        mtty = new VciMultiTty<vci_param>(
+                   stty.str().c_str(),
+                   IntTab(cluster_id, tgtid_mtty),
+                   mtd, stty.str().c_str(), NULL);
+        
+std::cout << "  - building dma_" << x_id << "_" << y_id << std::endl;
+
+        // dma
+        std::ostringstream sdma;
+        sdma << "dma_" << x_id << "_" << y_id;
+        mdma = new VciMultiDma<vci_param>(
+                   sdma.str().c_str(),
+                   mtd,
+                   IntTab(cluster_id, nprocs),		// SRCID
+                   IntTab(cluster_id, tgtid_mdma),	// TGTID
+                   64,					// burst size
+                   nprocs);				// number of IRQs
+
+std::cout << "  - building dring_" << x_id << "_" << y_id << std::endl;
+
+        // direct ring
+        size_t nb_direct_initiators      = nprocs + 1;
+        size_t nb_direct_targets         = 4;
+        if( io == true )
+        {
+            nb_direct_initiators         = nprocs + 2;
+            nb_direct_targets            = 7;
+	}
+        std::ostringstream sd;
+        sd << "ringd_" << x_id << "_" << y_id;
+        ringd = new VciLocalRingFast<vci_param,cmd_width,rsp_width>(
+                    sd.str().c_str(),
+                    mtd,
+                    IntTab(cluster_id),              	// cluster index
+                    4,                              	// wrapper fifo depth
+                    4,                              	// gateway fifo depth
+                    nb_direct_initiators,           	// number of initiators
+                    nb_direct_targets);             	// number of targets      
+        
+std::cout << "  - building cring_" << x_id << "_" << y_id << std::endl;
+
+        // coherence ring
+        std::ostringstream sc;
+        sc << "ringc_" << x_id << "_" << y_id;
+        ringc = new VciLocalRingFast<vci_param,cmd_width,rsp_width>(
+                    sc.str().c_str(),
+                    mtc,
+                    IntTab(cluster_id),                	// cluster index
+                    4,                                 	// wrapper fifo depth
+                    4,                                	// gateway fifo depth
+                    nprocs + 1,                		// number of initiators
+                    nprocs + 1);               		// number of targets
+        
+std::cout << "  - building cmdrouter_" << x_id << "_" << y_id << std::endl;
+
+        // CMD router
+        std::ostringstream scmd;
+        scmd << "cmdrouter_" << x_id << "_" << y_id;
+        cmdrouter = new VirtualDspinRouter<cmd_width>(
+                        scmd.str().c_str(),
+                        x_id,y_id,                    // coordinate in the mesh
+                        x_width, y_width,             // x & y fields width
+                        4,4);                         // input & output fifo depths
+        
+std::cout << "  - building rsprouter_" << x_id << "_" << y_id << std::endl;
+
+        // RSP router
+        std::ostringstream srsp;
+        srsp << "rsprouter_" << x_id << "_" << y_id;
+        rsprouter = new VirtualDspinRouter<rsp_width>(
+                        srsp.str().c_str(),
+                        x_id,y_id,                    // coordinates in mesh
+                        x_width, y_width,             // x & y fields width
+                        4,4);                         // input & output fifo depths
+        
+        // IO cluster components
+        if ( io == true )
+	{
+            brom = new VciSimpleRam<vci_param>(
+                       "brom",
+                       IntTab(cluster_id, tgtid_brom),
+                       mtd,
+                       loader);
+
+            fbuf = new VciFrameBuffer<vci_param>(
+                       "fbuf",
+                       IntTab(cluster_id, tgtid_fbuf),
+                       mtd,
+		       xfb, yfb); 
+
+            bdev = new VciBlockDeviceTsarV4<vci_param>(
+                       "bdev",
+                       mtd,
+                       IntTab(cluster_id, nprocs+1),
+                       IntTab(cluster_id, tgtid_bdev),
+                       disk_name,
+                       block_size);
+	}
+
+std::cout << "  - all components constructed" << std::endl;
+
+        ////////////////////////////////////
+        // Connections are defined here
+        ////////////////////////////////////
+
+        // CMDROUTER and RSPROUTER
+        cmdrouter->p_clk                	(this->p_clk);
+        cmdrouter->p_resetn             	(this->p_resetn);
+        rsprouter->p_clk                	(this->p_clk);
+        rsprouter->p_resetn             	(this->p_resetn);
+        for(int x = 0; x < 2; x++)
+        {
+          for(int y = 0; y < 4; y++)
+          {
+            cmdrouter->p_out[x][y]              (this->p_cmd_out[x][y]);
+            cmdrouter->p_in[x][y]               (this->p_cmd_in[x][y]);
+            rsprouter->p_out[x][y]              (this->p_rsp_out[x][y]);
+            rsprouter->p_in[x][y]               (this->p_rsp_in[x][y]);
+          }
+        }
+        
+        cmdrouter->p_out[0][4]  		(signal_dspin_cmd_g2l_d);
+        cmdrouter->p_out[1][4]  		(signal_dspin_cmd_g2l_c);
+        cmdrouter->p_in[0][4]   		(signal_dspin_cmd_l2g_d);
+        cmdrouter->p_in[1][4]   		(signal_dspin_cmd_l2g_c);
+
+        rsprouter->p_out[0][4]  		(signal_dspin_rsp_g2l_d);
+        rsprouter->p_out[1][4]  		(signal_dspin_rsp_g2l_c);
+        rsprouter->p_in[0][4]   		(signal_dspin_rsp_l2g_d);
+        rsprouter->p_in[1][4]   		(signal_dspin_rsp_l2g_c);
+
+        // RINGD
+        ringd->p_clk                  		(this->p_clk);
+        ringd->p_resetn                 	(this->p_resetn);
+        ringd->p_gate_cmd_out           	(signal_dspin_cmd_l2g_d);
+        ringd->p_gate_cmd_in            	(signal_dspin_cmd_g2l_d);
+        ringd->p_gate_rsp_out           	(signal_dspin_rsp_l2g_d);
+        ringd->p_gate_rsp_in            	(signal_dspin_rsp_g2l_d);
+          
+        ringd->p_to_target[tgtid_memc]  	(signal_vci_tgt_d_memc);
+        ringd->p_to_target[tgtid_xicu]  	(signal_vci_tgt_d_xicu);
+        ringd->p_to_target[tgtid_mtty]  	(signal_vci_tgt_d_mtty);
+        ringd->p_to_target[tgtid_mdma]  	(signal_vci_tgt_d_mdma);
+          
+        ringd->p_to_initiator[nprocs]  		(signal_vci_ini_d_mdma);
+        for ( size_t p=0 ; p<nprocs ; p++)
+        {
+            ringd->p_to_initiator[p]		(signal_vci_ini_d_proc[p]);
+        }
+
+	if ( io == true )
+	{
+            ringd->p_to_target[tgtid_brom]  	(signal_vci_tgt_d_brom);
+            ringd->p_to_target[tgtid_bdev]  	(signal_vci_tgt_d_bdev);
+            ringd->p_to_target[tgtid_fbuf]  	(signal_vci_tgt_d_fbuf);
+            
+            ringd->p_to_initiator[nprocs+1]  	(signal_vci_ini_d_bdev);
+	}
+        
+        // RINGC
+        ringc->p_clk                    	(this->p_clk);
+        ringc->p_resetn                 	(this->p_resetn);
+        ringc->p_gate_cmd_out           	(signal_dspin_cmd_l2g_c);
+        ringc->p_gate_cmd_in            	(signal_dspin_cmd_g2l_c);
+        ringc->p_gate_rsp_out           	(signal_dspin_rsp_l2g_c);
+        ringc->p_gate_rsp_in            	(signal_dspin_rsp_g2l_c);
+        ringc->p_to_initiator[nprocs]  		(signal_vci_ini_c_memc);
+        ringc->p_to_target[nprocs]     		(signal_vci_tgt_c_memc);
+        for ( size_t p=0 ; p<nprocs ; p++)
+        {
+            ringc->p_to_target[p]       	(signal_vci_tgt_c_proc[p]);
+            ringc->p_to_initiator[p]    	(signal_vci_ini_c_proc[p]);
+        }
+
+        // Processors
+        for ( size_t p=0 ; p<nprocs ; p++)
+        {
+            proc[p]->p_clk              	(this->p_clk);
+            proc[p]->p_resetn           	(this->p_resetn);
+            proc[p]->p_vci_ini_rw       	(signal_vci_ini_d_proc[p]);
+            proc[p]->p_vci_ini_c        	(signal_vci_ini_c_proc[p]);
+            proc[p]->p_vci_tgt          	(signal_vci_tgt_c_proc[p]);
+            proc[p]->p_irq[0][0]           	(signal_proc_it[p]);
+            for ( size_t j = 1 ; j < 6 ; j++ )
+            {
+                proc[p]->p_irq[0][j]       	(signal_false);
+            }
+        }
+        
+        // XICU
+        xicu->p_clk                     	(this->p_clk);
+        xicu->p_resetn                  	(this->p_resetn);
+        xicu->p_vci                     	(signal_vci_tgt_d_xicu);
+        for ( size_t p=0 ; p<nprocs ; p++)
+        {
+            xicu->p_irq[p]              	(signal_proc_it[p]);
+        }
+        xicu->p_hwi[0]				(signal_irq_mtty);
+        xicu->p_hwi[1]				(signal_false);
+        xicu->p_hwi[2]				(signal_false);
+        xicu->p_hwi[3]				(signal_false);
+        for ( size_t p=0 ; p<nprocs ; p++)
+        {
+            xicu->p_hwi[p+4]			(signal_irq_mdma[p]);
+        }
+        for ( size_t x=nprocs ; x<4 ; x++)
+        {
+            xicu->p_hwi[x+4]			(signal_false);
+        }
+        if ( io == true )
+	{
+            xicu->p_hwi[8]			(signal_irq_bdev);
+	}
+
+        // MEMC
+        memc->p_clk                     	(this->p_clk);
+        memc->p_resetn                  	(this->p_resetn);
+        memc->p_vci_ixr                 	(signal_vci_xram);
+        memc->p_vci_tgt                 	(signal_vci_tgt_d_memc);
+        memc->p_vci_ini                 	(signal_vci_ini_c_memc);
+        memc->p_vci_tgt_cleanup         	(signal_vci_tgt_c_memc);
+
+        // XRAM
+        xram->p_clk                     	(this->p_clk);
+        xram->p_resetn                  	(this->p_resetn);
+        xram->p_vci                 		(signal_vci_xram);
+
+        // MTTY
+        mtty->p_clk                       	(this->p_clk);
+        mtty->p_resetn                    	(this->p_resetn);
+        mtty->p_vci                       	(signal_vci_tgt_d_mtty);
+        mtty->p_irq[0]           		(signal_irq_mtty);
+
+        // CDMA
+        mdma->p_clk                       	(this->p_clk);
+        mdma->p_resetn                    	(this->p_resetn);
+        mdma->p_vci_target                	(signal_vci_tgt_d_mdma);
+        mdma->p_vci_initiator             	(signal_vci_ini_d_mdma);
+        for (size_t p=0 ; p<nprocs ; p++)
+        {
+            mdma->p_irq[p]                       (signal_irq_mdma[p]);
+        }
+
+	// Components in IO cluster
+
+	if ( io == true )
+	{
+        	// BDEV            
+		bdev->p_clk                      (this->p_clk);
+        	bdev->p_resetn                   (this->p_resetn);
+        	bdev->p_irq                      (signal_irq_bdev);
+        	bdev->p_vci_target               (signal_vci_tgt_d_bdev);
+        	bdev->p_vci_initiator            (signal_vci_ini_d_bdev);
+
+        	// FBUF
+        	fbuf->p_clk                       (this->p_clk);
+        	fbuf->p_resetn                    (this->p_resetn);
+        	fbuf->p_vci                       (signal_vci_tgt_d_fbuf);
+
+        	// BROM
+        	brom->p_clk                       (this->p_clk);
+        	brom->p_resetn                    (this->p_resetn);
+        	brom->p_vci                       (signal_vci_tgt_d_brom);
+
+        }
+} // end constructor
+
+///////////////////////////////////////////////////////////////////////////
+//    destructor
+///////////////////////////////////////////////////////////////////////////
+template<typename vci_param, typename iss_t, int cmd_width, int rsp_width>
+TsarV4ClusterRing<vci_param, iss_t, cmd_width, rsp_width>::~TsarV4ClusterRing() {}
+
+}}
Index: branches/v4/platforms/tsarv4_generic_xbar/Makefile
===================================================================
--- branches/v4/platforms/tsarv4_generic_xbar/Makefile	(revision 371)
+++ branches/v4/platforms/tsarv4_generic_xbar/Makefile	(revision 371)
@@ -0,0 +1,8 @@
+
+simulator.x: top.cpp top.desc
+	soclib-cc -P -p top.desc -I../../modules -o simul.x
+
+clean:
+	soclib-cc -x -p top.desc -I.
+	rm -rf *.o *.x tty*
+
Index: branches/v4/platforms/tsarv4_generic_xbar/soclib.conf
===================================================================
--- branches/v4/platforms/tsarv4_generic_xbar/soclib.conf	(revision 371)
+++ branches/v4/platforms/tsarv4_generic_xbar/soclib.conf	(revision 371)
@@ -0,0 +1,25 @@
+config.lib_systemcass_openmp_mine = Library(
+	parent = config.systemc,
+	dir = "/users/outil/nbsdtsar/systemcass",
+	libdir = "%(dir)s/lib-linux",
+	cflags = config.systemc.cflags+['-fopenmp']+['-O3'],
+	#cflags = config.systemc.cflags,
+	libs = ['-ldl', '-lm', '-lpthread', '-L%(libdir)s', '-lsystemc', '-rdynamic', '-fopenmp'],
+	#libs = ['-ldl', '-lm', '-lpthread', '-L%(libdir)s', '-lsystemc', '-rdynamic'],
+)
+
+config.systemcass_openmp_mine = BuildEnv(
+	parent = config.systemc_64,
+	libraries = [ config.lib_systemcass_openmp_mine ],
+	#base = config.systemc_32,
+	repos = "/dsk/l1/misc/alain/soclib-cc/head/systemcass-mine",
+	cache_file = "/dsk/l1/misc/alain/soclib-cc/head/systemcass-mine/soclib_cc.cache",
+	toolchain = config.toolchain_64,
+	#toolchain = config.dist_toolchain,
+)
+
+#config.default = config.systemcass
+config.default = config.systemcass_openmp_mine
+
+config.default.toolchain.set("cflags", config.default.toolchain.cflags + ['-DI_WANT_ILLEGAL_VCI'])
+
Index: branches/v4/platforms/tsarv4_generic_xbar/top.cpp
===================================================================
--- branches/v4/platforms/tsarv4_generic_xbar/top.cpp	(revision 371)
+++ branches/v4/platforms/tsarv4_generic_xbar/top.cpp	(revision 371)
@@ -0,0 +1,970 @@
+/////////////////////////////////////////////////////////////////////////
+// File: tsarv4_generic_xbar.cpp
+// Author: Alain Greiner 
+// Copyright: UPMC/LIP6
+// Date : april 2011
+// This program is released under the GNU public license
+/////////////////////////////////////////////////////////////////////////
+// This file define a generic TSAR architecture without virtual memory.
+// - It uses vci_local_crossbar as local interconnect 
+// - It uses virtual_dspin as global interconnect
+// - It uses the vci_cc_xcache_wrapper_v4 
+// - It uses the vci_mem_cache_v4
+// - It uses the vci_xicu, with one vci_multi_tty, and one
+//   vci_multi_dma controlers per cluster.
+// The physical address space is 32 bits.
+// The number of clusters cannot be larger than 256.
+// The number of processors per cluster cannot be larger than 4.
+// The parameters must be power of 2.
+// - xmax   : number of clusters in a row
+// - ymax   : number of clusters in a column
+// - nprocs : number of processors per cluster
+//
+// The peripherals BDEV, FBUF, and the boot BROM
+// are in the cluster containing address 0xBFC00000.
+// - The nprocs TTY IRQs are connected to IRQ_IN[0] to IRQ_IN[3]
+// - The nprocs DMA IRQs are connected to IRQ_IN[4] to IRQ_IN[7]
+// - The IOC IRQ is connected to IRQ_IN[8]
+// 
+// General policy for 32 bits address decoding in direct space:
+// All segments base addresses are multiple of 64 Kbytes
+// Therefore the 16 address MSB bits completely define the target: 
+// The (x_width + y_width) MSB bits (left aligned) define
+// the cluster index, and the 8 LSB bits define the local index:
+// 
+//      | X_ID  | Y_ID  |---| LADR |     OFFSET          |
+//      |x_width|y_width|---|  8   |       16            |
+//
+// Half of all clusters being in the protected address space domain 
+// (addresses larger than 0x8000000), software must execute in
+// kernel mode to access memory if we want to exploit locality,
+// because some stacks and heaps will be in the protected domain.
+/////////////////////////////////////////////////////////////////////////
+
+#include <systemc>
+#include <sys/time.h>
+#include <iostream>
+#include <sstream>
+#include <cstdlib>
+#include <cstdarg>
+#include <stdint.h>
+
+#include "gdbserver.h"
+#include "mapping_table.h"
+#include "tsarv4_cluster_xbar.h"
+#include "alloc_elems.h"
+
+///////////////////////////////////////////////////
+//               Parallelisation
+///////////////////////////////////////////////////
+
+#define OMP_THREADS        	8
+
+#ifdef _OPENMP
+#include <omp.h>
+#endif
+
+
+//  cluster index (computed from x,y coordinates)
+#define cluster(x,y)	(y + ymax*x)
+
+// flit widths for the DSPIN network
+#define cmd_width	         40
+#define rsp_width	         33
+
+// VCI format
+#define cell_width	         4
+#define address_width	         32
+#define plen_width	         8
+#define error_width	         2
+#define clen_width	         1
+#define rflag_width	         1
+#define srcid_width	         14
+#define pktid_width	         4
+#define trdid_width	         4
+#define wrplen_width	         1
+
+///////////////////////////////////////////////////
+//     Parameters default values         
+///////////////////////////////////////////////////
+
+#define MESH_XMAX		2
+#define MESH_YMAX		2
+
+#define NPROCS			4
+#define XRAM_LATENCY            0
+
+#define MEMC_WAYS               16
+#define MEMC_SETS               256
+
+#define L1_IWAYS                4
+#define L1_ISETS                64
+
+#define L1_DWAYS                4
+#define L1_DSETS                64
+
+#define FBUF_X_SIZE             1024
+#define FBUF_Y_SIZE             1024
+
+#define	BDEV_SECTOR_SIZE 	1024
+#define BDEV_IMAGE_NAME	        "../../softs/soft_filter_giet/philips_image.raw"
+
+#define BOOT_SOFT_NAME	 	"../../softs/soft_filter_giet/bin.soft"
+
+/////////////////////////////////////////////////////////
+// Segments definition 
+/////////////////////////////////////////////////////////
+// There is 5 segments replicated in all clusters:
+// - seg_icu 	-> ICU  / LADR = 0xF0
+// - seg_tty 	-> MTTY / LADR = 0xF1
+// - seg_dma 	-> CDMA / LADR = 0xF2
+// - seg_stack	-> RAM  / LADR = 0x80 to 0x8F
+// - seg_heap	-> RAM  / LADR = 0x30 to 0x7F
+//
+// There is 3 specific segments in the "IO" cluster 
+// (containing address 0xBF000000)
+// - seg_reset	-> BROM / LADR = 0xC0 to 0xCF
+// - seg_fbuf	-> FBUF / LADR = 0xD0 to OxEF
+// - seg_bdev	-> BDEV / LADR = 0xF3
+//
+// There is 3 specific segments in the "kcode" cluster
+// (containing address 0x80000000)
+// - seg_kcode	-> RAM  / LADR = 0x00 to 0x0F
+// - seg_kdata	-> RAM  / LADR = 0x10 to 0x1F
+// - seg_kunc 	-> RAM  / LADR = 0x20 to 0x2F
+//
+// There is 2 specific segments in the "code" cluster
+// (containing address 0x00000000)
+// - seg_code	-> RAM  / LADR = 0x00 to Ox0F
+// - seg_data 	-> RAM  / LADR = 0x10 to 0x1F
+//
+// There is one special segment corresponding to
+// the processors in the coherence address space
+// - seg_proc	-> PROCS / LADR = 0xB0 to 0xBF
+///////////////////////////////////////////////////
+
+// specific segments in "kcode" cluster
+
+#define KCOD_BASE               0x80000000      
+#define KCOD_SIZE               0x00010000
+
+#define KDAT_BASE               0x80100000      
+#define KDAT_SIZE               0x00010000
+
+#define KUNC_BASE               0x80200000      
+#define KUNC_SIZE               0x00010000
+
+// specific segments in "code" cluster
+
+#define CODE_BASE               0x00000000      
+#define CODE_SIZE               0x00010000
+
+#define DATA_BASE               0x00100000      
+#define DATA_SIZE               0x00010000
+
+// specific segments in "IO" cluster
+
+#define BROM_BASE               0xBFC00000      
+#define BROM_SIZE               0x00010000
+
+#define FBUF_BASE               0xBFD00000      
+#define FBUF_SIZE               0x00200000
+
+#define BDEV_BASE               0xBFF30000      
+#define BDEV_SIZE               0x00000020
+
+// replicated segments
+
+#define HEAP_BASE               0x00300000      
+#define HEAP_SIZE               0x00500000
+
+#define STAK_BASE               0x00800000      
+#define STAK_SIZE               0x00100000
+
+#define XICU_BASE               0x00F00000      
+#define XICU_SIZE               0x00001000
+
+#define MTTY_BASE               0x00F10000      
+#define MTTY_SIZE               0x00000040
+
+#define CDMA_BASE               0x00F20000      
+#define CDMA_SIZE               0x00000080
+
+#define PROC_BASE               0x00B00000      
+#define PROC_SIZE               0x00000010
+
+////////////////////////////////////////////////////////////////////
+//     TGTID definition in direct space
+// For all components:  global TGTID = global SRCID = cluster_index
+////////////////////////////////////////////////////////////////////
+
+#define MEMC_TGTID               0
+#define XICU_TGTID               1
+#define MTTY_TGTID               2
+#define CDMA_TGTID               3
+#define FBUF_TGTID               4
+#define BROM_TGTID               5
+#define BDEV_TGTID               6
+
+///////////////////////////////////////////////////
+// service functions for VCI & DSIN signal trace
+//////////////////////////////////////////////////
+
+template <typename T>
+void  print_vci_signal(std::string name, T &sig) 
+{
+    if ( sig.cmdval )
+    {
+        std::cout << name << std::hex << " CMD VCI : "; 
+        if ( sig.cmd.read() == 1 ) 	std::cout << "RD ";
+        if ( sig.cmd.read() == 2 ) 	std::cout << "WR ";
+        if ( sig.cmd.read() == 3 ) 	std::cout << "LL ";
+        if ( sig.cmd.read() == 0 ) 	std::cout << "SC ";
+        std::cout  << " @ = " << sig.address 
+                   << " | wdata = " << sig.wdata  
+                   << " | srcid = " << sig.srcid 
+                   << " | trdid = " << sig.trdid 
+                   << " | eop = " << sig.eop 
+                   << " | ack = " << sig.cmdack << std::endl;
+    }
+    if ( sig.rspval )
+    {
+         std::cout << name << std::hex 
+                   << " RSP VCI : rerror = " << sig.rerror
+                   << " | rdata = " << sig.rdata 
+                   << " | rsrcid = " << sig.rsrcid 
+                   << " | rtrdid = " << sig.rtrdid 
+                   << " | reop = " << sig.reop
+                   << " | ack = " << sig.rspack << std::endl;
+    }
+}
+
+template <typename T>
+void print_dspin_signal(std::string name, T &sig)
+{
+    if ( sig.write )
+    {
+        std::cout << name << " DSPIN : data = " << std::hex << sig.data
+                  << " | ack = " << sig.read << std::endl;
+    }
+}
+
+/////////////////////////////////
+int _main(int argc, char *argv[])
+{
+    using namespace sc_core;
+    using namespace soclib::caba;
+    using namespace soclib::common;
+    
+    
+    char    soft_name[256] = BOOT_SOFT_NAME;  	// pathname to binary code
+    size_t  ncycles        = 1000000000;       	// simulated cycles
+    size_t  xmax           = MESH_XMAX;  	// number of clusters in a row
+    size_t  ymax           = MESH_YMAX;         // number of clusters in a column
+    size_t  nprocs         = NPROCS;    	// number of processors per cluster
+    size_t  xfb            = FBUF_X_SIZE;	// frameBuffer column number
+    size_t  yfb            = FBUF_Y_SIZE;      	// frameBuffer lines number
+    size_t  memc_ways      = MEMC_WAYS;
+    size_t  memc_sets      = MEMC_SETS;
+    size_t  l1_d_ways      = L1_DWAYS;
+    size_t  l1_d_sets      = L1_DSETS;
+    size_t  l1_i_ways      = L1_IWAYS;
+    size_t  l1_i_sets      = L1_ISETS;
+    char    disk_name[256] = BDEV_IMAGE_NAME;  	// pathname to the disk image
+    size_t  blk_size       = BDEV_SECTOR_SIZE;  // block size (in bytes)
+    size_t  xram_latency   = XRAM_LATENCY;	// external RAM latency
+    bool    trace_ok       = false;            	// debug activated
+    size_t  from_cycle     = 0;                	// debug start cycle
+    size_t  omp_threads    = OMP_THREADS;	// number of cores for OpenMP
+
+    ////////////// command line arguments //////////////////////
+    if (argc > 1)
+    {
+        for( int n=1 ; n<argc ; n=n+2 )
+        {
+            if( (strcmp(argv[n],"-NCYCLES") == 0) && (n+1<argc) )
+            {
+                ncycles = atoi(argv[n+1]);
+            }
+            else if( (strcmp(argv[n],"-NPROCS") == 0) && (n+1<argc) )
+            {
+                nprocs = atoi(argv[n+1]);
+                assert( ((nprocs == 1) || (nprocs == 2) || (nprocs == 4)) &&
+                        "NPROCS must be equal to 1, 2, or 4");
+            }
+            else if( (strcmp(argv[n],"-THREADS") == 0) && (n+1<argc) )
+            {
+                omp_threads = atoi(argv[n+1]);
+            }
+            else if( (strcmp(argv[n],"-XMAX") == 0) && (n+1<argc) )
+            {
+                xmax = atoi(argv[n+1]);
+                assert( ((xmax == 1) || (xmax == 2) || (xmax == 4) || (xmax == 8) || (xmax == 16)) 
+                         && "The XMAX parameter must be 2, 4, 8, or 16" );
+            }
+            
+	    else if( (strcmp(argv[n],"-YMAX") == 0) && (n+1<argc) )
+            {
+                ymax = atoi(argv[n+1]);
+                assert( ((ymax == 1) || (ymax == 2) || (ymax == 4) || (ymax == 8) || (ymax == 16)) 
+                         && "The YMAX parameter must be 2, 4, 8, or 16" );
+            }
+	    else if( (strcmp(argv[n],"-XFB") == 0) && (n+1<argc) )
+            {
+	        xfb = atoi(argv[n+1]);
+            }
+	    else if( (strcmp(argv[n],"-YFB") == 0) && (n+1<argc) )
+            {
+                yfb = atoi(argv[n+1]);
+            }
+            else if( (strcmp(argv[n],"-SOFT") == 0) && (n+1<argc) )
+            {
+                strcpy(soft_name, argv[n+1]);
+            }
+            else if( (strcmp(argv[n],"-DISK") == 0) && (n+1<argc) )
+            {
+                strcpy(disk_name, argv[n+1]);
+            }
+            else if( (strcmp(argv[n],"-TRACE") == 0) && (n+1<argc) )
+            {
+                trace_ok = true;
+                from_cycle = atoi(argv[n+1]);
+            }
+	    else if((strcmp(argv[n], "-MCWAYS") == 0) && (n+1 < argc))
+	    {
+	        memc_ways = atoi(argv[n+1]);
+	    }
+	    else if((strcmp(argv[n], "-MCSETS") == 0) && (n+1 < argc))
+	    {
+	        memc_sets = atoi(argv[n+1]);
+	    }
+	    else if((strcmp(argv[n], "-XLATENCY") == 0) && (n+1 < argc))
+	    {
+	        xram_latency = atoi(argv[n+1]);
+	    }
+            else
+            {
+                std::cout << "   Arguments on the command line are (key,value) couples." << std::endl;
+                std::cout << "   The order is not important." << std::endl;
+                std::cout << "   Accepted arguments are :" << std::endl << std::endl;
+                std::cout << "     -SOFT pathname_for_embedded_soft" << std::endl;
+                std::cout << "     -DISK pathname_for_disk_image" << std::endl;
+                std::cout << "     -NCYCLES number_of_simulated_cycles" << std::endl;
+                std::cout << "     -NPROCS number_of_processors_per_cluster" << std::endl;
+                std::cout << "     -XMAX number_of_clusters_in_a_row" << std::endl;
+                std::cout << "     -YMAX number_of_clusters_in_a_column" << std::endl;
+                std::cout << "     -TRACE debug_start_cycle" << std::endl;
+                std::cout << "     -MCWAYS memory_cache_number_of_ways" << std::endl;
+                std::cout << "     -MCSETS memory_cache_number_of_sets" << std::endl;
+                std::cout << "     -XLATENCY external_ram_latency_value" << std::endl;
+                std::cout << "     -XFB fram_buffer_number_of_pixels" << std::endl;
+                std::cout << "     -YFB fram_buffer_number_of_lines" << std::endl;
+                std::cout << "     -THREADS number_of_cores_for_OpenMP" << std::endl;
+                exit(0);
+            }
+        }
+    }
+
+    std::cout << std::endl;
+    std::cout << " - NPROCS    = " << nprocs <<  std::endl;
+    std::cout << " - NCLUSTERS = " << xmax*ymax << std::endl;
+    std::cout << std::endl;
+
+#ifdef _OPENMP
+        omp_set_dynamic(false);
+        omp_set_num_threads(omp_threads);
+        std::cout << "Built with openmp version " << _OPENMP << std::endl;
+        std::cout << "Number of threads = " << omp_threads << std::endl;
+#endif
+
+    // Define VCI parameters
+    typedef soclib::caba::VciParams<cell_width,
+                                    plen_width,
+                                    address_width,
+                                    error_width,                                   
+                                    clen_width,
+                                    rflag_width,
+                                    srcid_width,
+                                    pktid_width,
+                                    trdid_width,
+                                    wrplen_width> vci_param;
+
+    size_t	cluster_io_index;
+    size_t	cluster_code_index;
+    size_t	cluster_kcode_index;
+    size_t	x_width;
+    size_t	y_width;
+
+    if      (xmax == 1) x_width = 0;
+    else if (xmax == 2) x_width = 1;
+    else if (xmax <= 4) x_width = 2;
+    else if (xmax <= 8) x_width = 3;
+    else                x_width = 4;
+
+    if      (ymax == 1) y_width = 0;
+    else if (ymax == 2) y_width = 1;
+    else if (ymax <= 4) y_width = 2;
+    else if (ymax <= 8) y_width = 3;
+    else                y_width = 4;
+
+    cluster_io_index = 0xBF >> (8 - x_width - y_width);
+    cluster_kcode_index = 0x80 >> (8 - x_width - y_width);
+    cluster_code_index = 0;
+    
+    /////////////////////
+    //  Mapping Tables
+    /////////////////////
+
+    // direct network
+    MappingTable maptabd(address_width, 
+                         IntTab(x_width + y_width, 16 - x_width - y_width), 
+                         IntTab(x_width + y_width, srcid_width - x_width - y_width), 
+                         0x00FF0000);
+
+    for ( size_t x = 0 ; x < xmax ; x++)
+    {
+        for ( size_t y = 0 ; y < ymax ; y++)
+        {
+            sc_uint<address_width> offset  = cluster(x,y) << (address_width-x_width-y_width);
+
+            std::ostringstream 	sh;
+            sh << "d_seg_heap_" << x << "_" << y;
+            maptabd.add(Segment(sh.str(), HEAP_BASE+offset, HEAP_SIZE, IntTab(cluster(x,y),MEMC_TGTID), true));
+
+            std::ostringstream 	ss;
+            ss << "d_seg_stak_" << x << "_" << y;
+            maptabd.add(Segment(ss.str(), STAK_BASE+offset, STAK_SIZE, IntTab(cluster(x,y),MEMC_TGTID), true));
+
+            std::ostringstream 	si;
+            si << "d_seg_xicu_" << x << "_" << y;
+            maptabd.add(Segment(si.str(), XICU_BASE+offset, XICU_SIZE, IntTab(cluster(x,y),XICU_TGTID), false));
+
+            std::ostringstream 	st;
+            st << "d_seg_mtty_" << x << "_" << y;
+            maptabd.add(Segment(st.str(), MTTY_BASE+offset, MTTY_SIZE, IntTab(cluster(x,y),MTTY_TGTID), false));
+
+            std::ostringstream 	sd;
+            sd << "d_seg_cdma_" << x << "_" << y;
+            maptabd.add(Segment(sd.str(), CDMA_BASE+offset, CDMA_SIZE, IntTab(cluster(x,y),CDMA_TGTID), false));
+
+            if ( cluster(x,y) == cluster_io_index )
+            {
+	      maptabd.add(Segment("d_seg_fbuf    ", FBUF_BASE, FBUF_SIZE, IntTab(cluster(x,y),FBUF_TGTID), false));
+	      maptabd.add(Segment("d_seg_bdev    ", BDEV_BASE, BDEV_SIZE, IntTab(cluster(x,y),BDEV_TGTID), false));
+	      maptabd.add(Segment("d_seg_brom    ", BROM_BASE, BROM_SIZE, IntTab(cluster(x,y),BROM_TGTID), true));
+            }
+            if ( cluster(x,y) == cluster_code_index )
+            {
+	      maptabd.add(Segment("d_seg_code    ", CODE_BASE, CODE_SIZE, IntTab(cluster(x,y),MEMC_TGTID), true));
+	      maptabd.add(Segment("d_seg_data    ", DATA_BASE, DATA_SIZE, IntTab(cluster(x,y),MEMC_TGTID), true));
+            }
+            if ( cluster(x,y) == cluster_kcode_index )
+            {
+	      maptabd.add(Segment("d_seg_kcod    ", KCOD_BASE, KCOD_SIZE, IntTab(cluster(x,y),MEMC_TGTID), true));
+	      maptabd.add(Segment("d_seg_kdat    ", KDAT_BASE, KDAT_SIZE, IntTab(cluster(x,y),MEMC_TGTID), true));
+	      maptabd.add(Segment("d_seg_kunc    ", KUNC_BASE, KUNC_SIZE, IntTab(cluster(x,y),MEMC_TGTID), true));
+            }
+        }
+    }
+    std::cout << maptabd << std::endl;
+
+    // coherence network
+    // - tgtid_c_proc = srcid_c_proc = local procid
+    // - tgtid_c_memc = srcid_c_memc = nprocs
+    MappingTable maptabc(address_width, 
+                         IntTab(x_width + y_width, 16 - x_width - y_width), 
+                         IntTab(x_width + y_width, srcid_width - x_width - y_width), 
+                         0x00FF0000);
+
+    for ( size_t x = 0 ; x < xmax ; x++)
+    {
+        for ( size_t y = 0 ; y < ymax ; y++)
+        {
+            sc_uint<address_width> offset  = cluster(x,y) << (address_width-x_width-y_width);
+
+            // cleanup requests regarding the heap segment must be routed to the memory cache
+            std::ostringstream sh;
+            sh << "c_seg_heap_" << x << "_" << y;
+            maptabc.add(Segment(sh.str(), HEAP_BASE+offset, HEAP_SIZE, IntTab(cluster(x,y), nprocs), false));
+
+            // cleanup requests regarding the stack segmentmust be routed to the memory cache
+            std::ostringstream ss;
+            ss << "c_seg_stak_" << x << "_" << y;
+            maptabc.add(Segment(ss.str(), STAK_BASE+offset, STAK_SIZE, IntTab(cluster(x,y), nprocs), false));
+
+            // cleanup requests regarding the BROM segment are also be routed to the memory cache
+            if ( cluster(x,y) == cluster_io_index )
+            {
+                maptabc.add(Segment("c_seg_brom    ", BROM_BASE, BROM_SIZE, IntTab(cluster(x,y), nprocs), false));
+            }
+
+            // cleanup requests regarding the code and data segment musts be send to the memory cache
+            if ( cluster(x,y) == cluster_code_index )
+            {
+                maptabc.add(Segment("c_seg_code    ", CODE_BASE, CODE_SIZE, IntTab(cluster(x,y), nprocs), false));
+                maptabc.add(Segment("c_seg_data    ", DATA_BASE, DATA_SIZE, IntTab(cluster(x,y), nprocs), false));
+            }
+            // cleanup requests regarding the kcode, kunc, and kdata segments must be send to the memory cache
+            if ( cluster(x,y) == cluster_kcode_index )
+            {
+                maptabc.add(Segment("c_seg_kcod    ", KCOD_BASE, KCOD_SIZE, IntTab(cluster(x,y), nprocs), false));
+                maptabc.add(Segment("c_seg_kdat    ", KDAT_BASE, KDAT_SIZE, IntTab(cluster(x,y), nprocs), false));
+                maptabc.add(Segment("c_seg_kunc    ", KUNC_BASE, KUNC_SIZE, IntTab(cluster(x,y), nprocs), false));
+            }
+
+            // update & invalidate requests must be routed to the proper processor
+	    for ( size_t p = 0 ; p < nprocs ; p++)
+            {
+                std::ostringstream sp;
+	        sp << "c_seg_proc_" << x << "_" << y << "_" << p;
+	        maptabc.add(Segment(sp.str(), PROC_BASE+offset+(p*0x10000), PROC_SIZE, 
+                            IntTab(cluster(x,y), p), false, true, IntTab(cluster(x,y), p))); 
+            }
+        }
+    }
+    std::cout << maptabc << std::endl;
+
+    // external network
+    MappingTable maptabx(address_width, IntTab(1), IntTab(x_width+y_width), 0xF0000000);
+
+    for ( size_t x = 0 ; x < xmax ; x++)
+    {
+        for ( size_t y = 0 ; y < ymax ; y++)
+        { 
+
+            sc_uint<address_width> offset  = cluster(x,y) << (address_width-x_width-y_width);
+
+            std::ostringstream sh;
+            sh << "x_seg_heap_" << x << "_" << y;
+            maptabx.add(Segment(sh.str(), HEAP_BASE+offset, HEAP_SIZE, IntTab(cluster(x,y)), false));
+
+            std::ostringstream ss;
+            ss << "x_seg_stak_" << x << "_" << y;
+            maptabx.add(Segment(ss.str(), STAK_BASE+offset, STAK_SIZE, IntTab(cluster(x,y)), false));
+
+            if ( cluster(x,y) == cluster_code_index )
+            {
+                maptabx.add(Segment("x_seg_code    ", CODE_BASE, CODE_SIZE, IntTab(cluster(x,y)), false));
+                maptabx.add(Segment("x_seg_data    ", DATA_BASE, DATA_SIZE, IntTab(cluster(x,y)), false));
+            }
+            if ( cluster(x,y) == cluster_kcode_index )
+            {
+                maptabx.add(Segment("x_seg_kcod    ", KCOD_BASE, KCOD_SIZE, IntTab(cluster(x,y)), false));
+                maptabx.add(Segment("x_seg_kdat    ", KDAT_BASE, KDAT_SIZE, IntTab(cluster(x,y)), false));
+                maptabx.add(Segment("x_seg_kunc    ", KUNC_BASE, KUNC_SIZE, IntTab(cluster(x,y)), false));
+            }
+        }
+    }
+    std::cout << maptabx << std::endl;
+
+    ////////////////////
+    // Signals
+    ///////////////////
+
+    sc_clock		signal_clk("clk");
+    sc_signal<bool> 	signal_resetn("resetn");
+
+    // Horizontal inter-clusters DSPIN signals
+    DspinSignals<cmd_width>*** signal_dspin_h_cmd_inc =
+      alloc_elems<DspinSignals<cmd_width> >("signal_dspin_h_cmd_inc", xmax-1, ymax, 2);
+    DspinSignals<cmd_width>*** signal_dspin_h_cmd_dec =
+      alloc_elems<DspinSignals<cmd_width> >("signal_dspin_h_cmd_dec", xmax-1, ymax, 2);
+    DspinSignals<rsp_width>*** signal_dspin_h_rsp_inc =
+      alloc_elems<DspinSignals<rsp_width> >("signal_dspin_h_rsp_inc", xmax-1, ymax, 2);
+    DspinSignals<rsp_width>*** signal_dspin_h_rsp_dec =
+      alloc_elems<DspinSignals<rsp_width> >("signal_dspin_h_rsp_dec", xmax-1, ymax, 2);
+
+    // Vertical inter-clusters DSPIN signals
+    DspinSignals<cmd_width>*** signal_dspin_v_cmd_inc =
+        alloc_elems<DspinSignals<cmd_width> >("signal_dspin_v_cmd_inc", xmax, ymax-1, 2);
+    DspinSignals<cmd_width>*** signal_dspin_v_cmd_dec =
+        alloc_elems<DspinSignals<cmd_width> >("signal_dspin_v_cmd_dec", xmax, ymax-1, 2);
+    DspinSignals<rsp_width>*** signal_dspin_v_rsp_inc =
+        alloc_elems<DspinSignals<rsp_width> >("signal_dspin_v_rsp_inc", xmax, ymax-1, 2);
+    DspinSignals<rsp_width>*** signal_dspin_v_rsp_dec =
+        alloc_elems<DspinSignals<rsp_width> >("signal_dspin_v_rsp_dec", xmax, ymax-1, 2);
+
+    // Mesh boundaries DSPIN signals
+    DspinSignals<cmd_width>**** signal_dspin_false_cmd_in =
+        alloc_elems<DspinSignals<cmd_width> >("signal_dspin_false_cmd_in", xmax, ymax, 2, 4);
+    DspinSignals<cmd_width>**** signal_dspin_false_cmd_out =
+        alloc_elems<DspinSignals<cmd_width> >("signal_dspin_false_cmd_out", xmax, ymax, 2, 4);
+    DspinSignals<rsp_width>**** signal_dspin_false_rsp_in =
+        alloc_elems<DspinSignals<rsp_width> >("signal_dspin_false_rsp_in", xmax, ymax, 2, 4);
+    DspinSignals<rsp_width>**** signal_dspin_false_rsp_out =
+        alloc_elems<DspinSignals<rsp_width> >("signal_dspin_false_rsp_out", xmax, ymax, 2, 4);
+
+
+    ////////////////////////////
+    //      Components
+    ////////////////////////////
+
+#if USE_ALMOS
+    soclib::common::Loader loader("bootloader.bin",
+				  "arch-info.bin@"TO_STR(BOOT_INFO_BLOCK)":D",
+				  "kernel-soclib.bin@"TO_STR(KERNEL_BIN_IMG)":D");
+#else
+    soclib::common::Loader loader(soft_name);
+#endif
+
+    typedef soclib::common::GdbServer<soclib::common::Mips32ElIss> proc_iss;
+    proc_iss::set_loader(loader);
+
+    TsarV4ClusterXbar<vci_param, proc_iss, cmd_width, rsp_width>* clusters[xmax][ymax];
+
+#ifdef _OPENMP
+
+#pragma omp parallel
+{
+#pragma omp for
+    for( int i = 0 ; i  < (int)(xmax * ymax); i++)
+    {
+        size_t x = i / ymax;
+        size_t y = i % ymax;
+
+#pragma omp critical
+        {
+	std::ostringstream sc;
+	sc << "cluster_" << x << "_" << y;
+	clusters[x][y] = new TsarV4ClusterXbar<vci_param, proc_iss, cmd_width, rsp_width>
+	    (sc.str().c_str(),
+             nprocs,
+	     x,
+	     y,
+	     cluster(x,y),
+	     maptabd,
+	     maptabc,
+	     maptabx,
+	     x_width,
+	     y_width,
+	     MEMC_TGTID,
+	     XICU_TGTID,
+	     FBUF_TGTID,
+	     MTTY_TGTID,
+	     BROM_TGTID,
+	     BDEV_TGTID,
+	     CDMA_TGTID,
+             memc_ways,
+             memc_sets,
+             l1_i_ways,
+             l1_i_sets,
+             l1_d_ways,
+             l1_d_sets,
+             xram_latency,
+	     (cluster(x,y) == cluster_io_index),
+	     xfb,
+	     yfb,
+	     disk_name,
+	     blk_size,
+	     loader);
+	}
+    }
+}
+
+#else  // _OPENMP
+
+    for( size_t x = 0 ; x  < xmax ; x++)
+    {
+        for( size_t y = 0 ; y < ymax ; y++ )
+        {
+
+std::cout << "building cluster_" << x << "_" << y << std::endl;
+
+	    std::ostringstream sc;
+	    sc << "cluster_" << x << "_" << y;
+	    clusters[x][y] = new TsarV4ClusterXbar<vci_param, proc_iss, cmd_width, rsp_width>
+	    (sc.str().c_str(),
+             nprocs,
+	     x,
+	     y,
+	     cluster(x,y),
+	     maptabd,
+	     maptabc,
+	     maptabx,
+	     x_width,
+	     y_width,
+	     MEMC_TGTID,
+	     XICU_TGTID,
+	     FBUF_TGTID,
+	     MTTY_TGTID,
+	     BROM_TGTID,
+	     BDEV_TGTID,
+	     CDMA_TGTID,
+             memc_ways,
+             memc_sets,
+             l1_i_ways,
+             l1_i_sets,
+             l1_d_ways,
+             l1_d_sets,
+             xram_latency,
+	     (cluster(x,y) == cluster_io_index),
+	     xfb,
+	     yfb,
+	     disk_name,
+	     blk_size,
+	     loader);
+
+std::cout << "cluster_" << x << "_" << y << " constructed" << std::endl;
+
+	}
+    }
+    
+#endif	// _OPENMP
+
+    ///////////////////////////////////////////////////////////////
+    //     Net-list 
+    ///////////////////////////////////////////////////////////////
+
+    // Clock & RESET
+    for ( size_t x = 0 ; x < (xmax) ; x++ )
+    {
+        for ( size_t y = 0 ; y < ymax ; y++ )
+        {
+            clusters[x][y]->p_clk			(signal_clk);
+            clusters[x][y]->p_resetn			(signal_resetn);
+        }
+    }
+
+    // Inter Clusters horizontal connections
+    if ( xmax > 1 )
+    {
+        for ( size_t x = 0 ; x < (xmax-1) ; x++ )
+        {
+            for ( size_t y = 0 ; y < ymax ; y++ )
+            {
+                for ( size_t k = 0 ; k < 2 ; k++ )
+                {
+		clusters[x][y]->p_cmd_out[k][EAST]      (signal_dspin_h_cmd_inc[x][y][k]);
+                clusters[x+1][y]->p_cmd_in[k][WEST]     (signal_dspin_h_cmd_inc[x][y][k]);
+                clusters[x][y]->p_cmd_in[k][EAST]       (signal_dspin_h_cmd_dec[x][y][k]);
+                clusters[x+1][y]->p_cmd_out[k][WEST]    (signal_dspin_h_cmd_dec[x][y][k]);
+                clusters[x][y]->p_rsp_out[k][EAST]      (signal_dspin_h_rsp_inc[x][y][k]);
+                clusters[x+1][y]->p_rsp_in[k][WEST]     (signal_dspin_h_rsp_inc[x][y][k]);
+                clusters[x][y]->p_rsp_in[k][EAST]       (signal_dspin_h_rsp_dec[x][y][k]);
+                clusters[x+1][y]->p_rsp_out[k][WEST]    (signal_dspin_h_rsp_dec[x][y][k]);
+                }
+            }
+        }
+    }
+    std::cout << "Horizontal connections established" << std::endl;	
+
+    // Inter Clusters vertical connections
+    if ( ymax > 1 )
+    {
+        for ( size_t y = 0 ; y < (ymax-1) ; y++ )
+        {
+            for ( size_t x = 0 ; x < xmax ; x++ )
+            {
+                for ( size_t k = 0 ; k < 2 ; k++ )
+                {
+                clusters[x][y]->p_cmd_out[k][NORTH]     (signal_dspin_v_cmd_inc[x][y][k]);
+                clusters[x][y+1]->p_cmd_in[k][SOUTH]    (signal_dspin_v_cmd_inc[x][y][k]);
+                clusters[x][y]->p_cmd_in[k][NORTH]      (signal_dspin_v_cmd_dec[x][y][k]);
+                clusters[x][y+1]->p_cmd_out[k][SOUTH]   (signal_dspin_v_cmd_dec[x][y][k]);
+                clusters[x][y]->p_rsp_out[k][NORTH]     (signal_dspin_v_rsp_inc[x][y][k]);
+                clusters[x][y+1]->p_rsp_in[k][SOUTH]    (signal_dspin_v_rsp_inc[x][y][k]);
+                clusters[x][y]->p_rsp_in[k][NORTH]      (signal_dspin_v_rsp_dec[x][y][k]);
+                clusters[x][y+1]->p_rsp_out[k][SOUTH]   (signal_dspin_v_rsp_dec[x][y][k]);
+                }
+            }
+        }
+    }
+    std::cout << "Vertical connections established" << std::endl;
+
+    // East & West boundary cluster connections
+    for ( size_t y = 0 ; y < ymax ; y++ )
+    {
+        for ( size_t k = 0 ; k < 2 ; k++ )
+        {
+	    clusters[0][y]->p_cmd_in[k][WEST]       	(signal_dspin_false_cmd_in[0][y][k][WEST]);
+	    clusters[0][y]->p_cmd_out[k][WEST]      	(signal_dspin_false_cmd_out[0][y][k][WEST]);
+	    clusters[0][y]->p_rsp_in[k][WEST]       	(signal_dspin_false_rsp_in[0][y][k][WEST]);
+	    clusters[0][y]->p_rsp_out[k][WEST]      	(signal_dspin_false_rsp_out[0][y][k][WEST]);
+	  
+	    clusters[xmax-1][y]->p_cmd_in[k][EAST]  	(signal_dspin_false_cmd_in[xmax-1][y][k][EAST]);
+	    clusters[xmax-1][y]->p_cmd_out[k][EAST] 	(signal_dspin_false_cmd_out[xmax-1][y][k][EAST]);
+	    clusters[xmax-1][y]->p_rsp_in[k][EAST]  	(signal_dspin_false_rsp_in[xmax-1][y][k][EAST]);
+	    clusters[xmax-1][y]->p_rsp_out[k][EAST] 	(signal_dspin_false_rsp_out[xmax-1][y][k][EAST]);
+	}
+    }
+    
+    // North & South boundary clusters connections
+    for ( size_t x = 0 ; x < xmax ; x++ )
+    {
+        for ( size_t k = 0 ; k < 2 ; k++ )
+        {
+	    clusters[x][0]->p_cmd_in[k][SOUTH]      	(signal_dspin_false_cmd_in[x][0][k][SOUTH]);
+	    clusters[x][0]->p_cmd_out[k][SOUTH]     	(signal_dspin_false_cmd_out[x][0][k][SOUTH]);
+	    clusters[x][0]->p_rsp_in[k][SOUTH]      	(signal_dspin_false_rsp_in[x][0][k][SOUTH]);
+	    clusters[x][0]->p_rsp_out[k][SOUTH]     	(signal_dspin_false_rsp_out[x][0][k][SOUTH]);
+	    
+	    clusters[x][ymax-1]->p_cmd_in[k][NORTH] 	(signal_dspin_false_cmd_in[x][ymax-1][k][NORTH]);
+	    clusters[x][ymax-1]->p_cmd_out[k][NORTH]	(signal_dspin_false_cmd_out[x][ymax-1][k][NORTH]);
+	    clusters[x][ymax-1]->p_rsp_in[k][NORTH] 	(signal_dspin_false_rsp_in[x][ymax-1][k][NORTH]);
+	    clusters[x][ymax-1]->p_rsp_out[k][NORTH]	(signal_dspin_false_rsp_out[x][ymax-1][k][NORTH]);
+	}
+    }
+      
+
+    ////////////////////////////////////////////////////////
+    //   Simulation
+    ///////////////////////////////////////////////////////
+
+    sc_start(sc_core::sc_time(0, SC_NS));
+    signal_resetn = false;
+
+    // network boundaries signals
+    for(size_t x=0; x<xmax ; x++)
+    {
+        for(size_t y=0 ; y<ymax ; y++)
+        {
+            for (size_t k=0; k<2; k++)
+            {
+                for(size_t a=0; a<4; a++)
+                {
+		        signal_dspin_false_cmd_in[x][y][k][a].write = false;
+		        signal_dspin_false_cmd_in[x][y][k][a].read = true;
+                        signal_dspin_false_cmd_out[x][y][k][a].write = false;
+                        signal_dspin_false_cmd_out[x][y][k][a].read = true;
+
+                        signal_dspin_false_rsp_in[x][y][k][a].write = false;
+                        signal_dspin_false_rsp_in[x][y][k][a].read = true;
+                        signal_dspin_false_rsp_out[x][y][k][a].write = false;
+                        signal_dspin_false_rsp_out[x][y][k][a].read = true;
+		}
+            }
+        }
+    }
+
+    sc_start(sc_core::sc_time(1, SC_NS));
+    signal_resetn = true;
+
+    sc_start(sc_core::sc_time(ncycles, SC_NS));
+
+/*
+    for ( size_t n=0 ; n<ncycles ; n++)
+    {
+        sc_start(sc_core::sc_time(1, SC_NS));
+
+        if ( trace_ok && (n > from_cycle) )
+        {
+            std::cout << "****************** cycle " << std::dec << n ;
+            std::cout << " ***********************************" << std::endl;
+            clusters[5][7]->proc[2]->print_trace();
+            print_vci_signal("proc_5_7_2_d", clusters[5][7]->signal_vci_ini_d_proc[2]);
+
+            clusters[0][0]->proc[1]->print_trace();
+            clusters[0][0]->proc[2]->print_trace();
+            clusters[0][0]->proc[3]->print_trace();
+            std::cout << std::endl;  
+
+            clusters[0][1]->proc[0]->print_trace();
+            clusters[0][1]->proc[1]->print_trace();
+            clusters[0][1]->proc[2]->print_trace();
+            clusters[0][1]->proc[3]->print_trace();
+
+            std::cout << std::endl;  
+
+            clusters[1][0]->proc[0]->print_trace();
+            clusters[1][0]->proc[1]->print_trace();
+            clusters[1][0]->iniwrapperd->print_trace();
+            clusters[1][0]->proc[2]->print_trace();
+            print_vci_signal("proc_1_0_2_tgt_c", clusters[1][0]->signal_vci_tgt_c_proc[2]);
+            print_vci_signal("proc_1_0_2_d", clusters[1][0]->signal_vci_ini_d_proc[2]);
+            print_vci_signal("memc_0_0_d", clusters[0][0]->signal_vci_tgt_d_memc);
+            print_vci_signal("g2l_0_0_d", clusters[0][0]->signal_vci_g2l_d);
+            print_dspin_signal("l2g_0_0_d RSP", clusters[0][0]->signal_dspin_rsp_l2g_d);
+            print_dspin_signal("c10_to_c00 RSP", signal_dspin_h_rsp_dec[0][0][0]);
+            print_dspin_signal("c00_to_c10 RSP", signal_dspin_h_rsp_inc[0][0][0]);
+            print_dspin_signal("g2l_1_0_d RSP", clusters[1][0]->signal_dspin_rsp_g2l_d);
+            print_vci_signal("l2g_1_0_d", clusters[1][0]->signal_vci_l2g_d);
+            clusters[1][0]->proc[3]->print_trace();
+
+            std::cout << std::endl;  
+
+            clusters[1][1]->proc[0]->print_trace();
+            clusters[1][1]->proc[1]->print_trace();
+            clusters[1][1]->proc[2]->print_trace();
+            clusters[1][1]->proc[3]->print_trace();
+
+            std::cout << std::endl;  
+
+            clusters[0][0]->memc->print_trace();
+            clusters[0][1]->memc->print_trace();
+            clusters[1][0]->memc->print_trace();
+            clusters[1][1]->memc->print_trace();
+
+            clusters[0][0]->iniwrapperd->print_trace();
+            clusters[0][0]->tgtwrapperd->print_trace();
+            clusters[1][0]->iniwrapperd->print_trace();
+            clusters[1][0]->tgtwrapperd->print_trace();
+            clusters[0][1]->iniwrapperd->print_trace();
+            clusters[0][1]->tgtwrapperd->print_trace();
+            clusters[1][1]->iniwrapperd->print_trace();
+            clusters[1][1]->tgtwrapperd->print_trace();
+
+            std::cout << std::endl;  
+
+            print_vci_signal("proc_0_0_0_d", clusters[0][0]->signal_vci_ini_d_proc[0]);
+            print_vci_signal("proc_1_0_0_d", clusters[1][0]->signal_vci_ini_d_proc[0]);
+            print_vci_signal("proc_0_1_0_d", clusters[0][1]->signal_vci_ini_d_proc[0]);
+            print_vci_signal("proc_1_1_0_d", clusters[1][1]->signal_vci_ini_d_proc[0]);
+
+            print_vci_signal("proc_0_0_0_c", clusters[0][0]->signal_vci_tgt_c_proc[0]);
+            print_vci_signal("proc_1_0_0_c", clusters[1][0]->signal_vci_tgt_c_proc[0]);
+            print_vci_signal("proc_0_1_0_c", clusters[0][1]->signal_vci_tgt_c_proc[0]);
+            print_vci_signal("proc_1_1_0_c", clusters[1][1]->signal_vci_tgt_c_proc[0]);
+
+            print_vci_signal("memc_0_0_d", clusters[0][0]->signal_vci_tgt_d_memc);
+            print_vci_signal("memc_1_0_d", clusters[1][0]->signal_vci_tgt_d_memc);
+            print_vci_signal("memc_0_1_d", clusters[0][1]->signal_vci_tgt_d_memc);
+            print_vci_signal("memc_1_1_d", clusters[1][1]->signal_vci_tgt_d_memc);
+
+            print_vci_signal("memc_1_0_ini_c", clusters[1][0]->signal_vci_ini_c_memc);
+
+            print_vci_signal("l2g_1_0_c", clusters[1][0]->signal_vci_l2g_c);
+
+            print_dspin_signal("l2g_1_0_c CMD", clusters[1][0]->signal_dspin_cmd_l2g_c);
+
+            print_vci_signal("l2g_0_0_d", clusters[0][0]->signal_vci_l2g_d);
+            print_vci_signal("g2l_0_0_d", clusters[0][0]->signal_vci_g2l_d);
+
+            print_vci_signal("l2g_1_0_d", clusters[1][0]->signal_vci_l2g_d);
+            print_vci_signal("g2l_1_0_d", clusters[1][0]->signal_vci_g2l_d);
+
+            print_dspin_signal("l2g_0_0_d CMD", clusters[0][0]->signal_dspin_cmd_l2g_d);
+            print_dspin_signal("g2l_0_0_d CMD", clusters[0][0]->signal_dspin_cmd_g2l_d);
+            print_dspin_signal("l2g_0_0_d RSP", clusters[0][0]->signal_dspin_rsp_l2g_d);
+            print_dspin_signal("g2l_0_0_d RSP", clusters[0][0]->signal_dspin_rsp_g2l_d);
+
+            print_dspin_signal("l2g_1_0_d CMD", clusters[1][0]->signal_dspin_cmd_l2g_d);
+            print_dspin_signal("g2l_1_0_d CMD", clusters[1][0]->signal_dspin_cmd_g2l_d);
+            print_dspin_signal("l2g_1_0_d RSP", clusters[1][0]->signal_dspin_rsp_l2g_d);
+            print_dspin_signal("g2l_1_0_d RSP", clusters[1][0]->signal_dspin_rsp_g2l_d);
+
+            print_vci_signal("bdev_tgt", clusters[1][0]->signal_vci_tgt_d_bdev);
+            print_vci_signal("bdev_ini", clusters[1][0]->signal_vci_ini_d_bdev);
+
+            print_vci_signal("brom_tgt", clusters[1][0]->signal_vci_tgt_d_brom);
+            
+            if ( clusters[0][0]->signal_irq_bdev.read() != 0) std::cout << " IRQ_BDEV" << std::endl;
+            if ( clusters[0][0]->signal_proc_it[0].read() != 0) std::cout << " IRQ_PROC" << std::endl;
+        }
+    }
+*/
+
+    return EXIT_SUCCESS;
+}
+
+int sc_main (int argc, char *argv[])
+{
+	try {
+		return _main(argc, argv);
+	} catch (std::exception &e) {
+		std::cout << e.what() << std::endl;
+	} catch (...) {
+		std::cout << "Unknown exception occured" << std::endl;
+		throw;
+	}
+	return 1;
+}
Index: branches/v4/platforms/tsarv4_generic_xbar/top.desc
===================================================================
--- branches/v4/platforms/tsarv4_generic_xbar/top.desc	(revision 371)
+++ branches/v4/platforms/tsarv4_generic_xbar/top.desc	(revision 371)
@@ -0,0 +1,22 @@
+
+# -*- python -*-
+
+todo = Platform('caba', 'top.cpp',
+	uses = [
+            Uses('caba:tsarv4_cluster_xbar', iss_t = 'common:gdb_iss', 
+                                              gdb_iss_t = 'common:mips32el', 
+                                              cmd_width = 40, rsp_width = 33),
+	    Uses('common:elf_file_loader'),
+            Uses('common:plain_file_loader'),
+	],
+	cell_size = 4,
+	plen_size = 8,
+	addr_size = 32,
+	rerror_size = 2,
+	clen_size = 1,
+	rflag_size = 1,
+	srcid_size = 14,
+	pktid_size = 4,
+	trdid_size = 4,
+	wrplen_size = 1,
+)
Index: branches/v4/platforms/tsarv4_generic_xbar/tsarv4_cluster_xbar/caba/metadata/tsarv4_cluster_xbar.sd
===================================================================
--- branches/v4/platforms/tsarv4_generic_xbar/tsarv4_cluster_xbar/caba/metadata/tsarv4_cluster_xbar.sd	(revision 371)
+++ branches/v4/platforms/tsarv4_generic_xbar/tsarv4_cluster_xbar/caba/metadata/tsarv4_cluster_xbar.sd	(revision 371)
@@ -0,0 +1,71 @@
+
+# -*- python -*-
+
+Module('caba:tsarv4_cluster_xbar',
+	classname = 'soclib::caba::TsarV4ClusterXbar',
+	tmpl_parameters = [
+		parameter.Module('vci_param', default = 'caba:vci_param'),
+		parameter.Module('iss_t'),
+		parameter.Int('cmd_width'),
+		parameter.Int('rsp_width'),
+		],
+	header_files = [ '../source/include/tsarv4_cluster_xbar.h', ],
+	implementation_files = [ '../source/src/tsarv4_cluster_xbar.cpp', ],
+	uses = [
+		Uses('caba:base_module'),
+		Uses('common:mapping_table'),
+		Uses('common:iss2'),
+                Uses('caba:vci_cc_xcache_wrapper_v4', iss_t = 'common:gdb_iss', gdb_iss_t = 'common:mips32el'),
+                Uses('caba:vci_mem_cache_v4'),
+            	Uses('caba:vci_simple_ram'),
+            	Uses('caba:vci_xicu'),
+            	Uses('caba:vci_local_crossbar'),
+            	Uses('caba:virtual_dspin_router', flit_width = parameter.Reference('cmd_width')),
+            	Uses('caba:virtual_dspin_router', flit_width = parameter.Reference('rsp_width')),
+            	Uses('caba:vci_vdspin_target_wrapper', dspin_cmd_width = parameter.Reference('cmd_width'), 
+                                                       dspin_rsp_width = parameter.Reference('rsp_width')),
+            	Uses('caba:vci_vdspin_initiator_wrapper', dspin_cmd_width = parameter.Reference('cmd_width'), 
+                                                          dspin_rsp_width = parameter.Reference('rsp_width')),
+		Uses('caba:vci_multi_tty'),
+		Uses('caba:vci_framebuffer'),
+		Uses('caba:vci_block_device_tsar_v4'),
+		Uses('caba:vci_multi_dma'),
+		Uses('common:elf_file_loader'),
+		],
+        instance_parameters = [
+                parameter.Int('n_x'),
+                parameter.Int('n_y'),
+		parameter.Int('n_cluster'),
+		parameter.Module('mtd', 'common:mapping_table'),
+                parameter.Module('mtc', 'common:mapping_table'),
+		parameter.Module('mtx', 'common:mapping_table'),
+		parameter.Int('x_width'),
+		parameter.Int('y_width'),
+		parameter.Int('memc_tgtid'),
+		parameter.Int('xicu_tgtid'),
+		parameter.Int('fbuf_tgtid'),
+		parameter.Int('mtty_tgtid'),
+		parameter.Int('brom_tgtid'),
+		parameter.Int('bdev_tgtid'),
+		parameter.Int('cdma_tgtid'),
+		parameter.Int('memc_ways'),
+		parameter.Int('memc_sets'),
+		parameter.Int('l1_i_ways'),
+		parameter.Int('l1_i_sets'),
+		parameter.Int('l1_d_ways'),
+		parameter.Int('l1_d_sets'),
+                parameter.Int('xram_latency'),
+		parameter.Bool('io'),
+                ],
+
+	ports = [
+		Port('caba:bit_in', 'p_resetn', auto = 'resetn'),
+		Port('caba:clock_in', 'p_clk', auto = 'clock'),
+		Port('caba:dspin_output', 'p_cmd_out', [2, 4], dspin_data_size = parameter.Reference('cmd_width')),
+		Port('caba:dspin_input', 'p_cmd_in', [2, 4], dspin_data_size = parameter.Reference('cmd_width')),
+		Port('caba:dspin_output', 'p_rsp_out', [2, 4], dspin_data_size = parameter.Reference('rsp_width')), 
+                Port('caba:dspin_input', 'p_rsp_in', [2, 4], dspin_data_size = parameter.Reference('rsp_width')),
+		],
+)
+
+
Index: branches/v4/platforms/tsarv4_generic_xbar/tsarv4_cluster_xbar/caba/source/include/tsarv4_cluster_xbar.h
===================================================================
--- branches/v4/platforms/tsarv4_generic_xbar/tsarv4_cluster_xbar/caba/source/include/tsarv4_cluster_xbar.h	(revision 371)
+++ branches/v4/platforms/tsarv4_generic_xbar/tsarv4_cluster_xbar/caba/source/include/tsarv4_cluster_xbar.h	(revision 371)
@@ -0,0 +1,170 @@
+//////////////////////////////////////////////////////////////////////////////
+// File: tsarv4_cluster_xbar.h
+// Author: Alain Greiner 
+// Copyright: UPMC/LIP6
+// Date : march 2011
+// This program is released under the GNU public license
+//////////////////////////////////////////////////////////////////////////////
+// This file define a TSAR cluster architecture without virtual memory,
+// - It uses the virtual_dspin_router  as distributed global interconnect 
+// - It uses the vci_local_crossbar as local interconnect 
+// - It uses the vci_cc_xcache_wrapper_v4
+// - It uses the vci_mem_cache_v4
+// - It contains a private RAM a variable latency to emulate the L3 cache
+// - It can contains 1, 2 or 4 processors
+// - Each processor has a private local TTY terminal (vci_multi_tty)
+// - Each processor has a private dma channel (vci_multi_dma)
+// - It uses the vci_xicu interrupt controller
+// - The nprocs tty irq are connected to IRQ_IN[0]...IRQ_IN[3]
+// - The nprocs dma irq are connected to IRQ_IN[4]...IRQ_IN[7]
+// - The peripherals BDEV, FBUF, and the boot BROM are in the cluster 
+//   containing address 0xBFC00000, and the bdev_irq is connected to IRQ_IN[8]
+////////////////////////////////////////////////////////////////////////////////// 
+
+#ifndef SOCLIB_CABA_TSAR_CLUSTER_V4_XBAR_H
+#define SOCLIB_CABA_TSAR_CLUSTER_V4_XBAR_H
+
+#include <systemc>
+#include <sys/time.h>
+#include <iostream>
+#include <sstream>
+#include <cstdlib>
+#include <cstdarg>
+
+#include "gdbserver.h"
+#include "mapping_table.h"
+#include "mips32.h"
+#include "vci_simple_ram.h"
+#include "vci_xicu.h"
+#include "vci_local_crossbar.h"
+#include "virtual_dspin_router.h"
+#include "vci_vdspin_target_wrapper.h"
+#include "vci_vdspin_initiator_wrapper.h"
+#include "vci_multi_tty.h"
+#include "vci_block_device_tsar_v4.h"
+#include "vci_framebuffer.h"
+#include "vci_multi_dma.h"
+#include "vci_mem_cache_v4.h"
+#include "vci_cc_xcache_wrapper_v4.h"
+
+namespace soclib {
+namespace caba	{
+
+///////////////////////////////////////////////////////////////////////////
+template<typename vci_param, typename iss_t, int cmd_width, int rsp_width>
+class TsarV4ClusterXbar 
+///////////////////////////////////////////////////////////////////////////
+    : public soclib::caba::BaseModule
+{
+
+  public:
+
+	// Ports
+    	sc_in<bool>                             		p_clk;
+    	sc_in<bool>                             		p_resetn;
+	soclib::caba::DspinOutput<cmd_width>   			**p_cmd_out;
+	soclib::caba::DspinInput<cmd_width>    			**p_cmd_in;
+        soclib::caba::DspinOutput<rsp_width>                   	**p_rsp_out;
+        soclib::caba::DspinInput<rsp_width>                   	**p_rsp_in;
+
+        // interrupt signals
+	sc_signal<bool>     		signal_false;
+	sc_signal<bool> 		signal_proc_it[4];
+	sc_signal<bool> 		signal_irq_mdma[4];
+	sc_signal<bool>			signal_irq_mtty;
+	sc_signal<bool> 		signal_irq_bdev;
+	
+	// DSPIN signals between DSPIN routers and VCI/DSPIN wrappers
+	DspinSignals<cmd_width> 	signal_dspin_cmd_l2g_d; 
+	DspinSignals<cmd_width> 	signal_dspin_cmd_g2l_d; 
+	DspinSignals<cmd_width> 	signal_dspin_cmd_l2g_c;
+	DspinSignals<cmd_width> 	signal_dspin_cmd_g2l_c; 
+	DspinSignals<rsp_width> 	signal_dspin_rsp_l2g_d; 
+	DspinSignals<rsp_width> 	signal_dspin_rsp_g2l_d; 
+	DspinSignals<rsp_width> 	signal_dspin_rsp_l2g_c;
+	DspinSignals<rsp_width> 	signal_dspin_rsp_g2l_c;
+
+	// VCI signals between VCI/DSPIN wrappers and local crossbars
+	VciSignals<vci_param>  		signal_vci_l2g_d; 
+	VciSignals<vci_param>  		signal_vci_g2l_d; 
+	VciSignals<vci_param>  		signal_vci_l2g_c; 
+	VciSignals<vci_param>  		signal_vci_g2l_c; 
+
+	// Direct VCI signals
+	VciSignals<vci_param> 		signal_vci_ini_d_proc[4]; 
+	VciSignals<vci_param>  		signal_vci_ini_d_bdev; 
+	VciSignals<vci_param>  		signal_vci_ini_d_mdma; 
+
+	VciSignals<vci_param>		signal_vci_tgt_d_memc;
+	VciSignals<vci_param> 		signal_vci_tgt_d_mtty;
+	VciSignals<vci_param> 		signal_vci_tgt_d_xicu;
+	VciSignals<vci_param> 		signal_vci_tgt_d_bdev;
+	VciSignals<vci_param> 		signal_vci_tgt_d_mdma;
+	VciSignals<vci_param> 		signal_vci_tgt_d_brom;
+	VciSignals<vci_param> 		signal_vci_tgt_d_fbuf;
+
+	// Coherence VCi signals
+	VciSignals<vci_param> 		signal_vci_ini_c_proc[4];
+	VciSignals<vci_param> 		signal_vci_tgt_c_proc[4];
+	VciSignals<vci_param> 		signal_vci_ini_c_memc;
+	VciSignals<vci_param> 		signal_vci_tgt_c_memc;
+
+	// external RAM VCI signal
+	VciSignals<vci_param> 		signal_vci_xram;
+	
+        // Components
+
+        VciCcXCacheWrapperV4<vci_param, iss_t>*                 	proc[4];
+        VciMemCacheV4<vci_param>*                               	memc;
+        VciXicu<vci_param>*                                     	xicu;
+        VciLocalCrossbar<vci_param>*        				xbard;
+        VciLocalCrossbar<vci_param>*        				xbarc;
+        VciVdspinTargetWrapper<vci_param,cmd_width,rsp_width>*		tgtwrapperd;
+        VciVdspinInitiatorWrapper<vci_param,cmd_width,rsp_width>*	iniwrapperd;
+        VciVdspinTargetWrapper<vci_param,cmd_width,rsp_width>*		tgtwrapperc;
+        VciVdspinInitiatorWrapper<vci_param,cmd_width,rsp_width>*	iniwrapperc;
+        VirtualDspinRouter<cmd_width>*   	                	cmdrouter;
+        VirtualDspinRouter<rsp_width>*	                        	rsprouter;
+        VciSimpleRam<vci_param>*                 			brom;
+        VciMultiTty<vci_param>*                  			mtty;
+        VciFrameBuffer<vci_param>*               			fbuf;
+        VciBlockDeviceTsarV4<vci_param>*         			bdev;
+        VciMultiDma<vci_param>*                 			mdma;
+        VciSimpleRam<vci_param>*					xram;
+
+	TsarV4ClusterXbar(	sc_module_name  insname,
+                        size_t		nprocs,					// number of processors 
+			size_t		n_x,					// x coordinate
+			size_t		n_y,					// y coordinate
+			size_t		n_cluster,				// y + ymax*x
+			const 		soclib::common::MappingTable &mtd,	// direct mapping table
+			const		soclib::common::MappingTable &mtc,	// coherence mapping table
+			const		soclib::common::MappingTable &mtx,	// xram mapping table
+			size_t		x_width,				// x field number of bits
+			size_t		y_width,				// y field number of bits
+                        size_t		tgtid_memc,
+                        size_t		tgtid_xicu,
+                        size_t		tgtid_fbuf,
+                        size_t		tgtid_mtty,
+                        size_t		tgtid_brom,
+                        size_t		tgtid_bdev,
+                        size_t		tgtid_mdma,
+                        size_t		memc_ways,				// number of ways for MEMC
+                        size_t		memc_sets,				// number of sets for MEMC
+                        size_t		l1_i_ways,				// number of ways for L1 ICACHE
+                        size_t		l1_i_sets,				// number of sets for L1 ICACHE
+                        size_t		l1_d_ways,				// number of ways for L1 DCACHE
+                        size_t		l1_d_sets,				// number of sets for L1 DCACHE
+                        size_t		xram_latency,				// external ram latency
+			bool		io,					// I/O cluster if true
+                        size_t          xfb,					// frame buffer pixels
+                        size_t          yfb,					// frame buffer lines
+                        char*           disk_name,				// virtual disk name for BDEV
+                        size_t          block_size,				// block size for BDEV
+			const Loader   &loader);				// loader for BROM
+
+	~TsarV4ClusterXbar();
+};
+}}
+
+#endif
Index: branches/v4/platforms/tsarv4_generic_xbar/tsarv4_cluster_xbar/caba/source/src/tsarv4_cluster_xbar.cpp
===================================================================
--- branches/v4/platforms/tsarv4_generic_xbar/tsarv4_cluster_xbar/caba/source/src/tsarv4_cluster_xbar.cpp	(revision 371)
+++ branches/v4/platforms/tsarv4_generic_xbar/tsarv4_cluster_xbar/caba/source/src/tsarv4_cluster_xbar.cpp	(revision 371)
@@ -0,0 +1,484 @@
+#include "../include/tsarv4_cluster_xbar.h"
+
+namespace soclib {
+namespace caba  {
+
+//////////////////////////////////////////////////////////////////////////
+//                 Constructor
+//////////////////////////////////////////////////////////////////////////
+template<typename vci_param, typename iss_t, int cmd_width, int rsp_width>
+TsarV4ClusterXbar<vci_param, iss_t, cmd_width, rsp_width>::TsarV4ClusterXbar(
+                        sc_module_name  insname,
+                        size_t          nprocs,
+                        size_t          x_id,
+                        size_t          y_id,
+                        size_t          cluster_id,
+                        const   	soclib::common::MappingTable &mtd,
+                        const   	soclib::common::MappingTable &mtc, 
+                        const   	soclib::common::MappingTable &mtx, 
+                        size_t          x_width,
+                        size_t          y_width,
+                        size_t		tgtid_memc,
+                        size_t		tgtid_xicu,
+                        size_t		tgtid_fbuf,
+                        size_t		tgtid_mtty,
+                        size_t		tgtid_brom,
+                        size_t		tgtid_bdev,
+                        size_t		tgtid_mdma,
+                        size_t		memc_ways,
+                        size_t		memc_sets,
+                        size_t		l1_i_ways,
+                        size_t		l1_i_sets,
+                        size_t		l1_d_ways,
+                        size_t		l1_d_sets,
+                        size_t		xram_latency,
+                        bool            io,
+                        size_t		xfb,
+                        size_t		yfb,
+                        char*		disk_name,
+                        size_t		block_size,
+                        Loader		loader)
+      : soclib::caba::BaseModule(insname),
+        p_clk("clk"),
+        p_resetn("resetn"),
+
+        signal_dspin_cmd_l2g_d("signal_dspin_cmd_l2g_d"),
+        signal_dspin_cmd_g2l_d("signal_dspin_cmd_g2l_d"),
+        signal_dspin_cmd_l2g_c("signal_dspin_cmd_l2g_c"),
+        signal_dspin_cmd_g2l_c("signal_dspin_cmd_g2l_c"),
+        signal_dspin_rsp_l2g_d("signal_dspin_rsp_l2g_d"),
+        signal_dspin_rsp_g2l_d("signal_dspin_rsp_g2l_d"),
+        signal_dspin_rsp_l2g_c("signal_dspin_rsp_l2g_c"),
+        signal_dspin_rsp_g2l_c("signal_dspin_rsp_g2l_c"),
+
+	signal_vci_ini_d_bdev("signal_vci_ini_d_bdev"),
+	signal_vci_ini_d_mdma("signal_vci_ini_d_mdma"),
+
+        signal_vci_tgt_d_memc("signal_vci_tgt_d_memc"),
+        signal_vci_tgt_d_mtty("signal_vci_tgt_d_mtty"),
+        signal_vci_tgt_d_xicu("signal_vci_tgt_d_xicu"),
+        signal_vci_tgt_d_bdev("signal_vci_tgt_d_bdev"),
+        signal_vci_tgt_d_mdma("signal_vci_tgt_d_mdma"),
+        signal_vci_tgt_d_brom("signal_vci_tgt_d_brom"),
+        signal_vci_tgt_d_fbuf("signal_vci_tgt_d_fbuf"),
+
+        signal_vci_ini_c_memc("signal_vci_ini_c_memc"), 
+        signal_vci_tgt_c_memc("signal_vci_tgt_c_memc"),
+
+        signal_vci_xram("signal_vci_xram")
+
+{
+        // Vectors of ports definition
+
+        p_cmd_in        = alloc_elems<DspinInput<cmd_width> >("p_cmd_in", 2, 4);
+        p_cmd_out       = alloc_elems<DspinOutput<cmd_width> >("p_cmd_out", 2, 4);
+        p_rsp_in        = alloc_elems<DspinInput<rsp_width> >("p_rsp_in", 2, 4);
+        p_rsp_out       = alloc_elems<DspinOutput<rsp_width> >("p_rsp_out", 2, 4);
+
+        // Components definition 
+
+        // on direct network : local srcid[proc] in [0...nprocs-1]
+        // on direct network : local srcid[mdma] = nprocs
+        // on direct network : local srcid[bdev] = nprocs + 1
+
+        // on coherence network : local srcid[proc] in [0...nprocs-1]
+	// on coherence network : local srcid[memc] = nprocs
+
+std::cout << "  - building proc_" << x_id << "_" << y_id << "-*" << std::endl;
+
+        for ( size_t p=0 ; p<nprocs ; p++ )
+        { 
+            std::ostringstream sproc;
+            sproc << "proc_" << x_id << "_" << y_id << "_" << p;
+            proc[p] = new VciCcXCacheWrapperV4<vci_param, iss_t>(
+                sproc.str().c_str(),
+                cluster_id*nprocs + p,
+                mtd,				// Mapping Table Direct
+                mtc,				// Mapping Table Coherence
+                IntTab(cluster_id,p),    	// SRCID_D
+                IntTab(cluster_id,p),    	// SRCID_C
+                IntTab(cluster_id,p),    	// TGTID_C
+                1,				// single core
+                1,				// single dcache
+                l1_i_ways,l1_i_sets,16,  	// ICACHE size
+                l1_d_ways,l1_d_sets,16,      	// DCACHE size
+                4,				// WBUF width
+                8 				// WBUF depth
+                );
+        }
+
+std::cout << "  - building memc_" << x_id << "_" << y_id << std::endl;
+
+        std::ostringstream smemc;
+        smemc << "memc_" << x_id << "_" << y_id;
+        memc = new VciMemCacheV4<vci_param>(
+                   smemc.str().c_str(),
+                   mtd, mtc, mtx,
+                   IntTab(cluster_id),           	// SRCID_X
+                   IntTab(cluster_id, nprocs),   	// SRCID_C
+                   IntTab(cluster_id, tgtid_memc),	// TGTID_D
+                   IntTab(cluster_id, nprocs),   	// TGTID_C
+                   memc_ways, memc_sets, 16,	 	// CACHE SIZE
+                   4096,     			 	// HEAP SIZE
+                   8,					// TRANSACTION TABLE DEPTH
+                   8);					// UPDATE TABLE DEPTH
+
+        
+std::cout << "  - building xram_" << x_id << "_" << y_id << std::endl;
+
+        std::ostringstream sxram;
+        sxram << "xram_" << x_id << "_" << y_id;
+        xram = new VciSimpleRam<vci_param>(
+                   sxram.str().c_str(),
+                   IntTab(cluster_id),
+                   mtx,
+                   loader,
+                   xram_latency);
+
+std::cout << "  - building xicu_" << x_id << "_" << y_id << std::endl;
+
+        size_t  nhwi = 8;				// always 8 (or 9) ports, even if 
+        if( io == true ) nhwi = 9;			// there if less than 4 processors
+        std::ostringstream sicu;
+        sicu << "xicu_" << x_id << "_" << y_id;
+        xicu = new VciXicu<vci_param>(
+                  sicu.str().c_str(),
+                  mtd,				  	// mapping table
+                  IntTab(cluster_id, tgtid_xicu),  	// TGTID_D
+                  0,					// number of timer IRQs
+                  nhwi,                          	// number of hard IRQs
+                  0,					// number of soft IRQs
+                  nprocs);				// number of output IRQs
+
+std::cout << "  - building tty_" << x_id << "_" << y_id << std::endl;
+
+        // tty
+        std::ostringstream stty;
+        stty << "tty_" << x_id << "_" << y_id;
+        mtty = new VciMultiTty<vci_param>(
+                   stty.str().c_str(),
+                   IntTab(cluster_id, tgtid_mtty),
+                   mtd, stty.str().c_str(), NULL);
+        
+std::cout << "  - building dma_" << x_id << "_" << y_id << std::endl;
+
+        // dma
+        std::ostringstream sdma;
+        sdma << "dma_" << x_id << "_" << y_id;
+        mdma = new VciMultiDma<vci_param>(
+                   sdma.str().c_str(),
+                   mtd,
+                   IntTab(cluster_id, nprocs),		// SRCID
+                   IntTab(cluster_id, tgtid_mdma),	// TGTID
+                   64,					// burst size
+                   nprocs);				// number of IRQs
+
+std::cout << "  - building xbard_" << x_id << "_" << y_id << std::endl;
+
+        // direct local crossbar
+        size_t nb_direct_initiators      = nprocs + 1;
+        size_t nb_direct_targets         = 4;
+        if( io == true )
+        {
+            nb_direct_initiators         = nprocs + 2;
+            nb_direct_targets            = 7;
+	}
+        std::ostringstream sd;
+        sd << "xbard_" << x_id << "_" << y_id;
+        xbard = new VciLocalCrossbar<vci_param>(
+                    sd.str().c_str(),
+                    mtd,
+                    IntTab(cluster_id),              	// cluster initiator index
+                    IntTab(cluster_id),              	// cluster target index
+                    nb_direct_initiators,           	// number of initiators
+                    nb_direct_targets);             	// number of targets      
+        
+std::cout << "  - building xbarc_" << x_id << "_" << y_id << std::endl;
+
+        // coherence local crossbar
+        std::ostringstream sc;
+        sc << "xbarc_" << x_id << "_" << y_id;
+        xbarc = new VciLocalCrossbar<vci_param>(
+                    sc.str().c_str(),
+                    mtc,
+                    IntTab(cluster_id),                	// cluster initiator index
+                    IntTab(cluster_id),                	// cluster target index
+                    nprocs + 1,                		// number of initiators
+                    nprocs + 1);               		// number of targets
+        
+std::cout << "  - building wrappers in cluster_" << x_id << "_" << y_id << std::endl;
+
+        // direct initiator wrapper
+        std::ostringstream wid;
+        wid << "iniwrapperd_" << x_id << "_" << y_id;
+        iniwrapperd = new VciVdspinInitiatorWrapper<vci_param,cmd_width,rsp_width>(
+                          wid.str().c_str(),
+                          4,				// cmd fifo depth
+                          4);				// rsp fifo depth
+
+        // direct target wrapper
+        std::ostringstream wtd;
+        wtd << "tgtwrapperd_" << x_id << "_" << y_id;
+        tgtwrapperd = new VciVdspinTargetWrapper<vci_param,cmd_width,rsp_width>(
+                          wtd.str().c_str(),
+                          4,				// cmd fifo depth
+                          4);				// rsp fifo depth
+
+        // coherence initiator wrapper
+        std::ostringstream wic;
+        wic << "iniwrapperc_" << x_id << "_" << y_id;
+        iniwrapperc = new VciVdspinInitiatorWrapper<vci_param,cmd_width,rsp_width>(
+                          wic.str().c_str(),
+                          4,				// cmd fifo depth
+                          4);				// rsp fifo depth
+
+        // coherence target wrapper
+        std::ostringstream wtc;
+        wtc << "tgtwrapperc_" << x_id << "_" << y_id;
+        tgtwrapperc = new VciVdspinTargetWrapper<vci_param,cmd_width,rsp_width>(
+                          wtc.str().c_str(),
+                          4,				// cmd fifo depth
+                          4);				// rsp fifo depth
+
+std::cout << "  - building cmdrouter_" << x_id << "_" << y_id << std::endl;
+
+        // CMD router
+        std::ostringstream scmd;
+        scmd << "cmdrouter_" << x_id << "_" << y_id;
+        cmdrouter = new VirtualDspinRouter<cmd_width>(
+                        scmd.str().c_str(),
+                        x_id,y_id,                    // coordinate in the mesh
+                        x_width, y_width,             // x & y fields width
+                        4,4);                         // input & output fifo depths
+        
+std::cout << "  - building rsprouter_" << x_id << "_" << y_id << std::endl;
+
+        // RSP router
+        std::ostringstream srsp;
+        srsp << "rsprouter_" << x_id << "_" << y_id;
+        rsprouter = new VirtualDspinRouter<rsp_width>(
+                        srsp.str().c_str(),
+                        x_id,y_id,                    // coordinates in mesh
+                        x_width, y_width,             // x & y fields width
+                        4,4);                         // input & output fifo depths
+        
+        // IO cluster components
+        if ( io == true )
+	{
+            brom = new VciSimpleRam<vci_param>(
+                       "brom",
+                       IntTab(cluster_id, tgtid_brom),
+                       mtd,
+                       loader);
+
+            fbuf = new VciFrameBuffer<vci_param>(
+                       "fbuf",
+                       IntTab(cluster_id, tgtid_fbuf),
+                       mtd,
+		       xfb, yfb); 
+
+            bdev = new VciBlockDeviceTsarV4<vci_param>(
+                       "bdev",
+                       mtd,
+                       IntTab(cluster_id, nprocs+1),
+                       IntTab(cluster_id, tgtid_bdev),
+                       disk_name,
+                       block_size);
+	}
+
+std::cout << "  - all components constructed" << std::endl;
+
+        ////////////////////////////////////
+        // Connections are defined here
+        ////////////////////////////////////
+
+        // CMDROUTER and RSPROUTER
+        cmdrouter->p_clk                	(this->p_clk);
+        cmdrouter->p_resetn             	(this->p_resetn);
+        rsprouter->p_clk                	(this->p_clk);
+        rsprouter->p_resetn             	(this->p_resetn);
+        for(int x = 0; x < 2; x++)
+        {
+          for(int y = 0; y < 4; y++)
+          {
+            cmdrouter->p_out[x][y]              (this->p_cmd_out[x][y]);
+            cmdrouter->p_in[x][y]               (this->p_cmd_in[x][y]);
+            rsprouter->p_out[x][y]              (this->p_rsp_out[x][y]);
+            rsprouter->p_in[x][y]               (this->p_rsp_in[x][y]);
+          }
+        }
+        
+        cmdrouter->p_out[0][4]  		(signal_dspin_cmd_g2l_d);
+        cmdrouter->p_out[1][4]  		(signal_dspin_cmd_g2l_c);
+        cmdrouter->p_in[0][4]   		(signal_dspin_cmd_l2g_d);
+        cmdrouter->p_in[1][4]   		(signal_dspin_cmd_l2g_c);
+
+        rsprouter->p_out[0][4]  		(signal_dspin_rsp_g2l_d);
+        rsprouter->p_out[1][4]  		(signal_dspin_rsp_g2l_c);
+        rsprouter->p_in[0][4]   		(signal_dspin_rsp_l2g_d);
+        rsprouter->p_in[1][4]   		(signal_dspin_rsp_l2g_c);
+
+        // VCI/DSPIN WRAPPERS
+        iniwrapperd->p_clk			(this->p_clk);
+        iniwrapperd->p_resetn			(this->p_resetn);
+	iniwrapperd->p_vci			(signal_vci_l2g_d);
+	iniwrapperd->p_dspin_out		(signal_dspin_cmd_l2g_d);
+	iniwrapperd->p_dspin_in			(signal_dspin_rsp_g2l_d);
+
+        tgtwrapperd->p_clk			(this->p_clk);
+        tgtwrapperd->p_resetn			(this->p_resetn);
+	tgtwrapperd->p_vci			(signal_vci_g2l_d);
+	tgtwrapperd->p_dspin_out		(signal_dspin_rsp_l2g_d);
+	tgtwrapperd->p_dspin_in			(signal_dspin_cmd_g2l_d);
+
+        iniwrapperc->p_clk			(this->p_clk);
+        iniwrapperc->p_resetn			(this->p_resetn);
+	iniwrapperc->p_vci			(signal_vci_l2g_c);
+	iniwrapperc->p_dspin_out		(signal_dspin_cmd_l2g_c);
+	iniwrapperc->p_dspin_in			(signal_dspin_rsp_g2l_c);
+
+        tgtwrapperc->p_clk			(this->p_clk);
+        tgtwrapperc->p_resetn			(this->p_resetn);
+	tgtwrapperc->p_vci			(signal_vci_g2l_c);
+	tgtwrapperc->p_dspin_out		(signal_dspin_rsp_l2g_c);
+	tgtwrapperc->p_dspin_in			(signal_dspin_cmd_g2l_c);
+
+        // CROSSBAR direct
+        xbard->p_clk                  		(this->p_clk);
+        xbard->p_resetn                 	(this->p_resetn);
+        xbard->p_initiator_to_up        	(signal_vci_l2g_d);
+        xbard->p_target_to_up           	(signal_vci_g2l_d);
+          
+        xbard->p_to_target[tgtid_memc]  	(signal_vci_tgt_d_memc);
+        xbard->p_to_target[tgtid_xicu]  	(signal_vci_tgt_d_xicu);
+        xbard->p_to_target[tgtid_mtty]  	(signal_vci_tgt_d_mtty);
+        xbard->p_to_target[tgtid_mdma]  	(signal_vci_tgt_d_mdma);
+          
+        xbard->p_to_initiator[nprocs]  		(signal_vci_ini_d_mdma);
+        for ( size_t p=0 ; p<nprocs ; p++)
+        {
+            xbard->p_to_initiator[p]		(signal_vci_ini_d_proc[p]);
+        }
+
+	if ( io == true )
+	{
+            xbard->p_to_target[tgtid_brom]  	(signal_vci_tgt_d_brom);
+            xbard->p_to_target[tgtid_bdev]  	(signal_vci_tgt_d_bdev);
+            xbard->p_to_target[tgtid_fbuf]  	(signal_vci_tgt_d_fbuf);
+            
+            xbard->p_to_initiator[nprocs+1]  	(signal_vci_ini_d_bdev);
+	}
+        
+        // CROSSBAR coherence
+        xbarc->p_clk                    	(this->p_clk);
+        xbarc->p_resetn                 	(this->p_resetn);
+        xbarc->p_initiator_to_up        	(signal_vci_l2g_c);
+        xbarc->p_target_to_up           	(signal_vci_g2l_c);
+        xbarc->p_to_initiator[nprocs]  		(signal_vci_ini_c_memc);
+        xbarc->p_to_target[nprocs]     		(signal_vci_tgt_c_memc);
+        for ( size_t p=0 ; p<nprocs ; p++)
+        {
+            xbarc->p_to_target[p]       	(signal_vci_tgt_c_proc[p]);
+            xbarc->p_to_initiator[p]    	(signal_vci_ini_c_proc[p]);
+        }
+
+        // Processors
+        for ( size_t p=0 ; p<nprocs ; p++)
+        {
+            proc[p]->p_clk              	(this->p_clk);
+            proc[p]->p_resetn           	(this->p_resetn);
+            proc[p]->p_vci_ini_rw       	(signal_vci_ini_d_proc[p]);
+            proc[p]->p_vci_ini_c        	(signal_vci_ini_c_proc[p]);
+            proc[p]->p_vci_tgt          	(signal_vci_tgt_c_proc[p]);
+            proc[p]->p_irq[0][0]           	(signal_proc_it[p]);
+            for ( size_t j = 1 ; j < 6 ; j++ )
+            {
+                proc[p]->p_irq[0][j]       	(signal_false);
+            }
+        }
+        
+        // XICU
+        xicu->p_clk                     	(this->p_clk);
+        xicu->p_resetn                  	(this->p_resetn);
+        xicu->p_vci                     	(signal_vci_tgt_d_xicu);
+        for ( size_t p=0 ; p<nprocs ; p++)
+        {
+            xicu->p_irq[p]              	(signal_proc_it[p]);
+        }
+        xicu->p_hwi[0]				(signal_irq_mtty);
+        xicu->p_hwi[1]				(signal_false);
+        xicu->p_hwi[2]				(signal_false);
+        xicu->p_hwi[3]				(signal_false);
+        for ( size_t p=0 ; p<nprocs ; p++)
+        {
+            xicu->p_hwi[p+4]			(signal_irq_mdma[p]);
+        }
+        for ( size_t x=nprocs ; x<4 ; x++)
+        {
+            xicu->p_hwi[x+4]			(signal_false);
+        }
+        if ( io == true )
+	{
+            xicu->p_hwi[8]			(signal_irq_bdev);
+	}
+
+        // MEMC
+        memc->p_clk                     	(this->p_clk);
+        memc->p_resetn                  	(this->p_resetn);
+        memc->p_vci_ixr                 	(signal_vci_xram);
+        memc->p_vci_tgt                 	(signal_vci_tgt_d_memc);
+        memc->p_vci_ini                 	(signal_vci_ini_c_memc);
+        memc->p_vci_tgt_cleanup         	(signal_vci_tgt_c_memc);
+
+        // XRAM
+        xram->p_clk                     	(this->p_clk);
+        xram->p_resetn                  	(this->p_resetn);
+        xram->p_vci                 		(signal_vci_xram);
+
+        // MTTY
+        mtty->p_clk                       	(this->p_clk);
+        mtty->p_resetn                    	(this->p_resetn);
+        mtty->p_vci                       	(signal_vci_tgt_d_mtty);
+        mtty->p_irq[0]           		(signal_irq_mtty);
+
+        // CDMA
+        mdma->p_clk                       	(this->p_clk);
+        mdma->p_resetn                    	(this->p_resetn);
+        mdma->p_vci_target                	(signal_vci_tgt_d_mdma);
+        mdma->p_vci_initiator             	(signal_vci_ini_d_mdma);
+        for (size_t p=0 ; p<nprocs ; p++)
+        {
+            mdma->p_irq[p]                       (signal_irq_mdma[p]);
+        }
+
+	// Components in IO cluster
+
+	if ( io == true )
+	{
+        	// BDEV            
+		bdev->p_clk                      (this->p_clk);
+        	bdev->p_resetn                   (this->p_resetn);
+        	bdev->p_irq                      (signal_irq_bdev);
+        	bdev->p_vci_target               (signal_vci_tgt_d_bdev);
+        	bdev->p_vci_initiator            (signal_vci_ini_d_bdev);
+
+        	// FBUF
+        	fbuf->p_clk                       (this->p_clk);
+        	fbuf->p_resetn                    (this->p_resetn);
+        	fbuf->p_vci                       (signal_vci_tgt_d_fbuf);
+
+        	// BROM
+        	brom->p_clk                       (this->p_clk);
+        	brom->p_resetn                    (this->p_resetn);
+        	brom->p_vci                       (signal_vci_tgt_d_brom);
+
+        }
+} // end constructor
+
+///////////////////////////////////////////////////////////////////////////
+//    destructor
+///////////////////////////////////////////////////////////////////////////
+template<typename vci_param, typename iss_t, int cmd_width, int rsp_width>
+TsarV4ClusterXbar<vci_param, iss_t, cmd_width, rsp_width>::~TsarV4ClusterXbar() {}
+
+}}
Index: branches/v4/platforms/tsarv4_mono_mmu/Makefile
===================================================================
--- branches/v4/platforms/tsarv4_mono_mmu/Makefile	(revision 371)
+++ branches/v4/platforms/tsarv4_mono_mmu/Makefile	(revision 371)
@@ -0,0 +1,7 @@
+simul.x: top.cpp top.desc
+	soclib-cc -j8 -P -p top.desc -I. -o simul.x
+
+clean:
+	soclib-cc -x -p top.desc -I.
+	rm -rf *.o *.x tty*
+
Index: branches/v4/platforms/tsarv4_mono_mmu/top.cpp
===================================================================
--- branches/v4/platforms/tsarv4_mono_mmu/top.cpp	(revision 371)
+++ branches/v4/platforms/tsarv4_mono_mmu/top.cpp	(revision 371)
@@ -0,0 +1,393 @@
+
+#include <systemc>
+#include <sys/time.h>
+#include <iostream>
+#include <cstdlib>
+#include <cstdarg>
+
+#ifdef _OPENMP
+#include <omp.h>
+#endif
+
+#include "mapping_table.h"
+#include "mips32.h"
+#include "vci_simple_ram.h"
+#include "vci_multi_tty.h"
+#include "vci_vgmn.h"
+#include "vci_mem_cache_v4.h"
+#include "vci_cc_vcache_wrapper_v4.h"
+#include "vci_xicu.h"
+#include "vci_simhelper.h"
+#include "vci_multi_dma.h"
+
+// VCI format
+
+#define    cell_width	         4
+#define    address_width	 32
+#define    plen_width	         8
+#define    error_width	         2
+#define    clen_width	         1
+#define    rflag_width	         1
+#define    srcid_width	         14
+#define    pktid_width	         4
+#define    trdid_width	         4
+#define    wrplen_width	         1
+
+//   segments definition in direct space
+
+#define    XICU_BASE	0xd8200000
+#define    XICU_SIZE	0x00001000
+
+#define	   MDMA_BASE	0xe8000000
+#define	   MDMA_SIZE	0x00000014
+
+#define    MTTY_BASE	0xd0200000
+#define    MTTY_SIZE	0x00000010
+
+#define    EXIT_BASE	0xe0000000
+#define    EXIT_SIZE	0x00000010
+
+#define    BOOT_BASE	0xbfc00000
+#define    BOOT_SIZE	0x00040000
+
+#define    MEMC_BASE    0x00000000
+#define    MEMC_SIZE    0x02000000
+
+/////////////////////////////////
+int _main(int argc, char *argv[])
+{
+
+using namespace sc_core;
+using namespace soclib::common;
+using namespace soclib::caba;
+
+#ifdef _OPENMP
+        omp_set_dynamic(false);
+	omp_set_num_threads(1);
+	std::cerr << "Built with openmp version " << _OPENMP << std::endl;
+#endif
+
+    char	soft_name[256] 	= "test.elf";	// pathname to binary code
+    size_t	ncycles		= 1000000000;	// max number of simulation cycles
+    bool	trace_ok	= false;
+    size_t	from_cycle	= 0;		// debug start cycle 
+    size_t	max_frozen	= 1000;		// max number of frozen cycles
+    size_t      nprocs          = 1;    
+
+    /////////////// command line arguments ////////////////
+    if (argc > 1)
+    {
+        for( int n=1 ; n<argc ; n=n+2 )
+        {
+            if( (strcmp(argv[n],"-NCYCLES") == 0) && (n+1<argc) )
+            {
+                ncycles = atoi(argv[n+1]);
+            }
+            else if( (strcmp(argv[n],"-SOFT") == 0) && (n+1<argc) )
+            {
+                strcpy(soft_name, argv[n+1]);
+            }
+            else if( (strcmp(argv[n],"-TRACE") == 0) && (n+1<argc) )
+            {
+                trace_ok = true;
+                from_cycle = atoi(argv[n+1]);
+            }
+            else if( (strcmp(argv[n],"-MAXFROZEN") == 0) && (n+1<argc) )
+            {
+                max_frozen = atoi(argv[n+1]);
+            }
+            else
+            {
+                std::cout << "   Arguments on the command line are (key,value) couples." << std::endl;
+                std::cout << "   The order is not important." << std::endl;
+                std::cout << "   Accepted arguments are :" << std::endl << std::endl;
+                std::cout << "     -SOFT pathname_for_embedded_soft" << std::endl;
+                std::cout << "     -NCYCLES number_of_simulated_cycles" << std::endl;
+                std::cout << "     -TRACE debug_start_cycle" << std::endl;
+                exit(0);
+            }
+        }
+    }
+
+    // Define VCI parameters
+    typedef VciParams<cell_width,
+                                    plen_width,
+                                    address_width,
+                                    error_width,
+                                    clen_width,
+                                    rflag_width,
+                                    srcid_width,
+                                    pktid_width,
+                                    trdid_width,
+                                    wrplen_width> vci_param;
+
+    // Define processor type
+    typedef soclib::common::Mips32ElIss proc_iss;
+
+    // Mapping table for direct network
+    soclib::common::MappingTable maptabd(32, IntTab(6), IntTab(6), 0xF0000000);
+    maptabd.add(Segment("memc_d" , MEMC_BASE , MEMC_SIZE , IntTab(0), true));
+    maptabd.add(Segment("boot_d" , BOOT_BASE , BOOT_SIZE , IntTab(1), true));
+    maptabd.add(Segment("exit_d" , EXIT_BASE , EXIT_SIZE , IntTab(2), false));
+    maptabd.add(Segment("mtty_d" , MTTY_BASE , MTTY_SIZE , IntTab(3), false));
+    maptabd.add(Segment("xicu_d" , XICU_BASE , XICU_SIZE , IntTab(4), false));
+    maptabd.add(Segment("mdma_d" , MDMA_BASE , MDMA_SIZE , IntTab(5), false));
+    std::cout << maptabd << std::endl;
+
+    // Mapping table for coherence network
+    soclib::common::MappingTable maptabc(32, IntTab(srcid_width), IntTab(srcid_width), 0xF0000000);
+    maptabc.add(
+        Segment( "proc_c"
+                , 0x0000000
+                , 0x10
+                , IntTab(0)
+                , false
+        )
+    );
+
+    maptabc.add(
+        Segment( "memc_c"
+                , nprocs << (address_width - srcid_width)
+                , 0x10
+                , IntTab(nprocs)
+                , false
+        )
+    );
+    std::cout << maptabc << std::endl;
+	
+    // Signals
+
+    sc_clock        signal_clk			("signal_clk");
+    sc_signal<bool> signal_resetn		("isgnal_resetn");
+   
+    sc_signal<bool> signal_mdma_irq		("signal_mdma_irq");
+    sc_signal<bool> signal_mtty_irq		("signal_mtty_irq");
+    sc_signal<bool> signal_proc_irq		("signal_proc_irq"); 
+    sc_signal<bool> signal_false		("signal_false");
+
+    VciSignals<vci_param> signal_vci_ini_d_proc	("vci_ini_d_proc");
+    VciSignals<vci_param> signal_vci_ini_c_proc	("vci_ini_c_proc");
+    VciSignals<vci_param> signal_vci_tgt_c_proc	("vci_tgt_c_proc");
+
+    VciSignals<vci_param> signal_vci_tgt_d_mtty	("signal_vci_tgt_d_mtty");
+
+    VciSignals<vci_param> signal_vci_tgt_d_exit	("signal_vci_tgt_d_exit");
+
+    VciSignals<vci_param> signal_vci_tgt_d_xicu	("signal_vci_tgt_d_xicu");
+
+    VciSignals<vci_param> signal_vci_ini_d_mdma	("signal_vci_ini_d_mdma");
+    VciSignals<vci_param> signal_vci_tgt_d_mdma	("signal_vci_tgt_d_mdma");
+
+    VciSignals<vci_param> signal_vci_tgt_d_brom ("signal_vci_tgt_d_brom");
+
+
+    VciSignals<vci_param> signal_vci_ini_c_memc ("signal_vci_ini_c_memc");
+    VciSignals<vci_param> signal_vci_tgt_d_memc ("signal_vci_tgt_d_memc");
+    VciSignals<vci_param> signal_vci_tgt_c_memc ("signal_vci_tgt_c_memc");
+
+    VciSignals<vci_param> signal_vci_xram	("signal_vci_xram");
+
+    // Components
+
+    soclib::common::Loader loader(soft_name);
+
+    VciCcVCacheWrapperV4<vci_param, proc_iss > 
+    proc("proc", 
+         0,			// proc_id 
+         maptabd, 		// direct space
+         maptabc, 		// coherence space
+         IntTab(0),		// srcid_d
+         IntTab(0),		// srcid_c
+         IntTab(0),		// tgtid_c
+         8,8,			// itlb size
+         8,8,			// dtlb size
+         4,64,16,		// icache size
+         4,64,16,		// dcache size
+         4, 4, 			// wbuf size
+         0, 0,                  // x, y Width
+         nprocs,                // memory cache local id
+         max_frozen,		// max frozen cycles
+         from_cycle, trace_ok);
+
+    VciSimpleRam<vci_param> 
+    rom("rom", 
+         IntTab(1), 		// tgtid_d
+         maptabd, 
+         loader);
+
+    VciSimpleRam<vci_param> 
+    xram("xram", 
+         IntTab(0),		// tgtid_d(RAM) = tgtid_d(MEMC) 
+         maptabd, 
+         loader);
+
+    VciMemCacheV4<vci_param> 
+    memc("memc",
+         maptabd,
+         maptabc,
+         maptabd,
+         IntTab(0),		// srcid_x
+         IntTab(1),		// srcid_c
+         IntTab(0), 		// tgtid_d
+         IntTab(1),		// tgtid_c
+         16,256,16, 		// cache size
+         1024,			// HEAP size
+         4,			// TRT size
+         4,			// UPT size
+         from_cycle, trace_ok);
+       
+    VciSimhelper<vci_param> 
+    vciexit("vciexit",
+         IntTab(2), 		// tgtid_d
+         maptabd);
+
+    VciXicu<vci_param> 
+    xicu("xicu", 
+         maptabd,
+         IntTab(4),		// tgtid_d
+         1,			// number of timers
+         2,			// number of hard interrupts 
+         0,			// number of soft interrupts
+         1);			// number of output IRQs
+
+    VciMultiTty<vci_param> 
+    mtty("mtty", 
+         IntTab(3),		// tgtid_d 
+         maptabd, 
+         "mtty0", NULL);
+
+    VciMultiDma<vci_param>
+    mdma("mdma", 
+         maptabd, 
+         IntTab(1),		// srcid_d 
+         IntTab(5), 		// tgtid_d
+         64,			// burst size
+         1);			// number of channels 
+	
+    VciVgmn<vci_param> 
+    ringd("ringd",
+         maptabd, 
+         2, 			// number of initiators
+         6, 			// number of targets
+         2, 
+         8);
+
+    VciVgmn<vci_param> 
+    ringc("ringc",
+         maptabc, 
+         2, 			// number of initiators
+         2, 			// number of targets
+         2, 
+         8);
+
+    // net-list
+    proc.p_clk(signal_clk);  
+    proc.p_resetn		(signal_resetn);  
+    proc.p_irq[0]		(signal_proc_irq); 
+    proc.p_irq[1]		(signal_false); 
+    proc.p_irq[2]		(signal_false); 
+    proc.p_irq[3]		(signal_false); 
+    proc.p_irq[4]		(signal_false); 
+    proc.p_irq[5]		(signal_false); 
+    proc.p_vci_ini_d		(signal_vci_ini_d_proc);
+    proc.p_vci_ini_c		(signal_vci_ini_c_proc);
+    proc.p_vci_tgt_c		(signal_vci_tgt_c_proc);
+
+    rom.p_clk			(signal_clk);
+    rom.p_resetn		(signal_resetn);
+    rom.p_vci			(signal_vci_tgt_d_brom);
+
+    xicu.p_resetn		(signal_resetn);
+    xicu.p_clk			(signal_clk);
+    xicu.p_vci			(signal_vci_tgt_d_xicu);
+    xicu.p_hwi[0]		(signal_mtty_irq);
+    xicu.p_hwi[1]		(signal_mdma_irq);
+    xicu.p_irq[0]		(signal_proc_irq);
+
+    mdma.p_clk			(signal_clk);
+    mdma.p_resetn		(signal_resetn);
+    mdma.p_vci_target		(signal_vci_tgt_d_mdma);
+    mdma.p_vci_initiator	(signal_vci_ini_d_mdma);
+    mdma.p_irq[0]		(signal_mdma_irq); 
+
+    mtty.p_clk			(signal_clk);
+    mtty.p_resetn		(signal_resetn);
+    mtty.p_vci			(signal_vci_tgt_d_mtty);
+    mtty.p_irq[0]		(signal_mtty_irq); 
+
+    vciexit.p_clk		(signal_clk);
+    vciexit.p_resetn		(signal_resetn);
+    vciexit.p_vci		(signal_vci_tgt_d_exit);
+
+    memc.p_clk			(signal_clk);
+    memc.p_resetn		(signal_resetn);
+    memc.p_vci_tgt		(signal_vci_tgt_d_memc);
+    memc.p_vci_tgt_cleanup	(signal_vci_tgt_c_memc);
+    memc.p_vci_ini		(signal_vci_ini_c_memc);
+    memc.p_vci_ixr		(signal_vci_xram);
+
+    xram.p_clk			(signal_clk);
+    xram.p_resetn		(signal_resetn);
+    xram.p_vci			(signal_vci_xram);
+	
+    ringc.p_clk			(signal_clk);
+    ringc.p_resetn		(signal_resetn);
+    ringc.p_to_initiator[0]	(signal_vci_ini_c_proc);
+    ringc.p_to_initiator[1]	(signal_vci_ini_c_memc);
+    ringc.p_to_target[0]	(signal_vci_tgt_c_proc);
+    ringc.p_to_target[1]	(signal_vci_tgt_c_memc);
+
+    ringd.p_clk			(signal_clk);
+    ringd.p_resetn		(signal_resetn);
+    ringd.p_to_initiator[0]	(signal_vci_ini_d_proc);
+    ringd.p_to_initiator[1]	(signal_vci_ini_d_mdma);
+    ringd.p_to_target[0]	(signal_vci_tgt_d_memc);
+    ringd.p_to_target[1]	(signal_vci_tgt_d_brom);
+    ringd.p_to_target[2]	(signal_vci_tgt_d_exit);
+    ringd.p_to_target[3]	(signal_vci_tgt_d_mtty);
+    ringd.p_to_target[4]	(signal_vci_tgt_d_xicu);
+    ringd.p_to_target[5]	(signal_vci_tgt_d_mdma);
+	
+    // simulation loop
+
+    sc_start(sc_core::sc_time(0, SC_NS));
+    signal_resetn = false;
+
+    sc_start(sc_core::sc_time(1, SC_NS));
+    signal_resetn = true;
+        
+    signal_false = false;
+
+    for ( size_t n=1 ; n<ncycles ; n++ )
+    {
+        if ( trace_ok and (n > from_cycle) )
+        {
+            std::cout << "****************** cycle " << std::dec << n
+                      << " ************************************************" << std::endl;
+            proc.print_trace();
+            memc.print_trace();
+            signal_vci_ini_d_proc.print_trace("proc_ini_d");
+            signal_vci_tgt_c_proc.print_trace("proc_tgt_c");
+            signal_vci_ini_c_proc.print_trace("proc_ini_c");
+            signal_vci_tgt_d_memc.print_trace("memc_tgt_d");
+            signal_vci_tgt_c_memc.print_trace("memc_tgt_c");
+            signal_vci_ini_c_memc.print_trace("memc_ini_c");
+            if ( signal_proc_irq.read() ) std::cout << "---- IRQ ----" << std::endl;
+        }
+        sc_start(sc_core::sc_time(1, SC_NS));
+    }
+    return EXIT_SUCCESS;
+}
+
+int sc_main (int argc, char *argv[])
+{
+	try {
+		return _main(argc, argv);
+	} catch (std::exception &e) {
+		std::cout << e.what() << std::endl;
+	} catch (...) {
+		std::cout << "Unknown exception occured" << std::endl;
+		throw;
+	}
+	return 1;
+}
Index: branches/v4/platforms/tsarv4_mono_mmu/top.desc
===================================================================
--- branches/v4/platforms/tsarv4_mono_mmu/top.desc	(revision 371)
+++ branches/v4/platforms/tsarv4_mono_mmu/top.desc	(revision 371)
@@ -0,0 +1,29 @@
+
+# -*- python -*-
+
+todo = Platform('caba', 'top.cpp',
+                uses = [
+	Uses('common:mapping_table'),
+	Uses('caba:vci_cc_vcache_wrapper_v4', iss_t = 'common:mips32el'),
+	Uses('caba:vci_simple_ram'),
+        Uses('caba:vci_logger'),
+	Uses('caba:vci_multi_tty'),
+        Uses('caba:vci_xicu'),
+        Uses('caba:vci_multi_dma'),
+	Uses('caba:vci_vgmn'),
+	Uses('caba:vci_simhelper'),
+	Uses('caba:vci_mem_cache_v4'),
+	Uses('common:elf_file_loader'),
+	],
+	cell_size = 4,
+	plen_size = 8,
+	addr_size = 32,
+	rerror_size = 2,
+	clen_size = 1,
+	rflag_size = 1,
+	srcid_size = 14,
+	pktid_size = 4,
+	trdid_size = 4,
+	wrplen_size = 1
+)
+
Index: branches/v4/platforms/tsarv4_mono_nommu/Makefile
===================================================================
--- branches/v4/platforms/tsarv4_mono_nommu/Makefile	(revision 371)
+++ branches/v4/platforms/tsarv4_mono_nommu/Makefile	(revision 371)
@@ -0,0 +1,7 @@
+simul.x: top.cpp top.desc
+	soclib-cc -P -p top.desc -I. -o simul.x
+
+clean:
+	soclib-cc -x -p top.desc -I.
+	rm -rf *.o *.x tty*
+
Index: branches/v4/platforms/tsarv4_mono_nommu/top.cpp
===================================================================
--- branches/v4/platforms/tsarv4_mono_nommu/top.cpp	(revision 371)
+++ branches/v4/platforms/tsarv4_mono_nommu/top.cpp	(revision 371)
@@ -0,0 +1,384 @@
+
+#include <systemc>
+#include <sys/time.h>
+#include <iostream>
+#include <cstdlib>
+#include <cstdarg>
+
+#ifdef _OPENMP
+#include <omp.h>
+#endif
+
+#include "mapping_table.h"
+#include "mips32.h"
+#include "vci_simple_ram.h"
+#include "vci_multi_tty.h"
+#include "vci_vgmn.h"
+#include "vci_mem_cache_v4.h"
+#include "vci_cc_xcache_wrapper_v4.h"
+#include "vci_xicu.h"
+#include "vci_simhelper.h"
+#include "vci_multi_dma.h"
+
+// VCI format
+
+#define    cell_width	         4
+#define    address_width	 32
+#define    plen_width	         8
+#define    error_width	         2
+#define    clen_width	         1
+#define    rflag_width	         1
+#define    srcid_width	         14
+#define    pktid_width	         4
+#define    trdid_width	         4
+#define    wrplen_width	         1
+
+//   segments definition in direct space
+
+#define    XICU_BASE	0xd8200000
+#define    XICU_SIZE	0x00001000
+
+#define	   MDMA_BASE	0xe8000000
+#define	   MDMA_SIZE	0x00000014
+
+#define    MTTY_BASE	0xd0200000
+#define    MTTY_SIZE	0x00000010
+
+#define    EXIT_BASE	0xe0000000
+#define    EXIT_SIZE	0x00000010
+
+#define    BOOT_BASE	0xbfc00000
+#define    BOOT_SIZE	0x00040000
+
+#define    MEMC_BASE    0x00000000
+#define    MEMC_SIZE    0x02000000
+
+//  segments definition in coherence space
+
+#define    C_L1_BASE	0x10000000
+#define    C_L1_SIZE	0x00000010
+
+#define    C_MC_BASE	0x00000000
+#define    C_MC_SIZE	0x02000010
+
+#define    C_BR_BASE	0xbfc00000
+#define    C_BR_SIZE	0x00040000
+
+/////////////////////////////////
+int _main(int argc, char *argv[])
+{
+
+using namespace sc_core;
+using namespace soclib::common;
+using namespace soclib::caba;
+
+#ifdef _OPENMP
+        omp_set_dynamic(false);
+	omp_set_num_threads(1);
+	std::cerr << "Built with openmp version " << _OPENMP << std::endl;
+#endif
+
+    char	soft_name[256] 	= "test.elf";	// pathname to binary code
+    size_t	ncycles		= 1000000000;	// max number of simulation cycles
+    bool	trace_ok	= false;
+    size_t	from_cycle	= 0;		// debug start cycle 
+    size_t	max_frozen	= 1000;		// max number of frozen cycles
+
+    /////////////// command line arguments ////////////////
+    if (argc > 1)
+    {
+        for( int n=1 ; n<argc ; n=n+2 )
+        {
+            if( (strcmp(argv[n],"-NCYCLES") == 0) && (n+1<argc) )
+            {
+                ncycles = atoi(argv[n+1]);
+            }
+            else if( (strcmp(argv[n],"-SOFT") == 0) && (n+1<argc) )
+            {
+                strcpy(soft_name, argv[n+1]);
+            }
+            else if( (strcmp(argv[n],"-TRACE") == 0) && (n+1<argc) )
+            {
+                trace_ok = true;
+                from_cycle = atoi(argv[n+1]);
+            }
+            else if( (strcmp(argv[n],"-MAXFROZEN") == 0) && (n+1<argc) )
+            {
+                max_frozen = atoi(argv[n+1]);
+            }
+            else
+            {
+                std::cout << "   Arguments on the command line are (key,value) couples." << std::endl;
+                std::cout << "   The order is not important." << std::endl;
+                std::cout << "   Accepted arguments are :" << std::endl << std::endl;
+                std::cout << "     -SOFT pathname_for_embedded_soft" << std::endl;
+                std::cout << "     -NCYCLES number_of_simulated_cycles" << std::endl;
+                std::cout << "     -TRACE debug_start_cycle" << std::endl;
+                exit(0);
+            }
+        }
+    }
+
+    // Define VCI parameters
+    typedef VciParams<cell_width,
+                                    plen_width,
+                                    address_width,
+                                    error_width,
+                                    clen_width,
+                                    rflag_width,
+                                    srcid_width,
+                                    pktid_width,
+                                    trdid_width,
+                                    wrplen_width> vci_param;
+
+    // Define processor type
+    typedef soclib::common::Mips32ElIss proc_iss;
+
+    // Mapping table for direct network
+    soclib::common::MappingTable maptabd(32, IntTab(6), IntTab(6), 0xF0000000);
+    maptabd.add(Segment("memc_d" , MEMC_BASE , MEMC_SIZE , IntTab(0), true));
+    maptabd.add(Segment("boot_d" , BOOT_BASE , BOOT_SIZE , IntTab(1), true));
+    maptabd.add(Segment("exit_d" , EXIT_BASE , EXIT_SIZE , IntTab(2), false));
+    maptabd.add(Segment("mtty_d" , MTTY_BASE , MTTY_SIZE , IntTab(3), false));
+    maptabd.add(Segment("xicu_d" , XICU_BASE , XICU_SIZE , IntTab(4), false));
+    maptabd.add(Segment("mdma_d" , MDMA_BASE , MDMA_SIZE , IntTab(5), false));
+    std::cout << maptabd << std::endl;
+
+    // Mapping table for coherence network
+    soclib::common::MappingTable maptabc(32, IntTab(6), IntTab(6), 0xF0000000);
+    maptabc.add(Segment("proc_c" , C_L1_BASE , C_L1_SIZE , IntTab(0), false, true, IntTab(0)));
+    maptabc.add(Segment("memc_c" , C_MC_BASE , C_MC_SIZE , IntTab(1), false ));
+    maptabc.add(Segment("brom_c" , C_BR_BASE , C_BR_SIZE , IntTab(1), false ));
+    std::cout << maptabc << std::endl;
+	
+    // Signals
+
+    sc_clock	signal_clk			("signal_clk");
+    sc_signal<bool> signal_resetn		("isgnal_resetn");
+   
+    sc_signal<bool> signal_mdma_irq		("signal_mdma_irq");
+    sc_signal<bool> signal_mtty_irq		("signal_mtty_irq");
+    sc_signal<bool> signal_proc_irq		("signal_proc_irq"); 
+    sc_signal<bool> signal_false		("signal_false");
+
+    VciSignals<vci_param> signal_vci_ini_d_proc	("vci_ini_d_proc");
+    VciSignals<vci_param> signal_vci_ini_c_proc	("vci_ini_c_proc");
+    VciSignals<vci_param> signal_vci_tgt_c_proc	("vci_tgt_c_proc");
+
+    VciSignals<vci_param> signal_vci_tgt_d_mtty	("signal_vci_tgt_d_mtty");
+
+    VciSignals<vci_param> signal_vci_tgt_d_exit	("signal_vci_tgt_d_exit");
+
+    VciSignals<vci_param> signal_vci_tgt_d_xicu	("signal_vci_tgt_d_xicu");
+
+    VciSignals<vci_param> signal_vci_ini_d_mdma	("signal_vci_ini_d_mdma");
+    VciSignals<vci_param> signal_vci_tgt_d_mdma	("signal_vci_tgt_d_mdma");
+
+    VciSignals<vci_param> signal_vci_tgt_d_brom ("signal_vci_tgt_d_brom");
+
+
+    VciSignals<vci_param> signal_vci_ini_c_memc ("signal_vci_ini_c_memc");
+    VciSignals<vci_param> signal_vci_tgt_d_memc ("signal_vci_tgt_d_memc");
+    VciSignals<vci_param> signal_vci_tgt_c_memc ("signal_vci_tgt_c_memc");
+
+    VciSignals<vci_param> signal_vci_xram	("signal_vci_xram");
+
+    // Components
+
+    soclib::common::Loader loader(soft_name);
+
+    VciCcXCacheWrapperV4<vci_param, proc_iss > 
+    proc("proc", 
+         0,			// proc_id 
+         maptabd, 		// direct space
+         maptabc, 		// coherence space
+         IntTab(0),		// srcid_d
+         IntTab(0),		// srcid_c
+         IntTab(0),		// tgtid_c
+         4,64,16,		// icache size
+         4,64,16,		// dcache size
+         4, 4, 			// wbuf size
+         max_frozen);		// max frozen cycles
+
+    VciSimpleRam<vci_param> 
+    rom("rom", 
+         IntTab(1), 		// tgtid_d
+         maptabd, 
+         loader);
+
+    VciSimpleRam<vci_param> 
+    xram("xram", 
+         IntTab(0),		// tgtid_d(RAM) = tgtid_d(MEMC) 
+         maptabd, 
+         loader);
+
+    VciMemCacheV4<vci_param> 
+    memc("memc",
+         maptabd,
+         maptabc,
+         maptabd,
+         IntTab(0),		// srcid_x
+         IntTab(1),		// srcid_c
+         IntTab(0), 		// tgtid_d
+         IntTab(1),		// tgtid_c
+         16,256,16, 		// cache size
+         1024,			// HEAP size
+         4,			// TRT size
+         4,			// UPT size
+         from_cycle, trace_ok);
+       
+    VciSimhelper<vci_param> 
+    vciexit("vciexit",
+         IntTab(2), 		// tgtid_d
+         maptabd);
+
+    VciXicu<vci_param> 
+    xicu("xicu", 
+         maptabd,
+         IntTab(4),		// tgtid_d
+         1,			// number of timers
+         2,			// number of hard interrupts 
+         0,			// number of soft interrupts
+         1);			// number of output IRQs
+
+    VciMultiTty<vci_param> 
+    mtty("mtty", 
+         IntTab(3),		// tgtid_d 
+         maptabd, 
+         "mtty0", NULL);
+
+    VciMultiDma<vci_param>
+    mdma("mdma", 
+         maptabd, 
+         IntTab(1),		// srcid_d 
+         IntTab(5), 		// tgtid_d
+         64,			// burst size
+         1);			// number of channels 
+	
+    VciVgmn<vci_param> 
+    ringd("ringd",
+         maptabd, 
+         2, 			// number of initiators
+         6, 			// number of targets
+         2, 
+         8);
+
+    VciVgmn<vci_param> 
+    ringc("ringc",
+         maptabc, 
+         2, 			// number of initiators
+         2, 			// number of targets
+         2, 
+         8);
+
+    // net-list
+    proc.p_clk(signal_clk);  
+    proc.p_resetn		(signal_resetn);  
+    proc.p_irq[0]		(signal_proc_irq); 
+    proc.p_irq[1]		(signal_false); 
+    proc.p_irq[2]		(signal_false); 
+    proc.p_irq[3]		(signal_false); 
+    proc.p_irq[4]		(signal_false); 
+    proc.p_irq[5]		(signal_false); 
+    proc.p_vci_ini_d		(signal_vci_ini_d_proc);
+    proc.p_vci_ini_c		(signal_vci_ini_c_proc);
+    proc.p_vci_tgt_c		(signal_vci_tgt_c_proc);
+
+    rom.p_clk			(signal_clk);
+    rom.p_resetn		(signal_resetn);
+    rom.p_vci			(signal_vci_tgt_d_brom);
+
+    xicu.p_resetn		(signal_resetn);
+    xicu.p_clk			(signal_clk);
+    xicu.p_vci			(signal_vci_tgt_d_xicu);
+    xicu.p_hwi[0]		(signal_mtty_irq);
+    xicu.p_hwi[1]		(signal_mdma_irq);
+    xicu.p_irq[0]		(signal_proc_irq);
+
+    mdma.p_clk			(signal_clk);
+    mdma.p_resetn		(signal_resetn);
+    mdma.p_vci_target		(signal_vci_tgt_d_mdma);
+    mdma.p_vci_initiator	(signal_vci_ini_d_mdma);
+    mdma.p_irq[0]		(signal_mdma_irq); 
+
+    mtty.p_clk			(signal_clk);
+    mtty.p_resetn		(signal_resetn);
+    mtty.p_vci			(signal_vci_tgt_d_mtty);
+    mtty.p_irq[0]		(signal_mtty_irq); 
+
+    vciexit.p_clk		(signal_clk);
+    vciexit.p_resetn		(signal_resetn);
+    vciexit.p_vci		(signal_vci_tgt_d_exit);
+
+    memc.p_clk			(signal_clk);
+    memc.p_resetn		(signal_resetn);
+    memc.p_vci_tgt		(signal_vci_tgt_d_memc);
+    memc.p_vci_tgt_cleanup	(signal_vci_tgt_c_memc);
+    memc.p_vci_ini		(signal_vci_ini_c_memc);
+    memc.p_vci_ixr		(signal_vci_xram);
+
+    xram.p_clk			(signal_clk);
+    xram.p_resetn		(signal_resetn);
+    xram.p_vci			(signal_vci_xram);
+	
+    ringc.p_clk			(signal_clk);
+    ringc.p_resetn		(signal_resetn);
+    ringc.p_to_initiator[0]	(signal_vci_ini_c_proc);
+    ringc.p_to_initiator[1]	(signal_vci_ini_c_memc);
+    ringc.p_to_target[0]	(signal_vci_tgt_c_proc);
+    ringc.p_to_target[1]	(signal_vci_tgt_c_memc);
+
+    ringd.p_clk			(signal_clk);
+    ringd.p_resetn		(signal_resetn);
+    ringd.p_to_initiator[0]	(signal_vci_ini_d_proc);
+    ringd.p_to_initiator[1]	(signal_vci_ini_d_mdma);
+    ringd.p_to_target[0]	(signal_vci_tgt_d_memc);
+    ringd.p_to_target[1]	(signal_vci_tgt_d_brom);
+    ringd.p_to_target[2]	(signal_vci_tgt_d_exit);
+    ringd.p_to_target[3]	(signal_vci_tgt_d_mtty);
+    ringd.p_to_target[4]	(signal_vci_tgt_d_xicu);
+    ringd.p_to_target[5]	(signal_vci_tgt_d_mdma);
+	
+    // simulation loop
+
+    sc_start(sc_core::sc_time(0, SC_NS));
+    signal_resetn = false;
+
+    sc_start(sc_core::sc_time(1, SC_NS));
+    signal_resetn = true;
+        
+    signal_false = false;
+
+    for ( size_t n=1 ; n<ncycles ; n++ )
+    {
+        if ( trace_ok and (n > from_cycle) )
+        {
+            std::cout << "****************** cycle " << std::dec << n
+                      << " ************************************************" << std::endl;
+            proc.print_trace();
+            memc.print_trace();
+            signal_vci_ini_d_proc.print_trace("proc_ini_d");
+            signal_vci_tgt_c_proc.print_trace("proc_tgt_c");
+            signal_vci_ini_c_proc.print_trace("proc_ini_c");
+            signal_vci_tgt_d_memc.print_trace("memc_tgt_d");
+            signal_vci_tgt_c_memc.print_trace("memc_tgt_c");
+            signal_vci_ini_c_memc.print_trace("memc_ini_c");
+            if ( signal_proc_irq.read() ) std::cout << "---- IRQ ----" << std::endl;
+        }
+        sc_start(sc_core::sc_time(1, SC_NS));
+    }
+    return EXIT_SUCCESS;
+}
+
+int sc_main (int argc, char *argv[])
+{
+	try {
+		return _main(argc, argv);
+	} catch (std::exception &e) {
+		std::cout << e.what() << std::endl;
+	} catch (...) {
+		std::cout << "Unknown exception occured" << std::endl;
+		throw;
+	}
+	return 1;
+}
Index: branches/v4/platforms/tsarv4_mono_nommu/top.desc
===================================================================
--- branches/v4/platforms/tsarv4_mono_nommu/top.desc	(revision 371)
+++ branches/v4/platforms/tsarv4_mono_nommu/top.desc	(revision 371)
@@ -0,0 +1,29 @@
+
+# -*- python -*-
+
+todo = Platform('caba', 'top.cpp',
+                uses = [
+	Uses('common:mapping_table'),
+	Uses('caba:vci_cc_xcache_wrapper_v4', iss_t = 'common:mips32el'),
+	Uses('caba:vci_simple_ram'),
+        Uses('caba:vci_logger'),
+	Uses('caba:vci_multi_tty'),
+        Uses('caba:vci_xicu'),
+        Uses('caba:vci_multi_dma'),
+	Uses('caba:vci_vgmn'),
+	Uses('caba:vci_simhelper'),
+	Uses('caba:vci_mem_cache_v4'),
+	Uses('common:elf_file_loader'),
+	],
+	cell_size = 4,
+	plen_size = 8,
+	addr_size = 32,
+	rerror_size = 2,
+	clen_size = 1,
+	rflag_size = 1,
+	srcid_size = 14,
+	pktid_size = 4,
+	trdid_size = 4,
+	wrplen_size = 1
+)
+
Index: branches/v4/platforms/tsarv4_vgmn_generic_32/Makefile
===================================================================
--- branches/v4/platforms/tsarv4_vgmn_generic_32/Makefile	(revision 371)
+++ branches/v4/platforms/tsarv4_vgmn_generic_32/Makefile	(revision 371)
@@ -0,0 +1,7 @@
+
+simulator.x: tsarv4_vgmn_generic_32_top.cpp tsarv4_vgmn_generic_32_desc
+	soclib-cc -p tsarv4_vgmn_generic_32_desc -o simulator.x
+
+clean:
+	rm -rf *.o simulator.x temp tty*
+
Index: branches/v4/platforms/tsarv4_vgmn_generic_32/tsarv4_vgmn_generic_32_desc
===================================================================
--- branches/v4/platforms/tsarv4_vgmn_generic_32/tsarv4_vgmn_generic_32_desc	(revision 371)
+++ branches/v4/platforms/tsarv4_vgmn_generic_32/tsarv4_vgmn_generic_32_desc	(revision 371)
@@ -0,0 +1,30 @@
+
+# -*- python -*-
+
+todo = Platform('caba', 'tsarv4_vgmn_generic_32_top.cpp',
+	uses = [
+            Uses('caba:vci_cc_xcache_wrapper_v4', iss_t = 'common:mips32el'),
+            Uses('caba:vci_cc_xcache_wrapper_v4', iss_t = 'common:gdb_iss', gdb_iss_t = 'common:mips32el'),
+            Uses('caba:vci_mem_cache_v4'),
+	    Uses('caba:vci_simple_ram'),
+	    Uses('caba:vci_multi_tty'),
+	    Uses('caba:vci_xicu'),
+	    Uses('caba:vci_vgmn'),
+	    Uses('caba:vci_framebuffer'),
+	    Uses('caba:vci_dma_tsar_v2'),
+	    Uses('caba:vci_block_device_tsar_v2'),
+ 	    Uses('caba:vci_local_crossbar'),
+	    Uses('common:elf_file_loader'),
+            Uses('common:plain_file_loader')
+	],
+	cell_size = 4,
+	plen_size = 8,
+	addr_size = 32,
+	rerror_size = 1,
+	clen_size = 1,
+	rflag_size = 1,
+	srcid_size = 14,
+	pktid_size = 4,
+	trdid_size = 4,
+	wrplen_size = 1,
+)
Index: branches/v4/platforms/tsarv4_vgmn_generic_32/tsarv4_vgmn_generic_32_top.cpp
===================================================================
--- branches/v4/platforms/tsarv4_vgmn_generic_32/tsarv4_vgmn_generic_32_top.cpp	(revision 371)
+++ branches/v4/platforms/tsarv4_vgmn_generic_32/tsarv4_vgmn_generic_32_top.cpp	(revision 371)
@@ -0,0 +1,858 @@
+/////////////////////////////////////////////////////////////////////////
+// File: tsarv4_vgmn_generic_32_top.cpp
+// Author: Alain Greiner
+// Copyright: UPMC/LIP6
+// Date : november 5 2010
+// This program is released under the GNU public license
+/////////////////////////////////////////////////////////////////////////
+// This file define a generic TSAR architecture without virtual memory.
+// - It uses the vci_vgmn as global interconnect 
+// - It uses the vci_local_crossbar  as local interconnect 
+// - It uses the vci_cc_xcache (No MMU) 
+// The physical address space is 32 bits.
+// The number of clusters cannot be larger than 256.
+// The three parameters are 
+// - xmax : number of clusters in a row
+// - ymax : number of clusters in a column
+// - nprocs : number of processor per cluster
+//
+// Each cluster contains nprocs processors, one Memory Cache,
+// and one XICU component.
+// The peripherals BDEV, CDMA, FBUF, MTTY and the boot BROM
+// are in the cluster containing address 0xBFC00000.
+// - The bdev_irq is connected to IRQ_IN[0]
+// - The cdma_irq is connected to IRQ_IN[1]
+// - The tty_irq[i] is connected to IRQ_IN[i+2]
+// For all clusters, the XICU component contains nprocs timers.
+// 
+// As we target up to 256 clusters, each cluster can contain 
+// at most 16 Mbytes (in a 4Gbytes address space).
+// - Each memory cache contains 9 Mbytes.
+// - The Frame buffer contains 2 Mbytes.
+// - The Boot ROM contains 1 Mbytes.
+//
+// General policy for 32 bits address decoding:
+// To simplifly, all segments base addresses are aligned
+// on 1 Mbyte addresses. Therefore the 12 address MSB bits
+// define the target in the direct address space.
+// In these 12 bits, the (x_width + y_width) MSB bits define
+// the cluster index, and the 4 LSB bits define the local index:
+// 
+//      | X_ID  | Y_ID  |---| L_ID |     OFFSET          |
+//	|x_width|y_width|---|  4   |       20            |
+/////////////////////////////////////////////////////////////////////////
+
+#include <systemc>
+#include <sys/time.h>
+#include <iostream>
+#include <sstream>
+#include <cstdlib>
+#include <cstdarg>
+#include <stdint.h>
+
+#include "mapping_table.h"
+#include "mips32.h"
+#include "vci_simple_ram.h"
+#include "vci_multi_tty.h"
+#include "vci_mem_cache_v4.h"
+#include "vci_cc_xcache_wrapper_v4.h"
+#include "vci_xicu.h"
+#include "vci_vgmn.h"
+#include "vci_local_crossbar.h"
+#include "vci_framebuffer.h"
+#include "vci_dma_tsar_v2.h"
+#include "vci_block_device_tsar_v2.h"
+#include "gdbserver.h"
+
+#define	SECTOR_SIZE	2048
+
+#define FBUF_XSIZE	960
+#define FBUF_YSIZE	960
+
+#define N_TTYS		4
+
+//////////////////////////////////////////////
+// segments definition in direct space.
+// There is 16 Mbytes address space per cluster.
+// The 8 MSB bits define the cluster index (x,y),
+// even if the number of clusters is less than 256.
+// Each memory cache contains up to 9 Mbytes.
+// There is one MEMC segment and one XICU segment per cluster
+// The peripherals BDEV, FBUF, MTTY, CDMA and the boot BROM
+// are mapped in cluster containing address 0xBFC00000
+
+#define	MEMC_BASE	0x00000000	
+#define MEMC_SIZE	0x00900000
+
+#define	XICU_BASE	0x00900000	
+#define XICU_SIZE	0x00001000
+
+#define	FBUF_BASE	0xBFA00000	
+#define FBUF_SIZE	0x00200000
+
+#define	BROM_BASE	0xBFC00000	
+#define BROM_SIZE	0x00100000
+
+#define	BDEV_BASE	0xBFD00000	
+#define BDEV_SIZE	0x00000100
+
+#define	MTTY_BASE	0xBFE00000	
+#define MTTY_SIZE	0x00000100
+
+#define	CDMA_BASE	0xBFF00000	
+#define CDMA_SIZE	0x00000100
+
+/* Pour ALMOS
+
+#define BOOT_INFO_BLOCK 0xbfc08000
+#define KERNEL_BIN_IMG  0xbfc10000
+
+*/
+
+////////////////////////////////////////////////////////////////////
+//     TGTID & SRCID definition in direct space
+// For all components:  global TGTID = global SRCID = cluster_index
+// For processors, the local SRCID is between 0 & nprocs-1
+
+#define MEMC_TGTID	0
+#define XICU_TGTID	1
+#define FBUF_TGTID	2
+#define MTTY_TGTID	3
+#define BROM_TGTID	4
+#define BDEV_TGTID	5
+#define CDMA_TGTID	6
+
+#define PROC_SRCID	0
+#define BDEV_SRCID	nprocs
+#define CDMA_SRCID	(nprocs+1)
+
+////////////////////////////////////////////////////////
+//     TGTID & SRCID definition in coherence space
+// For all components:  global TGTID = global SRCID = cluster_index
+// For MEMC       : local SRCID = local TGTID = nprocs
+// For processors : local SRCID = local TGTID = PROC_ID
+
+//////////////////////
+// Router ports index
+
+#define NORTH		0
+#define SOUTH		1
+#define EAST		2
+#define WEST		3
+#define LOCAL		4
+
+///////////////
+// VCI format
+#define cell_width	4
+#define address_width	32
+#define plen_width	8
+#define error_width	1
+#define clen_width	1
+#define rflag_width	1
+#define srcid_width	14
+#define pktid_width	4
+#define trdid_width	4
+#define wrplen_width	1
+
+//  cluster index (computed from x,y coordinates)
+#define cluster(x,y)	(y + ymax*x)
+
+/////////////////////////////////
+int _main(int argc, char *argv[])
+{
+    using namespace sc_core;
+    using namespace soclib::caba;
+    using namespace soclib::common;
+
+    char    soft_name[128]  = "undefined_binary_code";	// pathname to binary code
+    char    disk_name[128]  = "undefined_disk_image";	// pathname to the disk image
+    size_t  ncycles         = 1000000000;       	// simulated cycles
+    size_t  xmax            = 2;			// number of clusters in a row
+    size_t  ymax            = 2;                	// number of clusters in a column
+    size_t  nprocs          = 1;			// number of processors per cluster
+    bool    debug_ok        = false;            	// debug activated
+    size_t  from_cycle      = 0;                	// debug start cycle
+    size_t  to_cycle        = 1000000000;       	// debug end cycle
+
+    ////////////// command line arguments //////////////////////
+    if (argc > 1)
+    {
+        for( int n=1 ; n<argc ; n=n+2 )
+        {
+            if( (strcmp(argv[n],"-NCYCLES") == 0) && (n+1<argc) )
+            {
+                ncycles = atoi(argv[n+1]);
+            }
+            else if( (strcmp(argv[n],"-NPROCS") == 0) && (n+1<argc) )
+            {
+                nprocs = atoi(argv[n+1]);
+                assert( (nprocs <= 8) && "The number of processors per cluster cannot be larger than 8");
+            }
+            else if( (strcmp(argv[n],"-XMAX") == 0) && (n+1<argc) )
+            {
+                xmax = atoi(argv[n+1]);
+                assert( ((xmax >= 2) && (xmax <= 16)) 
+                    && "The XMAX parameter (number of clusters in a row) must be in the range [2,16]" );
+            }
+            else if( (strcmp(argv[n],"-YMAX") == 0) && (n+1<argc) )
+            {
+                ymax = atoi(argv[n+1]);
+                assert( ((ymax >= 2) && (ymax <= 16)) 
+                    && "The YMAX parameter (number of clusters in a column) must be in the range [2,16]" );
+            }
+            else if( (strcmp(argv[n],"-SOFT") == 0) && (n+1<argc) )
+            {
+                strcpy(soft_name, argv[n+1]);
+            }
+            else if( (strcmp(argv[n],"-DISK") == 0) && (n+1<argc) )
+            {
+                strcpy(disk_name, argv[n+1]);
+            }
+            else if( (strcmp(argv[n],"-DEBUG") == 0) && (n+1<argc) )
+            {
+                debug_ok = true;
+                from_cycle = atoi(argv[n+1]);
+            }
+            else if( (strcmp(argv[n],"-TOCYCLE") == 0) && (n+1<argc) )
+            {
+                to_cycle = atoi(argv[n+1]);
+            }
+            else
+            {
+                std::cout << "   Arguments on the command line are (key,value) couples." << std::endl;
+                std::cout << "   The order is not important." << std::endl;
+                std::cout << "   Accepted arguments are :" << std::endl << std::endl;
+                std::cout << "     -SOFT elf_file_name" << std::endl;
+                std::cout << "     -DISK disk_image_file_name" << std::endl;
+                std::cout << "     -NCYCLES number_of_simulated_cycles" << std::endl;
+                std::cout << "     -NPROCS number_of_processors_per_cluster" << std::endl;
+                std::cout << "     -XMAX number_of_clusters_in_a_row" << std::endl;
+                std::cout << "     -YMAX number_of_clusters_in_a_column" << std::endl;
+                std::cout << "     -DEBUG debug_start_cycle" << std::endl;
+                std::cout << "     -TOCYCLE debug_end_cycle" << std::endl;
+                exit(0);
+            }
+        }
+    }
+
+    std::cout << std::endl << "***********  TSAR ARCHITECTURE  **************" << std::endl
+              << " - Interconnect = VGMN & CROSSBAR" << std::endl
+              << " - Number of clusters = " << xmax << " * " << ymax << std::endl
+              << " - Number of processors per cluster = " << nprocs << std::endl
+              << "**********************************************" << std::endl
+              << std::endl;
+
+
+    // Define VCI parameters
+    typedef soclib::caba::VciParams<cell_width,
+                                    plen_width,
+                                    address_width,
+                                    error_width,                                   
+                                    clen_width,
+                                    rflag_width,
+                                    srcid_width,
+                                    pktid_width,
+                                    trdid_width,
+                                    wrplen_width> vci_param;
+
+    size_t	cluster_io_index;
+    size_t	x_width;
+    size_t	y_width;
+
+    if      (xmax == 2) x_width = 1;
+    else if (xmax <= 4) x_width = 2;
+    else if (xmax <= 8) x_width = 3;
+    else                x_width = 4;
+
+    if      (ymax == 2) y_width = 1;
+    else if (ymax <= 4) y_width = 2;
+    else if (ymax <= 8) y_width = 3;
+    else                y_width = 4;
+
+    cluster_io_index = 0xBF >> (8 - x_width - y_width);
+    
+    /////////////////////
+    //  Mapping Tables
+    /////////////////////
+
+    // direct network
+    MappingTable maptabd(address_width, 
+                         IntTab(x_width + y_width, 12 - x_width - y_width), 
+                         IntTab(x_width + y_width, srcid_width - x_width - y_width), 
+                         0x00F00000);
+    for ( size_t x = 0 ; x < xmax ; x++)
+    {
+        for ( size_t y = 0 ; y < ymax ; y++)
+        {
+            sc_uint<address_width> offset  = cluster(x,y) << (address_width-x_width-y_width);
+            std::ostringstream 	sm;
+            sm << "d_seg_memc_" << x << "_" << y;
+            maptabd.add(Segment(sm.str(), MEMC_BASE+offset, MEMC_SIZE, IntTab(cluster(x,y),MEMC_TGTID), true));
+            std::ostringstream 	si;
+            si << "d_seg_xicu_" << x << "_" << y;
+            maptabd.add(Segment(si.str(), XICU_BASE+offset, XICU_SIZE, IntTab(cluster(x,y),XICU_TGTID), false));
+            if ( cluster(x,y) == cluster_io_index )
+            {
+	      maptabd.add(Segment("d_seg_fbuf", FBUF_BASE, FBUF_SIZE, IntTab(cluster(x,y),FBUF_TGTID), false));
+	      maptabd.add(Segment("d_seg_bdev", BDEV_BASE, BDEV_SIZE, IntTab(cluster(x,y),BDEV_TGTID), false));
+	      maptabd.add(Segment("d_seg_mtty", MTTY_BASE, MTTY_SIZE, IntTab(cluster(x,y),MTTY_TGTID), false));
+	      maptabd.add(Segment("d_seg_brom", BROM_BASE, BROM_SIZE, IntTab(cluster(x,y),BROM_TGTID), true));
+	      maptabd.add(Segment("d_seg_cdma", CDMA_BASE, CDMA_SIZE, IntTab(cluster(x,y),CDMA_TGTID), false));
+            }
+        }
+    }
+    std::cout << maptabd << std::endl;
+
+    // coherence network
+    MappingTable maptabc(address_width, 
+                         IntTab(x_width + y_width, 12 - x_width - y_width), 
+                         IntTab(x_width + y_width, srcid_width - x_width - y_width), 
+                         0xF0000000);
+
+    for ( size_t x = 0 ; x < xmax ; x++)
+    {
+        for ( size_t y = 0 ; y < ymax ; y++)
+        {
+            sc_uint<address_width> offset  = cluster(x,y) << (address_width-x_width-y_width);
+            
+            std::ostringstream sm;
+            sm << "c_seg_memc_" << x << "_" << y;
+            maptabc.add(Segment(sm.str(), MEMC_BASE+offset, MEMC_SIZE, IntTab(cluster(x,y), nprocs), false));
+            // the segment base and size will be modified 
+            // when the segmentation of the coherence space will be simplified
+
+            if ( cluster(x,y) == cluster_io_index )
+            {
+                std::ostringstream sr;
+                sr << "c_seg_brom_" << x << "_" << y;
+                maptabc.add(Segment(sr.str(), BROM_BASE, BROM_SIZE, IntTab(cluster(x,y), nprocs), false));
+            }
+
+	    sc_uint<address_width> avoid_collision  = 0;
+	    for ( size_t p = 0 ; p < nprocs ; p++)
+            {
+	        sc_uint<address_width> base = MEMC_SIZE + (p*0x100000) + offset;
+                // the following test is to avoid a collision between the c_seg_brom segment
+                // and a c_seg_proc segment (all segments base addresses being multiple of 1Mbytes)
+                if ( base == BROM_BASE ) avoid_collision = 0x100000;
+	        std::ostringstream sp;
+	        sp << "c_seg_proc_" << x << "_" << y << "_" << p;
+	        maptabc.add(Segment(sp.str(), base + avoid_collision, 0x20, IntTab(cluster(x,y), p), false, 
+				  true, IntTab(cluster(x,y), p))); 
+                // the two last arguments will be removed 
+                // when the segmentation of the coherence space will be simplified
+            }
+        }
+    }
+    std::cout << maptabc << std::endl;
+
+    // external network
+    MappingTable maptabx(address_width, IntTab(1), IntTab(10), 0xF0000000);
+
+    for ( size_t x = 0 ; x < xmax ; x++)
+    {
+        for ( size_t y = 0 ; y < ymax ; y++)
+        { 
+	  sc_uint<address_width> offset  = cluster(x,y) << (address_width-x_width-y_width);
+	  std::ostringstream sx;
+	  
+	  sx << "seg_xram_" << x << "_" << y;
+	  maptabx.add(Segment(sx.str(), MEMC_BASE + offset, MEMC_SIZE, IntTab(0), false));
+        }
+    }
+    std::cout << maptabx << std::endl;
+
+    ////////////////////
+    // Signals
+    ///////////////////
+
+    sc_clock		signal_clk("clk");
+    sc_signal<bool> 	signal_resetn("resetn");
+    sc_signal<bool>	signal_false;
+   
+    // IRQ signals (one signal per proc)
+    sc_signal<bool>****	signal_proc_it =
+      alloc_elems<sc_signal<bool> >("signal_proc_it", 1,xmax, ymax, nprocs);
+
+    sc_signal<bool>*	signal_irq_mtty = 
+        alloc_elems<sc_signal<bool> >("signal_irq_mtty", N_TTYS);
+
+    sc_signal<bool>	signal_irq_bdev;
+    sc_signal<bool>	signal_irq_cdma;
+
+    // Direct VCI signals
+
+    VciSignals<vci_param>*** signal_vci_ini_d_proc = 
+        alloc_elems<VciSignals<vci_param> >("signal_vci_ini_d_proc", xmax, ymax, nprocs);
+
+    VciSignals<vci_param>** signal_vci_tgt_d_memc = 
+        alloc_elems<VciSignals<vci_param> >("signal_vci_tgt_d_memc", xmax, ymax);
+
+    VciSignals<vci_param>** signal_vci_tgt_d_xicu = 
+        alloc_elems<VciSignals<vci_param> >("signal_vci_tgt_d_xicu", xmax, ymax);
+
+    VciSignals<vci_param>** signal_vci_l2g_d = 
+        alloc_elems<VciSignals<vci_param> >("signal_vci_l2g_d", xmax, ymax);
+
+    VciSignals<vci_param>** signal_vci_g2l_d = 
+        alloc_elems<VciSignals<vci_param> >("signal_vci_g2l_d", xmax, ymax);
+
+    VciSignals<vci_param> signal_vci_tgt_d_mtty("signal_vci_tgt_d_mtty");
+    VciSignals<vci_param> signal_vci_tgt_d_brom("signal_vci_tgt_d_brom");
+    VciSignals<vci_param> signal_vci_tgt_d_bdev("signal_vci_tgt_d_bdev");
+    VciSignals<vci_param> signal_vci_tgt_d_fbuf("signal_vci_tgt_d_fbuf");
+    VciSignals<vci_param> signal_vci_tgt_d_cdma("signal_vci_tgt_d_cdma");
+
+    VciSignals<vci_param> signal_vci_ini_d_bdev("signal_vci_ini_d_bdev");
+    VciSignals<vci_param> signal_vci_ini_d_cdma("signal_vci_ini_d_cdma");
+
+    // Coherence VCI signals
+
+    VciSignals<vci_param>*** signal_vci_ini_c_proc = 
+        alloc_elems<VciSignals<vci_param> >("signal_vci_ini_c_proc", xmax, ymax, nprocs);
+
+    VciSignals<vci_param>*** signal_vci_tgt_c_proc = 
+        alloc_elems<VciSignals<vci_param> >("signal_vci_tgt_c_proc", xmax, ymax, nprocs);
+
+    VciSignals<vci_param>** signal_vci_ini_c_memc = 
+        alloc_elems<VciSignals<vci_param> >("signal_vci_ini_c_memc", xmax, ymax);
+
+    VciSignals<vci_param>** signal_vci_tgt_c_memc = 
+        alloc_elems<VciSignals<vci_param> >("signal_vci_tgt_c_memc", xmax, ymax);
+
+    VciSignals<vci_param>** signal_vci_l2g_c = 
+        alloc_elems<VciSignals<vci_param> >("signal_vci_l2g_c", xmax, ymax);
+
+    VciSignals<vci_param>** signal_vci_g2l_c = 
+        alloc_elems<VciSignals<vci_param> >("signal_vci_g2l_c", xmax, ymax);
+
+    // Xternal network VCI signals
+
+    VciSignals<vci_param> signal_vci_tgt_x_xram("signal_vci_tgt_x_xram");
+    VciSignals<vci_param>** signal_vci_ini_x_memc = 
+        alloc_elems<VciSignals<vci_param> >("signal_vci_ini_x_memc", xmax, ymax);
+
+    ////////////////////////////
+    //      Components
+    ////////////////////////////
+
+    typedef soclib::common::GdbServer<soclib::common::Mips32ElIss> proc_iss;
+
+    soclib::common::Loader loader(soft_name);
+    proc_iss::set_loader(loader);
+
+/* code specifique ALMOS pour chargement du binaire 
+
+#define _TO_STR(_str) #_str
+#define  TO_STR(_str) _TO_STR(_str)
+
+    soclib::common::Loader loader("bootloader.bin",
+				  "arch-info.bin@"TO_STR(BOOT_INFO_BLOCK)":D",
+				  "kernel-soclib.bin@"TO_STR(KERNEL_BIN_IMG)":D");
+*/
+
+    // External RAM
+    VciSimpleRam<vci_param> xram(
+        "xram", 
+        IntTab(0), 
+        maptabx, 
+        loader);
+
+    // Direct network
+    VciVgmn<vci_param> dnoc(
+        "dnoc",
+        maptabd, 
+        xmax*ymax,
+        xmax*ymax,
+        2, 2);
+
+    // Coherence network
+    VciVgmn<vci_param> cnoc(
+        "cnoc",
+        maptabc, 
+        xmax*ymax,
+        xmax*ymax,
+        2, 2);
+
+    // External network
+    VciVgmn<vci_param> xnoc(
+        "xnoc",
+        maptabx, 
+        xmax*ymax,
+        1, 
+        2, 2);
+
+    // Peripherals : TTY, Frame Buffer, Block Device, Boot ROM, & DMA 
+    VciSimpleRam<vci_param> brom(
+        "brom", 
+        IntTab(cluster_io_index, BROM_TGTID), 
+        maptabd, 
+        loader);
+
+    VciMultiTty<vci_param> mtty(
+        "mtty",
+        IntTab(cluster_io_index, MTTY_TGTID),
+        maptabd,
+        "tty0","tty1","tty2","tty3",NULL);
+
+    VciFrameBuffer<vci_param> fbuf(
+        "fbuf", 
+        IntTab(cluster_io_index, FBUF_TGTID),
+        maptabd, 
+        FBUF_XSIZE,
+        FBUF_YSIZE);
+
+    VciBlockDeviceTsarV2<vci_param> bdev(
+        "bdev", 
+        maptabd, 
+        IntTab(cluster_io_index, BDEV_SRCID),	// SRCID_D
+        IntTab(cluster_io_index, BDEV_TGTID),	// TGTID_D
+        disk_name, 
+        SECTOR_SIZE); 
+
+    VciDmaTsarV2<vci_param> cdma(
+	"cdma",
+	maptabd,
+	IntTab(cluster_io_index,CDMA_SRCID),	// SRCID_D
+	IntTab(cluster_io_index,CDMA_TGTID),	// TGTID_D
+	64); 
+
+    // processors (nprocs per cluster)
+
+    VciCcXCacheWrapperV4<vci_param, proc_iss> *proc[xmax][ymax][nprocs];
+
+    for( size_t x = 0 ; x < xmax ; x++ )
+    {
+      for( size_t y = 0 ; y < ymax ; y++ )
+      {
+	for ( size_t p = 0 ; p < nprocs ; p++ ) 
+	{
+	  
+	  std::ostringstream sp;
+	  sp << "proc_" << x << "_" << y << "_" << p;
+			       
+	  proc[x][y][p] = new VciCcXCacheWrapperV4<vci_param, proc_iss>(
+                    sp.str().c_str(),
+                    p+nprocs*cluster(x,y), 
+                    maptabd, maptabc,
+                    IntTab(cluster(x,y), PROC_SRCID+p),		// SRCID_D
+                    IntTab(cluster(x,y), PROC_SRCID+p),		// SRCID_C
+                    IntTab(cluster(x,y), PROC_SRCID+p),		// TGTID_C
+                    1,1,
+                    4,64,16,4,64,16 				// Icache and Dcache sizes
+                    ,4,8
+                    );
+	}
+      }
+    }
+
+    //  memory caches (one per cluster)
+    VciMemCacheV4<vci_param>* memc[xmax][ymax];
+
+    for( size_t x = 0 ; x < xmax ; x++ )
+    {
+        for( size_t y = 0 ; y < ymax ; y++ )
+	{
+	  std::ostringstream sm;
+	  sm << "memc_" << x << "_" << y;
+
+	  memc[x][y] = new VciMemCacheV4<vci_param>(
+                sm.str().c_str(),
+                maptabd, maptabc, maptabx,
+                IntTab(cluster(x,y)),				// SRCID_X
+                IntTab(cluster(x,y), nprocs),			// SRCID_C
+                IntTab(cluster(x,y), MEMC_TGTID),		// TGTID_D
+                IntTab(cluster(x,y), nprocs),         		// TGTID_C
+                16,256,16,					// CACHE SIZE
+                4096);						// HEAP SIZE
+        }
+    }
+
+    // XICU (one per cluster)
+    VciXicu<vci_param> *xicu[xmax][ymax];
+    
+    for( size_t x = 0 ; x < xmax ; x++ )
+    {
+        for( size_t y = 0 ; y < ymax ; y++ )
+        {
+            std::ostringstream si;
+            si << "xicu_" << x << "_" << y;
+            size_t	nhwi;
+            if ( cluster(x,y) == cluster_io_index )	nhwi = N_TTYS + 2;
+            else					nhwi = 0;
+	    xicu[x][y] = new VciXicu<vci_param>(
+                si.str().c_str(),
+                maptabd,
+                IntTab(cluster(x,y), XICU_TGTID),	// TGTID_D
+               	nprocs,					// number of TIMERS
+		nhwi,					// number of hard IRQs
+		nprocs,					// number of soft IRQs
+		nprocs);				// number of output IRQ lines
+        }
+    }
+                                                
+    // Local interconnects : one direct crossbar & one coherence crossbar per cluster
+    VciLocalCrossbar<vci_param>* dxbar[xmax][ymax];
+    
+    VciLocalCrossbar<vci_param>* cxbar[xmax][ymax];
+
+    for( size_t x = 0 ; x < xmax ; x++ )
+    {
+        for( size_t y = 0 ; y < ymax ; y++ )
+        {
+            std::ostringstream sd;
+            sd << "dxbar_" << x << "_" << y;
+            size_t nb_direct_initiators 	= nprocs;
+            size_t nb_direct_targets	        = 2;
+            if ( cluster(x,y) == cluster_io_index ) 
+            {
+                nb_direct_initiators		= nprocs + 2;
+                nb_direct_targets		= 7;
+            }
+	    dxbar[x][y] = new VciLocalCrossbar<vci_param>( 
+                sd.str().c_str(),
+                maptabd,
+                IntTab(cluster(x,y)),		// global initiator index
+                IntTab(cluster(x,y)),		// global target index
+                nb_direct_initiators,		// number of initiators
+                nb_direct_targets);		// number of targets
+
+            std::ostringstream sc;
+            sc << "cxbar_" << x << "_" << y;
+	    cxbar[x][y] = new VciLocalCrossbar<vci_param>( 
+                sc.str().c_str(),
+                maptabc,
+                IntTab(cluster(x,y)),		// global initiator index
+                IntTab(cluster(x,y)),		// global target index
+                nprocs+1,			// number of initiators
+		nprocs+1);			// number of targets
+        }
+    }
+
+    std::cout << "all components created" << std::endl;
+
+    ///////////////////////////////////////////////////////////////
+    //     Net-list 
+    ///////////////////////////////////////////////////////////////
+
+    // External Ram (one instance)
+    xram.p_clk						(signal_clk);
+    xram.p_resetn					(signal_resetn);
+    xram.p_vci						(signal_vci_tgt_x_xram);	
+
+    // External Network (one instance)
+    xnoc.p_clk						(signal_clk);
+    xnoc.p_resetn					(signal_resetn);
+    xnoc.p_to_target[0]					(signal_vci_tgt_x_xram);
+    for ( size_t x = 0 ; x < xmax ; x++ )
+    {
+        for ( size_t y = 0 ; y < ymax ; y++ )
+        {
+            xnoc.p_to_initiator[cluster(x,y)]		(signal_vci_ini_x_memc[x][y]);
+        }
+    }
+
+    // Direct Network (one instance)
+    dnoc.p_clk						(signal_clk);
+    dnoc.p_resetn					(signal_resetn);
+    for ( size_t x = 0 ; x < xmax ; x++ )
+    {
+        for ( size_t y = 0 ; y < ymax ; y++ )
+        {
+            dnoc.p_to_initiator[cluster(x,y)]		(signal_vci_l2g_d[x][y]);
+            dnoc.p_to_target[cluster(x,y)]		(signal_vci_g2l_d[x][y]);
+        }
+    }
+
+    // Coherence Network (one instance)
+    cnoc.p_clk						(signal_clk);
+    cnoc.p_resetn					(signal_resetn);
+    for ( size_t x = 0 ; x < xmax ; x++ )
+    {
+        for ( size_t y = 0 ; y < ymax ; y++ )
+        {
+            cnoc.p_to_initiator[cluster(x,y)]		(signal_vci_l2g_c[x][y]);
+            cnoc.p_to_target[cluster(x,y)]		(signal_vci_g2l_c[x][y]);
+        }
+    }
+
+    // Distributed components (in clusters)
+
+    for ( size_t x = 0 ; x < xmax ; x++ )
+    {
+        for ( size_t y = 0 ; y < ymax ; y++ )
+	{
+            // direct local crossbar
+            dxbar[x][y]->p_clk				(signal_clk);
+            dxbar[x][y]->p_resetn			(signal_resetn);
+            dxbar[x][y]->p_initiator_to_up		(signal_vci_l2g_d[x][y]);
+	    dxbar[x][y]->p_target_to_up			(signal_vci_g2l_d[x][y]);
+            dxbar[x][y]->p_to_target[MEMC_TGTID]	(signal_vci_tgt_d_memc[x][y]);
+            dxbar[x][y]->p_to_target[XICU_TGTID]	(signal_vci_tgt_d_xicu[x][y]);
+	    for ( size_t p = 0 ; p < nprocs ; p++ )
+            {
+	        dxbar[x][y]->p_to_initiator[p]		(signal_vci_ini_d_proc[x][y][p]);
+	    }
+
+            // coherence local crossbar
+            cxbar[x][y]->p_clk				(signal_clk);
+            cxbar[x][y]->p_resetn			(signal_resetn);
+            cxbar[x][y]->p_initiator_to_up		(signal_vci_l2g_c[x][y]);
+            cxbar[x][y]->p_target_to_up			(signal_vci_g2l_c[x][y]);
+            cxbar[x][y]->p_to_initiator[nprocs]	(signal_vci_ini_c_memc[x][y]);
+            cxbar[x][y]->p_to_target[nprocs]		(signal_vci_tgt_c_memc[x][y]);
+            for ( size_t p = 0 ; p < nprocs ; p++ )
+            {
+                cxbar[x][y]->p_to_initiator[p]		(signal_vci_ini_c_proc[x][y][p]);
+                cxbar[x][y]->p_to_target[p]		(signal_vci_tgt_c_proc[x][y][p]);
+            }
+	
+	    // Processors
+	    for ( size_t p = 0 ; p < nprocs ; p++ )
+            {
+                proc[x][y][p]->p_clk			(signal_clk);  
+                proc[x][y][p]->p_resetn			(signal_resetn);  
+                proc[x][y][p]->p_vci_ini_rw		(signal_vci_ini_d_proc[x][y][p]);
+                proc[x][y][p]->p_vci_ini_c		(signal_vci_ini_c_proc[x][y][p]);
+                proc[x][y][p]->p_vci_tgt		(signal_vci_tgt_c_proc[x][y][p]);
+                proc[x][y][p]->p_irq[0][0]	        (signal_proc_it[0][x][y][p]);
+                for ( size_t j = 1 ; j < 6 ; j++ )
+                {
+                    proc[x][y][p]->p_irq[0][j]		(signal_false); 
+                }
+	    }
+
+            // XICU
+	    xicu[x][y]->p_clk				(signal_clk);
+            xicu[x][y]->p_resetn			(signal_resetn);
+	    xicu[x][y]->p_vci				(signal_vci_tgt_d_xicu[x][y]);
+	    for ( size_t p = 0 ; p < nprocs ; p++ )
+            {
+                xicu[x][y]->p_irq[p]			(signal_proc_it[0][x][y][p]);
+            }
+
+            // MEMC
+            memc[x][y]->p_clk				(signal_clk);
+            memc[x][y]->p_resetn			(signal_resetn);
+            memc[x][y]->p_vci_tgt			(signal_vci_tgt_d_memc[x][y]);	
+            memc[x][y]->p_vci_ini			(signal_vci_ini_c_memc[x][y]);
+            memc[x][y]->p_vci_tgt_cleanup		(signal_vci_tgt_c_memc[x][y]);
+            memc[x][y]->p_vci_ixr			(signal_vci_ini_x_memc[x][y]);
+
+            // I/O peripherals
+            if ( cluster(x,y) == cluster_io_index )
+            {
+	        bdev.p_clk				(signal_clk);
+	        bdev.p_resetn				(signal_resetn);
+	        bdev.p_irq				(signal_irq_bdev); 
+	        bdev.p_vci_target			(signal_vci_tgt_d_bdev);
+	        bdev.p_vci_initiator			(signal_vci_ini_d_bdev);
+
+	        cdma.p_clk				(signal_clk);
+	        cdma.p_resetn				(signal_resetn);
+	        cdma.p_irq				(signal_irq_cdma); 
+	        cdma.p_vci_target			(signal_vci_tgt_d_cdma);
+	        cdma.p_vci_initiator			(signal_vci_ini_d_cdma);
+
+	        fbuf.p_clk				(signal_clk); 
+	        fbuf.p_resetn				(signal_resetn); 
+	        fbuf.p_vci				(signal_vci_tgt_d_fbuf); 
+
+	        brom.p_clk				(signal_clk);
+	        brom.p_resetn				(signal_resetn);
+	        brom.p_vci				(signal_vci_tgt_d_brom);
+
+	        mtty.p_clk				(signal_clk);
+	        mtty.p_resetn				(signal_resetn);
+	        mtty.p_vci				(signal_vci_tgt_d_mtty);
+		for(size_t i=0 ; i<N_TTYS ; i++)
+                {
+                    mtty.p_irq[i]			(signal_irq_mtty[i]);
+                }
+
+                dxbar[x][y]->p_to_target[BROM_TGTID]	(signal_vci_tgt_d_brom);
+                dxbar[x][y]->p_to_target[MTTY_TGTID]	(signal_vci_tgt_d_mtty);
+	        dxbar[x][y]->p_to_target[BDEV_TGTID]	(signal_vci_tgt_d_bdev);
+	        dxbar[x][y]->p_to_target[FBUF_TGTID]	(signal_vci_tgt_d_fbuf);
+	        dxbar[x][y]->p_to_target[CDMA_TGTID]	(signal_vci_tgt_d_cdma);
+
+	        dxbar[x][y]->p_to_initiator[BDEV_SRCID]	(signal_vci_ini_d_bdev);
+	        dxbar[x][y]->p_to_initiator[CDMA_SRCID]	(signal_vci_ini_d_cdma);
+
+                xicu[x][y]->p_hwi[0]			(signal_irq_bdev);
+                xicu[x][y]->p_hwi[1]			(signal_irq_cdma);
+		
+		for(size_t i=0 ; i<N_TTYS ; i++)
+                {
+                    xicu[x][y]->p_hwi[2+i]		(signal_irq_mtty[i]);
+                }
+            }
+        } // end for y
+    } // end for x
+
+    std::cout << "all components connected" << std::endl;
+
+    ////////////////////////////////////////////////////////
+    //   Simulation
+    ///////////////////////////////////////////////////////
+    
+    sc_start(sc_core::sc_time(0, SC_NS));
+    signal_resetn = false;
+
+    sc_start(sc_core::sc_time(1, SC_NS));
+    signal_resetn = true;
+
+    for(size_t i=1 ; i<ncycles ; i++)
+    {
+        sc_start(sc_core::sc_time(1, SC_NS));
+
+        if( debug_ok && (i > from_cycle) && (i < to_cycle) )
+        {
+        std::cout << std::dec << "*************** cycle " << i << "    ***********************" << std::endl; 
+        proc[0][0][0]->print_trace();
+        proc[0][1][0]->print_trace();
+        proc[1][0][0]->print_trace();
+        proc[1][1][0]->print_trace();
+        std::cout << std::endl;
+        dxbar[0][0]->print_trace();
+        dxbar[0][1]->print_trace();
+        dxbar[1][0]->print_trace();
+        dxbar[1][1]->print_trace();
+        std::cout << std::endl;
+        cxbar[0][0]->print_trace();
+        cxbar[0][1]->print_trace();
+        cxbar[1][0]->print_trace();
+        cxbar[1][1]->print_trace();
+        std::cout << std::endl;
+        memc[0][0]->print_trace();
+        memc[0][1]->print_trace();
+        memc[1][0]->print_trace();
+        memc[1][1]->print_trace();
+        std::cout << std::endl;
+        }
+    }
+
+    std::cout << "Hit ENTER to end simulation" << std::endl;
+    char buf[1];
+    std::cin.getline(buf,1);
+
+    for( size_t x = 0 ; x < xmax ; x++ )
+      for( size_t y = 0 ; y < ymax ; y++ )
+	for ( size_t p = 0 ; p < nprocs ; p++ ) 
+          proc[x][y][p]->print_stats();
+
+    return EXIT_SUCCESS;
+}
+
+int sc_main (int argc, char *argv[])
+{
+	try {
+		return _main(argc, argv);
+	} catch (std::exception &e) {
+		std::cout << e.what() << std::endl;
+	} catch (...) {
+		std::cout << "Unknown exception occured" << std::endl;
+		throw;
+	}
+	return 1;
+}
Index: branches/v4/platforms/tsarv4_vgmn_io_bridge/Makefile
===================================================================
--- branches/v4/platforms/tsarv4_vgmn_io_bridge/Makefile	(revision 371)
+++ branches/v4/platforms/tsarv4_vgmn_io_bridge/Makefile	(revision 371)
@@ -0,0 +1,12 @@
+
+all : simulator.x simulator_without_io_bridge.x
+
+simulator.x: tsarv4_vgmn_io_bridge_top.cpp tsarv4_vgmn_io_bridge_desc
+	soclib-cc -p tsarv4_vgmn_io_bridge_desc -o simulator.x
+
+simulator_without_io_bridge.x: tsarv4_vgmn_without_io_bridge_top.cpp tsarv4_vgmn_without_io_bridge_desc
+	soclib-cc -p tsarv4_vgmn_without_io_bridge_desc -o simulator_without_io_bridge.x
+
+clean:
+	rm -rf *.o simulator.x simulator_without_io_bridge.x temp tty*
+
Index: branches/v4/platforms/tsarv4_vgmn_io_bridge/tsarv4_vgmn_io_bridge_desc
===================================================================
--- branches/v4/platforms/tsarv4_vgmn_io_bridge/tsarv4_vgmn_io_bridge_desc	(revision 371)
+++ branches/v4/platforms/tsarv4_vgmn_io_bridge/tsarv4_vgmn_io_bridge_desc	(revision 371)
@@ -0,0 +1,70 @@
+
+# -*- python -*-
+
+todo = Platform('caba', 'tsarv4_vgmn_io_bridge_top.cpp',
+    uses = [
+#        Uses('caba:vci_cc_vcache_wrapper_v4', iss_t = 'common:mips32el'),
+        Uses('caba:vci_cc_vcache_wrapper_v4', iss_t = 'common:gdb_iss', gdb_iss_t = 'common:mips32el'),
+        Uses('caba:vci_mem_cache_v4'),
+        Uses('caba:vci_simple_ram'),
+        Uses('caba:vci_multi_tty'),
+#        Uses('caba:vci_xicu'),
+#        Uses('caba:vci_icu'),
+        Uses('caba:vci_multi_icu'),
+        Uses('caba:vci_vgmn'),
+        Uses('caba:vci_framebuffer'),
+        Uses('caba:vci_dma_tsar_v2'),
+        Uses('caba:vci_block_device_tsar_v4',),
+#        Uses('caba:vci_block_device',),
+        Uses('caba:vci_local_crossbar'),
+        Uses('caba:vci_io_bridge',
+               #vci_params on the Direct NoC
+               cell_size_d = 4,
+               plen_size_d = 8,
+               addr_size_d = 32,
+               rerror_size_d = 1,
+               clen_size_d = 1,
+               rflag_size_d = 1,
+               srcid_size_d = 14,
+               pktid_size_d = 4,
+               trdid_size_d = 4,
+               wrplen_size_d = 1,
+               #vci_params on the Xram Noc
+               cell_size_x = 4,
+               plen_size_x = 8,
+               addr_size_x = 32,
+               rerror_size_x = 1,
+               clen_size_x = 1,
+               rflag_size_x = 1,
+               srcid_size_x = 14,
+               pktid_size_x = 4,
+               trdid_size_x = 4,
+               wrplen_size_x = 1,
+               #vci_params on the IO Noc
+               cell_size_io = 4,
+               plen_size_io = 8,
+               addr_size_io = 32,
+               rerror_size_io = 1,
+               clen_size_io = 1,
+               rflag_size_io = 1,
+               srcid_size_io = 14,
+               pktid_size_io = 4,
+               trdid_size_io = 4,
+               wrplen_size_io = 1,
+             ),
+            
+        Uses('common:elf_file_loader'),
+        Uses('common:plain_file_loader')
+    ],
+    #default vci_param
+    cell_size = 4,
+    plen_size = 8,
+    addr_size = 32,
+    rerror_size = 1,
+    clen_size = 1,
+    rflag_size = 1,
+    srcid_size = 14,
+    pktid_size = 4,
+    trdid_size = 4,
+    wrplen_size = 1,
+)
Index: branches/v4/platforms/tsarv4_vgmn_io_bridge/tsarv4_vgmn_io_bridge_top.cpp
===================================================================
--- branches/v4/platforms/tsarv4_vgmn_io_bridge/tsarv4_vgmn_io_bridge_top.cpp	(revision 371)
+++ branches/v4/platforms/tsarv4_vgmn_io_bridge/tsarv4_vgmn_io_bridge_top.cpp	(revision 371)
@@ -0,0 +1,815 @@
+/////////////////////////////////////////////////////////////////////////
+// File: tsarv4_vgmn_generic_32_top.cpp
+// Author: Alain Greiner
+// Copyright: UPMC/LIP6
+// Date : november 5 2010
+// This program is released under the GNU public license
+/////////////////////////////////////////////////////////////////////////
+// This file define a generic TSAR architecture without virtual memory.
+// - It uses the vci_vgmn as global interconnect 
+// - It uses the vci_local_crossbar  as local interconnect 
+// - It uses the vci_cc_xcache (No MMU) 
+// The physical address space is 32 bits.
+// The number of clusters cannot be larger than 256.
+// The three parameters are 
+// - xmax : number of clusters in a row
+// - ymax : number of clusters in a column
+// - nprocs : number of processor per cluster
+//
+// Each cluster contains nprocs processors, one Memory Cache,
+// and one XICU component.
+// The peripherals BDEV, CDMA, FBUF, MTTY and the boot BROM
+// are in the cluster containing address 0xBFC00000.
+// - The bdev_irq is connected to IRQ_IN[0]
+// - The cdma_irq is connected to IRQ_IN[1]
+// - The tty_irq[i] is connected to IRQ_IN[i+2]
+// For all clusters, the XICU component contains nprocs timers.
+// 
+// As we target up to 256 clusters, each cluster can contain 
+// at most 16 Mbytes (in a 4Gbytes address space).
+// - Each memory cache contains 9 Mbytes.
+// - The Frame buffer contains 2 Mbytes.
+// - The Boot ROM contains 1 Mbytes.
+//
+// General policy for 32 bits address decoding:
+// To simplifly, all segments base addresses are aligned
+// on 1 Mbyte addresses. Therefore the 12 address MSB bits
+// define the target in the direct address space.
+// In these 12 bits, the (x_width + y_width) MSB bits define
+// the cluster index, and the 4 LSB bits define the local index:
+// 
+//      | X_ID  | Y_ID  |---| L_ID |     OFFSET          |
+//  |x_width|y_width|---|  4   |       20            |
+/////////////////////////////////////////////////////////////////////////
+
+#include <systemc>
+#include <sys/time.h>
+#include <iostream>
+#include <sstream>
+#include <cstdlib>
+#include <cstdarg>
+#include <stdint.h>
+
+#include "mapping_table.h"
+#include "mips32.h"
+#include "vci_simple_ram.h"
+#include "vci_multi_tty.h"
+#include "vci_mem_cache_v4.h"
+#include "vci_cc_vcache_wrapper_v4.h"
+//#include "vci_xicu.h"
+#include "vci_multi_icu.h"
+#include "vci_vgmn.h"
+#include "vci_framebuffer.h"
+#include "vci_dma_tsar_v2.h"
+#include "vci_block_device_tsar_v4.h"
+//#include "vci_block_device.h"
+#include "vci_io_bridge.h"
+#include "gdbserver.h"
+
+//#define SECTOR_SIZE 2048
+#define SECTOR_SIZE 512
+
+#define FBUF_XSIZE  128
+#define FBUF_YSIZE  128
+
+#define NB_TTYS      9
+
+//////////////////////////////////////////////
+// segments definition in direct space.
+// There is 16 Mbytes address space per cluster.
+// The 8 MSB bits define the cluster index (x,y),
+// even if the number of clusters is less than 256.
+// Each memory cache contains up to 9 Mbytes.
+// There is one MEMC segment and one XICU segment per cluster
+// The peripherals BDEV, FBUF, MTTY, CDMA and the boot BROM
+// are mapped in cluster containing address 0xBFC00000
+
+//#define MEMC_BASE   0x00000000  
+//#define MEMC_SIZE   0x00900000
+
+#define BROM_BASE   0xBFC00000  
+#define BROM_SIZE   0x00010000
+
+#define USER_BASE   0x00000000  
+#define USER_SIZE   0x01000000
+
+#define KERNEL_BASE   0x80000000  
+#define KERNEL_SIZE   0x00100000
+
+//#define XICU_BASE   0x00900000  
+//#define XICU_SIZE   0x00001000
+
+#define MTTY_BASE   0x90000000  
+#define MTTY_SIZE   0x00000200
+
+#define TIM_BASE   0x91000000  
+#define TIM_SIZE   0x00000080
+
+#define BDEV_BASE   0x92000000  
+#define BDEV_SIZE   0x00000020
+
+#define CDMA_BASE   0x93000000  
+#define CDMA_SIZE   0x00000100
+
+#define FBUF_BASE   0x96000000  
+#define FBUF_SIZE   0x00004000
+
+#define IOB_BASE    0x9E000000  
+#define IOB_SIZE    0x00000100
+
+#define ICU_BASE   0x9F000000  
+#define ICU_SIZE   0x00000100
+
+/* Pour ALMOS
+
+#define BOOT_INFO_BLOCK 0xbfc08000
+#define KERNEL_BIN_IMG  0xbfc10000
+
+*/
+
+////////////////////////////////////////////////////////////////////
+//     TGTID & SRCID definition in direct space
+// For all components:  global TGTID = global SRCID = cluster_index
+// For processors, the local SRCID is between 0 & nprocs-1
+
+#define PROC_SRCID   0
+
+#define MEMC_TGTID      4
+#define BROM_TGTID      1 
+//#define XICU_TGTID   2
+#define ICU_TGTID       2
+#define MTTY_TGTID      3
+#define IOB_TGTID   0
+//#define BDEV_TGTID  1
+//#define CDMA_TGTID  2
+//#define FBUF_TGTID  3
+
+////////////////////////////////////////////////////////////////////
+//     TGTID & SRCID definition in IO space
+
+#define IOB_TGTID_IO  0
+#define BDEV_TGTID_IO 1
+#define CDMA_TGTID_IO 2
+#define FBUF_TGTID_IO 3
+
+#define IOB_SRCID_IO  0
+#define BDEV_SRCID_IO 1
+#define CDMA_SRCID_IO 2
+
+////////////////////////////////////////////////////////
+//     TGTID & SRCID definition in coherence space
+// For all components:  global TGTID = global SRCID = cluster_index
+// For MEMC       : local SRCID = local TGTID = nprocs
+// For processors : local SRCID = local TGTID = PROC_ID
+
+///////////////
+// VCI format
+#define cell_width  4
+#define address_width 32  // 40 Ã  terme
+#define address_width_io 32
+#define plen_width  8
+#define error_width 1
+#define clen_width  1
+#define rflag_width 1
+#define srcid_width 14
+#define pktid_width 4
+#define trdid_width 4
+#define wrplen_width    1
+
+//  cluster index (computed from x,y coordinates)
+#define cluster(x,y)    (y + ymax*x)
+
+/////////////////////////////////
+int _main(int argc, char *argv[])
+{
+    using namespace sc_core;
+    using namespace soclib::caba;
+    using namespace soclib::common;
+
+    char    soft_name[128]  = "giet_vm171/soft.elf";  // pathname to binary code
+    char    disk_name[128]  = "giet_vm171/apps/display/images.raw";   // pathname to the disk image
+    size_t  ncycles         = 1000000000;           // simulated cycles
+    size_t  nprocs          = 1;            // number of processors per cluster
+    bool    debug_ok        = false;                // debug activated
+    size_t  from_cycle      = 0;                    // debug start cycle
+    size_t  to_cycle        = 1000000000;           // debug end cycle
+
+    ////////////// command line arguments //////////////////////
+    if (argc > 1)
+    {
+        for( int n=1 ; n<argc ; n=n+2 )
+        {
+            if( (strcmp(argv[n],"-NCYCLES") == 0) && (n+1<argc) )
+            {
+                ncycles = atoi(argv[n+1]);
+            }
+            else if( (strcmp(argv[n],"-NPROCS") == 0) && (n+1<argc) )
+            {
+                nprocs = atoi(argv[n+1]);
+                assert( (nprocs <= 8) && "The number of processors per cluster cannot be larger than 8");
+            }
+            else if( (strcmp(argv[n],"-SOFT") == 0) && (n+1<argc) )
+            {
+                strcpy(soft_name, argv[n+1]);
+            }
+            else if( (strcmp(argv[n],"-DISK") == 0) && (n+1<argc) )
+            {
+                strcpy(disk_name, argv[n+1]);
+            }
+            else if( (strcmp(argv[n],"-DEBUG") == 0) && (n+1<argc) )
+            {
+                debug_ok = true;
+                from_cycle = atoi(argv[n+1]);
+            }
+            else if( (strcmp(argv[n],"-TOCYCLE") == 0) && (n+1<argc) )
+            {
+                to_cycle = atoi(argv[n+1]);
+            }
+            else
+            {
+                std::cout << "   Arguments on the command line are (key,value) couples." << std::endl;
+                std::cout << "   The order is not important." << std::endl;
+                std::cout << "   Accepted arguments are :" << std::endl << std::endl;
+                std::cout << "     -SOFT elf_file_name" << std::endl;
+                std::cout << "     -DISK disk_image_file_name" << std::endl;
+                std::cout << "     -NCYCLES number_of_simulated_cycles" << std::endl;
+                std::cout << "     -NPROCS number_of_processors_per_cluster" << std::endl;
+                std::cout << "     -DEBUG debug_start_cycle" << std::endl;
+                std::cout << "     -TOCYCLE debug_end_cycle" << std::endl;
+                exit(0);
+            }
+        }
+    }
+
+    std::cout << std::endl << "***********  TSAR ARCHITECTURE  **************" << std::endl
+              << " - Interconnect = VGMN & CROSSBAR" << std::endl
+              << " - Number of clusters 1" << std::endl
+              << " - Number of processors per cluster = " << nprocs << std::endl
+              << "**********************************************" << std::endl
+              << std::endl;
+
+
+    // Define VCI parameters
+    typedef soclib::caba::VciParams<cell_width,
+                                    plen_width,
+                                    address_width,
+                                    error_width,                                   
+                                    clen_width,
+                                    rflag_width,
+                                    srcid_width,
+                                    pktid_width,
+                                    trdid_width,
+                                    wrplen_width> vci_param;
+
+    typedef soclib::caba::VciParams<cell_width,
+                                    plen_width,
+                                    address_width_io,
+                                    error_width,                                   
+                                    clen_width,
+                                    rflag_width,
+                                    srcid_width,
+                                    pktid_width,
+                                    trdid_width,
+                                    wrplen_width> vci_param_io;
+    /////////////////////
+    //  Mapping Tables
+    /////////////////////
+
+    // direct network
+    MappingTable maptabd(address_width, 
+                         IntTab(12),
+                         IntTab(srcid_width),
+                         0xFFF00000);
+
+    Segment seg_config_iob("d_seg_iob" , IOB_BASE , IOB_SIZE , IntTab(IOB_TGTID ), false);
+//    maptabd.add(Segment("d_seg_memc", MEMC_BASE, MEMC_SIZE, IntTab(MEMC_TGTID), true));
+    maptabd.add(Segment("d_seg_memc_user", USER_BASE, USER_SIZE, IntTab(MEMC_TGTID), true));
+    maptabd.add(Segment("d_seg_memc_kernel", KERNEL_BASE, KERNEL_SIZE, IntTab(MEMC_TGTID), true));
+    maptabd.add(Segment("d_seg_brom", BROM_BASE, BROM_SIZE, IntTab(BROM_TGTID), true));
+//    maptabd.add(Segment("d_seg_xicu", XICU_BASE, XICU_SIZE, IntTab(XICU_TGTID), false));
+    maptabd.add(Segment("d_seg_icu", ICU_BASE, ICU_SIZE, IntTab(ICU_TGTID), false));
+    maptabd.add(Segment("d_seg_mtty", MTTY_BASE, MTTY_SIZE, IntTab(MTTY_TGTID), false));
+    
+    //maptabd.add(Segment("d_seg_tim" , TIM_BASE , TIM_SIZE , IntTab(MEMC_TGTID ), false));
+    maptabd.add(seg_config_iob);
+    maptabd.add(Segment("d_seg_bdev", BDEV_BASE, BDEV_SIZE, IntTab(IOB_TGTID ), false));
+    maptabd.add(Segment("d_seg_cdma", CDMA_BASE, CDMA_SIZE, IntTab(IOB_TGTID ), false));
+    maptabd.add(Segment("d_seg_fbuf", FBUF_BASE, FBUF_SIZE, IntTab(IOB_TGTID ), false));
+
+    std::cout << maptabd << std::endl;
+
+    // coherence network
+    MappingTable maptabc(address_width, 
+                         IntTab(12), 
+                         IntTab(srcid_width), 
+                         0xF0000000);
+
+    std::ostringstream sm;
+    sm << "c_seg_memc_0";
+//    maptabc.add(Segment(sm.str(), MEMC_BASE, MEMC_SIZE, IntTab(nprocs), false));
+    maptabc.add(Segment(sm.str(), USER_BASE, USER_SIZE, IntTab(nprocs), false));
+    maptabc.add(Segment("c_seb_memc_kernel", KERNEL_BASE, KERNEL_SIZE, IntTab(nprocs), false));
+    // the segment base and size will be modified 
+    // when the segmentation of the coherence space will be simplified
+
+    std::ostringstream sr;
+    sr << "c_seg_brom_0";
+    maptabc.add(Segment(sr.str(), BROM_BASE, BROM_SIZE, IntTab(nprocs), false));
+
+    sc_uint<address_width> avoid_collision  = 0;
+    for ( size_t p = 0 ; p < nprocs ; p++)
+    {
+    sc_uint<address_width> base = USER_SIZE + KERNEL_SIZE + (p*0x100000);
+        // the following test is to avoid a collision between the c_seg_brom segment
+        // and a c_seg_proc segment (all segments base addresses being multiple of 1Mbytes)
+        if ( base == BROM_BASE ) avoid_collision = 0x100000;
+          std::ostringstream sp;
+          sp << "c_seg_proc_" << p;
+          maptabc.add(Segment(sp.str(), base + avoid_collision, 0x20, IntTab(p), false, true, IntTab(p))); 
+        // the two last arguments will be removed 
+        // when the segmentation of the coherence space will be simplified
+    }
+
+    std::cout << maptabc << std::endl;
+
+    // external network
+    MappingTable maptabx(address_width, IntTab(1), IntTab(srcid_width), 0xF0000000);
+
+//    maptabx.add(Segment("seg_memc_x", MEMC_BASE, MEMC_SIZE, IntTab(0), false));
+    maptabx.add(Segment("seg_memc_x_user", USER_BASE, USER_SIZE, IntTab(0), false));
+    maptabx.add(Segment("seg_memc_x_kernel", KERNEL_BASE, KERNEL_SIZE, IntTab(0), false));
+    
+    std::cout << maptabx << std::endl;
+
+    // io network
+    MappingTable maptabio(address_width, 
+                          IntTab(12),
+                          IntTab(srcid_width),
+                          0x00F00000);
+
+    maptabio.add(Segment("io_seg_iob" , IOB_BASE , IOB_SIZE , IntTab(IOB_TGTID_IO) , false));
+    maptabio.add(Segment("io_seg_bdev", BDEV_BASE, BDEV_SIZE, IntTab(BDEV_TGTID_IO), false));
+    maptabio.add(Segment("io_seg_cdma", CDMA_BASE, CDMA_SIZE, IntTab(CDMA_TGTID_IO), false));
+    maptabio.add(Segment("io_seg_fbuf", FBUF_BASE, FBUF_SIZE, IntTab(FBUF_TGTID_IO), false));
+
+    std::cout << maptabio << std::endl;
+    ////////////////////
+    // Signals
+    ///////////////////
+
+    sc_clock        signal_clk("clk");
+    sc_signal<bool>     signal_resetn("resetn");
+    sc_signal<bool> signal_false;
+   
+    // IRQ signals (one signal per proc)
+    sc_signal<bool>*    signal_proc_it =
+      alloc_elems<sc_signal<bool> >("signal_proc_it", nprocs);
+
+    sc_signal<bool>*    signal_irq_mtty = 
+        alloc_elems<sc_signal<bool> >("signal_irq_mtty", NB_TTYS);
+
+    sc_signal<bool> signal_irq_bdev;
+    sc_signal<bool> signal_irq_cdma;
+
+    sc_signal<bool> empty;
+    
+    // Direct VCI signals
+    VciSignals<vci_param>* signal_vci_ini_d_proc = 
+        alloc_elems<VciSignals<vci_param> >("signal_vci_ini_d_proc", nprocs);
+    VciSignals<vci_param> signal_vci_ini_d_iob("signal_vci_ini_d_iob");
+
+    VciSignals<vci_param> signal_vci_tgt_d_memc("signal_vci_tgt_d_memc");
+    VciSignals<vci_param> signal_vci_tgt_d_brom("signal_vci_tgt_d_brom");
+//    VciSignals<vci_param> signal_vci_tgt_d_xicu("signal_vci_tgt_d_xicu");
+    VciSignals<vci_param> signal_vci_tgt_d_icu("signal_vci_tgt_d_icu");
+    VciSignals<vci_param> signal_vci_tgt_d_mtty("signal_vci_tgt_d_mtty");
+    VciSignals<vci_param> signal_vci_tgt_d_iob("signal_vci_tgt_d_iob");
+
+    // IO network VCI signals
+    VciSignals<vci_param_io> signal_vci_tgt_io_iob ("signal_vci_tgt_io_iob");
+    VciSignals<vci_param_io> signal_vci_tgt_io_bdev("signal_vci_tgt_io_bdev");
+    VciSignals<vci_param_io> signal_vci_tgt_io_cdma("signal_vci_tgt_io_cdma");
+    VciSignals<vci_param_io> signal_vci_tgt_io_fbuf("signal_vci_tgt_io_fbuf");
+
+    VciSignals<vci_param_io> signal_vci_ini_io_bdev("signal_vci_ini_io_bdev");
+    VciSignals<vci_param_io> signal_vci_ini_io_cdma("signal_vci_ini_io_cdma");
+    VciSignals<vci_param_io> signal_vci_ini_io_iob ("signal_vci_ini_io_iob");
+
+    // Coherence VCI signals
+
+    VciSignals<vci_param>* signal_vci_ini_c_proc = 
+        alloc_elems<VciSignals<vci_param> >("signal_vci_ini_c_proc", nprocs);
+
+    VciSignals<vci_param>* signal_vci_tgt_c_proc = 
+        alloc_elems<VciSignals<vci_param> >("signal_vci_tgt_c_proc", nprocs);
+
+    VciSignals<vci_param> signal_vci_ini_c_memc("signal_vci_ini_c_memc");
+    VciSignals<vci_param> signal_vci_tgt_c_memc("signal_vci_tgt_c_memc");
+
+    // Xternal network VCI signals
+
+    VciSignals<vci_param> signal_vci_tgt_x_xram("signal_vci_tgt_x_xram");
+    VciSignals<vci_param> signal_vci_ini_x_memc("signal_vci_ini_x_memc");
+    VciSignals<vci_param> signal_vci_ini_x_iob("signal_vci_ini_x_iob");
+
+    ////////////////////////////
+    //      Components
+    ////////////////////////////
+
+    typedef soclib::common::GdbServer<soclib::common::Mips32ElIss> proc_iss;
+
+    
+    soclib::common::Loader loader(soft_name);
+    proc_iss::set_loader(loader);
+    
+
+    // External RAM
+    VciSimpleRam<vci_param> xram(
+        "xram", 
+        IntTab(0), 
+        maptabx, 
+        loader);
+
+    // External network
+    VciVgmn<vci_param> xnoc(
+        "xnoc",
+        maptabx, 
+        2,
+        1, 
+        2,
+    2);
+
+    // Direct network
+    VciVgmn<vci_param> dnoc(
+        "dnoc",
+        maptabd, 
+        nprocs+1,
+        5,
+        2, 2);
+
+    // Coherence network
+    VciVgmn<vci_param> cnoc(
+        "cnoc",
+        maptabc, 
+        nprocs+1,
+        nprocs+1,
+        2, 2);
+
+    // IO network
+    VciVgmn<vci_param_io> ionoc(
+        "ionoc",
+        maptabio, 
+        3,
+        4,
+        2, 2);
+
+
+    // Peripherals : TTY, Frame Buffer, Block Device, Boot ROM, & DMA 
+    VciSimpleRam<vci_param> brom(
+        "brom", 
+        IntTab(BROM_TGTID), 
+        maptabd, 
+        loader);
+    
+
+    VciIoBridge<vci_param, vci_param, vci_param_io> iob(
+        "vci_iob",
+        3,          // number of peripherals
+        maptabx,
+        maptabd,
+        maptabio,
+/**/    seg_config_iob,
+        IntTab(),
+//        IntTab(IOB_TGTID),
+        IntTab(nprocs),
+        IntTab(IOB_TGTID_IO),
+        IntTab(IOB_SRCID_IO),
+        IntTab(1),
+        16,
+        4,
+        4,
+        from_cycle,
+        debug_ok
+        );
+    
+
+    VciMultiTty<vci_param> mtty(
+        "mtty",
+        IntTab(MTTY_TGTID),
+        maptabd,
+        "tty0","tty1","tty2","tty3",
+        "tty4","tty5","tty6","tty7",
+        "tty8", NULL);
+
+    VciFrameBuffer<vci_param_io> fbuf(
+        "fbuf", 
+        IntTab(FBUF_TGTID_IO),
+        maptabio, 
+        FBUF_XSIZE,
+        FBUF_YSIZE);
+
+    VciBlockDeviceTsarV4<vci_param_io> bdev(
+//    VciBlockDevice<vci_param_io> bdev(
+        "bdev", 
+        maptabio, 
+        IntTab(BDEV_SRCID_IO), // SRCID_D
+        IntTab(BDEV_TGTID_IO), // TGTID_D
+        disk_name, 
+        SECTOR_SIZE); 
+
+    VciDmaTsarV2<vci_param_io> cdma(
+        "cdma",
+        maptabio,
+        IntTab(CDMA_SRCID_IO), // SRCID_D
+        IntTab(CDMA_TGTID_IO), // TGTID_D
+        64); 
+
+    // processors (nprocs per cluster)
+
+    VciCcVCacheWrapperV4<vci_param, proc_iss> *proc[nprocs];
+
+    for ( size_t p = 0 ; p < nprocs ; p++ ) 
+    {
+      
+      std::ostringstream sp;
+      sp << "proc_" << "_" << p;
+                   
+      proc[p] = new VciCcVCacheWrapperV4<vci_param, proc_iss>(
+        sp.str().c_str(),
+        p, 
+        maptabd, maptabc,
+        IntTab(PROC_SRCID+p),       // SRCID_D
+        IntTab(PROC_SRCID+p),       // SRCID_C
+        IntTab(PROC_SRCID+p),       // TGTID_C
+        4,4,                // itlb ways, sets
+        4,4,                // dtlb ways, sets
+        4,64,16,4,64,16,    // Icache and Dcache sizes (way, set, words)
+        4,8,
+        20000000,
+        from_cycle,
+        debug_ok
+        );
+    }
+
+    //  memory caches (one per cluster)
+    VciMemCacheV4<vci_param> memc(
+        sm.str().c_str(),
+        maptabd, maptabc, maptabx,
+        IntTab(0),              // SRCID_X
+        IntTab(nprocs),         // SRCID_C
+        IntTab(MEMC_TGTID),     // TGTID_D
+        IntTab(nprocs),         // TGTID_C
+        16,256,16,              // CACHE SIZE
+        4096,                   // HEAP SIZE
+        4,4,                    // TRANSACTION and UPDATE TAB lines
+        from_cycle,
+        debug_ok
+        );                 
+/*
+    // XICU (one per cluster)
+    VciXicu<vci_param> xicu(
+        "vci_xicu",
+        maptabd,
+        IntTab(XICU_TGTID),     // TGTID_D
+        nprocs,                 // number of TIMERS
+        NB_TTYS,                      // number of hard IRQs
+        nprocs+1,               // number of soft IRQs
+        nprocs);                // number of output IRQ lines
+*/
+    // ICU
+/*   
+    VciIcu<vci_param> icu(
+        "vci_icu",
+        IntTab(ICU_TGTID),     // TGTID_D
+        maptabd,
+        NB_TTYS + 2             // number of hard IRQs
+        );                
+*/
+    VciMultiIcu<vci_param> *icu;
+      icu = new VciMultiIcu<vci_param>("icu",
+              IntTab(ICU_TGTID),
+              maptabd,
+              32,           // number of irq in
+              1); //NB_PROCS number of irq out
+   
+ 
+    std::cout << "all components created" << std::endl;
+
+    ///////////////////////////////////////////////////////////////
+    //     Net-list 
+    ///////////////////////////////////////////////////////////////
+
+    // External Ram (one instance)
+    xram.p_clk                      (signal_clk);
+    xram.p_resetn                   (signal_resetn);
+    xram.p_vci                      (signal_vci_tgt_x_xram);    
+
+    // External Network (one instance)
+    xnoc.p_clk                      (signal_clk);
+    xnoc.p_resetn                   (signal_resetn);
+    xnoc.p_to_target[0]             (signal_vci_tgt_x_xram);
+    xnoc.p_to_initiator[0]          (signal_vci_ini_x_memc);
+    xnoc.p_to_initiator[1]          (signal_vci_ini_x_iob);
+
+    // Direct Network (one instance)
+    dnoc.p_clk                      (signal_clk);
+    dnoc.p_resetn                   (signal_resetn);
+    dnoc.p_to_target[MEMC_TGTID]    (signal_vci_tgt_d_memc);
+    dnoc.p_to_target[BROM_TGTID]    (signal_vci_tgt_d_brom);
+//    dnoc.p_to_target[XICU_TGTID]    (signal_vci_tgt_d_xicu);
+    dnoc.p_to_target[ICU_TGTID]    (signal_vci_tgt_d_icu);
+    dnoc.p_to_target[MTTY_TGTID]    (signal_vci_tgt_d_mtty);
+    dnoc.p_to_target[IOB_TGTID]     (signal_vci_tgt_d_iob);
+//    dnoc.p_to_target[BDEV_TGTID]     (signal_vci_tgt_d_iob);
+//    dnoc.p_to_target[CDMA_TGTID]     (signal_vci_tgt_d_iob);
+//    dnoc.p_to_target[FBUF_TGTID]     (signal_vci_tgt_d_iob);
+    
+    dnoc.p_to_initiator[nprocs]     (signal_vci_ini_d_iob);
+
+
+    // Coherence Network (one instance)
+    cnoc.p_clk                      (signal_clk);
+    cnoc.p_resetn                   (signal_resetn);
+    cnoc.p_to_initiator[nprocs]     (signal_vci_ini_c_memc);
+    cnoc.p_to_target[nprocs]        (signal_vci_tgt_c_memc);
+
+    // Processors
+    for ( size_t p = 0 ; p < nprocs ; p++ )
+    {
+        dnoc.p_to_initiator[p]    (signal_vci_ini_d_proc[p]);
+        cnoc.p_to_initiator[p]    (signal_vci_ini_c_proc[p]);
+        cnoc.p_to_target[p]       (signal_vci_tgt_c_proc[p]);
+
+        proc[p]->p_clk            (signal_clk);  
+        proc[p]->p_resetn         (signal_resetn);  
+        proc[p]->p_vci_ini_d      (signal_vci_ini_d_proc[p]);
+        proc[p]->p_vci_ini_c      (signal_vci_ini_c_proc[p]);
+        proc[p]->p_vci_tgt_c      (signal_vci_tgt_c_proc[p]);
+        proc[p]->p_irq[0]         (signal_proc_it[p]);
+        for ( size_t j = 1 ; j < 6 ; j++ )
+        {
+            proc[p]->p_irq[j]      (signal_false); 
+        }
+    }
+
+    std::cout << "ionoc: begin" << std::endl;
+    
+    ionoc.p_clk                         (signal_clk);
+    ionoc.p_resetn                      (signal_resetn);
+    ionoc.p_to_initiator[IOB_SRCID_IO]  (signal_vci_ini_io_iob);
+    ionoc.p_to_initiator[BDEV_SRCID_IO] (signal_vci_ini_io_bdev);
+    ionoc.p_to_initiator[CDMA_SRCID_IO] (signal_vci_ini_io_cdma);
+    ionoc.p_to_target[IOB_TGTID_IO]     (signal_vci_tgt_io_iob);
+    ionoc.p_to_target[BDEV_TGTID_IO]    (signal_vci_tgt_io_bdev);
+    ionoc.p_to_target[CDMA_TGTID_IO]    (signal_vci_tgt_io_cdma);
+    ionoc.p_to_target[FBUF_TGTID_IO]    (signal_vci_tgt_io_fbuf);
+
+    std::cout << "ionoc: end" << std::endl;
+/*
+    // XICU
+    xicu.p_clk               (signal_clk);
+    xicu.p_resetn            (signal_resetn);
+    xicu.p_vci               (signal_vci_tgt_d_xicu);
+    for ( size_t p = 0 ; p < nprocs ; p++ )
+    {
+        xicu.p_irq[p]            (signal_proc_it[p]);
+    }
+
+    for(size_t i=0 ; i<NB_TTYS ; i++)
+    {
+        xicu.p_hwi[i]          (signal_irq_mtty[i]);
+    }
+*/
+    // ICU
+    icu->p_clk               (signal_clk);
+    icu->p_resetn            (signal_resetn);
+    icu->p_vci               (signal_vci_tgt_d_icu);
+    icu->p_irq_out[0]        (signal_proc_it[0]);
+
+    for (size_t i = 0 ; i < 32 ; i++ )
+    {   
+//       if      ( i < NB_TIMERS )      icu->p_irq_in[i] (signal_irq_tim[i]);
+        if ( i < 8 )              icu->p_irq_in[i] (signal_false);
+        else if ( i == 8)              icu->p_irq_in[i] (signal_irq_cdma);
+        else if ( i < 16 )             icu->p_irq_in[i] (signal_false);
+        else if ( i < (16 + NB_TTYS) ) icu->p_irq_in[i] (signal_irq_mtty[i-16]);
+        else if ( i < 31 )             icu->p_irq_in[i] (signal_false);
+        else                           icu->p_irq_in[i] (signal_irq_bdev);
+    }   
+ 
+    // MEMC
+    memc.p_clk               (signal_clk);
+    memc.p_resetn            (signal_resetn);
+    memc.p_vci_tgt           (signal_vci_tgt_d_memc);  
+    memc.p_vci_ini           (signal_vci_ini_c_memc);
+    memc.p_vci_tgt_cleanup   (signal_vci_tgt_c_memc);
+    memc.p_vci_ixr           (signal_vci_ini_x_memc);
+
+    brom.p_clk                (signal_clk);
+    brom.p_resetn             (signal_resetn);
+    brom.p_vci                (signal_vci_tgt_d_brom);
+
+    mtty.p_clk                (signal_clk);
+    mtty.p_resetn             (signal_resetn);
+    mtty.p_vci                (signal_vci_tgt_d_mtty);
+
+    for(size_t i=0 ; i<NB_TTYS ; i++)
+    {
+        mtty.p_irq[i]           (signal_irq_mtty[i]);
+    }
+
+    std::cout << "iob: begin" << std::endl;
+    
+    iob.p_clk                 (signal_clk);
+    iob.p_resetn              (signal_resetn);
+//    iob.p_irq_in[0]           (signal_irq_cdma);
+//    iob.p_irq_in[1]           (signal_irq_bdev);
+    iob.p_irq_in[0]           (empty);
+    iob.p_irq_in[1]           (empty);
+    iob.p_irq_in[2]           (empty);
+    iob.p_vci_ini_dma         (signal_vci_ini_x_iob);
+    iob.p_vci_tgt_dma         (signal_vci_tgt_io_iob);
+    iob.p_vci_ini_config      (signal_vci_ini_io_iob);
+    iob.p_vci_ini_miss        (signal_vci_ini_d_iob);
+    iob.p_vci_tgt_config      (signal_vci_tgt_d_iob);
+    
+    std::cout << "iob: end" << std::endl;
+
+    bdev.p_clk                (signal_clk);
+    bdev.p_resetn             (signal_resetn);
+    bdev.p_irq                (signal_irq_bdev); 
+    bdev.p_vci_target         (signal_vci_tgt_io_bdev);
+    bdev.p_vci_initiator      (signal_vci_ini_io_bdev);
+
+    cdma.p_clk                (signal_clk);
+    cdma.p_resetn             (signal_resetn);
+    cdma.p_irq                (signal_irq_cdma); 
+    cdma.p_vci_target         (signal_vci_tgt_io_cdma);
+    cdma.p_vci_initiator      (signal_vci_ini_io_cdma);
+
+    fbuf.p_clk                (signal_clk); 
+    fbuf.p_resetn             (signal_resetn); 
+    fbuf.p_vci                (signal_vci_tgt_io_fbuf); 
+
+
+    std::cout << "all components connected" << std::endl;
+
+    ////////////////////////////////////////////////////////
+    //   Simulation
+    ///////////////////////////////////////////////////////
+    
+    sc_start(sc_core::sc_time(0, SC_NS));
+    signal_resetn = false;
+
+    sc_start(sc_core::sc_time(1, SC_NS));
+    signal_resetn = true;
+    char buf[1];
+
+    for(size_t i=1 ; i<ncycles ; i++)
+    {
+        sc_start(sc_core::sc_time(1, SC_NS));
+
+        if( debug_ok && (i > from_cycle) && (i < to_cycle) )
+        {
+        std::cout << std::dec << "*************** cycle " << i << "    ***********************" << std::endl; 
+        proc[0]->print_trace();
+        std::cout << std::endl;
+        
+        memc.print_trace();
+        std::cout << std::endl;
+
+        iob.print_trace();
+        std::cout << std::endl;
+        
+        icu->print_trace();
+        std::cout << std::endl;
+        
+        bdev.print_trace();
+        std::cout << std::endl;
+        
+        xram.print_trace();
+        std::cout << std::endl;
+        } 
+    }
+
+    std::cout << "Hit ENTER to end simulation" << std::endl;
+    std::cin.getline(buf,1);
+
+//  for ( size_t p = 0 ; p < nprocs ; p++ ) 
+//        proc[p]->print_stats();
+
+    return EXIT_SUCCESS;
+}
+
+int sc_main (int argc, char *argv[])
+{
+    try {
+        return _main(argc, argv);
+    } catch (std::exception &e) {
+        std::cout << e.what() << std::endl;
+    } catch (...) {
+        std::cout << "Unknown exception occured" << std::endl;
+        throw;
+    }
+    return 1;
+}
Index: branches/v4/platforms/tsarv4_vgmn_io_bridge/tsarv4_vgmn_without_io_bridge_desc
===================================================================
--- branches/v4/platforms/tsarv4_vgmn_io_bridge/tsarv4_vgmn_without_io_bridge_desc	(revision 371)
+++ branches/v4/platforms/tsarv4_vgmn_io_bridge/tsarv4_vgmn_without_io_bridge_desc	(revision 371)
@@ -0,0 +1,35 @@
+
+# -*- python -*-
+
+todo = Platform('caba', 'tsarv4_vgmn_without_io_bridge_top.cpp',
+    uses = [
+#        Uses('caba:vci_cc_vcache_wrapper_v4', iss_t = 'common:mips32el'),
+        Uses('caba:vci_cc_vcache_wrapper_v4', iss_t = 'common:gdb_iss', gdb_iss_t = 'common:mips32el'),
+        Uses('caba:vci_mem_cache_v4'),
+        Uses('caba:vci_simple_ram'),
+        Uses('caba:vci_multi_tty'),
+#        Uses('caba:vci_xicu'),
+#        Uses('caba:vci_icu'),
+        Uses('caba:vci_multi_icu'),
+        Uses('caba:vci_vgmn'),
+        Uses('caba:vci_framebuffer'),
+        Uses('caba:vci_dma_tsar_v2'),
+        Uses('caba:vci_block_device_tsar_v4',),
+#        Uses('caba:vci_block_device',),
+        Uses('caba:vci_local_crossbar'),
+            
+        Uses('common:elf_file_loader'),
+        Uses('common:plain_file_loader')
+    ],
+    #default vci_param
+    cell_size = 4,
+    plen_size = 8,
+    addr_size = 32,
+    rerror_size = 1,
+    clen_size = 1,
+    rflag_size = 1,
+    srcid_size = 14,
+    pktid_size = 4,
+    trdid_size = 4,
+    wrplen_size = 1,
+)
Index: branches/v4/platforms/tsarv4_vgmn_io_bridge/tsarv4_vgmn_without_io_bridge_top.cpp
===================================================================
--- branches/v4/platforms/tsarv4_vgmn_io_bridge/tsarv4_vgmn_without_io_bridge_top.cpp	(revision 371)
+++ branches/v4/platforms/tsarv4_vgmn_io_bridge/tsarv4_vgmn_without_io_bridge_top.cpp	(revision 371)
@@ -0,0 +1,732 @@
+/////////////////////////////////////////////////////////////////////////
+// File: tsarv4_vgmn_generic_32_top.cpp
+// Author: Alain Greiner
+// Copyright: UPMC/LIP6
+// Date : november 5 2010
+// This program is released under the GNU public license
+/////////////////////////////////////////////////////////////////////////
+// This file define a generic TSAR architecture without virtual memory.
+// - It uses the vci_vgmn as global interconnect 
+// - It uses the vci_local_crossbar  as local interconnect 
+// - It uses the vci_cc_xcache (No MMU) 
+// The physical address space is 32 bits.
+// The number of clusters cannot be larger than 256.
+// The three parameters are 
+// - xmax : number of clusters in a row
+// - ymax : number of clusters in a column
+// - nprocs : number of processor per cluster
+//
+// Each cluster contains nprocs processors, one Memory Cache,
+// and one XICU component.
+// The peripherals BDEV, CDMA, FBUF, MTTY and the boot BROM
+// are in the cluster containing address 0xBFC00000.
+// - The bdev_irq is connected to IRQ_IN[0]
+// - The cdma_irq is connected to IRQ_IN[1]
+// - The tty_irq[i] is connected to IRQ_IN[i+2]
+// For all clusters, the XICU component contains nprocs timers.
+// 
+// As we target up to 256 clusters, each cluster can contain 
+// at most 16 Mbytes (in a 4Gbytes address space).
+// - Each memory cache contains 9 Mbytes.
+// - The Frame buffer contains 2 Mbytes.
+// - The Boot ROM contains 1 Mbytes.
+//
+// General policy for 32 bits address decoding:
+// To simplifly, all segments base addresses are aligned
+// on 1 Mbyte addresses. Therefore the 12 address MSB bits
+// define the target in the direct address space.
+// In these 12 bits, the (x_width + y_width) MSB bits define
+// the cluster index, and the 4 LSB bits define the local index:
+// 
+//      | X_ID  | Y_ID  |---| L_ID |     OFFSET          |
+//  |x_width|y_width|---|  4   |       20            |
+/////////////////////////////////////////////////////////////////////////
+
+#include <systemc>
+#include <sys/time.h>
+#include <iostream>
+#include <sstream>
+#include <cstdlib>
+#include <cstdarg>
+#include <stdint.h>
+
+#include "mapping_table.h"
+#include "mips32.h"
+#include "vci_simple_ram.h"
+#include "vci_multi_tty.h"
+#include "vci_mem_cache_v4.h"
+#include "vci_cc_vcache_wrapper_v4.h"
+//#include "vci_xicu.h"
+#include "vci_multi_icu.h"
+#include "vci_vgmn.h"
+#include "vci_framebuffer.h"
+#include "vci_dma_tsar_v2.h"
+#include "vci_block_device_tsar_v4.h"
+//#include "vci_block_device.h"
+//#include "vci_io_bridge.h"
+#include "gdbserver.h"
+
+//#define SECTOR_SIZE 2048
+#define SECTOR_SIZE 512
+
+#define FBUF_XSIZE  128
+#define FBUF_YSIZE  128
+
+#define NB_TTYS      9
+
+//////////////////////////////////////////////
+// segments definition in direct space.
+// There is 16 Mbytes address space per cluster.
+// The 8 MSB bits define the cluster index (x,y),
+// even if the number of clusters is less than 256.
+// Each memory cache contains up to 9 Mbytes.
+// There is one MEMC segment and one XICU segment per cluster
+// The peripherals BDEV, FBUF, MTTY, CDMA and the boot BROM
+// are mapped in cluster containing address 0xBFC00000
+
+//#define MEMC_BASE   0x00000000  
+//#define MEMC_SIZE   0x00900000
+
+#define BROM_BASE   0xBFC00000  
+#define BROM_SIZE   0x00010000
+
+#define USER_BASE   0x00000000  
+#define USER_SIZE   0x01000000
+
+#define KERNEL_BASE   0x80000000  
+#define KERNEL_SIZE   0x00100000
+
+//#define XICU_BASE   0x00900000  
+//#define XICU_SIZE   0x00001000
+
+#define MTTY_BASE   0x90000000  
+#define MTTY_SIZE   0x00000200
+
+#define TIM_BASE   0x91000000  
+#define TIM_SIZE   0x00000080
+
+#define BDEV_BASE   0x92000000  
+#define BDEV_SIZE   0x00000020
+
+#define CDMA_BASE   0x93000000  
+#define CDMA_SIZE   0x00000100
+
+#define FBUF_BASE   0x96000000  
+#define FBUF_SIZE   0x00004000
+
+//#define IOB_BASE    0x9E000000  
+//#define IOB_SIZE    0x00000100
+
+#define ICU_BASE   0x9F000000  
+#define ICU_SIZE   0x00000100
+
+/* Pour ALMOS
+
+#define BOOT_INFO_BLOCK 0xbfc08000
+#define KERNEL_BIN_IMG  0xbfc10000
+
+*/
+
+////////////////////////////////////////////////////////////////////
+//     TGTID & SRCID definition in direct space
+// For all components:  global TGTID = global SRCID = cluster_index
+// For processors, the local SRCID is between 0 & nprocs-1
+
+#define PROC_SRCID   0
+#define BDEV_SRCID 1
+#define CDMA_SRCID 2
+
+#define MEMC_TGTID      4
+#define BROM_TGTID      1 
+//#define XICU_TGTID   2
+#define ICU_TGTID       2
+#define MTTY_TGTID      3
+//#define IOB_TGTID   0
+#define BDEV_TGTID  0
+#define CDMA_TGTID  5
+#define FBUF_TGTID  6
+
+////////////////////////////////////////////////////////////////////
+//     TGTID & SRCID definition in IO space
+
+//#define IOB_TGTID_IO  0
+//#define BDEV_TGTID_IO 1
+//#define CDMA_TGTID_IO 2
+//#define FBUF_TGTID_IO 3
+
+//#define IOB_SRCID_IO  0
+//#define BDEV_SRCID_IO 1
+//#define CDMA_SRCID_IO 2
+
+////////////////////////////////////////////////////////
+//     TGTID & SRCID definition in coherence space
+// For all components:  global TGTID = global SRCID = cluster_index
+// For MEMC       : local SRCID = local TGTID = nprocs
+// For processors : local SRCID = local TGTID = PROC_ID
+
+///////////////
+// VCI format
+#define cell_width  4
+#define address_width 32  // 40 Ã  terme
+#define address_width_io 32
+#define plen_width  8
+#define error_width 1
+#define clen_width  1
+#define rflag_width 1
+#define srcid_width 14
+#define pktid_width 4
+#define trdid_width 4
+#define wrplen_width    1
+
+//  cluster index (computed from x,y coordinates)
+#define cluster(x,y)    (y + ymax*x)
+
+/////////////////////////////////
+int _main(int argc, char *argv[])
+{
+    using namespace sc_core;
+    using namespace soclib::caba;
+    using namespace soclib::common;
+
+    char    soft_name[128]  = "giet_vm171/soft.elf";  // pathname to binary code
+    char    disk_name[128]  = "giet_vm171/apps/display/images.raw";   // pathname to the disk image
+    size_t  ncycles         = 1000000000;           // simulated cycles
+    size_t  nprocs          = 1;            // number of processors per cluster
+    bool    debug_ok        = false;                // debug activated
+    size_t  from_cycle      = 0;                    // debug start cycle
+    size_t  to_cycle        = 1000000000;           // debug end cycle
+
+    ////////////// command line arguments //////////////////////
+    if (argc > 1)
+    {
+        for( int n=1 ; n<argc ; n=n+2 )
+        {
+            if( (strcmp(argv[n],"-NCYCLES") == 0) && (n+1<argc) )
+            {
+                ncycles = atoi(argv[n+1]);
+            }
+            else if( (strcmp(argv[n],"-NPROCS") == 0) && (n+1<argc) )
+            {
+                nprocs = atoi(argv[n+1]);
+                assert( (nprocs <= 8) && "The number of processors per cluster cannot be larger than 8");
+            }
+            else if( (strcmp(argv[n],"-SOFT") == 0) && (n+1<argc) )
+            {
+                strcpy(soft_name, argv[n+1]);
+            }
+            else if( (strcmp(argv[n],"-DISK") == 0) && (n+1<argc) )
+            {
+                strcpy(disk_name, argv[n+1]);
+            }
+            else if( (strcmp(argv[n],"-DEBUG") == 0) && (n+1<argc) )
+            {
+                debug_ok = true;
+                from_cycle = atoi(argv[n+1]);
+            }
+            else if( (strcmp(argv[n],"-TOCYCLE") == 0) && (n+1<argc) )
+            {
+                to_cycle = atoi(argv[n+1]);
+            }
+            else
+            {
+                std::cout << "   Arguments on the command line are (key,value) couples." << std::endl;
+                std::cout << "   The order is not important." << std::endl;
+                std::cout << "   Accepted arguments are :" << std::endl << std::endl;
+                std::cout << "     -SOFT elf_file_name" << std::endl;
+                std::cout << "     -DISK disk_image_file_name" << std::endl;
+                std::cout << "     -NCYCLES number_of_simulated_cycles" << std::endl;
+                std::cout << "     -NPROCS number_of_processors_per_cluster" << std::endl;
+                std::cout << "     -DEBUG debug_start_cycle" << std::endl;
+                std::cout << "     -TOCYCLE debug_end_cycle" << std::endl;
+                exit(0);
+            }
+        }
+    }
+
+    std::cout << std::endl << "***********  TSAR ARCHITECTURE  **************" << std::endl
+              << " - Interconnect = VGMN & CROSSBAR" << std::endl
+              << " - Number of clusters 1" << std::endl
+              << " - Number of processors per cluster = " << nprocs << std::endl
+              << "**********************************************" << std::endl
+              << std::endl;
+
+
+    // Define VCI parameters
+    typedef soclib::caba::VciParams<cell_width,
+                                    plen_width,
+                                    address_width,
+                                    error_width,                                   
+                                    clen_width,
+                                    rflag_width,
+                                    srcid_width,
+                                    pktid_width,
+                                    trdid_width,
+                                    wrplen_width> vci_param;
+
+    typedef soclib::caba::VciParams<cell_width,
+                                    plen_width,
+                                    address_width_io,
+                                    error_width,                                   
+                                    clen_width,
+                                    rflag_width,
+                                    srcid_width,
+                                    pktid_width,
+                                    trdid_width,
+                                    wrplen_width> vci_param_io;
+    /////////////////////
+    //  Mapping Tables
+    /////////////////////
+
+    // direct network
+    MappingTable maptabd(address_width, 
+                         IntTab(12),
+                         IntTab(srcid_width),
+                         0xFFF00000);
+
+//    maptabd.add(Segment("d_seg_memc", MEMC_BASE, MEMC_SIZE, IntTab(MEMC_TGTID), true));
+    maptabd.add(Segment("d_seg_memc_user", USER_BASE, USER_SIZE, IntTab(MEMC_TGTID), true));
+    maptabd.add(Segment("d_seg_memc_kernel", KERNEL_BASE, KERNEL_SIZE, IntTab(MEMC_TGTID), true));
+    maptabd.add(Segment("d_seg_brom", BROM_BASE, BROM_SIZE, IntTab(BROM_TGTID), true));
+//    maptabd.add(Segment("d_seg_xicu", XICU_BASE, XICU_SIZE, IntTab(XICU_TGTID), false));
+    maptabd.add(Segment("d_seg_icu", ICU_BASE, ICU_SIZE, IntTab(ICU_TGTID), false));
+    maptabd.add(Segment("d_seg_mtty", MTTY_BASE, MTTY_SIZE, IntTab(MTTY_TGTID), false));
+    
+    //maptabd.add(Segment("d_seg_tim" , TIM_BASE , TIM_SIZE , IntTab(MEMC_TGTID ), false));
+    maptabd.add(Segment("d_seg_bdev", BDEV_BASE, BDEV_SIZE, IntTab(BDEV_TGTID ), false));
+    maptabd.add(Segment("d_seg_cdma", CDMA_BASE, CDMA_SIZE, IntTab(CDMA_TGTID ), false));
+    maptabd.add(Segment("d_seg_fbuf", FBUF_BASE, FBUF_SIZE, IntTab(FBUF_TGTID ), false));
+
+    std::cout << maptabd << std::endl;
+
+    // coherence network
+    MappingTable maptabc(address_width, 
+                         IntTab(12), 
+                         IntTab(srcid_width), 
+                         0xF0000000);
+
+    std::ostringstream sm;
+    sm << "c_seg_memc_0";
+//    maptabc.add(Segment(sm.str(), MEMC_BASE, MEMC_SIZE, IntTab(nprocs), false));
+    maptabc.add(Segment(sm.str(), USER_BASE, USER_SIZE, IntTab(nprocs), false));
+    maptabc.add(Segment("c_seb_memc_kernel", KERNEL_BASE, KERNEL_SIZE, IntTab(nprocs), false));
+    // the segment base and size will be modified 
+    // when the segmentation of the coherence space will be simplified
+
+    std::ostringstream sr;
+    sr << "c_seg_brom_0";
+    maptabc.add(Segment(sr.str(), BROM_BASE, BROM_SIZE, IntTab(nprocs), false));
+
+    sc_uint<address_width> avoid_collision  = 0;
+    for ( size_t p = 0 ; p < nprocs ; p++)
+    {
+    sc_uint<address_width> base = USER_SIZE + KERNEL_SIZE + (p*0x100000);
+        // the following test is to avoid a collision between the c_seg_brom segment
+        // and a c_seg_proc segment (all segments base addresses being multiple of 1Mbytes)
+        if ( base == BROM_BASE ) avoid_collision = 0x100000;
+          std::ostringstream sp;
+          sp << "c_seg_proc_" << p;
+          maptabc.add(Segment(sp.str(), base + avoid_collision, 0x20, IntTab(p), false, true, IntTab(p))); 
+        // the two last arguments will be removed 
+        // when the segmentation of the coherence space will be simplified
+    }
+
+    std::cout << maptabc << std::endl;
+
+    // external network
+    MappingTable maptabx(address_width, IntTab(1), IntTab(srcid_width), 0xF0000000);
+
+//    maptabx.add(Segment("seg_memc_x", MEMC_BASE, MEMC_SIZE, IntTab(0), false));
+    maptabx.add(Segment("seg_memc_x_user", USER_BASE, USER_SIZE, IntTab(0), false));
+    maptabx.add(Segment("seg_memc_x_kernel", KERNEL_BASE, KERNEL_SIZE, IntTab(0), false));
+    
+    std::cout << maptabx << std::endl;
+
+    ////////////////////
+    // Signals
+    ///////////////////
+
+    sc_clock        signal_clk("clk");
+    sc_signal<bool>     signal_resetn("resetn");
+    sc_signal<bool> signal_false;
+   
+    // IRQ signals (one signal per proc)
+    sc_signal<bool>*    signal_proc_it =
+      alloc_elems<sc_signal<bool> >("signal_proc_it", nprocs);
+
+    sc_signal<bool>*    signal_irq_mtty = 
+        alloc_elems<sc_signal<bool> >("signal_irq_mtty", NB_TTYS);
+
+    sc_signal<bool> signal_irq_bdev;
+    sc_signal<bool> signal_irq_cdma;
+
+    sc_signal<bool> empty;
+    
+    // Direct VCI signals
+    
+    VciSignals<vci_param>* signal_vci_ini_d_proc = 
+        alloc_elems<VciSignals<vci_param> >("signal_vci_ini_d_proc", nprocs);
+    VciSignals<vci_param_io> signal_vci_ini_d_bdev("signal_vci_ini_d_bdev");
+    VciSignals<vci_param_io> signal_vci_ini_d_cdma("signal_vci_ini_d_cdma");
+
+    VciSignals<vci_param> signal_vci_tgt_d_memc("signal_vci_tgt_d_memc");
+    VciSignals<vci_param> signal_vci_tgt_d_brom("signal_vci_tgt_d_brom");
+//    VciSignals<vci_param> signal_vci_tgt_d_xicu("signal_vci_tgt_d_xicu");
+    VciSignals<vci_param> signal_vci_tgt_d_icu("signal_vci_tgt_d_icu");
+    VciSignals<vci_param> signal_vci_tgt_d_mtty("signal_vci_tgt_d_mtty");
+    VciSignals<vci_param_io> signal_vci_tgt_d_bdev("signal_vci_tgt_d_bdev");
+    VciSignals<vci_param_io> signal_vci_tgt_d_cmda("signal_vci_tgt_d_cmda");
+    VciSignals<vci_param_io> signal_vci_tgt_d_fbuf("signal_vci_tgt_d_fbuf");
+
+    // Coherence VCI signals
+
+    VciSignals<vci_param>* signal_vci_ini_c_proc = 
+        alloc_elems<VciSignals<vci_param> >("signal_vci_ini_c_proc", nprocs);
+
+    VciSignals<vci_param>* signal_vci_tgt_c_proc = 
+        alloc_elems<VciSignals<vci_param> >("signal_vci_tgt_c_proc", nprocs);
+
+    VciSignals<vci_param> signal_vci_ini_c_memc("signal_vci_ini_c_memc");
+    VciSignals<vci_param> signal_vci_tgt_c_memc("signal_vci_tgt_c_memc");
+
+    // Xternal network VCI signals
+
+    VciSignals<vci_param> signal_vci_tgt_x_xram("signal_vci_tgt_x_xram");
+    VciSignals<vci_param> signal_vci_ini_x_memc("signal_vci_ini_x_memc");
+
+    ////////////////////////////
+    //      Components
+    ////////////////////////////
+
+    typedef soclib::common::GdbServer<soclib::common::Mips32ElIss> proc_iss;
+
+    
+    soclib::common::Loader loader(soft_name);
+    proc_iss::set_loader(loader);
+    
+
+    // External RAM
+    VciSimpleRam<vci_param> xram(
+        "xram", 
+        IntTab(0), 
+        maptabx, 
+        loader);
+
+    // External network
+    VciVgmn<vci_param> xnoc(
+        "xnoc",
+        maptabx, 
+        1,  // initiators
+        1,  // targets
+        2,
+    2);
+
+    // Direct network
+    VciVgmn<vci_param> dnoc(
+        "dnoc",
+        maptabd, 
+        nprocs+2,   // nb of initiators
+        7,          // nb of targets
+        2, 2);      //latence, FIFO depth
+
+    // Coherence network
+    VciVgmn<vci_param> cnoc(
+        "cnoc",
+        maptabc, 
+        nprocs+1,
+        nprocs+1,
+        2, 2);
+
+    // Peripherals : TTY, Frame Buffer, Block Device, Boot ROM, & DMA 
+    VciSimpleRam<vci_param> brom(
+        "brom", 
+        IntTab(BROM_TGTID), 
+        maptabd, 
+        loader);
+    
+    VciMultiTty<vci_param> mtty(
+        "mtty",
+        IntTab(MTTY_TGTID),
+        maptabd,
+        "tty0","tty1","tty2","tty3",
+        "tty4","tty5","tty6","tty7",
+        "tty8", NULL);
+
+    VciFrameBuffer<vci_param_io> fbuf(
+        "fbuf", 
+        IntTab(FBUF_TGTID),
+        maptabd, 
+        FBUF_XSIZE,
+        FBUF_YSIZE);
+
+    VciBlockDeviceTsarV4<vci_param_io> bdev(
+//    VciBlockDevice<vci_param_io> bdev(
+        "bdev", 
+        maptabd, 
+        IntTab(BDEV_SRCID), // SRCID_D
+        IntTab(BDEV_TGTID), // TGTID_D
+        disk_name, 
+        SECTOR_SIZE,
+        32); // burst size 
+
+    VciDmaTsarV2<vci_param_io> cdma(
+        "cdma",
+        maptabd,
+        IntTab(CDMA_SRCID), // SRCID_D
+        IntTab(CDMA_TGTID), // TGTID_D
+        64); 
+
+    // processors (nprocs per cluster)
+
+    VciCcVCacheWrapperV4<vci_param, proc_iss> *proc[nprocs];
+
+    for ( size_t p = 0 ; p < nprocs ; p++ ) 
+    {
+      
+      std::ostringstream sp;
+      sp << "proc_" << "_" << p;
+                   
+      proc[p] = new VciCcVCacheWrapperV4<vci_param, proc_iss>(
+        sp.str().c_str(),
+        p, 
+        maptabd, maptabc,
+        IntTab(PROC_SRCID+p),       // SRCID_D
+        IntTab(PROC_SRCID+p),       // SRCID_C
+        IntTab(PROC_SRCID+p),       // TGTID_C
+        4,4,                // itlb ways, sets
+        4,4,                // dtlb ways, sets
+        4,64,16,4,64,16,    // Icache and Dcache sizes (way, set, words)
+        4,8,
+        20000000,
+        from_cycle,
+        false 
+        );
+    }
+
+    //  memory caches (one per cluster)
+    VciMemCacheV4<vci_param> memc(
+        sm.str().c_str(),
+        maptabd, maptabc, maptabx,
+        IntTab(0),              // SRCID_X
+        IntTab(nprocs),         // SRCID_C
+        IntTab(MEMC_TGTID),     // TGTID_D
+        IntTab(nprocs),         // TGTID_C
+        16,256,16,              // CACHE SIZE
+        4096,                   // HEAP SIZE
+        4,4,                    // TRANSACTION and UPDATE TAB lines
+        from_cycle,
+        debug_ok
+        );                 
+/*
+    // XICU (one per cluster)
+    VciXicu<vci_param> xicu(
+        "vci_xicu",
+        maptabd,
+        IntTab(XICU_TGTID),     // TGTID_D
+        nprocs,                 // number of TIMERS
+        NB_TTYS,                      // number of hard IRQs
+        nprocs+1,               // number of soft IRQs
+        nprocs);                // number of output IRQ lines
+*/
+    // ICU
+/*   
+    VciIcu<vci_param> icu(
+        "vci_icu",
+        IntTab(ICU_TGTID),     // TGTID_D
+        maptabd,
+        NB_TTYS + 2             // number of hard IRQs
+        );                
+*/
+    VciMultiIcu<vci_param> *icu;
+      icu = new VciMultiIcu<vci_param>("icu",
+              IntTab(ICU_TGTID),
+              maptabd,
+              32,           // number of irq in
+              1); //NB_PROCS number of irq out
+   
+ 
+    std::cout << "all components created" << std::endl;
+
+    ///////////////////////////////////////////////////////////////
+    //     Net-list 
+    ///////////////////////////////////////////////////////////////
+
+    // External Ram (one instance)
+    xram.p_clk                      (signal_clk);
+    xram.p_resetn                   (signal_resetn);
+    xram.p_vci                      (signal_vci_tgt_x_xram);    
+    
+    // External Network (one instance)
+    xnoc.p_clk                      (signal_clk);
+    xnoc.p_resetn                   (signal_resetn);
+    xnoc.p_to_target[0]             (signal_vci_tgt_x_xram);
+    xnoc.p_to_initiator[0]          (signal_vci_ini_x_memc);
+
+    // Direct Network (one instance)
+    dnoc.p_clk                      (signal_clk);
+    dnoc.p_resetn                   (signal_resetn);
+    dnoc.p_to_target[MEMC_TGTID]    (signal_vci_tgt_d_memc);
+    dnoc.p_to_target[BROM_TGTID]    (signal_vci_tgt_d_brom);
+//    dnoc.p_to_target[XICU_TGTID]    (signal_vci_tgt_d_xicu);
+    dnoc.p_to_target[ICU_TGTID]      (signal_vci_tgt_d_icu);
+    dnoc.p_to_target[MTTY_TGTID]     (signal_vci_tgt_d_mtty);
+    dnoc.p_to_target[BDEV_TGTID]     (signal_vci_tgt_d_bdev);
+    dnoc.p_to_target[CDMA_TGTID]     (signal_vci_tgt_d_cmda);
+    dnoc.p_to_target[FBUF_TGTID]     (signal_vci_tgt_d_fbuf);
+    
+    dnoc.p_to_initiator[BDEV_SRCID] (signal_vci_ini_d_bdev);
+    dnoc.p_to_initiator[CDMA_SRCID] (signal_vci_ini_d_cdma);
+    
+    // Coherence Network (one instance)
+    cnoc.p_clk                      (signal_clk);
+    cnoc.p_resetn                   (signal_resetn);
+    cnoc.p_to_initiator[nprocs]     (signal_vci_ini_c_memc);
+    cnoc.p_to_target[nprocs]        (signal_vci_tgt_c_memc);
+    
+    // Processors
+    for ( size_t p = 0 ; p < nprocs ; p++ )
+    {
+        dnoc.p_to_initiator[p]    (signal_vci_ini_d_proc[p]);
+        cnoc.p_to_initiator[p]    (signal_vci_ini_c_proc[p]);
+        cnoc.p_to_target[p]       (signal_vci_tgt_c_proc[p]);
+
+        proc[p]->p_clk            (signal_clk);  
+        proc[p]->p_resetn         (signal_resetn);  
+        proc[p]->p_vci_ini_d      (signal_vci_ini_d_proc[p]);
+        proc[p]->p_vci_ini_c      (signal_vci_ini_c_proc[p]);
+        proc[p]->p_vci_tgt_c      (signal_vci_tgt_c_proc[p]);
+        proc[p]->p_irq[0]         (signal_proc_it[p]);
+        for ( size_t j = 1 ; j < 6 ; j++ )
+        {
+            proc[p]->p_irq[j]      (signal_false); 
+        }
+    }
+
+    
+/*
+    // XICU
+    xicu.p_clk               (signal_clk);
+    xicu.p_resetn            (signal_resetn);
+    xicu.p_vci               (signal_vci_tgt_d_xicu);
+    for ( size_t p = 0 ; p < nprocs ; p++ )
+    {
+        xicu.p_irq[p]            (signal_proc_it[p]);
+    }
+
+    for(size_t i=0 ; i<NB_TTYS ; i++)
+    {
+        xicu.p_hwi[i]          (signal_irq_mtty[i]);
+    }
+*/
+    // ICU
+    icu->p_clk               (signal_clk);
+    icu->p_resetn            (signal_resetn);
+    icu->p_vci               (signal_vci_tgt_d_icu);
+    icu->p_irq_out[0]        (signal_proc_it[0]);
+
+    for (size_t i = 0 ; i < 32 ; i++ )
+    {   
+//       if      ( i < NB_TIMERS )      icu->p_irq_in[i] (signal_irq_tim[i]);
+        if ( i < 8 )              icu->p_irq_in[i] (signal_false);
+        else if ( i == 8)              icu->p_irq_in[i] (signal_irq_cdma);
+        else if ( i < 16 )             icu->p_irq_in[i] (signal_false);
+        else if ( i < (16 + NB_TTYS) ) icu->p_irq_in[i] (signal_irq_mtty[i-16]);
+        else if ( i < 31 )             icu->p_irq_in[i] (signal_false);
+        else                           icu->p_irq_in[i] (signal_irq_bdev);
+    }  
+ 
+    // MEMC
+    memc.p_clk               (signal_clk);
+    memc.p_resetn            (signal_resetn);
+    memc.p_vci_tgt           (signal_vci_tgt_d_memc);  
+    memc.p_vci_ini           (signal_vci_ini_c_memc);
+    memc.p_vci_tgt_cleanup   (signal_vci_tgt_c_memc);
+    memc.p_vci_ixr           (signal_vci_ini_x_memc);
+    
+    brom.p_clk                (signal_clk);
+    brom.p_resetn             (signal_resetn);
+    brom.p_vci                (signal_vci_tgt_d_brom);
+
+    mtty.p_clk                (signal_clk);
+    mtty.p_resetn             (signal_resetn);
+    mtty.p_vci                (signal_vci_tgt_d_mtty);
+
+    for(size_t i=0 ; i<NB_TTYS ; i++)
+    {
+        mtty.p_irq[i]           (signal_irq_mtty[i]);
+    }
+
+    bdev.p_clk                (signal_clk);
+    bdev.p_resetn             (signal_resetn);
+    bdev.p_irq                (signal_irq_bdev); 
+    bdev.p_vci_target         (signal_vci_tgt_d_bdev);
+    bdev.p_vci_initiator      (signal_vci_ini_d_bdev);
+
+    cdma.p_clk                (signal_clk);
+    cdma.p_resetn             (signal_resetn);
+    cdma.p_irq                (signal_irq_cdma); 
+    cdma.p_vci_target         (signal_vci_tgt_d_cmda);
+    cdma.p_vci_initiator      (signal_vci_ini_d_cdma);
+
+    fbuf.p_clk                (signal_clk); 
+    fbuf.p_resetn             (signal_resetn); 
+    fbuf.p_vci                (signal_vci_tgt_d_fbuf); 
+
+
+    std::cout << "all components connected" << std::endl;
+
+    ////////////////////////////////////////////////////////
+    //   Simulation
+    ///////////////////////////////////////////////////////
+    
+    sc_start(sc_core::sc_time(0, SC_NS));
+    signal_resetn = false;
+
+    sc_start(sc_core::sc_time(1, SC_NS));
+    signal_resetn = true;
+    char buf[1];
+
+    for(size_t i=1 ; i<ncycles ; i++)
+    {
+        sc_start(sc_core::sc_time(1, SC_NS));
+
+        if( debug_ok && (i > from_cycle) && (i < to_cycle) )
+        {
+        std::cout << std::dec << "*************** cycle " << i << "    ***********************" << std::endl; 
+        proc[0]->print_trace();
+        std::cout << std::endl;
+        
+        memc.print_trace();
+        std::cout << std::endl;
+
+        icu->print_trace();
+        std::cout << std::endl;
+        
+//        bdev.print_trace();
+//        std::cout << std::endl;
+        
+        xram.print_trace();
+        std::cout << std::endl;
+        } 
+    }
+
+    std::cout << "Hit ENTER to end simulation" << std::endl;
+    std::cin.getline(buf,1);
+
+//  for ( size_t p = 0 ; p < nprocs ; p++ ) 
+//        proc[p]->print_stats();
+
+    return EXIT_SUCCESS;
+}
+
+int sc_main (int argc, char *argv[])
+{
+    try {
+        return _main(argc, argv);
+    } catch (std::exception &e) {
+        std::cout << e.what() << std::endl;
+    } catch (...) {
+        std::cout << "Unknown exception occured" << std::endl;
+        throw;
+    }
+    return 1;
+}
Index: branches/v4/softs/giet_tsar/block_device.h
===================================================================
--- branches/v4/softs/giet_tsar/block_device.h	(revision 371)
+++ branches/v4/softs/giet_tsar/block_device.h	(revision 371)
@@ -0,0 +1,67 @@
+/*
+ * SOCLIB_LGPL_HEADER_BEGIN
+ *
+ * This file is part of SoCLib, GNU LGPLv2.1.
+ *
+ * SoCLib is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU Lesser General Public License as published
+ * by the Free Software Foundation; version 2.1 of the License.
+ *
+ * SoCLib is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with SoCLib; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301 USA
+ *
+ * SOCLIB_LGPL_HEADER_END
+ *
+ * Copyright (c) UPMC, Lip6, Asim
+ *         Nicolas Pouillon <nipo@ssji.net>, 2007
+ *
+ * Maintainers: nipo
+ */
+#ifndef BLOCK_DEVICE_REGS_H
+#define BLOCK_DEVICE_REGS_H
+
+enum SoclibBlockDeviceRegisters {
+    BLOCK_DEVICE_BUFFER,
+    BLOCK_DEVICE_LBA,
+    BLOCK_DEVICE_COUNT,
+    BLOCK_DEVICE_OP,
+    BLOCK_DEVICE_STATUS,
+    BLOCK_DEVICE_IRQ_ENABLE,
+    BLOCK_DEVICE_SIZE,
+    BLOCK_DEVICE_BLOCK_SIZE,
+};
+
+enum SoclibBlockDeviceOp {
+    BLOCK_DEVICE_NOOP,
+    BLOCK_DEVICE_READ,
+    BLOCK_DEVICE_WRITE,
+};
+
+enum SoclibBlockDeviceStatus {
+    BLOCK_DEVICE_IDLE,
+    BLOCK_DEVICE_BUSY,
+    BLOCK_DEVICE_READ_SUCCESS,
+    BLOCK_DEVICE_WRITE_SUCCESS,
+    BLOCK_DEVICE_READ_ERROR,
+    BLOCK_DEVICE_WRITE_ERROR,
+    BLOCK_DEVICE_ERROR,
+};
+
+#endif /* BLOCK_DEVICE_REGS_H */
+
+// Local Variables:
+// tab-width: 4
+// c-basic-offset: 4
+// c-file-offsets:((innamespace . 0)(inline-open . 0))
+// indent-tabs-mode: nil
+// End:
+
+// vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4
+
Index: branches/v4/softs/giet_tsar/dma.h
===================================================================
--- branches/v4/softs/giet_tsar/dma.h	(revision 371)
+++ branches/v4/softs/giet_tsar/dma.h	(revision 371)
@@ -0,0 +1,31 @@
+#ifndef DMA_REGS_H
+#define DMA_REGS_H
+
+enum SoCLibDmaRegisters {
+    DMA_SRC         = 0,
+    DMA_DST         = 1,
+    DMA_LEN         = 2,
+    DMA_RESET       = 3,
+    DMA_IRQ_DISABLE = 4,
+    /***/
+    DMA_SPAN        = 0x400,
+};
+
+enum DmaStatusValues {
+    DMA_SUCCESS     = 0,
+    DMA_READ_ERROR  = 1,
+    DMA_IDLE        = 2,
+    DMA_WRITE_ERROR = 3,
+};
+
+#endif
+
+// Local Variables:
+// tab-width: 4;
+// c-basic-offset: 4;
+// c-file-offsets:((innamespace . 0)(inline-open . 0));
+// indent-tabs-mode: nil;
+// End:
+//
+// vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4
+
Index: branches/v4/softs/giet_tsar/drivers.c
===================================================================
--- branches/v4/softs/giet_tsar/drivers.c	(revision 371)
+++ branches/v4/softs/giet_tsar/drivers.c	(revision 371)
@@ -0,0 +1,954 @@
+/****************************************************************************************
+File : drivers.c
+Written by Alain Greiner & Nicolas Pouillon
+Date : december 2010
+
+Basic drivers used by the GIET, that is running
+on the MIPS32 processor architecture.
+
+The supported peripherals are:
+- the SoClib pibus_multi_tty
+- the SocLib pibus_timer
+- the SocLib pibus_dma
+- The SoCLib pibus_icu
+- The SoCLib pibus_gcd
+- The SoCLib pibus_frame_buffer
+- The SoCLib pibus_block_device
+
+The following global parameters must be defined in the ldscript.
+- NB_CLUSTERS : number of clusters 
+- NB_PROCS : number of processor per cluster
+- NB_NTASKS : max number of tasks per processor
+- NB_LOCKS : max number of supported spin_locks
+- NB_TIMERS : max number of timers per processor
+
+The follobing base addresses must be defined in the ldscript
+- seg_icu_base
+- seg_timer_base
+- seg_tty_base
+- seg_gcd_base
+- seg_dma_base
+- seg_locks_base
+- seg_fb_base
+- seg_ioc_base
+****************************************************************************************/
+
+#include "drivers.h"
+#include "icu.h"
+#include "block_device.h"
+#include "dma.h"
+
+struct plouf;
+
+//////////////////////////////////////////////////////////////
+// various informations that must be defined in ldscript
+//////////////////////////////////////////////////////////////
+extern struct plouf seg_icu_base;
+extern struct plouf seg_timer_base;
+extern struct plouf seg_tty_base;
+extern struct plouf seg_gcd_base;
+extern struct plouf seg_dma_base;
+extern struct plouf seg_locks_base;
+extern struct plouf seg_fb_base;
+extern struct plouf seg_ioc_base;
+
+extern struct plouf NB_CLUSTERS;
+extern struct plouf NB_PROCS;
+extern struct plouf NB_TASKS;
+extern struct plouf NB_TIMERS;
+extern struct plouf NB_LOCKS;
+
+#define in_drivers __attribute__((section (".drivers")))
+#define in_unckdata __attribute__((section (".unckdata")))
+
+////////////////////////////////////////////////////////////////////////////////////////
+//  Global uncachable variables for synchronization between drivers and ISRs
+////////////////////////////////////////////////////////////////////////////////////////
+
+in_unckdata int volatile    _dma_status[256];
+in_unckdata int volatile    _dma_busy[256]   =   { 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
+                                                   0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
+                                                   0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
+                                                   0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
+                                                   0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
+                                                   0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
+                                                   0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
+                                                   0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
+                                                   0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
+                                                   0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
+                                                   0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
+                                                   0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
+                                                   0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
+                                                   0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
+                                                   0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
+                                                   0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 };
+
+in_unckdata int volatile    _ioc_lock    = 0;
+in_unckdata int volatile    _ioc_done    = 0;
+in_unckdata int volatile    _ioc_status;
+
+in_unckdata char volatile   _tty_get_buf[256];
+in_unckdata int volatile    _tty_get_full[256] = { 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
+                                                   0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
+                                                   0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
+                                                   0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
+                                                   0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
+                                                   0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
+                                                   0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
+                                                   0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
+                                                   0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
+                                                   0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
+                                                   0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
+                                                   0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
+                                                   0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
+                                                   0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
+                                                   0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
+                                                   0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 };
+
+in_unckdata char volatile   _tty_put_buf[256];
+in_unckdata int volatile    _tty_put_full[256] = { 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
+                                                   0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
+                                                   0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
+                                                   0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
+                                                   0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
+                                                   0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
+                                                   0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
+                                                   0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
+                                                   0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
+                                                   0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
+                                                   0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
+                                                   0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
+                                                   0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
+                                                   0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
+                                                   0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
+                                                   0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 };
+
+////////////////////////////////////////////////////////////////////////////////////////
+//  Global uncachable variables for inter-task barriers
+////////////////////////////////////////////////////////////////////////////////////////
+
+in_unckdata int volatile    _barrier_initial_value[16] = { 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 };
+in_unckdata int volatile    _barrier_count[16]         = { 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 };
+in_unckdata int volatile    _barrier_lock[16]          = { 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 };
+
+////////////////////////////////////////////////////////////////////////////////////////
+//  Global uncachable variables for spin_locks using LL/C instructions
+////////////////////////////////////////////////////////////////////////////////////////
+
+in_unckdata int volatile    _spin_lock[256] =    { 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
+                                                   0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
+                                                   0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
+                                                   0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
+                                                   0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
+                                                   0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
+                                                   0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
+                                                   0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
+                                                   0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
+                                                   0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
+                                                   0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
+                                                   0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
+                                                   0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
+                                                   0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
+                                                   0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
+                                                   0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 };
+
+////////////////////////////////////////////////////////////////////////////////////////
+//  mempcy()
+// GCC requires this function. Taken from MutekH.
+////////////////////////////////////////////////////////////////////////////////////////
+__attribute((used))
+in_drivers static void *memcpy(void *_dst, const void *_src, unsigned int size)
+{
+    unsigned int *dst = _dst;
+    const unsigned int *src = _src;
+    if ( ! ((unsigned int)dst & 3) && ! ((unsigned int)src & 3) )
+        while (size > 3) {
+            *dst++ = *src++;
+            size -= 4;
+        }
+
+    unsigned char *cdst = (unsigned char*)dst;
+    unsigned char *csrc = (unsigned char*)src;
+
+    while (size--) {
+        *cdst++ = *csrc++;
+    }
+    return _dst;
+}
+
+////////////////////////////////////////////////////////////////////////////////////////
+//  _procid()
+// Access CP0 and returns processor ident
+// No more than 1024 processors...
+////////////////////////////////////////////////////////////////////////////////////////
+in_drivers unsigned int _procid()
+{
+    unsigned int ret;
+    asm volatile( "mfc0 %0, $15, 1": "=r"(ret) );
+    return (ret & 0x3FF);
+}
+////////////////////////////////////////////////////////////////////////////////////////
+//  _segment_increment()
+// Access CP0 to get the procid, and returns the address increment to access 
+// various peripherals (TTY, TIMER, ICU, DMA), in case of multiprocessors architectures.
+// It uses the NB_PROCS and NB_CLUSTERS parameters to compute this increment:
+// - increment  = cluster_id*cluster_increment + local_id*local_increment
+// - cluster_id = procid / NB_PROCS  
+// - local_id   = procid % NB_PROCS 
+// - cluster_increment = 4G / NB_CLUSTERS
+////////////////////////////////////////////////////////////////////////////////////////
+in_drivers unsigned int _segment_increment(unsigned int local_increment)
+{
+    unsigned int	nprocs   		= (unsigned int)&NB_PROCS;
+    unsigned int	nclusters		= (unsigned int)&NB_CLUSTERS;
+    unsigned int	cluster_increment	= (0x80000000/nclusters)*2;
+    unsigned int	pid			= _procid();
+    return (pid / nprocs)*cluster_increment + (pid % nprocs)*local_increment;
+}
+////////////////////////////////////////////////////////////////////////////////////////
+//  _proctime()
+// Access CP0 and returns processor time
+////////////////////////////////////////////////////////////////////////////////////////
+in_drivers unsigned int _proctime()
+{
+    unsigned int ret;
+    asm volatile( "mfc0 %0, $9": "=r"(ret) );
+    return ret;
+}
+////////////////////////////////////////////////////////////////////////////////////////
+//  _procnumber()
+// Returns the number of processsors controled by the GIET
+////////////////////////////////////////////////////////////////////////////////////////
+in_drivers unsigned int _procnumber()
+{
+    return (unsigned int)&NB_PROCS * (unsigned int)&NB_CLUSTERS;
+}
+////////////////////////////////////////////////////////////////////////////////////////
+//  _it_mask()
+// Access CP0 and mask IRQs
+////////////////////////////////////////////////////////////////////////////////////////
+in_drivers void _it_mask()
+{
+    int tmp;
+    asm volatile("mfc0  %0, $12"    : "=r" (tmp) );
+    asm volatile("ori   %0, %0, 1"  : "=r" (tmp) );
+    asm volatile("mtc0  %0, $12"    : "=r" (tmp) );
+}
+////////////////////////////////////////////////////////////////////////////////////////
+//  _it_enable()
+// Access CP0 and enable IRQs
+////////////////////////////////////////////////////////////////////////////////////////
+in_drivers void _it_enable()
+{
+    int tmp;
+    asm volatile("mfc0  %0, $12"    : "=r" (tmp) );
+    asm volatile("addi  %0, %0, -1" : "=r" (tmp) );
+    asm volatile("mtc0  %0, $12"    : "=r" (tmp) );
+}
+//////////////////////////////////////////////////////////////////////
+//  _dcache_buf_invalidate()
+// Invalidate all cache lines corresponding to a memory buffer.
+// This is used by the block_device driver.
+/////////////////////////////////////////////////////////////////////////
+in_drivers void _dcache_buf_invalidate(const void * buffer, size_t size)
+{
+    size_t i;
+    size_t dcache_line_size;
+
+    // retrieve dcache line size from config register (bits 12:10)
+    asm volatile("mfc0 %0, $16, 1" : "=r" (dcache_line_size));
+
+    dcache_line_size = 2 << ((dcache_line_size>>10) & 0x7);
+
+    // iterate on lines to invalidate each one of them
+    for ( i=0; i<size; i+=dcache_line_size )
+        asm volatile(" cache %0, %1"
+                :
+                :"i" (0x11), "R" (*((char*)buffer+i)));
+}
+
+/////////////////////////////////////////////////////////////////////////
+//  _itoa_dec()
+// convert a 32 bits unsigned int to a string of 10 decimal characters.
+/////////////////////////////////////////////////////////////////////////
+in_drivers void _itoa_dec(unsigned val, char* buf)
+{
+    const char  DecTab[] = "0123456789";
+    unsigned int i;
+    for( i=0 ; i<10 ; i++ )
+    {
+        if( (val!=0) || (i==0) ) buf[9-i] = DecTab[val % 10];
+        else                     buf[9-i] = 0x20;
+        val /= 10;
+    }
+}
+//////////////////////////////////////////////////////////////////////////
+//  _itoa_hex()
+// convert a 32 bits unsigned int to a string of 8 hexadecimal characters.
+///////////////////////////////////////////////////////////////////////////
+in_drivers void _itoa_hex(int val, char* buf)
+{
+    const char  HexaTab[] = "0123456789ABCD";
+    unsigned int i;
+    for( i=0 ; i<8 ; i++ )
+    {
+        buf[7-i] = HexaTab[val % 16];
+        val /= 16;
+    }
+}
+///////////////////////////////////////////////////////////////////////////////////////
+// MULTI_TIMER component
+// Each processor can handle up to NB_TIMERS independant timers.
+// The segment base address is defined as
+//         seg_timer_base + segment_increment(NB_TIMERS*16) + index*16
+///////////////////////////////////////////////////////////////////////////////////////
+//  _timer_write()
+// Write a 32 bits word in a memory mapped register of the MULTI_TIMER
+///////////////////////////////////////////////////////////////////////////////////////
+in_drivers int _timer_write(size_t timer_index, size_t register_index, int value)
+{
+    int*    		timer_address;
+    size_t           	ntimers 	= (size_t)&NB_TIMERS;
+    unsigned int     	base      	= (unsigned int)&seg_timer_base;
+    unsigned int     	increment 	= _segment_increment(ntimers*TIMER_SPAN*4); 
+
+    if( timer_index >= ntimers) 	return -1;
+    if( register_index >= TIMER_SPAN ) 	return -1;
+
+    timer_address = (int*)(base + increment + timer_index*TIMER_SPAN*4);
+    timer_address[register_index] = value;          // write word
+    return 0;
+}
+///////////////////////////////////////////////////////////////////////////////////////
+//  _timer_read()
+// Read a 32 bits word in a memory mapped register of the MULTI_TIMER
+///////////////////////////////////////////////////////////////////////////////////////
+in_drivers int _timer_read(size_t timer_index, size_t register_index, int* buffer)
+{
+    int*    		timer_address;
+    size_t           	ntimers 	= (size_t)&NB_TIMERS;
+    unsigned int     	base      	= (unsigned int)&seg_timer_base;
+    unsigned int     	increment 	= _segment_increment(ntimers*TIMER_SPAN*4); 
+
+    if( timer_index >= ntimers) 	return -1;
+    if( register_index >= TIMER_SPAN ) 	return -1;
+
+    if( timer_index >= ntimers) return -1;
+    if( register_index >= TIMER_SPAN ) return -1;
+
+    timer_address = (int*)(base + increment + timer_index*TIMER_SPAN*4);
+    *buffer = timer_address[register_index];        // read word
+    return 0;
+}
+///////////////////////////////////////////////////////////////////////////////////////
+//  MULTI_TTY COMPONENT
+// The total number of TTYs is equal to NB_CLUSTERS * NB_PROCS * NB_TASKS.
+// - tty_address = seg_tty_base + _segment_increment(NB_TASKS*16) + task_id*16
+// - tty_index   = proc_id*NB_TASKS + task_id
+///////////////////////////////////////////////////////////////////////////////////////
+//  _tty_write()
+// Write one or several characters directly from a fixed length user buffer
+// to the TTY_WRITE register of the TTY controler.
+// It doesn't use the TTY_PUT_IRQ interrupt and the associated kernel buffer.
+// This is a non blocking call : it test the TTY_STATUS register.
+// If the TTY_STATUS_WRITE bit is set, the transfer stops and the function
+// returns  the number of characters that have been actually written.
+// It returns -1 in case of error (proc_id or task index too large)
+///////////////////////////////////////////////////////////////////////////////////////
+in_drivers int _tty_write(char* buffer, int length)
+{
+    char*   		tty_address;
+    size_t  		ntasks 		= (size_t)&NB_TASKS;
+    size_t  		nprocs 		= (size_t)&NB_PROCS;
+    size_t		    nclusters	= (size_t)&NB_CLUSTERS;
+    unsigned int    base		= (unsigned int)&seg_tty_base;
+    unsigned int	increment 	= _segment_increment(ntasks*TTY_SPAN*4);
+    size_t  		pid 		= _procid();
+    int     		nwritten 	= 0;
+    size_t		    tid;
+    int     		i;
+
+    if( ntasks == 0 )  tid = 0;
+    else               tid = _current_task_array[pid];
+
+    if( tid >= ntasks )   		        return -1;
+    if( pid >= nprocs*nclusters )   	return -1;
+
+    tty_address = (char*)(base + increment + tid*TTY_SPAN*4);
+    //tty_address = (char*)(base + tid*TTY_SPAN*4);
+
+    for ( i=0 ; i < length ; i++ )
+    {
+        if((tty_address[TTY_STATUS*4] & 0x2) == 0x2)  break;
+        else
+        {
+            tty_address[TTY_WRITE*4] = buffer[i]; // write character
+            nwritten++;
+        }
+    }
+    return nwritten;
+}
+///////////////////////////////////////////////////////////////////////////////////////
+//  _tty_read()
+// Fetch one character directly from the TTY_READ register of the TTY controler,
+// and writes this character to the user buffer.
+// It doesn't use the TTY_GET_IRQ interrupt and the associated kernel buffer.
+// This is a non blocking call : it returns 0 if the register is empty,
+// and returns 1 if the register is full.
+// It returns -1 in case of error (proc_id or task_id too large or length != 1)
+// The length argument is not used in this implementation, and has been
+// introduced for future implementations.
+///////////////////////////////////////////////////////////////////////////////////////
+in_drivers int _tty_read(char* buffer, int length)
+{
+    char*   		tty_address;
+    size_t  		ntasks 		= (size_t)&NB_TASKS;
+    size_t  		nprocs 		= (size_t)&NB_PROCS;
+    size_t  		nclusters	= (size_t)&NB_CLUSTERS;
+    unsigned int    base		= (unsigned int)&seg_tty_base;
+    unsigned int	increment 	= _segment_increment(ntasks*TTY_SPAN*4);
+    size_t  		pid 		= _procid();
+    size_t		    tid;
+
+    if( pid > 7 )   tid = 0;
+    else            tid	= _current_task_array[pid];
+
+    if( length != 1)      		    return -1;
+    if( pid >= nprocs*nclusters )   return -1;
+    if( tid >= ntasks )   		    return -1;
+    
+    tty_address = (char*)(base + increment + tid*TTY_SPAN*4);
+
+    if((tty_address[TTY_STATUS*4] & 0x1) == 0x1)
+    {
+        buffer[0] = tty_address[TTY_READ*4];
+        return 1;
+    }
+    else
+    {
+        return 0;
+    }
+}
+///////////////////////////////////////////////////////////////////////////////////////
+//  _tty_read_irq()
+// iAS it uses the TTY_GET_IRQ interrupt and the associated kernel buffer,
+// that has been written by the ISR, this function does not access the TTY registers.
+// It fetch one single character from the _tty_get_buf[tty_index] kernel buffer, writes 
+// this character to the user buffer, and reset the _tty_get_full[tty_index] buffer.
+// This is a non blocking call : it returns 0 if the kernel buffer is empty,
+// and returns 1 if the buffer is full.
+// It returns -1 in case of error (proc_id or task_id too large, or length != 1)
+// The length argument is not used in this implementation, and has been
+// introduced for future implementations.
+///////////////////////////////////////////////////////////////////////////////////////
+in_drivers int _tty_read_irq(char* buffer, int length)
+{
+    int     pid 	= _procid();
+    int     ntasks 	= (int)&NB_TASKS;
+    int     nprocs 	= (int)&NB_PROCS;
+    int     nclusters	= (int)&NB_CLUSTERS;
+    int     tty_index;
+    int     tid;
+
+    if( pid > 7 )   tid = 0;
+    else            tid	= _current_task_array[pid];
+ 
+    if( length != 1)      		return -1;
+    if( pid >= nprocs*nclusters )   	return -1;
+    if( tid >= ntasks )   		return -1;
+
+    tty_index = pid*ntasks + tid;
+    if( _tty_get_full[tty_index] == 0 ) return 0;
+
+    *buffer = _tty_get_buf[tty_index];
+    _tty_get_full[tty_index] = 0;
+    return 1;
+}
+///////////////////////////////////////////////////////////////////////////////////////
+//  _exit()
+// Exit (suicide) after printing message on  a TTY terminal.
+///////////////////////////////////////////////////////////////////////////////////////
+in_drivers int  _exit()
+{
+    char buf[] = "\n\n!!!  Exit  Processor          !!!\n";
+    int pid = _procid();
+
+    buf[24] = '0';
+    buf[25] = 'x';
+    buf[26] = (char)((pid>>8) & 0xF) + 0x30;
+    buf[27] = (char)((pid>>4) & 0xF) + 0x30;
+    buf[28] = (char)(pid & 0xF)      + 0x30;
+    _tty_write(buf, 36);
+
+    while(1) asm volatile("nop");   // infinite loop...
+}
+
+///////////////////////////////////////////////////////////////////////////////////////
+//  _icu_write()
+// Write a 32 bits word in a memory mapped register of the ICU peripheral
+// The base address is defined by the processor ID
+///////////////////////////////////////////////////////////////////////////////////////
+in_drivers int _icu_write(size_t register_index, int value)
+{
+    int*    		icu_address;
+    unsigned int	base = (int)&seg_icu_base;
+    unsigned int	increment = _segment_increment(ICU_SPAN*4);
+
+    if( register_index >= ICU_SPAN ) return -1;
+
+    icu_address = (int*)(base + increment);
+    icu_address[register_index] = value;   // write word
+    return 0;
+}
+///////////////////////////////////////////////////////////////////////////////////////
+//  _icu_read()
+// Read a 32 bits word in a memory mapped register of the ICU peripheral
+// The ICU base address is defined by the processor ID
+///////////////////////////////////////////////////////////////////////////////////////
+in_drivers int _icu_read(size_t register_index, int* buffer)
+{
+    int*    		icu_address;
+    unsigned int	base = (int)&seg_icu_base;
+    unsigned int	increment = _segment_increment(ICU_SPAN*4);
+
+    if( register_index >= ICU_SPAN ) return -1;
+
+    icu_address = (int*)(base + increment);
+    *buffer = icu_address[register_index]; 	// read word
+    return 0;
+}
+///////////////////////////////////////////////////////////////////////////////////////
+//  _gcd_write()
+// Write a 32 bits word in a memory mapped register of the GCD coprocessor
+///////////////////////////////////////////////////////////////////////////////////////
+in_drivers int _gcd_write(size_t register_index, int value)
+{
+    int*    gcd_address;
+    if( register_index >= 4 ) return -1;
+
+    gcd_address = (int*)&seg_gcd_base;
+    gcd_address[register_index] = value;            // write word
+    return 0;
+}
+///////////////////////////////////////////////////////////////////////////////////////
+//  _gcd_read()
+// Read a 32 bits word in a memory mapped register of the GCD coprocessor
+///////////////////////////////////////////////////////////////////////////////////////
+in_drivers int _gcd_read(size_t register_index, int* buffer)
+{
+    int*    gcd_address;
+    if( register_index >= 4 ) return -1;
+
+    gcd_address = (int*)&seg_gcd_base;
+    *buffer = gcd_address[register_index];          // read word
+    return 0;
+}
+///////////////////////////////////////////////////////////////////////////////////////
+//  _locks_write()
+// Release a software spin-lock 
+///////////////////////////////////////////////////////////////////////////////////////
+in_drivers int _locks_write(size_t index)
+
+{
+    int     max = (int)&NB_LOCKS;
+    if( index >= max ) return -1;
+
+    _spin_lock[index] = 0;
+    return 0;
+}
+///////////////////////////////////////////////////////////////////////////////////////
+//  _locks_read()
+// Try to take a software spin-lock.
+// This is a blocking call, as there is a busy-waiting loop,
+// until the lock is granted to the requester.
+// There is an internal delay of about 100 cycles between
+// two successive lock read, to avoid bus saturation.
+///////////////////////////////////////////////////////////////////////////////////////
+in_drivers int _locks_read(size_t index)
+{
+    int     max = (int)&NB_LOCKS;
+    if( index >= max ) return -1;
+
+    register int   delay = ((_proctime() +_procid()) & 0xF) << 4;
+    register int * plock = (int *) &_spin_lock[index];			
+
+    asm volatile ("_locks_llsc:		        \n"
+                  "ll   $2,    0(%0)		\n" 	// $2 <= _locks_lock
+                  "bnez $2,    _locks_delay	\n" 	// random delay if busy
+                  "li   $3,    1   		\n" 	// prepare argument for sc  
+                  "sc   $3,    0(%0)       	\n" 	// try to set _locks_busy
+                  "bnez $3,    _locks_ok     	\n" 	// exit if atomic 
+                  "_locks_delay:		\n"
+                  "move $4,    %1		\n"	// $4 <= delay
+                  "_locks_loop:			\n"
+                  "addi $4,    $4,    -1	\n"	// $4 <= $4 - 1
+                  "beqz $4,    _locks_loop	\n"	// test end delay
+                  "j           _locks_llsc    	\n"	// retry
+                  "_locks_ok:			\n"
+                  ::"r"(plock),"r"(delay):"$2","$3","$4");
+    return 0;
+}
+//////////////////////////////////////////////////////////////////////////////////////////
+//  I/O BLOCK_DEVICE
+// The three functions below use the three variables _ioc_lock _ioc_done, 
+// and _ioc_status for synchronisation.
+// - As the IOC component can be used by several programs running in parallel,
+// the _ioc_lock variable guaranties exclusive access to the device.
+// The _ioc_read() and _ioc_write() functions use atomic LL/SC to get the lock.
+// and set _ioc_lock to a non zero value. 
+// The _ioc_write() and _ioc_read() functions are blocking, polling the _ioc_lock
+// variable until the device is available.
+// - When the tranfer is completed, the ISR routine activated by the IOC IRQ
+// set the _ioc_done variable to a non-zero value. Possible address errors detected
+// by the IOC peripheral are reported by the ISR in the _ioc_status variable.
+// The _ioc_completed() function is polling the _ioc_done variable, waiting for
+// tranfer conpletion. When the completion is signaled, the _ioc_completed() function
+// reset the _ioc_done variable to zero, and releases the _ioc_lock variable.
+// 
+// In a multi-tasks environment, this polling policy must be replaced by a
+// descheduling policy for the requesting process. 
+///////////////////////////////////////////////////////////////////////////////////////
+//  _ioc_get_lock()
+// This blocking function is used by the _ioc_read() and _ioc_write() functions 
+// to get _ioc_lock using LL/SC.
+///////////////////////////////////////////////////////////////////////////////////////
+in_drivers void _ioc_get_lock()
+{
+    register unsigned int*	plock = (unsigned int*)&_ioc_lock;			
+
+    asm volatile ("_ioc_llsc:			    \n"
+                  "ll   $2,    0(%0)		    \n"	// $2 <= _ioc_lock
+                  "bnez $2,    _ioc_llsc	    \n" // retry  if busy
+                  "li   $3,    1   		    \n"	// prepare argument for sc  
+                  "sc   $3,    0(%0)       	    \n" // try to set _ioc_busy
+                  "beqz $3,    _ioc_llsc   	    \n" // retry if not atomic 
+                  ::"r"(plock):"$2","$3");
+}
+//////////////////////////////////////////////////////////////////////////////////////
+//  _ioc_write()
+// Transfer data from a memory buffer to a file on the block_device.
+// - lba    : first block index on the disk
+// - buffer : base address of the memory buffer
+// - count  : number of blocks to be transfered
+// The source buffer must be in user address space.
+///////////////////////////////////////////////////////////////////////////////////////
+in_drivers int _ioc_write(size_t lba, void* buffer, size_t count)
+{
+    volatile unsigned int*    	ioc_address = (unsigned int*)&seg_ioc_base;
+
+    // buffer must be in user space
+//  size_t block_size = ioc_address[BLOCK_DEVICE_BLOCK_SIZE];
+//  if( ( (size_t)buffer + block_size*count ) >= 0x80000000 ) return -1;
+//  if( ( (size_t)buffer                    ) >= 0x80000000 ) return -1;
+
+    // get the lock
+    _ioc_get_lock();
+
+    // block_device configuration
+    ioc_address[BLOCK_DEVICE_BUFFER] = (int)buffer;
+    ioc_address[BLOCK_DEVICE_COUNT] = count;
+    ioc_address[BLOCK_DEVICE_LBA] = lba;
+    ioc_address[BLOCK_DEVICE_IRQ_ENABLE] = 1;
+    ioc_address[BLOCK_DEVICE_OP] = BLOCK_DEVICE_WRITE;
+    return 0;
+}
+///////////////////////////////////////////////////////////////////////////////////////
+//  _ioc_read()
+// Transfer data from a file on the block device to a memory buffer.
+// - lba    : first block index on the disk
+// - buffer : base address of the memory buffer
+// - count  : number of blocks to be transfered
+// The destination buffer must be in user address space.
+// All cache lines corresponding to the the target buffer must be invalidated
+// for cache coherence.
+///////////////////////////////////////////////////////////////////////////////////////
+in_drivers int _ioc_read(size_t lba, void* buffer, size_t count)
+{
+    volatile unsigned int*    	ioc_address = (unsigned int*)&seg_ioc_base;
+
+    // buffer must be in user space
+//  size_t block_size = ioc_address[BLOCK_DEVICE_BLOCK_SIZE];
+//  if( ( (size_t)buffer + block_size*count ) >= 0x80000000 ) return -1;
+//  if( ( (size_t)buffer                    ) >= 0x80000000 ) return -1;
+
+    // get the lock
+    _ioc_get_lock();
+
+    // block_device configuration
+    ioc_address[BLOCK_DEVICE_BUFFER] = (int)buffer;
+    ioc_address[BLOCK_DEVICE_COUNT] = count;
+    ioc_address[BLOCK_DEVICE_LBA] = lba;
+    ioc_address[BLOCK_DEVICE_IRQ_ENABLE] = 1;
+    ioc_address[BLOCK_DEVICE_OP] = BLOCK_DEVICE_READ;
+
+    return 0;
+}
+///////////////////////////////////////////////////////////////////////////////////////
+//  _ioc_completed()
+// This blocking function cheks completion of an I/O transfer and reports errors.
+// It returns 0 if the transfer is successfully completed.
+// It returns -1 if an error has been reported.
+///////////////////////////////////////////////////////////////////////////////////////
+in_drivers int _ioc_completed()
+{
+    // waiting for completion
+    while (_ioc_done == 0) { asm volatile("nop"); }
+    
+    // reset synchronisation variables
+    _ioc_done = 0;
+    _ioc_lock = 0;
+
+    // return errors
+    if((_ioc_status != BLOCK_DEVICE_READ_SUCCESS) &&
+            (_ioc_status != BLOCK_DEVICE_WRITE_SUCCESS))    return -1;
+    else                        				            return 0;
+}
+
+//////////////////////////////////////////////////////////////////////////////////////
+//  FRAME_BUFFER
+// The _fb_sync_write & _fb_sync_read functions use a memcpy strategy to implement 
+// the transfer between a data buffer (user space) and the frame buffer (kernel space).
+// They are blocking until completion of the transfer.
+//////////////////////////////////////////////////////////////////////////////////////
+//  _fb_sync_write()
+// Transfer data from an user buffer to the frame_buffer device with a memcpy.
+// - offset     : offset (in bytes) in the frame buffer
+// - buffer : base address of the memory buffer
+// - length : number of bytes to be transfered
+//////////////////////////////////////////////////////////////////////////////////////
+in_drivers int  _fb_sync_write(size_t offset, void* buffer, size_t length)
+{
+    volatile char*  fb = (char*)(void*)&seg_fb_base + offset;
+    char*       ub = buffer;
+    size_t      i;
+
+    // buffer must be in user space
+//  if( ( (size_t)buffer + length ) >= 0x80000000 ) return -1;
+//  if( ( (size_t)buffer          ) >= 0x80000000 ) return -1;
+
+    // memory copy
+    for(i=0 ; i<length ; i++) fb[i] = ub[i];
+    return 0;
+}
+///////////////////////////////////////////////////////////////////////////////////////
+//  _fb_sync_read()
+// Transfer data from the frame_buffer device to an user buffer with a memcpy.
+// - offset     : offset (in bytes) in the frame buffer
+// - buffer : base address of the memory buffer
+// - length : number of bytes to be transfered
+//////////////////////////////////////////////////////////////////////////////////////
+in_drivers int  _fb_sync_read(size_t offset, void* buffer, size_t length)
+{
+    volatile char*  fb = (char*)(void*)&seg_fb_base + offset;
+    char*       ub = buffer;
+    size_t      i;
+
+    // buffer must be in user space
+//  if( ( (size_t)buffer + length ) >= 0x80000000 ) return -1;
+//  if( ( (size_t)buffer          ) >= 0x80000000 ) return -1;
+
+    // memory copy
+    for(i=0 ; i<length ; i++) ub[i] = fb[i];
+    return 0;
+}
+//////////////////////////////////////////////////////////////////////////////////////
+// The _fb_write() and _fb_read() functions use the MULTI_DMA
+// coprocessor to transfer data between the user buffer and the frame buffer.
+// The _fb_completed() function, use a polling policy to test
+// the global variables _dma_busy[i] and detect the transfer completion.
+// As each processor can have it's private DMA, there is up to 256 _dma_busy[i]
+// set/reset variables that are indexed by the proc_id.
+// The _dma_busy variable is reset by the ISR associated to the DMA IRQ.
+///////////////////////////////////////////////////////////////////////////////////////
+//  _fb_write()
+// Transfer data from an user buffer to the frame_buffer device using DMA.
+// - offset : offset (in bytes) in the frame buffer
+// - buffer : base address of the memory buffer
+// - length : number of bytes to be transfered
+//////////////////////////////////////////////////////////////////////////////////////
+in_drivers int  _fb_write(size_t offset, void* buffer, size_t length)
+{
+    int*   		dma_address;
+    unsigned int    	base   		= (unsigned int) &seg_dma_base;
+    unsigned int    	increment	= _segment_increment(DMA_SPAN*4);
+    char *  	fb		= (char *) &seg_fb_base + offset;
+    unsigned int    	delay = (_proctime() & 0xF) << 4;
+    unsigned int	pid		= _procid();
+    unsigned int    	i;
+
+
+    // checking buffer boundaries (bytes)
+//  if( ( (size_t)buffer + length ) >= 0x80000000 ) return -1;
+//  if( ( (size_t)buffer          ) >= 0x80000000 ) return -1;
+
+    // waiting until DMA device is available
+    while (_dma_busy[pid] != 0)
+    {
+        for( i=0 ; i<delay ; i++)   // busy waiting
+        {                           // with a pseudo random
+            asm volatile("nop");    // delay between bus accesses
+        }
+    }
+    _dma_busy[pid] = 1;
+
+    dma_address = (int*)(base + increment);
+ 
+    // DMA configuration
+    dma_address[DMA_IRQ_DISABLE] = 0;
+    dma_address[DMA_SRC] 	= (int)buffer;
+    dma_address[DMA_DST] 	= (int)fb;
+    dma_address[DMA_LEN] 	= (int)length;
+    return 0;
+}
+///////////////////////////////////////////////////////////////////////////////////////
+//  _fb_read()
+// Transfer data from the frame_buffer device to an user buffer using DMA.
+// - offset     : offset (in bytes) in the frame buffer
+// - buffer : base address of the memory buffer
+// - length : number of bytes to be transfered
+//////////////////////////////////////////////////////////////////////////////////////
+in_drivers int  _fb_read(size_t offset, void* buffer, size_t length)
+{
+    int*		dma_address;
+    unsigned int    	base		= (unsigned int)&seg_dma_base; 
+    unsigned int    	increment	= _segment_increment(DMA_SPAN*4);
+    char*  		fb    		= (char*)&seg_fb_base + offset;
+    unsigned int    	delay 		= (_proctime() & 0xF) << 4;
+    unsigned int	pid		= _procid();
+    unsigned int    	i;
+
+    // checking buffer boundaries (bytes)
+//  if( ( (size_t)buffer + length ) >= 0x80000000 ) return -1;
+//  if( ( (size_t)buffer          ) >= 0x80000000 ) return -1;
+
+    // waiting until DMA device is available
+    while (_dma_busy[pid] != 0)
+    {
+        for( i=0 ; i<delay ; i++)   // busy waiting
+        {                           // with a pseudo random
+            asm volatile("nop");    // delay between bus accesses
+        }
+    }
+    _dma_busy[pid] = 1;
+
+    dma_address = (int*)(base + increment);
+
+    // DMA configuration
+    dma_address[DMA_IRQ_DISABLE] = 0;
+    dma_address[DMA_SRC] 	= (int)fb;
+    dma_address[DMA_DST] 	= (int)buffer;
+    dma_address[DMA_LEN] 	= (int)length;
+    return 0;
+}
+///////////////////////////////////////////////////////////////////////////////////////
+//  _fb_completed()
+// This blocking function cheks completion of a DMA transfer to or fom the frame buffer.
+// The MIPS32 wait instruction stall the processor until the next interrupt.
+// It returns 0 if the transfer is successfully completed
+// It returns -1 if an error has been reported.
+///////////////////////////////////////////////////////////////////////////////////////
+in_drivers int _fb_completed()
+{
+    unsigned int	pid = _procid();
+
+    while (_dma_busy[pid] != 0)
+    {
+        asm volatile("nop");
+    }
+    if(_dma_status[pid] == DMA_SUCCESS)  return 0;
+    else                                 return _dma_status[pid];
+}
+//////////////////////////////////////////////////////////////////////////////////////
+// _barrier_init()
+// This function makes a cooperative initialisation of the barrier:
+// - barrier_count[index] <= N
+// - barrier_lock[index]  <= 0
+// All tasks try to initialize the barrier, but the initialisation 
+// is done by only one task, using LL/SC instructions.
+// This cooperative initialisation is questionnable, 
+// bcause the barrier can ony be initialised once...
+//////////////////////////////////////////////////////////////////////////////////////
+in_drivers int _barrier_init(unsigned int index, unsigned int value)
+{
+
+    register int* pinit 	= (int*)&_barrier_initial_value[index];
+    register int* pcount 	= (int*)&_barrier_count[index];
+    register int* plock  	= (int*)&_barrier_lock[index];
+
+    if ( index > 7 )	return 1;
+
+    // parallel initialisation using atomic instructions LL/SC
+    asm volatile ("_barrier_init_test:          	\n"
+                  "ll   $2,     0(%0)           	\n"	// read barrier_inital_value 
+                  "bnez $2,     _barrier_init_done	\n"
+                  "move $3,     %3			        \n"
+                  "sc   $3,     0(%0)    	      	\n"	// try to write barrier_initial_value
+                  "beqz $3,     _barrier_init_test	\n"
+                  "move $3,	%3			            \n" 
+                  "sw   $3,	0(%1)			        \n"	// barrier_count <= barrier_initial_value
+                  "move $3, $0                      \n" // 
+                  "sw   $3,	0(%2)			        \n"	// barrier_lock <= 0
+                  "_barrier_init_done:			\n"
+                  ::"r"(pinit),"r"(pcount),"r"(plock),"r"(value):"$2","$3");
+    return 0 ;
+}
+//////////////////////////////////////////////////////////////////////////////////////
+// 	_barrier_wait()
+// This blocking function uses a busy_wait technics (on the barrier_lock value), 
+// because the GIET does not support dynamic scheduling/descheduling of tasks. 
+// The barrier state is actually defined by two variables:
+// _barrier_count[index] define the number of particpants that are waiting
+// _barrier_lock[index] define the bool variable whose value is polled 
+// The last participant change the value of _barrier_lock[index] to release the barrier...
+// There is at most 16 independant barriers, and an error is returned
+// if the barrier index is larger than 15.
+//////////////////////////////////////////////////////////////////////////////////////
+in_drivers int _barrier_wait(unsigned int index)
+{
+    register int* 	pcount 		= (int*)&_barrier_count[index];		
+    register int  	count;
+
+    int 	       lock 		= _barrier_lock[index];		
+
+    if ( index > 15 )	return 1;
+    
+    // parallel decrement _barrier_count[index] using atomic instructions LL/SC
+    // input : pointer on _barrier_count[index]
+    // output : count = _barrier_count[index] (before decrementation)
+    asm volatile ("_barrier_decrement:          		\n"
+                  "ll   %0,     0(%1)           		\n"
+                  "addi $3,     %0,     -1      		\n"
+                  "sc   $3,     0(%1)           		\n"
+                  "beqz $3,     _barrier_decrement		\n"
+                  :"=&r"(count)
+                  :"r"(pcount)
+                  :"$2","$3");
+
+    // the last task re-initializes the barrier_ count variable
+    // and the barrier_lock variable, waking up all other waiting tasks
+
+    if ( count == 1 ) 	 // last task
+    {
+        _barrier_count[index] = _barrier_initial_value[index];
+        asm volatile( "sync" );
+        _barrier_lock[index]   = (lock == 0) ? 1 : 0;
+        return 0 ;
+    }
+    else 		// other tasks
+    {
+        while ( lock == _barrier_lock[index] ) 	{ }	// busy waiting 
+        return 0 ;
+    }
+} 
+//////////////////////////////////////////////////////////////////////////////////////
+
+
+// Local Variables:
+// tab-width: 4;
+// c-basic-offset: 4;
+// c-file-offsets:((innamespace . 0)(inline-open . 0));
+// indent-tabs-mode: nil;
+// End:
+//
+// vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4
+
Index: branches/v4/softs/giet_tsar/drivers.h
===================================================================
--- branches/v4/softs/giet_tsar/drivers.h	(revision 371)
+++ branches/v4/softs/giet_tsar/drivers.h	(revision 371)
@@ -0,0 +1,108 @@
+/****************************************************************************************
+    File : drivers.h
+    Written by Alain Greiner & Nicolas Pouillon
+    Date : september 2009
+
+    These system calls are used by the MIPS GIET, that is running
+    on the MIPS32 processor architecture.
+
+    The supported peripherals are:
+    - the SoClib vci_multi_tty
+    - the SocLib vci_multi_timer
+    - the SocLib vci_dma
+    - The SoCLib vci_icu
+    - The SoCLib vci_gcd
+    - The SoCLib vci_frame_buffer
+    - The SoCLib vci_block_device
+****************************************************************************************/
+
+#ifndef _DRIVERS_H_
+#define _DRIVERS_H_
+
+#include "tty.h"
+#include "dma.h"
+#include "gcd.h"
+#include "timer.h"
+#include "icu.h"
+#include "block_device.h"
+
+typedef unsigned int    size_t;
+
+// global variables defined in giet.s
+
+extern  unsigned int    _task_context_array[];
+extern  unsigned int    _current_task_array[];
+extern  unsigned int    _task_number_array[];
+
+// function defined in giet.s
+
+void _ctx_switch();
+
+// global variables defined in drivers.c
+
+extern  int volatile	_dma_status[];
+extern  int volatile	_dma_busy[];
+
+extern  int volatile	_ioc_lock;
+extern  int volatile	_ioc_done;
+extern  int volatile	_ioc_status;
+
+extern  char volatile	_tty_get_buf[];
+extern  int volatile	_tty_get_full[];
+
+extern  char volatile	_tty_put_buf[];
+extern  int volatile	_tty_put_full[];
+
+// functions defined in drivers.c
+
+unsigned int 	_procid();
+unsigned int 	_proctime();
+unsigned int 	_procnumber();
+
+unsigned int 	_segment_increment();
+
+void _itoa_dec(unsigned int val, char* buf);
+void _itoa_hex(int val, char* buf);
+
+int _exit();
+
+int _timer_write(size_t timer_index, size_t register_index, int value);
+int _timer_read(size_t timer_index, size_t register_index, int* buffer);
+
+int _tty_write(char* buffer, int length);
+int _tty_read(char* buffer, int length);
+
+int _io_write(size_t lba, void* buffer, size_t count);
+int _io_read(size_t lba, void* buffer, size_t count);
+int _io_completed();
+
+int _icu_write(size_t register_index, int  value);
+int _icu_read(size_t register_index, int*  buffer);
+
+int _gcd_write(size_t register_index, int  value);
+int _gcd_read(size_t register_index, int*  buffer);
+
+int _locks_write(size_t lock_index);
+int _locks_read(size_t lock_index);
+
+int _fb_sync_write(size_t offset, void* buffer, size_t length);
+int _fb_sync_read(size_t offset, void* buffer, size_t length);
+
+int _fb_write(size_t offset, void* buffer, size_t length);
+int _fb_read(size_t offset, void* buffer, size_t length);
+int _fb_completed();
+
+int _barrier_init(size_t index, size_t count);
+int _barrier_wait(size_t index);
+
+#endif
+
+// Local Variables:
+// tab-width: 4;
+// c-basic-offset: 4;
+// c-file-offsets:((innamespace . 0)(inline-open . 0));
+// indent-tabs-mode: nil;
+// End:
+//
+// vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4
+
Index: branches/v4/softs/giet_tsar/gcd.h
===================================================================
--- branches/v4/softs/giet_tsar/gcd.h	(revision 371)
+++ branches/v4/softs/giet_tsar/gcd.h	(revision 371)
@@ -0,0 +1,23 @@
+#ifndef GCD_REGS_H
+#define GCD_REGS_H
+
+enum SoclibLcdRegisters {
+    GCD_OPA = 0,
+    GCD_OPB = 1,
+    GCD_START  = 2,
+    GCD_STATUS = 3,
+    /**/
+    GCD_SPAN  = 4,
+};
+
+#endif
+
+// Local Variables:
+// tab-width: 4;
+// c-basic-offset: 4;
+// c-file-offsets:((innamespace . 0)(inline-open . 0));
+// indent-tabs-mode: nil;
+// End:
+//
+// vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4
+
Index: branches/v4/softs/giet_tsar/giet.s
===================================================================
--- branches/v4/softs/giet_tsar/giet.s	(revision 371)
+++ branches/v4/softs/giet_tsar/giet.s	(revision 371)
@@ -0,0 +1,726 @@
+/*********************************************************************************
+*    File : giet.s
+*    Author : Franck Wajsburt & Alain Greiner & Joel Porquet
+*    Date : 2009 - 2010
+**********************************************************************************
+*    Interruption/Exception/Trap Handler for MIPS32 processor
+*    The base address of the segment containing this code
+*    MUST be 0x80000000, in order to have the entry point
+*    at address 0x80000180 !!!
+*    All messages are printed on the TTY defined by the processor ID.
+**********************************************************************************
+*    History :
+*    15/09/2009 : The GIET entry point has been modified to comply with
+*        the MIPS32 specification : 0x80000180
+*    5/10/2009  : The syscall handler has been modified to comply with the
+*        MIPS32 specification : the value stored in EPC register is the
+*        syscall instruction address => it must be incremented by 4
+*        to obtain the return address.
+*    15/10/2009 : The Interrupt handler has been modified to comply with the
+*        VCI_ICU specification : The IRQ index is obtained by a read
+*        to (icu_base_address + 16).
+*    26/10/2009 : The interrupt handler has been modified to support
+*        multi-processors architectures with one ICU per processor.
+*        Finally, the mfc0 instruction uses now the select parameter
+*        to comply with the MIPS32 specification when accessing the
+*        processor_id (mtfc0 $x, $15, 1)
+*    08/11/2009 : The syscall handler has been extended to support 32 values
+*        for the syscall index, and to enable interrupts when processing
+*        a system call.
+*        Five new syscalls have been introduced to access the frame buffer
+*        Three new syscalls have been introduced to access the block device
+*        The two syscalls associated to the DMA have been removed.
+*    18/11/2009 : The syscall handler has been modified to save the SR in
+*        the stack before enabling interrupts.
+*    15/03/2010 : replace the itoa_print assembler function by the itoa_hex()
+*        function defined in the syscalls.c file.
+*    10/04/2010 : modify the interrupt handler to use the new ICU component
+*        supporting up to 8 output IRQs for 8 processors.
+*        The active IRQ index is obtained as ICU[32*PROC_ID+16].
+*    12/09/2010 : The ctx_switch functionhas been included in this file to
+*        simplify the compilation process.
+*   25/09/2010 : add '.end' directive to end the _giet function
+*        and modify the 'sharp' comment character into the regular "slash
+*        asterix ... asterix slash" comment syntax
+*   27/09/2010 : respect stack convention with 4 minimum slots before calling
+*        C functions
+*   28/09/2010 : Save all the non-persistant registers in the int_handler
+*   02/02/2011 : Introduce the "segment_increment" parameter in the interrupt
+*        handler to support clusterised multi-processing.
+*        Introducing the barrier_init() & barrier_wait() system calls.
+*   04/04/2011 : introducing the system call proc_num() 
+*   12/04/2011 : modifying the _int_handler to support the XICU component in
+*        multi_clusters/multi-processors architectures:
+*        the XICU base address depends the cluster_id and the PRIO register
+*        address depends on the local_id.
+**********************************************************************************/
+
+    .section .giet,"ax",@progbits
+    .align 2
+    .global _interrupt_vector    # makes interrupt_vector an external symbol 
+
+    .extern seg_icu_base
+    .extern seg_tty_base
+    .extern NB_CLUSTERS
+    .extern NB_PROCS
+
+    .extern isr_default
+
+    .extern _procid
+    .extern _proctime
+    .extern _tty_write
+    .extern _tty_read
+    .extern _tty_read_irq
+    .extern _timer_write
+    .extern _timer_read
+    .extern _icu_write
+    .extern _icu_read
+    .extern _gcd_write
+    .extern _gcd_read
+    .extern _locks_read
+    .extern _locks_write
+    .extern _exit
+    .extern _fb_sync_write
+    .extern _fb_sync_read
+    .extern _fb_write
+    .extern _fb_read
+    .extern _fb_completed
+    .extern _ioc_write
+    .extern _ioc_read
+    .extern _ioc_completed
+    .extern _itoa_hex
+    .extern _barrier_init
+    .extern _barrier_wait
+
+    .ent _giet
+
+/***************************************************************
+*    Cause Table (indexed by the Cause register)
+***************************************************************/
+tab_causes:
+    .word _int_handler  # 0000 : external interrupt 
+    .word _cause_ukn    # 0001 : undefined exception 
+    .word _cause_ukn    # 0010 : undefined exception 
+    .word _cause_ukn    # 0011 : undefined exception 
+    .word _cause_adel   # 0100 : illegal address read exception 
+    .word _cause_ades   # 0101 : illegal address write exception 
+    .word _cause_ibe    # 0110 : instruction bus error exception 
+    .word _cause_dbe    # 0111 : data bus error exception 
+    .word _sys_handler  # 1000 : system call 
+    .word _cause_bp     # 1001 : breakpoint exception 
+    .word _cause_ri     # 1010 : illegal codop exception 
+    .word _cause_cpu    # 1011 : illegal coprocessor access 
+    .word _cause_ovf    # 1100 : arithmetic overflow exception 
+    .word _cause_ukn    # 1101 : undefined exception 
+    .word _cause_ukn    # 1110 : undefined exception 
+    .word _cause_ukn    # 1111 : undefined exception 
+
+    .space 320
+
+/***************************************************************
+*    Entry point (at address 0x80000180)
+***************************************************************/
+_giet:
+    mfc0    $27,    $13             # Cause Register analysis 
+    lui     $26,    0x8000          # $26 <= tab_causes 
+    andi    $27,    $27,    0x3c
+    addu    $26,    $26,    $27
+    lw      $26,    ($26)
+    jr      $26                     # Jump indexed by CR 
+    .end _giet
+
+/****************************************************************
+*   System Call Handler
+* A system call is handled as a special function call.
+*   - $2 contains the system call index (< 16).
+*   - $3 is used to store the syscall address
+*   - $4, $5, $6, $7 contain the arguments values.
+*   - The return address (EPC) iand the SR are saved in the stack.
+*   - Interrupts are enabled before branching to the syscall.
+*   - All syscalls must return to the syscall handler.
+*   - $2, $3, $4, $5, $6, $7 as well as $26 & $27 can be modified.
+*
+* In case of undefined system call, an error message displays
+* the value of EPC on the TTY corresponding to the processor,
+* and the user program is killed.
+****************************************************************/
+_sys_handler:
+    addiu   $29,    $29,    -24     # 2 slots for SR&EPC, 4 slots for args passing 
+    mfc0    $26,    $12             # load SR 
+    sw      $26,    16($29)         # save it in the stack 
+    mfc0    $27,    $14             # load EPC 
+    addiu   $27,    $27,    4       # increment EPC for return address 
+    sw      $27,    20($29)         # save it in the stack 
+
+    andi    $26,    $2,     0x1F    # $26 <= syscall index (i < 32) 
+    sll     $26,    $26,    2       # $26 <= index * 4 
+    la      $27,    tab_syscalls    # $27 <= &tab_syscalls[0] 
+    addu    $27,    $27,    $26     # $27 <= &tab_syscalls[i] 
+    lw      $3,     0($27)          # $3  <= syscall address 
+
+    li      $27,    0xFFFFFFED      # Mask for UM & EXL bits 
+    mfc0    $26,    $12             # $26 <= SR 
+    and     $26,    $26,    $27     # UM = 0 / EXL = 0 
+    mtc0    $26,    $12             # interrupt enabled 
+    jalr    $3                      # jump to the proper syscall 
+    mtc0    $0,     $12             # interrupt disbled 
+
+    lw      $26,    16($29)         # load SR from stack 
+    mtc0    $26,    $12             # restore SR 
+    lw      $26,    20($29)         # load EPC from stack 
+    mtc0    $26,    $14             # restore EPC 
+    addiu   $29,    $29,     24     # restore stack pointer 
+    eret                            # exit GIET 
+
+_sys_ukn:                           # undefined system call 
+    la      $4,     msg_uknsyscall  # $4 <= message address 
+    li      $5,    36               # $5 <= message length 
+    jal     _tty_write              # print unknown message 
+
+    la      $4,     msg_epc         # $4 <= message address 
+    li      $5,    8                # $5 <= message length 
+    jal     _tty_write              # print EPC message 
+
+    mfc0    $4,     $14             # $4 <= EPC 
+    la      $5,     itoa_buffer     # $5 <= buffer address 
+    addiu   $5,     $5,     2       # skip the 0x prefix 
+    jal     _itoa_hex               # fill the buffer 
+
+    la      $4,     itoa_buffer     # $4 <= buffer address 
+    li      $5,     10              # $5 <= buffer length 
+    jal     _tty_write              # print EPC value 
+
+    j       _exit                   # end of program 
+
+itoa_buffer: .ascii "0x00000000"
+
+    .align 2
+
+/****************************************************************
+* System Call Table (indexed by syscall index) 
+****************************************************************/
+tab_syscalls:
+    .word _procid           # 0x00 
+    .word _proctime         # 0x01 
+    .word _tty_write        # 0x02 
+    .word _tty_read         # 0x03 
+    .word _timer_write      # 0x04 
+    .word _timer_read       # 0x05 
+    .word _gcd_write        # 0x06 
+    .word _gcd_read         # 0x07 
+    .word _icu_write        # 0x08 
+    .word _icu_read         # 0x09 
+    .word _tty_read_irq     # 0x0A 
+    .word _sys_ukn          # 0x0B 
+    .word _locks_write      # 0x0C 
+    .word _locks_read       # 0x0D 
+    .word _exit             # 0x0E 
+    .word _procnumber       # 0x0F 
+    .word _fb_sync_write    # 0x10 
+    .word _fb_sync_read     # 0x11 
+    .word _fb_write         # 0x12 
+    .word _fb_read          # 0x13 
+    .word _fb_completed     # 0x14 
+    .word _ioc_write        # 0x15 
+    .word _ioc_read         # 0x16 
+    .word _ioc_completed    # 0x17 
+    .word _barrier_init     # 0x18 
+    .word _barrier_wait     # 0x19 
+    .word _sys_ukn          # 0x1A 
+    .word _sys_ukn          # 0x1B 
+    .word _sys_ukn          # 0x1C 
+    .word _sys_ukn          # 0x1D 
+    .word _sys_ukn          # 0x1E 
+    .word _sys_ukn          # 0x1F 
+
+/******************************************************************
+*    Interrupt Handler
+* This simple interrupt handler cannot be interrupted.
+* It uses an external ICU component (Interrupt Controler Unit)
+* that concentrates up to 32 interrupts lines to a single IRQ
+* line that can be connected to any of the 6 MIPS IT inputs.
+* This component returns the highest priority active interrupt index
+* (smaller indexes have the highest priority).
+*
+* In case of a multi-clusters architecture, it exist one ICU 
+* per cluster. The base address of the ICU segment depends on both
+* the cluster_id and the proc_id:
+* - icu_base_address = seg_icu_base + (32 * local_id) +
+*                    (cluster_increment * cluster _id)
+* - cluster_id = proc_id / NB_PROCS 
+* - local_id = proc_id % NB_PROCS
+* - cluster_increment = 4G / NB_CLUSTERS
+*
+* The interrupt handler reads the XICU PRIO register,
+* using the offset 16.
+* This component returns the highest priority interrupt index
+* (smaller indexes have the highest priority).
+* Any value larger than 31 means "no active interrupt", and
+* the default ISR (that does nothing) is executed.
+* The interrupt vector (32 ISR addresses array stored at
+* _interrupt_vector address) is initialised with the default
+* ISR address. The actual ISR addresses are supposed to be written
+* in the interrupt vector array by the boot code.
+* All non persistant registers, such as $1 to $15, and $24 to $25,
+* as well as register $31 and EPC, are saved in the interrupted
+* program stack, before calling the Interrupt Service Routine.
+* These registers can be used by the ISR code.
+*******************************************************************/
+_int_handler:
+    addiu   $29,    $29,    -23*4   # stack space reservation 
+    .set noat
+    sw      $1,     4*4($29)        # save $1 
+    .set at
+    sw      $2,     4*5($29)        # save $2 
+    sw      $3,     4*6($29)        # save $3 
+    sw      $4,     4*7($29)        # save $4 
+    sw      $5,     4*8($29)        # save $5 
+    sw      $6,     4*9($29)        # save $6 
+    sw      $7,     4*10($29)       # save $7 
+    sw      $8,     4*11($29)       # save $8 
+    sw      $9,     4*12($29)       # save $9 
+    sw      $10,    4*13($29)       # save $10 
+    sw      $11,    4*14($29)       # save $11 
+    sw      $12,    4*15($29)       # save $12 
+    sw      $13,    4*16($29)       # save $13 
+    sw      $14,    4*17($29)       # save $14 
+    sw      $15,    4*18($29)       # save $15 
+    sw      $24,    4*19($29)       # save $24 
+    sw      $25,    4*20($29)       # save $25 
+    sw      $31,    4*21($29)       # save $31 
+    mfc0    $27,    $14
+    sw      $27,    4*22($29)       # save EPC 
+
+    # XICU PRIO register address computation (depending on cluster_id & local_id)
+    mfc0    $10,    $15,    1       # $10 <= proc_id 
+    andi    $10,    $10,    0x3FF   # at most 1024 processors 
+    la      $11,    NB_PROCS        # $11 <= NB_PROCS 
+    divu    $10,    $11
+    mflo    $12                     # $12 <= cluster_id 
+    mfhi    $13                     # $13 <= local_id 
+    la      $11,    NB_CLUSTERS     # $11 <= NB_CLUSTERS 
+    li      $14,    0x80000000	    
+    divu    $14,    $11
+    mflo    $15	
+    sll     $15,    $15,    1       # $15 <= cluster_increment = 4G / NB_CLUSTERS 
+    multu   $15,    $12
+    mflo    $6	                    # $6 <= cluster_increment * cluster_id 
+    li      $7,     0b011110000000  # $7 <= PRIO offset 
+    sll     $8,     $13,    2       # $8 <= local_id*4 
+    addu    $9,     $7,     $8      # $9 <= PRIO offset + local_id*4 
+    la      $27,    seg_icu_base    
+    addu    $26,    $9,     $27     # $26 <= seg_icu_base + PRIO offset + local_id*4 
+    addu    $26,    $26,    $6      # $26 <= seg_icu_base + increment*cluster_id + PRIO offset + local_id*4 
+
+    # XICU access and interrupt vector access
+    lw      $26,    ($26)           # $26 <= PRIO register value 
+    andi    $27,    $26,    0x2     # test bit HWI active
+    beq     $27,    $0,     restore # do nothing if no active IRQ 
+    srl     $26,    $26,    14      # $26 <= $26 >> 14 
+    andi    $26,    $26,    0x7C    # $26 <= interrupt_index * 4 
+    la      $27,    _interrupt_vector
+    addu    $26,    $26,    $27
+    lw      $26,    ($26)           # read ISR address 
+    jalr    $26                     # call ISR 
+restore:
+    .set noat
+    lw      $1,     4*4($29)        # restore $1 
+    .set at
+    lw      $2,     4*5($29)        # restore $2 
+    lw      $3,     4*6($29)        # restore $3 
+    lw      $4,     4*7($29)        # restore $4 
+    lw      $5,     4*8($29)        # restore $5 
+    lw      $6,     4*9($29)        # restore $6 
+    lw      $7,     4*10($29)       # restore $7 
+    lw      $8,     4*11($29)       # restore $8 
+    lw      $9,     4*12($29)       # restore $9 
+    lw      $10,    4*13($29)       # restore $10 
+    lw      $11,    4*14($29)       # restore $11 
+    lw      $12,    4*15($29)       # restore $12 
+    lw      $13,    4*16($29)       # restore $13 
+    lw      $14,    4*17($29)       # restore $14 
+    lw      $15,    4*18($29)       # restore $15 
+    lw      $24,    4*19($29)       # restore $24 
+    lw      $25,    4*20($29)       # restore $25 
+    lw      $31,    4*21($29)       # restore $31 
+    lw      $27,    4*22($29)       # return address (EPC) 
+    addiu   $29,    $29,    23*4    # restore stack pointer 
+    mtc0    $27,    $14             # restore EPC 
+    eret                            # exit GIET 
+
+/* The default ISR is called when no specific ISR has been installed in the
+ interrupt vector. It simply displays a message on TTY 0. */
+
+isr_default:
+    addiu   $29,    $29,    -20     # get space in stack 
+    sw      $31,    16($29)         # to save the return address 
+    la      $4,     msg_default     # $4 <= string address 
+    addi    $5,     $0,     36      # $5 <= string length 
+    jal     _tty_write              # print 
+    lw      $31,    16($29)         # restore return address 
+    addiu   $29,    $29,    20      # free space 
+    jr      $31                     # returns to interrupt handler 
+
+/*****************************************************
+ Interrupt Vector Table (indexed by interrupt index)
+  32 words corresponding to 32 ISR addresses 
+******************************************************/
+_interrupt_vector:
+    .word isr_default   # ISR 0 
+    .word isr_default   # ISR 1 
+    .word isr_default   # ISR 2 
+    .word isr_default   # ISR 3 
+    .word isr_default   # ISR 4 
+    .word isr_default   # ISR 5 
+    .word isr_default   # ISR 6 
+    .word isr_default   # ISR 7 
+    .word isr_default   # ISR 8 
+    .word isr_default   # ISR 9 
+    .word isr_default   # ISR 10 
+    .word isr_default   # ISR 11 
+    .word isr_default   # ISR 12 
+    .word isr_default   # ISR 13 
+    .word isr_default   # ISR 14 
+    .word isr_default   # ISR 15 
+    .word isr_default   # ISR 16 
+    .word isr_default   # ISR 17 
+    .word isr_default   # ISR 18 
+    .word isr_default   # ISR 19 
+    .word isr_default   # ISR 20 
+    .word isr_default   # ISR 21 
+    .word isr_default   # ISR 22 
+    .word isr_default   # ISR 23 
+    .word isr_default   # ISR 24 
+    .word isr_default   # ISR 25 
+    .word isr_default   # ISR 26 
+    .word isr_default   # ISR 27 
+    .word isr_default   # ISR 28 
+    .word isr_default   # ISR 29 
+    .word isr_default   # ISR 30 
+    .word isr_default   # ISR 31 
+
+/***********************************************************
+*    Exception Handler
+* Same code for all fatal exceptions :
+* Print the exception type and the values of EPC & BAR
+* on the TTY correspondintg to the processor PROCID,
+* and the user program is killed.
+***********************************************************/
+_cause_bp:
+_cause_ukn:
+_cause_ri:
+_cause_ovf:
+_cause_adel:
+_cause_ades:
+_cause_ibe:
+_cause_dbe:
+_cause_cpu:
+    mfc0    $26,    $13             # $26 <= CR 
+    andi    $26,    $26,    0x3C    # $26 <= _cause_index * 4 
+    la      $27,    mess_causes     # mess_cause table base address 
+    addu    $27,    $26,    $27     # pointer on the message base address 
+
+    lw      $4,     ($27)           # $4 <= message address 
+    li      $5,     36              # $5 <= message length 
+    jal     _tty_write              # print message cause 
+
+    la      $4,     msg_epc         # $4 <= message address 
+    li      $5,     8               # $5 <= message length 
+    jal     _tty_write              # print message EPC 
+
+    mfc0    $4,     $14             # $4 <= EPC value 
+    la      $5,     itoa_buffer     # $5 <= buffer address 
+    addiu   $5,     $5,     2       # skip 0x prefix 
+    jal     _itoa_hex               # fill buffer 
+
+    la      $4,     itoa_buffer     # $4 <= buffer address 
+    li      $5,     10              # $5 <= buffer length 
+    jal     _tty_write              # print EPC value 
+
+    la      $4,     msg_bar         # $4 <= mesage address 
+    li      $5,     8               # $5 <= message length 
+    jal     _tty_write              # print message BAR 
+
+    mfc0    $4,     $8              # $4 <= BAR value 
+    la      $5,     itoa_buffer     # $5 <= buffer address 
+    addiu   $5,     $5,     2       # skip 0x prefix 
+    jal     _itoa_hex               # fill buffer 
+
+    la      $4,     itoa_buffer     # $4 <= mesage address 
+    li      $5,     10              # $5 <= message length 
+    jal     _tty_write              # print BAR value 
+
+    j       _exit                   # end program 
+
+# Exceptions Messages table (indexed by CAUSE)  
+mess_causes:
+    .word msg_ukncause
+    .word msg_ukncause
+    .word msg_ukncause
+    .word msg_ukncause
+    .word msg_adel
+    .word msg_ades
+    .word msg_ibe
+    .word msg_dbe
+    .word msg_ukncause
+    .word msg_bp
+    .word msg_ri
+    .word msg_cpu
+    .word msg_ovf
+    .word msg_ukncause
+    .word msg_ukncause
+    .word msg_ukncause
+
+/*****************************************************************
+*    All messages
+* Messages length are fixed : 8 or 36 characters...
+*****************************************************************/
+msg_bar:        .asciiz "\nBAR  = "
+msg_epc:        .asciiz "\nEPC  = "
+msg_default:    .asciiz "\n\n  !!! Default ISR  !!!           \n"
+msg_uknsyscall: .asciiz "\n\n  !!! Undefined System Call !!!  \n"
+msg_ukncause:   .asciiz "\n\nException : strange unknown cause\n"
+msg_adel:       .asciiz "\n\nException : illegal read address \n"
+msg_ades:       .asciiz "\n\nException : illegal write address\n"
+msg_ibe:        .asciiz "\n\nException : inst bus error       \n"
+msg_dbe:        .asciiz "\n\nException : data bus error       \n"
+msg_bp:         .asciiz "\n\nException : breakpoint           \n"
+msg_ri:         .asciiz "\n\nException : reserved instruction \n"
+msg_ovf:        .asciiz "\n\nException : arithmetic overflow  \n"
+msg_cpu:        .asciiz "\n\nException : illegal coproc access\n"
+    .align 2
+
+
+/***************************************************************************
+*        _ctx_switch
+*   The _ctx_switch function performs a context switch between the
+*   current task and another task.
+*   It can be used in a multi-processor architecture, with the assumption
+*   that the tasks are statically allocated to processors.
+*   The max number of processorsi is 8, and the max number of tasks is 4.
+*   The scheduling policy is very simple : For each processor, the task index
+*   is incremented,  modulo the number of tasks allocated to the processor.
+*
+*   It has no argument, and no return value.
+*
+*   It uses three global variables:
+*    - _current_task_array :  an array of 8 task index:
+*      (index of the task actually running on each processor)
+*    - _task_number_array : an array of 8 numbers:
+*      (the number of tasks allocated to each processor)
+*       - _task_context_array : an array of 32 task contexts:
+*      (at most 8 processors / each processor can run up to 4 tasks)
+*   A task context is an array of 64 words = 256 bytes.
+*   It is indexed by m = (proc_id*4 + task_id)
+*   It contains copies of the processor registers.
+*   As much as possible a register is stored at the index defined by its number
+*   ( for example, $8 is saved in ctx[8]).
+*   The exception are :
+*   $0 is not saved since always 0
+*   $26, $27 are not saved since not used by the task
+*
+*   0*4(ctx) SR    8*4(ctx) $8    16*4(ctx) $16   24*4(ctx) $24   32*4(ctx) EPC
+*   1*4(ctx) $1    9*4(ctx) $9    17*4(ctx) $17   25*4(ctx) $25   33*4(ctx) CR
+*   2*4(ctx) $2   10*4(ctx) $10   18*4(ctx) $18   26*4(ctx) LO    34*4(ctx) reserved
+*   3*4(ctx) $3   11*4(ctx) $11   19*4(ctx) $19   27*4(ctx) HI    35*4(ctx) reserved
+*   4*4(ctx) $4   12*4(ctx) $12   20*4(ctx) $20   28*4(ctx) $28   36*4(ctx) reserved
+*   5*4(ctx) $5   13*4(ctx) $13   21*4(ctx) $21   29*4(ctx) $29   37*4(ctx) reserved
+*   6*4(ctx) $6   14*4(ctx) $14   22*4(ctx) $22   30*4(ctx) $30   38*4(ctx) reserved
+*   7*4(ctx) $7   15*4(ctx) $15   23*4(ctx) $23   31*4(ctx) $31   39*4(ctx) reserved
+*
+*   The return address contained in $31 is saved in the _current task context
+*   (in the ctx[31] slot), and the function actually returns to the address contained
+*   in the ctx[31] slot of the new task context.
+*
+*   Caution : This function is intended to be used with periodic interrupts.
+*   It can be directly called by the OS, but interrupts must be disabled before calling.
+***************************************************************************************/
+
+    .section .ksave
+
+    .global _task_context_array # initialised in reset.s 
+    .global _current_task_array # initialised in reset.s 
+    .global _task_number_array  # initialised in reset.s 
+
+_task_context_array:    # 32 contexts : indexed by (proc_id*4 + task_id) 
+    .space  8192
+
+_current_task_array:    # 8 words : indexed by the proc_id 
+    .word   0           # _current_task_array[0] <= 0 
+    .word   0           # _current_task_array[1] <= 0 
+    .word   0           # _current_task_array[2] <= 0 
+    .word   0           # _current_task_array[3] <= 0 
+    .word   0           # _current_task_array[4] <= 0 
+    .word   0           # _current_task_array[5] <= 0 
+    .word   0           # _current_task_array[6] <= 0 
+    .word   0           # _current_task_array[7] <= 0 
+
+_task_number_array:     # 8 words : indexed by the proc_id 
+    .word   1           # _task_number_array[0] <= 1 
+    .word   1           # _task_number_array[1] <= 1 
+    .word   1           # _task_number_array[2] <= 1 
+    .word   1           # _task_number_array[3] <= 1 
+    .word   1           # _task_number_array[4] <= 1 
+    .word   1           # _task_number_array[5] <= 1 
+    .word   1           # _task_number_array[6] <= 1 
+    .word   1           # _task_number_array[7] <= 1 
+
+/***************************************************************************************/
+
+    .section .switch
+
+    .global _ctx_switch # makes it an external symbol 
+    .align  2
+
+_ctx_switch:
+
+    # test if more than one task on the processor 
+
+    mfc0    $26,    $15,    1
+    andi    $26,    $26,    0x7         # $26 <= proc_id 
+    sll     $26,    $26,    2           # $26 <= 4*proc_id 
+    la      $27,    _task_number_array  # $27 <= base address of _task_number_array 
+    addu    $27,    $27,    $26         # $27 <= _task_number_array + 4*proc_id 
+    lw      $27,    ($27)               # $27 <= task number 
+    addi    $26,    $27,    -1          # $26 <= _task_number - 1 
+    bnez    $26,    do_it               # 0 if only one task 
+    jr      $31                         # return 
+
+    # save _current task context 
+
+do_it:
+    mfc0    $26,    $15,    1
+    andi    $26,    $26,    0x7         # $26 <= proc_id 
+    sll     $26,    $26,    2           # $26 <= 4*proc_id 
+    la      $27,    _current_task_array # $27 <= base address of _current_task_array 
+    addu    $27,    $27,    $26         # $27 <= _current_task_array + 4*proc_id 
+    lw      $26,    ($27)               # $26 <= current task index 
+    sll     $26,    $26,    8           # $26 <= 256*task_id 
+    la      $27,    _task_context_array # $27 <= base address of context array 
+    addu    $27,    $27,    $26         # $27 <= _task_context_array + 256*task_id 
+    mfc0    $26,    $15,    1
+    andi    $26,    $26,    0x7         # $26 <= proc_id 
+    sll     $26,    $26,    10          # $26 <= 1024*proc_id 
+    addu    $27,    $27,    $26         # $27 <= taxk_context_array + 256*(proc_id*4 + task_id) 
+
+    mfc0    $26,    $12         # $26 <= SR 
+    sw      $26,    0*4($27)    # ctx[0] <= SR 
+    .set noat
+    sw      $1,     1*4($27)    # ctx[1] <= $1 
+    .set at
+    sw      $2,     2*4($27)    # ctx[2] <= $2 
+    sw      $3,     3*4($27)    # ctx[3] <= $3 
+    sw      $4,     4*4($27)    # ctx[4] <= $4 
+    sw      $5,     5*4($27)    # ctx[5] <= $5 
+    sw      $6,     6*4($27)    # ctx[6] <= $6 
+    sw      $7,     7*4($27)    # ctx[7] <= $7 
+    sw      $8,     8*4($27)    # ctx[8] <= $8 
+    sw      $9,     9*4($27)    # ctx[9] <= $9 
+    sw      $10,    10*4($27)   # ctx[10] <= $10 
+    sw      $11,    11*4($27)   # ctx[11] <= $11 
+    sw      $12,    12*4($27)   # ctx[12] <= $12 
+    sw      $13,    13*4($27)   # ctx[13] <= $13 
+    sw      $14,    14*4($27)   # ctx[14] <= $14 
+    sw      $15,    15*4($27)   # ctx[15] <= $15 
+    sw      $16,    16*4($27)   # ctx[16] <= $16 
+    sw      $17,    17*4($27)   # ctx[17] <= $17 
+    sw      $18,    18*4($27)   # ctx[18] <= $18 
+    sw      $19,    19*4($27)   # ctx[19] <= $19 
+    sw      $20,    20*4($27)   # ctx[20] <= $20 
+    sw      $21,    21*4($27)   # ctx[21] <= $21 
+    sw      $22,    22*4($27)   # ctx[22] <= $22 
+    sw      $23,    23*4($27)   # ctx[23] <= $23 
+    sw      $24,    24*4($27)   # ctx[24] <= $24 
+    sw      $25,    25*4($27)   # ctx[25] <= $25 
+    mflo    $26
+    sw      $26,    26*4($27)   # ctx[26] <= LO 
+    mfhi    $26
+    sw      $26,    27*4($27)   # ctx[27] <= H1 
+    sw      $28,    28*4($27)   # ctx[28] <= $28 
+    sw      $29,    29*4($27)   # ctx[29] <= $29 
+    sw      $30,    30*4($27)   # ctx[30] <= $30 
+    sw      $31,    31*4($27)   # ctx[31] <= $31 
+    mfc0    $26,    $14
+    sw      $26,    32*4($27)   # ctx[32] <= EPC 
+    mfc0    $26,    $13
+    sw      $26,    33*4($27)   # ctx[33] <= CR 
+
+    # select  the new task 
+
+    mfc0    $15,    $15,    1
+    andi    $15,    $15,    0x7         # $15 <= proc_id 
+    sll     $16,    $15,    2           # $16 <= 4*proc_id 
+    la      $17,    _current_task_array # $17 <= base address of _current_task_array 
+    addu    $17,    $17,    $16         # $17 <= _current_task_array + 4*proc_id 
+    lw      $18,    ($17)               # $18 <= _current task index 
+    la      $19,    _task_number_array  # $19 <= base address of _task_number_array 
+    addu    $19,    $19,    $16         # $19 <= _task_number_array + 4*proc_id 
+    lw      $20,    ($19)               # $20 <= max = number of tasks 
+    addiu   $18,    $18,    1           # $18 <= new task index 
+    sub     $2,     $18,    $20         # test modulo max 
+    bne     $2,     $0,     no_wrap
+    add     $18,    $0,     $0          # $18 <= new task index 
+no_wrap:
+    sw      $18,    ($17)               # update _current_task_array 
+
+    # restore next task context 
+
+    sll     $19,    $18,    8           # $19 <= 256*task_id 
+    la      $27,    _task_context_array # $27 <= base address of context array 
+    addu    $27,    $27,    $19         # $27 <= _task_context_array + 256*task_id 
+    sll     $19,    $15,    10          # $19 <= 1024*proc_id 
+    addu    $27,    $27,    $19         # $27 <= _task_context_array + 256*(proc_id*4 + task_id) 
+
+    lw      $26,    0*4($27)
+    mtc0    $26,    $12                 # restore SR 
+    .set noat
+    lw      $1,     1*4($27)            # restore $1 
+    .set at
+    lw      $2,     2*4($27)            # restore $2 
+    lw      $3,     3*4($27)            # restore $3 
+    lw      $4,     4*4($27)            # restore $4 
+    lw      $5,     5*4($27)            # restore $5 
+    lw      $6,     6*4($27)            # restore $6 
+    lw      $7,     7*4($27)            # restore $7 
+    lw      $8,     8*4($27)            # restore $8 
+    lw      $9,     9*4($27)            # restore $9 
+    lw      $10,    10*4($27)           # restore $10 
+    lw      $11,    11*4($27)           # restore $11 
+    lw      $12,    12*4($27)           # restore $12 
+    lw      $13,    13*4($27)           # restore $13 
+    lw      $14,    14*4($27)           # restore $14 
+    lw      $15,    15*4($27)           # restore $15 
+    lw      $16,    16*4($27)           # restore $16 
+    lw      $17,    17*4($27)           # restore $17 
+    lw      $18,    18*4($27)           # restore $18 
+    lw      $19,    19*4($27)           # restore $19 
+    lw      $20,    20*4($27)           # restore $20 
+    lw      $21,    21*4($27)           # restore $21 
+    lw      $22,    22*4($27)           # restore $22 
+    lw      $23,    23*4($27)           # restore $23 
+    lw      $24,    24*4($27)           # restore $24 
+    lw      $25,    25*4($27)           # restore $25 
+    lw      $26,    26*4($27)
+    mtlo    $26                         # restore LO 
+    lw      $26,    27*4($27)
+    mthi    $26                         # restore HI 
+    lw      $28,    28*4($27)           # restore $28 
+    lw      $29,    29*4($27)           # restore $29 
+    lw      $30,    30*4($27)           # restore $30 
+    lw      $31,    31*4($27)           # restore $31 
+    lw      $26,    32*4($27)
+    mtc0    $26,    $14                 # restore EPC 
+    lw      $26,    33*4($27)
+    mtc0    $26,    $13                 # restore CR 
+
+    jr      $31                         # returns to caller 
+
+/* Local Variables:
+   tab-width: 4;
+   c-basic-offset: 4;
+   c-file-offsets:((innamespace . 0)(inline-open . 0));
+   indent-tabs-mode: nil;
+   End: */
+
+/* vim: set filetype=asm expandtab shiftwidth=4 tabstop=4 softtabstop=4: */
+
Index: branches/v4/softs/giet_tsar/icu.h
===================================================================
--- branches/v4/softs/giet_tsar/icu.h	(revision 371)
+++ branches/v4/softs/giet_tsar/icu.h	(revision 371)
@@ -0,0 +1,24 @@
+#ifndef ICU_REGS_H
+#define ICU_REGS_H
+
+enum SoclibPicRegisters {
+    ICU_INT = 0,
+    ICU_MASK = 1,
+    ICU_MASK_SET = 2,
+    ICU_MASK_CLEAR = 3,
+    ICU_IT_VECTOR = 4,
+    /***/
+    ICU_SPAN = 8,
+};
+
+#endif
+
+// Local Variables:
+// tab-width: 4;
+// c-basic-offset: 4;
+// c-file-offsets:((innamespace . 0)(inline-open . 0));
+// indent-tabs-mode: nil;
+// End:
+//
+// vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4
+
Index: branches/v4/softs/giet_tsar/isr.c
===================================================================
--- branches/v4/softs/giet_tsar/isr.c	(revision 371)
+++ branches/v4/softs/giet_tsar/isr.c	(revision 371)
@@ -0,0 +1,186 @@
+/*************************************************************************************
+   File : isr.c
+   Authors : Alain Greiner
+   Date : april 2011
+
+   These routines must be "intalled" by the boot code in the
+   interrupt vector, depending on the system architecture.
+*************************************************************************************/
+
+#include "isr.h"
+#include "drivers.h"
+
+#define in_isr __attribute__((section (".isr")))
+
+struct plaf;
+
+extern struct plaf seg_dma_base;
+extern struct plaf seg_ioc_base;
+extern struct plaf seg_timer_base;
+extern struct plaf seg_tty_base;
+
+extern struct plaf NB_TIMERS;
+extern struct plaf NB_TASKS;
+
+//////////////////////////////////////////////////////////////////////////////////////
+//  _isr_dma
+//  Each processor controls its own private DMA.
+//  It acknowledge the IRQ using the dma base address depending on the proc_id
+//  as computed by the  _segment_increment() function, writes the transfer
+//  status in the _dma_status[pid] variable, and resets the _dma_busy[pid]
+//  synchrnisation variable to signal completion.
+//  Both variables are defined in the drivers.c file.
+/////////////////////////////////////////////////////////////////////////////////////
+in_isr void _isr_dma()
+{
+    int*		dma_address;
+    unsigned int	base		= (unsigned int)&seg_dma_base;
+    unsigned int	increment 	= _segment_increment(DMA_SPAN*4);
+    size_t		pid		= _procid();
+   
+    dma_address	= (int*)(base + increment);
+    
+    _dma_status[pid]		= dma_address[DMA_LEN];	// save status
+    _dma_busy[pid]		= 0;			// release DMA
+    dma_address[DMA_RESET]	= 0;			// reset IRQ
+}
+//////////////////////////////////////////////////////////////////////////////////////
+//  _isr_ioc
+//  There is only one IOC controler shared by all tasks.
+//  It acknowledge the IRQ using the ioc base address, save the status,
+//  and set the _ioc_done variable to signal completion.
+//  This variable is defined in the drivers.c file.
+//////////////////////////////////////////////////////////////////////////////////////
+in_isr void _isr_ioc()
+{
+    int* ioc_address = (int*)&seg_ioc_base;
+    
+    _ioc_status = ioc_address[BLOCK_DEVICE_STATUS];	// save status & reset IRQ
+    _ioc_done   = 1;					// signals completion
+}
+//////////////////////////////////////////////////////////////////////////////////////
+//  _isr_timer* (* = 0,1,2,3)
+//  A single processor can use up to 4 independant timers.
+//  These 4 ISRs handle up to 4 IRQs generated by 4 independant timers,
+//  connected to a single processor.
+//  It acknowledge the IRQ using the timer base address depending
+//  on both the proc_id and the timer_id (0,1,2,3).
+//  It displays a message on TTY[proc_id,task_id]. 
+//////////////////////////////////////////////////////////////////////////////////////
+in_isr void _isr_timer_indexed(size_t timer_id)
+{
+    int*		timer_address;
+    size_t		ntimers		= (size_t)&NB_TIMERS;
+    unsigned int	base		= (unsigned int)&seg_timer_base;
+    unsigned int	increment 	= _segment_increment(ntimers*TIMER_SPAN*4);
+    int			date 		= (int)_proctime();
+    char		buf[10];
+
+    timer_address = (int*)(base + increment + timer_id*TIMER_SPAN*4);
+
+    timer_address[TIMER_RESETIRQ] = 0;			// reset IRQ
+
+    _itoa_dec(date, buf);				// print message
+    _tty_write("\n!!! interrupt timer0 received at cycle ", 40);
+    _tty_write(buf, 10); 
+    _tty_write("\n\n", 2);
+}
+in_isr void _isr_timer()
+{
+    _isr_timer_indexed(0);
+}
+in_isr void _isr_timer0()
+{
+    _isr_timer_indexed(0);
+}
+in_isr void _isr_timer1()
+{
+    _isr_timer_indexed(1);
+}
+in_isr void _isr_timer2()
+{
+    _isr_timer_indexed(2);
+}
+in_isr void _isr_timer3()
+{
+    _isr_timer_indexed(3);
+}
+//////////////////////////////////////////////////////////////////////////////////////
+//  _isr_tty_get_task* (* = 0,1,2,3)
+//  A single processor can run up to 4 tasks in pseudo-parallelismr,
+//  and each task has is own private terminal.
+//  These 4 ISRs handle up to 4 IRQs associate to 4 independant terminals
+//  connected to a single processor.
+//  It acknowledge the IRQ using the terminal basee address depending
+//  on both the proc_id  and the task_id (0,1,2,3).
+//  There is one communication buffer _tty_get_buf[tty_id] per terminal.
+//  protected by a set/reset variable _tty_get_full[tty_id].
+//  The _tty_get_full[tty_id] synchronisation variable is set
+//  by the ISR, and reset by the OS.
+//  Both variables are defined in the drivers.c file.
+//  To access these buffers, the terminal index is computed as
+//      tty_id = proc_id*ntasks + task_id
+//  A character is lost if the buffer is full when the ISR is executed.
+//////////////////////////////////////////////////////////////////////////////////////
+in_isr void _isr_tty_get_indexed(size_t task_id)
+{
+    char*		tty_address;
+    size_t		ntasks		= (size_t)&NB_TASKS;
+    size_t		tty_id		= _procid()*ntasks + task_id;
+    unsigned int	base		= (unsigned int)&seg_tty_base;
+    unsigned int	increment 	= _segment_increment(ntasks*TTY_SPAN*4);
+
+    tty_address = (char*)(base + increment + task_id*TTY_SPAN*4);
+
+    _tty_get_buf[tty_id] = tty_address[TTY_READ*4];	// save character and reset IRQ
+    _tty_get_full[tty_id] = 1;				// signals character available
+}
+in_isr void _isr_tty_get()
+{
+    _isr_tty_get_indexed(0);
+}
+in_isr void _isr_tty_get_task0()
+{
+    _isr_tty_get_indexed(0);
+}
+in_isr void _isr_tty_get_task1()
+{
+    _isr_tty_get_indexed(1);
+}
+in_isr void _isr_tty_get_task2()
+{
+    _isr_tty_get_indexed(2);
+}
+in_isr void _isr_tty_get_task3()
+{
+    _isr_tty_get_indexed(3);
+}
+//////////////////////////////////////////////////////////////////////////////////////
+//  _isr_switch
+//  This ISR is in charge of context switch.
+//  It handles up to 4 IRQs, corresponding to 4 different processors.
+//  If the processor uses several timers, the context switch is driven
+//  by the IRQ associated to timer0.
+//  It acknowledges the IRQ on TIMER[proc_id] and calls the _ctx_switch() function.
+//////////////////////////////////////////////////////////////////////////////////////
+in_isr void _isr_switch()
+{
+    int*		timer_address;
+    unsigned int	base		= (unsigned int)&seg_timer_base;
+    unsigned int	increment	= _segment_increment(TIMER_SPAN*4);
+
+    timer_address = (int*)(base + increment);
+
+    timer_address[TIMER_RESETIRQ] = 0;			// reset IRQ
+    _ctx_switch();
+}
+
+/* Local Variables:
+   tab-width: 4;
+   c-basic-offset: 4;
+   c-file-offsets:((innamespace . 0)(inline-open . 0));
+   indent-tabs-mode: nil;
+   End: */
+
+/* vim: set filetype=c expandtab shiftwidth=4 tabstop=4 softtabstop=4: */
+
Index: branches/v4/softs/giet_tsar/isr.h
===================================================================
--- branches/v4/softs/giet_tsar/isr.h	(revision 371)
+++ branches/v4/softs/giet_tsar/isr.h	(revision 371)
@@ -0,0 +1,24 @@
+/**************************************************************************************
+    File : isr.h
+    Written by Alain Greiner
+    Date : April 2011
+
+    The Interrupt Service Routine (ISR) supported by the GIET are:
+**************************************************************************************/
+
+void _isr_dma();
+
+void _isr_ioc();
+
+void _isr_timer0();
+void _isr_timer1();
+void _isr_timer2();
+void _isr_timer3();
+
+void _isr_tty_get();
+void _isr_tty_get_task0();
+void _isr_tty_get_task1();
+void _isr_tty_get_task2();
+void _isr_tty_get_task3();
+
+void _isr_switch();
Index: branches/v4/softs/giet_tsar/reset.s
===================================================================
--- branches/v4/softs/giet_tsar/reset.s	(revision 371)
+++ branches/v4/softs/giet_tsar/reset.s	(revision 371)
@@ -0,0 +1,135 @@
+#################################################################################
+#	File : reset.s
+#	Author : Alain Greiner
+#	Date : 15/04/2011
+#################################################################################
+# 	This is a boot code for a generic multi-clusters / multi-processors
+#       TSAR architecture (up to 256 clusters / up to 4  processors per cluster). 
+#       There is one XICU, one TTY, one DMA and one stack segment per cluster.
+#       segment base adresses = base + cluster_segment_increment*cluster_id
+#	- Each processor initializes the stack pointer ($29) depending on pid.
+#	- Only processor 0 initializes the Interrupt vector (TTY, DMA & IOC).
+#       - Each processor initialises its private ICU mask register.
+#	- Each processor initializes the Status Register (SR) 
+#	- Each processor initializes the EPC register, and jumps to the main 
+#	  address in kernel mode...
+#################################################################################
+		
+	.section .reset,"ax",@progbits
+
+	.extern	seg_stack_base
+	.extern	seg_icu_base
+	.extern _interrupt_vector
+	.extern _isr_tty_get
+	.extern _isr_dma
+	.extern _isr_ioc
+
+        .extern NB_PROCS
+        .extern NB_CLUSTERS
+
+	.globl  reset	 			# makes reset an external symbol 
+	.ent	reset
+	.align	2
+
+reset:
+       	.set noreorder
+
+# computes proc_id, local_id, cluster_id, and cluster_increment
+    mfc0    $26,    $15,    1
+    andi    $10,    $26,    0x3FF	# $10 <= proc_id (at most 1024 processors)
+    la      $26,    NB_PROCS		# $26 <= number of processors per cluster
+    divu    $10,    $26
+    mfhi    $11                 	# $11 <= local_id = proc_id % NB_PROCS
+    mflo    $12              		# $12 <= cluster_id = proc_id / NB_PROCS
+    la      $26,    NB_CLUSTERS
+    li      $13,    0x80000000
+    divu    $13,    $26
+    mflo    $14
+    sll     $14,    1			# $14 <= cluster_increment = 4G / NB_CLUSTERS
+    mult    $14,    $12	
+    mflo    $13                 	# $13 <= cluster_id * cluster_increment
+
+# initializes stack pointer depending on both the local_id and the cluster_id
+    la      $27,    seg_stack_base
+    addu    $27,    $27,    $13		# $27 <= seg_stack_base + cluster_id * increment
+    li      $26,    0x10000		# $26 <= 64K
+    addi    $25,    $11,    1		# $25 <= local_id + 1
+    mult    $25,    $26
+    mflo    $24				# $24 <= 64K * (local_id+1)
+    addu    $29,    $27,    $24		# $29 <= seg_stack_base + (cluster_id*increment) + (local_id+1)*64K
+
+# in each cluster, each processor initializes its private XICU mask register
+# in each cluster, the ICU base address depends on the cluster_id
+    la      $20,    seg_icu_base
+    addu    $20,    $20,    $13		# $20 <= seg_icu_base + cluster_id*cluster_increment
+    la      $21,    _reset_switch
+    sll     $22,    $11,    2           # $22 <= local_id*4
+    addu    $23,    $21,    $22         # $23 <= &_reset_switch[local_id*4]
+    lw      $24,    0($23)
+    jr      $24
+    nop
+_reset_proc0:
+    li      $13,    0b010010000000      # offset for MSK_HWI_ENABLE & proc[0]
+    addu    $13,    $20,    $13
+    li      $27,    0x111		# TTY[0] DMA[0] IOC
+    sw      $27,    0($13)              # MASK[0]
+    j       _reset_itvector
+_reset_proc1:
+    li      $13,    0b010010000100      # offset for MSK_HWI_ENABLE & proc[1]
+    addu    $13,    $20,    $13
+    li      $27,    0x022		# TTY[1] DMA[1]
+    sw      $27,    0($13)              # MASK[1]
+    j       _reset_itvector
+_reset_proc2:
+    li      $13,    0b010010001000      # offset for MSK_HWI_ENABLE & proc[2]
+    addu    $13,    $20,    $13
+    li      $27,    0x044		# TTY[2] DMA[2]
+    sw      $27,    0($13)              # MASK[2]
+    j       _reset_itvector
+_reset_proc3:
+    li      $13,    0b010010001100      # offset for MSK_HWI_ENABLE & proc[3]
+    addu    $13,    $20,    $13
+    li      $27,    0x088		# TTY[3] DMA[3]
+    sw      $27,    0($13)              # MASK[3]
+    j       _reset_itvector
+    nop
+
+_reset_switch:
+    .word	_reset_proc0
+    .word	_reset_proc1
+    .word	_reset_proc2
+    .word	_reset_proc3
+
+# only processor 0 in cluster 0 initializes interrupt vector
+
+_reset_itvector:
+    bne	    $10,    $0,    _reset_end
+    nop
+    la      $26,    _interrupt_vector   # interrupt vector address
+    la      $27,    _isr_dma 
+    sw      $27,    0($26)              # interrupt_vector[0] <= _isr_dma_get
+    sw      $27,    4($26)              # interrupt_vector[1] <= _isr_dma_get
+    sw      $27,    8($26)              # interrupt_vector[2] <= _isr_dma_get
+    sw      $27,   12($26)              # interrupt_vector[3] <= _isr_dma_get
+    la      $27,    _isr_tty_get 
+    sw      $27,   16($26)              # interrupt_vector[4] <= _isr_tty
+    sw      $27,   20($26)              # interrupt_vector[5] <= _isr_tty
+    sw      $27,   24($26)              # interrupt_vector[6] <= _isr_tty
+    sw      $27,   28($26)              # interrupt_vector[7] <= _isr_tty
+    la      $27,    _isr_ioc 
+    sw      $27,   32($26)              # interrupt_vector[8] <= _isr_ioc
+
+_reset_end:
+
+# initializes SR register
+    li	    $26,    0x0000FF01		
+    mtc0    $26,    $12			# SR <= kernel mode / IRQ enable 
+
+# jumps to main in kernel mode
+    la	    $26,    main
+    jr      $26
+    nop
+
+    .end	reset
+
+    .set reorder
Index: branches/v4/softs/giet_tsar/stdio.c
===================================================================
--- branches/v4/softs/giet_tsar/stdio.c	(revision 371)
+++ branches/v4/softs/giet_tsar/stdio.c	(revision 371)
@@ -0,0 +1,833 @@
+/*********************************************************************
+    fichier stdio.c
+    Written Alain greiner & Nicolas Pouillon
+    Date : 19/10/2009
+
+ These function implement the drivers for the SoCLib peripherals.
+ *********************************************************************/
+
+#include <stdarg.h>
+
+#include "stdio.h"
+
+#include "timer.h"
+#include "tty.h"
+#include "gcd.h"
+#include "icu.h"
+#include "dma.h"
+#include "block_device.h"
+
+/*********************************************************************
+  We define a generic C function to implement all system calls.
+ *********************************************************************/
+inline int sys_call( int call_no,
+        int arg_0,
+        int arg_1,
+        int arg_2,
+        int arg_3 )
+{
+    register int reg_no_and_output asm("v0") = call_no;
+    register int reg_a0 asm("a0") = arg_0;
+    register int reg_a1 asm("a1") = arg_1;
+    register int reg_a2 asm("a2") = arg_2;
+    register int reg_a3 asm("a3") = arg_3;
+
+    asm volatile(
+            "syscall"
+            : "=r" (reg_no_and_output)  // arguments de sortie
+            : "r" (reg_a0),         // arguments d'entrée
+            "r" (reg_a1),
+            "r" (reg_a2),
+            "r" (reg_a3),
+            "r" (reg_no_and_output)
+            : "memory",             // ressources modifiees:
+            "at",
+            "v1",
+            "ra",            // Ces registres persistants seront sauvegardes
+            "t0",            // sur la pile par le compilateur
+            "t1",            // seulement s'ils contiennent des donnees
+            "t2",            // calculees par la fonction effectuant le syscall,
+            "t3",            // et que ces valeurs sont reutilisees par cette
+            "t4",            // fonction au retour du syscall.
+            "t5",
+            "t6",
+            "t7",
+            "t8",
+            "t9"
+               );
+    return reg_no_and_output;
+}
+
+/********************************************************************
+  procid()
+  Returns the processor ident.
+ ********************************************************************/
+int procid()
+{
+    return sys_call(SYSCALL_PROCID, 0, 0, 0, 0);
+}
+/********************************************************************
+  proctime()
+  Returns the local processor time.
+ ********************************************************************/
+int proctime()
+{
+    return sys_call(SYSCALL_PROCTIME, 0, 0, 0, 0);
+}
+/********************************************************************
+  procnumber()
+  Returns the number of processors controled by the system.
+ ********************************************************************/
+int procnumber()
+{
+    return sys_call(SYSCALL_PROCNUMBER, 0, 0, 0, 0);
+}
+/********************************************************************
+  exit()
+  Exit the program with a TTY message, and enter an infinite loop...
+ ********************************************************************/
+int exit()
+{
+    int proc_index = procid();
+    return sys_call(SYSCALL_EXIT, proc_index, 0, 0, 0);
+}
+/********************************************************************
+  rand()
+  Returns a pseudo-random value derived from the processor cycle count.
+  This value is comprised between 0 & 65535.
+ ********************************************************************/
+int rand()
+{
+    int x = sys_call(SYSCALL_PROCTIME, 0, 0, 0, 0);
+    if((x & 0xF) > 7)
+        return (x*x & 0xFFFF);
+    else
+        return (x*x*x & 0xFFFF);
+}
+
+/*************************************************************************
+  MULTI-TTY
+ **************************************************************************
+ tty_putc()
+ Display a single ascii character on a terminal.
+ The terminal index is implicitely defined by the processor ID.
+ (and by the task ID in case of multi-tasking)
+ It doesn't use the TTY_PUT_IRQ interrupt, and the associated kernel buffer.
+ This function returns 0 in case of success.
+ ******************************i*******************************************/
+int tty_putc(char byte)
+{
+    return sys_call(SYSCALL_TTY_WRITE,
+            (int)(&byte),
+            1,
+            0,0);
+}
+/*************************************************************************
+  tty_puts()
+  Display a string on a terminal.
+  The terminal index is implicitely defined by the processor ID.
+  (and by the task ID in case of multi-tasking)
+  The string must be terminated by a NUL character.
+  It doesn't use the TTY_PUT_IRQinterrupt, and the associated kernel buffer.
+  This function returns 0 in case of success.
+ **************************************************************************/
+int tty_puts(char* string)
+{
+    int length = 0;
+    while (string[length] != 0) {
+        length++;
+    }
+    return sys_call(SYSCALL_TTY_WRITE,
+            (int)string,
+            length,
+            0,0);
+}
+/*************************************************************************
+  tty_putw()
+  Display the value of a 32 bits word (decimal characters).
+  The terminal index is implicitely defined by the processor ID.
+  (and by pthe task ID in case of multi-tasking)
+  It doesn't use the TTY_PUT_IRQ interrupt, and the associated kernel buffer.
+  This function returns 0 in case of success.
+ **************************************************************************/
+int tty_putw(int val)
+{
+    char buf[10];
+    int i;
+    for( i=0 ; i<10 ; i++ ) {
+        buf[9-i] = (val % 10) + 0x30;
+        val = val / 10;
+    }
+    return sys_call(SYSCALL_TTY_WRITE,
+            (int)buf,
+            10,
+            0,0);
+}
+/********************************************************************
+  tty_getc()
+  Fetch a single ascii character from a terminal.
+  The terminal index is implicitely defined by the processor ID.
+  (and by the task ID in case of multi-tasking)
+  It doesn't use the IRQ_GET interrupt, and the associated kernel buffer.
+  It is a blocking function that returns 0 if a valid char is stored
+  in the buffer, and returns -1 in case of error.
+ ********************************************************************/
+int tty_getc(char* buf)
+{
+    int ret = 0;
+    while( ret == 0 )
+    {
+        ret = sys_call(SYSCALL_TTY_READ,
+                (int)buf,
+                1,
+                0,0);
+        if ((ret < 0) || (ret > 1)) return -1;  // return error
+    }
+    return 0;   // return ok
+}
+/********************************************************************
+  tty_getc_irq()
+  Fetch a single ascii character from a terminal.
+  The terminal index is implicitely defined by the processor ID.
+  (and by the task ID in case of multi-tasking)
+  It uses the IRQ_GET interrupt, and the associated kernel buffer.
+  It is a blocking function that returns 0 if a valid char is stored
+  in the buffer, and returns -1 in case of error.
+ ********************************************************************/
+int tty_getc_irq(char* buf)
+{
+    int ret = 0;
+    while( ret == 0 )
+    {
+        ret = sys_call(SYSCALL_TTY_READ_IRQ,
+                (int)buf,
+                1,
+                0,0);
+        if ((ret < 0) || (ret > 1)) return -1;  // return error
+    }
+    return 0;   // return ok
+}
+/********************************************************************
+  tty_gets_irq()
+  Fetch a string from a terminal to a bounded length buffer.
+  The terminal index is implicitely defined by the processor ID.
+  (and by the task ID in case of multi-tasking)
+  It uses the TTY_GET_IRQ interrupt, anf the associated kernel buffer.
+  It is a blocking function that returns 0 if a valid string is stored
+  in the buffer, and returns -1 in case of error.
+  Up to (bufsize - 1) characters (including the non printable
+  characters) will be copied into buffer, and the string is
+  always completed by a NUL character.
+  The <LF> character is interpreted, as the function close
+  the string with a NUL character if <LF> is read.
+  The <DEL> character is interpreted, and the corresponding
+  character(s) are removed from the target buffer.
+ ********************************************************************/
+int tty_gets_irq(char* buf, int bufsize)
+{
+    int ret;
+    unsigned char byte;
+    unsigned int index = 0;
+
+    while( index < (bufsize-1) )
+    {
+        ret = sys_call(SYSCALL_TTY_READ_IRQ,
+                (int)(&byte),
+                1,
+                0,0);
+
+        if ((ret < 0) || (ret > 1)) return -1;  // return error
+
+        else if ( ret == 1 )            // valid character
+        {
+            if ( byte == 0x0A ) break; // LF
+            else if ((byte == 0x7F) && (index>0)) index--; // DEL
+            else
+            {
+                buf[index] = byte;
+                index++;
+            }
+        }
+    } // end while
+    buf[index] = 0;
+    return 0;       // return ok
+}
+/********************************************************************
+  tty_getw_irq()
+  Fetch a string of decimal characters (most significant digit first)
+  to build a 32 bits unsigned int.
+  The terminal index is implicitely defined by the processor ID.
+  (and by the task ID in case of multi-tasking)
+  This is a blocking function that returns 0 if a valid unsigned int
+  is stored in the buffer, and returns -1 in case of error.
+  It uses the TTY_GET_IRQ interrupt, anf the associated kernel buffer.
+  The non-blocking system function _tty_read_irq is called several times,
+  and the decimal characters are written in a 32 characters buffer
+  until a <LF> character is read.
+  The <DEL> character is interpreted, and previous characters can be
+  cancelled. All others characters are ignored.
+  When the <LF> character is received, the string is converted to
+  an unsigned int value. If the number of decimal digit is too large
+  for the 32 bits range, the zero value is returned.
+ ********************************************************************/
+int tty_getw_irq(int* word_buffer)
+{
+    unsigned char buf[32];
+    unsigned char byte;
+    unsigned int save = 0;
+    unsigned int val = 0;
+    unsigned int done = 0;
+    unsigned int overflow = 0;
+    unsigned int max = 0;
+    unsigned int i;
+    int ret;
+
+    while(done == 0)
+    {
+        ret = sys_call(SYSCALL_TTY_READ_IRQ,
+                (int)(&byte),
+                1,
+                0,0);
+        if ((ret < 0) || (ret > 1)) return -1;  // return error
+
+        if ( ret == 1 )     // get one character
+        {
+            if (( byte > 0x2F) && (byte < 0x3A))  // decimal character
+            {
+                buf[max] = byte;
+                max++;
+                tty_putc(byte);
+            }
+            else if ( (byte == 0x0A) || (byte == 0x0D) ) // LF or CR character
+            {
+                done = 1;
+            }
+            else if ( byte == 0x7F )        // DEL character
+            {
+                if (max > 0)
+                {
+                    max--;          // cancel the character
+                    tty_putc(0x08);
+                    tty_putc(0x20);
+                    tty_putc(0x08);
+                }
+            }
+            if ( max == 32 )            // decimal string overflow
+            {
+                for( i=0 ; i<max ; i++)     // cancel the string
+                {
+                    tty_putc(0x08);
+                    tty_putc(0x20);
+                    tty_putc(0x08);
+                }
+                tty_putc(0x30);
+                *word_buffer = 0;           // return 0 value
+                return 0;
+            }
+        }
+    } // end while
+
+    // string conversion
+    for( i=0 ; i<max ; i++ )
+    {
+        val = val*10 + (buf[i] - 0x30);
+        if (val < save) overflow = 1;
+        save = val;
+    }
+    if (overflow == 0)
+    {
+        *word_buffer = val;     // return decimal value
+    }
+    else
+    {
+        for( i=0 ; i<max ; i++)     // cancel the string
+        {
+            tty_putc(0x08);
+            tty_putc(0x20);
+            tty_putc(0x08);
+        }
+        tty_putc(0x30);
+        *word_buffer = 0;       // return 0 value
+    }
+    return 0;
+}
+/*********************************************************************
+  tty_printf()
+  This function is a simplified version of the mutek_printf() function.
+  The terminal index is implicitely defined by the processor ID.
+  (and by the task ID in case of multi-tasking)
+  It doesn't use the IRQ_PUT interrupt, anf the associated kernel buffer.
+  Only a limited number of formats are supported:
+  - %d : signed decimal
+  - %u : unsigned decimal
+  - %x : hexadecimal
+  - %c : char
+  - %s : string
+ *********************************************************************/
+int tty_printf(char *format, ...)
+{
+    va_list ap;
+    va_start(ap, format);
+
+printf_text:
+
+    while (*format) {
+        unsigned int i;
+        for (i = 0; format[i] && format[i] != '%'; i++)
+            ;
+        if (i) {
+            sys_call(SYSCALL_TTY_WRITE,
+                    (int)format,
+                    i,
+                    0,0);
+            format += i;
+        }
+        if (*format == '%') {
+            format++;
+            goto printf_arguments;
+        }
+    } // end while
+
+    va_end(ap);
+    return 0;
+
+printf_arguments:
+
+    {
+        int         val = va_arg(ap, long);
+        char            buf[20];
+        char*           pbuf;
+        unsigned int        len = 0;
+        static const char   HexaTab[] = "0123456789ABCDEF";
+        unsigned int        i;
+
+        switch (*format++) {
+            case ('c'):             // char conversion
+                len = 1;
+                buf[0] = val;
+                pbuf = buf;
+                break;
+            case ('d'):             // decimal signed integer
+                if (val < 0) {
+                    val = -val;
+                    sys_call(SYSCALL_TTY_WRITE,
+                            (int)"-",
+                            1,
+                            0,0);
+                }
+            case ('u'):             // decimal unsigned integer
+                for( i=0 ; i<10 ; i++) {
+                    buf[9-i] = HexaTab[val % 10];
+                    if (!(val /= 10)) break;
+                }
+                len =  i+1;
+                pbuf = &buf[9-i];
+                break;
+            case ('x'):             // hexadecimal integer
+                sys_call(SYSCALL_TTY_WRITE,
+                        (int)"0x",
+                        2,
+                        0,0);
+                for( i=0 ; i<8 ; i++) {
+                    buf[7-i] = HexaTab[val % 16U];
+                    if (!(val /= 16U)) break;
+                }
+                len =  i+1;
+                pbuf = &buf[7-i];
+                break;
+            case ('s'):             // string
+                {
+                    char *str = (char*)val;
+                    while ( str[len] ) len++;
+                    pbuf = (char*)val;
+                }
+                break;
+            default:
+                goto printf_text;
+        } // end switch
+
+        sys_call(SYSCALL_TTY_WRITE,
+                (int)pbuf,
+                len,
+                0,0);
+        goto printf_text;
+    }
+} // end printf()
+
+/********************************************************************
+  MULTI-TIMER
+  For all system calls, the first argument is the Timer index.
+ *********************************************************************
+ timer_set_mode()
+ The possible values for the TIMER_MODE register are
+ - 0x0 : Timer not activated
+ - 0x1 : Timer activated, but no interrupt is generated
+ - 0x3 : Timer activarted and periodic interrupts generated
+ ********************************************************************/
+int timer_set_mode(int timer_index, int val)
+{
+    return sys_call(SYSCALL_TIMER_WRITE,
+            timer_index,
+            TIMER_MODE,
+            val,
+            0);
+}
+/********************************************************************
+  timer_set_period()
+  Defines the period value for the periodic interrupt.
+ ********************************************************************/
+int timer_set_period(int timer_index, int val)
+{
+    return sys_call(SYSCALL_TIMER_WRITE,
+            timer_index,
+            TIMER_PERIOD,
+            val,
+            0);
+}
+/********************************************************************
+  timer_reset_irq()
+ ********************************************************************/
+int timer_reset_irq(int timer_index)
+{
+    return sys_call(SYSCALL_TIMER_WRITE,
+            timer_index,
+            TIMER_RESETIRQ,
+            0, 0);
+}
+/********************************************************************
+  timer_get_time()
+  returns the current timer value.
+ ********************************************************************/
+int timer_get_time(int timer_index, int* time)
+{
+    return sys_call(SYSCALL_TIMER_READ,
+            timer_index,
+            TIMER_VALUE,
+            (int)time,
+            0);
+}
+
+/********************************************************************
+  GCD COPROCESSOR
+ *********************************************************************
+ gcd_set_opa(int val)
+ Set operand A in the GCD (Greater Common Divider) coprocessor.
+ ********************************************************************/
+int gcd_set_opa(int val)
+{
+    return sys_call(SYSCALL_GCD_WRITE,
+            GCD_OPA,
+            val,
+            0, 0);
+}
+/********************************************************************
+  gcd_set_opb(int val)
+  Set operand B in the GCD (Greater Common Divider) coprocessor.
+ ********************************************************************/
+int gcd_set_opb(int val)
+{
+    return sys_call(SYSCALL_GCD_WRITE,
+            GCD_OPB,
+            val,
+            0, 0);
+}
+/********************************************************************
+  gcd_start()
+  Start computation in the GCD (Greater Common Divider) coprocessor.
+ ********************************************************************/
+int gcd_start(int val)
+{
+    return sys_call(SYSCALL_GCD_WRITE,
+            GCD_START,
+            0, 0, 0);
+}
+/********************************************************************
+  gcd_get_status(int* val)
+  Get status fromn the GCD (Greater Common Divider) coprocessor.
+  The value is nul when the coprocessor is idle (computation completed)
+ ********************************************************************/
+int gcd_get_status(int* val)
+{
+    return sys_call(SYSCALL_GCD_READ,
+            GCD_STATUS,
+            (int)val,
+            0, 0);
+}
+/********************************************************************
+  gcd_get_result(int* val)
+  Get result fromn the GCD (Greater Common Divider) coprocessor.
+ ********************************************************************/
+int gcd_get_result(int* val)
+{
+    return sys_call(SYSCALL_GCD_READ,
+            GCD_OPA,
+            (int)val,
+            0, 0);
+}
+
+/********************************************************************
+  ICU(s)
+ *********************************************************************
+ icu_set_mask()
+ Set some bits in the Interrupt Enable Mask of the ICU component.
+ Each bit set in the written word will be set in the Mask Enable.
+ ********************************************************************/
+int icu_set_mask(int val)
+{
+    return sys_call(SYSCALL_ICU_WRITE,
+            ICU_MASK_SET,
+            val,
+            0, 0);
+}
+/********************************************************************
+  icu_clear_mask()
+  Reset some bits in the Interrupt Enable Mask of the ICU component.
+  Each bit set in the written word will be reset in the Mask Enable.
+ ********************************************************************/
+int icu_clear_mask(int val)
+{
+    return sys_call(SYSCALL_ICU_WRITE,
+            ICU_MASK_CLEAR,
+            val,
+            0, 0);
+}
+/********************************************************************
+  icu_get_mask()
+  Read the Interrupt Enable Mask of the ICU component.
+ ********************************************************************/
+int icu_get_mask(int* buffer)
+{
+    return sys_call(SYSCALL_ICU_READ,
+            ICU_MASK,
+            (int)buffer,
+            0, 0);
+}
+/********************************************************************
+  icu_get_irqs()
+  Read the value of the 32 interrupt lines (IRQ inputs).
+ ********************************************************************/
+int icu_get_irqs(int* buffer)
+{
+    return sys_call(SYSCALL_ICU_READ,
+            ICU_INT,
+            (int)buffer,
+            0, 0);
+}
+/********************************************************************
+  icu_get_index()
+  Read the index of the highest priority active interrupt.
+  (If no active interrupt, -1 is returned).
+ ********************************************************************/
+int icu_get_index(int* buffer)
+{
+    return sys_call(SYSCALL_ICU_READ,
+            ICU_IT_VECTOR,
+            (int)buffer,
+            0, 0);
+}
+
+/********************************************************************
+  LOCKS
+ *********************************************************************
+ lock_acquire()
+ This system call performs a spin-lock acquisition.
+ It is dedicated to the SoCLib LOCKS peripheral.
+ In case of busy waiting, there is a random delay
+ of about 100 cycles between two successive lock read,
+ to avoid bus saturation.
+ ********************************************************************/
+int lock_acquire(int lock_index)
+{
+    return sys_call(SYSCALL_LOCKS_READ,
+            lock_index,
+            0, 0, 0);
+}
+
+/********************************************************************
+  lock_release()
+  You must use this system call to release a spin-lock,
+  as the LOCKS peripheral is in the kernel segment.
+ ********************************************************************/
+int lock_release(int lock_index)
+{
+    return sys_call(SYSCALL_LOCKS_WRITE,
+            lock_index,
+            0, 0, 0);
+}
+
+/********************************************************************
+  I/O BLOCK DEVICE
+ *********************************************************************
+ ioc_write()
+ Transfer data from a memory buffer to a file on the block_device.
+ - lba        : Logical Block Address (first block index)
+ - buffer     : base address of the memory buffer
+ - count      : number of blocks to be transfered
+ This function returns 0 if the transfert can be done.
+ It returns -1 if the buffer is not in user address space.
+ ********************************************************************/
+int ioc_write(size_t lba, void* buffer, size_t count)
+{
+    return sys_call(SYSCALL_IOC_WRITE,
+            lba,
+            (int)buffer,
+            count,
+            0);
+}
+/********************************************************************
+  ioc_read()
+  Transfer data from a file on the block_device to a memory buffer.
+  - lba        : Logical Block Address (first block index)
+  - buffer     : base address of the memory buffer
+  - count      : number of blocks to be transfered
+  This function returns 0 if the transfert can be done.
+  It returns -1 if the buffer is not in user address space.
+ ********************************************************************/
+int ioc_read(size_t lba, void* buffer, size_t count)
+{
+    return sys_call(SYSCALL_IOC_READ,
+            lba,
+            (int)buffer,
+            count,
+            0);
+}
+/********************************************************************
+  ioc_completed()
+  This blocking function returns 0 when the I/O transfer is
+  successfully completed, and returns -1 if an address error
+  has been detected.
+ ********************************************************************/
+int ioc_completed()
+{
+    return sys_call(SYSCALL_IOC_COMPLETED,
+            0, 0, 0, 0);
+}
+
+/********************************************************************
+  FRAME BUFFER
+ *********************************************************************
+ fb_sync_write()
+ This blocking function use a memory copy strategy to transfer data
+ from a user buffer to the frame buffer device in kernel space,
+ - offset     : offset (in bytes) in the frame buffer
+ - buffer     : base address of the memory buffer
+ - length     : number of bytes to be transfered
+ It returns 0 when the transfer is completed.
+ ********************************************************************/
+int fb_sync_write(size_t offset, void* buffer, size_t length)
+{
+    return sys_call(SYSCALL_FB_SYNC_WRITE,
+            offset,
+            (int)buffer,
+            length,
+            0);
+}
+/********************************************************************
+  fb_sync_read()
+  This blocking function use a memory copy strategy to transfer data
+  from the frame buffer device in kernel space to an user buffer.
+  - offset     : offset (in bytes) in the frame buffer
+  - buffer     : base address of the user buffer
+  - length     : number of bytes to be transfered
+  It returns 0 when the transfer is completed.
+ ********************************************************************/
+int fb_sync_read(size_t offset, void* buffer, size_t length)
+{
+    return sys_call(SYSCALL_FB_SYNC_READ,
+            offset,
+            (int)buffer,
+            length,
+            0);
+}
+/********************************************************************
+  fb_write()
+  This non-blocking function use the DMA coprocessor to transfer data
+  from a user buffer to the frame buffer device in kernel space,
+  - offset     : offset (in bytes) in the frame buffer
+  - buffer     : base address of the user buffer
+  - length     : number of bytes to be transfered
+  It returns 0 when the transfer can be started.
+  It returns -1 if the buffer is not in user address space.
+  The transfer completion is signaled by an IRQ, and must be
+  tested by the fb_completed() function.
+ ********************************************************************/
+int fb_write(size_t offset, void* buffer, size_t length)
+{
+    return sys_call(SYSCALL_FB_WRITE,
+            offset,
+            (int)buffer,
+            length,
+            0);
+}
+/********************************************************************
+  fb_read()
+  This non-blocking function use the DMA coprocessor to transfer data
+  from the frame buffer device in kernel space to an user buffer.
+  - offset     : offset (in bytes) in the frame buffer
+  - buffer     : base address of the memory buffer
+  - length     : number of bytes to be transfered
+  It returns 0 when the transfer can be started.
+  It returns -1 if the buffer is not in user address space.
+  The transfer completion is signaled by an IRQ, and must be
+  tested by the fb_completed() function.
+ ********************************************************************/
+int fb_read(size_t offset, void* buffer, size_t length)
+{
+    return sys_call(SYSCALL_FB_READ,
+            offset,
+            (int)buffer,
+            length,
+            0);
+}
+/********************************************************************
+  fb_completed()
+  This blocking function returns when the transfer is completed.
+  It returns 0 if the transfer is successful.
+  It returns -1 if an address error has been detected.
+ ********************************************************************/
+int fb_completed()
+{
+    return sys_call(SYSCALL_FB_COMPLETED,
+            0, 0, 0, 0);
+}
+
+/********************************************************************
+  SYNCHRONISATION BARRIERS
+ *********************************************************************
+  barrier_init()
+  This function initializes the counter for barrier[index].
+  - index     : index of the barrier (between 0 & 7)
+  - count     : number of tasks to be synchronized.
+  The GIET supports up to 8 independant barriers.
+  It returns a non zero value when the barrier index is larger than 7.
+* ********************************************************************/
+int barrier_init(size_t index, size_t count)
+{
+    return sys_call(SYSCALL_BARRIER_INIT,
+            (int)index,
+            (int)count,
+            0, 0);
+}
+/********************************************************************
+  barrier_wait()
+  This blocking function use a busy waiting policy, and returns only
+  when all synchonized asks have reached the barrier.
+  - index     : index of the barrier (between 0 & 7)
+  The GIET supports up to 8 independant barriers.
+  It returns a non zero value when the barrier index is larger than 7.
+ ********************************************************************/
+int barrier_wait(size_t index)
+{
+    return sys_call(SYSCALL_BARRIER_WAIT,
+            (int)index,
+            0, 0, 0);
+}
+// Local Variables:
+// tab-width: 4;
+// c-basic-offset: 4;
+// c-file-offsets:((innamespace . 0)(inline-open . 0));
+// indent-tabs-mode: nil;
+// End:
+//
+// vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4
+
Index: branches/v4/softs/giet_tsar/stdio.h
===================================================================
--- branches/v4/softs/giet_tsar/stdio.h	(revision 371)
+++ branches/v4/softs/giet_tsar/stdio.h	(revision 371)
@@ -0,0 +1,137 @@
+/*********************************************************************************
+    fichier stdio.h
+    Written Alain greiner & Nicolas Pouillon
+    Date : 15/09/2009
+ *********************************************************************************/
+
+#ifndef _STDIO_H_
+#define _STDIO_H_
+
+#define SYSCALL_PROCID          0x00
+#define SYSCALL_PROCTIME        0x01
+#define SYSCALL_TTY_WRITE       0x02
+#define SYSCALL_TTY_READ        0x03
+#define SYSCALL_TIMER_WRITE     0x04
+#define SYSCALL_TIMER_READ      0x05
+#define SYSCALL_GCD_WRITE       0x06
+#define SYSCALL_GCD_READ        0x07
+#define SYSCALL_ICU_WRITE       0x08
+#define SYSCALL_ICU_READ        0x09
+#define SYSCALL_TTY_READ_IRQ    0x0A
+#define SYSCALL_TTY_WRITE_IRQ   0x0B
+#define SYSCALL_LOCKS_WRITE     0x0C
+#define SYSCALL_LOCKS_READ      0x0D
+#define SYSCALL_EXIT            0x0E
+#define SYSCALL_PROCNUMBER      0x0F
+
+#define SYSCALL_FB_SYNC_WRITE   0x10
+#define SYSCALL_FB_SYNC_READ    0x11
+#define SYSCALL_FB_WRITE        0x12
+#define SYSCALL_FB_READ         0x13
+#define SYSCALL_FB_COMPLETED    0x14
+#define SYSCALL_IOC_WRITE       0x15
+#define SYSCALL_IOC_READ        0x16
+#define SYSCALL_IOC_COMPLETED   0x17
+#define SYSCALL_BARRIER_INIT	0x18
+#define SYSCALL_BARRIER_WAIT	0x19
+
+typedef unsigned int size_t;
+
+/****************************************************************
+  this is a generic C function to implement all system calls.
+  - The first argument is the system call index.
+  - The four next arguments are the system call arguments.
+  They will be written in registers $2, $4, $5, $6, $7.
+ ****************************************************************/
+int sys_call(int call_no,
+        int arg_o,
+        int arg_1,
+        int arg_2,
+        int arg_3);
+
+/****************************************************************
+  These functions access the MIPS protected registers
+ ****************************************************************/
+int procid();
+int proctime();
+int procnumber();
+int exit();
+int rand();
+
+/****************************************************************
+  These functions access the MULTI_TTY peripheral
+ ****************************************************************/
+int tty_puts(char* string);
+int tty_putc(char byte);
+int tty_putw(int word);
+int tty_getc(char* byte);
+int tty_getc_irq(char* byte);
+int tty_gets_irq(char* buf, int bufsize);
+int tty_getw_irq(int* word);
+int tty_printf(char* format,...);
+
+/****************************************************************
+  These functions access the MULTI_TIMER peripheral
+ ****************************************************************/
+int timer_set_mode(int timer_index, int mode);
+int timer_set_period(int timer_index, int period);
+int timer_reset_irq(int timer_index);
+int timer_get_time(int timer_index, int* time);
+
+/****************************************************************
+  These functions access the GCD peripheral
+ ****************************************************************/
+int gcd_set_opa(int val);
+int gcd_set_opb(int val);
+int gcd_start();
+int gcd_get_result(int* val);
+int gcd_get_status(int* val);
+
+/****************************************************************
+  These functions access the ICU peripheral
+ ****************************************************************/
+int icu_set_mask(int val);
+int icu_clear_mask(int val);
+int icu_get_mask(int* buffer);
+int icu_get_irqs(int* buffer);
+int icu_get_index(int* buffer);
+
+/****************************************************************
+  These functions access the LOCKS peripheral
+ ****************************************************************/
+int lock_acquire(int lock_index);
+int lock_release(int lock_index);
+
+/****************************************************************
+  These functions access the BLOCK_DEVICE peripheral
+ ****************************************************************/
+int ioc_read(size_t lba, void* buffer, size_t count);
+int ioc_write(size_t lba, void* buffer, size_t count);
+int ioc_completed();
+
+/****************************************************************
+  These functions access the FRAME_BUFFER peripheral
+ ****************************************************************/
+int fb_read(size_t offset, void* buffer, size_t length);
+int fb_write(size_t offset, void* buffer, size_t length);
+int fb_completed();
+int fb_sync_read(size_t offset, void* buffer, size_t length);
+int fb_sync_write(size_t offset, void* buffer, size_t length);
+
+/****************************************************************
+  These functions access the synchronization barriers
+ ****************************************************************/
+int barrier_init(size_t index, size_t count);
+int barrier_wait(size_t index);
+
+#endif
+
+// Local Variables:
+// tab-width: 4;
+// c-basic-offset: 4;
+// c-file-offsets:((innamespace . 0)(inline-open . 0));
+// indent-tabs-mode: nil;
+// End:
+//
+// vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4
+
Index: branches/v4/softs/giet_tsar/timer.h
===================================================================
--- branches/v4/softs/giet_tsar/timer.h	(revision 371)
+++ branches/v4/softs/giet_tsar/timer.h	(revision 371)
@@ -0,0 +1,23 @@
+#ifndef TIMER_REGS_H
+#define TIMER_REGS_H
+
+enum SoclibTimerRegisters {
+    TIMER_VALUE     =   0,
+    TIMER_MODE      =   1,
+    TIMER_PERIOD    =   2,
+    TIMER_RESETIRQ  =   3,
+    /**/
+    TIMER_SPAN      =   4,
+};
+
+#endif /* TIMER_REGS_H */
+
+// Local Variables:
+// tab-width: 4;
+// c-basic-offset: 4;
+// c-file-offsets:((innamespace . 0)(inline-open . 0));
+// indent-tabs-mode: nil;
+// End:
+//
+// vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4
+
Index: branches/v4/softs/giet_tsar/tty.h
===================================================================
--- branches/v4/softs/giet_tsar/tty.h	(revision 371)
+++ branches/v4/softs/giet_tsar/tty.h	(revision 371)
@@ -0,0 +1,23 @@
+#ifndef TTY_REGS_H
+#define TTY_REGS_H
+
+enum SoclibTtyRegisters {
+    TTY_WRITE   = 0,
+    TTY_STATUS  = 1,
+    TTY_READ    = 2,
+    TTY_CONFIG  = 3,
+    /**/
+    TTY_SPAN    = 4,
+};
+
+#endif
+
+// Local Variables:
+// tab-width: 4;
+// c-basic-offset: 4;
+// c-file-offsets:((innamespace . 0)(inline-open . 0));
+// indent-tabs-mode: nil;
+// End:
+//
+// vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4
+
Index: branches/v4/softs/soft_filter_giet/Makefile
===================================================================
--- branches/v4/softs/soft_filter_giet/Makefile	(revision 371)
+++ branches/v4/softs/soft_filter_giet/Makefile	(revision 371)
@@ -0,0 +1,47 @@
+
+LD = mipsel-unknown-elf-ld
+CC = mipsel-unknown-elf-gcc
+AS = mipsel-unknown-elf-as
+DU = mipsel-unknown-elf-objdump
+
+OBJS = reset.o \
+	giet.o \
+	isr.o \
+	drivers.o \
+	stdio.o \
+	main.o
+
+CFLAGS = -Wall -g -mno-gpopt -ffreestanding -fomit-frame-pointer -mips32 -ggdb
+
+GIET =	../giet_tsar
+
+bin.soft: $(OBJS) ldscript
+	$(LD) -o $@ -T ldscript $(OBJS)
+	$(DU) -D $@ > $@.txt
+
+reset.o: $(GIET)/reset.s
+	$(AS) -g -mips32 -o $@ $<
+	$(DU) -D $@ > $@.txt
+
+giet.o: $(GIET)/giet.s
+	$(AS) -g -mips32 -o $@ $<
+	$(DU) -D $@ > $@.txt
+
+isr.o: $(GIET)/isr.c
+	$(CC) $(CFLAGS) -c -o $@ $<
+	$(DU) -D $@ > $@.txt
+
+stdio.o: $(GIET)/stdio.c
+	$(CC) $(CFLAGS) -c -o $@ $<
+	$(DU) -D $@ > $@.txt
+
+drivers.o: $(GIET)/drivers.c
+	$(CC) $(CFLAGS) -c -o $@ $<
+	$(DU) -D $@ > $@.txt
+
+main.o: main.c
+	$(CC) $(CFLAGS) -I$(GIET) -c -o $@ $<
+	$(DU) -D $@ > $@.txt
+
+clean:
+	rm -f *.o bin.soft *.txt core *~ proc* term* temp
Index: branches/v4/softs/soft_filter_giet/ldscript
===================================================================
--- branches/v4/softs/soft_filter_giet/ldscript	(revision 371)
+++ branches/v4/softs/soft_filter_giet/ldscript	(revision 371)
@@ -0,0 +1,90 @@
+/**********************************************************
+	File : ldscript 
+	Author : Alain Greiner
+	Date : March 2011  
+**********************************************************/
+
+/* definition of various hardware parameters.
+These variables are referenced in the drivers.c file,
+and must be defined, even if the corresponding
+peripherals are not present in the architecture */
+
+NB_CLUSTERS = 4;		/* number of clusters */
+NB_PROCS    = 4;		/* number of processors per cluster */
+NB_TASKS    = 1;		/* number of tasks per processor */
+NB_TIMERS   = 1;		/* max number of timers per processor */
+NB_LOCKS    = 8;		/* number of spin_locks */
+
+/* definition of the base address for all segments 
+The peripherals base addresses are referenced by the
+software drivers and must be defined, even if the 
+peripherals are not present in the architecture */
+
+seg_code_base   = 0x00000000;       /* le code utilisateur */ 
+seg_data_base   = 0x00100000;       /* les données utilisateur */
+
+seg_heap_base   = 0x00300000;       /* le tas utilisateur */
+seg_stack_base  = 0x00800000;       /* la pile utilisateur */
+
+seg_kcode_base  = 0x80000000;       /* le code du système */
+seg_kdata_base  = 0x80100000;       /* les donnees du système */
+seg_kunc_base   = 0x80200000;       /* les données non cachées du système */
+
+seg_icu_base    = 0x00F00000;       /* controleur ICU */
+seg_tty_base    = 0xBFF20000;       /* controleur TTY */
+seg_dma_base    = 0x00F30000;       /* controleur DMA */
+
+seg_reset_base  = 0xBFC00000;       /* le code de boot */
+seg_fb_base     = 0xBFD00000;       /* controleur FRAME BUFFER */
+seg_ioc_base    = 0xBFF10000;       /* controleur I/O */
+
+seg_timer_base  = 0x00F0000;       /* controleur TIMER */
+seg_gcd_base    = 0xBFF50000;       /* controleur GCD */
+
+/* Grouping sections into segments */
+
+SECTIONS
+{
+   . = seg_kcode_base;
+   seg_kcode : {
+      *(.giet)
+      *(.switch)
+      *(.drivers)
+      *(.isr)
+   } 
+   . = seg_kdata_base;
+   seg_kdata : {
+      *(.kdata)
+   } 
+   . = seg_kunc_base;
+   seg_kunc : {
+      *(.unckdata)
+   } 
+   . = seg_kdata_base;
+   seg_kdata : {
+      *(.ksave)
+   } 
+   . = seg_code_base;
+   seg_code : {
+      *(.text)
+   } 
+   . = seg_reset_base;
+   seg_reset : {
+      *(.reset)
+   } 
+   . = seg_data_base;
+   seg_data : {
+      *(.rodata)
+      . = ALIGN(4);
+      *(.rodata.*)
+      . = ALIGN(4);
+      *(.data)
+      . = ALIGN(4);
+      *(.sdata)
+      . = ALIGN(4);
+      *(.bss)
+      *(COMMON)
+      *(.sbss)
+   } 
+}
+
Index: branches/v4/softs/soft_filter_giet/main.c
===================================================================
--- branches/v4/softs/soft_filter_giet/main.c	(revision 371)
+++ branches/v4/softs/soft_filter_giet/main.c	(revision 371)
@@ -0,0 +1,631 @@
+
+#include "limits.h"
+#include "stdio.h"
+
+#include "../giet_tsar/block_device.h"
+
+////////////////////////////////////
+// Image parameters
+
+#define NB_CLUSTER_MAX 256
+#define PIXEL_SIZE     2
+#define NL             1024
+#define NP             1024
+
+#define NB_PIXELS      ((NP) * (NL))
+#define FRAME_SIZE     ((NB_PIXELS) * (PIXEL_SIZE))
+
+#define PRINTF(...)      ({ if (proc_id == 0) { tty_printf(__VA_ARGS__); } })
+
+#define TA(c,l,p)  (A[c][((NP) * (l)) + (p)])
+#define TB(c,p,l)  (B[c][((NL) * (p)) + (l)])
+#define TC(c,l,p)  (C[c][((NP) * (l)) + (p)])
+#define TD(c,l,p)  (D[c][((NP) * (l)) + (p)])
+#define TZ(c,l,p)  (Z[c][((NP) * (l)) + (p)])
+
+#define max(x,y) ((x) > (y) ? (x) : (y))
+#define min(x,y) ((x) < (y) ? (x) : (y))
+
+///////////////////////////////////////////
+// tricks to read parameters from ldscript
+///////////////////////////////////////////
+
+struct plaf;
+
+extern struct plouf seg_ioc_base;
+extern struct plaf seg_heap_base;
+extern struct plaf NB_PROCS;
+extern struct plaf NB_CLUSTERS;
+
+
+// Required when initializing an array all at once
+static void *memcpy(void *_dst, const void *_src, unsigned int size){
+   unsigned int *dst = _dst;
+   const unsigned int *src = _src;
+   if (! ((unsigned int)dst & 3) && ! ((unsigned int)src & 3)){
+      while (size > 3){
+         *dst++ = *src++;
+         size -= 4;
+      }
+   }
+
+   unsigned char *cdst = (unsigned char*)dst;
+   unsigned char *csrc = (unsigned char*)src;
+
+   while (size--){
+      *cdst++ = *csrc++;
+   }
+   return _dst;
+}
+
+
+
+
+
+
+
+
+void main(){
+
+   //////////////////////////////////
+   // convolution kernel parameters
+   // The content of this section is
+   // Philips proprietary information.
+   ///////////////////////////////////
+
+   int   vnorm  = 115;
+   int   vf[35] = { 1, 1, 2, 2, 2,
+                    2, 3, 3, 3, 4,
+                    4, 4, 4, 5, 5,
+                    5, 5, 5, 5, 5,
+                    5, 5, 4, 4, 4,
+                    4, 3, 3, 3, 2,
+                    2, 2, 2, 1, 1 };
+
+   int hrange = 100;
+   int hnorm  = 201;
+
+   unsigned int date = 0;
+
+   int c; // cluster index for loops
+   int l; // line index for loops
+   int p; // pixel index for loops
+   int x; // filter index for loops
+
+   const unsigned int proc_id       = procid();                      // processor id
+   const unsigned int nlocal_procs  = (int) &NB_PROCS;               // number of processors per cluster
+   const unsigned int nclusters     = (int) &NB_CLUSTERS;            // number of clusters
+   const unsigned int local_id      = proc_id % nlocal_procs;        // local task id
+   const unsigned int cluster_id    = proc_id / nlocal_procs;        // cluster task id
+   const unsigned int base          = (unsigned int) &seg_heap_base; // base address for shared buffers
+   const unsigned int increment     = 0x80000000 / nclusters * 2;    // cluster increment
+   const unsigned int nglobal_procs = nclusters * nlocal_procs;      // number of tasks
+   const unsigned int npixels       = NB_PIXELS;                     // Number of pixel per frame
+   const unsigned int frame_size    = FRAME_SIZE;                    // Size of 1 frame (in bytes)
+   const unsigned int * ioc_address = (unsigned int *) &seg_ioc_base;
+   const unsigned int block_size    = ioc_address[BLOCK_DEVICE_BLOCK_SIZE];
+   const unsigned int nblocks       = frame_size / block_size;       // number of blocks per frame
+
+   const unsigned int lines_per_task     = NL / nglobal_procs; // number of lines per task
+   const unsigned int lines_per_cluster  = NL / nclusters;     // number of lines per cluster
+   const unsigned int pixels_per_task    = NP / nglobal_procs; // number of columns per task
+   const unsigned int pixels_per_cluster = NP / nclusters;     // number of columns per cluster
+
+   int first, last;
+
+   PRINTF("\n*** Processor %d entering main at cycle %d ***\n\n", proc_id, proctime());
+
+
+   /////////////////////////
+   // parameters checking //
+   /////////////////////////
+   
+
+   if ((nlocal_procs != 1) && (nlocal_procs != 2) && (nlocal_procs != 4)){
+      PRINTF("NB_PROCS must be 1, 2 or 4\n");
+      exit();
+   }
+
+   ////////////////////////////////////////////////////////////////////////
+   // Warning: NB_CLUSTERS must be at least 4 because of the heap size;  //
+   //          if there are less clusters, the heap mixes with the stack //
+   //          (the total heap size must be at least 0x01000000)         //
+   ////////////////////////////////////////////////////////////////////////
+   if ((nclusters !=  4) && (nclusters !=  8) && (nclusters != 16) && 
+         (nclusters != 32) && (nclusters != 64) && (nclusters !=128) && (nclusters != 256)){
+      PRINTF("NB_CLUSTERS must be a power of 2 between 4 and 256\n");
+      exit();
+   }
+
+   if (proc_id >= nglobal_procs){
+      PRINTF("processor id %d larger than NB_CLUSTERS*NB_PROCS\n", proc_id);
+      exit();
+   }
+
+   if (NL % nclusters != 0){
+      PRINTF("NB_CLUSTERS must be a divider of NL");
+      exit();
+   }
+
+   if (NP % nclusters != 0){
+      PRINTF("NB_CLUSTERS must be a divider of NP");
+      exit();
+   }
+
+
+   // Arrays of pointers on the shared, distributed buffers  
+   // containing the images (sized for the worst case : 256 clusters)
+   unsigned short * A[NB_CLUSTER_MAX];
+   int *            B[NB_CLUSTER_MAX];
+   int *            C[NB_CLUSTER_MAX];
+   int *            D[NB_CLUSTER_MAX];
+   unsigned char *  Z[NB_CLUSTER_MAX];
+
+   // Arrays of pointers on the instrumentation arrays
+   // These arrays are indexed by the cluster index (sized for the worst case : 256 clusters)
+   // each pointer points on the base adress of an array of 4 (NPROCS max) unsigned int
+   unsigned int * LOAD_START[NB_CLUSTER_MAX];
+   unsigned int * LOAD_END[NB_CLUSTER_MAX];
+   unsigned int * VERT_START[NB_CLUSTER_MAX];
+   unsigned int * VERT_END[NB_CLUSTER_MAX];
+   unsigned int * HORI_START[NB_CLUSTER_MAX];
+   unsigned int * HORI_END[NB_CLUSTER_MAX];
+   unsigned int * DISP_START[NB_CLUSTER_MAX];
+   unsigned int * DISP_END[NB_CLUSTER_MAX];
+
+   // The shared, distributed buffers addresses are computed
+   // from the seg_heap_base value defined in the ldscript file
+   // and from the cluster increment = 4Gbytes/nclusters.
+   // These arrays of pointers are identical and
+   // replicated in the stack of each task 
+   for (c = 0; c < nclusters; c++){
+      unsigned int offset = base + increment * c;
+      A[c] = (unsigned short *) (offset);
+      B[c] = (int *)            (offset + frame_size * 1 / nclusters); // We increment by 2 * frame_size
+      C[c] = (int *)            (offset + frame_size * 3 / nclusters); // because sizeof(int) = 2*sizeof(short)
+      D[c] = (int *)            (offset + frame_size * 5 / nclusters); // so an array of frame_size elements of type
+      Z[c] = (unsigned char *)  (offset + frame_size * 7 / nclusters); // int can contain the equivalent of 2 frames
+
+      offset = base + increment * c + frame_size * 8 / nclusters;
+      LOAD_START[c] = (unsigned int *) (offset + nlocal_procs * sizeof(unsigned int) * 0);
+      LOAD_END[c]   = (unsigned int *) (offset + nlocal_procs * sizeof(unsigned int) * 1);
+      VERT_START[c] = (unsigned int *) (offset + nlocal_procs * sizeof(unsigned int) * 2);
+      VERT_END[c]   = (unsigned int *) (offset + nlocal_procs * sizeof(unsigned int) * 3);
+      HORI_START[c] = (unsigned int *) (offset + nlocal_procs * sizeof(unsigned int) * 4);
+      HORI_END[c]   = (unsigned int *) (offset + nlocal_procs * sizeof(unsigned int) * 5);
+      DISP_START[c] = (unsigned int *) (offset + nlocal_procs * sizeof(unsigned int) * 6);
+      DISP_END[c]   = (unsigned int *) (offset + nlocal_procs * sizeof(unsigned int) * 7);
+   }
+
+   PRINTF("NB_CLUSTERS     = %d\n", nclusters); 
+   PRINTF("NB_LOCAL_PROCS  = %d\n", nlocal_procs); 
+   PRINTF("NB_GLOBAL_PROCS = %d\n", nglobal_procs);
+   PRINTF("NB_PIXELS       = %d\n", npixels);
+   PRINTF("PIXEL_SIZE      = %d\n", PIXEL_SIZE);
+   PRINTF("FRAME_SIZE      = %d\n", frame_size);
+   PRINTF("BLOCK_SIZE      = %d\n", block_size);
+   PRINTF("NB_BLOCKS       = %d\n\n", nblocks);
+
+
+   PRINTF("*** Starting barrier init at cycle %d ***\n", proctime());
+
+   //  barriers initialization
+   barrier_init(0, nglobal_procs);
+   barrier_init(1, nglobal_procs);
+   barrier_init(2, nglobal_procs);
+   barrier_init(3, nglobal_procs);
+
+   PRINTF("*** Completing barrier init at cycle %d ***\n", proctime());
+
+
+   ////////////////////////////////////////////////////////
+   // pseudo parallel load from disk to A[c] buffers
+   // only task running on processor with (local_id==0) does it
+   // nblocks/nclusters are loaded in each cluster
+   ////////////////////////////////////////////////////////
+
+   if (local_id == 0){
+      int p;
+      date  = proctime();
+      PRINTF("\n*** Starting load at cycle %d\n", date);
+      for (p = 0; p < nlocal_procs; p++){
+         LOAD_START[cluster_id][p] = date;
+      }
+
+      if (ioc_read(nblocks*cluster_id/nclusters, A[cluster_id], nblocks/nclusters)){
+         PRINTF("echec ioc_read\n");
+         exit(1);
+      }
+      if (ioc_completed()){
+         PRINTF("echec ioc_completed\n");
+         exit(1);
+      }
+
+      date  = proctime();
+      PRINTF("*** Completing load at cycle %d\n", date);
+      for (p = 0; p < nlocal_procs; p++){
+         LOAD_END[cluster_id][p] = date;
+      }
+   }
+
+   barrier_wait(0);
+
+
+   ////////////////////////////////////////////////////////
+   // parallel horizontal filter : 
+   // B <= transpose(FH(A))
+   // D <= A - FH(A)
+   // Each task computes (NL/nglobal_procs) lines 
+   // The image must be extended :
+   // if (z<0)    TA(cluster_id,l,z) == TA(cluster_id,l,0)
+   // if (z>NP-1) TA(cluster_id,l,z) == TA(cluster_id,l,NP-1)
+   ////////////////////////////////////////////////////////
+
+   date  = proctime();
+   PRINTF("\n*** Starting horizontal filter at cycle %d\n", date);
+   HORI_START[cluster_id][local_id] = date;
+
+   // l = absolute line index / p = absolute pixel index  
+   // first & last define which lines are handled by a given task(cluster_id,local_id)
+
+   first = (cluster_id * nlocal_procs + local_id) * lines_per_task;
+   last  = first + lines_per_task;
+
+   for (l = first; l < last; l++){
+      // src_c and src_l are the cluster index and the line index for A & D
+      int src_c = l / lines_per_cluster;
+      int src_l = l % lines_per_cluster;
+
+      // We use the specific values of the horizontal ep-filter for optimisation:
+      // sum(p) = sum(p-1) + TA[p+hrange] - TA[p-hrange-1]
+      // To minimize the number of tests, the loop on pixels is split in three domains 
+
+      int sum_p = (hrange + 2) * TA(src_c, src_l, 0);
+      for (x = 1; x < hrange; x++){
+         sum_p = sum_p + TA(src_c, src_l, x);
+      }
+
+      // first domain : from 0 to hrange
+      for (p = 0; p < hrange + 1; p++){
+         // dst_c and dst_p are the cluster index and the pixel index for B
+         int dst_c = p / pixels_per_cluster;
+         int dst_p = p % pixels_per_cluster;
+         sum_p = sum_p + (int) TA(src_c, src_l, p + hrange) - (int) TA(src_c, src_l, 0);
+         TB(dst_c, dst_p, l) = sum_p / hnorm;
+         TD(src_c, src_l, p) = (int) TA(src_c, src_l, p) - sum_p / hnorm;
+      }
+      // second domain : from (hrange+1) to (NP-hrange-1)
+      for (p = hrange + 1; p < NP - hrange; p++){
+         // dst_c and dst_p are the cluster index and the pixel index for B
+         int dst_c = p / pixels_per_cluster;
+         int dst_p = p % pixels_per_cluster;
+         sum_p = sum_p + (int) TA(src_c, src_l, p + hrange) - (int) TA(src_c, src_l, p - hrange - 1);
+         TB(dst_c, dst_p, l) = sum_p / hnorm;
+         TD(src_c, src_l, p) = (int) TA(src_c, src_l, p) - sum_p / hnorm;
+      }
+      // third domain : from (NP-hrange) to (NP-1)
+      for (p = NP - hrange; p < NP; p++){
+         // dst_c and dst_p are the cluster index and the pixel index for B
+         int dst_c = p / pixels_per_cluster;
+         int dst_p = p % pixels_per_cluster;
+         sum_p = sum_p + (int) TA(src_c, src_l, NP - 1) - (int) TA(src_c, src_l, p - hrange - 1);
+         TB(dst_c, dst_p, l) = sum_p / hnorm;
+         TD(src_c, src_l, p) = (int) TA(src_c, src_l, p) - sum_p / hnorm;
+      }
+
+      PRINTF(" - line %d computed at cycle %d\n", l, proctime());
+   }
+
+   date  = proctime();
+   PRINTF("*** Completing horizontal filter at cycle %d\n", date);
+   HORI_END[cluster_id][local_id] = date;
+
+   barrier_wait(1);
+
+
+   //////////////////////////////////////////////////////////
+   // parallel vertical filter : 
+   // C <= transpose(FV(B))
+   // Each task computes (NP/nglobal_procs) columns
+   // The image must be extended :
+   // if (l<0)    TB(cluster_id,p,x) == TB(cluster_id,p,0)
+   // if (l>NL-1)   TB(cluster_id,p,x) == TB(cluster_id,p,NL-1)
+   //////////////////////////////////////////////////////////
+
+   date  = proctime();
+   PRINTF("\n*** starting vertical filter at cycle %d\n", date);
+   VERT_START[cluster_id][local_id] = date;
+
+   // l = absolute line index / p = absolute pixel index
+   // first & last define which pixels are handled by a given task(cluster_id,local_id)
+
+   first = (cluster_id * nlocal_procs + local_id) * pixels_per_task;
+   last  = first + pixels_per_task;
+
+   for (p = first; p < last; p++){
+      // src_c and src_p are the cluster index and the pixel index for B
+      int src_c = p / pixels_per_cluster;
+      int src_p = p % pixels_per_cluster;
+
+      int sum_l;
+
+      // We use the specific values of the vertical ep-filter
+      // To minimize the number of tests, the NL lines are split in three domains 
+
+      // first domain : explicit computation for the first 18 values
+      for (l = 0; l < 18; l++){
+         // dst_c and dst_l are the cluster index and the line index for C
+         int dst_c = l / lines_per_cluster;
+         int dst_l = l % lines_per_cluster;
+
+         for (x = 0, sum_l = 0; x < 35; x++){
+            sum_l = sum_l + vf[x] * TB(src_c, src_p, max(l - 17 + x,0) );
+         }
+         TC(dst_c, dst_l, p) = sum_l / vnorm;
+      }
+      // second domain
+      for (l = 18; l < NL - 17; l++){
+         // dst_c and dst_l are the cluster index and the line index for C
+         int dst_c = l / lines_per_cluster;
+         int dst_l = l % lines_per_cluster;
+
+         sum_l = sum_l + TB(src_c, src_p, l + 4)
+            + TB(src_c, src_p, l + 8)
+            + TB(src_c, src_p, l + 11)
+            + TB(src_c, src_p, l + 15)
+            + TB(src_c, src_p, l + 17)
+            - TB(src_c, src_p, l - 5)
+            - TB(src_c, src_p, l - 9)
+            - TB(src_c, src_p, l - 12)
+            - TB(src_c, src_p, l - 16)
+            - TB(src_c, src_p, l - 18);
+         TC(dst_c, dst_l, p) = sum_l / vnorm;
+      }
+      // third domain
+      for (l = NL - 17; l < NL; l++){
+         // dst_c and dst_l are the cluster index and the line index for C
+         int dst_c = l / lines_per_cluster;
+         int dst_l = l % lines_per_cluster;
+
+         sum_l = sum_l + TB(src_c, src_p, min(l + 4, NL - 1))
+            + TB(src_c, src_p, min(l + 8, NL - 1))
+            + TB(src_c, src_p, min(l + 11, NL - 1))
+            + TB(src_c, src_p, min(l + 15, NL - 1))
+            + TB(src_c, src_p, min(l + 17, NL - 1))
+            - TB(src_c, src_p, l - 5)
+            - TB(src_c, src_p, l - 9)
+            - TB(src_c, src_p, l - 12)
+            - TB(src_c, src_p, l - 16)
+            - TB(src_c, src_p, l - 18);
+         TC(dst_c, dst_l, p) = sum_l / vnorm;
+      }
+      PRINTF(" - column %d computed at cycle %d\n", p, proctime());
+   }
+
+   date  = proctime();
+   PRINTF("*** Completing vertical filter at cycle %d\n", date);
+   VERT_END[cluster_id][local_id] = date;
+
+   barrier_wait(2);
+
+
+   ////////////////////////////////////////////////////////////////
+   // final computation and parallel display 
+   // Z <= D + C
+   // Each processor use its private DMA channel to display 
+   // the resulting image, line  per line (one byte per pixel).
+   // Eah processor computes & displays (NL/nglobal_procs) lines. 
+   ////////////////////////////////////////////////////////////////
+
+   date  = proctime();
+   PRINTF("\n*** Starting display at cycle %d\n", date);
+   DISP_START[cluster_id][local_id] = date;
+
+   first = local_id * lines_per_task;
+   last  = first + lines_per_task;
+
+   for (l = first; l < last; l++){
+      for (p = 0; p < NP; p++){
+         TZ(cluster_id,l,p) = (unsigned char) (((TD(cluster_id,l,p) + TC(cluster_id,l,p)) >> 8) & 0xFF);
+      }
+      fb_write(NP * (cluster_id * lines_per_cluster + l), &TZ(cluster_id,l,0), NP);
+   }
+
+   date  = proctime();
+   PRINTF("*** Completing display at cycle %d\n", date);
+   DISP_END[cluster_id][local_id] = date;
+
+   barrier_wait(3);
+
+   
+   /////////////////////////////////////////////////////////
+   // Instrumentation (done by processor 0 in cluster 0)   
+   /////////////////////////////////////////////////////////
+
+   if (proc_id == 0){
+      date  = proctime();
+      PRINTF("\n*** Starting Instrumentation at cycle %d\n\n", date);
+
+      int cc, pp;
+      unsigned int min_load_start = INT_MAX;
+      unsigned int max_load_start = 0;
+      unsigned int min_load_ended = INT_MAX;
+      unsigned int max_load_ended = 0;
+
+      unsigned int min_hori_start = INT_MAX;
+      unsigned int max_hori_start = 0;
+      unsigned int min_hori_ended = INT_MAX;
+      unsigned int max_hori_ended = 0;
+
+      unsigned int min_vert_start = INT_MAX;
+      unsigned int max_vert_start = 0;
+      unsigned int min_vert_ended = INT_MAX;
+      unsigned int max_vert_ended = 0;
+
+      unsigned int min_disp_start = INT_MAX;
+      unsigned int max_disp_start = 0;
+      unsigned int min_disp_ended = INT_MAX;
+      unsigned int max_disp_ended = 0;
+
+      for (cc = 0; cc < nclusters; cc++){
+         for (pp = 0; pp < nlocal_procs; pp++ ){
+            if (LOAD_START[cc][pp] < min_load_start){
+               min_load_start = LOAD_START[cc][pp];
+            }
+            if (LOAD_START[cc][pp] > max_load_start){
+               max_load_start = LOAD_START[cc][pp];
+            }
+            if (LOAD_END[cc][pp] < min_load_ended){
+               min_load_ended = LOAD_END[cc][pp];
+            }
+            if (LOAD_END[cc][pp] > max_load_ended){
+               max_load_ended = LOAD_END[cc][pp];
+            }
+
+            if (HORI_START[cc][pp] < min_hori_start){
+               min_hori_start = HORI_START[cc][pp];
+            }
+            if (HORI_START[cc][pp] > max_hori_start){
+               max_hori_start = HORI_START[cc][pp];
+            }
+            if (HORI_END[cc][pp] < min_hori_ended){
+               min_hori_ended = HORI_END[cc][pp];
+            }
+            if (HORI_END[cc][pp] > max_hori_ended){
+               max_hori_ended = HORI_END[cc][pp];
+            }
+
+            if (VERT_START[cc][pp] < min_vert_start){
+               min_vert_start = VERT_START[cc][pp];
+            }
+            if (VERT_START[cc][pp] > max_vert_start){
+               max_vert_start = VERT_START[cc][pp];
+            }
+            if (VERT_END[cc][pp] < min_vert_ended){
+               min_vert_ended = VERT_END[cc][pp];
+            }
+            if (VERT_END[cc][pp] > max_vert_ended){
+               max_vert_ended = VERT_END[cc][pp];
+            }
+
+            if (DISP_START[cc][pp] < min_disp_start){
+               min_disp_start = DISP_START[cc][pp];
+            }
+            if (DISP_START[cc][pp] > max_disp_start){
+               max_disp_start = DISP_START[cc][pp];
+            }
+            if (DISP_END[cc][pp] < min_disp_ended){
+               min_disp_ended = DISP_END[cc][pp];
+            }
+            if (DISP_END[cc][pp] > max_disp_ended){
+               max_disp_ended = DISP_END[cc][pp];
+            }
+         }
+      }
+      PRINTF(" - LOAD_START : min = %d / max = %d / med = %d / delta = %d\n",
+            min_load_start, max_load_start, (min_load_start+max_load_start) / 2, max_load_start-min_load_start);
+      PRINTF(" - LOAD_END   : min = %d / max = %d / med = %d / delta = %d\n",
+            min_load_ended, max_load_ended, (min_load_ended+max_load_ended) / 2, max_load_ended-min_load_ended);
+
+      PRINTF(" - HORI_START : min = %d / max = %d / med = %d / delta = %d\n",
+            min_hori_start, max_hori_start, (min_hori_start+max_hori_start) / 2, max_hori_start-min_hori_start);
+      PRINTF(" - HORI_END   : min = %d / max = %d / med = %d / delta = %d\n",
+            min_hori_ended, max_hori_ended, (min_hori_ended+max_hori_ended) / 2, max_hori_ended-min_hori_ended);
+
+      PRINTF(" - VERT_START : min = %d / max = %d / med = %d / delta = %d\n",
+            min_vert_start, max_vert_start, (min_vert_start+max_vert_start) / 2, max_vert_start-min_vert_start);
+      PRINTF(" - VERT_END   : min = %d / max = %d / med = %d / delta = %d\n",
+            min_vert_ended, max_vert_ended, (min_vert_ended+max_vert_ended) / 2, max_vert_ended-min_vert_ended);
+
+      PRINTF(" - DISP_START : min = %d / max = %d / med = %d / delta = %d\n",
+            min_disp_start, max_disp_start, (min_disp_start+max_disp_start) / 2, max_disp_start-min_disp_start);
+      PRINTF(" - DISP_END   : min = %d / max = %d / med = %d / delta = %d\n",
+            min_disp_ended, max_disp_ended, (min_disp_ended+max_disp_ended) / 2, max_disp_ended-min_disp_ended);
+
+      PRINTF(" - BARRIER LOAD/HORI = %d\n", min_hori_start - max_load_ended);
+      PRINTF(" - BARRIER HORI/VERT = %d\n", min_vert_start - max_hori_ended);
+      PRINTF(" - BARRIER VERT/DISP = %d\n", min_disp_start - max_vert_ended);
+
+      PRINTF(" - LOAD              = %d\n", max_load_ended);
+      PRINTF(" - FILTER            = %d\n", max_vert_ended - max_load_ended);
+      PRINTF(" - DISPLAY           = %d\n", max_disp_ended - max_vert_ended);
+
+      PRINTF("\nBEGIN LOAD_START\n");
+      for (cc = 0; cc < nclusters; cc++){
+         for (pp = 0; pp < nlocal_procs; pp++){
+            PRINTF("cluster= %d proc= %d date= %d\n", cc, pp, LOAD_START[cc][pp]);  
+         }
+      }
+      PRINTF("END\n");
+
+      PRINTF("\nBEGIN LOAD_END\n");
+      for (cc = 0; cc < nclusters; cc++){
+         for (pp = 0; pp < nlocal_procs; pp++){
+            PRINTF("cluster= %d proc= %d date= %d\n", cc, pp, LOAD_END[cc][pp]);  
+         }
+      }
+      PRINTF("END\n");
+
+      PRINTF("\nBEGIN HORI_START\n");
+      for (cc = 0; cc < nclusters; cc++){
+         for (pp = 0; pp < nlocal_procs; pp++){
+            PRINTF("cluster= %d proc= %d date= %d\n", cc, pp, HORI_START[cc][pp]);  
+         }
+      }
+      PRINTF("END\n");
+
+      PRINTF("\nBEGIN HORI_END\n");
+      for (cc = 0; cc < nclusters; cc++){
+         for (pp = 0; pp < nlocal_procs; pp++){
+            PRINTF("cluster= %d proc= %d date= %d\n", cc, pp, HORI_END[cc][pp]);  
+         }
+      }
+      PRINTF("END\n");
+
+      PRINTF("\nBEGIN VERT_START\n");
+      for (cc = 0; cc < nclusters; cc++){
+         for (pp = 0; pp < nlocal_procs; pp++){
+            PRINTF("cluster= %d proc= %d date= %d\n", cc, pp, VERT_START[cc][pp]);  
+         }
+      }
+      PRINTF("END\n");
+
+      PRINTF("\nBEGIN VERT_END\n");
+      for (cc = 0; cc < nclusters; cc++){
+         for (pp = 0; pp < nlocal_procs; pp++ ){
+            PRINTF("cluster= %d proc= %d date= %d\n", cc, pp, VERT_END[cc][pp]);  
+         }
+      }
+      PRINTF("END\n");
+
+      PRINTF("\nBEGIN DISP_START\n");
+      for (cc = 0; cc < nclusters; cc++){
+         for (pp = 0; pp < nlocal_procs; pp++){
+            PRINTF("cluster= %d proc= %d date= %d\n", cc, pp, DISP_START[cc][pp]);  
+         }
+      }
+      PRINTF("END\n");
+
+      PRINTF("\nBEGIN DISP_END\n");
+      for (cc = 0; cc < nclusters; cc++){
+         for (pp = 0; pp < nlocal_procs; pp++){
+            PRINTF("cluster= %d proc= %d date= %d\n", cc, pp, DISP_END[cc][pp]);  
+         }
+      }
+      PRINTF("END\n");
+   }
+
+   while(1);
+
+} // end main()
+
+// Local Variables:
+// tab-width: 3
+// c-basic-offset: 3
+// c-file-offsets:((innamespace . 0)(inline-open . 0))
+// indent-tabs-mode: nil
+// End:
+
+// vim: filetype=cpp:expandtab:shiftwidth=3:tabstop=3:softtabstop=3
+
+
Index: branches/v4/softs/soft_transpose_giet/Makefile
===================================================================
--- branches/v4/softs/soft_transpose_giet/Makefile	(revision 371)
+++ branches/v4/softs/soft_transpose_giet/Makefile	(revision 371)
@@ -0,0 +1,46 @@
+LD = mipsel-unknown-elf-ld
+CC = mipsel-unknown-elf-gcc
+AS = mipsel-unknown-elf-as
+DU = mipsel-unknown-elf-objdump
+
+OBJS =   reset.o \
+	giet.o \
+	isr.o \
+	drivers.o \
+	stdio.o \
+	main.o
+
+CFLAGS = -Wall -mno-gpopt -ffreestanding -fomit-frame-pointer -mips32 -ggdb
+
+GIET =	../giet_tsar
+
+bin.soft: $(OBJS) ldscript
+	$(LD) -o $@ -T ldscript $(OBJS)
+	$(DU) -D $@ > $@.txt
+
+reset.o: $(GIET)/reset.s
+	$(AS) -g -mips32 -o $@ $<
+	$(DU) -D $@ > $@.txt
+
+giet.o: $(GIET)/giet.s
+	$(AS) -g -mips32 -o $@ $<
+	$(DU) -D $@ > $@.txt
+
+isr.o: $(GIET)/isr.c
+	$(CC) $(CFLAGS) -c -o $@ $<
+	$(DU) -D $@ > $@.txt
+
+stdio.o: $(GIET)/stdio.c
+	$(CC) $(CFLAGS) -c -o $@ $<
+	$(DU) -D $@ > $@.txt
+
+drivers.o: $(GIET)/drivers.c
+	$(CC) $(CFLAGS) -c -o $@ $<
+	$(DU) -D $@ > $@.txt
+
+main.o: main.c
+	$(CC) $(CFLAGS) -I$(GIET) -c -o $@ $<
+	$(DU) -D $@ > $@.txt
+
+clean:
+	rm -f *.o bin.soft *.txt core *~ proc* term* temp
Index: branches/v4/softs/soft_transpose_giet/bridge256.raw
===================================================================
--- branches/v4/softs/soft_transpose_giet/bridge256.raw	(revision 371)
+++ branches/v4/softs/soft_transpose_giet/bridge256.raw	(revision 371)
@@ -0,0 +1,869 @@
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+|©p·[ Ž»§¥³ £¯Š€¥°¢£€² {siRhws}}ºfy¬
+€¡œÁ«ª¡Š|hox mpy|unh}liOTWR`
+e`lX~vwgu
+zn{~Q{yk[}xÀl|nfpÃäåâãâ°ØåçÝÞªÒ¶²
+
+¢©²Å·xÇÅÔ±Âž£®°²Žµ§©§Ì¹âËÆÈÆŸ±­»š®œ««€§ª¢©ª|nwyiu`YUU_nnv]©~£r§[t·ÊÅÂ²º¯°£ŒÊÄ°³¹Ÿ²«kziq\_S^Musk€uVon@6JI,0FEg:erafXA
+k±«°Šu]Lp
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+Àªµ£žŠÃ¡º¿ÁÏ©ÕœáÈÖÓÁžž¬ÉšÀ²®°±¢¶­€«es`tYKUln
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Index: branches/v4/softs/soft_transpose_giet/couple_512.raw
===================================================================
--- branches/v4/softs/soft_transpose_giet/couple_512.raw	(revision 371)
+++ branches/v4/softs/soft_transpose_giet/couple_512.raw	(revision 371)
@@ -0,0 +1,6777 @@
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+ ¡©©£§¬¬©­°­°¬°®ª®ªš €£¡¥§§ §£¡€©€©¬¬±°±²¶¹Žµ¶Ž²¶°ªŽŽ¶Ž°°Ž®±¶¶®®µ±Ž·®§€š­±°š°°ª­±·¹œŸœ²ºœ°¶·ŽŽ¶µ±ª¶º¹²ŽŽ±¶®²µ©¬±ŽºŸŸŸ»·¹ºº·Ÿº¹µ­®©±¬©¬°±±µ±¥±¶»µ·º°··Ž²µŽ¬²·¹°²°®µ»»Žº¶¶¹¿ÄÇÇÁŸ»ŸÁÂº¹œ¹ÄÆÊœÃœ¹±ª¶»¹·²ŸºÂŸÃÁŸ·ÂÃÄÈËÇÂœº¹»¶œÁÂŸÁŸÄÌÆÂÃÃÄÁÇŸÇÈÆËÂÂÆÂ¿ÇÄÃ»ÁÆÁÁ·ºµ¹ÂÄº¶œÁ»Ä·¹»œŸœÃÃ¹®µŽ·œœ·œÆÊÄÃœÂÃÃŸÂ¿ÇÂÃÁœÆÎÐÑÑÑÊÎÆÏÐÔØÙØÓÌÔÙÛØÕÐÐÐÐÜ×ÓÕÎÎÌÁ~oosuv}hELZg©µµ·š¶§œºº²¹»º»°±°©€ª©®š®šš§€©ª¬²²­~fc²±²®¶¹²¬¥¥©©©€¶¬£°®š®¶¹œµ»»ºµ°­¬¬®®­°±±»¹Ž²²°²­µ®²°­š©£¥­µ®²±°°®®¬¬¶µ±Ž§¥®­Ž²©±Ž°¶­±¬Ž°Ž°µ±­¬VHLFDQ§ocQOLSR_£ ¡¥šš®°ª®­ª©¬±®®±€¡  ¡¥š©­®­ª©§¬¬±°®ª­ª©¬©ª©ª­­®­©ª±±±²°±°±²²ª©§¬°±ª­Ž®­Ž²®±µŽ¶µ»º¹²²¶µ±­š¬·º¶º¹ºµ£¬®š ¥©Ž¶µ¶±·ŽŽŽ®±±±°°šªª¬©²µ²­²Ž°·±°Ž²°Ž±µªš±±§§©­ªª¶œ°µœ¹µµ²·œÂÁŸŽºŽ­»Â¶±Ž·Ÿº¶œŸºµŽºŸÂµµŽ¹ŸÄÄ¿¿ÂÄÆÄÊÈœÂÄºº¹œºµ·»ŸÂÄÃÊÊÌÈ¿ÄÂ¿ÄÁÇ¿·¿ÂºÈÁÄÂÂ»ÄÈÃ»¹œ¿Ÿ¹ÂŸÁ¿Á¿ÃœÃ»ºœ¹ºÂÁ»»¶²ª»Ÿ¹¹ÆÆ»ÁŽŽ»ÁÂÃÇÐÐÊÌÐÔÙÐÑÎÌÑÓÔÑÌØØÐÓÕØ××ÌÎÎÊÆÈÌËÂÄÆËÃÃplos|qcFM[k¬±º»µŽ²µœº±¹¹®±©§ š§šªŽ¹±©ªŽ£§©¬­²~~
+bU®¶µµ±¶¹µ²µ°§¡¬¥±®§®µ¶¶·ºµ¬±·»µ­¬ª±µ©¡­¬°©¬°­±®­¥®¥®¬¥§©ª£©§®±¬©Ž®ª¬ª²²­©®¬µŽ¬±¬±­ª¬©°¶¬·¶¶Žœ°ZNIIES­pdWQLOU`x
Index: branches/v4/softs/soft_transpose_giet/ldscript
===================================================================
--- branches/v4/softs/soft_transpose_giet/ldscript	(revision 371)
+++ branches/v4/softs/soft_transpose_giet/ldscript	(revision 371)
@@ -0,0 +1,90 @@
+/**********************************************************
+	File : ldscript 
+	Author : Alain Greiner
+	Date : March 2011  
+**********************************************************/
+
+/* definition of various hardware parameters.
+These variables are referenced in the drivers.c file,
+and must be defined, even if the corresponding
+peripherals are not present in the architecture */
+
+NB_CLUSTERS		= 4;		/* number of clusters */
+NB_PROCS		= 4;		/* number of processors per cluster */
+NB_TASKS		= 1;		/* number of tasks per processor */
+NB_TIMERS       	= 1;		/* max number of timers per processor */
+NB_LOCKS        	= 8;		/* number of spin_locks */
+
+/* definition of the base address for all segments 
+The peripherals base addresses are referenced by the
+software drivers and must be defined, even if the 
+peripherals are not present in the architecture */
+
+seg_code_base   = 0x00000000;       /* le code utilisateur */ 
+seg_data_base   = 0x00100000;       /* les données utilisateur */
+
+seg_heap_base   = 0x00300000;       /* le tas utilisateur */
+seg_stack_base  = 0x00800000;       /* la pile utilisateur */
+
+seg_kcode_base  = 0x80000000;       /* le code du système */
+seg_kdata_base  = 0x80100000;       /* les donnees du système */
+seg_kunc_base   = 0x80200000;       /* les données non cachées du système */
+
+seg_icu_base    = 0x00F00000;       /* controleur ICU */
+seg_tty_base    = 0xBFF20000;       /* controleur TTY */
+seg_dma_base    = 0x00F30000;       /* controleur DMA */
+
+seg_reset_base  = 0xBFC00000;       /* le code de boot */
+seg_fb_base     = 0xBFD00000;       /* controleur FRAME BUFFER */
+seg_ioc_base    = 0xBFF10000;       /* controleur I/O */
+
+seg_timer_base  = 0x00F00000;       /* controleur TIMER */
+seg_gcd_base    = 0xBFF50000;       /* controleur GCD */
+
+/* Grouping sections into segments */
+
+SECTIONS
+{
+   . = seg_kcode_base;
+   seg_kcode : {
+      *(.giet)
+      *(.switch)
+      *(.drivers)
+      *(.isr)
+   } 
+   . = seg_kdata_base;
+   seg_kdata : {
+      *(.kdata)
+   } 
+   . = seg_kunc_base;
+   seg_kunc : {
+      *(.unckdata)
+   } 
+   . = seg_kdata_base;
+   seg_kdata : {
+      *(.ksave)
+   } 
+   . = seg_code_base;
+   seg_code : {
+      *(.text)
+   } 
+   . = seg_reset_base;
+   seg_reset : {
+      *(.reset)
+   } 
+   . = seg_data_base;
+   seg_data : {
+      *(.rodata)
+      . = ALIGN(4);
+      *(.rodata.*)
+      . = ALIGN(4);
+      *(.data)
+      . = ALIGN(4);
+      *(.sdata)
+      . = ALIGN(4);
+      *(.bss)
+      *(COMMON)
+      *(.sbss)
+   } 
+}
+
Index: branches/v4/softs/soft_transpose_giet/main.c
===================================================================
--- branches/v4/softs/soft_transpose_giet/main.c	(revision 371)
+++ branches/v4/softs/soft_transpose_giet/main.c	(revision 371)
@@ -0,0 +1,310 @@
+
+#include "stdio.h"
+#include "limits.h"
+#include "../giet_tsar/block_device.h"
+
+#define NL              512
+#define NP              512
+#define NB_IMAGES       1
+#define NB_CLUSTER_MAX  256
+
+#define PRINTF(...)      ({ if (proc_id == 0) { tty_printf(__VA_ARGS__); } })
+
+//#define DISPLAY_ONLY
+
+///////////////////////////////////////////
+// tricks to read parameters from ldscript
+///////////////////////////////////////////
+
+struct plaf;
+
+extern struct plouf seg_ioc_base;
+extern struct plaf seg_heap_base;
+extern struct plaf NB_PROCS;
+extern struct plaf NB_CLUSTERS;
+
+/////////////
+void main(){
+   unsigned int frame = 0;
+   unsigned int date  = 0;
+
+   unsigned int c; // cluster index for loops
+   unsigned int l; // line index for loops
+   unsigned int p; // pixel index for loops
+
+   unsigned int proc_id       = procid();                      // processor id
+   unsigned int nlocal_procs  = (unsigned int) &NB_PROCS;      // number of processors per cluster
+   unsigned int nclusters     = (unsigned int) &NB_CLUSTERS;   // number of clusters
+   unsigned int local_id      = proc_id % nlocal_procs;        // local processor id
+   unsigned int cluster_id    = proc_id / nlocal_procs;        // cluster id
+   unsigned int base          = (unsigned int) &seg_heap_base; // base address for shared buffers
+   unsigned int increment     = 0x80000000 / nclusters * 2;    // cluster increment
+   unsigned int nglobal_procs = nclusters * nlocal_procs;      // number of tasks
+   unsigned int npixels       = NP * NL;                       // number of pixel per frame
+   
+   unsigned int * ioc_address = (unsigned int *) &seg_ioc_base;
+   unsigned int block_size    = ioc_address[BLOCK_DEVICE_BLOCK_SIZE];
+   unsigned int nblocks       = npixels / block_size;   // number of blocks per frame
+
+   PRINTF("\n *** Entering main at cycle %d ***\n\n", proctime());
+
+   //  parameters checking
+   if ((nlocal_procs != 1) && (nlocal_procs != 2) && (nlocal_procs != 4)){
+      PRINTF("NB_PROCS must be 1, 2 or 4\n");
+      exit(1);
+   }
+   if ((nclusters != 1) && (nclusters != 2) && (nclusters != 4) && (nclusters != 8) &&
+         (nclusters != 16) && (nclusters != 32) && (nclusters != 64) && (nclusters != 128) &&
+         (nclusters != 256)){
+      PRINTF("NB_CLUSTERS must be a power of 1 between 1 and 256\n");
+      exit(1);
+   }
+   if (nglobal_procs > 1024){
+      PRINTF("NB_PROCS * NB_CLUSTERS cannot be larger than 1024\n");
+      exit(1);
+   }
+   if (proc_id >= nglobal_procs){
+      PRINTF("processor id %d larger than NB_CLUSTERS*NB_PROCS\n", proc_id);
+      exit(1);
+   }
+
+   // Arrays of pointers on the shared, distributed buffers containing the frames 
+   // These arrays are indexed by the cluster index (sized for the worst case : 256 clusters)
+   unsigned char * A[NB_CLUSTER_MAX];
+   unsigned char * B[NB_CLUSTER_MAX];
+
+   // Arrays of pointers on the instrumentation arrays
+   // These arrays are indexed by the cluster index (sized for the worst case : 256 clusters)
+   // each pointer points on the base adress of an array of NPROCS unsigned int
+   unsigned int * LOAD_START[NB_CLUSTER_MAX];
+   unsigned int * LOAD_END[NB_CLUSTER_MAX];
+   unsigned int * TRSP_START[NB_CLUSTER_MAX];
+   unsigned int * TRSP_END[NB_CLUSTER_MAX];
+   unsigned int * DISP_START[NB_CLUSTER_MAX];
+   unsigned int * DISP_END[NB_CLUSTER_MAX];
+
+   // shared buffers address definition 
+   // from the seg_heap_base and increment depending on the cluster index
+   // These arrays of pointers are identical and replicated in the stack of each task 
+   for (c = 0; c < nclusters; c++){
+      A[c]          = (unsigned char *) (base                                  + increment * c);
+      B[c]          = (unsigned char *) (base +     npixels                    + increment * c);
+      LOAD_START[c] = (unsigned int *)  (base + 2 * npixels                    + increment * c);
+      LOAD_END[c]   = (unsigned int *)  (base + 2 * npixels +     nlocal_procs + increment * c);
+      TRSP_START[c] = (unsigned int *)  (base + 2 * npixels + 2 * nlocal_procs + increment * c);
+      TRSP_END[c]   = (unsigned int *)  (base + 2 * npixels + 3 * nlocal_procs + increment * c);
+      DISP_START[c] = (unsigned int *)  (base + 2 * npixels + 4 * nlocal_procs + increment * c);
+      DISP_END[c]   = (unsigned int *)  (base + 2 * npixels + 5 * nlocal_procs + increment * c);
+   }
+
+   PRINTF("NB_CLUSTERS     = %d\n", nclusters); 
+   PRINTF("NB_LOCAL_PROCS  = %d\n", nlocal_procs); 
+   PRINTF("NB_GLOBAL_PROCS = %d\n", nglobal_procs);
+   PRINTF("NB_PIXELS       = %d\n", npixels);
+   PRINTF("BLOCK_SIZE      = %d\n", block_size);
+   PRINTF("NB_BLOCKS       = %d\n\n", nblocks);
+
+
+   PRINTF("*** Starting barrier init at cycle %d ***\n", proctime());
+
+   //  barriers initialization
+   barrier_init(0, nglobal_procs);
+   barrier_init(1, nglobal_procs);
+   barrier_init(2, nglobal_procs);
+
+   PRINTF("*** Completing barrier init at cycle %d ***\n", proctime());
+
+   // Main loop (on frames)
+   while (frame < NB_IMAGES){
+      // pseudo parallel load from disk to A[c] buffer : nblocks/nclusters blocks
+      // only task running on processor with (local_id == 0) does it
+
+      if (local_id == 0){
+         int p;
+
+         date = proctime();
+         PRINTF("\n*** Starting load for frame %d at cycle %d\n", frame, date);
+         
+         for (p = 0; p < nlocal_procs; p++){
+            LOAD_START[cluster_id][p] = date;
+         }
+         if (ioc_read(frame * nblocks + nblocks * cluster_id / nclusters, A[cluster_id], nblocks / nclusters)){
+            PRINTF("echec ioc_read\n");
+            exit();
+         }
+         if (ioc_completed()){
+            PRINTF("echec ioc_completed\n");
+            exit();
+         }
+
+         date = proctime();
+         PRINTF("*** Completing load for frame %d at cycle %d\n", frame, date);
+         for (p = 0; p < nlocal_procs; p++){
+            LOAD_END[cluster_id][p] = date;
+         }
+      }
+
+      barrier_wait(0);
+
+      // parallel transpose from A to B buffers
+      // each processor makes the transposition for (NL/nglobal_procs) lines
+      // (p,l) are the (x,y) pixel coordinates in the source frame
+
+#ifndef DISPLAY_ONLY
+      date = proctime();
+      PRINTF("\n*** Starting transpose for frame %d at cycle %d\n", frame, date);
+      TRSP_START[cluster_id][local_id] = date;
+
+      unsigned int nlt   = NL / nglobal_procs; // Nombre de ligne Ã  traiter par processeur
+      unsigned int first = proc_id * nlt;      // Index de la premiÃšre ligne Ã  traiter pour le proc courant (celui qui exÃ©cute le code)
+      unsigned int last  = first + nlt;        // Index de la derniÃšre ligne
+      unsigned int nlines_clusters = NL / nclusters; // Nombre de lignes Ã  traiter par cluster
+      unsigned int npix_clusters   = NP / nclusters; // Nombre de pixels par ligne Ã  traiter par cluster
+
+      for (l = first; l < last; l++){
+         PRINTF("    - processing line %d\n", l);
+         for (p = 0; p < NP; p++){
+            unsigned int source_index   = (l % nlines_clusters) * NP + p;
+            unsigned int dest_cluster   = p / npix_clusters;
+            unsigned int dest_index     = (p % npix_clusters) * NL + l;
+            B[dest_cluster][dest_index] = A[cluster_id][source_index];
+         }
+      }
+
+      date = proctime();
+      PRINTF("*** Completing transpose for frame %d at cycle %d\n", frame, date);
+      TRSP_END[cluster_id][local_id] = date;
+      barrier_wait(1);
+#endif
+
+      // parallel display from B[c] to frame buffer 
+      // each processor uses its private dma to display NL*NP/nglobal_procs pixels
+
+      date = proctime();
+      PRINTF("\n*** Starting display for frame %d at cycle %d\n", frame, date);
+      DISP_START[cluster_id][local_id] = date;
+
+      unsigned int npxt = npixels / nglobal_procs;   // number of pixels per proc
+
+#ifndef DISPLAY_ONLY
+      if (fb_write(npxt * proc_id, B[cluster_id] + npxt * local_id, npxt)){
+         PRINTF("[%d]: echec fb_sync_write\n", proc_id);
+         exit();
+      }
+#else
+      if (fb_write(npxt * proc_id, A[cluster_id] + npxt * local_id, npxt)){
+         PRINTF("[%d]: echec fb_sync_write\n", proc_id);
+         exit();
+      }
+#endif
+
+      if (fb_completed()){
+         PRINTF("[%d]: echec fb_completed\n", proc_id);
+         exit();
+      }
+
+      date = proctime();
+      PRINTF("*** Completing display for frame %d at cycle %d\n", frame, date);
+      DISP_END[cluster_id][local_id] = date;
+
+      barrier_wait(2);
+
+      // Instrumentation (done by processor 0 in cluster 0)
+      if (local_id == 0){ 
+         date = proctime();
+         PRINTF("\n*** Starting Instrumentation for frame %d at cycle %d\n\n", frame, date);
+
+         int cc, pp;
+         unsigned int min_load_start = INT_MAX;
+         unsigned int max_load_start = 0;
+         unsigned int min_load_ended = INT_MAX;
+         unsigned int max_load_ended = 0;
+         unsigned int min_trsp_start = INT_MAX;
+         unsigned int max_trsp_start = 0;
+         unsigned int min_trsp_ended = INT_MAX;
+         unsigned int max_trsp_ended = 0;
+         unsigned int min_disp_start = INT_MAX;
+         unsigned int max_disp_start = 0;
+         unsigned int min_disp_ended = INT_MAX;
+         unsigned int max_disp_ended = 0;
+
+         for (cc = 0; cc < nclusters; cc++){
+            for (pp = 0; pp < nlocal_procs; pp++){
+               if (LOAD_START[cc][pp] < min_load_start){
+                  min_load_start = LOAD_START[cc][pp];
+               }
+               if (LOAD_START[cc][pp] > max_load_start){
+                  max_load_start = LOAD_START[cc][pp];
+               }
+               if (LOAD_END[cc][pp] < min_load_ended){
+                  min_load_ended = LOAD_END[cc][pp];
+               }
+               if (LOAD_END[cc][pp] > max_load_ended){
+                  max_load_ended = LOAD_END[cc][pp];
+               }
+
+               if (TRSP_START[cc][pp] < min_trsp_start){
+                  min_trsp_start = TRSP_START[cc][pp];
+               }
+               if (TRSP_START[cc][pp] > max_trsp_start){
+                  max_trsp_start = TRSP_START[cc][pp];
+               }
+               if (TRSP_END[cc][pp] < min_trsp_ended){
+                  min_trsp_ended = TRSP_END[cc][pp];
+               }
+               if (TRSP_END[cc][pp] > max_trsp_ended){
+                  max_trsp_ended = TRSP_END[cc][pp];
+               }
+
+               if (DISP_START[cc][pp] < min_disp_start){
+                  min_disp_start = DISP_START[cc][pp];
+               }
+               if (DISP_START[cc][pp] > max_disp_start){
+                  max_disp_start = DISP_START[cc][pp];
+               }
+               if (DISP_END[cc][pp] < min_disp_ended){
+                  min_disp_ended = DISP_END[cc][pp];
+               }
+               if (DISP_END[cc][pp] > max_disp_ended){
+                  max_disp_ended = DISP_END[cc][pp];
+               }
+            }
+         }
+
+         PRINTF(" - LOAD_START : min = %d / max = %d / med = %d / delta = %d\n",
+               min_load_start, max_load_start, (min_load_start+max_load_start)/2, max_load_start-min_load_start); 
+         PRINTF(" - LOAD_END   : min = %d / max = %d / med = %d / delta = %d\n",
+               min_load_ended, max_load_ended, (min_load_ended+max_load_ended)/2, max_load_ended-min_load_ended); 
+
+         PRINTF(" - TRSP_START : min = %d / max = %d / med = %d / delta = %d\n",
+               min_trsp_start, max_trsp_start, (min_trsp_start+max_trsp_start)/2, max_trsp_start-min_trsp_start); 
+         PRINTF(" - TRSP_END   : min = %d / max = %d / med = %d / delta = %d\n",
+               min_trsp_ended, max_trsp_ended, (min_trsp_ended+max_trsp_ended)/2, max_trsp_ended-min_trsp_ended); 
+
+         PRINTF(" - DISP_START : min = %d / max = %d / med = %d / delta = %d\n",
+               min_disp_start, max_disp_start, (min_disp_start+max_disp_start)/2, max_disp_start-min_disp_start); 
+         PRINTF(" - DISP_END   : min = %d / max = %d / med = %d / delta = %d\n",
+               min_disp_ended, max_disp_ended, (min_disp_ended+max_disp_ended)/2, max_disp_ended-min_disp_ended); 
+
+         PRINTF(" - BARRIER TRSP/DISP = %d\n", min_disp_start - max_trsp_ended);
+      }
+      frame++;
+
+   } // end while frame      
+
+   PRINTF("*** End of main ***\n");
+
+   while(1);
+} // end main()
+
+// Local Variables:
+// tab-width: 3
+// c-basic-offset: 3
+// c-file-offsets:((innamespace . 0)(inline-open . 0))
+// indent-tabs-mode: nil
+// End:
+
+// vim: filetype=cpp:expandtab:shiftwidth=3:tabstop=3:softtabstop=3
+
+
+
Index: branches/v4/softs/tests_ccvcache_v4/Makefile.inc
===================================================================
--- branches/v4/softs/tests_ccvcache_v4/Makefile.inc	(revision 371)
+++ branches/v4/softs/tests_ccvcache_v4/Makefile.inc	(revision 371)
@@ -0,0 +1,27 @@
+all: test.elf
+
+COMMON= ../common
+LDSCRIPT?= ../common/ldscript
+
+CC= mipsel-unknown-elf-gcc
+LD= mipsel-unknown-elf-ld
+DU= mipsel-unknown-elf-objdump
+
+CFLAGS= -mips32 -nostdinc -I. -I${COMMON} -mno-abicalls
+### LDFLAGS=-mips32 -nostdlib -Wl,-T${LDSCRIPT} -Ttext=0xbfc00000
+
+#### object files generation
+test.o: test.S 
+	${CC} ${CFLAGS} -c -o $@ $<
+	${DU} -D $@ > $@.txt
+
+subr.o: ${COMMON}/subr.S
+	${CC} ${CFLAGS} -c -o $@ $<
+	${DU} -D $@ > $@.txt
+
+### linking : test.o has to be the first object 
+test.elf: test.o subr.o ${EXTRA_OBJ}
+	${LD} -o $@ -T ${LDSCRIPT} -Ttext 0xbfc00000 $^
+	${DU} -D $@ > $@.txt
+clean:
+	rm -f *.o test.elf *.txt run.out temp
Index: branches/v4/softs/tests_ccvcache_v4/README
===================================================================
--- branches/v4/softs/tests_ccvcache_v4/README	(revision 371)
+++ branches/v4/softs/tests_ccvcache_v4/README	(revision 371)
@@ -0,0 +1,46 @@
+This is a very basic framework for running regression tests against
+a mips32+ccvcache TSAR platform. Here's the layout of this directory:
+
+../../../platforms/tsarv4_mono_mmu
+	contains the soclib platform description and simulation executable.
+	It should be compiled before starting tests.
+	it uses the vci_simhelper component, used to stop the simulation
+	with an exit value.  The framework uses this exit status
+	(with other things, see below) to determine if a test
+	is successfull. The simulator will exit with a non-0 exit status
+	after 100000 cycles (and a message to stderr), so the tests are
+	expected to be simple.
+	The platform has a tty, which is redirected to a file along with
+	the simlulator's output. The test framework may search for specific
+	strings in this file to determine if a test was successfull.
+common/
+	Some common functions, ldscripts, etc ... used by the tests.
+	It has a subr.S which holds usefull subroutines, such as
+	print() and printx().
+Makefile.inc
+	included from the test's Makefiles. Basic stuff to compile a
+	mips32 ELF executable for a test. It expects a test.S,
+	add the subr.S from common and eventually additionnal object
+	files.
+test_*/
+	these directories holds the test themselves. They have a run
+	script which does what is needed to compile and run a test,
+	print "test failed" or "test passed" on stdout, and clean the
+	directory if it's successfull. A sample script will call
+	make, then run the simulator with srdout/stderr redirected
+	to a file. If the simulator exists with a 0 status, this
+	script search for some strings in the output (that the
+	test program would have printed). This is an additionnal way
+	to check that all worked properly.
+	Tests are written in assembly; as we're testing for very specific
+	conditions (such as an instruction in a branch's delay slot on
+	a page boundary), we don't want the compiler to optimise things
+	or otherwise reorder instructions.
+	If the test was successfull, the 'run' script cleanups the
+	directory. Otherwise the 'run.out' file is available to
+	start looking at what's wrong.
+run_tests
+	runs all the test_*/run scripts - the goal being that
+	all of them print "test passsed" :). Directories are explicitely
+	listed in the run_tests script (order does matter to have a readable
+	output)
Index: branches/v4/softs/tests_ccvcache_v4/bilan
===================================================================
--- branches/v4/softs/tests_ccvcache_v4/bilan	(revision 371)
+++ branches/v4/softs/tests_ccvcache_v4/bilan	(revision 371)
@@ -0,0 +1,106 @@
+-n test_sanity: 
+test passsed
+-n test_exceptions: 
+test passsed
+-n test_mmu_basic: 
+test passsed
+-n test_excep_ls: 
+test passsed
+-n test_excep_ls_delayslot: 
+test passsed
+-n test_excep_ls_llsc: 
+test passsed
+-n test_excep_if: 
+test passsed
+-n test_excep_if_delayslot: 
+test passsed
+-n test_excep_if_llsc: 
+test passsed
+-n test_exception_epc_modify: 
+test passsed
+-n test_dtlb_inval: 
+test passsed
+-n test_dtlb_inval2: 
+test passsed
+-n test_dtlb_inval3: 
+test passsed
+-n test_itlb_inval: 
+test passsed
+-n test_itlb_inval2: 
+test passsed
+-n test_idtlb_inval: 
+test passsed
+-n test_idtlb_inval2: 
+test passsed
+-n test_idtlb_inval3: 
+test passsed
+-n test_idtlb_inval4: 
+test passsed
+-n test_dtlb_ptprinval: 
+test passsed
+-n test_itlb_ptprinval: 
+test passsed
+-n test_idtlb_ptprinval: 
+test passsed
+-n test_sync: 
+test passsed
+-n test_sc_update_cache: 
+test passsed
+-n test_pte_llsc: 
+test passsed
+-n test_interrupt: 
+test passsed
+-n test_interrupt_epc_modify: 
+test passsed
+-n test_xicu_timer: 
+test passsed
+-n test_interrupt_delayslot: 
+test FAILED
+-n test_interrupt_mask: 
+test passsed
+-n test_interrupt_external_mask: 
+test passsed
+-n test_excep_cop: 
+test passsed
+-n test_excep_cop_delayslot: 
+test passsed
+-n test_excep_cop1: 
+test passsed
+-n test_syscall: 
+test passsed
+-n test_syscall_delayslot: 
+test passsed
+-n test_breakpoint: 
+test passsed
+-n test_breakpoint_delayslot: 
+test passsed
+-n test_ri: 
+test passsed
+-n test_ri_delayslot: 
+test passsed
+-n test_ao: 
+test passsed
+-n test_ao_delayslot: 
+test passsed
+-n test_trap: 
+test passsed
+-n test_trap_delayslot: 
+test passsed
+-n test_fpediv: 
+test FAILED
+-n test_fpe_delayslot: 
+test FAILED
+-n test_dcache_inval_pa: 
+test passsed
+-n test_icache_inval_pa: 
+test passsed
+-n test_pte2i_ref: 
+test passsed
+-n test_pte2lw_ref: 
+test passsed
+-n test_pte2ll_ref: 
+test passsed
+-n test_pte2sw_dirty: 
+test passsed
+-n test_pte2sc_dirty: 
+test passsed
Index: branches/v4/softs/tests_ccvcache_v4/common/common.sh
===================================================================
--- branches/v4/softs/tests_ccvcache_v4/common/common.sh	(revision 371)
+++ branches/v4/softs/tests_ccvcache_v4/common/common.sh	(revision 371)
@@ -0,0 +1,3 @@
+SIMUL=../../../platforms/tsarv4_mono_mmu/simul.x
+
+#SIMUL=../../../../soclib-svn-june-2009/soclib/soclib/platform/topcells/caba_vgsb_almo_mmu/simul.x
Index: branches/v4/softs/tests_ccvcache_v4/common/ldscript
===================================================================
--- branches/v4/softs/tests_ccvcache_v4/common/ldscript	(revision 371)
+++ branches/v4/softs/tests_ccvcache_v4/common/ldscript	(revision 371)
@@ -0,0 +1,65 @@
+/*
+ *
+ * SOCLIB_GPL_HEADER_BEGIN
+ * 
+ * This file is part of SoCLib, GNU GPLv2.
+ * 
+ * SoCLib is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ * 
+ * SoCLib is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * General Public License for more details.
+ * 
+ * You should have received a copy of the GNU General Public License
+ * along with SoCLib; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301, USA.
+ * 
+ * SOCLIB_GPL_HEADER_END
+ *
+ * Copyright (c) UPMC, Lip6, SoC
+ *         Nicolas Pouillon <nipo@ssji.net>, 2006-2007
+ *
+ * Maintainers: abdelmalek.si-merabet@lip6.fr
+ */
+
+ENTRY(_start)
+
+SECTIONS
+{
+   . = 0xbfc00000;
+   .text : {
+      *(.text)
+   }
+   .rodata : {
+      *(.rodata)
+      . = ALIGN(4);
+   }
+   . = 0x00000000;
+   .data  : {
+      *(.data)
+   }
+   .sdata : {
+      *(.lit8)
+      *(.lit4)
+      *(.sdata)
+   }
+   _gp = .;
+   . = ALIGN(4);
+   _edata = .;
+   .sbss  : {
+      *(.sbss)
+      *(.scommon)
+   }
+   .bss   : {
+      *(.bss)
+      *(COMMON)
+   }
+   . = ALIGN(4);
+   _end = .;
+   _heap = .;
+   _stack = 0x00400000-16;
+}
Index: branches/v4/softs/tests_ccvcache_v4/common/misc.h
===================================================================
--- branches/v4/softs/tests_ccvcache_v4/common/misc.h	(revision 371)
+++ branches/v4/softs/tests_ccvcache_v4/common/misc.h	(revision 371)
@@ -0,0 +1,56 @@
+/* multi-tty definitions */
+#define TTY_BASE 0xd0200000
+#define TTY_WRITE  0
+#define TTY_STATUS 1
+#define TTY_READ 2
+
+/* vci_exit definitions */
+#define EXIT_BASE 0xe0000000
+
+#define BOOT_ADDRESS 0xbfc00000
+#define EXCEP_ADDRESS 0xbfc00380
+
+/* vci dma */
+#define DMA_BASE 	0xe8000000
+#define DMA_SRC  	0
+#define DMA_DST  	4
+#define DMA_LEN  	8
+#define DMA_RESET	12
+
+/* cop0 definitions */
+#define COP_0_BADVADDR	$8
+#define COP0_STATUS	$12
+#define COP0_CAUSE	$13
+#define COP0_EXPC	$14
+
+/* easy print macros */
+#define PRINT(str) \
+        la      a0, str;\
+	jal     print; \
+	nop
+
+#define PRINT_SYNC(str) \
+        la      a0, str;\
+	jal     print_sync; \
+	nop
+
+
+
+#define PRINTX \
+	jal     printx;\
+	nop
+
+#define PUTCHAR(c) li a0, c; sb a0, 0(k0)
+
+#define EXIT(a) \
+	li a0, a; \
+	sw a0, 4(k1); \
+	1:      j 1b; \
+	nop
+
+/* some magic numers to test */
+#define MAGIC1	0xdead
+#define MAGIC2	0xbeef
+#define MAGIC3	0x900d
+#define MAGIC4	0xf00d
+
Index: branches/v4/softs/tests_ccvcache_v4/common/registers.h
===================================================================
--- branches/v4/softs/tests_ccvcache_v4/common/registers.h	(revision 371)
+++ branches/v4/softs/tests_ccvcache_v4/common/registers.h	(revision 371)
@@ -0,0 +1,32 @@
+#define zero	$0
+#define at	$at
+#define v0	$2
+#define v1	$3
+#define a0	$4
+#define a1	$5
+#define a2	$6
+#define a3	$7
+#define t0	$8
+#define t1	$9
+#define t2	$10
+#define t3	$11
+#define t4	$12
+#define t5	$13
+#define t6	$14
+#define t7	$15
+#define s0	$16
+#define s1	$17
+#define s2	$18
+#define s3	$19
+#define s4	$20
+#define s5	$21
+#define s6	$22
+#define s7	$23
+#define t8	$24
+#define t9	$25
+#define k0	$26
+#define k1	$27
+#define gp	$28
+#define sp	$29
+#define fp	$30
+#define ra	$31
Index: branches/v4/softs/tests_ccvcache_v4/common/subr.S
===================================================================
--- branches/v4/softs/tests_ccvcache_v4/common/subr.S	(revision 371)
+++ branches/v4/softs/tests_ccvcache_v4/common/subr.S	(revision 371)
@@ -0,0 +1,78 @@
+#include <registers.h>
+/* test common subroutines
+
+	.text
+/*
+ * void print(char *): print a string to the multitty.
+ * assumes k0 points to the tty base.
+ */
+	.globl print
+print:
+	.set noreorder
+	move	t0, a0
+1:
+	lb	t1, 0(t0);
+	beq	t1, zero, end
+	nop
+	sb	t1, 0(k0)
+	addiu	t0, t0, 1
+	j	1b
+	nop
+end:
+	jr	ra
+	nop
+
+/*
+ * void print_sync(char *): print a string to the multitty with a sync instruction for each character.
+ * assumes k0 points to the tty base.
+ */
+	.globl print_sync
+print_sync:
+	.set noreorder
+	move	t0, a0
+1:
+	lb	t1, 0(t0);
+	beq	t1, zero, end_print_sync
+	nop
+	sb	t1, 0(k0)
+    sync
+	addiu	t0, t0, 1
+	j	1b
+	nop
+end_print_sync:
+	jr	ra
+	nop
+
+
+/*
+ * void printx(uint32_t): print a number in hex to the multitty
+ * assumes points to the tty base.
+ */
+	.globl printx
+printx:
+	.set noreorder
+	move	t0, a0
+	li	t1, '0'
+	sb	t1, 0(k0)
+	li	t1, 'x'
+	sb	t1, 0(k0)
+	li	t1, 8
+1:
+	lui	t2, 0xf000;
+	and	t2, t0, t2
+	srl	t2, t2, 28
+	slti	t3, t2, 0xa
+	beq	t3, zero, 2f /* in range A-F */
+	nop
+	addi	t2, t2, '0'
+	j	3f
+	nop
+2:
+	addi    t2, t2, 'A' - 0xa
+3:
+	sb      t2, 0(k0)
+	addi	t1, t1, -1
+	bgtz	t1, 1b
+	sll	t0, t0, 4
+	jr	ra
+	nop
Index: branches/v4/softs/tests_ccvcache_v4/common/vcache.h
===================================================================
--- branches/v4/softs/tests_ccvcache_v4/common/vcache.h	(revision 371)
+++ branches/v4/softs/tests_ccvcache_v4/common/vcache.h	(revision 371)
@@ -0,0 +1,66 @@
+/* cop2/vcache definitions */
+#define VC_PTPR			$0 		/* set Page Table Pointer Register */
+#define VC_TLB_EN		$1 		/* set Data & Inst TLBs Mode Register */
+#define	  VC_TLB_EN_ITLB		0x8 	/* enable instruction TLB */
+#define	  VC_TLB_EN_DTLB		0x4 	/* enable data TLB */
+#define	  VC_TLB_EN_ICACHE		0x2 	/* enable instruction cache */
+#define	  VC_TLB_EN_DCACHE		0x1 	/* enable data cache */
+#define VC_ICACHE_FLUSH 	$2 		/* Instruction Cache flush */
+#define VC_DCACHE_FLUSH 	$3 		/* Data Cache flush */
+#define VC_ITLB_INVAL		$4 		/* Instruction TLB line invalidate */
+#define VC_DTLB_INVAL		$5 		/* Data TLB line invalidate */
+#define VC_ICACHE_INVAL 	$6 		/* Instruction Cache line invalidate */
+#define VC_DCACHE_INVAL 	$7 		/* Data Cache line invalidate */
+#define VC_ICACHE_PREFETCH 	$8 		/* Instruction Cache line prefetch */
+#define VC_DCACHE_PREFETCH 	$9 		/* Data Cache line prefetch */
+#define VC_SYNC			$10 		/* Complete pending writes */
+#define VC_IERR_TYPE		$11 		/* Instruction Exception type Register */
+#define VC_DERR_TYPE		$12 		/* Data Exception type Register */
+#define VC_DATA_LO		$17 		/* misc register low */
+#define VC_DATA_HI		$18 		/* misc register hight */
+#define VC_ICACHE_INVAL_PA 	$19 		/* misc register hight */
+#define VC_DCACHE_INVAL_PA 	$20 		/* misc register hight */
+#define	  VC_ERR_PT1_UNMAPPED		0x001 	/* Page fault on Table1 (invalid PTE) */
+#define	  VC_ERR_PT2_UNMAPPED		0x002 	/* Page fault on Table 2 (invalid PTE) */
+#define	  VC_ERR_PRIVILEGE_VIOLATION	0x004 	/* Protected access in user mode */
+#define	  VC_ERR_WRITE_VIOLATION	0x008 	/* Write access to a non write page */
+#define	  VC_ERR_EXEC_VIOLATION		0x010 	/* Exec access to a non exec page */
+#define	  VC_ERR_UNDEFINED_XTN		0x020 	/* Undefined external access address */
+#define	  VC_ERR_PT1_ILLEGAL_ACCESS	0x040 	/* Bus Error in Table1 access */
+#define	  VC_ERR_PT2_ILLEGAL_ACCESS	0x080 	/* Bus Error in Table2 access */
+#define	  VC_ERR_CACHE_ILLEGAL_ACCESS	0x100 	/* Bus Error during the cache access */
+#define VC_I_BAD_VADDR		$13 		/* Instruction Bad Virtual Address Register */
+#define VC_D_BAD_VADDR		$14 		/* Data Bad Virtual Address Register */
+#define VC_DATA_L		$17 		/* cache parameters */
+#define VC_DATA_H		$18 		/* cache parameters */
+#define VC_ICACHE_INVAL_PA	$19 		/* icache inval per physical address */
+#define VC_DCACHE_INVAL_PA	$20 		/* dcache inval per physical address */
+
+/* vcache page level 1 format */
+#define PTE1_V  (1 << 31)       		/* entry valid */
+#define PTE1_T  (1 << 30)       		/* 0 == entry is a PTE1 (maps a 2M page) */
+#define PTE1_L  (1 << 29)       		/* accessed by local CPU */
+#define PTE1_R  (1 << 28)       		/* accessed by remote CPU */
+#define PTE1_C  (1 << 27)       		/* cachable */
+#define PTE1_W  (1 << 26)       		/* writable */
+#define PTE1_X  (1 << 25)       		/* executable */
+#define PTE1_U  (1 << 24)       		/* user-accessible */
+#define PTE1_G  (1 << 23)       		/* global */
+#define PTE1_D  (1 << 22)       		/* dirty */
+
+/* vcache page level 2 format: same as level 1, PTE1_T  */
+#define PTE2_V  (1 << 31)       		/* entry valid */
+						/* reserved, 0 */
+#define PTE2_L  (1 << 29)       		/* accessed by local CPU */
+#define PTE2_R  (1 << 28)       		/* accessed by remote CPU */
+#define PTE2_C  (1 << 27)       		/* cachable */
+#define PTE2_W  (1 << 26)       		/* writable */
+#define PTE2_X  (1 << 25)       		/* executable */
+#define PTE2_U  (1 << 24)       		/* user-accessible */
+#define PTE2_G  (1 << 23)       		/* global */
+#define PTE2_D  (1 << 22)       		/* dirty */
+#define PTE2_os 0xff				/* OS-reserved bits */
+
+#define PTE2_SHIFT 	12
+#define PTE2_MASK 	0x0001ff000
+#define VADDR_TO_PTE2I(va) (((va) & PTE2_MASK) >> PTE2_SHIFT)
Index: branches/v4/softs/tests_ccvcache_v4/common/xicu.h
===================================================================
--- branches/v4/softs/tests_ccvcache_v4/common/xicu.h	(revision 371)
+++ branches/v4/softs/tests_ccvcache_v4/common/xicu.h	(revision 371)
@@ -0,0 +1,96 @@
+#define XICU_BASE 0xd8200000
+#define __XICU_FUNC_SHIFT 7
+#define __XICU_IDX_SHIFT 2
+#define __XICU_RIDX(func, idx) \
+    ((((func) & 0x1f) << __XICU_FUNC_SHIFT) + \
+     (((idx) & 0x1f) << __XICU_IDX_SHIFT))
+
+/* triggers the wtiidx interrupt. R/W */
+#define XICU_WTI_REG_FUNC 0x00
+#define XICU_WTI_REG(wtiidx) __XICU_RIDX(XICU_WTI_REG_FUNC, wtiidx)
+
+/* Timer period R/W */
+#define XICU_PTI_PER_FUNC 0x01
+#define XICU_PTI_PER(ptiidx) __XICU_RIDX(XICU_PTI_PER_FUNC, ptiidx)
+
+/* timer value R/W */
+#define XICU_PTI_VAL_FUNC 0x02
+#define XICU_PTI_VAL(ptiidx) __XICU_RIDX(XICU_PTI_VAL_FUNC, ptiidx)
+
+/* Timer interrupt acknowledge. R */
+#define XICU_PTI_ACK_FUNC 0x03
+#define XICU_PTI_ACK(ptiidx) __XICU_RIDX(XICU_PTI_ACK_FUNC, ptiidx)
+
+/*
+ * remaining registers define the way interrupt sources are mutiplexed to
+ * the output lines. Indexed by output line number.
+ */
+/*
+ * Multiplex timers to output lines:
+ * XICU_MSK_PTI mask register for outidx line (bit to 1 enable interrupt)
+ * XICU_MSK_PTI_E atomically add a set of bits to XICU_MSK_PTI
+ * XICU_MSK_PTI_D atomically clear a set of bits from XICU_MSK_PTI
+ * XICU_PTI_ACT get active PTI lines for this output line
+ */
+#define XICU_MSK_PTI_FUNC 0x04 /* R/W */
+#define XICU_MSK_PTI(outidx) __XICU_RIDX(XICU_MSK_PTI_FUNC, outidx)
+
+#define XICU_MSK_PTI_E_FUNC 0x05 /* W */
+#define XICU_MSK_PTI_E(outidx) __XICU_RIDX(XICU_MSK_PTI_E_FUNC, outidx)
+
+#define XICU_MSK_PTI_D_FUNC 0x06 /* W */
+#define XICU_MSK_PTI_D(outidx) __XICU_RIDX(XICU_MSK_PTI_D_FUNC, outidx)
+
+#define XICU_PTI_ACT_FUNC 0x06 /* R */
+#define XICU_PTI_ACT(outidx) __XICU_RIDX(XICU_PTI_ACT_FUNC, outidx)
+
+/*
+ * Multiplex hardware input lines to output lines:
+ * XICU_MSK_HWI mask register for outidx line (bit to 1 enable interrupt)
+ * XICU_MSK_HWI_E atomically add a set of bits to XICU_MSK_HWI
+ * XICU_MSK_HWI_D atomically clear a set of bits from XICU_MSK_HWI
+ * XICU_HWI_ACT get active HWI lines for this output line
+ */
+#define XICU_MSK_HWI_FUNC 0x08 /* R/W */
+#define XICU_MSK_HWI(outidx) __XICU_RIDX(XICU_MSK_HWI_FUNC, outidx)
+
+#define XICU_MSK_HWI_E_FUNC 0x09 /* W */
+#define XICU_MSK_HWI_E(outidx) __XICU_RIDX(XICU_MSK_HWI_E_FUNC, outidx)
+
+#define XICU_MSK_HWI_D_FUNC 0x0a /* W */
+#define XICU_MSK_HWI_D(outidx) __XICU_RIDX(XICU_MSK_HWI_D_FUNC, outidx)
+
+#define XICU_HWI_ACT_FUNC 0x0a /* R */
+#define XICU_HWI_ACT(outidx) __XICU_RIDX(XICU_HWI_ACT_FUNC, outidx)
+
+/*
+ * Multiplex hardware input lines to output lines:
+ * XICU_MSK_WTI mask register for outidx line (bit to 1 enable interrupt)
+ * XICU_MSK_WTI_E atomically add a set of bits to XICU_MSK_WTI
+ * XICU_MSK_WTI_D atomically clear a set of bits from XICU_MSK_WTI
+ * XICU_WTI_ACT get active WTI lines for this output line
+ */
+#define XICU_MSK_WTI_FUNC 0x0c /* R/W */
+#define XICU_MSK_WTI(outidx) __XICU_RIDX(XICU_MSK_WTI_FUNC, outidx)
+
+#define XICU_MSK_WTI_E_FUNC 0x0d /* W */
+#define XICU_MSK_WTI_E(outidx) __XICU_RIDX(XICU_MSK_WTI_E_FUNC, outidx)
+
+#define XICU_MSK_WTI_D_FUNC 0x0e /* W */
+#define XICU_MSK_WTI_D(outidx) __XICU_RIDX(XICU_MSK_WTI_D_FUNC, outidx)
+
+#define XICU_WTI_ACT_FUNC 0x0e /* R */
+#define XICU_WTI_ACT(outidx) __XICU_RIDX(XICU_WTI_ACT_FUNC, outidx)
+
+/* source priority encoder for outpout lines */
+#define XICU_PRIO_FUNC 0x0f
+#define XICU_PRIO(outidx) __XICU_RIDX(XICU_PRIO_FUNC, outidx)
+
+#define XICU_PRIO_PTI 0x00000001 /* Timer interrrupt pending */
+#define XICU_PRIO_PTII(val) ((val) >> 8 & 0x1f) /* first PTI pending */
+#define XICU_PRIO_HWI 0x00000002 /* Hardware interrrupt pending */
+#define XICU_PRIO_HWII(val) ((val) >> 16 & 0x1f) /* first HWI pending */
+#define XICU_PRIO_WTI 0x00000004 /* write-triggered interrrupt pending */
+#define XICU_PRIO_WTII(val) ((val) >> 24 & 0x1f) /* first WTI pending */
+
+#define XICU_PRIO_PENDING (XICU_PRIO_PTI|XICU_PRIO_HWI|XICU_PRIO_WTI)
Index: branches/v4/softs/tests_ccvcache_v4/run_tests
===================================================================
--- branches/v4/softs/tests_ccvcache_v4/run_tests	(revision 371)
+++ branches/v4/softs/tests_ccvcache_v4/run_tests	(revision 371)
@@ -0,0 +1,36 @@
+#!/bin/sh
+
+PATH=${PATH}:/dsk/l1/misc/bouyer/tmp/tsarmips/obj/netbsd-5/tooldir/bin
+export PATH
+SOCLIB_TTY=TERM
+export SOCLIB_TTY
+
+for dir in test_sanity test_exceptions test_mmu_basic \
+   test_excep_ls test_excep_ls_delayslot test_excep_ls_llsc \
+   test_excep_if test_excep_if_delayslot test_excep_if_llsc \
+   test_exception_epc_modify	\
+   test_dtlb_inval test_dtlb_inval2 test_dtlb_inval3 \
+   test_itlb_inval test_itlb_inval2 \
+   test_idtlb_inval test_idtlb_inval2 test_idtlb_inval3 test_idtlb_inval4 \
+   test_dtlb_ptprinval test_itlb_ptprinval test_idtlb_ptprinval \
+   test_sync \
+   test_llsc test_sc_no_ll test_sc_update_cache test_pte_llsc \
+   test_interrupt \
+   test_interrupt_epc_modify \
+   test_xicu_timer \
+   test_interrupt_delayslot \
+   test_interrupt_mask \
+   test_interrupt_external_mask \
+   test_excep_cop test_excep_cop_delayslot test_excep_cop1 \
+   test_syscall test_syscall_delayslot \
+   test_breakpoint test_breakpoint_delayslot \
+   test_ri test_ri_delayslot \
+   test_ao test_ao_delayslot \
+   test_trap test_trap_delayslot \
+   test_dcache_inval_pa test_icache_inval_pa \
+   test_pte2i_ref test_pte2lw_ref test_pte2ll_ref test_pte2sw_dirty test_pte2sc_dirty \
+   test_dma_basic test_dma_unaligned \
+   ; do
+	echo -n ${dir}": "
+	(cd $dir && ./run)
+done
Index: branches/v4/softs/tests_ccvcache_v4/test_ao/Makefile
===================================================================
--- branches/v4/softs/tests_ccvcache_v4/test_ao/Makefile	(revision 371)
+++ branches/v4/softs/tests_ccvcache_v4/test_ao/Makefile	(revision 371)
@@ -0,0 +1,1 @@
+include ../Makefile.inc
Index: branches/v4/softs/tests_ccvcache_v4/test_ao/mtty0
===================================================================
--- branches/v4/softs/tests_ccvcache_v4/test_ao/mtty0	(revision 371)
+++ branches/v4/softs/tests_ccvcache_v4/test_ao/mtty0	(revision 371)
@@ -0,0 +1,2 @@
+[20hstart
+status 0x00400002 cause 0x00000030 pc 0xBFC00034 badva 0x00000000
Index: branches/v4/softs/tests_ccvcache_v4/test_ao/run
===================================================================
--- branches/v4/softs/tests_ccvcache_v4/test_ao/run	(revision 371)
+++ branches/v4/softs/tests_ccvcache_v4/test_ao/run	(revision 371)
@@ -0,0 +1,28 @@
+#!/bin/sh 
+
+. ../common/common.sh
+
+check_output()
+{
+	egrep "^status 0x00400002 cause 0x00000030 pc 0xBFC00034 badva 0x00000000$" run.out > /dev/null
+	if [ $? -ne 0 ]; then
+		echo "couldn't find string 1 in output - mtty not working ?" >> run.out
+		return 1
+	fi
+	return 0;
+}
+
+make --quiet || exit 1
+${SIMUL} > run.out 2>&1 
+if [ $? -eq 0 ]; then
+	if check_output; then
+		echo "test passsed";
+		make --quiet clean
+		exit 0;
+	fi
+	echo "test FAILED"
+	exit 1
+fi
+echo "test FAILED"
+exit 1
+
Index: branches/v4/softs/tests_ccvcache_v4/test_ao/test.S
===================================================================
--- branches/v4/softs/tests_ccvcache_v4/test_ao/test.S	(revision 371)
+++ branches/v4/softs/tests_ccvcache_v4/test_ao/test.S	(revision 371)
@@ -0,0 +1,63 @@
+/*
+ * arithmetic overflow test: check that a add can generates an exception
+ */
+#include <registers.h>
+#include <misc.h>
+
+	.text
+	.globl  _start
+_start:
+	.set noreorder
+	la	k0, TTY_BASE
+	la	k1, EXIT_BASE
+	la	sp, 0x00400000 - 16
+
+	PRINT(startstr)
+
+	/* reset cop0 status (keep BEV) */
+	lui	a0, 0x0040;
+	mtc0	a0, COP0_STATUS
+	la	a0, 0x7fffffff
+	li	a1, 0x02
+	add	a0, a0, a1
+	EXIT(2)
+
+	.globl excep
+excep:
+	.set noreorder
+	PRINT(statusstr)
+	mfc0	a0, COP0_STATUS
+	PRINTX
+
+	PRINT(causestr)
+	mfc0	a0, COP0_CAUSE
+	PRINTX
+
+	PRINT(pcstr)
+	mfc0	a0, COP0_EXPC
+	PRINTX
+
+	PRINT(badvastr)
+	mfc0	a0, COP_0_BADVADDR
+	PRINTX
+	PUTCHAR('\n')
+#we should end there
+	EXIT(0)
+
+	.rodata:
+statusstr: .ascii "status \0"
+causestr: .ascii " cause \0"
+pcstr: .ascii " pc \0"
+badvastr: .ascii " badva \0"
+startstr: .ascii "start\n\0"
+usrstr: .ascii "usrmode\n\0"
+
+	.org EXCEP_ADDRESS - BOOT_ADDRESS
+	.globl evect
+evect:
+	j	excep
+	nop
+	.data
+	.word MAGIC1
+testval:
+	.word MAGIC2
Index: branches/v4/softs/tests_ccvcache_v4/test_ao_delayslot/Makefile
===================================================================
--- branches/v4/softs/tests_ccvcache_v4/test_ao_delayslot/Makefile	(revision 371)
+++ branches/v4/softs/tests_ccvcache_v4/test_ao_delayslot/Makefile	(revision 371)
@@ -0,0 +1,1 @@
+include ../Makefile.inc
Index: branches/v4/softs/tests_ccvcache_v4/test_ao_delayslot/run
===================================================================
--- branches/v4/softs/tests_ccvcache_v4/test_ao_delayslot/run	(revision 371)
+++ branches/v4/softs/tests_ccvcache_v4/test_ao_delayslot/run	(revision 371)
@@ -0,0 +1,28 @@
+#!/bin/sh 
+
+. ../common/common.sh
+
+check_output()
+{
+	egrep "^status 0x00400002 cause 0x80000030 pc 0xBFC00034 badva 0x00000000$" run.out > /dev/null
+	if [ $? -ne 0 ]; then
+		echo "couldn't find string 1 in output - mtty not working ?" >> run.out
+		return 1
+	fi
+	return 0;
+}
+
+make --quiet || exit 1
+${SIMUL} > run.out 2>&1 
+if [ $? -eq 0 ]; then
+	if check_output; then
+		echo "test passsed";
+		make --quiet clean
+		exit 0;
+	fi
+	echo "test FAILED"
+	exit 1
+fi
+echo "test FAILED"
+exit 1
+
Index: branches/v4/softs/tests_ccvcache_v4/test_ao_delayslot/test.S
===================================================================
--- branches/v4/softs/tests_ccvcache_v4/test_ao_delayslot/test.S	(revision 371)
+++ branches/v4/softs/tests_ccvcache_v4/test_ao_delayslot/test.S	(revision 371)
@@ -0,0 +1,84 @@
+/*
+ * arithmetic overflow test: check that a overflow in a delay slot is
+ * properly handled
+ */
+#include <registers.h>
+#include <misc.h>
+
+	.text
+	.globl  _start
+_start:
+	.set noreorder
+	la	k0, TTY_BASE
+	la	k1, EXIT_BASE
+	la	sp, 0x00400000 - 16
+
+	PRINT(startstr)
+
+	/* reset cop0 status (keep BEV) */
+	lui	a0, 0x0040;
+	mtc0	a0, COP0_STATUS
+	la	a0, 0x7fffffff
+	li	a1, 0x02
+	j	exit
+	add	a0, a0, a1
+	/* we should not get there, */
+	EXIT(2)
+	.globl exit
+exit:
+	move	a0, v0
+	PRINTX
+	PUTCHAR(' ')
+	move	a0, v1
+	PRINTX
+	PUTCHAR('\n')
+	/* we should get there */
+	EXIT(0)
+
+	.globl excep
+excep:
+	.set noreorder
+	PRINT(statusstr)
+	mfc0	a0, COP0_STATUS
+	PRINTX
+
+	PRINT(causestr)
+	mfc0	a0, COP0_CAUSE
+	PRINTX
+
+	PRINT(pcstr)
+	mfc0	a0, COP0_EXPC
+	PRINTX
+
+	PRINT(badvastr)
+	mfc0	a0, COP_0_BADVADDR
+	PRINTX
+	PUTCHAR('\n')
+	la	a0, exit
+	mtc0	a0, COP0_EXPC
+	li	v0, MAGIC1
+	li	v1, MAGIC2
+	li	a3, 1
+	eret
+	nop
+
+#we should not end there
+	EXIT(1)
+
+	.rodata:
+statusstr: .ascii "status \0"
+causestr: .ascii " cause \0"
+pcstr: .ascii " pc \0"
+badvastr: .ascii " badva \0"
+startstr: .ascii "start\n\0"
+usrstr: .ascii "usrmode\n\0"
+
+	.org EXCEP_ADDRESS - BOOT_ADDRESS
+	.globl evect
+evect:
+	j	excep
+	nop
+	.data
+	.word MAGIC1
+testval:
+	.word MAGIC2
Index: branches/v4/softs/tests_ccvcache_v4/test_breakpoint/Makefile
===================================================================
--- branches/v4/softs/tests_ccvcache_v4/test_breakpoint/Makefile	(revision 371)
+++ branches/v4/softs/tests_ccvcache_v4/test_breakpoint/Makefile	(revision 371)
@@ -0,0 +1,1 @@
+include ../Makefile.inc
Index: branches/v4/softs/tests_ccvcache_v4/test_breakpoint/run
===================================================================
--- branches/v4/softs/tests_ccvcache_v4/test_breakpoint/run	(revision 371)
+++ branches/v4/softs/tests_ccvcache_v4/test_breakpoint/run	(revision 371)
@@ -0,0 +1,33 @@
+#!/bin/sh 
+
+. ../common/common.sh
+
+check_output()
+{
+	egrep "^status 0x00400002 cause 0x00000024 pc 0xBFC00034 badva 0x00000000$" run.out > /dev/null
+	if [ $? -ne 0 ]; then
+		echo "couldn't find string 1 in output - mtty not working ?" >> run.out
+		return 1
+	fi
+	egrep "^0x0000DEAD 0x0000BEEF$" run.out > /dev/null
+	if [ $? -ne 0 ]; then
+		echo "couldn't find string 2 in output - mtty not working ?" >> run.out
+		return 1
+	fi
+	return 0;
+}
+
+make --quiet || exit 1
+${SIMUL} > run.out 2>&1 
+if [ $? -eq 0 ]; then
+	if check_output; then
+		echo "test passsed";
+		make --quiet clean
+		exit 0;
+	fi
+	echo "test FAILED"
+	exit 1
+fi
+echo "test FAILED"
+exit 1
+
Index: branches/v4/softs/tests_ccvcache_v4/test_breakpoint/test.S
===================================================================
--- branches/v4/softs/tests_ccvcache_v4/test_breakpoint/test.S	(revision 371)
+++ branches/v4/softs/tests_ccvcache_v4/test_breakpoint/test.S	(revision 371)
@@ -0,0 +1,86 @@
+/*
+ * breakpoint test: check that a breakpoint generates an exception, and we can
+ * return 
+ */
+#include <registers.h>
+#include <misc.h>
+
+	.text
+	.globl  _start
+_start:
+	.set noreorder
+	la	k0, TTY_BASE
+	la	k1, EXIT_BASE
+	la	sp, 0x00400000 - 16
+
+	PRINT(startstr)
+
+	/* reset cop0 status (keep BEV) */
+	lui	a0, 0x0040;
+	mtc0	a0, COP0_STATUS
+	nop
+	nop
+	nop
+	break
+	bne a3, zero, exit
+	nop
+	/* we should not get there, a3 is not 0 */
+	EXIT(2)
+exit:
+	move	a0, v0
+	PRINTX
+	PUTCHAR(' ')
+	move	a0, v1
+	PRINTX
+	PUTCHAR('\n')
+	/* we should get there */
+	EXIT(0)
+
+	.globl excep
+excep:
+	.set noreorder
+	PRINT(statusstr)
+	mfc0	a0, COP0_STATUS
+	PRINTX
+
+	PRINT(causestr)
+	mfc0	a0, COP0_CAUSE
+	PRINTX
+
+	PRINT(pcstr)
+	mfc0	a0, COP0_EXPC
+	PRINTX
+
+	PRINT(badvastr)
+	mfc0	a0, COP_0_BADVADDR
+	PRINTX
+	PUTCHAR('\n')
+	mfc0	a0, COP0_EXPC
+	addiu	a0, a0, 4
+	mtc0	a0, COP0_EXPC
+	li	v0, MAGIC1
+	li	v1, MAGIC2
+	li	a3, 1
+	eret
+	nop
+
+#we should not end there
+	EXIT(1)
+
+	.rodata:
+statusstr: .ascii "status \0"
+causestr: .ascii " cause \0"
+pcstr: .ascii " pc \0"
+badvastr: .ascii " badva \0"
+startstr: .ascii "start\n\0"
+usrstr: .ascii "usrmode\n\0"
+
+	.org EXCEP_ADDRESS - BOOT_ADDRESS
+	.globl evect
+evect:
+	j	excep
+	nop
+	.data
+	.word MAGIC1
+testval:
+	.word MAGIC2
Index: branches/v4/softs/tests_ccvcache_v4/test_breakpoint_delayslot/Makefile
===================================================================
--- branches/v4/softs/tests_ccvcache_v4/test_breakpoint_delayslot/Makefile	(revision 371)
+++ branches/v4/softs/tests_ccvcache_v4/test_breakpoint_delayslot/Makefile	(revision 371)
@@ -0,0 +1,1 @@
+include ../Makefile.inc
Index: branches/v4/softs/tests_ccvcache_v4/test_breakpoint_delayslot/run
===================================================================
--- branches/v4/softs/tests_ccvcache_v4/test_breakpoint_delayslot/run	(revision 371)
+++ branches/v4/softs/tests_ccvcache_v4/test_breakpoint_delayslot/run	(revision 371)
@@ -0,0 +1,28 @@
+#!/bin/sh 
+
+. ../common/common.sh
+
+check_output()
+{
+	egrep "^status 0x00400002 cause 0x80000024 pc 0xBFC00034 badva 0x00000000$" run.out > /dev/null
+	if [ $? -ne 0 ]; then
+		echo "couldn't find string 1 in output - mtty not working ?" >> run.out
+		return 1
+	fi
+	return 0;
+}
+
+make --quiet || exit 1
+${SIMUL} > run.out 2>&1 
+if [ $? -eq 0 ]; then
+	if check_output; then
+		echo "test passsed";
+		make --quiet clean
+		exit 0;
+	fi
+	echo "test FAILED"
+	exit 1
+fi
+echo "test FAILED"
+exit 1
+
Index: branches/v4/softs/tests_ccvcache_v4/test_breakpoint_delayslot/test.S
===================================================================
--- branches/v4/softs/tests_ccvcache_v4/test_breakpoint_delayslot/test.S	(revision 371)
+++ branches/v4/softs/tests_ccvcache_v4/test_breakpoint_delayslot/test.S	(revision 371)
@@ -0,0 +1,85 @@
+/*
+ * breakpoint test: check that a breakpoint in a delay slot is properly handled
+ */
+#include <registers.h>
+#include <misc.h>
+
+	.text
+	.globl  _start
+_start:
+	.set noreorder
+	la	k0, TTY_BASE
+	la	k1, EXIT_BASE
+	la	sp, 0x00400000 - 16
+
+	PRINT(startstr)
+
+	/* reset cop0 status (keep BEV) */
+	lui	a0, 0x0040;
+	mtc0	a0, COP0_STATUS
+	nop
+	nop
+	nop
+	j	exit
+	break
+	nop
+	/* we should not get there, */
+	EXIT(2)
+	.globl exit
+exit:
+	move	a0, v0
+	PRINTX
+	PUTCHAR(' ')
+	move	a0, v1
+	PRINTX
+	PUTCHAR('\n')
+	/* we should get there */
+	EXIT(0)
+
+	.globl excep
+excep:
+	.set noreorder
+	PRINT(statusstr)
+	mfc0	a0, COP0_STATUS
+	PRINTX
+
+	PRINT(causestr)
+	mfc0	a0, COP0_CAUSE
+	PRINTX
+
+	PRINT(pcstr)
+	mfc0	a0, COP0_EXPC
+	PRINTX
+
+	PRINT(badvastr)
+	mfc0	a0, COP_0_BADVADDR
+	PRINTX
+	PUTCHAR('\n')
+	la	a0, exit
+	mtc0	a0, COP0_EXPC
+	li	v0, MAGIC1
+	li	v1, MAGIC2
+	li	a3, 1
+	eret
+	nop
+
+#we should not end there
+	EXIT(1)
+
+	.rodata:
+statusstr: .ascii "status \0"
+causestr: .ascii " cause \0"
+pcstr: .ascii " pc \0"
+badvastr: .ascii " badva \0"
+startstr: .ascii "start\n\0"
+usrstr: .ascii "usrmode\n\0"
+
+	.org EXCEP_ADDRESS - BOOT_ADDRESS
+	.globl evect
+evect:
+	j	excep
+	nop
+	.data
+	.word MAGIC1
+testval:
+	.word MAGIC2
Index: branches/v4/softs/tests_ccvcache_v4/test_dcache_inval_pa/Makefile
===================================================================
--- branches/v4/softs/tests_ccvcache_v4/test_dcache_inval_pa/Makefile	(revision 371)
+++ branches/v4/softs/tests_ccvcache_v4/test_dcache_inval_pa/Makefile	(revision 371)
@@ -0,0 +1,1 @@
+include ../Makefile.inc
Index: branches/v4/softs/tests_ccvcache_v4/test_dcache_inval_pa/mtty0
===================================================================
--- branches/v4/softs/tests_ccvcache_v4/test_dcache_inval_pa/mtty0	(revision 371)
+++ branches/v4/softs/tests_ccvcache_v4/test_dcache_inval_pa/mtty0	(revision 371)
@@ -0,0 +1,4 @@
+[20hstart
+mmu started before DMA 0x0000BEEF
+mmu started after DMA 0x0000F00D
+mmu started after FLUSH 0x0000F00D
Index: branches/v4/softs/tests_ccvcache_v4/test_dcache_inval_pa/run
===================================================================
--- branches/v4/softs/tests_ccvcache_v4/test_dcache_inval_pa/run	(revision 371)
+++ branches/v4/softs/tests_ccvcache_v4/test_dcache_inval_pa/run	(revision 371)
@@ -0,0 +1,38 @@
+#!/bin/sh 
+
+. ../common/common.sh
+
+check_output()
+{
+	egrep "^mmu started before DMA 0x0000BEEF$" run.out > /dev/null
+	if [ $? -ne 0 ]; then
+		echo "couldn't find string 1 in output - mtty not working ?" >> run.out
+		return 1
+	fi
+	egrep "^mmu started after DMA 0x0000F00D$" run.out > /dev/null
+	if [ $? -ne 0 ]; then
+		echo "couldn't find string 2 in output - mtty not working ?" >> run.out
+		return 1
+	fi
+	egrep "^mmu started after FLUSH 0x0000F00D$" run.out > /dev/null
+	if [ $? -ne 0 ]; then
+		echo "couldn't find string 3 in output - mtty not working ?" >> run.out
+		return 1
+	fi
+	return 0;
+}
+
+make --quiet || exit 1
+${SIMUL} > run.out 2>&1 
+if [ $? -eq 0 ]; then
+	if check_output; then
+		echo "test passsed";
+		make --quiet clean
+		exit 0;
+	fi
+	echo "test FAILED"
+	exit 1
+fi
+echo "test FAILED"
+exit 1
+
Index: branches/v4/softs/tests_ccvcache_v4/test_dcache_inval_pa/test.S
===================================================================
--- branches/v4/softs/tests_ccvcache_v4/test_dcache_inval_pa/test.S	(revision 371)
+++ branches/v4/softs/tests_ccvcache_v4/test_dcache_inval_pa/test.S	(revision 371)
@@ -0,0 +1,136 @@
+/*
+ * cache inval test: check that VC_DCACHE_INVAL_PA does the job
+ * on a cc_vcache, the cache invalidation/update should be done by hardware
+ * and VC_DCACHE_INVAL_PA should not be needed.
+ */
+#include <registers.h>
+#include <misc.h>
+#include <vcache.h>
+	.text
+	.globl  _start
+_start:
+	.set noreorder
+	la	k0, TTY_BASE
+	la	k1, EXIT_BASE
+
+	PRINT(startstr)
+
+	/* reset cop0 status (keep BEV) */
+	lui	a0, 0x0040;
+	mtc0	a0, COP0_STATUS
+
+	la	a0, pte1_a
+	srl	a0, a0, 13
+	mtc2	a0, VC_PTPR
+	nop
+
+	li	a0, VC_TLB_EN_ITLB | VC_TLB_EN_DTLB | VC_TLB_EN_ICACHE | VC_TLB_EN_DCACHE
+	mtc2 	a0, VC_TLB_EN
+
+	PRINT(mmustr_a)
+	la	t0, testval
+	lw 	a0, 0(t0);
+	PRINTX
+	PUTCHAR('\n')
+	la	a1, DMA_BASE
+	la	a0, testval2
+	sw	a0, DMA_SRC(a1)
+	la	a0, testval
+	sw	a0, DMA_DST(a1)
+	li	a0, 4
+	sw	a0, DMA_LEN(a1) /* start DMA */
+loop:
+	lw	a0, DMA_LEN(a1)
+	bne	a0, zero, loop;
+	nop
+
+	PRINT(mmustr_b)
+	la	t0, testval
+	lw 	a0, 0(t0);
+	PRINTX
+	PUTCHAR('\n')
+
+	la      a0, testval
+	mtc2	a0, VC_DATA_LO
+	mtc2	zero, VC_DATA_HI
+	mtc2	zero, VC_DCACHE_INVAL_PA
+	nop
+
+	PRINT(mmustr_c)
+	la	t0, testval
+	lw 	a0, 0(t0);
+	PRINTX
+	PUTCHAR('\n')
+
+	/* we should get there */
+	EXIT(0)
+
+	.globl excep
+excep:
+	.set noreorder
+	PRINT(statusstr)
+	mfc0	a0, COP0_STATUS
+	PRINTX
+
+	PRINT(causestr)
+	mfc0	a0, COP0_CAUSE
+	PRINTX
+
+	PRINT(pcstr)
+	mfc0	a0, COP0_EXPC
+	PRINTX
+
+	PRINT(badvastr)
+	mfc0	a0, COP_0_BADVADDR
+	PRINTX
+
+	PUTCHAR('\n')
+	/* we should not get there */
+	EXIT(3)
+
+	.rodata:
+statusstr: .ascii "status \0"
+causestr: .ascii " cause \0"
+pcstr: .ascii " pc \0"
+badvastr: .ascii " badva \0"
+mmustr_a: .ascii "mmu started before DMA \0"
+mmustr_b: .ascii "mmu started after DMA \0"
+mmustr_c: .ascii "mmu started after FLUSH \0"
+startstr: .ascii "start\n\0"
+
+	.org EXCEP_ADDRESS - BOOT_ADDRESS
+	.globl evect
+evect:
+	j	excep
+	nop
+
+	.data
+data_a:
+	.word MAGIC1
+testval:
+	.word MAGIC2
+data_b:
+	.word MAGIC3
+testval2:
+	.word MAGIC4
+	.globl pte2_a
+
+pte2_a:
+	.align 12
+	.word PTE2_V | PTE2_C | PTE2_X
+	.word 0x0000 >> 12 /* check real value of data_a */
+	.org pte2_a + 4092
+	.word 0
+	.globl pte1_a
+pte1_a:
+	.align 13
+	.word PTE1_V | PTE1_C | PTE1_W | 0x0 /* map PA 0 at VA 0 */
+	.word PTE1_V | PTE1_T | (0x2000 >> 12) /* map PA 0x0 at VA 0x00200000 via pte2_a */
+	.org pte1_a + (BOOT_ADDRESS >> 21) * 4
+	.word PTE1_V | PTE1_C | PTE1_X | (BOOT_ADDRESS >> 21) /* map PA 0xbfc00000 at VA 0xbfc00000 */
+	.org pte1_a + (TTY_BASE >> 21) * 4
+	.word PTE1_V | PTE1_W | (TTY_BASE >> 21) /* map PA 0xd0200000 at VA 0xd0200000 */
+	.org pte1_a + (EXIT_BASE >> 21) * 4
+	.word PTE1_V | PTE1_W | (EXIT_BASE >> 21) /* map PA 0xe0000000 at VA 0xe0000000 */
+	.org pte1_a + (DMA_BASE >> 21) * 4
+	.word PTE1_V | PTE1_W | (DMA_BASE >> 21) /* map PA 0xe8000000 at VA 0xe0000000 */
Index: branches/v4/softs/tests_ccvcache_v4/test_dma_basic/Makefile
===================================================================
--- branches/v4/softs/tests_ccvcache_v4/test_dma_basic/Makefile	(revision 371)
+++ branches/v4/softs/tests_ccvcache_v4/test_dma_basic/Makefile	(revision 371)
@@ -0,0 +1,1 @@
+include ../Makefile.inc
Index: branches/v4/softs/tests_ccvcache_v4/test_dma_basic/mtty0
===================================================================
--- branches/v4/softs/tests_ccvcache_v4/test_dma_basic/mtty0	(revision 371)
+++ branches/v4/softs/tests_ccvcache_v4/test_dma_basic/mtty0	(revision 371)
@@ -0,0 +1,2 @@
+[20hbefore DMA 0x0000BEEF 0x0000F00D
+after DMA 0x0000F00D 0x0000F00D 0x0000BEEF 0x0000DEAD 0x0000DEAD
Index: branches/v4/softs/tests_ccvcache_v4/test_dma_basic/run
===================================================================
--- branches/v4/softs/tests_ccvcache_v4/test_dma_basic/run	(revision 371)
+++ branches/v4/softs/tests_ccvcache_v4/test_dma_basic/run	(revision 371)
@@ -0,0 +1,28 @@
+#!/bin/sh 
+
+. ../common/common.sh
+
+check_output()
+{
+	egrep "^after DMA 0x0000F00D 0x0000F00D 0x0000BEEF 0x0000DEAD 0x0000DEAD$" run.out > /dev/null
+	if [ $? -eq 0 ]; then
+		return 0;
+	fi
+	echo "couldn't find string in output - mtty not working ?" >> run.out
+	return 1
+}
+
+make --quiet || exit 1
+${SIMUL} > run.out 2>&1 
+if [ $? -eq 0 ]; then
+	if check_output; then
+		echo "test passsed";
+		make --quiet clean
+		exit 0;
+	fi
+	echo "test FAILED"
+	exit 1
+fi
+echo "test FAILED"
+exit 1
+
Index: branches/v4/softs/tests_ccvcache_v4/test_dma_basic/test.S
===================================================================
--- branches/v4/softs/tests_ccvcache_v4/test_dma_basic/test.S	(revision 371)
+++ branches/v4/softs/tests_ccvcache_v4/test_dma_basic/test.S	(revision 371)
@@ -0,0 +1,135 @@
+/*
+ * basic DMA check: check that the DMA engine works and and doens't
+ * clobbers memory
+ */
+#include <registers.h>
+#include <misc.h>
+#include <vcache.h>
+	.text
+	.globl  _start
+_start:
+	.set noreorder
+	la	k0, TTY_BASE
+	la	k1, EXIT_BASE
+
+	PRINT(mmustr_a)
+
+	/* reset cop0 status (keep BEV) */
+	lui	a0, 0x0040;
+	mtc0	a0, COP0_STATUS
+
+	la	t0, testval
+	lw 	a0, 0(t0);
+	PRINTX
+	PUTCHAR(' ')
+	la	t0, testval2
+	lw 	a0, 0(t0);
+	PRINTX
+	PUTCHAR('\n')
+	la	t0, testval
+	la	t1, testval3
+	lw 	a0, 0(t0);
+	sw	a0, 0(t1)
+
+	la	a1, DMA_BASE
+	la	a0, tstsrc
+	sw	a0, DMA_SRC(a1)
+	la	a0, tstdst
+	sw	a0, DMA_DST(a1)
+	la	a0, 0x18
+	sw	a0, DMA_LEN(a1) /* start DMA */
+loop:
+	lw	a0, DMA_LEN(a1)
+	bne	a0, zero, loop;
+	nop
+	sw	a0, DMA_RESET(a1) /* reset DMA */
+
+	la	a0, testval2
+	sw	a0, DMA_SRC(a1)
+	la	a0, testval 
+	sw	a0, DMA_DST(a1)
+	la	a0, 0x4
+	sw	a0, DMA_LEN(a1) /* start DMA */
+loop2:
+	lw	a0, DMA_LEN(a1)
+	bne	a0, zero, loop2;
+	nop
+	sw	a0, DMA_RESET(a1) /* reset DMA */
+
+	PRINT(mmustr_b)
+	la	t0, testval
+	lw 	a0, 0(t0);
+	PRINTX
+	PUTCHAR(' ')
+	la	t0, testval2
+	lw 	a0, 0(t0);
+	PRINTX
+	PUTCHAR(' ')
+	la	t0, testval3
+	lw 	a0, 0(t0);
+	PRINTX
+	PUTCHAR(' ')
+	la	t0, tstsrc
+	lw 	a0, 0(t0);
+	PRINTX
+	PUTCHAR(' ')
+	la	t0, tstdst
+	lw 	a0, 0(t0);
+	PRINTX
+	PUTCHAR('\n')
+
+	/* we should get there */
+	EXIT(0)
+
+	.globl excep
+excep:
+	.set noreorder
+	PRINT(statusstr)
+	mfc0	a0, COP0_STATUS
+	PRINTX
+
+	PRINT(causestr)
+	mfc0	a0, COP0_CAUSE
+	PRINTX
+
+	PRINT(pcstr)
+	mfc0	a0, COP0_EXPC
+	PRINTX
+
+	PRINT(badvastr)
+	mfc0	a0, COP_0_BADVADDR
+	PRINTX
+
+	PUTCHAR('\n')
+	/* we should not get there */
+	EXIT(3)
+
+	.rodata:
+statusstr: .ascii "status \0"
+causestr: .ascii " cause \0"
+pcstr: .ascii " pc \0"
+badvastr: .ascii " badva \0"
+mmustr_a: .ascii "before DMA \0"
+mmustr_b: .ascii "after DMA \0"
+startstr: .ascii "start\n\0"
+
+	.org EXCEP_ADDRESS - BOOT_ADDRESS
+	.globl evect
+evect:
+	j	excep
+	nop
+
+	.data
+testval:
+	.word MAGIC2
+testval2:
+	.word MAGIC4
+testval3:
+	.word MAGIC4
+tstdst:
+	.word 0
+	.org 0x1000
+	.word 0
+tstsrc:
+	.word MAGIC1
+
Index: branches/v4/softs/tests_ccvcache_v4/test_dma_unaligned/Makefile
===================================================================
--- branches/v4/softs/tests_ccvcache_v4/test_dma_unaligned/Makefile	(revision 371)
+++ branches/v4/softs/tests_ccvcache_v4/test_dma_unaligned/Makefile	(revision 371)
@@ -0,0 +1,1 @@
+include ../Makefile.inc
Index: branches/v4/softs/tests_ccvcache_v4/test_dma_unaligned/run
===================================================================
--- branches/v4/softs/tests_ccvcache_v4/test_dma_unaligned/run	(revision 371)
+++ branches/v4/softs/tests_ccvcache_v4/test_dma_unaligned/run	(revision 371)
@@ -0,0 +1,28 @@
+#!/bin/sh 
+
+. ../common/common.sh
+
+check_output()
+{
+	egrep "^after DMA this is the test string unaligned and more than 64 chars long abcdefghijklmnopqrstuvwxyz ABCDEFGHIJKLMNOPQRSTUVWXYZ 123456789      abcdefghijklmnopqrstuvwxyz$" run.out > /dev/null
+	if [ $? -eq 0 ]; then
+		return 0;
+	fi
+	echo "couldn't find string in output - mtty not working ?" >> run.out
+	return 1
+}
+
+make --quiet || exit 1
+${SIMUL} > run.out 2>&1 
+if [ $? -eq 0 ]; then
+	if check_output; then
+		echo "test passsed";
+		make --quiet clean
+		exit 0;
+	fi
+	echo "test FAILED"
+	exit 1
+fi
+echo "test FAILED"
+exit 1
+
Index: branches/v4/softs/tests_ccvcache_v4/test_dma_unaligned/test.S
===================================================================
--- branches/v4/softs/tests_ccvcache_v4/test_dma_unaligned/test.S	(revision 371)
+++ branches/v4/softs/tests_ccvcache_v4/test_dma_unaligned/test.S	(revision 371)
@@ -0,0 +1,96 @@
+/*
+ * basic DMA check: check that the DMA engine works and and doens't
+ * clobbers memory
+ */
+#include <registers.h>
+#include <misc.h>
+#include <vcache.h>
+	.text
+	.globl  _start
+_start:
+	.set noreorder
+	la	k0, TTY_BASE
+	la	k1, EXIT_BASE
+
+	PRINT(mmustr_a)
+
+	/* reset cop0 status (keep BEV) */
+	lui	a0, 0x0040;
+	mtc0	a0, COP0_STATUS
+
+	la	t0, tstdst
+	sw 	zero, 0(t0);
+	PRINT(tstdst)
+	PUTCHAR('E')
+	PUTCHAR('\n')
+
+	la	a1, DMA_BASE
+	la	a0, tstsrc
+	sw	a0, DMA_SRC(a1)
+	la	a0, tstdst
+	sw	a0, DMA_DST(a1)
+	la	a0, 160 #strlen(tstsrc)
+	sw	a0, DMA_LEN(a1) /* start DMA */
+loop:
+	lw	a0, DMA_LEN(a1)
+	bne	a0, zero, loop;
+	nop
+
+	PRINT(mmustr_b)
+	PRINT(tstdst)
+
+	/* we should get there */
+	EXIT(0)
+
+	.globl excep
+excep:
+	.set noreorder
+	PRINT(statusstr)
+	mfc0	a0, COP0_STATUS
+	PRINTX
+
+	PRINT(causestr)
+	mfc0	a0, COP0_CAUSE
+	PRINTX
+
+	PRINT(pcstr)
+	mfc0	a0, COP0_EXPC
+	PRINTX
+
+	PRINT(badvastr)
+	mfc0	a0, COP_0_BADVADDR
+	PRINTX
+
+	PUTCHAR('\n')
+	/* we should not get there */
+	EXIT(3)
+
+	.rodata:
+statusstr: .ascii "status \0"
+causestr: .ascii " cause \0"
+pcstr: .ascii " pc \0"
+badvastr: .ascii " badva \0"
+mmustr_a: .ascii "before DMA \0"
+mmustr_b: .ascii "after DMA \0"
+startstr: .ascii "start\n\0"
+
+	.org EXCEP_ADDRESS - BOOT_ADDRESS
+	.globl evect
+evect:
+	j	excep
+	nop
+
+	.data
+testval:
+	.word MAGIC2
+testval2:
+	.word MAGIC4
+testval3:
+	.word MAGIC4
+tstdst:
+	.word 0
+	.org 0x1000
+testval4:
+	.word MAGIC1
+tstsrc:
+	.ascii "this is the test string unaligned and more than 64 chars long abcdefghijklmnopqrstuvwxyz ABCDEFGHIJKLMNOPQRSTUVWXYZ 123456789      abcdefghijklmnopqrstuvwxyz\n\0"
Index: branches/v4/softs/tests_ccvcache_v4/test_dtlb_inval/Makefile
===================================================================
--- branches/v4/softs/tests_ccvcache_v4/test_dtlb_inval/Makefile	(revision 371)
+++ branches/v4/softs/tests_ccvcache_v4/test_dtlb_inval/Makefile	(revision 371)
@@ -0,0 +1,1 @@
+include ../Makefile.inc
Index: branches/v4/softs/tests_ccvcache_v4/test_dtlb_inval/mtty0
===================================================================
--- branches/v4/softs/tests_ccvcache_v4/test_dtlb_inval/mtty0	(revision 371)
+++ branches/v4/softs/tests_ccvcache_v4/test_dtlb_inval/mtty0	(revision 371)
@@ -0,0 +1,2 @@
+[20hstart
+mmu started 0x0000BEEF status 0x00400002 cause 0x0000001C pc 0xBFC00080 badva 0x00200004
Index: branches/v4/softs/tests_ccvcache_v4/test_dtlb_inval/run
===================================================================
--- branches/v4/softs/tests_ccvcache_v4/test_dtlb_inval/run	(revision 371)
+++ branches/v4/softs/tests_ccvcache_v4/test_dtlb_inval/run	(revision 371)
@@ -0,0 +1,28 @@
+#!/bin/sh 
+
+.  ../common/common.sh
+
+check_output()
+{
+	egrep "^mmu started 0x0000BEEF status 0x00400002 cause 0x0000001C pc 0xBFC00080 badva 0x00200004$" run.out > /dev/null
+	if [ $? -ne 0 ]; then
+		echo "couldn't find string in output - mtty not working ?" >> run.out
+		return 1
+	fi
+	return 0;
+}
+
+make --quiet || exit 1
+${SIMUL} > run.out 2>&1 
+if [ $? -eq 0 ]; then
+	if check_output; then
+		echo "test passsed";
+		make --quiet clean
+		exit 0;
+	fi
+	echo "test FAILED"
+	exit 1
+fi
+echo "test FAILED"
+exit 1
+
Index: branches/v4/softs/tests_ccvcache_v4/test_dtlb_inval/test.S
===================================================================
--- branches/v4/softs/tests_ccvcache_v4/test_dtlb_inval/test.S	(revision 371)
+++ branches/v4/softs/tests_ccvcache_v4/test_dtlb_inval/test.S	(revision 371)
@@ -0,0 +1,117 @@
+/*
+ * dtlb inval: a write to VC_DTLB_INVAL should invalidate the corresponding
+ * dtlb entry. On a ccvcache, VC_DTLB_INVAL should not be needed, and
+ * the first access after clearing pte2_a should fail
+ */
+#include <registers.h>
+#include <misc.h>
+#include <vcache.h>
+	.text
+	.globl  _start
+_start:
+	.set noreorder
+	la	k0, TTY_BASE
+	la	k1, EXIT_BASE
+
+	PRINT(startstr)
+
+	/* reset cop0 status (keep BEV) */
+	lui	a0, 0x0040;
+	mtc0	a0, COP0_STATUS
+
+	la	a0, pte1_a
+	srl	a0, a0, 13
+	mtc2	a0, VC_PTPR
+	nop
+
+	li	a0, VC_TLB_EN_ITLB | VC_TLB_EN_DTLB | VC_TLB_EN_ICACHE | VC_TLB_EN_DCACHE
+	mtc2 	a0, VC_TLB_EN
+
+	PRINT(mmustr)
+	la	t0, testval + 0x00200000
+	lw 	a0, 0(t0);
+	PRINTX
+	PUTCHAR(' ')
+	la 	a0, pte2_a
+	sw	zero, 0(a0) /* invalidate PTE2 entry */
+	sync
+	la	t0, testval + 0x00200000
+	lw 	a0, 0(t0); /* TLB entry not invalidated yet, we can do this */
+	PRINTX
+	PUTCHAR('\n')
+	la	t0, testval + 0x00200000
+	mtc2	t0, VC_DTLB_INVAL /* invalidate VA */
+	lw 	a0, 0(t0); /* now this should fail */
+	PRINTX
+	PUTCHAR('\n')
+
+	/* we should not get there */
+	EXIT(1)
+
+	.globl excep
+excep:
+	.set noreorder
+	PRINT(statusstr)
+	mfc0	a0, COP0_STATUS
+	PRINTX
+
+	PRINT(causestr)
+	mfc0	a0, COP0_CAUSE
+	PRINTX
+
+	PRINT(pcstr)
+	mfc0	a0, COP0_EXPC
+	PRINTX
+
+	PRINT(badvastr)
+	mfc0	a0, COP_0_BADVADDR
+	PRINTX
+
+	PUTCHAR('\n')
+	/* we should get there */
+	EXIT(0)
+
+	.rodata:
+statusstr: .ascii "status \0"
+causestr: .ascii " cause \0"
+pcstr: .ascii " pc \0"
+badvastr: .ascii " badva \0"
+mmustr: .ascii "mmu started \0"
+startstr: .ascii "start\n\0"
+
+	.org EXCEP_ADDRESS - BOOT_ADDRESS
+	.globl evect
+evect:
+	j	excep
+	nop
+
+	.data
+	/* first 2 pages is data that will be switched my mmu switch */
+data_a:
+	.word MAGIC1
+testval:
+	.word MAGIC2
+	.globl pte2_a
+/*
+ * one PD with a level 2 PTP: we invalidate an entry in the PTP and
+ * check that the VA is no longer accessible
+ */
+pte2_a:
+	.align 12
+	.word PTE2_V | PTE2_C | PTE2_X
+	.word 0x0000 >> 12 /* check real value of data_a */
+	.org pte2_a + 4092
+	.word 0
+	.globl pte2_b
+	.globl pte1_a
+pte1_a:
+	.align 13
+	.word PTE1_V | PTE1_C | PTE1_W | 0x0 /* map PA 0 at VA 0 */
+	.word PTE1_V | PTE1_T | (0x1000 >> 12) /* map PA 0x0 at VA 0x00200000 via pte2_a */
+	.org pte1_a + (BOOT_ADDRESS >> 21) * 4
+	.word PTE1_V | PTE1_C | PTE1_X | (BOOT_ADDRESS >> 21) /* map PA 0xbfc00000 at VA 0xbfc00000 */
+	.org pte1_a + (TTY_BASE >> 21) * 4
+	.word PTE1_V | PTE1_W | (TTY_BASE >> 21) /* map PA 0xd0200000 at VA 0xd0200000 */
+	.org pte1_a + (EXIT_BASE >> 21) * 4
+	.word PTE1_V | PTE1_W | (EXIT_BASE >> 21) /* map PA 0xe0000000 at VA 0xe0000000 */
+	.org pte1_a + 8192
Index: branches/v4/softs/tests_ccvcache_v4/test_dtlb_inval2/Makefile
===================================================================
--- branches/v4/softs/tests_ccvcache_v4/test_dtlb_inval2/Makefile	(revision 371)
+++ branches/v4/softs/tests_ccvcache_v4/test_dtlb_inval2/Makefile	(revision 371)
@@ -0,0 +1,1 @@
+include ../Makefile.inc
Index: branches/v4/softs/tests_ccvcache_v4/test_dtlb_inval2/run
===================================================================
--- branches/v4/softs/tests_ccvcache_v4/test_dtlb_inval2/run	(revision 371)
+++ branches/v4/softs/tests_ccvcache_v4/test_dtlb_inval2/run	(revision 371)
@@ -0,0 +1,28 @@
+#!/bin/sh 
+
+. ../common/common.sh
+
+check_output()
+{
+	egrep "^mmu started 0x0000BEEF 0x0000DEAD$" run.out > /dev/null
+	if [ $? -ne 0 ]; then
+		echo "couldn't find string in output - mtty not working ?" >> run.out
+		return 1
+	fi
+	return 0;
+}
+
+make --quiet || exit 1
+${SIMUL} > run.out 2>&1 
+if [ $? -eq 0 ]; then
+	if check_output; then
+		echo "test passsed";
+		make --quiet clean
+		exit 0;
+	fi
+	echo "test FAILED"
+	exit 1
+fi
+echo "test FAILED"
+exit 1
+
Index: branches/v4/softs/tests_ccvcache_v4/test_dtlb_inval2/test.S
===================================================================
--- branches/v4/softs/tests_ccvcache_v4/test_dtlb_inval2/test.S	(revision 371)
+++ branches/v4/softs/tests_ccvcache_v4/test_dtlb_inval2/test.S	(revision 371)
@@ -0,0 +1,121 @@
+/*
+ * dtlb inval: a write to a PTE2 should invalidate the corresponding
+ * dtlb entry. 
+ */
+#include <registers.h>
+#include <misc.h>
+#include <vcache.h>
+	.text
+	.globl  _start
+_start:
+	.set noreorder
+	la	k0, TTY_BASE
+	la	k1, EXIT_BASE
+
+	PRINT(startstr)
+
+	/* reset cop0 status (keep BEV) */
+	lui	a0, 0x0040;
+	mtc0	a0, COP0_STATUS
+
+	la	a0, pte1_a
+	srl	a0, a0, 13
+	mtc2	a0, VC_PTPR
+	nop
+
+	li	a0, VC_TLB_EN_ITLB | VC_TLB_EN_DTLB | VC_TLB_EN_ICACHE | VC_TLB_EN_DCACHE
+	mtc2 	a0, VC_TLB_EN
+
+	PRINT(mmustr)
+	la	t0, testval + 0x00200000
+	lw 	a0, 0(t0);
+	PRINTX
+	PUTCHAR(' ')
+	la 	t0, pte2_a
+	la	a0, 0x1000 >> 12 
+	sw	a0, 4(t0) /* swap PTE2 entry */
+1:
+	ll	a0, 0(t0)
+	la	a0, PTE2_V | PTE2_C | PTE2_X
+	sc	a0, 0(t0)
+	beqz	a0, 1b
+	nop
+
+	la	t0, testval + 0x00200000
+	lw 	a0, 0(t0); /* should get MAGIC1 */
+	PRINTX
+	PUTCHAR('\n')
+
+	/* we should get there */
+	EXIT(0)
+
+	.globl excep
+excep:
+	.set noreorder
+	PRINT(statusstr)
+	mfc0	a0, COP0_STATUS
+	PRINTX
+
+	PRINT(causestr)
+	mfc0	a0, COP0_CAUSE
+	PRINTX
+
+	PRINT(pcstr)
+	mfc0	a0, COP0_EXPC
+	PRINTX
+
+	PRINT(badvastr)
+	mfc0	a0, COP_0_BADVADDR
+	PRINTX
+
+	PUTCHAR('\n')
+	/* we should not get there */
+	EXIT(1)
+
+	.rodata:
+statusstr: .ascii "status \0"
+causestr: .ascii " cause \0"
+pcstr: .ascii " pc \0"
+badvastr: .ascii " badva \0"
+mmustr: .ascii "mmu started \0"
+startstr: .ascii "start\n\0"
+
+	.org EXCEP_ADDRESS - BOOT_ADDRESS
+	.globl evect
+evect:
+	j	excep
+	nop
+
+	.data
+	/* first 2 pages is data that will be switched my mmu switch */
+data_a:
+	.word MAGIC1
+testval:
+	.word MAGIC2
+	.align 12
+	.word MAGIC2
+	.word MAGIC1
+	.globl pte2_a
+/*
+ * one PD with a level 2 PTP: we switch an entry in the PTP and
+ * check that the dtlb is invalidated
+ */
+pte2_a:
+	.align 12
+	.word PTE2_V | PTE2_C | PTE2_X
+	.word 0x0000 >> 12 /* check real value of data_a */
+	.org pte2_a + 4092
+	.word 0
+	.globl pte2_b
+	.globl pte1_a
+pte1_a:
+	.align 13
+	.word PTE1_V | PTE1_C | PTE1_W | 0x0 /* map PA 0 at VA 0 */
+	.word PTE1_V | PTE1_T | (0x2000 >> 12) /* map PA 0x0 at VA 0x00200000 via pte2_a */
+	.org pte1_a + (BOOT_ADDRESS >> 21) * 4
+	.word PTE1_V | PTE1_C | PTE1_X | (BOOT_ADDRESS >> 21) /* map PA 0xbfc00000 at VA 0xbfc00000 */
+	.org pte1_a + (TTY_BASE >> 21) * 4
+	.word PTE1_V | PTE1_W | (TTY_BASE >> 21) /* map PA 0xd0200000 at VA 0xd0200000 */
+	.org pte1_a + (EXIT_BASE >> 21) * 4
+	.word PTE1_V | PTE1_W | (EXIT_BASE >> 21) /* map PA 0xe0000000 at VA 0xe0000000 */
+	.org pte1_a + 8192
Index: branches/v4/softs/tests_ccvcache_v4/test_dtlb_inval3/Makefile
===================================================================
--- branches/v4/softs/tests_ccvcache_v4/test_dtlb_inval3/Makefile	(revision 371)
+++ branches/v4/softs/tests_ccvcache_v4/test_dtlb_inval3/Makefile	(revision 371)
@@ -0,0 +1,1 @@
+include ../Makefile.inc
Index: branches/v4/softs/tests_ccvcache_v4/test_dtlb_inval3/run
===================================================================
--- branches/v4/softs/tests_ccvcache_v4/test_dtlb_inval3/run	(revision 371)
+++ branches/v4/softs/tests_ccvcache_v4/test_dtlb_inval3/run	(revision 371)
@@ -0,0 +1,28 @@
+#!/bin/sh 
+
+. ../common/common.sh
+
+check_output()
+{
+	egrep "mmu started 0x0000BEEF 0xAC400000 0x0000900D status 0x00400002 cause 0x0000001C pc 0xBFC000D4 badva 0x00200004" run.out > /dev/null
+	if [ $? -ne 0 ]; then
+		echo "couldn't find string in output - mtty not working ?" >> run.out
+		return 1
+	fi
+	return 0;
+}
+
+make --quiet || exit 1
+${SIMUL} > run.out 2>&1 
+if [ $? -eq 0 ]; then
+	if check_output; then
+		echo "test passsed";
+		make --quiet clean
+		exit 0;
+	fi
+	echo "test FAILED"
+	exit 1
+fi
+echo "test FAILED"
+exit 1
+
Index: branches/v4/softs/tests_ccvcache_v4/test_dtlb_inval3/test.S
===================================================================
--- branches/v4/softs/tests_ccvcache_v4/test_dtlb_inval3/test.S	(revision 371)
+++ branches/v4/softs/tests_ccvcache_v4/test_dtlb_inval3/test.S	(revision 371)
@@ -0,0 +1,128 @@
+/*
+ * dtlb inval: a write to a PTE2 should invalidate the corresponding
+ * dtlb entry. Check that this is true is we change only the write flag
+ */
+#include <registers.h>
+#include <misc.h>
+#include <vcache.h>
+	.text
+	.globl  _start
+_start:
+	.set noreorder
+	la	k0, TTY_BASE
+	la	k1, EXIT_BASE
+
+	PRINT(startstr)
+
+	/* reset cop0 status (keep BEV) */
+	lui	a0, 0x0040;
+	mtc0	a0, COP0_STATUS
+
+	la	a0, pte1_a
+	srl	a0, a0, 13
+	mtc2	a0, VC_PTPR
+	nop
+
+	li	a0, VC_TLB_EN_ITLB | VC_TLB_EN_DTLB | VC_TLB_EN_ICACHE | VC_TLB_EN_DCACHE
+	mtc2 	a0, VC_TLB_EN
+
+	PRINT(mmustr)
+	la	t0, testval + 0x00200000
+	lw 	a0, 0(t0);
+	PRINTX
+	PUTCHAR(' ')
+	la	t0, testval + 0x00200000
+	la	a0, MAGIC3
+	sw	a0, 0(t0)
+	la 	t0, pte2_a
+1:
+	ll	a0, 0(t0)
+	la	a1, ~PTE2_W
+	and	a1, a0, a1
+	sc	a1, 0(t0)
+	beqz	a1, 1b
+	nop
+	PRINTX
+	PUTCHAR(' ')
+
+	la	t0, testval + 0x00200000
+	lw 	a0, 0(t0); /* should get MAGIC3 */
+	PRINTX
+	PUTCHAR(' ')
+	la	t0, testval + 0x00200000
+	la	a0, MAGIC1
+	sw	a0, 0(t0)
+
+	/* we should not get there */
+	EXIT(1)
+
+	.globl excep
+excep:
+	.set noreorder
+	PRINT(statusstr)
+	mfc0	a0, COP0_STATUS
+	PRINTX
+
+	PRINT(causestr)
+	mfc0	a0, COP0_CAUSE
+	PRINTX
+
+	PRINT(pcstr)
+	mfc0	a0, COP0_EXPC
+	PRINTX
+
+	PRINT(badvastr)
+	mfc0	a0, COP_0_BADVADDR
+	PRINTX
+
+	PUTCHAR('\n')
+	/* we should get there */
+	EXIT(0)
+
+	.rodata:
+statusstr: .ascii "status \0"
+causestr: .ascii " cause \0"
+pcstr: .ascii " pc \0"
+badvastr: .ascii " badva \0"
+mmustr: .ascii "mmu started \0"
+startstr: .ascii "start\n\0"
+
+	.org EXCEP_ADDRESS - BOOT_ADDRESS
+	.globl evect
+evect:
+	j	excep
+	nop
+
+	.data
+	/* first 2 pages is data that will be switched my mmu switch */
+data_a:
+	.word MAGIC1
+testval:
+	.word MAGIC2
+	.align 12
+	.word MAGIC2
+	.word MAGIC1
+	.globl pte2_a
+/*
+ * one PD with a level 2 PTP: we switch an entry in the PTP and
+ * check that the dtlb is invalidated
+ */
+pte2_a:
+	.align 12
+	.word PTE2_V | PTE2_C | PTE2_W
+	.word 0x0000 >> 12 /* check real value of data_a */
+	.org pte2_a + 4092
+	.word 0
+	.globl pte2_b
+	.globl pte1_a
+pte1_a:
+	.align 13
+	.word PTE1_V | PTE1_C | PTE1_W | 0x0 /* map PA 0 at VA 0 */
+	.word PTE1_V | PTE1_T | (0x2000 >> 12) /* map PA 0x0 at VA 0x00200000 via pte2_a */
+	.org pte1_a + (BOOT_ADDRESS >> 21) * 4
+	.word PTE1_V | PTE1_C | PTE1_X | (BOOT_ADDRESS >> 21) /* map PA 0xbfc00000 at VA 0xbfc00000 */
+	.org pte1_a + (TTY_BASE >> 21) * 4
+	.word PTE1_V | PTE1_W | (TTY_BASE >> 21) /* map PA 0xd0200000 at VA 0xd0200000 */
+	.org pte1_a + (EXIT_BASE >> 21) * 4
+	.word PTE1_V | PTE1_W | (EXIT_BASE >> 21) /* map PA 0xe0000000 at VA 0xe0000000 */
+	.org pte1_a + 8192
Index: branches/v4/softs/tests_ccvcache_v4/test_dtlb_ptprinval/Makefile
===================================================================
--- branches/v4/softs/tests_ccvcache_v4/test_dtlb_ptprinval/Makefile	(revision 371)
+++ branches/v4/softs/tests_ccvcache_v4/test_dtlb_ptprinval/Makefile	(revision 371)
@@ -0,0 +1,1 @@
+include ../Makefile.inc
Index: branches/v4/softs/tests_ccvcache_v4/test_dtlb_ptprinval/run
===================================================================
--- branches/v4/softs/tests_ccvcache_v4/test_dtlb_ptprinval/run	(revision 371)
+++ branches/v4/softs/tests_ccvcache_v4/test_dtlb_ptprinval/run	(revision 371)
@@ -0,0 +1,33 @@
+#!/bin/sh 
+
+. ../common/common.sh
+
+check_output()
+{
+	egrep "^mmu started ptpr_b 0x0000F00D$" run.out > /dev/null
+	if [ $? -ne 0 ]; then
+		echo "couldn't find string 1 in output - mtty not working ?" >> run.out
+		return 1
+	fi
+	egrep "^mmu started ptpr_a 0x0000BEEF$" run.out > /dev/null
+	if [ $? -ne 0 ]; then
+		echo "couldn't find string 2 in output - mtty not working ?" >> run.out
+		return 1
+	fi
+	return 0;
+}
+
+make --quiet || exit 1
+${SIMUL} > run.out 2>&1 
+if [ $? -eq 0 ]; then
+	if check_output; then
+		echo "test passsed";
+		make --quiet clean
+		exit 0;
+	fi
+	echo "test FAILED"
+	exit 1
+fi
+echo "test FAILED"
+exit 1
+
Index: branches/v4/softs/tests_ccvcache_v4/test_dtlb_ptprinval/test.S
===================================================================
--- branches/v4/softs/tests_ccvcache_v4/test_dtlb_ptprinval/test.S	(revision 371)
+++ branches/v4/softs/tests_ccvcache_v4/test_dtlb_ptprinval/test.S	(revision 371)
@@ -0,0 +1,145 @@
+/*
+ * dtlb inval on PTPR write: check that no stale entry exists in the dtlb
+ * after MMU context swicth
+ */
+#include <registers.h>
+#include <misc.h>
+#include <vcache.h>
+	.text
+	.globl  _start
+_start:
+	.set noreorder
+	la	k0, TTY_BASE
+	la	k1, EXIT_BASE
+
+	PRINT(startstr)
+
+	/* reset cop0 status (keep BEV) */
+	lui	a0, 0x0040;
+	mtc0	a0, COP0_STATUS
+
+	la	a0, pte1_b
+	srl	a0, a0, 13
+	mtc2	a0, VC_PTPR	# PTPR <= pte1_b
+	nop
+
+	li	a0, VC_TLB_EN_ITLB | VC_TLB_EN_DTLB | VC_TLB_EN_ICACHE | VC_TLB_EN_DCACHE
+	mtc2 	a0, VC_TLB_EN
+
+	PRINT(mmustr_b)
+	la	t0, testval + 0x00200000
+	lw 	a0, 0(t0);
+	PRINTX			# print MAGIC3
+	PUTCHAR('\n')
+
+	la	a0, pte1_a
+	srl	a0, a0, 13
+	mtc2	a0, VC_PTPR	# PTPR <= pte1_a
+	nop
+	PRINT(mmustr_a)
+	la	t0, testval + 0x00200000
+	lw 	a0, 0(t0);
+	PRINTX			# print MAGIC1
+	PUTCHAR('\n')
+
+	/* we should get there */
+	EXIT(0)
+
+	.globl excep
+excep:
+	.set noreorder
+	PRINT(statusstr)
+	mfc0	a0, COP0_STATUS
+	PRINTX
+
+	PRINT(causestr)
+	mfc0	a0, COP0_CAUSE
+	PRINTX
+
+	PRINT(pcstr)
+	mfc0	a0, COP0_EXPC
+	PRINTX
+
+	PRINT(badvastr)
+	mfc0	a0, COP_0_BADVADDR
+	PRINTX
+
+	PUTCHAR('\n')
+	/* we should not get there */
+	EXIT(3)
+
+	.rodata:
+statusstr: .ascii "status \0"
+causestr: .ascii " cause \0"
+pcstr: .ascii " pc \0"
+badvastr: .ascii " badva \0"
+mmustr_a: .ascii "mmu started ptpr_a \0"
+mmustr_b: .ascii "mmu started ptpr_b \0"
+startstr: .ascii "start\n\0"
+
+	.org EXCEP_ADDRESS - BOOT_ADDRESS
+	.globl evect
+evect:
+	j	excep
+	nop
+
+	.data
+	/* first 2 pages is data that will be switched my mmu switch */
+data_a:
+	.word MAGIC1
+testval:
+	.word MAGIC2
+	.org data_a + 0x1000
+data_b:
+	.word MAGIC3
+	.word MAGIC4
+
+/*
+ * two PD with two different PTE2 for code: check that dtlb points to
+ * the right one by loading 2 different data at the same virtual address
+ */
+	.globl pte2_a
+pte2_a:
+	.align 12
+	.word PTE2_V | PTE2_C | PTE2_X
+	.word 0x0000 >> 12 /* check real value of data_a */
+
+	.org pte2_a + 4092
+	.word 0
+	.globl pte2_b
+pte2_b:
+	.align 12
+	.word PTE2_V | PTE2_C | PTE2_X
+	.word 0x1000 >> 12 /* check real value of data_b */
+
+	.org pte2_b + 4092
+	.word 0
+
+	.globl pte1_a
+pte1_a:
+	.align 13
+	.word PTE1_V | PTE1_C | PTE1_W | 0x0 /* map PA 0 at VA 0 */
+	.word PTE1_V | PTE1_T | (0x2000 >> 12) /* map PA 0x0 at VA 0x00200000 via pte2_a */
+
+	.org pte1_a + (BOOT_ADDRESS >> 21) * 4
+	.word PTE1_V | PTE1_C | PTE1_X | (BOOT_ADDRESS >> 21) /* map PA 0xbfc00000 at VA 0xbfc00000 */
+
+	.org pte1_a + (TTY_BASE >> 21) * 4
+	.word PTE1_V | PTE1_W | (TTY_BASE >> 21) /* map PA 0xd0200000 at VA 0xd0200000 */
+
+	.org pte1_a + (EXIT_BASE >> 21) * 4
+	.word PTE1_V | PTE1_W | (EXIT_BASE >> 21) /* map PA 0xe0000000 at VA 0xe0000000 */
+	.org pte1_a + 8192
+	.globl pte1_b
+pte1_b:
+	.align 13
+	.word PTE1_V | PTE1_C | PTE1_W | 0x0 /* map PA 0 at VA 0 */
+	.word PTE1_V | PTE1_T | (0x3000 >> 12) /* map PA 0x1000 at VA 0x00200000 via pte2_b */
+	.org pte1_b + (BOOT_ADDRESS >> 21) * 4
+	.word PTE1_V | PTE1_C | PTE1_X | (BOOT_ADDRESS >> 21) /* map PA 0xbfc00000 at VA 0xbfc00000 */
+	.org pte1_b + (TTY_BASE >> 21) * 4
+	.word PTE1_V | PTE1_W | (TTY_BASE >> 21) /* map PA 0xd0200000 at VA 0xd0200000 */
+	.org pte1_b + (EXIT_BASE >> 21) * 4
+	.word PTE1_V | PTE1_W | (EXIT_BASE >> 21) /* map PA 0xe0000000 at VA 0xe0000000 */
+	.org pte1_b + 8188
+	.word 0
Index: branches/v4/softs/tests_ccvcache_v4/test_excep_cop/Makefile
===================================================================
--- branches/v4/softs/tests_ccvcache_v4/test_excep_cop/Makefile	(revision 371)
+++ branches/v4/softs/tests_ccvcache_v4/test_excep_cop/Makefile	(revision 371)
@@ -0,0 +1,1 @@
+include ../Makefile.inc
Index: branches/v4/softs/tests_ccvcache_v4/test_excep_cop/run
===================================================================
--- branches/v4/softs/tests_ccvcache_v4/test_excep_cop/run	(revision 371)
+++ branches/v4/softs/tests_ccvcache_v4/test_excep_cop/run	(revision 371)
@@ -0,0 +1,28 @@
+#!/bin/sh 
+
+. ../common/common.sh
+
+check_output()
+{
+	egrep "^status 0x00400002 cause 0x1000002C pc 0xBFC0002C badva 0x00000000$" run.out > /dev/null
+	if [ $? -ne 0 ]; then
+		echo "couldn't find string 1 in output - mtty not working ?" >> run.out
+		return 1
+	fi
+	return 0;
+}
+
+make --quiet || exit 1
+${SIMUL} > run.out 2>&1 
+if [ $? -eq 0 ]; then
+	if check_output; then
+		echo "test passsed";
+		make --quiet clean
+		exit 0;
+	fi
+	echo "test FAILED"
+	exit 1
+fi
+echo "test FAILED"
+exit 1
+
Index: branches/v4/softs/tests_ccvcache_v4/test_excep_cop/test.S
===================================================================
--- branches/v4/softs/tests_ccvcache_v4/test_excep_cop/test.S	(revision 371)
+++ branches/v4/softs/tests_ccvcache_v4/test_excep_cop/test.S	(revision 371)
@@ -0,0 +1,71 @@
+/*
+ * coproc unusable exception test: we take an exception on COP1 use
+ */
+#include <registers.h>
+#include <misc.h>
+
+	.text
+	.globl  _start
+_start:
+	.set noreorder
+	la	k0, TTY_BASE
+	la	k1, EXIT_BASE
+	la	sp, 0x00400000 - 16
+
+	PRINT(startstr)
+
+	/* reset cop0 status (keep BEV) */
+	lui	a0, 0x0040;
+	mtc0	a0, COP0_STATUS
+	li	t3, MAGIC1
+	mtc1    t3,$f2
+	mfc1	a0,$f2
+	PRINTX
+	PUTCHAR('\n')
+	nop
+	nop
+	nop
+	nop
+
+1:
+	/* we should not get there */
+	EXIT(1)
+
+	.globl excep
+excep:
+	.set noreorder
+	PRINT(statusstr)
+	mfc0	a0, COP0_STATUS
+	PRINTX
+
+	PRINT(causestr)
+	mfc0	a0, COP0_CAUSE
+	PRINTX
+
+	PRINT(pcstr)
+	mfc0	a0, COP0_EXPC
+	PRINTX
+
+	PRINT(badvastr)
+	mfc0	a0, COP_0_BADVADDR
+	PRINTX
+	PUTCHAR('\n')
+
+	EXIT(0)
+
+	.rodata:
+statusstr: .ascii "status \0"
+causestr: .ascii " cause \0"
+pcstr: .ascii " pc \0"
+badvastr: .ascii " badva \0"
+startstr: .ascii "start\n\0"
+
+	.org EXCEP_ADDRESS - BOOT_ADDRESS
+	.globl evect
+evect:
+	j	excep
+	nop
+	.data
+	.word MAGIC1
+testval:
+	.word MAGIC2
Index: branches/v4/softs/tests_ccvcache_v4/test_excep_cop1/Makefile
===================================================================
--- branches/v4/softs/tests_ccvcache_v4/test_excep_cop1/Makefile	(revision 371)
+++ branches/v4/softs/tests_ccvcache_v4/test_excep_cop1/Makefile	(revision 371)
@@ -0,0 +1,1 @@
+include ../Makefile.inc
Index: branches/v4/softs/tests_ccvcache_v4/test_excep_cop1/run
===================================================================
--- branches/v4/softs/tests_ccvcache_v4/test_excep_cop1/run	(revision 371)
+++ branches/v4/softs/tests_ccvcache_v4/test_excep_cop1/run	(revision 371)
@@ -0,0 +1,28 @@
+#!/bin/sh 
+
+. ../common/common.sh
+
+check_output()
+{
+	egrep "^status 0x00400002 cause 0x1000002C pc 0xBFC00030 badva 0x00000000$" run.out > /dev/null
+	if [ $? -ne 0 ]; then
+		echo "couldn't find string 1 in output - mtty not working ?" >> run.out
+		return 1
+	fi
+	return 0;
+}
+
+make --quiet || exit 1
+${SIMUL} > run.out 2>&1 
+if [ $? -eq 0 ]; then
+	if check_output; then
+		echo "test passsed";
+		make --quiet clean
+		exit 0;
+	fi
+	echo "test FAILED"
+	exit 1
+fi
+echo "test FAILED"
+exit 1
+
Index: branches/v4/softs/tests_ccvcache_v4/test_excep_cop1/test.S
===================================================================
--- branches/v4/softs/tests_ccvcache_v4/test_excep_cop1/test.S	(revision 371)
+++ branches/v4/softs/tests_ccvcache_v4/test_excep_cop1/test.S	(revision 371)
@@ -0,0 +1,71 @@
+/*
+ * trap test: check that we get a trap on FPU access though [ls][dw]c1
+ */
+#include <registers.h>
+#include <misc.h>
+
+	.text
+	.globl  _start
+_start:
+	.set noreorder
+	la	k0, TTY_BASE
+	la	k1, EXIT_BASE
+	la	sp, 0x00400000 - 16
+
+	PRINT(startstr)
+
+	/* reset cop0 status (keep BEV), enable cop1 */
+	lui	a0, 0x0040;
+	mtc0	a0, COP0_STATUS
+
+	la	a0, div1;
+	lwc1	$f0, 0(a0)
+	PRINTX
+	PUTCHAR('\n')
+	EXIT(2)
+
+	.globl excep
+excep:
+	.set noreorder
+	PRINT(statusstr)
+	mfc0	a0, COP0_STATUS
+	PRINTX
+
+	PRINT(causestr)
+	mfc0	a0, COP0_CAUSE
+	PRINTX
+
+	PRINT(pcstr)
+	mfc0	a0, COP0_EXPC
+	PRINTX
+
+	PRINT(badvastr)
+	mfc0	a0, COP_0_BADVADDR
+	PRINTX
+	PUTCHAR('\n')
+#we should end there
+	EXIT(0)
+
+	.rodata:
+statusstr: .ascii "status \0"
+causestr: .ascii " cause \0"
+pcstr: .ascii " pc \0"
+badvastr: .ascii " badva \0"
+startstr: .ascii "start\n\0"
+usrstr: .ascii "usrmode\n\0"
+
+	.org EXCEP_ADDRESS - BOOT_ADDRESS
+	.globl evect
+evect:
+	j	excep
+	nop
+	.data
+	.word MAGIC1
+testval:
+	.word MAGIC2
+	.globl div1
+div1:
+	.float	10.0
+	.globl div2
+div2:
+	.float	0.0
Index: branches/v4/softs/tests_ccvcache_v4/test_excep_cop_delayslot/Makefile
===================================================================
--- branches/v4/softs/tests_ccvcache_v4/test_excep_cop_delayslot/Makefile	(revision 371)
+++ branches/v4/softs/tests_ccvcache_v4/test_excep_cop_delayslot/Makefile	(revision 371)
@@ -0,0 +1,1 @@
+include ../Makefile.inc
Index: branches/v4/softs/tests_ccvcache_v4/test_excep_cop_delayslot/run
===================================================================
--- branches/v4/softs/tests_ccvcache_v4/test_excep_cop_delayslot/run	(revision 371)
+++ branches/v4/softs/tests_ccvcache_v4/test_excep_cop_delayslot/run	(revision 371)
@@ -0,0 +1,28 @@
+#!/bin/sh 
+
+. ../common/common.sh
+
+check_output()
+{
+	egrep "^status 0x00400002 cause 0x9000002C pc 0xBFC00028 badva 0x00000000$" run.out > /dev/null
+	if [ $? -ne 0 ]; then
+		echo "couldn't find string 1 in output - mtty not working ?" >> run.out
+		return 1
+	fi
+	return 0;
+}
+
+make --quiet || exit 1
+${SIMUL} > run.out 2>&1 
+if [ $? -eq 0 ]; then
+	if check_output; then
+		echo "test passsed";
+		make --quiet clean
+		exit 0;
+	fi
+	echo "test FAILED"
+	exit 1
+fi
+echo "test FAILED"
+exit 1
+
Index: branches/v4/softs/tests_ccvcache_v4/test_excep_cop_delayslot/test.S
===================================================================
--- branches/v4/softs/tests_ccvcache_v4/test_excep_cop_delayslot/test.S	(revision 371)
+++ branches/v4/softs/tests_ccvcache_v4/test_excep_cop_delayslot/test.S	(revision 371)
@@ -0,0 +1,65 @@
+/*
+ * coproc unusable exception test: 0x80000000 bit is set in cause register
+ */
+#include <registers.h>
+#include <misc.h>
+
+	.text
+	.globl  _start
+_start:
+	.set noreorder
+	la	k0, TTY_BASE
+	la	k1, EXIT_BASE
+	la	sp, 0x00400000 - 16
+
+	PRINT(startstr)
+
+	/* reset cop0 status (keep BEV) */
+	lui	a0, 0x0040;
+	mtc0	a0, COP0_STATUS
+	j	1f
+	mtc1    t3,$f2
+	nop
+
+1:
+	/* we should not get there */
+	EXIT(1)
+
+	.globl excep
+excep:
+	.set noreorder
+	PRINT(statusstr)
+	mfc0	a0, COP0_STATUS
+	PRINTX
+
+	PRINT(causestr)
+	mfc0	a0, COP0_CAUSE
+	PRINTX
+
+	PRINT(pcstr)
+	mfc0	a0, COP0_EXPC
+	PRINTX
+
+	PRINT(badvastr)
+	mfc0	a0, COP_0_BADVADDR
+	PRINTX
+	PUTCHAR('\n')
+
+	EXIT(0)
+
+	.rodata:
+statusstr: .ascii "status \0"
+causestr: .ascii " cause \0"
+pcstr: .ascii " pc \0"
+badvastr: .ascii " badva \0"
+startstr: .ascii "start\n\0"
+
+	.org EXCEP_ADDRESS - BOOT_ADDRESS
+	.globl evect
+evect:
+	j	excep
+	nop
+	.data
+	.word MAGIC1
+testval:
+	.word MAGIC2
Index: branches/v4/softs/tests_ccvcache_v4/test_excep_if/Makefile
===================================================================
--- branches/v4/softs/tests_ccvcache_v4/test_excep_if/Makefile	(revision 371)
+++ branches/v4/softs/tests_ccvcache_v4/test_excep_if/Makefile	(revision 371)
@@ -0,0 +1,2 @@
+LDSCRIPT=./ldscript
+include ../Makefile.inc
Index: branches/v4/softs/tests_ccvcache_v4/test_excep_if/ldscript
===================================================================
--- branches/v4/softs/tests_ccvcache_v4/test_excep_if/ldscript	(revision 371)
+++ branches/v4/softs/tests_ccvcache_v4/test_excep_if/ldscript	(revision 371)
@@ -0,0 +1,67 @@
+/*
+ *
+ * SOCLIB_GPL_HEADER_BEGIN
+ * 
+ * This file is part of SoCLib, GNU GPLv2.
+ * 
+ * SoCLib is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ * 
+ * SoCLib is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * General Public License for more details.
+ * 
+ * You should have received a copy of the GNU General Public License
+ * along with SoCLib; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301, USA.
+ * 
+ * SOCLIB_GPL_HEADER_END
+ *
+ * Copyright (c) UPMC, Lip6, SoC
+ *         Nicolas Pouillon <nipo@ssji.net>, 2006-2007
+ *
+ * Maintainers: abdelmalek.si-merabet@lip6.fr
+ */
+ENTRY(_start)
+
+SECTIONS
+{
+   . = 0xbfc00000;
+   .text : {
+      *(.text)
+/* load .text2 one page after .text */
+      . = ALIGN(0x1000);
+      *(.text2)
+   }
+   .rodata : {
+      *(.rodata)
+      . = ALIGN(4);
+   }
+   . = 0x00000000;
+   .data  : {
+      *(.data)
+   }
+   .sdata : {
+      *(.lit8)
+      *(.lit4)
+      *(.sdata)
+   }
+   _gp = .;
+   . = ALIGN(4);
+   _edata = .;
+   .sbss  : {
+      *(.sbss)
+      *(.scommon)
+   }
+   .bss   : {
+      *(.bss)
+      *(COMMON)
+   }
+   . = ALIGN(4);
+   _end = .;
+   _heap = .;
+   _stack = 0x00400000-16;
+}
Index: branches/v4/softs/tests_ccvcache_v4/test_excep_if/mtty0
===================================================================
--- branches/v4/softs/tests_ccvcache_v4/test_excep_if/mtty0	(revision 371)
+++ branches/v4/softs/tests_ccvcache_v4/test_excep_if/mtty0	(revision 371)
@@ -0,0 +1,4 @@
+[20hstart
+mmu started
+status 0x00400002 cause 0x00000018 pc 0xBFC01000 badva 0x00000000
+0x00000004: 0x0000BEEF
Index: branches/v4/softs/tests_ccvcache_v4/test_excep_if/run
===================================================================
--- branches/v4/softs/tests_ccvcache_v4/test_excep_if/run	(revision 371)
+++ branches/v4/softs/tests_ccvcache_v4/test_excep_if/run	(revision 371)
@@ -0,0 +1,33 @@
+#!/bin/sh 
+
+. ../common/common.sh
+
+check_output()
+{
+	egrep "^0x00000004: 0x0000BEEF$" run.out > /dev/null
+	if [ $? -ne 0 ]; then
+		echo "couldn't find string 1 in output - mtty not working ?" >> run.out
+		return 1
+	fi
+	egrep "^status 0x00400002 cause 0x00000018 pc 0xBFC01000 badva 0x00000000$" run.out > /dev/null
+	if [ $? -ne 0 ]; then
+		echo "couldn't find string 2 in output - mtty not working ?" >> run.out
+		return 1
+	fi
+	return 0;
+}
+
+make --quiet || exit 1
+${SIMUL} > run.out 2>&1 
+if [ $? -eq 0 ]; then
+	if check_output; then
+		echo "test passsed";
+		make --quiet clean
+		exit 0;
+	fi
+	echo "test FAILED"
+	exit 1
+fi
+echo "test FAILED"
+exit 1
+
Index: branches/v4/softs/tests_ccvcache_v4/test_excep_if/test.S
===================================================================
--- branches/v4/softs/tests_ccvcache_v4/test_excep_if/test.S	(revision 371)
+++ branches/v4/softs/tests_ccvcache_v4/test_excep_if/test.S	(revision 371)
@@ -0,0 +1,135 @@
+/*
+ * ifetch bus fault exception test: we can restart the faulting instruction
+ * We use the MMU to cause fault.
+ */
+#include <registers.h>
+#include <misc.h>
+#include <vcache.h>
+
+	.text
+	.globl  _start
+_start:
+	.set noreorder
+	la	k0, TTY_BASE
+	la	k1, EXIT_BASE
+	la	sp, 0x00200000 - 16
+
+	PRINT(startstr)
+
+	/* reset cop0 status (keep BEV) */
+	lui	a0, 0x0040;
+	mtc0	a0, COP0_STATUS
+
+	la	a0, pte1
+	srl	a0, a0, 13
+	mtc2	a0, VC_PTPR
+	nop
+
+	li	a0, VC_TLB_EN_ITLB | VC_TLB_EN_DTLB | VC_TLB_EN_ICACHE | VC_TLB_EN_DCACHE
+	mtc2 	a0, VC_TLB_EN
+
+	PRINT(mmustr)
+
+	move	a1, zero
+	la	s0, testval
+	jal	doload
+	move	a0, s0
+	PRINTX
+	PUTCHAR(':')
+	PUTCHAR(' ')
+	move	a0, a1
+	PRINTX
+	PUTCHAR('\n')
+
+	/* we should get there */
+	EXIT(0)
+
+	.globl excep
+excep:
+	.set noreorder
+	/* don't clobber a0 and ra */
+	addiu   sp, sp, -8
+	sw      a0, 4(sp)
+	sw      ra, 8(sp)
+
+	PRINT(statusstr)
+	mfc0	a0, COP0_STATUS
+	PRINTX
+
+	PRINT(causestr)
+	mfc0	a0, COP0_CAUSE
+	PRINTX
+
+	PRINT(pcstr)
+	mfc0	a0, COP0_EXPC
+	PRINTX
+
+	PRINT(badvastr)
+	mfc0	a0, COP_0_BADVADDR
+	PRINTX
+
+	PUTCHAR('\n')
+	/* map VA 0xbfc01000 at PA 0xbfc01000 */
+	la	t0, pte2 + VADDR_TO_PTE2I(0xbfc01000) * 8
+	la	a0, (0xbfc01000 >> PTE2_SHIFT)
+	sw	a0, 4(t0)
+	la	a0, (PTE2_V | PTE2_C | PTE2_X)
+	sw	a0, 0(t0)
+	/* la	a0, 0xbfc01000
+	mtc2	a0, VC_ITLB_INVAL */
+
+	lw      a0, 4(sp)
+	lw      ra, 8(sp)
+	addiu   sp, sp, 8
+	eret
+
+	.rodata:
+statusstr: .ascii "status \0"
+causestr: .ascii " cause \0"
+pcstr: .ascii " pc \0"
+badvastr: .ascii " badva \0"
+mmustr:	.ascii "mmu started\n\0"
+startstr: .ascii "start\n\0"
+
+	.org EXCEP_ADDRESS - BOOT_ADDRESS
+	.globl evect
+evect:
+	j	excep
+	nop
+	/*
+	 * we use a ldscript trick here, to load this function at
+	 * the appropriate address
+	 */
+	.section .text2, "ax"
+	.globl doload
+doload:
+	jr      ra
+	lw      a1, 0(s0) /* this should trigger the exception */
+
+	/* we should not get there */
+	nop
+	nop
+	EXIT(1)
+
+	.data
+	.word MAGIC1
+testval:
+	.word MAGIC2
+	.globl pte2
+pte2:
+	.align 12
+	.word PTE2_V | PTE2_C | PTE2_X
+	.word BOOT_ADDRESS >> 12
+	.org pte2 + 4092
+	.globl pte1
+pte1:
+	.align 13
+	.word PTE1_V | PTE1_C | PTE1_W | 0x0 /* map PA 0 at VA 0 */
+	.word 0x0
+	.org pte1 + (BOOT_ADDRESS >> 21) * 4
+	.word PTE1_V | PTE1_T | (0x1000 >> 12) /* map PA 0xbfc00000 at VA 0xbfc00000 with 4k page: check real address of PTE2 !!! */
+	.org pte1 + (TTY_BASE >> 21) * 4
+	.word PTE1_V | PTE1_W | (TTY_BASE >> 21) /* map PA 0xd0200000 at VA 0xd0200000 */
+	.org pte1 + (EXIT_BASE >> 21) * 4
+	.word PTE1_V | PTE1_W | (EXIT_BASE >> 21) /* map PA 0xe0000000 at VA 0xe0000000 */
+	.org pte1 + 8192
Index: branches/v4/softs/tests_ccvcache_v4/test_excep_if_delayslot/Makefile
===================================================================
--- branches/v4/softs/tests_ccvcache_v4/test_excep_if_delayslot/Makefile	(revision 371)
+++ branches/v4/softs/tests_ccvcache_v4/test_excep_if_delayslot/Makefile	(revision 371)
@@ -0,0 +1,2 @@
+LDSCRIPT=./ldscript
+include ../Makefile.inc
Index: branches/v4/softs/tests_ccvcache_v4/test_excep_if_delayslot/ldscript
===================================================================
--- branches/v4/softs/tests_ccvcache_v4/test_excep_if_delayslot/ldscript	(revision 371)
+++ branches/v4/softs/tests_ccvcache_v4/test_excep_if_delayslot/ldscript	(revision 371)
@@ -0,0 +1,67 @@
+/*
+ *
+ * SOCLIB_GPL_HEADER_BEGIN
+ * 
+ * This file is part of SoCLib, GNU GPLv2.
+ * 
+ * SoCLib is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ * 
+ * SoCLib is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * General Public License for more details.
+ * 
+ * You should have received a copy of the GNU General Public License
+ * along with SoCLib; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301, USA.
+ * 
+ * SOCLIB_GPL_HEADER_END
+ *
+ * Copyright (c) UPMC, Lip6, SoC
+ *         Nicolas Pouillon <nipo@ssji.net>, 2006-2007
+ *
+ * Maintainers: abdelmalek.si-merabet@lip6.fr
+ */
+ENTRY(_start)
+
+SECTIONS
+{
+   . = 0xbfc00000;
+   .text : {
+      *(.text)
+/* load .text2 one page after .text */
+      . = ALIGN(0x1000) - 4;
+      *(.text2)
+   }
+   .rodata : {
+      *(.rodata)
+      . = ALIGN(4);
+   }
+   . = 0x00000000;
+   .data  : {
+      *(.data)
+   }
+   .sdata : {
+      *(.lit8)
+      *(.lit4)
+      *(.sdata)
+   }
+   _gp = .;
+   . = ALIGN(4);
+   _edata = .;
+   .sbss  : {
+      *(.sbss)
+      *(.scommon)
+   }
+   .bss   : {
+      *(.bss)
+      *(COMMON)
+   }
+   . = ALIGN(4);
+   _end = .;
+   _heap = .;
+   _stack = 0x00400000-16;
+}
Index: branches/v4/softs/tests_ccvcache_v4/test_excep_if_delayslot/run
===================================================================
--- branches/v4/softs/tests_ccvcache_v4/test_excep_if_delayslot/run	(revision 371)
+++ branches/v4/softs/tests_ccvcache_v4/test_excep_if_delayslot/run	(revision 371)
@@ -0,0 +1,33 @@
+#!/bin/sh 
+
+. ../common/common.sh
+
+check_output()
+{
+	egrep "^0x00000004: 0x0000BEEF$" run.out > /dev/null
+	if [ $? -ne 0 ]; then
+		echo "couldn't find string 1 in output - mtty not working ?" >> run.out
+		return 1
+	fi
+	egrep "^status 0x00400002 cause 0x80000018 pc 0xBFC00FFC badva 0x00000000$" run.out > /dev/null
+	if [ $? -ne 0 ]; then
+		echo "couldn't find string 2 in output - mtty not working ?" >> run.out
+		return 1
+	fi
+	return 0;
+}
+
+make --quiet || exit 1
+${SIMUL} > run.out 2>&1 
+if [ $? -eq 0 ]; then
+	if check_output; then
+		echo "test passsed";
+		make --quiet clean
+		exit 0;
+	fi
+	echo "test FAILED"
+	exit 1
+fi
+echo "test FAILED"
+exit 1
+
Index: branches/v4/softs/tests_ccvcache_v4/test_excep_if_delayslot/test.S
===================================================================
--- branches/v4/softs/tests_ccvcache_v4/test_excep_if_delayslot/test.S	(revision 371)
+++ branches/v4/softs/tests_ccvcache_v4/test_excep_if_delayslot/test.S	(revision 371)
@@ -0,0 +1,135 @@
+/*
+ * ifetch bus fault exception test: we can restart the faulting instruction
+ * when the fault occurs in the branch delay slot.
+ * We use the MMU to cause fault.
+ */
+#include <registers.h>
+#include <misc.h>
+#include <vcache.h>
+	.text
+	.globl  _start
+_start:
+	.set noreorder
+	la	k0, TTY_BASE
+	la	k1, EXIT_BASE
+	la	sp, 0x00200000 - 16
+
+	PRINT(startstr)
+
+	/* reset cop0 status (keep BEV) */
+	lui	a0, 0x0040;
+	mtc0	a0, COP0_STATUS
+
+	la	a0, pte1
+	srl	a0, a0, 13
+	mtc2	a0, VC_PTPR
+	nop
+
+	li	a0, VC_TLB_EN_ITLB | VC_TLB_EN_DTLB | VC_TLB_EN_ICACHE | VC_TLB_EN_DCACHE
+	mtc2 	a0, VC_TLB_EN
+
+	PRINT(mmustr)
+
+	move	a1, zero
+	la	s0, testval
+	jal	doload
+	move	a0, s0
+	PRINTX
+	PUTCHAR(':')
+	PUTCHAR(' ')
+	move	a0, a1
+	PRINTX
+	PUTCHAR('\n')
+
+	/* we should get there */
+	EXIT(0)
+
+	.globl excep
+excep:
+	.set noreorder
+	/* don't clobber a0 and ra */
+	addiu   sp, sp, -8
+	sw      a0, 4(sp)
+	sw      ra, 8(sp)
+
+	PRINT(statusstr)
+	mfc0	a0, COP0_STATUS
+	PRINTX
+
+	PRINT(causestr)
+	mfc0	a0, COP0_CAUSE
+	PRINTX
+
+	PRINT(pcstr)
+	mfc0	a0, COP0_EXPC
+	PRINTX
+
+	PRINT(badvastr)
+	mfc0	a0, COP_0_BADVADDR
+	PRINTX
+
+	PUTCHAR('\n')
+	/* map VA 0xbfc01000 at PA 0xbfc01000 */
+	la	t0, pte2 + VADDR_TO_PTE2I(0xbfc01000) * 8
+	la	a0, (0xbfc01000 >> PTE2_SHIFT)
+	sw	a0, 4(t0)
+	la	a0, (PTE2_V | PTE2_C | PTE2_X)
+	sw	a0, 0(t0)
+	/* la	a0, 0xbfc01000
+	mtc2	a0, VC_ITLB_INVAL */
+
+	lw      a0, 4(sp)
+	lw      ra, 8(sp)
+	addiu   sp, sp, 8
+	eret
+
+	.rodata:
+statusstr: .ascii "status \0"
+causestr: .ascii " cause \0"
+pcstr: .ascii " pc \0"
+badvastr: .ascii " badva \0"
+mmustr:	.ascii "mmu started\n\0"
+startstr: .ascii "start\n\0"
+
+	.org EXCEP_ADDRESS - BOOT_ADDRESS
+	.globl evect
+evect:
+	j	excep
+	nop
+	/*
+	 * we use a ldscript trick here, to load this function at
+	 * the appropriate address
+	 */
+	.section .text2, "ax"
+	.globl doload
+doload:
+	jr      ra
+	lw      a1, 0(s0) /* this should trigger the exception */
+
+	/* we should not get there */
+	nop
+	nop
+	EXIT(1)
+
+	.data
+	.word MAGIC1
+testval:
+	.word MAGIC2
+	.globl pte2
+pte2:
+	.align 12
+	.word PTE2_V | PTE2_C | PTE2_X
+	.word BOOT_ADDRESS >> 12
+	.org pte2 + 4092
+	.globl pte1
+pte1:
+	.align 13
+	.word PTE1_V | PTE1_C | PTE1_W | 0x0 /* map PA 0 at VA 0 */
+	.word 0x0
+	.org pte1 + (BOOT_ADDRESS >> 21) * 4
+	.word PTE1_V | PTE1_T | (0x1000 >> 12) /* map PA 0xbfc00000 at VA 0xbfc00000 with 4k page: check real address of PTE2 !!! */
+	.org pte1 + (TTY_BASE >> 21) * 4
+	.word PTE1_V | PTE1_W | (TTY_BASE >> 21) /* map PA 0xd0200000 at VA 0xd0200000 */
+	.org pte1 + (EXIT_BASE >> 21) * 4
+	.word PTE1_V | PTE1_W | (EXIT_BASE >> 21) /* map PA 0xe0000000 at VA 0xe0000000 */
+	.org pte1 + 8192
Index: branches/v4/softs/tests_ccvcache_v4/test_excep_if_llsc/Makefile
===================================================================
--- branches/v4/softs/tests_ccvcache_v4/test_excep_if_llsc/Makefile	(revision 371)
+++ branches/v4/softs/tests_ccvcache_v4/test_excep_if_llsc/Makefile	(revision 371)
@@ -0,0 +1,2 @@
+LDSCRIPT=./ldscript
+include ../Makefile.inc
Index: branches/v4/softs/tests_ccvcache_v4/test_excep_if_llsc/ldscript
===================================================================
--- branches/v4/softs/tests_ccvcache_v4/test_excep_if_llsc/ldscript	(revision 371)
+++ branches/v4/softs/tests_ccvcache_v4/test_excep_if_llsc/ldscript	(revision 371)
@@ -0,0 +1,67 @@
+/*
+ *
+ * SOCLIB_GPL_HEADER_BEGIN
+ * 
+ * This file is part of SoCLib, GNU GPLv2.
+ * 
+ * SoCLib is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ * 
+ * SoCLib is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * General Public License for more details.
+ * 
+ * You should have received a copy of the GNU General Public License
+ * along with SoCLib; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301, USA.
+ * 
+ * SOCLIB_GPL_HEADER_END
+ *
+ * Copyright (c) UPMC, Lip6, SoC
+ *         Nicolas Pouillon <nipo@ssji.net>, 2006-2007
+ *
+ * Maintainers: abdelmalek.si-merabet@lip6.fr
+ */
+ENTRY(_start)
+
+SECTIONS
+{
+   . = 0xbfc00000;
+   .text : {
+      *(.text)
+/* load .text2 one page after .text */
+      . = ALIGN(0x1000);
+      *(.text2)
+   }
+   .rodata : {
+      *(.rodata)
+      . = ALIGN(4);
+   }
+   . = 0x00000000;
+   .data  : {
+      *(.data)
+   }
+   .sdata : {
+      *(.lit8)
+      *(.lit4)
+      *(.sdata)
+   }
+   _gp = .;
+   . = ALIGN(4);
+   _edata = .;
+   .sbss  : {
+      *(.sbss)
+      *(.scommon)
+   }
+   .bss   : {
+      *(.bss)
+      *(COMMON)
+   }
+   . = ALIGN(4);
+   _end = .;
+   _heap = .;
+   _stack = 0x00400000-16;
+}
Index: branches/v4/softs/tests_ccvcache_v4/test_excep_if_llsc/run
===================================================================
--- branches/v4/softs/tests_ccvcache_v4/test_excep_if_llsc/run	(revision 371)
+++ branches/v4/softs/tests_ccvcache_v4/test_excep_if_llsc/run	(revision 371)
@@ -0,0 +1,33 @@
+#!/bin/sh 
+
+. ../common/common.sh
+
+check_output()
+{
+	egrep "^0x00000004: 0x0000BEEF$" run.out > /dev/null
+	if [ $? -ne 0 ]; then
+		echo "couldn't find string 1 in output - mtty not working ?" >> run.out
+		return 1
+	fi
+	egrep "^status 0x00400002 cause 0x00000018 pc 0xBFC01000 badva 0x00000000$" run.out > /dev/null
+	if [ $? -ne 0 ]; then
+		echo "couldn't find string 2 in output - mtty not working ?" >> run.out
+		return 1
+	fi
+	return 0;
+}
+
+make --quiet || exit 1
+${SIMUL} > run.out 2>&1 
+if [ $? -eq 0 ]; then
+	if check_output; then
+		echo "test passsed";
+		make --quiet clean
+		exit 0;
+	fi
+	echo "test FAILED"
+	exit 1
+fi
+echo "test FAILED"
+exit 1
+
Index: branches/v4/softs/tests_ccvcache_v4/test_excep_if_llsc/test.S
===================================================================
--- branches/v4/softs/tests_ccvcache_v4/test_excep_if_llsc/test.S	(revision 371)
+++ branches/v4/softs/tests_ccvcache_v4/test_excep_if_llsc/test.S	(revision 371)
@@ -0,0 +1,136 @@
+/*
+ * ifetch bus fault exception test: we can restart the faulting instruction
+ * We use the MMU to cause fault.
+ * Match what NetBSD does for page table update: sw for ppn, ll/sc for flags
+ */
+#include <registers.h>
+#include <misc.h>
+#include <vcache.h>
+
+	.text
+	.globl  _start
+_start:
+	.set noreorder
+	la	k0, TTY_BASE
+	la	k1, EXIT_BASE
+	la	sp, 0x00200000 - 16
+
+	PRINT(startstr)
+
+	/* reset cop0 status (keep BEV) */
+	lui	a0, 0x0040;
+	mtc0	a0, COP0_STATUS
+
+	la	a0, pte1
+	srl	a0, a0, 13
+	mtc2	a0, VC_PTPR
+	nop
+
+	li	a0, VC_TLB_EN_ITLB | VC_TLB_EN_DTLB | VC_TLB_EN_ICACHE | VC_TLB_EN_DCACHE
+	mtc2 	a0, VC_TLB_EN
+
+	PRINT(mmustr)
+
+	move	a1, zero
+	la	s0, testval
+	jal	doload
+	move	a0, s0
+	PRINTX
+	PUTCHAR(':')
+	PUTCHAR(' ')
+	move	a0, a1
+	PRINTX
+	PUTCHAR('\n')
+
+	/* we should get there */
+	EXIT(0)
+
+	.globl excep
+excep:
+	.set noreorder
+	/* don't clobber a0 and ra */
+	addiu   sp, sp, -8
+	sw      a0, 4(sp)
+	sw      ra, 8(sp)
+
+	PRINT(statusstr)
+	mfc0	a0, COP0_STATUS
+	PRINTX
+
+	PRINT(causestr)
+	mfc0	a0, COP0_CAUSE
+	PRINTX
+
+	PRINT(pcstr)
+	mfc0	a0, COP0_EXPC
+	PRINTX
+
+	PRINT(badvastr)
+	mfc0	a0, COP_0_BADVADDR
+	PRINTX
+
+	PUTCHAR('\n')
+	/* map VA 0xbfc01000 at PA 0xbfc01000 */
+	la	t0, pte2 + VADDR_TO_PTE2I(0xbfc01000) * 8
+	la	a0, (0xbfc01000 >> PTE2_SHIFT)
+	sw	a0, 4(t0)
+1:
+	ll	a0, 0(t0)
+	la	a0, (PTE2_V | PTE2_C | PTE2_X)
+	sc	a0, 0(t0)
+	beqz	a0, 1b
+
+	lw      a0, 4(sp)
+	lw      ra, 8(sp)
+	addiu   sp, sp, 8
+	eret
+
+	.rodata:
+statusstr: .ascii "status \0"
+causestr: .ascii " cause \0"
+pcstr: .ascii " pc \0"
+badvastr: .ascii " badva \0"
+mmustr:	.ascii "mmu started\n\0"
+startstr: .ascii "start\n\0"
+
+	.org EXCEP_ADDRESS - BOOT_ADDRESS
+	.globl evect
+evect:
+	j	excep
+	nop
+	/*
+	 * we use a ldscript trick here, to load this function at
+	 * the appropriate address
+	 */
+	.section .text2, "ax"
+	.globl doload
+doload:
+	jr      ra
+	lw      a1, 0(s0) /* this should trigger the exception */
+	/* we should not get there */
+	nop
+	nop
+	EXIT(1)
+
+	.data
+	.word MAGIC1
+testval:
+	.word MAGIC2
+	.globl pte2
+pte2:
+	.align 12
+	.word PTE2_V | PTE2_C | PTE2_X
+	.word BOOT_ADDRESS >> 12
+	.org pte2 + 4092
+	.globl pte1
+pte1:
+	.align 13
+	.word PTE1_V | PTE1_C | PTE1_W | 0x0 /* map PA 0 at VA 0 */
+	.word 0x0
+	.org pte1 + (BOOT_ADDRESS >> 21) * 4
+	.word PTE1_V | PTE1_T | (0x1000 >> 12) /* map PA 0xbfc00000 at VA 0xbfc00000 with 4k page: check real address of PTE2 !!! */
+	.org pte1 + (TTY_BASE >> 21) * 4
+	.word PTE1_V | PTE1_W | (TTY_BASE >> 21) /* map PA 0xd0200000 at VA 0xd0200000 */
+	.org pte1 + (EXIT_BASE >> 21) * 4
+	.word PTE1_V | PTE1_W | (EXIT_BASE >> 21) /* map PA 0xe0000000 at VA 0xe0000000 */
+	.org pte1 + 8192
Index: branches/v4/softs/tests_ccvcache_v4/test_excep_intr/Makefile
===================================================================
--- branches/v4/softs/tests_ccvcache_v4/test_excep_intr/Makefile	(revision 371)
+++ branches/v4/softs/tests_ccvcache_v4/test_excep_intr/Makefile	(revision 371)
@@ -0,0 +1,3 @@
+LDSCRIPT=./ldscript
+include ../Makefile.inc
+CFLAGS+= -DINTERRUPT_DELAY=${INTERRUPT_DELAY}
Index: branches/v4/softs/tests_ccvcache_v4/test_excep_intr/ldscript
===================================================================
--- branches/v4/softs/tests_ccvcache_v4/test_excep_intr/ldscript	(revision 371)
+++ branches/v4/softs/tests_ccvcache_v4/test_excep_intr/ldscript	(revision 371)
@@ -0,0 +1,67 @@
+/*
+ *
+ * SOCLIB_GPL_HEADER_BEGIN
+ * 
+ * This file is part of SoCLib, GNU GPLv2.
+ * 
+ * SoCLib is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ * 
+ * SoCLib is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * General Public License for more details.
+ * 
+ * You should have received a copy of the GNU General Public License
+ * along with SoCLib; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301, USA.
+ * 
+ * SOCLIB_GPL_HEADER_END
+ *
+ * Copyright (c) UPMC, Lip6, SoC
+ *         Nicolas Pouillon <nipo@ssji.net>, 2006-2007
+ *
+ * Maintainers: abdelmalek.si-merabet@lip6.fr
+ */
+ENTRY(_start)
+
+SECTIONS
+{
+   . = 0xbfc00000;
+   .text : {
+      *(.text)
+/* load .text2 one page after .text */
+      . = ALIGN(0x1000);
+      *(.text2)
+   }
+   .rodata : {
+      *(.rodata)
+      . = ALIGN(4);
+   }
+   . = 0x00000000;
+   .data  : {
+      *(.data)
+   }
+   .sdata : {
+      *(.lit8)
+      *(.lit4)
+      *(.sdata)
+   }
+   _gp = .;
+   . = ALIGN(4);
+   _edata = .;
+   .sbss  : {
+      *(.sbss)
+      *(.scommon)
+   }
+   .bss   : {
+      *(.bss)
+      *(COMMON)
+   }
+   . = ALIGN(4);
+   _end = .;
+   _heap = .;
+   _stack = 0x00400000-16;
+}
Index: branches/v4/softs/tests_ccvcache_v4/test_excep_intr/mtty0
===================================================================
--- branches/v4/softs/tests_ccvcache_v4/test_excep_intr/mtty0	(revision 371)
+++ branches/v4/softs/tests_ccvcache_v4/test_excep_intr/mtty0	(revision 371)
@@ -0,0 +1,4 @@
+[20hstart
+status 0x00400403 cause 0x00000018 pc 0x80000000 badva 0x00000000 xicu 0x00000001
+status 0x00400403 cause 0x00000400 pc 0x80000000 badva 0x00000000 xicu 0x00000001
+end 0x0000BEEF 0x00000001
Index: branches/v4/softs/tests_ccvcache_v4/test_excep_intr/run
===================================================================
--- branches/v4/softs/tests_ccvcache_v4/test_excep_intr/run	(revision 371)
+++ branches/v4/softs/tests_ccvcache_v4/test_excep_intr/run	(revision 371)
@@ -0,0 +1,44 @@
+#!/bin/sh 
+
+. ../common/common.sh
+
+check_output()
+{
+	egrep "^end 0x0000BEEF 0x00000001$" run.out > /dev/null
+	if [ $? -ne 0 ]; then
+		echo "couldn't find string 1 in output - mtty not working ?" >> run.out
+		return 1
+	fi
+	egrep "^status 0x00400403 cause 0x00000018 pc 0x80000000 badva 0x00000000 xicu 0x00000000$" run.out > /dev/null
+	if [ $? -ne 0 ]; then
+		echo "couldn't find string 2 in output - mtty not working ?" >> run.out
+		return 1
+	fi
+	egrep "^status 0x00400403 cause 0x00000400 pc 0x80000000 badva 0x00000000 xicu 0x00000001$" run.out > /dev/null
+	if [ $? -ne 0 ]; then
+		echo "couldn't find string 3 in output - mtty not working ?" >> run.out
+		return 1
+	fi
+	return 0;
+}
+echo 
+i=1180
+while true; do
+	echo -n "    DELAY=$i: "
+	make INTERRUPT_DELAY=$i --quiet || exit 1
+	${SIMUL} > run.out 2>&1 
+	if [ $? -eq 0 ]; then
+		if check_output; then
+			echo "test passsed";
+			make --quiet clean
+		else
+			echo "test FAILED"
+			exit 1
+		fi
+	else 
+		echo "test FAILED"
+		exit 1
+	fi
+	i=$((i+1))
+done
+
Index: branches/v4/softs/tests_ccvcache_v4/test_excep_intr/run.out
===================================================================
--- branches/v4/softs/tests_ccvcache_v4/test_excep_intr/run.out	(revision 371)
+++ branches/v4/softs/tests_ccvcache_v4/test_excep_intr/run.out	(revision 371)
@@ -0,0 +1,25 @@
+
+             SystemC 2.2.0 --- Apr 14 2011 18:52:40
+        Copyright (c) 1996-2006 by all Contributors
+                    ALL RIGHTS RESERVED
+Mapping table: ad:(6) id:(6) cacheability mask: 0xf0000000
+ <Segment "memc_d": base = 0 / size = 0x2000000 / tgtid = (0) / cached>
+ <Segment "boot_d": base = 0xbfc00000 / size = 0x40000 / tgtid = (1) / cached>
+ <Segment "exit_d": base = 0xe0000000 / size = 0x4 / tgtid = (2) / uncached>
+ <Segment "mtty_d": base = 0xd0200000 / size = 0x10 / tgtid = (3) / uncached>
+ <Segment "xicu_d": base = 0xd8200000 / size = 0x1000 / tgtid = (4) / uncached>
+ <Segment "mdma_d": base = 0xe8000000 / size = 0x14 / tgtid = (5) / uncached>
+
+Mapping table: ad:(6) id:(6) cacheability mask: 0xf0000000
+ <Segment "proc_c": base = 0x10000000 / size = 0x10 / tgtid = (0) / uncached / init = (0)>
+ <Segment "memc_c": base = 0 / size = 0x2000010 / tgtid = (1) / uncached>
+ <Segment "brom_c": base = 0xbfc00000 / size = 0x40000 / tgtid = (1) / uncached>
+
+Loading at 0xbfc00000 size 262144: .text .reginfo 
+Loading at 0 size 33554432: .data 
+start
+status 0x00400403 cause 0x00000018 pc 0x80000000 badva 0x00000000 xicu 0x00000001
+status 0x00400403 cause 0x00000400 pc 0x80000000 badva 0x00000000 xicu 0x00000001
+end 0x0000BEEF 0x00000001
+vci_exit terminate simulation, status 0d0
+couldn't find string 2 in output - mtty not working ?
Index: branches/v4/softs/tests_ccvcache_v4/test_excep_intr/subr.o.txt
===================================================================
--- branches/v4/softs/tests_ccvcache_v4/test_excep_intr/subr.o.txt	(revision 371)
+++ branches/v4/softs/tests_ccvcache_v4/test_excep_intr/subr.o.txt	(revision 371)
@@ -0,0 +1,49 @@
+
+subr.o:     file format elf32-littlemips
+
+
+Disassembly of section .text:
+
+00000000 <print>:
+   0:	00804021 	move	t0,a0
+   4:	81090000 	lb	t1,0(t0)
+   8:	11200005 	beqz	t1,20 <end>
+   c:	00000000 	nop
+  10:	a3490000 	sb	t1,0(k0)
+  14:	25080001 	addiu	t0,t0,1
+  18:	08000001 	j	4 <print+0x4>
+  1c:	00000000 	nop
+
+00000020 <end>:
+  20:	03e00008 	jr	ra
+  24:	00000000 	nop
+
+00000028 <printx>:
+  28:	00804021 	move	t0,a0
+  2c:	24090030 	li	t1,48
+  30:	a3490000 	sb	t1,0(k0)
+  34:	24090078 	li	t1,120
+  38:	a3490000 	sb	t1,0(k0)
+  3c:	24090008 	li	t1,8
+  40:	3c0af000 	lui	t2,0xf000
+  44:	010a5024 	and	t2,t0,t2
+  48:	000a5702 	srl	t2,t2,0x1c
+  4c:	294b000a 	slti	t3,t2,10
+  50:	11600004 	beqz	t3,64 <printx+0x3c>
+  54:	00000000 	nop
+  58:	214a0030 	addi	t2,t2,48
+  5c:	0800001a 	j	68 <printx+0x40>
+  60:	00000000 	nop
+  64:	214a0037 	addi	t2,t2,55
+  68:	a34a0000 	sb	t2,0(k0)
+  6c:	2129ffff 	addi	t1,t1,-1
+  70:	1d20fff3 	bgtz	t1,40 <printx+0x18>
+  74:	00084100 	sll	t0,t0,0x4
+  78:	03e00008 	jr	ra
+  7c:	00000000 	nop
+
+Disassembly of section .reginfo:
+
+00000000 <.reginfo>:
+   0:	84000f10 	lh	zero,3856(zero)
+	...
Index: branches/v4/softs/tests_ccvcache_v4/test_excep_intr/test.S
===================================================================
--- branches/v4/softs/tests_ccvcache_v4/test_excep_intr/test.S	(revision 371)
+++ branches/v4/softs/tests_ccvcache_v4/test_excep_intr/test.S	(revision 371)
@@ -0,0 +1,201 @@
+/*
+ * Check interrupt while in trap handler.
+ * Cache is enabled so we have one instruction/cycle
+ */
+#include <registers.h>
+#include <misc.h>
+#include <vcache.h>
+#include <xicu.h>
+
+#define DOLOAD_ADDR 0x80000000
+
+	.text
+	.globl  _start
+_start:
+	.set noreorder
+	la	k0, TTY_BASE
+	la	k1, EXIT_BASE
+	la	sp, 0x00200000 - 16
+
+	/* reset cause, make sure IV is off */
+	mtc0	zero, COP0_CAUSE
+
+	la	a0, pte1
+	srl	a0, a0, 13
+	mtc2	a0, VC_PTPR
+	nop
+	nop
+
+	li	a0, VC_TLB_EN_ITLB | VC_TLB_EN_DTLB | VC_TLB_EN_ICACHE | VC_TLB_EN_DCACHE
+	mtc2 	a0, VC_TLB_EN
+
+	PRINT(startstr)
+
+	/* program xicu */
+	la	t0, XICU_BASE
+	/* clear pending interrupt */
+	lw	a0, XICU_PTI_ACK(0)(t0)
+	/* route PTI0 to irq 0 */
+	li	a0, 1 << 0
+	sw	a0, XICU_MSK_PTI_E(0)(t0)
+	/* init s0 */
+	li	s0, MAGIC2
+	/*
+	 * interrupt in INTERRUPT_DELAY cycles.
+	 */
+	li	a0, INTERRUPT_DELAY
+	sw	a0, XICU_PTI_PER(0)(t0)
+	/* clear pending interrupt */
+	lw	a0, XICU_PTI_ACK(0)(t0)
+	/* reset cop0 status (keep BEV), enable interrupt 0 */
+	lui     a0, 0x0040;
+	addiu	a0, 0x0401;
+	mtc0    a0, COP0_STATUS
+	nop
+	nop
+	nop
+	nop
+	nop
+
+	nop
+	move	a1, zero
+	la	s0, DOLOAD_ADDR
+	jalr	s0
+	nop
+	j	end
+	nop
+	/* we should not end there */
+	EXIT(1)
+
+end:
+	PRINT(endstr)
+	move	a0, a1
+	PRINTX
+	PUTCHAR(' ')
+	la	a0, myvar
+	lw	a0, 0(a0)
+	PRINTX
+	PUTCHAR('\n')
+	EXIT(0)
+
+	.globl excep
+excep:
+	.set noreorder
+        /* don't clobber a0 and ra */
+	addiu   sp, sp, -8
+	sw      a0, 4(sp)
+	sw      ra, 8(sp)
+
+	PRINT(statusstr)
+	mfc0	a0, COP0_STATUS
+	PRINTX
+
+	PRINT(causestr)
+	mfc0	a0, COP0_CAUSE
+	move	s0, a0
+	PRINTX
+
+	PRINT(pcstr)
+	mfc0	a0, COP0_EXPC
+	PRINTX
+
+	PRINT(badvastr)
+	mfc0	a0, COP_0_BADVADDR
+	PRINTX
+
+	PRINT(xicustr)
+	la	t0, XICU_BASE
+	lw	a0, XICU_PRIO(0)(t0)
+	PRINTX
+	PUTCHAR('\n')
+	/* map VA DOLOAD_ADDR at PA 0xbfc01000 */
+	la	t0, pte22 + VADDR_TO_PTE2I(DOLOAD_ADDR) * 8
+	la	a0, (0xbfc01000 >> PTE2_SHIFT)
+	sw	a0, 4(t0)
+	la	a0, (PTE2_V | PTE2_C | PTE2_X)
+	sw	a0, 0(t0)
+	mtc2	zero, VC_DCACHE_FLUSH /* flush the whole data cache */
+
+	andi	a0, s0, 0xff00
+	beq	a0, zero, notintr
+	nop
+
+	/* disable timer0 */
+	la	t0, XICU_BASE
+	sw	zero, XICU_PTI_PER(0)(t0)
+notintr:
+	la	a1, myvar
+	la	a0, 0(a1)
+	beq	a0, zero, noex
+	nop
+	EXIT(2)
+noex:
+	li	a0, 1
+	sw	a0, 0(a1)
+	lw	a0, 4(sp)
+	lw	ra, 8(sp)
+	addiu	sp, sp, 8
+	eret
+	/* we should not end there */
+	EXIT(1)
+
+	.rodata:
+statusstr: .ascii "status \0"
+causestr: .ascii " cause \0"
+pcstr: .ascii " pc \0"
+badvastr: .ascii " badva \0"
+xicustr: .ascii " xicu \0"
+startstr: .ascii "start\n\0"
+endstr: .ascii "end \0"
+
+	.org EXCEP_ADDRESS - BOOT_ADDRESS
+	.globl evect
+evect:
+	j	excep
+	nop
+	/*
+	 * we use a ldscript trick here, to load this function at
+	 * the appropriate address
+	 */
+	.section .text2, "ax"
+	.globl doload
+doload:
+	la	s0, testval
+	jr	ra
+	lw	a1, 0(s0) /* this should trigger the exception */
+	/* we should not get there */
+	EXIT(1)
+	nop
+	.data
+myvar:	.word 0
+testval:
+	.word MAGIC2
+	.globl pte2
+pte2:
+        .align 12
+        .word PTE2_V | PTE2_C | PTE2_X
+        .word BOOT_ADDRESS >> 12
+        .org pte2 + 4092
+	.globl pte22
+pte22:
+        .align 12
+        .word 0
+        .word 0
+        .org pte22 + 4092
+        .globl pte1
+pte1:
+	.align 13
+	.word PTE1_V | PTE1_C | PTE1_W | 0x0 /* map PA 0 at VA 0 */
+	.org pte1 + (DOLOAD_ADDR >> 21) * 4
+        .word PTE1_V | PTE1_T | (0x2000 >> 12) /* map VA DOLOAD_ADDR with 4k page: check real address of PTE22 !!! */
+	.org pte1 + (BOOT_ADDRESS >> 21) * 4
+        .word PTE1_V | PTE1_T | (0x1000 >> 12) /* map PA 0xbfc00000 at VA 0xbfc00000 with 4k page: check real address of PTE2 !!! */
+	.org pte1 + (TTY_BASE >> 21) * 4
+	.word PTE1_V | PTE1_W | (TTY_BASE >> 21) /* map PA 0xd0200000 at VA 0xd0200000 */
+	.org pte1 + (XICU_BASE >> 21) * 4
+	.word PTE1_V | PTE1_W | (XICU_BASE >> 21) /* map PA 0xd2000000 at VA 0xd2000000 */
+	.org pte1 + (EXIT_BASE >> 21) * 4
+	.word PTE1_V | PTE1_W | (EXIT_BASE >> 21) /* map PA 0xe0000000 at VA 0xe0000000 */
+	.org pte1 + 8192
+	.word 0
+
Index: branches/v4/softs/tests_ccvcache_v4/test_excep_intr/test.elf.txt
===================================================================
--- branches/v4/softs/tests_ccvcache_v4/test_excep_intr/test.elf.txt	(revision 371)
+++ branches/v4/softs/tests_ccvcache_v4/test_excep_intr/test.elf.txt	(revision 371)
@@ -0,0 +1,273 @@
+
+test.elf:     file format elf32-littlemips
+
+
+Disassembly of section .text:
+
+bfc00000 <_start>:
+bfc00000:	3c1ad020 	lui	k0,0xd020
+bfc00004:	3c1be000 	lui	k1,0xe000
+bfc00008:	3c1d001f 	lui	sp,0x1f
+bfc0000c:	37bdfff0 	ori	sp,sp,0xfff0
+bfc00010:	40806800 	mtc0	zero,c0_cause
+bfc00014:	3c040000 	lui	a0,0x0
+bfc00018:	24844000 	addiu	a0,a0,16384
+bfc0001c:	00042342 	srl	a0,a0,0xd
+bfc00020:	48840000 	mtc2	a0,$0
+	...
+bfc0002c:	2404000f 	li	a0,15
+bfc00030:	48840800 	mtc2	a0,$1
+bfc00034:	3c04bfc0 	lui	a0,0xbfc0
+bfc00038:	2484024c 	addiu	a0,a0,588
+bfc0003c:	0ff000e4 	jal	bfc00390 <print>
+bfc00040:	00000000 	nop
+bfc00044:	3c08d820 	lui	t0,0xd820
+bfc00048:	8d040180 	lw	a0,384(t0)
+bfc0004c:	24040001 	li	a0,1
+bfc00050:	ad040280 	sw	a0,640(t0)
+bfc00054:	3410beef 	li	s0,0xbeef
+bfc00058:	2404049c 	li	a0,1180
+bfc0005c:	ad040080 	sw	a0,128(t0)
+bfc00060:	8d040180 	lw	a0,384(t0)
+bfc00064:	3c040040 	lui	a0,0x40
+bfc00068:	24840401 	addiu	a0,a0,1025
+bfc0006c:	40846000 	mtc0	a0,c0_status
+	...
+bfc00088:	00002821 	move	a1,zero
+bfc0008c:	3c108000 	lui	s0,0x8000
+bfc00090:	0200f809 	jalr	s0
+bfc00094:	00000000 	nop
+bfc00098:	0bf0002c 	j	bfc000b0 <end>
+bfc0009c:	00000000 	nop
+bfc000a0:	24040001 	li	a0,1
+bfc000a4:	af640000 	sw	a0,0(k1)
+bfc000a8:	0bf0002a 	j	bfc000a8 <_start+0xa8>
+bfc000ac:	00000000 	nop
+
+bfc000b0 <end>:
+bfc000b0:	3c04bfc0 	lui	a0,0xbfc0
+bfc000b4:	24840253 	addiu	a0,a0,595
+bfc000b8:	0ff000e4 	jal	bfc00390 <print>
+bfc000bc:	00000000 	nop
+bfc000c0:	00a02021 	move	a0,a1
+bfc000c4:	0ff000ee 	jal	bfc003b8 <printx>
+bfc000c8:	00000000 	nop
+bfc000cc:	24040020 	li	a0,32
+bfc000d0:	a3440000 	sb	a0,0(k0)
+bfc000d4:	3c040000 	lui	a0,0x0
+bfc000d8:	24840000 	addiu	a0,a0,0
+bfc000dc:	8c840000 	lw	a0,0(a0)
+bfc000e0:	0ff000ee 	jal	bfc003b8 <printx>
+bfc000e4:	00000000 	nop
+bfc000e8:	2404000a 	li	a0,10
+bfc000ec:	a3440000 	sb	a0,0(k0)
+bfc000f0:	24040000 	li	a0,0
+bfc000f4:	af640000 	sw	a0,0(k1)
+bfc000f8:	0bf0003e 	j	bfc000f8 <end+0x48>
+bfc000fc:	00000000 	nop
+
+bfc00100 <excep>:
+bfc00100:	27bdfff8 	addiu	sp,sp,-8
+bfc00104:	afa40004 	sw	a0,4(sp)
+bfc00108:	afbf0008 	sw	ra,8(sp)
+bfc0010c:	3c04bfc0 	lui	a0,0xbfc0
+bfc00110:	24840228 	addiu	a0,a0,552
+bfc00114:	0ff000e4 	jal	bfc00390 <print>
+bfc00118:	00000000 	nop
+bfc0011c:	40046000 	mfc0	a0,c0_status
+bfc00120:	0ff000ee 	jal	bfc003b8 <printx>
+bfc00124:	00000000 	nop
+bfc00128:	3c04bfc0 	lui	a0,0xbfc0
+bfc0012c:	24840230 	addiu	a0,a0,560
+bfc00130:	0ff000e4 	jal	bfc00390 <print>
+bfc00134:	00000000 	nop
+bfc00138:	40046800 	mfc0	a0,c0_cause
+bfc0013c:	00808021 	move	s0,a0
+bfc00140:	0ff000ee 	jal	bfc003b8 <printx>
+bfc00144:	00000000 	nop
+bfc00148:	3c04bfc0 	lui	a0,0xbfc0
+bfc0014c:	24840238 	addiu	a0,a0,568
+bfc00150:	0ff000e4 	jal	bfc00390 <print>
+bfc00154:	00000000 	nop
+bfc00158:	40047000 	mfc0	a0,c0_epc
+bfc0015c:	0ff000ee 	jal	bfc003b8 <printx>
+bfc00160:	00000000 	nop
+bfc00164:	3c04bfc0 	lui	a0,0xbfc0
+bfc00168:	2484023d 	addiu	a0,a0,573
+bfc0016c:	0ff000e4 	jal	bfc00390 <print>
+bfc00170:	00000000 	nop
+bfc00174:	40044000 	mfc0	a0,c0_badvaddr
+bfc00178:	0ff000ee 	jal	bfc003b8 <printx>
+bfc0017c:	00000000 	nop
+bfc00180:	3c04bfc0 	lui	a0,0xbfc0
+bfc00184:	24840245 	addiu	a0,a0,581
+bfc00188:	0ff000e4 	jal	bfc00390 <print>
+bfc0018c:	00000000 	nop
+bfc00190:	3c08d820 	lui	t0,0xd820
+bfc00194:	8d040780 	lw	a0,1920(t0)
+bfc00198:	0ff000ee 	jal	bfc003b8 <printx>
+bfc0019c:	00000000 	nop
+bfc001a0:	2404000a 	li	a0,10
+bfc001a4:	a3440000 	sb	a0,0(k0)
+bfc001a8:	3c080000 	lui	t0,0x0
+bfc001ac:	25082000 	addiu	t0,t0,8192
+bfc001b0:	3c04000b 	lui	a0,0xb
+bfc001b4:	3484fc01 	ori	a0,a0,0xfc01
+bfc001b8:	ad040004 	sw	a0,4(t0)
+bfc001bc:	3c048a00 	lui	a0,0x8a00
+bfc001c0:	ad040000 	sw	a0,0(t0)
+bfc001c4:	48801800 	mtc2	zero,$3
+bfc001c8:	3204ff00 	andi	a0,s0,0xff00
+bfc001cc:	10800003 	beqz	a0,bfc001dc <notintr>
+bfc001d0:	00000000 	nop
+bfc001d4:	3c08d820 	lui	t0,0xd820
+bfc001d8:	ad000080 	sw	zero,128(t0)
+
+bfc001dc <notintr>:
+bfc001dc:	3c050000 	lui	a1,0x0
+bfc001e0:	24a50000 	addiu	a1,a1,0
+bfc001e4:	24a40000 	addiu	a0,a1,0
+bfc001e8:	10800005 	beqz	a0,bfc00200 <noex>
+bfc001ec:	00000000 	nop
+bfc001f0:	24040002 	li	a0,2
+bfc001f4:	af640000 	sw	a0,0(k1)
+bfc001f8:	0bf0007e 	j	bfc001f8 <notintr+0x1c>
+bfc001fc:	00000000 	nop
+
+bfc00200 <noex>:
+bfc00200:	24040001 	li	a0,1
+bfc00204:	aca40000 	sw	a0,0(a1)
+bfc00208:	8fa40004 	lw	a0,4(sp)
+bfc0020c:	8fbf0008 	lw	ra,8(sp)
+bfc00210:	27bd0008 	addiu	sp,sp,8
+bfc00214:	42000018 	eret
+bfc00218:	24040001 	li	a0,1
+bfc0021c:	af640000 	sw	a0,0(k1)
+bfc00220:	0bf00088 	j	bfc00220 <noex+0x20>
+bfc00224:	00000000 	nop
+
+bfc00228 <statusstr>:
+bfc00228:	74617473 	jalx	b185d1cc <_stack+0xb145d1dc>
+bfc0022c:	00207375 	0x207375
+
+bfc00230 <causestr>:
+bfc00230:	75616320 	jalx	b5858c80 <_stack+0xb5458c90>
+bfc00234:	00206573 	tltu	at,zero,0x195
+
+bfc00238 <pcstr>:
+bfc00238:	20637020 	addi	v1,v1,28704
+	...
+
+bfc0023d <badvastr>:
+bfc0023d:	6220      	sw	ra,128(sp)
+bfc0023f:	6461      	restore	8,ra,s0
+bfc00241:	6176      	btnez	bfc0032f <endstr+0xdc>
+bfc00243:	0020      	addiu	s0,sp,128
+
+bfc00245 <xicustr>:
+bfc00245:	7820      	sd	s1,0(s0)
+bfc00247:	6369      	addiu	sp,840
+bfc00249:	2075      	beqz	s0,bfc00335 <endstr+0xe2>
+	...
+
+bfc0024c <startstr>:
+bfc0024c:	72617473 	0x72617473
+bfc00250:	65000a74 	0x65000a74
+
+bfc00253 <endstr>:
+bfc00253:	6e65      	li	a2,101
+bfc00255:	2064      	beqz	s0,bfc0031f <endstr+0xcc>
+	...
+
+bfc00380 <evect>:
+bfc00380:	0bf00040 	j	bfc00100 <excep>
+bfc00384:	00000000 	nop
+	...
+
+bfc00390 <print>:
+bfc00390:	00804021 	move	t0,a0
+bfc00394:	81090000 	lb	t1,0(t0)
+bfc00398:	11200005 	beqz	t1,bfc003b0 <end>
+bfc0039c:	00000000 	nop
+bfc003a0:	a3490000 	sb	t1,0(k0)
+bfc003a4:	25080001 	addiu	t0,t0,1
+bfc003a8:	0bf000e5 	j	bfc00394 <print+0x4>
+bfc003ac:	00000000 	nop
+
+bfc003b0 <end>:
+bfc003b0:	03e00008 	jr	ra
+bfc003b4:	00000000 	nop
+
+bfc003b8 <printx>:
+bfc003b8:	00804021 	move	t0,a0
+bfc003bc:	24090030 	li	t1,48
+bfc003c0:	a3490000 	sb	t1,0(k0)
+bfc003c4:	24090078 	li	t1,120
+bfc003c8:	a3490000 	sb	t1,0(k0)
+bfc003cc:	24090008 	li	t1,8
+bfc003d0:	3c0af000 	lui	t2,0xf000
+bfc003d4:	010a5024 	and	t2,t0,t2
+bfc003d8:	000a5702 	srl	t2,t2,0x1c
+bfc003dc:	294b000a 	slti	t3,t2,10
+bfc003e0:	11600004 	beqz	t3,bfc003f4 <printx+0x3c>
+bfc003e4:	00000000 	nop
+bfc003e8:	214a0030 	addi	t2,t2,48
+bfc003ec:	0bf000fe 	j	bfc003f8 <printx+0x40>
+bfc003f0:	00000000 	nop
+bfc003f4:	214a0037 	addi	t2,t2,55
+bfc003f8:	a34a0000 	sb	t2,0(k0)
+bfc003fc:	2129ffff 	addi	t1,t1,-1
+bfc00400:	1d20fff3 	bgtz	t1,bfc003d0 <printx+0x18>
+bfc00404:	00084100 	sll	t0,t0,0x4
+bfc00408:	03e00008 	jr	ra
+bfc0040c:	00000000 	nop
+	...
+
+bfc01000 <doload>:
+bfc01000:	3c100000 	lui	s0,0x0
+bfc01004:	26100004 	addiu	s0,s0,4
+bfc01008:	03e00008 	jr	ra
+bfc0100c:	8e050000 	lw	a1,0(s0)
+bfc01010:	24040001 	li	a0,1
+bfc01014:	af640000 	sw	a0,0(k1)
+bfc01018:	0bf00406 	j	bfc01018 <doload+0x18>
+bfc0101c:	00000000 	nop
+bfc01020:	00000000 	nop
+
+Disassembly of section .reginfo:
+
+bfc01024 <.reginfo>:
+bfc01024:	bc010130 	cache	0x1,304(zero)
+	...
+bfc01038:	00008000 	sll	s0,zero,0x0
+
+Disassembly of section .data:
+
+00000000 <myvar>:
+       0:	00000000 	nop
+
+00000004 <testval>:
+       4:	0000beef 	0xbeef
+	...
+
+00001000 <pte2>:
+    1000:	8a000000 	lwl	zero,0(s0)
+    1004:	000bfc00 	sll	ra,t3,0x10
+	...
+
+00002000 <pte22>:
+	...
+
+00004000 <pte1>:
+    4000:	8c000000 	lw	zero,0(zero)
+	...
+    5000:	c0000002 	ll	zero,2(zero)
+	...
+    57f8:	c0000001 	ll	zero,1(zero)
+	...
+    5a04:	84000681 	lh	zero,1665(zero)
+	...
+    5b04:	840006c1 	lh	zero,1729(zero)
+	...
+    5c00:	84000700 	lh	zero,1792(zero)
+	...
Index: branches/v4/softs/tests_ccvcache_v4/test_excep_ls/Makefile
===================================================================
--- branches/v4/softs/tests_ccvcache_v4/test_excep_ls/Makefile	(revision 371)
+++ branches/v4/softs/tests_ccvcache_v4/test_excep_ls/Makefile	(revision 371)
@@ -0,0 +1,1 @@
+include ../Makefile.inc
Index: branches/v4/softs/tests_ccvcache_v4/test_excep_ls/mtty0
===================================================================
--- branches/v4/softs/tests_ccvcache_v4/test_excep_ls/mtty0	(revision 371)
+++ branches/v4/softs/tests_ccvcache_v4/test_excep_ls/mtty0	(revision 371)
@@ -0,0 +1,4 @@
+[20hstart
+mmu started
+status 0x00400002 cause 0x0000001C pc 0xBFC00058 badva 0x00000004
+0x00000004: 0x0000BEEF
Index: branches/v4/softs/tests_ccvcache_v4/test_excep_ls/run
===================================================================
--- branches/v4/softs/tests_ccvcache_v4/test_excep_ls/run	(revision 371)
+++ branches/v4/softs/tests_ccvcache_v4/test_excep_ls/run	(revision 371)
@@ -0,0 +1,33 @@
+#!/bin/sh 
+
+. ../common/common.sh
+
+check_output()
+{
+	egrep "^0x00000004: 0x0000BEEF$" run.out > /dev/null
+	if [ $? -ne 0 ]; then
+		echo "couldn't find string 1 in output - mtty not working ?" >> run.out
+		return 1
+	fi
+	egrep "^status 0x00400002 cause 0x0000001C pc 0xBFC00058 badva 0x00000004$" run.out > /dev/null
+	if [ $? -ne 0 ]; then
+		echo "couldn't find string 2 in output - mtty not working ?" >> run.out
+		return 1
+	fi
+	return 0;
+}
+
+make --quiet || exit 1
+${SIMUL} > run.out 2>&1 
+if [ $? -eq 0 ]; then
+	if check_output; then
+		echo "test passsed";
+		make --quiet clean
+		exit 0;
+	fi
+	echo "test FAILED"
+	exit 1
+fi
+echo "test FAILED"
+exit 1
+
Index: branches/v4/softs/tests_ccvcache_v4/test_excep_ls/test.S
===================================================================
--- branches/v4/softs/tests_ccvcache_v4/test_excep_ls/test.S	(revision 371)
+++ branches/v4/softs/tests_ccvcache_v4/test_excep_ls/test.S	(revision 371)
@@ -0,0 +1,103 @@
+/*
+ * load/store bus fault exception test: we can restart the faulting instruction
+ * We use the MMU to cause fault
+ */
+#include <registers.h>
+#include <misc.h>
+#include <vcache.h>
+	.text
+	.globl  _start
+_start:
+	.set noreorder
+	la	k0, TTY_BASE
+	la	k1, EXIT_BASE
+
+	PRINT(startstr)
+
+	/* reset cop0 status (keep BEV) */
+	lui	a0, 0x0040;
+	mtc0	a0, COP0_STATUS
+
+	la	a0, pte1
+	srl	a0, a0, 13
+	mtc2	a0, VC_PTPR
+	nop
+
+	li	a0, VC_TLB_EN_ITLB | VC_TLB_EN_DTLB | VC_TLB_EN_ICACHE | VC_TLB_EN_DCACHE
+	mtc2 	a0, VC_TLB_EN
+
+	PRINT(mmustr)
+
+	/* 0x00000000 not mapped yet: we fault, load the MMU and retry */
+	move	a1, zero
+	la	s0, testval
+	lw	a1, 0(s0) /* this should trigger the exception */
+	move	a0, s0
+	PRINTX
+	PUTCHAR(':')
+	PUTCHAR(' ')
+	move	a0, a1
+	PRINTX
+	PUTCHAR('\n')
+
+	/* we should get there */
+	EXIT(0)
+
+	.globl excep
+excep:
+	.set noreorder
+	PRINT(statusstr)
+	mfc0	a0, COP0_STATUS
+	PRINTX
+
+	PRINT(causestr)
+	mfc0	a0, COP0_CAUSE
+	PRINTX
+
+	PRINT(pcstr)
+	mfc0	a0, COP0_EXPC
+	PRINTX
+
+	PRINT(badvastr)
+	mfc0	a0, COP_0_BADVADDR
+	PRINTX
+
+	PUTCHAR('\n')
+	/* map VA 0 at PA 0: just copy entry for 0x00200000 */
+	la	t0, pte1 + 0x00200000
+	lw	a0, 4(t0)
+	sw	a0, 0(t0)
+	/* mtc2	zero, VC_DTLB_INVAL */
+	eret
+
+	.rodata:
+statusstr: .ascii "status \0"
+causestr: .ascii " cause \0"
+pcstr: .ascii " pc \0"
+badvastr: .ascii " badva \0"
+mmustr:	.ascii "mmu started\n\0"
+startstr: .ascii "start\n\0"
+
+	.org EXCEP_ADDRESS - BOOT_ADDRESS
+	.globl evect
+evect:
+	j	excep
+	nop
+	.data
+	.word MAGIC1
+testval:
+	.word MAGIC2
+	.globl pte1
+pte1:
+	.align 13
+	.word 0x0                            /* map PA 0 at VA 0 */
+	.word PTE1_V | PTE1_C | PTE1_W | 0x0 /* map PA 0 at VA 0x00200000 */
+	.org pte1 + (BOOT_ADDRESS >> 21) * 4
+	.word PTE1_V | PTE1_C | PTE1_X | (BOOT_ADDRESS >> 21) /* map PA 0xbfc00000 at VA 0xbfc00000 */
+	.org pte1 + (TTY_BASE >> 21) * 4
+	.word PTE1_V | PTE1_W | (TTY_BASE >> 21) /* map PA 0xd0200000 at VA 0xd0200000 */
+	.org pte1 + (EXIT_BASE >> 21) * 4
+	.word PTE1_V | PTE1_W | (EXIT_BASE >> 21) /* map PA 0xe0000000 at VA 0xe0000000 */
+	.org pte1 + 8192
+	.word 0
+
Index: branches/v4/softs/tests_ccvcache_v4/test_excep_ls_delayslot/Makefile
===================================================================
--- branches/v4/softs/tests_ccvcache_v4/test_excep_ls_delayslot/Makefile	(revision 371)
+++ branches/v4/softs/tests_ccvcache_v4/test_excep_ls_delayslot/Makefile	(revision 371)
@@ -0,0 +1,1 @@
+include ../Makefile.inc
Index: branches/v4/softs/tests_ccvcache_v4/test_excep_ls_delayslot/run
===================================================================
--- branches/v4/softs/tests_ccvcache_v4/test_excep_ls_delayslot/run	(revision 371)
+++ branches/v4/softs/tests_ccvcache_v4/test_excep_ls_delayslot/run	(revision 371)
@@ -0,0 +1,33 @@
+#!/bin/sh 
+
+. ../common/common.sh
+
+check_output()
+{
+	egrep "^0x00000004: 0x0000BEEF$" run.out > /dev/null
+	if [ $? -ne 0 ]; then
+		echo "couldn't find string 1 in output - mtty not working ?" >> run.out
+		return 1
+	fi
+	egrep "^status 0x00400002 cause 0x8000001C pc 0xBFC000AC badva 0x00000004$" run.out > /dev/null
+	if [ $? -ne 0 ]; then
+		echo "couldn't find string 2 in output - mtty not working ?" >> run.out
+		return 1
+	fi
+	return 0;
+}
+
+make --quiet || exit 1
+${SIMUL} > run.out 2>&1 
+if [ $? -eq 0 ]; then
+	if check_output; then
+		echo "test passsed";
+		make --quiet clean
+		exit 0;
+	fi
+	echo "test FAILED"
+	exit 1
+fi
+echo "test FAILED"
+exit 1
+
Index: branches/v4/softs/tests_ccvcache_v4/test_excep_ls_delayslot/test.S
===================================================================
--- branches/v4/softs/tests_ccvcache_v4/test_excep_ls_delayslot/test.S	(revision 371)
+++ branches/v4/softs/tests_ccvcache_v4/test_excep_ls_delayslot/test.S	(revision 371)
@@ -0,0 +1,123 @@
+/*
+ * load/store bus fault exception test: we can restart the jump when the
+ * instruction in the delay slot takes a fault.
+ * We use the MMU to cause fault
+ */
+#include <registers.h>
+#include <misc.h>
+#include <vcache.h>
+
+	.text
+	.globl  _start
+_start:
+	.set noreorder
+	la	k0, TTY_BASE
+	la	k1, EXIT_BASE
+	la	sp, 0x00400000 - 16
+
+	PRINT(startstr)
+
+	/* reset cop0 status (keep BEV) */
+	lui	a0, 0x0040;
+	mtc0	a0, COP0_STATUS
+
+	la	a0, pte1
+	srl	a0, a0, 13
+	mtc2	a0, VC_PTPR
+	nop
+
+	li	a0, VC_TLB_EN_ITLB | VC_TLB_EN_DTLB | VC_TLB_EN_ICACHE | VC_TLB_EN_DCACHE
+	mtc2 	a0, VC_TLB_EN
+
+	PRINT(mmustr)
+
+	/* 0x00000000 not mapped yet: we fault, load the MMU and retry */
+	move	a1, zero
+	la	s0, testval
+	jal	doload
+	move	a0, s0
+	PRINTX
+	PUTCHAR(':')
+	PUTCHAR(' ')
+	move	a0, a1
+	PRINTX
+	PUTCHAR('\n')
+
+	/* we should get there */
+	EXIT(0)
+
+	.globl doload
+doload:
+	nop
+	nop
+	jr 	ra
+	lw	a1, 0(s0) /* this should trigger the exception */
+
+	/* we should not get there */
+	EXIT(1)
+
+	.globl excep
+excep:
+	.set noreorder
+	/* don't clobber a0 and ra */
+	addiu	sp, sp, -8
+	sw	a0, 4(sp)
+	sw	ra, 8(sp)
+	PRINT(statusstr)
+	mfc0	a0, COP0_STATUS
+	PRINTX
+
+	PRINT(causestr)
+	mfc0	a0, COP0_CAUSE
+	PRINTX
+
+	PRINT(pcstr)
+	mfc0	a0, COP0_EXPC
+	PRINTX
+
+	PRINT(badvastr)
+	mfc0	a0, COP_0_BADVADDR
+	PRINTX
+
+	PUTCHAR('\n')
+	/* map VA 0 at PA 0: just copy entry for 0x00200000 */
+	la	t0, pte1 + 0x00200000
+	lw	a0, 4(t0)
+	sw	a0, 0(t0)
+	/* mtc2	zero, VC_DTLB_INVAL */
+	lw	a0, 4(sp)
+	lw	ra, 8(sp)
+	addiu	sp, sp, 8
+	eret
+
+	.rodata:
+statusstr: .ascii "status \0"
+causestr: .ascii " cause \0"
+pcstr: .ascii " pc \0"
+badvastr: .ascii " badva \0"
+mmustr:	.ascii "mmu started\n\0"
+startstr: .ascii "start\n\0"
+
+	.org EXCEP_ADDRESS - BOOT_ADDRESS
+	.globl evect
+evect:
+	j	excep
+	nop
+	.data
+	.word MAGIC1
+testval:
+	.word MAGIC2
+	.globl pte1
+pte1:
+	.align 13
+	.word 0x0                            /* map PA 0 at VA 0 */
+	.word PTE1_V | PTE1_C | PTE1_W | 0x0 /* map PA 0 at VA 0x00200000 */
+	.org pte1 + (BOOT_ADDRESS >> 21) * 4
+	.word PTE1_V | PTE1_C | PTE1_X | (BOOT_ADDRESS >> 21) /* map PA 0xbfc00000 at VA 0xbfc00000 */
+	.org pte1 + (TTY_BASE >> 21) * 4
+	.word PTE1_V | PTE1_W | (TTY_BASE >> 21) /* map PA 0xd0200000 at VA 0xd0200000 */
+	.org pte1 + (EXIT_BASE >> 21) * 4
+	.word PTE1_V | PTE1_W | (EXIT_BASE >> 21) /* map PA 0xe0000000 at VA 0xe0000000 */
+	.org pte1 + 8192
+	.word 0
+
Index: branches/v4/softs/tests_ccvcache_v4/test_excep_ls_llsc/Makefile
===================================================================
--- branches/v4/softs/tests_ccvcache_v4/test_excep_ls_llsc/Makefile	(revision 371)
+++ branches/v4/softs/tests_ccvcache_v4/test_excep_ls_llsc/Makefile	(revision 371)
@@ -0,0 +1,1 @@
+include ../Makefile.inc
Index: branches/v4/softs/tests_ccvcache_v4/test_excep_ls_llsc/run
===================================================================
--- branches/v4/softs/tests_ccvcache_v4/test_excep_ls_llsc/run	(revision 371)
+++ branches/v4/softs/tests_ccvcache_v4/test_excep_ls_llsc/run	(revision 371)
@@ -0,0 +1,33 @@
+#!/bin/sh 
+
+. ../common/common.sh
+
+check_output()
+{
+	egrep "^0x00000004: 0x0000BEEF$" run.out > /dev/null
+	if [ $? -ne 0 ]; then
+		echo "couldn't find string 1 in output - mtty not working ?" >> run.out
+		return 1
+	fi
+	egrep "^status 0x00400002 cause 0x0000001C pc 0xBFC00058 badva 0x00000004$" run.out > /dev/null
+	if [ $? -ne 0 ]; then
+		echo "couldn't find string 2 in output - mtty not working ?" >> run.out
+		return 1
+	fi
+	return 0;
+}
+
+make --quiet || exit 1
+${SIMUL} > run.out 2>&1 
+if [ $? -eq 0 ]; then
+	if check_output; then
+		echo "test passsed";
+		make --quiet clean
+		exit 0;
+	fi
+	echo "test FAILED"
+	exit 1
+fi
+echo "test FAILED"
+exit 1
+
Index: branches/v4/softs/tests_ccvcache_v4/test_excep_ls_llsc/test.S
===================================================================
--- branches/v4/softs/tests_ccvcache_v4/test_excep_ls_llsc/test.S	(revision 371)
+++ branches/v4/softs/tests_ccvcache_v4/test_excep_ls_llsc/test.S	(revision 371)
@@ -0,0 +1,107 @@
+/*
+ * load/store bus fault exception test: we can restart the faulting instruction
+ * We use the MMU to cause fault
+ * Match what NetBSD does for page table update: sw for ppn, ll/sc for flags
+ */
+#include <registers.h>
+#include <misc.h>
+#include <vcache.h>
+	.text
+	.globl  _start
+_start:
+	.set noreorder
+	la	k0, TTY_BASE
+	la	k1, EXIT_BASE
+
+	PRINT(startstr)
+
+	/* reset cop0 status (keep BEV) */
+	lui	a0, 0x0040;
+	mtc0	a0, COP0_STATUS
+
+	la	a0, pte1
+	srl	a0, a0, 13
+	mtc2	a0, VC_PTPR
+	nop
+
+	li	a0, VC_TLB_EN_ITLB | VC_TLB_EN_DTLB | VC_TLB_EN_ICACHE | VC_TLB_EN_DCACHE
+	mtc2 	a0, VC_TLB_EN
+
+	PRINT(mmustr)
+
+	/* 0x00000000 not mapped yet: we fault, load the MMU and retry */
+	move	a1, zero
+	la	s0, testval
+	lw	a1, 0(s0) /* this should trigger the exception */
+	move	a0, s0
+	PRINTX
+	PUTCHAR(':')
+	PUTCHAR(' ')
+	move	a0, a1
+	PRINTX
+	PUTCHAR('\n')
+
+	/* we should get there */
+	EXIT(0)
+
+	.globl excep
+excep:
+	.set noreorder
+	PRINT(statusstr)
+	mfc0	a0, COP0_STATUS
+	PRINTX
+
+	PRINT(causestr)
+	mfc0	a0, COP0_CAUSE
+	PRINTX
+
+	PRINT(pcstr)
+	mfc0	a0, COP0_EXPC
+	PRINTX
+
+	PRINT(badvastr)
+	mfc0	a0, COP_0_BADVADDR
+	PRINTX
+
+	PUTCHAR('\n')
+	/* map VA 0 at PA 0: just copy entry for 0x00200000 */
+	la	t0, pte1 + 0x00200000
+1:
+	ll	a0, 0(t0)
+	lw	a0, 4(t0)
+	sc	a0, 0(t0)
+	beqz	a0, 1b
+	/* mtc2	zero, VC_DTLB_INVAL */
+	eret
+
+	.rodata:
+statusstr: .ascii "status \0"
+causestr: .ascii " cause \0"
+pcstr: .ascii " pc \0"
+badvastr: .ascii " badva \0"
+mmustr:	.ascii "mmu started\n\0"
+startstr: .ascii "start\n\0"
+
+	.org EXCEP_ADDRESS - BOOT_ADDRESS
+	.globl evect
+evect:
+	j	excep
+	nop
+	.data
+	.word MAGIC1
+testval:
+	.word MAGIC2
+	.globl pte1
+pte1:
+	.align 13
+	.word 0x0                            /* map PA 0 at VA 0 */
+	.word PTE1_V | PTE1_C | PTE1_W | 0x0 /* map PA 0 at VA 0x00200000 */
+	.org pte1 + (BOOT_ADDRESS >> 21) * 4
+	.word PTE1_V | PTE1_C | PTE1_X | (BOOT_ADDRESS >> 21) /* map PA 0xbfc00000 at VA 0xbfc00000 */
+	.org pte1 + (TTY_BASE >> 21) * 4
+	.word PTE1_V | PTE1_W | (TTY_BASE >> 21) /* map PA 0xd0200000 at VA 0xd0200000 */
+	.org pte1 + (EXIT_BASE >> 21) * 4
+	.word PTE1_V | PTE1_W | (EXIT_BASE >> 21) /* map PA 0xe0000000 at VA 0xe0000000 */
+	.org pte1 + 8192
+	.word 0
+
Index: branches/v4/softs/tests_ccvcache_v4/test_exception_epc_modify/Makefile
===================================================================
--- branches/v4/softs/tests_ccvcache_v4/test_exception_epc_modify/Makefile	(revision 371)
+++ branches/v4/softs/tests_ccvcache_v4/test_exception_epc_modify/Makefile	(revision 371)
@@ -0,0 +1,1 @@
+include ../Makefile.inc
Index: branches/v4/softs/tests_ccvcache_v4/test_exception_epc_modify/run
===================================================================
--- branches/v4/softs/tests_ccvcache_v4/test_exception_epc_modify/run	(revision 371)
+++ branches/v4/softs/tests_ccvcache_v4/test_exception_epc_modify/run	(revision 371)
@@ -0,0 +1,28 @@
+#!/bin/sh 
+
+. ../common/common.sh
+
+check_output()
+{
+	egrep "^eret$" run.out > /dev/null
+	if [ $? -eq 0 ]; then
+		return 0;
+	fi
+	echo "couldn't find string in output - mtty not working ?" >> run.out
+	return 1
+}
+
+make --quiet || exit 1
+${SIMUL} > run.out 2>&1 
+if [ $? -eq 0 ]; then
+	if check_output; then
+		echo "test passsed";
+		make --quiet clean
+		exit 0;
+	fi
+	echo "test FAILED"
+	exit 1
+fi
+echo "test FAILED"
+exit 1
+
Index: branches/v4/softs/tests_ccvcache_v4/test_exception_epc_modify/test.S
===================================================================
--- branches/v4/softs/tests_ccvcache_v4/test_exception_epc_modify/test.S	(revision 371)
+++ branches/v4/softs/tests_ccvcache_v4/test_exception_epc_modify/test.S	(revision 371)
@@ -0,0 +1,71 @@
+/*
+ * Check that on return from exception the modified EPC is handled.
+ * We use a load to an unaligned address to trigger the exception.
+ */
+#include <registers.h>
+#include <misc.h>
+
+	.text
+	.globl  _start
+_start:
+	.set noreorder
+	la	k0, TTY_BASE
+	la	k1, EXIT_BASE
+
+	PRINT(startstr)
+
+	/* reset cop0 status (keep BEV) */
+	lui	a0, 0x0040;
+	mtc0	a0, COP0_STATUS
+
+	li	a0, 1
+	lw	a0, 0(a0) /* fault */
+
+	/* we shouldn't get there */
+	EXIT(1)
+
+	.globl exret
+
+exret:
+	PRINT(eretstr)
+	EXIT(0)
+
+	.globl excep
+excep:
+	.set noreorder
+	PRINT(statusstr)
+	mfc0	a0, COP0_STATUS
+	PRINTX
+
+	PRINT(causestr)
+	mfc0	a0, COP0_CAUSE
+	PRINTX
+
+	PRINT(pcstr)
+	mfc0	a0, COP0_EXPC
+	PRINTX
+
+	PRINT(badvastr)
+	mfc0	a0, COP_0_BADVADDR
+	PRINTX
+
+	PUTCHAR('\n')
+	la	a0, exret
+	mtc0	a0, COP0_EXPC
+	eret
+
+	.rodata:
+statusstr: .ascii "status \0"
+causestr: .ascii " cause \0"
+pcstr: .ascii " pc \0"
+badvastr: .ascii " badva \0"
+startstr: .ascii "start\n\0"
+eretstr: .ascii "eret\n\0"
+
+	.org EXCEP_ADDRESS - BOOT_ADDRESS
+	.globl evect
+evect:
+	j	excep
+	nop
+	.data
+myvar:	.word 0
Index: branches/v4/softs/tests_ccvcache_v4/test_exceptions/Makefile
===================================================================
--- branches/v4/softs/tests_ccvcache_v4/test_exceptions/Makefile	(revision 371)
+++ branches/v4/softs/tests_ccvcache_v4/test_exceptions/Makefile	(revision 371)
@@ -0,0 +1,1 @@
+include ../Makefile.inc
Index: branches/v4/softs/tests_ccvcache_v4/test_exceptions/run
===================================================================
--- branches/v4/softs/tests_ccvcache_v4/test_exceptions/run	(revision 371)
+++ branches/v4/softs/tests_ccvcache_v4/test_exceptions/run	(revision 371)
@@ -0,0 +1,28 @@
+#!/bin/sh 
+
+. ../common/common.sh
+
+check_output()
+{
+	egrep "^status 0x00400006 cause 0x00000010 pc 0xBFC0001C badva 0x00000001$" run.out > /dev/null
+	if [ $? -eq 0 ]; then
+		return 0;
+	fi
+	echo "couldn't find string in output - mtty not working ?" >> run.out
+	return 1
+}
+
+make --quiet || exit 1
+${SIMUL} > run.out 2>&1 
+if [ $? -eq 0 ]; then
+	if check_output; then
+		echo "test passsed";
+		make --quiet clean
+		exit 0;
+	fi
+	echo "test FAILED"
+	exit 1
+fi
+echo "test FAILED"
+exit 1
+
Index: branches/v4/softs/tests_ccvcache_v4/test_exceptions/test.S
===================================================================
--- branches/v4/softs/tests_ccvcache_v4/test_exceptions/test.S	(revision 371)
+++ branches/v4/softs/tests_ccvcache_v4/test_exceptions/test.S	(revision 371)
@@ -0,0 +1,60 @@
+/*
+ * Check that the exeption vector is called on exception.
+ * We use a load to an unaligned address to trigger the exception.
+ */
+#include <registers.h>
+#include <misc.h>
+
+	.text
+	.globl  _start
+_start:
+	.set noreorder
+	la	k0, TTY_BASE
+	la	k1, EXIT_BASE
+
+	PRINT(startstr)
+
+	li	a0, 1
+	lw	a0, 0(a0) /* fault */
+
+	/* we shouldn't get there */
+        EXIT(1)
+
+	.globl excep
+excep:
+	.set noreorder
+	PRINT(statusstr)
+	mfc0	a0, COP0_STATUS
+	PRINTX
+
+	PRINT(causestr)
+	mfc0	a0, COP0_CAUSE
+	PRINTX
+
+	PRINT(pcstr)
+	mfc0	a0, COP0_EXPC
+	PRINTX
+
+	PRINT(badvastr)
+	mfc0	a0, COP_0_BADVADDR
+	PRINTX
+
+	li	a0, '\n'
+	sb	a0, 0(k0)
+
+	EXIT(0)
+
+	.rodata:
+statusstr: .ascii "status \0"
+causestr: .ascii " cause \0"
+pcstr: .ascii " pc \0"
+badvastr: .ascii " badva \0"
+startstr: .ascii "start\n\0"
+
+	.org EXCEP_ADDRESS - BOOT_ADDRESS
+	.globl evect
+evect:
+	j	excep
+	nop
+	.data
+myvar:	.word 0
Index: branches/v4/softs/tests_ccvcache_v4/test_fpe_delayslot/Makefile
===================================================================
--- branches/v4/softs/tests_ccvcache_v4/test_fpe_delayslot/Makefile	(revision 371)
+++ branches/v4/softs/tests_ccvcache_v4/test_fpe_delayslot/Makefile	(revision 371)
@@ -0,0 +1,1 @@
+include ../Makefile.inc
Index: branches/v4/softs/tests_ccvcache_v4/test_fpe_delayslot/mtty0
===================================================================
--- branches/v4/softs/tests_ccvcache_v4/test_fpe_delayslot/mtty0	(revision 371)
+++ branches/v4/softs/tests_ccvcache_v4/test_fpe_delayslot/mtty0	(revision 371)
@@ -0,0 +1,2 @@
+[20hstart
+0x00000000 0x00000000
Index: branches/v4/softs/tests_ccvcache_v4/test_fpe_delayslot/run
===================================================================
--- branches/v4/softs/tests_ccvcache_v4/test_fpe_delayslot/run	(revision 371)
+++ branches/v4/softs/tests_ccvcache_v4/test_fpe_delayslot/run	(revision 371)
@@ -0,0 +1,28 @@
+#!/bin/sh 
+
+. ../common/common.sh
+
+check_output()
+{
+	egrep "^status 0x00400002 cause 0x80000034 pc 0xBFC00034 badva 0x00000000$" run.out > /dev/null
+	if [ $? -ne 0 ]; then
+		echo "couldn't find string 1 in output - mtty not working ?" >> run.out
+		return 1
+	fi
+	return 0;
+}
+
+make --quiet || exit 1
+${SIMUL} > run.out 2>&1 
+if [ $? -eq 0 ]; then
+	if check_output; then
+		echo "test passsed";
+		make --quiet clean
+		exit 0;
+	fi
+	echo "test FAILED"
+	exit 1
+fi
+echo "test FAILED"
+exit 1
+
Index: branches/v4/softs/tests_ccvcache_v4/test_fpe_delayslot/run.out
===================================================================
--- branches/v4/softs/tests_ccvcache_v4/test_fpe_delayslot/run.out	(revision 371)
+++ branches/v4/softs/tests_ccvcache_v4/test_fpe_delayslot/run.out	(revision 371)
@@ -0,0 +1,23 @@
+
+             SystemC 2.2.0 --- Apr 14 2011 18:52:40
+        Copyright (c) 1996-2006 by all Contributors
+                    ALL RIGHTS RESERVED
+Mapping table: ad:(6) id:(6) cacheability mask: 0xf0000000
+ <Segment "memc_d": base = 0 / size = 0x2000000 / tgtid = (0) / cached>
+ <Segment "boot_d": base = 0xbfc00000 / size = 0x40000 / tgtid = (1) / cached>
+ <Segment "exit_d": base = 0xe0000000 / size = 0x4 / tgtid = (2) / uncached>
+ <Segment "mtty_d": base = 0xd0200000 / size = 0x10 / tgtid = (3) / uncached>
+ <Segment "xicu_d": base = 0xd8200000 / size = 0x1000 / tgtid = (4) / uncached>
+ <Segment "mdma_d": base = 0xe8000000 / size = 0x14 / tgtid = (5) / uncached>
+
+Mapping table: ad:(6) id:(6) cacheability mask: 0xf0000000
+ <Segment "proc_c": base = 0x10000000 / size = 0x10 / tgtid = (0) / uncached / init = (0)>
+ <Segment "memc_c": base = 0 / size = 0x2000010 / tgtid = (1) / uncached>
+ <Segment "brom_c": base = 0xbfc00000 / size = 0x40000 / tgtid = (1) / uncached>
+
+Loading at 0xbfc00000 size 262144: .text .reginfo 
+Loading at 0 size 33554432: .data 
+start
+0x00000000 0x00000000
+vci_exit terminate simulation, status 0d0
+couldn't find string 1 in output - mtty not working ?
Index: branches/v4/softs/tests_ccvcache_v4/test_fpe_delayslot/subr.o.txt
===================================================================
--- branches/v4/softs/tests_ccvcache_v4/test_fpe_delayslot/subr.o.txt	(revision 371)
+++ branches/v4/softs/tests_ccvcache_v4/test_fpe_delayslot/subr.o.txt	(revision 371)
@@ -0,0 +1,49 @@
+
+subr.o:     file format elf32-littlemips
+
+
+Disassembly of section .text:
+
+00000000 <print>:
+   0:	00804021 	move	t0,a0
+   4:	81090000 	lb	t1,0(t0)
+   8:	11200005 	beqz	t1,20 <end>
+   c:	00000000 	nop
+  10:	a3490000 	sb	t1,0(k0)
+  14:	25080001 	addiu	t0,t0,1
+  18:	08000001 	j	4 <print+0x4>
+  1c:	00000000 	nop
+
+00000020 <end>:
+  20:	03e00008 	jr	ra
+  24:	00000000 	nop
+
+00000028 <printx>:
+  28:	00804021 	move	t0,a0
+  2c:	24090030 	li	t1,48
+  30:	a3490000 	sb	t1,0(k0)
+  34:	24090078 	li	t1,120
+  38:	a3490000 	sb	t1,0(k0)
+  3c:	24090008 	li	t1,8
+  40:	3c0af000 	lui	t2,0xf000
+  44:	010a5024 	and	t2,t0,t2
+  48:	000a5702 	srl	t2,t2,0x1c
+  4c:	294b000a 	slti	t3,t2,10
+  50:	11600004 	beqz	t3,64 <printx+0x3c>
+  54:	00000000 	nop
+  58:	214a0030 	addi	t2,t2,48
+  5c:	0800001a 	j	68 <printx+0x40>
+  60:	00000000 	nop
+  64:	214a0037 	addi	t2,t2,55
+  68:	a34a0000 	sb	t2,0(k0)
+  6c:	2129ffff 	addi	t1,t1,-1
+  70:	1d20fff3 	bgtz	t1,40 <printx+0x18>
+  74:	00084100 	sll	t0,t0,0x4
+  78:	03e00008 	jr	ra
+  7c:	00000000 	nop
+
+Disassembly of section .reginfo:
+
+00000000 <.reginfo>:
+   0:	84000f10 	lh	zero,3856(zero)
+	...
Index: branches/v4/softs/tests_ccvcache_v4/test_fpe_delayslot/temp
===================================================================
--- branches/v4/softs/tests_ccvcache_v4/test_fpe_delayslot/temp	(revision 371)
+++ branches/v4/softs/tests_ccvcache_v4/test_fpe_delayslot/temp	(revision 371)
@@ -0,0 +1,8775 @@
+Mapping table: ad:(6) id:(6) cacheability mask: 0xf0000000
+ <Segment "memc_d": base = 0 / size = 0x2000000 / tgtid = (0) / cached>
+ <Segment "boot_d": base = 0xbfc00000 / size = 0x40000 / tgtid = (1) / cached>
+ <Segment "exit_d": base = 0xe0000000 / size = 0x4 / tgtid = (2) / uncached>
+ <Segment "mtty_d": base = 0xd0200000 / size = 0x10 / tgtid = (3) / uncached>
+ <Segment "xicu_d": base = 0xd8200000 / size = 0x1000 / tgtid = (4) / uncached>
+ <Segment "mdma_d": base = 0xe8000000 / size = 0x14 / tgtid = (5) / uncached>
+
+Mapping table: ad:(6) id:(6) cacheability mask: 0xf0000000
+ <Segment "proc_c": base = 0x10000000 / size = 0x10 / tgtid = (0) / uncached / init = (0)>
+ <Segment "memc_c": base = 0 / size = 0x2000010 / tgtid = (1) / uncached>
+ <Segment "brom_c": base = 0xbfc00000 / size = 0x40000 / tgtid = (1) / uncached>
+
+Loading at 0xbfc00000 size 262144: .text .reginfo 
+Loading at 0 size 33554432: .data 
+****************** cycle 1 ************************************************
+PROC proc
+  <InsReq  invalid mode MODE_HYPER @ 0>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 2 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00000>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 3 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00000>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_VICTIM | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 4 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00000>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_INS_MISS | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d CMD VCI : RD  @ = 0x0bfc00000  wdata = 0x000000000  srcid = 0x0000  trdid = 0x03  plen  = 0x040  eop = 0x1  ack = 0x1
+****************** cycle 5 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00000>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 6 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00000>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 7 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00000>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 8 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00000>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 9 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00000>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 10 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00000>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 11 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00000>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x03c1ad020 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0
+****************** cycle 12 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00000>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x03c1ad020 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 13 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00000>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x03c1be000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 14 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00000>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x03c1d003f | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0
+****************** cycle 15 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00000>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x03c1d003f | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 16 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00000>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x037bdfff0 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 17 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00000>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x03c04bfc0 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 18 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00000>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x024840155 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 19 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00000>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x00ff000e4 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 20 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00000>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 21 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00000>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x03c042040 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 22 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00000>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x040846000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 23 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00000>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x03c040000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 24 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00000>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x024840008 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 25 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00000>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x0c4820000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 26 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00000>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x03c040000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 27 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00000>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x02484000c | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 28 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00000>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x0c4800000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0x1 | ack = 0x1
+****************** cycle 29 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00000>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 30 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00000>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 31 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00000>
+  <InsRsp    valid no error ins 0x3c1ad020>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 32 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00004>
+  <InsRsp    valid no error ins 0x3c1be000>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 33 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00008>
+  <InsRsp    valid no error ins 0x3c1d003f>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 34 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc0000c>
+  <InsRsp    valid no error ins 0x37bdfff0>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 35 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00010>
+  <InsRsp    valid no error ins 0x3c04bfc0>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 36 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00014>
+  <InsRsp    valid no error ins 0x24840155>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 37 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00018>
+  <InsRsp    valid no error ins 0xff000e4>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 38 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc0001c>
+  <InsRsp    valid no error ins 0>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 39 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00390>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_VICTIM | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 40 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00390>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_INS_MISS | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d CMD VCI : RD  @ = 0x0bfc00380  wdata = 0x000000000  srcid = 0x0000  trdid = 0x03  plen  = 0x040  eop = 0x1  ack = 0x1
+****************** cycle 41 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00390>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 42 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00390>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 43 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00390>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 44 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00390>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 45 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00390>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 46 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00390>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 47 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00390>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x00bf00024 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0
+****************** cycle 48 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00390>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x00bf00024 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 49 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00390>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 50 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00390>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0
+****************** cycle 51 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00390>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 52 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00390>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 53 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00390>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000804021 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 54 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00390>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x081090000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 55 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00390>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x011200005 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 56 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00390>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 57 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00390>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x0a3490000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 58 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00390>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x025080001 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 59 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00390>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x00bf000e5 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 60 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00390>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 61 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00390>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x003e00008 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 62 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00390>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 63 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00390>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000804021 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 64 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00390>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x024090030 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0x1 | ack = 0x1
+****************** cycle 65 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00390>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 66 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00390>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 67 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00390>
+  <InsRsp    valid no error ins 0x804021>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 68 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00394>
+  <InsRsp    valid no error ins 0x81090000>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 69 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
+  <InsRsp    valid no error ins 0x11200005>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0xbfc00154 wdata 0 be 0x2>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 70 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
+  <InsRsp    valid no error ins 0x11200005>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0xbfc00154 wdata 0 be 0x2>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_VICTIM | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+  <PROC.DCACHE_MISS_VICTIM> Select a slot: / way = 0 / set = 0x5 / valid = 0 / line = 0x000000005
+****************** cycle 71 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
+  <InsRsp    valid no error ins 0x11200005>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0xbfc00154 wdata 0 be 0x2>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_DATA_MISS | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d CMD VCI : RD  @ = 0x0bfc00140  wdata = 0x000000000  srcid = 0x0000  trdid = 0x01  plen  = 0x040  eop = 0x1  ack = 0x1
+****************** cycle 72 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
+  <InsRsp    valid no error ins 0x11200005>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0xbfc00154 wdata 0 be 0x2>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 73 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
+  <InsRsp    valid no error ins 0x11200005>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0xbfc00154 wdata 0 be 0x2>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 74 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
+  <InsRsp    valid no error ins 0x11200005>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0xbfc00154 wdata 0 be 0x2>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 75 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
+  <InsRsp    valid no error ins 0x11200005>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0xbfc00154 wdata 0 be 0x2>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 76 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
+  <InsRsp    valid no error ins 0x11200005>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0xbfc00154 wdata 0 be 0x2>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 77 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
+  <InsRsp    valid no error ins 0x11200005>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0xbfc00154 wdata 0 be 0x2>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 78 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
+  <InsRsp    valid no error ins 0x11200005>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0xbfc00154 wdata 0 be 0x2>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x075616320 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0
+****************** cycle 79 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
+  <InsRsp    valid no error ins 0x11200005>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0xbfc00154 wdata 0 be 0x2>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_DATA_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x075616320 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1
+****************** cycle 80 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
+  <InsRsp    valid no error ins 0x11200005>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0xbfc00154 wdata 0 be 0x2>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_DATA_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000206573 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1
+****************** cycle 81 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
+  <InsRsp    valid no error ins 0x11200005>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0xbfc00154 wdata 0 be 0x2>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_UPDT | CMD_IDLE | RSP_DATA_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x020637020 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0
+  <PROC.DCACHE_MISS_UPDT> Write one word: address = 0x0bfc00154 / data = 0x75616320 / way = 0 / set = 0x5 / word = 0
+****************** cycle 82 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
+  <InsRsp    valid no error ins 0x11200005>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0xbfc00154 wdata 0 be 0x2>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_UPDT | CMD_IDLE | RSP_DATA_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x020637020 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1
+  <PROC.DCACHE_MISS_UPDT> Write one word: address = 0x0bfc00154 / data = 0x206573 / way = 0 / set = 0x5 / word = 0x1
+****************** cycle 83 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
+  <InsRsp    valid no error ins 0x11200005>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0xbfc00154 wdata 0 be 0x2>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_UPDT | CMD_IDLE | RSP_DATA_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x061622000 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1
+  <PROC.DCACHE_MISS_UPDT> Write one word: address = 0x0bfc00154 / data = 0x20637020 / way = 0 / set = 0x5 / word = 0x2
+****************** cycle 84 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
+  <InsRsp    valid no error ins 0x11200005>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0xbfc00154 wdata 0 be 0x2>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_UPDT | CMD_IDLE | RSP_DATA_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x020617664 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1
+  <PROC.DCACHE_MISS_UPDT> Write one word: address = 0x0bfc00154 / data = 0x61622000 / way = 0 / set = 0x5 / word = 0x3
+****************** cycle 85 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
+  <InsRsp    valid no error ins 0x11200005>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0xbfc00154 wdata 0 be 0x2>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_UPDT | CMD_IDLE | RSP_DATA_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x061747300 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1
+  <PROC.DCACHE_MISS_UPDT> Write one word: address = 0x0bfc00154 / data = 0x20617664 / way = 0 / set = 0x5 / word = 0x4
+****************** cycle 86 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
+  <InsRsp    valid no error ins 0x11200005>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0xbfc00154 wdata 0 be 0x2>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_UPDT | CMD_IDLE | RSP_DATA_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x0000a7472 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1
+  <PROC.DCACHE_MISS_UPDT> Write one word: address = 0x0bfc00154 / data = 0x61747300 / way = 0 / set = 0x5 / word = 0x5
+****************** cycle 87 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
+  <InsRsp    valid no error ins 0x11200005>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0xbfc00154 wdata 0 be 0x2>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_UPDT | CMD_IDLE | RSP_DATA_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x06d727375 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1
+  <PROC.DCACHE_MISS_UPDT> Write one word: address = 0x0bfc00154 / data = 0xa7472 / way = 0 / set = 0x5 / word = 0x6
+****************** cycle 88 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
+  <InsRsp    valid no error ins 0x11200005>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0xbfc00154 wdata 0 be 0x2>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_UPDT | CMD_IDLE | RSP_DATA_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x00a65646f | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1
+  <PROC.DCACHE_MISS_UPDT> Write one word: address = 0x0bfc00154 / data = 0x6d727375 / way = 0 / set = 0x5 / word = 0x7
+****************** cycle 89 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
+  <InsRsp    valid no error ins 0x11200005>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0xbfc00154 wdata 0 be 0x2>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_UPDT | CMD_IDLE | RSP_DATA_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1
+  <PROC.DCACHE_MISS_UPDT> Write one word: address = 0x0bfc00154 / data = 0xa65646f / way = 0 / set = 0x5 / word = 0x8
+****************** cycle 90 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
+  <InsRsp    valid no error ins 0x11200005>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0xbfc00154 wdata 0 be 0x2>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_UPDT | CMD_IDLE | RSP_DATA_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1
+  <PROC.DCACHE_MISS_UPDT> Write one word: address = 0x0bfc00154 / data = 0 / way = 0 / set = 0x5 / word = 0x9
+****************** cycle 91 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
+  <InsRsp    valid no error ins 0x11200005>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0xbfc00154 wdata 0 be 0x2>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_UPDT | CMD_IDLE | RSP_DATA_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1
+  <PROC.DCACHE_MISS_UPDT> Write one word: address = 0x0bfc00154 / data = 0 / way = 0 / set = 0x5 / word = 0xa
+****************** cycle 92 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
+  <InsRsp    valid no error ins 0x11200005>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0xbfc00154 wdata 0 be 0x2>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_UPDT | CMD_IDLE | RSP_DATA_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1
+  <PROC.DCACHE_MISS_UPDT> Write one word: address = 0x0bfc00154 / data = 0 / way = 0 / set = 0x5 / word = 0xb
+****************** cycle 93 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
+  <InsRsp    valid no error ins 0x11200005>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0xbfc00154 wdata 0 be 0x2>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_UPDT | CMD_IDLE | RSP_DATA_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1
+  <PROC.DCACHE_MISS_UPDT> Write one word: address = 0x0bfc00154 / data = 0 / way = 0 / set = 0x5 / word = 0xc
+****************** cycle 94 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
+  <InsRsp    valid no error ins 0x11200005>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0xbfc00154 wdata 0 be 0x2>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_UPDT | CMD_IDLE | RSP_DATA_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1
+  <PROC.DCACHE_MISS_UPDT> Write one word: address = 0x0bfc00154 / data = 0 / way = 0 / set = 0x5 / word = 0xd
+****************** cycle 95 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
+  <InsRsp    valid no error ins 0x11200005>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0xbfc00154 wdata 0 be 0x2>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_UPDT | CMD_IDLE | RSP_DATA_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0x1 | ack = 0x1
+  <PROC.DCACHE_MISS_UPDT> Write one word: address = 0x0bfc00154 / data = 0 / way = 0 / set = 0x5 / word = 0xe
+****************** cycle 96 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
+  <InsRsp    valid no error ins 0x11200005>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0xbfc00154 wdata 0 be 0x2>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_UPDT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+  <PROC.DCACHE_MISS_UPDT> Write one word: address = 0x0bfc00154 / data = 0 / way = 0 / set = 0x5 / word = 0xf
+****************** cycle 97 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
+  <InsRsp    valid no error ins 0x11200005>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0xbfc00154 wdata 0 be 0x2>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+  <PROC.DCACHE_IDLE> HIT in dcache
+****************** cycle 98 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
+  <InsRsp    valid no error ins 0x11200005>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0xbfc00154 wdata 0 be 0x2>
+  <DataRsp   valid no error rdata 0x61747300>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 99 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
+  <InsRsp    valid no error ins 0x11200005>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xbfc00154 wdata 0 be 0x2>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 100 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc0039c>
+  <InsRsp    valid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xbfc00154 wdata 0 be 0x2>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 101 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003a0>
+  <InsRsp    valid no error ins 0xa3490000>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xbfc00154 wdata 0 be 0x2>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 102 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003a4>
+  <InsRsp    valid no error ins 0x25080001>
+  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x73 be 0x1>
+  <DataRsp   valid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 103 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003a8>
+  <InsRsp    valid no error ins 0xbf000e5>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x73 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 104 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003ac>
+  <InsRsp    valid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x73 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_DATA_WRITE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d CMD VCI : WR  @ = 0x0d0200000  wdata = 0x000000073  srcid = 0x0000  trdid = 0x08  plen  = 0x004  eop = 0x1  ack = 0x1
+****************** cycle 105 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00394>
+  <InsRsp    valid no error ins 0x81090000>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x73 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 106 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
+  <InsRsp    valid no error ins 0x11200005>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0xbfc00154 wdata 0 be 0x4>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+  <PROC.DCACHE_IDLE> HIT in dcache
+****************** cycle 107 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
+  <InsRsp    valid no error ins 0x11200005>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0xbfc00154 wdata 0 be 0x4>
+  <DataRsp   valid no error rdata 0x61747300>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 108 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
+  <InsRsp    valid no error ins 0x11200005>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xbfc00154 wdata 0 be 0x4>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 109 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc0039c>
+  <InsRsp    valid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xbfc00154 wdata 0 be 0x4>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 110 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003a0>
+  <InsRsp    valid no error ins 0xa3490000>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xbfc00154 wdata 0 be 0x4>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 111 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003a4>
+  <InsRsp    valid no error ins 0x25080001>
+  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x74 be 0x1>
+  <DataRsp   valid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0
+****************** cycle 112 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003a8>
+  <InsRsp    valid no error ins 0xbf000e5>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x74 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_DATA_WRITE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0x1
+****************** cycle 113 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003ac>
+  <InsRsp    valid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x74 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 114 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00394>
+  <InsRsp    valid no error ins 0x81090000>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x74 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 115 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
+  <InsRsp    valid no error ins 0x11200005>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0xbfc00154 wdata 0 be 0x8>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_DATA_WRITE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d CMD VCI : WR  @ = 0x0d0200000  wdata = 0x000000074  srcid = 0x0000  trdid = 0x08  plen  = 0x004  eop = 0x1  ack = 0x1
+  <PROC.DCACHE_IDLE> HIT in dcache
+****************** cycle 116 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
+  <InsRsp    valid no error ins 0x11200005>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0xbfc00154 wdata 0 be 0x8>
+  <DataRsp   valid no error rdata 0x61747300>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 117 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
+  <InsRsp    valid no error ins 0x11200005>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xbfc00154 wdata 0 be 0x8>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 118 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc0039c>
+  <InsRsp    valid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xbfc00154 wdata 0 be 0x8>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 119 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003a0>
+  <InsRsp    valid no error ins 0xa3490000>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xbfc00154 wdata 0 be 0x8>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 120 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003a4>
+  <InsRsp    valid no error ins 0x25080001>
+  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x61 be 0x1>
+  <DataRsp   valid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 121 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003a8>
+  <InsRsp    valid no error ins 0xbf000e5>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x61 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 122 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003ac>
+  <InsRsp    valid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x61 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0
+****************** cycle 123 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00394>
+  <InsRsp    valid no error ins 0x81090000>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x61 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_DATA_WRITE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0x1
+****************** cycle 124 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
+  <InsRsp    valid no error ins 0x11200005>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0xbfc00158 wdata 0 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 125 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
+  <InsRsp    valid no error ins 0x11200005>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0xbfc00158 wdata 0 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+  <PROC.DCACHE_IDLE> HIT in dcache
+****************** cycle 126 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
+  <InsRsp    valid no error ins 0x11200005>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0xbfc00158 wdata 0 be 0x1>
+  <DataRsp   valid no error rdata 0xa7472>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_DATA_WRITE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d CMD VCI : WR  @ = 0x0d0200000  wdata = 0x000000061  srcid = 0x0000  trdid = 0x08  plen  = 0x004  eop = 0x1  ack = 0x1
+****************** cycle 127 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
+  <InsRsp    valid no error ins 0x11200005>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xbfc00158 wdata 0 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 128 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc0039c>
+  <InsRsp    valid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xbfc00158 wdata 0 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 129 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003a0>
+  <InsRsp    valid no error ins 0xa3490000>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xbfc00158 wdata 0 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 130 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003a4>
+  <InsRsp    valid no error ins 0x25080001>
+  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x72 be 0x1>
+  <DataRsp   valid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 131 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003a8>
+  <InsRsp    valid no error ins 0xbf000e5>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x72 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 132 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003ac>
+  <InsRsp    valid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x72 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 133 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00394>
+  <InsRsp    valid no error ins 0x81090000>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x72 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0
+****************** cycle 134 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
+  <InsRsp    valid no error ins 0x11200005>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0xbfc00158 wdata 0 be 0x2>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_DATA_WRITE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0x1
+****************** cycle 135 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
+  <InsRsp    valid no error ins 0x11200005>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0xbfc00158 wdata 0 be 0x2>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 136 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
+  <InsRsp    valid no error ins 0x11200005>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0xbfc00158 wdata 0 be 0x2>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+  <PROC.DCACHE_IDLE> HIT in dcache
+****************** cycle 137 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
+  <InsRsp    valid no error ins 0x11200005>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0xbfc00158 wdata 0 be 0x2>
+  <DataRsp   valid no error rdata 0xa7472>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_DATA_WRITE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d CMD VCI : WR  @ = 0x0d0200000  wdata = 0x000000072  srcid = 0x0000  trdid = 0x08  plen  = 0x004  eop = 0x1  ack = 0x1
+****************** cycle 138 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
+  <InsRsp    valid no error ins 0x11200005>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xbfc00158 wdata 0 be 0x2>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 139 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc0039c>
+  <InsRsp    valid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xbfc00158 wdata 0 be 0x2>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 140 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003a0>
+  <InsRsp    valid no error ins 0xa3490000>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xbfc00158 wdata 0 be 0x2>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 141 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003a4>
+  <InsRsp    valid no error ins 0x25080001>
+  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x74 be 0x1>
+  <DataRsp   valid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 142 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003a8>
+  <InsRsp    valid no error ins 0xbf000e5>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x74 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 143 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003ac>
+  <InsRsp    valid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x74 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 144 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00394>
+  <InsRsp    valid no error ins 0x81090000>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x74 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0
+****************** cycle 145 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
+  <InsRsp    valid no error ins 0x11200005>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0xbfc00158 wdata 0 be 0x4>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_DATA_WRITE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0x1
+****************** cycle 146 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
+  <InsRsp    valid no error ins 0x11200005>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0xbfc00158 wdata 0 be 0x4>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 147 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
+  <InsRsp    valid no error ins 0x11200005>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0xbfc00158 wdata 0 be 0x4>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+  <PROC.DCACHE_IDLE> HIT in dcache
+****************** cycle 148 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
+  <InsRsp    valid no error ins 0x11200005>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0xbfc00158 wdata 0 be 0x4>
+  <DataRsp   valid no error rdata 0xa7472>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_DATA_WRITE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d CMD VCI : WR  @ = 0x0d0200000  wdata = 0x000000074  srcid = 0x0000  trdid = 0x08  plen  = 0x004  eop = 0x1  ack = 0x1
+****************** cycle 149 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
+  <InsRsp    valid no error ins 0x11200005>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xbfc00158 wdata 0 be 0x4>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 150 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc0039c>
+  <InsRsp    valid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xbfc00158 wdata 0 be 0x4>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 151 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003a0>
+  <InsRsp    valid no error ins 0xa3490000>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xbfc00158 wdata 0 be 0x4>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 152 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003a4>
+  <InsRsp    valid no error ins 0x25080001>
+  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0xa be 0x1>
+  <DataRsp   valid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 153 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003a8>
+  <InsRsp    valid no error ins 0xbf000e5>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0xa be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 154 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003ac>
+  <InsRsp    valid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0xa be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 155 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00394>
+  <InsRsp    valid no error ins 0x81090000>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0xa be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0
+****************** cycle 156 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
+  <InsRsp    valid no error ins 0x11200005>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0xbfc00158 wdata 0 be 0x8>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_DATA_WRITE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0x1
+****************** cycle 157 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
+  <InsRsp    valid no error ins 0x11200005>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0xbfc00158 wdata 0 be 0x8>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 158 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
+  <InsRsp    valid no error ins 0x11200005>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0xbfc00158 wdata 0 be 0x8>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+  <PROC.DCACHE_IDLE> HIT in dcache
+****************** cycle 159 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
+  <InsRsp    valid no error ins 0x11200005>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0xbfc00158 wdata 0 be 0x8>
+  <DataRsp   valid no error rdata 0xa7472>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_DATA_WRITE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d CMD VCI : WR  @ = 0x0d0200000  wdata = 0x00000000a  srcid = 0x0000  trdid = 0x08  plen  = 0x004  eop = 0x1  ack = 0x1
+****************** cycle 160 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
+  <InsRsp    valid no error ins 0x11200005>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xbfc00158 wdata 0 be 0x8>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 161 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc0039c>
+  <InsRsp    valid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xbfc00158 wdata 0 be 0x8>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 162 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003b0>
+  <InsRsp    valid no error ins 0x3e00008>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xbfc00158 wdata 0 be 0x8>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 163 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003b4>
+  <InsRsp    valid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xbfc00158 wdata 0 be 0x8>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 164 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00020>
+  <InsRsp    valid no error ins 0x3c042040>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xbfc00158 wdata 0 be 0x8>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 165 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00024>
+  <InsRsp    valid no error ins 0x40846000>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xbfc00158 wdata 0 be 0x8>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 166 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00028>
+  <InsRsp    valid no error ins 0x3c040000>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xbfc00158 wdata 0 be 0x8>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0
+****************** cycle 167 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc0002c>
+  <InsRsp    valid no error ins 0x24840008>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xbfc00158 wdata 0 be 0x8>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_DATA_WRITE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0x1
+****************** cycle 168 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00030>
+  <InsRsp    valid no error ins 0xc4820000>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xbfc00158 wdata 0 be 0x8>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 169 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00034>
+  <InsRsp    valid no error ins 0x3c040000>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 170 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00034>
+  <InsRsp    valid no error ins 0x3c040000>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_VICTIM | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+  <PROC.DCACHE_MISS_VICTIM> Select a slot: / way = 0 / set = 0 / valid = 0 / line = 0x000000000
+****************** cycle 171 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00034>
+  <InsRsp    valid no error ins 0x3c040000>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_DATA_MISS | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d CMD VCI : RD  @ = 0x000000000  wdata = 0x000000000  srcid = 0x0000  trdid = 0x01  plen  = 0x040  eop = 0x1  ack = 0x1
+****************** cycle 172 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00034>
+  <InsRsp    valid no error ins 0x3c040000>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 173 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00034>
+  <InsRsp    valid no error ins 0x3c040000>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 174 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00034>
+  <InsRsp    valid no error ins 0x3c040000>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+memc_tgt_d CMD VCI : RD  @ = 0x000000000  wdata = 0x000000000  srcid = 0x0000  trdid = 0x01  plen  = 0x040  eop = 0x1  ack = 0
+  <MEMC.TGT_CMD_IDLE> Receive command from srcid 0x0000 / for address 0x000000000
+****************** cycle 175 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00034>
+  <InsRsp    valid no error ins 0x3c040000>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_READ | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+memc_tgt_d CMD VCI : RD  @ = 0x000000000  wdata = 0x000000000  srcid = 0x0000  trdid = 0x01  plen  = 0x040  eop = 0x1  ack = 0x1
+  <MEMC.TGT_CMD_READ> Push into read_fifo: address = 0x000000000 srcid = 0x0000 trdid = 0x01 plen = 0x040
+****************** cycle 176 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00034>
+  <InsRsp    valid no error ins 0x3c040000>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+  <MEMC.READ_IDLE> Read request: srcid = 0 / address = 0 / nwords = 16
+****************** cycle 177 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00034>
+  <InsRsp    valid no error ins 0x3c040000>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_DIR_LOCK | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+  <MEMC.READ_DIR_LOCK> Accessing directory:  address = 0 / hit = 0 / count = 0 / is_cnt = 0
+****************** cycle 178 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00034>
+  <InsRsp    valid no error ins 0x3c040000>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_TRT_LOCK | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+  <MEMC.READ_TRT_LOCK> Check TRT: hit_read = 0 / hit_write = 0 / full = 0
+****************** cycle 179 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00034>
+  <InsRsp    valid no error ins 0x3c040000>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_TRT_SET | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+  <MEMC.READ_TRT_SET> Write in Transaction Table:  address = 0 / srcid = 0
+****************** cycle 180 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00034>
+  <InsRsp    valid no error ins 0x3c040000>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_TRT_REQ | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+  <MEMC.READ_TRT_REQ> Request GET transaction for address 0
+****************** cycle 181 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00034>
+  <InsRsp    valid no error ins 0x3c040000>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 182 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00034>
+  <InsRsp    valid no error ins 0x3c040000>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_NLINE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+  <MEMC.IXR_CMD_READ_NLINE> Send a get request to xram
+****************** cycle 183 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00034>
+  <InsRsp    valid no error ins 0x3c040000>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+  <MEMC.IXR_RSP_IDLE> Response from XRAM to a get transaction
+****************** cycle 184 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00034>
+  <InsRsp    valid no error ins 0x3c040000>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_TRT_READ | XRAM_RSP_IDLE
+****************** cycle 185 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00034>
+  <InsRsp    valid no error ins 0x3c040000>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_TRT_READ | XRAM_RSP_IDLE
+  <MEMC.IXR_RSP_TRT_READ> Writing a word in TRT :  index = 0 / word = 0 / data = 0xdead
+****************** cycle 186 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00034>
+  <InsRsp    valid no error ins 0x3c040000>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_TRT_READ | XRAM_RSP_IDLE
+  <MEMC.IXR_RSP_TRT_READ> Writing a word in TRT :  index = 0 / word = 1 / data = 0xbeef
+****************** cycle 187 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00034>
+  <InsRsp    valid no error ins 0x3c040000>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_TRT_READ | XRAM_RSP_IDLE
+  <MEMC.IXR_RSP_TRT_READ> Writing a word in TRT :  index = 0 / word = 2 / data = 0x41200000
+****************** cycle 188 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00034>
+  <InsRsp    valid no error ins 0x3c040000>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_TRT_READ | XRAM_RSP_IDLE
+  <MEMC.IXR_RSP_TRT_READ> Writing a word in TRT :  index = 0 / word = 3 / data = 0
+****************** cycle 189 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00034>
+  <InsRsp    valid no error ins 0x3c040000>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_TRT_READ | XRAM_RSP_IDLE
+  <MEMC.IXR_RSP_TRT_READ> Writing a word in TRT :  index = 0 / word = 4 / data = 0
+****************** cycle 190 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00034>
+  <InsRsp    valid no error ins 0x3c040000>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_TRT_READ | XRAM_RSP_IDLE
+  <MEMC.IXR_RSP_TRT_READ> Writing a word in TRT :  index = 0 / word = 5 / data = 0
+****************** cycle 191 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00034>
+  <InsRsp    valid no error ins 0x3c040000>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_TRT_READ | XRAM_RSP_IDLE
+  <MEMC.IXR_RSP_TRT_READ> Writing a word in TRT :  index = 0 / word = 6 / data = 0
+****************** cycle 192 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00034>
+  <InsRsp    valid no error ins 0x3c040000>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_TRT_READ | XRAM_RSP_IDLE
+  <MEMC.IXR_RSP_TRT_READ> Writing a word in TRT :  index = 0 / word = 7 / data = 0
+****************** cycle 193 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00034>
+  <InsRsp    valid no error ins 0x3c040000>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_TRT_READ | XRAM_RSP_IDLE
+  <MEMC.IXR_RSP_TRT_READ> Writing a word in TRT :  index = 0 / word = 8 / data = 0
+****************** cycle 194 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00034>
+  <InsRsp    valid no error ins 0x3c040000>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_TRT_READ | XRAM_RSP_IDLE
+  <MEMC.IXR_RSP_TRT_READ> Writing a word in TRT :  index = 0 / word = 9 / data = 0
+****************** cycle 195 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00034>
+  <InsRsp    valid no error ins 0x3c040000>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_TRT_READ | XRAM_RSP_IDLE
+  <MEMC.IXR_RSP_TRT_READ> Writing a word in TRT :  index = 0 / word = 10 / data = 0
+****************** cycle 196 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00034>
+  <InsRsp    valid no error ins 0x3c040000>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_TRT_READ | XRAM_RSP_IDLE
+  <MEMC.IXR_RSP_TRT_READ> Writing a word in TRT :  index = 0 / word = 11 / data = 0
+****************** cycle 197 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00034>
+  <InsRsp    valid no error ins 0x3c040000>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_TRT_READ | XRAM_RSP_IDLE
+  <MEMC.IXR_RSP_TRT_READ> Writing a word in TRT :  index = 0 / word = 12 / data = 0
+****************** cycle 198 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00034>
+  <InsRsp    valid no error ins 0x3c040000>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_TRT_READ | XRAM_RSP_IDLE
+  <MEMC.IXR_RSP_TRT_READ> Writing a word in TRT :  index = 0 / word = 13 / data = 0
+****************** cycle 199 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00034>
+  <InsRsp    valid no error ins 0x3c040000>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_TRT_READ | XRAM_RSP_IDLE
+  <MEMC.IXR_RSP_TRT_READ> Writing a word in TRT :  index = 0 / word = 14 / data = 0
+****************** cycle 200 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00034>
+  <InsRsp    valid no error ins 0x3c040000>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_TRT_READ | XRAM_RSP_IDLE
+  <MEMC.IXR_RSP_TRT_READ> Writing a word in TRT :  index = 0 / word = 15 / data = 0
+****************** cycle 201 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00034>
+  <InsRsp    valid no error ins 0x3c040000>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+  <MEMC.XRAM_RSP_IDLE> Available cache line in TRT: index = 0
+****************** cycle 202 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00034>
+  <InsRsp    valid no error ins 0x3c040000>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_DIR_LOCK
+****************** cycle 203 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00034>
+  <InsRsp    valid no error ins 0x3c040000>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_DIR_LOCK
+  <MEMC.XRAM_RSP_DIR_LOCK> Get access to directory
+****************** cycle 204 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00034>
+  <InsRsp    valid no error ins 0x3c040000>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_TRT_COPY
+****************** cycle 205 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00034>
+  <InsRsp    valid no error ins 0x3c040000>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_TRT_COPY
+  <MEMC.XRAM_RSP_TRT_COPY> Select a slot:  way = 0 / set = 0 / inval_required = 0
+****************** cycle 206 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00034>
+  <InsRsp    valid no error ins 0x3c040000>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_INVAL_LOCK
+****************** cycle 207 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00034>
+  <InsRsp    valid no error ins 0x3c040000>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_INVAL_LOCK
+  <MEMC.XRAM_RSP_INVAL_LOCK> Get acces to UPT
+****************** cycle 208 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00034>
+  <InsRsp    valid no error ins 0x3c040000>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_DIR_UPDT
+  <MEMC.XRAM_RSP_DIR_UPDT> Directory update:  way = 0 / set = 0 / count = 1 / is_cnt = 0
+****************** cycle 209 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00034>
+  <InsRsp    valid no error ins 0x3c040000>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_DIR_RSP
+  <MEMC.XRAM_RSP_DIR_RSP> Request the TGT_RSP FSM to return data: rsrcid = 0 / address = 0 / nwords = 16
+****************** cycle 210 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00034>
+  <InsRsp    valid no error ins 0x3c040000>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 211 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00034>
+  <InsRsp    valid no error ins 0x3c040000>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+memc_tgt_d RSP VCI : rerror = 0x0 | rdata = 0x00000dead | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1
+  <MEMC.TGT_RSP_XRAM> Response following XRAM access / rsrcid = 0 / rtrdid = 0x1 / rdata = 0xdead / cpt = 0
+****************** cycle 212 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00034>
+  <InsRsp    valid no error ins 0x3c040000>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+memc_tgt_d RSP VCI : rerror = 0x0 | rdata = 0x00000beef | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1
+  <MEMC.TGT_RSP_XRAM> Response following XRAM access / rsrcid = 0 / rtrdid = 0x1 / rdata = 0xbeef / cpt = 0x1
+****************** cycle 213 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00034>
+  <InsRsp    valid no error ins 0x3c040000>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+memc_tgt_d RSP VCI : rerror = 0x0 | rdata = 0x041200000 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1
+  <MEMC.TGT_RSP_XRAM> Response following XRAM access / rsrcid = 0 / rtrdid = 0x1 / rdata = 0x41200000 / cpt = 0x2
+****************** cycle 214 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00034>
+  <InsRsp    valid no error ins 0x3c040000>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x00000dead | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0
+memc_tgt_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1
+  <MEMC.TGT_RSP_XRAM> Response following XRAM access / rsrcid = 0 / rtrdid = 0x1 / rdata = 0 / cpt = 0x3
+****************** cycle 215 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00034>
+  <InsRsp    valid no error ins 0x3c040000>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_DATA_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x00000dead | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1
+memc_tgt_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1
+  <MEMC.TGT_RSP_XRAM> Response following XRAM access / rsrcid = 0 / rtrdid = 0x1 / rdata = 0 / cpt = 0x4
+****************** cycle 216 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00034>
+  <InsRsp    valid no error ins 0x3c040000>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_DATA_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x00000beef | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1
+memc_tgt_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1
+  <MEMC.TGT_RSP_XRAM> Response following XRAM access / rsrcid = 0 / rtrdid = 0x1 / rdata = 0 / cpt = 0x5
+****************** cycle 217 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00034>
+  <InsRsp    valid no error ins 0x3c040000>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_UPDT | CMD_IDLE | RSP_DATA_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x041200000 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0
+memc_tgt_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1
+  <PROC.DCACHE_MISS_UPDT> Write one word: address = 0x000000008 / data = 0xdead / way = 0 / set = 0 / word = 0
+  <MEMC.TGT_RSP_XRAM> Response following XRAM access / rsrcid = 0 / rtrdid = 0x1 / rdata = 0 / cpt = 0x6
+****************** cycle 218 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00034>
+  <InsRsp    valid no error ins 0x3c040000>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_UPDT | CMD_IDLE | RSP_DATA_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x041200000 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1
+memc_tgt_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1
+  <PROC.DCACHE_MISS_UPDT> Write one word: address = 0x000000008 / data = 0xbeef / way = 0 / set = 0 / word = 0x1
+  <MEMC.TGT_RSP_XRAM> Response following XRAM access / rsrcid = 0 / rtrdid = 0x1 / rdata = 0 / cpt = 0x7
+****************** cycle 219 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00034>
+  <InsRsp    valid no error ins 0x3c040000>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_UPDT | CMD_IDLE | RSP_DATA_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1
+memc_tgt_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1
+  <PROC.DCACHE_MISS_UPDT> Write one word: address = 0x000000008 / data = 0x41200000 / way = 0 / set = 0 / word = 0x2
+  <MEMC.TGT_RSP_XRAM> Response following XRAM access / rsrcid = 0 / rtrdid = 0x1 / rdata = 0 / cpt = 0x8
+****************** cycle 220 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00034>
+  <InsRsp    valid no error ins 0x3c040000>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_UPDT | CMD_IDLE | RSP_DATA_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1
+memc_tgt_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1
+  <PROC.DCACHE_MISS_UPDT> Write one word: address = 0x000000008 / data = 0 / way = 0 / set = 0 / word = 0x3
+  <MEMC.TGT_RSP_XRAM> Response following XRAM access / rsrcid = 0 / rtrdid = 0x1 / rdata = 0 / cpt = 0x9
+****************** cycle 221 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00034>
+  <InsRsp    valid no error ins 0x3c040000>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_UPDT | CMD_IDLE | RSP_DATA_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1
+memc_tgt_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1
+  <PROC.DCACHE_MISS_UPDT> Write one word: address = 0x000000008 / data = 0 / way = 0 / set = 0 / word = 0x4
+  <MEMC.TGT_RSP_XRAM> Response following XRAM access / rsrcid = 0 / rtrdid = 0x1 / rdata = 0 / cpt = 0xa
+****************** cycle 222 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00034>
+  <InsRsp    valid no error ins 0x3c040000>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_UPDT | CMD_IDLE | RSP_DATA_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1
+memc_tgt_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1
+  <PROC.DCACHE_MISS_UPDT> Write one word: address = 0x000000008 / data = 0 / way = 0 / set = 0 / word = 0x5
+  <MEMC.TGT_RSP_XRAM> Response following XRAM access / rsrcid = 0 / rtrdid = 0x1 / rdata = 0 / cpt = 0xb
+****************** cycle 223 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00034>
+  <InsRsp    valid no error ins 0x3c040000>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_UPDT | CMD_IDLE | RSP_DATA_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1
+memc_tgt_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1
+  <PROC.DCACHE_MISS_UPDT> Write one word: address = 0x000000008 / data = 0 / way = 0 / set = 0 / word = 0x6
+  <MEMC.TGT_RSP_XRAM> Response following XRAM access / rsrcid = 0 / rtrdid = 0x1 / rdata = 0 / cpt = 0xc
+****************** cycle 224 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00034>
+  <InsRsp    valid no error ins 0x3c040000>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_UPDT | CMD_IDLE | RSP_DATA_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1
+memc_tgt_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1
+  <PROC.DCACHE_MISS_UPDT> Write one word: address = 0x000000008 / data = 0 / way = 0 / set = 0 / word = 0x7
+  <MEMC.TGT_RSP_XRAM> Response following XRAM access / rsrcid = 0 / rtrdid = 0x1 / rdata = 0 / cpt = 0xd
+****************** cycle 225 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00034>
+  <InsRsp    valid no error ins 0x3c040000>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_UPDT | CMD_IDLE | RSP_DATA_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1
+memc_tgt_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1
+  <PROC.DCACHE_MISS_UPDT> Write one word: address = 0x000000008 / data = 0 / way = 0 / set = 0 / word = 0x8
+  <MEMC.TGT_RSP_XRAM> Response following XRAM access / rsrcid = 0 / rtrdid = 0x1 / rdata = 0 / cpt = 0xe
+****************** cycle 226 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00034>
+  <InsRsp    valid no error ins 0x3c040000>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_UPDT | CMD_IDLE | RSP_DATA_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1
+memc_tgt_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0x1 | ack = 0x1
+  <PROC.DCACHE_MISS_UPDT> Write one word: address = 0x000000008 / data = 0 / way = 0 / set = 0 / word = 0x9
+  <MEMC.TGT_RSP_XRAM> Response following XRAM access / rsrcid = 0 / rtrdid = 0x1 / rdata = 0 / cpt = 0xf
+****************** cycle 227 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00034>
+  <InsRsp    valid no error ins 0x3c040000>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_UPDT | CMD_IDLE | RSP_DATA_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1
+  <PROC.DCACHE_MISS_UPDT> Write one word: address = 0x000000008 / data = 0 / way = 0 / set = 0 / word = 0xa
+****************** cycle 228 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00034>
+  <InsRsp    valid no error ins 0x3c040000>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_UPDT | CMD_IDLE | RSP_DATA_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1
+  <PROC.DCACHE_MISS_UPDT> Write one word: address = 0x000000008 / data = 0 / way = 0 / set = 0 / word = 0xb
+****************** cycle 229 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00034>
+  <InsRsp    valid no error ins 0x3c040000>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_UPDT | CMD_IDLE | RSP_DATA_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1
+  <PROC.DCACHE_MISS_UPDT> Write one word: address = 0x000000008 / data = 0 / way = 0 / set = 0 / word = 0xc
+****************** cycle 230 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00034>
+  <InsRsp    valid no error ins 0x3c040000>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_UPDT | CMD_IDLE | RSP_DATA_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1
+  <PROC.DCACHE_MISS_UPDT> Write one word: address = 0x000000008 / data = 0 / way = 0 / set = 0 / word = 0xd
+****************** cycle 231 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00034>
+  <InsRsp    valid no error ins 0x3c040000>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_UPDT | CMD_IDLE | RSP_DATA_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0x1 | ack = 0x1
+  <PROC.DCACHE_MISS_UPDT> Write one word: address = 0x000000008 / data = 0 / way = 0 / set = 0 / word = 0xe
+****************** cycle 232 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00034>
+  <InsRsp    valid no error ins 0x3c040000>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_UPDT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+  <PROC.DCACHE_MISS_UPDT> Write one word: address = 0x000000008 / data = 0 / way = 0 / set = 0 / word = 0xf
+****************** cycle 233 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00034>
+  <InsRsp    valid no error ins 0x3c040000>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+  <PROC.DCACHE_IDLE> HIT in dcache
+****************** cycle 234 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00034>
+  <InsRsp    valid no error ins 0x3c040000>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp   valid no error rdata 0x41200000>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 235 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00038>
+  <InsRsp    valid no error ins 0x2484000c>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 236 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc0003c>
+  <InsRsp    valid no error ins 0xc4800000>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+  <PROC.DCACHE_IDLE> HIT in dcache
+****************** cycle 237 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00040>
+  <InsRsp  invalid no error ins 0>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0xc wdata 0 be 0xf>
+  <DataRsp   valid no error rdata 0>
+  ICACHE_MISS_VICTIM | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 238 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00040>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xc wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_INS_MISS | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d CMD VCI : RD  @ = 0x0bfc00040  wdata = 0x000000000  srcid = 0x0000  trdid = 0x03  plen  = 0x040  eop = 0x1  ack = 0x1
+****************** cycle 239 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00040>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xc wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 240 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00040>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xc wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 241 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00040>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xc wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 242 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00040>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xc wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 243 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00040>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xc wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 244 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00040>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xc wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 245 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00040>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xc wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x00bf00016 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0
+****************** cycle 246 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00040>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xc wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x00bf00016 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 247 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00040>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xc wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x046020003 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 248 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00040>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xc wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x024040002 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0
+****************** cycle 249 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00040>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xc wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x024040002 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 250 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00040>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xc wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x0af640000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 251 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00040>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xc wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x00bf00014 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 252 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00040>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xc wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 253 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00040>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xc wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000402021 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 254 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00040>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xc wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x00ff000ee | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 255 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00040>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xc wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 256 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00040>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xc wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x024040020 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 257 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00040>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xc wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x0a3440000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 258 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00040>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xc wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000602021 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 259 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00040>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xc wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x00ff000ee | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 260 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00040>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xc wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 261 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00040>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xc wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x02404000a | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 262 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00040>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xc wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x0a3440000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0x1 | ack = 0x1
+****************** cycle 263 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00040>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xc wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 264 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00040>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xc wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 265 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00040>
+  <InsRsp    valid no error ins 0xbf00016>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xc wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 266 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00044>
+  <InsRsp    valid no error ins 0x46020003>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xc wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 267 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00058>
+  <InsRsp    valid no error ins 0x402021>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xc wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 268 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc0005c>
+  <InsRsp    valid no error ins 0xff000ee>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xc wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 269 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00060>
+  <InsRsp    valid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xc wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 270 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003b8>
+  <InsRsp    valid no error ins 0x804021>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xc wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 271 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003bc>
+  <InsRsp    valid no error ins 0x24090030>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xc wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 272 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003c0>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xc wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_VICTIM | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 273 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003c0>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xc wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_INS_MISS | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d CMD VCI : RD  @ = 0x0bfc003c0  wdata = 0x000000000  srcid = 0x0000  trdid = 0x03  plen  = 0x040  eop = 0x1  ack = 0x1
+****************** cycle 274 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003c0>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xc wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 275 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003c0>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xc wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 276 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003c0>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xc wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 277 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003c0>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xc wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 278 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003c0>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xc wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 279 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003c0>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xc wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 280 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003c0>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xc wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x0a3490000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0
+****************** cycle 281 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003c0>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xc wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x0a3490000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 282 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003c0>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xc wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x024090078 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 283 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003c0>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xc wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x0a3490000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0
+****************** cycle 284 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003c0>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xc wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x0a3490000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 285 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003c0>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xc wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x024090008 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 286 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003c0>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xc wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x03c0af000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 287 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003c0>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xc wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x0010a5024 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 288 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003c0>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xc wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x0000a5702 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 289 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003c0>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xc wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x0294b000a | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 290 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003c0>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xc wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x011600004 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 291 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003c0>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xc wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 292 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003c0>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xc wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x0214a0030 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 293 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003c0>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xc wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x00bf000fe | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 294 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003c0>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xc wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 295 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003c0>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xc wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x0214a0037 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 296 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003c0>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xc wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x0a34a0000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 297 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003c0>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xc wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x02129ffff | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0x1 | ack = 0x1
+****************** cycle 298 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003c0>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xc wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 299 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003c0>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xc wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 300 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003c0>
+  <InsRsp    valid no error ins 0xa3490000>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xc wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 301 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003c4>
+  <InsRsp    valid no error ins 0x24090078>
+  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp   valid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 302 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003c8>
+  <InsRsp    valid no error ins 0xa3490000>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 303 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003cc>
+  <InsRsp    valid no error ins 0x24090008>
+  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x78 be 0x1>
+  <DataRsp   valid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_DATA_WRITE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d CMD VCI : WR  @ = 0x0d0200000  wdata = 0x000000030  srcid = 0x0000  trdid = 0x08  plen  = 0x004  eop = 0x1  ack = 0x1
+****************** cycle 304 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003d0>
+  <InsRsp    valid no error ins 0x3c0af000>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x78 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 305 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003d4>
+  <InsRsp    valid no error ins 0x10a5024>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x78 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 306 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003d8>
+  <InsRsp    valid no error ins 0xa5702>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x78 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 307 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003dc>
+  <InsRsp    valid no error ins 0x294b000a>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x78 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 308 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003e0>
+  <InsRsp    valid no error ins 0x11600004>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x78 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 309 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003e4>
+  <InsRsp    valid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x78 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 310 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003e8>
+  <InsRsp    valid no error ins 0x214a0030>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x78 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0
+****************** cycle 311 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003ec>
+  <InsRsp    valid no error ins 0xbf000fe>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x78 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_DATA_WRITE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0x1
+****************** cycle 312 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003f0>
+  <InsRsp    valid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x78 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 313 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003f8>
+  <InsRsp    valid no error ins 0xa34a0000>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x78 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 314 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003fc>
+  <InsRsp    valid no error ins 0x2129ffff>
+  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp   valid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_DATA_WRITE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d CMD VCI : WR  @ = 0x0d0200000  wdata = 0x000000078  srcid = 0x0000  trdid = 0x08  plen  = 0x004  eop = 0x1  ack = 0x1
+****************** cycle 315 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00400>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_VICTIM | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 316 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00400>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_INS_MISS | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d CMD VCI : RD  @ = 0x0bfc00400  wdata = 0x000000000  srcid = 0x0000  trdid = 0x03  plen  = 0x040  eop = 0x1  ack = 0x1
+****************** cycle 317 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00400>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 318 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00400>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 319 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00400>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 320 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00400>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 321 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00400>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0
+****************** cycle 322 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00400>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_DATA_WRITE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0x1
+****************** cycle 323 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00400>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 324 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00400>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x01d20fff3 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0
+****************** cycle 325 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00400>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_DATA_WRITE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d CMD VCI : WR  @ = 0x0d0200000  wdata = 0x000000030  srcid = 0x0000  trdid = 0x08  plen  = 0x004  eop = 0x1  ack = 0x1
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x01d20fff3 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 326 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00400>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000084100 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 327 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00400>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x003e00008 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0
+****************** cycle 328 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00400>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x003e00008 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 329 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00400>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 330 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00400>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x0bc00009c | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 331 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00400>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 332 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00400>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000005 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 333 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00400>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 334 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00400>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 335 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00400>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000010 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 336 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00400>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 337 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00400>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 338 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00400>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 339 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00400>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 340 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00400>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 341 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00400>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0x1 | ack = 0x1
+****************** cycle 342 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00400>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0
+****************** cycle 343 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00400>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_DATA_WRITE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0x1
+****************** cycle 344 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00400>
+  <InsRsp    valid no error ins 0x1d20fff3>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 345 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00404>
+  <InsRsp    valid no error ins 0x84100>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 346 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003d0>
+  <InsRsp    valid no error ins 0x3c0af000>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 347 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003d4>
+  <InsRsp    valid no error ins 0x10a5024>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 348 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003d8>
+  <InsRsp    valid no error ins 0xa5702>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 349 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003dc>
+  <InsRsp    valid no error ins 0x294b000a>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 350 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003e0>
+  <InsRsp    valid no error ins 0x11600004>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 351 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003e4>
+  <InsRsp    valid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 352 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003e8>
+  <InsRsp    valid no error ins 0x214a0030>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 353 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003ec>
+  <InsRsp    valid no error ins 0xbf000fe>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 354 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003f0>
+  <InsRsp    valid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 355 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003f8>
+  <InsRsp    valid no error ins 0xa34a0000>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 356 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003fc>
+  <InsRsp    valid no error ins 0x2129ffff>
+  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp   valid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 357 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00400>
+  <InsRsp    valid no error ins 0x1d20fff3>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 358 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00404>
+  <InsRsp    valid no error ins 0x84100>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_DATA_WRITE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d CMD VCI : WR  @ = 0x0d0200000  wdata = 0x000000030  srcid = 0x0000  trdid = 0x08  plen  = 0x004  eop = 0x1  ack = 0x1
+****************** cycle 359 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003d0>
+  <InsRsp    valid no error ins 0x3c0af000>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 360 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003d4>
+  <InsRsp    valid no error ins 0x10a5024>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 361 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003d8>
+  <InsRsp    valid no error ins 0xa5702>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 362 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003dc>
+  <InsRsp    valid no error ins 0x294b000a>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 363 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003e0>
+  <InsRsp    valid no error ins 0x11600004>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 364 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003e4>
+  <InsRsp    valid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 365 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003e8>
+  <InsRsp    valid no error ins 0x214a0030>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0
+****************** cycle 366 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003ec>
+  <InsRsp    valid no error ins 0xbf000fe>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_DATA_WRITE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0x1
+****************** cycle 367 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003f0>
+  <InsRsp    valid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 368 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003f8>
+  <InsRsp    valid no error ins 0xa34a0000>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 369 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003fc>
+  <InsRsp    valid no error ins 0x2129ffff>
+  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp   valid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 370 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00400>
+  <InsRsp    valid no error ins 0x1d20fff3>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 371 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00404>
+  <InsRsp    valid no error ins 0x84100>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_DATA_WRITE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d CMD VCI : WR  @ = 0x0d0200000  wdata = 0x000000030  srcid = 0x0000  trdid = 0x08  plen  = 0x004  eop = 0x1  ack = 0x1
+****************** cycle 372 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003d0>
+  <InsRsp    valid no error ins 0x3c0af000>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 373 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003d4>
+  <InsRsp    valid no error ins 0x10a5024>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 374 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003d8>
+  <InsRsp    valid no error ins 0xa5702>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 375 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003dc>
+  <InsRsp    valid no error ins 0x294b000a>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 376 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003e0>
+  <InsRsp    valid no error ins 0x11600004>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 377 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003e4>
+  <InsRsp    valid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 378 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003e8>
+  <InsRsp    valid no error ins 0x214a0030>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0
+****************** cycle 379 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003ec>
+  <InsRsp    valid no error ins 0xbf000fe>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_DATA_WRITE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0x1
+****************** cycle 380 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003f0>
+  <InsRsp    valid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 381 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003f8>
+  <InsRsp    valid no error ins 0xa34a0000>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 382 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003fc>
+  <InsRsp    valid no error ins 0x2129ffff>
+  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp   valid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 383 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00400>
+  <InsRsp    valid no error ins 0x1d20fff3>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 384 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00404>
+  <InsRsp    valid no error ins 0x84100>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_DATA_WRITE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d CMD VCI : WR  @ = 0x0d0200000  wdata = 0x000000030  srcid = 0x0000  trdid = 0x08  plen  = 0x004  eop = 0x1  ack = 0x1
+****************** cycle 385 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003d0>
+  <InsRsp    valid no error ins 0x3c0af000>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 386 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003d4>
+  <InsRsp    valid no error ins 0x10a5024>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 387 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003d8>
+  <InsRsp    valid no error ins 0xa5702>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 388 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003dc>
+  <InsRsp    valid no error ins 0x294b000a>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 389 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003e0>
+  <InsRsp    valid no error ins 0x11600004>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 390 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003e4>
+  <InsRsp    valid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 391 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003e8>
+  <InsRsp    valid no error ins 0x214a0030>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0
+****************** cycle 392 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003ec>
+  <InsRsp    valid no error ins 0xbf000fe>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_DATA_WRITE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0x1
+****************** cycle 393 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003f0>
+  <InsRsp    valid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 394 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003f8>
+  <InsRsp    valid no error ins 0xa34a0000>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 395 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003fc>
+  <InsRsp    valid no error ins 0x2129ffff>
+  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp   valid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 396 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00400>
+  <InsRsp    valid no error ins 0x1d20fff3>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 397 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00404>
+  <InsRsp    valid no error ins 0x84100>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_DATA_WRITE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d CMD VCI : WR  @ = 0x0d0200000  wdata = 0x000000030  srcid = 0x0000  trdid = 0x08  plen  = 0x004  eop = 0x1  ack = 0x1
+****************** cycle 398 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003d0>
+  <InsRsp    valid no error ins 0x3c0af000>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 399 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003d4>
+  <InsRsp    valid no error ins 0x10a5024>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 400 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003d8>
+  <InsRsp    valid no error ins 0xa5702>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 401 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003dc>
+  <InsRsp    valid no error ins 0x294b000a>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 402 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003e0>
+  <InsRsp    valid no error ins 0x11600004>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 403 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003e4>
+  <InsRsp    valid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 404 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003e8>
+  <InsRsp    valid no error ins 0x214a0030>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0
+****************** cycle 405 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003ec>
+  <InsRsp    valid no error ins 0xbf000fe>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_DATA_WRITE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0x1
+****************** cycle 406 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003f0>
+  <InsRsp    valid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 407 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003f8>
+  <InsRsp    valid no error ins 0xa34a0000>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 408 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003fc>
+  <InsRsp    valid no error ins 0x2129ffff>
+  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp   valid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 409 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00400>
+  <InsRsp    valid no error ins 0x1d20fff3>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 410 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00404>
+  <InsRsp    valid no error ins 0x84100>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_DATA_WRITE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d CMD VCI : WR  @ = 0x0d0200000  wdata = 0x000000030  srcid = 0x0000  trdid = 0x08  plen  = 0x004  eop = 0x1  ack = 0x1
+****************** cycle 411 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003d0>
+  <InsRsp    valid no error ins 0x3c0af000>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 412 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003d4>
+  <InsRsp    valid no error ins 0x10a5024>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 413 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003d8>
+  <InsRsp    valid no error ins 0xa5702>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 414 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003dc>
+  <InsRsp    valid no error ins 0x294b000a>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 415 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003e0>
+  <InsRsp    valid no error ins 0x11600004>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 416 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003e4>
+  <InsRsp    valid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 417 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003e8>
+  <InsRsp    valid no error ins 0x214a0030>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0
+****************** cycle 418 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003ec>
+  <InsRsp    valid no error ins 0xbf000fe>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_DATA_WRITE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0x1
+****************** cycle 419 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003f0>
+  <InsRsp    valid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 420 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003f8>
+  <InsRsp    valid no error ins 0xa34a0000>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 421 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003fc>
+  <InsRsp    valid no error ins 0x2129ffff>
+  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp   valid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 422 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00400>
+  <InsRsp    valid no error ins 0x1d20fff3>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 423 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00404>
+  <InsRsp    valid no error ins 0x84100>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_DATA_WRITE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d CMD VCI : WR  @ = 0x0d0200000  wdata = 0x000000030  srcid = 0x0000  trdid = 0x08  plen  = 0x004  eop = 0x1  ack = 0x1
+****************** cycle 424 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003d0>
+  <InsRsp    valid no error ins 0x3c0af000>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 425 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003d4>
+  <InsRsp    valid no error ins 0x10a5024>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 426 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003d8>
+  <InsRsp    valid no error ins 0xa5702>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 427 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003dc>
+  <InsRsp    valid no error ins 0x294b000a>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 428 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003e0>
+  <InsRsp    valid no error ins 0x11600004>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 429 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003e4>
+  <InsRsp    valid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 430 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003e8>
+  <InsRsp    valid no error ins 0x214a0030>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0
+****************** cycle 431 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003ec>
+  <InsRsp    valid no error ins 0xbf000fe>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_DATA_WRITE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0x1
+****************** cycle 432 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003f0>
+  <InsRsp    valid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 433 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003f8>
+  <InsRsp    valid no error ins 0xa34a0000>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 434 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003fc>
+  <InsRsp    valid no error ins 0x2129ffff>
+  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp   valid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 435 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00400>
+  <InsRsp    valid no error ins 0x1d20fff3>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 436 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00404>
+  <InsRsp    valid no error ins 0x84100>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_DATA_WRITE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d CMD VCI : WR  @ = 0x0d0200000  wdata = 0x000000030  srcid = 0x0000  trdid = 0x08  plen  = 0x004  eop = 0x1  ack = 0x1
+****************** cycle 437 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00408>
+  <InsRsp    valid no error ins 0x3e00008>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 438 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc0040c>
+  <InsRsp    valid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 439 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00064>
+  <InsRsp    valid no error ins 0x24040020>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 440 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00068>
+  <InsRsp    valid no error ins 0xa3440000>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 441 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc0006c>
+  <InsRsp    valid no error ins 0x602021>
+  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x20 be 0x1>
+  <DataRsp   valid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 442 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00070>
+  <InsRsp    valid no error ins 0xff000ee>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x20 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 443 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00074>
+  <InsRsp    valid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x20 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0
+****************** cycle 444 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003b8>
+  <InsRsp    valid no error ins 0x804021>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x20 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_DATA_WRITE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0x1
+****************** cycle 445 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003bc>
+  <InsRsp    valid no error ins 0x24090030>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x20 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 446 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003c0>
+  <InsRsp    valid no error ins 0xa3490000>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x20 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 447 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003c4>
+  <InsRsp    valid no error ins 0x24090078>
+  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp   valid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_DATA_WRITE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d CMD VCI : WR  @ = 0x0d0200000  wdata = 0x000000020  srcid = 0x0000  trdid = 0x08  plen  = 0x004  eop = 0x1  ack = 0x1
+****************** cycle 448 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003c8>
+  <InsRsp    valid no error ins 0xa3490000>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 449 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003cc>
+  <InsRsp    valid no error ins 0x24090008>
+  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x78 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 450 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003cc>
+  <InsRsp    valid no error ins 0x24090008>
+  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x78 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 451 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003cc>
+  <InsRsp    valid no error ins 0x24090008>
+  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x78 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 452 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003cc>
+  <InsRsp    valid no error ins 0x24090008>
+  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x78 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 453 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003cc>
+  <InsRsp    valid no error ins 0x24090008>
+  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x78 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 454 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003cc>
+  <InsRsp    valid no error ins 0x24090008>
+  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x78 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0
+****************** cycle 455 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003cc>
+  <InsRsp    valid no error ins 0x24090008>
+  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x78 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_DATA_WRITE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0x1
+****************** cycle 456 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003cc>
+  <InsRsp    valid no error ins 0x24090008>
+  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x78 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 457 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003cc>
+  <InsRsp    valid no error ins 0x24090008>
+  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x78 be 0x1>
+  <DataRsp   valid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 458 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003d0>
+  <InsRsp    valid no error ins 0x3c0af000>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x78 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_DATA_WRITE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d CMD VCI : WR  @ = 0x0d0200000  wdata = 0x000000030  srcid = 0x0000  trdid = 0x08  plen  = 0x004  eop = 0x1  ack = 0x1
+****************** cycle 459 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003d4>
+  <InsRsp    valid no error ins 0x10a5024>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x78 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 460 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003d8>
+  <InsRsp    valid no error ins 0xa5702>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x78 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 461 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003dc>
+  <InsRsp    valid no error ins 0x294b000a>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x78 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 462 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003e0>
+  <InsRsp    valid no error ins 0x11600004>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x78 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 463 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003e4>
+  <InsRsp    valid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x78 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 464 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003e8>
+  <InsRsp    valid no error ins 0x214a0030>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x78 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 465 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003ec>
+  <InsRsp    valid no error ins 0xbf000fe>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x78 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0
+****************** cycle 466 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003f0>
+  <InsRsp    valid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x78 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_DATA_WRITE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0x1
+****************** cycle 467 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003f8>
+  <InsRsp    valid no error ins 0xa34a0000>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x78 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 468 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003fc>
+  <InsRsp    valid no error ins 0x2129ffff>
+  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp   valid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 469 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00400>
+  <InsRsp    valid no error ins 0x1d20fff3>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_DATA_WRITE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d CMD VCI : WR  @ = 0x0d0200000  wdata = 0x000000078  srcid = 0x0000  trdid = 0x08  plen  = 0x004  eop = 0x1  ack = 0x1
+****************** cycle 470 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00404>
+  <InsRsp    valid no error ins 0x84100>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 471 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003d0>
+  <InsRsp    valid no error ins 0x3c0af000>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 472 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003d4>
+  <InsRsp    valid no error ins 0x10a5024>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 473 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003d8>
+  <InsRsp    valid no error ins 0xa5702>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 474 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003dc>
+  <InsRsp    valid no error ins 0x294b000a>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 475 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003e0>
+  <InsRsp    valid no error ins 0x11600004>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 476 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003e4>
+  <InsRsp    valid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0
+****************** cycle 477 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003e8>
+  <InsRsp    valid no error ins 0x214a0030>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_DATA_WRITE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0x1
+****************** cycle 478 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003ec>
+  <InsRsp    valid no error ins 0xbf000fe>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 479 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003f0>
+  <InsRsp    valid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 480 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003f8>
+  <InsRsp    valid no error ins 0xa34a0000>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_DATA_WRITE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d CMD VCI : WR  @ = 0x0d0200000  wdata = 0x000000030  srcid = 0x0000  trdid = 0x08  plen  = 0x004  eop = 0x1  ack = 0x1
+****************** cycle 481 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003fc>
+  <InsRsp    valid no error ins 0x2129ffff>
+  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp   valid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 482 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00400>
+  <InsRsp    valid no error ins 0x1d20fff3>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 483 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00404>
+  <InsRsp    valid no error ins 0x84100>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 484 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003d0>
+  <InsRsp    valid no error ins 0x3c0af000>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 485 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003d4>
+  <InsRsp    valid no error ins 0x10a5024>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 486 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003d8>
+  <InsRsp    valid no error ins 0xa5702>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 487 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003dc>
+  <InsRsp    valid no error ins 0x294b000a>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0
+****************** cycle 488 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003e0>
+  <InsRsp    valid no error ins 0x11600004>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_DATA_WRITE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0x1
+****************** cycle 489 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003e4>
+  <InsRsp    valid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 490 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003e8>
+  <InsRsp    valid no error ins 0x214a0030>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 491 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003ec>
+  <InsRsp    valid no error ins 0xbf000fe>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_DATA_WRITE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d CMD VCI : WR  @ = 0x0d0200000  wdata = 0x000000030  srcid = 0x0000  trdid = 0x08  plen  = 0x004  eop = 0x1  ack = 0x1
+****************** cycle 492 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003f0>
+  <InsRsp    valid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 493 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003f8>
+  <InsRsp    valid no error ins 0xa34a0000>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 494 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003fc>
+  <InsRsp    valid no error ins 0x2129ffff>
+  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp   valid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 495 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00400>
+  <InsRsp    valid no error ins 0x1d20fff3>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 496 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00404>
+  <InsRsp    valid no error ins 0x84100>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 497 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003d0>
+  <InsRsp    valid no error ins 0x3c0af000>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 498 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003d4>
+  <InsRsp    valid no error ins 0x10a5024>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0
+****************** cycle 499 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003d8>
+  <InsRsp    valid no error ins 0xa5702>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_DATA_WRITE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0x1
+****************** cycle 500 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003dc>
+  <InsRsp    valid no error ins 0x294b000a>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 501 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003e0>
+  <InsRsp    valid no error ins 0x11600004>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 502 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003e4>
+  <InsRsp    valid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_DATA_WRITE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d CMD VCI : WR  @ = 0x0d0200000  wdata = 0x000000030  srcid = 0x0000  trdid = 0x08  plen  = 0x004  eop = 0x1  ack = 0x1
+****************** cycle 503 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003e8>
+  <InsRsp    valid no error ins 0x214a0030>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 504 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003ec>
+  <InsRsp    valid no error ins 0xbf000fe>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 505 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003f0>
+  <InsRsp    valid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 506 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003f8>
+  <InsRsp    valid no error ins 0xa34a0000>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 507 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003fc>
+  <InsRsp    valid no error ins 0x2129ffff>
+  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp   valid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 508 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00400>
+  <InsRsp    valid no error ins 0x1d20fff3>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 509 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00404>
+  <InsRsp    valid no error ins 0x84100>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0
+****************** cycle 510 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003d0>
+  <InsRsp    valid no error ins 0x3c0af000>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_DATA_WRITE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0x1
+****************** cycle 511 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003d4>
+  <InsRsp    valid no error ins 0x10a5024>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 512 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003d8>
+  <InsRsp    valid no error ins 0xa5702>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 513 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003dc>
+  <InsRsp    valid no error ins 0x294b000a>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_DATA_WRITE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d CMD VCI : WR  @ = 0x0d0200000  wdata = 0x000000030  srcid = 0x0000  trdid = 0x08  plen  = 0x004  eop = 0x1  ack = 0x1
+****************** cycle 514 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003e0>
+  <InsRsp    valid no error ins 0x11600004>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 515 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003e4>
+  <InsRsp    valid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 516 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003e8>
+  <InsRsp    valid no error ins 0x214a0030>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 517 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003ec>
+  <InsRsp    valid no error ins 0xbf000fe>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 518 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003f0>
+  <InsRsp    valid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 519 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003f8>
+  <InsRsp    valid no error ins 0xa34a0000>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 520 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003fc>
+  <InsRsp    valid no error ins 0x2129ffff>
+  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp   valid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0
+****************** cycle 521 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00400>
+  <InsRsp    valid no error ins 0x1d20fff3>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_DATA_WRITE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0x1
+****************** cycle 522 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00404>
+  <InsRsp    valid no error ins 0x84100>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 523 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003d0>
+  <InsRsp    valid no error ins 0x3c0af000>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 524 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003d4>
+  <InsRsp    valid no error ins 0x10a5024>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_DATA_WRITE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d CMD VCI : WR  @ = 0x0d0200000  wdata = 0x000000030  srcid = 0x0000  trdid = 0x08  plen  = 0x004  eop = 0x1  ack = 0x1
+****************** cycle 525 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003d8>
+  <InsRsp    valid no error ins 0xa5702>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 526 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003dc>
+  <InsRsp    valid no error ins 0x294b000a>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 527 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003e0>
+  <InsRsp    valid no error ins 0x11600004>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 528 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003e4>
+  <InsRsp    valid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 529 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003e8>
+  <InsRsp    valid no error ins 0x214a0030>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 530 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003ec>
+  <InsRsp    valid no error ins 0xbf000fe>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 531 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003f0>
+  <InsRsp    valid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0
+****************** cycle 532 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003f8>
+  <InsRsp    valid no error ins 0xa34a0000>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_DATA_WRITE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0x1
+****************** cycle 533 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003fc>
+  <InsRsp    valid no error ins 0x2129ffff>
+  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp   valid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 534 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00400>
+  <InsRsp    valid no error ins 0x1d20fff3>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 535 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00404>
+  <InsRsp    valid no error ins 0x84100>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_DATA_WRITE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d CMD VCI : WR  @ = 0x0d0200000  wdata = 0x000000030  srcid = 0x0000  trdid = 0x08  plen  = 0x004  eop = 0x1  ack = 0x1
+****************** cycle 536 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003d0>
+  <InsRsp    valid no error ins 0x3c0af000>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 537 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003d4>
+  <InsRsp    valid no error ins 0x10a5024>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 538 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003d8>
+  <InsRsp    valid no error ins 0xa5702>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 539 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003dc>
+  <InsRsp    valid no error ins 0x294b000a>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 540 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003e0>
+  <InsRsp    valid no error ins 0x11600004>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 541 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003e4>
+  <InsRsp    valid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 542 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003e8>
+  <InsRsp    valid no error ins 0x214a0030>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0
+****************** cycle 543 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003ec>
+  <InsRsp    valid no error ins 0xbf000fe>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_DATA_WRITE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0x1
+****************** cycle 544 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003f0>
+  <InsRsp    valid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 545 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003f8>
+  <InsRsp    valid no error ins 0xa34a0000>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 546 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003fc>
+  <InsRsp    valid no error ins 0x2129ffff>
+  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp   valid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 547 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00400>
+  <InsRsp    valid no error ins 0x1d20fff3>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 548 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00404>
+  <InsRsp    valid no error ins 0x84100>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_DATA_WRITE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d CMD VCI : WR  @ = 0x0d0200000  wdata = 0x000000030  srcid = 0x0000  trdid = 0x08  plen  = 0x004  eop = 0x1  ack = 0x1
+****************** cycle 549 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003d0>
+  <InsRsp    valid no error ins 0x3c0af000>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 550 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003d4>
+  <InsRsp    valid no error ins 0x10a5024>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 551 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003d8>
+  <InsRsp    valid no error ins 0xa5702>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 552 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003dc>
+  <InsRsp    valid no error ins 0x294b000a>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 553 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003e0>
+  <InsRsp    valid no error ins 0x11600004>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 554 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003e4>
+  <InsRsp    valid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 555 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003e8>
+  <InsRsp    valid no error ins 0x214a0030>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0
+****************** cycle 556 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003ec>
+  <InsRsp    valid no error ins 0xbf000fe>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_DATA_WRITE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0x1
+****************** cycle 557 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003f0>
+  <InsRsp    valid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 558 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003f8>
+  <InsRsp    valid no error ins 0xa34a0000>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 559 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003fc>
+  <InsRsp    valid no error ins 0x2129ffff>
+  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp   valid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 560 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00400>
+  <InsRsp    valid no error ins 0x1d20fff3>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 561 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00404>
+  <InsRsp    valid no error ins 0x84100>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_DATA_WRITE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d CMD VCI : WR  @ = 0x0d0200000  wdata = 0x000000030  srcid = 0x0000  trdid = 0x08  plen  = 0x004  eop = 0x1  ack = 0x1
+****************** cycle 562 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00408>
+  <InsRsp    valid no error ins 0x3e00008>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 563 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc0040c>
+  <InsRsp    valid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 564 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00078>
+  <InsRsp    valid no error ins 0x2404000a>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 565 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc0007c>
+  <InsRsp    valid no error ins 0xa3440000>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 566 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00080>
+  <InsRsp  invalid no error ins 0>
+  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0xa be 0x1>
+  <DataRsp   valid no error rdata 0>
+  ICACHE_MISS_VICTIM | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 567 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00080>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0xa be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_INS_MISS | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d CMD VCI : RD  @ = 0x0bfc00080  wdata = 0x000000000  srcid = 0x0000  trdid = 0x03  plen  = 0x040  eop = 0x1  ack = 0x1
+****************** cycle 568 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00080>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0xa be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0
+****************** cycle 569 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00080>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0xa be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_DATA_WRITE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0x1
+****************** cycle 570 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00080>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0xa be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 571 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00080>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0xa be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 572 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00080>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0xa be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_DATA_WRITE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d CMD VCI : WR  @ = 0x0d0200000  wdata = 0x00000000a  srcid = 0x0000  trdid = 0x08  plen  = 0x004  eop = 0x1  ack = 0x1
+****************** cycle 573 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00080>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0xa be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 574 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00080>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0xa be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x024040000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0
+****************** cycle 575 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00080>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0xa be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x024040000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 576 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00080>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0xa be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x0af640000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 577 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00080>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0xa be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x00bf00022 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0
+****************** cycle 578 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00080>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0xa be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x00bf00022 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 579 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00080>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0xa be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 580 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00080>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0xa be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x03c04bfc0 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 581 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00080>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0xa be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x024840138 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 582 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00080>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0xa be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x00ff000e4 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 583 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00080>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0xa be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 584 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00080>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0xa be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x040046000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 585 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00080>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0xa be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x00ff000ee | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 586 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00080>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0xa be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 587 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00080>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0xa be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x03c04bfc0 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 588 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00080>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0xa be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x024840140 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 589 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00080>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0xa be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x00ff000e4 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 590 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00080>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0xa be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 591 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00080>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0xa be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x040046800 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0x1 | ack = 0x1
+****************** cycle 592 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00080>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0xa be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0
+****************** cycle 593 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00080>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0xa be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_DATA_WRITE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0x1
+****************** cycle 594 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00080>
+  <InsRsp    valid no error ins 0x24040000>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0xa be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 595 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00084>
+  <InsRsp    valid no error ins 0xaf640000>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0xa be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 596 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00088>
+  <InsRsp    valid no error ins 0xbf00022>
+  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xe0000000 wdata 0 be 0xf>
+  <DataRsp   valid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 597 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc0008c>
+  <InsRsp    valid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xe0000000 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 598 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00088>
+  <InsRsp    valid no error ins 0xbf00022>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xe0000000 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_DATA_WRITE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d CMD VCI : WR  @ = 0x0e0000000  wdata = 0x000000000  srcid = 0x0000  trdid = 0x08  plen  = 0x004  eop = 0x1  ack = 0x1
+****************** cycle 599 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc0008c>
+  <InsRsp    valid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xe0000000 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 600 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00088>
+  <InsRsp    valid no error ins 0xbf00022>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xe0000000 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 601 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc0008c>
+  <InsRsp    valid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xe0000000 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+  Data TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+  Instruction TLB
+     set way    V  L  R  C  W  X  U  G  D  B  Z   TAG        PPN          NLINE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+vci_exit terminate simulation, status 0x000000000
Index: branches/v4/softs/tests_ccvcache_v4/test_fpe_delayslot/test.S
===================================================================
--- branches/v4/softs/tests_ccvcache_v4/test_fpe_delayslot/test.S	(revision 371)
+++ branches/v4/softs/tests_ccvcache_v4/test_fpe_delayslot/test.S	(revision 371)
@@ -0,0 +1,92 @@
+/*
+ * trap test: check that a trap in a delay slot is
+ * properly handled
+ */
+#include <registers.h>
+#include <misc.h>
+
+	.text
+	.globl  _start
+_start:
+	.set noreorder
+	la	k0, TTY_BASE
+	la	k1, EXIT_BASE
+	la	sp, 0x00400000 - 16
+
+	PRINT(startstr)
+
+	/* reset cop0 status (keep BEV), enable cop1 */
+	lui	a0, 0x2040;
+	mtc0	a0, COP0_STATUS
+
+	la	a0, div1
+	lwc1	$f2, 0(a0)
+	la	a0, div2
+	lwc1	$f0, 0(a0)
+	j exit
+	div.s	$f0, $f0, $f2
+	/* we should not get there, */
+	EXIT(2)
+	.globl exit
+exit:
+	move	a0, v0
+	PRINTX
+	PUTCHAR(' ')
+	move	a0, v1
+	PRINTX
+	PUTCHAR('\n')
+	/* we should get there */
+	EXIT(0)
+
+	.globl excep
+excep:
+	.set noreorder
+	PRINT(statusstr)
+	mfc0	a0, COP0_STATUS
+	PRINTX
+
+	PRINT(causestr)
+	mfc0	a0, COP0_CAUSE
+	PRINTX
+
+	PRINT(pcstr)
+	mfc0	a0, COP0_EXPC
+	PRINTX
+
+	PRINT(badvastr)
+	mfc0	a0, COP_0_BADVADDR
+	PRINTX
+	PUTCHAR('\n')
+	la	a0, exit
+	mtc0	a0, COP0_EXPC
+	li	v0, MAGIC1
+	li	v1, MAGIC2
+	li	a3, 1
+	eret
+	nop
+
+#we should not end there
+	EXIT(1)
+
+	.rodata:
+statusstr: .ascii "status \0"
+causestr: .ascii " cause \0"
+pcstr: .ascii " pc \0"
+badvastr: .ascii " badva \0"
+startstr: .ascii "start\n\0"
+usrstr: .ascii "usrmode\n\0"
+
+	.org EXCEP_ADDRESS - BOOT_ADDRESS
+	.globl evect
+evect:
+	j	excep
+	nop
+	.data
+	.word MAGIC1
+testval:
+	.word MAGIC2
+div1:
+	.float	10.0
+	.globl div2
+div2:
+	.float	0.0
Index: branches/v4/softs/tests_ccvcache_v4/test_fpe_delayslot/test.elf.txt
===================================================================
--- branches/v4/softs/tests_ccvcache_v4/test_fpe_delayslot/test.elf.txt	(revision 371)
+++ branches/v4/softs/tests_ccvcache_v4/test_fpe_delayslot/test.elf.txt	(revision 371)
@@ -0,0 +1,185 @@
+
+test.elf:     file format elf32-littlemips
+
+
+Disassembly of section .text:
+
+bfc00000 <_start>:
+bfc00000:	3c1ad020 	lui	k0,0xd020
+bfc00004:	3c1be000 	lui	k1,0xe000
+bfc00008:	3c1d003f 	lui	sp,0x3f
+bfc0000c:	37bdfff0 	ori	sp,sp,0xfff0
+bfc00010:	3c04bfc0 	lui	a0,0xbfc0
+bfc00014:	24840155 	addiu	a0,a0,341
+bfc00018:	0ff000e4 	jal	bfc00390 <print>
+bfc0001c:	00000000 	nop
+bfc00020:	3c042040 	lui	a0,0x2040
+bfc00024:	40846000 	mtc0	a0,c0_status
+bfc00028:	3c040000 	lui	a0,0x0
+bfc0002c:	24840008 	addiu	a0,a0,8
+bfc00030:	c4820000 	lwc1	$f2,0(a0)
+bfc00034:	3c040000 	lui	a0,0x0
+bfc00038:	2484000c 	addiu	a0,a0,12
+bfc0003c:	c4800000 	lwc1	$f0,0(a0)
+bfc00040:	0bf00016 	j	bfc00058 <exit>
+bfc00044:	46020003 	div.s	$f0,$f0,$f2
+bfc00048:	24040002 	li	a0,2
+bfc0004c:	af640000 	sw	a0,0(k1)
+bfc00050:	0bf00014 	j	bfc00050 <_start+0x50>
+bfc00054:	00000000 	nop
+
+bfc00058 <exit>:
+bfc00058:	00402021 	move	a0,v0
+bfc0005c:	0ff000ee 	jal	bfc003b8 <printx>
+bfc00060:	00000000 	nop
+bfc00064:	24040020 	li	a0,32
+bfc00068:	a3440000 	sb	a0,0(k0)
+bfc0006c:	00602021 	move	a0,v1
+bfc00070:	0ff000ee 	jal	bfc003b8 <printx>
+bfc00074:	00000000 	nop
+bfc00078:	2404000a 	li	a0,10
+bfc0007c:	a3440000 	sb	a0,0(k0)
+bfc00080:	24040000 	li	a0,0
+bfc00084:	af640000 	sw	a0,0(k1)
+bfc00088:	0bf00022 	j	bfc00088 <exit+0x30>
+bfc0008c:	00000000 	nop
+
+bfc00090 <excep>:
+bfc00090:	3c04bfc0 	lui	a0,0xbfc0
+bfc00094:	24840138 	addiu	a0,a0,312
+bfc00098:	0ff000e4 	jal	bfc00390 <print>
+bfc0009c:	00000000 	nop
+bfc000a0:	40046000 	mfc0	a0,c0_status
+bfc000a4:	0ff000ee 	jal	bfc003b8 <printx>
+bfc000a8:	00000000 	nop
+bfc000ac:	3c04bfc0 	lui	a0,0xbfc0
+bfc000b0:	24840140 	addiu	a0,a0,320
+bfc000b4:	0ff000e4 	jal	bfc00390 <print>
+bfc000b8:	00000000 	nop
+bfc000bc:	40046800 	mfc0	a0,c0_cause
+bfc000c0:	0ff000ee 	jal	bfc003b8 <printx>
+bfc000c4:	00000000 	nop
+bfc000c8:	3c04bfc0 	lui	a0,0xbfc0
+bfc000cc:	24840148 	addiu	a0,a0,328
+bfc000d0:	0ff000e4 	jal	bfc00390 <print>
+bfc000d4:	00000000 	nop
+bfc000d8:	40047000 	mfc0	a0,c0_epc
+bfc000dc:	0ff000ee 	jal	bfc003b8 <printx>
+bfc000e0:	00000000 	nop
+bfc000e4:	3c04bfc0 	lui	a0,0xbfc0
+bfc000e8:	2484014d 	addiu	a0,a0,333
+bfc000ec:	0ff000e4 	jal	bfc00390 <print>
+bfc000f0:	00000000 	nop
+bfc000f4:	40044000 	mfc0	a0,c0_badvaddr
+bfc000f8:	0ff000ee 	jal	bfc003b8 <printx>
+bfc000fc:	00000000 	nop
+bfc00100:	2404000a 	li	a0,10
+bfc00104:	a3440000 	sb	a0,0(k0)
+bfc00108:	3c04bfc0 	lui	a0,0xbfc0
+bfc0010c:	24840058 	addiu	a0,a0,88
+bfc00110:	40847000 	mtc0	a0,c0_epc
+bfc00114:	3402dead 	li	v0,0xdead
+bfc00118:	3403beef 	li	v1,0xbeef
+bfc0011c:	24070001 	li	a3,1
+bfc00120:	42000018 	eret
+bfc00124:	00000000 	nop
+bfc00128:	24040001 	li	a0,1
+bfc0012c:	af640000 	sw	a0,0(k1)
+bfc00130:	0bf0004c 	j	bfc00130 <excep+0xa0>
+bfc00134:	00000000 	nop
+
+bfc00138 <statusstr>:
+bfc00138:	74617473 	jalx	b185d1cc <_stack+0xb145d1dc>
+bfc0013c:	00207375 	0x207375
+
+bfc00140 <causestr>:
+bfc00140:	75616320 	jalx	b5858c80 <_stack+0xb5458c90>
+bfc00144:	00206573 	tltu	at,zero,0x195
+
+bfc00148 <pcstr>:
+bfc00148:	20637020 	addi	v1,v1,28704
+	...
+
+bfc0014d <badvastr>:
+bfc0014d:	6220      	sw	ra,128(sp)
+bfc0014f:	6461      	restore	8,ra,s0
+bfc00151:	6176      	btnez	bfc0023f <usrstr+0xe3>
+bfc00153:	0020      	addiu	s0,sp,128
+
+bfc00155 <startstr>:
+bfc00155:	7473      	cmpi	a0,115
+bfc00157:	7261      	cmpi	v0,97
+bfc00159:	0a74      	la	v0,bfc00328 <usrstr+0x1cc>
+	...
+
+bfc0015c <usrstr>:
+bfc0015c:	6d727375 	0x6d727375
+bfc00160:	0a65646f 	j	b99591bc <_stack+0xb95591cc>
+bfc00164:	00000000 	nop
+	...
+
+bfc00380 <evect>:
+bfc00380:	0bf00024 	j	bfc00090 <excep>
+bfc00384:	00000000 	nop
+	...
+
+bfc00390 <print>:
+bfc00390:	00804021 	move	t0,a0
+bfc00394:	81090000 	lb	t1,0(t0)
+bfc00398:	11200005 	beqz	t1,bfc003b0 <end>
+bfc0039c:	00000000 	nop
+bfc003a0:	a3490000 	sb	t1,0(k0)
+bfc003a4:	25080001 	addiu	t0,t0,1
+bfc003a8:	0bf000e5 	j	bfc00394 <print+0x4>
+bfc003ac:	00000000 	nop
+
+bfc003b0 <end>:
+bfc003b0:	03e00008 	jr	ra
+bfc003b4:	00000000 	nop
+
+bfc003b8 <printx>:
+bfc003b8:	00804021 	move	t0,a0
+bfc003bc:	24090030 	li	t1,48
+bfc003c0:	a3490000 	sb	t1,0(k0)
+bfc003c4:	24090078 	li	t1,120
+bfc003c8:	a3490000 	sb	t1,0(k0)
+bfc003cc:	24090008 	li	t1,8
+bfc003d0:	3c0af000 	lui	t2,0xf000
+bfc003d4:	010a5024 	and	t2,t0,t2
+bfc003d8:	000a5702 	srl	t2,t2,0x1c
+bfc003dc:	294b000a 	slti	t3,t2,10
+bfc003e0:	11600004 	beqz	t3,bfc003f4 <printx+0x3c>
+bfc003e4:	00000000 	nop
+bfc003e8:	214a0030 	addi	t2,t2,48
+bfc003ec:	0bf000fe 	j	bfc003f8 <printx+0x40>
+bfc003f0:	00000000 	nop
+bfc003f4:	214a0037 	addi	t2,t2,55
+bfc003f8:	a34a0000 	sb	t2,0(k0)
+bfc003fc:	2129ffff 	addi	t1,t1,-1
+bfc00400:	1d20fff3 	bgtz	t1,bfc003d0 <printx+0x18>
+bfc00404:	00084100 	sll	t0,t0,0x4
+bfc00408:	03e00008 	jr	ra
+bfc0040c:	00000000 	nop
+
+Disassembly of section .reginfo:
+
+bfc00410 <.reginfo>:
+bfc00410:	bc00009c 	cache	0x0,156(zero)
+bfc00414:	00000000 	nop
+bfc00418:	00000005 	0x5
+	...
+bfc00424:	00000010 	mfhi	zero
+
+Disassembly of section .data:
+
+00000000 <testval-0x4>:
+   0:	0000dead 	0xdead
+
+00000004 <testval>:
+   4:	0000beef 	0xbeef
+
+00000008 <div1>:
+   8:	41200000 	0x41200000
+
+0000000c <div2>:
+   c:	00000000 	nop
Index: branches/v4/softs/tests_ccvcache_v4/test_fpediv/Makefile
===================================================================
--- branches/v4/softs/tests_ccvcache_v4/test_fpediv/Makefile	(revision 371)
+++ branches/v4/softs/tests_ccvcache_v4/test_fpediv/Makefile	(revision 371)
@@ -0,0 +1,1 @@
+include ../Makefile.inc
Index: branches/v4/softs/tests_ccvcache_v4/test_fpediv/mtty0
===================================================================
--- branches/v4/softs/tests_ccvcache_v4/test_fpediv/mtty0	(revision 371)
+++ branches/v4/softs/tests_ccvcache_v4/test_fpediv/mtty0	(revision 371)
@@ -0,0 +1,2 @@
+[20hstart
+0x00008F80
Index: branches/v4/softs/tests_ccvcache_v4/test_fpediv/run
===================================================================
--- branches/v4/softs/tests_ccvcache_v4/test_fpediv/run	(revision 371)
+++ branches/v4/softs/tests_ccvcache_v4/test_fpediv/run	(revision 371)
@@ -0,0 +1,28 @@
+#!/bin/sh 
+
+. ../common/common.sh
+
+check_output()
+{
+	egrep "^status 0x00400002 cause 0x00000038 pc 0xBFC00034 badva 0x00000000$" run.out > /dev/null
+	if [ $? -ne 0 ]; then
+		echo "couldn't find string 1 in output - mtty not working ?" >> run.out
+		return 1
+	fi
+	return 0;
+}
+
+make --quiet || exit 1
+${SIMUL} > run.out 2>&1 
+if [ $? -eq 0 ]; then
+	if check_output; then
+		echo "test passsed";
+		make --quiet clean
+		exit 0;
+	fi
+	echo "test FAILED"
+	exit 1
+fi
+echo "test FAILED"
+exit 1
+
Index: branches/v4/softs/tests_ccvcache_v4/test_fpediv/run.out
===================================================================
--- branches/v4/softs/tests_ccvcache_v4/test_fpediv/run.out	(revision 371)
+++ branches/v4/softs/tests_ccvcache_v4/test_fpediv/run.out	(revision 371)
@@ -0,0 +1,22 @@
+
+             SystemC 2.2.0 --- Apr 14 2011 18:52:40
+        Copyright (c) 1996-2006 by all Contributors
+                    ALL RIGHTS RESERVED
+Mapping table: ad:(6) id:(6) cacheability mask: 0xf0000000
+ <Segment "memc_d": base = 0 / size = 0x2000000 / tgtid = (0) / cached>
+ <Segment "boot_d": base = 0xbfc00000 / size = 0x40000 / tgtid = (1) / cached>
+ <Segment "exit_d": base = 0xe0000000 / size = 0x4 / tgtid = (2) / uncached>
+ <Segment "mtty_d": base = 0xd0200000 / size = 0x10 / tgtid = (3) / uncached>
+ <Segment "xicu_d": base = 0xd8200000 / size = 0x1000 / tgtid = (4) / uncached>
+ <Segment "mdma_d": base = 0xe8000000 / size = 0x14 / tgtid = (5) / uncached>
+
+Mapping table: ad:(6) id:(6) cacheability mask: 0xf0000000
+ <Segment "proc_c": base = 0x10000000 / size = 0x10 / tgtid = (0) / uncached / init = (0)>
+ <Segment "memc_c": base = 0 / size = 0x2000010 / tgtid = (1) / uncached>
+ <Segment "brom_c": base = 0xbfc00000 / size = 0x40000 / tgtid = (1) / uncached>
+
+Loading at 0xbfc00000 size 262144: .text .reginfo 
+Loading at 0 size 33554432: .data 
+start
+0x00008F80
+vci_exit terminate simulation, status 0d2
Index: branches/v4/softs/tests_ccvcache_v4/test_fpediv/subr.o.txt
===================================================================
--- branches/v4/softs/tests_ccvcache_v4/test_fpediv/subr.o.txt	(revision 371)
+++ branches/v4/softs/tests_ccvcache_v4/test_fpediv/subr.o.txt	(revision 371)
@@ -0,0 +1,49 @@
+
+subr.o:     file format elf32-littlemips
+
+
+Disassembly of section .text:
+
+00000000 <print>:
+   0:	00804021 	move	t0,a0
+   4:	81090000 	lb	t1,0(t0)
+   8:	11200005 	beqz	t1,20 <end>
+   c:	00000000 	nop
+  10:	a3490000 	sb	t1,0(k0)
+  14:	25080001 	addiu	t0,t0,1
+  18:	08000001 	j	4 <print+0x4>
+  1c:	00000000 	nop
+
+00000020 <end>:
+  20:	03e00008 	jr	ra
+  24:	00000000 	nop
+
+00000028 <printx>:
+  28:	00804021 	move	t0,a0
+  2c:	24090030 	li	t1,48
+  30:	a3490000 	sb	t1,0(k0)
+  34:	24090078 	li	t1,120
+  38:	a3490000 	sb	t1,0(k0)
+  3c:	24090008 	li	t1,8
+  40:	3c0af000 	lui	t2,0xf000
+  44:	010a5024 	and	t2,t0,t2
+  48:	000a5702 	srl	t2,t2,0x1c
+  4c:	294b000a 	slti	t3,t2,10
+  50:	11600004 	beqz	t3,64 <printx+0x3c>
+  54:	00000000 	nop
+  58:	214a0030 	addi	t2,t2,48
+  5c:	0800001a 	j	68 <printx+0x40>
+  60:	00000000 	nop
+  64:	214a0037 	addi	t2,t2,55
+  68:	a34a0000 	sb	t2,0(k0)
+  6c:	2129ffff 	addi	t1,t1,-1
+  70:	1d20fff3 	bgtz	t1,40 <printx+0x18>
+  74:	00084100 	sll	t0,t0,0x4
+  78:	03e00008 	jr	ra
+  7c:	00000000 	nop
+
+Disassembly of section .reginfo:
+
+00000000 <.reginfo>:
+   0:	84000f10 	lh	zero,3856(zero)
+	...
Index: branches/v4/softs/tests_ccvcache_v4/test_fpediv/temp
===================================================================
--- branches/v4/softs/tests_ccvcache_v4/test_fpediv/temp	(revision 371)
+++ branches/v4/softs/tests_ccvcache_v4/test_fpediv/temp	(revision 371)
@@ -0,0 +1,4909 @@
+Mapping table: ad:(6) id:(6) cacheability mask: 0xf0000000
+ <Segment "memc_d": base = 0 / size = 0x2000000 / tgtid = (0) / cached>
+ <Segment "boot_d": base = 0xbfc00000 / size = 0x40000 / tgtid = (1) / cached>
+ <Segment "exit_d": base = 0xe0000000 / size = 0x4 / tgtid = (2) / uncached>
+ <Segment "mtty_d": base = 0xd0200000 / size = 0x10 / tgtid = (3) / uncached>
+ <Segment "xicu_d": base = 0xd8200000 / size = 0x1000 / tgtid = (4) / uncached>
+ <Segment "mdma_d": base = 0xe8000000 / size = 0x14 / tgtid = (5) / uncached>
+
+Mapping table: ad:(6) id:(6) cacheability mask: 0xf0000000
+ <Segment "proc_c": base = 0x10000000 / size = 0x10 / tgtid = (0) / uncached / init = (0)>
+ <Segment "memc_c": base = 0 / size = 0x2000010 / tgtid = (1) / uncached>
+ <Segment "brom_c": base = 0xbfc00000 / size = 0x40000 / tgtid = (1) / uncached>
+
+Loading at 0xbfc00000 size 262144: .text .reginfo 
+Loading at 0 size 33554432: .data 
+****************** cycle 1 ************************************************
+PROC proc
+  <InsReq  invalid mode MODE_HYPER @ 0>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 2 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00000>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 3 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00000>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_VICTIM | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 4 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00000>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_INS_MISS | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d CMD VCI : RD  @ = 0x0bfc00000  wdata = 0x000000000  srcid = 0x0000  trdid = 0x03  plen  = 0x040  eop = 0x1  ack = 0x1
+****************** cycle 5 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00000>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 6 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00000>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 7 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00000>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 8 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00000>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 9 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00000>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 10 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00000>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 11 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00000>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x03c1ad020 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0
+****************** cycle 12 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00000>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x03c1ad020 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 13 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00000>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x03c1be000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 14 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00000>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x03c1d003f | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0
+****************** cycle 15 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00000>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x03c1d003f | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 16 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00000>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x037bdfff0 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 17 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00000>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x03c04bfc0 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 18 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00000>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x024840115 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 19 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00000>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x00ff000e4 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 20 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00000>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 21 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00000>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x03c042040 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 22 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00000>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x040846000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 23 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00000>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x024040f80 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 24 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00000>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x044c4f800 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 25 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00000>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x03c040000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 26 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00000>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x024840008 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 27 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00000>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x0c4820000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 28 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00000>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x03c040000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0x1 | ack = 0x1
+****************** cycle 29 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00000>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 30 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00000>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 31 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00000>
+  <InsRsp    valid no error ins 0x3c1ad020>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 32 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00004>
+  <InsRsp    valid no error ins 0x3c1be000>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 33 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00008>
+  <InsRsp    valid no error ins 0x3c1d003f>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 34 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc0000c>
+  <InsRsp    valid no error ins 0x37bdfff0>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 35 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00010>
+  <InsRsp    valid no error ins 0x3c04bfc0>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 36 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00014>
+  <InsRsp    valid no error ins 0x24840115>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 37 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00018>
+  <InsRsp    valid no error ins 0xff000e4>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 38 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc0001c>
+  <InsRsp    valid no error ins 0>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 39 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00390>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_VICTIM | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 40 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00390>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_INS_MISS | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d CMD VCI : RD  @ = 0x0bfc00380  wdata = 0x000000000  srcid = 0x0000  trdid = 0x03  plen  = 0x040  eop = 0x1  ack = 0x1
+****************** cycle 41 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00390>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 42 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00390>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 43 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00390>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 44 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00390>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 45 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00390>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 46 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00390>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 47 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00390>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x00bf0001c | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0
+****************** cycle 48 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00390>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x00bf0001c | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 49 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00390>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 50 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00390>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0
+****************** cycle 51 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00390>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 52 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00390>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 53 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00390>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000804021 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 54 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00390>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x081090000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 55 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00390>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x011200005 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 56 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00390>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 57 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00390>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x0a3490000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 58 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00390>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x025080001 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 59 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00390>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x00bf000e5 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 60 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00390>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 61 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00390>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x003e00008 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 62 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00390>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 63 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00390>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000804021 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 64 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00390>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x024090030 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0x1 | ack = 0x1
+****************** cycle 65 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00390>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 66 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00390>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 67 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00390>
+  <InsRsp    valid no error ins 0x804021>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 68 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00394>
+  <InsRsp    valid no error ins 0x81090000>
+  <DataReq invalid mode MODE_HYPER type DATA_READ @ 0 wdata 0 be 0>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 69 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
+  <InsRsp    valid no error ins 0x11200005>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0xbfc00114 wdata 0 be 0x2>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 70 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
+  <InsRsp    valid no error ins 0x11200005>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0xbfc00114 wdata 0 be 0x2>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_VICTIM | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+  <PROC.DCACHE_MISS_VICTIM> Select a slot: / way = 0 / set = 0x4 / valid = 0 / line = 0x000000004
+****************** cycle 71 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
+  <InsRsp    valid no error ins 0x11200005>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0xbfc00114 wdata 0 be 0x2>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_DATA_MISS | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d CMD VCI : RD  @ = 0x0bfc00100  wdata = 0x000000000  srcid = 0x0000  trdid = 0x01  plen  = 0x040  eop = 0x1  ack = 0x1
+****************** cycle 72 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
+  <InsRsp    valid no error ins 0x11200005>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0xbfc00114 wdata 0 be 0x2>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 73 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
+  <InsRsp    valid no error ins 0x11200005>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0xbfc00114 wdata 0 be 0x2>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 74 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
+  <InsRsp    valid no error ins 0x11200005>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0xbfc00114 wdata 0 be 0x2>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 75 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
+  <InsRsp    valid no error ins 0x11200005>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0xbfc00114 wdata 0 be 0x2>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 76 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
+  <InsRsp    valid no error ins 0x11200005>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0xbfc00114 wdata 0 be 0x2>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 77 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
+  <InsRsp    valid no error ins 0x11200005>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0xbfc00114 wdata 0 be 0x2>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 78 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
+  <InsRsp    valid no error ins 0x11200005>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0xbfc00114 wdata 0 be 0x2>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x075616320 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0
+****************** cycle 79 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
+  <InsRsp    valid no error ins 0x11200005>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0xbfc00114 wdata 0 be 0x2>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_DATA_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x075616320 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1
+****************** cycle 80 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
+  <InsRsp    valid no error ins 0x11200005>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0xbfc00114 wdata 0 be 0x2>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_DATA_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000206573 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1
+****************** cycle 81 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
+  <InsRsp    valid no error ins 0x11200005>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0xbfc00114 wdata 0 be 0x2>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_UPDT | CMD_IDLE | RSP_DATA_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x020637020 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0
+  <PROC.DCACHE_MISS_UPDT> Write one word: address = 0x0bfc00114 / data = 0x75616320 / way = 0 / set = 0x4 / word = 0
+****************** cycle 82 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
+  <InsRsp    valid no error ins 0x11200005>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0xbfc00114 wdata 0 be 0x2>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_UPDT | CMD_IDLE | RSP_DATA_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x020637020 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1
+  <PROC.DCACHE_MISS_UPDT> Write one word: address = 0x0bfc00114 / data = 0x206573 / way = 0 / set = 0x4 / word = 0x1
+****************** cycle 83 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
+  <InsRsp    valid no error ins 0x11200005>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0xbfc00114 wdata 0 be 0x2>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_UPDT | CMD_IDLE | RSP_DATA_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x061622000 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1
+  <PROC.DCACHE_MISS_UPDT> Write one word: address = 0x0bfc00114 / data = 0x20637020 / way = 0 / set = 0x4 / word = 0x2
+****************** cycle 84 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
+  <InsRsp    valid no error ins 0x11200005>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0xbfc00114 wdata 0 be 0x2>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_UPDT | CMD_IDLE | RSP_DATA_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x020617664 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1
+  <PROC.DCACHE_MISS_UPDT> Write one word: address = 0x0bfc00114 / data = 0x61622000 / way = 0 / set = 0x4 / word = 0x3
+****************** cycle 85 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
+  <InsRsp    valid no error ins 0x11200005>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0xbfc00114 wdata 0 be 0x2>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_UPDT | CMD_IDLE | RSP_DATA_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x061747300 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1
+  <PROC.DCACHE_MISS_UPDT> Write one word: address = 0x0bfc00114 / data = 0x20617664 / way = 0 / set = 0x4 / word = 0x4
+****************** cycle 86 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
+  <InsRsp    valid no error ins 0x11200005>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0xbfc00114 wdata 0 be 0x2>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_UPDT | CMD_IDLE | RSP_DATA_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x0000a7472 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1
+  <PROC.DCACHE_MISS_UPDT> Write one word: address = 0x0bfc00114 / data = 0x61747300 / way = 0 / set = 0x4 / word = 0x5
+****************** cycle 87 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
+  <InsRsp    valid no error ins 0x11200005>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0xbfc00114 wdata 0 be 0x2>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_UPDT | CMD_IDLE | RSP_DATA_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x06d727375 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1
+  <PROC.DCACHE_MISS_UPDT> Write one word: address = 0x0bfc00114 / data = 0xa7472 / way = 0 / set = 0x4 / word = 0x6
+****************** cycle 88 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
+  <InsRsp    valid no error ins 0x11200005>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0xbfc00114 wdata 0 be 0x2>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_UPDT | CMD_IDLE | RSP_DATA_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x00a65646f | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1
+  <PROC.DCACHE_MISS_UPDT> Write one word: address = 0x0bfc00114 / data = 0x6d727375 / way = 0 / set = 0x4 / word = 0x7
+****************** cycle 89 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
+  <InsRsp    valid no error ins 0x11200005>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0xbfc00114 wdata 0 be 0x2>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_UPDT | CMD_IDLE | RSP_DATA_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1
+  <PROC.DCACHE_MISS_UPDT> Write one word: address = 0x0bfc00114 / data = 0xa65646f / way = 0 / set = 0x4 / word = 0x8
+****************** cycle 90 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
+  <InsRsp    valid no error ins 0x11200005>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0xbfc00114 wdata 0 be 0x2>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_UPDT | CMD_IDLE | RSP_DATA_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1
+  <PROC.DCACHE_MISS_UPDT> Write one word: address = 0x0bfc00114 / data = 0 / way = 0 / set = 0x4 / word = 0x9
+****************** cycle 91 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
+  <InsRsp    valid no error ins 0x11200005>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0xbfc00114 wdata 0 be 0x2>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_UPDT | CMD_IDLE | RSP_DATA_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1
+  <PROC.DCACHE_MISS_UPDT> Write one word: address = 0x0bfc00114 / data = 0 / way = 0 / set = 0x4 / word = 0xa
+****************** cycle 92 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
+  <InsRsp    valid no error ins 0x11200005>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0xbfc00114 wdata 0 be 0x2>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_UPDT | CMD_IDLE | RSP_DATA_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1
+  <PROC.DCACHE_MISS_UPDT> Write one word: address = 0x0bfc00114 / data = 0 / way = 0 / set = 0x4 / word = 0xb
+****************** cycle 93 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
+  <InsRsp    valid no error ins 0x11200005>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0xbfc00114 wdata 0 be 0x2>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_UPDT | CMD_IDLE | RSP_DATA_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1
+  <PROC.DCACHE_MISS_UPDT> Write one word: address = 0x0bfc00114 / data = 0 / way = 0 / set = 0x4 / word = 0xc
+****************** cycle 94 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
+  <InsRsp    valid no error ins 0x11200005>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0xbfc00114 wdata 0 be 0x2>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_UPDT | CMD_IDLE | RSP_DATA_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1
+  <PROC.DCACHE_MISS_UPDT> Write one word: address = 0x0bfc00114 / data = 0 / way = 0 / set = 0x4 / word = 0xd
+****************** cycle 95 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
+  <InsRsp    valid no error ins 0x11200005>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0xbfc00114 wdata 0 be 0x2>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_UPDT | CMD_IDLE | RSP_DATA_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0x1 | ack = 0x1
+  <PROC.DCACHE_MISS_UPDT> Write one word: address = 0x0bfc00114 / data = 0 / way = 0 / set = 0x4 / word = 0xe
+****************** cycle 96 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
+  <InsRsp    valid no error ins 0x11200005>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0xbfc00114 wdata 0 be 0x2>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_UPDT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+  <PROC.DCACHE_MISS_UPDT> Write one word: address = 0x0bfc00114 / data = 0 / way = 0 / set = 0x4 / word = 0xf
+****************** cycle 97 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
+  <InsRsp    valid no error ins 0x11200005>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0xbfc00114 wdata 0 be 0x2>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+  <PROC.DCACHE_IDLE> HIT in dcache
+****************** cycle 98 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
+  <InsRsp    valid no error ins 0x11200005>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0xbfc00114 wdata 0 be 0x2>
+  <DataRsp   valid no error rdata 0x61747300>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 99 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
+  <InsRsp    valid no error ins 0x11200005>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xbfc00114 wdata 0 be 0x2>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 100 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc0039c>
+  <InsRsp    valid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xbfc00114 wdata 0 be 0x2>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 101 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003a0>
+  <InsRsp    valid no error ins 0xa3490000>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xbfc00114 wdata 0 be 0x2>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 102 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003a4>
+  <InsRsp    valid no error ins 0x25080001>
+  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x73 be 0x1>
+  <DataRsp   valid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 103 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003a8>
+  <InsRsp    valid no error ins 0xbf000e5>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x73 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 104 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003ac>
+  <InsRsp    valid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x73 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_DATA_WRITE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d CMD VCI : WR  @ = 0x0d0200000  wdata = 0x000000073  srcid = 0x0000  trdid = 0x08  plen  = 0x004  eop = 0x1  ack = 0x1
+****************** cycle 105 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00394>
+  <InsRsp    valid no error ins 0x81090000>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x73 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 106 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
+  <InsRsp    valid no error ins 0x11200005>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0xbfc00114 wdata 0 be 0x4>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+  <PROC.DCACHE_IDLE> HIT in dcache
+****************** cycle 107 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
+  <InsRsp    valid no error ins 0x11200005>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0xbfc00114 wdata 0 be 0x4>
+  <DataRsp   valid no error rdata 0x61747300>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 108 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
+  <InsRsp    valid no error ins 0x11200005>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xbfc00114 wdata 0 be 0x4>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 109 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc0039c>
+  <InsRsp    valid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xbfc00114 wdata 0 be 0x4>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 110 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003a0>
+  <InsRsp    valid no error ins 0xa3490000>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xbfc00114 wdata 0 be 0x4>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 111 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003a4>
+  <InsRsp    valid no error ins 0x25080001>
+  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x74 be 0x1>
+  <DataRsp   valid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0
+****************** cycle 112 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003a8>
+  <InsRsp    valid no error ins 0xbf000e5>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x74 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_DATA_WRITE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0x1
+****************** cycle 113 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003ac>
+  <InsRsp    valid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x74 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 114 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00394>
+  <InsRsp    valid no error ins 0x81090000>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x74 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 115 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
+  <InsRsp    valid no error ins 0x11200005>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0xbfc00114 wdata 0 be 0x8>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_DATA_WRITE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d CMD VCI : WR  @ = 0x0d0200000  wdata = 0x000000074  srcid = 0x0000  trdid = 0x08  plen  = 0x004  eop = 0x1  ack = 0x1
+  <PROC.DCACHE_IDLE> HIT in dcache
+****************** cycle 116 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
+  <InsRsp    valid no error ins 0x11200005>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0xbfc00114 wdata 0 be 0x8>
+  <DataRsp   valid no error rdata 0x61747300>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 117 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
+  <InsRsp    valid no error ins 0x11200005>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xbfc00114 wdata 0 be 0x8>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 118 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc0039c>
+  <InsRsp    valid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xbfc00114 wdata 0 be 0x8>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 119 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003a0>
+  <InsRsp    valid no error ins 0xa3490000>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xbfc00114 wdata 0 be 0x8>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 120 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003a4>
+  <InsRsp    valid no error ins 0x25080001>
+  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x61 be 0x1>
+  <DataRsp   valid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 121 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003a8>
+  <InsRsp    valid no error ins 0xbf000e5>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x61 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 122 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003ac>
+  <InsRsp    valid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x61 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0
+****************** cycle 123 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00394>
+  <InsRsp    valid no error ins 0x81090000>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x61 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_DATA_WRITE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0x1
+****************** cycle 124 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
+  <InsRsp    valid no error ins 0x11200005>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0xbfc00118 wdata 0 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 125 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
+  <InsRsp    valid no error ins 0x11200005>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0xbfc00118 wdata 0 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+  <PROC.DCACHE_IDLE> HIT in dcache
+****************** cycle 126 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
+  <InsRsp    valid no error ins 0x11200005>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0xbfc00118 wdata 0 be 0x1>
+  <DataRsp   valid no error rdata 0xa7472>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_DATA_WRITE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d CMD VCI : WR  @ = 0x0d0200000  wdata = 0x000000061  srcid = 0x0000  trdid = 0x08  plen  = 0x004  eop = 0x1  ack = 0x1
+****************** cycle 127 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
+  <InsRsp    valid no error ins 0x11200005>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xbfc00118 wdata 0 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 128 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc0039c>
+  <InsRsp    valid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xbfc00118 wdata 0 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 129 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003a0>
+  <InsRsp    valid no error ins 0xa3490000>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xbfc00118 wdata 0 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 130 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003a4>
+  <InsRsp    valid no error ins 0x25080001>
+  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x72 be 0x1>
+  <DataRsp   valid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 131 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003a8>
+  <InsRsp    valid no error ins 0xbf000e5>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x72 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 132 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003ac>
+  <InsRsp    valid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x72 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 133 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00394>
+  <InsRsp    valid no error ins 0x81090000>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x72 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0
+****************** cycle 134 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
+  <InsRsp    valid no error ins 0x11200005>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0xbfc00118 wdata 0 be 0x2>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_DATA_WRITE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0x1
+****************** cycle 135 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
+  <InsRsp    valid no error ins 0x11200005>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0xbfc00118 wdata 0 be 0x2>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 136 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
+  <InsRsp    valid no error ins 0x11200005>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0xbfc00118 wdata 0 be 0x2>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+  <PROC.DCACHE_IDLE> HIT in dcache
+****************** cycle 137 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
+  <InsRsp    valid no error ins 0x11200005>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0xbfc00118 wdata 0 be 0x2>
+  <DataRsp   valid no error rdata 0xa7472>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_DATA_WRITE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d CMD VCI : WR  @ = 0x0d0200000  wdata = 0x000000072  srcid = 0x0000  trdid = 0x08  plen  = 0x004  eop = 0x1  ack = 0x1
+****************** cycle 138 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
+  <InsRsp    valid no error ins 0x11200005>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xbfc00118 wdata 0 be 0x2>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 139 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc0039c>
+  <InsRsp    valid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xbfc00118 wdata 0 be 0x2>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 140 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003a0>
+  <InsRsp    valid no error ins 0xa3490000>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xbfc00118 wdata 0 be 0x2>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 141 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003a4>
+  <InsRsp    valid no error ins 0x25080001>
+  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x74 be 0x1>
+  <DataRsp   valid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 142 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003a8>
+  <InsRsp    valid no error ins 0xbf000e5>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x74 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 143 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003ac>
+  <InsRsp    valid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x74 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 144 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00394>
+  <InsRsp    valid no error ins 0x81090000>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x74 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0
+****************** cycle 145 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
+  <InsRsp    valid no error ins 0x11200005>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0xbfc00118 wdata 0 be 0x4>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_DATA_WRITE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0x1
+****************** cycle 146 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
+  <InsRsp    valid no error ins 0x11200005>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0xbfc00118 wdata 0 be 0x4>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 147 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
+  <InsRsp    valid no error ins 0x11200005>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0xbfc00118 wdata 0 be 0x4>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+  <PROC.DCACHE_IDLE> HIT in dcache
+****************** cycle 148 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
+  <InsRsp    valid no error ins 0x11200005>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0xbfc00118 wdata 0 be 0x4>
+  <DataRsp   valid no error rdata 0xa7472>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_DATA_WRITE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d CMD VCI : WR  @ = 0x0d0200000  wdata = 0x000000074  srcid = 0x0000  trdid = 0x08  plen  = 0x004  eop = 0x1  ack = 0x1
+****************** cycle 149 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
+  <InsRsp    valid no error ins 0x11200005>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xbfc00118 wdata 0 be 0x4>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 150 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc0039c>
+  <InsRsp    valid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xbfc00118 wdata 0 be 0x4>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 151 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003a0>
+  <InsRsp    valid no error ins 0xa3490000>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xbfc00118 wdata 0 be 0x4>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 152 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003a4>
+  <InsRsp    valid no error ins 0x25080001>
+  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0xa be 0x1>
+  <DataRsp   valid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 153 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003a8>
+  <InsRsp    valid no error ins 0xbf000e5>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0xa be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 154 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003ac>
+  <InsRsp    valid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0xa be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 155 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00394>
+  <InsRsp    valid no error ins 0x81090000>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0xa be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0
+****************** cycle 156 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
+  <InsRsp    valid no error ins 0x11200005>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0xbfc00118 wdata 0 be 0x8>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_DATA_WRITE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0x1
+****************** cycle 157 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
+  <InsRsp    valid no error ins 0x11200005>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0xbfc00118 wdata 0 be 0x8>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 158 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
+  <InsRsp    valid no error ins 0x11200005>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0xbfc00118 wdata 0 be 0x8>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+  <PROC.DCACHE_IDLE> HIT in dcache
+****************** cycle 159 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
+  <InsRsp    valid no error ins 0x11200005>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0xbfc00118 wdata 0 be 0x8>
+  <DataRsp   valid no error rdata 0xa7472>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_DATA_WRITE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d CMD VCI : WR  @ = 0x0d0200000  wdata = 0x00000000a  srcid = 0x0000  trdid = 0x08  plen  = 0x004  eop = 0x1  ack = 0x1
+****************** cycle 160 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00398>
+  <InsRsp    valid no error ins 0x11200005>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xbfc00118 wdata 0 be 0x8>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 161 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc0039c>
+  <InsRsp    valid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xbfc00118 wdata 0 be 0x8>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 162 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003b0>
+  <InsRsp    valid no error ins 0x3e00008>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xbfc00118 wdata 0 be 0x8>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 163 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003b4>
+  <InsRsp    valid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xbfc00118 wdata 0 be 0x8>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 164 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00020>
+  <InsRsp    valid no error ins 0x3c042040>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xbfc00118 wdata 0 be 0x8>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 165 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00024>
+  <InsRsp    valid no error ins 0x40846000>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xbfc00118 wdata 0 be 0x8>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 166 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00028>
+  <InsRsp    valid no error ins 0x24040f80>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xbfc00118 wdata 0 be 0x8>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0
+****************** cycle 167 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc0002c>
+  <InsRsp    valid no error ins 0x44c4f800>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xbfc00118 wdata 0 be 0x8>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_DATA_WRITE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0x1
+****************** cycle 168 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00030>
+  <InsRsp    valid no error ins 0x3c040000>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xbfc00118 wdata 0 be 0x8>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 169 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00034>
+  <InsRsp    valid no error ins 0x24840008>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xbfc00118 wdata 0 be 0x8>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 170 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00038>
+  <InsRsp    valid no error ins 0xc4820000>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xbfc00118 wdata 0 be 0x8>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 171 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc0003c>
+  <InsRsp    valid no error ins 0x3c040000>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 172 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc0003c>
+  <InsRsp    valid no error ins 0x3c040000>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_VICTIM | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+  <PROC.DCACHE_MISS_VICTIM> Select a slot: / way = 0 / set = 0 / valid = 0 / line = 0x000000000
+****************** cycle 173 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc0003c>
+  <InsRsp    valid no error ins 0x3c040000>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_DATA_MISS | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d CMD VCI : RD  @ = 0x000000000  wdata = 0x000000000  srcid = 0x0000  trdid = 0x01  plen  = 0x040  eop = 0x1  ack = 0x1
+****************** cycle 174 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc0003c>
+  <InsRsp    valid no error ins 0x3c040000>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 175 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc0003c>
+  <InsRsp    valid no error ins 0x3c040000>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 176 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc0003c>
+  <InsRsp    valid no error ins 0x3c040000>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+memc_tgt_d CMD VCI : RD  @ = 0x000000000  wdata = 0x000000000  srcid = 0x0000  trdid = 0x01  plen  = 0x040  eop = 0x1  ack = 0
+  <MEMC.TGT_CMD_IDLE> Receive command from srcid 0x0000 / for address 0x000000000
+****************** cycle 177 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc0003c>
+  <InsRsp    valid no error ins 0x3c040000>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_READ | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+memc_tgt_d CMD VCI : RD  @ = 0x000000000  wdata = 0x000000000  srcid = 0x0000  trdid = 0x01  plen  = 0x040  eop = 0x1  ack = 0x1
+  <MEMC.TGT_CMD_READ> Push into read_fifo: address = 0x000000000 srcid = 0x0000 trdid = 0x01 plen = 0x040
+****************** cycle 178 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc0003c>
+  <InsRsp    valid no error ins 0x3c040000>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+  <MEMC.READ_IDLE> Read request: srcid = 0 / address = 0 / nwords = 16
+****************** cycle 179 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc0003c>
+  <InsRsp    valid no error ins 0x3c040000>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_DIR_LOCK | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+  <MEMC.READ_DIR_LOCK> Accessing directory:  address = 0 / hit = 0 / count = 0 / is_cnt = 0
+****************** cycle 180 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc0003c>
+  <InsRsp    valid no error ins 0x3c040000>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_TRT_LOCK | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+  <MEMC.READ_TRT_LOCK> Check TRT: hit_read = 0 / hit_write = 0 / full = 0
+****************** cycle 181 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc0003c>
+  <InsRsp    valid no error ins 0x3c040000>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_TRT_SET | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+  <MEMC.READ_TRT_SET> Write in Transaction Table:  address = 0 / srcid = 0
+****************** cycle 182 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc0003c>
+  <InsRsp    valid no error ins 0x3c040000>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_TRT_REQ | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+  <MEMC.READ_TRT_REQ> Request GET transaction for address 0
+****************** cycle 183 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc0003c>
+  <InsRsp    valid no error ins 0x3c040000>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 184 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc0003c>
+  <InsRsp    valid no error ins 0x3c040000>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_NLINE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+  <MEMC.IXR_CMD_READ_NLINE> Send a get request to xram
+****************** cycle 185 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc0003c>
+  <InsRsp    valid no error ins 0x3c040000>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+  <MEMC.IXR_RSP_IDLE> Response from XRAM to a get transaction
+****************** cycle 186 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc0003c>
+  <InsRsp    valid no error ins 0x3c040000>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_TRT_READ | XRAM_RSP_IDLE
+****************** cycle 187 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc0003c>
+  <InsRsp    valid no error ins 0x3c040000>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_TRT_READ | XRAM_RSP_IDLE
+  <MEMC.IXR_RSP_TRT_READ> Writing a word in TRT :  index = 0 / word = 0 / data = 0xdead
+****************** cycle 188 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc0003c>
+  <InsRsp    valid no error ins 0x3c040000>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_TRT_READ | XRAM_RSP_IDLE
+  <MEMC.IXR_RSP_TRT_READ> Writing a word in TRT :  index = 0 / word = 1 / data = 0xbeef
+****************** cycle 189 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc0003c>
+  <InsRsp    valid no error ins 0x3c040000>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_TRT_READ | XRAM_RSP_IDLE
+  <MEMC.IXR_RSP_TRT_READ> Writing a word in TRT :  index = 0 / word = 2 / data = 0x41200000
+****************** cycle 190 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc0003c>
+  <InsRsp    valid no error ins 0x3c040000>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_TRT_READ | XRAM_RSP_IDLE
+  <MEMC.IXR_RSP_TRT_READ> Writing a word in TRT :  index = 0 / word = 3 / data = 0
+****************** cycle 191 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc0003c>
+  <InsRsp    valid no error ins 0x3c040000>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_TRT_READ | XRAM_RSP_IDLE
+  <MEMC.IXR_RSP_TRT_READ> Writing a word in TRT :  index = 0 / word = 4 / data = 0
+****************** cycle 192 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc0003c>
+  <InsRsp    valid no error ins 0x3c040000>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_TRT_READ | XRAM_RSP_IDLE
+  <MEMC.IXR_RSP_TRT_READ> Writing a word in TRT :  index = 0 / word = 5 / data = 0
+****************** cycle 193 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc0003c>
+  <InsRsp    valid no error ins 0x3c040000>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_TRT_READ | XRAM_RSP_IDLE
+  <MEMC.IXR_RSP_TRT_READ> Writing a word in TRT :  index = 0 / word = 6 / data = 0
+****************** cycle 194 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc0003c>
+  <InsRsp    valid no error ins 0x3c040000>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_TRT_READ | XRAM_RSP_IDLE
+  <MEMC.IXR_RSP_TRT_READ> Writing a word in TRT :  index = 0 / word = 7 / data = 0
+****************** cycle 195 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc0003c>
+  <InsRsp    valid no error ins 0x3c040000>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_TRT_READ | XRAM_RSP_IDLE
+  <MEMC.IXR_RSP_TRT_READ> Writing a word in TRT :  index = 0 / word = 8 / data = 0
+****************** cycle 196 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc0003c>
+  <InsRsp    valid no error ins 0x3c040000>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_TRT_READ | XRAM_RSP_IDLE
+  <MEMC.IXR_RSP_TRT_READ> Writing a word in TRT :  index = 0 / word = 9 / data = 0
+****************** cycle 197 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc0003c>
+  <InsRsp    valid no error ins 0x3c040000>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_TRT_READ | XRAM_RSP_IDLE
+  <MEMC.IXR_RSP_TRT_READ> Writing a word in TRT :  index = 0 / word = 10 / data = 0
+****************** cycle 198 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc0003c>
+  <InsRsp    valid no error ins 0x3c040000>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_TRT_READ | XRAM_RSP_IDLE
+  <MEMC.IXR_RSP_TRT_READ> Writing a word in TRT :  index = 0 / word = 11 / data = 0
+****************** cycle 199 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc0003c>
+  <InsRsp    valid no error ins 0x3c040000>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_TRT_READ | XRAM_RSP_IDLE
+  <MEMC.IXR_RSP_TRT_READ> Writing a word in TRT :  index = 0 / word = 12 / data = 0
+****************** cycle 200 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc0003c>
+  <InsRsp    valid no error ins 0x3c040000>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_TRT_READ | XRAM_RSP_IDLE
+  <MEMC.IXR_RSP_TRT_READ> Writing a word in TRT :  index = 0 / word = 13 / data = 0
+****************** cycle 201 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc0003c>
+  <InsRsp    valid no error ins 0x3c040000>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_TRT_READ | XRAM_RSP_IDLE
+  <MEMC.IXR_RSP_TRT_READ> Writing a word in TRT :  index = 0 / word = 14 / data = 0
+****************** cycle 202 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc0003c>
+  <InsRsp    valid no error ins 0x3c040000>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_TRT_READ | XRAM_RSP_IDLE
+  <MEMC.IXR_RSP_TRT_READ> Writing a word in TRT :  index = 0 / word = 15 / data = 0
+****************** cycle 203 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc0003c>
+  <InsRsp    valid no error ins 0x3c040000>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+  <MEMC.XRAM_RSP_IDLE> Available cache line in TRT: index = 0
+****************** cycle 204 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc0003c>
+  <InsRsp    valid no error ins 0x3c040000>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_DIR_LOCK
+****************** cycle 205 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc0003c>
+  <InsRsp    valid no error ins 0x3c040000>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_DIR_LOCK
+  <MEMC.XRAM_RSP_DIR_LOCK> Get access to directory
+****************** cycle 206 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc0003c>
+  <InsRsp    valid no error ins 0x3c040000>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_TRT_COPY
+****************** cycle 207 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc0003c>
+  <InsRsp    valid no error ins 0x3c040000>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_TRT_COPY
+  <MEMC.XRAM_RSP_TRT_COPY> Select a slot:  way = 0 / set = 0 / inval_required = 0
+****************** cycle 208 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc0003c>
+  <InsRsp    valid no error ins 0x3c040000>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_INVAL_LOCK
+****************** cycle 209 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc0003c>
+  <InsRsp    valid no error ins 0x3c040000>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_INVAL_LOCK
+  <MEMC.XRAM_RSP_INVAL_LOCK> Get acces to UPT
+****************** cycle 210 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc0003c>
+  <InsRsp    valid no error ins 0x3c040000>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_DIR_UPDT
+  <MEMC.XRAM_RSP_DIR_UPDT> Directory update:  way = 0 / set = 0 / count = 1 / is_cnt = 0
+****************** cycle 211 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc0003c>
+  <InsRsp    valid no error ins 0x3c040000>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_DIR_RSP
+  <MEMC.XRAM_RSP_DIR_RSP> Request the TGT_RSP FSM to return data: rsrcid = 0 / address = 0 / nwords = 16
+****************** cycle 212 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc0003c>
+  <InsRsp    valid no error ins 0x3c040000>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_READ_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 213 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc0003c>
+  <InsRsp    valid no error ins 0x3c040000>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+memc_tgt_d RSP VCI : rerror = 0x0 | rdata = 0x00000dead | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1
+  <MEMC.TGT_RSP_XRAM> Response following XRAM access / rsrcid = 0 / rtrdid = 0x1 / rdata = 0xdead / cpt = 0
+****************** cycle 214 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc0003c>
+  <InsRsp    valid no error ins 0x3c040000>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+memc_tgt_d RSP VCI : rerror = 0x0 | rdata = 0x00000beef | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1
+  <MEMC.TGT_RSP_XRAM> Response following XRAM access / rsrcid = 0 / rtrdid = 0x1 / rdata = 0xbeef / cpt = 0x1
+****************** cycle 215 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc0003c>
+  <InsRsp    valid no error ins 0x3c040000>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+memc_tgt_d RSP VCI : rerror = 0x0 | rdata = 0x041200000 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1
+  <MEMC.TGT_RSP_XRAM> Response following XRAM access / rsrcid = 0 / rtrdid = 0x1 / rdata = 0x41200000 / cpt = 0x2
+****************** cycle 216 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc0003c>
+  <InsRsp    valid no error ins 0x3c040000>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x00000dead | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0
+memc_tgt_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1
+  <MEMC.TGT_RSP_XRAM> Response following XRAM access / rsrcid = 0 / rtrdid = 0x1 / rdata = 0 / cpt = 0x3
+****************** cycle 217 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc0003c>
+  <InsRsp    valid no error ins 0x3c040000>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_DATA_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x00000dead | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1
+memc_tgt_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1
+  <MEMC.TGT_RSP_XRAM> Response following XRAM access / rsrcid = 0 / rtrdid = 0x1 / rdata = 0 / cpt = 0x4
+****************** cycle 218 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc0003c>
+  <InsRsp    valid no error ins 0x3c040000>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_WAIT | CMD_IDLE | RSP_DATA_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x00000beef | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1
+memc_tgt_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1
+  <MEMC.TGT_RSP_XRAM> Response following XRAM access / rsrcid = 0 / rtrdid = 0x1 / rdata = 0 / cpt = 0x5
+****************** cycle 219 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc0003c>
+  <InsRsp    valid no error ins 0x3c040000>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_UPDT | CMD_IDLE | RSP_DATA_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x041200000 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0
+memc_tgt_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1
+  <PROC.DCACHE_MISS_UPDT> Write one word: address = 0x000000008 / data = 0xdead / way = 0 / set = 0 / word = 0
+  <MEMC.TGT_RSP_XRAM> Response following XRAM access / rsrcid = 0 / rtrdid = 0x1 / rdata = 0 / cpt = 0x6
+****************** cycle 220 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc0003c>
+  <InsRsp    valid no error ins 0x3c040000>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_UPDT | CMD_IDLE | RSP_DATA_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x041200000 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1
+memc_tgt_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1
+  <PROC.DCACHE_MISS_UPDT> Write one word: address = 0x000000008 / data = 0xbeef / way = 0 / set = 0 / word = 0x1
+  <MEMC.TGT_RSP_XRAM> Response following XRAM access / rsrcid = 0 / rtrdid = 0x1 / rdata = 0 / cpt = 0x7
+****************** cycle 221 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc0003c>
+  <InsRsp    valid no error ins 0x3c040000>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_UPDT | CMD_IDLE | RSP_DATA_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1
+memc_tgt_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1
+  <PROC.DCACHE_MISS_UPDT> Write one word: address = 0x000000008 / data = 0x41200000 / way = 0 / set = 0 / word = 0x2
+  <MEMC.TGT_RSP_XRAM> Response following XRAM access / rsrcid = 0 / rtrdid = 0x1 / rdata = 0 / cpt = 0x8
+****************** cycle 222 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc0003c>
+  <InsRsp    valid no error ins 0x3c040000>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_UPDT | CMD_IDLE | RSP_DATA_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1
+memc_tgt_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1
+  <PROC.DCACHE_MISS_UPDT> Write one word: address = 0x000000008 / data = 0 / way = 0 / set = 0 / word = 0x3
+  <MEMC.TGT_RSP_XRAM> Response following XRAM access / rsrcid = 0 / rtrdid = 0x1 / rdata = 0 / cpt = 0x9
+****************** cycle 223 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc0003c>
+  <InsRsp    valid no error ins 0x3c040000>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_UPDT | CMD_IDLE | RSP_DATA_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1
+memc_tgt_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1
+  <PROC.DCACHE_MISS_UPDT> Write one word: address = 0x000000008 / data = 0 / way = 0 / set = 0 / word = 0x4
+  <MEMC.TGT_RSP_XRAM> Response following XRAM access / rsrcid = 0 / rtrdid = 0x1 / rdata = 0 / cpt = 0xa
+****************** cycle 224 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc0003c>
+  <InsRsp    valid no error ins 0x3c040000>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_UPDT | CMD_IDLE | RSP_DATA_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1
+memc_tgt_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1
+  <PROC.DCACHE_MISS_UPDT> Write one word: address = 0x000000008 / data = 0 / way = 0 / set = 0 / word = 0x5
+  <MEMC.TGT_RSP_XRAM> Response following XRAM access / rsrcid = 0 / rtrdid = 0x1 / rdata = 0 / cpt = 0xb
+****************** cycle 225 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc0003c>
+  <InsRsp    valid no error ins 0x3c040000>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_UPDT | CMD_IDLE | RSP_DATA_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1
+memc_tgt_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1
+  <PROC.DCACHE_MISS_UPDT> Write one word: address = 0x000000008 / data = 0 / way = 0 / set = 0 / word = 0x6
+  <MEMC.TGT_RSP_XRAM> Response following XRAM access / rsrcid = 0 / rtrdid = 0x1 / rdata = 0 / cpt = 0xc
+****************** cycle 226 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc0003c>
+  <InsRsp    valid no error ins 0x3c040000>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_UPDT | CMD_IDLE | RSP_DATA_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1
+memc_tgt_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1
+  <PROC.DCACHE_MISS_UPDT> Write one word: address = 0x000000008 / data = 0 / way = 0 / set = 0 / word = 0x7
+  <MEMC.TGT_RSP_XRAM> Response following XRAM access / rsrcid = 0 / rtrdid = 0x1 / rdata = 0 / cpt = 0xd
+****************** cycle 227 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc0003c>
+  <InsRsp    valid no error ins 0x3c040000>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_UPDT | CMD_IDLE | RSP_DATA_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1
+memc_tgt_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1
+  <PROC.DCACHE_MISS_UPDT> Write one word: address = 0x000000008 / data = 0 / way = 0 / set = 0 / word = 0x8
+  <MEMC.TGT_RSP_XRAM> Response following XRAM access / rsrcid = 0 / rtrdid = 0x1 / rdata = 0 / cpt = 0xe
+****************** cycle 228 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc0003c>
+  <InsRsp    valid no error ins 0x3c040000>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_UPDT | CMD_IDLE | RSP_DATA_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1
+memc_tgt_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0x1 | ack = 0x1
+  <PROC.DCACHE_MISS_UPDT> Write one word: address = 0x000000008 / data = 0 / way = 0 / set = 0 / word = 0x9
+  <MEMC.TGT_RSP_XRAM> Response following XRAM access / rsrcid = 0 / rtrdid = 0x1 / rdata = 0 / cpt = 0xf
+****************** cycle 229 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc0003c>
+  <InsRsp    valid no error ins 0x3c040000>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_UPDT | CMD_IDLE | RSP_DATA_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1
+  <PROC.DCACHE_MISS_UPDT> Write one word: address = 0x000000008 / data = 0 / way = 0 / set = 0 / word = 0xa
+****************** cycle 230 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc0003c>
+  <InsRsp    valid no error ins 0x3c040000>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_UPDT | CMD_IDLE | RSP_DATA_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1
+  <PROC.DCACHE_MISS_UPDT> Write one word: address = 0x000000008 / data = 0 / way = 0 / set = 0 / word = 0xb
+****************** cycle 231 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc0003c>
+  <InsRsp    valid no error ins 0x3c040000>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_UPDT | CMD_IDLE | RSP_DATA_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1
+  <PROC.DCACHE_MISS_UPDT> Write one word: address = 0x000000008 / data = 0 / way = 0 / set = 0 / word = 0xc
+****************** cycle 232 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc0003c>
+  <InsRsp    valid no error ins 0x3c040000>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_UPDT | CMD_IDLE | RSP_DATA_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0 | ack = 0x1
+  <PROC.DCACHE_MISS_UPDT> Write one word: address = 0x000000008 / data = 0 / way = 0 / set = 0 / word = 0xd
+****************** cycle 233 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc0003c>
+  <InsRsp    valid no error ins 0x3c040000>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_UPDT | CMD_IDLE | RSP_DATA_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x01 | reop = 0x1 | ack = 0x1
+  <PROC.DCACHE_MISS_UPDT> Write one word: address = 0x000000008 / data = 0 / way = 0 / set = 0 / word = 0xe
+****************** cycle 234 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc0003c>
+  <InsRsp    valid no error ins 0x3c040000>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_MISS_UPDT | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+  <PROC.DCACHE_MISS_UPDT> Write one word: address = 0x000000008 / data = 0 / way = 0 / set = 0 / word = 0xf
+****************** cycle 235 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc0003c>
+  <InsRsp    valid no error ins 0x3c040000>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+  <PROC.DCACHE_IDLE> HIT in dcache
+****************** cycle 236 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc0003c>
+  <InsRsp    valid no error ins 0x3c040000>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp   valid no error rdata 0x41200000>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 237 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00040>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_VICTIM | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 238 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00040>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_INS_MISS | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d CMD VCI : RD  @ = 0x0bfc00040  wdata = 0x000000000  srcid = 0x0000  trdid = 0x03  plen  = 0x040  eop = 0x1  ack = 0x1
+****************** cycle 239 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00040>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 240 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00040>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 241 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00040>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 242 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00040>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 243 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00040>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 244 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00040>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 245 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00040>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x02484000c | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0
+****************** cycle 246 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00040>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x02484000c | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 247 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00040>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x0c4800000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 248 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00040>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x046001003 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0
+****************** cycle 249 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00040>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x046001003 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 250 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00040>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x04444f800 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 251 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00040>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x00ff000ee | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 252 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00040>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 253 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00040>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x02404000a | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 254 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00040>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x0a3440000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 255 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00040>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x024040002 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 256 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00040>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x0af640000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 257 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00040>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x00bf0001a | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 258 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00040>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 259 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00040>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x03c04bfc0 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 260 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00040>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x0248400f8 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 261 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00040>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x00ff000e4 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 262 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00040>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0x1 | ack = 0x1
+****************** cycle 263 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00040>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 264 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00040>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 265 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00040>
+  <InsRsp    valid no error ins 0x2484000c>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 266 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00044>
+  <InsRsp    valid no error ins 0xc4800000>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0x8 wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+  <PROC.DCACHE_IDLE> HIT in dcache
+****************** cycle 267 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00048>
+  <InsRsp    valid no error ins 0x46001003>
+  <DataReq   valid mode MODE_KERNEL type DATA_READ @ 0xc wdata 0 be 0xf>
+  <DataRsp   valid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 268 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc0004c>
+  <InsRsp    valid no error ins 0x4444f800>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xc wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 269 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00050>
+  <InsRsp    valid no error ins 0xff000ee>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xc wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 270 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00054>
+  <InsRsp    valid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xc wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 271 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003b8>
+  <InsRsp    valid no error ins 0x804021>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xc wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 272 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003bc>
+  <InsRsp    valid no error ins 0x24090030>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xc wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 273 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003c0>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xc wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_VICTIM | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 274 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003c0>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xc wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_INS_MISS | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d CMD VCI : RD  @ = 0x0bfc003c0  wdata = 0x000000000  srcid = 0x0000  trdid = 0x03  plen  = 0x040  eop = 0x1  ack = 0x1
+****************** cycle 275 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003c0>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xc wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 276 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003c0>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xc wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 277 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003c0>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xc wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 278 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003c0>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xc wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 279 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003c0>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xc wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 280 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003c0>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xc wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 281 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003c0>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xc wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x0a3490000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0
+****************** cycle 282 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003c0>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xc wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x0a3490000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 283 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003c0>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xc wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x024090078 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 284 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003c0>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xc wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x0a3490000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0
+****************** cycle 285 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003c0>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xc wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x0a3490000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 286 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003c0>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xc wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x024090008 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 287 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003c0>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xc wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x03c0af000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 288 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003c0>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xc wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x0010a5024 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 289 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003c0>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xc wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x0000a5702 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 290 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003c0>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xc wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x0294b000a | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 291 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003c0>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xc wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x011600004 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 292 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003c0>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xc wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 293 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003c0>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xc wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x0214a0030 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 294 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003c0>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xc wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x00bf000fe | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 295 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003c0>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xc wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 296 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003c0>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xc wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x0214a0037 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 297 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003c0>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xc wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x0a34a0000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 298 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003c0>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xc wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x02129ffff | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0x1 | ack = 0x1
+****************** cycle 299 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003c0>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xc wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 300 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003c0>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xc wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 301 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003c0>
+  <InsRsp    valid no error ins 0xa3490000>
+  <DataReq invalid mode MODE_KERNEL type DATA_READ @ 0xc wdata 0 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 302 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003c4>
+  <InsRsp    valid no error ins 0x24090078>
+  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp   valid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 303 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003c8>
+  <InsRsp    valid no error ins 0xa3490000>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 304 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003cc>
+  <InsRsp    valid no error ins 0x24090008>
+  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x78 be 0x1>
+  <DataRsp   valid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_DATA_WRITE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d CMD VCI : WR  @ = 0x0d0200000  wdata = 0x000000030  srcid = 0x0000  trdid = 0x08  plen  = 0x004  eop = 0x1  ack = 0x1
+****************** cycle 305 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003d0>
+  <InsRsp    valid no error ins 0x3c0af000>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x78 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 306 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003d4>
+  <InsRsp    valid no error ins 0x10a5024>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x78 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 307 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003d8>
+  <InsRsp    valid no error ins 0xa5702>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x78 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 308 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003dc>
+  <InsRsp    valid no error ins 0x294b000a>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x78 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 309 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003e0>
+  <InsRsp    valid no error ins 0x11600004>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x78 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 310 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003e4>
+  <InsRsp    valid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x78 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 311 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003e8>
+  <InsRsp    valid no error ins 0x214a0030>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x78 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0
+****************** cycle 312 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003ec>
+  <InsRsp    valid no error ins 0xbf000fe>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x78 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_DATA_WRITE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0x1
+****************** cycle 313 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003f0>
+  <InsRsp    valid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x78 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 314 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003f8>
+  <InsRsp    valid no error ins 0xa34a0000>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x78 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 315 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003fc>
+  <InsRsp    valid no error ins 0x2129ffff>
+  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp   valid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_DATA_WRITE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d CMD VCI : WR  @ = 0x0d0200000  wdata = 0x000000078  srcid = 0x0000  trdid = 0x08  plen  = 0x004  eop = 0x1  ack = 0x1
+****************** cycle 316 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00400>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_VICTIM | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 317 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00400>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_INS_MISS | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d CMD VCI : RD  @ = 0x0bfc00400  wdata = 0x000000000  srcid = 0x0000  trdid = 0x03  plen  = 0x040  eop = 0x1  ack = 0x1
+****************** cycle 318 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00400>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 319 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00400>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 320 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00400>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 321 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00400>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 322 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00400>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0
+****************** cycle 323 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00400>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_DATA_WRITE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0x1
+****************** cycle 324 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00400>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 325 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00400>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x01d20fff3 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0
+****************** cycle 326 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00400>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_DATA_WRITE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d CMD VCI : WR  @ = 0x0d0200000  wdata = 0x000000030  srcid = 0x0000  trdid = 0x08  plen  = 0x004  eop = 0x1  ack = 0x1
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x01d20fff3 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 327 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00400>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_WAIT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000084100 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 328 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00400>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x003e00008 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0
+****************** cycle 329 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00400>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x003e00008 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 330 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00400>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 331 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00400>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x0bc000010 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 332 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00400>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 333 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00400>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000005 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 334 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00400>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 335 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00400>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 336 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00400>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000010 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 337 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00400>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 338 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00400>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 339 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00400>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 340 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00400>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 341 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00400>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0 | ack = 0x1
+****************** cycle 342 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00400>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_INS_MISS | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x03 | reop = 0x1 | ack = 0x1
+****************** cycle 343 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00400>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_MISS_UPDT | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0
+****************** cycle 344 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00400>
+  <InsRsp  invalid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_DATA_WRITE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0x1
+****************** cycle 345 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00400>
+  <InsRsp    valid no error ins 0x1d20fff3>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 346 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00404>
+  <InsRsp    valid no error ins 0x84100>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 347 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003d0>
+  <InsRsp    valid no error ins 0x3c0af000>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 348 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003d4>
+  <InsRsp    valid no error ins 0x10a5024>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 349 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003d8>
+  <InsRsp    valid no error ins 0xa5702>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 350 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003dc>
+  <InsRsp    valid no error ins 0x294b000a>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 351 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003e0>
+  <InsRsp    valid no error ins 0x11600004>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 352 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003e4>
+  <InsRsp    valid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 353 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003e8>
+  <InsRsp    valid no error ins 0x214a0030>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 354 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003ec>
+  <InsRsp    valid no error ins 0xbf000fe>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 355 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003f0>
+  <InsRsp    valid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 356 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003f8>
+  <InsRsp    valid no error ins 0xa34a0000>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 357 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003fc>
+  <InsRsp    valid no error ins 0x2129ffff>
+  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp   valid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 358 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00400>
+  <InsRsp    valid no error ins 0x1d20fff3>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 359 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00404>
+  <InsRsp    valid no error ins 0x84100>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_DATA_WRITE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d CMD VCI : WR  @ = 0x0d0200000  wdata = 0x000000030  srcid = 0x0000  trdid = 0x08  plen  = 0x004  eop = 0x1  ack = 0x1
+****************** cycle 360 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003d0>
+  <InsRsp    valid no error ins 0x3c0af000>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 361 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003d4>
+  <InsRsp    valid no error ins 0x10a5024>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 362 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003d8>
+  <InsRsp    valid no error ins 0xa5702>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 363 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003dc>
+  <InsRsp    valid no error ins 0x294b000a>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 364 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003e0>
+  <InsRsp    valid no error ins 0x11600004>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 365 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003e4>
+  <InsRsp    valid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 366 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003e8>
+  <InsRsp    valid no error ins 0x214a0030>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0
+****************** cycle 367 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003ec>
+  <InsRsp    valid no error ins 0xbf000fe>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_DATA_WRITE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0x1
+****************** cycle 368 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003f0>
+  <InsRsp    valid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 369 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003f8>
+  <InsRsp    valid no error ins 0xa34a0000>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 370 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003fc>
+  <InsRsp    valid no error ins 0x2129ffff>
+  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp   valid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 371 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00400>
+  <InsRsp    valid no error ins 0x1d20fff3>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 372 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00404>
+  <InsRsp    valid no error ins 0x84100>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_DATA_WRITE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d CMD VCI : WR  @ = 0x0d0200000  wdata = 0x000000030  srcid = 0x0000  trdid = 0x08  plen  = 0x004  eop = 0x1  ack = 0x1
+****************** cycle 373 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003d0>
+  <InsRsp    valid no error ins 0x3c0af000>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 374 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003d4>
+  <InsRsp    valid no error ins 0x10a5024>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 375 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003d8>
+  <InsRsp    valid no error ins 0xa5702>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 376 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003dc>
+  <InsRsp    valid no error ins 0x294b000a>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 377 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003e0>
+  <InsRsp    valid no error ins 0x11600004>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 378 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003e4>
+  <InsRsp    valid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 379 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003e8>
+  <InsRsp    valid no error ins 0x214a0030>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0
+****************** cycle 380 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003ec>
+  <InsRsp    valid no error ins 0xbf000fe>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_DATA_WRITE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0x1
+****************** cycle 381 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003f0>
+  <InsRsp    valid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 382 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003f8>
+  <InsRsp    valid no error ins 0xa34a0000>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 383 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003fc>
+  <InsRsp    valid no error ins 0x2129ffff>
+  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp   valid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 384 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00400>
+  <InsRsp    valid no error ins 0x1d20fff3>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 385 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00404>
+  <InsRsp    valid no error ins 0x84100>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_DATA_WRITE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d CMD VCI : WR  @ = 0x0d0200000  wdata = 0x000000030  srcid = 0x0000  trdid = 0x08  plen  = 0x004  eop = 0x1  ack = 0x1
+****************** cycle 386 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003d0>
+  <InsRsp    valid no error ins 0x3c0af000>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 387 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003d4>
+  <InsRsp    valid no error ins 0x10a5024>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 388 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003d8>
+  <InsRsp    valid no error ins 0xa5702>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 389 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003dc>
+  <InsRsp    valid no error ins 0x294b000a>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 390 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003e0>
+  <InsRsp    valid no error ins 0x11600004>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 391 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003e4>
+  <InsRsp    valid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 392 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003e8>
+  <InsRsp    valid no error ins 0x214a0030>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0
+****************** cycle 393 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003ec>
+  <InsRsp    valid no error ins 0xbf000fe>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_DATA_WRITE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0x1
+****************** cycle 394 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003f0>
+  <InsRsp    valid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 395 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003f8>
+  <InsRsp    valid no error ins 0xa34a0000>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 396 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003fc>
+  <InsRsp    valid no error ins 0x2129ffff>
+  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x38 be 0x1>
+  <DataRsp   valid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 397 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00400>
+  <InsRsp    valid no error ins 0x1d20fff3>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x38 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 398 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00404>
+  <InsRsp    valid no error ins 0x84100>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x38 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_DATA_WRITE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d CMD VCI : WR  @ = 0x0d0200000  wdata = 0x000000038  srcid = 0x0000  trdid = 0x08  plen  = 0x004  eop = 0x1  ack = 0x1
+****************** cycle 399 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003d0>
+  <InsRsp    valid no error ins 0x3c0af000>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x38 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 400 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003d4>
+  <InsRsp    valid no error ins 0x10a5024>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x38 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 401 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003d8>
+  <InsRsp    valid no error ins 0xa5702>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x38 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 402 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003dc>
+  <InsRsp    valid no error ins 0x294b000a>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x38 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 403 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003e0>
+  <InsRsp    valid no error ins 0x11600004>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x38 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 404 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003e4>
+  <InsRsp    valid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x38 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 405 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003f4>
+  <InsRsp    valid no error ins 0x214a0037>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x38 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0
+****************** cycle 406 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003f8>
+  <InsRsp    valid no error ins 0xa34a0000>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x38 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_DATA_WRITE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0x1
+****************** cycle 407 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003fc>
+  <InsRsp    valid no error ins 0x2129ffff>
+  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x46 be 0x1>
+  <DataRsp   valid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 408 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00400>
+  <InsRsp    valid no error ins 0x1d20fff3>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x46 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 409 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00404>
+  <InsRsp    valid no error ins 0x84100>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x46 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_DATA_WRITE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d CMD VCI : WR  @ = 0x0d0200000  wdata = 0x000000046  srcid = 0x0000  trdid = 0x08  plen  = 0x004  eop = 0x1  ack = 0x1
+****************** cycle 410 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003d0>
+  <InsRsp    valid no error ins 0x3c0af000>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x46 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 411 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003d4>
+  <InsRsp    valid no error ins 0x10a5024>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x46 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 412 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003d8>
+  <InsRsp    valid no error ins 0xa5702>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x46 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 413 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003dc>
+  <InsRsp    valid no error ins 0x294b000a>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x46 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 414 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003e0>
+  <InsRsp    valid no error ins 0x11600004>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x46 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 415 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003e4>
+  <InsRsp    valid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x46 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 416 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003e8>
+  <InsRsp    valid no error ins 0x214a0030>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x46 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0
+****************** cycle 417 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003ec>
+  <InsRsp    valid no error ins 0xbf000fe>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x46 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_DATA_WRITE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0x1
+****************** cycle 418 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003f0>
+  <InsRsp    valid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x46 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 419 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003f8>
+  <InsRsp    valid no error ins 0xa34a0000>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x46 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 420 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003fc>
+  <InsRsp    valid no error ins 0x2129ffff>
+  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x38 be 0x1>
+  <DataRsp   valid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 421 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00400>
+  <InsRsp    valid no error ins 0x1d20fff3>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x38 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 422 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00404>
+  <InsRsp    valid no error ins 0x84100>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x38 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_DATA_WRITE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d CMD VCI : WR  @ = 0x0d0200000  wdata = 0x000000038  srcid = 0x0000  trdid = 0x08  plen  = 0x004  eop = 0x1  ack = 0x1
+****************** cycle 423 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003d0>
+  <InsRsp    valid no error ins 0x3c0af000>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x38 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 424 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003d4>
+  <InsRsp    valid no error ins 0x10a5024>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x38 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 425 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003d8>
+  <InsRsp    valid no error ins 0xa5702>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x38 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 426 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003dc>
+  <InsRsp    valid no error ins 0x294b000a>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x38 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 427 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003e0>
+  <InsRsp    valid no error ins 0x11600004>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x38 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 428 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003e4>
+  <InsRsp    valid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x38 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 429 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003e8>
+  <InsRsp    valid no error ins 0x214a0030>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x38 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0
+****************** cycle 430 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003ec>
+  <InsRsp    valid no error ins 0xbf000fe>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x38 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_DATA_WRITE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0x1
+****************** cycle 431 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003f0>
+  <InsRsp    valid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x38 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 432 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003f8>
+  <InsRsp    valid no error ins 0xa34a0000>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x38 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 433 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc003fc>
+  <InsRsp    valid no error ins 0x2129ffff>
+  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp   valid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 434 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00400>
+  <InsRsp    valid no error ins 0x1d20fff3>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 435 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00404>
+  <InsRsp    valid no error ins 0x84100>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_DATA_WRITE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d CMD VCI : WR  @ = 0x0d0200000  wdata = 0x000000030  srcid = 0x0000  trdid = 0x08  plen  = 0x004  eop = 0x1  ack = 0x1
+****************** cycle 436 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00408>
+  <InsRsp    valid no error ins 0x3e00008>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 437 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc0040c>
+  <InsRsp    valid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 438 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00058>
+  <InsRsp    valid no error ins 0x2404000a>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 439 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc0005c>
+  <InsRsp    valid no error ins 0xa3440000>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 440 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00060>
+  <InsRsp    valid no error ins 0x24040002>
+  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0xa be 0x1>
+  <DataRsp   valid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 441 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00064>
+  <InsRsp    valid no error ins 0xaf640000>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xd0200000 wdata 0xa be 0x1>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 442 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00068>
+  <InsRsp    valid no error ins 0xbf0001a>
+  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xe0000000 wdata 0x2 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0
+****************** cycle 443 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00068>
+  <InsRsp    valid no error ins 0xbf0001a>
+  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xe0000000 wdata 0x2 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_DATA_WRITE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0x1
+****************** cycle 444 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00068>
+  <InsRsp    valid no error ins 0xbf0001a>
+  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xe0000000 wdata 0x2 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 445 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00068>
+  <InsRsp    valid no error ins 0xbf0001a>
+  <DataReq   valid mode MODE_KERNEL type DATA_WRITE @ 0xe0000000 wdata 0x2 be 0xf>
+  <DataRsp   valid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 446 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc0006c>
+  <InsRsp    valid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xe0000000 wdata 0x2 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_DATA_WRITE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d CMD VCI : WR  @ = 0x0d0200000  wdata = 0x00000000a  srcid = 0x0000  trdid = 0x08  plen  = 0x004  eop = 0x1  ack = 0x1
+****************** cycle 447 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00068>
+  <InsRsp    valid no error ins 0xbf0001a>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xe0000000 wdata 0x2 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 448 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc0006c>
+  <InsRsp    valid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xe0000000 wdata 0x2 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 449 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00068>
+  <InsRsp    valid no error ins 0xbf0001a>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xe0000000 wdata 0x2 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 450 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc0006c>
+  <InsRsp    valid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xe0000000 wdata 0x2 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 451 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00068>
+  <InsRsp    valid no error ins 0xbf0001a>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xe0000000 wdata 0x2 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 452 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc0006c>
+  <InsRsp    valid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xe0000000 wdata 0x2 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 453 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00068>
+  <InsRsp    valid no error ins 0xbf0001a>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xe0000000 wdata 0x2 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0
+****************** cycle 454 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc0006c>
+  <InsRsp    valid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xe0000000 wdata 0x2 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_DATA_WRITE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d RSP VCI : rerror = 0x0 | rdata = 0x000000000 | rsrcid = 0x0000 | rtrdid = 0x08 | reop = 0x1 | ack = 0x1
+****************** cycle 455 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00068>
+  <InsRsp    valid no error ins 0xbf0001a>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xe0000000 wdata 0x2 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE | P1_WRITE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 456 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc0006c>
+  <InsRsp    valid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xe0000000 wdata 0x2 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 457 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00068>
+  <InsRsp    valid no error ins 0xbf0001a>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xe0000000 wdata 0x2 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_DATA_WRITE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+proc_ini_d CMD VCI : WR  @ = 0x0e0000000  wdata = 0x000000002  srcid = 0x0000  trdid = 0x08  plen  = 0x004  eop = 0x1  ack = 0x1
+****************** cycle 458 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc0006c>
+  <InsRsp    valid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xe0000000 wdata 0x2 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 459 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc00068>
+  <InsRsp    valid no error ins 0xbf0001a>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xe0000000 wdata 0x2 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+****************** cycle 460 ************************************************
+PROC proc
+  <InsReq    valid mode MODE_KERNEL @ 0xbfc0006c>
+  <InsRsp    valid no error ins 0>
+  <DataReq invalid mode MODE_KERNEL type DATA_WRITE @ 0xe0000000 wdata 0x2 be 0xf>
+  <DataRsp invalid no error rdata 0>
+  ICACHE_IDLE | DCACHE_IDLE | CMD_IDLE | RSP_IDLE | TGT_IDLE | CLEANUP_DATA_IDLE
+MEMC memc
+  TGT_CMD_IDLE | TGT_RSP_XRAM_IDLE | READ_IDLE | WRITE_IDLE | SC_IDLE | CLEANUP_IDLE
+  INIT_CMD_INVAL_IDLE | INIT_RSP_IDLE | IXR_CMD_READ_IDLE | IXR_RSP_IDLE | XRAM_RSP_IDLE
+vci_exit terminate simulation, status 0x000000002
Index: branches/v4/softs/tests_ccvcache_v4/test_fpediv/test.S
===================================================================
--- branches/v4/softs/tests_ccvcache_v4/test_fpediv/test.S	(revision 371)
+++ branches/v4/softs/tests_ccvcache_v4/test_fpediv/test.S	(revision 371)
@@ -0,0 +1,81 @@
+/*
+ * trap test: check that a we can generate a trap from FPE instruction
+ */
+#include <registers.h>
+#include <misc.h>
+
+	.text
+	.globl  _start
+_start:
+	.set noreorder
+	la	k0, TTY_BASE
+	la	k1, EXIT_BASE
+	la	sp, 0x00400000 - 16
+
+	PRINT(startstr)
+
+	/* reset cop0 status (keep BEV), enable cop1 */
+	lui	a0, 0x2040;
+	mtc0	a0, COP0_STATUS
+	/* enable COP1 exceptions */
+	li	a0, 0x0f80
+	ctc1	a0, $31
+#if 0
+	li	a0, 0xf000
+	ctc1	a0, $26
+#endif
+	la	a0, div1
+	lwc1	$f2, 0(a0)
+	la	a0, div2
+	lwc1	$f0, 0(a0)
+	div.s	$f0, $f2, $f0
+	cfc1	a0, $31
+	PRINTX
+	PUTCHAR('\n')
+	EXIT(2)
+
+	.globl excep
+excep:
+	.set noreorder
+	PRINT(statusstr)
+	mfc0	a0, COP0_STATUS
+	PRINTX
+
+	PRINT(causestr)
+	mfc0	a0, COP0_CAUSE
+	PRINTX
+
+	PRINT(pcstr)
+	mfc0	a0, COP0_EXPC
+	PRINTX
+
+	PRINT(badvastr)
+	mfc0	a0, COP_0_BADVADDR
+	PRINTX
+	PUTCHAR('\n')
+#we should end there
+	EXIT(0)
+
+	.rodata:
+statusstr: .ascii "status \0"
+causestr: .ascii " cause \0"
+pcstr: .ascii " pc \0"
+badvastr: .ascii " badva \0"
+startstr: .ascii "start\n\0"
+usrstr: .ascii "usrmode\n\0"
+
+	.org EXCEP_ADDRESS - BOOT_ADDRESS
+	.globl evect
+evect:
+	j	excep
+	nop
+	.data
+	.word MAGIC1
+testval:
+	.word MAGIC2
+	.globl div1
+div1:
+	.float	10.0
+	.globl div2
+div2:
+	.float	0.0
Index: branches/v4/softs/tests_ccvcache_v4/test_fpediv/test.elf.txt
===================================================================
--- branches/v4/softs/tests_ccvcache_v4/test_fpediv/test.elf.txt	(revision 371)
+++ branches/v4/softs/tests_ccvcache_v4/test_fpediv/test.elf.txt	(revision 371)
@@ -0,0 +1,167 @@
+
+test.elf:     file format elf32-littlemips
+
+
+Disassembly of section .text:
+
+bfc00000 <_start>:
+bfc00000:	3c1ad020 	lui	k0,0xd020
+bfc00004:	3c1be000 	lui	k1,0xe000
+bfc00008:	3c1d003f 	lui	sp,0x3f
+bfc0000c:	37bdfff0 	ori	sp,sp,0xfff0
+bfc00010:	3c04bfc0 	lui	a0,0xbfc0
+bfc00014:	24840115 	addiu	a0,a0,277
+bfc00018:	0ff000e4 	jal	bfc00390 <print>
+bfc0001c:	00000000 	nop
+bfc00020:	3c042040 	lui	a0,0x2040
+bfc00024:	40846000 	mtc0	a0,c0_status
+bfc00028:	24040f80 	li	a0,3968
+bfc0002c:	44c4f800 	ctc1	a0,$31
+bfc00030:	3c040000 	lui	a0,0x0
+bfc00034:	24840008 	addiu	a0,a0,8
+bfc00038:	c4820000 	lwc1	$f2,0(a0)
+bfc0003c:	3c040000 	lui	a0,0x0
+bfc00040:	2484000c 	addiu	a0,a0,12
+bfc00044:	c4800000 	lwc1	$f0,0(a0)
+bfc00048:	46001003 	div.s	$f0,$f2,$f0
+bfc0004c:	4444f800 	cfc1	a0,$31
+bfc00050:	0ff000ee 	jal	bfc003b8 <printx>
+bfc00054:	00000000 	nop
+bfc00058:	2404000a 	li	a0,10
+bfc0005c:	a3440000 	sb	a0,0(k0)
+bfc00060:	24040002 	li	a0,2
+bfc00064:	af640000 	sw	a0,0(k1)
+bfc00068:	0bf0001a 	j	bfc00068 <_start+0x68>
+bfc0006c:	00000000 	nop
+
+bfc00070 <excep>:
+bfc00070:	3c04bfc0 	lui	a0,0xbfc0
+bfc00074:	248400f8 	addiu	a0,a0,248
+bfc00078:	0ff000e4 	jal	bfc00390 <print>
+bfc0007c:	00000000 	nop
+bfc00080:	40046000 	mfc0	a0,c0_status
+bfc00084:	0ff000ee 	jal	bfc003b8 <printx>
+bfc00088:	00000000 	nop
+bfc0008c:	3c04bfc0 	lui	a0,0xbfc0
+bfc00090:	24840100 	addiu	a0,a0,256
+bfc00094:	0ff000e4 	jal	bfc00390 <print>
+bfc00098:	00000000 	nop
+bfc0009c:	40046800 	mfc0	a0,c0_cause
+bfc000a0:	0ff000ee 	jal	bfc003b8 <printx>
+bfc000a4:	00000000 	nop
+bfc000a8:	3c04bfc0 	lui	a0,0xbfc0
+bfc000ac:	24840108 	addiu	a0,a0,264
+bfc000b0:	0ff000e4 	jal	bfc00390 <print>
+bfc000b4:	00000000 	nop
+bfc000b8:	40047000 	mfc0	a0,c0_epc
+bfc000bc:	0ff000ee 	jal	bfc003b8 <printx>
+bfc000c0:	00000000 	nop
+bfc000c4:	3c04bfc0 	lui	a0,0xbfc0
+bfc000c8:	2484010d 	addiu	a0,a0,269
+bfc000cc:	0ff000e4 	jal	bfc00390 <print>
+bfc000d0:	00000000 	nop
+bfc000d4:	40044000 	mfc0	a0,c0_badvaddr
+bfc000d8:	0ff000ee 	jal	bfc003b8 <printx>
+bfc000dc:	00000000 	nop
+bfc000e0:	2404000a 	li	a0,10
+bfc000e4:	a3440000 	sb	a0,0(k0)
+bfc000e8:	24040000 	li	a0,0
+bfc000ec:	af640000 	sw	a0,0(k1)
+bfc000f0:	0bf0003c 	j	bfc000f0 <excep+0x80>
+bfc000f4:	00000000 	nop
+
+bfc000f8 <statusstr>:
+bfc000f8:	74617473 	jalx	b185d1cc <_stack+0xb145d1dc>
+bfc000fc:	00207375 	0x207375
+
+bfc00100 <causestr>:
+bfc00100:	75616320 	jalx	b5858c80 <_stack+0xb5458c90>
+bfc00104:	00206573 	tltu	at,zero,0x195
+
+bfc00108 <pcstr>:
+bfc00108:	20637020 	addi	v1,v1,28704
+	...
+
+bfc0010d <badvastr>:
+bfc0010d:	6220      	sw	ra,128(sp)
+bfc0010f:	6461      	restore	8,ra,s0
+bfc00111:	6176      	btnez	bfc001ff <usrstr+0xe3>
+bfc00113:	0020      	addiu	s0,sp,128
+
+bfc00115 <startstr>:
+bfc00115:	7473      	cmpi	a0,115
+bfc00117:	7261      	cmpi	v0,97
+bfc00119:	0a74      	la	v0,bfc002e8 <usrstr+0x1cc>
+	...
+
+bfc0011c <usrstr>:
+bfc0011c:	6d727375 	0x6d727375
+bfc00120:	0a65646f 	j	b99591bc <_stack+0xb95591cc>
+bfc00124:	00000000 	nop
+	...
+
+bfc00380 <evect>:
+bfc00380:	0bf0001c 	j	bfc00070 <excep>
+bfc00384:	00000000 	nop
+	...
+
+bfc00390 <print>:
+bfc00390:	00804021 	move	t0,a0
+bfc00394:	81090000 	lb	t1,0(t0)
+bfc00398:	11200005 	beqz	t1,bfc003b0 <end>
+bfc0039c:	00000000 	nop
+bfc003a0:	a3490000 	sb	t1,0(k0)
+bfc003a4:	25080001 	addiu	t0,t0,1
+bfc003a8:	0bf000e5 	j	bfc00394 <print+0x4>
+bfc003ac:	00000000 	nop
+
+bfc003b0 <end>:
+bfc003b0:	03e00008 	jr	ra
+bfc003b4:	00000000 	nop
+
+bfc003b8 <printx>:
+bfc003b8:	00804021 	move	t0,a0
+bfc003bc:	24090030 	li	t1,48
+bfc003c0:	a3490000 	sb	t1,0(k0)
+bfc003c4:	24090078 	li	t1,120
+bfc003c8:	a3490000 	sb	t1,0(k0)
+bfc003cc:	24090008 	li	t1,8
+bfc003d0:	3c0af000 	lui	t2,0xf000
+bfc003d4:	010a5024 	and	t2,t0,t2
+bfc003d8:	000a5702 	srl	t2,t2,0x1c
+bfc003dc:	294b000a 	slti	t3,t2,10
+bfc003e0:	11600004 	beqz	t3,bfc003f4 <printx+0x3c>
+bfc003e4:	00000000 	nop
+bfc003e8:	214a0030 	addi	t2,t2,48
+bfc003ec:	0bf000fe 	j	bfc003f8 <printx+0x40>
+bfc003f0:	00000000 	nop
+bfc003f4:	214a0037 	addi	t2,t2,55
+bfc003f8:	a34a0000 	sb	t2,0(k0)
+bfc003fc:	2129ffff 	addi	t1,t1,-1
+bfc00400:	1d20fff3 	bgtz	t1,bfc003d0 <printx+0x18>
+bfc00404:	00084100 	sll	t0,t0,0x4
+bfc00408:	03e00008 	jr	ra
+bfc0040c:	00000000 	nop
+
+Disassembly of section .reginfo:
+
+bfc00410 <.reginfo>:
+bfc00410:	bc000010 	cache	0x0,16(zero)
+bfc00414:	00000000 	nop
+bfc00418:	00000005 	0x5
+	...
+bfc00424:	00000010 	mfhi	zero
+
+Disassembly of section .data:
+
+00000000 <testval-0x4>:
+   0:	0000dead 	0xdead
+
+00000004 <testval>:
+   4:	0000beef 	0xbeef
+
+00000008 <div1>:
+   8:	41200000 	0x41200000
+
+0000000c <div2>:
+   c:	00000000 	nop
Index: branches/v4/softs/tests_ccvcache_v4/test_icache_inval_pa/Makefile
===================================================================
--- branches/v4/softs/tests_ccvcache_v4/test_icache_inval_pa/Makefile	(revision 371)
+++ branches/v4/softs/tests_ccvcache_v4/test_icache_inval_pa/Makefile	(revision 371)
@@ -0,0 +1,2 @@
+LDSCRIPT=./ldscript
+include ../Makefile.inc
Index: branches/v4/softs/tests_ccvcache_v4/test_icache_inval_pa/ldscript
===================================================================
--- branches/v4/softs/tests_ccvcache_v4/test_icache_inval_pa/ldscript	(revision 371)
+++ branches/v4/softs/tests_ccvcache_v4/test_icache_inval_pa/ldscript	(revision 371)
@@ -0,0 +1,67 @@
+/*
+ *
+ * SOCLIB_GPL_HEADER_BEGIN
+ * 
+ * This file is part of SoCLib, GNU GPLv2.
+ * 
+ * SoCLib is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ * 
+ * SoCLib is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * General Public License for more details.
+ * 
+ * You should have received a copy of the GNU General Public License
+ * along with SoCLib; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301, USA.
+ * 
+ * SOCLIB_GPL_HEADER_END
+ *
+ * Copyright (c) UPMC, Lip6, SoC
+ *         Nicolas Pouillon <nipo@ssji.net>, 2006-2007
+ *
+ * Maintainers: abdelmalek.si-merabet@lip6.fr
+ */
+ENTRY(_start)
+
+SECTIONS
+{
+   . = 0xbfc00000;
+   .text : {
+      *(.text)
+/* load .text2 one page after .text */
+      . = ALIGN(0x1000);
+      *(.text2)
+   }
+   .rodata : {
+      *(.rodata)
+      . = ALIGN(4);
+   }
+   . = 0x00000000;
+   .data  : {
+      *(.data)
+   }
+   .sdata : {
+      *(.lit8)
+      *(.lit4)
+      *(.sdata)
+   }
+   _gp = .;
+   . = ALIGN(4);
+   _edata = .;
+   .sbss  : {
+      *(.sbss)
+      *(.scommon)
+   }
+   .bss   : {
+      *(.bss)
+      *(COMMON)
+   }
+   . = ALIGN(4);
+   _end = .;
+   _heap = .;
+   _stack = 0x00400000-16;
+}
Index: branches/v4/softs/tests_ccvcache_v4/test_icache_inval_pa/mtty0
===================================================================
--- branches/v4/softs/tests_ccvcache_v4/test_icache_inval_pa/mtty0	(revision 371)
+++ branches/v4/softs/tests_ccvcache_v4/test_icache_inval_pa/mtty0	(revision 371)
@@ -0,0 +1,4 @@
+[20hstart
+mmu started before DMA 0x0000DEAD
+mmu started after DMA 0x0000BEEF
+mmu started after FLUSH 0x0000BEEF
Index: branches/v4/softs/tests_ccvcache_v4/test_icache_inval_pa/run
===================================================================
--- branches/v4/softs/tests_ccvcache_v4/test_icache_inval_pa/run	(revision 371)
+++ branches/v4/softs/tests_ccvcache_v4/test_icache_inval_pa/run	(revision 371)
@@ -0,0 +1,38 @@
+#!/bin/sh 
+
+. ../common/common.sh
+
+check_output()
+{
+	egrep "^mmu started before DMA 0x0000DEAD$" run.out > /dev/null
+	if [ $? -ne 0 ]; then
+		echo "couldn't find string 1 in output - mtty not working ?" >> run.out
+		return 1
+	fi
+	egrep "^mmu started after DMA 0x0000BEEF$" run.out > /dev/null
+	if [ $? -ne 0 ]; then
+		echo "couldn't find string 2 in output - mtty not working ?" >> run.out
+		return 1
+	fi
+	egrep "^mmu started after FLUSH 0x0000BEEF$" run.out > /dev/null
+	if [ $? -ne 0 ]; then
+		echo "couldn't find string 3 in output - mtty not working ?" >> run.out
+		return 1
+	fi
+	return 0;
+}
+
+make --quiet || exit 1
+${SIMUL} > run.out 2>&1 
+if [ $? -eq 0 ]; then
+	if check_output; then
+		echo "test passsed";
+		make --quiet clean
+		exit 0;
+	fi
+	echo "test FAILED"
+	exit 1
+fi
+echo "test FAILED"
+exit 1
+
Index: branches/v4/softs/tests_ccvcache_v4/test_icache_inval_pa/test.S
===================================================================
--- branches/v4/softs/tests_ccvcache_v4/test_icache_inval_pa/test.S	(revision 371)
+++ branches/v4/softs/tests_ccvcache_v4/test_icache_inval_pa/test.S	(revision 371)
@@ -0,0 +1,167 @@
+/*
+ * cache inval test: check that VC_ICACHE_INVAL_PA does the job
+ * on a cc_vcache, the cache invalidation/update should be done by hardware
+ * and VC_ICACHE_INVAL_PA should not be needed.
+ */
+#include <registers.h>
+#include <misc.h>
+#include <vcache.h>
+
+#define TEST_ADDRESS 0x200000
+
+	.text
+	.globl  _start
+_start:
+	.set noreorder
+	la	k0, TTY_BASE
+	la	k1, EXIT_BASE
+
+	PRINT(startstr)
+
+	/* reset cop0 status (keep BEV) */
+	lui	a0, 0x0040;
+	mtc0	a0, COP0_STATUS
+
+	la	a0, pte1_a
+	srl	a0, a0, 13
+	mtc2	a0, VC_PTPR
+	nop
+
+	li	a0, VC_TLB_EN_ITLB | VC_TLB_EN_DTLB | VC_TLB_EN_ICACHE | VC_TLB_EN_DCACHE
+	mtc2 	a0, VC_TLB_EN
+
+	PRINT(mmustr_a)
+	#copy 'doload' to TEST_ADDRESS 
+	la	a1, DMA_BASE
+	la	a0, doload 
+	sw      a0, DMA_SRC(a1)
+	la	a0, TEST_ADDRESS
+	sw      a0, DMA_DST(a1)
+        li      a0, 8
+	sw      a0, DMA_LEN(a1) /* start DMA */
+loop1:
+	lw      a0, DMA_LEN(a1)
+	bne     a0, zero, loop1;
+	nop
+	sw	zero, DMA_RESET(a1)
+
+	la	a0, TEST_ADDRESS
+	jalr	a0
+	nop
+	PRINTX
+	PUTCHAR('\n')
+	#copy 'doload2' to TEST_ADDRESS 
+	la	a1, DMA_BASE
+	la	a0, doload2
+	sw      a0, DMA_SRC(a1)
+	la	a0, TEST_ADDRESS
+	sw      a0, DMA_DST(a1)
+        li      a0, 8
+	sw      a0, DMA_LEN(a1) /* start DMA */
+loop2:
+	lw      a0, DMA_LEN(a1)
+	bne     a0, zero, loop2;
+	nop
+	sw	zero, DMA_RESET(a1)
+
+	PRINT(mmustr_b)
+	la	a0, TEST_ADDRESS
+	jalr	a0
+	nop
+	PRINTX
+	PUTCHAR('\n')
+
+        la      a0, TEST_ADDRESS
+	mtc2    a0, VC_DATA_LO
+	mtc2    zero, VC_DATA_HI
+	mtc2    zero, VC_ICACHE_INVAL_PA
+	addi	a0, a0, 4
+	mtc2    a0, VC_DATA_LO
+	mtc2    zero, VC_DATA_HI
+	mtc2    zero, VC_ICACHE_INVAL_PA
+	nop
+
+	PRINT(mmustr_c)
+	la	a0, TEST_ADDRESS
+	jalr	a0
+	nop
+	PRINTX
+	PUTCHAR('\n')
+	/* we should get there */
+	EXIT(0)
+
+	.globl doload
+doload:
+	jr      ra
+	li      a0, MAGIC1
+	/* we should not get there */
+	EXIT(1)
+	nop
+
+	.globl doload2
+doload2:
+	jr ra
+	li      a0, MAGIC2
+	/* we should not get there */
+	EXIT(2)
+	nop
+
+	.globl excep
+excep:
+	.set noreorder
+	PRINT(statusstr)
+	mfc0	a0, COP0_STATUS
+	PRINTX
+
+	PRINT(causestr)
+	mfc0	a0, COP0_CAUSE
+	PRINTX
+
+	PRINT(pcstr)
+	mfc0	a0, COP0_EXPC
+	PRINTX
+
+	PRINT(badvastr)
+	mfc0	a0, COP_0_BADVADDR
+	PRINTX
+
+	PUTCHAR('\n')
+	/* we should not get there */
+	EXIT(3)
+
+	.rodata:
+statusstr: .ascii "status \0"
+causestr: .ascii " cause \0"
+pcstr: .ascii " pc \0"
+badvastr: .ascii " badva \0"
+mmustr_a: .ascii "mmu started before DMA \0"
+mmustr_b: .ascii "mmu started after DMA \0"
+mmustr_c: .ascii "mmu started after FLUSH \0"
+startstr: .ascii "start\n\0"
+
+	.org EXCEP_ADDRESS - BOOT_ADDRESS
+	.globl evect
+evect:
+	j	excep
+	nop
+
+	.data
+	.word MAGIC1
+testval:
+	.word MAGIC2
+
+	.globl pte1_a
+pte1_a:
+	.align 13
+	.word PTE1_V | PTE1_C | PTE1_W | 0x0 /* map PA 0 at VA 0 */
+	.org pte1_a + (TEST_ADDRESS >> 21) * 4
+	.word PTE1_V | PTE1_C | PTE1_X | (TEST_ADDRESS >> 21) /* map PA 0x200000 at VA 0x200000, read-only/exec */
+	.word 0x0
+	.org pte1_a + (BOOT_ADDRESS >> 21) * 4
+	.word PTE1_V | PTE1_C | PTE1_X | (BOOT_ADDRESS >> 21) /* map PA 0xbfc00000 at VA 0xbfc00000 */
+	.org pte1_a + (TTY_BASE >> 21) * 4
+	.word PTE1_V | PTE1_W | (TTY_BASE >> 21) /* map PA 0xd0200000 at VA 0xd0200000 */
+	.org pte1_a + (EXIT_BASE >> 21) * 4
+	.word PTE1_V | PTE1_W | (EXIT_BASE >> 21) /* map PA 0xe0000000 at VA 0xe0000000 */
+	.org pte1_a + (DMA_BASE >> 21) * 4
+	.word PTE1_V | PTE1_W | (DMA_BASE >> 21) /* map PA 0xe8000000 at VA 0xe0000000 */
Index: branches/v4/softs/tests_ccvcache_v4/test_idtlb_inval/Makefile
===================================================================
--- branches/v4/softs/tests_ccvcache_v4/test_idtlb_inval/Makefile	(revision 371)
+++ branches/v4/softs/tests_ccvcache_v4/test_idtlb_inval/Makefile	(revision 371)
@@ -0,0 +1,2 @@
+LDSCRIPT=./ldscript
+include ../Makefile.inc
Index: branches/v4/softs/tests_ccvcache_v4/test_idtlb_inval/ldscript
===================================================================
--- branches/v4/softs/tests_ccvcache_v4/test_idtlb_inval/ldscript	(revision 371)
+++ branches/v4/softs/tests_ccvcache_v4/test_idtlb_inval/ldscript	(revision 371)
@@ -0,0 +1,67 @@
+/*
+ *
+ * SOCLIB_GPL_HEADER_BEGIN
+ * 
+ * This file is part of SoCLib, GNU GPLv2.
+ * 
+ * SoCLib is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ * 
+ * SoCLib is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * General Public License for more details.
+ * 
+ * You should have received a copy of the GNU General Public License
+ * along with SoCLib; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301, USA.
+ * 
+ * SOCLIB_GPL_HEADER_END
+ *
+ * Copyright (c) UPMC, Lip6, SoC
+ *         Nicolas Pouillon <nipo@ssji.net>, 2006-2007
+ *
+ * Maintainers: abdelmalek.si-merabet@lip6.fr
+ */
+ENTRY(_start)
+
+SECTIONS
+{
+   . = 0xbfc00000;
+   .text : {
+      *(.text)
+/* load .text2 one page after .text */
+      . = ALIGN(0x1000);
+      *(.text2)
+   }
+   .rodata : {
+      *(.rodata)
+      . = ALIGN(4);
+   }
+   . = 0x00000000;
+   .data  : {
+      *(.data)
+   }
+   .sdata : {
+      *(.lit8)
+      *(.lit4)
+      *(.sdata)
+   }
+   _gp = .;
+   . = ALIGN(4);
+   _edata = .;
+   .sbss  : {
+      *(.sbss)
+      *(.scommon)
+   }
+   .bss   : {
+      *(.bss)
+      *(COMMON)
+   }
+   . = ALIGN(4);
+   _end = .;
+   _heap = .;
+   _stack = 0x00400000-16;
+}
Index: branches/v4/softs/tests_ccvcache_v4/test_idtlb_inval/run
===================================================================
--- branches/v4/softs/tests_ccvcache_v4/test_idtlb_inval/run	(revision 371)
+++ branches/v4/softs/tests_ccvcache_v4/test_idtlb_inval/run	(revision 371)
@@ -0,0 +1,28 @@
+#!/bin/sh 
+
+. ../common/common.sh
+
+check_output()
+{
+	egrep "^mmu started 0x0000BEEF 0x0000DEAD 0x0000DEAD 0x0000BEEF$" run.out > /dev/null
+	if [ $? -ne 0 ]; then
+		echo "couldn't find string in output - mtty not working ?" >> run.out
+		return 1
+	fi
+	return 0;
+}
+
+make --quiet || exit 1
+${SIMUL} > run.out 2>&1 
+if [ $? -eq 0 ]; then
+	if check_output; then
+		echo "test passsed";
+		make --quiet clean
+		exit 0;
+	fi
+	echo "test FAILED"
+	exit 1
+fi
+echo "test FAILED"
+exit 1
+
Index: branches/v4/softs/tests_ccvcache_v4/test_idtlb_inval/test.S
===================================================================
--- branches/v4/softs/tests_ccvcache_v4/test_idtlb_inval/test.S	(revision 371)
+++ branches/v4/softs/tests_ccvcache_v4/test_idtlb_inval/test.S	(revision 371)
@@ -0,0 +1,158 @@
+/*
+ * itlb inval: a write to a PTE2 should invalidate the corresponding
+ * itlb and dtlb entries. 
+ */
+#include <registers.h>
+#include <misc.h>
+#include <vcache.h>
+
+	.text
+	.globl  _start
+_start:
+	.set noreorder
+	la	k0, TTY_BASE
+	la	k1, EXIT_BASE
+
+	PRINT(startstr)
+
+	/* reset cop0 status (keep BEV) */
+	lui	a0, 0x0040;
+	mtc0	a0, COP0_STATUS
+
+	la	a0, pte1_a
+	srl	a0, a0, 13
+	mtc2	a0, VC_PTPR
+	nop
+
+	li	a0, VC_TLB_EN_ITLB | VC_TLB_EN_DTLB | VC_TLB_EN_ICACHE | VC_TLB_EN_DCACHE
+	mtc2 	a0, VC_TLB_EN
+
+	PRINT(mmustr)
+	/* cause a DTLB miss */
+	la	t0, roval
+	lw	a0, 0(t0)
+	PRINTX
+	PUTCHAR(' ')
+
+	/* cause a itlb miss */
+	jal	doload
+	nop
+	PRINTX
+	PUTCHAR(' ')
+
+	la	t0, pte2_a
+	la	a0, (BOOT_ADDRESS+0x2000) >> 12
+	sw	a0, 12(t0) /* change PTE2 */
+	sync
+1:
+	ll	a0, 8(t0)
+	la	a0, PTE2_V | PTE2_C | PTE2_X
+	sc	a0, 8(t0)
+	beqz	a0, 1b
+	nop
+
+	/* now we should get the second values */
+	la	t0, roval
+	lw	a0, 0(t0)
+	PRINTX
+	PUTCHAR(' ')
+
+	jal	doload 
+	nop
+	PRINTX
+	PUTCHAR('\n')
+	/* we should get there */
+	EXIT(0)
+
+	.globl excep
+excep:
+	.set noreorder
+	PRINT(statusstr)
+	mfc0	a0, COP0_STATUS
+	PRINTX
+
+	PRINT(causestr)
+	mfc0	a0, COP0_CAUSE
+	PRINTX
+
+	PRINT(pcstr)
+	mfc0	a0, COP0_EXPC
+	PRINTX
+
+	PRINT(badvastr)
+	mfc0	a0, COP_0_BADVADDR
+	PRINTX
+
+	PUTCHAR('\n')
+	/* we should not get there */
+	EXIT(1)
+
+	.rodata:
+statusstr: .ascii "status \0"
+causestr: .ascii " cause \0"
+pcstr: .ascii " pc \0"
+badvastr: .ascii " badva \0"
+mmustr: .ascii "mmu started \0"
+startstr: .ascii "start\n\0"
+
+	.org EXCEP_ADDRESS - BOOT_ADDRESS
+	.globl evect
+evect:
+	j	excep
+	nop
+
+	/*
+	 * code that will be switched by MMU switch.
+	 * we use a ldscript trick here, to load this function at
+	 * the appropriate address
+	 */
+	.section .text2, "ax"
+	.globl doload
+doload:
+	jr      ra
+	li      a0, MAGIC1
+	/* we should not get there */
+	EXIT(1)
+	nop
+roval:	.word MAGIC2
+	.align 12
+	.globl doload2
+doload2:
+	jr      ra
+	li      a0, MAGIC2
+	/* we should not get there */
+	EXIT(1)
+	nop
+roval2:	.word MAGIC1
+
+	.data
+	.word MAGIC1
+testval:
+	.word MAGIC2
+	.globl pte2_a
+
+/*
+ * one PD with a level 2 PTP: we change an entry in the PTP and
+ * check that the ITLB has been invalidated
+ */
+pte2_a:
+	.align 12
+	.word PTE2_V | PTE2_C | PTE2_X
+	.word BOOT_ADDRESS >> 12
+	.word PTE2_V | PTE2_C | PTE2_X
+	.word (BOOT_ADDRESS+0x1000) >> 12
+	.org pte2_a + 4092
+	.word 0
+	.globl pte2_b
+	.globl pte1_a
+pte1_a:
+	.align 13
+	.word PTE1_V | PTE1_C | PTE1_W | 0x0 /* map PA 0 at VA 0 */
+	.word 0x0
+	.org pte1_a + (BOOT_ADDRESS >> 21) * 4
+	.word PTE1_V | PTE1_T | (0x1000 >> 12) /* map PA 0xbfc00000 at VA 0xbfc00000 with 4k page: check real address of pte2_a !!! */
+	.org pte1_a + (TTY_BASE >> 21) * 4
+	.word PTE1_V | PTE1_W | (TTY_BASE >> 21) /* map PA 0xd0200000 at VA 0xd0200000 */
+	.org pte1_a + (EXIT_BASE >> 21) * 4
+	.word PTE1_V | PTE1_W | (EXIT_BASE >> 21) /* map PA 0xe0000000 at VA 0xe0000000 */
+	.org pte1_a + 8192
Index: branches/v4/softs/tests_ccvcache_v4/test_idtlb_inval2/Makefile
===================================================================
--- branches/v4/softs/tests_ccvcache_v4/test_idtlb_inval2/Makefile	(revision 371)
+++ branches/v4/softs/tests_ccvcache_v4/test_idtlb_inval2/Makefile	(revision 371)
@@ -0,0 +1,2 @@
+LDSCRIPT=./ldscript
+include ../Makefile.inc
Index: branches/v4/softs/tests_ccvcache_v4/test_idtlb_inval2/ldscript
===================================================================
--- branches/v4/softs/tests_ccvcache_v4/test_idtlb_inval2/ldscript	(revision 371)
+++ branches/v4/softs/tests_ccvcache_v4/test_idtlb_inval2/ldscript	(revision 371)
@@ -0,0 +1,67 @@
+/*
+ *
+ * SOCLIB_GPL_HEADER_BEGIN
+ * 
+ * This file is part of SoCLib, GNU GPLv2.
+ * 
+ * SoCLib is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ * 
+ * SoCLib is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * General Public License for more details.
+ * 
+ * You should have received a copy of the GNU General Public License
+ * along with SoCLib; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301, USA.
+ * 
+ * SOCLIB_GPL_HEADER_END
+ *
+ * Copyright (c) UPMC, Lip6, SoC
+ *         Nicolas Pouillon <nipo@ssji.net>, 2006-2007
+ *
+ * Maintainers: abdelmalek.si-merabet@lip6.fr
+ */
+ENTRY(_start)
+
+SECTIONS
+{
+   . = 0xbfc00000;
+   .text : {
+      *(.text)
+/* load .text2 one page after .text */
+      . = ALIGN(0x1000);
+      *(.text2)
+   }
+   .rodata : {
+      *(.rodata)
+      . = ALIGN(4);
+   }
+   . = 0x00000000;
+   .data  : {
+      *(.data)
+   }
+   .sdata : {
+      *(.lit8)
+      *(.lit4)
+      *(.sdata)
+   }
+   _gp = .;
+   . = ALIGN(4);
+   _edata = .;
+   .sbss  : {
+      *(.sbss)
+      *(.scommon)
+   }
+   .bss   : {
+      *(.bss)
+      *(COMMON)
+   }
+   . = ALIGN(4);
+   _end = .;
+   _heap = .;
+   _stack = 0x00400000-16;
+}
Index: branches/v4/softs/tests_ccvcache_v4/test_idtlb_inval2/run
===================================================================
--- branches/v4/softs/tests_ccvcache_v4/test_idtlb_inval2/run	(revision 371)
+++ branches/v4/softs/tests_ccvcache_v4/test_idtlb_inval2/run	(revision 371)
@@ -0,0 +1,28 @@
+#!/bin/sh 
+
+. ../common/common.sh
+
+check_output()
+{
+	egrep "^mmu started 0x0000BEEF 0x0000DEAD 0x0000DEAD 0x0000BEEF$" run.out > /dev/null
+	if [ $? -ne 0 ]; then
+		echo "couldn't find string in output - mtty not working ?" >> run.out
+		return 1
+	fi
+	return 0;
+}
+
+make --quiet || exit 1
+${SIMUL} > run.out 2>&1 
+if [ $? -eq 0 ]; then
+	if check_output; then
+		echo "test passsed";
+		make --quiet clean
+		exit 0;
+	fi
+	echo "test FAILED"
+	exit 1
+fi
+echo "test FAILED"
+exit 1
+
Index: branches/v4/softs/tests_ccvcache_v4/test_idtlb_inval2/test.S
===================================================================
--- branches/v4/softs/tests_ccvcache_v4/test_idtlb_inval2/test.S	(revision 371)
+++ branches/v4/softs/tests_ccvcache_v4/test_idtlb_inval2/test.S	(revision 371)
@@ -0,0 +1,160 @@
+/*
+ * itlb inval: a write to a PTE2 should invalidate the corresponding
+ * itlb and dtlb entries. 
+ */
+#include <registers.h>
+#include <misc.h>
+#include <vcache.h>
+
+	.text
+	.globl  _start
+_start:
+	.set noreorder
+	la	k0, TTY_BASE
+	la	k1, EXIT_BASE
+
+	PRINT(startstr)
+
+	/* reset cop0 status (keep BEV) */
+	lui	a0, 0x0040;
+	mtc0	a0, COP0_STATUS
+
+	la	a0, pte1_a
+	srl	a0, a0, 13
+	mtc2	a0, VC_PTPR
+	nop
+
+	li	a0, VC_TLB_EN_ITLB | VC_TLB_EN_DTLB | VC_TLB_EN_ICACHE | VC_TLB_EN_DCACHE
+	mtc2 	a0, VC_TLB_EN
+
+	PRINT(mmustr)
+	/* cause a DTLB miss */
+	la	t0, roval
+	lw	a0, 0(t0)
+	PRINTX
+	PUTCHAR(' ')
+
+	/* cause a itlb miss */
+	jal	doload
+	nop
+	PRINTX
+	PUTCHAR(' ')
+
+	la	t0, pte2_a
+	mtc2 	t0, VC_DTLB_INVAL /* force tlb miss on write */
+	la	a0, (BOOT_ADDRESS+0x2000) >> 12
+	sw	a0, 12(t0) /* change PTE2 */
+	sync
+1:
+	ll	a0, 8(t0)
+	mtc2 	t0, VC_DTLB_INVAL /* force tlb miss on write */
+	la	a0, PTE2_V | PTE2_C | PTE2_X
+	sc	a0, 8(t0)
+	beqz	a0, 1b
+	nop
+
+	/* now we should get the second values */
+	la	t0, roval
+	lw	a0, 0(t0)
+	PRINTX
+	PUTCHAR(' ')
+
+	jal	doload 
+	nop
+	PRINTX
+	PUTCHAR('\n')
+	/* we should get there */
+	EXIT(0)
+
+	.globl excep
+excep:
+	.set noreorder
+	PRINT(statusstr)
+	mfc0	a0, COP0_STATUS
+	PRINTX
+
+	PRINT(causestr)
+	mfc0	a0, COP0_CAUSE
+	PRINTX
+
+	PRINT(pcstr)
+	mfc0	a0, COP0_EXPC
+	PRINTX
+
+	PRINT(badvastr)
+	mfc0	a0, COP_0_BADVADDR
+	PRINTX
+
+	PUTCHAR('\n')
+	/* we should not get there */
+	EXIT(1)
+
+	.rodata:
+statusstr: .ascii "status \0"
+causestr: .ascii " cause \0"
+pcstr: .ascii " pc \0"
+badvastr: .ascii " badva \0"
+mmustr: .ascii "mmu started \0"
+startstr: .ascii "start\n\0"
+
+	.org EXCEP_ADDRESS - BOOT_ADDRESS
+	.globl evect
+evect:
+	j	excep
+	nop
+
+	/*
+	 * code that will be switched by MMU switch.
+	 * we use a ldscript trick here, to load this function at
+	 * the appropriate address
+	 */
+	.section .text2, "ax"
+	.globl doload
+doload:
+	jr      ra
+	li      a0, MAGIC1
+	/* we should not get there */
+	EXIT(1)
+	nop
+roval:	.word MAGIC2
+	.align 12
+	.globl doload2
+doload2:
+	jr      ra
+	li      a0, MAGIC2
+	/* we should not get there */
+	EXIT(1)
+	nop
+roval2:	.word MAGIC1
+
+	.data
+	.word MAGIC1
+testval:
+	.word MAGIC2
+	.globl pte2_a
+
+/*
+ * one PD with a level 2 PTP: we change an entry in the PTP and
+ * check that the ITLB has been invalidated
+ */
+pte2_a:
+	.align 12
+	.word PTE2_V | PTE2_C | PTE2_X
+	.word BOOT_ADDRESS >> 12
+	.word PTE2_V | PTE2_C | PTE2_X
+	.word (BOOT_ADDRESS+0x1000) >> 12
+	.org pte2_a + 4092
+	.word 0
+	.globl pte2_b
+	.globl pte1_a
+pte1_a:
+	.align 13
+	.word PTE1_V | PTE1_C | PTE1_W | 0x0 /* map PA 0 at VA 0 */
+	.word 0x0
+	.org pte1_a + (BOOT_ADDRESS >> 21) * 4
+	.word PTE1_V | PTE1_T | (0x1000 >> 12) /* map PA 0xbfc00000 at VA 0xbfc00000 with 4k page: check real address of pte2_a !!! */
+	.org pte1_a + (TTY_BASE >> 21) * 4
+	.word PTE1_V | PTE1_W | (TTY_BASE >> 21) /* map PA 0xd0200000 at VA 0xd0200000 */
+	.org pte1_a + (EXIT_BASE >> 21) * 4
+	.word PTE1_V | PTE1_W | (EXIT_BASE >> 21) /* map PA 0xe0000000 at VA 0xe0000000 */
+	.org pte1_a + 8192
Index: branches/v4/softs/tests_ccvcache_v4/test_idtlb_inval3/Makefile
===================================================================
--- branches/v4/softs/tests_ccvcache_v4/test_idtlb_inval3/Makefile	(revision 371)
+++ branches/v4/softs/tests_ccvcache_v4/test_idtlb_inval3/Makefile	(revision 371)
@@ -0,0 +1,2 @@
+LDSCRIPT=./ldscript
+include ../Makefile.inc
Index: branches/v4/softs/tests_ccvcache_v4/test_idtlb_inval3/ldscript
===================================================================
--- branches/v4/softs/tests_ccvcache_v4/test_idtlb_inval3/ldscript	(revision 371)
+++ branches/v4/softs/tests_ccvcache_v4/test_idtlb_inval3/ldscript	(revision 371)
@@ -0,0 +1,67 @@
+/*
+ *
+ * SOCLIB_GPL_HEADER_BEGIN
+ * 
+ * This file is part of SoCLib, GNU GPLv2.
+ * 
+ * SoCLib is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ * 
+ * SoCLib is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * General Public License for more details.
+ * 
+ * You should have received a copy of the GNU General Public License
+ * along with SoCLib; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301, USA.
+ * 
+ * SOCLIB_GPL_HEADER_END
+ *
+ * Copyright (c) UPMC, Lip6, SoC
+ *         Nicolas Pouillon <nipo@ssji.net>, 2006-2007
+ *
+ * Maintainers: abdelmalek.si-merabet@lip6.fr
+ */
+ENTRY(_start)
+
+SECTIONS
+{
+   . = 0xbfc00000;
+   .text : {
+      *(.text)
+/* load .text2 one page after .text */
+      . = ALIGN(0x1000);
+      *(.text2)
+   }
+   .rodata : {
+      *(.rodata)
+      . = ALIGN(4);
+   }
+   . = 0x00000000;
+   .data  : {
+      *(.data)
+   }
+   .sdata : {
+      *(.lit8)
+      *(.lit4)
+      *(.sdata)
+   }
+   _gp = .;
+   . = ALIGN(4);
+   _edata = .;
+   .sbss  : {
+      *(.sbss)
+      *(.scommon)
+   }
+   .bss   : {
+      *(.bss)
+      *(COMMON)
+   }
+   . = ALIGN(4);
+   _end = .;
+   _heap = .;
+   _stack = 0x00400000-16;
+}
Index: branches/v4/softs/tests_ccvcache_v4/test_idtlb_inval3/mtty0
===================================================================
--- branches/v4/softs/tests_ccvcache_v4/test_idtlb_inval3/mtty0	(revision 371)
+++ branches/v4/softs/tests_ccvcache_v4/test_idtlb_inval3/mtty0	(revision 371)
@@ -0,0 +1,2 @@
+[20hstart
+mmu started 0x0000BEEF 0x0000DEAD 0x0000DEAD 0x0000BEEF
Index: branches/v4/softs/tests_ccvcache_v4/test_idtlb_inval3/run
===================================================================
--- branches/v4/softs/tests_ccvcache_v4/test_idtlb_inval3/run	(revision 371)
+++ branches/v4/softs/tests_ccvcache_v4/test_idtlb_inval3/run	(revision 371)
@@ -0,0 +1,28 @@
+#!/bin/sh 
+
+. ../common/common.sh
+
+check_output()
+{
+	egrep "^mmu started 0x0000BEEF 0x0000DEAD 0x0000DEAD 0x0000BEEF$" run.out > /dev/null
+	if [ $? -ne 0 ]; then
+		echo "couldn't find string in output - mtty not working ?" >> run.out
+		return 1
+	fi
+	return 0;
+}
+
+make --quiet || exit 1
+${SIMUL} > run.out 2>&1 
+if [ $? -eq 0 ]; then
+	if check_output; then
+		echo "test passsed";
+		make --quiet clean
+		exit 0;
+	fi
+	echo "test FAILED"
+	exit 1
+fi
+echo "test FAILED"
+exit 1
+
Index: branches/v4/softs/tests_ccvcache_v4/test_idtlb_inval3/test.S
===================================================================
--- branches/v4/softs/tests_ccvcache_v4/test_idtlb_inval3/test.S	(revision 371)
+++ branches/v4/softs/tests_ccvcache_v4/test_idtlb_inval3/test.S	(revision 371)
@@ -0,0 +1,162 @@
+/*
+ * itlb inval: a write to a PTE2 should invalidate the corresponding
+ * itlb and dtlb entries. 
+ */
+#include <registers.h>
+#include <misc.h>
+#include <vcache.h>
+
+	.text
+	.globl  _start
+_start:
+	.set noreorder
+	la	k0, TTY_BASE
+	la	k1, EXIT_BASE
+
+	PRINT(startstr)
+
+	/* reset cop0 status (keep BEV) */
+	lui	a0, 0x0040;
+	mtc0	a0, COP0_STATUS
+
+	la	a0, pte1_a
+	srl	a0, a0, 13
+	mtc2	a0, VC_PTPR
+	nop
+
+	li	a0, VC_TLB_EN_ITLB | VC_TLB_EN_DTLB | VC_TLB_EN_ICACHE | VC_TLB_EN_DCACHE
+	mtc2 	a0, VC_TLB_EN
+
+	PRINT(mmustr)
+	/* cause a DTLB miss */
+	la	t0, roval
+	lw	a0, 0(t0)
+	PRINTX
+	PUTCHAR(' ')
+
+	/* cause a itlb miss */
+	jal	doload
+	nop
+	PRINTX
+	PUTCHAR(' ')
+
+	la	t0, pte2_a
+	mtc2 	t0, VC_DATA_L /* force dcache miss on write */
+	mtc2	zero, VC_DATA_H
+	mtc2	zero, VC_DCACHE_INVAL_PA
+	la	a0, (BOOT_ADDRESS+0x2000) >> 12
+	sw	a0, 12(t0) /* change PTE2 */
+	sync
+1:
+	ll	a0, 8(t0)
+	mtc2 	t0, VC_DTLB_INVAL /* force tlb miss on write */
+	la	a0, PTE2_V | PTE2_C | PTE2_X
+	sc	a0, 8(t0)
+	beqz	a0, 1b
+	nop
+
+	/* now we should get the second values */
+	la	t0, roval
+	lw	a0, 0(t0)
+	PRINTX
+	PUTCHAR(' ')
+
+	jal	doload 
+	nop
+	PRINTX
+	PUTCHAR('\n')
+	/* we should get there */
+	EXIT(0)
+
+	.globl excep
+excep:
+	.set noreorder
+	PRINT(statusstr)
+	mfc0	a0, COP0_STATUS
+	PRINTX
+
+	PRINT(causestr)
+	mfc0	a0, COP0_CAUSE
+	PRINTX
+
+	PRINT(pcstr)
+	mfc0	a0, COP0_EXPC
+	PRINTX
+
+	PRINT(badvastr)
+	mfc0	a0, COP_0_BADVADDR
+	PRINTX
+
+	PUTCHAR('\n')
+	/* we should not get there */
+	EXIT(1)
+
+	.rodata:
+statusstr: .ascii "status \0"
+causestr: .ascii " cause \0"
+pcstr: .ascii " pc \0"
+badvastr: .ascii " badva \0"
+mmustr: .ascii "mmu started \0"
+startstr: .ascii "start\n\0"
+
+	.org EXCEP_ADDRESS - BOOT_ADDRESS
+	.globl evect
+evect:
+	j	excep
+	nop
+
+	/*
+	 * code that will be switched by MMU switch.
+	 * we use a ldscript trick here, to load this function at
+	 * the appropriate address
+	 */
+	.section .text2, "ax"
+	.globl doload
+doload:
+	jr      ra
+	li      a0, MAGIC1
+	/* we should not get there */
+	EXIT(1)
+	nop
+roval:	.word MAGIC2
+	.align 12
+	.globl doload2
+doload2:
+	jr      ra
+	li      a0, MAGIC2
+	/* we should not get there */
+	EXIT(1)
+	nop
+roval2:	.word MAGIC1
+
+	.data
+	.word MAGIC1
+testval:
+	.word MAGIC2
+	.globl pte2_a
+
+/*
+ * one PD with a level 2 PTP: we change an entry in the PTP and
+ * check that the ITLB has been invalidated
+ */
+pte2_a:
+	.align 12
+	.word PTE2_V | PTE2_C | PTE2_X
+	.word BOOT_ADDRESS >> 12
+	.word PTE2_V | PTE2_C | PTE2_X
+	.word (BOOT_ADDRESS+0x1000) >> 12
+	.org pte2_a + 4092
+	.word 0
+	.globl pte2_b
+	.globl pte1_a
+pte1_a:
+	.align 13
+	.word PTE1_V | PTE1_C | PTE1_W | 0x0 /* map PA 0 at VA 0 */
+	.word 0x0
+	.org pte1_a + (BOOT_ADDRESS >> 21) * 4
+	.word PTE1_V | PTE1_T | (0x1000 >> 12) /* map PA 0xbfc00000 at VA 0xbfc00000 with 4k page: check real address of pte2_a !!! */
+	.org pte1_a + (TTY_BASE >> 21) * 4
+	.word PTE1_V | PTE1_W | (TTY_BASE >> 21) /* map PA 0xd0200000 at VA 0xd0200000 */
+	.org pte1_a + (EXIT_BASE >> 21) * 4
+	.word PTE1_V | PTE1_W | (EXIT_BASE >> 21) /* map PA 0xe0000000 at VA 0xe0000000 */
+	.org pte1_a + 8192
Index: branches/v4/softs/tests_ccvcache_v4/test_idtlb_inval4/Makefile
===================================================================
--- branches/v4/softs/tests_ccvcache_v4/test_idtlb_inval4/Makefile	(revision 371)
+++ branches/v4/softs/tests_ccvcache_v4/test_idtlb_inval4/Makefile	(revision 371)
@@ -0,0 +1,2 @@
+LDSCRIPT=./ldscript
+include ../Makefile.inc
Index: branches/v4/softs/tests_ccvcache_v4/test_idtlb_inval4/ldscript
===================================================================
--- branches/v4/softs/tests_ccvcache_v4/test_idtlb_inval4/ldscript	(revision 371)
+++ branches/v4/softs/tests_ccvcache_v4/test_idtlb_inval4/ldscript	(revision 371)
@@ -0,0 +1,67 @@
+/*
+ *
+ * SOCLIB_GPL_HEADER_BEGIN
+ * 
+ * This file is part of SoCLib, GNU GPLv2.
+ * 
+ * SoCLib is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ * 
+ * SoCLib is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * General Public License for more details.
+ * 
+ * You should have received a copy of the GNU General Public License
+ * along with SoCLib; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301, USA.
+ * 
+ * SOCLIB_GPL_HEADER_END
+ *
+ * Copyright (c) UPMC, Lip6, SoC
+ *         Nicolas Pouillon <nipo@ssji.net>, 2006-2007
+ *
+ * Maintainers: abdelmalek.si-merabet@lip6.fr
+ */
+ENTRY(_start)
+
+SECTIONS
+{
+   . = 0xbfc00000;
+   .text : {
+      *(.text)
+/* load .text2 one page after .text */
+      . = ALIGN(0x1000);
+      *(.text2)
+   }
+   .rodata : {
+      *(.rodata)
+      . = ALIGN(4);
+   }
+   . = 0x00000000;
+   .data  : {
+      *(.data)
+   }
+   .sdata : {
+      *(.lit8)
+      *(.lit4)
+      *(.sdata)
+   }
+   _gp = .;
+   . = ALIGN(4);
+   _edata = .;
+   .sbss  : {
+      *(.sbss)
+      *(.scommon)
+   }
+   .bss   : {
+      *(.bss)
+      *(COMMON)
+   }
+   . = ALIGN(4);
+   _end = .;
+   _heap = .;
+   _stack = 0x00400000-16;
+}
Index: branches/v4/softs/tests_ccvcache_v4/test_idtlb_inval4/mtty0
===================================================================
--- branches/v4/softs/tests_ccvcache_v4/test_idtlb_inval4/mtty0	(revision 371)
+++ branches/v4/softs/tests_ccvcache_v4/test_idtlb_inval4/mtty0	(revision 371)
@@ -0,0 +1,2 @@
+[20hstart
+mmu started 0x0000BEEF 0x0000DEAD 0x0000DEAD 0x0000BEEF
Index: branches/v4/softs/tests_ccvcache_v4/test_idtlb_inval4/run
===================================================================
--- branches/v4/softs/tests_ccvcache_v4/test_idtlb_inval4/run	(revision 371)
+++ branches/v4/softs/tests_ccvcache_v4/test_idtlb_inval4/run	(revision 371)
@@ -0,0 +1,28 @@
+#!/bin/sh 
+
+. ../common/common.sh
+
+check_output()
+{
+	egrep "^mmu started 0x0000BEEF 0x0000DEAD 0x0000DEAD 0x0000BEEF$" run.out > /dev/null
+	if [ $? -ne 0 ]; then
+		echo "couldn't find string in output - mtty not working ?" >> run.out
+		return 1
+	fi
+	return 0;
+}
+
+make --quiet || exit 1
+${SIMUL} > run.out 2>&1 
+if [ $? -eq 0 ]; then
+	if check_output; then
+		echo "test passsed";
+		make --quiet clean
+		exit 0;
+	fi
+	echo "test FAILED"
+	exit 1
+fi
+echo "test FAILED"
+exit 1
+
Index: branches/v4/softs/tests_ccvcache_v4/test_idtlb_inval4/test.S
===================================================================
--- branches/v4/softs/tests_ccvcache_v4/test_idtlb_inval4/test.S	(revision 371)
+++ branches/v4/softs/tests_ccvcache_v4/test_idtlb_inval4/test.S	(revision 371)
@@ -0,0 +1,166 @@
+/*
+ * itlb inval: a write to a PTD1 should invalidate the corresponding
+ * itlb and dtlb entries. 
+ */
+#include <registers.h>
+#include <misc.h>
+#include <vcache.h>
+
+	.text
+	.globl  _start
+_start:
+	.set noreorder
+	la	k0, TTY_BASE
+	la	k1, EXIT_BASE
+
+	PRINT(startstr)
+
+	/* reset cop0 status (keep BEV) */
+	lui	a0, 0x0040;
+	mtc0	a0, COP0_STATUS
+
+	la	a0, pte1_a
+	srl	a0, a0, 13
+	mtc2	a0, VC_PTPR
+	nop
+
+	li	a0, VC_TLB_EN_ITLB | VC_TLB_EN_DTLB | VC_TLB_EN_ICACHE | VC_TLB_EN_DCACHE
+	mtc2 	a0, VC_TLB_EN
+
+	PRINT(mmustr)
+	/* cause a DTLB miss */
+	la	t0, roval
+	lw	a0, 0(t0)
+	PRINTX
+	PUTCHAR(' ')
+
+	/* cause a itlb miss */
+	jal	doload
+	nop
+	PRINTX
+	PUTCHAR(' ')
+
+	la	t0, pte1_ac
+1:
+	ll	a0, 0(t0)
+	la	a0, (0x2000 >> 12) | PTE1_V | PTE1_T /* check real address of pet2_b */
+	sc	a0, 0(t0) /* change PTD1 */
+	beqz	a0, 1b
+	nop
+
+	/* now we should get the second values */
+	la	t0, roval
+	lw	a0, 0(t0)
+	PRINTX
+	PUTCHAR(' ')
+
+	jal	doload 
+	nop
+	PRINTX
+	PUTCHAR('\n')
+	/* we should get there */
+	EXIT(0)
+
+	.globl excep
+excep:
+	.set noreorder
+	PRINT(statusstr)
+	mfc0	a0, COP0_STATUS
+	PRINTX
+
+	PRINT(causestr)
+	mfc0	a0, COP0_CAUSE
+	PRINTX
+
+	PRINT(pcstr)
+	mfc0	a0, COP0_EXPC
+	PRINTX
+
+	PRINT(badvastr)
+	mfc0	a0, COP_0_BADVADDR
+	PRINTX
+
+	PUTCHAR('\n')
+	/* we should not get there */
+	EXIT(1)
+
+	.rodata:
+statusstr: .ascii "status \0"
+causestr: .ascii " cause \0"
+pcstr: .ascii " pc \0"
+badvastr: .ascii " badva \0"
+mmustr: .ascii "mmu started \0"
+startstr: .ascii "start\n\0"
+
+	.org EXCEP_ADDRESS - BOOT_ADDRESS
+	.globl evect
+evect:
+	j	excep
+	nop
+
+	/*
+	 * code that will be switched by MMU switch.
+	 * we use a ldscript trick here, to load this function at
+	 * the appropriate address
+	 */
+	.section .text2, "ax"
+	.globl doload
+doload:
+	jr      ra
+	li      a0, MAGIC1
+	/* we should not get there */
+	EXIT(1)
+	nop
+roval:	.word MAGIC2
+	.align 12
+	.globl doload2
+doload2:
+	jr      ra
+	li      a0, MAGIC2
+	/* we should not get there */
+	EXIT(1)
+	nop
+roval2:	.word MAGIC1
+
+	.data
+	.word MAGIC1
+testval:
+	.word MAGIC2
+	.globl pte2_a
+
+/*
+ * one PD with a level 2 PTP: we change an entry in the PD and
+ * check that the TLBs has been invalidated
+ */
+pte2_a:
+	.align 12
+	.word PTE2_V | PTE2_C | PTE2_X
+	.word BOOT_ADDRESS >> 12
+	.word PTE2_V | PTE2_C | PTE2_X
+	.word (BOOT_ADDRESS+0x1000) >> 12 /* address of doload */
+	.org pte2_a + 4092
+	.word 0
+	.globl pte2_b
+	.globl pte1_a
+pte2_b:
+	.align 12
+	.word PTE2_V | PTE2_C | PTE2_X
+	.word BOOT_ADDRESS >> 12
+	.word PTE2_V | PTE2_C | PTE2_X
+	.word (BOOT_ADDRESS+0x2000) >> 12 /* address of doload2 */
+	.org pte2_b + 4092
+	.word 0
+	.globl pte2_b
+	.globl pte1_a
+pte1_a:
+	.align 13
+	.word PTE1_V | PTE1_C | PTE1_W | 0x0 /* map PA 0 at VA 0 */
+	.word 0x0
+	.org pte1_a + (BOOT_ADDRESS >> 21) * 4
+pte1_ac:
+	.word PTE1_V | PTE1_T | (0x1000 >> 12) /* map PA 0xbfc00000 at VA 0xbfc00000 with 4k page: check real address of pte2_a !!! */
+	.org pte1_a + (TTY_BASE >> 21) * 4
+	.word PTE1_V | PTE1_W | (TTY_BASE >> 21) /* map PA 0xd0200000 at VA 0xd0200000 */
+	.org pte1_a + (EXIT_BASE >> 21) * 4
+	.word PTE1_V | PTE1_W | (EXIT_BASE >> 21) /* map PA 0xe0000000 at VA 0xe0000000 */
+	.org pte1_a + 8192
Index: branches/v4/softs/tests_ccvcache_v4/test_idtlb_ptprinval/Makefile
===================================================================
--- branches/v4/softs/tests_ccvcache_v4/test_idtlb_ptprinval/Makefile	(revision 371)
+++ branches/v4/softs/tests_ccvcache_v4/test_idtlb_ptprinval/Makefile	(revision 371)
@@ -0,0 +1,2 @@
+LDSCRIPT=./ldscript
+include ../Makefile.inc
Index: branches/v4/softs/tests_ccvcache_v4/test_idtlb_ptprinval/ldscript
===================================================================
--- branches/v4/softs/tests_ccvcache_v4/test_idtlb_ptprinval/ldscript	(revision 371)
+++ branches/v4/softs/tests_ccvcache_v4/test_idtlb_ptprinval/ldscript	(revision 371)
@@ -0,0 +1,67 @@
+/*
+ *
+ * SOCLIB_GPL_HEADER_BEGIN
+ * 
+ * This file is part of SoCLib, GNU GPLv2.
+ * 
+ * SoCLib is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ * 
+ * SoCLib is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * General Public License for more details.
+ * 
+ * You should have received a copy of the GNU General Public License
+ * along with SoCLib; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301, USA.
+ * 
+ * SOCLIB_GPL_HEADER_END
+ *
+ * Copyright (c) UPMC, Lip6, SoC
+ *         Nicolas Pouillon <nipo@ssji.net>, 2006-2007
+ *
+ * Maintainers: abdelmalek.si-merabet@lip6.fr
+ */
+ENTRY(_start)
+
+SECTIONS
+{
+   . = 0xbfc00000;
+   .text : {
+      *(.text)
+/* load .text2 one page after .text */
+      . = ALIGN(0x1000);
+      *(.text2)
+   }
+   .rodata : {
+      *(.rodata)
+      . = ALIGN(4);
+   }
+   . = 0x00000000;
+   .data  : {
+      *(.data)
+   }
+   .sdata : {
+      *(.lit8)
+      *(.lit4)
+      *(.sdata)
+   }
+   _gp = .;
+   . = ALIGN(4);
+   _edata = .;
+   .sbss  : {
+      *(.sbss)
+      *(.scommon)
+   }
+   .bss   : {
+      *(.bss)
+      *(COMMON)
+   }
+   . = ALIGN(4);
+   _end = .;
+   _heap = .;
+   _stack = 0x00400000-16;
+}
Index: branches/v4/softs/tests_ccvcache_v4/test_idtlb_ptprinval/run
===================================================================
--- branches/v4/softs/tests_ccvcache_v4/test_idtlb_ptprinval/run	(revision 371)
+++ branches/v4/softs/tests_ccvcache_v4/test_idtlb_ptprinval/run	(revision 371)
@@ -0,0 +1,33 @@
+#!/bin/sh 
+
+. ../common/common.sh
+
+check_output()
+{
+	egrep "^mmu started ptpr_b 0x0000DEAD 0x0000BEEF$" run.out > /dev/null
+	if [ $? -ne 0 ]; then
+		echo "couldn't find string 1 in output - mtty not working ?" >> run.out
+		return 1
+	fi
+	egrep "^mmu started ptpr_a 0x0000BEEF 0x0000DEAD$" run.out > /dev/null
+	if [ $? -ne 0 ]; then
+		echo "couldn't find string 2 in output - mtty not working ?" >> run.out
+		return 1
+	fi
+	return 0;
+}
+
+make --quiet || exit 1
+${SIMUL} > run.out 2>&1 
+if [ $? -eq 0 ]; then
+	if check_output; then
+		echo "test passsed";
+		make --quiet clean
+		exit 0;
+	fi
+	echo "test FAILED"
+	exit 1
+fi
+echo "test FAILED"
+exit 1
+
Index: branches/v4/softs/tests_ccvcache_v4/test_idtlb_ptprinval/test.S
===================================================================
--- branches/v4/softs/tests_ccvcache_v4/test_idtlb_ptprinval/test.S	(revision 371)
+++ branches/v4/softs/tests_ccvcache_v4/test_idtlb_ptprinval/test.S	(revision 371)
@@ -0,0 +1,173 @@
+/*
+ * itlb inval on PTPR write: check that no stale entry exists in the itlb
+ * after MMU context swicth
+ */
+#include <registers.h>
+#include <misc.h>
+#include <vcache.h>
+	.text
+	.globl  _start
+_start:
+	.set noreorder
+	la	k0, TTY_BASE
+	la	k1, EXIT_BASE
+
+	PRINT(startstr)
+
+	/* reset cop0 status (keep BEV) */
+	lui	a0, 0x0040;
+	mtc0	a0, COP0_STATUS
+
+	la	a0, pte1_b
+	srl	a0, a0, 13
+	mtc2	a0, VC_PTPR
+	nop
+
+	li	a0, VC_TLB_EN_ITLB | VC_TLB_EN_DTLB | VC_TLB_EN_ICACHE | VC_TLB_EN_DCACHE
+	mtc2 	a0, VC_TLB_EN
+
+	PRINT(mmustr_b)
+	la	t0, rodata
+	lw	a0, 0(t0)
+	PRINTX
+	PUTCHAR(' ')
+	jal	doload
+	nop
+	PRINTX
+	PUTCHAR('\n')
+	la	a0, pte1_a
+	srl	a0, a0, 13
+	mtc2	a0, VC_PTPR
+	nop
+#if 0 /* works with this - this shows the old pte2 address is cached */
+	la	a0, pte2_a
+	lw	a1, 12(a0)
+	la	a0, pte2_b
+	sw	a1, 12(a0)
+#endif
+	PRINT(mmustr_a)
+	la	t0, rodata
+	lw	a0, 0(t0)
+	PRINTX
+	PUTCHAR(' ')
+	jal	doload
+	nop
+	PRINTX
+	PUTCHAR('\n')
+
+	/* we should get there */
+	EXIT(0)
+
+	.globl excep
+excep:
+	.set noreorder
+	PRINT(statusstr)
+	mfc0	a0, COP0_STATUS
+	PRINTX
+
+	PRINT(causestr)
+	mfc0	a0, COP0_CAUSE
+	PRINTX
+
+	PRINT(pcstr)
+	mfc0	a0, COP0_EXPC
+	PRINTX
+
+	PRINT(badvastr)
+	mfc0	a0, COP_0_BADVADDR
+	PRINTX
+
+	PUTCHAR('\n')
+	/* we should not get there */
+	EXIT(3)
+
+	.rodata:
+statusstr: .ascii "status \0"
+causestr: .ascii " cause \0"
+pcstr: .ascii " pc \0"
+badvastr: .ascii " badva \0"
+mmustr_a: .ascii "mmu started ptpr_a \0"
+mmustr_b: .ascii "mmu started ptpr_b \0"
+startstr: .ascii "start\n\0"
+
+	.org EXCEP_ADDRESS - BOOT_ADDRESS
+	.globl evect
+evect:
+	j	excep
+	nop
+
+	/*
+	 * code that will be switched by MMU switch.
+	 * we use a ldscript trick here, to load this function at
+	 * the appropriate address
+	 */
+	.section .text2, "ax"
+	.globl doload
+doload:
+	jr      ra
+	li      a0, MAGIC1
+	/* we should not get there */
+	EXIT(1)
+	nop
+rodata:
+	.word MAGIC2
+	.org doload + 0x1000 /* in the second page, mapped by pte1_b */
+	jr ra
+	li      a0, MAGIC2
+	/* we should not get there */
+	EXIT(2)
+	nop
+	.word MAGIC1
+
+	.data
+	.word MAGIC1
+testval:
+	.word MAGIC2
+	.globl pte2_a
+
+/*
+ * two PD with two different PTE2 for code: check that itlb points to
+ * the right one by executing 2 different code at the same address
+ */
+pte2_a:
+	.align 12
+	.word PTE2_V | PTE2_C | PTE2_X
+	.word BOOT_ADDRESS >> 12
+	.word PTE2_V | PTE2_C | PTE2_X
+	.word (BOOT_ADDRESS+0x1000) >> 12
+	.org pte2_a + 4092
+	.word 0
+	.globl pte2_b
+pte2_b:
+	.align 12
+	.word PTE2_V | PTE2_C | PTE2_X
+	.word BOOT_ADDRESS >> 12
+	.word PTE2_V | PTE2_C | PTE2_X
+	.word (BOOT_ADDRESS+0x2000) >> 12
+	.org pte2_b + 4092
+	.word 0
+	.globl pte1_a
+pte1_a:
+	.align 13
+	.word PTE1_V | PTE1_C | PTE1_W | 0x0 /* map PA 0 at VA 0 */
+	.word 0x0
+	.org pte1_a + (BOOT_ADDRESS >> 21) * 4
+	.word PTE1_V | PTE1_T | (0x1000 >> 12) /* map PA 0xbfc00000 at VA 0xbfc00000 with 4k page: check real address of pte2_a !!! */
+	.org pte1_a + (TTY_BASE >> 21) * 4
+	.word PTE1_V | PTE1_W | (TTY_BASE >> 21) /* map PA 0xd0200000 at VA 0xd0200000 */
+	.org pte1_a + (EXIT_BASE >> 21) * 4
+	.word PTE1_V | PTE1_W | (EXIT_BASE >> 21) /* map PA 0xe0000000 at VA 0xe0000000 */
+	.org pte1_a + 8192
+	.globl pte1_b
+pte1_b:
+	.align 13
+	.word PTE1_V | PTE1_C | PTE1_W | 0x0 /* map PA 0 at VA 0 */
+	.word 0x0
+	.org pte1_b + (BOOT_ADDRESS >> 21) * 4
+	.word PTE1_V | PTE1_T | (0x2000 >> 12) /* map PA 0xbfc00000 at VA 0xbfc00000 with 4k page: check real address of pte2_b !!! */
+	.org pte1_b + (TTY_BASE >> 21) * 4
+	.word PTE1_V | PTE1_W | (TTY_BASE >> 21) /* map PA 0xd0200000 at VA 0xd0200000 */
+	.org pte1_b + (EXIT_BASE >> 21) * 4
+	.word PTE1_V | PTE1_W | (EXIT_BASE >> 21) /* map PA 0xe0000000 at VA 0xe0000000 */
+	.org pte1_b + 8188
+	.word 0
Index: branches/v4/softs/tests_ccvcache_v4/test_interrupt/Makefile
===================================================================
--- branches/v4/softs/tests_ccvcache_v4/test_interrupt/Makefile	(revision 371)
+++ branches/v4/softs/tests_ccvcache_v4/test_interrupt/Makefile	(revision 371)
@@ -0,0 +1,1 @@
+include ../Makefile.inc
Index: branches/v4/softs/tests_ccvcache_v4/test_interrupt/run
===================================================================
--- branches/v4/softs/tests_ccvcache_v4/test_interrupt/run	(revision 371)
+++ branches/v4/softs/tests_ccvcache_v4/test_interrupt/run	(revision 371)
@@ -0,0 +1,33 @@
+#!/bin/sh 
+
+. ../common/common.sh
+
+check_output()
+{
+	egrep "^0x0000DEAD$" run.out > /dev/null
+	if [ $? -ne 0 ]; then
+		echo "couldn't find string 1 in output - mtty not working ?" >> run.out
+		return 1
+	fi
+	egrep "^status 0x00400103 cause 0x00000100 pc 0xBFC00038 badva 0x00000000$" run.out > /dev/null
+	if [ $? -ne 0 ]; then
+		echo "couldn't find string 2 in output - mtty not working ?" >> run.out
+		return 1
+	fi
+	return 0;
+}
+
+make --quiet || exit 1
+${SIMUL} > run.out 2>&1 
+if [ $? -eq 0 ]; then
+	if check_output; then
+		echo "test passsed";
+		make --quiet clean
+		exit 0;
+	fi
+	echo "test FAILED"
+	exit 1
+fi
+echo "test FAILED"
+exit 1
+
Index: branches/v4/softs/tests_ccvcache_v4/test_interrupt/test.S
===================================================================
--- branches/v4/softs/tests_ccvcache_v4/test_interrupt/test.S	(revision 371)
+++ branches/v4/softs/tests_ccvcache_v4/test_interrupt/test.S	(revision 371)
@@ -0,0 +1,80 @@
+/*
+ * Check that we can take an interrupt, and return from it.
+ * We use a software-triggerted interrupt.
+ */
+#include <registers.h>
+#include <misc.h>
+
+
+	.text
+	.globl  _start
+_start:
+	.set noreorder
+	la	k0, TTY_BASE
+	la	k1, EXIT_BASE
+
+	/* reset cop0 status (keep BEV), enbale soft interrupt 0 */
+	lui     a0, 0x0040;
+	addiu	a0, 0x0101;
+	mtc0    a0, COP0_STATUS
+
+	/* reset cause, make sure IV is off */
+	mtc0	zero, COP0_CAUSE
+
+	PRINT(startstr)
+
+	/* generate an interrupt */
+	mfc0	a0, COP0_CAUSE
+	nop
+	ori	a0, 0x0100
+	mtc0	a0, COP0_CAUSE
+	li	a0, MAGIC1
+	PRINTX
+	PUTCHAR('\n')
+	/* we should end here after taking the exeption */
+	EXIT(0)
+
+	.globl excep
+excep:
+	.set noreorder
+	PRINT(statusstr)
+	mfc0	a0, COP0_STATUS
+	PRINTX
+
+	PRINT(causestr)
+	mfc0	a0, COP0_CAUSE
+	PRINTX
+
+	PRINT(pcstr)
+	mfc0	a0, COP0_EXPC
+	PRINTX
+
+	PRINT(badvastr)
+	mfc0	a0, COP_0_BADVADDR
+	PRINTX
+
+	PUTCHAR('\n')
+	/* clear interrupt */
+	mfc0	a0, COP0_CAUSE
+	xori	a0, 0x100
+	mtc0	a0, COP0_CAUSE
+	nop
+	eret
+	/* we should not end there */
+	EXIT(1)
+
+	.rodata:
+statusstr: .ascii "status \0"
+causestr: .ascii " cause \0"
+pcstr: .ascii " pc \0"
+badvastr: .ascii " badva \0"
+startstr: .ascii "start\n\0"
+eretstr: .ascii "eret\n\0"
+
+	.org EXCEP_ADDRESS - BOOT_ADDRESS
+	.globl evect
+evect:
+	j	excep
+	nop
+	.data
+myvar:	.word 0
Index: branches/v4/softs/tests_ccvcache_v4/test_interrupt_delayslot/Makefile
===================================================================
--- branches/v4/softs/tests_ccvcache_v4/test_interrupt_delayslot/Makefile	(revision 371)
+++ branches/v4/softs/tests_ccvcache_v4/test_interrupt_delayslot/Makefile	(revision 371)
@@ -0,0 +1,2 @@
+include ../Makefile.inc
+CFLAGS+= -DINTERRUPT_DELAY=${INTERRUPT_DELAY}
Index: branches/v4/softs/tests_ccvcache_v4/test_interrupt_delayslot/mtty0
===================================================================
--- branches/v4/softs/tests_ccvcache_v4/test_interrupt_delayslot/mtty0	(revision 371)
+++ branches/v4/softs/tests_ccvcache_v4/test_interrupt_delayslot/mtty0	(revision 371)
@@ -0,0 +1,3 @@
+[20hstart
+status 0x00400403 cause 0x80000000 pc 0xBFC00054 badva 0x00000000 xicu 0x00000000
+end 0x0000DEAD
Index: branches/v4/softs/tests_ccvcache_v4/test_interrupt_delayslot/run
===================================================================
--- branches/v4/softs/tests_ccvcache_v4/test_interrupt_delayslot/run	(revision 371)
+++ branches/v4/softs/tests_ccvcache_v4/test_interrupt_delayslot/run	(revision 371)
@@ -0,0 +1,36 @@
+#!/bin/sh 
+
+. ../common/common.sh
+
+check_output()
+{
+	egrep "^end 0x0000DEAD$" run.out > /dev/null
+	if [ $? -ne 0 ]; then
+		echo "couldn't find string 1 in output - mtty not working ?" >> run.out
+		return 1
+	fi
+	egrep "^status 0x00400403 cause 0x80000000 pc 0xBFC00054 badva 0x00000000 xicu 0x[01][0-9A-F][01][0-9A-F][01][0-9A-F]00$" run.out > /dev/null
+	if [ $? -ne 0 ]; then
+		echo "couldn't find string 2 in output - mtty not working ?" >> run.out
+		return 1
+	fi
+	return 0;
+}
+
+
+for i in 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70; do
+	make clean --quiet
+	make INTERRUPT_DELAY=$i --quiet || exit 1
+    ${SIMUL} > run.out 2>&1 
+	if [ $? -eq 0 ]; then
+		if check_output; then
+			echo "test $i passed";
+			make --quiet clean
+		    exit 0;
+		fi
+	else
+		echo "test FAILED"
+		exit 1
+	fi
+done
+echo "test FAILED"
Index: branches/v4/softs/tests_ccvcache_v4/test_interrupt_delayslot/test.S
===================================================================
--- branches/v4/softs/tests_ccvcache_v4/test_interrupt_delayslot/test.S	(revision 371)
+++ branches/v4/softs/tests_ccvcache_v4/test_interrupt_delayslot/test.S	(revision 371)
@@ -0,0 +1,112 @@
+/*
+ * Check that we can take an interrupt from the xicu timer0
+ */
+#include <registers.h>
+#include <misc.h>
+#include <xicu.h>
+
+	.text
+	.globl  _start
+_start:
+	.set noreorder
+	la	k0, TTY_BASE
+	la	k1, EXIT_BASE
+
+	/* reset cause, make sure IV is off */
+	mtc0	zero, COP0_CAUSE
+
+	PRINT(startstr)
+
+	/* program xicu */
+	la	t0, XICU_BASE
+	/* clear pending interrupt */
+	lw	a0, XICU_PTI_ACK(0)(t0)
+	/* route PTI0 to irq 0 */
+	li	a0, 1 << 0
+	sw	a0, XICU_MSK_PTI_E(0)(t0)
+	/* init s0 */
+	li	s0, MAGIC2
+	/*
+	 * interrupt in INTERRUPT_DELAY cycles.
+	 * Without cache this takes us to the delay slot of the jump.
+	 */
+
+	li	a0, INTERRUPT_DELAY
+	//li	a0, 38
+	sw	a0, XICU_PTI_PER(0)(t0)
+	/* clear pending interrupt */
+	lw	a0, XICU_PTI_ACK(0)(t0)
+	/* reset cop0 status (keep BEV), enable interrupt 0 */
+	lui     a0, 0x0040;
+	addiu	a0, 0x0401;
+	mtc0    a0, COP0_STATUS
+
+	nop
+	nop
+	nop
+	j	end
+	li 	s0, MAGIC1
+	nop
+	/* we should not end there */
+	EXIT(1)
+
+end:
+	PRINT(endstr)
+	move	a0, s0
+	PRINTX
+	PUTCHAR('\n')
+	EXIT(0)
+
+	.globl excep
+excep:
+	.set noreorder
+	/* disable timer0 */
+	la	t0, XICU_BASE
+	sw	zero, XICU_PTI_PER(0)(t0)
+	PRINT(statusstr)
+	mfc0	a0, COP0_STATUS
+	PRINTX
+
+	PRINT(causestr)
+	mfc0	a0, COP0_CAUSE
+	PRINTX
+
+	PRINT(pcstr)
+	mfc0	a0, COP0_EXPC
+	PRINTX
+
+	PRINT(badvastr)
+	mfc0	a0, COP_0_BADVADDR
+	PRINTX
+
+	PRINT(xicustr)
+	la	t0, XICU_BASE
+	lw	a0, XICU_PRIO(0)(t0)
+	PRINTX
+
+	PUTCHAR('\n')
+	/* clear interrupt */
+	mfc0	a0, COP0_CAUSE
+	andi	t0, a0, 0xff00
+	xor	a0, a0, t0
+	mtc0	a0, COP0_CAUSE
+	eret
+	/* we should not end there */
+	EXIT(1)
+
+	.rodata:
+statusstr: .ascii "status \0"
+causestr: .ascii " cause \0"
+pcstr: .ascii " pc \0"
+badvastr: .ascii " badva \0"
+xicustr: .ascii " xicu \0"
+startstr: .ascii "start\n\0"
+endstr: .ascii "end \0"
+
+	.org EXCEP_ADDRESS - BOOT_ADDRESS
+	.globl evect
+evect:
+	j	excep
+	nop
+	.data
+myvar:	.word 0
Index: branches/v4/softs/tests_ccvcache_v4/test_interrupt_epc_modify/Makefile
===================================================================
--- branches/v4/softs/tests_ccvcache_v4/test_interrupt_epc_modify/Makefile	(revision 371)
+++ branches/v4/softs/tests_ccvcache_v4/test_interrupt_epc_modify/Makefile	(revision 371)
@@ -0,0 +1,1 @@
+include ../Makefile.inc
Index: branches/v4/softs/tests_ccvcache_v4/test_interrupt_epc_modify/run
===================================================================
--- branches/v4/softs/tests_ccvcache_v4/test_interrupt_epc_modify/run	(revision 371)
+++ branches/v4/softs/tests_ccvcache_v4/test_interrupt_epc_modify/run	(revision 371)
@@ -0,0 +1,33 @@
+#!/bin/sh 
+
+. ../common/common.sh
+
+check_output()
+{
+	egrep "^eret$" run.out > /dev/null
+	if [ $? -ne 0 ]; then
+		echo "couldn't find string 1 in output - mtty not working ?" >> run.out
+		return 1
+	fi
+	egrep "^status 0x00400103 cause 0x00000100 pc 0xBFC00038 badva 0x00000000$" run.out > /dev/null
+	if [ $? -ne 0 ]; then
+		echo "couldn't find string 2 in output - mtty not working ?" >> run.out
+		return 1
+	fi
+	return 0;
+}
+
+make --quiet || exit 1
+${SIMUL} > run.out 2>&1 
+if [ $? -eq 0 ]; then
+	if check_output; then
+		echo "test passsed";
+		make --quiet clean
+		exit 0;
+	fi
+	echo "test FAILED"
+	exit 1
+fi
+echo "test FAILED"
+exit 1
+
Index: branches/v4/softs/tests_ccvcache_v4/test_interrupt_epc_modify/test.S
===================================================================
--- branches/v4/softs/tests_ccvcache_v4/test_interrupt_epc_modify/test.S	(revision 371)
+++ branches/v4/softs/tests_ccvcache_v4/test_interrupt_epc_modify/test.S	(revision 371)
@@ -0,0 +1,85 @@
+/*
+ * Check that we can take an interrupt, and return to a different address.
+ * We use a software-triggerted interrupt.
+ */
+#include <registers.h>
+#include <misc.h>
+
+	.text
+	.globl  _start
+_start:
+	.set noreorder
+	la	k0, TTY_BASE
+	la	k1, EXIT_BASE
+
+	/* reset cop0 status (keep BEV), enbale soft interrupt 0 */
+	lui     a0, 0x0040;
+	addiu	a0, 0x0101;
+	mtc0    a0, COP0_STATUS
+
+	/* reset cause, make sure IV is off */
+	mtc0	zero, COP0_CAUSE
+
+	PRINT(startstr)
+
+	/* generate an interrupt */
+	mfc0	a0, COP0_CAUSE
+	nop
+	ori	a0, 0x0100
+	mtc0	a0, COP0_CAUSE
+	nop
+	/* we should not end there */
+	EXIT(1)
+
+exret:
+	PRINT(eretstr)
+	EXIT(0)
+
+
+	.globl excep
+excep:
+	.set noreorder
+	PRINT(statusstr)
+	mfc0	a0, COP0_STATUS
+	PRINTX
+
+	PRINT(causestr)
+	mfc0	a0, COP0_CAUSE
+	PRINTX
+
+	PRINT(pcstr)
+	mfc0	a0, COP0_EXPC
+	PRINTX
+
+	PRINT(badvastr)
+	mfc0	a0, COP_0_BADVADDR
+	PRINTX
+
+	PUTCHAR('\n')
+	/* clear interrupt */
+	mfc0	a0, COP0_CAUSE
+	xori	a0, 0x100
+	mtc0	a0, COP0_CAUSE
+	nop
+	la	a0, exret
+	mtc0	a0, COP0_EXPC
+	nop
+	eret
+	/* we should not end there */
+	EXIT(1)
+
+	.rodata:
+statusstr: .ascii "status \0"
+causestr: .ascii " cause \0"
+pcstr: .ascii " pc \0"
+badvastr: .ascii " badva \0"
+startstr: .ascii "start\n\0"
+eretstr: .ascii "eret\n\0"
+
+	.org EXCEP_ADDRESS - BOOT_ADDRESS
+	.globl evect
+evect:
+	j	excep
+	nop
+	.data
+myvar:	.word 0
Index: branches/v4/softs/tests_ccvcache_v4/test_interrupt_extended/Makefile
===================================================================
--- branches/v4/softs/tests_ccvcache_v4/test_interrupt_extended/Makefile	(revision 371)
+++ branches/v4/softs/tests_ccvcache_v4/test_interrupt_extended/Makefile	(revision 371)
@@ -0,0 +1,2 @@
+include ../Makefile.inc
+CFLAGS+= -DINTERRUPT_DELAY=${INTERRUPT_DELAY}
Index: branches/v4/softs/tests_ccvcache_v4/test_interrupt_extended/run
===================================================================
--- branches/v4/softs/tests_ccvcache_v4/test_interrupt_extended/run	(revision 371)
+++ branches/v4/softs/tests_ccvcache_v4/test_interrupt_extended/run	(revision 371)
@@ -0,0 +1,31 @@
+#!/bin/sh 
+
+check_output()
+{
+	egrep "^end 0x0000DEAE$" run.out > /dev/null
+	if [ $? -ne 0 ]; then
+		echo "couldn't find string 1 in output - mtty not working ?" >> run.out
+		return 1
+	fi
+	egrep ^status run.out
+	return 0;
+}
+echo 
+for i in 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70; do
+	echo -n "    DELAY=$i: "
+	make INTERRUPT_DELAY=$i --quiet || exit 1
+	../platform/simulation.x > run.out 2>&1 
+	if [ $? -eq 0 ]; then
+		if check_output; then
+			echo "test passsed";
+			make --quiet clean
+		else
+			echo "test FAILED"
+			exit 1
+		fi
+	else 
+		echo "test FAILED"
+		exit 1
+	fi
+done
+
Index: branches/v4/softs/tests_ccvcache_v4/test_interrupt_extended/test.S
===================================================================
--- branches/v4/softs/tests_ccvcache_v4/test_interrupt_extended/test.S	(revision 371)
+++ branches/v4/softs/tests_ccvcache_v4/test_interrupt_extended/test.S	(revision 371)
@@ -0,0 +1,137 @@
+/*
+ * Check interrupt/return with interrup occuring at various points in
+ * the software. Cache is enabled to we have on interrupt/cycle
+ */
+#include <registers.h>
+#include <misc.h>
+#include <vcache.h>
+#include <xicu.h>
+
+	.text
+	.globl  _start
+_start:
+	.set noreorder
+	la	k0, TTY_BASE
+	la	k1, EXIT_BASE
+
+	/* reset cause, make sure IV is off */
+	mtc0	zero, COP0_CAUSE
+
+	la	a0, pte1
+	srl	a0, a0, 13
+	mtc2	a0, VC_PTPR
+	nop
+	nop
+
+	li	a0, VC_TLB_EN_ITLB | VC_TLB_EN_DTLB | VC_TLB_EN_ICACHE | VC_TLB_EN_DCACHE
+	mtc2 	a0, VC_TLB_EN
+
+	PRINT(startstr)
+
+	/* program xicu */
+	la	t0, XICU_BASE
+	/* clear pending interrupt */
+	lw	a0, XICU_PTI_ACK(0)(t0)
+	/* route PTI0 to irq 0 */
+	li	a0, 1 << 0
+	sw	a0, XICU_MSK_PTI_E(0)(t0)
+	/* init s0 */
+	li	s0, MAGIC2
+	/*
+	 * interrupt in INTERRUPT_DELAY cycles.
+	 */
+	li	a0, INTERRUPT_DELAY
+	sw	a0, XICU_PTI_PER(0)(t0)
+	/* clear pending interrupt */
+	lw	a0, XICU_PTI_ACK(0)(t0)
+	/* reset cop0 status (keep BEV), enable interrupt 0 */
+	lui     a0, 0x0040;
+	addiu	a0, 0x0401;
+	mtc0    a0, COP0_STATUS
+
+	li      s0, MAGIC1
+	addiu	s0, s0, -1
+	addiu	s0, s0, -1
+	addiu	s0, s0, -1
+	addiu	s0, s0, -1
+	nop
+	j	end
+	addiu	s0, s0, 5
+	nop
+	/* we should not end there */
+	EXIT(1)
+
+end:
+	PRINT(endstr)
+	move	a0, s0
+	PRINTX
+	PUTCHAR('\n')
+	EXIT(0)
+
+	.globl excep
+excep:
+	.set noreorder
+	/* disable timer0 */
+	la	t0, XICU_BASE
+	sw	zero, XICU_PTI_PER(0)(t0)
+	PRINT(statusstr)
+	mfc0	a0, COP0_STATUS
+	PRINTX
+
+	PRINT(causestr)
+	mfc0	a0, COP0_CAUSE
+	PRINTX
+
+	PRINT(pcstr)
+	mfc0	a0, COP0_EXPC
+	PRINTX
+
+	PRINT(badvastr)
+	mfc0	a0, COP_0_BADVADDR
+	PRINTX
+
+	PRINT(xicustr)
+	la	t0, XICU_BASE
+	lw	a0, XICU_PRIO(0)(t0)
+	PRINTX
+
+	PUTCHAR('\n')
+	/* clear interrupt */
+	mfc0	a0, COP0_CAUSE
+	andi	t0, a0, 0xff00
+	xor	a0, a0, t0
+	mtc0	a0, COP0_CAUSE
+	eret
+	/* we should not end there */
+	EXIT(1)
+
+	.rodata:
+statusstr: .ascii "status \0"
+causestr: .ascii " cause \0"
+pcstr: .ascii " pc \0"
+badvastr: .ascii " badva \0"
+xicustr: .ascii " xicu \0"
+startstr: .ascii "start\n\0"
+endstr: .ascii "end \0"
+
+	.org EXCEP_ADDRESS - BOOT_ADDRESS
+	.globl evect
+evect:
+	j	excep
+	nop
+	.data
+myvar:	.word 0
+pte1:
+	.align 13
+	.word PTE1_V | PTE1_C | PTE1_W | 0x0 /* map PA 0 at VA 0 */
+	.org pte1 + (BOOT_ADDRESS >> 21) * 4
+	.word PTE1_V | PTE1_C | PTE1_X | (BOOT_ADDRESS >> 21) /* map PA 0xbfc00000 at VA 0xbfc00000 */
+	.org pte1 + (TTY_BASE >> 21) * 4
+	.word PTE1_V | PTE1_W | (TTY_BASE >> 21) /* map PA 0xd0200000 at VA 0xd0200000 */
+	.org pte1 + (XICU_BASE >> 21) * 4
+	.word PTE1_V | PTE1_W | (XICU_BASE >> 21) /* map PA 0xd2000000 at VA 0xd2000000 */
+	.org pte1 + (EXIT_BASE >> 21) * 4
+	.word PTE1_V | PTE1_W | (EXIT_BASE >> 21) /* map PA 0xe0000000 at VA 0xe0000000 */
+	.org pte1 + 8192
+	.word 0
+
Index: branches/v4/softs/tests_ccvcache_v4/test_interrupt_extended2/Makefile
===================================================================
--- branches/v4/softs/tests_ccvcache_v4/test_interrupt_extended2/Makefile	(revision 371)
+++ branches/v4/softs/tests_ccvcache_v4/test_interrupt_extended2/Makefile	(revision 371)
@@ -0,0 +1,2 @@
+include ../Makefile.inc
+CFLAGS+= -DINTERRUPT_DELAY=${INTERRUPT_DELAY}
Index: branches/v4/softs/tests_ccvcache_v4/test_interrupt_extended2/run
===================================================================
--- branches/v4/softs/tests_ccvcache_v4/test_interrupt_extended2/run	(revision 371)
+++ branches/v4/softs/tests_ccvcache_v4/test_interrupt_extended2/run	(revision 371)
@@ -0,0 +1,31 @@
+#!/bin/sh 
+
+check_output()
+{
+	egrep "^end 0x0000DEAD 0x0000BEF0$" run.out > /dev/null
+	if [ $? -ne 0 ]; then
+		echo "couldn't find string 1 in output - mtty not working ?" >> run.out
+		return 1
+	fi
+	egrep "^status 0x00400403" run.out
+	return 0;
+}
+echo 
+for i in 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99; do
+	echo -n "    DELAY=$i: "
+	make INTERRUPT_DELAY=$i --quiet || exit 1
+	../platform/simulation.x > run.out 2>&1 
+	if [ $? -eq 0 ]; then
+		if check_output; then
+			echo "test passsed";
+			make --quiet clean
+		else
+			echo "test FAILED"
+			exit 1
+		fi
+	else 
+		echo "test FAILED"
+		exit 1
+	fi
+done
+
Index: branches/v4/softs/tests_ccvcache_v4/test_interrupt_extended2/test.S
===================================================================
--- branches/v4/softs/tests_ccvcache_v4/test_interrupt_extended2/test.S	(revision 371)
+++ branches/v4/softs/tests_ccvcache_v4/test_interrupt_extended2/test.S	(revision 371)
@@ -0,0 +1,181 @@
+/*
+ * Check interrupt/return with interrup occuring at various points in
+ * the software. Cache is enabled to we have on interrupt/cycle
+ */
+#include <registers.h>
+#include <misc.h>
+#include <vcache.h>
+#include <xicu.h>
+
+	.text
+	.globl  _start
+_start:
+	.set noreorder
+	la	k0, TTY_BASE
+	la	k1, EXIT_BASE
+
+	/* reset cause, make sure IV is off */
+	mtc0	zero, COP0_CAUSE
+
+	la	a0, pte1
+	srl	a0, a0, 13
+	mtc2	a0, VC_PTPR
+	nop
+	nop
+
+	li	a0, VC_TLB_EN_ITLB | VC_TLB_EN_DTLB | VC_TLB_EN_ICACHE | VC_TLB_EN_DCACHE
+	mtc2 	a0, VC_TLB_EN
+
+	PRINT(startstr)
+
+	/* program xicu */
+	la	t0, XICU_BASE
+	/* clear pending interrupt */
+	lw	a0, XICU_PTI_ACK(0)(t0)
+	/* route PTI0 to irq 0 */
+	li	a0, 1 << 0
+	sw	a0, XICU_MSK_PTI_E(0)(t0)
+	/* init s0 */
+	li	s0, MAGIC2
+
+	/* reset cop0 status (keep BEV), enable soft interrupt 0 */
+	lui     a0, 0x0040;
+	addiu	a0, 0x0101;
+	mtc0    a0, COP0_STATUS
+#if 1
+	/* trigger soft interrupt, so that exept is in cache */
+	mfc0    a0, COP0_CAUSE
+	ori     a0, 0x0100
+	mtc0    a0, COP0_CAUSE
+	nop
+#endif
+
+	/*
+	 * interrupt in INTERRUPT_DELAY cycles.
+	 */
+	la	t0, XICU_BASE
+	li	a0, INTERRUPT_DELAY
+	sw	a0, XICU_PTI_PER(0)(t0)
+	/* clear pending interrupt */
+	lw	a0, XICU_PTI_ACK(0)(t0)
+	/* reset cop0 status (keep BEV), enable interrupt 0 */
+	lui     a0, 0x0040;
+	addiu	a0, 0x0401;
+	mtc0    a0, COP0_STATUS
+
+	li      s0, MAGIC1
+	li      s1, MAGIC2
+	addiu	s0, s0, -1
+	jal	incr
+	nop
+	addiu	s0, s0, -1
+	jal	incr
+	nop
+	addiu	s0, s0, -1
+	jal	incr
+	nop
+	addiu	s0, s0, -1
+	jal	incr
+	nop
+	j	end
+	addiu	s1, s1, 5
+	nop
+	/* we should not end there */
+	EXIT(1)
+
+	.align 6
+	nop
+incr:
+	addiu	s1, s1, -1
+	j	ra
+	addiu	s0, s0, 1
+
+	.align 6
+end:
+	PRINT(endstr)
+	move	a0, s0
+	PRINTX
+	PUTCHAR(' ')
+	move	a0, s1
+	PRINTX
+	PUTCHAR('\n')
+	EXIT(0)
+fail:
+	EXIT(4)
+
+
+	.rodata:
+statusstr: .ascii "status \0"
+causestr: .ascii " cause \0"
+pcstr: .ascii " pc \0"
+badvastr: .ascii " badva \0"
+xicustr: .ascii " xicu \0"
+startstr: .ascii "start\n\0"
+endstr: .ascii "end \0"
+
+	.org EXCEP_ADDRESS - BOOT_ADDRESS
+	.globl excep
+excep:
+	.set noreorder
+	move	s2, ra
+	mfc0	a0, COP0_CAUSE
+	andi	a0, a0, 0x0400
+	beq	a0, zero, softint
+	nop
+	/* disable timer0 */
+	la	t0, XICU_BASE
+	sw	zero, XICU_PTI_PER(0)(t0)
+
+	PRINT(statusstr)
+	mfc0	a0, COP0_STATUS
+	PRINTX
+
+	PRINT(causestr)
+	mfc0	a0, COP0_CAUSE
+	PRINTX
+
+	PRINT(pcstr)
+	mfc0	a0, COP0_EXPC
+	PRINTX
+
+	PRINT(badvastr)
+	mfc0	a0, COP_0_BADVADDR
+	PRINTX
+
+	PRINT(xicustr)
+	la	t0, XICU_BASE
+	lw	a0, XICU_PRIO(0)(t0)
+	PRINTX
+
+	PUTCHAR('\n')
+softint:
+	/* clear interrupt */
+	mfc0	a0, COP0_CAUSE
+	andi	t0, a0, 0xff00
+	xor	a0, a0, t0
+	mtc0	a0, COP0_CAUSE
+	/* fluch cache line of incr */
+	la	a0, incr
+	mtc2	a0, VC_ICACHE_INVAL
+	//mtc2	a0, VC_ITLB_INVAL
+	move	ra, s2
+	la	s2, fail
+	eret
+	/* we should not end there */
+	EXIT(3)
+	.data
+myvar:	.word 0
+pte1:
+	.align 13
+	.word PTE1_V | PTE1_C | PTE1_W | 0x0 /* map PA 0 at VA 0 */
+	.org pte1 + (BOOT_ADDRESS >> 21) * 4
+	.word PTE1_V | PTE1_C | PTE1_X | (BOOT_ADDRESS >> 21) /* map PA 0xbfc00000 at VA 0xbfc00000 */
+	.org pte1 + (TTY_BASE >> 21) * 4
+	.word PTE1_V | PTE1_W | (TTY_BASE >> 21) /* map PA 0xd0200000 at VA 0xd0200000 */
+	.org pte1 + (XICU_BASE >> 21) * 4
+	.word PTE1_V | PTE1_W | (XICU_BASE >> 21) /* map PA 0xd2000000 at VA 0xd2000000 */
+	.org pte1 + (EXIT_BASE >> 21) * 4
+	.word PTE1_V | PTE1_W | (EXIT_BASE >> 21) /* map PA 0xe0000000 at VA 0xe0000000 */
+	.org pte1 + 8192
+	.word 0
+
Index: branches/v4/softs/tests_ccvcache_v4/test_interrupt_external_mask/Makefile
===================================================================
--- branches/v4/softs/tests_ccvcache_v4/test_interrupt_external_mask/Makefile	(revision 371)
+++ branches/v4/softs/tests_ccvcache_v4/test_interrupt_external_mask/Makefile	(revision 371)
@@ -0,0 +1,1 @@
+include ../Makefile.inc
Index: branches/v4/softs/tests_ccvcache_v4/test_interrupt_external_mask/run
===================================================================
--- branches/v4/softs/tests_ccvcache_v4/test_interrupt_external_mask/run	(revision 371)
+++ branches/v4/softs/tests_ccvcache_v4/test_interrupt_external_mask/run	(revision 371)
@@ -0,0 +1,28 @@
+#!/bin/sh 
+
+. ../common/common.sh
+
+check_output()
+{
+	egrep "^status 0x0040CC03 cause 0x00000400 pc 0xBFC00088 badva 0x00000000 xicu 0x[01][0-9A-F][01][0-9A-F]0001$" run.out > /dev/null
+	if [ $? -ne 0 ]; then
+		echo "couldn't find string in output - mtty not working ?" >> run.out
+		return 1
+	fi
+	return 0;
+}
+
+make --quiet || exit 1
+${SIMUL} > run.out 2>&1 
+if [ $? -eq 0 ]; then
+	if check_output; then
+		echo "test passsed";
+		make --quiet clean
+		exit 0;
+	fi
+	echo "test FAILED"
+	exit 1
+fi
+echo "test FAILED"
+exit 1
+
Index: branches/v4/softs/tests_ccvcache_v4/test_interrupt_external_mask/test.S
===================================================================
--- branches/v4/softs/tests_ccvcache_v4/test_interrupt_external_mask/test.S	(revision 371)
+++ branches/v4/softs/tests_ccvcache_v4/test_interrupt_external_mask/test.S	(revision 371)
@@ -0,0 +1,110 @@
+/*
+ * Check that we can mask an external interrupt
+ */
+#include <registers.h>
+#include <misc.h>
+#include <xicu.h>
+
+	.text
+	.globl  _start
+_start:
+	.set noreorder
+	la	k0, TTY_BASE
+	la	k1, EXIT_BASE
+
+	/* reset cop0 status (keep BEV), enable interrupt 0 */
+	lui     a0, 0x0040;
+	ori	a0, 0xc801;
+	mtc0    a0, COP0_STATUS
+
+	/* reset cause, make sure IV is off */
+	mtc0	zero, COP0_CAUSE
+
+	PRINT(startstr)
+
+	/* program xicu */
+	la	t0, XICU_BASE
+	/* clear pending interrupt */
+	lw	a0, XICU_PTI_ACK(0)(t0)
+	/* route PTI0 to irq 0 */
+	li	a0, 1 << 0
+	sw	a0, XICU_MSK_PTI_E(0)(t0)
+	/* interrupt in 10 cycles */
+	li	a0, 10
+	sw	a0, XICU_PTI_PER(0)(t0)
+	/* interrupts still disabled at the MIPS level */
+	li	a0, MAGIC1
+	PRINTX
+	PUTCHAR('\n')
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	/* enable interrupt from timer0 */
+	mfc0	a0, COP0_STATUS
+	ori	a0, 0x0400
+	mtc0	a0, COP0_STATUS
+
+	nop
+	nop
+
+1:	j 1b
+	nop
+	/* we should not end there */
+	EXIT(1)
+
+	.globl excep
+excep:
+	.set noreorder
+	PRINT(statusstr)
+	mfc0	a0, COP0_STATUS
+	PRINTX
+
+	PRINT(causestr)
+	mfc0	a0, COP0_CAUSE
+	PRINTX
+
+	PRINT(pcstr)
+	mfc0	a0, COP0_EXPC
+	PRINTX
+
+	PRINT(badvastr)
+	mfc0	a0, COP_0_BADVADDR
+	PRINTX
+
+	PRINT(xicustr)
+	la	t0, XICU_BASE
+	lw	a0, XICU_PRIO(0)(t0)
+	PRINTX
+
+	PUTCHAR('\n')
+	/* clear interrupt */
+	mfc0	a0, COP0_CAUSE
+	andi	t0, a0, 0xff00
+	xor	a0, a0, t0
+	mtc0	a0, COP0_CAUSE
+	/* we should end there */
+	EXIT(0)
+
+	.rodata:
+statusstr: .ascii "status \0"
+causestr: .ascii " cause \0"
+pcstr: .ascii " pc \0"
+badvastr: .ascii " badva \0"
+xicustr: .ascii " xicu \0"
+startstr: .ascii "start\n\0"
+eretstr: .ascii "eret\n\0"
+
+	.org EXCEP_ADDRESS - BOOT_ADDRESS
+	.globl evect
+evect:
+	j	excep
+	nop
+	.data
+myvar:	.word 0
Index: branches/v4/softs/tests_ccvcache_v4/test_interrupt_loop_tmp/Makefile
===================================================================
--- branches/v4/softs/tests_ccvcache_v4/test_interrupt_loop_tmp/Makefile	(revision 371)
+++ branches/v4/softs/tests_ccvcache_v4/test_interrupt_loop_tmp/Makefile	(revision 371)
@@ -0,0 +1,1 @@
+include ../Makefile.inc
Index: branches/v4/softs/tests_ccvcache_v4/test_interrupt_loop_tmp/run
===================================================================
--- branches/v4/softs/tests_ccvcache_v4/test_interrupt_loop_tmp/run	(revision 371)
+++ branches/v4/softs/tests_ccvcache_v4/test_interrupt_loop_tmp/run	(revision 371)
@@ -0,0 +1,12 @@
+#!/bin/sh 
+
+make --quiet || exit 1
+../platform/simulation.x > run.out 2>&1 
+if [ $? -eq 0 ]; then
+	echo "test passsed";
+	make --quiet clean
+	exit 0;
+fi
+echo "test failed"
+exit 1
+
Index: branches/v4/softs/tests_ccvcache_v4/test_interrupt_loop_tmp/run.out
===================================================================
--- branches/v4/softs/tests_ccvcache_v4/test_interrupt_loop_tmp/run.out	(revision 371)
+++ branches/v4/softs/tests_ccvcache_v4/test_interrupt_loop_tmp/run.out	(revision 371)
@@ -0,0 +1,41356 @@
+ ____            _                  ____    _    ____ ____  
+/ ___| _   _ ___| |_ ___ _ __ ___  / ___|  / \  / ___/ ___| 
+\___ \| | | / __| __/ _ \ '_ ` _ \| |     / _ \ \___ \___ \ 
+ ___) | |_| \__ \ ||  __/ | | | | | |___ / ___ \ ___) |__) |
+|____/ \__, |___/\__\___|_| |_| |_|\____/_/   \_\____/____/ 
+       |___/                                                
+
+         Cycle Accurate System Simulator
+            ASIM/LIP6/UPMC
+            E-mail support:  Richard.Buchmann@asim.lip6.fr
+            Contributors : Richard Buchmann, Sami Taktak,
+                           Paul-Jerome Kingbo, Frédéric Pétrot,
+                           Nicolas Pouillon
+
+                           Last change : Mar 10 2008
+
+Loading at 0xbfc00000 size 4194304: .text .reginfo 
+Loading at 0 size 4194304: .data 
+mips0 executeNCycles( 1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00000 m_jump_pc: 0xbfc00004 m_ifetch_addr: 0xbfc00000
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00000 m_jump_pc: 0xbfc00004 m_ifetch_addr: 0xbfc00000
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00000 m_jump_pc: 0xbfc00004 m_ifetch_addr: 0xbfc00000
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00000 m_jump_pc: 0xbfc00004 m_ifetch_addr: 0xbfc00000
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00000 m_jump_pc: 0xbfc00004 m_ifetch_addr: 0xbfc00000
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00000 m_jump_pc: 0xbfc00004 m_ifetch_addr: 0xbfc00000
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00000 m_jump_pc: 0xbfc00004 m_ifetch_addr: 0xbfc00000
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00000 m_jump_pc: 0xbfc00004 m_ifetch_addr: 0xbfc00000
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00000 m_jump_pc: 0xbfc00004 m_ifetch_addr: 0xbfc00000
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00000 m_jump_pc: 0xbfc00004 m_ifetch_addr: 0xbfc00000
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00000 m_jump_pc: 0xbfc00004 m_ifetch_addr: 0xbfc00000
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c1ad020>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00000 NPC: 0xbfc00004 Ins: 0x3c1ad020
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 0 .erl: 1 .whole: 0x400004
+ op:  0xf (lui)
+ i rs: 0 rt: 0x1a i: 0xd020
+ r rs: 0 rt: 26 rd: 26 sh: 0 func: 0x20
+ V rs: 0 rt: 0
+  0: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 00000000 17: 00000000 18: 00000000 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: 00000000 27: 00000000 28: 00000000 29: 00000000 30: 00000000 31: 00000000
+mips0 m_next_pc: 0xbfc00004 m_jump_pc: 0xbfc00008 m_ifetch_addr: 0xbfc00004
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0x3c1ad020>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00004 m_jump_pc: 0xbfc00008 m_ifetch_addr: 0xbfc00004
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00004 m_jump_pc: 0xbfc00008 m_ifetch_addr: 0xbfc00004
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00004 m_jump_pc: 0xbfc00008 m_ifetch_addr: 0xbfc00004
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00004 m_jump_pc: 0xbfc00008 m_ifetch_addr: 0xbfc00004
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00004 m_jump_pc: 0xbfc00008 m_ifetch_addr: 0xbfc00004
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00004 m_jump_pc: 0xbfc00008 m_ifetch_addr: 0xbfc00004
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00004 m_jump_pc: 0xbfc00008 m_ifetch_addr: 0xbfc00004
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00004 m_jump_pc: 0xbfc00008 m_ifetch_addr: 0xbfc00004
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00004 m_jump_pc: 0xbfc00008 m_ifetch_addr: 0xbfc00004
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00004 m_jump_pc: 0xbfc00008 m_ifetch_addr: 0xbfc00004
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00004 m_jump_pc: 0xbfc00008 m_ifetch_addr: 0xbfc00004
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c1be000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00004 NPC: 0xbfc00008 Ins: 0x3c1be000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 0 .erl: 1 .whole: 0x400004
+ op:  0xf (lui)
+ i rs: 0 rt: 0x1b i: 0xe000
+ r rs: 0 rt: 27 rd: 28 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 00000000 17: 00000000 18: 00000000 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: 00000000 28: 00000000 29: 00000000 30: 00000000 31: 00000000
+mips0 m_next_pc: 0xbfc00008 m_jump_pc: 0xbfc0000c m_ifetch_addr: 0xbfc00008
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0x3c1be000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00008 m_jump_pc: 0xbfc0000c m_ifetch_addr: 0xbfc00008
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00008 m_jump_pc: 0xbfc0000c m_ifetch_addr: 0xbfc00008
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00008 m_jump_pc: 0xbfc0000c m_ifetch_addr: 0xbfc00008
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00008 m_jump_pc: 0xbfc0000c m_ifetch_addr: 0xbfc00008
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00008 m_jump_pc: 0xbfc0000c m_ifetch_addr: 0xbfc00008
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00008 m_jump_pc: 0xbfc0000c m_ifetch_addr: 0xbfc00008
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00008 m_jump_pc: 0xbfc0000c m_ifetch_addr: 0xbfc00008
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00008 m_jump_pc: 0xbfc0000c m_ifetch_addr: 0xbfc00008
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00008 m_jump_pc: 0xbfc0000c m_ifetch_addr: 0xbfc00008
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00008 m_jump_pc: 0xbfc0000c m_ifetch_addr: 0xbfc00008
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00008 m_jump_pc: 0xbfc0000c m_ifetch_addr: 0xbfc00008
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x40806800>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00008 NPC: 0xbfc0000c Ins: 0x40806800
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 0 .erl: 1 .whole: 0x400004
+ op:  0x10 (cop0)
+ i rs: 0x4 rt: 0 i: 0x6800
+ r rs: 4 rt: 0 rd: 13 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 00000000 17: 00000000 18: 00000000 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: 00000000
+mips0 m_next_pc: 0xbfc0000c m_jump_pc: 0xbfc00010 m_ifetch_addr: 0xbfc0000c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0x40806800>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc0000c m_jump_pc: 0xbfc00010 m_ifetch_addr: 0xbfc0000c
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc0000c m_jump_pc: 0xbfc00010 m_ifetch_addr: 0xbfc0000c
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc0000c m_jump_pc: 0xbfc00010 m_ifetch_addr: 0xbfc0000c
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc0000c m_jump_pc: 0xbfc00010 m_ifetch_addr: 0xbfc0000c
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc0000c m_jump_pc: 0xbfc00010 m_ifetch_addr: 0xbfc0000c
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc0000c m_jump_pc: 0xbfc00010 m_ifetch_addr: 0xbfc0000c
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc0000c m_jump_pc: 0xbfc00010 m_ifetch_addr: 0xbfc0000c
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc0000c m_jump_pc: 0xbfc00010 m_ifetch_addr: 0xbfc0000c
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc0000c m_jump_pc: 0xbfc00010 m_ifetch_addr: 0xbfc0000c
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc0000c m_jump_pc: 0xbfc00010 m_ifetch_addr: 0xbfc0000c
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc0000c m_jump_pc: 0xbfc00010 m_ifetch_addr: 0xbfc0000c
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c040000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0000c NPC: 0xbfc00010 Ins: 0x3c040000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 0 .erl: 1 .whole: 0x400004
+ op:  0xf (lui)
+ i rs: 0 rt: 0x4 i: 0
+ r rs: 0 rt: 4 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 00000000 17: 00000000 18: 00000000 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: 00000000
+mips0 m_next_pc: 0xbfc00010 m_jump_pc: 0xbfc00014 m_ifetch_addr: 0xbfc00010
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0x3c040000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00010 m_jump_pc: 0xbfc00014 m_ifetch_addr: 0xbfc00010
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00010 m_jump_pc: 0xbfc00014 m_ifetch_addr: 0xbfc00010
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00010 m_jump_pc: 0xbfc00014 m_ifetch_addr: 0xbfc00010
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00010 m_jump_pc: 0xbfc00014 m_ifetch_addr: 0xbfc00010
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00010 m_jump_pc: 0xbfc00014 m_ifetch_addr: 0xbfc00010
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00010 m_jump_pc: 0xbfc00014 m_ifetch_addr: 0xbfc00010
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00010 m_jump_pc: 0xbfc00014 m_ifetch_addr: 0xbfc00010
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00010 m_jump_pc: 0xbfc00014 m_ifetch_addr: 0xbfc00010
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00010 m_jump_pc: 0xbfc00014 m_ifetch_addr: 0xbfc00010
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00010 m_jump_pc: 0xbfc00014 m_ifetch_addr: 0xbfc00010
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00010 m_jump_pc: 0xbfc00014 m_ifetch_addr: 0xbfc00010
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x24842000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00010 NPC: 0xbfc00014 Ins: 0x24842000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 0 .erl: 1 .whole: 0x400004
+ op:  0x9 (addiu)
+ i rs: 0x4 rt: 0x4 i: 0x2000
+ r rs: 4 rt: 4 rd: 4 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 00000000 17: 00000000 18: 00000000 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: 00000000
+mips0 m_next_pc: 0xbfc00014 m_jump_pc: 0xbfc00018 m_ifetch_addr: 0xbfc00014
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0x24842000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00014 m_jump_pc: 0xbfc00018 m_ifetch_addr: 0xbfc00014
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00014 m_jump_pc: 0xbfc00018 m_ifetch_addr: 0xbfc00014
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00014 m_jump_pc: 0xbfc00018 m_ifetch_addr: 0xbfc00014
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00014 m_jump_pc: 0xbfc00018 m_ifetch_addr: 0xbfc00014
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00014 m_jump_pc: 0xbfc00018 m_ifetch_addr: 0xbfc00014
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00014 m_jump_pc: 0xbfc00018 m_ifetch_addr: 0xbfc00014
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00014 m_jump_pc: 0xbfc00018 m_ifetch_addr: 0xbfc00014
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00014 m_jump_pc: 0xbfc00018 m_ifetch_addr: 0xbfc00014
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00014 m_jump_pc: 0xbfc00018 m_ifetch_addr: 0xbfc00014
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00014 m_jump_pc: 0xbfc00018 m_ifetch_addr: 0xbfc00014
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00014 m_jump_pc: 0xbfc00018 m_ifetch_addr: 0xbfc00014
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x42342>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00014 NPC: 0xbfc00018 Ins: 0x42342
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 0 .erl: 1 .whole: 0x400004
+ op:  0 (special)
+ i rs: 0 rt: 0x4 i: 0x2342
+ r rs: 0 rt: 4 rd: 4 sh: 13 func: 0x2
+ V rs: 0 rt: 0x2000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00002000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 00000000 17: 00000000 18: 00000000 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: 00000000
+mips0 m_next_pc: 0xbfc00018 m_jump_pc: 0xbfc0001c m_ifetch_addr: 0xbfc00018
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0x42342>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00018 m_jump_pc: 0xbfc0001c m_ifetch_addr: 0xbfc00018
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00018 m_jump_pc: 0xbfc0001c m_ifetch_addr: 0xbfc00018
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00018 m_jump_pc: 0xbfc0001c m_ifetch_addr: 0xbfc00018
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00018 m_jump_pc: 0xbfc0001c m_ifetch_addr: 0xbfc00018
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00018 m_jump_pc: 0xbfc0001c m_ifetch_addr: 0xbfc00018
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00018 m_jump_pc: 0xbfc0001c m_ifetch_addr: 0xbfc00018
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00018 m_jump_pc: 0xbfc0001c m_ifetch_addr: 0xbfc00018
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00018 m_jump_pc: 0xbfc0001c m_ifetch_addr: 0xbfc00018
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00018 m_jump_pc: 0xbfc0001c m_ifetch_addr: 0xbfc00018
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00018 m_jump_pc: 0xbfc0001c m_ifetch_addr: 0xbfc00018
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00018 m_jump_pc: 0xbfc0001c m_ifetch_addr: 0xbfc00018
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x48840000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00018 NPC: 0xbfc0001c Ins: 0x48840000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 0 .erl: 1 .whole: 0x400004
+ op:  0x12 (cop2)
+ i rs: 0x4 rt: 0x4 i: 0
+ r rs: 4 rt: 4 rd: 0 sh: 0 func: 0
+ V rs: 0x1 rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000001 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 00000000 17: 00000000 18: 00000000 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: 00000000
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type XTN_WRITE (XTN_PTPR) wdata 0x1 be 0xf> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc0001c m_jump_pc: 0xbfc00020 m_ifetch_addr: 0xbfc0001c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0x48840000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc0001c m_jump_pc: 0xbfc00020 m_ifetch_addr: 0xbfc0001c
+mips0 early_end: ireq_ok=0 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc0001c m_jump_pc: 0xbfc00020 m_ifetch_addr: 0xbfc0001c
+mips0 early_end: ireq_ok=0 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc0001c m_jump_pc: 0xbfc00020 m_ifetch_addr: 0xbfc0001c
+mips0 early_end: ireq_ok=0 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc0001c m_jump_pc: 0xbfc00020 m_ifetch_addr: 0xbfc0001c
+mips0 early_end: ireq_ok=0 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc0001c m_jump_pc: 0xbfc00020 m_ifetch_addr: 0xbfc0001c
+mips0 early_end: ireq_ok=0 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc0001c m_jump_pc: 0xbfc00020 m_ifetch_addr: 0xbfc0001c
+mips0 early_end: ireq_ok=0 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc0001c m_jump_pc: 0xbfc00020 m_ifetch_addr: 0xbfc0001c
+mips0 early_end: ireq_ok=0 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc0001c m_jump_pc: 0xbfc00020 m_ifetch_addr: 0xbfc0001c
+mips0 early_end: ireq_ok=0 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc0001c m_jump_pc: 0xbfc00020 m_ifetch_addr: 0xbfc0001c
+mips0 early_end: ireq_ok=0 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc0001c m_jump_pc: 0xbfc00020 m_ifetch_addr: 0xbfc0001c
+mips0 early_end: ireq_ok=0 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc0001c m_jump_pc: 0xbfc00020 m_ifetch_addr: 0xbfc0001c
+mips0 early_end: ireq_ok=0 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc0001c m_jump_pc: 0xbfc00020 m_ifetch_addr: 0xbfc0001c
+mips0 early_end: ireq_ok=0 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc0001c m_jump_pc: 0xbfc00020 m_ifetch_addr: 0xbfc0001c
+mips0 early_end: ireq_ok=0 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc0001c NPC: 0xbfc00020 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 0 .erl: 1 .whole: 0x400004
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000001 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 00000000 17: 00000000 18: 00000000 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: 00000000
+mips0 m_next_pc: 0xbfc00020 m_jump_pc: 0xbfc00024 m_ifetch_addr: 0xbfc00020
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00020 m_jump_pc: 0xbfc00024 m_ifetch_addr: 0xbfc00020
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00020 m_jump_pc: 0xbfc00024 m_ifetch_addr: 0xbfc00020
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00020 m_jump_pc: 0xbfc00024 m_ifetch_addr: 0xbfc00020
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00020 m_jump_pc: 0xbfc00024 m_ifetch_addr: 0xbfc00020
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00020 m_jump_pc: 0xbfc00024 m_ifetch_addr: 0xbfc00020
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00020 m_jump_pc: 0xbfc00024 m_ifetch_addr: 0xbfc00020
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00020 m_jump_pc: 0xbfc00024 m_ifetch_addr: 0xbfc00020
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00020 m_jump_pc: 0xbfc00024 m_ifetch_addr: 0xbfc00020
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00020 m_jump_pc: 0xbfc00024 m_ifetch_addr: 0xbfc00020
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00020 m_jump_pc: 0xbfc00024 m_ifetch_addr: 0xbfc00020
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00020 m_jump_pc: 0xbfc00024 m_ifetch_addr: 0xbfc00020
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2404000f>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00020 NPC: 0xbfc00024 Ins: 0x2404000f
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 0 .erl: 1 .whole: 0x400004
+ op:  0x9 (addiu)
+ i rs: 0 rt: 0x4 i: 0xf
+ r rs: 0 rt: 4 rd: 0 sh: 0 func: 0xf
+ V rs: 0 rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000001 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 00000000 17: 00000000 18: 00000000 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: 00000000
+mips0 m_next_pc: 0xbfc00024 m_jump_pc: 0xbfc00028 m_ifetch_addr: 0xbfc00024
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0x2404000f>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00024 m_jump_pc: 0xbfc00028 m_ifetch_addr: 0xbfc00024
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00024 m_jump_pc: 0xbfc00028 m_ifetch_addr: 0xbfc00024
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00024 m_jump_pc: 0xbfc00028 m_ifetch_addr: 0xbfc00024
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00024 m_jump_pc: 0xbfc00028 m_ifetch_addr: 0xbfc00024
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00024 m_jump_pc: 0xbfc00028 m_ifetch_addr: 0xbfc00024
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00024 m_jump_pc: 0xbfc00028 m_ifetch_addr: 0xbfc00024
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00024 m_jump_pc: 0xbfc00028 m_ifetch_addr: 0xbfc00024
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00024 m_jump_pc: 0xbfc00028 m_ifetch_addr: 0xbfc00024
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00024 m_jump_pc: 0xbfc00028 m_ifetch_addr: 0xbfc00024
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00024 m_jump_pc: 0xbfc00028 m_ifetch_addr: 0xbfc00024
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00024 m_jump_pc: 0xbfc00028 m_ifetch_addr: 0xbfc00024
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x48840800>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00024 NPC: 0xbfc00028 Ins: 0x48840800
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 0 .erl: 1 .whole: 0x400004
+ op:  0x12 (cop2)
+ i rs: 0x4 rt: 0x4 i: 0x800
+ r rs: 4 rt: 4 rd: 1 sh: 0 func: 0
+ V rs: 0xf rt: 0xf
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 0000000f 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 00000000 17: 00000000 18: 00000000 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: 00000000
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type XTN_WRITE (XTN_TLB_MODE) wdata 0xf be 0xf> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0x48840800>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00028 m_jump_pc: 0xbfc0002c m_ifetch_addr: 0xbfc00028
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c04bfc0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00028 NPC: 0xbfc0002c Ins: 0x3c04bfc0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 0 .erl: 1 .whole: 0x400004
+ op:  0xf (lui)
+ i rs: 0 rt: 0x4 i: 0xbfc0
+ r rs: 0 rt: 4 rd: 23 sh: 31 func: 0
+ V rs: 0 rt: 0xf
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 0000000f 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 00000000 17: 00000000 18: 00000000 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: 00000000
+mips0 m_next_pc: 0xbfc0002c m_jump_pc: 0xbfc00030 m_ifetch_addr: 0xbfc0002c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x24840248>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0002c NPC: 0xbfc00030 Ins: 0x24840248
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 0 .erl: 1 .whole: 0x400004
+ op:  0x9 (addiu)
+ i rs: 0x4 rt: 0x4 i: 0x248
+ r rs: 4 rt: 4 rd: 0 sh: 9 func: 0x8
+ V rs: 0xbfc00000 rt: 0xbfc00000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 00000000 17: 00000000 18: 00000000 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: 00000000
+mips0 m_next_pc: 0xbfc00030 m_jump_pc: 0xbfc00034 m_ifetch_addr: 0xbfc00030
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xff000f0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00030 NPC: 0xbfc00034 Ins: 0xff000f0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 0 .erl: 1 .whole: 0x400004
+ op:  0x3 (jal)
+ i rs: 0x1f rt: 0x10 i: 0xf0
+ r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x30
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00248 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 00000000 17: 00000000 18: 00000000 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: 00000000
+mips0 m_next_pc: 0xbfc00034 m_jump_pc: 0xbfc003c0 m_ifetch_addr: 0xbfc00034
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00034 NPC: 0xbfc003c0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 0 .erl: 1 .whole: 0x400004
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00248 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 00000000 17: 00000000 18: 00000000 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00038
+mips0 m_next_pc: 0xbfc003c0 m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003c0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c0 m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003c0
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c0 m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003c0
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c0 m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003c0
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c0 m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003c0
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c0 m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003c0
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c0 m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003c0
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c0 m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003c0
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c0 m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003c0
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c0 m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003c0
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c0 m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003c0
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c0 m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003c0
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c0 m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003c0
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c0 m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003c0
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c0 m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003c0
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c0 m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003c0
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c0 m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003c0
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c0 m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003c0
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c0 m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003c0
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c0 m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003c0
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c0 m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003c0
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c0 m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003c0
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c0 m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003c0
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c0 m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003c0
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c0 m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003c0
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c0 m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003c0
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c0 m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003c0
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c0 m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003c0
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x804021>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c0 NPC: 0xbfc003c4 Ins: 0x804021
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 0 .erl: 1 .whole: 0x400004
+ op:  0 (special)
+ i rs: 0x4 rt: 0 i: 0x4021
+ r rs: 4 rt: 0 rd: 8 sh: 0 func: 0x21
+ V rs: 0xbfc00248 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00248 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 00000000 17: 00000000 18: 00000000 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00038
+mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x81090000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 0 .erl: 1 .whole: 0x400004
+ op:  0x20 (lb)
+ i rs: 0x8 rt: 0x9 i: 0
+ r rs: 8 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xbfc00248 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00248 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00248 09: 00000000 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 00000000 17: 00000000 18: 00000000 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00038
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_READ @ 0xbfc00248 wdata 0 be 0x1> off: 0 sign_ext: 0x1 dest: gp+0x9
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp valid no error rdata 0x72617473>, 0)
+mips0 setData: <DataRsp valid no error rdata 0x72617473> off: 0 sign_ext: 0x1 dest: r_gp+0x9
+mips0 setData: <DataRsp valid no error rdata 0x72617473> off: 0 count: 0x1 le: 0 old: 0 from_mem: 0x72617473 mask: 0xffffffff new_data: 0x73
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 0 .erl: 1 .whole: 0x400004
+ op:  0x4 (beq)
+ i rs: 0x9 rt: 0 i: 0x5
+ r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5
+ V rs: 0x73 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00248 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00248 09: 00000073 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 00000000 17: 00000000 18: 00000000 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00038
+mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 0 .erl: 1 .whole: 0x400004
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00248 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00248 09: 00000073 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 00000000 17: 00000000 18: 00000000 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00038
+mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa3490000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 0 .erl: 1 .whole: 0x400004
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0x9 i: 0
+ r rs: 26 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x73
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00248 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00248 09: 00000073 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 00000000 17: 00000000 18: 00000000 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00038
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x73 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 0 .erl: 1 .whole: 0x400004
+ op:  0x9 (addiu)
+ i rs: 0x8 rt: 0x8 i: 0x1
+ r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1
+ V rs: 0xbfc00248 rt: 0xbfc00248
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00248 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00248 09: 00000073 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 00000000 17: 00000000 18: 00000000 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00038
+mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf000f1>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 0 .erl: 1 .whole: 0x400004
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0xf1
+ r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31
+ V rs: 0xbfc00038 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00248 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00249 09: 00000073 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 00000000 17: 00000000 18: 00000000 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00038
+mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 0 .erl: 1 .whole: 0x400004
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00248 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00249 09: 00000073 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 00000000 17: 00000000 18: 00000000 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00038
+mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x81090000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 0 .erl: 1 .whole: 0x400004
+ op:  0x20 (lb)
+ i rs: 0x8 rt: 0x9 i: 0
+ r rs: 8 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xbfc00249 rt: 0x73
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00248 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00249 09: 00000073 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 00000000 17: 00000000 18: 00000000 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00038
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_READ @ 0xbfc00248 wdata 0 be 0x2> off: 0x1 sign_ext: 0x1 dest: gp+0x9
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp valid no error rdata 0x72617473>, 0)
+mips0 setData: <DataRsp valid no error rdata 0x72617473> off: 0 sign_ext: 0x1 dest: r_gp+0x9
+mips0 setData: <DataRsp valid no error rdata 0x72617473> off: 0 count: 0x1 le: 0x1 old: 0x73 from_mem: 0x72617473 mask: 0xffffffff new_data: 0x74
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1
+smips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 0 .erl: 1 .whole: 0x400004
+ op:  0x4 (beq)
+ i rs: 0x9 rt: 0 i: 0x5
+ r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5
+ V rs: 0x74 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00248 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00249 09: 00000074 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 00000000 17: 00000000 18: 00000000 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00038
+mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 0 .erl: 1 .whole: 0x400004
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00248 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00249 09: 00000074 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 00000000 17: 00000000 18: 00000000 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00038
+mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa3490000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 0 .erl: 1 .whole: 0x400004
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0x9 i: 0
+ r rs: 26 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x74
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00248 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00249 09: 00000074 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 00000000 17: 00000000 18: 00000000 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00038
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x74 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 0 .erl: 1 .whole: 0x400004
+ op:  0x9 (addiu)
+ i rs: 0x8 rt: 0x8 i: 0x1
+ r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1
+ V rs: 0xbfc00249 rt: 0xbfc00249
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00248 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00249 09: 00000074 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 00000000 17: 00000000 18: 00000000 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00038
+mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf000f1>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 0 .erl: 1 .whole: 0x400004
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0xf1
+ r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31
+ V rs: 0xbfc00038 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00248 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0024a 09: 00000074 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 00000000 17: 00000000 18: 00000000 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00038
+mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 0 .erl: 1 .whole: 0x400004
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00248 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0024a 09: 00000074 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 00000000 17: 00000000 18: 00000000 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00038
+mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x81090000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 0 .erl: 1 .whole: 0x400004
+ op:  0x20 (lb)
+ i rs: 0x8 rt: 0x9 i: 0
+ r rs: 8 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xbfc0024a rt: 0x74
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00248 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0024a 09: 00000074 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 00000000 17: 00000000 18: 00000000 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00038
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_READ @ 0xbfc00248 wdata 0 be 0x4> off: 0x2 sign_ext: 0x1 dest: gp+0x9
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp valid no error rdata 0x72617473>, 0)
+mips0 setData: <DataRsp valid no error rdata 0x72617473> off: 0 sign_ext: 0x1 dest: r_gp+0x9
+mips0 setData: <DataRsp valid no error rdata 0x72617473> off: 0 count: 0x1 le: 0x2 old: 0x74 from_mem: 0x72617473 mask: 0xffffffff new_data: 0x61
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 0 .erl: 1 .whole: 0x400004
+ op:  0x4 (beq)
+ i rs: 0x9 rt: 0 i: 0x5
+ r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5
+ V rs: 0x61 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00248 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0024a 09: 00000061 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 00000000 17: 00000000 18: 00000000 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00038
+mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+tmips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 0 .erl: 1 .whole: 0x400004
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00248 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0024a 09: 00000061 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 00000000 17: 00000000 18: 00000000 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00038
+mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa3490000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 0 .erl: 1 .whole: 0x400004
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0x9 i: 0
+ r rs: 26 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x61
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00248 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0024a 09: 00000061 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 00000000 17: 00000000 18: 00000000 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00038
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x61 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 0 .erl: 1 .whole: 0x400004
+ op:  0x9 (addiu)
+ i rs: 0x8 rt: 0x8 i: 0x1
+ r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1
+ V rs: 0xbfc0024a rt: 0xbfc0024a
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00248 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0024a 09: 00000061 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 00000000 17: 00000000 18: 00000000 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00038
+mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf000f1>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 0 .erl: 1 .whole: 0x400004
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0xf1
+ r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31
+ V rs: 0xbfc00038 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00248 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0024b 09: 00000061 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 00000000 17: 00000000 18: 00000000 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00038
+mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 0 .erl: 1 .whole: 0x400004
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00248 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0024b 09: 00000061 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 00000000 17: 00000000 18: 00000000 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00038
+mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x81090000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 0 .erl: 1 .whole: 0x400004
+ op:  0x20 (lb)
+ i rs: 0x8 rt: 0x9 i: 0
+ r rs: 8 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xbfc0024b rt: 0x61
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00248 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0024b 09: 00000061 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 00000000 17: 00000000 18: 00000000 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00038
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_READ @ 0xbfc00248 wdata 0 be 0x8> off: 0x3 sign_ext: 0x1 dest: gp+0x9
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp valid no error rdata 0x72617473>, 0)
+mips0 setData: <DataRsp valid no error rdata 0x72617473> off: 0 sign_ext: 0x1 dest: r_gp+0x9
+mips0 setData: <DataRsp valid no error rdata 0x72617473> off: 0 count: 0x1 le: 0x3 old: 0x61 from_mem: 0x72617473 mask: 0xffffffff new_data: 0x72
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 0 .erl: 1 .whole: 0x400004
+ op:  0x4 (beq)
+ i rs: 0x9 rt: 0 i: 0x5
+ r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5
+ V rs: 0x72 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00248 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0024b 09: 00000072 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 00000000 17: 00000000 18: 00000000 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00038
+mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 0 .erl: 1 .whole: 0x400004
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00248 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0024b 09: 00000072 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 00000000 17: 00000000 18: 00000000 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00038
+mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+amips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa3490000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 0 .erl: 1 .whole: 0x400004
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0x9 i: 0
+ r rs: 26 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x72
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00248 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0024b 09: 00000072 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 00000000 17: 00000000 18: 00000000 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00038
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x72 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 0 .erl: 1 .whole: 0x400004
+ op:  0x9 (addiu)
+ i rs: 0x8 rt: 0x8 i: 0x1
+ r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1
+ V rs: 0xbfc0024b rt: 0xbfc0024b
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00248 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0024b 09: 00000072 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 00000000 17: 00000000 18: 00000000 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00038
+mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf000f1>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 0 .erl: 1 .whole: 0x400004
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0xf1
+ r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31
+ V rs: 0xbfc00038 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00248 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0024c 09: 00000072 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 00000000 17: 00000000 18: 00000000 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00038
+mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 0 .erl: 1 .whole: 0x400004
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00248 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0024c 09: 00000072 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 00000000 17: 00000000 18: 00000000 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00038
+mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x81090000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 0 .erl: 1 .whole: 0x400004
+ op:  0x20 (lb)
+ i rs: 0x8 rt: 0x9 i: 0
+ r rs: 8 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xbfc0024c rt: 0x72
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00248 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0024c 09: 00000072 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 00000000 17: 00000000 18: 00000000 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00038
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_READ @ 0xbfc0024c wdata 0 be 0x1> off: 0 sign_ext: 0x1 dest: gp+0x9
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp valid no error rdata 0x20000a74>, 0)
+mips0 setData: <DataRsp valid no error rdata 0x20000a74> off: 0 sign_ext: 0x1 dest: r_gp+0x9
+mips0 setData: <DataRsp valid no error rdata 0x20000a74> off: 0 count: 0x1 le: 0 old: 0x72 from_mem: 0x20000a74 mask: 0xffffffff new_data: 0x74
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 0 .erl: 1 .whole: 0x400004
+ op:  0x4 (beq)
+ i rs: 0x9 rt: 0 i: 0x5
+ r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5
+ V rs: 0x74 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00248 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0024c 09: 00000074 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 00000000 17: 00000000 18: 00000000 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00038
+mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 0 .erl: 1 .whole: 0x400004
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00248 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0024c 09: 00000074 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 00000000 17: 00000000 18: 00000000 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00038
+mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa3490000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 0 .erl: 1 .whole: 0x400004
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0x9 i: 0
+ r rs: 26 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x74
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00248 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0024c 09: 00000074 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 00000000 17: 00000000 18: 00000000 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00038
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x74 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+rmips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 0 .erl: 1 .whole: 0x400004
+ op:  0x9 (addiu)
+ i rs: 0x8 rt: 0x8 i: 0x1
+ r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1
+ V rs: 0xbfc0024c rt: 0xbfc0024c
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00248 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0024c 09: 00000074 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 00000000 17: 00000000 18: 00000000 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00038
+mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf000f1>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 0 .erl: 1 .whole: 0x400004
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0xf1
+ r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31
+ V rs: 0xbfc00038 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00248 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0024d 09: 00000074 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 00000000 17: 00000000 18: 00000000 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00038
+mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 0 .erl: 1 .whole: 0x400004
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00248 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0024d 09: 00000074 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 00000000 17: 00000000 18: 00000000 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00038
+mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x81090000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 0 .erl: 1 .whole: 0x400004
+ op:  0x20 (lb)
+ i rs: 0x8 rt: 0x9 i: 0
+ r rs: 8 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xbfc0024d rt: 0x74
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00248 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0024d 09: 00000074 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 00000000 17: 00000000 18: 00000000 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00038
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_READ @ 0xbfc0024c wdata 0 be 0x2> off: 0x1 sign_ext: 0x1 dest: gp+0x9
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp valid no error rdata 0x20000a74>, 0)
+mips0 setData: <DataRsp valid no error rdata 0x20000a74> off: 0 sign_ext: 0x1 dest: r_gp+0x9
+mips0 setData: <DataRsp valid no error rdata 0x20000a74> off: 0 count: 0x1 le: 0x1 old: 0x74 from_mem: 0x20000a74 mask: 0xffffffff new_data: 0xa
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 0 .erl: 1 .whole: 0x400004
+ op:  0x4 (beq)
+ i rs: 0x9 rt: 0 i: 0x5
+ r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5
+ V rs: 0xa rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00248 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0024d 09: 0000000a 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 00000000 17: 00000000 18: 00000000 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00038
+mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 0 .erl: 1 .whole: 0x400004
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00248 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0024d 09: 0000000a 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 00000000 17: 00000000 18: 00000000 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00038
+mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa3490000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 0 .erl: 1 .whole: 0x400004
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0x9 i: 0
+ r rs: 26 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0xa
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00248 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0024d 09: 0000000a 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 00000000 17: 00000000 18: 00000000 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00038
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0xa be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+tmips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 0 .erl: 1 .whole: 0x400004
+ op:  0x9 (addiu)
+ i rs: 0x8 rt: 0x8 i: 0x1
+ r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1
+ V rs: 0xbfc0024d rt: 0xbfc0024d
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00248 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0024d 09: 0000000a 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 00000000 17: 00000000 18: 00000000 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00038
+mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf000f1>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 0 .erl: 1 .whole: 0x400004
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0xf1
+ r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31
+ V rs: 0xbfc00038 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00248 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0024e 09: 0000000a 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 00000000 17: 00000000 18: 00000000 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00038
+mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 0 .erl: 1 .whole: 0x400004
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00248 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0024e 09: 0000000a 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 00000000 17: 00000000 18: 00000000 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00038
+mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x81090000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 0 .erl: 1 .whole: 0x400004
+ op:  0x20 (lb)
+ i rs: 0x8 rt: 0x9 i: 0
+ r rs: 8 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xbfc0024e rt: 0xa
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00248 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0024e 09: 0000000a 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 00000000 17: 00000000 18: 00000000 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00038
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_READ @ 0xbfc0024c wdata 0 be 0x4> off: 0x2 sign_ext: 0x1 dest: gp+0x9
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp valid no error rdata 0x20000a74>, 0)
+mips0 setData: <DataRsp valid no error rdata 0x20000a74> off: 0 sign_ext: 0x1 dest: r_gp+0x9
+mips0 setData: <DataRsp valid no error rdata 0x20000a74> off: 0 count: 0x1 le: 0x2 old: 0xa from_mem: 0x20000a74 mask: 0xffffffff new_data: 0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 0 .erl: 1 .whole: 0x400004
+ op:  0x4 (beq)
+ i rs: 0x9 rt: 0 i: 0x5
+ r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00248 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0024e 09: 00000000 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 00000000 17: 00000000 18: 00000000 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00038
+mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003e0 m_ifetch_addr: 0xbfc003cc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003cc NPC: 0xbfc003e0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 0 .erl: 1 .whole: 0x400004
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00248 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0024e 09: 00000000 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 00000000 17: 00000000 18: 00000000 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00038
+mips0 m_next_pc: 0xbfc003e0 m_jump_pc: 0xbfc003e4 m_ifetch_addr: 0xbfc003e0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3e00008>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003e0 NPC: 0xbfc003e4 Ins: 0x3e00008
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 0 .erl: 1 .whole: 0x400004
+ op:  0 (special)
+ i rs: 0x1f rt: 0 i: 0x8
+ r rs: 31 rt: 0 rd: 0 sh: 0 func: 0x8
+ V rs: 0xbfc00038 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00248 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0024e 09: 00000000 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 00000000 17: 00000000 18: 00000000 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00038
+mips0 m_next_pc: 0xbfc003e4 m_jump_pc: 0xbfc00038 m_ifetch_addr: 0xbfc003e4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003e4 NPC: 0xbfc00038 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 0 .erl: 1 .whole: 0x400004
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00248 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0024e 09: 00000000 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 00000000 17: 00000000 18: 00000000 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00038
+mips0 m_next_pc: 0xbfc00038 m_jump_pc: 0xbfc0003c m_ifetch_addr: 0xbfc00038
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c08d820>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00038 NPC: 0xbfc0003c Ins: 0x3c08d820
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 0 .erl: 1 .whole: 0x400004
+ op:  0xf (lui)
+ i rs: 0 rt: 0x8 i: 0xd820
+ r rs: 0 rt: 8 rd: 27 sh: 0 func: 0x20
+ V rs: 0 rt: 0xbfc0024e
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00248 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0024e 09: 00000000 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 00000000 17: 00000000 18: 00000000 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00038
+mips0 m_next_pc: 0xbfc0003c m_jump_pc: 0xbfc00040 m_ifetch_addr: 0xbfc0003c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x8d040180>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0003c NPC: 0xbfc00040 Ins: 0x8d040180
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 0 .erl: 1 .whole: 0x400004
+ op:  0x23 (lw)
+ i rs: 0x8 rt: 0x4 i: 0x180
+ r rs: 8 rt: 4 rd: 0 sh: 6 func: 0
+ V rs: 0xd8200000 rt: 0xbfc00248
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00248 05: 00000000 06: 00000000 07: 00000000
+ 08: d8200000 09: 00000000 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 00000000 17: 00000000 18: 00000000 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00038
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_READ @ 0xd8200180 wdata 0 be 0xf> off: 0 sign_ext: 0 dest: gp+0x4
+mips0 m_next_pc: 0xbfc00040 m_jump_pc: 0xbfc00044 m_ifetch_addr: 0xbfc00040
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00040 m_jump_pc: 0xbfc00044 m_ifetch_addr: 0xbfc00040
+mips0 early_end: ireq_ok=0 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00040 m_jump_pc: 0xbfc00044 m_ifetch_addr: 0xbfc00040
+mips0 early_end: ireq_ok=0 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00040 m_jump_pc: 0xbfc00044 m_ifetch_addr: 0xbfc00040
+mips0 early_end: ireq_ok=0 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00040 m_jump_pc: 0xbfc00044 m_ifetch_addr: 0xbfc00040
+mips0 early_end: ireq_ok=0 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00040 m_jump_pc: 0xbfc00044 m_ifetch_addr: 0xbfc00040
+mips0 early_end: ireq_ok=0 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00040 m_jump_pc: 0xbfc00044 m_ifetch_addr: 0xbfc00040
+mips0 early_end: ireq_ok=0 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00040 m_jump_pc: 0xbfc00044 m_ifetch_addr: 0xbfc00040
+mips0 early_end: ireq_ok=0 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00040 m_jump_pc: 0xbfc00044 m_ifetch_addr: 0xbfc00040
+mips0 early_end: ireq_ok=0 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00040 m_jump_pc: 0xbfc00044 m_ifetch_addr: 0xbfc00040
+mips0 early_end: ireq_ok=0 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00040 m_jump_pc: 0xbfc00044 m_ifetch_addr: 0xbfc00040
+mips0 early_end: ireq_ok=0 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00040 m_jump_pc: 0xbfc00044 m_ifetch_addr: 0xbfc00040
+mips0 early_end: ireq_ok=0 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00040 m_jump_pc: 0xbfc00044 m_ifetch_addr: 0xbfc00040
+mips0 early_end: ireq_ok=0 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00040 m_jump_pc: 0xbfc00044 m_ifetch_addr: 0xbfc00040
+mips0 early_end: ireq_ok=0 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00040 m_jump_pc: 0xbfc00044 m_ifetch_addr: 0xbfc00040
+mips0 early_end: ireq_ok=0 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00040 m_jump_pc: 0xbfc00044 m_ifetch_addr: 0xbfc00040
+mips0 early_end: ireq_ok=0 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00040 m_jump_pc: 0xbfc00044 m_ifetch_addr: 0xbfc00040
+mips0 early_end: ireq_ok=0 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00040 m_jump_pc: 0xbfc00044 m_ifetch_addr: 0xbfc00040
+mips0 early_end: ireq_ok=0 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00040 m_jump_pc: 0xbfc00044 m_ifetch_addr: 0xbfc00040
+mips0 early_end: ireq_ok=0 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00040 m_jump_pc: 0xbfc00044 m_ifetch_addr: 0xbfc00040
+mips0 early_end: ireq_ok=0 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00040 m_jump_pc: 0xbfc00044 m_ifetch_addr: 0xbfc00040
+mips0 early_end: ireq_ok=0 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00040 m_jump_pc: 0xbfc00044 m_ifetch_addr: 0xbfc00040
+mips0 early_end: ireq_ok=0 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00040 m_jump_pc: 0xbfc00044 m_ifetch_addr: 0xbfc00040
+mips0 early_end: ireq_ok=0 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00040 m_jump_pc: 0xbfc00044 m_ifetch_addr: 0xbfc00040
+mips0 early_end: ireq_ok=0 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00040 m_jump_pc: 0xbfc00044 m_ifetch_addr: 0xbfc00040
+mips0 early_end: ireq_ok=0 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00040 m_jump_pc: 0xbfc00044 m_ifetch_addr: 0xbfc00040
+mips0 early_end: ireq_ok=0 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00040 m_jump_pc: 0xbfc00044 m_ifetch_addr: 0xbfc00040
+mips0 early_end: ireq_ok=0 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00040 m_jump_pc: 0xbfc00044 m_ifetch_addr: 0xbfc00040
+mips0 early_end: ireq_ok=0 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00040 m_jump_pc: 0xbfc00044 m_ifetch_addr: 0xbfc00040
+mips0 early_end: ireq_ok=0 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x24040001>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00040 m_jump_pc: 0xbfc00044 m_ifetch_addr: 0xbfc00040
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x24040001>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00040 m_jump_pc: 0xbfc00044 m_ifetch_addr: 0xbfc00040
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x24040001>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00040 m_jump_pc: 0xbfc00044 m_ifetch_addr: 0xbfc00040
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x24040001>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00040 m_jump_pc: 0xbfc00044 m_ifetch_addr: 0xbfc00040
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x24040001>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00040 m_jump_pc: 0xbfc00044 m_ifetch_addr: 0xbfc00040
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x24040001>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00040 m_jump_pc: 0xbfc00044 m_ifetch_addr: 0xbfc00040
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x24040001>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00040 m_jump_pc: 0xbfc00044 m_ifetch_addr: 0xbfc00040
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x24040001>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00040 m_jump_pc: 0xbfc00044 m_ifetch_addr: 0xbfc00040
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x24040001>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00040 m_jump_pc: 0xbfc00044 m_ifetch_addr: 0xbfc00040
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x24040001>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00040 m_jump_pc: 0xbfc00044 m_ifetch_addr: 0xbfc00040
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x24040001>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00040 m_jump_pc: 0xbfc00044 m_ifetch_addr: 0xbfc00040
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x24040001>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00040 m_jump_pc: 0xbfc00044 m_ifetch_addr: 0xbfc00040
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x24040001>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00040 m_jump_pc: 0xbfc00044 m_ifetch_addr: 0xbfc00040
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x24040001>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00040 m_jump_pc: 0xbfc00044 m_ifetch_addr: 0xbfc00040
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x24040001>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00040 m_jump_pc: 0xbfc00044 m_ifetch_addr: 0xbfc00040
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x24040001>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00040 m_jump_pc: 0xbfc00044 m_ifetch_addr: 0xbfc00040
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x24040001>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00040 m_jump_pc: 0xbfc00044 m_ifetch_addr: 0xbfc00040
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x24040001>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00040 m_jump_pc: 0xbfc00044 m_ifetch_addr: 0xbfc00040
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x24040001>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00040 m_jump_pc: 0xbfc00044 m_ifetch_addr: 0xbfc00040
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x24040001>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00040 m_jump_pc: 0xbfc00044 m_ifetch_addr: 0xbfc00040
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x24040001>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00040 m_jump_pc: 0xbfc00044 m_ifetch_addr: 0xbfc00040
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x24040001>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00040 m_jump_pc: 0xbfc00044 m_ifetch_addr: 0xbfc00040
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x24040001>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00040 m_jump_pc: 0xbfc00044 m_ifetch_addr: 0xbfc00040
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x24040001>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00040 m_jump_pc: 0xbfc00044 m_ifetch_addr: 0xbfc00040
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x24040001>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00040 m_jump_pc: 0xbfc00044 m_ifetch_addr: 0xbfc00040
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x24040001>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00040 m_jump_pc: 0xbfc00044 m_ifetch_addr: 0xbfc00040
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x24040001>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00040 m_jump_pc: 0xbfc00044 m_ifetch_addr: 0xbfc00040
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x24040001>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00040 m_jump_pc: 0xbfc00044 m_ifetch_addr: 0xbfc00040
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x24040001>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00040 m_jump_pc: 0xbfc00044 m_ifetch_addr: 0xbfc00040
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x24040001>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00040 m_jump_pc: 0xbfc00044 m_ifetch_addr: 0xbfc00040
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x24040001>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00040 m_jump_pc: 0xbfc00044 m_ifetch_addr: 0xbfc00040
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x24040001>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00040 m_jump_pc: 0xbfc00044 m_ifetch_addr: 0xbfc00040
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x24040001>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00040 m_jump_pc: 0xbfc00044 m_ifetch_addr: 0xbfc00040
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x24040001>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00040 m_jump_pc: 0xbfc00044 m_ifetch_addr: 0xbfc00040
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x24040001>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00040 m_jump_pc: 0xbfc00044 m_ifetch_addr: 0xbfc00040
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x24040001>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00040 m_jump_pc: 0xbfc00044 m_ifetch_addr: 0xbfc00040
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x24040001>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00040 m_jump_pc: 0xbfc00044 m_ifetch_addr: 0xbfc00040
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x24040001>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00040 m_jump_pc: 0xbfc00044 m_ifetch_addr: 0xbfc00040
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x24040001>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00040 m_jump_pc: 0xbfc00044 m_ifetch_addr: 0xbfc00040
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x24040001>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00040 m_jump_pc: 0xbfc00044 m_ifetch_addr: 0xbfc00040
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x24040001>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00040 m_jump_pc: 0xbfc00044 m_ifetch_addr: 0xbfc00040
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x24040001>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00040 m_jump_pc: 0xbfc00044 m_ifetch_addr: 0xbfc00040
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x24040001>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00040 m_jump_pc: 0xbfc00044 m_ifetch_addr: 0xbfc00040
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x24040001>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00040 m_jump_pc: 0xbfc00044 m_ifetch_addr: 0xbfc00040
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x24040001>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00040 m_jump_pc: 0xbfc00044 m_ifetch_addr: 0xbfc00040
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x24040001>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00040 m_jump_pc: 0xbfc00044 m_ifetch_addr: 0xbfc00040
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x24040001>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00040 m_jump_pc: 0xbfc00044 m_ifetch_addr: 0xbfc00040
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x24040001>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00040 m_jump_pc: 0xbfc00044 m_ifetch_addr: 0xbfc00040
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x24040001>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00040 m_jump_pc: 0xbfc00044 m_ifetch_addr: 0xbfc00040
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x24040001>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00040 m_jump_pc: 0xbfc00044 m_ifetch_addr: 0xbfc00040
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x24040001>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00040 m_jump_pc: 0xbfc00044 m_ifetch_addr: 0xbfc00040
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x24040001>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00040 m_jump_pc: 0xbfc00044 m_ifetch_addr: 0xbfc00040
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x24040001>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00040 m_jump_pc: 0xbfc00044 m_ifetch_addr: 0xbfc00040
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x24040001>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00040 m_jump_pc: 0xbfc00044 m_ifetch_addr: 0xbfc00040
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x24040001>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00040 m_jump_pc: 0xbfc00044 m_ifetch_addr: 0xbfc00040
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x24040001>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00040 m_jump_pc: 0xbfc00044 m_ifetch_addr: 0xbfc00040
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x24040001>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x4
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 count: 0x4 le: 0 old: 0xbfc00248 from_mem: 0 mask: 0xffffffff new_data: 0
+mips0 PC: 0xbfc00040 NPC: 0xbfc00044 Ins: 0x24040001
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 0 .erl: 1 .whole: 0x400004
+ op:  0x9 (addiu)
+ i rs: 0 rt: 0x4 i: 0x1
+ r rs: 0 rt: 4 rd: 0 sh: 0 func: 0x1
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: d8200000 09: 00000000 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 00000000 17: 00000000 18: 00000000 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00038
+mips0 m_next_pc: 0xbfc00044 m_jump_pc: 0xbfc00048 m_ifetch_addr: 0xbfc00044
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xad040280>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00044 NPC: 0xbfc00048 Ins: 0xad040280
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 0 .erl: 1 .whole: 0x400004
+ op:  0x2b (sw)
+ i rs: 0x8 rt: 0x4 i: 0x280
+ r rs: 8 rt: 4 rd: 0 sh: 10 func: 0
+ V rs: 0xd8200000 rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000001 05: 00000000 06: 00000000 07: 00000000
+ 08: d8200000 09: 00000000 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 00000000 17: 00000000 18: 00000000 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00038
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd8200280 wdata 0x1 be 0xf> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc00048 m_jump_pc: 0xbfc0004c m_ifetch_addr: 0xbfc00048
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3410beef>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00048 m_jump_pc: 0xbfc0004c m_ifetch_addr: 0xbfc00048
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3410beef>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00048 m_jump_pc: 0xbfc0004c m_ifetch_addr: 0xbfc00048
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3410beef>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00048 m_jump_pc: 0xbfc0004c m_ifetch_addr: 0xbfc00048
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3410beef>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00048 m_jump_pc: 0xbfc0004c m_ifetch_addr: 0xbfc00048
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3410beef>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00048 m_jump_pc: 0xbfc0004c m_ifetch_addr: 0xbfc00048
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3410beef>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00048 m_jump_pc: 0xbfc0004c m_ifetch_addr: 0xbfc00048
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3410beef>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00048 m_jump_pc: 0xbfc0004c m_ifetch_addr: 0xbfc00048
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3410beef>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00048 m_jump_pc: 0xbfc0004c m_ifetch_addr: 0xbfc00048
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3410beef>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00048 m_jump_pc: 0xbfc0004c m_ifetch_addr: 0xbfc00048
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3410beef>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00048 m_jump_pc: 0xbfc0004c m_ifetch_addr: 0xbfc00048
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3410beef>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00048 m_jump_pc: 0xbfc0004c m_ifetch_addr: 0xbfc00048
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3410beef>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00048 m_jump_pc: 0xbfc0004c m_ifetch_addr: 0xbfc00048
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3410beef>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00048 m_jump_pc: 0xbfc0004c m_ifetch_addr: 0xbfc00048
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3410beef>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00048 m_jump_pc: 0xbfc0004c m_ifetch_addr: 0xbfc00048
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3410beef>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00048 m_jump_pc: 0xbfc0004c m_ifetch_addr: 0xbfc00048
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3410beef>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00048 m_jump_pc: 0xbfc0004c m_ifetch_addr: 0xbfc00048
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3410beef>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00048 m_jump_pc: 0xbfc0004c m_ifetch_addr: 0xbfc00048
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3410beef>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00048 m_jump_pc: 0xbfc0004c m_ifetch_addr: 0xbfc00048
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3410beef>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00048 m_jump_pc: 0xbfc0004c m_ifetch_addr: 0xbfc00048
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3410beef>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00048 m_jump_pc: 0xbfc0004c m_ifetch_addr: 0xbfc00048
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3410beef>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00048 m_jump_pc: 0xbfc0004c m_ifetch_addr: 0xbfc00048
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3410beef>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc00048 NPC: 0xbfc0004c Ins: 0x3410beef
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 0 .erl: 1 .whole: 0x400004
+ op:  0xd (ori)
+ i rs: 0 rt: 0x10 i: 0xbeef
+ r rs: 0 rt: 16 rd: 23 sh: 27 func: 0x2f
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000001 05: 00000000 06: 00000000 07: 00000000
+ 08: d8200000 09: 00000000 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 00000000 17: 00000000 18: 00000000 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00038
+mips0 m_next_pc: 0xbfc0004c m_jump_pc: 0xbfc00050 m_ifetch_addr: 0xbfc0004c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x24120001>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0004c NPC: 0xbfc00050 Ins: 0x24120001
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 0 .erl: 1 .whole: 0x400004
+ op:  0x9 (addiu)
+ i rs: 0 rt: 0x12 i: 0x1
+ r rs: 0 rt: 18 rd: 0 sh: 0 func: 0x1
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000001 05: 00000000 06: 00000000 07: 00000000
+ 08: d8200000 09: 00000000 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beef 17: 00000000 18: 00000000 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00038
+mips0 m_next_pc: 0xbfc00050 m_jump_pc: 0xbfc00054 m_ifetch_addr: 0xbfc00050
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xad120080>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00050 NPC: 0xbfc00054 Ins: 0xad120080
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 0 .erl: 1 .whole: 0x400004
+ op:  0x2b (sw)
+ i rs: 0x8 rt: 0x12 i: 0x80
+ r rs: 8 rt: 18 rd: 0 sh: 2 func: 0
+ V rs: 0xd8200000 rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000001 05: 00000000 06: 00000000 07: 00000000
+ 08: d8200000 09: 00000000 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beef 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00038
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd8200080 wdata 0x1 be 0xf> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc00054 m_jump_pc: 0xbfc00058 m_ifetch_addr: 0xbfc00054
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x8d040180>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc00054 NPC: 0xbfc00058 Ins: 0x8d040180
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 0 .erl: 1 .whole: 0x400004
+ op:  0x23 (lw)
+ i rs: 0x8 rt: 0x4 i: 0x180
+ r rs: 8 rt: 4 rd: 0 sh: 6 func: 0
+ V rs: 0xd8200000 rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000001 05: 00000000 06: 00000000 07: 00000000
+ 08: d8200000 09: 00000000 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beef 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00038
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_READ @ 0xd8200180 wdata 0 be 0xf> off: 0 sign_ext: 0 dest: gp+0x4
+mips0 m_next_pc: 0xbfc00058 m_jump_pc: 0xbfc0005c m_ifetch_addr: 0xbfc00058
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c040040>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00058 m_jump_pc: 0xbfc0005c m_ifetch_addr: 0xbfc00058
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c040040>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00058 m_jump_pc: 0xbfc0005c m_ifetch_addr: 0xbfc00058
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c040040>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00058 m_jump_pc: 0xbfc0005c m_ifetch_addr: 0xbfc00058
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c040040>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00058 m_jump_pc: 0xbfc0005c m_ifetch_addr: 0xbfc00058
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c040040>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00058 m_jump_pc: 0xbfc0005c m_ifetch_addr: 0xbfc00058
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c040040>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00058 m_jump_pc: 0xbfc0005c m_ifetch_addr: 0xbfc00058
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c040040>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00058 m_jump_pc: 0xbfc0005c m_ifetch_addr: 0xbfc00058
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c040040>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00058 m_jump_pc: 0xbfc0005c m_ifetch_addr: 0xbfc00058
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c040040>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00058 m_jump_pc: 0xbfc0005c m_ifetch_addr: 0xbfc00058
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c040040>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00058 m_jump_pc: 0xbfc0005c m_ifetch_addr: 0xbfc00058
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c040040>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00058 m_jump_pc: 0xbfc0005c m_ifetch_addr: 0xbfc00058
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c040040>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00058 m_jump_pc: 0xbfc0005c m_ifetch_addr: 0xbfc00058
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c040040>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00058 m_jump_pc: 0xbfc0005c m_ifetch_addr: 0xbfc00058
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c040040>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00058 m_jump_pc: 0xbfc0005c m_ifetch_addr: 0xbfc00058
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c040040>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00058 m_jump_pc: 0xbfc0005c m_ifetch_addr: 0xbfc00058
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c040040>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00058 m_jump_pc: 0xbfc0005c m_ifetch_addr: 0xbfc00058
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c040040>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00058 m_jump_pc: 0xbfc0005c m_ifetch_addr: 0xbfc00058
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c040040>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00058 m_jump_pc: 0xbfc0005c m_ifetch_addr: 0xbfc00058
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c040040>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00058 m_jump_pc: 0xbfc0005c m_ifetch_addr: 0xbfc00058
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c040040>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00058 m_jump_pc: 0xbfc0005c m_ifetch_addr: 0xbfc00058
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c040040>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00058 m_jump_pc: 0xbfc0005c m_ifetch_addr: 0xbfc00058
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c040040>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00058 m_jump_pc: 0xbfc0005c m_ifetch_addr: 0xbfc00058
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c040040>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00058 m_jump_pc: 0xbfc0005c m_ifetch_addr: 0xbfc00058
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c040040>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00058 m_jump_pc: 0xbfc0005c m_ifetch_addr: 0xbfc00058
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c040040>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00058 m_jump_pc: 0xbfc0005c m_ifetch_addr: 0xbfc00058
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c040040>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00058 m_jump_pc: 0xbfc0005c m_ifetch_addr: 0xbfc00058
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c040040>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00058 m_jump_pc: 0xbfc0005c m_ifetch_addr: 0xbfc00058
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c040040>, <DataRsp valid no error rdata 0>, 0x1)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x4
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 count: 0x4 le: 0 old: 0x1 from_mem: 0 mask: 0xffffffff new_data: 0
+mips0 PC: 0xbfc00058 NPC: 0xbfc0005c Ins: 0x3c040040
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 0 .erl: 1 .whole: 0x400004
+ op:  0xf (lui)
+ i rs: 0 rt: 0x4 i: 0x40
+ r rs: 0 rt: 4 rd: 0 sh: 1 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: d8200000 09: 00000000 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beef 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00038
+mips0 m_next_pc: 0xbfc0005c m_jump_pc: 0xbfc00060 m_ifetch_addr: 0xbfc0005c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x24840401>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 PC: 0xbfc0005c NPC: 0xbfc00060 Ins: 0x24840401
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 0 .erl: 1 .whole: 0x400004
+ op:  0x9 (addiu)
+ i rs: 0x4 rt: 0x4 i: 0x401
+ r rs: 4 rt: 4 rd: 0 sh: 16 func: 0x1
+ V rs: 0x400000 rt: 0x400000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400000 05: 00000000 06: 00000000 07: 00000000
+ 08: d8200000 09: 00000000 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beef 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00038
+mips0 m_next_pc: 0xbfc00060 m_jump_pc: 0xbfc00064 m_ifetch_addr: 0xbfc00060
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x40846000>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 PC: 0xbfc00060 NPC: 0xbfc00064 Ins: 0x40846000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 0 .erl: 1 .whole: 0x400004
+ op:  0x10 (cop0)
+ i rs: 0x4 rt: 0x4 i: 0x6000
+ r rs: 4 rt: 4 rd: 12 sh: 0 func: 0
+ V rs: 0x400401 rt: 0x400401
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400401 05: 00000000 06: 00000000 07: 00000000
+ 08: d8200000 09: 00000000 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beef 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00038
+mips0 m_next_pc: 0xbfc00064 m_jump_pc: 0xbfc00068 m_ifetch_addr: 0xbfc00064
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 PC: 0xbfc00064 NPC: 0xbfc00068 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 0 .erl: 0 .whole: 0x400401
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400401 05: 00000000 06: 00000000 07: 00000000
+ 08: d8200000 09: 00000000 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beef 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00038
+mips0 exception: 0
+ m_ins: 0 epc: bfc00068 error_epc: 0 bar: d8200180 cause.xcode: 0 .bd: 0 .ip: 4 status.exl: 1 .erl: 0 exception address: bfc00380
+mips0 executeNCycles( 1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0004d>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 PC: 0xbfc00380 NPC: 0xbfc00384 Ins: 0xbf0004d
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0x4d
+ r rs: 31 rt: 16 rd: 0 sh: 1 func: 0xd
+ V rs: 0xbfc00038 rt: 0xbeef
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400401 05: 00000000 06: 00000000 07: 00000000
+ 08: d8200000 09: 00000000 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beef 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00038
+mips0 m_next_pc: 0xbfc00384 m_jump_pc: 0xbfc00134 m_ifetch_addr: 0xbfc00384
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 PC: 0xbfc00384 NPC: 0xbfc00134 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400401 05: 00000000 06: 00000000 07: 00000000
+ 08: d8200000 09: 00000000 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beef 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00038
+mips0 m_next_pc: 0xbfc00134 m_jump_pc: 0xbfc00138 m_ifetch_addr: 0xbfc00134
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00134 m_jump_pc: 0xbfc00138 m_ifetch_addr: 0xbfc00134
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00134 m_jump_pc: 0xbfc00138 m_ifetch_addr: 0xbfc00134
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00134 m_jump_pc: 0xbfc00138 m_ifetch_addr: 0xbfc00134
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00134 m_jump_pc: 0xbfc00138 m_ifetch_addr: 0xbfc00134
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00134 m_jump_pc: 0xbfc00138 m_ifetch_addr: 0xbfc00134
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00134 m_jump_pc: 0xbfc00138 m_ifetch_addr: 0xbfc00134
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00134 m_jump_pc: 0xbfc00138 m_ifetch_addr: 0xbfc00134
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00134 m_jump_pc: 0xbfc00138 m_ifetch_addr: 0xbfc00134
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00134 m_jump_pc: 0xbfc00138 m_ifetch_addr: 0xbfc00134
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00134 m_jump_pc: 0xbfc00138 m_ifetch_addr: 0xbfc00134
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00134 m_jump_pc: 0xbfc00138 m_ifetch_addr: 0xbfc00134
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00134 m_jump_pc: 0xbfc00138 m_ifetch_addr: 0xbfc00134
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00134 m_jump_pc: 0xbfc00138 m_ifetch_addr: 0xbfc00134
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00134 m_jump_pc: 0xbfc00138 m_ifetch_addr: 0xbfc00134
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00134 m_jump_pc: 0xbfc00138 m_ifetch_addr: 0xbfc00134
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00134 m_jump_pc: 0xbfc00138 m_ifetch_addr: 0xbfc00134
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00134 m_jump_pc: 0xbfc00138 m_ifetch_addr: 0xbfc00134
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00134 m_jump_pc: 0xbfc00138 m_ifetch_addr: 0xbfc00134
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00134 m_jump_pc: 0xbfc00138 m_ifetch_addr: 0xbfc00134
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00134 m_jump_pc: 0xbfc00138 m_ifetch_addr: 0xbfc00134
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00134 m_jump_pc: 0xbfc00138 m_ifetch_addr: 0xbfc00134
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00134 m_jump_pc: 0xbfc00138 m_ifetch_addr: 0xbfc00134
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00134 m_jump_pc: 0xbfc00138 m_ifetch_addr: 0xbfc00134
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00134 m_jump_pc: 0xbfc00138 m_ifetch_addr: 0xbfc00134
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00134 m_jump_pc: 0xbfc00138 m_ifetch_addr: 0xbfc00134
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00134 m_jump_pc: 0xbfc00138 m_ifetch_addr: 0xbfc00134
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00134 m_jump_pc: 0xbfc00138 m_ifetch_addr: 0xbfc00134
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2610ffff>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 PC: 0xbfc00134 NPC: 0xbfc00138 Ins: 0x2610ffff
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0x10 rt: 0x10 i: 0xffff
+ r rs: 16 rt: 16 rd: 31 sh: 31 func: 0x3f
+ V rs: 0xbeef rt: 0xbeef
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400401 05: 00000000 06: 00000000 07: 00000000
+ 08: d8200000 09: 00000000 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beef 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00038
+mips0 m_next_pc: 0xbfc00138 m_jump_pc: 0xbfc0013c m_ifetch_addr: 0xbfc00138
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c08d820>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 PC: 0xbfc00138 NPC: 0xbfc0013c Ins: 0x3c08d820
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0x8 i: 0xd820
+ r rs: 0 rt: 8 rd: 27 sh: 0 func: 0x20
+ V rs: 0 rt: 0xd8200000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400401 05: 00000000 06: 00000000 07: 00000000
+ 08: d8200000 09: 00000000 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00038
+mips0 m_next_pc: 0xbfc0013c m_jump_pc: 0xbfc00140 m_ifetch_addr: 0xbfc0013c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xad000080>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 PC: 0xbfc0013c NPC: 0xbfc00140 Ins: 0xad000080
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2b (sw)
+ i rs: 0x8 rt: 0 i: 0x80
+ r rs: 8 rt: 0 rd: 0 sh: 2 func: 0
+ V rs: 0xd8200000 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400401 05: 00000000 06: 00000000 07: 00000000
+ 08: d8200000 09: 00000000 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00038
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd8200080 wdata 0 be 0xf> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc00140 m_jump_pc: 0xbfc00144 m_ifetch_addr: 0xbfc00140
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp valid no error rdata 0>, 0x1)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 m_next_pc: 0xbfc00140 m_jump_pc: 0xbfc00144 m_ifetch_addr: 0xbfc00140
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00140 m_jump_pc: 0xbfc00144 m_ifetch_addr: 0xbfc00140
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00140 m_jump_pc: 0xbfc00144 m_ifetch_addr: 0xbfc00140
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00140 m_jump_pc: 0xbfc00144 m_ifetch_addr: 0xbfc00140
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00140 m_jump_pc: 0xbfc00144 m_ifetch_addr: 0xbfc00140
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00140 m_jump_pc: 0xbfc00144 m_ifetch_addr: 0xbfc00140
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00140 m_jump_pc: 0xbfc00144 m_ifetch_addr: 0xbfc00140
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00140 m_jump_pc: 0xbfc00144 m_ifetch_addr: 0xbfc00140
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00140 m_jump_pc: 0xbfc00144 m_ifetch_addr: 0xbfc00140
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00140 m_jump_pc: 0xbfc00144 m_ifetch_addr: 0xbfc00140
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00140 m_jump_pc: 0xbfc00144 m_ifetch_addr: 0xbfc00140
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00140 m_jump_pc: 0xbfc00144 m_ifetch_addr: 0xbfc00140
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00140 m_jump_pc: 0xbfc00144 m_ifetch_addr: 0xbfc00140
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00140 m_jump_pc: 0xbfc00144 m_ifetch_addr: 0xbfc00140
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00140 m_jump_pc: 0xbfc00144 m_ifetch_addr: 0xbfc00140
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00140 m_jump_pc: 0xbfc00144 m_ifetch_addr: 0xbfc00140
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00140 m_jump_pc: 0xbfc00144 m_ifetch_addr: 0xbfc00140
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00140 m_jump_pc: 0xbfc00144 m_ifetch_addr: 0xbfc00140
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00140 m_jump_pc: 0xbfc00144 m_ifetch_addr: 0xbfc00140
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00140 m_jump_pc: 0xbfc00144 m_ifetch_addr: 0xbfc00140
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00140 m_jump_pc: 0xbfc00144 m_ifetch_addr: 0xbfc00140
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00140 m_jump_pc: 0xbfc00144 m_ifetch_addr: 0xbfc00140
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00140 m_jump_pc: 0xbfc00144 m_ifetch_addr: 0xbfc00140
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00140 m_jump_pc: 0xbfc00144 m_ifetch_addr: 0xbfc00140
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00140 m_jump_pc: 0xbfc00144 m_ifetch_addr: 0xbfc00140
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00140 m_jump_pc: 0xbfc00144 m_ifetch_addr: 0xbfc00140
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00140 m_jump_pc: 0xbfc00144 m_ifetch_addr: 0xbfc00140
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c04bfc0>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 PC: 0xbfc00140 NPC: 0xbfc00144 Ins: 0x3c04bfc0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0x4 i: 0xbfc0
+ r rs: 0 rt: 4 rd: 23 sh: 31 func: 0
+ V rs: 0 rt: 0x400401
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400401 05: 00000000 06: 00000000 07: 00000000
+ 08: d8200000 09: 00000000 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00038
+mips0 m_next_pc: 0xbfc00144 m_jump_pc: 0xbfc00148 m_ifetch_addr: 0xbfc00144
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x24840224>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 PC: 0xbfc00144 NPC: 0xbfc00148 Ins: 0x24840224
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0x4 rt: 0x4 i: 0x224
+ r rs: 4 rt: 4 rd: 0 sh: 8 func: 0x24
+ V rs: 0xbfc00000 rt: 0xbfc00000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00000 05: 00000000 06: 00000000 07: 00000000
+ 08: d8200000 09: 00000000 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00038
+mips0 m_next_pc: 0xbfc00148 m_jump_pc: 0xbfc0014c m_ifetch_addr: 0xbfc00148
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xff000f0>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 PC: 0xbfc00148 NPC: 0xbfc0014c Ins: 0xff000f0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x3 (jal)
+ i rs: 0x1f rt: 0x10 i: 0xf0
+ r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x30
+ V rs: 0xbfc00038 rt: 0xbeee
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: d8200000 09: 00000000 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00038
+mips0 m_next_pc: 0xbfc0014c m_jump_pc: 0xbfc003c0 m_ifetch_addr: 0xbfc0014c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0014c NPC: 0xbfc003c0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: d8200000 09: 00000000 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 m_next_pc: 0xbfc003c0 m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003c0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x804021>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c0 NPC: 0xbfc003c4 Ins: 0x804021
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x4 rt: 0 i: 0x4021
+ r rs: 4 rt: 0 rd: 8 sh: 0 func: 0x21
+ V rs: 0xbfc00224 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: d8200000 09: 00000000 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x81090000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x20 (lb)
+ i rs: 0x8 rt: 0x9 i: 0
+ r rs: 8 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xbfc00224 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00224 09: 00000000 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_READ @ 0xbfc00224 wdata 0 be 0x1> off: 0 sign_ext: 0x1 dest: gp+0x9
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp valid no error rdata 0x74617473>, 0)
+mips0 setData: <DataRsp valid no error rdata 0x74617473> off: 0 sign_ext: 0x1 dest: r_gp+0x9
+mips0 setData: <DataRsp valid no error rdata 0x74617473> off: 0 count: 0x1 le: 0 old: 0 from_mem: 0x74617473 mask: 0xffffffff new_data: 0x73
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0x9 rt: 0 i: 0x5
+ r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5
+ V rs: 0x73 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00224 09: 00000073 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00224 09: 00000073 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa3490000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0x9 i: 0
+ r rs: 26 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x73
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00224 09: 00000073 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x73 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0x8 rt: 0x8 i: 0x1
+ r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1
+ V rs: 0xbfc00224 rt: 0xbfc00224
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00224 09: 00000073 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf000f1>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0xf1
+ r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31
+ V rs: 0xbfc00150 rt: 0xbeee
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00225 09: 00000073 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00225 09: 00000073 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x81090000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x20 (lb)
+ i rs: 0x8 rt: 0x9 i: 0
+ r rs: 8 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xbfc00225 rt: 0x73
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00225 09: 00000073 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_READ @ 0xbfc00224 wdata 0 be 0x2> off: 0x1 sign_ext: 0x1 dest: gp+0x9
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp valid no error rdata 0x74617473>, 0)
+mips0 setData: <DataRsp valid no error rdata 0x74617473> off: 0 sign_ext: 0x1 dest: r_gp+0x9
+mips0 setData: <DataRsp valid no error rdata 0x74617473> off: 0 count: 0x1 le: 0x1 old: 0x73 from_mem: 0x74617473 mask: 0xffffffff new_data: 0x74
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1
+smips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0x9 rt: 0 i: 0x5
+ r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5
+ V rs: 0x74 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00225 09: 00000074 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00225 09: 00000074 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa3490000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0x9 i: 0
+ r rs: 26 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x74
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00225 09: 00000074 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x74 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0x8 rt: 0x8 i: 0x1
+ r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1
+ V rs: 0xbfc00225 rt: 0xbfc00225
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00225 09: 00000074 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf000f1>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0xf1
+ r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31
+ V rs: 0xbfc00150 rt: 0xbeee
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00226 09: 00000074 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00226 09: 00000074 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x81090000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x20 (lb)
+ i rs: 0x8 rt: 0x9 i: 0
+ r rs: 8 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xbfc00226 rt: 0x74
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00226 09: 00000074 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_READ @ 0xbfc00224 wdata 0 be 0x4> off: 0x2 sign_ext: 0x1 dest: gp+0x9
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp valid no error rdata 0x74617473>, 0)
+mips0 setData: <DataRsp valid no error rdata 0x74617473> off: 0 sign_ext: 0x1 dest: r_gp+0x9
+mips0 setData: <DataRsp valid no error rdata 0x74617473> off: 0 count: 0x1 le: 0x2 old: 0x74 from_mem: 0x74617473 mask: 0xffffffff new_data: 0x61
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0x9 rt: 0 i: 0x5
+ r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5
+ V rs: 0x61 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00226 09: 00000061 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+tmips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00226 09: 00000061 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa3490000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0x9 i: 0
+ r rs: 26 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x61
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00226 09: 00000061 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x61 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0x8 rt: 0x8 i: 0x1
+ r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1
+ V rs: 0xbfc00226 rt: 0xbfc00226
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00226 09: 00000061 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf000f1>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0xf1
+ r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31
+ V rs: 0xbfc00150 rt: 0xbeee
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00227 09: 00000061 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00227 09: 00000061 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x81090000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x20 (lb)
+ i rs: 0x8 rt: 0x9 i: 0
+ r rs: 8 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xbfc00227 rt: 0x61
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00227 09: 00000061 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_READ @ 0xbfc00224 wdata 0 be 0x8> off: 0x3 sign_ext: 0x1 dest: gp+0x9
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp valid no error rdata 0x74617473>, 0)
+mips0 setData: <DataRsp valid no error rdata 0x74617473> off: 0 sign_ext: 0x1 dest: r_gp+0x9
+mips0 setData: <DataRsp valid no error rdata 0x74617473> off: 0 count: 0x1 le: 0x3 old: 0x61 from_mem: 0x74617473 mask: 0xffffffff new_data: 0x74
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0x9 rt: 0 i: 0x5
+ r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5
+ V rs: 0x74 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00227 09: 00000074 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00227 09: 00000074 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+amips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa3490000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0x9 i: 0
+ r rs: 26 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x74
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00227 09: 00000074 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x74 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0x8 rt: 0x8 i: 0x1
+ r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1
+ V rs: 0xbfc00227 rt: 0xbfc00227
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00227 09: 00000074 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf000f1>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0xf1
+ r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31
+ V rs: 0xbfc00150 rt: 0xbeee
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00228 09: 00000074 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00228 09: 00000074 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x81090000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x20 (lb)
+ i rs: 0x8 rt: 0x9 i: 0
+ r rs: 8 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xbfc00228 rt: 0x74
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00228 09: 00000074 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_READ @ 0xbfc00228 wdata 0 be 0x1> off: 0 sign_ext: 0x1 dest: gp+0x9
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp valid no error rdata 0x207375>, 0)
+mips0 setData: <DataRsp valid no error rdata 0x207375> off: 0 sign_ext: 0x1 dest: r_gp+0x9
+mips0 setData: <DataRsp valid no error rdata 0x207375> off: 0 count: 0x1 le: 0 old: 0x74 from_mem: 0x207375 mask: 0xffffffff new_data: 0x75
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0x9 rt: 0 i: 0x5
+ r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5
+ V rs: 0x75 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00228 09: 00000075 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00228 09: 00000075 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa3490000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0x9 i: 0
+ r rs: 26 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x75
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00228 09: 00000075 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x75 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+tmips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0x8 rt: 0x8 i: 0x1
+ r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1
+ V rs: 0xbfc00228 rt: 0xbfc00228
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00228 09: 00000075 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf000f1>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0xf1
+ r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31
+ V rs: 0xbfc00150 rt: 0xbeee
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00229 09: 00000075 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00229 09: 00000075 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x81090000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x20 (lb)
+ i rs: 0x8 rt: 0x9 i: 0
+ r rs: 8 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xbfc00229 rt: 0x75
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00229 09: 00000075 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_READ @ 0xbfc00228 wdata 0 be 0x2> off: 0x1 sign_ext: 0x1 dest: gp+0x9
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp valid no error rdata 0x207375>, 0)
+mips0 setData: <DataRsp valid no error rdata 0x207375> off: 0 sign_ext: 0x1 dest: r_gp+0x9
+mips0 setData: <DataRsp valid no error rdata 0x207375> off: 0 count: 0x1 le: 0x1 old: 0x75 from_mem: 0x207375 mask: 0xffffffff new_data: 0x73
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0x9 rt: 0 i: 0x5
+ r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5
+ V rs: 0x73 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00229 09: 00000073 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00229 09: 00000073 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa3490000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0x9 i: 0
+ r rs: 26 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x73
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00229 09: 00000073 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x73 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+umips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0x8 rt: 0x8 i: 0x1
+ r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1
+ V rs: 0xbfc00229 rt: 0xbfc00229
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00229 09: 00000073 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf000f1>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0xf1
+ r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31
+ V rs: 0xbfc00150 rt: 0xbeee
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0022a 09: 00000073 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0022a 09: 00000073 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x81090000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x20 (lb)
+ i rs: 0x8 rt: 0x9 i: 0
+ r rs: 8 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xbfc0022a rt: 0x73
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0022a 09: 00000073 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_READ @ 0xbfc00228 wdata 0 be 0x4> off: 0x2 sign_ext: 0x1 dest: gp+0x9
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp valid no error rdata 0x207375>, 0)
+mips0 setData: <DataRsp valid no error rdata 0x207375> off: 0 sign_ext: 0x1 dest: r_gp+0x9
+mips0 setData: <DataRsp valid no error rdata 0x207375> off: 0 count: 0x1 le: 0x2 old: 0x73 from_mem: 0x207375 mask: 0xffffffff new_data: 0x20
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0x9 rt: 0 i: 0x5
+ r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5
+ V rs: 0x20 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0022a 09: 00000020 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0022a 09: 00000020 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa3490000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0x9 i: 0
+ r rs: 26 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x20
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0022a 09: 00000020 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x20 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+smips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0x8 rt: 0x8 i: 0x1
+ r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1
+ V rs: 0xbfc0022a rt: 0xbfc0022a
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0022a 09: 00000020 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf000f1>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0xf1
+ r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31
+ V rs: 0xbfc00150 rt: 0xbeee
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0022b 09: 00000020 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0022b 09: 00000020 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x81090000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x20 (lb)
+ i rs: 0x8 rt: 0x9 i: 0
+ r rs: 8 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xbfc0022b rt: 0x20
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0022b 09: 00000020 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_READ @ 0xbfc00228 wdata 0 be 0x8> off: 0x3 sign_ext: 0x1 dest: gp+0x9
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp valid no error rdata 0x207375>, 0)
+mips0 setData: <DataRsp valid no error rdata 0x207375> off: 0 sign_ext: 0x1 dest: r_gp+0x9
+mips0 setData: <DataRsp valid no error rdata 0x207375> off: 0 count: 0x1 le: 0x3 old: 0x20 from_mem: 0x207375 mask: 0xffffffff new_data: 0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0x9 rt: 0 i: 0x5
+ r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0022b 09: 00000000 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003e0 m_ifetch_addr: 0xbfc003cc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003cc NPC: 0xbfc003e0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0022b 09: 00000000 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 m_next_pc: 0xbfc003e0 m_jump_pc: 0xbfc003e4 m_ifetch_addr: 0xbfc003e0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3e00008>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003e0 NPC: 0xbfc003e4 Ins: 0x3e00008
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x1f rt: 0 i: 0x8
+ r rs: 31 rt: 0 rd: 0 sh: 0 func: 0x8
+ V rs: 0xbfc00150 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0022b 09: 00000000 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 m_next_pc: 0xbfc003e4 m_jump_pc: 0xbfc00150 m_ifetch_addr: 0xbfc003e4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+ mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003e4 NPC: 0xbfc00150 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0022b 09: 00000000 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 m_next_pc: 0xbfc00150 m_jump_pc: 0xbfc00154 m_ifetch_addr: 0xbfc00150
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x40046000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00150 NPC: 0xbfc00154 Ins: 0x40046000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x10 (cop0)
+ i rs: 0 rt: 0x4 i: 0x6000
+ r rs: 0 rt: 4 rd: 12 sh: 0 func: 0
+ V rs: 0 rt: 0xbfc00224
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0022b 09: 00000000 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 m_next_pc: 0xbfc00154 m_jump_pc: 0xbfc00158 m_ifetch_addr: 0xbfc00154
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xff000fa>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00154 NPC: 0xbfc00158 Ins: 0xff000fa
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x3 (jal)
+ i rs: 0x1f rt: 0x10 i: 0xfa
+ r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x3a
+ V rs: 0xbfc00150 rt: 0xbeee
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0022b 09: 00000000 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 m_next_pc: 0xbfc00158 m_jump_pc: 0xbfc003e8 m_ifetch_addr: 0xbfc00158
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00158 NPC: 0xbfc003e8 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0022b 09: 00000000 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc003e8 m_jump_pc: 0xbfc003ec m_ifetch_addr: 0xbfc003e8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x804021>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003e8 NPC: 0xbfc003ec Ins: 0x804021
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x4 rt: 0 i: 0x4021
+ r rs: 4 rt: 0 rd: 8 sh: 0 func: 0x21
+ V rs: 0x400403 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0022b 09: 00000000 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc003ec m_jump_pc: 0xbfc003f0 m_ifetch_addr: 0xbfc003ec
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x24090030>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003ec NPC: 0xbfc003f0 Ins: 0x24090030
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0 rt: 0x9 i: 0x30
+ r rs: 0 rt: 9 rd: 0 sh: 0 func: 0x30
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 00400403 09: 00000000 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc003f0 m_jump_pc: 0xbfc003f4 m_ifetch_addr: 0xbfc003f0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa3490000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003f0 NPC: 0xbfc003f4 Ins: 0xa3490000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0x9 i: 0
+ r rs: 26 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 00400403 09: 00000030 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc003f4 m_jump_pc: 0xbfc003f8 m_ifetch_addr: 0xbfc003f4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x24090078>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc003f4 NPC: 0xbfc003f8 Ins: 0x24090078
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0 rt: 0x9 i: 0x78
+ r rs: 0 rt: 9 rd: 0 sh: 1 func: 0x38
+ V rs: 0 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 00400403 09: 00000030 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc003f8 m_jump_pc: 0xbfc003fc m_ifetch_addr: 0xbfc003f8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa3490000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003f8 NPC: 0xbfc003fc Ins: 0xa3490000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0x9 i: 0
+ r rs: 26 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x78
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 00400403 09: 00000078 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x78 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc003fc m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc003fc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x24090008>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc003fc NPC: 0xbfc00400 Ins: 0x24090008
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0 rt: 0x9 i: 0x8
+ r rs: 0 rt: 9 rd: 0 sh: 0 func: 0x8
+ V rs: 0 rt: 0x78
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 00400403 09: 00000078 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+0mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c0af000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0xa i: 0xf000
+ r rs: 0 rt: 10 rd: 30 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 00400403 09: 00000008 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x10a5024>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x8 rt: 0xa i: 0x5024
+ r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24
+ V rs: 0x400403 rt: 0xf0000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 00400403 09: 00000008 10: f0000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+xmips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa5702>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0xa i: 0x5702
+ r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 00400403 09: 00000008 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x294b000a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xa (slti)
+ i rs: 0xa rt: 0xb i: 0xa
+ r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 00400403 09: 00000008 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11600004>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0xb rt: 0 i: 0x4
+ r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4
+ V rs: 0x1 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 00400403 09: 00000008 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 00400403 09: 00000008 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x214a0030>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0xa rt: 0xa i: 0x30
+ r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 00400403 09: 00000008 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0010a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0x10a
+ r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa
+ V rs: 0xbfc0015c rt: 0xbeee
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 00400403 09: 00000008 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 00400403 09: 00000008 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa34a0000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0xa i: 0
+ r rs: 26 rt: 10 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 00400403 09: 00000008 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2129ffff>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0x9 rt: 0x9 i: 0xffff
+ r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f
+ V rs: 0x8 rt: 0x8
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 00400403 09: 00000008 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x1d20fff3>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x7 (bgtz)
+ i rs: 0x9 rt: 0 i: 0xfff3
+ r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33
+ V rs: 0x7 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 00400403 09: 00000007 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x84100>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0x8 i: 0x4100
+ r rs: 0 rt: 8 rd: 8 sh: 4 func: 0
+ V rs: 0 rt: 0x400403
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 00400403 09: 00000007 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c0af000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0xa i: 0xf000
+ r rs: 0 rt: 10 rd: 30 sh: 0 func: 0
+ V rs: 0 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 04004030 09: 00000007 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x10a5024>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x8 rt: 0xa i: 0x5024
+ r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24
+ V rs: 0x4004030 rt: 0xf0000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 04004030 09: 00000007 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa5702>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0xa i: 0x5702
+ r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 04004030 09: 00000007 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+0mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x294b000a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xa (slti)
+ i rs: 0xa rt: 0xb i: 0xa
+ r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa
+ V rs: 0 rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 04004030 09: 00000007 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11600004>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0xb rt: 0 i: 0x4
+ r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4
+ V rs: 0x1 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 04004030 09: 00000007 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 04004030 09: 00000007 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x214a0030>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0xa rt: 0xa i: 0x30
+ r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 04004030 09: 00000007 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0010a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0x10a
+ r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa
+ V rs: 0xbfc0015c rt: 0xbeee
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 04004030 09: 00000007 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 04004030 09: 00000007 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa34a0000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0xa i: 0
+ r rs: 26 rt: 10 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 04004030 09: 00000007 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2129ffff>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0x9 rt: 0x9 i: 0xffff
+ r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f
+ V rs: 0x7 rt: 0x7
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 04004030 09: 00000007 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x1d20fff3>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x7 (bgtz)
+ i rs: 0x9 rt: 0 i: 0xfff3
+ r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33
+ V rs: 0x6 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 04004030 09: 00000006 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x84100>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0x8 i: 0x4100
+ r rs: 0 rt: 8 rd: 8 sh: 4 func: 0
+ V rs: 0 rt: 0x4004030
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 04004030 09: 00000006 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c0af000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0xa i: 0xf000
+ r rs: 0 rt: 10 rd: 30 sh: 0 func: 0
+ V rs: 0 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 40040300 09: 00000006 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x10a5024>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x8 rt: 0xa i: 0x5024
+ r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24
+ V rs: 0x40040300 rt: 0xf0000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 40040300 09: 00000006 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa5702>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0xa i: 0x5702
+ r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2
+ V rs: 0 rt: 0x40000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 40040300 09: 00000006 10: 40000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+0mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x294b000a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xa (slti)
+ i rs: 0xa rt: 0xb i: 0xa
+ r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa
+ V rs: 0x4 rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 40040300 09: 00000006 10: 00000004 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11600004>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0xb rt: 0 i: 0x4
+ r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4
+ V rs: 0x1 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 40040300 09: 00000006 10: 00000004 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 40040300 09: 00000006 10: 00000004 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x214a0030>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0xa rt: 0xa i: 0x30
+ r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30
+ V rs: 0x4 rt: 0x4
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 40040300 09: 00000006 10: 00000004 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0010a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0x10a
+ r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa
+ V rs: 0xbfc0015c rt: 0xbeee
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 40040300 09: 00000006 10: 00000034 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 40040300 09: 00000006 10: 00000034 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa34a0000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0xa i: 0
+ r rs: 26 rt: 10 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x34
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 40040300 09: 00000006 10: 00000034 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x34 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2129ffff>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0x9 rt: 0x9 i: 0xffff
+ r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f
+ V rs: 0x6 rt: 0x6
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 40040300 09: 00000006 10: 00000034 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x1d20fff3>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x7 (bgtz)
+ i rs: 0x9 rt: 0 i: 0xfff3
+ r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33
+ V rs: 0x5 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 40040300 09: 00000005 10: 00000034 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x84100>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0x8 i: 0x4100
+ r rs: 0 rt: 8 rd: 8 sh: 4 func: 0
+ V rs: 0 rt: 0x40040300
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 40040300 09: 00000005 10: 00000034 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c0af000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0xa i: 0xf000
+ r rs: 0 rt: 10 rd: 30 sh: 0 func: 0
+ V rs: 0 rt: 0x34
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 00403000 09: 00000005 10: 00000034 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x10a5024>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x8 rt: 0xa i: 0x5024
+ r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24
+ V rs: 0x403000 rt: 0xf0000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 00403000 09: 00000005 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa5702>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0xa i: 0x5702
+ r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 00403000 09: 00000005 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+4mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x294b000a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xa (slti)
+ i rs: 0xa rt: 0xb i: 0xa
+ r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa
+ V rs: 0 rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 00403000 09: 00000005 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11600004>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0xb rt: 0 i: 0x4
+ r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4
+ V rs: 0x1 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 00403000 09: 00000005 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 00403000 09: 00000005 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x214a0030>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0xa rt: 0xa i: 0x30
+ r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 00403000 09: 00000005 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0010a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0x10a
+ r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa
+ V rs: 0xbfc0015c rt: 0xbeee
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 00403000 09: 00000005 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 00403000 09: 00000005 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa34a0000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0xa i: 0
+ r rs: 26 rt: 10 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 00403000 09: 00000005 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2129ffff>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0x9 rt: 0x9 i: 0xffff
+ r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f
+ V rs: 0x5 rt: 0x5
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 00403000 09: 00000005 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x1d20fff3>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x7 (bgtz)
+ i rs: 0x9 rt: 0 i: 0xfff3
+ r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33
+ V rs: 0x4 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 00403000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x84100>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0x8 i: 0x4100
+ r rs: 0 rt: 8 rd: 8 sh: 4 func: 0
+ V rs: 0 rt: 0x403000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 00403000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c0af000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0xa i: 0xf000
+ r rs: 0 rt: 10 rd: 30 sh: 0 func: 0
+ V rs: 0 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 04030000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x10a5024>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x8 rt: 0xa i: 0x5024
+ r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24
+ V rs: 0x4030000 rt: 0xf0000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 04030000 09: 00000004 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa5702>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0xa i: 0x5702
+ r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 04030000 09: 00000004 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+0mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x294b000a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xa (slti)
+ i rs: 0xa rt: 0xb i: 0xa
+ r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa
+ V rs: 0 rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 04030000 09: 00000004 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11600004>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0xb rt: 0 i: 0x4
+ r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4
+ V rs: 0x1 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 04030000 09: 00000004 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 04030000 09: 00000004 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x214a0030>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0xa rt: 0xa i: 0x30
+ r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 04030000 09: 00000004 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0010a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0x10a
+ r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa
+ V rs: 0xbfc0015c rt: 0xbeee
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 04030000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 04030000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa34a0000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0xa i: 0
+ r rs: 26 rt: 10 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 04030000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2129ffff>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0x9 rt: 0x9 i: 0xffff
+ r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f
+ V rs: 0x4 rt: 0x4
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 04030000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x1d20fff3>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x7 (bgtz)
+ i rs: 0x9 rt: 0 i: 0xfff3
+ r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33
+ V rs: 0x3 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 04030000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x84100>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0x8 i: 0x4100
+ r rs: 0 rt: 8 rd: 8 sh: 4 func: 0
+ V rs: 0 rt: 0x4030000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 04030000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c0af000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0xa i: 0xf000
+ r rs: 0 rt: 10 rd: 30 sh: 0 func: 0
+ V rs: 0 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 40300000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x10a5024>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x8 rt: 0xa i: 0x5024
+ r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24
+ V rs: 0x40300000 rt: 0xf0000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 40300000 09: 00000003 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa5702>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0xa i: 0x5702
+ r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2
+ V rs: 0 rt: 0x40000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 40300000 09: 00000003 10: 40000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+0mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x294b000a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xa (slti)
+ i rs: 0xa rt: 0xb i: 0xa
+ r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa
+ V rs: 0x4 rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 40300000 09: 00000003 10: 00000004 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11600004>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0xb rt: 0 i: 0x4
+ r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4
+ V rs: 0x1 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 40300000 09: 00000003 10: 00000004 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 40300000 09: 00000003 10: 00000004 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x214a0030>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0xa rt: 0xa i: 0x30
+ r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30
+ V rs: 0x4 rt: 0x4
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 40300000 09: 00000003 10: 00000004 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0010a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0x10a
+ r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa
+ V rs: 0xbfc0015c rt: 0xbeee
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 40300000 09: 00000003 10: 00000034 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 40300000 09: 00000003 10: 00000034 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa34a0000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0xa i: 0
+ r rs: 26 rt: 10 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x34
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 40300000 09: 00000003 10: 00000034 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x34 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2129ffff>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0x9 rt: 0x9 i: 0xffff
+ r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f
+ V rs: 0x3 rt: 0x3
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 40300000 09: 00000003 10: 00000034 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x1d20fff3>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x7 (bgtz)
+ i rs: 0x9 rt: 0 i: 0xfff3
+ r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33
+ V rs: 0x2 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 40300000 09: 00000002 10: 00000034 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x84100>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0x8 i: 0x4100
+ r rs: 0 rt: 8 rd: 8 sh: 4 func: 0
+ V rs: 0 rt: 0x40300000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 40300000 09: 00000002 10: 00000034 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c0af000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0xa i: 0xf000
+ r rs: 0 rt: 10 rd: 30 sh: 0 func: 0
+ V rs: 0 rt: 0x34
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 03000000 09: 00000002 10: 00000034 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x10a5024>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x8 rt: 0xa i: 0x5024
+ r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24
+ V rs: 0x3000000 rt: 0xf0000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 03000000 09: 00000002 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa5702>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0xa i: 0x5702
+ r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 03000000 09: 00000002 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+4mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x294b000a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xa (slti)
+ i rs: 0xa rt: 0xb i: 0xa
+ r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa
+ V rs: 0 rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 03000000 09: 00000002 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11600004>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0xb rt: 0 i: 0x4
+ r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4
+ V rs: 0x1 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 03000000 09: 00000002 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 03000000 09: 00000002 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x214a0030>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0xa rt: 0xa i: 0x30
+ r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 03000000 09: 00000002 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0010a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0x10a
+ r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa
+ V rs: 0xbfc0015c rt: 0xbeee
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 03000000 09: 00000002 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 03000000 09: 00000002 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa34a0000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0xa i: 0
+ r rs: 26 rt: 10 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 03000000 09: 00000002 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2129ffff>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0x9 rt: 0x9 i: 0xffff
+ r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f
+ V rs: 0x2 rt: 0x2
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 03000000 09: 00000002 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x1d20fff3>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x7 (bgtz)
+ i rs: 0x9 rt: 0 i: 0xfff3
+ r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33
+ V rs: 0x1 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 03000000 09: 00000001 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x84100>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0x8 i: 0x4100
+ r rs: 0 rt: 8 rd: 8 sh: 4 func: 0
+ V rs: 0 rt: 0x3000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 03000000 09: 00000001 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c0af000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0xa i: 0xf000
+ r rs: 0 rt: 10 rd: 30 sh: 0 func: 0
+ V rs: 0 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 30000000 09: 00000001 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x10a5024>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x8 rt: 0xa i: 0x5024
+ r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24
+ V rs: 0x30000000 rt: 0xf0000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 30000000 09: 00000001 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa5702>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0xa i: 0x5702
+ r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2
+ V rs: 0 rt: 0x30000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 30000000 09: 00000001 10: 30000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+0mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x294b000a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xa (slti)
+ i rs: 0xa rt: 0xb i: 0xa
+ r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa
+ V rs: 0x3 rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 30000000 09: 00000001 10: 00000003 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11600004>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0xb rt: 0 i: 0x4
+ r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4
+ V rs: 0x1 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 30000000 09: 00000001 10: 00000003 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 30000000 09: 00000001 10: 00000003 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x214a0030>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0xa rt: 0xa i: 0x30
+ r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30
+ V rs: 0x3 rt: 0x3
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 30000000 09: 00000001 10: 00000003 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0010a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0x10a
+ r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa
+ V rs: 0xbfc0015c rt: 0xbeee
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 30000000 09: 00000001 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 30000000 09: 00000001 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa34a0000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0xa i: 0
+ r rs: 26 rt: 10 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x33
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 30000000 09: 00000001 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x33 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2129ffff>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0x9 rt: 0x9 i: 0xffff
+ r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f
+ V rs: 0x1 rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 30000000 09: 00000001 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x1d20fff3>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x7 (bgtz)
+ i rs: 0x9 rt: 0 i: 0xfff3
+ r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 30000000 09: 00000000 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00438 m_ifetch_addr: 0xbfc00434
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x84100>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00434 NPC: 0xbfc00438 Ins: 0x84100
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0x8 i: 0x4100
+ r rs: 0 rt: 8 rd: 8 sh: 4 func: 0
+ V rs: 0 rt: 0x30000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 30000000 09: 00000000 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00438 m_jump_pc: 0xbfc0043c m_ifetch_addr: 0xbfc00438
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3e00008>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00438 NPC: 0xbfc0043c Ins: 0x3e00008
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x1f rt: 0 i: 0x8
+ r rs: 31 rt: 0 rd: 0 sh: 0 func: 0x8
+ V rs: 0xbfc0015c rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc0043c m_jump_pc: 0xbfc0015c m_ifetch_addr: 0xbfc0043c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0043c NPC: 0xbfc0015c Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc0015c m_jump_pc: 0xbfc00160 m_ifetch_addr: 0xbfc0015c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c04bfc0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0015c NPC: 0xbfc00160 Ins: 0x3c04bfc0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0x4 i: 0xbfc0
+ r rs: 0 rt: 4 rd: 23 sh: 31 func: 0
+ V rs: 0 rt: 0x400403
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00160 m_jump_pc: 0xbfc00164 m_ifetch_addr: 0xbfc00160
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+3mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x24840234>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00160 NPC: 0xbfc00164 Ins: 0x24840234
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0x4 rt: 0x4 i: 0x234
+ r rs: 4 rt: 4 rd: 0 sh: 8 func: 0x34
+ V rs: 0xbfc00000 rt: 0xbfc00000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00164 m_jump_pc: 0xbfc00168 m_ifetch_addr: 0xbfc00164
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xff000f0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00164 NPC: 0xbfc00168 Ins: 0xff000f0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x3 (jal)
+ i rs: 0x1f rt: 0x10 i: 0xf0
+ r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x30
+ V rs: 0xbfc0015c rt: 0xbeee
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00168 m_jump_pc: 0xbfc003c0 m_ifetch_addr: 0xbfc00168
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00168 NPC: 0xbfc003c0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c
+mips0 m_next_pc: 0xbfc003c0 m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003c0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x804021>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c0 NPC: 0xbfc003c4 Ins: 0x804021
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x4 rt: 0 i: 0x4021
+ r rs: 4 rt: 0 rd: 8 sh: 0 func: 0x21
+ V rs: 0xbfc00234 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c
+mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x81090000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x20 (lb)
+ i rs: 0x8 rt: 0x9 i: 0
+ r rs: 8 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xbfc00234 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00234 09: 00000000 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_READ @ 0xbfc00234 wdata 0 be 0x1> off: 0 sign_ext: 0x1 dest: gp+0x9
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp valid no error rdata 0x20637020>, 0)
+mips0 setData: <DataRsp valid no error rdata 0x20637020> off: 0 sign_ext: 0x1 dest: r_gp+0x9
+mips0 setData: <DataRsp valid no error rdata 0x20637020> off: 0 count: 0x1 le: 0 old: 0 from_mem: 0x20637020 mask: 0xffffffff new_data: 0x20
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0x9 rt: 0 i: 0x5
+ r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5
+ V rs: 0x20 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00234 09: 00000020 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c
+mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00234 09: 00000020 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c
+mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa3490000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0x9 i: 0
+ r rs: 26 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x20
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00234 09: 00000020 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x20 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0x8 rt: 0x8 i: 0x1
+ r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1
+ V rs: 0xbfc00234 rt: 0xbfc00234
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00234 09: 00000020 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c
+mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf000f1>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0xf1
+ r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31
+ V rs: 0xbfc0016c rt: 0xbeee
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00235 09: 00000020 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c
+mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00235 09: 00000020 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c
+mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x81090000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x20 (lb)
+ i rs: 0x8 rt: 0x9 i: 0
+ r rs: 8 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xbfc00235 rt: 0x20
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00235 09: 00000020 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_READ @ 0xbfc00234 wdata 0 be 0x2> off: 0x1 sign_ext: 0x1 dest: gp+0x9
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp valid no error rdata 0x20637020>, 0)
+mips0 setData: <DataRsp valid no error rdata 0x20637020> off: 0 sign_ext: 0x1 dest: r_gp+0x9
+mips0 setData: <DataRsp valid no error rdata 0x20637020> off: 0 count: 0x1 le: 0x1 old: 0x20 from_mem: 0x20637020 mask: 0xffffffff new_data: 0x70
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1
+ mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0x9 rt: 0 i: 0x5
+ r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5
+ V rs: 0x70 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00235 09: 00000070 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c
+mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00235 09: 00000070 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c
+mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa3490000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0x9 i: 0
+ r rs: 26 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x70
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00235 09: 00000070 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x70 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0x8 rt: 0x8 i: 0x1
+ r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1
+ V rs: 0xbfc00235 rt: 0xbfc00235
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00235 09: 00000070 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c
+mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf000f1>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0xf1
+ r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31
+ V rs: 0xbfc0016c rt: 0xbeee
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00236 09: 00000070 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c
+mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00236 09: 00000070 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c
+mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x81090000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x20 (lb)
+ i rs: 0x8 rt: 0x9 i: 0
+ r rs: 8 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xbfc00236 rt: 0x70
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00236 09: 00000070 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_READ @ 0xbfc00234 wdata 0 be 0x4> off: 0x2 sign_ext: 0x1 dest: gp+0x9
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp valid no error rdata 0x20637020>, 0)
+mips0 setData: <DataRsp valid no error rdata 0x20637020> off: 0 sign_ext: 0x1 dest: r_gp+0x9
+mips0 setData: <DataRsp valid no error rdata 0x20637020> off: 0 count: 0x1 le: 0x2 old: 0x70 from_mem: 0x20637020 mask: 0xffffffff new_data: 0x63
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0x9 rt: 0 i: 0x5
+ r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5
+ V rs: 0x63 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00236 09: 00000063 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c
+mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+pmips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00236 09: 00000063 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c
+mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa3490000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0x9 i: 0
+ r rs: 26 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x63
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00236 09: 00000063 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x63 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0x8 rt: 0x8 i: 0x1
+ r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1
+ V rs: 0xbfc00236 rt: 0xbfc00236
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00236 09: 00000063 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c
+mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf000f1>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0xf1
+ r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31
+ V rs: 0xbfc0016c rt: 0xbeee
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00237 09: 00000063 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c
+mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00237 09: 00000063 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c
+mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x81090000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x20 (lb)
+ i rs: 0x8 rt: 0x9 i: 0
+ r rs: 8 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xbfc00237 rt: 0x63
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00237 09: 00000063 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_READ @ 0xbfc00234 wdata 0 be 0x8> off: 0x3 sign_ext: 0x1 dest: gp+0x9
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp valid no error rdata 0x20637020>, 0)
+mips0 setData: <DataRsp valid no error rdata 0x20637020> off: 0 sign_ext: 0x1 dest: r_gp+0x9
+mips0 setData: <DataRsp valid no error rdata 0x20637020> off: 0 count: 0x1 le: 0x3 old: 0x63 from_mem: 0x20637020 mask: 0xffffffff new_data: 0x20
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0x9 rt: 0 i: 0x5
+ r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5
+ V rs: 0x20 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00237 09: 00000020 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c
+mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00237 09: 00000020 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c
+mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+cmips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa3490000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0x9 i: 0
+ r rs: 26 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x20
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00237 09: 00000020 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x20 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0x8 rt: 0x8 i: 0x1
+ r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1
+ V rs: 0xbfc00237 rt: 0xbfc00237
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00237 09: 00000020 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c
+mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf000f1>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0xf1
+ r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31
+ V rs: 0xbfc0016c rt: 0xbeee
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00238 09: 00000020 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c
+mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00238 09: 00000020 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c
+mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x81090000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x20 (lb)
+ i rs: 0x8 rt: 0x9 i: 0
+ r rs: 8 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xbfc00238 rt: 0x20
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00238 09: 00000020 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_READ @ 0xbfc00238 wdata 0 be 0x1> off: 0 sign_ext: 0x1 dest: gp+0x9
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp valid no error rdata 0x61622000>, 0)
+mips0 setData: <DataRsp valid no error rdata 0x61622000> off: 0 sign_ext: 0x1 dest: r_gp+0x9
+mips0 setData: <DataRsp valid no error rdata 0x61622000> off: 0 count: 0x1 le: 0 old: 0x20 from_mem: 0x61622000 mask: 0xffffffff new_data: 0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0x9 rt: 0 i: 0x5
+ r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00238 09: 00000000 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c
+mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003e0 m_ifetch_addr: 0xbfc003cc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003cc NPC: 0xbfc003e0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00238 09: 00000000 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c
+mips0 m_next_pc: 0xbfc003e0 m_jump_pc: 0xbfc003e4 m_ifetch_addr: 0xbfc003e0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3e00008>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003e0 NPC: 0xbfc003e4 Ins: 0x3e00008
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x1f rt: 0 i: 0x8
+ r rs: 31 rt: 0 rd: 0 sh: 0 func: 0x8
+ V rs: 0xbfc0016c rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00238 09: 00000000 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c
+mips0 m_next_pc: 0xbfc003e4 m_jump_pc: 0xbfc0016c m_ifetch_addr: 0xbfc003e4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+ mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003e4 NPC: 0xbfc0016c Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00238 09: 00000000 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c
+mips0 m_next_pc: 0xbfc0016c m_jump_pc: 0xbfc00170 m_ifetch_addr: 0xbfc0016c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x40047000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0016c NPC: 0xbfc00170 Ins: 0x40047000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x10 (cop0)
+ i rs: 0 rt: 0x4 i: 0x7000
+ r rs: 0 rt: 4 rd: 14 sh: 0 func: 0
+ V rs: 0 rt: 0xbfc00234
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00238 09: 00000000 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c
+mips0 m_next_pc: 0xbfc00170 m_jump_pc: 0xbfc00174 m_ifetch_addr: 0xbfc00170
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xff000fa>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00170 NPC: 0xbfc00174 Ins: 0xff000fa
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x3 (jal)
+ i rs: 0x1f rt: 0x10 i: 0xfa
+ r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x3a
+ V rs: 0xbfc0016c rt: 0xbeee
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00238 09: 00000000 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c
+mips0 m_next_pc: 0xbfc00174 m_jump_pc: 0xbfc003e8 m_ifetch_addr: 0xbfc00174
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00174 NPC: 0xbfc003e8 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00238 09: 00000000 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc003e8 m_jump_pc: 0xbfc003ec m_ifetch_addr: 0xbfc003e8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x804021>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003e8 NPC: 0xbfc003ec Ins: 0x804021
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x4 rt: 0 i: 0x4021
+ r rs: 4 rt: 0 rd: 8 sh: 0 func: 0x21
+ V rs: 0xbfc00068 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00238 09: 00000000 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc003ec m_jump_pc: 0xbfc003f0 m_ifetch_addr: 0xbfc003ec
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x24090030>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003ec NPC: 0xbfc003f0 Ins: 0x24090030
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0 rt: 0x9 i: 0x30
+ r rs: 0 rt: 9 rd: 0 sh: 0 func: 0x30
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00068 09: 00000000 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc003f0 m_jump_pc: 0xbfc003f4 m_ifetch_addr: 0xbfc003f0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa3490000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003f0 NPC: 0xbfc003f4 Ins: 0xa3490000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0x9 i: 0
+ r rs: 26 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00068 09: 00000030 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc003f4 m_jump_pc: 0xbfc003f8 m_ifetch_addr: 0xbfc003f4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x24090078>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc003f4 NPC: 0xbfc003f8 Ins: 0x24090078
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0 rt: 0x9 i: 0x78
+ r rs: 0 rt: 9 rd: 0 sh: 1 func: 0x38
+ V rs: 0 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00068 09: 00000030 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc003f8 m_jump_pc: 0xbfc003fc m_ifetch_addr: 0xbfc003f8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa3490000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003f8 NPC: 0xbfc003fc Ins: 0xa3490000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0x9 i: 0
+ r rs: 26 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x78
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00068 09: 00000078 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x78 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc003fc m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc003fc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x24090008>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc003fc NPC: 0xbfc00400 Ins: 0x24090008
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0 rt: 0x9 i: 0x8
+ r rs: 0 rt: 9 rd: 0 sh: 0 func: 0x8
+ V rs: 0 rt: 0x78
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00068 09: 00000078 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c0af000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0xa i: 0xf000
+ r rs: 0 rt: 10 rd: 30 sh: 0 func: 0
+ V rs: 0 rt: 0x33
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00068 09: 00000008 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x10a5024>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x8 rt: 0xa i: 0x5024
+ r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24
+ V rs: 0xbfc00068 rt: 0xf0000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00068 09: 00000008 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa5702>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0xa i: 0x5702
+ r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2
+ V rs: 0 rt: 0xb0000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00068 09: 00000008 10: b0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+0mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x294b000a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xa (slti)
+ i rs: 0xa rt: 0xb i: 0xa
+ r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa
+ V rs: 0xb rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00068 09: 00000008 10: 0000000b 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11600004>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0xb rt: 0 i: 0x4
+ r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00068 09: 00000008 10: 0000000b 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00424 m_ifetch_addr: 0xbfc00414
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00414 NPC: 0xbfc00424 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00068 09: 00000008 10: 0000000b 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00424 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00424
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x214a0037>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00424 NPC: 0xbfc00428 Ins: 0x214a0037
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0xa rt: 0xa i: 0x37
+ r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x37
+ V rs: 0xb rt: 0xb
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00068 09: 00000008 10: 0000000b 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa34a0000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0xa i: 0
+ r rs: 26 rt: 10 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x42
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00068 09: 00000008 10: 00000042 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x42 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2129ffff>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0x9 rt: 0x9 i: 0xffff
+ r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f
+ V rs: 0x8 rt: 0x8
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00068 09: 00000008 10: 00000042 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x1d20fff3>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x7 (bgtz)
+ i rs: 0x9 rt: 0 i: 0xfff3
+ r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33
+ V rs: 0x7 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00068 09: 00000007 10: 00000042 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x84100>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0x8 i: 0x4100
+ r rs: 0 rt: 8 rd: 8 sh: 4 func: 0
+ V rs: 0 rt: 0xbfc00068
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00068 09: 00000007 10: 00000042 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c0af000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0xa i: 0xf000
+ r rs: 0 rt: 10 rd: 30 sh: 0 func: 0
+ V rs: 0 rt: 0x42
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000
+ 08: fc000680 09: 00000007 10: 00000042 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x10a5024>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x8 rt: 0xa i: 0x5024
+ r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24
+ V rs: 0xfc000680 rt: 0xf0000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000
+ 08: fc000680 09: 00000007 10: f0000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+xmips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa5702>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0xa i: 0x5702
+ r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2
+ V rs: 0 rt: 0xf0000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000
+ 08: fc000680 09: 00000007 10: f0000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x294b000a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xa (slti)
+ i rs: 0xa rt: 0xb i: 0xa
+ r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa
+ V rs: 0xf rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000
+ 08: fc000680 09: 00000007 10: 0000000f 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11600004>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0xb rt: 0 i: 0x4
+ r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000
+ 08: fc000680 09: 00000007 10: 0000000f 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00424 m_ifetch_addr: 0xbfc00414
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00414 NPC: 0xbfc00424 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000
+ 08: fc000680 09: 00000007 10: 0000000f 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00424 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00424
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x214a0037>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00424 NPC: 0xbfc00428 Ins: 0x214a0037
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0xa rt: 0xa i: 0x37
+ r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x37
+ V rs: 0xf rt: 0xf
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000
+ 08: fc000680 09: 00000007 10: 0000000f 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa34a0000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0xa i: 0
+ r rs: 26 rt: 10 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x46
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000
+ 08: fc000680 09: 00000007 10: 00000046 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x46 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2129ffff>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0x9 rt: 0x9 i: 0xffff
+ r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f
+ V rs: 0x7 rt: 0x7
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000
+ 08: fc000680 09: 00000007 10: 00000046 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x1d20fff3>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x7 (bgtz)
+ i rs: 0x9 rt: 0 i: 0xfff3
+ r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33
+ V rs: 0x6 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000
+ 08: fc000680 09: 00000006 10: 00000046 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x84100>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0x8 i: 0x4100
+ r rs: 0 rt: 8 rd: 8 sh: 4 func: 0
+ V rs: 0 rt: 0xfc000680
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000
+ 08: fc000680 09: 00000006 10: 00000046 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c0af000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0xa i: 0xf000
+ r rs: 0 rt: 10 rd: 30 sh: 0 func: 0
+ V rs: 0 rt: 0x46
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000
+ 08: c0006800 09: 00000006 10: 00000046 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+Bmips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x10a5024>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x8 rt: 0xa i: 0x5024
+ r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24
+ V rs: 0xc0006800 rt: 0xf0000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000
+ 08: c0006800 09: 00000006 10: f0000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa5702>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0xa i: 0x5702
+ r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2
+ V rs: 0 rt: 0xc0000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000
+ 08: c0006800 09: 00000006 10: c0000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x294b000a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xa (slti)
+ i rs: 0xa rt: 0xb i: 0xa
+ r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa
+ V rs: 0xc rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000
+ 08: c0006800 09: 00000006 10: 0000000c 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11600004>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0xb rt: 0 i: 0x4
+ r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000
+ 08: c0006800 09: 00000006 10: 0000000c 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00424 m_ifetch_addr: 0xbfc00414
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00414 NPC: 0xbfc00424 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000
+ 08: c0006800 09: 00000006 10: 0000000c 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00424 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00424
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x214a0037>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00424 NPC: 0xbfc00428 Ins: 0x214a0037
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0xa rt: 0xa i: 0x37
+ r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x37
+ V rs: 0xc rt: 0xc
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000
+ 08: c0006800 09: 00000006 10: 0000000c 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa34a0000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0xa i: 0
+ r rs: 26 rt: 10 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x43
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000
+ 08: c0006800 09: 00000006 10: 00000043 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x43 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2129ffff>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0x9 rt: 0x9 i: 0xffff
+ r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f
+ V rs: 0x6 rt: 0x6
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000
+ 08: c0006800 09: 00000006 10: 00000043 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x1d20fff3>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x7 (bgtz)
+ i rs: 0x9 rt: 0 i: 0xfff3
+ r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33
+ V rs: 0x5 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000
+ 08: c0006800 09: 00000005 10: 00000043 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x84100>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0x8 i: 0x4100
+ r rs: 0 rt: 8 rd: 8 sh: 4 func: 0
+ V rs: 0 rt: 0xc0006800
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000
+ 08: c0006800 09: 00000005 10: 00000043 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+Fmips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c0af000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0xa i: 0xf000
+ r rs: 0 rt: 10 rd: 30 sh: 0 func: 0
+ V rs: 0 rt: 0x43
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000
+ 08: 00068000 09: 00000005 10: 00000043 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x10a5024>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x8 rt: 0xa i: 0x5024
+ r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24
+ V rs: 0x68000 rt: 0xf0000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000
+ 08: 00068000 09: 00000005 10: f0000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa5702>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0xa i: 0x5702
+ r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000
+ 08: 00068000 09: 00000005 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x294b000a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xa (slti)
+ i rs: 0xa rt: 0xb i: 0xa
+ r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000
+ 08: 00068000 09: 00000005 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11600004>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0xb rt: 0 i: 0x4
+ r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4
+ V rs: 0x1 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000
+ 08: 00068000 09: 00000005 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000
+ 08: 00068000 09: 00000005 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x214a0030>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0xa rt: 0xa i: 0x30
+ r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000
+ 08: 00068000 09: 00000005 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0010a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0x10a
+ r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa
+ V rs: 0xbfc00178 rt: 0xbeee
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000
+ 08: 00068000 09: 00000005 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000
+ 08: 00068000 09: 00000005 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa34a0000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0xa i: 0
+ r rs: 26 rt: 10 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000
+ 08: 00068000 09: 00000005 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+Cmips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2129ffff>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0x9 rt: 0x9 i: 0xffff
+ r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f
+ V rs: 0x5 rt: 0x5
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000
+ 08: 00068000 09: 00000005 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x1d20fff3>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x7 (bgtz)
+ i rs: 0x9 rt: 0 i: 0xfff3
+ r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33
+ V rs: 0x4 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000
+ 08: 00068000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x84100>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0x8 i: 0x4100
+ r rs: 0 rt: 8 rd: 8 sh: 4 func: 0
+ V rs: 0 rt: 0x68000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000
+ 08: 00068000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c0af000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0xa i: 0xf000
+ r rs: 0 rt: 10 rd: 30 sh: 0 func: 0
+ V rs: 0 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000
+ 08: 00680000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x10a5024>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x8 rt: 0xa i: 0x5024
+ r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24
+ V rs: 0x680000 rt: 0xf0000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000
+ 08: 00680000 09: 00000004 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa5702>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0xa i: 0x5702
+ r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000
+ 08: 00680000 09: 00000004 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x294b000a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xa (slti)
+ i rs: 0xa rt: 0xb i: 0xa
+ r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa
+ V rs: 0 rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000
+ 08: 00680000 09: 00000004 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11600004>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0xb rt: 0 i: 0x4
+ r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4
+ V rs: 0x1 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000
+ 08: 00680000 09: 00000004 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000
+ 08: 00680000 09: 00000004 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x214a0030>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0xa rt: 0xa i: 0x30
+ r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000
+ 08: 00680000 09: 00000004 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+0mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0010a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0x10a
+ r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa
+ V rs: 0xbfc00178 rt: 0xbeee
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000
+ 08: 00680000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000
+ 08: 00680000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa34a0000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0xa i: 0
+ r rs: 26 rt: 10 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000
+ 08: 00680000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2129ffff>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0x9 rt: 0x9 i: 0xffff
+ r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f
+ V rs: 0x4 rt: 0x4
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000
+ 08: 00680000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x1d20fff3>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x7 (bgtz)
+ i rs: 0x9 rt: 0 i: 0xfff3
+ r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33
+ V rs: 0x3 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000
+ 08: 00680000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x84100>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0x8 i: 0x4100
+ r rs: 0 rt: 8 rd: 8 sh: 4 func: 0
+ V rs: 0 rt: 0x680000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000
+ 08: 00680000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c0af000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0xa i: 0xf000
+ r rs: 0 rt: 10 rd: 30 sh: 0 func: 0
+ V rs: 0 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000
+ 08: 06800000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x10a5024>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x8 rt: 0xa i: 0x5024
+ r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24
+ V rs: 0x6800000 rt: 0xf0000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000
+ 08: 06800000 09: 00000003 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa5702>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0xa i: 0x5702
+ r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000
+ 08: 06800000 09: 00000003 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x294b000a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xa (slti)
+ i rs: 0xa rt: 0xb i: 0xa
+ r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa
+ V rs: 0 rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000
+ 08: 06800000 09: 00000003 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+0mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11600004>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0xb rt: 0 i: 0x4
+ r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4
+ V rs: 0x1 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000
+ 08: 06800000 09: 00000003 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000
+ 08: 06800000 09: 00000003 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x214a0030>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0xa rt: 0xa i: 0x30
+ r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000
+ 08: 06800000 09: 00000003 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0010a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0x10a
+ r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa
+ V rs: 0xbfc00178 rt: 0xbeee
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000
+ 08: 06800000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000
+ 08: 06800000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa34a0000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0xa i: 0
+ r rs: 26 rt: 10 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000
+ 08: 06800000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2129ffff>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0x9 rt: 0x9 i: 0xffff
+ r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f
+ V rs: 0x3 rt: 0x3
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000
+ 08: 06800000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x1d20fff3>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x7 (bgtz)
+ i rs: 0x9 rt: 0 i: 0xfff3
+ r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33
+ V rs: 0x2 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000
+ 08: 06800000 09: 00000002 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x84100>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0x8 i: 0x4100
+ r rs: 0 rt: 8 rd: 8 sh: 4 func: 0
+ V rs: 0 rt: 0x6800000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000
+ 08: 06800000 09: 00000002 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c0af000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0xa i: 0xf000
+ r rs: 0 rt: 10 rd: 30 sh: 0 func: 0
+ V rs: 0 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000
+ 08: 68000000 09: 00000002 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x10a5024>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x8 rt: 0xa i: 0x5024
+ r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24
+ V rs: 0x68000000 rt: 0xf0000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000
+ 08: 68000000 09: 00000002 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa5702>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0xa i: 0x5702
+ r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2
+ V rs: 0 rt: 0x60000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000
+ 08: 68000000 09: 00000002 10: 60000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+0mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x294b000a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xa (slti)
+ i rs: 0xa rt: 0xb i: 0xa
+ r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa
+ V rs: 0x6 rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000
+ 08: 68000000 09: 00000002 10: 00000006 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11600004>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0xb rt: 0 i: 0x4
+ r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4
+ V rs: 0x1 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000
+ 08: 68000000 09: 00000002 10: 00000006 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000
+ 08: 68000000 09: 00000002 10: 00000006 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x214a0030>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0xa rt: 0xa i: 0x30
+ r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30
+ V rs: 0x6 rt: 0x6
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000
+ 08: 68000000 09: 00000002 10: 00000006 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0010a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0x10a
+ r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa
+ V rs: 0xbfc00178 rt: 0xbeee
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000
+ 08: 68000000 09: 00000002 10: 00000036 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000
+ 08: 68000000 09: 00000002 10: 00000036 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa34a0000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0xa i: 0
+ r rs: 26 rt: 10 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x36
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000
+ 08: 68000000 09: 00000002 10: 00000036 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x36 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2129ffff>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0x9 rt: 0x9 i: 0xffff
+ r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f
+ V rs: 0x2 rt: 0x2
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000
+ 08: 68000000 09: 00000002 10: 00000036 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x1d20fff3>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x7 (bgtz)
+ i rs: 0x9 rt: 0 i: 0xfff3
+ r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33
+ V rs: 0x1 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000
+ 08: 68000000 09: 00000001 10: 00000036 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x84100>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0x8 i: 0x4100
+ r rs: 0 rt: 8 rd: 8 sh: 4 func: 0
+ V rs: 0 rt: 0x68000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000
+ 08: 68000000 09: 00000001 10: 00000036 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c0af000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0xa i: 0xf000
+ r rs: 0 rt: 10 rd: 30 sh: 0 func: 0
+ V rs: 0 rt: 0x36
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000
+ 08: 80000000 09: 00000001 10: 00000036 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x10a5024>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x8 rt: 0xa i: 0x5024
+ r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24
+ V rs: 0x80000000 rt: 0xf0000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000
+ 08: 80000000 09: 00000001 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa5702>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0xa i: 0x5702
+ r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2
+ V rs: 0 rt: 0x80000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000
+ 08: 80000000 09: 00000001 10: 80000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+6mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x294b000a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xa (slti)
+ i rs: 0xa rt: 0xb i: 0xa
+ r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa
+ V rs: 0x8 rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000
+ 08: 80000000 09: 00000001 10: 00000008 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11600004>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0xb rt: 0 i: 0x4
+ r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4
+ V rs: 0x1 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000
+ 08: 80000000 09: 00000001 10: 00000008 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000
+ 08: 80000000 09: 00000001 10: 00000008 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x214a0030>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0xa rt: 0xa i: 0x30
+ r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30
+ V rs: 0x8 rt: 0x8
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000
+ 08: 80000000 09: 00000001 10: 00000008 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0010a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0x10a
+ r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa
+ V rs: 0xbfc00178 rt: 0xbeee
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000
+ 08: 80000000 09: 00000001 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000
+ 08: 80000000 09: 00000001 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa34a0000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0xa i: 0
+ r rs: 26 rt: 10 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x38
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000
+ 08: 80000000 09: 00000001 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x38 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2129ffff>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0x9 rt: 0x9 i: 0xffff
+ r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f
+ V rs: 0x1 rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000
+ 08: 80000000 09: 00000001 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x1d20fff3>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x7 (bgtz)
+ i rs: 0x9 rt: 0 i: 0xfff3
+ r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000
+ 08: 80000000 09: 00000000 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00438 m_ifetch_addr: 0xbfc00434
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x84100>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00434 NPC: 0xbfc00438 Ins: 0x84100
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0x8 i: 0x4100
+ r rs: 0 rt: 8 rd: 8 sh: 4 func: 0
+ V rs: 0 rt: 0x80000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000
+ 08: 80000000 09: 00000000 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00438 m_jump_pc: 0xbfc0043c m_ifetch_addr: 0xbfc00438
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3e00008>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00438 NPC: 0xbfc0043c Ins: 0x3e00008
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x1f rt: 0 i: 0x8
+ r rs: 31 rt: 0 rd: 0 sh: 0 func: 0x8
+ V rs: 0xbfc00178 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc0043c m_jump_pc: 0xbfc00178 m_ifetch_addr: 0xbfc0043c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0043c NPC: 0xbfc00178 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00178 m_jump_pc: 0xbfc0017c m_ifetch_addr: 0xbfc00178
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c04bfc0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00178 NPC: 0xbfc0017c Ins: 0x3c04bfc0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0x4 i: 0xbfc0
+ r rs: 0 rt: 4 rd: 23 sh: 31 func: 0
+ V rs: 0 rt: 0xbfc00068
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00068 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc0017c m_jump_pc: 0xbfc00180 m_ifetch_addr: 0xbfc0017c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+8mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2484022c>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0017c NPC: 0xbfc00180 Ins: 0x2484022c
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0x4 rt: 0x4 i: 0x22c
+ r rs: 4 rt: 4 rd: 0 sh: 8 func: 0x2c
+ V rs: 0xbfc00000 rt: 0xbfc00000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00180 m_jump_pc: 0xbfc00184 m_ifetch_addr: 0xbfc00180
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00180 m_jump_pc: 0xbfc00184 m_ifetch_addr: 0xbfc00180
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00180 m_jump_pc: 0xbfc00184 m_ifetch_addr: 0xbfc00180
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00180 m_jump_pc: 0xbfc00184 m_ifetch_addr: 0xbfc00180
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00180 m_jump_pc: 0xbfc00184 m_ifetch_addr: 0xbfc00180
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00180 m_jump_pc: 0xbfc00184 m_ifetch_addr: 0xbfc00180
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00180 m_jump_pc: 0xbfc00184 m_ifetch_addr: 0xbfc00180
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00180 m_jump_pc: 0xbfc00184 m_ifetch_addr: 0xbfc00180
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00180 m_jump_pc: 0xbfc00184 m_ifetch_addr: 0xbfc00180
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00180 m_jump_pc: 0xbfc00184 m_ifetch_addr: 0xbfc00180
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00180 m_jump_pc: 0xbfc00184 m_ifetch_addr: 0xbfc00180
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00180 m_jump_pc: 0xbfc00184 m_ifetch_addr: 0xbfc00180
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00180 m_jump_pc: 0xbfc00184 m_ifetch_addr: 0xbfc00180
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00180 m_jump_pc: 0xbfc00184 m_ifetch_addr: 0xbfc00180
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00180 m_jump_pc: 0xbfc00184 m_ifetch_addr: 0xbfc00180
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00180 m_jump_pc: 0xbfc00184 m_ifetch_addr: 0xbfc00180
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00180 m_jump_pc: 0xbfc00184 m_ifetch_addr: 0xbfc00180
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00180 m_jump_pc: 0xbfc00184 m_ifetch_addr: 0xbfc00180
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00180 m_jump_pc: 0xbfc00184 m_ifetch_addr: 0xbfc00180
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00180 m_jump_pc: 0xbfc00184 m_ifetch_addr: 0xbfc00180
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00180 m_jump_pc: 0xbfc00184 m_ifetch_addr: 0xbfc00180
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00180 m_jump_pc: 0xbfc00184 m_ifetch_addr: 0xbfc00180
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00180 m_jump_pc: 0xbfc00184 m_ifetch_addr: 0xbfc00180
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00180 m_jump_pc: 0xbfc00184 m_ifetch_addr: 0xbfc00180
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00180 m_jump_pc: 0xbfc00184 m_ifetch_addr: 0xbfc00180
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00180 m_jump_pc: 0xbfc00184 m_ifetch_addr: 0xbfc00180
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00180 m_jump_pc: 0xbfc00184 m_ifetch_addr: 0xbfc00180
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00180 m_jump_pc: 0xbfc00184 m_ifetch_addr: 0xbfc00180
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00180 m_jump_pc: 0xbfc00184 m_ifetch_addr: 0xbfc00180
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00180 m_jump_pc: 0xbfc00184 m_ifetch_addr: 0xbfc00180
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00180 m_jump_pc: 0xbfc00184 m_ifetch_addr: 0xbfc00180
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xff000f0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00180 NPC: 0xbfc00184 Ins: 0xff000f0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x3 (jal)
+ i rs: 0x1f rt: 0x10 i: 0xf0
+ r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x30
+ V rs: 0xbfc00178 rt: 0xbeee
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00184 m_jump_pc: 0xbfc003c0 m_ifetch_addr: 0xbfc00184
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00184 NPC: 0xbfc003c0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 m_next_pc: 0xbfc003c0 m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003c0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x804021>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c0 NPC: 0xbfc003c4 Ins: 0x804021
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x4 rt: 0 i: 0x4021
+ r rs: 4 rt: 0 rd: 8 sh: 0 func: 0x21
+ V rs: 0xbfc0022c rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x81090000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x20 (lb)
+ i rs: 0x8 rt: 0x9 i: 0
+ r rs: 8 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xbfc0022c rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0022c 09: 00000000 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_READ @ 0xbfc0022c wdata 0 be 0x1> off: 0 sign_ext: 0x1 dest: gp+0x9
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp valid no error rdata 0x75616320>, 0)
+mips0 setData: <DataRsp valid no error rdata 0x75616320> off: 0 sign_ext: 0x1 dest: r_gp+0x9
+mips0 setData: <DataRsp valid no error rdata 0x75616320> off: 0 count: 0x1 le: 0 old: 0 from_mem: 0x75616320 mask: 0xffffffff new_data: 0x20
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0x9 rt: 0 i: 0x5
+ r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5
+ V rs: 0x20 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0022c 09: 00000020 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0022c 09: 00000020 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa3490000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0x9 i: 0
+ r rs: 26 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x20
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0022c 09: 00000020 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x20 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0x8 rt: 0x8 i: 0x1
+ r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1
+ V rs: 0xbfc0022c rt: 0xbfc0022c
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0022c 09: 00000020 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf000f1>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0xf1
+ r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31
+ V rs: 0xbfc00188 rt: 0xbeee
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0022d 09: 00000020 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0022d 09: 00000020 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x81090000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x20 (lb)
+ i rs: 0x8 rt: 0x9 i: 0
+ r rs: 8 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xbfc0022d rt: 0x20
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0022d 09: 00000020 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_READ @ 0xbfc0022c wdata 0 be 0x2> off: 0x1 sign_ext: 0x1 dest: gp+0x9
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp valid no error rdata 0x75616320>, 0)
+mips0 setData: <DataRsp valid no error rdata 0x75616320> off: 0 sign_ext: 0x1 dest: r_gp+0x9
+mips0 setData: <DataRsp valid no error rdata 0x75616320> off: 0 count: 0x1 le: 0x1 old: 0x20 from_mem: 0x75616320 mask: 0xffffffff new_data: 0x63
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1
+ mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0x9 rt: 0 i: 0x5
+ r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5
+ V rs: 0x63 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0022d 09: 00000063 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0022d 09: 00000063 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa3490000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0x9 i: 0
+ r rs: 26 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x63
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0022d 09: 00000063 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x63 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0x8 rt: 0x8 i: 0x1
+ r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1
+ V rs: 0xbfc0022d rt: 0xbfc0022d
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0022d 09: 00000063 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf000f1>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0xf1
+ r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31
+ V rs: 0xbfc00188 rt: 0xbeee
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0022e 09: 00000063 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0022e 09: 00000063 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x81090000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x20 (lb)
+ i rs: 0x8 rt: 0x9 i: 0
+ r rs: 8 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xbfc0022e rt: 0x63
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0022e 09: 00000063 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_READ @ 0xbfc0022c wdata 0 be 0x4> off: 0x2 sign_ext: 0x1 dest: gp+0x9
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp valid no error rdata 0x75616320>, 0)
+mips0 setData: <DataRsp valid no error rdata 0x75616320> off: 0 sign_ext: 0x1 dest: r_gp+0x9
+mips0 setData: <DataRsp valid no error rdata 0x75616320> off: 0 count: 0x1 le: 0x2 old: 0x63 from_mem: 0x75616320 mask: 0xffffffff new_data: 0x61
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0x9 rt: 0 i: 0x5
+ r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5
+ V rs: 0x61 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0022e 09: 00000061 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+cmips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0022e 09: 00000061 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa3490000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0x9 i: 0
+ r rs: 26 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x61
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0022e 09: 00000061 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x61 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0x8 rt: 0x8 i: 0x1
+ r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1
+ V rs: 0xbfc0022e rt: 0xbfc0022e
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0022e 09: 00000061 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf000f1>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0xf1
+ r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31
+ V rs: 0xbfc00188 rt: 0xbeee
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0022f 09: 00000061 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0022f 09: 00000061 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x81090000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x20 (lb)
+ i rs: 0x8 rt: 0x9 i: 0
+ r rs: 8 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xbfc0022f rt: 0x61
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0022f 09: 00000061 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_READ @ 0xbfc0022c wdata 0 be 0x8> off: 0x3 sign_ext: 0x1 dest: gp+0x9
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp valid no error rdata 0x75616320>, 0)
+mips0 setData: <DataRsp valid no error rdata 0x75616320> off: 0 sign_ext: 0x1 dest: r_gp+0x9
+mips0 setData: <DataRsp valid no error rdata 0x75616320> off: 0 count: 0x1 le: 0x3 old: 0x61 from_mem: 0x75616320 mask: 0xffffffff new_data: 0x75
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0x9 rt: 0 i: 0x5
+ r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5
+ V rs: 0x75 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0022f 09: 00000075 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0022f 09: 00000075 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+amips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa3490000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0x9 i: 0
+ r rs: 26 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x75
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0022f 09: 00000075 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x75 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0x8 rt: 0x8 i: 0x1
+ r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1
+ V rs: 0xbfc0022f rt: 0xbfc0022f
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0022f 09: 00000075 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf000f1>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0xf1
+ r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31
+ V rs: 0xbfc00188 rt: 0xbeee
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00230 09: 00000075 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00230 09: 00000075 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x81090000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x20 (lb)
+ i rs: 0x8 rt: 0x9 i: 0
+ r rs: 8 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xbfc00230 rt: 0x75
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00230 09: 00000075 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_READ @ 0xbfc00230 wdata 0 be 0x1> off: 0 sign_ext: 0x1 dest: gp+0x9
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp valid no error rdata 0x206573>, 0)
+mips0 setData: <DataRsp valid no error rdata 0x206573> off: 0 sign_ext: 0x1 dest: r_gp+0x9
+mips0 setData: <DataRsp valid no error rdata 0x206573> off: 0 count: 0x1 le: 0 old: 0x75 from_mem: 0x206573 mask: 0xffffffff new_data: 0x73
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0x9 rt: 0 i: 0x5
+ r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5
+ V rs: 0x73 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00230 09: 00000073 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00230 09: 00000073 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa3490000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0x9 i: 0
+ r rs: 26 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x73
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00230 09: 00000073 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x73 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+umips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0x8 rt: 0x8 i: 0x1
+ r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1
+ V rs: 0xbfc00230 rt: 0xbfc00230
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00230 09: 00000073 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf000f1>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0xf1
+ r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31
+ V rs: 0xbfc00188 rt: 0xbeee
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00231 09: 00000073 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00231 09: 00000073 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x81090000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x20 (lb)
+ i rs: 0x8 rt: 0x9 i: 0
+ r rs: 8 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xbfc00231 rt: 0x73
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00231 09: 00000073 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_READ @ 0xbfc00230 wdata 0 be 0x2> off: 0x1 sign_ext: 0x1 dest: gp+0x9
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp valid no error rdata 0x206573>, 0)
+mips0 setData: <DataRsp valid no error rdata 0x206573> off: 0 sign_ext: 0x1 dest: r_gp+0x9
+mips0 setData: <DataRsp valid no error rdata 0x206573> off: 0 count: 0x1 le: 0x1 old: 0x73 from_mem: 0x206573 mask: 0xffffffff new_data: 0x65
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0x9 rt: 0 i: 0x5
+ r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5
+ V rs: 0x65 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00231 09: 00000065 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00231 09: 00000065 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa3490000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0x9 i: 0
+ r rs: 26 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x65
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00231 09: 00000065 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x65 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+smips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0x8 rt: 0x8 i: 0x1
+ r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1
+ V rs: 0xbfc00231 rt: 0xbfc00231
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00231 09: 00000065 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf000f1>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0xf1
+ r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31
+ V rs: 0xbfc00188 rt: 0xbeee
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00232 09: 00000065 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00232 09: 00000065 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x81090000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x20 (lb)
+ i rs: 0x8 rt: 0x9 i: 0
+ r rs: 8 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xbfc00232 rt: 0x65
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00232 09: 00000065 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_READ @ 0xbfc00230 wdata 0 be 0x4> off: 0x2 sign_ext: 0x1 dest: gp+0x9
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp valid no error rdata 0x206573>, 0)
+mips0 setData: <DataRsp valid no error rdata 0x206573> off: 0 sign_ext: 0x1 dest: r_gp+0x9
+mips0 setData: <DataRsp valid no error rdata 0x206573> off: 0 count: 0x1 le: 0x2 old: 0x65 from_mem: 0x206573 mask: 0xffffffff new_data: 0x20
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0x9 rt: 0 i: 0x5
+ r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5
+ V rs: 0x20 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00232 09: 00000020 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00232 09: 00000020 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa3490000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0x9 i: 0
+ r rs: 26 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x20
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00232 09: 00000020 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x20 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+emips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0x8 rt: 0x8 i: 0x1
+ r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1
+ V rs: 0xbfc00232 rt: 0xbfc00232
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00232 09: 00000020 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf000f1>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0xf1
+ r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31
+ V rs: 0xbfc00188 rt: 0xbeee
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00233 09: 00000020 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00233 09: 00000020 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x81090000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x20 (lb)
+ i rs: 0x8 rt: 0x9 i: 0
+ r rs: 8 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xbfc00233 rt: 0x20
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00233 09: 00000020 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_READ @ 0xbfc00230 wdata 0 be 0x8> off: 0x3 sign_ext: 0x1 dest: gp+0x9
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp valid no error rdata 0x206573>, 0)
+mips0 setData: <DataRsp valid no error rdata 0x206573> off: 0 sign_ext: 0x1 dest: r_gp+0x9
+mips0 setData: <DataRsp valid no error rdata 0x206573> off: 0 count: 0x1 le: 0x3 old: 0x20 from_mem: 0x206573 mask: 0xffffffff new_data: 0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0x9 rt: 0 i: 0x5
+ r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00233 09: 00000000 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003e0 m_ifetch_addr: 0xbfc003cc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003cc NPC: 0xbfc003e0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00233 09: 00000000 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 m_next_pc: 0xbfc003e0 m_jump_pc: 0xbfc003e4 m_ifetch_addr: 0xbfc003e0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3e00008>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003e0 NPC: 0xbfc003e4 Ins: 0x3e00008
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x1f rt: 0 i: 0x8
+ r rs: 31 rt: 0 rd: 0 sh: 0 func: 0x8
+ V rs: 0xbfc00188 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00233 09: 00000000 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 m_next_pc: 0xbfc003e4 m_jump_pc: 0xbfc00188 m_ifetch_addr: 0xbfc003e4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+ mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003e4 NPC: 0xbfc00188 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00233 09: 00000000 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 m_next_pc: 0xbfc00188 m_jump_pc: 0xbfc0018c m_ifetch_addr: 0xbfc00188
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x40046800>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00188 NPC: 0xbfc0018c Ins: 0x40046800
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x10 (cop0)
+ i rs: 0 rt: 0x4 i: 0x6800
+ r rs: 0 rt: 4 rd: 13 sh: 0 func: 0
+ V rs: 0 rt: 0xbfc0022c
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00233 09: 00000000 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 m_next_pc: 0xbfc0018c m_jump_pc: 0xbfc00190 m_ifetch_addr: 0xbfc0018c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xff000fa>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0018c NPC: 0xbfc00190 Ins: 0xff000fa
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x3 (jal)
+ i rs: 0x1f rt: 0x10 i: 0xfa
+ r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x3a
+ V rs: 0xbfc00188 rt: 0xbeee
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00233 09: 00000000 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 m_next_pc: 0xbfc00190 m_jump_pc: 0xbfc003e8 m_ifetch_addr: 0xbfc00190
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00190 NPC: 0xbfc003e8 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00233 09: 00000000 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc003e8 m_jump_pc: 0xbfc003ec m_ifetch_addr: 0xbfc003e8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x804021>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003e8 NPC: 0xbfc003ec Ins: 0x804021
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x4 rt: 0 i: 0x4021
+ r rs: 4 rt: 0 rd: 8 sh: 0 func: 0x21
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00233 09: 00000000 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc003ec m_jump_pc: 0xbfc003f0 m_ifetch_addr: 0xbfc003ec
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x24090030>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003ec NPC: 0xbfc003f0 Ins: 0x24090030
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0 rt: 0x9 i: 0x30
+ r rs: 0 rt: 9 rd: 0 sh: 0 func: 0x30
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc003f0 m_jump_pc: 0xbfc003f4 m_ifetch_addr: 0xbfc003f0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa3490000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003f0 NPC: 0xbfc003f4 Ins: 0xa3490000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0x9 i: 0
+ r rs: 26 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000030 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc003f4 m_jump_pc: 0xbfc003f8 m_ifetch_addr: 0xbfc003f4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x24090078>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc003f4 NPC: 0xbfc003f8 Ins: 0x24090078
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0 rt: 0x9 i: 0x78
+ r rs: 0 rt: 9 rd: 0 sh: 1 func: 0x38
+ V rs: 0 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000030 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc003f8 m_jump_pc: 0xbfc003fc m_ifetch_addr: 0xbfc003f8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa3490000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003f8 NPC: 0xbfc003fc Ins: 0xa3490000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0x9 i: 0
+ r rs: 26 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x78
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000078 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x78 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc003fc m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc003fc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x24090008>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc003fc NPC: 0xbfc00400 Ins: 0x24090008
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0 rt: 0x9 i: 0x8
+ r rs: 0 rt: 9 rd: 0 sh: 0 func: 0x8
+ V rs: 0 rt: 0x78
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000078 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c0af000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0xa i: 0xf000
+ r rs: 0 rt: 10 rd: 30 sh: 0 func: 0
+ V rs: 0 rt: 0x38
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000008 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x10a5024>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x8 rt: 0xa i: 0x5024
+ r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24
+ V rs: 0 rt: 0xf0000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000008 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa5702>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0xa i: 0x5702
+ r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000008 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+0mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x294b000a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xa (slti)
+ i rs: 0xa rt: 0xb i: 0xa
+ r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa
+ V rs: 0 rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000008 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11600004>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0xb rt: 0 i: 0x4
+ r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4
+ V rs: 0x1 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000008 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000008 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x214a0030>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0xa rt: 0xa i: 0x30
+ r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000008 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0010a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0x10a
+ r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa
+ V rs: 0xbfc00194 rt: 0xbeee
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000008 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000008 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa34a0000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0xa i: 0
+ r rs: 26 rt: 10 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000008 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2129ffff>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0x9 rt: 0x9 i: 0xffff
+ r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f
+ V rs: 0x8 rt: 0x8
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000008 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x1d20fff3>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x7 (bgtz)
+ i rs: 0x9 rt: 0 i: 0xfff3
+ r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33
+ V rs: 0x7 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000007 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x84100>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0x8 i: 0x4100
+ r rs: 0 rt: 8 rd: 8 sh: 4 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000007 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+xmips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c0af000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0xa i: 0xf000
+ r rs: 0 rt: 10 rd: 30 sh: 0 func: 0
+ V rs: 0 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000007 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x10a5024>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x8 rt: 0xa i: 0x5024
+ r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24
+ V rs: 0 rt: 0xf0000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000007 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa5702>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0xa i: 0x5702
+ r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000007 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x294b000a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xa (slti)
+ i rs: 0xa rt: 0xb i: 0xa
+ r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa
+ V rs: 0 rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000007 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11600004>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0xb rt: 0 i: 0x4
+ r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4
+ V rs: 0x1 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000007 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000007 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x214a0030>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0xa rt: 0xa i: 0x30
+ r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000007 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0010a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0x10a
+ r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa
+ V rs: 0xbfc00194 rt: 0xbeee
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000007 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000007 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa34a0000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0xa i: 0
+ r rs: 26 rt: 10 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000007 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+0mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2129ffff>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0x9 rt: 0x9 i: 0xffff
+ r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f
+ V rs: 0x7 rt: 0x7
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000007 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x1d20fff3>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x7 (bgtz)
+ i rs: 0x9 rt: 0 i: 0xfff3
+ r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33
+ V rs: 0x6 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000006 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x84100>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0x8 i: 0x4100
+ r rs: 0 rt: 8 rd: 8 sh: 4 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000006 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c0af000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0xa i: 0xf000
+ r rs: 0 rt: 10 rd: 30 sh: 0 func: 0
+ V rs: 0 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000006 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x10a5024>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x8 rt: 0xa i: 0x5024
+ r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24
+ V rs: 0 rt: 0xf0000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000006 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa5702>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0xa i: 0x5702
+ r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000006 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x294b000a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xa (slti)
+ i rs: 0xa rt: 0xb i: 0xa
+ r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa
+ V rs: 0 rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000006 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11600004>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0xb rt: 0 i: 0x4
+ r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4
+ V rs: 0x1 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000006 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000006 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x214a0030>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0xa rt: 0xa i: 0x30
+ r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000006 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+0mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0010a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0x10a
+ r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa
+ V rs: 0xbfc00194 rt: 0xbeee
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000006 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000006 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa34a0000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0xa i: 0
+ r rs: 26 rt: 10 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000006 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2129ffff>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0x9 rt: 0x9 i: 0xffff
+ r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f
+ V rs: 0x6 rt: 0x6
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000006 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x1d20fff3>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x7 (bgtz)
+ i rs: 0x9 rt: 0 i: 0xfff3
+ r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33
+ V rs: 0x5 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000005 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x84100>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0x8 i: 0x4100
+ r rs: 0 rt: 8 rd: 8 sh: 4 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000005 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c0af000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0xa i: 0xf000
+ r rs: 0 rt: 10 rd: 30 sh: 0 func: 0
+ V rs: 0 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000005 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x10a5024>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x8 rt: 0xa i: 0x5024
+ r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24
+ V rs: 0 rt: 0xf0000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000005 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa5702>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0xa i: 0x5702
+ r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000005 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x294b000a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xa (slti)
+ i rs: 0xa rt: 0xb i: 0xa
+ r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa
+ V rs: 0 rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000005 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+0mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11600004>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0xb rt: 0 i: 0x4
+ r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4
+ V rs: 0x1 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000005 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000005 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x214a0030>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0xa rt: 0xa i: 0x30
+ r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000005 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0010a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0x10a
+ r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa
+ V rs: 0xbfc00194 rt: 0xbeee
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000005 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000005 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa34a0000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0xa i: 0
+ r rs: 26 rt: 10 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000005 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2129ffff>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0x9 rt: 0x9 i: 0xffff
+ r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f
+ V rs: 0x5 rt: 0x5
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000005 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x1d20fff3>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x7 (bgtz)
+ i rs: 0x9 rt: 0 i: 0xfff3
+ r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33
+ V rs: 0x4 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x84100>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0x8 i: 0x4100
+ r rs: 0 rt: 8 rd: 8 sh: 4 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c0af000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0xa i: 0xf000
+ r rs: 0 rt: 10 rd: 30 sh: 0 func: 0
+ V rs: 0 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x10a5024>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x8 rt: 0xa i: 0x5024
+ r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24
+ V rs: 0 rt: 0xf0000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000004 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa5702>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0xa i: 0x5702
+ r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000004 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+0mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x294b000a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xa (slti)
+ i rs: 0xa rt: 0xb i: 0xa
+ r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa
+ V rs: 0 rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000004 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11600004>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0xb rt: 0 i: 0x4
+ r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4
+ V rs: 0x1 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000004 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000004 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x214a0030>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0xa rt: 0xa i: 0x30
+ r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000004 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0010a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0x10a
+ r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa
+ V rs: 0xbfc00194 rt: 0xbeee
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa34a0000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0xa i: 0
+ r rs: 26 rt: 10 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2129ffff>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0x9 rt: 0x9 i: 0xffff
+ r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f
+ V rs: 0x4 rt: 0x4
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x1d20fff3>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x7 (bgtz)
+ i rs: 0x9 rt: 0 i: 0xfff3
+ r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33
+ V rs: 0x3 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x84100>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0x8 i: 0x4100
+ r rs: 0 rt: 8 rd: 8 sh: 4 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c0af000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0xa i: 0xf000
+ r rs: 0 rt: 10 rd: 30 sh: 0 func: 0
+ V rs: 0 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x10a5024>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x8 rt: 0xa i: 0x5024
+ r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24
+ V rs: 0 rt: 0xf0000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000003 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa5702>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0xa i: 0x5702
+ r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000003 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+0mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x294b000a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xa (slti)
+ i rs: 0xa rt: 0xb i: 0xa
+ r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa
+ V rs: 0 rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000003 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11600004>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0xb rt: 0 i: 0x4
+ r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4
+ V rs: 0x1 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000003 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000003 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x214a0030>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0xa rt: 0xa i: 0x30
+ r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000003 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0010a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0x10a
+ r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa
+ V rs: 0xbfc00194 rt: 0xbeee
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa34a0000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0xa i: 0
+ r rs: 26 rt: 10 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2129ffff>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0x9 rt: 0x9 i: 0xffff
+ r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f
+ V rs: 0x3 rt: 0x3
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x1d20fff3>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x7 (bgtz)
+ i rs: 0x9 rt: 0 i: 0xfff3
+ r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33
+ V rs: 0x2 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000002 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x84100>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0x8 i: 0x4100
+ r rs: 0 rt: 8 rd: 8 sh: 4 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000002 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c0af000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0xa i: 0xf000
+ r rs: 0 rt: 10 rd: 30 sh: 0 func: 0
+ V rs: 0 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000002 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x10a5024>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x8 rt: 0xa i: 0x5024
+ r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24
+ V rs: 0 rt: 0xf0000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000002 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa5702>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0xa i: 0x5702
+ r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000002 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+0mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x294b000a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xa (slti)
+ i rs: 0xa rt: 0xb i: 0xa
+ r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa
+ V rs: 0 rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000002 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11600004>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0xb rt: 0 i: 0x4
+ r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4
+ V rs: 0x1 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000002 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000002 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x214a0030>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0xa rt: 0xa i: 0x30
+ r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000002 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0010a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0x10a
+ r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa
+ V rs: 0xbfc00194 rt: 0xbeee
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000002 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000002 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa34a0000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0xa i: 0
+ r rs: 26 rt: 10 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000002 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2129ffff>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0x9 rt: 0x9 i: 0xffff
+ r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f
+ V rs: 0x2 rt: 0x2
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000002 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x1d20fff3>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x7 (bgtz)
+ i rs: 0x9 rt: 0 i: 0xfff3
+ r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33
+ V rs: 0x1 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000001 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x84100>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0x8 i: 0x4100
+ r rs: 0 rt: 8 rd: 8 sh: 4 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000001 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c0af000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0xa i: 0xf000
+ r rs: 0 rt: 10 rd: 30 sh: 0 func: 0
+ V rs: 0 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000001 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x10a5024>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x8 rt: 0xa i: 0x5024
+ r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24
+ V rs: 0 rt: 0xf0000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000001 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa5702>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0xa i: 0x5702
+ r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000001 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+0mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x294b000a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xa (slti)
+ i rs: 0xa rt: 0xb i: 0xa
+ r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa
+ V rs: 0 rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000001 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11600004>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0xb rt: 0 i: 0x4
+ r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4
+ V rs: 0x1 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000001 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000001 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x214a0030>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0xa rt: 0xa i: 0x30
+ r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000001 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0010a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0x10a
+ r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa
+ V rs: 0xbfc00194 rt: 0xbeee
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000001 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000001 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa34a0000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0xa i: 0
+ r rs: 26 rt: 10 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000001 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2129ffff>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0x9 rt: 0x9 i: 0xffff
+ r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f
+ V rs: 0x1 rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000001 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x1d20fff3>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x7 (bgtz)
+ i rs: 0x9 rt: 0 i: 0xfff3
+ r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00438 m_ifetch_addr: 0xbfc00434
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x84100>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00434 NPC: 0xbfc00438 Ins: 0x84100
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0x8 i: 0x4100
+ r rs: 0 rt: 8 rd: 8 sh: 4 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00438 m_jump_pc: 0xbfc0043c m_ifetch_addr: 0xbfc00438
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3e00008>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00438 NPC: 0xbfc0043c Ins: 0x3e00008
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x1f rt: 0 i: 0x8
+ r rs: 31 rt: 0 rd: 0 sh: 0 func: 0x8
+ V rs: 0xbfc00194 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc0043c m_jump_pc: 0xbfc00194 m_ifetch_addr: 0xbfc0043c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0043c NPC: 0xbfc00194 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00194 m_jump_pc: 0xbfc00198 m_ifetch_addr: 0xbfc00194
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c04bfc0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00194 NPC: 0xbfc00198 Ins: 0x3c04bfc0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0x4 i: 0xbfc0
+ r rs: 0 rt: 4 rd: 23 sh: 31 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00198 m_jump_pc: 0xbfc0019c m_ifetch_addr: 0xbfc00198
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+0mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x24840239>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00198 NPC: 0xbfc0019c Ins: 0x24840239
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0x4 rt: 0x4 i: 0x239
+ r rs: 4 rt: 4 rd: 0 sh: 8 func: 0x39
+ V rs: 0xbfc00000 rt: 0xbfc00000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc0019c m_jump_pc: 0xbfc001a0 m_ifetch_addr: 0xbfc0019c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xff000f0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0019c NPC: 0xbfc001a0 Ins: 0xff000f0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x3 (jal)
+ i rs: 0x1f rt: 0x10 i: 0xf0
+ r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x30
+ V rs: 0xbfc00194 rt: 0xbeee
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc001a0 m_jump_pc: 0xbfc003c0 m_ifetch_addr: 0xbfc001a0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc001a0 NPC: 0xbfc003c0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 m_next_pc: 0xbfc003c0 m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003c0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x804021>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c0 NPC: 0xbfc003c4 Ins: 0x804021
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x4 rt: 0 i: 0x4021
+ r rs: 4 rt: 0 rd: 8 sh: 0 func: 0x21
+ V rs: 0xbfc00239 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x81090000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x20 (lb)
+ i rs: 0x8 rt: 0x9 i: 0
+ r rs: 8 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xbfc00239 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00239 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_READ @ 0xbfc00238 wdata 0 be 0x2> off: 0x1 sign_ext: 0x1 dest: gp+0x9
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp valid no error rdata 0x61622000>, 0)
+mips0 setData: <DataRsp valid no error rdata 0x61622000> off: 0 sign_ext: 0x1 dest: r_gp+0x9
+mips0 setData: <DataRsp valid no error rdata 0x61622000> off: 0 count: 0x1 le: 0x1 old: 0 from_mem: 0x61622000 mask: 0xffffffff new_data: 0x20
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0x9 rt: 0 i: 0x5
+ r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5
+ V rs: 0x20 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00239 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00239 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa3490000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0x9 i: 0
+ r rs: 26 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x20
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00239 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x20 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0x8 rt: 0x8 i: 0x1
+ r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1
+ V rs: 0xbfc00239 rt: 0xbfc00239
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00239 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf000f1>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0xf1
+ r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31
+ V rs: 0xbfc001a4 rt: 0xbeee
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0023a 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0023a 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x81090000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x20 (lb)
+ i rs: 0x8 rt: 0x9 i: 0
+ r rs: 8 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xbfc0023a rt: 0x20
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0023a 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_READ @ 0xbfc00238 wdata 0 be 0x4> off: 0x2 sign_ext: 0x1 dest: gp+0x9
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp valid no error rdata 0x61622000>, 0)
+mips0 setData: <DataRsp valid no error rdata 0x61622000> off: 0 sign_ext: 0x1 dest: r_gp+0x9
+mips0 setData: <DataRsp valid no error rdata 0x61622000> off: 0 count: 0x1 le: 0x2 old: 0x20 from_mem: 0x61622000 mask: 0xffffffff new_data: 0x62
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1
+ mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0x9 rt: 0 i: 0x5
+ r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5
+ V rs: 0x62 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0023a 09: 00000062 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0023a 09: 00000062 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa3490000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0x9 i: 0
+ r rs: 26 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x62
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0023a 09: 00000062 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x62 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0x8 rt: 0x8 i: 0x1
+ r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1
+ V rs: 0xbfc0023a rt: 0xbfc0023a
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0023a 09: 00000062 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf000f1>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0xf1
+ r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31
+ V rs: 0xbfc001a4 rt: 0xbeee
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0023b 09: 00000062 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0023b 09: 00000062 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x81090000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x20 (lb)
+ i rs: 0x8 rt: 0x9 i: 0
+ r rs: 8 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xbfc0023b rt: 0x62
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0023b 09: 00000062 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_READ @ 0xbfc00238 wdata 0 be 0x8> off: 0x3 sign_ext: 0x1 dest: gp+0x9
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp valid no error rdata 0x61622000>, 0)
+mips0 setData: <DataRsp valid no error rdata 0x61622000> off: 0 sign_ext: 0x1 dest: r_gp+0x9
+mips0 setData: <DataRsp valid no error rdata 0x61622000> off: 0 count: 0x1 le: 0x3 old: 0x62 from_mem: 0x61622000 mask: 0xffffffff new_data: 0x61
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0x9 rt: 0 i: 0x5
+ r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5
+ V rs: 0x61 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0023b 09: 00000061 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+bmips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0023b 09: 00000061 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa3490000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0x9 i: 0
+ r rs: 26 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x61
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0023b 09: 00000061 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x61 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0x8 rt: 0x8 i: 0x1
+ r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1
+ V rs: 0xbfc0023b rt: 0xbfc0023b
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0023b 09: 00000061 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf000f1>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0xf1
+ r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31
+ V rs: 0xbfc001a4 rt: 0xbeee
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0023c 09: 00000061 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0023c 09: 00000061 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x81090000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x20 (lb)
+ i rs: 0x8 rt: 0x9 i: 0
+ r rs: 8 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xbfc0023c rt: 0x61
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0023c 09: 00000061 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_READ @ 0xbfc0023c wdata 0 be 0x1> off: 0 sign_ext: 0x1 dest: gp+0x9
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp valid no error rdata 0x20617664>, 0)
+mips0 setData: <DataRsp valid no error rdata 0x20617664> off: 0 sign_ext: 0x1 dest: r_gp+0x9
+mips0 setData: <DataRsp valid no error rdata 0x20617664> off: 0 count: 0x1 le: 0 old: 0x61 from_mem: 0x20617664 mask: 0xffffffff new_data: 0x64
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0x9 rt: 0 i: 0x5
+ r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5
+ V rs: 0x64 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0023c 09: 00000064 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0023c 09: 00000064 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+amips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa3490000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0x9 i: 0
+ r rs: 26 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x64
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0023c 09: 00000064 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x64 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0x8 rt: 0x8 i: 0x1
+ r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1
+ V rs: 0xbfc0023c rt: 0xbfc0023c
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0023c 09: 00000064 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf000f1>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0xf1
+ r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31
+ V rs: 0xbfc001a4 rt: 0xbeee
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0023d 09: 00000064 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0023d 09: 00000064 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x81090000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x20 (lb)
+ i rs: 0x8 rt: 0x9 i: 0
+ r rs: 8 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xbfc0023d rt: 0x64
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0023d 09: 00000064 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_READ @ 0xbfc0023c wdata 0 be 0x2> off: 0x1 sign_ext: 0x1 dest: gp+0x9
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp valid no error rdata 0x20617664>, 0)
+mips0 setData: <DataRsp valid no error rdata 0x20617664> off: 0 sign_ext: 0x1 dest: r_gp+0x9
+mips0 setData: <DataRsp valid no error rdata 0x20617664> off: 0 count: 0x1 le: 0x1 old: 0x64 from_mem: 0x20617664 mask: 0xffffffff new_data: 0x76
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0x9 rt: 0 i: 0x5
+ r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5
+ V rs: 0x76 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0023d 09: 00000076 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0023d 09: 00000076 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa3490000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0x9 i: 0
+ r rs: 26 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x76
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0023d 09: 00000076 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x76 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+dmips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0x8 rt: 0x8 i: 0x1
+ r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1
+ V rs: 0xbfc0023d rt: 0xbfc0023d
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0023d 09: 00000076 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf000f1>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0xf1
+ r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31
+ V rs: 0xbfc001a4 rt: 0xbeee
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0023e 09: 00000076 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0023e 09: 00000076 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x81090000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x20 (lb)
+ i rs: 0x8 rt: 0x9 i: 0
+ r rs: 8 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xbfc0023e rt: 0x76
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0023e 09: 00000076 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_READ @ 0xbfc0023c wdata 0 be 0x4> off: 0x2 sign_ext: 0x1 dest: gp+0x9
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp valid no error rdata 0x20617664>, 0)
+mips0 setData: <DataRsp valid no error rdata 0x20617664> off: 0 sign_ext: 0x1 dest: r_gp+0x9
+mips0 setData: <DataRsp valid no error rdata 0x20617664> off: 0 count: 0x1 le: 0x2 old: 0x76 from_mem: 0x20617664 mask: 0xffffffff new_data: 0x61
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0x9 rt: 0 i: 0x5
+ r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5
+ V rs: 0x61 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0023e 09: 00000061 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0023e 09: 00000061 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa3490000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0x9 i: 0
+ r rs: 26 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x61
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0023e 09: 00000061 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x61 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+vmips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0x8 rt: 0x8 i: 0x1
+ r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1
+ V rs: 0xbfc0023e rt: 0xbfc0023e
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0023e 09: 00000061 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf000f1>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0xf1
+ r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31
+ V rs: 0xbfc001a4 rt: 0xbeee
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0023f 09: 00000061 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0023f 09: 00000061 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x81090000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x20 (lb)
+ i rs: 0x8 rt: 0x9 i: 0
+ r rs: 8 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xbfc0023f rt: 0x61
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0023f 09: 00000061 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_READ @ 0xbfc0023c wdata 0 be 0x8> off: 0x3 sign_ext: 0x1 dest: gp+0x9
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp valid no error rdata 0x20617664>, 0)
+mips0 setData: <DataRsp valid no error rdata 0x20617664> off: 0 sign_ext: 0x1 dest: r_gp+0x9
+mips0 setData: <DataRsp valid no error rdata 0x20617664> off: 0 count: 0x1 le: 0x3 old: 0x61 from_mem: 0x20617664 mask: 0xffffffff new_data: 0x20
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0x9 rt: 0 i: 0x5
+ r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5
+ V rs: 0x20 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0023f 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0023f 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa3490000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0x9 i: 0
+ r rs: 26 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x20
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0023f 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x20 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+amips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0x8 rt: 0x8 i: 0x1
+ r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1
+ V rs: 0xbfc0023f rt: 0xbfc0023f
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0023f 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf000f1>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0xf1
+ r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31
+ V rs: 0xbfc001a4 rt: 0xbeee
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00240 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00240 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x81090000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x20 (lb)
+ i rs: 0x8 rt: 0x9 i: 0
+ r rs: 8 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xbfc00240 rt: 0x20
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00240 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_READ @ 0xbfc00240 wdata 0 be 0x1> off: 0 sign_ext: 0x1 dest: gp+0x9
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp valid no error rdata 0x69782000>, 0)
+mips0 setData: <DataRsp valid no error rdata 0x69782000> off: 0 sign_ext: 0x1 dest: r_gp+0x9
+mips0 setData: <DataRsp valid no error rdata 0x69782000> off: 0 count: 0x1 le: 0 old: 0x20 from_mem: 0x69782000 mask: 0xffffffff new_data: 0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0x9 rt: 0 i: 0x5
+ r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00240 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003e0 m_ifetch_addr: 0xbfc003cc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003cc NPC: 0xbfc003e0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00240 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 m_next_pc: 0xbfc003e0 m_jump_pc: 0xbfc003e4 m_ifetch_addr: 0xbfc003e0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3e00008>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003e0 NPC: 0xbfc003e4 Ins: 0x3e00008
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x1f rt: 0 i: 0x8
+ r rs: 31 rt: 0 rd: 0 sh: 0 func: 0x8
+ V rs: 0xbfc001a4 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00240 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 m_next_pc: 0xbfc003e4 m_jump_pc: 0xbfc001a4 m_ifetch_addr: 0xbfc003e4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+ mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003e4 NPC: 0xbfc001a4 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00240 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 m_next_pc: 0xbfc001a4 m_jump_pc: 0xbfc001a8 m_ifetch_addr: 0xbfc001a4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x40044000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc001a4 NPC: 0xbfc001a8 Ins: 0x40044000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x10 (cop0)
+ i rs: 0 rt: 0x4 i: 0x4000
+ r rs: 0 rt: 4 rd: 8 sh: 0 func: 0
+ V rs: 0 rt: 0xbfc00239
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00240 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 m_next_pc: 0xbfc001a8 m_jump_pc: 0xbfc001ac m_ifetch_addr: 0xbfc001a8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xff000fa>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc001a8 NPC: 0xbfc001ac Ins: 0xff000fa
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x3 (jal)
+ i rs: 0x1f rt: 0x10 i: 0xfa
+ r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x3a
+ V rs: 0xbfc001a4 rt: 0xbeee
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00240 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 m_next_pc: 0xbfc001ac m_jump_pc: 0xbfc003e8 m_ifetch_addr: 0xbfc001ac
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc001ac NPC: 0xbfc003e8 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00240 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc003e8 m_jump_pc: 0xbfc003ec m_ifetch_addr: 0xbfc003e8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x804021>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003e8 NPC: 0xbfc003ec Ins: 0x804021
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x4 rt: 0 i: 0x4021
+ r rs: 4 rt: 0 rd: 8 sh: 0 func: 0x21
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00240 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc003ec m_jump_pc: 0xbfc003f0 m_ifetch_addr: 0xbfc003ec
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x24090030>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003ec NPC: 0xbfc003f0 Ins: 0x24090030
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0 rt: 0x9 i: 0x30
+ r rs: 0 rt: 9 rd: 0 sh: 0 func: 0x30
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc003f0 m_jump_pc: 0xbfc003f4 m_ifetch_addr: 0xbfc003f0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa3490000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003f0 NPC: 0xbfc003f4 Ins: 0xa3490000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0x9 i: 0
+ r rs: 26 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000030 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc003f4 m_jump_pc: 0xbfc003f8 m_ifetch_addr: 0xbfc003f4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x24090078>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc003f4 NPC: 0xbfc003f8 Ins: 0x24090078
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0 rt: 0x9 i: 0x78
+ r rs: 0 rt: 9 rd: 0 sh: 1 func: 0x38
+ V rs: 0 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000030 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc003f8 m_jump_pc: 0xbfc003fc m_ifetch_addr: 0xbfc003f8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa3490000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003f8 NPC: 0xbfc003fc Ins: 0xa3490000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0x9 i: 0
+ r rs: 26 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x78
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000078 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x78 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc003fc m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc003fc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x24090008>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc003fc NPC: 0xbfc00400 Ins: 0x24090008
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0 rt: 0x9 i: 0x8
+ r rs: 0 rt: 9 rd: 0 sh: 0 func: 0x8
+ V rs: 0 rt: 0x78
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000078 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c0af000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0xa i: 0xf000
+ r rs: 0 rt: 10 rd: 30 sh: 0 func: 0
+ V rs: 0 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000008 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x10a5024>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x8 rt: 0xa i: 0x5024
+ r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24
+ V rs: 0 rt: 0xf0000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000008 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa5702>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0xa i: 0x5702
+ r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000008 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+0mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x294b000a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xa (slti)
+ i rs: 0xa rt: 0xb i: 0xa
+ r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa
+ V rs: 0 rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000008 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11600004>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0xb rt: 0 i: 0x4
+ r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4
+ V rs: 0x1 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000008 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000008 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x214a0030>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0xa rt: 0xa i: 0x30
+ r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000008 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0010a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0x10a
+ r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa
+ V rs: 0xbfc001b0 rt: 0xbeee
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000008 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000008 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa34a0000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0xa i: 0
+ r rs: 26 rt: 10 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000008 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2129ffff>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0x9 rt: 0x9 i: 0xffff
+ r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f
+ V rs: 0x8 rt: 0x8
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000008 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x1d20fff3>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x7 (bgtz)
+ i rs: 0x9 rt: 0 i: 0xfff3
+ r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33
+ V rs: 0x7 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000007 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x84100>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0x8 i: 0x4100
+ r rs: 0 rt: 8 rd: 8 sh: 4 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000007 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+xmips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c0af000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0xa i: 0xf000
+ r rs: 0 rt: 10 rd: 30 sh: 0 func: 0
+ V rs: 0 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000007 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x10a5024>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x8 rt: 0xa i: 0x5024
+ r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24
+ V rs: 0 rt: 0xf0000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000007 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa5702>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0xa i: 0x5702
+ r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000007 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x294b000a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xa (slti)
+ i rs: 0xa rt: 0xb i: 0xa
+ r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa
+ V rs: 0 rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000007 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11600004>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0xb rt: 0 i: 0x4
+ r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4
+ V rs: 0x1 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000007 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000007 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x214a0030>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0xa rt: 0xa i: 0x30
+ r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000007 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0010a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0x10a
+ r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa
+ V rs: 0xbfc001b0 rt: 0xbeee
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000007 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000007 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa34a0000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0xa i: 0
+ r rs: 26 rt: 10 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000007 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+0mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2129ffff>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0x9 rt: 0x9 i: 0xffff
+ r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f
+ V rs: 0x7 rt: 0x7
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000007 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x1d20fff3>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x7 (bgtz)
+ i rs: 0x9 rt: 0 i: 0xfff3
+ r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33
+ V rs: 0x6 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000006 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x84100>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0x8 i: 0x4100
+ r rs: 0 rt: 8 rd: 8 sh: 4 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000006 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c0af000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0xa i: 0xf000
+ r rs: 0 rt: 10 rd: 30 sh: 0 func: 0
+ V rs: 0 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000006 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x10a5024>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x8 rt: 0xa i: 0x5024
+ r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24
+ V rs: 0 rt: 0xf0000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000006 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa5702>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0xa i: 0x5702
+ r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000006 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x294b000a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xa (slti)
+ i rs: 0xa rt: 0xb i: 0xa
+ r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa
+ V rs: 0 rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000006 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11600004>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0xb rt: 0 i: 0x4
+ r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4
+ V rs: 0x1 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000006 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000006 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x214a0030>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0xa rt: 0xa i: 0x30
+ r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000006 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+0mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0010a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0x10a
+ r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa
+ V rs: 0xbfc001b0 rt: 0xbeee
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000006 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000006 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa34a0000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0xa i: 0
+ r rs: 26 rt: 10 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000006 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2129ffff>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0x9 rt: 0x9 i: 0xffff
+ r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f
+ V rs: 0x6 rt: 0x6
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000006 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x1d20fff3>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x7 (bgtz)
+ i rs: 0x9 rt: 0 i: 0xfff3
+ r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33
+ V rs: 0x5 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000005 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x84100>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0x8 i: 0x4100
+ r rs: 0 rt: 8 rd: 8 sh: 4 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000005 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c0af000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0xa i: 0xf000
+ r rs: 0 rt: 10 rd: 30 sh: 0 func: 0
+ V rs: 0 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000005 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x10a5024>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x8 rt: 0xa i: 0x5024
+ r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24
+ V rs: 0 rt: 0xf0000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000005 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa5702>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0xa i: 0x5702
+ r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000005 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x294b000a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xa (slti)
+ i rs: 0xa rt: 0xb i: 0xa
+ r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa
+ V rs: 0 rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000005 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+0mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11600004>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0xb rt: 0 i: 0x4
+ r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4
+ V rs: 0x1 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000005 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000005 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x214a0030>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0xa rt: 0xa i: 0x30
+ r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000005 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0010a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0x10a
+ r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa
+ V rs: 0xbfc001b0 rt: 0xbeee
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000005 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000005 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa34a0000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0xa i: 0
+ r rs: 26 rt: 10 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000005 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2129ffff>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0x9 rt: 0x9 i: 0xffff
+ r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f
+ V rs: 0x5 rt: 0x5
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000005 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x1d20fff3>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x7 (bgtz)
+ i rs: 0x9 rt: 0 i: 0xfff3
+ r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33
+ V rs: 0x4 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x84100>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0x8 i: 0x4100
+ r rs: 0 rt: 8 rd: 8 sh: 4 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c0af000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0xa i: 0xf000
+ r rs: 0 rt: 10 rd: 30 sh: 0 func: 0
+ V rs: 0 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x10a5024>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x8 rt: 0xa i: 0x5024
+ r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24
+ V rs: 0 rt: 0xf0000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000004 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa5702>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0xa i: 0x5702
+ r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000004 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+0mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x294b000a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xa (slti)
+ i rs: 0xa rt: 0xb i: 0xa
+ r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa
+ V rs: 0 rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000004 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11600004>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0xb rt: 0 i: 0x4
+ r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4
+ V rs: 0x1 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000004 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000004 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x214a0030>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0xa rt: 0xa i: 0x30
+ r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000004 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0010a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0x10a
+ r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa
+ V rs: 0xbfc001b0 rt: 0xbeee
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa34a0000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0xa i: 0
+ r rs: 26 rt: 10 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2129ffff>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0x9 rt: 0x9 i: 0xffff
+ r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f
+ V rs: 0x4 rt: 0x4
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x1d20fff3>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x7 (bgtz)
+ i rs: 0x9 rt: 0 i: 0xfff3
+ r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33
+ V rs: 0x3 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x84100>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0x8 i: 0x4100
+ r rs: 0 rt: 8 rd: 8 sh: 4 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c0af000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0xa i: 0xf000
+ r rs: 0 rt: 10 rd: 30 sh: 0 func: 0
+ V rs: 0 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x10a5024>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x8 rt: 0xa i: 0x5024
+ r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24
+ V rs: 0 rt: 0xf0000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000003 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa5702>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0xa i: 0x5702
+ r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000003 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+0mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x294b000a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xa (slti)
+ i rs: 0xa rt: 0xb i: 0xa
+ r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa
+ V rs: 0 rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000003 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11600004>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0xb rt: 0 i: 0x4
+ r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4
+ V rs: 0x1 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000003 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000003 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x214a0030>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0xa rt: 0xa i: 0x30
+ r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000003 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0010a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0x10a
+ r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa
+ V rs: 0xbfc001b0 rt: 0xbeee
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa34a0000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0xa i: 0
+ r rs: 26 rt: 10 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2129ffff>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0x9 rt: 0x9 i: 0xffff
+ r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f
+ V rs: 0x3 rt: 0x3
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x1d20fff3>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x7 (bgtz)
+ i rs: 0x9 rt: 0 i: 0xfff3
+ r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33
+ V rs: 0x2 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000002 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x84100>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0x8 i: 0x4100
+ r rs: 0 rt: 8 rd: 8 sh: 4 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000002 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c0af000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0xa i: 0xf000
+ r rs: 0 rt: 10 rd: 30 sh: 0 func: 0
+ V rs: 0 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000002 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x10a5024>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x8 rt: 0xa i: 0x5024
+ r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24
+ V rs: 0 rt: 0xf0000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000002 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa5702>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0xa i: 0x5702
+ r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000002 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+0mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x294b000a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xa (slti)
+ i rs: 0xa rt: 0xb i: 0xa
+ r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa
+ V rs: 0 rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000002 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11600004>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0xb rt: 0 i: 0x4
+ r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4
+ V rs: 0x1 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000002 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000002 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x214a0030>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0xa rt: 0xa i: 0x30
+ r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000002 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0010a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0x10a
+ r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa
+ V rs: 0xbfc001b0 rt: 0xbeee
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000002 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000002 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa34a0000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0xa i: 0
+ r rs: 26 rt: 10 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000002 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2129ffff>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0x9 rt: 0x9 i: 0xffff
+ r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f
+ V rs: 0x2 rt: 0x2
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000002 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x1d20fff3>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x7 (bgtz)
+ i rs: 0x9 rt: 0 i: 0xfff3
+ r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33
+ V rs: 0x1 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000001 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x84100>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0x8 i: 0x4100
+ r rs: 0 rt: 8 rd: 8 sh: 4 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000001 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c0af000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0xa i: 0xf000
+ r rs: 0 rt: 10 rd: 30 sh: 0 func: 0
+ V rs: 0 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000001 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x10a5024>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x8 rt: 0xa i: 0x5024
+ r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24
+ V rs: 0 rt: 0xf0000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000001 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa5702>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0xa i: 0x5702
+ r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000001 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+0mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x294b000a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xa (slti)
+ i rs: 0xa rt: 0xb i: 0xa
+ r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa
+ V rs: 0 rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000001 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11600004>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0xb rt: 0 i: 0x4
+ r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4
+ V rs: 0x1 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000001 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000001 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x214a0030>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0xa rt: 0xa i: 0x30
+ r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000001 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0010a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0x10a
+ r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa
+ V rs: 0xbfc001b0 rt: 0xbeee
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000001 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000001 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa34a0000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0xa i: 0
+ r rs: 26 rt: 10 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000001 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2129ffff>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0x9 rt: 0x9 i: 0xffff
+ r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f
+ V rs: 0x1 rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000001 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x1d20fff3>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x7 (bgtz)
+ i rs: 0x9 rt: 0 i: 0xfff3
+ r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00438 m_ifetch_addr: 0xbfc00434
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x84100>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00434 NPC: 0xbfc00438 Ins: 0x84100
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0x8 i: 0x4100
+ r rs: 0 rt: 8 rd: 8 sh: 4 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00438 m_jump_pc: 0xbfc0043c m_ifetch_addr: 0xbfc00438
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3e00008>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00438 NPC: 0xbfc0043c Ins: 0x3e00008
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x1f rt: 0 i: 0x8
+ r rs: 31 rt: 0 rd: 0 sh: 0 func: 0x8
+ V rs: 0xbfc001b0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc0043c m_jump_pc: 0xbfc001b0 m_ifetch_addr: 0xbfc0043c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0043c NPC: 0xbfc001b0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc001b0 m_jump_pc: 0xbfc001b4 m_ifetch_addr: 0xbfc001b0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c04bfc0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc001b0 NPC: 0xbfc001b4 Ins: 0x3c04bfc0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0x4 i: 0xbfc0
+ r rs: 0 rt: 4 rd: 23 sh: 31 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc001b4 m_jump_pc: 0xbfc001b8 m_ifetch_addr: 0xbfc001b4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+0mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x24840241>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc001b4 NPC: 0xbfc001b8 Ins: 0x24840241
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0x4 rt: 0x4 i: 0x241
+ r rs: 4 rt: 4 rd: 0 sh: 9 func: 0x1
+ V rs: 0xbfc00000 rt: 0xbfc00000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc001b8 m_jump_pc: 0xbfc001bc m_ifetch_addr: 0xbfc001b8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xff000f0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc001b8 NPC: 0xbfc001bc Ins: 0xff000f0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x3 (jal)
+ i rs: 0x1f rt: 0x10 i: 0xf0
+ r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x30
+ V rs: 0xbfc001b0 rt: 0xbeee
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc001bc m_jump_pc: 0xbfc003c0 m_ifetch_addr: 0xbfc001bc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc001bc NPC: 0xbfc003c0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 m_next_pc: 0xbfc003c0 m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003c0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x804021>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c0 NPC: 0xbfc003c4 Ins: 0x804021
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x4 rt: 0 i: 0x4021
+ r rs: 4 rt: 0 rd: 8 sh: 0 func: 0x21
+ V rs: 0xbfc00241 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x81090000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x20 (lb)
+ i rs: 0x8 rt: 0x9 i: 0
+ r rs: 8 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xbfc00241 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00241 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_READ @ 0xbfc00240 wdata 0 be 0x2> off: 0x1 sign_ext: 0x1 dest: gp+0x9
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp valid no error rdata 0x69782000>, 0)
+mips0 setData: <DataRsp valid no error rdata 0x69782000> off: 0 sign_ext: 0x1 dest: r_gp+0x9
+mips0 setData: <DataRsp valid no error rdata 0x69782000> off: 0 count: 0x1 le: 0x1 old: 0 from_mem: 0x69782000 mask: 0xffffffff new_data: 0x20
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0x9 rt: 0 i: 0x5
+ r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5
+ V rs: 0x20 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00241 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00241 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa3490000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0x9 i: 0
+ r rs: 26 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x20
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00241 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x20 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0x8 rt: 0x8 i: 0x1
+ r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1
+ V rs: 0xbfc00241 rt: 0xbfc00241
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00241 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf000f1>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0xf1
+ r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31
+ V rs: 0xbfc001c0 rt: 0xbeee
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00242 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00242 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x81090000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x20 (lb)
+ i rs: 0x8 rt: 0x9 i: 0
+ r rs: 8 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xbfc00242 rt: 0x20
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00242 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_READ @ 0xbfc00240 wdata 0 be 0x4> off: 0x2 sign_ext: 0x1 dest: gp+0x9
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp valid no error rdata 0x69782000>, 0)
+mips0 setData: <DataRsp valid no error rdata 0x69782000> off: 0 sign_ext: 0x1 dest: r_gp+0x9
+mips0 setData: <DataRsp valid no error rdata 0x69782000> off: 0 count: 0x1 le: 0x2 old: 0x20 from_mem: 0x69782000 mask: 0xffffffff new_data: 0x78
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1
+ mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0x9 rt: 0 i: 0x5
+ r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5
+ V rs: 0x78 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00242 09: 00000078 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00242 09: 00000078 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa3490000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0x9 i: 0
+ r rs: 26 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x78
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00242 09: 00000078 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x78 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0x8 rt: 0x8 i: 0x1
+ r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1
+ V rs: 0xbfc00242 rt: 0xbfc00242
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00242 09: 00000078 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf000f1>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0xf1
+ r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31
+ V rs: 0xbfc001c0 rt: 0xbeee
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00243 09: 00000078 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00243 09: 00000078 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x81090000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x20 (lb)
+ i rs: 0x8 rt: 0x9 i: 0
+ r rs: 8 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xbfc00243 rt: 0x78
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00243 09: 00000078 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_READ @ 0xbfc00240 wdata 0 be 0x8> off: 0x3 sign_ext: 0x1 dest: gp+0x9
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp valid no error rdata 0x69782000>, 0)
+mips0 setData: <DataRsp valid no error rdata 0x69782000> off: 0 sign_ext: 0x1 dest: r_gp+0x9
+mips0 setData: <DataRsp valid no error rdata 0x69782000> off: 0 count: 0x1 le: 0x3 old: 0x78 from_mem: 0x69782000 mask: 0xffffffff new_data: 0x69
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0x9 rt: 0 i: 0x5
+ r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5
+ V rs: 0x69 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00243 09: 00000069 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+xmips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00243 09: 00000069 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa3490000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0x9 i: 0
+ r rs: 26 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x69
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00243 09: 00000069 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x69 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0x8 rt: 0x8 i: 0x1
+ r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1
+ V rs: 0xbfc00243 rt: 0xbfc00243
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00243 09: 00000069 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf000f1>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0xf1
+ r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31
+ V rs: 0xbfc001c0 rt: 0xbeee
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00244 09: 00000069 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00244 09: 00000069 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x81090000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x20 (lb)
+ i rs: 0x8 rt: 0x9 i: 0
+ r rs: 8 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xbfc00244 rt: 0x69
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00244 09: 00000069 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_READ @ 0xbfc00244 wdata 0 be 0x1> off: 0 sign_ext: 0x1 dest: gp+0x9
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp valid no error rdata 0x207563>, 0)
+mips0 setData: <DataRsp valid no error rdata 0x207563> off: 0 sign_ext: 0x1 dest: r_gp+0x9
+mips0 setData: <DataRsp valid no error rdata 0x207563> off: 0 count: 0x1 le: 0 old: 0x69 from_mem: 0x207563 mask: 0xffffffff new_data: 0x63
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0x9 rt: 0 i: 0x5
+ r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5
+ V rs: 0x63 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00244 09: 00000063 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00244 09: 00000063 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+imips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa3490000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0x9 i: 0
+ r rs: 26 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x63
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00244 09: 00000063 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x63 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0x8 rt: 0x8 i: 0x1
+ r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1
+ V rs: 0xbfc00244 rt: 0xbfc00244
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00244 09: 00000063 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf000f1>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0xf1
+ r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31
+ V rs: 0xbfc001c0 rt: 0xbeee
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00245 09: 00000063 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00245 09: 00000063 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x81090000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x20 (lb)
+ i rs: 0x8 rt: 0x9 i: 0
+ r rs: 8 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xbfc00245 rt: 0x63
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00245 09: 00000063 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_READ @ 0xbfc00244 wdata 0 be 0x2> off: 0x1 sign_ext: 0x1 dest: gp+0x9
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp valid no error rdata 0x207563>, 0)
+mips0 setData: <DataRsp valid no error rdata 0x207563> off: 0 sign_ext: 0x1 dest: r_gp+0x9
+mips0 setData: <DataRsp valid no error rdata 0x207563> off: 0 count: 0x1 le: 0x1 old: 0x63 from_mem: 0x207563 mask: 0xffffffff new_data: 0x75
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0x9 rt: 0 i: 0x5
+ r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5
+ V rs: 0x75 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00245 09: 00000075 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00245 09: 00000075 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa3490000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0x9 i: 0
+ r rs: 26 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x75
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00245 09: 00000075 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x75 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+cmips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0x8 rt: 0x8 i: 0x1
+ r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1
+ V rs: 0xbfc00245 rt: 0xbfc00245
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00245 09: 00000075 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf000f1>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0xf1
+ r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31
+ V rs: 0xbfc001c0 rt: 0xbeee
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00246 09: 00000075 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00246 09: 00000075 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x81090000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x20 (lb)
+ i rs: 0x8 rt: 0x9 i: 0
+ r rs: 8 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xbfc00246 rt: 0x75
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00246 09: 00000075 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_READ @ 0xbfc00244 wdata 0 be 0x4> off: 0x2 sign_ext: 0x1 dest: gp+0x9
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp valid no error rdata 0x207563>, 0)
+mips0 setData: <DataRsp valid no error rdata 0x207563> off: 0 sign_ext: 0x1 dest: r_gp+0x9
+mips0 setData: <DataRsp valid no error rdata 0x207563> off: 0 count: 0x1 le: 0x2 old: 0x75 from_mem: 0x207563 mask: 0xffffffff new_data: 0x20
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0x9 rt: 0 i: 0x5
+ r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5
+ V rs: 0x20 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00246 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00246 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa3490000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0x9 i: 0
+ r rs: 26 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x20
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00246 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x20 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+umips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0x8 rt: 0x8 i: 0x1
+ r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1
+ V rs: 0xbfc00246 rt: 0xbfc00246
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00246 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf000f1>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0xf1
+ r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31
+ V rs: 0xbfc001c0 rt: 0xbeee
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00247 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00247 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x81090000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x20 (lb)
+ i rs: 0x8 rt: 0x9 i: 0
+ r rs: 8 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xbfc00247 rt: 0x20
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00247 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_READ @ 0xbfc00244 wdata 0 be 0x8> off: 0x3 sign_ext: 0x1 dest: gp+0x9
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp valid no error rdata 0x207563>, 0)
+mips0 setData: <DataRsp valid no error rdata 0x207563> off: 0 sign_ext: 0x1 dest: r_gp+0x9
+mips0 setData: <DataRsp valid no error rdata 0x207563> off: 0 count: 0x1 le: 0x3 old: 0x20 from_mem: 0x207563 mask: 0xffffffff new_data: 0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0x9 rt: 0 i: 0x5
+ r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00247 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003e0 m_ifetch_addr: 0xbfc003cc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003cc NPC: 0xbfc003e0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00247 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 m_next_pc: 0xbfc003e0 m_jump_pc: 0xbfc003e4 m_ifetch_addr: 0xbfc003e0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3e00008>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003e0 NPC: 0xbfc003e4 Ins: 0x3e00008
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x1f rt: 0 i: 0x8
+ r rs: 31 rt: 0 rd: 0 sh: 0 func: 0x8
+ V rs: 0xbfc001c0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00247 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 m_next_pc: 0xbfc003e4 m_jump_pc: 0xbfc001c0 m_ifetch_addr: 0xbfc003e4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+ mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003e4 NPC: 0xbfc001c0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00247 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 m_next_pc: 0xbfc001c0 m_jump_pc: 0xbfc001c4 m_ifetch_addr: 0xbfc001c0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc001c0 m_jump_pc: 0xbfc001c4 m_ifetch_addr: 0xbfc001c0
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc001c0 m_jump_pc: 0xbfc001c4 m_ifetch_addr: 0xbfc001c0
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc001c0 m_jump_pc: 0xbfc001c4 m_ifetch_addr: 0xbfc001c0
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc001c0 m_jump_pc: 0xbfc001c4 m_ifetch_addr: 0xbfc001c0
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc001c0 m_jump_pc: 0xbfc001c4 m_ifetch_addr: 0xbfc001c0
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc001c0 m_jump_pc: 0xbfc001c4 m_ifetch_addr: 0xbfc001c0
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc001c0 m_jump_pc: 0xbfc001c4 m_ifetch_addr: 0xbfc001c0
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc001c0 m_jump_pc: 0xbfc001c4 m_ifetch_addr: 0xbfc001c0
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc001c0 m_jump_pc: 0xbfc001c4 m_ifetch_addr: 0xbfc001c0
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc001c0 m_jump_pc: 0xbfc001c4 m_ifetch_addr: 0xbfc001c0
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc001c0 m_jump_pc: 0xbfc001c4 m_ifetch_addr: 0xbfc001c0
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc001c0 m_jump_pc: 0xbfc001c4 m_ifetch_addr: 0xbfc001c0
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc001c0 m_jump_pc: 0xbfc001c4 m_ifetch_addr: 0xbfc001c0
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc001c0 m_jump_pc: 0xbfc001c4 m_ifetch_addr: 0xbfc001c0
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc001c0 m_jump_pc: 0xbfc001c4 m_ifetch_addr: 0xbfc001c0
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc001c0 m_jump_pc: 0xbfc001c4 m_ifetch_addr: 0xbfc001c0
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc001c0 m_jump_pc: 0xbfc001c4 m_ifetch_addr: 0xbfc001c0
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc001c0 m_jump_pc: 0xbfc001c4 m_ifetch_addr: 0xbfc001c0
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc001c0 m_jump_pc: 0xbfc001c4 m_ifetch_addr: 0xbfc001c0
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc001c0 m_jump_pc: 0xbfc001c4 m_ifetch_addr: 0xbfc001c0
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc001c0 m_jump_pc: 0xbfc001c4 m_ifetch_addr: 0xbfc001c0
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc001c0 m_jump_pc: 0xbfc001c4 m_ifetch_addr: 0xbfc001c0
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc001c0 m_jump_pc: 0xbfc001c4 m_ifetch_addr: 0xbfc001c0
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc001c0 m_jump_pc: 0xbfc001c4 m_ifetch_addr: 0xbfc001c0
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc001c0 m_jump_pc: 0xbfc001c4 m_ifetch_addr: 0xbfc001c0
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc001c0 m_jump_pc: 0xbfc001c4 m_ifetch_addr: 0xbfc001c0
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc001c0 m_jump_pc: 0xbfc001c4 m_ifetch_addr: 0xbfc001c0
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc001c0 m_jump_pc: 0xbfc001c4 m_ifetch_addr: 0xbfc001c0
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc001c0 m_jump_pc: 0xbfc001c4 m_ifetch_addr: 0xbfc001c0
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc001c0 m_jump_pc: 0xbfc001c4 m_ifetch_addr: 0xbfc001c0
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c08d820>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc001c0 NPC: 0xbfc001c4 Ins: 0x3c08d820
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0x8 i: 0xd820
+ r rs: 0 rt: 8 rd: 27 sh: 0 func: 0x20
+ V rs: 0 rt: 0xbfc00247
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00247 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 m_next_pc: 0xbfc001c4 m_jump_pc: 0xbfc001c8 m_ifetch_addr: 0xbfc001c4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x8d040780>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc001c4 NPC: 0xbfc001c8 Ins: 0x8d040780
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x23 (lw)
+ i rs: 0x8 rt: 0x4 i: 0x780
+ r rs: 8 rt: 4 rd: 0 sh: 30 func: 0
+ V rs: 0xd8200000 rt: 0xbfc00241
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: d8200000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_READ @ 0xd8200780 wdata 0 be 0xf> off: 0 sign_ext: 0 dest: gp+0x4
+mips0 m_next_pc: 0xbfc001c8 m_jump_pc: 0xbfc001cc m_ifetch_addr: 0xbfc001c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xff000fa>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc001c8 m_jump_pc: 0xbfc001cc m_ifetch_addr: 0xbfc001c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xff000fa>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc001c8 m_jump_pc: 0xbfc001cc m_ifetch_addr: 0xbfc001c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xff000fa>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc001c8 m_jump_pc: 0xbfc001cc m_ifetch_addr: 0xbfc001c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xff000fa>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc001c8 m_jump_pc: 0xbfc001cc m_ifetch_addr: 0xbfc001c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xff000fa>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc001c8 m_jump_pc: 0xbfc001cc m_ifetch_addr: 0xbfc001c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xff000fa>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc001c8 m_jump_pc: 0xbfc001cc m_ifetch_addr: 0xbfc001c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xff000fa>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc001c8 m_jump_pc: 0xbfc001cc m_ifetch_addr: 0xbfc001c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xff000fa>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc001c8 m_jump_pc: 0xbfc001cc m_ifetch_addr: 0xbfc001c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xff000fa>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc001c8 m_jump_pc: 0xbfc001cc m_ifetch_addr: 0xbfc001c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xff000fa>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc001c8 m_jump_pc: 0xbfc001cc m_ifetch_addr: 0xbfc001c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xff000fa>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc001c8 m_jump_pc: 0xbfc001cc m_ifetch_addr: 0xbfc001c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xff000fa>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x4
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 count: 0x4 le: 0 old: 0xbfc00241 from_mem: 0 mask: 0xffffffff new_data: 0
+mips0 PC: 0xbfc001c8 NPC: 0xbfc001cc Ins: 0xff000fa
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x3 (jal)
+ i rs: 0x1f rt: 0x10 i: 0xfa
+ r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x3a
+ V rs: 0xbfc001c0 rt: 0xbeee
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: d8200000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 m_next_pc: 0xbfc001cc m_jump_pc: 0xbfc003e8 m_ifetch_addr: 0xbfc001cc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc001cc NPC: 0xbfc003e8 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: d8200000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc003e8 m_jump_pc: 0xbfc003ec m_ifetch_addr: 0xbfc003e8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x804021>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003e8 NPC: 0xbfc003ec Ins: 0x804021
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x4 rt: 0 i: 0x4021
+ r rs: 4 rt: 0 rd: 8 sh: 0 func: 0x21
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: d8200000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc003ec m_jump_pc: 0xbfc003f0 m_ifetch_addr: 0xbfc003ec
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x24090030>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003ec NPC: 0xbfc003f0 Ins: 0x24090030
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0 rt: 0x9 i: 0x30
+ r rs: 0 rt: 9 rd: 0 sh: 0 func: 0x30
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc003f0 m_jump_pc: 0xbfc003f4 m_ifetch_addr: 0xbfc003f0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa3490000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003f0 NPC: 0xbfc003f4 Ins: 0xa3490000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0x9 i: 0
+ r rs: 26 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000030 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc003f4 m_jump_pc: 0xbfc003f8 m_ifetch_addr: 0xbfc003f4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x24090078>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc003f4 NPC: 0xbfc003f8 Ins: 0x24090078
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0 rt: 0x9 i: 0x78
+ r rs: 0 rt: 9 rd: 0 sh: 1 func: 0x38
+ V rs: 0 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000030 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc003f8 m_jump_pc: 0xbfc003fc m_ifetch_addr: 0xbfc003f8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa3490000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003f8 NPC: 0xbfc003fc Ins: 0xa3490000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0x9 i: 0
+ r rs: 26 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x78
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000078 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x78 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc003fc m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc003fc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x24090008>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc003fc NPC: 0xbfc00400 Ins: 0x24090008
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0 rt: 0x9 i: 0x8
+ r rs: 0 rt: 9 rd: 0 sh: 0 func: 0x8
+ V rs: 0 rt: 0x78
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000078 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c0af000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0xa i: 0xf000
+ r rs: 0 rt: 10 rd: 30 sh: 0 func: 0
+ V rs: 0 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000008 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x10a5024>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x8 rt: 0xa i: 0x5024
+ r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24
+ V rs: 0 rt: 0xf0000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000008 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa5702>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0xa i: 0x5702
+ r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000008 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+0mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x294b000a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xa (slti)
+ i rs: 0xa rt: 0xb i: 0xa
+ r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa
+ V rs: 0 rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000008 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11600004>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0xb rt: 0 i: 0x4
+ r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4
+ V rs: 0x1 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000008 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000008 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x214a0030>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0xa rt: 0xa i: 0x30
+ r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000008 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0010a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0x10a
+ r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa
+ V rs: 0xbfc001d0 rt: 0xbeee
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000008 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000008 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa34a0000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0xa i: 0
+ r rs: 26 rt: 10 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000008 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2129ffff>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0x9 rt: 0x9 i: 0xffff
+ r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f
+ V rs: 0x8 rt: 0x8
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000008 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x1d20fff3>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x7 (bgtz)
+ i rs: 0x9 rt: 0 i: 0xfff3
+ r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33
+ V rs: 0x7 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000007 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x84100>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0x8 i: 0x4100
+ r rs: 0 rt: 8 rd: 8 sh: 4 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000007 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+xmips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c0af000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0xa i: 0xf000
+ r rs: 0 rt: 10 rd: 30 sh: 0 func: 0
+ V rs: 0 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000007 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x10a5024>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x8 rt: 0xa i: 0x5024
+ r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24
+ V rs: 0 rt: 0xf0000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000007 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa5702>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0xa i: 0x5702
+ r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000007 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x294b000a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xa (slti)
+ i rs: 0xa rt: 0xb i: 0xa
+ r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa
+ V rs: 0 rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000007 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11600004>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0xb rt: 0 i: 0x4
+ r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4
+ V rs: 0x1 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000007 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000007 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x214a0030>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0xa rt: 0xa i: 0x30
+ r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000007 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0010a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0x10a
+ r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa
+ V rs: 0xbfc001d0 rt: 0xbeee
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000007 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000007 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa34a0000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0xa i: 0
+ r rs: 26 rt: 10 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000007 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+0mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2129ffff>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0x9 rt: 0x9 i: 0xffff
+ r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f
+ V rs: 0x7 rt: 0x7
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000007 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x1d20fff3>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x7 (bgtz)
+ i rs: 0x9 rt: 0 i: 0xfff3
+ r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33
+ V rs: 0x6 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000006 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x84100>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0x8 i: 0x4100
+ r rs: 0 rt: 8 rd: 8 sh: 4 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000006 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c0af000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0xa i: 0xf000
+ r rs: 0 rt: 10 rd: 30 sh: 0 func: 0
+ V rs: 0 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000006 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x10a5024>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x8 rt: 0xa i: 0x5024
+ r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24
+ V rs: 0 rt: 0xf0000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000006 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa5702>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0xa i: 0x5702
+ r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000006 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x294b000a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xa (slti)
+ i rs: 0xa rt: 0xb i: 0xa
+ r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa
+ V rs: 0 rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000006 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11600004>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0xb rt: 0 i: 0x4
+ r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4
+ V rs: 0x1 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000006 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000006 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x214a0030>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0xa rt: 0xa i: 0x30
+ r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000006 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+0mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0010a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0x10a
+ r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa
+ V rs: 0xbfc001d0 rt: 0xbeee
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000006 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000006 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa34a0000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0xa i: 0
+ r rs: 26 rt: 10 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000006 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2129ffff>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0x9 rt: 0x9 i: 0xffff
+ r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f
+ V rs: 0x6 rt: 0x6
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000006 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x1d20fff3>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x7 (bgtz)
+ i rs: 0x9 rt: 0 i: 0xfff3
+ r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33
+ V rs: 0x5 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000005 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x84100>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0x8 i: 0x4100
+ r rs: 0 rt: 8 rd: 8 sh: 4 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000005 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c0af000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0xa i: 0xf000
+ r rs: 0 rt: 10 rd: 30 sh: 0 func: 0
+ V rs: 0 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000005 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x10a5024>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x8 rt: 0xa i: 0x5024
+ r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24
+ V rs: 0 rt: 0xf0000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000005 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa5702>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0xa i: 0x5702
+ r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000005 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x294b000a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xa (slti)
+ i rs: 0xa rt: 0xb i: 0xa
+ r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa
+ V rs: 0 rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000005 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+0mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11600004>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0xb rt: 0 i: 0x4
+ r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4
+ V rs: 0x1 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000005 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000005 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x214a0030>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0xa rt: 0xa i: 0x30
+ r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000005 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0010a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0x10a
+ r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa
+ V rs: 0xbfc001d0 rt: 0xbeee
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000005 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000005 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa34a0000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0xa i: 0
+ r rs: 26 rt: 10 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000005 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2129ffff>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0x9 rt: 0x9 i: 0xffff
+ r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f
+ V rs: 0x5 rt: 0x5
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000005 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x1d20fff3>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x7 (bgtz)
+ i rs: 0x9 rt: 0 i: 0xfff3
+ r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33
+ V rs: 0x4 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x84100>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0x8 i: 0x4100
+ r rs: 0 rt: 8 rd: 8 sh: 4 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c0af000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0xa i: 0xf000
+ r rs: 0 rt: 10 rd: 30 sh: 0 func: 0
+ V rs: 0 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x10a5024>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x8 rt: 0xa i: 0x5024
+ r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24
+ V rs: 0 rt: 0xf0000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000004 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa5702>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0xa i: 0x5702
+ r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000004 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+0mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x294b000a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xa (slti)
+ i rs: 0xa rt: 0xb i: 0xa
+ r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa
+ V rs: 0 rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000004 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11600004>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0xb rt: 0 i: 0x4
+ r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4
+ V rs: 0x1 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000004 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000004 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x214a0030>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0xa rt: 0xa i: 0x30
+ r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000004 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0010a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0x10a
+ r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa
+ V rs: 0xbfc001d0 rt: 0xbeee
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa34a0000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0xa i: 0
+ r rs: 26 rt: 10 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2129ffff>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0x9 rt: 0x9 i: 0xffff
+ r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f
+ V rs: 0x4 rt: 0x4
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x1d20fff3>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x7 (bgtz)
+ i rs: 0x9 rt: 0 i: 0xfff3
+ r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33
+ V rs: 0x3 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x84100>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0x8 i: 0x4100
+ r rs: 0 rt: 8 rd: 8 sh: 4 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c0af000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0xa i: 0xf000
+ r rs: 0 rt: 10 rd: 30 sh: 0 func: 0
+ V rs: 0 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x10a5024>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x8 rt: 0xa i: 0x5024
+ r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24
+ V rs: 0 rt: 0xf0000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000003 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa5702>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0xa i: 0x5702
+ r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000003 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+0mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x294b000a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xa (slti)
+ i rs: 0xa rt: 0xb i: 0xa
+ r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa
+ V rs: 0 rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000003 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11600004>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0xb rt: 0 i: 0x4
+ r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4
+ V rs: 0x1 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000003 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000003 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x214a0030>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0xa rt: 0xa i: 0x30
+ r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000003 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0010a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0x10a
+ r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa
+ V rs: 0xbfc001d0 rt: 0xbeee
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa34a0000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0xa i: 0
+ r rs: 26 rt: 10 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2129ffff>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0x9 rt: 0x9 i: 0xffff
+ r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f
+ V rs: 0x3 rt: 0x3
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x1d20fff3>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x7 (bgtz)
+ i rs: 0x9 rt: 0 i: 0xfff3
+ r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33
+ V rs: 0x2 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000002 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x84100>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0x8 i: 0x4100
+ r rs: 0 rt: 8 rd: 8 sh: 4 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000002 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c0af000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0xa i: 0xf000
+ r rs: 0 rt: 10 rd: 30 sh: 0 func: 0
+ V rs: 0 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000002 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x10a5024>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x8 rt: 0xa i: 0x5024
+ r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24
+ V rs: 0 rt: 0xf0000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000002 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa5702>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0xa i: 0x5702
+ r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000002 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+0mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x294b000a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xa (slti)
+ i rs: 0xa rt: 0xb i: 0xa
+ r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa
+ V rs: 0 rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000002 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11600004>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0xb rt: 0 i: 0x4
+ r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4
+ V rs: 0x1 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000002 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000002 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x214a0030>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0xa rt: 0xa i: 0x30
+ r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000002 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0010a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0x10a
+ r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa
+ V rs: 0xbfc001d0 rt: 0xbeee
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000002 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000002 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa34a0000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0xa i: 0
+ r rs: 26 rt: 10 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000002 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2129ffff>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0x9 rt: 0x9 i: 0xffff
+ r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f
+ V rs: 0x2 rt: 0x2
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000002 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x1d20fff3>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x7 (bgtz)
+ i rs: 0x9 rt: 0 i: 0xfff3
+ r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33
+ V rs: 0x1 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000001 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x84100>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0x8 i: 0x4100
+ r rs: 0 rt: 8 rd: 8 sh: 4 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000001 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c0af000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0xa i: 0xf000
+ r rs: 0 rt: 10 rd: 30 sh: 0 func: 0
+ V rs: 0 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000001 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x10a5024>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x8 rt: 0xa i: 0x5024
+ r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24
+ V rs: 0 rt: 0xf0000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000001 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa5702>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0xa i: 0x5702
+ r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000001 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+0mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x294b000a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xa (slti)
+ i rs: 0xa rt: 0xb i: 0xa
+ r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa
+ V rs: 0 rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000001 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11600004>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0xb rt: 0 i: 0x4
+ r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4
+ V rs: 0x1 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000001 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000001 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x214a0030>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0xa rt: 0xa i: 0x30
+ r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000001 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0010a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0x10a
+ r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa
+ V rs: 0xbfc001d0 rt: 0xbeee
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000001 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000001 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa34a0000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0xa i: 0
+ r rs: 26 rt: 10 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000001 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2129ffff>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0x9 rt: 0x9 i: 0xffff
+ r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f
+ V rs: 0x1 rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000001 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x1d20fff3>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x7 (bgtz)
+ i rs: 0x9 rt: 0 i: 0xfff3
+ r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00438 m_ifetch_addr: 0xbfc00434
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x84100>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00434 NPC: 0xbfc00438 Ins: 0x84100
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0x8 i: 0x4100
+ r rs: 0 rt: 8 rd: 8 sh: 4 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00438 m_jump_pc: 0xbfc0043c m_ifetch_addr: 0xbfc00438
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3e00008>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00438 NPC: 0xbfc0043c Ins: 0x3e00008
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x1f rt: 0 i: 0x8
+ r rs: 31 rt: 0 rd: 0 sh: 0 func: 0x8
+ V rs: 0xbfc001d0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc0043c m_jump_pc: 0xbfc001d0 m_ifetch_addr: 0xbfc0043c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0043c NPC: 0xbfc001d0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc001d0 m_jump_pc: 0xbfc001d4 m_ifetch_addr: 0xbfc001d0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2404000a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc001d0 NPC: 0xbfc001d4 Ins: 0x2404000a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0 rt: 0x4 i: 0xa
+ r rs: 0 rt: 4 rd: 0 sh: 0 func: 0xa
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc001d4 m_jump_pc: 0xbfc001d8 m_ifetch_addr: 0xbfc001d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+0mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa3440000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc001d4 NPC: 0xbfc001d8 Ins: 0xa3440000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0x4 i: 0
+ r rs: 26 rt: 4 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0xa
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 0000000a 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0xa be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc001d8 m_jump_pc: 0xbfc001dc m_ifetch_addr: 0xbfc001d8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x32530001>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc001d8 NPC: 0xbfc001dc Ins: 0x32530001
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xc (andi)
+ i rs: 0x12 rt: 0x13 i: 0x1
+ r rs: 18 rt: 19 rd: 0 sh: 0 func: 0x1
+ V rs: 0x1 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 0000000a 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc001dc m_jump_pc: 0xbfc001e0 m_ifetch_addr: 0xbfc001dc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x12600002>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc001dc NPC: 0xbfc001e0 Ins: 0x12600002
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0x13 rt: 0 i: 0x2
+ r rs: 19 rt: 0 rd: 0 sh: 0 func: 0x2
+ V rs: 0x1 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 0000000a 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc001e0 m_jump_pc: 0xbfc001e4 m_ifetch_addr: 0xbfc001e0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc001e0 NPC: 0xbfc001e4 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 0000000a 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc001e4 m_jump_pc: 0xbfc001e8 m_ifetch_addr: 0xbfc001e4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x26100001>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc001e4 NPC: 0xbfc001e8 Ins: 0x26100001
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0x10 rt: 0x10 i: 0x1
+ r rs: 16 rt: 16 rd: 0 sh: 0 func: 0x1
+ V rs: 0xbeee rt: 0xbeee
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 0000000a 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beee 17: 00000000 18: 00000001 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc001e8 m_jump_pc: 0xbfc001ec m_ifetch_addr: 0xbfc001e8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x26520001>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc001e8 NPC: 0xbfc001ec Ins: 0x26520001
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0x12 rt: 0x12 i: 0x1
+ r rs: 18 rt: 18 rd: 0 sh: 0 func: 0x1
+ V rs: 0x1 rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 0000000a 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beef 17: 00000000 18: 00000001 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc001ec m_jump_pc: 0xbfc001f0 m_ifetch_addr: 0xbfc001ec
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x24130184>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc001ec NPC: 0xbfc001f0 Ins: 0x24130184
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0 rt: 0x13 i: 0x184
+ r rs: 0 rt: 19 rd: 0 sh: 6 func: 0x4
+ V rs: 0 rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 0000000a 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beef 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc001f0 m_jump_pc: 0xbfc001f4 m_ifetch_addr: 0xbfc001f0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x12530008>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc001f0 NPC: 0xbfc001f4 Ins: 0x12530008
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0x12 rt: 0x13 i: 0x8
+ r rs: 18 rt: 19 rd: 0 sh: 0 func: 0x8
+ V rs: 0x2 rt: 0x184
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 0000000a 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beef 17: 00000000 18: 00000002 19: 00000184 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc001f4 m_jump_pc: 0xbfc001f8 m_ifetch_addr: 0xbfc001f4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x129842>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc001f4 NPC: 0xbfc001f8 Ins: 0x129842
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0x12 i: 0x9842
+ r rs: 0 rt: 18 rd: 19 sh: 1 func: 0x2
+ V rs: 0 rt: 0x2
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 0000000a 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beef 17: 00000000 18: 00000002 19: 00000184 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc001f8 m_jump_pc: 0xbfc001fc m_ifetch_addr: 0xbfc001f8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c08d820>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc001f8 NPC: 0xbfc001fc Ins: 0x3c08d820
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0x8 i: 0xd820
+ r rs: 0 rt: 8 rd: 27 sh: 0 func: 0x20
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 0000000a 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beef 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc001fc m_jump_pc: 0xbfc00200 m_ifetch_addr: 0xbfc001fc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xad130080>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc001fc NPC: 0xbfc00200 Ins: 0xad130080
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2b (sw)
+ i rs: 0x8 rt: 0x13 i: 0x80
+ r rs: 8 rt: 19 rd: 0 sh: 2 func: 0
+ V rs: 0xd8200000 rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 0000000a 05: 00000000 06: 00000000 07: 00000000
+ 08: d8200000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beef 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd8200080 wdata 0x1 be 0xf> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc00200 m_jump_pc: 0xbfc00204 m_ifetch_addr: 0xbfc00200
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 m_next_pc: 0xbfc00200 m_jump_pc: 0xbfc00204 m_ifetch_addr: 0xbfc00200
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00200 m_jump_pc: 0xbfc00204 m_ifetch_addr: 0xbfc00200
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00200 m_jump_pc: 0xbfc00204 m_ifetch_addr: 0xbfc00200
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00200 m_jump_pc: 0xbfc00204 m_ifetch_addr: 0xbfc00200
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00200 m_jump_pc: 0xbfc00204 m_ifetch_addr: 0xbfc00200
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00200 m_jump_pc: 0xbfc00204 m_ifetch_addr: 0xbfc00200
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00200 m_jump_pc: 0xbfc00204 m_ifetch_addr: 0xbfc00200
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00200 m_jump_pc: 0xbfc00204 m_ifetch_addr: 0xbfc00200
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00200 m_jump_pc: 0xbfc00204 m_ifetch_addr: 0xbfc00200
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00200 m_jump_pc: 0xbfc00204 m_ifetch_addr: 0xbfc00200
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00200 m_jump_pc: 0xbfc00204 m_ifetch_addr: 0xbfc00200
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00200 m_jump_pc: 0xbfc00204 m_ifetch_addr: 0xbfc00200
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00200 m_jump_pc: 0xbfc00204 m_ifetch_addr: 0xbfc00200
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00200 m_jump_pc: 0xbfc00204 m_ifetch_addr: 0xbfc00200
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00200 m_jump_pc: 0xbfc00204 m_ifetch_addr: 0xbfc00200
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00200 m_jump_pc: 0xbfc00204 m_ifetch_addr: 0xbfc00200
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00200 m_jump_pc: 0xbfc00204 m_ifetch_addr: 0xbfc00200
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00200 m_jump_pc: 0xbfc00204 m_ifetch_addr: 0xbfc00200
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00200 m_jump_pc: 0xbfc00204 m_ifetch_addr: 0xbfc00200
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00200 m_jump_pc: 0xbfc00204 m_ifetch_addr: 0xbfc00200
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00200 m_jump_pc: 0xbfc00204 m_ifetch_addr: 0xbfc00200
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00200 m_jump_pc: 0xbfc00204 m_ifetch_addr: 0xbfc00200
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00200 m_jump_pc: 0xbfc00204 m_ifetch_addr: 0xbfc00200
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00200 m_jump_pc: 0xbfc00204 m_ifetch_addr: 0xbfc00200
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00200 m_jump_pc: 0xbfc00204 m_ifetch_addr: 0xbfc00200
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00200 m_jump_pc: 0xbfc00204 m_ifetch_addr: 0xbfc00200
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00200 m_jump_pc: 0xbfc00204 m_ifetch_addr: 0xbfc00200
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00200 m_jump_pc: 0xbfc00204 m_ifetch_addr: 0xbfc00200
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00200 m_jump_pc: 0xbfc00204 m_ifetch_addr: 0xbfc00200
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00200 m_jump_pc: 0xbfc00204 m_ifetch_addr: 0xbfc00200
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x42000018>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00200 NPC: 0xbfc00204 Ins: 0x42000018
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x10 (cop0)
+ i rs: 0x10 rt: 0 i: 0x18
+ r rs: 16 rt: 0 rd: 0 sh: 0 func: 0x18
+ V rs: 0xbeef rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 0000000a 05: 00000000 06: 00000000 07: 00000000
+ 08: d8200000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beef 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 ERET  exl jump_pc: bfc0006c
+mips0 m_next_pc: 0xbfc00068 m_jump_pc: 0xbfc0006c m_ifetch_addr: 0xbfc00068
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3410dead>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00068 NPC: 0xbfc0006c Ins: 0x3410dead
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 0 .erl: 0 .whole: 0x400401
+ op:  0xd (ori)
+ i rs: 0 rt: 0x10 i: 0xdead
+ r rs: 0 rt: 16 rd: 27 sh: 26 func: 0x2d
+ V rs: 0 rt: 0xbeef
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 0000000a 05: 00000000 06: 00000000 07: 00000000
+ 08: d8200000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000beef 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc0006c m_jump_pc: 0xbfc00070 m_ifetch_addr: 0xbfc0006c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2610ffff>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0006c NPC: 0xbfc00070 Ins: 0x2610ffff
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 0 .erl: 0 .whole: 0x400401
+ op:  0x9 (addiu)
+ i rs: 0x10 rt: 0x10 i: 0xffff
+ r rs: 16 rt: 16 rd: 31 sh: 31 func: 0x3f
+ V rs: 0xdead rt: 0xdead
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 0000000a 05: 00000000 06: 00000000 07: 00000000
+ 08: d8200000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dead 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00070 m_jump_pc: 0xbfc00074 m_ifetch_addr: 0xbfc00070
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2610ffff>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00070 NPC: 0xbfc00074 Ins: 0x2610ffff
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 0 .erl: 0 .whole: 0x400401
+ op:  0x9 (addiu)
+ i rs: 0x10 rt: 0x10 i: 0xffff
+ r rs: 16 rt: 16 rd: 31 sh: 31 func: 0x3f
+ V rs: 0xdeac rt: 0xdeac
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 0000000a 05: 00000000 06: 00000000 07: 00000000
+ 08: d8200000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00074 m_jump_pc: 0xbfc00078 m_ifetch_addr: 0xbfc00074
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2610ffff>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 PC: 0xbfc00074 NPC: 0xbfc00078 Ins: 0x2610ffff
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 0 .erl: 0 .whole: 0x400401
+ op:  0x9 (addiu)
+ i rs: 0x10 rt: 0x10 i: 0xffff
+ r rs: 16 rt: 16 rd: 31 sh: 31 func: 0x3f
+ V rs: 0xdeab rt: 0xdeab
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 0000000a 05: 00000000 06: 00000000 07: 00000000
+ 08: d8200000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deab 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 exception: 0
+ m_ins: 9 epc: bfc00078 error_epc: 0 bar: d8200080 cause.xcode: 0 .bd: 0 .ip: 4 status.exl: 1 .erl: 0 exception address: bfc00380
+mips0 executeNCycles( 1, <InsRsp  valid no error ins 0xbf0004d>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 PC: 0xbfc00380 NPC: 0xbfc00384 Ins: 0xbf0004d
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0x4d
+ r rs: 31 rt: 16 rd: 0 sh: 1 func: 0xd
+ V rs: 0xbfc001d0 rt: 0xdeaa
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 0000000a 05: 00000000 06: 00000000 07: 00000000
+ 08: d8200000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deaa 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00384 m_jump_pc: 0xbfc00134 m_ifetch_addr: 0xbfc00384
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 PC: 0xbfc00384 NPC: 0xbfc00134 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 0000000a 05: 00000000 06: 00000000 07: 00000000
+ 08: d8200000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deaa 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00134 m_jump_pc: 0xbfc00138 m_ifetch_addr: 0xbfc00134
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2610ffff>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 PC: 0xbfc00134 NPC: 0xbfc00138 Ins: 0x2610ffff
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0x10 rt: 0x10 i: 0xffff
+ r rs: 16 rt: 16 rd: 31 sh: 31 func: 0x3f
+ V rs: 0xdeaa rt: 0xdeaa
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 0000000a 05: 00000000 06: 00000000 07: 00000000
+ 08: d8200000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deaa 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00138 m_jump_pc: 0xbfc0013c m_ifetch_addr: 0xbfc00138
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c08d820>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 PC: 0xbfc00138 NPC: 0xbfc0013c Ins: 0x3c08d820
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0x8 i: 0xd820
+ r rs: 0 rt: 8 rd: 27 sh: 0 func: 0x20
+ V rs: 0 rt: 0xd8200000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 0000000a 05: 00000000 06: 00000000 07: 00000000
+ 08: d8200000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc0013c m_jump_pc: 0xbfc00140 m_ifetch_addr: 0xbfc0013c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xad000080>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 PC: 0xbfc0013c NPC: 0xbfc00140 Ins: 0xad000080
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2b (sw)
+ i rs: 0x8 rt: 0 i: 0x80
+ r rs: 8 rt: 0 rd: 0 sh: 2 func: 0
+ V rs: 0xd8200000 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 0000000a 05: 00000000 06: 00000000 07: 00000000
+ 08: d8200000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd8200080 wdata 0 be 0xf> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc00140 m_jump_pc: 0xbfc00144 m_ifetch_addr: 0xbfc00140
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c04bfc0>, <DataRsp valid no error rdata 0>, 0x1)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc00140 NPC: 0xbfc00144 Ins: 0x3c04bfc0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0x4 i: 0xbfc0
+ r rs: 0 rt: 4 rd: 23 sh: 31 func: 0
+ V rs: 0 rt: 0xa
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 0000000a 05: 00000000 06: 00000000 07: 00000000
+ 08: d8200000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00144 m_jump_pc: 0xbfc00148 m_ifetch_addr: 0xbfc00144
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x24840224>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 PC: 0xbfc00144 NPC: 0xbfc00148 Ins: 0x24840224
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0x4 rt: 0x4 i: 0x224
+ r rs: 4 rt: 4 rd: 0 sh: 8 func: 0x24
+ V rs: 0xbfc00000 rt: 0xbfc00000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00000 05: 00000000 06: 00000000 07: 00000000
+ 08: d8200000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00148 m_jump_pc: 0xbfc0014c m_ifetch_addr: 0xbfc00148
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xff000f0>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 PC: 0xbfc00148 NPC: 0xbfc0014c Ins: 0xff000f0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x3 (jal)
+ i rs: 0x1f rt: 0x10 i: 0xf0
+ r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x30
+ V rs: 0xbfc001d0 rt: 0xdea9
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: d8200000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc0014c m_jump_pc: 0xbfc003c0 m_ifetch_addr: 0xbfc0014c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 PC: 0xbfc0014c NPC: 0xbfc003c0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: d8200000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 m_next_pc: 0xbfc003c0 m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003c0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x804021>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 PC: 0xbfc003c0 NPC: 0xbfc003c4 Ins: 0x804021
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x4 rt: 0 i: 0x4021
+ r rs: 4 rt: 0 rd: 8 sh: 0 func: 0x21
+ V rs: 0xbfc00224 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: d8200000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x81090000>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x20 (lb)
+ i rs: 0x8 rt: 0x9 i: 0
+ r rs: 8 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xbfc00224 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00224 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_READ @ 0xbfc00224 wdata 0 be 0x1> off: 0 sign_ext: 0x1 dest: gp+0x9
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp valid no error rdata 0x74617473>, 0)
+mips0 setData: <DataRsp valid no error rdata 0x74617473> off: 0 sign_ext: 0x1 dest: r_gp+0x9
+mips0 setData: <DataRsp valid no error rdata 0x74617473> off: 0 count: 0x1 le: 0 old: 0 from_mem: 0x74617473 mask: 0xffffffff new_data: 0x73
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0x9 rt: 0 i: 0x5
+ r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5
+ V rs: 0x73 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00224 09: 00000073 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00224 09: 00000073 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa3490000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0x9 i: 0
+ r rs: 26 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x73
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00224 09: 00000073 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x73 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0x8 rt: 0x8 i: 0x1
+ r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1
+ V rs: 0xbfc00224 rt: 0xbfc00224
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00224 09: 00000073 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf000f1>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0xf1
+ r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31
+ V rs: 0xbfc00150 rt: 0xdea9
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00225 09: 00000073 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00225 09: 00000073 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x81090000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x20 (lb)
+ i rs: 0x8 rt: 0x9 i: 0
+ r rs: 8 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xbfc00225 rt: 0x73
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00225 09: 00000073 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_READ @ 0xbfc00224 wdata 0 be 0x2> off: 0x1 sign_ext: 0x1 dest: gp+0x9
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp valid no error rdata 0x74617473>, 0)
+mips0 setData: <DataRsp valid no error rdata 0x74617473> off: 0 sign_ext: 0x1 dest: r_gp+0x9
+mips0 setData: <DataRsp valid no error rdata 0x74617473> off: 0 count: 0x1 le: 0x1 old: 0x73 from_mem: 0x74617473 mask: 0xffffffff new_data: 0x74
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1
+smips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0x9 rt: 0 i: 0x5
+ r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5
+ V rs: 0x74 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00225 09: 00000074 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00225 09: 00000074 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa3490000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0x9 i: 0
+ r rs: 26 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x74
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00225 09: 00000074 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x74 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0x8 rt: 0x8 i: 0x1
+ r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1
+ V rs: 0xbfc00225 rt: 0xbfc00225
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00225 09: 00000074 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf000f1>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0xf1
+ r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31
+ V rs: 0xbfc00150 rt: 0xdea9
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00226 09: 00000074 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00226 09: 00000074 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x81090000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x20 (lb)
+ i rs: 0x8 rt: 0x9 i: 0
+ r rs: 8 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xbfc00226 rt: 0x74
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00226 09: 00000074 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_READ @ 0xbfc00224 wdata 0 be 0x4> off: 0x2 sign_ext: 0x1 dest: gp+0x9
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp valid no error rdata 0x74617473>, 0)
+mips0 setData: <DataRsp valid no error rdata 0x74617473> off: 0 sign_ext: 0x1 dest: r_gp+0x9
+mips0 setData: <DataRsp valid no error rdata 0x74617473> off: 0 count: 0x1 le: 0x2 old: 0x74 from_mem: 0x74617473 mask: 0xffffffff new_data: 0x61
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0x9 rt: 0 i: 0x5
+ r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5
+ V rs: 0x61 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00226 09: 00000061 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+tmips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00226 09: 00000061 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa3490000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0x9 i: 0
+ r rs: 26 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x61
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00226 09: 00000061 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x61 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0x8 rt: 0x8 i: 0x1
+ r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1
+ V rs: 0xbfc00226 rt: 0xbfc00226
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00226 09: 00000061 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf000f1>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0xf1
+ r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31
+ V rs: 0xbfc00150 rt: 0xdea9
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00227 09: 00000061 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00227 09: 00000061 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x81090000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x20 (lb)
+ i rs: 0x8 rt: 0x9 i: 0
+ r rs: 8 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xbfc00227 rt: 0x61
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00227 09: 00000061 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_READ @ 0xbfc00224 wdata 0 be 0x8> off: 0x3 sign_ext: 0x1 dest: gp+0x9
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp valid no error rdata 0x74617473>, 0)
+mips0 setData: <DataRsp valid no error rdata 0x74617473> off: 0 sign_ext: 0x1 dest: r_gp+0x9
+mips0 setData: <DataRsp valid no error rdata 0x74617473> off: 0 count: 0x1 le: 0x3 old: 0x61 from_mem: 0x74617473 mask: 0xffffffff new_data: 0x74
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0x9 rt: 0 i: 0x5
+ r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5
+ V rs: 0x74 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00227 09: 00000074 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00227 09: 00000074 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+amips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa3490000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0x9 i: 0
+ r rs: 26 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x74
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00227 09: 00000074 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x74 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0x8 rt: 0x8 i: 0x1
+ r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1
+ V rs: 0xbfc00227 rt: 0xbfc00227
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00227 09: 00000074 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf000f1>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0xf1
+ r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31
+ V rs: 0xbfc00150 rt: 0xdea9
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00228 09: 00000074 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00228 09: 00000074 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x81090000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x20 (lb)
+ i rs: 0x8 rt: 0x9 i: 0
+ r rs: 8 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xbfc00228 rt: 0x74
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00228 09: 00000074 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_READ @ 0xbfc00228 wdata 0 be 0x1> off: 0 sign_ext: 0x1 dest: gp+0x9
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp valid no error rdata 0x207375>, 0)
+mips0 setData: <DataRsp valid no error rdata 0x207375> off: 0 sign_ext: 0x1 dest: r_gp+0x9
+mips0 setData: <DataRsp valid no error rdata 0x207375> off: 0 count: 0x1 le: 0 old: 0x74 from_mem: 0x207375 mask: 0xffffffff new_data: 0x75
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0x9 rt: 0 i: 0x5
+ r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5
+ V rs: 0x75 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00228 09: 00000075 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00228 09: 00000075 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa3490000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0x9 i: 0
+ r rs: 26 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x75
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00228 09: 00000075 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x75 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+tmips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0x8 rt: 0x8 i: 0x1
+ r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1
+ V rs: 0xbfc00228 rt: 0xbfc00228
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00228 09: 00000075 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf000f1>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0xf1
+ r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31
+ V rs: 0xbfc00150 rt: 0xdea9
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00229 09: 00000075 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00229 09: 00000075 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x81090000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x20 (lb)
+ i rs: 0x8 rt: 0x9 i: 0
+ r rs: 8 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xbfc00229 rt: 0x75
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00229 09: 00000075 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_READ @ 0xbfc00228 wdata 0 be 0x2> off: 0x1 sign_ext: 0x1 dest: gp+0x9
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp valid no error rdata 0x207375>, 0)
+mips0 setData: <DataRsp valid no error rdata 0x207375> off: 0 sign_ext: 0x1 dest: r_gp+0x9
+mips0 setData: <DataRsp valid no error rdata 0x207375> off: 0 count: 0x1 le: 0x1 old: 0x75 from_mem: 0x207375 mask: 0xffffffff new_data: 0x73
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0x9 rt: 0 i: 0x5
+ r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5
+ V rs: 0x73 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00229 09: 00000073 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00229 09: 00000073 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa3490000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0x9 i: 0
+ r rs: 26 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x73
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00229 09: 00000073 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x73 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+umips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0x8 rt: 0x8 i: 0x1
+ r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1
+ V rs: 0xbfc00229 rt: 0xbfc00229
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00229 09: 00000073 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf000f1>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0xf1
+ r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31
+ V rs: 0xbfc00150 rt: 0xdea9
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0022a 09: 00000073 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0022a 09: 00000073 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x81090000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x20 (lb)
+ i rs: 0x8 rt: 0x9 i: 0
+ r rs: 8 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xbfc0022a rt: 0x73
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0022a 09: 00000073 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_READ @ 0xbfc00228 wdata 0 be 0x4> off: 0x2 sign_ext: 0x1 dest: gp+0x9
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp valid no error rdata 0x207375>, 0)
+mips0 setData: <DataRsp valid no error rdata 0x207375> off: 0 sign_ext: 0x1 dest: r_gp+0x9
+mips0 setData: <DataRsp valid no error rdata 0x207375> off: 0 count: 0x1 le: 0x2 old: 0x73 from_mem: 0x207375 mask: 0xffffffff new_data: 0x20
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0x9 rt: 0 i: 0x5
+ r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5
+ V rs: 0x20 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0022a 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0022a 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa3490000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0x9 i: 0
+ r rs: 26 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x20
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0022a 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x20 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+smips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0x8 rt: 0x8 i: 0x1
+ r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1
+ V rs: 0xbfc0022a rt: 0xbfc0022a
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0022a 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf000f1>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0xf1
+ r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31
+ V rs: 0xbfc00150 rt: 0xdea9
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0022b 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0022b 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x81090000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x20 (lb)
+ i rs: 0x8 rt: 0x9 i: 0
+ r rs: 8 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xbfc0022b rt: 0x20
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0022b 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_READ @ 0xbfc00228 wdata 0 be 0x8> off: 0x3 sign_ext: 0x1 dest: gp+0x9
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp valid no error rdata 0x207375>, 0)
+mips0 setData: <DataRsp valid no error rdata 0x207375> off: 0 sign_ext: 0x1 dest: r_gp+0x9
+mips0 setData: <DataRsp valid no error rdata 0x207375> off: 0 count: 0x1 le: 0x3 old: 0x20 from_mem: 0x207375 mask: 0xffffffff new_data: 0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0x9 rt: 0 i: 0x5
+ r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0022b 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003e0 m_ifetch_addr: 0xbfc003cc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003cc NPC: 0xbfc003e0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0022b 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 m_next_pc: 0xbfc003e0 m_jump_pc: 0xbfc003e4 m_ifetch_addr: 0xbfc003e0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3e00008>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003e0 NPC: 0xbfc003e4 Ins: 0x3e00008
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x1f rt: 0 i: 0x8
+ r rs: 31 rt: 0 rd: 0 sh: 0 func: 0x8
+ V rs: 0xbfc00150 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0022b 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 m_next_pc: 0xbfc003e4 m_jump_pc: 0xbfc00150 m_ifetch_addr: 0xbfc003e4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+ mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003e4 NPC: 0xbfc00150 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0022b 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 m_next_pc: 0xbfc00150 m_jump_pc: 0xbfc00154 m_ifetch_addr: 0xbfc00150
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x40046000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00150 NPC: 0xbfc00154 Ins: 0x40046000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x10 (cop0)
+ i rs: 0 rt: 0x4 i: 0x6000
+ r rs: 0 rt: 4 rd: 12 sh: 0 func: 0
+ V rs: 0 rt: 0xbfc00224
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0022b 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 m_next_pc: 0xbfc00154 m_jump_pc: 0xbfc00158 m_ifetch_addr: 0xbfc00154
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xff000fa>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00154 NPC: 0xbfc00158 Ins: 0xff000fa
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x3 (jal)
+ i rs: 0x1f rt: 0x10 i: 0xfa
+ r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x3a
+ V rs: 0xbfc00150 rt: 0xdea9
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0022b 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 m_next_pc: 0xbfc00158 m_jump_pc: 0xbfc003e8 m_ifetch_addr: 0xbfc00158
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00158 NPC: 0xbfc003e8 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0022b 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc003e8 m_jump_pc: 0xbfc003ec m_ifetch_addr: 0xbfc003e8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x804021>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003e8 NPC: 0xbfc003ec Ins: 0x804021
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x4 rt: 0 i: 0x4021
+ r rs: 4 rt: 0 rd: 8 sh: 0 func: 0x21
+ V rs: 0x400403 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0022b 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc003ec m_jump_pc: 0xbfc003f0 m_ifetch_addr: 0xbfc003ec
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x24090030>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003ec NPC: 0xbfc003f0 Ins: 0x24090030
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0 rt: 0x9 i: 0x30
+ r rs: 0 rt: 9 rd: 0 sh: 0 func: 0x30
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 00400403 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc003f0 m_jump_pc: 0xbfc003f4 m_ifetch_addr: 0xbfc003f0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa3490000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003f0 NPC: 0xbfc003f4 Ins: 0xa3490000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0x9 i: 0
+ r rs: 26 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 00400403 09: 00000030 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc003f4 m_jump_pc: 0xbfc003f8 m_ifetch_addr: 0xbfc003f4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x24090078>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc003f4 NPC: 0xbfc003f8 Ins: 0x24090078
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0 rt: 0x9 i: 0x78
+ r rs: 0 rt: 9 rd: 0 sh: 1 func: 0x38
+ V rs: 0 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 00400403 09: 00000030 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc003f8 m_jump_pc: 0xbfc003fc m_ifetch_addr: 0xbfc003f8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa3490000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003f8 NPC: 0xbfc003fc Ins: 0xa3490000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0x9 i: 0
+ r rs: 26 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x78
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 00400403 09: 00000078 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x78 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc003fc m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc003fc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x24090008>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc003fc NPC: 0xbfc00400 Ins: 0x24090008
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0 rt: 0x9 i: 0x8
+ r rs: 0 rt: 9 rd: 0 sh: 0 func: 0x8
+ V rs: 0 rt: 0x78
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 00400403 09: 00000078 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c0af000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0xa i: 0xf000
+ r rs: 0 rt: 10 rd: 30 sh: 0 func: 0
+ V rs: 0 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 00400403 09: 00000008 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x10a5024>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x8 rt: 0xa i: 0x5024
+ r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24
+ V rs: 0x400403 rt: 0xf0000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 00400403 09: 00000008 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa5702>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0xa i: 0x5702
+ r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 00400403 09: 00000008 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+0mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x294b000a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xa (slti)
+ i rs: 0xa rt: 0xb i: 0xa
+ r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa
+ V rs: 0 rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 00400403 09: 00000008 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11600004>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0xb rt: 0 i: 0x4
+ r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4
+ V rs: 0x1 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 00400403 09: 00000008 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 00400403 09: 00000008 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x214a0030>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0xa rt: 0xa i: 0x30
+ r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 00400403 09: 00000008 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0010a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0x10a
+ r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa
+ V rs: 0xbfc0015c rt: 0xdea9
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 00400403 09: 00000008 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 00400403 09: 00000008 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa34a0000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0xa i: 0
+ r rs: 26 rt: 10 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 00400403 09: 00000008 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2129ffff>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0x9 rt: 0x9 i: 0xffff
+ r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f
+ V rs: 0x8 rt: 0x8
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 00400403 09: 00000008 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x1d20fff3>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x7 (bgtz)
+ i rs: 0x9 rt: 0 i: 0xfff3
+ r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33
+ V rs: 0x7 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 00400403 09: 00000007 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x84100>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0x8 i: 0x4100
+ r rs: 0 rt: 8 rd: 8 sh: 4 func: 0
+ V rs: 0 rt: 0x400403
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 00400403 09: 00000007 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+xmips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c0af000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0xa i: 0xf000
+ r rs: 0 rt: 10 rd: 30 sh: 0 func: 0
+ V rs: 0 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 04004030 09: 00000007 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x10a5024>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x8 rt: 0xa i: 0x5024
+ r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24
+ V rs: 0x4004030 rt: 0xf0000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 04004030 09: 00000007 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa5702>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0xa i: 0x5702
+ r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 04004030 09: 00000007 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x294b000a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xa (slti)
+ i rs: 0xa rt: 0xb i: 0xa
+ r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa
+ V rs: 0 rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 04004030 09: 00000007 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11600004>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0xb rt: 0 i: 0x4
+ r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4
+ V rs: 0x1 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 04004030 09: 00000007 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 04004030 09: 00000007 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x214a0030>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0xa rt: 0xa i: 0x30
+ r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 04004030 09: 00000007 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0010a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0x10a
+ r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa
+ V rs: 0xbfc0015c rt: 0xdea9
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 04004030 09: 00000007 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 04004030 09: 00000007 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa34a0000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0xa i: 0
+ r rs: 26 rt: 10 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 04004030 09: 00000007 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+0mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2129ffff>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0x9 rt: 0x9 i: 0xffff
+ r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f
+ V rs: 0x7 rt: 0x7
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 04004030 09: 00000007 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x1d20fff3>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x7 (bgtz)
+ i rs: 0x9 rt: 0 i: 0xfff3
+ r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33
+ V rs: 0x6 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 04004030 09: 00000006 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x84100>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0x8 i: 0x4100
+ r rs: 0 rt: 8 rd: 8 sh: 4 func: 0
+ V rs: 0 rt: 0x4004030
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 04004030 09: 00000006 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c0af000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0xa i: 0xf000
+ r rs: 0 rt: 10 rd: 30 sh: 0 func: 0
+ V rs: 0 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 40040300 09: 00000006 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x10a5024>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x8 rt: 0xa i: 0x5024
+ r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24
+ V rs: 0x40040300 rt: 0xf0000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 40040300 09: 00000006 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa5702>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0xa i: 0x5702
+ r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2
+ V rs: 0 rt: 0x40000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 40040300 09: 00000006 10: 40000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x294b000a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xa (slti)
+ i rs: 0xa rt: 0xb i: 0xa
+ r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa
+ V rs: 0x4 rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 40040300 09: 00000006 10: 00000004 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11600004>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0xb rt: 0 i: 0x4
+ r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4
+ V rs: 0x1 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 40040300 09: 00000006 10: 00000004 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 40040300 09: 00000006 10: 00000004 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x214a0030>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0xa rt: 0xa i: 0x30
+ r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30
+ V rs: 0x4 rt: 0x4
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 40040300 09: 00000006 10: 00000004 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+0mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0010a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0x10a
+ r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa
+ V rs: 0xbfc0015c rt: 0xdea9
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 40040300 09: 00000006 10: 00000034 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 40040300 09: 00000006 10: 00000034 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa34a0000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0xa i: 0
+ r rs: 26 rt: 10 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x34
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 40040300 09: 00000006 10: 00000034 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x34 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2129ffff>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0x9 rt: 0x9 i: 0xffff
+ r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f
+ V rs: 0x6 rt: 0x6
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 40040300 09: 00000006 10: 00000034 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x1d20fff3>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x7 (bgtz)
+ i rs: 0x9 rt: 0 i: 0xfff3
+ r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33
+ V rs: 0x5 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 40040300 09: 00000005 10: 00000034 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x84100>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0x8 i: 0x4100
+ r rs: 0 rt: 8 rd: 8 sh: 4 func: 0
+ V rs: 0 rt: 0x40040300
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 40040300 09: 00000005 10: 00000034 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c0af000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0xa i: 0xf000
+ r rs: 0 rt: 10 rd: 30 sh: 0 func: 0
+ V rs: 0 rt: 0x34
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 00403000 09: 00000005 10: 00000034 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x10a5024>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x8 rt: 0xa i: 0x5024
+ r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24
+ V rs: 0x403000 rt: 0xf0000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 00403000 09: 00000005 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa5702>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0xa i: 0x5702
+ r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 00403000 09: 00000005 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x294b000a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xa (slti)
+ i rs: 0xa rt: 0xb i: 0xa
+ r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa
+ V rs: 0 rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 00403000 09: 00000005 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+4mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11600004>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0xb rt: 0 i: 0x4
+ r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4
+ V rs: 0x1 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 00403000 09: 00000005 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 00403000 09: 00000005 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x214a0030>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0xa rt: 0xa i: 0x30
+ r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 00403000 09: 00000005 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0010a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0x10a
+ r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa
+ V rs: 0xbfc0015c rt: 0xdea9
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 00403000 09: 00000005 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 00403000 09: 00000005 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa34a0000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0xa i: 0
+ r rs: 26 rt: 10 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 00403000 09: 00000005 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2129ffff>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0x9 rt: 0x9 i: 0xffff
+ r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f
+ V rs: 0x5 rt: 0x5
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 00403000 09: 00000005 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x1d20fff3>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x7 (bgtz)
+ i rs: 0x9 rt: 0 i: 0xfff3
+ r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33
+ V rs: 0x4 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 00403000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x84100>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0x8 i: 0x4100
+ r rs: 0 rt: 8 rd: 8 sh: 4 func: 0
+ V rs: 0 rt: 0x403000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 00403000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c0af000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0xa i: 0xf000
+ r rs: 0 rt: 10 rd: 30 sh: 0 func: 0
+ V rs: 0 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 04030000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x10a5024>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x8 rt: 0xa i: 0x5024
+ r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24
+ V rs: 0x4030000 rt: 0xf0000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 04030000 09: 00000004 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa5702>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0xa i: 0x5702
+ r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 04030000 09: 00000004 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+0mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x294b000a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xa (slti)
+ i rs: 0xa rt: 0xb i: 0xa
+ r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa
+ V rs: 0 rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 04030000 09: 00000004 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11600004>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0xb rt: 0 i: 0x4
+ r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4
+ V rs: 0x1 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 04030000 09: 00000004 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 04030000 09: 00000004 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x214a0030>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0xa rt: 0xa i: 0x30
+ r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 04030000 09: 00000004 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0010a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0x10a
+ r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa
+ V rs: 0xbfc0015c rt: 0xdea9
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 04030000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 04030000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa34a0000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0xa i: 0
+ r rs: 26 rt: 10 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 04030000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2129ffff>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0x9 rt: 0x9 i: 0xffff
+ r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f
+ V rs: 0x4 rt: 0x4
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 04030000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x1d20fff3>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x7 (bgtz)
+ i rs: 0x9 rt: 0 i: 0xfff3
+ r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33
+ V rs: 0x3 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 04030000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x84100>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0x8 i: 0x4100
+ r rs: 0 rt: 8 rd: 8 sh: 4 func: 0
+ V rs: 0 rt: 0x4030000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 04030000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c0af000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0xa i: 0xf000
+ r rs: 0 rt: 10 rd: 30 sh: 0 func: 0
+ V rs: 0 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 40300000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x10a5024>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x8 rt: 0xa i: 0x5024
+ r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24
+ V rs: 0x40300000 rt: 0xf0000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 40300000 09: 00000003 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa5702>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0xa i: 0x5702
+ r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2
+ V rs: 0 rt: 0x40000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 40300000 09: 00000003 10: 40000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+0mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x294b000a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xa (slti)
+ i rs: 0xa rt: 0xb i: 0xa
+ r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa
+ V rs: 0x4 rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 40300000 09: 00000003 10: 00000004 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11600004>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0xb rt: 0 i: 0x4
+ r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4
+ V rs: 0x1 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 40300000 09: 00000003 10: 00000004 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 40300000 09: 00000003 10: 00000004 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x214a0030>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0xa rt: 0xa i: 0x30
+ r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30
+ V rs: 0x4 rt: 0x4
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 40300000 09: 00000003 10: 00000004 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0010a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0x10a
+ r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa
+ V rs: 0xbfc0015c rt: 0xdea9
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 40300000 09: 00000003 10: 00000034 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 40300000 09: 00000003 10: 00000034 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa34a0000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0xa i: 0
+ r rs: 26 rt: 10 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x34
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 40300000 09: 00000003 10: 00000034 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x34 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2129ffff>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0x9 rt: 0x9 i: 0xffff
+ r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f
+ V rs: 0x3 rt: 0x3
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 40300000 09: 00000003 10: 00000034 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x1d20fff3>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x7 (bgtz)
+ i rs: 0x9 rt: 0 i: 0xfff3
+ r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33
+ V rs: 0x2 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 40300000 09: 00000002 10: 00000034 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x84100>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0x8 i: 0x4100
+ r rs: 0 rt: 8 rd: 8 sh: 4 func: 0
+ V rs: 0 rt: 0x40300000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 40300000 09: 00000002 10: 00000034 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c0af000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0xa i: 0xf000
+ r rs: 0 rt: 10 rd: 30 sh: 0 func: 0
+ V rs: 0 rt: 0x34
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 03000000 09: 00000002 10: 00000034 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x10a5024>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x8 rt: 0xa i: 0x5024
+ r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24
+ V rs: 0x3000000 rt: 0xf0000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 03000000 09: 00000002 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa5702>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0xa i: 0x5702
+ r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 03000000 09: 00000002 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+4mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x294b000a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xa (slti)
+ i rs: 0xa rt: 0xb i: 0xa
+ r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa
+ V rs: 0 rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 03000000 09: 00000002 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11600004>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0xb rt: 0 i: 0x4
+ r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4
+ V rs: 0x1 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 03000000 09: 00000002 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 03000000 09: 00000002 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x214a0030>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0xa rt: 0xa i: 0x30
+ r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 03000000 09: 00000002 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0010a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0x10a
+ r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa
+ V rs: 0xbfc0015c rt: 0xdea9
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 03000000 09: 00000002 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 03000000 09: 00000002 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa34a0000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0xa i: 0
+ r rs: 26 rt: 10 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 03000000 09: 00000002 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2129ffff>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0x9 rt: 0x9 i: 0xffff
+ r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f
+ V rs: 0x2 rt: 0x2
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 03000000 09: 00000002 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x1d20fff3>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x7 (bgtz)
+ i rs: 0x9 rt: 0 i: 0xfff3
+ r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33
+ V rs: 0x1 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 03000000 09: 00000001 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x84100>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0x8 i: 0x4100
+ r rs: 0 rt: 8 rd: 8 sh: 4 func: 0
+ V rs: 0 rt: 0x3000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 03000000 09: 00000001 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c0af000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0xa i: 0xf000
+ r rs: 0 rt: 10 rd: 30 sh: 0 func: 0
+ V rs: 0 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 30000000 09: 00000001 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x10a5024>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x8 rt: 0xa i: 0x5024
+ r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24
+ V rs: 0x30000000 rt: 0xf0000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 30000000 09: 00000001 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa5702>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0xa i: 0x5702
+ r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2
+ V rs: 0 rt: 0x30000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 30000000 09: 00000001 10: 30000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+0mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x294b000a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xa (slti)
+ i rs: 0xa rt: 0xb i: 0xa
+ r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa
+ V rs: 0x3 rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 30000000 09: 00000001 10: 00000003 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11600004>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0xb rt: 0 i: 0x4
+ r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4
+ V rs: 0x1 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 30000000 09: 00000001 10: 00000003 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 30000000 09: 00000001 10: 00000003 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x214a0030>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0xa rt: 0xa i: 0x30
+ r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30
+ V rs: 0x3 rt: 0x3
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 30000000 09: 00000001 10: 00000003 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0010a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0x10a
+ r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa
+ V rs: 0xbfc0015c rt: 0xdea9
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 30000000 09: 00000001 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 30000000 09: 00000001 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa34a0000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0xa i: 0
+ r rs: 26 rt: 10 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x33
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 30000000 09: 00000001 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x33 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2129ffff>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0x9 rt: 0x9 i: 0xffff
+ r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f
+ V rs: 0x1 rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 30000000 09: 00000001 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x1d20fff3>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x7 (bgtz)
+ i rs: 0x9 rt: 0 i: 0xfff3
+ r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 30000000 09: 00000000 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00438 m_ifetch_addr: 0xbfc00434
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x84100>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00434 NPC: 0xbfc00438 Ins: 0x84100
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0x8 i: 0x4100
+ r rs: 0 rt: 8 rd: 8 sh: 4 func: 0
+ V rs: 0 rt: 0x30000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 30000000 09: 00000000 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00438 m_jump_pc: 0xbfc0043c m_ifetch_addr: 0xbfc00438
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3e00008>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00438 NPC: 0xbfc0043c Ins: 0x3e00008
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x1f rt: 0 i: 0x8
+ r rs: 31 rt: 0 rd: 0 sh: 0 func: 0x8
+ V rs: 0xbfc0015c rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc0043c m_jump_pc: 0xbfc0015c m_ifetch_addr: 0xbfc0043c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0043c NPC: 0xbfc0015c Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc0015c m_jump_pc: 0xbfc00160 m_ifetch_addr: 0xbfc0015c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c04bfc0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0015c NPC: 0xbfc00160 Ins: 0x3c04bfc0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0x4 i: 0xbfc0
+ r rs: 0 rt: 4 rd: 23 sh: 31 func: 0
+ V rs: 0 rt: 0x400403
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00160 m_jump_pc: 0xbfc00164 m_ifetch_addr: 0xbfc00160
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+3mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x24840234>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00160 NPC: 0xbfc00164 Ins: 0x24840234
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0x4 rt: 0x4 i: 0x234
+ r rs: 4 rt: 4 rd: 0 sh: 8 func: 0x34
+ V rs: 0xbfc00000 rt: 0xbfc00000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00164 m_jump_pc: 0xbfc00168 m_ifetch_addr: 0xbfc00164
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xff000f0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00164 NPC: 0xbfc00168 Ins: 0xff000f0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x3 (jal)
+ i rs: 0x1f rt: 0x10 i: 0xf0
+ r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x30
+ V rs: 0xbfc0015c rt: 0xdea9
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00168 m_jump_pc: 0xbfc003c0 m_ifetch_addr: 0xbfc00168
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00168 NPC: 0xbfc003c0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c
+mips0 m_next_pc: 0xbfc003c0 m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003c0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x804021>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c0 NPC: 0xbfc003c4 Ins: 0x804021
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x4 rt: 0 i: 0x4021
+ r rs: 4 rt: 0 rd: 8 sh: 0 func: 0x21
+ V rs: 0xbfc00234 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c
+mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x81090000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x20 (lb)
+ i rs: 0x8 rt: 0x9 i: 0
+ r rs: 8 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xbfc00234 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00234 09: 00000000 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_READ @ 0xbfc00234 wdata 0 be 0x1> off: 0 sign_ext: 0x1 dest: gp+0x9
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp valid no error rdata 0x20637020>, 0)
+mips0 setData: <DataRsp valid no error rdata 0x20637020> off: 0 sign_ext: 0x1 dest: r_gp+0x9
+mips0 setData: <DataRsp valid no error rdata 0x20637020> off: 0 count: 0x1 le: 0 old: 0 from_mem: 0x20637020 mask: 0xffffffff new_data: 0x20
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0x9 rt: 0 i: 0x5
+ r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5
+ V rs: 0x20 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00234 09: 00000020 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c
+mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00234 09: 00000020 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c
+mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa3490000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0x9 i: 0
+ r rs: 26 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x20
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00234 09: 00000020 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x20 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0x8 rt: 0x8 i: 0x1
+ r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1
+ V rs: 0xbfc00234 rt: 0xbfc00234
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00234 09: 00000020 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c
+mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf000f1>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0xf1
+ r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31
+ V rs: 0xbfc0016c rt: 0xdea9
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00235 09: 00000020 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c
+mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00235 09: 00000020 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c
+mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x81090000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x20 (lb)
+ i rs: 0x8 rt: 0x9 i: 0
+ r rs: 8 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xbfc00235 rt: 0x20
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00235 09: 00000020 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_READ @ 0xbfc00234 wdata 0 be 0x2> off: 0x1 sign_ext: 0x1 dest: gp+0x9
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp valid no error rdata 0x20637020>, 0)
+mips0 setData: <DataRsp valid no error rdata 0x20637020> off: 0 sign_ext: 0x1 dest: r_gp+0x9
+mips0 setData: <DataRsp valid no error rdata 0x20637020> off: 0 count: 0x1 le: 0x1 old: 0x20 from_mem: 0x20637020 mask: 0xffffffff new_data: 0x70
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1
+ mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0x9 rt: 0 i: 0x5
+ r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5
+ V rs: 0x70 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00235 09: 00000070 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c
+mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00235 09: 00000070 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c
+mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa3490000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0x9 i: 0
+ r rs: 26 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x70
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00235 09: 00000070 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x70 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0x8 rt: 0x8 i: 0x1
+ r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1
+ V rs: 0xbfc00235 rt: 0xbfc00235
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00235 09: 00000070 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c
+mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf000f1>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0xf1
+ r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31
+ V rs: 0xbfc0016c rt: 0xdea9
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00236 09: 00000070 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c
+mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00236 09: 00000070 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c
+mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x81090000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x20 (lb)
+ i rs: 0x8 rt: 0x9 i: 0
+ r rs: 8 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xbfc00236 rt: 0x70
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00236 09: 00000070 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_READ @ 0xbfc00234 wdata 0 be 0x4> off: 0x2 sign_ext: 0x1 dest: gp+0x9
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp valid no error rdata 0x20637020>, 0)
+mips0 setData: <DataRsp valid no error rdata 0x20637020> off: 0 sign_ext: 0x1 dest: r_gp+0x9
+mips0 setData: <DataRsp valid no error rdata 0x20637020> off: 0 count: 0x1 le: 0x2 old: 0x70 from_mem: 0x20637020 mask: 0xffffffff new_data: 0x63
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0x9 rt: 0 i: 0x5
+ r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5
+ V rs: 0x63 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00236 09: 00000063 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c
+mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+pmips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00236 09: 00000063 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c
+mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa3490000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0x9 i: 0
+ r rs: 26 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x63
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00236 09: 00000063 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x63 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0x8 rt: 0x8 i: 0x1
+ r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1
+ V rs: 0xbfc00236 rt: 0xbfc00236
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00236 09: 00000063 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c
+mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf000f1>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0xf1
+ r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31
+ V rs: 0xbfc0016c rt: 0xdea9
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00237 09: 00000063 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c
+mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00237 09: 00000063 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c
+mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x81090000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x20 (lb)
+ i rs: 0x8 rt: 0x9 i: 0
+ r rs: 8 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xbfc00237 rt: 0x63
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00237 09: 00000063 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_READ @ 0xbfc00234 wdata 0 be 0x8> off: 0x3 sign_ext: 0x1 dest: gp+0x9
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp valid no error rdata 0x20637020>, 0)
+mips0 setData: <DataRsp valid no error rdata 0x20637020> off: 0 sign_ext: 0x1 dest: r_gp+0x9
+mips0 setData: <DataRsp valid no error rdata 0x20637020> off: 0 count: 0x1 le: 0x3 old: 0x63 from_mem: 0x20637020 mask: 0xffffffff new_data: 0x20
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0x9 rt: 0 i: 0x5
+ r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5
+ V rs: 0x20 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00237 09: 00000020 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c
+mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00237 09: 00000020 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c
+mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+cmips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa3490000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0x9 i: 0
+ r rs: 26 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x20
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00237 09: 00000020 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x20 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0x8 rt: 0x8 i: 0x1
+ r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1
+ V rs: 0xbfc00237 rt: 0xbfc00237
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00237 09: 00000020 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c
+mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf000f1>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0xf1
+ r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31
+ V rs: 0xbfc0016c rt: 0xdea9
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00238 09: 00000020 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c
+mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00238 09: 00000020 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c
+mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x81090000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x20 (lb)
+ i rs: 0x8 rt: 0x9 i: 0
+ r rs: 8 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xbfc00238 rt: 0x20
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00238 09: 00000020 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_READ @ 0xbfc00238 wdata 0 be 0x1> off: 0 sign_ext: 0x1 dest: gp+0x9
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp valid no error rdata 0x61622000>, 0)
+mips0 setData: <DataRsp valid no error rdata 0x61622000> off: 0 sign_ext: 0x1 dest: r_gp+0x9
+mips0 setData: <DataRsp valid no error rdata 0x61622000> off: 0 count: 0x1 le: 0 old: 0x20 from_mem: 0x61622000 mask: 0xffffffff new_data: 0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0x9 rt: 0 i: 0x5
+ r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00238 09: 00000000 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c
+mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003e0 m_ifetch_addr: 0xbfc003cc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003cc NPC: 0xbfc003e0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00238 09: 00000000 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c
+mips0 m_next_pc: 0xbfc003e0 m_jump_pc: 0xbfc003e4 m_ifetch_addr: 0xbfc003e0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3e00008>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003e0 NPC: 0xbfc003e4 Ins: 0x3e00008
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x1f rt: 0 i: 0x8
+ r rs: 31 rt: 0 rd: 0 sh: 0 func: 0x8
+ V rs: 0xbfc0016c rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00238 09: 00000000 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c
+mips0 m_next_pc: 0xbfc003e4 m_jump_pc: 0xbfc0016c m_ifetch_addr: 0xbfc003e4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+ mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003e4 NPC: 0xbfc0016c Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00238 09: 00000000 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c
+mips0 m_next_pc: 0xbfc0016c m_jump_pc: 0xbfc00170 m_ifetch_addr: 0xbfc0016c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x40047000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0016c NPC: 0xbfc00170 Ins: 0x40047000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x10 (cop0)
+ i rs: 0 rt: 0x4 i: 0x7000
+ r rs: 0 rt: 4 rd: 14 sh: 0 func: 0
+ V rs: 0 rt: 0xbfc00234
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00238 09: 00000000 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c
+mips0 m_next_pc: 0xbfc00170 m_jump_pc: 0xbfc00174 m_ifetch_addr: 0xbfc00170
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xff000fa>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00170 NPC: 0xbfc00174 Ins: 0xff000fa
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x3 (jal)
+ i rs: 0x1f rt: 0x10 i: 0xfa
+ r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x3a
+ V rs: 0xbfc0016c rt: 0xdea9
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00238 09: 00000000 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c
+mips0 m_next_pc: 0xbfc00174 m_jump_pc: 0xbfc003e8 m_ifetch_addr: 0xbfc00174
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00174 NPC: 0xbfc003e8 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00238 09: 00000000 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc003e8 m_jump_pc: 0xbfc003ec m_ifetch_addr: 0xbfc003e8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x804021>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003e8 NPC: 0xbfc003ec Ins: 0x804021
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x4 rt: 0 i: 0x4021
+ r rs: 4 rt: 0 rd: 8 sh: 0 func: 0x21
+ V rs: 0xbfc00078 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00238 09: 00000000 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc003ec m_jump_pc: 0xbfc003f0 m_ifetch_addr: 0xbfc003ec
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x24090030>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003ec NPC: 0xbfc003f0 Ins: 0x24090030
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0 rt: 0x9 i: 0x30
+ r rs: 0 rt: 9 rd: 0 sh: 0 func: 0x30
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00078 09: 00000000 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc003f0 m_jump_pc: 0xbfc003f4 m_ifetch_addr: 0xbfc003f0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa3490000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003f0 NPC: 0xbfc003f4 Ins: 0xa3490000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0x9 i: 0
+ r rs: 26 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00078 09: 00000030 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc003f4 m_jump_pc: 0xbfc003f8 m_ifetch_addr: 0xbfc003f4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x24090078>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc003f4 NPC: 0xbfc003f8 Ins: 0x24090078
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0 rt: 0x9 i: 0x78
+ r rs: 0 rt: 9 rd: 0 sh: 1 func: 0x38
+ V rs: 0 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00078 09: 00000030 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc003f8 m_jump_pc: 0xbfc003fc m_ifetch_addr: 0xbfc003f8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa3490000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003f8 NPC: 0xbfc003fc Ins: 0xa3490000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0x9 i: 0
+ r rs: 26 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x78
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00078 09: 00000078 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x78 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc003fc m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc003fc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x24090008>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc003fc NPC: 0xbfc00400 Ins: 0x24090008
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0 rt: 0x9 i: 0x8
+ r rs: 0 rt: 9 rd: 0 sh: 0 func: 0x8
+ V rs: 0 rt: 0x78
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00078 09: 00000078 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c0af000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0xa i: 0xf000
+ r rs: 0 rt: 10 rd: 30 sh: 0 func: 0
+ V rs: 0 rt: 0x33
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00078 09: 00000008 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x10a5024>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x8 rt: 0xa i: 0x5024
+ r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24
+ V rs: 0xbfc00078 rt: 0xf0000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00078 09: 00000008 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa5702>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0xa i: 0x5702
+ r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2
+ V rs: 0 rt: 0xb0000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00078 09: 00000008 10: b0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+0mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x294b000a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xa (slti)
+ i rs: 0xa rt: 0xb i: 0xa
+ r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa
+ V rs: 0xb rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00078 09: 00000008 10: 0000000b 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11600004>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0xb rt: 0 i: 0x4
+ r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00078 09: 00000008 10: 0000000b 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00424 m_ifetch_addr: 0xbfc00414
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00414 NPC: 0xbfc00424 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00078 09: 00000008 10: 0000000b 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00424 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00424
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x214a0037>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00424 NPC: 0xbfc00428 Ins: 0x214a0037
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0xa rt: 0xa i: 0x37
+ r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x37
+ V rs: 0xb rt: 0xb
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00078 09: 00000008 10: 0000000b 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa34a0000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0xa i: 0
+ r rs: 26 rt: 10 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x42
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00078 09: 00000008 10: 00000042 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x42 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2129ffff>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0x9 rt: 0x9 i: 0xffff
+ r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f
+ V rs: 0x8 rt: 0x8
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00078 09: 00000008 10: 00000042 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x1d20fff3>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x7 (bgtz)
+ i rs: 0x9 rt: 0 i: 0xfff3
+ r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33
+ V rs: 0x7 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00078 09: 00000007 10: 00000042 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x84100>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0x8 i: 0x4100
+ r rs: 0 rt: 8 rd: 8 sh: 4 func: 0
+ V rs: 0 rt: 0xbfc00078
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00078 09: 00000007 10: 00000042 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c0af000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0xa i: 0xf000
+ r rs: 0 rt: 10 rd: 30 sh: 0 func: 0
+ V rs: 0 rt: 0x42
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000
+ 08: fc000780 09: 00000007 10: 00000042 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x10a5024>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x8 rt: 0xa i: 0x5024
+ r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24
+ V rs: 0xfc000780 rt: 0xf0000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000
+ 08: fc000780 09: 00000007 10: f0000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+xmips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa5702>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0xa i: 0x5702
+ r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2
+ V rs: 0 rt: 0xf0000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000
+ 08: fc000780 09: 00000007 10: f0000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x294b000a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xa (slti)
+ i rs: 0xa rt: 0xb i: 0xa
+ r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa
+ V rs: 0xf rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000
+ 08: fc000780 09: 00000007 10: 0000000f 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11600004>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0xb rt: 0 i: 0x4
+ r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000
+ 08: fc000780 09: 00000007 10: 0000000f 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00424 m_ifetch_addr: 0xbfc00414
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00414 NPC: 0xbfc00424 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000
+ 08: fc000780 09: 00000007 10: 0000000f 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00424 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00424
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x214a0037>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00424 NPC: 0xbfc00428 Ins: 0x214a0037
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0xa rt: 0xa i: 0x37
+ r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x37
+ V rs: 0xf rt: 0xf
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000
+ 08: fc000780 09: 00000007 10: 0000000f 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa34a0000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0xa i: 0
+ r rs: 26 rt: 10 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x46
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000
+ 08: fc000780 09: 00000007 10: 00000046 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x46 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2129ffff>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0x9 rt: 0x9 i: 0xffff
+ r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f
+ V rs: 0x7 rt: 0x7
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000
+ 08: fc000780 09: 00000007 10: 00000046 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x1d20fff3>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x7 (bgtz)
+ i rs: 0x9 rt: 0 i: 0xfff3
+ r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33
+ V rs: 0x6 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000
+ 08: fc000780 09: 00000006 10: 00000046 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x84100>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0x8 i: 0x4100
+ r rs: 0 rt: 8 rd: 8 sh: 4 func: 0
+ V rs: 0 rt: 0xfc000780
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000
+ 08: fc000780 09: 00000006 10: 00000046 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c0af000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0xa i: 0xf000
+ r rs: 0 rt: 10 rd: 30 sh: 0 func: 0
+ V rs: 0 rt: 0x46
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000
+ 08: c0007800 09: 00000006 10: 00000046 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+Bmips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x10a5024>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x8 rt: 0xa i: 0x5024
+ r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24
+ V rs: 0xc0007800 rt: 0xf0000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000
+ 08: c0007800 09: 00000006 10: f0000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa5702>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0xa i: 0x5702
+ r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2
+ V rs: 0 rt: 0xc0000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000
+ 08: c0007800 09: 00000006 10: c0000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x294b000a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xa (slti)
+ i rs: 0xa rt: 0xb i: 0xa
+ r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa
+ V rs: 0xc rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000
+ 08: c0007800 09: 00000006 10: 0000000c 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11600004>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0xb rt: 0 i: 0x4
+ r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000
+ 08: c0007800 09: 00000006 10: 0000000c 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00424 m_ifetch_addr: 0xbfc00414
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00414 NPC: 0xbfc00424 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000
+ 08: c0007800 09: 00000006 10: 0000000c 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00424 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00424
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x214a0037>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00424 NPC: 0xbfc00428 Ins: 0x214a0037
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0xa rt: 0xa i: 0x37
+ r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x37
+ V rs: 0xc rt: 0xc
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000
+ 08: c0007800 09: 00000006 10: 0000000c 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa34a0000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0xa i: 0
+ r rs: 26 rt: 10 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x43
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000
+ 08: c0007800 09: 00000006 10: 00000043 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x43 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2129ffff>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0x9 rt: 0x9 i: 0xffff
+ r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f
+ V rs: 0x6 rt: 0x6
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000
+ 08: c0007800 09: 00000006 10: 00000043 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x1d20fff3>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x7 (bgtz)
+ i rs: 0x9 rt: 0 i: 0xfff3
+ r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33
+ V rs: 0x5 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000
+ 08: c0007800 09: 00000005 10: 00000043 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x84100>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0x8 i: 0x4100
+ r rs: 0 rt: 8 rd: 8 sh: 4 func: 0
+ V rs: 0 rt: 0xc0007800
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000
+ 08: c0007800 09: 00000005 10: 00000043 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+Fmips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c0af000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0xa i: 0xf000
+ r rs: 0 rt: 10 rd: 30 sh: 0 func: 0
+ V rs: 0 rt: 0x43
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000
+ 08: 00078000 09: 00000005 10: 00000043 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x10a5024>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x8 rt: 0xa i: 0x5024
+ r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24
+ V rs: 0x78000 rt: 0xf0000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000
+ 08: 00078000 09: 00000005 10: f0000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa5702>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0xa i: 0x5702
+ r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000
+ 08: 00078000 09: 00000005 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x294b000a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xa (slti)
+ i rs: 0xa rt: 0xb i: 0xa
+ r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000
+ 08: 00078000 09: 00000005 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11600004>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0xb rt: 0 i: 0x4
+ r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4
+ V rs: 0x1 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000
+ 08: 00078000 09: 00000005 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000
+ 08: 00078000 09: 00000005 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x214a0030>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0xa rt: 0xa i: 0x30
+ r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000
+ 08: 00078000 09: 00000005 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0010a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0x10a
+ r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa
+ V rs: 0xbfc00178 rt: 0xdea9
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000
+ 08: 00078000 09: 00000005 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000
+ 08: 00078000 09: 00000005 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa34a0000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0xa i: 0
+ r rs: 26 rt: 10 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000
+ 08: 00078000 09: 00000005 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+Cmips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2129ffff>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0x9 rt: 0x9 i: 0xffff
+ r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f
+ V rs: 0x5 rt: 0x5
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000
+ 08: 00078000 09: 00000005 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x1d20fff3>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x7 (bgtz)
+ i rs: 0x9 rt: 0 i: 0xfff3
+ r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33
+ V rs: 0x4 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000
+ 08: 00078000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x84100>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0x8 i: 0x4100
+ r rs: 0 rt: 8 rd: 8 sh: 4 func: 0
+ V rs: 0 rt: 0x78000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000
+ 08: 00078000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c0af000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0xa i: 0xf000
+ r rs: 0 rt: 10 rd: 30 sh: 0 func: 0
+ V rs: 0 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000
+ 08: 00780000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x10a5024>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x8 rt: 0xa i: 0x5024
+ r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24
+ V rs: 0x780000 rt: 0xf0000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000
+ 08: 00780000 09: 00000004 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa5702>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0xa i: 0x5702
+ r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000
+ 08: 00780000 09: 00000004 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x294b000a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xa (slti)
+ i rs: 0xa rt: 0xb i: 0xa
+ r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa
+ V rs: 0 rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000
+ 08: 00780000 09: 00000004 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11600004>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0xb rt: 0 i: 0x4
+ r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4
+ V rs: 0x1 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000
+ 08: 00780000 09: 00000004 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000
+ 08: 00780000 09: 00000004 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x214a0030>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0xa rt: 0xa i: 0x30
+ r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000
+ 08: 00780000 09: 00000004 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+0mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0010a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0x10a
+ r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa
+ V rs: 0xbfc00178 rt: 0xdea9
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000
+ 08: 00780000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000
+ 08: 00780000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa34a0000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0xa i: 0
+ r rs: 26 rt: 10 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000
+ 08: 00780000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2129ffff>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0x9 rt: 0x9 i: 0xffff
+ r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f
+ V rs: 0x4 rt: 0x4
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000
+ 08: 00780000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x1d20fff3>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x7 (bgtz)
+ i rs: 0x9 rt: 0 i: 0xfff3
+ r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33
+ V rs: 0x3 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000
+ 08: 00780000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x84100>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0x8 i: 0x4100
+ r rs: 0 rt: 8 rd: 8 sh: 4 func: 0
+ V rs: 0 rt: 0x780000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000
+ 08: 00780000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c0af000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0xa i: 0xf000
+ r rs: 0 rt: 10 rd: 30 sh: 0 func: 0
+ V rs: 0 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000
+ 08: 07800000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x10a5024>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x8 rt: 0xa i: 0x5024
+ r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24
+ V rs: 0x7800000 rt: 0xf0000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000
+ 08: 07800000 09: 00000003 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa5702>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0xa i: 0x5702
+ r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000
+ 08: 07800000 09: 00000003 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x294b000a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xa (slti)
+ i rs: 0xa rt: 0xb i: 0xa
+ r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa
+ V rs: 0 rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000
+ 08: 07800000 09: 00000003 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+0mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11600004>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0xb rt: 0 i: 0x4
+ r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4
+ V rs: 0x1 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000
+ 08: 07800000 09: 00000003 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000
+ 08: 07800000 09: 00000003 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x214a0030>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0xa rt: 0xa i: 0x30
+ r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000
+ 08: 07800000 09: 00000003 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0010a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0x10a
+ r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa
+ V rs: 0xbfc00178 rt: 0xdea9
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000
+ 08: 07800000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000
+ 08: 07800000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa34a0000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0xa i: 0
+ r rs: 26 rt: 10 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000
+ 08: 07800000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2129ffff>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0x9 rt: 0x9 i: 0xffff
+ r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f
+ V rs: 0x3 rt: 0x3
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000
+ 08: 07800000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x1d20fff3>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x7 (bgtz)
+ i rs: 0x9 rt: 0 i: 0xfff3
+ r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33
+ V rs: 0x2 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000
+ 08: 07800000 09: 00000002 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x84100>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0x8 i: 0x4100
+ r rs: 0 rt: 8 rd: 8 sh: 4 func: 0
+ V rs: 0 rt: 0x7800000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000
+ 08: 07800000 09: 00000002 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c0af000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0xa i: 0xf000
+ r rs: 0 rt: 10 rd: 30 sh: 0 func: 0
+ V rs: 0 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000
+ 08: 78000000 09: 00000002 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x10a5024>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x8 rt: 0xa i: 0x5024
+ r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24
+ V rs: 0x78000000 rt: 0xf0000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000
+ 08: 78000000 09: 00000002 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa5702>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0xa i: 0x5702
+ r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2
+ V rs: 0 rt: 0x70000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000
+ 08: 78000000 09: 00000002 10: 70000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+0mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x294b000a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xa (slti)
+ i rs: 0xa rt: 0xb i: 0xa
+ r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa
+ V rs: 0x7 rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000
+ 08: 78000000 09: 00000002 10: 00000007 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11600004>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0xb rt: 0 i: 0x4
+ r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4
+ V rs: 0x1 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000
+ 08: 78000000 09: 00000002 10: 00000007 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000
+ 08: 78000000 09: 00000002 10: 00000007 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x214a0030>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0xa rt: 0xa i: 0x30
+ r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30
+ V rs: 0x7 rt: 0x7
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000
+ 08: 78000000 09: 00000002 10: 00000007 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0010a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0x10a
+ r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa
+ V rs: 0xbfc00178 rt: 0xdea9
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000
+ 08: 78000000 09: 00000002 10: 00000037 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000
+ 08: 78000000 09: 00000002 10: 00000037 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa34a0000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0xa i: 0
+ r rs: 26 rt: 10 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x37
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000
+ 08: 78000000 09: 00000002 10: 00000037 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x37 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2129ffff>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0x9 rt: 0x9 i: 0xffff
+ r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f
+ V rs: 0x2 rt: 0x2
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000
+ 08: 78000000 09: 00000002 10: 00000037 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x1d20fff3>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x7 (bgtz)
+ i rs: 0x9 rt: 0 i: 0xfff3
+ r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33
+ V rs: 0x1 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000
+ 08: 78000000 09: 00000001 10: 00000037 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x84100>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0x8 i: 0x4100
+ r rs: 0 rt: 8 rd: 8 sh: 4 func: 0
+ V rs: 0 rt: 0x78000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000
+ 08: 78000000 09: 00000001 10: 00000037 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c0af000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0xa i: 0xf000
+ r rs: 0 rt: 10 rd: 30 sh: 0 func: 0
+ V rs: 0 rt: 0x37
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000
+ 08: 80000000 09: 00000001 10: 00000037 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x10a5024>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x8 rt: 0xa i: 0x5024
+ r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24
+ V rs: 0x80000000 rt: 0xf0000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000
+ 08: 80000000 09: 00000001 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa5702>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0xa i: 0x5702
+ r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2
+ V rs: 0 rt: 0x80000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000
+ 08: 80000000 09: 00000001 10: 80000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+7mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x294b000a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xa (slti)
+ i rs: 0xa rt: 0xb i: 0xa
+ r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa
+ V rs: 0x8 rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000
+ 08: 80000000 09: 00000001 10: 00000008 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11600004>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0xb rt: 0 i: 0x4
+ r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4
+ V rs: 0x1 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000
+ 08: 80000000 09: 00000001 10: 00000008 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000
+ 08: 80000000 09: 00000001 10: 00000008 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x214a0030>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0xa rt: 0xa i: 0x30
+ r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30
+ V rs: 0x8 rt: 0x8
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000
+ 08: 80000000 09: 00000001 10: 00000008 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0010a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0x10a
+ r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa
+ V rs: 0xbfc00178 rt: 0xdea9
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000
+ 08: 80000000 09: 00000001 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000
+ 08: 80000000 09: 00000001 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa34a0000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0xa i: 0
+ r rs: 26 rt: 10 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x38
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000
+ 08: 80000000 09: 00000001 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x38 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2129ffff>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0x9 rt: 0x9 i: 0xffff
+ r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f
+ V rs: 0x1 rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000
+ 08: 80000000 09: 00000001 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x1d20fff3>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x7 (bgtz)
+ i rs: 0x9 rt: 0 i: 0xfff3
+ r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000
+ 08: 80000000 09: 00000000 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00438 m_ifetch_addr: 0xbfc00434
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x84100>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00434 NPC: 0xbfc00438 Ins: 0x84100
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0x8 i: 0x4100
+ r rs: 0 rt: 8 rd: 8 sh: 4 func: 0
+ V rs: 0 rt: 0x80000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000
+ 08: 80000000 09: 00000000 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00438 m_jump_pc: 0xbfc0043c m_ifetch_addr: 0xbfc00438
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3e00008>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00438 NPC: 0xbfc0043c Ins: 0x3e00008
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x1f rt: 0 i: 0x8
+ r rs: 31 rt: 0 rd: 0 sh: 0 func: 0x8
+ V rs: 0xbfc00178 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc0043c m_jump_pc: 0xbfc00178 m_ifetch_addr: 0xbfc0043c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0043c NPC: 0xbfc00178 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00178 m_jump_pc: 0xbfc0017c m_ifetch_addr: 0xbfc00178
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c04bfc0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00178 NPC: 0xbfc0017c Ins: 0x3c04bfc0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0x4 i: 0xbfc0
+ r rs: 0 rt: 4 rd: 23 sh: 31 func: 0
+ V rs: 0 rt: 0xbfc00078
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00078 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc0017c m_jump_pc: 0xbfc00180 m_ifetch_addr: 0xbfc0017c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+8mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2484022c>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0017c NPC: 0xbfc00180 Ins: 0x2484022c
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0x4 rt: 0x4 i: 0x22c
+ r rs: 4 rt: 4 rd: 0 sh: 8 func: 0x2c
+ V rs: 0xbfc00000 rt: 0xbfc00000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00180 m_jump_pc: 0xbfc00184 m_ifetch_addr: 0xbfc00180
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xff000f0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00180 NPC: 0xbfc00184 Ins: 0xff000f0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x3 (jal)
+ i rs: 0x1f rt: 0x10 i: 0xf0
+ r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x30
+ V rs: 0xbfc00178 rt: 0xdea9
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00184 m_jump_pc: 0xbfc003c0 m_ifetch_addr: 0xbfc00184
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00184 NPC: 0xbfc003c0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 m_next_pc: 0xbfc003c0 m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003c0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x804021>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c0 NPC: 0xbfc003c4 Ins: 0x804021
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x4 rt: 0 i: 0x4021
+ r rs: 4 rt: 0 rd: 8 sh: 0 func: 0x21
+ V rs: 0xbfc0022c rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x81090000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x20 (lb)
+ i rs: 0x8 rt: 0x9 i: 0
+ r rs: 8 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xbfc0022c rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0022c 09: 00000000 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_READ @ 0xbfc0022c wdata 0 be 0x1> off: 0 sign_ext: 0x1 dest: gp+0x9
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp valid no error rdata 0x75616320>, 0)
+mips0 setData: <DataRsp valid no error rdata 0x75616320> off: 0 sign_ext: 0x1 dest: r_gp+0x9
+mips0 setData: <DataRsp valid no error rdata 0x75616320> off: 0 count: 0x1 le: 0 old: 0 from_mem: 0x75616320 mask: 0xffffffff new_data: 0x20
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0x9 rt: 0 i: 0x5
+ r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5
+ V rs: 0x20 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0022c 09: 00000020 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0022c 09: 00000020 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa3490000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0x9 i: 0
+ r rs: 26 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x20
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0022c 09: 00000020 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x20 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0x8 rt: 0x8 i: 0x1
+ r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1
+ V rs: 0xbfc0022c rt: 0xbfc0022c
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0022c 09: 00000020 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf000f1>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0xf1
+ r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31
+ V rs: 0xbfc00188 rt: 0xdea9
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0022d 09: 00000020 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0022d 09: 00000020 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x81090000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x20 (lb)
+ i rs: 0x8 rt: 0x9 i: 0
+ r rs: 8 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xbfc0022d rt: 0x20
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0022d 09: 00000020 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_READ @ 0xbfc0022c wdata 0 be 0x2> off: 0x1 sign_ext: 0x1 dest: gp+0x9
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp valid no error rdata 0x75616320>, 0)
+mips0 setData: <DataRsp valid no error rdata 0x75616320> off: 0 sign_ext: 0x1 dest: r_gp+0x9
+mips0 setData: <DataRsp valid no error rdata 0x75616320> off: 0 count: 0x1 le: 0x1 old: 0x20 from_mem: 0x75616320 mask: 0xffffffff new_data: 0x63
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1
+ mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0x9 rt: 0 i: 0x5
+ r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5
+ V rs: 0x63 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0022d 09: 00000063 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0022d 09: 00000063 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa3490000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0x9 i: 0
+ r rs: 26 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x63
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0022d 09: 00000063 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x63 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0x8 rt: 0x8 i: 0x1
+ r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1
+ V rs: 0xbfc0022d rt: 0xbfc0022d
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0022d 09: 00000063 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf000f1>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0xf1
+ r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31
+ V rs: 0xbfc00188 rt: 0xdea9
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0022e 09: 00000063 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0022e 09: 00000063 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x81090000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x20 (lb)
+ i rs: 0x8 rt: 0x9 i: 0
+ r rs: 8 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xbfc0022e rt: 0x63
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0022e 09: 00000063 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_READ @ 0xbfc0022c wdata 0 be 0x4> off: 0x2 sign_ext: 0x1 dest: gp+0x9
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp valid no error rdata 0x75616320>, 0)
+mips0 setData: <DataRsp valid no error rdata 0x75616320> off: 0 sign_ext: 0x1 dest: r_gp+0x9
+mips0 setData: <DataRsp valid no error rdata 0x75616320> off: 0 count: 0x1 le: 0x2 old: 0x63 from_mem: 0x75616320 mask: 0xffffffff new_data: 0x61
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0x9 rt: 0 i: 0x5
+ r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5
+ V rs: 0x61 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0022e 09: 00000061 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+cmips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0022e 09: 00000061 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa3490000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0x9 i: 0
+ r rs: 26 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x61
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0022e 09: 00000061 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x61 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0x8 rt: 0x8 i: 0x1
+ r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1
+ V rs: 0xbfc0022e rt: 0xbfc0022e
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0022e 09: 00000061 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf000f1>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0xf1
+ r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31
+ V rs: 0xbfc00188 rt: 0xdea9
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0022f 09: 00000061 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0022f 09: 00000061 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x81090000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x20 (lb)
+ i rs: 0x8 rt: 0x9 i: 0
+ r rs: 8 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xbfc0022f rt: 0x61
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0022f 09: 00000061 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_READ @ 0xbfc0022c wdata 0 be 0x8> off: 0x3 sign_ext: 0x1 dest: gp+0x9
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp valid no error rdata 0x75616320>, 0)
+mips0 setData: <DataRsp valid no error rdata 0x75616320> off: 0 sign_ext: 0x1 dest: r_gp+0x9
+mips0 setData: <DataRsp valid no error rdata 0x75616320> off: 0 count: 0x1 le: 0x3 old: 0x61 from_mem: 0x75616320 mask: 0xffffffff new_data: 0x75
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0x9 rt: 0 i: 0x5
+ r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5
+ V rs: 0x75 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0022f 09: 00000075 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0022f 09: 00000075 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+amips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa3490000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0x9 i: 0
+ r rs: 26 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x75
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0022f 09: 00000075 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x75 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0x8 rt: 0x8 i: 0x1
+ r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1
+ V rs: 0xbfc0022f rt: 0xbfc0022f
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0022f 09: 00000075 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf000f1>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0xf1
+ r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31
+ V rs: 0xbfc00188 rt: 0xdea9
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00230 09: 00000075 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00230 09: 00000075 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x81090000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x20 (lb)
+ i rs: 0x8 rt: 0x9 i: 0
+ r rs: 8 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xbfc00230 rt: 0x75
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00230 09: 00000075 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_READ @ 0xbfc00230 wdata 0 be 0x1> off: 0 sign_ext: 0x1 dest: gp+0x9
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp valid no error rdata 0x206573>, 0)
+mips0 setData: <DataRsp valid no error rdata 0x206573> off: 0 sign_ext: 0x1 dest: r_gp+0x9
+mips0 setData: <DataRsp valid no error rdata 0x206573> off: 0 count: 0x1 le: 0 old: 0x75 from_mem: 0x206573 mask: 0xffffffff new_data: 0x73
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0x9 rt: 0 i: 0x5
+ r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5
+ V rs: 0x73 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00230 09: 00000073 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00230 09: 00000073 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa3490000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0x9 i: 0
+ r rs: 26 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x73
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00230 09: 00000073 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x73 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+umips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0x8 rt: 0x8 i: 0x1
+ r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1
+ V rs: 0xbfc00230 rt: 0xbfc00230
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00230 09: 00000073 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf000f1>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0xf1
+ r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31
+ V rs: 0xbfc00188 rt: 0xdea9
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00231 09: 00000073 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00231 09: 00000073 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x81090000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x20 (lb)
+ i rs: 0x8 rt: 0x9 i: 0
+ r rs: 8 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xbfc00231 rt: 0x73
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00231 09: 00000073 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_READ @ 0xbfc00230 wdata 0 be 0x2> off: 0x1 sign_ext: 0x1 dest: gp+0x9
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp valid no error rdata 0x206573>, 0)
+mips0 setData: <DataRsp valid no error rdata 0x206573> off: 0 sign_ext: 0x1 dest: r_gp+0x9
+mips0 setData: <DataRsp valid no error rdata 0x206573> off: 0 count: 0x1 le: 0x1 old: 0x73 from_mem: 0x206573 mask: 0xffffffff new_data: 0x65
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0x9 rt: 0 i: 0x5
+ r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5
+ V rs: 0x65 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00231 09: 00000065 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00231 09: 00000065 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa3490000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0x9 i: 0
+ r rs: 26 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x65
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00231 09: 00000065 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x65 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+smips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0x8 rt: 0x8 i: 0x1
+ r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1
+ V rs: 0xbfc00231 rt: 0xbfc00231
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00231 09: 00000065 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf000f1>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0xf1
+ r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31
+ V rs: 0xbfc00188 rt: 0xdea9
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00232 09: 00000065 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00232 09: 00000065 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x81090000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x20 (lb)
+ i rs: 0x8 rt: 0x9 i: 0
+ r rs: 8 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xbfc00232 rt: 0x65
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00232 09: 00000065 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_READ @ 0xbfc00230 wdata 0 be 0x4> off: 0x2 sign_ext: 0x1 dest: gp+0x9
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp valid no error rdata 0x206573>, 0)
+mips0 setData: <DataRsp valid no error rdata 0x206573> off: 0 sign_ext: 0x1 dest: r_gp+0x9
+mips0 setData: <DataRsp valid no error rdata 0x206573> off: 0 count: 0x1 le: 0x2 old: 0x65 from_mem: 0x206573 mask: 0xffffffff new_data: 0x20
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0x9 rt: 0 i: 0x5
+ r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5
+ V rs: 0x20 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00232 09: 00000020 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00232 09: 00000020 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa3490000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0x9 i: 0
+ r rs: 26 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x20
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00232 09: 00000020 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x20 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+emips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0x8 rt: 0x8 i: 0x1
+ r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1
+ V rs: 0xbfc00232 rt: 0xbfc00232
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00232 09: 00000020 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf000f1>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0xf1
+ r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31
+ V rs: 0xbfc00188 rt: 0xdea9
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00233 09: 00000020 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00233 09: 00000020 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x81090000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x20 (lb)
+ i rs: 0x8 rt: 0x9 i: 0
+ r rs: 8 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xbfc00233 rt: 0x20
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00233 09: 00000020 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_READ @ 0xbfc00230 wdata 0 be 0x8> off: 0x3 sign_ext: 0x1 dest: gp+0x9
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp valid no error rdata 0x206573>, 0)
+mips0 setData: <DataRsp valid no error rdata 0x206573> off: 0 sign_ext: 0x1 dest: r_gp+0x9
+mips0 setData: <DataRsp valid no error rdata 0x206573> off: 0 count: 0x1 le: 0x3 old: 0x20 from_mem: 0x206573 mask: 0xffffffff new_data: 0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0x9 rt: 0 i: 0x5
+ r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00233 09: 00000000 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003e0 m_ifetch_addr: 0xbfc003cc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003cc NPC: 0xbfc003e0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00233 09: 00000000 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 m_next_pc: 0xbfc003e0 m_jump_pc: 0xbfc003e4 m_ifetch_addr: 0xbfc003e0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3e00008>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003e0 NPC: 0xbfc003e4 Ins: 0x3e00008
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x1f rt: 0 i: 0x8
+ r rs: 31 rt: 0 rd: 0 sh: 0 func: 0x8
+ V rs: 0xbfc00188 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00233 09: 00000000 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 m_next_pc: 0xbfc003e4 m_jump_pc: 0xbfc00188 m_ifetch_addr: 0xbfc003e4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+ mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003e4 NPC: 0xbfc00188 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00233 09: 00000000 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 m_next_pc: 0xbfc00188 m_jump_pc: 0xbfc0018c m_ifetch_addr: 0xbfc00188
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x40046800>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00188 NPC: 0xbfc0018c Ins: 0x40046800
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x10 (cop0)
+ i rs: 0 rt: 0x4 i: 0x6800
+ r rs: 0 rt: 4 rd: 13 sh: 0 func: 0
+ V rs: 0 rt: 0xbfc0022c
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00233 09: 00000000 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 m_next_pc: 0xbfc0018c m_jump_pc: 0xbfc00190 m_ifetch_addr: 0xbfc0018c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xff000fa>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0018c NPC: 0xbfc00190 Ins: 0xff000fa
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x3 (jal)
+ i rs: 0x1f rt: 0x10 i: 0xfa
+ r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x3a
+ V rs: 0xbfc00188 rt: 0xdea9
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00233 09: 00000000 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 m_next_pc: 0xbfc00190 m_jump_pc: 0xbfc003e8 m_ifetch_addr: 0xbfc00190
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00190 NPC: 0xbfc003e8 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00233 09: 00000000 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc003e8 m_jump_pc: 0xbfc003ec m_ifetch_addr: 0xbfc003e8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x804021>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003e8 NPC: 0xbfc003ec Ins: 0x804021
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x4 rt: 0 i: 0x4021
+ r rs: 4 rt: 0 rd: 8 sh: 0 func: 0x21
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00233 09: 00000000 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc003ec m_jump_pc: 0xbfc003f0 m_ifetch_addr: 0xbfc003ec
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x24090030>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003ec NPC: 0xbfc003f0 Ins: 0x24090030
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0 rt: 0x9 i: 0x30
+ r rs: 0 rt: 9 rd: 0 sh: 0 func: 0x30
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc003f0 m_jump_pc: 0xbfc003f4 m_ifetch_addr: 0xbfc003f0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa3490000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003f0 NPC: 0xbfc003f4 Ins: 0xa3490000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0x9 i: 0
+ r rs: 26 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000030 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc003f4 m_jump_pc: 0xbfc003f8 m_ifetch_addr: 0xbfc003f4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x24090078>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc003f4 NPC: 0xbfc003f8 Ins: 0x24090078
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0 rt: 0x9 i: 0x78
+ r rs: 0 rt: 9 rd: 0 sh: 1 func: 0x38
+ V rs: 0 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000030 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc003f8 m_jump_pc: 0xbfc003fc m_ifetch_addr: 0xbfc003f8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa3490000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003f8 NPC: 0xbfc003fc Ins: 0xa3490000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0x9 i: 0
+ r rs: 26 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x78
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000078 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x78 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc003fc m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc003fc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x24090008>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc003fc NPC: 0xbfc00400 Ins: 0x24090008
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0 rt: 0x9 i: 0x8
+ r rs: 0 rt: 9 rd: 0 sh: 0 func: 0x8
+ V rs: 0 rt: 0x78
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000078 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c0af000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0xa i: 0xf000
+ r rs: 0 rt: 10 rd: 30 sh: 0 func: 0
+ V rs: 0 rt: 0x38
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000008 10: 00000038 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x10a5024>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x8 rt: 0xa i: 0x5024
+ r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24
+ V rs: 0 rt: 0xf0000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000008 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa5702>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0xa i: 0x5702
+ r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000008 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+0mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x294b000a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xa (slti)
+ i rs: 0xa rt: 0xb i: 0xa
+ r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa
+ V rs: 0 rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000008 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11600004>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0xb rt: 0 i: 0x4
+ r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4
+ V rs: 0x1 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000008 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000008 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x214a0030>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0xa rt: 0xa i: 0x30
+ r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000008 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0010a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0x10a
+ r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa
+ V rs: 0xbfc00194 rt: 0xdea9
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000008 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000008 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa34a0000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0xa i: 0
+ r rs: 26 rt: 10 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000008 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2129ffff>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0x9 rt: 0x9 i: 0xffff
+ r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f
+ V rs: 0x8 rt: 0x8
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000008 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x1d20fff3>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x7 (bgtz)
+ i rs: 0x9 rt: 0 i: 0xfff3
+ r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33
+ V rs: 0x7 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000007 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x84100>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0x8 i: 0x4100
+ r rs: 0 rt: 8 rd: 8 sh: 4 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000007 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+xmips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c0af000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0xa i: 0xf000
+ r rs: 0 rt: 10 rd: 30 sh: 0 func: 0
+ V rs: 0 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000007 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x10a5024>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x8 rt: 0xa i: 0x5024
+ r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24
+ V rs: 0 rt: 0xf0000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000007 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa5702>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0xa i: 0x5702
+ r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000007 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x294b000a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xa (slti)
+ i rs: 0xa rt: 0xb i: 0xa
+ r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa
+ V rs: 0 rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000007 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11600004>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0xb rt: 0 i: 0x4
+ r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4
+ V rs: 0x1 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000007 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000007 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x214a0030>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0xa rt: 0xa i: 0x30
+ r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000007 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0010a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0x10a
+ r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa
+ V rs: 0xbfc00194 rt: 0xdea9
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000007 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000007 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa34a0000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0xa i: 0
+ r rs: 26 rt: 10 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000007 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+0mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2129ffff>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0x9 rt: 0x9 i: 0xffff
+ r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f
+ V rs: 0x7 rt: 0x7
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000007 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x1d20fff3>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x7 (bgtz)
+ i rs: 0x9 rt: 0 i: 0xfff3
+ r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33
+ V rs: 0x6 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000006 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x84100>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0x8 i: 0x4100
+ r rs: 0 rt: 8 rd: 8 sh: 4 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000006 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c0af000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0xa i: 0xf000
+ r rs: 0 rt: 10 rd: 30 sh: 0 func: 0
+ V rs: 0 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000006 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x10a5024>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x8 rt: 0xa i: 0x5024
+ r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24
+ V rs: 0 rt: 0xf0000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000006 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa5702>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0xa i: 0x5702
+ r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000006 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x294b000a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xa (slti)
+ i rs: 0xa rt: 0xb i: 0xa
+ r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa
+ V rs: 0 rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000006 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11600004>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0xb rt: 0 i: 0x4
+ r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4
+ V rs: 0x1 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000006 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000006 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x214a0030>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0xa rt: 0xa i: 0x30
+ r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000006 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+0mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0010a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0x10a
+ r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa
+ V rs: 0xbfc00194 rt: 0xdea9
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000006 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000006 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa34a0000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0xa i: 0
+ r rs: 26 rt: 10 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000006 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2129ffff>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0x9 rt: 0x9 i: 0xffff
+ r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f
+ V rs: 0x6 rt: 0x6
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000006 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x1d20fff3>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x7 (bgtz)
+ i rs: 0x9 rt: 0 i: 0xfff3
+ r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33
+ V rs: 0x5 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000005 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x84100>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0x8 i: 0x4100
+ r rs: 0 rt: 8 rd: 8 sh: 4 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000005 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c0af000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0xa i: 0xf000
+ r rs: 0 rt: 10 rd: 30 sh: 0 func: 0
+ V rs: 0 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000005 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x10a5024>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x8 rt: 0xa i: 0x5024
+ r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24
+ V rs: 0 rt: 0xf0000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000005 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa5702>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0xa i: 0x5702
+ r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000005 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x294b000a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xa (slti)
+ i rs: 0xa rt: 0xb i: 0xa
+ r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa
+ V rs: 0 rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000005 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+0mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11600004>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0xb rt: 0 i: 0x4
+ r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4
+ V rs: 0x1 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000005 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000005 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x214a0030>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0xa rt: 0xa i: 0x30
+ r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000005 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0010a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0x10a
+ r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa
+ V rs: 0xbfc00194 rt: 0xdea9
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000005 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000005 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa34a0000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0xa i: 0
+ r rs: 26 rt: 10 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000005 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2129ffff>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0x9 rt: 0x9 i: 0xffff
+ r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f
+ V rs: 0x5 rt: 0x5
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000005 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x1d20fff3>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x7 (bgtz)
+ i rs: 0x9 rt: 0 i: 0xfff3
+ r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33
+ V rs: 0x4 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x84100>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0x8 i: 0x4100
+ r rs: 0 rt: 8 rd: 8 sh: 4 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c0af000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0xa i: 0xf000
+ r rs: 0 rt: 10 rd: 30 sh: 0 func: 0
+ V rs: 0 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x10a5024>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x8 rt: 0xa i: 0x5024
+ r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24
+ V rs: 0 rt: 0xf0000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000004 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa5702>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0xa i: 0x5702
+ r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000004 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+0mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x294b000a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xa (slti)
+ i rs: 0xa rt: 0xb i: 0xa
+ r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa
+ V rs: 0 rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000004 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11600004>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0xb rt: 0 i: 0x4
+ r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4
+ V rs: 0x1 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000004 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000004 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x214a0030>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0xa rt: 0xa i: 0x30
+ r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000004 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0010a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0x10a
+ r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa
+ V rs: 0xbfc00194 rt: 0xdea9
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa34a0000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0xa i: 0
+ r rs: 26 rt: 10 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2129ffff>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0x9 rt: 0x9 i: 0xffff
+ r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f
+ V rs: 0x4 rt: 0x4
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x1d20fff3>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x7 (bgtz)
+ i rs: 0x9 rt: 0 i: 0xfff3
+ r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33
+ V rs: 0x3 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x84100>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0x8 i: 0x4100
+ r rs: 0 rt: 8 rd: 8 sh: 4 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c0af000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0xa i: 0xf000
+ r rs: 0 rt: 10 rd: 30 sh: 0 func: 0
+ V rs: 0 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x10a5024>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x8 rt: 0xa i: 0x5024
+ r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24
+ V rs: 0 rt: 0xf0000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000003 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa5702>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0xa i: 0x5702
+ r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000003 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+0mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x294b000a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xa (slti)
+ i rs: 0xa rt: 0xb i: 0xa
+ r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa
+ V rs: 0 rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000003 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11600004>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0xb rt: 0 i: 0x4
+ r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4
+ V rs: 0x1 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000003 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000003 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x214a0030>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0xa rt: 0xa i: 0x30
+ r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000003 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0010a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0x10a
+ r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa
+ V rs: 0xbfc00194 rt: 0xdea9
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa34a0000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0xa i: 0
+ r rs: 26 rt: 10 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2129ffff>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0x9 rt: 0x9 i: 0xffff
+ r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f
+ V rs: 0x3 rt: 0x3
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x1d20fff3>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x7 (bgtz)
+ i rs: 0x9 rt: 0 i: 0xfff3
+ r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33
+ V rs: 0x2 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000002 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x84100>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0x8 i: 0x4100
+ r rs: 0 rt: 8 rd: 8 sh: 4 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000002 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c0af000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0xa i: 0xf000
+ r rs: 0 rt: 10 rd: 30 sh: 0 func: 0
+ V rs: 0 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000002 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x10a5024>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x8 rt: 0xa i: 0x5024
+ r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24
+ V rs: 0 rt: 0xf0000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000002 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa5702>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0xa i: 0x5702
+ r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000002 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+0mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x294b000a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xa (slti)
+ i rs: 0xa rt: 0xb i: 0xa
+ r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa
+ V rs: 0 rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000002 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11600004>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0xb rt: 0 i: 0x4
+ r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4
+ V rs: 0x1 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000002 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000002 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x214a0030>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0xa rt: 0xa i: 0x30
+ r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000002 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0010a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0x10a
+ r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa
+ V rs: 0xbfc00194 rt: 0xdea9
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000002 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000002 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa34a0000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0xa i: 0
+ r rs: 26 rt: 10 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000002 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2129ffff>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0x9 rt: 0x9 i: 0xffff
+ r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f
+ V rs: 0x2 rt: 0x2
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000002 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x1d20fff3>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x7 (bgtz)
+ i rs: 0x9 rt: 0 i: 0xfff3
+ r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33
+ V rs: 0x1 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000001 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x84100>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0x8 i: 0x4100
+ r rs: 0 rt: 8 rd: 8 sh: 4 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000001 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c0af000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0xa i: 0xf000
+ r rs: 0 rt: 10 rd: 30 sh: 0 func: 0
+ V rs: 0 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000001 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x10a5024>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x8 rt: 0xa i: 0x5024
+ r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24
+ V rs: 0 rt: 0xf0000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000001 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa5702>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0xa i: 0x5702
+ r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000001 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+0mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x294b000a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xa (slti)
+ i rs: 0xa rt: 0xb i: 0xa
+ r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa
+ V rs: 0 rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000001 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11600004>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0xb rt: 0 i: 0x4
+ r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4
+ V rs: 0x1 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000001 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000001 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x214a0030>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0xa rt: 0xa i: 0x30
+ r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000001 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0010a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0x10a
+ r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa
+ V rs: 0xbfc00194 rt: 0xdea9
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000001 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000001 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa34a0000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0xa i: 0
+ r rs: 26 rt: 10 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000001 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2129ffff>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0x9 rt: 0x9 i: 0xffff
+ r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f
+ V rs: 0x1 rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000001 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x1d20fff3>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x7 (bgtz)
+ i rs: 0x9 rt: 0 i: 0xfff3
+ r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00438 m_ifetch_addr: 0xbfc00434
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x84100>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00434 NPC: 0xbfc00438 Ins: 0x84100
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0x8 i: 0x4100
+ r rs: 0 rt: 8 rd: 8 sh: 4 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00438 m_jump_pc: 0xbfc0043c m_ifetch_addr: 0xbfc00438
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3e00008>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00438 NPC: 0xbfc0043c Ins: 0x3e00008
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x1f rt: 0 i: 0x8
+ r rs: 31 rt: 0 rd: 0 sh: 0 func: 0x8
+ V rs: 0xbfc00194 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc0043c m_jump_pc: 0xbfc00194 m_ifetch_addr: 0xbfc0043c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0043c NPC: 0xbfc00194 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00194 m_jump_pc: 0xbfc00198 m_ifetch_addr: 0xbfc00194
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c04bfc0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00194 NPC: 0xbfc00198 Ins: 0x3c04bfc0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0x4 i: 0xbfc0
+ r rs: 0 rt: 4 rd: 23 sh: 31 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00198 m_jump_pc: 0xbfc0019c m_ifetch_addr: 0xbfc00198
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+0mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x24840239>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00198 NPC: 0xbfc0019c Ins: 0x24840239
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0x4 rt: 0x4 i: 0x239
+ r rs: 4 rt: 4 rd: 0 sh: 8 func: 0x39
+ V rs: 0xbfc00000 rt: 0xbfc00000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc0019c m_jump_pc: 0xbfc001a0 m_ifetch_addr: 0xbfc0019c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xff000f0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0019c NPC: 0xbfc001a0 Ins: 0xff000f0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x3 (jal)
+ i rs: 0x1f rt: 0x10 i: 0xf0
+ r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x30
+ V rs: 0xbfc00194 rt: 0xdea9
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc001a0 m_jump_pc: 0xbfc003c0 m_ifetch_addr: 0xbfc001a0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc001a0 NPC: 0xbfc003c0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 m_next_pc: 0xbfc003c0 m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003c0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x804021>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c0 NPC: 0xbfc003c4 Ins: 0x804021
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x4 rt: 0 i: 0x4021
+ r rs: 4 rt: 0 rd: 8 sh: 0 func: 0x21
+ V rs: 0xbfc00239 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x81090000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x20 (lb)
+ i rs: 0x8 rt: 0x9 i: 0
+ r rs: 8 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xbfc00239 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00239 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_READ @ 0xbfc00238 wdata 0 be 0x2> off: 0x1 sign_ext: 0x1 dest: gp+0x9
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp valid no error rdata 0x61622000>, 0)
+mips0 setData: <DataRsp valid no error rdata 0x61622000> off: 0 sign_ext: 0x1 dest: r_gp+0x9
+mips0 setData: <DataRsp valid no error rdata 0x61622000> off: 0 count: 0x1 le: 0x1 old: 0 from_mem: 0x61622000 mask: 0xffffffff new_data: 0x20
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0x9 rt: 0 i: 0x5
+ r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5
+ V rs: 0x20 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00239 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00239 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa3490000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0x9 i: 0
+ r rs: 26 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x20
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00239 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x20 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0x8 rt: 0x8 i: 0x1
+ r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1
+ V rs: 0xbfc00239 rt: 0xbfc00239
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00239 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf000f1>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0xf1
+ r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31
+ V rs: 0xbfc001a4 rt: 0xdea9
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0023a 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0023a 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x81090000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x20 (lb)
+ i rs: 0x8 rt: 0x9 i: 0
+ r rs: 8 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xbfc0023a rt: 0x20
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0023a 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_READ @ 0xbfc00238 wdata 0 be 0x4> off: 0x2 sign_ext: 0x1 dest: gp+0x9
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp valid no error rdata 0x61622000>, 0)
+mips0 setData: <DataRsp valid no error rdata 0x61622000> off: 0 sign_ext: 0x1 dest: r_gp+0x9
+mips0 setData: <DataRsp valid no error rdata 0x61622000> off: 0 count: 0x1 le: 0x2 old: 0x20 from_mem: 0x61622000 mask: 0xffffffff new_data: 0x62
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1
+ mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0x9 rt: 0 i: 0x5
+ r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5
+ V rs: 0x62 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0023a 09: 00000062 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0023a 09: 00000062 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa3490000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0x9 i: 0
+ r rs: 26 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x62
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0023a 09: 00000062 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x62 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0x8 rt: 0x8 i: 0x1
+ r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1
+ V rs: 0xbfc0023a rt: 0xbfc0023a
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0023a 09: 00000062 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf000f1>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0xf1
+ r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31
+ V rs: 0xbfc001a4 rt: 0xdea9
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0023b 09: 00000062 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0023b 09: 00000062 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x81090000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x20 (lb)
+ i rs: 0x8 rt: 0x9 i: 0
+ r rs: 8 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xbfc0023b rt: 0x62
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0023b 09: 00000062 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_READ @ 0xbfc00238 wdata 0 be 0x8> off: 0x3 sign_ext: 0x1 dest: gp+0x9
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp valid no error rdata 0x61622000>, 0)
+mips0 setData: <DataRsp valid no error rdata 0x61622000> off: 0 sign_ext: 0x1 dest: r_gp+0x9
+mips0 setData: <DataRsp valid no error rdata 0x61622000> off: 0 count: 0x1 le: 0x3 old: 0x62 from_mem: 0x61622000 mask: 0xffffffff new_data: 0x61
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0x9 rt: 0 i: 0x5
+ r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5
+ V rs: 0x61 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0023b 09: 00000061 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+bmips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0023b 09: 00000061 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa3490000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0x9 i: 0
+ r rs: 26 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x61
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0023b 09: 00000061 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x61 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0x8 rt: 0x8 i: 0x1
+ r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1
+ V rs: 0xbfc0023b rt: 0xbfc0023b
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0023b 09: 00000061 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf000f1>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0xf1
+ r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31
+ V rs: 0xbfc001a4 rt: 0xdea9
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0023c 09: 00000061 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0023c 09: 00000061 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x81090000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x20 (lb)
+ i rs: 0x8 rt: 0x9 i: 0
+ r rs: 8 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xbfc0023c rt: 0x61
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0023c 09: 00000061 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_READ @ 0xbfc0023c wdata 0 be 0x1> off: 0 sign_ext: 0x1 dest: gp+0x9
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp valid no error rdata 0x20617664>, 0)
+mips0 setData: <DataRsp valid no error rdata 0x20617664> off: 0 sign_ext: 0x1 dest: r_gp+0x9
+mips0 setData: <DataRsp valid no error rdata 0x20617664> off: 0 count: 0x1 le: 0 old: 0x61 from_mem: 0x20617664 mask: 0xffffffff new_data: 0x64
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0x9 rt: 0 i: 0x5
+ r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5
+ V rs: 0x64 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0023c 09: 00000064 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0023c 09: 00000064 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+amips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa3490000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0x9 i: 0
+ r rs: 26 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x64
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0023c 09: 00000064 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x64 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0x8 rt: 0x8 i: 0x1
+ r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1
+ V rs: 0xbfc0023c rt: 0xbfc0023c
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0023c 09: 00000064 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf000f1>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0xf1
+ r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31
+ V rs: 0xbfc001a4 rt: 0xdea9
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0023d 09: 00000064 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0023d 09: 00000064 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x81090000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x20 (lb)
+ i rs: 0x8 rt: 0x9 i: 0
+ r rs: 8 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xbfc0023d rt: 0x64
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0023d 09: 00000064 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_READ @ 0xbfc0023c wdata 0 be 0x2> off: 0x1 sign_ext: 0x1 dest: gp+0x9
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp valid no error rdata 0x20617664>, 0)
+mips0 setData: <DataRsp valid no error rdata 0x20617664> off: 0 sign_ext: 0x1 dest: r_gp+0x9
+mips0 setData: <DataRsp valid no error rdata 0x20617664> off: 0 count: 0x1 le: 0x1 old: 0x64 from_mem: 0x20617664 mask: 0xffffffff new_data: 0x76
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0x9 rt: 0 i: 0x5
+ r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5
+ V rs: 0x76 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0023d 09: 00000076 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0023d 09: 00000076 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa3490000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0x9 i: 0
+ r rs: 26 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x76
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0023d 09: 00000076 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x76 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+dmips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0x8 rt: 0x8 i: 0x1
+ r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1
+ V rs: 0xbfc0023d rt: 0xbfc0023d
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0023d 09: 00000076 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf000f1>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0xf1
+ r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31
+ V rs: 0xbfc001a4 rt: 0xdea9
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0023e 09: 00000076 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0023e 09: 00000076 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x81090000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x20 (lb)
+ i rs: 0x8 rt: 0x9 i: 0
+ r rs: 8 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xbfc0023e rt: 0x76
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0023e 09: 00000076 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_READ @ 0xbfc0023c wdata 0 be 0x4> off: 0x2 sign_ext: 0x1 dest: gp+0x9
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp valid no error rdata 0x20617664>, 0)
+mips0 setData: <DataRsp valid no error rdata 0x20617664> off: 0 sign_ext: 0x1 dest: r_gp+0x9
+mips0 setData: <DataRsp valid no error rdata 0x20617664> off: 0 count: 0x1 le: 0x2 old: 0x76 from_mem: 0x20617664 mask: 0xffffffff new_data: 0x61
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0x9 rt: 0 i: 0x5
+ r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5
+ V rs: 0x61 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0023e 09: 00000061 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0023e 09: 00000061 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa3490000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0x9 i: 0
+ r rs: 26 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x61
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0023e 09: 00000061 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x61 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+vmips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0x8 rt: 0x8 i: 0x1
+ r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1
+ V rs: 0xbfc0023e rt: 0xbfc0023e
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0023e 09: 00000061 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf000f1>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0xf1
+ r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31
+ V rs: 0xbfc001a4 rt: 0xdea9
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0023f 09: 00000061 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0023f 09: 00000061 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x81090000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x20 (lb)
+ i rs: 0x8 rt: 0x9 i: 0
+ r rs: 8 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xbfc0023f rt: 0x61
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0023f 09: 00000061 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_READ @ 0xbfc0023c wdata 0 be 0x8> off: 0x3 sign_ext: 0x1 dest: gp+0x9
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp valid no error rdata 0x20617664>, 0)
+mips0 setData: <DataRsp valid no error rdata 0x20617664> off: 0 sign_ext: 0x1 dest: r_gp+0x9
+mips0 setData: <DataRsp valid no error rdata 0x20617664> off: 0 count: 0x1 le: 0x3 old: 0x61 from_mem: 0x20617664 mask: 0xffffffff new_data: 0x20
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0x9 rt: 0 i: 0x5
+ r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5
+ V rs: 0x20 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0023f 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0023f 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa3490000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0x9 i: 0
+ r rs: 26 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x20
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0023f 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x20 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+amips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0x8 rt: 0x8 i: 0x1
+ r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1
+ V rs: 0xbfc0023f rt: 0xbfc0023f
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0023f 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf000f1>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0xf1
+ r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31
+ V rs: 0xbfc001a4 rt: 0xdea9
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00240 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00240 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x81090000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x20 (lb)
+ i rs: 0x8 rt: 0x9 i: 0
+ r rs: 8 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xbfc00240 rt: 0x20
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00240 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_READ @ 0xbfc00240 wdata 0 be 0x1> off: 0 sign_ext: 0x1 dest: gp+0x9
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp valid no error rdata 0x69782000>, 0)
+mips0 setData: <DataRsp valid no error rdata 0x69782000> off: 0 sign_ext: 0x1 dest: r_gp+0x9
+mips0 setData: <DataRsp valid no error rdata 0x69782000> off: 0 count: 0x1 le: 0 old: 0x20 from_mem: 0x69782000 mask: 0xffffffff new_data: 0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0x9 rt: 0 i: 0x5
+ r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00240 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003e0 m_ifetch_addr: 0xbfc003cc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003cc NPC: 0xbfc003e0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00240 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 m_next_pc: 0xbfc003e0 m_jump_pc: 0xbfc003e4 m_ifetch_addr: 0xbfc003e0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3e00008>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003e0 NPC: 0xbfc003e4 Ins: 0x3e00008
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x1f rt: 0 i: 0x8
+ r rs: 31 rt: 0 rd: 0 sh: 0 func: 0x8
+ V rs: 0xbfc001a4 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00240 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 m_next_pc: 0xbfc003e4 m_jump_pc: 0xbfc001a4 m_ifetch_addr: 0xbfc003e4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+ mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003e4 NPC: 0xbfc001a4 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00240 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 m_next_pc: 0xbfc001a4 m_jump_pc: 0xbfc001a8 m_ifetch_addr: 0xbfc001a4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x40044000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc001a4 NPC: 0xbfc001a8 Ins: 0x40044000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x10 (cop0)
+ i rs: 0 rt: 0x4 i: 0x4000
+ r rs: 0 rt: 4 rd: 8 sh: 0 func: 0
+ V rs: 0 rt: 0xbfc00239
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00240 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 m_next_pc: 0xbfc001a8 m_jump_pc: 0xbfc001ac m_ifetch_addr: 0xbfc001a8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xff000fa>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc001a8 NPC: 0xbfc001ac Ins: 0xff000fa
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x3 (jal)
+ i rs: 0x1f rt: 0x10 i: 0xfa
+ r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x3a
+ V rs: 0xbfc001a4 rt: 0xdea9
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00240 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 m_next_pc: 0xbfc001ac m_jump_pc: 0xbfc003e8 m_ifetch_addr: 0xbfc001ac
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc001ac NPC: 0xbfc003e8 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00240 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc003e8 m_jump_pc: 0xbfc003ec m_ifetch_addr: 0xbfc003e8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x804021>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003e8 NPC: 0xbfc003ec Ins: 0x804021
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x4 rt: 0 i: 0x4021
+ r rs: 4 rt: 0 rd: 8 sh: 0 func: 0x21
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00240 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc003ec m_jump_pc: 0xbfc003f0 m_ifetch_addr: 0xbfc003ec
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x24090030>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003ec NPC: 0xbfc003f0 Ins: 0x24090030
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0 rt: 0x9 i: 0x30
+ r rs: 0 rt: 9 rd: 0 sh: 0 func: 0x30
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc003f0 m_jump_pc: 0xbfc003f4 m_ifetch_addr: 0xbfc003f0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa3490000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003f0 NPC: 0xbfc003f4 Ins: 0xa3490000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0x9 i: 0
+ r rs: 26 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000030 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc003f4 m_jump_pc: 0xbfc003f8 m_ifetch_addr: 0xbfc003f4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x24090078>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc003f4 NPC: 0xbfc003f8 Ins: 0x24090078
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0 rt: 0x9 i: 0x78
+ r rs: 0 rt: 9 rd: 0 sh: 1 func: 0x38
+ V rs: 0 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000030 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc003f8 m_jump_pc: 0xbfc003fc m_ifetch_addr: 0xbfc003f8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa3490000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003f8 NPC: 0xbfc003fc Ins: 0xa3490000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0x9 i: 0
+ r rs: 26 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x78
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000078 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x78 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc003fc m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc003fc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x24090008>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc003fc NPC: 0xbfc00400 Ins: 0x24090008
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0 rt: 0x9 i: 0x8
+ r rs: 0 rt: 9 rd: 0 sh: 0 func: 0x8
+ V rs: 0 rt: 0x78
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000078 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c0af000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0xa i: 0xf000
+ r rs: 0 rt: 10 rd: 30 sh: 0 func: 0
+ V rs: 0 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000008 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x10a5024>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x8 rt: 0xa i: 0x5024
+ r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24
+ V rs: 0 rt: 0xf0000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000008 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa5702>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0xa i: 0x5702
+ r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000008 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+0mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x294b000a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xa (slti)
+ i rs: 0xa rt: 0xb i: 0xa
+ r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa
+ V rs: 0 rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000008 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11600004>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0xb rt: 0 i: 0x4
+ r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4
+ V rs: 0x1 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000008 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000008 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x214a0030>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0xa rt: 0xa i: 0x30
+ r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000008 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0010a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0x10a
+ r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa
+ V rs: 0xbfc001b0 rt: 0xdea9
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000008 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000008 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa34a0000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0xa i: 0
+ r rs: 26 rt: 10 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000008 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2129ffff>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0x9 rt: 0x9 i: 0xffff
+ r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f
+ V rs: 0x8 rt: 0x8
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000008 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x1d20fff3>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x7 (bgtz)
+ i rs: 0x9 rt: 0 i: 0xfff3
+ r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33
+ V rs: 0x7 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000007 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x84100>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0x8 i: 0x4100
+ r rs: 0 rt: 8 rd: 8 sh: 4 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000007 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+xmips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c0af000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0xa i: 0xf000
+ r rs: 0 rt: 10 rd: 30 sh: 0 func: 0
+ V rs: 0 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000007 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x10a5024>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x8 rt: 0xa i: 0x5024
+ r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24
+ V rs: 0 rt: 0xf0000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000007 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa5702>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0xa i: 0x5702
+ r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000007 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x294b000a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xa (slti)
+ i rs: 0xa rt: 0xb i: 0xa
+ r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa
+ V rs: 0 rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000007 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11600004>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0xb rt: 0 i: 0x4
+ r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4
+ V rs: 0x1 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000007 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000007 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x214a0030>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0xa rt: 0xa i: 0x30
+ r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000007 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0010a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0x10a
+ r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa
+ V rs: 0xbfc001b0 rt: 0xdea9
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000007 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000007 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa34a0000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0xa i: 0
+ r rs: 26 rt: 10 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000007 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+0mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2129ffff>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0x9 rt: 0x9 i: 0xffff
+ r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f
+ V rs: 0x7 rt: 0x7
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000007 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x1d20fff3>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x7 (bgtz)
+ i rs: 0x9 rt: 0 i: 0xfff3
+ r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33
+ V rs: 0x6 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000006 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x84100>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0x8 i: 0x4100
+ r rs: 0 rt: 8 rd: 8 sh: 4 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000006 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c0af000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0xa i: 0xf000
+ r rs: 0 rt: 10 rd: 30 sh: 0 func: 0
+ V rs: 0 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000006 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x10a5024>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x8 rt: 0xa i: 0x5024
+ r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24
+ V rs: 0 rt: 0xf0000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000006 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa5702>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0xa i: 0x5702
+ r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000006 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x294b000a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xa (slti)
+ i rs: 0xa rt: 0xb i: 0xa
+ r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa
+ V rs: 0 rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000006 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11600004>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0xb rt: 0 i: 0x4
+ r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4
+ V rs: 0x1 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000006 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000006 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x214a0030>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0xa rt: 0xa i: 0x30
+ r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000006 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+0mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0010a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0x10a
+ r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa
+ V rs: 0xbfc001b0 rt: 0xdea9
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000006 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000006 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa34a0000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0xa i: 0
+ r rs: 26 rt: 10 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000006 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2129ffff>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0x9 rt: 0x9 i: 0xffff
+ r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f
+ V rs: 0x6 rt: 0x6
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000006 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x1d20fff3>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x7 (bgtz)
+ i rs: 0x9 rt: 0 i: 0xfff3
+ r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33
+ V rs: 0x5 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000005 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x84100>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0x8 i: 0x4100
+ r rs: 0 rt: 8 rd: 8 sh: 4 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000005 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c0af000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0xa i: 0xf000
+ r rs: 0 rt: 10 rd: 30 sh: 0 func: 0
+ V rs: 0 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000005 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x10a5024>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x8 rt: 0xa i: 0x5024
+ r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24
+ V rs: 0 rt: 0xf0000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000005 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa5702>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0xa i: 0x5702
+ r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000005 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x294b000a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xa (slti)
+ i rs: 0xa rt: 0xb i: 0xa
+ r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa
+ V rs: 0 rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000005 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+0mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11600004>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0xb rt: 0 i: 0x4
+ r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4
+ V rs: 0x1 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000005 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000005 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x214a0030>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0xa rt: 0xa i: 0x30
+ r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000005 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0010a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0x10a
+ r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa
+ V rs: 0xbfc001b0 rt: 0xdea9
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000005 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000005 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa34a0000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0xa i: 0
+ r rs: 26 rt: 10 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000005 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2129ffff>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0x9 rt: 0x9 i: 0xffff
+ r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f
+ V rs: 0x5 rt: 0x5
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000005 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x1d20fff3>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x7 (bgtz)
+ i rs: 0x9 rt: 0 i: 0xfff3
+ r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33
+ V rs: 0x4 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x84100>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0x8 i: 0x4100
+ r rs: 0 rt: 8 rd: 8 sh: 4 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c0af000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0xa i: 0xf000
+ r rs: 0 rt: 10 rd: 30 sh: 0 func: 0
+ V rs: 0 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x10a5024>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x8 rt: 0xa i: 0x5024
+ r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24
+ V rs: 0 rt: 0xf0000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000004 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa5702>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0xa i: 0x5702
+ r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000004 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+0mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x294b000a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xa (slti)
+ i rs: 0xa rt: 0xb i: 0xa
+ r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa
+ V rs: 0 rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000004 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11600004>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0xb rt: 0 i: 0x4
+ r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4
+ V rs: 0x1 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000004 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000004 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x214a0030>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0xa rt: 0xa i: 0x30
+ r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000004 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0010a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0x10a
+ r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa
+ V rs: 0xbfc001b0 rt: 0xdea9
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa34a0000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0xa i: 0
+ r rs: 26 rt: 10 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2129ffff>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0x9 rt: 0x9 i: 0xffff
+ r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f
+ V rs: 0x4 rt: 0x4
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x1d20fff3>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x7 (bgtz)
+ i rs: 0x9 rt: 0 i: 0xfff3
+ r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33
+ V rs: 0x3 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x84100>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0x8 i: 0x4100
+ r rs: 0 rt: 8 rd: 8 sh: 4 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c0af000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0xa i: 0xf000
+ r rs: 0 rt: 10 rd: 30 sh: 0 func: 0
+ V rs: 0 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x10a5024>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x8 rt: 0xa i: 0x5024
+ r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24
+ V rs: 0 rt: 0xf0000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000003 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa5702>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0xa i: 0x5702
+ r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000003 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+0mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x294b000a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xa (slti)
+ i rs: 0xa rt: 0xb i: 0xa
+ r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa
+ V rs: 0 rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000003 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11600004>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0xb rt: 0 i: 0x4
+ r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4
+ V rs: 0x1 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000003 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000003 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x214a0030>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0xa rt: 0xa i: 0x30
+ r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000003 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0010a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0x10a
+ r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa
+ V rs: 0xbfc001b0 rt: 0xdea9
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa34a0000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0xa i: 0
+ r rs: 26 rt: 10 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2129ffff>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0x9 rt: 0x9 i: 0xffff
+ r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f
+ V rs: 0x3 rt: 0x3
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x1d20fff3>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x7 (bgtz)
+ i rs: 0x9 rt: 0 i: 0xfff3
+ r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33
+ V rs: 0x2 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000002 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x84100>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0x8 i: 0x4100
+ r rs: 0 rt: 8 rd: 8 sh: 4 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000002 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c0af000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0xa i: 0xf000
+ r rs: 0 rt: 10 rd: 30 sh: 0 func: 0
+ V rs: 0 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000002 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x10a5024>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x8 rt: 0xa i: 0x5024
+ r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24
+ V rs: 0 rt: 0xf0000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000002 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa5702>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0xa i: 0x5702
+ r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000002 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+0mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x294b000a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xa (slti)
+ i rs: 0xa rt: 0xb i: 0xa
+ r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa
+ V rs: 0 rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000002 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11600004>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0xb rt: 0 i: 0x4
+ r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4
+ V rs: 0x1 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000002 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000002 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x214a0030>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0xa rt: 0xa i: 0x30
+ r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000002 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0010a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0x10a
+ r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa
+ V rs: 0xbfc001b0 rt: 0xdea9
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000002 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000002 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa34a0000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0xa i: 0
+ r rs: 26 rt: 10 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000002 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2129ffff>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0x9 rt: 0x9 i: 0xffff
+ r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f
+ V rs: 0x2 rt: 0x2
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000002 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x1d20fff3>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x7 (bgtz)
+ i rs: 0x9 rt: 0 i: 0xfff3
+ r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33
+ V rs: 0x1 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000001 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x84100>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0x8 i: 0x4100
+ r rs: 0 rt: 8 rd: 8 sh: 4 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000001 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c0af000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0xa i: 0xf000
+ r rs: 0 rt: 10 rd: 30 sh: 0 func: 0
+ V rs: 0 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000001 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x10a5024>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x8 rt: 0xa i: 0x5024
+ r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24
+ V rs: 0 rt: 0xf0000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000001 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa5702>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0xa i: 0x5702
+ r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000001 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+0mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x294b000a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xa (slti)
+ i rs: 0xa rt: 0xb i: 0xa
+ r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa
+ V rs: 0 rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000001 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11600004>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0xb rt: 0 i: 0x4
+ r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4
+ V rs: 0x1 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000001 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000001 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x214a0030>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0xa rt: 0xa i: 0x30
+ r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000001 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0010a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0x10a
+ r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa
+ V rs: 0xbfc001b0 rt: 0xdea9
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000001 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000001 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa34a0000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0xa i: 0
+ r rs: 26 rt: 10 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000001 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2129ffff>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0x9 rt: 0x9 i: 0xffff
+ r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f
+ V rs: 0x1 rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000001 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x1d20fff3>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x7 (bgtz)
+ i rs: 0x9 rt: 0 i: 0xfff3
+ r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00438 m_ifetch_addr: 0xbfc00434
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x84100>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00434 NPC: 0xbfc00438 Ins: 0x84100
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0x8 i: 0x4100
+ r rs: 0 rt: 8 rd: 8 sh: 4 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00438 m_jump_pc: 0xbfc0043c m_ifetch_addr: 0xbfc00438
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3e00008>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00438 NPC: 0xbfc0043c Ins: 0x3e00008
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x1f rt: 0 i: 0x8
+ r rs: 31 rt: 0 rd: 0 sh: 0 func: 0x8
+ V rs: 0xbfc001b0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc0043c m_jump_pc: 0xbfc001b0 m_ifetch_addr: 0xbfc0043c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0043c NPC: 0xbfc001b0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc001b0 m_jump_pc: 0xbfc001b4 m_ifetch_addr: 0xbfc001b0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c04bfc0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc001b0 NPC: 0xbfc001b4 Ins: 0x3c04bfc0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0x4 i: 0xbfc0
+ r rs: 0 rt: 4 rd: 23 sh: 31 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc001b4 m_jump_pc: 0xbfc001b8 m_ifetch_addr: 0xbfc001b4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+0mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x24840241>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc001b4 NPC: 0xbfc001b8 Ins: 0x24840241
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0x4 rt: 0x4 i: 0x241
+ r rs: 4 rt: 4 rd: 0 sh: 9 func: 0x1
+ V rs: 0xbfc00000 rt: 0xbfc00000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc001b8 m_jump_pc: 0xbfc001bc m_ifetch_addr: 0xbfc001b8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xff000f0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc001b8 NPC: 0xbfc001bc Ins: 0xff000f0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x3 (jal)
+ i rs: 0x1f rt: 0x10 i: 0xf0
+ r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x30
+ V rs: 0xbfc001b0 rt: 0xdea9
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc001bc m_jump_pc: 0xbfc003c0 m_ifetch_addr: 0xbfc001bc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc001bc NPC: 0xbfc003c0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 m_next_pc: 0xbfc003c0 m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003c0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x804021>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c0 NPC: 0xbfc003c4 Ins: 0x804021
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x4 rt: 0 i: 0x4021
+ r rs: 4 rt: 0 rd: 8 sh: 0 func: 0x21
+ V rs: 0xbfc00241 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x81090000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x20 (lb)
+ i rs: 0x8 rt: 0x9 i: 0
+ r rs: 8 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xbfc00241 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00241 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_READ @ 0xbfc00240 wdata 0 be 0x2> off: 0x1 sign_ext: 0x1 dest: gp+0x9
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp valid no error rdata 0x69782000>, 0)
+mips0 setData: <DataRsp valid no error rdata 0x69782000> off: 0 sign_ext: 0x1 dest: r_gp+0x9
+mips0 setData: <DataRsp valid no error rdata 0x69782000> off: 0 count: 0x1 le: 0x1 old: 0 from_mem: 0x69782000 mask: 0xffffffff new_data: 0x20
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0x9 rt: 0 i: 0x5
+ r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5
+ V rs: 0x20 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00241 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00241 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa3490000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0x9 i: 0
+ r rs: 26 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x20
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00241 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x20 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0x8 rt: 0x8 i: 0x1
+ r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1
+ V rs: 0xbfc00241 rt: 0xbfc00241
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00241 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf000f1>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0xf1
+ r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31
+ V rs: 0xbfc001c0 rt: 0xdea9
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00242 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00242 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x81090000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x20 (lb)
+ i rs: 0x8 rt: 0x9 i: 0
+ r rs: 8 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xbfc00242 rt: 0x20
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00242 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_READ @ 0xbfc00240 wdata 0 be 0x4> off: 0x2 sign_ext: 0x1 dest: gp+0x9
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp valid no error rdata 0x69782000>, 0)
+mips0 setData: <DataRsp valid no error rdata 0x69782000> off: 0 sign_ext: 0x1 dest: r_gp+0x9
+mips0 setData: <DataRsp valid no error rdata 0x69782000> off: 0 count: 0x1 le: 0x2 old: 0x20 from_mem: 0x69782000 mask: 0xffffffff new_data: 0x78
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1
+ mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0x9 rt: 0 i: 0x5
+ r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5
+ V rs: 0x78 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00242 09: 00000078 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00242 09: 00000078 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa3490000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0x9 i: 0
+ r rs: 26 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x78
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00242 09: 00000078 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x78 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0x8 rt: 0x8 i: 0x1
+ r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1
+ V rs: 0xbfc00242 rt: 0xbfc00242
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00242 09: 00000078 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf000f1>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0xf1
+ r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31
+ V rs: 0xbfc001c0 rt: 0xdea9
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00243 09: 00000078 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00243 09: 00000078 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x81090000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x20 (lb)
+ i rs: 0x8 rt: 0x9 i: 0
+ r rs: 8 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xbfc00243 rt: 0x78
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00243 09: 00000078 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_READ @ 0xbfc00240 wdata 0 be 0x8> off: 0x3 sign_ext: 0x1 dest: gp+0x9
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp valid no error rdata 0x69782000>, 0)
+mips0 setData: <DataRsp valid no error rdata 0x69782000> off: 0 sign_ext: 0x1 dest: r_gp+0x9
+mips0 setData: <DataRsp valid no error rdata 0x69782000> off: 0 count: 0x1 le: 0x3 old: 0x78 from_mem: 0x69782000 mask: 0xffffffff new_data: 0x69
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0x9 rt: 0 i: 0x5
+ r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5
+ V rs: 0x69 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00243 09: 00000069 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+xmips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00243 09: 00000069 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa3490000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0x9 i: 0
+ r rs: 26 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x69
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00243 09: 00000069 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x69 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0x8 rt: 0x8 i: 0x1
+ r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1
+ V rs: 0xbfc00243 rt: 0xbfc00243
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00243 09: 00000069 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf000f1>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0xf1
+ r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31
+ V rs: 0xbfc001c0 rt: 0xdea9
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00244 09: 00000069 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00244 09: 00000069 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x81090000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x20 (lb)
+ i rs: 0x8 rt: 0x9 i: 0
+ r rs: 8 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xbfc00244 rt: 0x69
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00244 09: 00000069 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_READ @ 0xbfc00244 wdata 0 be 0x1> off: 0 sign_ext: 0x1 dest: gp+0x9
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp valid no error rdata 0x207563>, 0)
+mips0 setData: <DataRsp valid no error rdata 0x207563> off: 0 sign_ext: 0x1 dest: r_gp+0x9
+mips0 setData: <DataRsp valid no error rdata 0x207563> off: 0 count: 0x1 le: 0 old: 0x69 from_mem: 0x207563 mask: 0xffffffff new_data: 0x63
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0x9 rt: 0 i: 0x5
+ r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5
+ V rs: 0x63 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00244 09: 00000063 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00244 09: 00000063 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+imips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa3490000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0x9 i: 0
+ r rs: 26 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x63
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00244 09: 00000063 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x63 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0x8 rt: 0x8 i: 0x1
+ r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1
+ V rs: 0xbfc00244 rt: 0xbfc00244
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00244 09: 00000063 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf000f1>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0xf1
+ r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31
+ V rs: 0xbfc001c0 rt: 0xdea9
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00245 09: 00000063 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00245 09: 00000063 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x81090000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x20 (lb)
+ i rs: 0x8 rt: 0x9 i: 0
+ r rs: 8 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xbfc00245 rt: 0x63
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00245 09: 00000063 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_READ @ 0xbfc00244 wdata 0 be 0x2> off: 0x1 sign_ext: 0x1 dest: gp+0x9
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp valid no error rdata 0x207563>, 0)
+mips0 setData: <DataRsp valid no error rdata 0x207563> off: 0 sign_ext: 0x1 dest: r_gp+0x9
+mips0 setData: <DataRsp valid no error rdata 0x207563> off: 0 count: 0x1 le: 0x1 old: 0x63 from_mem: 0x207563 mask: 0xffffffff new_data: 0x75
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0x9 rt: 0 i: 0x5
+ r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5
+ V rs: 0x75 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00245 09: 00000075 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00245 09: 00000075 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa3490000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0x9 i: 0
+ r rs: 26 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x75
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00245 09: 00000075 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x75 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+cmips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0x8 rt: 0x8 i: 0x1
+ r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1
+ V rs: 0xbfc00245 rt: 0xbfc00245
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00245 09: 00000075 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf000f1>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0xf1
+ r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31
+ V rs: 0xbfc001c0 rt: 0xdea9
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00246 09: 00000075 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00246 09: 00000075 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x81090000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x20 (lb)
+ i rs: 0x8 rt: 0x9 i: 0
+ r rs: 8 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xbfc00246 rt: 0x75
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00246 09: 00000075 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_READ @ 0xbfc00244 wdata 0 be 0x4> off: 0x2 sign_ext: 0x1 dest: gp+0x9
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp valid no error rdata 0x207563>, 0)
+mips0 setData: <DataRsp valid no error rdata 0x207563> off: 0 sign_ext: 0x1 dest: r_gp+0x9
+mips0 setData: <DataRsp valid no error rdata 0x207563> off: 0 count: 0x1 le: 0x2 old: 0x75 from_mem: 0x207563 mask: 0xffffffff new_data: 0x20
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0x9 rt: 0 i: 0x5
+ r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5
+ V rs: 0x20 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00246 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00246 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa3490000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0x9 i: 0
+ r rs: 26 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x20
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00246 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x20 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+umips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0x8 rt: 0x8 i: 0x1
+ r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1
+ V rs: 0xbfc00246 rt: 0xbfc00246
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00246 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf000f1>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0xf1
+ r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31
+ V rs: 0xbfc001c0 rt: 0xdea9
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00247 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00247 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x81090000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x20 (lb)
+ i rs: 0x8 rt: 0x9 i: 0
+ r rs: 8 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xbfc00247 rt: 0x20
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00247 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_READ @ 0xbfc00244 wdata 0 be 0x8> off: 0x3 sign_ext: 0x1 dest: gp+0x9
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp valid no error rdata 0x207563>, 0)
+mips0 setData: <DataRsp valid no error rdata 0x207563> off: 0 sign_ext: 0x1 dest: r_gp+0x9
+mips0 setData: <DataRsp valid no error rdata 0x207563> off: 0 count: 0x1 le: 0x3 old: 0x20 from_mem: 0x207563 mask: 0xffffffff new_data: 0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0x9 rt: 0 i: 0x5
+ r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00247 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003e0 m_ifetch_addr: 0xbfc003cc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003cc NPC: 0xbfc003e0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00247 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 m_next_pc: 0xbfc003e0 m_jump_pc: 0xbfc003e4 m_ifetch_addr: 0xbfc003e0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3e00008>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003e0 NPC: 0xbfc003e4 Ins: 0x3e00008
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x1f rt: 0 i: 0x8
+ r rs: 31 rt: 0 rd: 0 sh: 0 func: 0x8
+ V rs: 0xbfc001c0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00247 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 m_next_pc: 0xbfc003e4 m_jump_pc: 0xbfc001c0 m_ifetch_addr: 0xbfc003e4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+ mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003e4 NPC: 0xbfc001c0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00247 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 m_next_pc: 0xbfc001c0 m_jump_pc: 0xbfc001c4 m_ifetch_addr: 0xbfc001c0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c08d820>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc001c0 NPC: 0xbfc001c4 Ins: 0x3c08d820
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0x8 i: 0xd820
+ r rs: 0 rt: 8 rd: 27 sh: 0 func: 0x20
+ V rs: 0 rt: 0xbfc00247
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00247 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 m_next_pc: 0xbfc001c4 m_jump_pc: 0xbfc001c8 m_ifetch_addr: 0xbfc001c4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x8d040780>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc001c4 NPC: 0xbfc001c8 Ins: 0x8d040780
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x23 (lw)
+ i rs: 0x8 rt: 0x4 i: 0x780
+ r rs: 8 rt: 4 rd: 0 sh: 30 func: 0
+ V rs: 0xd8200000 rt: 0xbfc00241
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: d8200000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_READ @ 0xd8200780 wdata 0 be 0xf> off: 0 sign_ext: 0 dest: gp+0x4
+mips0 m_next_pc: 0xbfc001c8 m_jump_pc: 0xbfc001cc m_ifetch_addr: 0xbfc001c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xff000fa>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc001c8 m_jump_pc: 0xbfc001cc m_ifetch_addr: 0xbfc001c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xff000fa>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc001c8 m_jump_pc: 0xbfc001cc m_ifetch_addr: 0xbfc001c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xff000fa>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc001c8 m_jump_pc: 0xbfc001cc m_ifetch_addr: 0xbfc001c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xff000fa>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc001c8 m_jump_pc: 0xbfc001cc m_ifetch_addr: 0xbfc001c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xff000fa>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc001c8 m_jump_pc: 0xbfc001cc m_ifetch_addr: 0xbfc001c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xff000fa>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc001c8 m_jump_pc: 0xbfc001cc m_ifetch_addr: 0xbfc001c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xff000fa>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc001c8 m_jump_pc: 0xbfc001cc m_ifetch_addr: 0xbfc001c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xff000fa>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc001c8 m_jump_pc: 0xbfc001cc m_ifetch_addr: 0xbfc001c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xff000fa>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc001c8 m_jump_pc: 0xbfc001cc m_ifetch_addr: 0xbfc001c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xff000fa>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc001c8 m_jump_pc: 0xbfc001cc m_ifetch_addr: 0xbfc001c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xff000fa>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc001c8 m_jump_pc: 0xbfc001cc m_ifetch_addr: 0xbfc001c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xff000fa>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc001c8 m_jump_pc: 0xbfc001cc m_ifetch_addr: 0xbfc001c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xff000fa>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x4
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 count: 0x4 le: 0 old: 0xbfc00241 from_mem: 0 mask: 0xffffffff new_data: 0
+mips0 PC: 0xbfc001c8 NPC: 0xbfc001cc Ins: 0xff000fa
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x3 (jal)
+ i rs: 0x1f rt: 0x10 i: 0xfa
+ r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x3a
+ V rs: 0xbfc001c0 rt: 0xdea9
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: d8200000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 m_next_pc: 0xbfc001cc m_jump_pc: 0xbfc003e8 m_ifetch_addr: 0xbfc001cc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc001cc NPC: 0xbfc003e8 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: d8200000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc003e8 m_jump_pc: 0xbfc003ec m_ifetch_addr: 0xbfc003e8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x804021>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003e8 NPC: 0xbfc003ec Ins: 0x804021
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x4 rt: 0 i: 0x4021
+ r rs: 4 rt: 0 rd: 8 sh: 0 func: 0x21
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: d8200000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc003ec m_jump_pc: 0xbfc003f0 m_ifetch_addr: 0xbfc003ec
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x24090030>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003ec NPC: 0xbfc003f0 Ins: 0x24090030
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0 rt: 0x9 i: 0x30
+ r rs: 0 rt: 9 rd: 0 sh: 0 func: 0x30
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc003f0 m_jump_pc: 0xbfc003f4 m_ifetch_addr: 0xbfc003f0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa3490000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003f0 NPC: 0xbfc003f4 Ins: 0xa3490000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0x9 i: 0
+ r rs: 26 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000030 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc003f4 m_jump_pc: 0xbfc003f8 m_ifetch_addr: 0xbfc003f4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x24090078>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc003f4 NPC: 0xbfc003f8 Ins: 0x24090078
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0 rt: 0x9 i: 0x78
+ r rs: 0 rt: 9 rd: 0 sh: 1 func: 0x38
+ V rs: 0 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000030 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc003f8 m_jump_pc: 0xbfc003fc m_ifetch_addr: 0xbfc003f8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa3490000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003f8 NPC: 0xbfc003fc Ins: 0xa3490000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0x9 i: 0
+ r rs: 26 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x78
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000078 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x78 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc003fc m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc003fc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x24090008>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc003fc NPC: 0xbfc00400 Ins: 0x24090008
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0 rt: 0x9 i: 0x8
+ r rs: 0 rt: 9 rd: 0 sh: 0 func: 0x8
+ V rs: 0 rt: 0x78
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000078 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c0af000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0xa i: 0xf000
+ r rs: 0 rt: 10 rd: 30 sh: 0 func: 0
+ V rs: 0 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000008 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x10a5024>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x8 rt: 0xa i: 0x5024
+ r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24
+ V rs: 0 rt: 0xf0000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000008 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa5702>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0xa i: 0x5702
+ r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000008 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+0mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x294b000a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xa (slti)
+ i rs: 0xa rt: 0xb i: 0xa
+ r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa
+ V rs: 0 rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000008 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11600004>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0xb rt: 0 i: 0x4
+ r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4
+ V rs: 0x1 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000008 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000008 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x214a0030>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0xa rt: 0xa i: 0x30
+ r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000008 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0010a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0x10a
+ r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa
+ V rs: 0xbfc001d0 rt: 0xdea9
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000008 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000008 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa34a0000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0xa i: 0
+ r rs: 26 rt: 10 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000008 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2129ffff>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0x9 rt: 0x9 i: 0xffff
+ r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f
+ V rs: 0x8 rt: 0x8
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000008 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x1d20fff3>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x7 (bgtz)
+ i rs: 0x9 rt: 0 i: 0xfff3
+ r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33
+ V rs: 0x7 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000007 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x84100>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0x8 i: 0x4100
+ r rs: 0 rt: 8 rd: 8 sh: 4 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000007 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+xmips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c0af000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0xa i: 0xf000
+ r rs: 0 rt: 10 rd: 30 sh: 0 func: 0
+ V rs: 0 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000007 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x10a5024>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x8 rt: 0xa i: 0x5024
+ r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24
+ V rs: 0 rt: 0xf0000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000007 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa5702>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0xa i: 0x5702
+ r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000007 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x294b000a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xa (slti)
+ i rs: 0xa rt: 0xb i: 0xa
+ r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa
+ V rs: 0 rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000007 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11600004>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0xb rt: 0 i: 0x4
+ r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4
+ V rs: 0x1 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000007 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000007 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x214a0030>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0xa rt: 0xa i: 0x30
+ r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000007 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0010a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0x10a
+ r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa
+ V rs: 0xbfc001d0 rt: 0xdea9
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000007 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000007 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa34a0000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0xa i: 0
+ r rs: 26 rt: 10 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000007 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+0mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2129ffff>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0x9 rt: 0x9 i: 0xffff
+ r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f
+ V rs: 0x7 rt: 0x7
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000007 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x1d20fff3>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x7 (bgtz)
+ i rs: 0x9 rt: 0 i: 0xfff3
+ r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33
+ V rs: 0x6 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000006 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x84100>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0x8 i: 0x4100
+ r rs: 0 rt: 8 rd: 8 sh: 4 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000006 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c0af000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0xa i: 0xf000
+ r rs: 0 rt: 10 rd: 30 sh: 0 func: 0
+ V rs: 0 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000006 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x10a5024>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x8 rt: 0xa i: 0x5024
+ r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24
+ V rs: 0 rt: 0xf0000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000006 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa5702>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0xa i: 0x5702
+ r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000006 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x294b000a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xa (slti)
+ i rs: 0xa rt: 0xb i: 0xa
+ r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa
+ V rs: 0 rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000006 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11600004>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0xb rt: 0 i: 0x4
+ r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4
+ V rs: 0x1 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000006 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000006 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x214a0030>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0xa rt: 0xa i: 0x30
+ r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000006 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+0mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0010a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0x10a
+ r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa
+ V rs: 0xbfc001d0 rt: 0xdea9
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000006 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000006 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa34a0000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0xa i: 0
+ r rs: 26 rt: 10 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000006 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2129ffff>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0x9 rt: 0x9 i: 0xffff
+ r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f
+ V rs: 0x6 rt: 0x6
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000006 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x1d20fff3>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x7 (bgtz)
+ i rs: 0x9 rt: 0 i: 0xfff3
+ r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33
+ V rs: 0x5 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000005 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x84100>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0x8 i: 0x4100
+ r rs: 0 rt: 8 rd: 8 sh: 4 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000005 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c0af000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0xa i: 0xf000
+ r rs: 0 rt: 10 rd: 30 sh: 0 func: 0
+ V rs: 0 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000005 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x10a5024>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x8 rt: 0xa i: 0x5024
+ r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24
+ V rs: 0 rt: 0xf0000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000005 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa5702>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0xa i: 0x5702
+ r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000005 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x294b000a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xa (slti)
+ i rs: 0xa rt: 0xb i: 0xa
+ r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa
+ V rs: 0 rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000005 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+0mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11600004>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0xb rt: 0 i: 0x4
+ r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4
+ V rs: 0x1 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000005 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000005 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x214a0030>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0xa rt: 0xa i: 0x30
+ r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000005 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0010a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0x10a
+ r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa
+ V rs: 0xbfc001d0 rt: 0xdea9
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000005 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000005 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa34a0000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0xa i: 0
+ r rs: 26 rt: 10 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000005 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2129ffff>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0x9 rt: 0x9 i: 0xffff
+ r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f
+ V rs: 0x5 rt: 0x5
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000005 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x1d20fff3>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x7 (bgtz)
+ i rs: 0x9 rt: 0 i: 0xfff3
+ r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33
+ V rs: 0x4 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x84100>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0x8 i: 0x4100
+ r rs: 0 rt: 8 rd: 8 sh: 4 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c0af000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0xa i: 0xf000
+ r rs: 0 rt: 10 rd: 30 sh: 0 func: 0
+ V rs: 0 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x10a5024>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x8 rt: 0xa i: 0x5024
+ r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24
+ V rs: 0 rt: 0xf0000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000004 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa5702>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0xa i: 0x5702
+ r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000004 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+0mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x294b000a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xa (slti)
+ i rs: 0xa rt: 0xb i: 0xa
+ r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa
+ V rs: 0 rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000004 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11600004>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0xb rt: 0 i: 0x4
+ r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4
+ V rs: 0x1 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000004 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000004 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x214a0030>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0xa rt: 0xa i: 0x30
+ r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000004 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0010a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0x10a
+ r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa
+ V rs: 0xbfc001d0 rt: 0xdea9
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa34a0000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0xa i: 0
+ r rs: 26 rt: 10 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2129ffff>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0x9 rt: 0x9 i: 0xffff
+ r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f
+ V rs: 0x4 rt: 0x4
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x1d20fff3>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x7 (bgtz)
+ i rs: 0x9 rt: 0 i: 0xfff3
+ r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33
+ V rs: 0x3 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x84100>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0x8 i: 0x4100
+ r rs: 0 rt: 8 rd: 8 sh: 4 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c0af000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0xa i: 0xf000
+ r rs: 0 rt: 10 rd: 30 sh: 0 func: 0
+ V rs: 0 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x10a5024>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x8 rt: 0xa i: 0x5024
+ r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24
+ V rs: 0 rt: 0xf0000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000003 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa5702>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0xa i: 0x5702
+ r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000003 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+0mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x294b000a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xa (slti)
+ i rs: 0xa rt: 0xb i: 0xa
+ r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa
+ V rs: 0 rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000003 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11600004>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0xb rt: 0 i: 0x4
+ r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4
+ V rs: 0x1 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000003 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000003 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x214a0030>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0xa rt: 0xa i: 0x30
+ r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000003 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0010a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0x10a
+ r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa
+ V rs: 0xbfc001d0 rt: 0xdea9
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa34a0000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0xa i: 0
+ r rs: 26 rt: 10 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2129ffff>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0x9 rt: 0x9 i: 0xffff
+ r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f
+ V rs: 0x3 rt: 0x3
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x1d20fff3>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x7 (bgtz)
+ i rs: 0x9 rt: 0 i: 0xfff3
+ r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33
+ V rs: 0x2 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000002 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x84100>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0x8 i: 0x4100
+ r rs: 0 rt: 8 rd: 8 sh: 4 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000002 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c0af000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0xa i: 0xf000
+ r rs: 0 rt: 10 rd: 30 sh: 0 func: 0
+ V rs: 0 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000002 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x10a5024>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x8 rt: 0xa i: 0x5024
+ r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24
+ V rs: 0 rt: 0xf0000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000002 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa5702>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0xa i: 0x5702
+ r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000002 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+0mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x294b000a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xa (slti)
+ i rs: 0xa rt: 0xb i: 0xa
+ r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa
+ V rs: 0 rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000002 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11600004>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0xb rt: 0 i: 0x4
+ r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4
+ V rs: 0x1 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000002 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000002 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x214a0030>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0xa rt: 0xa i: 0x30
+ r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000002 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0010a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0x10a
+ r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa
+ V rs: 0xbfc001d0 rt: 0xdea9
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000002 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000002 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa34a0000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0xa i: 0
+ r rs: 26 rt: 10 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000002 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2129ffff>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0x9 rt: 0x9 i: 0xffff
+ r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f
+ V rs: 0x2 rt: 0x2
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000002 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x1d20fff3>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x7 (bgtz)
+ i rs: 0x9 rt: 0 i: 0xfff3
+ r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33
+ V rs: 0x1 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000001 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x84100>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0x8 i: 0x4100
+ r rs: 0 rt: 8 rd: 8 sh: 4 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000001 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c0af000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0xa i: 0xf000
+ r rs: 0 rt: 10 rd: 30 sh: 0 func: 0
+ V rs: 0 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000001 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x10a5024>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x8 rt: 0xa i: 0x5024
+ r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24
+ V rs: 0 rt: 0xf0000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000001 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa5702>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0xa i: 0x5702
+ r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000001 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+0mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x294b000a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xa (slti)
+ i rs: 0xa rt: 0xb i: 0xa
+ r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa
+ V rs: 0 rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000001 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11600004>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0xb rt: 0 i: 0x4
+ r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4
+ V rs: 0x1 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000001 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000001 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x214a0030>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0xa rt: 0xa i: 0x30
+ r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000001 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0010a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0x10a
+ r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa
+ V rs: 0xbfc001d0 rt: 0xdea9
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000001 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000001 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa34a0000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0xa i: 0
+ r rs: 26 rt: 10 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000001 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2129ffff>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0x9 rt: 0x9 i: 0xffff
+ r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f
+ V rs: 0x1 rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000001 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x1d20fff3>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x7 (bgtz)
+ i rs: 0x9 rt: 0 i: 0xfff3
+ r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00438 m_ifetch_addr: 0xbfc00434
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x84100>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00434 NPC: 0xbfc00438 Ins: 0x84100
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0x8 i: 0x4100
+ r rs: 0 rt: 8 rd: 8 sh: 4 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00438 m_jump_pc: 0xbfc0043c m_ifetch_addr: 0xbfc00438
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3e00008>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00438 NPC: 0xbfc0043c Ins: 0x3e00008
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x1f rt: 0 i: 0x8
+ r rs: 31 rt: 0 rd: 0 sh: 0 func: 0x8
+ V rs: 0xbfc001d0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc0043c m_jump_pc: 0xbfc001d0 m_ifetch_addr: 0xbfc0043c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0043c NPC: 0xbfc001d0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc001d0 m_jump_pc: 0xbfc001d4 m_ifetch_addr: 0xbfc001d0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2404000a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc001d0 NPC: 0xbfc001d4 Ins: 0x2404000a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0 rt: 0x4 i: 0xa
+ r rs: 0 rt: 4 rd: 0 sh: 0 func: 0xa
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc001d4 m_jump_pc: 0xbfc001d8 m_ifetch_addr: 0xbfc001d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+0mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa3440000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc001d4 NPC: 0xbfc001d8 Ins: 0xa3440000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0x4 i: 0
+ r rs: 26 rt: 4 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0xa
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 0000000a 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0xa be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc001d8 m_jump_pc: 0xbfc001dc m_ifetch_addr: 0xbfc001d8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x32530001>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc001d8 NPC: 0xbfc001dc Ins: 0x32530001
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xc (andi)
+ i rs: 0x12 rt: 0x13 i: 0x1
+ r rs: 18 rt: 19 rd: 0 sh: 0 func: 0x1
+ V rs: 0x2 rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 0000000a 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc001dc m_jump_pc: 0xbfc001e0 m_ifetch_addr: 0xbfc001dc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x12600002>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc001dc NPC: 0xbfc001e0 Ins: 0x12600002
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0x13 rt: 0 i: 0x2
+ r rs: 19 rt: 0 rd: 0 sh: 0 func: 0x2
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 0000000a 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc001e0 m_jump_pc: 0xbfc001e8 m_ifetch_addr: 0xbfc001e0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc001e0 NPC: 0xbfc001e8 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 0000000a 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc001e8 m_jump_pc: 0xbfc001ec m_ifetch_addr: 0xbfc001e8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x26520001>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc001e8 NPC: 0xbfc001ec Ins: 0x26520001
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0x12 rt: 0x12 i: 0x1
+ r rs: 18 rt: 18 rd: 0 sh: 0 func: 0x1
+ V rs: 0x2 rt: 0x2
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 0000000a 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000002 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc001ec m_jump_pc: 0xbfc001f0 m_ifetch_addr: 0xbfc001ec
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x24130184>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc001ec NPC: 0xbfc001f0 Ins: 0x24130184
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0 rt: 0x13 i: 0x184
+ r rs: 0 rt: 19 rd: 0 sh: 6 func: 0x4
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 0000000a 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000003 19: 00000000 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc001f0 m_jump_pc: 0xbfc001f4 m_ifetch_addr: 0xbfc001f0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x12530008>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc001f0 NPC: 0xbfc001f4 Ins: 0x12530008
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0x12 rt: 0x13 i: 0x8
+ r rs: 18 rt: 19 rd: 0 sh: 0 func: 0x8
+ V rs: 0x3 rt: 0x184
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 0000000a 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000003 19: 00000184 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc001f4 m_jump_pc: 0xbfc001f8 m_ifetch_addr: 0xbfc001f4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x129842>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc001f4 NPC: 0xbfc001f8 Ins: 0x129842
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0x12 i: 0x9842
+ r rs: 0 rt: 18 rd: 19 sh: 1 func: 0x2
+ V rs: 0 rt: 0x3
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 0000000a 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000003 19: 00000184 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc001f8 m_jump_pc: 0xbfc001fc m_ifetch_addr: 0xbfc001f8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c08d820>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc001f8 NPC: 0xbfc001fc Ins: 0x3c08d820
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0x8 i: 0xd820
+ r rs: 0 rt: 8 rd: 27 sh: 0 func: 0x20
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 0000000a 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc001fc m_jump_pc: 0xbfc00200 m_ifetch_addr: 0xbfc001fc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xad130080>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc001fc NPC: 0xbfc00200 Ins: 0xad130080
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2b (sw)
+ i rs: 0x8 rt: 0x13 i: 0x80
+ r rs: 8 rt: 19 rd: 0 sh: 2 func: 0
+ V rs: 0xd8200000 rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 0000000a 05: 00000000 06: 00000000 07: 00000000
+ 08: d8200000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd8200080 wdata 0x1 be 0xf> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc00200 m_jump_pc: 0xbfc00204 m_ifetch_addr: 0xbfc00200
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x42000018>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc00200 NPC: 0xbfc00204 Ins: 0x42000018
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x10 (cop0)
+ i rs: 0x10 rt: 0 i: 0x18
+ r rs: 16 rt: 0 rd: 0 sh: 0 func: 0x18
+ V rs: 0xdea9 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 0000000a 05: 00000000 06: 00000000 07: 00000000
+ 08: d8200000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 ERET  exl jump_pc: bfc0007c
+mips0 m_next_pc: 0xbfc00078 m_jump_pc: 0xbfc0007c m_ifetch_addr: 0xbfc00078
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2610ffff>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00078 NPC: 0xbfc0007c Ins: 0x2610ffff
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 0 .erl: 0 .whole: 0x400401
+ op:  0x9 (addiu)
+ i rs: 0x10 rt: 0x10 i: 0xffff
+ r rs: 16 rt: 16 rd: 31 sh: 31 func: 0x3f
+ V rs: 0xdea9 rt: 0xdea9
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 0000000a 05: 00000000 06: 00000000 07: 00000000
+ 08: d8200000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea9 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc0007c m_jump_pc: 0xbfc00080 m_ifetch_addr: 0xbfc0007c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf00030>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0007c NPC: 0xbfc00080 Ins: 0xbf00030
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 0 .erl: 0 .whole: 0x400401
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0x30
+ r rs: 31 rt: 16 rd: 0 sh: 0 func: 0x30
+ V rs: 0xbfc001d0 rt: 0xdea8
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 0000000a 05: 00000000 06: 00000000 07: 00000000
+ 08: d8200000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea8 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00080 m_jump_pc: 0xbfc000c0 m_ifetch_addr: 0xbfc00080
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00080 m_jump_pc: 0xbfc000c0 m_ifetch_addr: 0xbfc00080
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00080 m_jump_pc: 0xbfc000c0 m_ifetch_addr: 0xbfc00080
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00080 m_jump_pc: 0xbfc000c0 m_ifetch_addr: 0xbfc00080
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00080 m_jump_pc: 0xbfc000c0 m_ifetch_addr: 0xbfc00080
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00080 m_jump_pc: 0xbfc000c0 m_ifetch_addr: 0xbfc00080
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00080 m_jump_pc: 0xbfc000c0 m_ifetch_addr: 0xbfc00080
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00080 m_jump_pc: 0xbfc000c0 m_ifetch_addr: 0xbfc00080
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00080 m_jump_pc: 0xbfc000c0 m_ifetch_addr: 0xbfc00080
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00080 m_jump_pc: 0xbfc000c0 m_ifetch_addr: 0xbfc00080
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00080 m_jump_pc: 0xbfc000c0 m_ifetch_addr: 0xbfc00080
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00080 m_jump_pc: 0xbfc000c0 m_ifetch_addr: 0xbfc00080
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00080 m_jump_pc: 0xbfc000c0 m_ifetch_addr: 0xbfc00080
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00080 m_jump_pc: 0xbfc000c0 m_ifetch_addr: 0xbfc00080
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00080 m_jump_pc: 0xbfc000c0 m_ifetch_addr: 0xbfc00080
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00080 m_jump_pc: 0xbfc000c0 m_ifetch_addr: 0xbfc00080
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00080 m_jump_pc: 0xbfc000c0 m_ifetch_addr: 0xbfc00080
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00080 m_jump_pc: 0xbfc000c0 m_ifetch_addr: 0xbfc00080
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00080 m_jump_pc: 0xbfc000c0 m_ifetch_addr: 0xbfc00080
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00080 m_jump_pc: 0xbfc000c0 m_ifetch_addr: 0xbfc00080
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00080 m_jump_pc: 0xbfc000c0 m_ifetch_addr: 0xbfc00080
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00080 m_jump_pc: 0xbfc000c0 m_ifetch_addr: 0xbfc00080
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00080 m_jump_pc: 0xbfc000c0 m_ifetch_addr: 0xbfc00080
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00080 m_jump_pc: 0xbfc000c0 m_ifetch_addr: 0xbfc00080
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00080 m_jump_pc: 0xbfc000c0 m_ifetch_addr: 0xbfc00080
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00080 m_jump_pc: 0xbfc000c0 m_ifetch_addr: 0xbfc00080
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00080 m_jump_pc: 0xbfc000c0 m_ifetch_addr: 0xbfc00080
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00080 m_jump_pc: 0xbfc000c0 m_ifetch_addr: 0xbfc00080
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc00080 m_jump_pc: 0xbfc000c0 m_ifetch_addr: 0xbfc00080
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x26100005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00080 NPC: 0xbfc000c0 Ins: 0x26100005
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 0 .erl: 0 .whole: 0x400401
+ op:  0x9 (addiu)
+ i rs: 0x10 rt: 0x10 i: 0x5
+ r rs: 16 rt: 16 rd: 0 sh: 0 func: 0x5
+ V rs: 0xdea8 rt: 0xdea8
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 0000000a 05: 00000000 06: 00000000 07: 00000000
+ 08: d8200000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dea8 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc000c0 m_jump_pc: 0xbfc000c4 m_ifetch_addr: 0xbfc000c0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc000c0 m_jump_pc: 0xbfc000c4 m_ifetch_addr: 0xbfc000c0
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc000c0 m_jump_pc: 0xbfc000c4 m_ifetch_addr: 0xbfc000c0
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc000c0 m_jump_pc: 0xbfc000c4 m_ifetch_addr: 0xbfc000c0
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 exception: 0
+ m_ins: 0x9 epc: 0xbfc000c0 error_epc: 0 bar: 0xd8200080 cause.xcode: 0 .bd: 0 .ip: 0x4 status.exl: 0x1 .erl: 0 exception address: 0xbfc00380
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  invalid no error ins 0>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380
+mips0 early_end: ireq_ok=0 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0004d>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 PC: 0xbfc00380 NPC: 0xbfc00384 Ins: 0xbf0004d
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0x4d
+ r rs: 31 rt: 16 rd: 0 sh: 1 func: 0xd
+ V rs: 0xbfc001d0 rt: 0xdead
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 0000000a 05: 00000000 06: 00000000 07: 00000000
+ 08: d8200000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dead 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00384 m_jump_pc: 0xbfc00134 m_ifetch_addr: 0xbfc00384
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 PC: 0xbfc00384 NPC: 0xbfc00134 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 0000000a 05: 00000000 06: 00000000 07: 00000000
+ 08: d8200000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dead 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00134 m_jump_pc: 0xbfc00138 m_ifetch_addr: 0xbfc00134
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2610ffff>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 PC: 0xbfc00134 NPC: 0xbfc00138 Ins: 0x2610ffff
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0x10 rt: 0x10 i: 0xffff
+ r rs: 16 rt: 16 rd: 31 sh: 31 func: 0x3f
+ V rs: 0xdead rt: 0xdead
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 0000000a 05: 00000000 06: 00000000 07: 00000000
+ 08: d8200000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dead 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00138 m_jump_pc: 0xbfc0013c m_ifetch_addr: 0xbfc00138
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c08d820>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 PC: 0xbfc00138 NPC: 0xbfc0013c Ins: 0x3c08d820
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0x8 i: 0xd820
+ r rs: 0 rt: 8 rd: 27 sh: 0 func: 0x20
+ V rs: 0 rt: 0xd8200000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 0000000a 05: 00000000 06: 00000000 07: 00000000
+ 08: d8200000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc0013c m_jump_pc: 0xbfc00140 m_ifetch_addr: 0xbfc0013c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xad000080>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 PC: 0xbfc0013c NPC: 0xbfc00140 Ins: 0xad000080
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2b (sw)
+ i rs: 0x8 rt: 0 i: 0x80
+ r rs: 8 rt: 0 rd: 0 sh: 2 func: 0
+ V rs: 0xd8200000 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 0000000a 05: 00000000 06: 00000000 07: 00000000
+ 08: d8200000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd8200080 wdata 0 be 0xf> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc00140 m_jump_pc: 0xbfc00144 m_ifetch_addr: 0xbfc00140
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c04bfc0>, <DataRsp valid no error rdata 0>, 0x1)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc00140 NPC: 0xbfc00144 Ins: 0x3c04bfc0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0x4 i: 0xbfc0
+ r rs: 0 rt: 4 rd: 23 sh: 31 func: 0
+ V rs: 0 rt: 0xa
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 0000000a 05: 00000000 06: 00000000 07: 00000000
+ 08: d8200000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00144 m_jump_pc: 0xbfc00148 m_ifetch_addr: 0xbfc00144
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x24840224>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 PC: 0xbfc00144 NPC: 0xbfc00148 Ins: 0x24840224
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0x4 rt: 0x4 i: 0x224
+ r rs: 4 rt: 4 rd: 0 sh: 8 func: 0x24
+ V rs: 0xbfc00000 rt: 0xbfc00000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00000 05: 00000000 06: 00000000 07: 00000000
+ 08: d8200000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00148 m_jump_pc: 0xbfc0014c m_ifetch_addr: 0xbfc00148
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xff000f0>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 PC: 0xbfc00148 NPC: 0xbfc0014c Ins: 0xff000f0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x3 (jal)
+ i rs: 0x1f rt: 0x10 i: 0xf0
+ r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x30
+ V rs: 0xbfc001d0 rt: 0xdeac
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: d8200000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc0014c m_jump_pc: 0xbfc003c0 m_ifetch_addr: 0xbfc0014c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 PC: 0xbfc0014c NPC: 0xbfc003c0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: d8200000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 m_next_pc: 0xbfc003c0 m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003c0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x804021>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 PC: 0xbfc003c0 NPC: 0xbfc003c4 Ins: 0x804021
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x4 rt: 0 i: 0x4021
+ r rs: 4 rt: 0 rd: 8 sh: 0 func: 0x21
+ V rs: 0xbfc00224 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: d8200000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x81090000>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x20 (lb)
+ i rs: 0x8 rt: 0x9 i: 0
+ r rs: 8 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xbfc00224 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00224 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_READ @ 0xbfc00224 wdata 0 be 0x1> off: 0 sign_ext: 0x1 dest: gp+0x9
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp valid no error rdata 0x74617473>, 0)
+mips0 setData: <DataRsp valid no error rdata 0x74617473> off: 0 sign_ext: 0x1 dest: r_gp+0x9
+mips0 setData: <DataRsp valid no error rdata 0x74617473> off: 0 count: 0x1 le: 0 old: 0 from_mem: 0x74617473 mask: 0xffffffff new_data: 0x73
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0x9 rt: 0 i: 0x5
+ r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5
+ V rs: 0x73 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00224 09: 00000073 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00224 09: 00000073 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa3490000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0x9 i: 0
+ r rs: 26 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x73
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00224 09: 00000073 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x73 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0x8 rt: 0x8 i: 0x1
+ r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1
+ V rs: 0xbfc00224 rt: 0xbfc00224
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00224 09: 00000073 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf000f1>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0xf1
+ r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31
+ V rs: 0xbfc00150 rt: 0xdeac
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00225 09: 00000073 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00225 09: 00000073 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x81090000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x20 (lb)
+ i rs: 0x8 rt: 0x9 i: 0
+ r rs: 8 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xbfc00225 rt: 0x73
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00225 09: 00000073 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_READ @ 0xbfc00224 wdata 0 be 0x2> off: 0x1 sign_ext: 0x1 dest: gp+0x9
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp valid no error rdata 0x74617473>, 0)
+mips0 setData: <DataRsp valid no error rdata 0x74617473> off: 0 sign_ext: 0x1 dest: r_gp+0x9
+mips0 setData: <DataRsp valid no error rdata 0x74617473> off: 0 count: 0x1 le: 0x1 old: 0x73 from_mem: 0x74617473 mask: 0xffffffff new_data: 0x74
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1
+smips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0x9 rt: 0 i: 0x5
+ r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5
+ V rs: 0x74 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00225 09: 00000074 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00225 09: 00000074 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa3490000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0x9 i: 0
+ r rs: 26 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x74
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00225 09: 00000074 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x74 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0x8 rt: 0x8 i: 0x1
+ r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1
+ V rs: 0xbfc00225 rt: 0xbfc00225
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00225 09: 00000074 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf000f1>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0xf1
+ r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31
+ V rs: 0xbfc00150 rt: 0xdeac
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00226 09: 00000074 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00226 09: 00000074 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x81090000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x20 (lb)
+ i rs: 0x8 rt: 0x9 i: 0
+ r rs: 8 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xbfc00226 rt: 0x74
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00226 09: 00000074 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_READ @ 0xbfc00224 wdata 0 be 0x4> off: 0x2 sign_ext: 0x1 dest: gp+0x9
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp valid no error rdata 0x74617473>, 0)
+mips0 setData: <DataRsp valid no error rdata 0x74617473> off: 0 sign_ext: 0x1 dest: r_gp+0x9
+mips0 setData: <DataRsp valid no error rdata 0x74617473> off: 0 count: 0x1 le: 0x2 old: 0x74 from_mem: 0x74617473 mask: 0xffffffff new_data: 0x61
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0x9 rt: 0 i: 0x5
+ r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5
+ V rs: 0x61 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00226 09: 00000061 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+tmips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00226 09: 00000061 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa3490000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0x9 i: 0
+ r rs: 26 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x61
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00226 09: 00000061 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x61 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0x8 rt: 0x8 i: 0x1
+ r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1
+ V rs: 0xbfc00226 rt: 0xbfc00226
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00226 09: 00000061 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf000f1>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0xf1
+ r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31
+ V rs: 0xbfc00150 rt: 0xdeac
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00227 09: 00000061 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00227 09: 00000061 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x81090000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x20 (lb)
+ i rs: 0x8 rt: 0x9 i: 0
+ r rs: 8 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xbfc00227 rt: 0x61
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00227 09: 00000061 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_READ @ 0xbfc00224 wdata 0 be 0x8> off: 0x3 sign_ext: 0x1 dest: gp+0x9
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp valid no error rdata 0x74617473>, 0)
+mips0 setData: <DataRsp valid no error rdata 0x74617473> off: 0 sign_ext: 0x1 dest: r_gp+0x9
+mips0 setData: <DataRsp valid no error rdata 0x74617473> off: 0 count: 0x1 le: 0x3 old: 0x61 from_mem: 0x74617473 mask: 0xffffffff new_data: 0x74
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0x9 rt: 0 i: 0x5
+ r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5
+ V rs: 0x74 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00227 09: 00000074 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00227 09: 00000074 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+amips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa3490000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0x9 i: 0
+ r rs: 26 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x74
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00227 09: 00000074 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x74 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0x8 rt: 0x8 i: 0x1
+ r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1
+ V rs: 0xbfc00227 rt: 0xbfc00227
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00227 09: 00000074 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf000f1>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0xf1
+ r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31
+ V rs: 0xbfc00150 rt: 0xdeac
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00228 09: 00000074 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00228 09: 00000074 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x81090000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x20 (lb)
+ i rs: 0x8 rt: 0x9 i: 0
+ r rs: 8 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xbfc00228 rt: 0x74
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00228 09: 00000074 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_READ @ 0xbfc00228 wdata 0 be 0x1> off: 0 sign_ext: 0x1 dest: gp+0x9
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp valid no error rdata 0x207375>, 0)
+mips0 setData: <DataRsp valid no error rdata 0x207375> off: 0 sign_ext: 0x1 dest: r_gp+0x9
+mips0 setData: <DataRsp valid no error rdata 0x207375> off: 0 count: 0x1 le: 0 old: 0x74 from_mem: 0x207375 mask: 0xffffffff new_data: 0x75
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0x9 rt: 0 i: 0x5
+ r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5
+ V rs: 0x75 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00228 09: 00000075 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00228 09: 00000075 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa3490000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0x9 i: 0
+ r rs: 26 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x75
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00228 09: 00000075 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x75 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+tmips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0x8 rt: 0x8 i: 0x1
+ r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1
+ V rs: 0xbfc00228 rt: 0xbfc00228
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00228 09: 00000075 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf000f1>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0xf1
+ r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31
+ V rs: 0xbfc00150 rt: 0xdeac
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00229 09: 00000075 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00229 09: 00000075 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x81090000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x20 (lb)
+ i rs: 0x8 rt: 0x9 i: 0
+ r rs: 8 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xbfc00229 rt: 0x75
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00229 09: 00000075 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_READ @ 0xbfc00228 wdata 0 be 0x2> off: 0x1 sign_ext: 0x1 dest: gp+0x9
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp valid no error rdata 0x207375>, 0)
+mips0 setData: <DataRsp valid no error rdata 0x207375> off: 0 sign_ext: 0x1 dest: r_gp+0x9
+mips0 setData: <DataRsp valid no error rdata 0x207375> off: 0 count: 0x1 le: 0x1 old: 0x75 from_mem: 0x207375 mask: 0xffffffff new_data: 0x73
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0x9 rt: 0 i: 0x5
+ r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5
+ V rs: 0x73 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00229 09: 00000073 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00229 09: 00000073 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa3490000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0x9 i: 0
+ r rs: 26 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x73
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00229 09: 00000073 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x73 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+umips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0x8 rt: 0x8 i: 0x1
+ r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1
+ V rs: 0xbfc00229 rt: 0xbfc00229
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00229 09: 00000073 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf000f1>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0xf1
+ r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31
+ V rs: 0xbfc00150 rt: 0xdeac
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0022a 09: 00000073 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0022a 09: 00000073 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x81090000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x20 (lb)
+ i rs: 0x8 rt: 0x9 i: 0
+ r rs: 8 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xbfc0022a rt: 0x73
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0022a 09: 00000073 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_READ @ 0xbfc00228 wdata 0 be 0x4> off: 0x2 sign_ext: 0x1 dest: gp+0x9
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp valid no error rdata 0x207375>, 0)
+mips0 setData: <DataRsp valid no error rdata 0x207375> off: 0 sign_ext: 0x1 dest: r_gp+0x9
+mips0 setData: <DataRsp valid no error rdata 0x207375> off: 0 count: 0x1 le: 0x2 old: 0x73 from_mem: 0x207375 mask: 0xffffffff new_data: 0x20
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0x9 rt: 0 i: 0x5
+ r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5
+ V rs: 0x20 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0022a 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0022a 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa3490000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0x9 i: 0
+ r rs: 26 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x20
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0022a 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x20 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+smips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0x8 rt: 0x8 i: 0x1
+ r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1
+ V rs: 0xbfc0022a rt: 0xbfc0022a
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0022a 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf000f1>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0xf1
+ r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31
+ V rs: 0xbfc00150 rt: 0xdeac
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0022b 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0022b 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x81090000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x20 (lb)
+ i rs: 0x8 rt: 0x9 i: 0
+ r rs: 8 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xbfc0022b rt: 0x20
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0022b 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_READ @ 0xbfc00228 wdata 0 be 0x8> off: 0x3 sign_ext: 0x1 dest: gp+0x9
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp valid no error rdata 0x207375>, 0)
+mips0 setData: <DataRsp valid no error rdata 0x207375> off: 0 sign_ext: 0x1 dest: r_gp+0x9
+mips0 setData: <DataRsp valid no error rdata 0x207375> off: 0 count: 0x1 le: 0x3 old: 0x20 from_mem: 0x207375 mask: 0xffffffff new_data: 0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0x9 rt: 0 i: 0x5
+ r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0022b 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003e0 m_ifetch_addr: 0xbfc003cc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003cc NPC: 0xbfc003e0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0022b 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 m_next_pc: 0xbfc003e0 m_jump_pc: 0xbfc003e4 m_ifetch_addr: 0xbfc003e0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3e00008>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003e0 NPC: 0xbfc003e4 Ins: 0x3e00008
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x1f rt: 0 i: 0x8
+ r rs: 31 rt: 0 rd: 0 sh: 0 func: 0x8
+ V rs: 0xbfc00150 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0022b 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 m_next_pc: 0xbfc003e4 m_jump_pc: 0xbfc00150 m_ifetch_addr: 0xbfc003e4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+ mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003e4 NPC: 0xbfc00150 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0022b 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 m_next_pc: 0xbfc00150 m_jump_pc: 0xbfc00154 m_ifetch_addr: 0xbfc00150
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x40046000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00150 NPC: 0xbfc00154 Ins: 0x40046000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x10 (cop0)
+ i rs: 0 rt: 0x4 i: 0x6000
+ r rs: 0 rt: 4 rd: 12 sh: 0 func: 0
+ V rs: 0 rt: 0xbfc00224
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00224 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0022b 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 m_next_pc: 0xbfc00154 m_jump_pc: 0xbfc00158 m_ifetch_addr: 0xbfc00154
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xff000fa>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00154 NPC: 0xbfc00158 Ins: 0xff000fa
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x3 (jal)
+ i rs: 0x1f rt: 0x10 i: 0xfa
+ r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x3a
+ V rs: 0xbfc00150 rt: 0xdeac
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0022b 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00150
+mips0 m_next_pc: 0xbfc00158 m_jump_pc: 0xbfc003e8 m_ifetch_addr: 0xbfc00158
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00158 NPC: 0xbfc003e8 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0022b 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc003e8 m_jump_pc: 0xbfc003ec m_ifetch_addr: 0xbfc003e8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x804021>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003e8 NPC: 0xbfc003ec Ins: 0x804021
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x4 rt: 0 i: 0x4021
+ r rs: 4 rt: 0 rd: 8 sh: 0 func: 0x21
+ V rs: 0x400403 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0022b 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc003ec m_jump_pc: 0xbfc003f0 m_ifetch_addr: 0xbfc003ec
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x24090030>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003ec NPC: 0xbfc003f0 Ins: 0x24090030
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0 rt: 0x9 i: 0x30
+ r rs: 0 rt: 9 rd: 0 sh: 0 func: 0x30
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 00400403 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc003f0 m_jump_pc: 0xbfc003f4 m_ifetch_addr: 0xbfc003f0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa3490000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003f0 NPC: 0xbfc003f4 Ins: 0xa3490000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0x9 i: 0
+ r rs: 26 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 00400403 09: 00000030 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc003f4 m_jump_pc: 0xbfc003f8 m_ifetch_addr: 0xbfc003f4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x24090078>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc003f4 NPC: 0xbfc003f8 Ins: 0x24090078
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0 rt: 0x9 i: 0x78
+ r rs: 0 rt: 9 rd: 0 sh: 1 func: 0x38
+ V rs: 0 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 00400403 09: 00000030 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc003f8 m_jump_pc: 0xbfc003fc m_ifetch_addr: 0xbfc003f8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa3490000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003f8 NPC: 0xbfc003fc Ins: 0xa3490000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0x9 i: 0
+ r rs: 26 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x78
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 00400403 09: 00000078 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x78 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc003fc m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc003fc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x24090008>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc003fc NPC: 0xbfc00400 Ins: 0x24090008
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0 rt: 0x9 i: 0x8
+ r rs: 0 rt: 9 rd: 0 sh: 0 func: 0x8
+ V rs: 0 rt: 0x78
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 00400403 09: 00000078 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c0af000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0xa i: 0xf000
+ r rs: 0 rt: 10 rd: 30 sh: 0 func: 0
+ V rs: 0 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 00400403 09: 00000008 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x10a5024>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x8 rt: 0xa i: 0x5024
+ r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24
+ V rs: 0x400403 rt: 0xf0000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 00400403 09: 00000008 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa5702>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0xa i: 0x5702
+ r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 00400403 09: 00000008 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+0mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x294b000a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xa (slti)
+ i rs: 0xa rt: 0xb i: 0xa
+ r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa
+ V rs: 0 rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 00400403 09: 00000008 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11600004>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0xb rt: 0 i: 0x4
+ r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4
+ V rs: 0x1 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 00400403 09: 00000008 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 00400403 09: 00000008 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x214a0030>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0xa rt: 0xa i: 0x30
+ r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 00400403 09: 00000008 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0010a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0x10a
+ r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa
+ V rs: 0xbfc0015c rt: 0xdeac
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 00400403 09: 00000008 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 00400403 09: 00000008 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa34a0000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0xa i: 0
+ r rs: 26 rt: 10 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 00400403 09: 00000008 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2129ffff>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0x9 rt: 0x9 i: 0xffff
+ r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f
+ V rs: 0x8 rt: 0x8
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 00400403 09: 00000008 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x1d20fff3>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x7 (bgtz)
+ i rs: 0x9 rt: 0 i: 0xfff3
+ r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33
+ V rs: 0x7 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 00400403 09: 00000007 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x84100>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0x8 i: 0x4100
+ r rs: 0 rt: 8 rd: 8 sh: 4 func: 0
+ V rs: 0 rt: 0x400403
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 00400403 09: 00000007 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+xmips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c0af000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0xa i: 0xf000
+ r rs: 0 rt: 10 rd: 30 sh: 0 func: 0
+ V rs: 0 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 04004030 09: 00000007 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x10a5024>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x8 rt: 0xa i: 0x5024
+ r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24
+ V rs: 0x4004030 rt: 0xf0000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 04004030 09: 00000007 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa5702>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0xa i: 0x5702
+ r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 04004030 09: 00000007 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x294b000a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xa (slti)
+ i rs: 0xa rt: 0xb i: 0xa
+ r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa
+ V rs: 0 rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 04004030 09: 00000007 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11600004>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0xb rt: 0 i: 0x4
+ r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4
+ V rs: 0x1 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 04004030 09: 00000007 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 04004030 09: 00000007 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x214a0030>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0xa rt: 0xa i: 0x30
+ r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 04004030 09: 00000007 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0010a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0x10a
+ r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa
+ V rs: 0xbfc0015c rt: 0xdeac
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 04004030 09: 00000007 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 04004030 09: 00000007 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa34a0000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0xa i: 0
+ r rs: 26 rt: 10 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 04004030 09: 00000007 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+0mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2129ffff>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0x9 rt: 0x9 i: 0xffff
+ r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f
+ V rs: 0x7 rt: 0x7
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 04004030 09: 00000007 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x1d20fff3>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x7 (bgtz)
+ i rs: 0x9 rt: 0 i: 0xfff3
+ r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33
+ V rs: 0x6 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 04004030 09: 00000006 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x84100>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0x8 i: 0x4100
+ r rs: 0 rt: 8 rd: 8 sh: 4 func: 0
+ V rs: 0 rt: 0x4004030
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 04004030 09: 00000006 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c0af000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0xa i: 0xf000
+ r rs: 0 rt: 10 rd: 30 sh: 0 func: 0
+ V rs: 0 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 40040300 09: 00000006 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x10a5024>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x8 rt: 0xa i: 0x5024
+ r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24
+ V rs: 0x40040300 rt: 0xf0000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 40040300 09: 00000006 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa5702>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0xa i: 0x5702
+ r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2
+ V rs: 0 rt: 0x40000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 40040300 09: 00000006 10: 40000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x294b000a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xa (slti)
+ i rs: 0xa rt: 0xb i: 0xa
+ r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa
+ V rs: 0x4 rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 40040300 09: 00000006 10: 00000004 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11600004>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0xb rt: 0 i: 0x4
+ r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4
+ V rs: 0x1 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 40040300 09: 00000006 10: 00000004 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 40040300 09: 00000006 10: 00000004 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x214a0030>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0xa rt: 0xa i: 0x30
+ r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30
+ V rs: 0x4 rt: 0x4
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 40040300 09: 00000006 10: 00000004 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+0mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0010a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0x10a
+ r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa
+ V rs: 0xbfc0015c rt: 0xdeac
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 40040300 09: 00000006 10: 00000034 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 40040300 09: 00000006 10: 00000034 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa34a0000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0xa i: 0
+ r rs: 26 rt: 10 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x34
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 40040300 09: 00000006 10: 00000034 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x34 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2129ffff>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0x9 rt: 0x9 i: 0xffff
+ r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f
+ V rs: 0x6 rt: 0x6
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 40040300 09: 00000006 10: 00000034 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x1d20fff3>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x7 (bgtz)
+ i rs: 0x9 rt: 0 i: 0xfff3
+ r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33
+ V rs: 0x5 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 40040300 09: 00000005 10: 00000034 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x84100>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0x8 i: 0x4100
+ r rs: 0 rt: 8 rd: 8 sh: 4 func: 0
+ V rs: 0 rt: 0x40040300
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 40040300 09: 00000005 10: 00000034 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c0af000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0xa i: 0xf000
+ r rs: 0 rt: 10 rd: 30 sh: 0 func: 0
+ V rs: 0 rt: 0x34
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 00403000 09: 00000005 10: 00000034 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x10a5024>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x8 rt: 0xa i: 0x5024
+ r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24
+ V rs: 0x403000 rt: 0xf0000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 00403000 09: 00000005 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa5702>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0xa i: 0x5702
+ r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 00403000 09: 00000005 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x294b000a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xa (slti)
+ i rs: 0xa rt: 0xb i: 0xa
+ r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa
+ V rs: 0 rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 00403000 09: 00000005 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+4mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11600004>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0xb rt: 0 i: 0x4
+ r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4
+ V rs: 0x1 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 00403000 09: 00000005 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 00403000 09: 00000005 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x214a0030>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0xa rt: 0xa i: 0x30
+ r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 00403000 09: 00000005 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0010a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0x10a
+ r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa
+ V rs: 0xbfc0015c rt: 0xdeac
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 00403000 09: 00000005 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 00403000 09: 00000005 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa34a0000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0xa i: 0
+ r rs: 26 rt: 10 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 00403000 09: 00000005 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2129ffff>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0x9 rt: 0x9 i: 0xffff
+ r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f
+ V rs: 0x5 rt: 0x5
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 00403000 09: 00000005 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x1d20fff3>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x7 (bgtz)
+ i rs: 0x9 rt: 0 i: 0xfff3
+ r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33
+ V rs: 0x4 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 00403000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x84100>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0x8 i: 0x4100
+ r rs: 0 rt: 8 rd: 8 sh: 4 func: 0
+ V rs: 0 rt: 0x403000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 00403000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c0af000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0xa i: 0xf000
+ r rs: 0 rt: 10 rd: 30 sh: 0 func: 0
+ V rs: 0 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 04030000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x10a5024>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x8 rt: 0xa i: 0x5024
+ r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24
+ V rs: 0x4030000 rt: 0xf0000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 04030000 09: 00000004 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa5702>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0xa i: 0x5702
+ r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 04030000 09: 00000004 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+0mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x294b000a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xa (slti)
+ i rs: 0xa rt: 0xb i: 0xa
+ r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa
+ V rs: 0 rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 04030000 09: 00000004 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11600004>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0xb rt: 0 i: 0x4
+ r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4
+ V rs: 0x1 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 04030000 09: 00000004 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 04030000 09: 00000004 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x214a0030>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0xa rt: 0xa i: 0x30
+ r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 04030000 09: 00000004 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0010a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0x10a
+ r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa
+ V rs: 0xbfc0015c rt: 0xdeac
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 04030000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 04030000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa34a0000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0xa i: 0
+ r rs: 26 rt: 10 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 04030000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2129ffff>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0x9 rt: 0x9 i: 0xffff
+ r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f
+ V rs: 0x4 rt: 0x4
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 04030000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x1d20fff3>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x7 (bgtz)
+ i rs: 0x9 rt: 0 i: 0xfff3
+ r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33
+ V rs: 0x3 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 04030000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x84100>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0x8 i: 0x4100
+ r rs: 0 rt: 8 rd: 8 sh: 4 func: 0
+ V rs: 0 rt: 0x4030000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 04030000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c0af000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0xa i: 0xf000
+ r rs: 0 rt: 10 rd: 30 sh: 0 func: 0
+ V rs: 0 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 40300000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x10a5024>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x8 rt: 0xa i: 0x5024
+ r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24
+ V rs: 0x40300000 rt: 0xf0000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 40300000 09: 00000003 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa5702>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0xa i: 0x5702
+ r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2
+ V rs: 0 rt: 0x40000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 40300000 09: 00000003 10: 40000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+0mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x294b000a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xa (slti)
+ i rs: 0xa rt: 0xb i: 0xa
+ r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa
+ V rs: 0x4 rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 40300000 09: 00000003 10: 00000004 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11600004>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0xb rt: 0 i: 0x4
+ r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4
+ V rs: 0x1 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 40300000 09: 00000003 10: 00000004 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 40300000 09: 00000003 10: 00000004 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x214a0030>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0xa rt: 0xa i: 0x30
+ r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30
+ V rs: 0x4 rt: 0x4
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 40300000 09: 00000003 10: 00000004 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0010a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0x10a
+ r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa
+ V rs: 0xbfc0015c rt: 0xdeac
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 40300000 09: 00000003 10: 00000034 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 40300000 09: 00000003 10: 00000034 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa34a0000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0xa i: 0
+ r rs: 26 rt: 10 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x34
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 40300000 09: 00000003 10: 00000034 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x34 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2129ffff>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0x9 rt: 0x9 i: 0xffff
+ r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f
+ V rs: 0x3 rt: 0x3
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 40300000 09: 00000003 10: 00000034 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x1d20fff3>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x7 (bgtz)
+ i rs: 0x9 rt: 0 i: 0xfff3
+ r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33
+ V rs: 0x2 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 40300000 09: 00000002 10: 00000034 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x84100>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0x8 i: 0x4100
+ r rs: 0 rt: 8 rd: 8 sh: 4 func: 0
+ V rs: 0 rt: 0x40300000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 40300000 09: 00000002 10: 00000034 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c0af000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0xa i: 0xf000
+ r rs: 0 rt: 10 rd: 30 sh: 0 func: 0
+ V rs: 0 rt: 0x34
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 03000000 09: 00000002 10: 00000034 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x10a5024>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x8 rt: 0xa i: 0x5024
+ r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24
+ V rs: 0x3000000 rt: 0xf0000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 03000000 09: 00000002 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa5702>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0xa i: 0x5702
+ r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 03000000 09: 00000002 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+4mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x294b000a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xa (slti)
+ i rs: 0xa rt: 0xb i: 0xa
+ r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa
+ V rs: 0 rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 03000000 09: 00000002 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11600004>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0xb rt: 0 i: 0x4
+ r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4
+ V rs: 0x1 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 03000000 09: 00000002 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 03000000 09: 00000002 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x214a0030>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0xa rt: 0xa i: 0x30
+ r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 03000000 09: 00000002 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0010a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0x10a
+ r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa
+ V rs: 0xbfc0015c rt: 0xdeac
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 03000000 09: 00000002 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 03000000 09: 00000002 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa34a0000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0xa i: 0
+ r rs: 26 rt: 10 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 03000000 09: 00000002 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2129ffff>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0x9 rt: 0x9 i: 0xffff
+ r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f
+ V rs: 0x2 rt: 0x2
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 03000000 09: 00000002 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x1d20fff3>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x7 (bgtz)
+ i rs: 0x9 rt: 0 i: 0xfff3
+ r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33
+ V rs: 0x1 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 03000000 09: 00000001 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x84100>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0x8 i: 0x4100
+ r rs: 0 rt: 8 rd: 8 sh: 4 func: 0
+ V rs: 0 rt: 0x3000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 03000000 09: 00000001 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c0af000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0xa i: 0xf000
+ r rs: 0 rt: 10 rd: 30 sh: 0 func: 0
+ V rs: 0 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 30000000 09: 00000001 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x10a5024>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x8 rt: 0xa i: 0x5024
+ r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24
+ V rs: 0x30000000 rt: 0xf0000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 30000000 09: 00000001 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa5702>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0xa i: 0x5702
+ r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2
+ V rs: 0 rt: 0x30000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 30000000 09: 00000001 10: 30000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+0mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x294b000a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xa (slti)
+ i rs: 0xa rt: 0xb i: 0xa
+ r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa
+ V rs: 0x3 rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 30000000 09: 00000001 10: 00000003 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11600004>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0xb rt: 0 i: 0x4
+ r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4
+ V rs: 0x1 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 30000000 09: 00000001 10: 00000003 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 30000000 09: 00000001 10: 00000003 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x214a0030>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0xa rt: 0xa i: 0x30
+ r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30
+ V rs: 0x3 rt: 0x3
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 30000000 09: 00000001 10: 00000003 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0010a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0x10a
+ r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa
+ V rs: 0xbfc0015c rt: 0xdeac
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 30000000 09: 00000001 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 30000000 09: 00000001 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa34a0000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0xa i: 0
+ r rs: 26 rt: 10 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x33
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 30000000 09: 00000001 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x33 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2129ffff>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0x9 rt: 0x9 i: 0xffff
+ r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f
+ V rs: 0x1 rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 30000000 09: 00000001 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x1d20fff3>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x7 (bgtz)
+ i rs: 0x9 rt: 0 i: 0xfff3
+ r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 30000000 09: 00000000 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00438 m_ifetch_addr: 0xbfc00434
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x84100>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00434 NPC: 0xbfc00438 Ins: 0x84100
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0x8 i: 0x4100
+ r rs: 0 rt: 8 rd: 8 sh: 4 func: 0
+ V rs: 0 rt: 0x30000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 30000000 09: 00000000 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00438 m_jump_pc: 0xbfc0043c m_ifetch_addr: 0xbfc00438
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3e00008>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00438 NPC: 0xbfc0043c Ins: 0x3e00008
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x1f rt: 0 i: 0x8
+ r rs: 31 rt: 0 rd: 0 sh: 0 func: 0x8
+ V rs: 0xbfc0015c rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc0043c m_jump_pc: 0xbfc0015c m_ifetch_addr: 0xbfc0043c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0043c NPC: 0xbfc0015c Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc0015c m_jump_pc: 0xbfc00160 m_ifetch_addr: 0xbfc0015c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c04bfc0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0015c NPC: 0xbfc00160 Ins: 0x3c04bfc0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0x4 i: 0xbfc0
+ r rs: 0 rt: 4 rd: 23 sh: 31 func: 0
+ V rs: 0 rt: 0x400403
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00400403 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00160 m_jump_pc: 0xbfc00164 m_ifetch_addr: 0xbfc00160
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+3mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x24840234>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00160 NPC: 0xbfc00164 Ins: 0x24840234
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0x4 rt: 0x4 i: 0x234
+ r rs: 4 rt: 4 rd: 0 sh: 8 func: 0x34
+ V rs: 0xbfc00000 rt: 0xbfc00000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00164 m_jump_pc: 0xbfc00168 m_ifetch_addr: 0xbfc00164
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xff000f0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00164 NPC: 0xbfc00168 Ins: 0xff000f0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x3 (jal)
+ i rs: 0x1f rt: 0x10 i: 0xf0
+ r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x30
+ V rs: 0xbfc0015c rt: 0xdeac
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0015c
+mips0 m_next_pc: 0xbfc00168 m_jump_pc: 0xbfc003c0 m_ifetch_addr: 0xbfc00168
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00168 NPC: 0xbfc003c0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c
+mips0 m_next_pc: 0xbfc003c0 m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003c0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x804021>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c0 NPC: 0xbfc003c4 Ins: 0x804021
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x4 rt: 0 i: 0x4021
+ r rs: 4 rt: 0 rd: 8 sh: 0 func: 0x21
+ V rs: 0xbfc00234 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c
+mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x81090000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x20 (lb)
+ i rs: 0x8 rt: 0x9 i: 0
+ r rs: 8 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xbfc00234 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00234 09: 00000000 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_READ @ 0xbfc00234 wdata 0 be 0x1> off: 0 sign_ext: 0x1 dest: gp+0x9
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp valid no error rdata 0x20637020>, 0)
+mips0 setData: <DataRsp valid no error rdata 0x20637020> off: 0 sign_ext: 0x1 dest: r_gp+0x9
+mips0 setData: <DataRsp valid no error rdata 0x20637020> off: 0 count: 0x1 le: 0 old: 0 from_mem: 0x20637020 mask: 0xffffffff new_data: 0x20
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0x9 rt: 0 i: 0x5
+ r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5
+ V rs: 0x20 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00234 09: 00000020 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c
+mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00234 09: 00000020 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c
+mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa3490000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0x9 i: 0
+ r rs: 26 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x20
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00234 09: 00000020 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x20 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0x8 rt: 0x8 i: 0x1
+ r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1
+ V rs: 0xbfc00234 rt: 0xbfc00234
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00234 09: 00000020 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c
+mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf000f1>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0xf1
+ r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31
+ V rs: 0xbfc0016c rt: 0xdeac
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00235 09: 00000020 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c
+mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00235 09: 00000020 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c
+mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x81090000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x20 (lb)
+ i rs: 0x8 rt: 0x9 i: 0
+ r rs: 8 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xbfc00235 rt: 0x20
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00235 09: 00000020 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_READ @ 0xbfc00234 wdata 0 be 0x2> off: 0x1 sign_ext: 0x1 dest: gp+0x9
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp valid no error rdata 0x20637020>, 0)
+mips0 setData: <DataRsp valid no error rdata 0x20637020> off: 0 sign_ext: 0x1 dest: r_gp+0x9
+mips0 setData: <DataRsp valid no error rdata 0x20637020> off: 0 count: 0x1 le: 0x1 old: 0x20 from_mem: 0x20637020 mask: 0xffffffff new_data: 0x70
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1
+ mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0x9 rt: 0 i: 0x5
+ r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5
+ V rs: 0x70 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00235 09: 00000070 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c
+mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00235 09: 00000070 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c
+mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa3490000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0x9 i: 0
+ r rs: 26 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x70
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00235 09: 00000070 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x70 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0x8 rt: 0x8 i: 0x1
+ r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1
+ V rs: 0xbfc00235 rt: 0xbfc00235
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00235 09: 00000070 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c
+mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf000f1>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0xf1
+ r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31
+ V rs: 0xbfc0016c rt: 0xdeac
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00236 09: 00000070 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c
+mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00236 09: 00000070 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c
+mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x81090000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x20 (lb)
+ i rs: 0x8 rt: 0x9 i: 0
+ r rs: 8 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xbfc00236 rt: 0x70
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00236 09: 00000070 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_READ @ 0xbfc00234 wdata 0 be 0x4> off: 0x2 sign_ext: 0x1 dest: gp+0x9
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp valid no error rdata 0x20637020>, 0)
+mips0 setData: <DataRsp valid no error rdata 0x20637020> off: 0 sign_ext: 0x1 dest: r_gp+0x9
+mips0 setData: <DataRsp valid no error rdata 0x20637020> off: 0 count: 0x1 le: 0x2 old: 0x70 from_mem: 0x20637020 mask: 0xffffffff new_data: 0x63
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0x9 rt: 0 i: 0x5
+ r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5
+ V rs: 0x63 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00236 09: 00000063 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c
+mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+pmips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00236 09: 00000063 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c
+mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa3490000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0x9 i: 0
+ r rs: 26 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x63
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00236 09: 00000063 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x63 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0x8 rt: 0x8 i: 0x1
+ r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1
+ V rs: 0xbfc00236 rt: 0xbfc00236
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00236 09: 00000063 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c
+mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf000f1>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0xf1
+ r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31
+ V rs: 0xbfc0016c rt: 0xdeac
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00237 09: 00000063 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c
+mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00237 09: 00000063 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c
+mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x81090000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x20 (lb)
+ i rs: 0x8 rt: 0x9 i: 0
+ r rs: 8 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xbfc00237 rt: 0x63
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00237 09: 00000063 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_READ @ 0xbfc00234 wdata 0 be 0x8> off: 0x3 sign_ext: 0x1 dest: gp+0x9
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp valid no error rdata 0x20637020>, 0)
+mips0 setData: <DataRsp valid no error rdata 0x20637020> off: 0 sign_ext: 0x1 dest: r_gp+0x9
+mips0 setData: <DataRsp valid no error rdata 0x20637020> off: 0 count: 0x1 le: 0x3 old: 0x63 from_mem: 0x20637020 mask: 0xffffffff new_data: 0x20
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0x9 rt: 0 i: 0x5
+ r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5
+ V rs: 0x20 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00237 09: 00000020 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c
+mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00237 09: 00000020 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c
+mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+cmips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa3490000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0x9 i: 0
+ r rs: 26 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x20
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00237 09: 00000020 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x20 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0x8 rt: 0x8 i: 0x1
+ r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1
+ V rs: 0xbfc00237 rt: 0xbfc00237
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00237 09: 00000020 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c
+mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf000f1>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0xf1
+ r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31
+ V rs: 0xbfc0016c rt: 0xdeac
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00238 09: 00000020 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c
+mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00238 09: 00000020 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c
+mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x81090000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x20 (lb)
+ i rs: 0x8 rt: 0x9 i: 0
+ r rs: 8 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xbfc00238 rt: 0x20
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00238 09: 00000020 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_READ @ 0xbfc00238 wdata 0 be 0x1> off: 0 sign_ext: 0x1 dest: gp+0x9
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp valid no error rdata 0x61622000>, 0)
+mips0 setData: <DataRsp valid no error rdata 0x61622000> off: 0 sign_ext: 0x1 dest: r_gp+0x9
+mips0 setData: <DataRsp valid no error rdata 0x61622000> off: 0 count: 0x1 le: 0 old: 0x20 from_mem: 0x61622000 mask: 0xffffffff new_data: 0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0x9 rt: 0 i: 0x5
+ r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00238 09: 00000000 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c
+mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003e0 m_ifetch_addr: 0xbfc003cc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003cc NPC: 0xbfc003e0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00238 09: 00000000 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c
+mips0 m_next_pc: 0xbfc003e0 m_jump_pc: 0xbfc003e4 m_ifetch_addr: 0xbfc003e0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3e00008>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003e0 NPC: 0xbfc003e4 Ins: 0x3e00008
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x1f rt: 0 i: 0x8
+ r rs: 31 rt: 0 rd: 0 sh: 0 func: 0x8
+ V rs: 0xbfc0016c rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00238 09: 00000000 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c
+mips0 m_next_pc: 0xbfc003e4 m_jump_pc: 0xbfc0016c m_ifetch_addr: 0xbfc003e4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+ mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003e4 NPC: 0xbfc0016c Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00238 09: 00000000 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c
+mips0 m_next_pc: 0xbfc0016c m_jump_pc: 0xbfc00170 m_ifetch_addr: 0xbfc0016c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x40047000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0016c NPC: 0xbfc00170 Ins: 0x40047000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x10 (cop0)
+ i rs: 0 rt: 0x4 i: 0x7000
+ r rs: 0 rt: 4 rd: 14 sh: 0 func: 0
+ V rs: 0 rt: 0xbfc00234
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00234 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00238 09: 00000000 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c
+mips0 m_next_pc: 0xbfc00170 m_jump_pc: 0xbfc00174 m_ifetch_addr: 0xbfc00170
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xff000fa>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00170 NPC: 0xbfc00174 Ins: 0xff000fa
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x3 (jal)
+ i rs: 0x1f rt: 0x10 i: 0xfa
+ r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x3a
+ V rs: 0xbfc0016c rt: 0xdeac
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00238 09: 00000000 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc0016c
+mips0 m_next_pc: 0xbfc00174 m_jump_pc: 0xbfc003e8 m_ifetch_addr: 0xbfc00174
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00174 NPC: 0xbfc003e8 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00238 09: 00000000 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc003e8 m_jump_pc: 0xbfc003ec m_ifetch_addr: 0xbfc003e8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x804021>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003e8 NPC: 0xbfc003ec Ins: 0x804021
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x4 rt: 0 i: 0x4021
+ r rs: 4 rt: 0 rd: 8 sh: 0 func: 0x21
+ V rs: 0xbfc000c0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00238 09: 00000000 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc003ec m_jump_pc: 0xbfc003f0 m_ifetch_addr: 0xbfc003ec
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x24090030>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003ec NPC: 0xbfc003f0 Ins: 0x24090030
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0 rt: 0x9 i: 0x30
+ r rs: 0 rt: 9 rd: 0 sh: 0 func: 0x30
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc000c0 09: 00000000 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc003f0 m_jump_pc: 0xbfc003f4 m_ifetch_addr: 0xbfc003f0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa3490000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003f0 NPC: 0xbfc003f4 Ins: 0xa3490000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0x9 i: 0
+ r rs: 26 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc000c0 09: 00000030 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc003f4 m_jump_pc: 0xbfc003f8 m_ifetch_addr: 0xbfc003f4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x24090078>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc003f4 NPC: 0xbfc003f8 Ins: 0x24090078
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0 rt: 0x9 i: 0x78
+ r rs: 0 rt: 9 rd: 0 sh: 1 func: 0x38
+ V rs: 0 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc000c0 09: 00000030 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc003f8 m_jump_pc: 0xbfc003fc m_ifetch_addr: 0xbfc003f8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa3490000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003f8 NPC: 0xbfc003fc Ins: 0xa3490000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0x9 i: 0
+ r rs: 26 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x78
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc000c0 09: 00000078 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x78 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc003fc m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc003fc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x24090008>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc003fc NPC: 0xbfc00400 Ins: 0x24090008
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0 rt: 0x9 i: 0x8
+ r rs: 0 rt: 9 rd: 0 sh: 0 func: 0x8
+ V rs: 0 rt: 0x78
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc000c0 09: 00000078 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c0af000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0xa i: 0xf000
+ r rs: 0 rt: 10 rd: 30 sh: 0 func: 0
+ V rs: 0 rt: 0x33
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc000c0 09: 00000008 10: 00000033 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x10a5024>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x8 rt: 0xa i: 0x5024
+ r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24
+ V rs: 0xbfc000c0 rt: 0xf0000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc000c0 09: 00000008 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa5702>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0xa i: 0x5702
+ r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2
+ V rs: 0 rt: 0xb0000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc000c0 09: 00000008 10: b0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+0mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x294b000a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xa (slti)
+ i rs: 0xa rt: 0xb i: 0xa
+ r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa
+ V rs: 0xb rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc000c0 09: 00000008 10: 0000000b 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11600004>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0xb rt: 0 i: 0x4
+ r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc000c0 09: 00000008 10: 0000000b 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00424 m_ifetch_addr: 0xbfc00414
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00414 NPC: 0xbfc00424 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc000c0 09: 00000008 10: 0000000b 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00424 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00424
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x214a0037>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00424 NPC: 0xbfc00428 Ins: 0x214a0037
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0xa rt: 0xa i: 0x37
+ r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x37
+ V rs: 0xb rt: 0xb
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc000c0 09: 00000008 10: 0000000b 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa34a0000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0xa i: 0
+ r rs: 26 rt: 10 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x42
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc000c0 09: 00000008 10: 00000042 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x42 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2129ffff>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0x9 rt: 0x9 i: 0xffff
+ r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f
+ V rs: 0x8 rt: 0x8
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc000c0 09: 00000008 10: 00000042 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x1d20fff3>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x7 (bgtz)
+ i rs: 0x9 rt: 0 i: 0xfff3
+ r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33
+ V rs: 0x7 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc000c0 09: 00000007 10: 00000042 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x84100>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0x8 i: 0x4100
+ r rs: 0 rt: 8 rd: 8 sh: 4 func: 0
+ V rs: 0 rt: 0xbfc000c0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc000c0 09: 00000007 10: 00000042 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c0af000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0xa i: 0xf000
+ r rs: 0 rt: 10 rd: 30 sh: 0 func: 0
+ V rs: 0 rt: 0x42
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000
+ 08: fc000c00 09: 00000007 10: 00000042 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x10a5024>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x8 rt: 0xa i: 0x5024
+ r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24
+ V rs: 0xfc000c00 rt: 0xf0000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000
+ 08: fc000c00 09: 00000007 10: f0000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+xmips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa5702>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0xa i: 0x5702
+ r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2
+ V rs: 0 rt: 0xf0000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000
+ 08: fc000c00 09: 00000007 10: f0000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x294b000a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xa (slti)
+ i rs: 0xa rt: 0xb i: 0xa
+ r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa
+ V rs: 0xf rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000
+ 08: fc000c00 09: 00000007 10: 0000000f 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11600004>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0xb rt: 0 i: 0x4
+ r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000
+ 08: fc000c00 09: 00000007 10: 0000000f 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00424 m_ifetch_addr: 0xbfc00414
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00414 NPC: 0xbfc00424 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000
+ 08: fc000c00 09: 00000007 10: 0000000f 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00424 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00424
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x214a0037>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00424 NPC: 0xbfc00428 Ins: 0x214a0037
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0xa rt: 0xa i: 0x37
+ r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x37
+ V rs: 0xf rt: 0xf
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000
+ 08: fc000c00 09: 00000007 10: 0000000f 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa34a0000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0xa i: 0
+ r rs: 26 rt: 10 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x46
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000
+ 08: fc000c00 09: 00000007 10: 00000046 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x46 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2129ffff>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0x9 rt: 0x9 i: 0xffff
+ r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f
+ V rs: 0x7 rt: 0x7
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000
+ 08: fc000c00 09: 00000007 10: 00000046 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x1d20fff3>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x7 (bgtz)
+ i rs: 0x9 rt: 0 i: 0xfff3
+ r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33
+ V rs: 0x6 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000
+ 08: fc000c00 09: 00000006 10: 00000046 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x84100>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0x8 i: 0x4100
+ r rs: 0 rt: 8 rd: 8 sh: 4 func: 0
+ V rs: 0 rt: 0xfc000c00
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000
+ 08: fc000c00 09: 00000006 10: 00000046 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c0af000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0xa i: 0xf000
+ r rs: 0 rt: 10 rd: 30 sh: 0 func: 0
+ V rs: 0 rt: 0x46
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000
+ 08: c000c000 09: 00000006 10: 00000046 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+Bmips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x10a5024>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x8 rt: 0xa i: 0x5024
+ r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24
+ V rs: 0xc000c000 rt: 0xf0000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000
+ 08: c000c000 09: 00000006 10: f0000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa5702>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0xa i: 0x5702
+ r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2
+ V rs: 0 rt: 0xc0000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000
+ 08: c000c000 09: 00000006 10: c0000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x294b000a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xa (slti)
+ i rs: 0xa rt: 0xb i: 0xa
+ r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa
+ V rs: 0xc rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000
+ 08: c000c000 09: 00000006 10: 0000000c 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11600004>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0xb rt: 0 i: 0x4
+ r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000
+ 08: c000c000 09: 00000006 10: 0000000c 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00424 m_ifetch_addr: 0xbfc00414
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00414 NPC: 0xbfc00424 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000
+ 08: c000c000 09: 00000006 10: 0000000c 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00424 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00424
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x214a0037>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00424 NPC: 0xbfc00428 Ins: 0x214a0037
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0xa rt: 0xa i: 0x37
+ r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x37
+ V rs: 0xc rt: 0xc
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000
+ 08: c000c000 09: 00000006 10: 0000000c 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa34a0000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0xa i: 0
+ r rs: 26 rt: 10 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x43
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000
+ 08: c000c000 09: 00000006 10: 00000043 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x43 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2129ffff>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0x9 rt: 0x9 i: 0xffff
+ r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f
+ V rs: 0x6 rt: 0x6
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000
+ 08: c000c000 09: 00000006 10: 00000043 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x1d20fff3>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x7 (bgtz)
+ i rs: 0x9 rt: 0 i: 0xfff3
+ r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33
+ V rs: 0x5 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000
+ 08: c000c000 09: 00000005 10: 00000043 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x84100>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0x8 i: 0x4100
+ r rs: 0 rt: 8 rd: 8 sh: 4 func: 0
+ V rs: 0 rt: 0xc000c000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000
+ 08: c000c000 09: 00000005 10: 00000043 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+Fmips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c0af000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0xa i: 0xf000
+ r rs: 0 rt: 10 rd: 30 sh: 0 func: 0
+ V rs: 0 rt: 0x43
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000
+ 08: 000c0000 09: 00000005 10: 00000043 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x10a5024>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x8 rt: 0xa i: 0x5024
+ r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24
+ V rs: 0xc0000 rt: 0xf0000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000
+ 08: 000c0000 09: 00000005 10: f0000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa5702>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0xa i: 0x5702
+ r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000
+ 08: 000c0000 09: 00000005 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x294b000a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xa (slti)
+ i rs: 0xa rt: 0xb i: 0xa
+ r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000
+ 08: 000c0000 09: 00000005 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11600004>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0xb rt: 0 i: 0x4
+ r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4
+ V rs: 0x1 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000
+ 08: 000c0000 09: 00000005 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000
+ 08: 000c0000 09: 00000005 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x214a0030>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0xa rt: 0xa i: 0x30
+ r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000
+ 08: 000c0000 09: 00000005 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0010a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0x10a
+ r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa
+ V rs: 0xbfc00178 rt: 0xdeac
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000
+ 08: 000c0000 09: 00000005 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000
+ 08: 000c0000 09: 00000005 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa34a0000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0xa i: 0
+ r rs: 26 rt: 10 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000
+ 08: 000c0000 09: 00000005 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+Cmips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2129ffff>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0x9 rt: 0x9 i: 0xffff
+ r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f
+ V rs: 0x5 rt: 0x5
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000
+ 08: 000c0000 09: 00000005 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x1d20fff3>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x7 (bgtz)
+ i rs: 0x9 rt: 0 i: 0xfff3
+ r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33
+ V rs: 0x4 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000
+ 08: 000c0000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x84100>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0x8 i: 0x4100
+ r rs: 0 rt: 8 rd: 8 sh: 4 func: 0
+ V rs: 0 rt: 0xc0000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000
+ 08: 000c0000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c0af000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0xa i: 0xf000
+ r rs: 0 rt: 10 rd: 30 sh: 0 func: 0
+ V rs: 0 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000
+ 08: 00c00000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x10a5024>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x8 rt: 0xa i: 0x5024
+ r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24
+ V rs: 0xc00000 rt: 0xf0000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000
+ 08: 00c00000 09: 00000004 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa5702>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0xa i: 0x5702
+ r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000
+ 08: 00c00000 09: 00000004 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x294b000a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xa (slti)
+ i rs: 0xa rt: 0xb i: 0xa
+ r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa
+ V rs: 0 rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000
+ 08: 00c00000 09: 00000004 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11600004>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0xb rt: 0 i: 0x4
+ r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4
+ V rs: 0x1 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000
+ 08: 00c00000 09: 00000004 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000
+ 08: 00c00000 09: 00000004 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x214a0030>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0xa rt: 0xa i: 0x30
+ r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000
+ 08: 00c00000 09: 00000004 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+0mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0010a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0x10a
+ r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa
+ V rs: 0xbfc00178 rt: 0xdeac
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000
+ 08: 00c00000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000
+ 08: 00c00000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa34a0000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0xa i: 0
+ r rs: 26 rt: 10 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000
+ 08: 00c00000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2129ffff>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0x9 rt: 0x9 i: 0xffff
+ r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f
+ V rs: 0x4 rt: 0x4
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000
+ 08: 00c00000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x1d20fff3>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x7 (bgtz)
+ i rs: 0x9 rt: 0 i: 0xfff3
+ r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33
+ V rs: 0x3 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000
+ 08: 00c00000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x84100>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0x8 i: 0x4100
+ r rs: 0 rt: 8 rd: 8 sh: 4 func: 0
+ V rs: 0 rt: 0xc00000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000
+ 08: 00c00000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c0af000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0xa i: 0xf000
+ r rs: 0 rt: 10 rd: 30 sh: 0 func: 0
+ V rs: 0 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000
+ 08: 0c000000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x10a5024>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x8 rt: 0xa i: 0x5024
+ r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24
+ V rs: 0xc000000 rt: 0xf0000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000
+ 08: 0c000000 09: 00000003 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa5702>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0xa i: 0x5702
+ r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000
+ 08: 0c000000 09: 00000003 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x294b000a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xa (slti)
+ i rs: 0xa rt: 0xb i: 0xa
+ r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa
+ V rs: 0 rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000
+ 08: 0c000000 09: 00000003 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+0mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11600004>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0xb rt: 0 i: 0x4
+ r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4
+ V rs: 0x1 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000
+ 08: 0c000000 09: 00000003 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000
+ 08: 0c000000 09: 00000003 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x214a0030>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0xa rt: 0xa i: 0x30
+ r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000
+ 08: 0c000000 09: 00000003 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0010a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0x10a
+ r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa
+ V rs: 0xbfc00178 rt: 0xdeac
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000
+ 08: 0c000000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000
+ 08: 0c000000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa34a0000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0xa i: 0
+ r rs: 26 rt: 10 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000
+ 08: 0c000000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2129ffff>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0x9 rt: 0x9 i: 0xffff
+ r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f
+ V rs: 0x3 rt: 0x3
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000
+ 08: 0c000000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x1d20fff3>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x7 (bgtz)
+ i rs: 0x9 rt: 0 i: 0xfff3
+ r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33
+ V rs: 0x2 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000
+ 08: 0c000000 09: 00000002 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x84100>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0x8 i: 0x4100
+ r rs: 0 rt: 8 rd: 8 sh: 4 func: 0
+ V rs: 0 rt: 0xc000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000
+ 08: 0c000000 09: 00000002 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c0af000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0xa i: 0xf000
+ r rs: 0 rt: 10 rd: 30 sh: 0 func: 0
+ V rs: 0 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000
+ 08: c0000000 09: 00000002 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x10a5024>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x8 rt: 0xa i: 0x5024
+ r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24
+ V rs: 0xc0000000 rt: 0xf0000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000
+ 08: c0000000 09: 00000002 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa5702>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0xa i: 0x5702
+ r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2
+ V rs: 0 rt: 0xc0000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000
+ 08: c0000000 09: 00000002 10: c0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+0mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x294b000a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xa (slti)
+ i rs: 0xa rt: 0xb i: 0xa
+ r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa
+ V rs: 0xc rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000
+ 08: c0000000 09: 00000002 10: 0000000c 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11600004>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0xb rt: 0 i: 0x4
+ r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000
+ 08: c0000000 09: 00000002 10: 0000000c 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00424 m_ifetch_addr: 0xbfc00414
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00414 NPC: 0xbfc00424 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000
+ 08: c0000000 09: 00000002 10: 0000000c 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00424 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00424
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x214a0037>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00424 NPC: 0xbfc00428 Ins: 0x214a0037
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0xa rt: 0xa i: 0x37
+ r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x37
+ V rs: 0xc rt: 0xc
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000
+ 08: c0000000 09: 00000002 10: 0000000c 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa34a0000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0xa i: 0
+ r rs: 26 rt: 10 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x43
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000
+ 08: c0000000 09: 00000002 10: 00000043 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x43 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2129ffff>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0x9 rt: 0x9 i: 0xffff
+ r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f
+ V rs: 0x2 rt: 0x2
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000
+ 08: c0000000 09: 00000002 10: 00000043 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x1d20fff3>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x7 (bgtz)
+ i rs: 0x9 rt: 0 i: 0xfff3
+ r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33
+ V rs: 0x1 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000
+ 08: c0000000 09: 00000001 10: 00000043 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x84100>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0x8 i: 0x4100
+ r rs: 0 rt: 8 rd: 8 sh: 4 func: 0
+ V rs: 0 rt: 0xc0000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000
+ 08: c0000000 09: 00000001 10: 00000043 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c0af000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0xa i: 0xf000
+ r rs: 0 rt: 10 rd: 30 sh: 0 func: 0
+ V rs: 0 rt: 0x43
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000001 10: 00000043 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x10a5024>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x8 rt: 0xa i: 0x5024
+ r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24
+ V rs: 0 rt: 0xf0000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000001 10: f0000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa5702>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0xa i: 0x5702
+ r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000001 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+Cmips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x294b000a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xa (slti)
+ i rs: 0xa rt: 0xb i: 0xa
+ r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000001 10: 00000000 11: 00000000 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11600004>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0xb rt: 0 i: 0x4
+ r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4
+ V rs: 0x1 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000001 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000001 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x214a0030>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0xa rt: 0xa i: 0x30
+ r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000001 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0010a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0x10a
+ r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa
+ V rs: 0xbfc00178 rt: 0xdeac
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000001 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000001 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa34a0000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0xa i: 0
+ r rs: 26 rt: 10 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000001 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2129ffff>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0x9 rt: 0x9 i: 0xffff
+ r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f
+ V rs: 0x1 rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000001 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x1d20fff3>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x7 (bgtz)
+ i rs: 0x9 rt: 0 i: 0xfff3
+ r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00438 m_ifetch_addr: 0xbfc00434
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x84100>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00434 NPC: 0xbfc00438 Ins: 0x84100
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0x8 i: 0x4100
+ r rs: 0 rt: 8 rd: 8 sh: 4 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00438 m_jump_pc: 0xbfc0043c m_ifetch_addr: 0xbfc00438
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3e00008>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00438 NPC: 0xbfc0043c Ins: 0x3e00008
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x1f rt: 0 i: 0x8
+ r rs: 31 rt: 0 rd: 0 sh: 0 func: 0x8
+ V rs: 0xbfc00178 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc0043c m_jump_pc: 0xbfc00178 m_ifetch_addr: 0xbfc0043c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0043c NPC: 0xbfc00178 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00178 m_jump_pc: 0xbfc0017c m_ifetch_addr: 0xbfc00178
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c04bfc0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00178 NPC: 0xbfc0017c Ins: 0x3c04bfc0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0x4 i: 0xbfc0
+ r rs: 0 rt: 4 rd: 23 sh: 31 func: 0
+ V rs: 0 rt: 0xbfc000c0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc000c0 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc0017c m_jump_pc: 0xbfc00180 m_ifetch_addr: 0xbfc0017c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+0mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2484022c>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0017c NPC: 0xbfc00180 Ins: 0x2484022c
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0x4 rt: 0x4 i: 0x22c
+ r rs: 4 rt: 4 rd: 0 sh: 8 func: 0x2c
+ V rs: 0xbfc00000 rt: 0xbfc00000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00180 m_jump_pc: 0xbfc00184 m_ifetch_addr: 0xbfc00180
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xff000f0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00180 NPC: 0xbfc00184 Ins: 0xff000f0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x3 (jal)
+ i rs: 0x1f rt: 0x10 i: 0xf0
+ r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x30
+ V rs: 0xbfc00178 rt: 0xdeac
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00178
+mips0 m_next_pc: 0xbfc00184 m_jump_pc: 0xbfc003c0 m_ifetch_addr: 0xbfc00184
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00184 NPC: 0xbfc003c0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 m_next_pc: 0xbfc003c0 m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003c0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x804021>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c0 NPC: 0xbfc003c4 Ins: 0x804021
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x4 rt: 0 i: 0x4021
+ r rs: 4 rt: 0 rd: 8 sh: 0 func: 0x21
+ V rs: 0xbfc0022c rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x81090000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x20 (lb)
+ i rs: 0x8 rt: 0x9 i: 0
+ r rs: 8 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xbfc0022c rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0022c 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_READ @ 0xbfc0022c wdata 0 be 0x1> off: 0 sign_ext: 0x1 dest: gp+0x9
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp valid no error rdata 0x75616320>, 0)
+mips0 setData: <DataRsp valid no error rdata 0x75616320> off: 0 sign_ext: 0x1 dest: r_gp+0x9
+mips0 setData: <DataRsp valid no error rdata 0x75616320> off: 0 count: 0x1 le: 0 old: 0 from_mem: 0x75616320 mask: 0xffffffff new_data: 0x20
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0x9 rt: 0 i: 0x5
+ r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5
+ V rs: 0x20 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0022c 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0022c 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa3490000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0x9 i: 0
+ r rs: 26 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x20
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0022c 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x20 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0x8 rt: 0x8 i: 0x1
+ r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1
+ V rs: 0xbfc0022c rt: 0xbfc0022c
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0022c 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf000f1>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0xf1
+ r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31
+ V rs: 0xbfc00188 rt: 0xdeac
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0022d 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0022d 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x81090000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x20 (lb)
+ i rs: 0x8 rt: 0x9 i: 0
+ r rs: 8 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xbfc0022d rt: 0x20
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0022d 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_READ @ 0xbfc0022c wdata 0 be 0x2> off: 0x1 sign_ext: 0x1 dest: gp+0x9
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp valid no error rdata 0x75616320>, 0)
+mips0 setData: <DataRsp valid no error rdata 0x75616320> off: 0 sign_ext: 0x1 dest: r_gp+0x9
+mips0 setData: <DataRsp valid no error rdata 0x75616320> off: 0 count: 0x1 le: 0x1 old: 0x20 from_mem: 0x75616320 mask: 0xffffffff new_data: 0x63
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1
+ mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0x9 rt: 0 i: 0x5
+ r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5
+ V rs: 0x63 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0022d 09: 00000063 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0022d 09: 00000063 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa3490000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0x9 i: 0
+ r rs: 26 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x63
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0022d 09: 00000063 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x63 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0x8 rt: 0x8 i: 0x1
+ r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1
+ V rs: 0xbfc0022d rt: 0xbfc0022d
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0022d 09: 00000063 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf000f1>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0xf1
+ r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31
+ V rs: 0xbfc00188 rt: 0xdeac
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0022e 09: 00000063 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0022e 09: 00000063 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x81090000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x20 (lb)
+ i rs: 0x8 rt: 0x9 i: 0
+ r rs: 8 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xbfc0022e rt: 0x63
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0022e 09: 00000063 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_READ @ 0xbfc0022c wdata 0 be 0x4> off: 0x2 sign_ext: 0x1 dest: gp+0x9
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp valid no error rdata 0x75616320>, 0)
+mips0 setData: <DataRsp valid no error rdata 0x75616320> off: 0 sign_ext: 0x1 dest: r_gp+0x9
+mips0 setData: <DataRsp valid no error rdata 0x75616320> off: 0 count: 0x1 le: 0x2 old: 0x63 from_mem: 0x75616320 mask: 0xffffffff new_data: 0x61
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0x9 rt: 0 i: 0x5
+ r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5
+ V rs: 0x61 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0022e 09: 00000061 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+cmips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0022e 09: 00000061 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa3490000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0x9 i: 0
+ r rs: 26 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x61
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0022e 09: 00000061 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x61 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0x8 rt: 0x8 i: 0x1
+ r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1
+ V rs: 0xbfc0022e rt: 0xbfc0022e
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0022e 09: 00000061 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf000f1>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0xf1
+ r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31
+ V rs: 0xbfc00188 rt: 0xdeac
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0022f 09: 00000061 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0022f 09: 00000061 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x81090000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x20 (lb)
+ i rs: 0x8 rt: 0x9 i: 0
+ r rs: 8 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xbfc0022f rt: 0x61
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0022f 09: 00000061 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_READ @ 0xbfc0022c wdata 0 be 0x8> off: 0x3 sign_ext: 0x1 dest: gp+0x9
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp valid no error rdata 0x75616320>, 0)
+mips0 setData: <DataRsp valid no error rdata 0x75616320> off: 0 sign_ext: 0x1 dest: r_gp+0x9
+mips0 setData: <DataRsp valid no error rdata 0x75616320> off: 0 count: 0x1 le: 0x3 old: 0x61 from_mem: 0x75616320 mask: 0xffffffff new_data: 0x75
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0x9 rt: 0 i: 0x5
+ r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5
+ V rs: 0x75 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0022f 09: 00000075 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0022f 09: 00000075 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+amips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa3490000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0x9 i: 0
+ r rs: 26 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x75
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0022f 09: 00000075 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x75 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0x8 rt: 0x8 i: 0x1
+ r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1
+ V rs: 0xbfc0022f rt: 0xbfc0022f
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0022f 09: 00000075 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf000f1>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0xf1
+ r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31
+ V rs: 0xbfc00188 rt: 0xdeac
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00230 09: 00000075 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00230 09: 00000075 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x81090000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x20 (lb)
+ i rs: 0x8 rt: 0x9 i: 0
+ r rs: 8 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xbfc00230 rt: 0x75
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00230 09: 00000075 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_READ @ 0xbfc00230 wdata 0 be 0x1> off: 0 sign_ext: 0x1 dest: gp+0x9
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp valid no error rdata 0x206573>, 0)
+mips0 setData: <DataRsp valid no error rdata 0x206573> off: 0 sign_ext: 0x1 dest: r_gp+0x9
+mips0 setData: <DataRsp valid no error rdata 0x206573> off: 0 count: 0x1 le: 0 old: 0x75 from_mem: 0x206573 mask: 0xffffffff new_data: 0x73
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0x9 rt: 0 i: 0x5
+ r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5
+ V rs: 0x73 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00230 09: 00000073 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00230 09: 00000073 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa3490000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0x9 i: 0
+ r rs: 26 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x73
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00230 09: 00000073 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x73 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+umips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0x8 rt: 0x8 i: 0x1
+ r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1
+ V rs: 0xbfc00230 rt: 0xbfc00230
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00230 09: 00000073 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf000f1>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0xf1
+ r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31
+ V rs: 0xbfc00188 rt: 0xdeac
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00231 09: 00000073 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00231 09: 00000073 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x81090000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x20 (lb)
+ i rs: 0x8 rt: 0x9 i: 0
+ r rs: 8 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xbfc00231 rt: 0x73
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00231 09: 00000073 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_READ @ 0xbfc00230 wdata 0 be 0x2> off: 0x1 sign_ext: 0x1 dest: gp+0x9
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp valid no error rdata 0x206573>, 0)
+mips0 setData: <DataRsp valid no error rdata 0x206573> off: 0 sign_ext: 0x1 dest: r_gp+0x9
+mips0 setData: <DataRsp valid no error rdata 0x206573> off: 0 count: 0x1 le: 0x1 old: 0x73 from_mem: 0x206573 mask: 0xffffffff new_data: 0x65
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0x9 rt: 0 i: 0x5
+ r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5
+ V rs: 0x65 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00231 09: 00000065 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00231 09: 00000065 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa3490000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0x9 i: 0
+ r rs: 26 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x65
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00231 09: 00000065 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x65 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+smips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0x8 rt: 0x8 i: 0x1
+ r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1
+ V rs: 0xbfc00231 rt: 0xbfc00231
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00231 09: 00000065 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf000f1>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0xf1
+ r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31
+ V rs: 0xbfc00188 rt: 0xdeac
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00232 09: 00000065 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00232 09: 00000065 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x81090000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x20 (lb)
+ i rs: 0x8 rt: 0x9 i: 0
+ r rs: 8 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xbfc00232 rt: 0x65
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00232 09: 00000065 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_READ @ 0xbfc00230 wdata 0 be 0x4> off: 0x2 sign_ext: 0x1 dest: gp+0x9
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp valid no error rdata 0x206573>, 0)
+mips0 setData: <DataRsp valid no error rdata 0x206573> off: 0 sign_ext: 0x1 dest: r_gp+0x9
+mips0 setData: <DataRsp valid no error rdata 0x206573> off: 0 count: 0x1 le: 0x2 old: 0x65 from_mem: 0x206573 mask: 0xffffffff new_data: 0x20
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0x9 rt: 0 i: 0x5
+ r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5
+ V rs: 0x20 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00232 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00232 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa3490000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0x9 i: 0
+ r rs: 26 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x20
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00232 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x20 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+emips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0x8 rt: 0x8 i: 0x1
+ r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1
+ V rs: 0xbfc00232 rt: 0xbfc00232
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00232 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf000f1>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0xf1
+ r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31
+ V rs: 0xbfc00188 rt: 0xdeac
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00233 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00233 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x81090000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x20 (lb)
+ i rs: 0x8 rt: 0x9 i: 0
+ r rs: 8 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xbfc00233 rt: 0x20
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00233 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_READ @ 0xbfc00230 wdata 0 be 0x8> off: 0x3 sign_ext: 0x1 dest: gp+0x9
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp valid no error rdata 0x206573>, 0)
+mips0 setData: <DataRsp valid no error rdata 0x206573> off: 0 sign_ext: 0x1 dest: r_gp+0x9
+mips0 setData: <DataRsp valid no error rdata 0x206573> off: 0 count: 0x1 le: 0x3 old: 0x20 from_mem: 0x206573 mask: 0xffffffff new_data: 0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0x9 rt: 0 i: 0x5
+ r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00233 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003e0 m_ifetch_addr: 0xbfc003cc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003cc NPC: 0xbfc003e0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00233 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 m_next_pc: 0xbfc003e0 m_jump_pc: 0xbfc003e4 m_ifetch_addr: 0xbfc003e0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3e00008>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003e0 NPC: 0xbfc003e4 Ins: 0x3e00008
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x1f rt: 0 i: 0x8
+ r rs: 31 rt: 0 rd: 0 sh: 0 func: 0x8
+ V rs: 0xbfc00188 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00233 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 m_next_pc: 0xbfc003e4 m_jump_pc: 0xbfc00188 m_ifetch_addr: 0xbfc003e4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+ mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003e4 NPC: 0xbfc00188 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00233 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 m_next_pc: 0xbfc00188 m_jump_pc: 0xbfc0018c m_ifetch_addr: 0xbfc00188
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x40046800>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00188 NPC: 0xbfc0018c Ins: 0x40046800
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x10 (cop0)
+ i rs: 0 rt: 0x4 i: 0x6800
+ r rs: 0 rt: 4 rd: 13 sh: 0 func: 0
+ V rs: 0 rt: 0xbfc0022c
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc0022c 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00233 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 m_next_pc: 0xbfc0018c m_jump_pc: 0xbfc00190 m_ifetch_addr: 0xbfc0018c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xff000fa>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0018c NPC: 0xbfc00190 Ins: 0xff000fa
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x3 (jal)
+ i rs: 0x1f rt: 0x10 i: 0xfa
+ r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x3a
+ V rs: 0xbfc00188 rt: 0xdeac
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00233 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00188
+mips0 m_next_pc: 0xbfc00190 m_jump_pc: 0xbfc003e8 m_ifetch_addr: 0xbfc00190
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00190 NPC: 0xbfc003e8 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00233 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc003e8 m_jump_pc: 0xbfc003ec m_ifetch_addr: 0xbfc003e8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x804021>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003e8 NPC: 0xbfc003ec Ins: 0x804021
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x4 rt: 0 i: 0x4021
+ r rs: 4 rt: 0 rd: 8 sh: 0 func: 0x21
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00233 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc003ec m_jump_pc: 0xbfc003f0 m_ifetch_addr: 0xbfc003ec
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x24090030>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003ec NPC: 0xbfc003f0 Ins: 0x24090030
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0 rt: 0x9 i: 0x30
+ r rs: 0 rt: 9 rd: 0 sh: 0 func: 0x30
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc003f0 m_jump_pc: 0xbfc003f4 m_ifetch_addr: 0xbfc003f0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa3490000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003f0 NPC: 0xbfc003f4 Ins: 0xa3490000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0x9 i: 0
+ r rs: 26 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000030 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc003f4 m_jump_pc: 0xbfc003f8 m_ifetch_addr: 0xbfc003f4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x24090078>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc003f4 NPC: 0xbfc003f8 Ins: 0x24090078
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0 rt: 0x9 i: 0x78
+ r rs: 0 rt: 9 rd: 0 sh: 1 func: 0x38
+ V rs: 0 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000030 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc003f8 m_jump_pc: 0xbfc003fc m_ifetch_addr: 0xbfc003f8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa3490000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003f8 NPC: 0xbfc003fc Ins: 0xa3490000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0x9 i: 0
+ r rs: 26 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x78
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000078 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x78 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc003fc m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc003fc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x24090008>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc003fc NPC: 0xbfc00400 Ins: 0x24090008
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0 rt: 0x9 i: 0x8
+ r rs: 0 rt: 9 rd: 0 sh: 0 func: 0x8
+ V rs: 0 rt: 0x78
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000078 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c0af000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0xa i: 0xf000
+ r rs: 0 rt: 10 rd: 30 sh: 0 func: 0
+ V rs: 0 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000008 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x10a5024>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x8 rt: 0xa i: 0x5024
+ r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24
+ V rs: 0 rt: 0xf0000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000008 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa5702>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0xa i: 0x5702
+ r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000008 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+0mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x294b000a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xa (slti)
+ i rs: 0xa rt: 0xb i: 0xa
+ r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa
+ V rs: 0 rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000008 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11600004>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0xb rt: 0 i: 0x4
+ r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4
+ V rs: 0x1 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000008 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000008 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x214a0030>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0xa rt: 0xa i: 0x30
+ r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000008 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0010a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0x10a
+ r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa
+ V rs: 0xbfc00194 rt: 0xdeac
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000008 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000008 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa34a0000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0xa i: 0
+ r rs: 26 rt: 10 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000008 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2129ffff>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0x9 rt: 0x9 i: 0xffff
+ r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f
+ V rs: 0x8 rt: 0x8
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000008 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x1d20fff3>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x7 (bgtz)
+ i rs: 0x9 rt: 0 i: 0xfff3
+ r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33
+ V rs: 0x7 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000007 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x84100>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0x8 i: 0x4100
+ r rs: 0 rt: 8 rd: 8 sh: 4 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000007 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+xmips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c0af000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0xa i: 0xf000
+ r rs: 0 rt: 10 rd: 30 sh: 0 func: 0
+ V rs: 0 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000007 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x10a5024>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x8 rt: 0xa i: 0x5024
+ r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24
+ V rs: 0 rt: 0xf0000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000007 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa5702>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0xa i: 0x5702
+ r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000007 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x294b000a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xa (slti)
+ i rs: 0xa rt: 0xb i: 0xa
+ r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa
+ V rs: 0 rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000007 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11600004>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0xb rt: 0 i: 0x4
+ r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4
+ V rs: 0x1 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000007 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000007 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x214a0030>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0xa rt: 0xa i: 0x30
+ r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000007 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0010a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0x10a
+ r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa
+ V rs: 0xbfc00194 rt: 0xdeac
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000007 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000007 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa34a0000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0xa i: 0
+ r rs: 26 rt: 10 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000007 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+0mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2129ffff>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0x9 rt: 0x9 i: 0xffff
+ r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f
+ V rs: 0x7 rt: 0x7
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000007 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x1d20fff3>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x7 (bgtz)
+ i rs: 0x9 rt: 0 i: 0xfff3
+ r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33
+ V rs: 0x6 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000006 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x84100>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0x8 i: 0x4100
+ r rs: 0 rt: 8 rd: 8 sh: 4 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000006 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c0af000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0xa i: 0xf000
+ r rs: 0 rt: 10 rd: 30 sh: 0 func: 0
+ V rs: 0 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000006 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x10a5024>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x8 rt: 0xa i: 0x5024
+ r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24
+ V rs: 0 rt: 0xf0000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000006 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa5702>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0xa i: 0x5702
+ r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000006 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x294b000a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xa (slti)
+ i rs: 0xa rt: 0xb i: 0xa
+ r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa
+ V rs: 0 rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000006 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11600004>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0xb rt: 0 i: 0x4
+ r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4
+ V rs: 0x1 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000006 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000006 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x214a0030>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0xa rt: 0xa i: 0x30
+ r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000006 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+0mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0010a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0x10a
+ r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa
+ V rs: 0xbfc00194 rt: 0xdeac
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000006 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000006 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa34a0000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0xa i: 0
+ r rs: 26 rt: 10 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000006 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2129ffff>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0x9 rt: 0x9 i: 0xffff
+ r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f
+ V rs: 0x6 rt: 0x6
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000006 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x1d20fff3>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x7 (bgtz)
+ i rs: 0x9 rt: 0 i: 0xfff3
+ r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33
+ V rs: 0x5 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000005 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x84100>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0x8 i: 0x4100
+ r rs: 0 rt: 8 rd: 8 sh: 4 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000005 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c0af000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0xa i: 0xf000
+ r rs: 0 rt: 10 rd: 30 sh: 0 func: 0
+ V rs: 0 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000005 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x10a5024>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x8 rt: 0xa i: 0x5024
+ r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24
+ V rs: 0 rt: 0xf0000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000005 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa5702>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0xa i: 0x5702
+ r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000005 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x294b000a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xa (slti)
+ i rs: 0xa rt: 0xb i: 0xa
+ r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa
+ V rs: 0 rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000005 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+0mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11600004>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0xb rt: 0 i: 0x4
+ r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4
+ V rs: 0x1 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000005 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000005 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x214a0030>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0xa rt: 0xa i: 0x30
+ r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000005 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0010a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0x10a
+ r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa
+ V rs: 0xbfc00194 rt: 0xdeac
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000005 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000005 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa34a0000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0xa i: 0
+ r rs: 26 rt: 10 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000005 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2129ffff>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0x9 rt: 0x9 i: 0xffff
+ r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f
+ V rs: 0x5 rt: 0x5
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000005 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x1d20fff3>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x7 (bgtz)
+ i rs: 0x9 rt: 0 i: 0xfff3
+ r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33
+ V rs: 0x4 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x84100>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0x8 i: 0x4100
+ r rs: 0 rt: 8 rd: 8 sh: 4 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c0af000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0xa i: 0xf000
+ r rs: 0 rt: 10 rd: 30 sh: 0 func: 0
+ V rs: 0 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x10a5024>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x8 rt: 0xa i: 0x5024
+ r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24
+ V rs: 0 rt: 0xf0000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000004 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa5702>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0xa i: 0x5702
+ r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000004 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+0mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x294b000a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xa (slti)
+ i rs: 0xa rt: 0xb i: 0xa
+ r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa
+ V rs: 0 rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000004 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11600004>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0xb rt: 0 i: 0x4
+ r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4
+ V rs: 0x1 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000004 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000004 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x214a0030>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0xa rt: 0xa i: 0x30
+ r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000004 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0010a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0x10a
+ r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa
+ V rs: 0xbfc00194 rt: 0xdeac
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa34a0000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0xa i: 0
+ r rs: 26 rt: 10 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2129ffff>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0x9 rt: 0x9 i: 0xffff
+ r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f
+ V rs: 0x4 rt: 0x4
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x1d20fff3>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x7 (bgtz)
+ i rs: 0x9 rt: 0 i: 0xfff3
+ r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33
+ V rs: 0x3 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x84100>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0x8 i: 0x4100
+ r rs: 0 rt: 8 rd: 8 sh: 4 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c0af000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0xa i: 0xf000
+ r rs: 0 rt: 10 rd: 30 sh: 0 func: 0
+ V rs: 0 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x10a5024>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x8 rt: 0xa i: 0x5024
+ r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24
+ V rs: 0 rt: 0xf0000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000003 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa5702>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0xa i: 0x5702
+ r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000003 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+0mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x294b000a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xa (slti)
+ i rs: 0xa rt: 0xb i: 0xa
+ r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa
+ V rs: 0 rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000003 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11600004>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0xb rt: 0 i: 0x4
+ r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4
+ V rs: 0x1 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000003 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000003 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x214a0030>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0xa rt: 0xa i: 0x30
+ r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000003 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0010a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0x10a
+ r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa
+ V rs: 0xbfc00194 rt: 0xdeac
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa34a0000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0xa i: 0
+ r rs: 26 rt: 10 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2129ffff>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0x9 rt: 0x9 i: 0xffff
+ r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f
+ V rs: 0x3 rt: 0x3
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x1d20fff3>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x7 (bgtz)
+ i rs: 0x9 rt: 0 i: 0xfff3
+ r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33
+ V rs: 0x2 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000002 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x84100>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0x8 i: 0x4100
+ r rs: 0 rt: 8 rd: 8 sh: 4 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000002 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c0af000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0xa i: 0xf000
+ r rs: 0 rt: 10 rd: 30 sh: 0 func: 0
+ V rs: 0 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000002 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x10a5024>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x8 rt: 0xa i: 0x5024
+ r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24
+ V rs: 0 rt: 0xf0000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000002 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa5702>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0xa i: 0x5702
+ r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000002 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+0mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x294b000a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xa (slti)
+ i rs: 0xa rt: 0xb i: 0xa
+ r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa
+ V rs: 0 rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000002 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11600004>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0xb rt: 0 i: 0x4
+ r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4
+ V rs: 0x1 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000002 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000002 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x214a0030>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0xa rt: 0xa i: 0x30
+ r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000002 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0010a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0x10a
+ r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa
+ V rs: 0xbfc00194 rt: 0xdeac
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000002 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000002 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa34a0000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0xa i: 0
+ r rs: 26 rt: 10 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000002 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2129ffff>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0x9 rt: 0x9 i: 0xffff
+ r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f
+ V rs: 0x2 rt: 0x2
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000002 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x1d20fff3>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x7 (bgtz)
+ i rs: 0x9 rt: 0 i: 0xfff3
+ r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33
+ V rs: 0x1 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000001 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x84100>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0x8 i: 0x4100
+ r rs: 0 rt: 8 rd: 8 sh: 4 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000001 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c0af000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0xa i: 0xf000
+ r rs: 0 rt: 10 rd: 30 sh: 0 func: 0
+ V rs: 0 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000001 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x10a5024>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x8 rt: 0xa i: 0x5024
+ r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24
+ V rs: 0 rt: 0xf0000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000001 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa5702>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0xa i: 0x5702
+ r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000001 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+0mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x294b000a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xa (slti)
+ i rs: 0xa rt: 0xb i: 0xa
+ r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa
+ V rs: 0 rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000001 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11600004>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0xb rt: 0 i: 0x4
+ r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4
+ V rs: 0x1 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000001 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000001 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x214a0030>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0xa rt: 0xa i: 0x30
+ r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000001 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0010a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0x10a
+ r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa
+ V rs: 0xbfc00194 rt: 0xdeac
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000001 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000001 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa34a0000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0xa i: 0
+ r rs: 26 rt: 10 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000001 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2129ffff>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0x9 rt: 0x9 i: 0xffff
+ r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f
+ V rs: 0x1 rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000001 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x1d20fff3>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x7 (bgtz)
+ i rs: 0x9 rt: 0 i: 0xfff3
+ r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00438 m_ifetch_addr: 0xbfc00434
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x84100>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00434 NPC: 0xbfc00438 Ins: 0x84100
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0x8 i: 0x4100
+ r rs: 0 rt: 8 rd: 8 sh: 4 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00438 m_jump_pc: 0xbfc0043c m_ifetch_addr: 0xbfc00438
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3e00008>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00438 NPC: 0xbfc0043c Ins: 0x3e00008
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x1f rt: 0 i: 0x8
+ r rs: 31 rt: 0 rd: 0 sh: 0 func: 0x8
+ V rs: 0xbfc00194 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc0043c m_jump_pc: 0xbfc00194 m_ifetch_addr: 0xbfc0043c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0043c NPC: 0xbfc00194 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00194 m_jump_pc: 0xbfc00198 m_ifetch_addr: 0xbfc00194
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c04bfc0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00194 NPC: 0xbfc00198 Ins: 0x3c04bfc0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0x4 i: 0xbfc0
+ r rs: 0 rt: 4 rd: 23 sh: 31 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc00198 m_jump_pc: 0xbfc0019c m_ifetch_addr: 0xbfc00198
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+0mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x24840239>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00198 NPC: 0xbfc0019c Ins: 0x24840239
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0x4 rt: 0x4 i: 0x239
+ r rs: 4 rt: 4 rd: 0 sh: 8 func: 0x39
+ V rs: 0xbfc00000 rt: 0xbfc00000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc0019c m_jump_pc: 0xbfc001a0 m_ifetch_addr: 0xbfc0019c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xff000f0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0019c NPC: 0xbfc001a0 Ins: 0xff000f0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x3 (jal)
+ i rs: 0x1f rt: 0x10 i: 0xf0
+ r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x30
+ V rs: 0xbfc00194 rt: 0xdeac
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc00194
+mips0 m_next_pc: 0xbfc001a0 m_jump_pc: 0xbfc003c0 m_ifetch_addr: 0xbfc001a0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc001a0 NPC: 0xbfc003c0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 m_next_pc: 0xbfc003c0 m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003c0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x804021>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c0 NPC: 0xbfc003c4 Ins: 0x804021
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x4 rt: 0 i: 0x4021
+ r rs: 4 rt: 0 rd: 8 sh: 0 func: 0x21
+ V rs: 0xbfc00239 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x81090000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x20 (lb)
+ i rs: 0x8 rt: 0x9 i: 0
+ r rs: 8 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xbfc00239 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00239 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_READ @ 0xbfc00238 wdata 0 be 0x2> off: 0x1 sign_ext: 0x1 dest: gp+0x9
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp valid no error rdata 0x61622000>, 0)
+mips0 setData: <DataRsp valid no error rdata 0x61622000> off: 0 sign_ext: 0x1 dest: r_gp+0x9
+mips0 setData: <DataRsp valid no error rdata 0x61622000> off: 0 count: 0x1 le: 0x1 old: 0 from_mem: 0x61622000 mask: 0xffffffff new_data: 0x20
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0x9 rt: 0 i: 0x5
+ r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5
+ V rs: 0x20 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00239 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00239 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa3490000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0x9 i: 0
+ r rs: 26 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x20
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00239 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x20 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0x8 rt: 0x8 i: 0x1
+ r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1
+ V rs: 0xbfc00239 rt: 0xbfc00239
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00239 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf000f1>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0xf1
+ r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31
+ V rs: 0xbfc001a4 rt: 0xdeac
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0023a 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0023a 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x81090000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x20 (lb)
+ i rs: 0x8 rt: 0x9 i: 0
+ r rs: 8 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xbfc0023a rt: 0x20
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0023a 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_READ @ 0xbfc00238 wdata 0 be 0x4> off: 0x2 sign_ext: 0x1 dest: gp+0x9
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp valid no error rdata 0x61622000>, 0)
+mips0 setData: <DataRsp valid no error rdata 0x61622000> off: 0 sign_ext: 0x1 dest: r_gp+0x9
+mips0 setData: <DataRsp valid no error rdata 0x61622000> off: 0 count: 0x1 le: 0x2 old: 0x20 from_mem: 0x61622000 mask: 0xffffffff new_data: 0x62
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1
+ mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0x9 rt: 0 i: 0x5
+ r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5
+ V rs: 0x62 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0023a 09: 00000062 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0023a 09: 00000062 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa3490000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0x9 i: 0
+ r rs: 26 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x62
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0023a 09: 00000062 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x62 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0x8 rt: 0x8 i: 0x1
+ r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1
+ V rs: 0xbfc0023a rt: 0xbfc0023a
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0023a 09: 00000062 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf000f1>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0xf1
+ r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31
+ V rs: 0xbfc001a4 rt: 0xdeac
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0023b 09: 00000062 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0023b 09: 00000062 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x81090000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x20 (lb)
+ i rs: 0x8 rt: 0x9 i: 0
+ r rs: 8 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xbfc0023b rt: 0x62
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0023b 09: 00000062 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_READ @ 0xbfc00238 wdata 0 be 0x8> off: 0x3 sign_ext: 0x1 dest: gp+0x9
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp valid no error rdata 0x61622000>, 0)
+mips0 setData: <DataRsp valid no error rdata 0x61622000> off: 0 sign_ext: 0x1 dest: r_gp+0x9
+mips0 setData: <DataRsp valid no error rdata 0x61622000> off: 0 count: 0x1 le: 0x3 old: 0x62 from_mem: 0x61622000 mask: 0xffffffff new_data: 0x61
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0x9 rt: 0 i: 0x5
+ r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5
+ V rs: 0x61 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0023b 09: 00000061 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+bmips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0023b 09: 00000061 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa3490000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0x9 i: 0
+ r rs: 26 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x61
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0023b 09: 00000061 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x61 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0x8 rt: 0x8 i: 0x1
+ r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1
+ V rs: 0xbfc0023b rt: 0xbfc0023b
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0023b 09: 00000061 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf000f1>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0xf1
+ r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31
+ V rs: 0xbfc001a4 rt: 0xdeac
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0023c 09: 00000061 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0023c 09: 00000061 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x81090000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x20 (lb)
+ i rs: 0x8 rt: 0x9 i: 0
+ r rs: 8 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xbfc0023c rt: 0x61
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0023c 09: 00000061 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_READ @ 0xbfc0023c wdata 0 be 0x1> off: 0 sign_ext: 0x1 dest: gp+0x9
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp valid no error rdata 0x20617664>, 0)
+mips0 setData: <DataRsp valid no error rdata 0x20617664> off: 0 sign_ext: 0x1 dest: r_gp+0x9
+mips0 setData: <DataRsp valid no error rdata 0x20617664> off: 0 count: 0x1 le: 0 old: 0x61 from_mem: 0x20617664 mask: 0xffffffff new_data: 0x64
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0x9 rt: 0 i: 0x5
+ r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5
+ V rs: 0x64 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0023c 09: 00000064 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0023c 09: 00000064 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+amips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa3490000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0x9 i: 0
+ r rs: 26 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x64
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0023c 09: 00000064 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x64 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0x8 rt: 0x8 i: 0x1
+ r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1
+ V rs: 0xbfc0023c rt: 0xbfc0023c
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0023c 09: 00000064 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf000f1>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0xf1
+ r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31
+ V rs: 0xbfc001a4 rt: 0xdeac
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0023d 09: 00000064 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0023d 09: 00000064 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x81090000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x20 (lb)
+ i rs: 0x8 rt: 0x9 i: 0
+ r rs: 8 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xbfc0023d rt: 0x64
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0023d 09: 00000064 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_READ @ 0xbfc0023c wdata 0 be 0x2> off: 0x1 sign_ext: 0x1 dest: gp+0x9
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp valid no error rdata 0x20617664>, 0)
+mips0 setData: <DataRsp valid no error rdata 0x20617664> off: 0 sign_ext: 0x1 dest: r_gp+0x9
+mips0 setData: <DataRsp valid no error rdata 0x20617664> off: 0 count: 0x1 le: 0x1 old: 0x64 from_mem: 0x20617664 mask: 0xffffffff new_data: 0x76
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0x9 rt: 0 i: 0x5
+ r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5
+ V rs: 0x76 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0023d 09: 00000076 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0023d 09: 00000076 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa3490000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0x9 i: 0
+ r rs: 26 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x76
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0023d 09: 00000076 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x76 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+dmips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0x8 rt: 0x8 i: 0x1
+ r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1
+ V rs: 0xbfc0023d rt: 0xbfc0023d
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0023d 09: 00000076 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf000f1>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0xf1
+ r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31
+ V rs: 0xbfc001a4 rt: 0xdeac
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0023e 09: 00000076 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0023e 09: 00000076 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x81090000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x20 (lb)
+ i rs: 0x8 rt: 0x9 i: 0
+ r rs: 8 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xbfc0023e rt: 0x76
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0023e 09: 00000076 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_READ @ 0xbfc0023c wdata 0 be 0x4> off: 0x2 sign_ext: 0x1 dest: gp+0x9
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp valid no error rdata 0x20617664>, 0)
+mips0 setData: <DataRsp valid no error rdata 0x20617664> off: 0 sign_ext: 0x1 dest: r_gp+0x9
+mips0 setData: <DataRsp valid no error rdata 0x20617664> off: 0 count: 0x1 le: 0x2 old: 0x76 from_mem: 0x20617664 mask: 0xffffffff new_data: 0x61
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0x9 rt: 0 i: 0x5
+ r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5
+ V rs: 0x61 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0023e 09: 00000061 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0023e 09: 00000061 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa3490000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0x9 i: 0
+ r rs: 26 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x61
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0023e 09: 00000061 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x61 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+vmips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0x8 rt: 0x8 i: 0x1
+ r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1
+ V rs: 0xbfc0023e rt: 0xbfc0023e
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0023e 09: 00000061 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf000f1>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0xf1
+ r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31
+ V rs: 0xbfc001a4 rt: 0xdeac
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0023f 09: 00000061 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0023f 09: 00000061 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x81090000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x20 (lb)
+ i rs: 0x8 rt: 0x9 i: 0
+ r rs: 8 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xbfc0023f rt: 0x61
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0023f 09: 00000061 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_READ @ 0xbfc0023c wdata 0 be 0x8> off: 0x3 sign_ext: 0x1 dest: gp+0x9
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp valid no error rdata 0x20617664>, 0)
+mips0 setData: <DataRsp valid no error rdata 0x20617664> off: 0 sign_ext: 0x1 dest: r_gp+0x9
+mips0 setData: <DataRsp valid no error rdata 0x20617664> off: 0 count: 0x1 le: 0x3 old: 0x61 from_mem: 0x20617664 mask: 0xffffffff new_data: 0x20
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0x9 rt: 0 i: 0x5
+ r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5
+ V rs: 0x20 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0023f 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0023f 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa3490000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0x9 i: 0
+ r rs: 26 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x20
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0023f 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x20 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+amips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0x8 rt: 0x8 i: 0x1
+ r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1
+ V rs: 0xbfc0023f rt: 0xbfc0023f
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc0023f 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf000f1>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0xf1
+ r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31
+ V rs: 0xbfc001a4 rt: 0xdeac
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00240 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00240 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x81090000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x20 (lb)
+ i rs: 0x8 rt: 0x9 i: 0
+ r rs: 8 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xbfc00240 rt: 0x20
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00240 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_READ @ 0xbfc00240 wdata 0 be 0x1> off: 0 sign_ext: 0x1 dest: gp+0x9
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp valid no error rdata 0x69782000>, 0)
+mips0 setData: <DataRsp valid no error rdata 0x69782000> off: 0 sign_ext: 0x1 dest: r_gp+0x9
+mips0 setData: <DataRsp valid no error rdata 0x69782000> off: 0 count: 0x1 le: 0 old: 0x20 from_mem: 0x69782000 mask: 0xffffffff new_data: 0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0x9 rt: 0 i: 0x5
+ r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00240 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003e0 m_ifetch_addr: 0xbfc003cc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003cc NPC: 0xbfc003e0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00240 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 m_next_pc: 0xbfc003e0 m_jump_pc: 0xbfc003e4 m_ifetch_addr: 0xbfc003e0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3e00008>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003e0 NPC: 0xbfc003e4 Ins: 0x3e00008
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x1f rt: 0 i: 0x8
+ r rs: 31 rt: 0 rd: 0 sh: 0 func: 0x8
+ V rs: 0xbfc001a4 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00240 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 m_next_pc: 0xbfc003e4 m_jump_pc: 0xbfc001a4 m_ifetch_addr: 0xbfc003e4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+ mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003e4 NPC: 0xbfc001a4 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00240 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 m_next_pc: 0xbfc001a4 m_jump_pc: 0xbfc001a8 m_ifetch_addr: 0xbfc001a4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x40044000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc001a4 NPC: 0xbfc001a8 Ins: 0x40044000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x10 (cop0)
+ i rs: 0 rt: 0x4 i: 0x4000
+ r rs: 0 rt: 4 rd: 8 sh: 0 func: 0
+ V rs: 0 rt: 0xbfc00239
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00239 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00240 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 m_next_pc: 0xbfc001a8 m_jump_pc: 0xbfc001ac m_ifetch_addr: 0xbfc001a8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xff000fa>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc001a8 NPC: 0xbfc001ac Ins: 0xff000fa
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x3 (jal)
+ i rs: 0x1f rt: 0x10 i: 0xfa
+ r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x3a
+ V rs: 0xbfc001a4 rt: 0xdeac
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00240 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001a4
+mips0 m_next_pc: 0xbfc001ac m_jump_pc: 0xbfc003e8 m_ifetch_addr: 0xbfc001ac
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc001ac NPC: 0xbfc003e8 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00240 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc003e8 m_jump_pc: 0xbfc003ec m_ifetch_addr: 0xbfc003e8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x804021>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003e8 NPC: 0xbfc003ec Ins: 0x804021
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x4 rt: 0 i: 0x4021
+ r rs: 4 rt: 0 rd: 8 sh: 0 func: 0x21
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00240 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc003ec m_jump_pc: 0xbfc003f0 m_ifetch_addr: 0xbfc003ec
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x24090030>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003ec NPC: 0xbfc003f0 Ins: 0x24090030
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0 rt: 0x9 i: 0x30
+ r rs: 0 rt: 9 rd: 0 sh: 0 func: 0x30
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc003f0 m_jump_pc: 0xbfc003f4 m_ifetch_addr: 0xbfc003f0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa3490000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003f0 NPC: 0xbfc003f4 Ins: 0xa3490000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0x9 i: 0
+ r rs: 26 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000030 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc003f4 m_jump_pc: 0xbfc003f8 m_ifetch_addr: 0xbfc003f4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x24090078>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc003f4 NPC: 0xbfc003f8 Ins: 0x24090078
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0 rt: 0x9 i: 0x78
+ r rs: 0 rt: 9 rd: 0 sh: 1 func: 0x38
+ V rs: 0 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000030 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc003f8 m_jump_pc: 0xbfc003fc m_ifetch_addr: 0xbfc003f8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa3490000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003f8 NPC: 0xbfc003fc Ins: 0xa3490000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0x9 i: 0
+ r rs: 26 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x78
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000078 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x78 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc003fc m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc003fc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x24090008>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc003fc NPC: 0xbfc00400 Ins: 0x24090008
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0 rt: 0x9 i: 0x8
+ r rs: 0 rt: 9 rd: 0 sh: 0 func: 0x8
+ V rs: 0 rt: 0x78
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000078 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c0af000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0xa i: 0xf000
+ r rs: 0 rt: 10 rd: 30 sh: 0 func: 0
+ V rs: 0 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000008 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x10a5024>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x8 rt: 0xa i: 0x5024
+ r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24
+ V rs: 0 rt: 0xf0000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000008 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa5702>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0xa i: 0x5702
+ r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000008 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+0mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x294b000a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xa (slti)
+ i rs: 0xa rt: 0xb i: 0xa
+ r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa
+ V rs: 0 rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000008 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11600004>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0xb rt: 0 i: 0x4
+ r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4
+ V rs: 0x1 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000008 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000008 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x214a0030>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0xa rt: 0xa i: 0x30
+ r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000008 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0010a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0x10a
+ r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa
+ V rs: 0xbfc001b0 rt: 0xdeac
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000008 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000008 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa34a0000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0xa i: 0
+ r rs: 26 rt: 10 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000008 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2129ffff>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0x9 rt: 0x9 i: 0xffff
+ r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f
+ V rs: 0x8 rt: 0x8
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000008 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x1d20fff3>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x7 (bgtz)
+ i rs: 0x9 rt: 0 i: 0xfff3
+ r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33
+ V rs: 0x7 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000007 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x84100>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0x8 i: 0x4100
+ r rs: 0 rt: 8 rd: 8 sh: 4 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000007 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+xmips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c0af000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0xa i: 0xf000
+ r rs: 0 rt: 10 rd: 30 sh: 0 func: 0
+ V rs: 0 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000007 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x10a5024>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x8 rt: 0xa i: 0x5024
+ r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24
+ V rs: 0 rt: 0xf0000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000007 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa5702>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0xa i: 0x5702
+ r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000007 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x294b000a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xa (slti)
+ i rs: 0xa rt: 0xb i: 0xa
+ r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa
+ V rs: 0 rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000007 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11600004>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0xb rt: 0 i: 0x4
+ r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4
+ V rs: 0x1 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000007 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000007 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x214a0030>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0xa rt: 0xa i: 0x30
+ r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000007 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0010a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0x10a
+ r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa
+ V rs: 0xbfc001b0 rt: 0xdeac
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000007 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000007 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa34a0000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0xa i: 0
+ r rs: 26 rt: 10 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000007 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+0mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2129ffff>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0x9 rt: 0x9 i: 0xffff
+ r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f
+ V rs: 0x7 rt: 0x7
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000007 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x1d20fff3>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x7 (bgtz)
+ i rs: 0x9 rt: 0 i: 0xfff3
+ r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33
+ V rs: 0x6 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000006 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x84100>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0x8 i: 0x4100
+ r rs: 0 rt: 8 rd: 8 sh: 4 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000006 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c0af000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0xa i: 0xf000
+ r rs: 0 rt: 10 rd: 30 sh: 0 func: 0
+ V rs: 0 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000006 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x10a5024>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x8 rt: 0xa i: 0x5024
+ r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24
+ V rs: 0 rt: 0xf0000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000006 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa5702>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0xa i: 0x5702
+ r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000006 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x294b000a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xa (slti)
+ i rs: 0xa rt: 0xb i: 0xa
+ r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa
+ V rs: 0 rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000006 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11600004>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0xb rt: 0 i: 0x4
+ r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4
+ V rs: 0x1 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000006 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000006 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x214a0030>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0xa rt: 0xa i: 0x30
+ r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000006 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+0mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0010a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0x10a
+ r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa
+ V rs: 0xbfc001b0 rt: 0xdeac
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000006 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000006 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa34a0000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0xa i: 0
+ r rs: 26 rt: 10 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000006 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2129ffff>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0x9 rt: 0x9 i: 0xffff
+ r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f
+ V rs: 0x6 rt: 0x6
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000006 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x1d20fff3>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x7 (bgtz)
+ i rs: 0x9 rt: 0 i: 0xfff3
+ r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33
+ V rs: 0x5 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000005 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x84100>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0x8 i: 0x4100
+ r rs: 0 rt: 8 rd: 8 sh: 4 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000005 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c0af000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0xa i: 0xf000
+ r rs: 0 rt: 10 rd: 30 sh: 0 func: 0
+ V rs: 0 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000005 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x10a5024>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x8 rt: 0xa i: 0x5024
+ r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24
+ V rs: 0 rt: 0xf0000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000005 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa5702>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0xa i: 0x5702
+ r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000005 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x294b000a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xa (slti)
+ i rs: 0xa rt: 0xb i: 0xa
+ r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa
+ V rs: 0 rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000005 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+0mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11600004>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0xb rt: 0 i: 0x4
+ r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4
+ V rs: 0x1 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000005 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000005 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x214a0030>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0xa rt: 0xa i: 0x30
+ r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000005 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0010a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0x10a
+ r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa
+ V rs: 0xbfc001b0 rt: 0xdeac
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000005 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000005 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa34a0000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0xa i: 0
+ r rs: 26 rt: 10 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000005 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2129ffff>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0x9 rt: 0x9 i: 0xffff
+ r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f
+ V rs: 0x5 rt: 0x5
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000005 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x1d20fff3>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x7 (bgtz)
+ i rs: 0x9 rt: 0 i: 0xfff3
+ r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33
+ V rs: 0x4 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x84100>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0x8 i: 0x4100
+ r rs: 0 rt: 8 rd: 8 sh: 4 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c0af000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0xa i: 0xf000
+ r rs: 0 rt: 10 rd: 30 sh: 0 func: 0
+ V rs: 0 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x10a5024>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x8 rt: 0xa i: 0x5024
+ r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24
+ V rs: 0 rt: 0xf0000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000004 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa5702>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0xa i: 0x5702
+ r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000004 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+0mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x294b000a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xa (slti)
+ i rs: 0xa rt: 0xb i: 0xa
+ r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa
+ V rs: 0 rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000004 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11600004>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0xb rt: 0 i: 0x4
+ r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4
+ V rs: 0x1 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000004 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000004 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x214a0030>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0xa rt: 0xa i: 0x30
+ r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000004 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0010a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0x10a
+ r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa
+ V rs: 0xbfc001b0 rt: 0xdeac
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa34a0000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0xa i: 0
+ r rs: 26 rt: 10 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2129ffff>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0x9 rt: 0x9 i: 0xffff
+ r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f
+ V rs: 0x4 rt: 0x4
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x1d20fff3>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x7 (bgtz)
+ i rs: 0x9 rt: 0 i: 0xfff3
+ r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33
+ V rs: 0x3 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x84100>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0x8 i: 0x4100
+ r rs: 0 rt: 8 rd: 8 sh: 4 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c0af000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0xa i: 0xf000
+ r rs: 0 rt: 10 rd: 30 sh: 0 func: 0
+ V rs: 0 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x10a5024>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x8 rt: 0xa i: 0x5024
+ r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24
+ V rs: 0 rt: 0xf0000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000003 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa5702>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0xa i: 0x5702
+ r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000003 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+0mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x294b000a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xa (slti)
+ i rs: 0xa rt: 0xb i: 0xa
+ r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa
+ V rs: 0 rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000003 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11600004>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0xb rt: 0 i: 0x4
+ r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4
+ V rs: 0x1 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000003 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000003 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x214a0030>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0xa rt: 0xa i: 0x30
+ r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000003 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0010a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0x10a
+ r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa
+ V rs: 0xbfc001b0 rt: 0xdeac
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa34a0000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0xa i: 0
+ r rs: 26 rt: 10 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2129ffff>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0x9 rt: 0x9 i: 0xffff
+ r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f
+ V rs: 0x3 rt: 0x3
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x1d20fff3>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x7 (bgtz)
+ i rs: 0x9 rt: 0 i: 0xfff3
+ r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33
+ V rs: 0x2 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000002 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x84100>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0x8 i: 0x4100
+ r rs: 0 rt: 8 rd: 8 sh: 4 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000002 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c0af000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0xa i: 0xf000
+ r rs: 0 rt: 10 rd: 30 sh: 0 func: 0
+ V rs: 0 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000002 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x10a5024>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x8 rt: 0xa i: 0x5024
+ r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24
+ V rs: 0 rt: 0xf0000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000002 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa5702>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0xa i: 0x5702
+ r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000002 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+0mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x294b000a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xa (slti)
+ i rs: 0xa rt: 0xb i: 0xa
+ r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa
+ V rs: 0 rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000002 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11600004>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0xb rt: 0 i: 0x4
+ r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4
+ V rs: 0x1 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000002 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000002 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x214a0030>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0xa rt: 0xa i: 0x30
+ r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000002 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0010a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0x10a
+ r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa
+ V rs: 0xbfc001b0 rt: 0xdeac
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000002 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000002 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa34a0000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0xa i: 0
+ r rs: 26 rt: 10 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000002 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2129ffff>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0x9 rt: 0x9 i: 0xffff
+ r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f
+ V rs: 0x2 rt: 0x2
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000002 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x1d20fff3>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x7 (bgtz)
+ i rs: 0x9 rt: 0 i: 0xfff3
+ r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33
+ V rs: 0x1 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000001 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x84100>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0x8 i: 0x4100
+ r rs: 0 rt: 8 rd: 8 sh: 4 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000001 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c0af000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0xa i: 0xf000
+ r rs: 0 rt: 10 rd: 30 sh: 0 func: 0
+ V rs: 0 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000001 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x10a5024>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x8 rt: 0xa i: 0x5024
+ r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24
+ V rs: 0 rt: 0xf0000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000001 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa5702>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0xa i: 0x5702
+ r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000001 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+0mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x294b000a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xa (slti)
+ i rs: 0xa rt: 0xb i: 0xa
+ r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa
+ V rs: 0 rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000001 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11600004>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0xb rt: 0 i: 0x4
+ r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4
+ V rs: 0x1 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000001 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000001 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x214a0030>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0xa rt: 0xa i: 0x30
+ r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000001 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0010a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0x10a
+ r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa
+ V rs: 0xbfc001b0 rt: 0xdeac
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000001 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000001 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa34a0000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0xa i: 0
+ r rs: 26 rt: 10 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000001 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2129ffff>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0x9 rt: 0x9 i: 0xffff
+ r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f
+ V rs: 0x1 rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000001 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x1d20fff3>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x7 (bgtz)
+ i rs: 0x9 rt: 0 i: 0xfff3
+ r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00438 m_ifetch_addr: 0xbfc00434
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x84100>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00434 NPC: 0xbfc00438 Ins: 0x84100
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0x8 i: 0x4100
+ r rs: 0 rt: 8 rd: 8 sh: 4 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc00438 m_jump_pc: 0xbfc0043c m_ifetch_addr: 0xbfc00438
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3e00008>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00438 NPC: 0xbfc0043c Ins: 0x3e00008
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x1f rt: 0 i: 0x8
+ r rs: 31 rt: 0 rd: 0 sh: 0 func: 0x8
+ V rs: 0xbfc001b0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc0043c m_jump_pc: 0xbfc001b0 m_ifetch_addr: 0xbfc0043c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0043c NPC: 0xbfc001b0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc001b0 m_jump_pc: 0xbfc001b4 m_ifetch_addr: 0xbfc001b0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c04bfc0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc001b0 NPC: 0xbfc001b4 Ins: 0x3c04bfc0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0x4 i: 0xbfc0
+ r rs: 0 rt: 4 rd: 23 sh: 31 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc001b4 m_jump_pc: 0xbfc001b8 m_ifetch_addr: 0xbfc001b4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+0mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x24840241>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc001b4 NPC: 0xbfc001b8 Ins: 0x24840241
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0x4 rt: 0x4 i: 0x241
+ r rs: 4 rt: 4 rd: 0 sh: 9 func: 0x1
+ V rs: 0xbfc00000 rt: 0xbfc00000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc001b8 m_jump_pc: 0xbfc001bc m_ifetch_addr: 0xbfc001b8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xff000f0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc001b8 NPC: 0xbfc001bc Ins: 0xff000f0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x3 (jal)
+ i rs: 0x1f rt: 0x10 i: 0xf0
+ r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x30
+ V rs: 0xbfc001b0 rt: 0xdeac
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001b0
+mips0 m_next_pc: 0xbfc001bc m_jump_pc: 0xbfc003c0 m_ifetch_addr: 0xbfc001bc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc001bc NPC: 0xbfc003c0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 m_next_pc: 0xbfc003c0 m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003c0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x804021>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c0 NPC: 0xbfc003c4 Ins: 0x804021
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x4 rt: 0 i: 0x4021
+ r rs: 4 rt: 0 rd: 8 sh: 0 func: 0x21
+ V rs: 0xbfc00241 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x81090000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x20 (lb)
+ i rs: 0x8 rt: 0x9 i: 0
+ r rs: 8 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xbfc00241 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00241 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_READ @ 0xbfc00240 wdata 0 be 0x2> off: 0x1 sign_ext: 0x1 dest: gp+0x9
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp valid no error rdata 0x69782000>, 0)
+mips0 setData: <DataRsp valid no error rdata 0x69782000> off: 0 sign_ext: 0x1 dest: r_gp+0x9
+mips0 setData: <DataRsp valid no error rdata 0x69782000> off: 0 count: 0x1 le: 0x1 old: 0 from_mem: 0x69782000 mask: 0xffffffff new_data: 0x20
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0x9 rt: 0 i: 0x5
+ r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5
+ V rs: 0x20 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00241 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00241 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa3490000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0x9 i: 0
+ r rs: 26 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x20
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00241 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x20 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0x8 rt: 0x8 i: 0x1
+ r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1
+ V rs: 0xbfc00241 rt: 0xbfc00241
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00241 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf000f1>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0xf1
+ r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31
+ V rs: 0xbfc001c0 rt: 0xdeac
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00242 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00242 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x81090000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x20 (lb)
+ i rs: 0x8 rt: 0x9 i: 0
+ r rs: 8 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xbfc00242 rt: 0x20
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00242 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_READ @ 0xbfc00240 wdata 0 be 0x4> off: 0x2 sign_ext: 0x1 dest: gp+0x9
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp valid no error rdata 0x69782000>, 0)
+mips0 setData: <DataRsp valid no error rdata 0x69782000> off: 0 sign_ext: 0x1 dest: r_gp+0x9
+mips0 setData: <DataRsp valid no error rdata 0x69782000> off: 0 count: 0x1 le: 0x2 old: 0x20 from_mem: 0x69782000 mask: 0xffffffff new_data: 0x78
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1
+ mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0x9 rt: 0 i: 0x5
+ r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5
+ V rs: 0x78 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00242 09: 00000078 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00242 09: 00000078 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa3490000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0x9 i: 0
+ r rs: 26 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x78
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00242 09: 00000078 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x78 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0x8 rt: 0x8 i: 0x1
+ r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1
+ V rs: 0xbfc00242 rt: 0xbfc00242
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00242 09: 00000078 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf000f1>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0xf1
+ r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31
+ V rs: 0xbfc001c0 rt: 0xdeac
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00243 09: 00000078 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00243 09: 00000078 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x81090000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x20 (lb)
+ i rs: 0x8 rt: 0x9 i: 0
+ r rs: 8 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xbfc00243 rt: 0x78
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00243 09: 00000078 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_READ @ 0xbfc00240 wdata 0 be 0x8> off: 0x3 sign_ext: 0x1 dest: gp+0x9
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp valid no error rdata 0x69782000>, 0)
+mips0 setData: <DataRsp valid no error rdata 0x69782000> off: 0 sign_ext: 0x1 dest: r_gp+0x9
+mips0 setData: <DataRsp valid no error rdata 0x69782000> off: 0 count: 0x1 le: 0x3 old: 0x78 from_mem: 0x69782000 mask: 0xffffffff new_data: 0x69
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0x9 rt: 0 i: 0x5
+ r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5
+ V rs: 0x69 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00243 09: 00000069 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+xmips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00243 09: 00000069 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa3490000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0x9 i: 0
+ r rs: 26 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x69
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00243 09: 00000069 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x69 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0x8 rt: 0x8 i: 0x1
+ r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1
+ V rs: 0xbfc00243 rt: 0xbfc00243
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00243 09: 00000069 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf000f1>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0xf1
+ r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31
+ V rs: 0xbfc001c0 rt: 0xdeac
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00244 09: 00000069 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00244 09: 00000069 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x81090000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x20 (lb)
+ i rs: 0x8 rt: 0x9 i: 0
+ r rs: 8 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xbfc00244 rt: 0x69
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00244 09: 00000069 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_READ @ 0xbfc00244 wdata 0 be 0x1> off: 0 sign_ext: 0x1 dest: gp+0x9
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp valid no error rdata 0x207563>, 0)
+mips0 setData: <DataRsp valid no error rdata 0x207563> off: 0 sign_ext: 0x1 dest: r_gp+0x9
+mips0 setData: <DataRsp valid no error rdata 0x207563> off: 0 count: 0x1 le: 0 old: 0x69 from_mem: 0x207563 mask: 0xffffffff new_data: 0x63
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0x9 rt: 0 i: 0x5
+ r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5
+ V rs: 0x63 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00244 09: 00000063 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00244 09: 00000063 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+imips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa3490000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0x9 i: 0
+ r rs: 26 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x63
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00244 09: 00000063 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x63 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0x8 rt: 0x8 i: 0x1
+ r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1
+ V rs: 0xbfc00244 rt: 0xbfc00244
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00244 09: 00000063 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf000f1>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0xf1
+ r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31
+ V rs: 0xbfc001c0 rt: 0xdeac
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00245 09: 00000063 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00245 09: 00000063 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x81090000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x20 (lb)
+ i rs: 0x8 rt: 0x9 i: 0
+ r rs: 8 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xbfc00245 rt: 0x63
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00245 09: 00000063 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_READ @ 0xbfc00244 wdata 0 be 0x2> off: 0x1 sign_ext: 0x1 dest: gp+0x9
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp valid no error rdata 0x207563>, 0)
+mips0 setData: <DataRsp valid no error rdata 0x207563> off: 0 sign_ext: 0x1 dest: r_gp+0x9
+mips0 setData: <DataRsp valid no error rdata 0x207563> off: 0 count: 0x1 le: 0x1 old: 0x63 from_mem: 0x207563 mask: 0xffffffff new_data: 0x75
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0x9 rt: 0 i: 0x5
+ r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5
+ V rs: 0x75 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00245 09: 00000075 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00245 09: 00000075 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa3490000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0x9 i: 0
+ r rs: 26 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x75
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00245 09: 00000075 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x75 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+cmips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0x8 rt: 0x8 i: 0x1
+ r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1
+ V rs: 0xbfc00245 rt: 0xbfc00245
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00245 09: 00000075 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf000f1>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0xf1
+ r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31
+ V rs: 0xbfc001c0 rt: 0xdeac
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00246 09: 00000075 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00246 09: 00000075 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x81090000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x20 (lb)
+ i rs: 0x8 rt: 0x9 i: 0
+ r rs: 8 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xbfc00246 rt: 0x75
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00246 09: 00000075 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_READ @ 0xbfc00244 wdata 0 be 0x4> off: 0x2 sign_ext: 0x1 dest: gp+0x9
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp valid no error rdata 0x207563>, 0)
+mips0 setData: <DataRsp valid no error rdata 0x207563> off: 0 sign_ext: 0x1 dest: r_gp+0x9
+mips0 setData: <DataRsp valid no error rdata 0x207563> off: 0 count: 0x1 le: 0x2 old: 0x75 from_mem: 0x207563 mask: 0xffffffff new_data: 0x20
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0x9 rt: 0 i: 0x5
+ r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5
+ V rs: 0x20 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00246 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003d0 m_ifetch_addr: 0xbfc003cc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003cc NPC: 0xbfc003d0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00246 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 m_next_pc: 0xbfc003d0 m_jump_pc: 0xbfc003d4 m_ifetch_addr: 0xbfc003d0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa3490000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d0 NPC: 0xbfc003d4 Ins: 0xa3490000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0x9 i: 0
+ r rs: 26 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x20
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00246 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x20 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc003d4 m_jump_pc: 0xbfc003d8 m_ifetch_addr: 0xbfc003d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+umips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x25080001>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc003d4 NPC: 0xbfc003d8 Ins: 0x25080001
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0x8 rt: 0x8 i: 0x1
+ r rs: 8 rt: 8 rd: 0 sh: 0 func: 0x1
+ V rs: 0xbfc00246 rt: 0xbfc00246
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00246 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 m_next_pc: 0xbfc003d8 m_jump_pc: 0xbfc003dc m_ifetch_addr: 0xbfc003d8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf000f1>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003d8 NPC: 0xbfc003dc Ins: 0xbf000f1
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0xf1
+ r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x31
+ V rs: 0xbfc001c0 rt: 0xdeac
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00247 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 m_next_pc: 0xbfc003dc m_jump_pc: 0xbfc003c4 m_ifetch_addr: 0xbfc003dc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003dc NPC: 0xbfc003c4 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00247 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 m_next_pc: 0xbfc003c4 m_jump_pc: 0xbfc003c8 m_ifetch_addr: 0xbfc003c4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x81090000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c4 NPC: 0xbfc003c8 Ins: 0x81090000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x20 (lb)
+ i rs: 0x8 rt: 0x9 i: 0
+ r rs: 8 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xbfc00247 rt: 0x20
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00247 09: 00000020 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_READ @ 0xbfc00244 wdata 0 be 0x8> off: 0x3 sign_ext: 0x1 dest: gp+0x9
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc003c8 m_jump_pc: 0xbfc003cc m_ifetch_addr: 0xbfc003c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp valid no error rdata 0x207563>, 0)
+mips0 setData: <DataRsp valid no error rdata 0x207563> off: 0 sign_ext: 0x1 dest: r_gp+0x9
+mips0 setData: <DataRsp valid no error rdata 0x207563> off: 0 count: 0x1 le: 0x3 old: 0x20 from_mem: 0x207563 mask: 0xffffffff new_data: 0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0 time_spent=0x1
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11200005>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003c8 NPC: 0xbfc003cc Ins: 0x11200005
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0x9 rt: 0 i: 0x5
+ r rs: 9 rt: 0 rd: 0 sh: 0 func: 0x5
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00247 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 m_next_pc: 0xbfc003cc m_jump_pc: 0xbfc003e0 m_ifetch_addr: 0xbfc003cc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003cc NPC: 0xbfc003e0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00247 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 m_next_pc: 0xbfc003e0 m_jump_pc: 0xbfc003e4 m_ifetch_addr: 0xbfc003e0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3e00008>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003e0 NPC: 0xbfc003e4 Ins: 0x3e00008
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x1f rt: 0 i: 0x8
+ r rs: 31 rt: 0 rd: 0 sh: 0 func: 0x8
+ V rs: 0xbfc001c0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00247 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 m_next_pc: 0xbfc003e4 m_jump_pc: 0xbfc001c0 m_ifetch_addr: 0xbfc003e4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+ mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003e4 NPC: 0xbfc001c0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00247 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 m_next_pc: 0xbfc001c0 m_jump_pc: 0xbfc001c4 m_ifetch_addr: 0xbfc001c0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c08d820>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc001c0 NPC: 0xbfc001c4 Ins: 0x3c08d820
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0x8 i: 0xd820
+ r rs: 0 rt: 8 rd: 27 sh: 0 func: 0x20
+ V rs: 0 rt: 0xbfc00247
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: bfc00247 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 m_next_pc: 0xbfc001c4 m_jump_pc: 0xbfc001c8 m_ifetch_addr: 0xbfc001c4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x8d040780>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc001c4 NPC: 0xbfc001c8 Ins: 0x8d040780
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x23 (lw)
+ i rs: 0x8 rt: 0x4 i: 0x780
+ r rs: 8 rt: 4 rd: 0 sh: 30 func: 0
+ V rs: 0xd8200000 rt: 0xbfc00241
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: bfc00241 05: 00000000 06: 00000000 07: 00000000
+ 08: d8200000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_READ @ 0xd8200780 wdata 0 be 0xf> off: 0 sign_ext: 0 dest: gp+0x4
+mips0 m_next_pc: 0xbfc001c8 m_jump_pc: 0xbfc001cc m_ifetch_addr: 0xbfc001c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xff000fa>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc001c8 m_jump_pc: 0xbfc001cc m_ifetch_addr: 0xbfc001c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xff000fa>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc001c8 m_jump_pc: 0xbfc001cc m_ifetch_addr: 0xbfc001c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xff000fa>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc001c8 m_jump_pc: 0xbfc001cc m_ifetch_addr: 0xbfc001c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xff000fa>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc001c8 m_jump_pc: 0xbfc001cc m_ifetch_addr: 0xbfc001c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xff000fa>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc001c8 m_jump_pc: 0xbfc001cc m_ifetch_addr: 0xbfc001c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xff000fa>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc001c8 m_jump_pc: 0xbfc001cc m_ifetch_addr: 0xbfc001c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xff000fa>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc001c8 m_jump_pc: 0xbfc001cc m_ifetch_addr: 0xbfc001c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xff000fa>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc001c8 m_jump_pc: 0xbfc001cc m_ifetch_addr: 0xbfc001c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xff000fa>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc001c8 m_jump_pc: 0xbfc001cc m_ifetch_addr: 0xbfc001c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xff000fa>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc001c8 m_jump_pc: 0xbfc001cc m_ifetch_addr: 0xbfc001c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xff000fa>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc001c8 m_jump_pc: 0xbfc001cc m_ifetch_addr: 0xbfc001c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xff000fa>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc001c8 m_jump_pc: 0xbfc001cc m_ifetch_addr: 0xbfc001c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xff000fa>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x4
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 count: 0x4 le: 0 old: 0xbfc00241 from_mem: 0 mask: 0xffffffff new_data: 0
+mips0 PC: 0xbfc001c8 NPC: 0xbfc001cc Ins: 0xff000fa
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x3 (jal)
+ i rs: 0x1f rt: 0x10 i: 0xfa
+ r rs: 31 rt: 16 rd: 0 sh: 3 func: 0x3a
+ V rs: 0xbfc001c0 rt: 0xdeac
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: d8200000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001c0
+mips0 m_next_pc: 0xbfc001cc m_jump_pc: 0xbfc003e8 m_ifetch_addr: 0xbfc001cc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc001cc NPC: 0xbfc003e8 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: d8200000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc003e8 m_jump_pc: 0xbfc003ec m_ifetch_addr: 0xbfc003e8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x804021>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003e8 NPC: 0xbfc003ec Ins: 0x804021
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x4 rt: 0 i: 0x4021
+ r rs: 4 rt: 0 rd: 8 sh: 0 func: 0x21
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: d8200000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc003ec m_jump_pc: 0xbfc003f0 m_ifetch_addr: 0xbfc003ec
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x24090030>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003ec NPC: 0xbfc003f0 Ins: 0x24090030
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0 rt: 0x9 i: 0x30
+ r rs: 0 rt: 9 rd: 0 sh: 0 func: 0x30
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc003f0 m_jump_pc: 0xbfc003f4 m_ifetch_addr: 0xbfc003f0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa3490000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003f0 NPC: 0xbfc003f4 Ins: 0xa3490000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0x9 i: 0
+ r rs: 26 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000030 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc003f4 m_jump_pc: 0xbfc003f8 m_ifetch_addr: 0xbfc003f4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x24090078>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc003f4 NPC: 0xbfc003f8 Ins: 0x24090078
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0 rt: 0x9 i: 0x78
+ r rs: 0 rt: 9 rd: 0 sh: 1 func: 0x38
+ V rs: 0 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000030 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc003f8 m_jump_pc: 0xbfc003fc m_ifetch_addr: 0xbfc003f8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa3490000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc003f8 NPC: 0xbfc003fc Ins: 0xa3490000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0x9 i: 0
+ r rs: 26 rt: 9 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x78
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000078 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x78 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc003fc m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc003fc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x24090008>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc003fc NPC: 0xbfc00400 Ins: 0x24090008
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0 rt: 0x9 i: 0x8
+ r rs: 0 rt: 9 rd: 0 sh: 0 func: 0x8
+ V rs: 0 rt: 0x78
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000078 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c0af000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0xa i: 0xf000
+ r rs: 0 rt: 10 rd: 30 sh: 0 func: 0
+ V rs: 0 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000008 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x10a5024>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x8 rt: 0xa i: 0x5024
+ r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24
+ V rs: 0 rt: 0xf0000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000008 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa5702>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0xa i: 0x5702
+ r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000008 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+0mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x294b000a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xa (slti)
+ i rs: 0xa rt: 0xb i: 0xa
+ r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa
+ V rs: 0 rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000008 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11600004>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0xb rt: 0 i: 0x4
+ r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4
+ V rs: 0x1 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000008 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000008 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x214a0030>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0xa rt: 0xa i: 0x30
+ r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000008 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0010a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0x10a
+ r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa
+ V rs: 0xbfc001d0 rt: 0xdeac
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000008 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000008 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa34a0000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0xa i: 0
+ r rs: 26 rt: 10 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000008 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2129ffff>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0x9 rt: 0x9 i: 0xffff
+ r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f
+ V rs: 0x8 rt: 0x8
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000008 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x1d20fff3>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x7 (bgtz)
+ i rs: 0x9 rt: 0 i: 0xfff3
+ r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33
+ V rs: 0x7 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000007 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x84100>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0x8 i: 0x4100
+ r rs: 0 rt: 8 rd: 8 sh: 4 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000007 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+xmips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c0af000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0xa i: 0xf000
+ r rs: 0 rt: 10 rd: 30 sh: 0 func: 0
+ V rs: 0 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000007 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x10a5024>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x8 rt: 0xa i: 0x5024
+ r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24
+ V rs: 0 rt: 0xf0000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000007 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa5702>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0xa i: 0x5702
+ r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000007 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x294b000a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xa (slti)
+ i rs: 0xa rt: 0xb i: 0xa
+ r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa
+ V rs: 0 rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000007 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11600004>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0xb rt: 0 i: 0x4
+ r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4
+ V rs: 0x1 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000007 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000007 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x214a0030>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0xa rt: 0xa i: 0x30
+ r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000007 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0010a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0x10a
+ r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa
+ V rs: 0xbfc001d0 rt: 0xdeac
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000007 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000007 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa34a0000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0xa i: 0
+ r rs: 26 rt: 10 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000007 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+0mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2129ffff>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0x9 rt: 0x9 i: 0xffff
+ r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f
+ V rs: 0x7 rt: 0x7
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000007 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x1d20fff3>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x7 (bgtz)
+ i rs: 0x9 rt: 0 i: 0xfff3
+ r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33
+ V rs: 0x6 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000006 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x84100>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0x8 i: 0x4100
+ r rs: 0 rt: 8 rd: 8 sh: 4 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000006 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c0af000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0xa i: 0xf000
+ r rs: 0 rt: 10 rd: 30 sh: 0 func: 0
+ V rs: 0 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000006 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x10a5024>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x8 rt: 0xa i: 0x5024
+ r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24
+ V rs: 0 rt: 0xf0000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000006 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa5702>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0xa i: 0x5702
+ r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000006 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x294b000a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xa (slti)
+ i rs: 0xa rt: 0xb i: 0xa
+ r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa
+ V rs: 0 rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000006 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11600004>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0xb rt: 0 i: 0x4
+ r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4
+ V rs: 0x1 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000006 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000006 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x214a0030>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0xa rt: 0xa i: 0x30
+ r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000006 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+0mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0010a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0x10a
+ r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa
+ V rs: 0xbfc001d0 rt: 0xdeac
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000006 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000006 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa34a0000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0xa i: 0
+ r rs: 26 rt: 10 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000006 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2129ffff>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0x9 rt: 0x9 i: 0xffff
+ r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f
+ V rs: 0x6 rt: 0x6
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000006 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x1d20fff3>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x7 (bgtz)
+ i rs: 0x9 rt: 0 i: 0xfff3
+ r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33
+ V rs: 0x5 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000005 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x84100>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0x8 i: 0x4100
+ r rs: 0 rt: 8 rd: 8 sh: 4 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000005 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c0af000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0xa i: 0xf000
+ r rs: 0 rt: 10 rd: 30 sh: 0 func: 0
+ V rs: 0 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000005 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x10a5024>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x8 rt: 0xa i: 0x5024
+ r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24
+ V rs: 0 rt: 0xf0000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000005 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa5702>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0xa i: 0x5702
+ r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000005 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x294b000a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xa (slti)
+ i rs: 0xa rt: 0xb i: 0xa
+ r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa
+ V rs: 0 rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000005 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+0mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11600004>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0xb rt: 0 i: 0x4
+ r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4
+ V rs: 0x1 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000005 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000005 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x214a0030>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0xa rt: 0xa i: 0x30
+ r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000005 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0010a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0x10a
+ r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa
+ V rs: 0xbfc001d0 rt: 0xdeac
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000005 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000005 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa34a0000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0xa i: 0
+ r rs: 26 rt: 10 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000005 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2129ffff>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0x9 rt: 0x9 i: 0xffff
+ r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f
+ V rs: 0x5 rt: 0x5
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000005 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x1d20fff3>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x7 (bgtz)
+ i rs: 0x9 rt: 0 i: 0xfff3
+ r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33
+ V rs: 0x4 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x84100>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0x8 i: 0x4100
+ r rs: 0 rt: 8 rd: 8 sh: 4 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c0af000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0xa i: 0xf000
+ r rs: 0 rt: 10 rd: 30 sh: 0 func: 0
+ V rs: 0 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x10a5024>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x8 rt: 0xa i: 0x5024
+ r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24
+ V rs: 0 rt: 0xf0000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000004 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa5702>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0xa i: 0x5702
+ r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000004 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+0mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x294b000a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xa (slti)
+ i rs: 0xa rt: 0xb i: 0xa
+ r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa
+ V rs: 0 rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000004 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11600004>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0xb rt: 0 i: 0x4
+ r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4
+ V rs: 0x1 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000004 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000004 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x214a0030>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0xa rt: 0xa i: 0x30
+ r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000004 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0010a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0x10a
+ r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa
+ V rs: 0xbfc001d0 rt: 0xdeac
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa34a0000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0xa i: 0
+ r rs: 26 rt: 10 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2129ffff>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0x9 rt: 0x9 i: 0xffff
+ r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f
+ V rs: 0x4 rt: 0x4
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000004 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x1d20fff3>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x7 (bgtz)
+ i rs: 0x9 rt: 0 i: 0xfff3
+ r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33
+ V rs: 0x3 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x84100>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0x8 i: 0x4100
+ r rs: 0 rt: 8 rd: 8 sh: 4 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c0af000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0xa i: 0xf000
+ r rs: 0 rt: 10 rd: 30 sh: 0 func: 0
+ V rs: 0 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x10a5024>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x8 rt: 0xa i: 0x5024
+ r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24
+ V rs: 0 rt: 0xf0000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000003 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa5702>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0xa i: 0x5702
+ r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000003 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+0mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x294b000a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xa (slti)
+ i rs: 0xa rt: 0xb i: 0xa
+ r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa
+ V rs: 0 rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000003 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11600004>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0xb rt: 0 i: 0x4
+ r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4
+ V rs: 0x1 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000003 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000003 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x214a0030>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0xa rt: 0xa i: 0x30
+ r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000003 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0010a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0x10a
+ r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa
+ V rs: 0xbfc001d0 rt: 0xdeac
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa34a0000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0xa i: 0
+ r rs: 26 rt: 10 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2129ffff>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0x9 rt: 0x9 i: 0xffff
+ r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f
+ V rs: 0x3 rt: 0x3
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000003 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x1d20fff3>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x7 (bgtz)
+ i rs: 0x9 rt: 0 i: 0xfff3
+ r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33
+ V rs: 0x2 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000002 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x84100>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0x8 i: 0x4100
+ r rs: 0 rt: 8 rd: 8 sh: 4 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000002 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c0af000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0xa i: 0xf000
+ r rs: 0 rt: 10 rd: 30 sh: 0 func: 0
+ V rs: 0 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000002 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x10a5024>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x8 rt: 0xa i: 0x5024
+ r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24
+ V rs: 0 rt: 0xf0000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000002 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa5702>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0xa i: 0x5702
+ r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000002 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+0mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x294b000a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xa (slti)
+ i rs: 0xa rt: 0xb i: 0xa
+ r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa
+ V rs: 0 rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000002 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11600004>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0xb rt: 0 i: 0x4
+ r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4
+ V rs: 0x1 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000002 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000002 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x214a0030>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0xa rt: 0xa i: 0x30
+ r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000002 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0010a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0x10a
+ r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa
+ V rs: 0xbfc001d0 rt: 0xdeac
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000002 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000002 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa34a0000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0xa i: 0
+ r rs: 26 rt: 10 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000002 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2129ffff>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0x9 rt: 0x9 i: 0xffff
+ r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f
+ V rs: 0x2 rt: 0x2
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000002 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x1d20fff3>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x7 (bgtz)
+ i rs: 0x9 rt: 0 i: 0xfff3
+ r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33
+ V rs: 0x1 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000001 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00400 m_ifetch_addr: 0xbfc00434
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x84100>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00434 NPC: 0xbfc00400 Ins: 0x84100
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0x8 i: 0x4100
+ r rs: 0 rt: 8 rd: 8 sh: 4 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000001 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00400 m_jump_pc: 0xbfc00404 m_ifetch_addr: 0xbfc00400
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c0af000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00400 NPC: 0xbfc00404 Ins: 0x3c0af000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0xa i: 0xf000
+ r rs: 0 rt: 10 rd: 30 sh: 0 func: 0
+ V rs: 0 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000001 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00404 m_jump_pc: 0xbfc00408 m_ifetch_addr: 0xbfc00404
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x10a5024>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00404 NPC: 0xbfc00408 Ins: 0x10a5024
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x8 rt: 0xa i: 0x5024
+ r rs: 8 rt: 10 rd: 10 sh: 0 func: 0x24
+ V rs: 0 rt: 0xf0000000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000001 10: f0000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00408 m_jump_pc: 0xbfc0040c m_ifetch_addr: 0xbfc00408
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa5702>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00408 NPC: 0xbfc0040c Ins: 0xa5702
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0xa i: 0x5702
+ r rs: 0 rt: 10 rd: 10 sh: 28 func: 0x2
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000001 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc0040c m_jump_pc: 0xbfc00410 m_ifetch_addr: 0xbfc0040c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+0mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x294b000a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0040c NPC: 0xbfc00410 Ins: 0x294b000a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xa (slti)
+ i rs: 0xa rt: 0xb i: 0xa
+ r rs: 10 rt: 11 rd: 0 sh: 0 func: 0xa
+ V rs: 0 rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000001 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00410 m_jump_pc: 0xbfc00414 m_ifetch_addr: 0xbfc00410
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x11600004>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00410 NPC: 0xbfc00414 Ins: 0x11600004
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0xb rt: 0 i: 0x4
+ r rs: 11 rt: 0 rd: 0 sh: 0 func: 0x4
+ V rs: 0x1 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000001 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00414 m_jump_pc: 0xbfc00418 m_ifetch_addr: 0xbfc00414
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00414 NPC: 0xbfc00418 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000001 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00418 m_jump_pc: 0xbfc0041c m_ifetch_addr: 0xbfc00418
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x214a0030>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00418 NPC: 0xbfc0041c Ins: 0x214a0030
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0xa rt: 0xa i: 0x30
+ r rs: 10 rt: 10 rd: 0 sh: 0 func: 0x30
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000001 10: 00000000 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc0041c m_jump_pc: 0xbfc00420 m_ifetch_addr: 0xbfc0041c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0010a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0041c NPC: 0xbfc00420 Ins: 0xbf0010a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0x10a
+ r rs: 31 rt: 16 rd: 0 sh: 4 func: 0xa
+ V rs: 0xbfc001d0 rt: 0xdeac
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000001 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00420 m_jump_pc: 0xbfc00428 m_ifetch_addr: 0xbfc00420
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00420 NPC: 0xbfc00428 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000001 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00428 m_jump_pc: 0xbfc0042c m_ifetch_addr: 0xbfc00428
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa34a0000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00428 NPC: 0xbfc0042c Ins: 0xa34a0000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0xa i: 0
+ r rs: 26 rt: 10 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0x30
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000001 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0x30 be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc0042c m_jump_pc: 0xbfc00430 m_ifetch_addr: 0xbfc0042c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2129ffff>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc0042c NPC: 0xbfc00430 Ins: 0x2129ffff
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x8 (addi)
+ i rs: 0x9 rt: 0x9 i: 0xffff
+ r rs: 9 rt: 9 rd: 31 sh: 31 func: 0x3f
+ V rs: 0x1 rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000001 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00430 m_jump_pc: 0xbfc00434 m_ifetch_addr: 0xbfc00430
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x1d20fff3>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00430 NPC: 0xbfc00434 Ins: 0x1d20fff3
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x7 (bgtz)
+ i rs: 0x9 rt: 0 i: 0xfff3
+ r rs: 9 rt: 0 rd: 31 sh: 31 func: 0x33
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00434 m_jump_pc: 0xbfc00438 m_ifetch_addr: 0xbfc00434
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x84100>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00434 NPC: 0xbfc00438 Ins: 0x84100
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0x8 i: 0x4100
+ r rs: 0 rt: 8 rd: 8 sh: 4 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00438 m_jump_pc: 0xbfc0043c m_ifetch_addr: 0xbfc00438
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3e00008>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc00438 NPC: 0xbfc0043c Ins: 0x3e00008
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0x1f rt: 0 i: 0x8
+ r rs: 31 rt: 0 rd: 0 sh: 0 func: 0x8
+ V rs: 0xbfc001d0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc0043c m_jump_pc: 0xbfc001d0 m_ifetch_addr: 0xbfc0043c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc0043c NPC: 0xbfc001d0 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc001d0 m_jump_pc: 0xbfc001d4 m_ifetch_addr: 0xbfc001d0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2404000a>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc001d0 NPC: 0xbfc001d4 Ins: 0x2404000a
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0 rt: 0x4 i: 0xa
+ r rs: 0 rt: 4 rd: 0 sh: 0 func: 0xa
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000000 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc001d4 m_jump_pc: 0xbfc001d8 m_ifetch_addr: 0xbfc001d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+0mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xa3440000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc001d4 NPC: 0xbfc001d8 Ins: 0xa3440000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x28 (sb)
+ i rs: 0x1a rt: 0x4 i: 0
+ r rs: 26 rt: 4 rd: 0 sh: 0 func: 0
+ V rs: 0xd0200000 rt: 0xa
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 0000000a 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd0200000 wdata 0xa be 0x1> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc001d8 m_jump_pc: 0xbfc001dc m_ifetch_addr: 0xbfc001d8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x32530001>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc001d8 NPC: 0xbfc001dc Ins: 0x32530001
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xc (andi)
+ i rs: 0x12 rt: 0x13 i: 0x1
+ r rs: 18 rt: 19 rd: 0 sh: 0 func: 0x1
+ V rs: 0x3 rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 0000000a 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc001dc m_jump_pc: 0xbfc001e0 m_ifetch_addr: 0xbfc001dc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x12600002>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc001dc NPC: 0xbfc001e0 Ins: 0x12600002
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0x13 rt: 0 i: 0x2
+ r rs: 19 rt: 0 rd: 0 sh: 0 func: 0x2
+ V rs: 0x1 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 0000000a 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc001e0 m_jump_pc: 0xbfc001e4 m_ifetch_addr: 0xbfc001e0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc001e0 NPC: 0xbfc001e4 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 0000000a 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc001e4 m_jump_pc: 0xbfc001e8 m_ifetch_addr: 0xbfc001e4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x26100001>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc001e4 NPC: 0xbfc001e8 Ins: 0x26100001
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0x10 rt: 0x10 i: 0x1
+ r rs: 16 rt: 16 rd: 0 sh: 0 func: 0x1
+ V rs: 0xdeac rt: 0xdeac
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 0000000a 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc001e8 m_jump_pc: 0xbfc001ec m_ifetch_addr: 0xbfc001e8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x26520001>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc001e8 NPC: 0xbfc001ec Ins: 0x26520001
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0x12 rt: 0x12 i: 0x1
+ r rs: 18 rt: 18 rd: 0 sh: 0 func: 0x1
+ V rs: 0x3 rt: 0x3
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 0000000a 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dead 17: 00000000 18: 00000003 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc001ec m_jump_pc: 0xbfc001f0 m_ifetch_addr: 0xbfc001ec
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x24130184>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc001ec NPC: 0xbfc001f0 Ins: 0x24130184
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0 rt: 0x13 i: 0x184
+ r rs: 0 rt: 19 rd: 0 sh: 6 func: 0x4
+ V rs: 0 rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 0000000a 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dead 17: 00000000 18: 00000004 19: 00000001 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc001f0 m_jump_pc: 0xbfc001f4 m_ifetch_addr: 0xbfc001f0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x12530008>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc001f0 NPC: 0xbfc001f4 Ins: 0x12530008
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x4 (beq)
+ i rs: 0x12 rt: 0x13 i: 0x8
+ r rs: 18 rt: 19 rd: 0 sh: 0 func: 0x8
+ V rs: 0x4 rt: 0x184
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 0000000a 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dead 17: 00000000 18: 00000004 19: 00000184 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc001f4 m_jump_pc: 0xbfc001f8 m_ifetch_addr: 0xbfc001f4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x129842>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc001f4 NPC: 0xbfc001f8 Ins: 0x129842
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0x12 i: 0x9842
+ r rs: 0 rt: 18 rd: 19 sh: 1 func: 0x2
+ V rs: 0 rt: 0x4
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 0000000a 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dead 17: 00000000 18: 00000004 19: 00000184 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc001f8 m_jump_pc: 0xbfc001fc m_ifetch_addr: 0xbfc001f8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c08d820>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc001f8 NPC: 0xbfc001fc Ins: 0x3c08d820
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0x8 i: 0xd820
+ r rs: 0 rt: 8 rd: 27 sh: 0 func: 0x20
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 0000000a 05: 00000000 06: 00000000 07: 00000000
+ 08: 00000000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dead 17: 00000000 18: 00000004 19: 00000002 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc001fc m_jump_pc: 0xbfc00200 m_ifetch_addr: 0xbfc001fc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xad130080>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc001fc NPC: 0xbfc00200 Ins: 0xad130080
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2b (sw)
+ i rs: 0x8 rt: 0x13 i: 0x80
+ r rs: 8 rt: 19 rd: 0 sh: 2 func: 0
+ V rs: 0xd8200000 rt: 0x2
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 0000000a 05: 00000000 06: 00000000 07: 00000000
+ 08: d8200000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dead 17: 00000000 18: 00000004 19: 00000002 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd8200080 wdata 0x2 be 0xf> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc00200 m_jump_pc: 0xbfc00204 m_ifetch_addr: 0xbfc00200
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x42000018>, <DataRsp valid no error rdata 0>, 0)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc00200 NPC: 0xbfc00204 Ins: 0x42000018
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x10 (cop0)
+ i rs: 0x10 rt: 0 i: 0x18
+ r rs: 16 rt: 0 rd: 0 sh: 0 func: 0x18
+ V rs: 0xdead rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 0000000a 05: 00000000 06: 00000000 07: 00000000
+ 08: d8200000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dead 17: 00000000 18: 00000004 19: 00000002 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 ERET  exl jump_pc: bfc000c4
+mips0 m_next_pc: 0xbfc000c0 m_jump_pc: 0xbfc000c4 m_ifetch_addr: 0xbfc000c0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2610ffff>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc000c0 NPC: 0xbfc000c4 Ins: 0x2610ffff
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 0 .erl: 0 .whole: 0x400401
+ op:  0x9 (addiu)
+ i rs: 0x10 rt: 0x10 i: 0xffff
+ r rs: 16 rt: 16 rd: 31 sh: 31 func: 0x3f
+ V rs: 0xdead rt: 0xdead
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 0000000a 05: 00000000 06: 00000000 07: 00000000
+ 08: d8200000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000dead 17: 00000000 18: 00000004 19: 00000002 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc000c4 m_jump_pc: 0xbfc000c8 m_ifetch_addr: 0xbfc000c4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3411dead>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc000c4 NPC: 0xbfc000c8 Ins: 0x3411dead
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 0 .erl: 0 .whole: 0x400401
+ op:  0xd (ori)
+ i rs: 0 rt: 0x11 i: 0xdead
+ r rs: 0 rt: 17 rd: 27 sh: 26 func: 0x2d
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 0000000a 05: 00000000 06: 00000000 07: 00000000
+ 08: d8200000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 00000000 18: 00000004 19: 00000002 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc000c8 m_jump_pc: 0xbfc000cc m_ifetch_addr: 0xbfc000c8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x1211ffe9>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc000c8 NPC: 0xbfc000cc Ins: 0x1211ffe9
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 0 .erl: 0 .whole: 0x400401
+ op:  0x4 (beq)
+ i rs: 0x10 rt: 0x11 i: 0xffe9
+ r rs: 16 rt: 17 rd: 31 sh: 31 func: 0x29
+ V rs: 0xdeac rt: 0xdead
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 0000000a 05: 00000000 06: 00000000 07: 00000000
+ 08: d8200000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 0000dead 18: 00000004 19: 00000002 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc000cc m_jump_pc: 0xbfc000d0 m_ifetch_addr: 0xbfc000cc
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2610ffff>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc000cc NPC: 0xbfc000d0 Ins: 0x2610ffff
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 0 .erl: 0 .whole: 0x400401
+ op:  0x9 (addiu)
+ i rs: 0x10 rt: 0x10 i: 0xffff
+ r rs: 16 rt: 16 rd: 31 sh: 31 func: 0x3f
+ V rs: 0xdeac rt: 0xdeac
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 0000000a 05: 00000000 06: 00000000 07: 00000000
+ 08: d8200000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deac 17: 0000dead 18: 00000004 19: 00000002 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc000d0 m_jump_pc: 0xbfc000d4 m_ifetch_addr: 0xbfc000d0
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x24040001>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc000d0 NPC: 0xbfc000d4 Ins: 0x24040001
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 0 .erl: 0 .whole: 0x400401
+ op:  0x9 (addiu)
+ i rs: 0 rt: 0x4 i: 0x1
+ r rs: 0 rt: 4 rd: 0 sh: 0 func: 0x1
+ V rs: 0 rt: 0xa
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 0000000a 05: 00000000 06: 00000000 07: 00000000
+ 08: d8200000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deab 17: 0000dead 18: 00000004 19: 00000002 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc000d4 m_jump_pc: 0xbfc000d8 m_ifetch_addr: 0xbfc000d4
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xaf640000>, <DataRsp invalid no error rdata 0>, 0)
+mips0 PC: 0xbfc000d4 NPC: 0xbfc000d8 Ins: 0xaf640000
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 0 .erl: 0 .whole: 0x400401
+ op:  0x2b (sw)
+ i rs: 0x1b rt: 0x4 i: 0
+ r rs: 27 rt: 4 rd: 0 sh: 0 func: 0
+ V rs: 0xe0000000 rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000001 05: 00000000 06: 00000000 07: 00000000
+ 08: d8200000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deab 17: 0000dead 18: 00000004 19: 00000002 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xe0000000 wdata 0x1 be 0xf> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc000d8 m_jump_pc: 0xbfc000dc m_ifetch_addr: 0xbfc000d8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf00036>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc000d8 m_jump_pc: 0xbfc000dc m_ifetch_addr: 0xbfc000d8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf00036>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc000d8 m_jump_pc: 0xbfc000dc m_ifetch_addr: 0xbfc000d8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf00036>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc000d8 m_jump_pc: 0xbfc000dc m_ifetch_addr: 0xbfc000d8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf00036>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc000d8 m_jump_pc: 0xbfc000dc m_ifetch_addr: 0xbfc000d8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf00036>, <DataRsp invalid no error rdata 0>, 0)
+mips0 m_next_pc: 0xbfc000d8 m_jump_pc: 0xbfc000dc m_ifetch_addr: 0xbfc000d8
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf00036>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 exception: 0
+ m_ins: 0x2 epc: 0xbfc000d8 error_epc: 0 bar: 0xe0000000 cause.xcode: 0 .bd: 0 .ip: 0x4 status.exl: 0x1 .erl: 0 exception address: 0xbfc00380
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0004d>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0004d>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0004d>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0004d>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0004d>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0004d>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0004d>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0004d>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0004d>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0004d>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0004d>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0004d>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0004d>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0004d>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0004d>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0004d>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0004d>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0004d>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0004d>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0004d>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0004d>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0004d>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0004d>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0004d>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0004d>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0004d>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0004d>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0004d>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0004d>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0004d>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0004d>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0004d>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0004d>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0004d>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0004d>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0004d>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0004d>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0004d>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0004d>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0004d>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0004d>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0004d>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0004d>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0004d>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0004d>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0004d>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0004d>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0004d>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0004d>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0004d>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0004d>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0004d>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0004d>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0004d>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0004d>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0004d>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0004d>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0004d>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0004d>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0004d>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0004d>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0004d>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0004d>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0004d>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0004d>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0004d>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0004d>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0004d>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0004d>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 m_next_pc: 0xbfc00380 m_jump_pc: 0xbfc00384 m_ifetch_addr: 0xbfc00380
+mips0 early_end: ireq_ok=0x1 dreq_ok=0 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xbf0004d>, <DataRsp valid no error rdata 0>, 0x1)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc00380 NPC: 0xbfc00384 Ins: 0xbf0004d
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2 (j)
+ i rs: 0x1f rt: 0x10 i: 0x4d
+ r rs: 31 rt: 16 rd: 0 sh: 1 func: 0xd
+ V rs: 0xbfc001d0 rt: 0xdeab
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000001 05: 00000000 06: 00000000 07: 00000000
+ 08: d8200000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deab 17: 0000dead 18: 00000004 19: 00000002 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00384 m_jump_pc: 0xbfc00134 m_ifetch_addr: 0xbfc00384
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 PC: 0xbfc00384 NPC: 0xbfc00134 Ins: 0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0 (special)
+ i rs: 0 rt: 0 i: 0
+ r rs: 0 rt: 0 rd: 0 sh: 0 func: 0
+ V rs: 0 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000001 05: 00000000 06: 00000000 07: 00000000
+ 08: d8200000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deab 17: 0000dead 18: 00000004 19: 00000002 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00134 m_jump_pc: 0xbfc00138 m_ifetch_addr: 0xbfc00134
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x2610ffff>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 PC: 0xbfc00134 NPC: 0xbfc00138 Ins: 0x2610ffff
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x9 (addiu)
+ i rs: 0x10 rt: 0x10 i: 0xffff
+ r rs: 16 rt: 16 rd: 31 sh: 31 func: 0x3f
+ V rs: 0xdeab rt: 0xdeab
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000001 05: 00000000 06: 00000000 07: 00000000
+ 08: d8200000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deab 17: 0000dead 18: 00000004 19: 00000002 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00138 m_jump_pc: 0xbfc0013c m_ifetch_addr: 0xbfc00138
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c08d820>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 PC: 0xbfc00138 NPC: 0xbfc0013c Ins: 0x3c08d820
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0x8 i: 0xd820
+ r rs: 0 rt: 8 rd: 27 sh: 0 func: 0x20
+ V rs: 0 rt: 0xd8200000
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000001 05: 00000000 06: 00000000 07: 00000000
+ 08: d8200000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deaa 17: 0000dead 18: 00000004 19: 00000002 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc0013c m_jump_pc: 0xbfc00140 m_ifetch_addr: 0xbfc0013c
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0xad000080>, <DataRsp invalid no error rdata 0>, 0x1)
+mips0 PC: 0xbfc0013c NPC: 0xbfc00140 Ins: 0xad000080
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0x2b (sw)
+ i rs: 0x8 rt: 0 i: 0x80
+ r rs: 8 rt: 0 rd: 0 sh: 2 func: 0
+ V rs: 0xd8200000 rt: 0
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000001 05: 00000000 06: 00000000 07: 00000000
+ 08: d8200000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deaa 17: 0000dead 18: 00000004 19: 00000002 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 do_mem_access: <DataReq mode MODE_KERNEL   valid type DATA_WRITE @ 0xd8200080 wdata 0 be 0xf> off: 0 sign_ext: 0 dest: gp+0x15f561
+mips0 m_next_pc: 0xbfc00140 m_jump_pc: 0xbfc00144 m_ifetch_addr: 0xbfc00140
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+mips0 executeNCycles( 0x1, <InsRsp  valid no error ins 0x3c04bfc0>, <DataRsp valid no error rdata 0>, 0x1)
+mips0 setData: <DataRsp valid no error rdata 0> off: 0 sign_ext: 0 dest: r_gp+0x15f561
+mips0 PC: 0xbfc00140 NPC: 0xbfc00144 Ins: 0x3c04bfc0
+ Cause.xcode: 0
+ Mode: 0 Status.ksu 0 .exl: 1 .erl: 0 .whole: 0x400403
+ op:  0xf (lui)
+ i rs: 0 rt: 0x4 i: 0xbfc0
+ r rs: 0 rt: 4 rd: 23 sh: 31 func: 0
+ V rs: 0 rt: 0x1
+ 00: 00000000 01: 00000000 02: 00000000 03: 00000000 04: 00000001 05: 00000000 06: 00000000 07: 00000000
+ 08: d8200000 09: 00000000 10: 00000030 11: 00000001 12: 00000000 13: 00000000 14: 00000000 15: 00000000
+ 16: 0000deaa 17: 0000dead 18: 00000004 19: 00000002 20: 00000000 21: 00000000 22: 00000000 23: 00000000
+ 24: 00000000 25: 00000000 26: d0200000 27: e0000000 28: 00000000 29: 00000000 30: 00000000 31: bfc001d0
+mips0 m_next_pc: 0xbfc00144 m_jump_pc: 0xbfc00148 m_ifetch_addr: 0xbfc00144
+mips0 early_end: ireq_ok=0x1 dreq_ok=0x1 m_ins_delay=0 ncycle=0x1 time_spent=0
+vci_exit terminate simulation, status 0x1
Index: branches/v4/softs/tests_ccvcache_v4/test_interrupt_loop_tmp/test.S
===================================================================
--- branches/v4/softs/tests_ccvcache_v4/test_interrupt_loop_tmp/test.S	(revision 371)
+++ branches/v4/softs/tests_ccvcache_v4/test_interrupt_loop_tmp/test.S	(revision 371)
@@ -0,0 +1,166 @@
+/*
+ * Check interrupt/return with interrup occuring at various points in
+ * the software. Cache is enabled to we have on interrupt/cycle
+ */
+#include <registers.h>
+#include <misc.h>
+#include <vcache.h>
+#include <xicu.h>
+
+	.text
+	.globl  _start
+_start:
+	.set noreorder
+	la	k0, TTY_BASE
+	la	k1, EXIT_BASE
+
+	/* reset cause, make sure IV is off */
+	mtc0	zero, COP0_CAUSE
+
+	la	a0, pte1
+	srl	a0, a0, 13
+	mtc2	a0, VC_PTPR
+	nop
+
+	li	a0, VC_TLB_EN_ITLB | VC_TLB_EN_DTLB | VC_TLB_EN_ICACHE | VC_TLB_EN_DCACHE
+	mtc2 	a0, VC_TLB_EN
+
+	PRINT(startstr)
+
+	/* program xicu */
+	la	t0, XICU_BASE
+	/* clear pending interrupt */
+	lw	a0, XICU_PTI_ACK(0)(t0)
+	/* route PTI0 to irq 0 */
+	li	a0, 1 << 0
+	sw	a0, XICU_MSK_PTI_E(0)(t0)
+	/* init s0 */
+	li	s0, MAGIC2
+	/*
+	 * interrupt in INTERRUPT_DELAY cycles.
+	 */
+	li	s2, 1
+	sw	s2, XICU_PTI_PER(0)(t0)
+	/* clear pending interrupt */
+	lw	a0, XICU_PTI_ACK(0)(t0)
+	/* reset cop0 status (keep BEV), enable interrupt 0 */
+	lui     a0, 0x0040;
+	addiu	a0, 0x0401;
+	mtc0    a0, COP0_STATUS
+
+	nop
+	li      s0, MAGIC1
+	addiu	s0, s0, -1
+loop:	
+	addiu	s0, s0, -1
+	addiu	s0, s0, -1
+	addiu	s0, s0, -1
+	j	bla
+	addiu	s0, s0, 5
+	EXIT(1)
+	addiu	s0, s0, -1
+	.align 6
+bla:
+	addiu	s0, s0, -1
+	li		s1, MAGIC1
+	beq	    s0, s1, loop
+	addiu	s0, s0, -1
+
+	/* we should not end there */
+	EXIT(1)
+
+	.align 6
+end:
+	PRINT(endstr)
+	move	a0, s0
+	PRINTX
+	PUTCHAR('\n')
+	EXIT(0)
+
+	.rodata:
+statusstr: .ascii "status \0"
+causestr: .ascii " cause \0"
+pcstr: .ascii " pc \0"
+badvastr: .ascii " badva \0"
+xicustr: .ascii " xicu \0"
+startstr: .ascii "start\n\0"
+perstr: .ascii " period \0"
+endstr: .ascii "end \0"
+
+	.org EXCEP_ADDRESS - BOOT_ADDRESS
+	.globl excep
+excep:
+	.set noreorder
+	addiu	s0, s0, -10
+	/* disable timer0 */
+	la	t0, XICU_BASE
+	sw	zero, XICU_PTI_PER(0)(t0)
+	PRINT(statusstr)
+	mfc0	a0, COP0_STATUS
+	PRINTX
+
+	PRINT(pcstr)
+	mfc0	a0, COP0_EXPC
+	PRINTX
+
+	PRINT(causestr)
+	mfc0	a0, COP0_CAUSE
+	PRINTX
+
+	PRINT(badvastr)
+	mfc0	a0, COP_0_BADVADDR
+	PRINTX
+
+	PRINT(xicustr)
+	la	t0, XICU_BASE
+	lw	a0, XICU_PRIO(0)(t0)
+	PRINTX
+
+//	PRINT(perstr)
+//	move a0, s2
+//	PRINTX
+//
+	PUTCHAR('\n')
+
+#if 0
+	andi s3, s2, 1
+	beqz s3, noflush
+#endif
+	addiu	s0, s0, 10
+
+#if 1
+	// Flush cache of jump routine
+	la s3, bla
+	mtc2 s3, VC_ICACHE_INVAL
+	mtc2 s3, VC_ITLB_INVAL
+#endif
+		
+noflush:
+	addiu s2, s2, 1
+	li s3, 194*2
+	beq s2, s3, end2
+	srl s3, s2, 1
+	la	t0, XICU_BASE
+	sw	s3, XICU_PTI_PER(0)(t0)
+	eret
+	/* we should not end there */
+	EXIT(1)
+end2:
+	EXIT(0)
+
+	.data
+myvar:	.word 0
+pte1:
+	.align 13
+	.word PTE1_V | PTE1_C | PTE1_W | 0x0 /* map PA 0 at VA 0 */
+	.org pte1 + (BOOT_ADDRESS >> 21) * 4
+	.word PTE1_V | PTE1_C | PTE1_X | (BOOT_ADDRESS >> 21) /* map PA 0xbfc00000 at VA 0xbfc00000 */
+	.org pte1 + (TTY_BASE >> 21) * 4
+	.word PTE1_V | PTE1_W | (TTY_BASE >> 21) /* map PA 0xd0200000 at VA 0xd0200000 */
+	.org pte1 + (XICU_BASE >> 21) * 4
+	.word PTE1_V | PTE1_W | (XICU_BASE >> 21) /* map PA 0xd2000000 at VA 0xd2000000 */
+	.org pte1 + (EXIT_BASE >> 21) * 4
+	.word PTE1_V | PTE1_W | (EXIT_BASE >> 21) /* map PA 0xe0000000 at VA 0xe0000000 */
+	.org pte1 + 8192
+	.word 0
+
Index: branches/v4/softs/tests_ccvcache_v4/test_interrupt_mask/Makefile
===================================================================
--- branches/v4/softs/tests_ccvcache_v4/test_interrupt_mask/Makefile	(revision 371)
+++ branches/v4/softs/tests_ccvcache_v4/test_interrupt_mask/Makefile	(revision 371)
@@ -0,0 +1,1 @@
+include ../Makefile.inc
Index: branches/v4/softs/tests_ccvcache_v4/test_interrupt_mask/run
===================================================================
--- branches/v4/softs/tests_ccvcache_v4/test_interrupt_mask/run	(revision 371)
+++ branches/v4/softs/tests_ccvcache_v4/test_interrupt_mask/run	(revision 371)
@@ -0,0 +1,33 @@
+#!/bin/sh 
+
+. ../common/common.sh
+
+check_output()
+{
+	egrep "^0x0000BEEF$" run.out > /dev/null
+	if [ $? -ne 0 ]; then
+		echo "couldn't find string 1 in output - mtty not working ?" >> run.out
+		return 1
+	fi
+	egrep "^status 0x0040FF03 cause 0x00000100 pc 0xBFC00074 badva 0x00000000$" run.out > /dev/null
+	if [ $? -ne 0 ]; then
+		echo "couldn't find string 2 in output - mtty not working ?" >> run.out
+		return 1
+	fi
+	return 0;
+}
+
+make --quiet || exit 1
+${SIMUL} > run.out 2>&1 
+if [ $? -eq 0 ]; then
+	if check_output; then
+		echo "test passsed";
+		make --quiet clean
+		exit 0;
+	fi
+	echo "test FAILED"
+	exit 1
+fi
+echo "test FAILED"
+exit 1
+
Index: branches/v4/softs/tests_ccvcache_v4/test_interrupt_mask/test.S
===================================================================
--- branches/v4/softs/tests_ccvcache_v4/test_interrupt_mask/test.S	(revision 371)
+++ branches/v4/softs/tests_ccvcache_v4/test_interrupt_mask/test.S	(revision 371)
@@ -0,0 +1,95 @@
+/*
+ * Check that the interrupt mask in status is properly handled:
+ * we generate a software-triggerted interrupt with interrupt enabled but
+ * the software interrupt masked. Later we unmask it.
+ */
+#include <registers.h>
+#include <misc.h>
+
+
+	.text
+	.globl  _start
+_start:
+	.set noreorder
+	la	k0, TTY_BASE
+	la	k1, EXIT_BASE
+
+	/* reset cop0 status (keep BEV), enbale interrupts but mask IM0 */
+	lui     a0, 0x0040;
+	ori	a0, 0xfe01;
+	mtc0    a0, COP0_STATUS
+
+	/* reset cause, make sure IV is off */
+	mtc0	zero, COP0_CAUSE
+
+	PRINT(startstr)
+
+	/* generate an interrupt */
+	mfc0	a0, COP0_CAUSE
+	nop
+	ori	a0, 0x0100
+	mtc0	a0, COP0_CAUSE
+	li	a0, MAGIC1
+	PRINTX
+	PUTCHAR('\n')
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	/* unmask the interrupt */
+	mfc0	a0, COP0_STATUS
+	nop
+	ori	a0, 0x0100
+	mtc0	a0, COP0_STATUS
+	/* we should end here after taking the exeption */
+	li	a0, MAGIC2
+	PRINTX
+	PUTCHAR('\n')
+	EXIT(0)
+
+	.globl excep
+excep:
+	.set noreorder
+	PRINT(statusstr)
+	mfc0	a0, COP0_STATUS
+	PRINTX
+
+	PRINT(causestr)
+	mfc0	a0, COP0_CAUSE
+	PRINTX
+
+	PRINT(pcstr)
+	mfc0	a0, COP0_EXPC
+	PRINTX
+
+	PRINT(badvastr)
+	mfc0	a0, COP_0_BADVADDR
+	PRINTX
+
+	PUTCHAR('\n')
+	/* clear interrupt */
+	mfc0	a0, COP0_CAUSE
+	xori	a0, 0x100
+	mtc0	a0, COP0_CAUSE
+	nop
+	eret
+	/* we should not end there */
+	EXIT(1)
+
+	.rodata:
+statusstr: .ascii "status \0"
+causestr: .ascii " cause \0"
+pcstr: .ascii " pc \0"
+badvastr: .ascii " badva \0"
+startstr: .ascii "start\n\0"
+eretstr: .ascii "eret\n\0"
+
+	.org EXCEP_ADDRESS - BOOT_ADDRESS
+	.globl evect
+evect:
+	j	excep
+	nop
+	.data
+myvar:	.word 0
Index: branches/v4/softs/tests_ccvcache_v4/test_itlb_inval/Makefile
===================================================================
--- branches/v4/softs/tests_ccvcache_v4/test_itlb_inval/Makefile	(revision 371)
+++ branches/v4/softs/tests_ccvcache_v4/test_itlb_inval/Makefile	(revision 371)
@@ -0,0 +1,2 @@
+LDSCRIPT=./ldscript
+include ../Makefile.inc
Index: branches/v4/softs/tests_ccvcache_v4/test_itlb_inval/ldscript
===================================================================
--- branches/v4/softs/tests_ccvcache_v4/test_itlb_inval/ldscript	(revision 371)
+++ branches/v4/softs/tests_ccvcache_v4/test_itlb_inval/ldscript	(revision 371)
@@ -0,0 +1,67 @@
+/*
+ *
+ * SOCLIB_GPL_HEADER_BEGIN
+ * 
+ * This file is part of SoCLib, GNU GPLv2.
+ * 
+ * SoCLib is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ * 
+ * SoCLib is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * General Public License for more details.
+ * 
+ * You should have received a copy of the GNU General Public License
+ * along with SoCLib; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301, USA.
+ * 
+ * SOCLIB_GPL_HEADER_END
+ *
+ * Copyright (c) UPMC, Lip6, SoC
+ *         Nicolas Pouillon <nipo@ssji.net>, 2006-2007
+ *
+ * Maintainers: abdelmalek.si-merabet@lip6.fr
+ */
+ENTRY(_start)
+
+SECTIONS
+{
+   . = 0xbfc00000;
+   .text : {
+      *(.text)
+/* load .text2 one page after .text */
+      . = ALIGN(0x1000);
+      *(.text2)
+   }
+   .rodata : {
+      *(.rodata)
+      . = ALIGN(4);
+   }
+   . = 0x00000000;
+   .data  : {
+      *(.data)
+   }
+   .sdata : {
+      *(.lit8)
+      *(.lit4)
+      *(.sdata)
+   }
+   _gp = .;
+   . = ALIGN(4);
+   _edata = .;
+   .sbss  : {
+      *(.sbss)
+      *(.scommon)
+   }
+   .bss   : {
+      *(.bss)
+      *(COMMON)
+   }
+   . = ALIGN(4);
+   _end = .;
+   _heap = .;
+   _stack = 0x00400000-16;
+}
Index: branches/v4/softs/tests_ccvcache_v4/test_itlb_inval/run
===================================================================
--- branches/v4/softs/tests_ccvcache_v4/test_itlb_inval/run	(revision 371)
+++ branches/v4/softs/tests_ccvcache_v4/test_itlb_inval/run	(revision 371)
@@ -0,0 +1,28 @@
+#!/bin/sh 
+
+. ../common/common.sh
+
+check_output()
+{
+	egrep "^mmu started 0x0000DEAD status 0x00400002 cause 0x00000018 pc 0xBFC01000 badva 0x00000000$" run.out > /dev/null
+	if [ $? -ne 0 ]; then
+		echo "couldn't find string in output - mtty not working ?" >> run.out
+		return 1
+	fi
+	return 0;
+}
+
+make --quiet || exit 1
+${SIMUL} > run.out 2>&1 
+if [ $? -eq 0 ]; then
+	if check_output; then
+		echo "test passsed";
+		make --quiet clean
+		exit 0;
+	fi
+	echo "test FAILED"
+	exit 1
+fi
+echo "test FAILED"
+exit 1
+
Index: branches/v4/softs/tests_ccvcache_v4/test_itlb_inval/test.S
===================================================================
--- branches/v4/softs/tests_ccvcache_v4/test_itlb_inval/test.S	(revision 371)
+++ branches/v4/softs/tests_ccvcache_v4/test_itlb_inval/test.S	(revision 371)
@@ -0,0 +1,135 @@
+/*
+ * itlb inval: a write to VC_ITLB_INVAL should invalidate the corresponding
+ * itlb entry. On a ccvcache, VC_ITLB_INVAL should not be needed, and
+ * the first access after clearing pte2_a should fail
+ */
+#include <registers.h>
+#include <misc.h>
+#include <vcache.h>
+
+	.text
+	.globl  _start
+_start:
+	.set noreorder
+	la	k0, TTY_BASE
+	la	k1, EXIT_BASE
+
+	PRINT(startstr)
+
+	/* reset cop0 status (keep BEV) */
+	lui	a0, 0x0040;
+	mtc0	a0, COP0_STATUS
+
+	la	a0, pte1_a
+	srl	a0, a0, 13
+	mtc2	a0, VC_PTPR
+	nop
+
+	li	a0, VC_TLB_EN_ITLB | VC_TLB_EN_DTLB | VC_TLB_EN_ICACHE | VC_TLB_EN_DCACHE
+	mtc2 	a0, VC_TLB_EN
+
+	PRINT(mmustr)
+	jal	doload
+	nop
+	PRINTX
+	PUTCHAR(' ')
+	la	a0, pte2_a
+	sw	zero, 8(a0) /* invalidate PTE2 */
+	sync
+	la      a0, pte2_a /* make the sync synchronous */
+	jal	doload /* TLB entry not invalidated yet, we can do this */
+	nop
+	PRINTX
+	PUTCHAR('\n')
+	la	a0, doload
+	mtc2	a0, VC_ITLB_INVAL /* invalidate VA */
+	jal	doload /* this should fail now */
+	nop
+	PRINTX
+	PUTCHAR('\n')
+
+	/* we should not get there */
+	EXIT(1)
+
+	.globl excep
+excep:
+	.set noreorder
+	PRINT(statusstr)
+	mfc0	a0, COP0_STATUS
+	PRINTX
+
+	PRINT(causestr)
+	mfc0	a0, COP0_CAUSE
+	PRINTX
+
+	PRINT(pcstr)
+	mfc0	a0, COP0_EXPC
+	PRINTX
+
+	PRINT(badvastr)
+	mfc0	a0, COP_0_BADVADDR
+	PRINTX
+
+	PUTCHAR('\n')
+	/* we should get there */
+	EXIT(0)
+
+	.rodata:
+statusstr: .ascii "status \0"
+causestr: .ascii " cause \0"
+pcstr: .ascii " pc \0"
+badvastr: .ascii " badva \0"
+mmustr: .ascii "mmu started \0"
+startstr: .ascii "start\n\0"
+
+	.org EXCEP_ADDRESS - BOOT_ADDRESS
+	.globl evect
+evect:
+	j	excep
+	nop
+
+	/*
+	 * code that will be switched by MMU switch.
+	 * we use a ldscript trick here, to load this function at
+	 * the appropriate address
+	 */
+	.section .text2, "ax"
+	.globl doload
+doload:
+	jr      ra
+	li      a0, MAGIC1
+	/* we should not get there */
+	EXIT(1)
+	nop
+
+	.data
+	.word MAGIC1
+testval:
+	.word MAGIC2
+	.globl pte2_a
+
+/*
+ * one PD with a level 2 PTP: we invalidate an entry in the PTP and
+ * check that the VA is no longer accessible
+ */
+pte2_a:
+	.align 12
+	.word PTE2_V | PTE2_C | PTE2_X
+	.word BOOT_ADDRESS >> 12
+	.word PTE2_V | PTE2_C | PTE2_X
+	.word (BOOT_ADDRESS+0x1000) >> 12
+	.org pte2_a + 4092
+	.word 0
+	.globl pte2_b
+	.globl pte1_a
+pte1_a:
+	.align 13
+	.word PTE1_V | PTE1_C | PTE1_W | 0x0 /* map PA 0 at VA 0 */
+	.word 0x0
+	.org pte1_a + (BOOT_ADDRESS >> 21) * 4
+	.word PTE1_V | PTE1_T | (0x1000 >> 12) /* map PA 0xbfc00000 at VA 0xbfc00000 with 4k page: check real address of pte2_a !!! */
+	.org pte1_a + (TTY_BASE >> 21) * 4
+	.word PTE1_V | PTE1_W | (TTY_BASE >> 21) /* map PA 0xd0200000 at VA 0xd0200000 */
+	.org pte1_a + (EXIT_BASE >> 21) * 4
+	.word PTE1_V | PTE1_W | (EXIT_BASE >> 21) /* map PA 0xe0000000 at VA 0xe0000000 */
+	.org pte1_a + 8192
Index: branches/v4/softs/tests_ccvcache_v4/test_itlb_inval2/Makefile
===================================================================
--- branches/v4/softs/tests_ccvcache_v4/test_itlb_inval2/Makefile	(revision 371)
+++ branches/v4/softs/tests_ccvcache_v4/test_itlb_inval2/Makefile	(revision 371)
@@ -0,0 +1,2 @@
+LDSCRIPT=./ldscript
+include ../Makefile.inc
Index: branches/v4/softs/tests_ccvcache_v4/test_itlb_inval2/ldscript
===================================================================
--- branches/v4/softs/tests_ccvcache_v4/test_itlb_inval2/ldscript	(revision 371)
+++ branches/v4/softs/tests_ccvcache_v4/test_itlb_inval2/ldscript	(revision 371)
@@ -0,0 +1,67 @@
+/*
+ *
+ * SOCLIB_GPL_HEADER_BEGIN
+ * 
+ * This file is part of SoCLib, GNU GPLv2.
+ * 
+ * SoCLib is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ * 
+ * SoCLib is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * General Public License for more details.
+ * 
+ * You should have received a copy of the GNU General Public License
+ * along with SoCLib; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301, USA.
+ * 
+ * SOCLIB_GPL_HEADER_END
+ *
+ * Copyright (c) UPMC, Lip6, SoC
+ *         Nicolas Pouillon <nipo@ssji.net>, 2006-2007
+ *
+ * Maintainers: abdelmalek.si-merabet@lip6.fr
+ */
+ENTRY(_start)
+
+SECTIONS
+{
+   . = 0xbfc00000;
+   .text : {
+      *(.text)
+/* load .text2 one page after .text */
+      . = ALIGN(0x1000);
+      *(.text2)
+   }
+   .rodata : {
+      *(.rodata)
+      . = ALIGN(4);
+   }
+   . = 0x00000000;
+   .data  : {
+      *(.data)
+   }
+   .sdata : {
+      *(.lit8)
+      *(.lit4)
+      *(.sdata)
+   }
+   _gp = .;
+   . = ALIGN(4);
+   _edata = .;
+   .sbss  : {
+      *(.sbss)
+      *(.scommon)
+   }
+   .bss   : {
+      *(.bss)
+      *(COMMON)
+   }
+   . = ALIGN(4);
+   _end = .;
+   _heap = .;
+   _stack = 0x00400000-16;
+}
Index: branches/v4/softs/tests_ccvcache_v4/test_itlb_inval2/run
===================================================================
--- branches/v4/softs/tests_ccvcache_v4/test_itlb_inval2/run	(revision 371)
+++ branches/v4/softs/tests_ccvcache_v4/test_itlb_inval2/run	(revision 371)
@@ -0,0 +1,28 @@
+#!/bin/sh 
+
+. ../common/common.sh
+
+check_output()
+{
+	egrep "^mmu started 0x0000DEAD 0x0000BEEF$" run.out > /dev/null
+	if [ $? -ne 0 ]; then
+		echo "couldn't find string in output - mtty not working ?" >> run.out
+		return 1
+	fi
+	return 0;
+}
+
+make --quiet || exit 1
+${SIMUL} > run.out 2>&1 
+if [ $? -eq 0 ]; then
+	if check_output; then
+		echo "test passsed";
+		make --quiet clean
+		exit 0;
+	fi
+	echo "test FAILED"
+	exit 1
+fi
+echo "test FAILED"
+exit 1
+
Index: branches/v4/softs/tests_ccvcache_v4/test_itlb_inval2/test.S
===================================================================
--- branches/v4/softs/tests_ccvcache_v4/test_itlb_inval2/test.S	(revision 371)
+++ branches/v4/softs/tests_ccvcache_v4/test_itlb_inval2/test.S	(revision 371)
@@ -0,0 +1,142 @@
+/*
+ * itlb inval: a write to a PTE2 should invalidate the corresponding
+ * itlb entry. 
+ */
+#include <registers.h>
+#include <misc.h>
+#include <vcache.h>
+
+	.text
+	.globl  _start
+_start:
+	.set noreorder
+	la	k0, TTY_BASE
+	la	k1, EXIT_BASE
+
+	PRINT(startstr)
+
+	/* reset cop0 status (keep BEV) */
+	lui	a0, 0x0040;
+	mtc0	a0, COP0_STATUS
+
+	la	a0, pte1_a
+	srl	a0, a0, 13
+	mtc2	a0, VC_PTPR
+	nop
+
+	li	a0, VC_TLB_EN_ITLB | VC_TLB_EN_DTLB | VC_TLB_EN_ICACHE | VC_TLB_EN_DCACHE
+	mtc2 	a0, VC_TLB_EN
+
+	PRINT(mmustr)
+	jal	doload
+	nop
+	PRINTX
+	PUTCHAR(' ')
+	la	t0, pte2_a
+	la	a0, (BOOT_ADDRESS+0x2000) >> 12
+	sw	a0, 12(t0) /* change PTE2 */
+	sync
+1:
+	ll	a0, 8(t0)
+	la	a0, PTE2_V | PTE2_C | PTE2_X
+	sc	a0, 8(t0)
+	beqz	a0, 1b
+	nop
+
+	jal	doload /* now we should get the second value */
+	nop
+	PRINTX
+	PUTCHAR('\n')
+	/* we should get there */
+	EXIT(0)
+
+	.globl excep
+excep:
+	.set noreorder
+	PRINT(statusstr)
+	mfc0	a0, COP0_STATUS
+	PRINTX
+
+	PRINT(causestr)
+	mfc0	a0, COP0_CAUSE
+	PRINTX
+
+	PRINT(pcstr)
+	mfc0	a0, COP0_EXPC
+	PRINTX
+
+	PRINT(badvastr)
+	mfc0	a0, COP_0_BADVADDR
+	PRINTX
+
+	PUTCHAR('\n')
+	/* we should not get there */
+	EXIT(1)
+
+	.rodata:
+statusstr: .ascii "status \0"
+causestr: .ascii " cause \0"
+pcstr: .ascii " pc \0"
+badvastr: .ascii " badva \0"
+mmustr: .ascii "mmu started \0"
+startstr: .ascii "start\n\0"
+
+	.org EXCEP_ADDRESS - BOOT_ADDRESS
+	.globl evect
+evect:
+	j	excep
+	nop
+
+	/*
+	 * code that will be switched by MMU switch.
+	 * we use a ldscript trick here, to load this function at
+	 * the appropriate address
+	 */
+	.section .text2, "ax"
+	.globl doload
+doload:
+	jr      ra
+	li      a0, MAGIC1
+	/* we should not get there */
+	EXIT(1)
+	nop
+	.align 12
+	.globl doload2
+doload2:
+	jr      ra
+	li      a0, MAGIC2
+	/* we should not get there */
+	EXIT(1)
+	nop
+
+	.data
+	.word MAGIC1
+testval:
+	.word MAGIC2
+	.globl pte2_a
+
+/*
+ * one PD with a level 2 PTP: we change an entry in the PTP and
+ * check that the ITLB has been invalidated
+ */
+pte2_a:
+	.align 12
+	.word PTE2_V | PTE2_C | PTE2_X
+	.word BOOT_ADDRESS >> 12
+	.word PTE2_V | PTE2_C | PTE2_X
+	.word (BOOT_ADDRESS+0x1000) >> 12
+	.org pte2_a + 4092
+	.word 0
+	.globl pte2_b
+	.globl pte1_a
+pte1_a:
+	.align 13
+	.word PTE1_V | PTE1_C | PTE1_W | 0x0 /* map PA 0 at VA 0 */
+	.word 0x0
+	.org pte1_a + (BOOT_ADDRESS >> 21) * 4
+	.word PTE1_V | PTE1_T | (0x1000 >> 12) /* map PA 0xbfc00000 at VA 0xbfc00000 with 4k page: check real address of pte2_a !!! */
+	.org pte1_a + (TTY_BASE >> 21) * 4
+	.word PTE1_V | PTE1_W | (TTY_BASE >> 21) /* map PA 0xd0200000 at VA 0xd0200000 */
+	.org pte1_a + (EXIT_BASE >> 21) * 4
+	.word PTE1_V | PTE1_W | (EXIT_BASE >> 21) /* map PA 0xe0000000 at VA 0xe0000000 */
+	.org pte1_a + 8192
Index: branches/v4/softs/tests_ccvcache_v4/test_itlb_ptprinval/Makefile
===================================================================
--- branches/v4/softs/tests_ccvcache_v4/test_itlb_ptprinval/Makefile	(revision 371)
+++ branches/v4/softs/tests_ccvcache_v4/test_itlb_ptprinval/Makefile	(revision 371)
@@ -0,0 +1,2 @@
+LDSCRIPT=./ldscript
+include ../Makefile.inc
Index: branches/v4/softs/tests_ccvcache_v4/test_itlb_ptprinval/ldscript
===================================================================
--- branches/v4/softs/tests_ccvcache_v4/test_itlb_ptprinval/ldscript	(revision 371)
+++ branches/v4/softs/tests_ccvcache_v4/test_itlb_ptprinval/ldscript	(revision 371)
@@ -0,0 +1,67 @@
+/*
+ *
+ * SOCLIB_GPL_HEADER_BEGIN
+ * 
+ * This file is part of SoCLib, GNU GPLv2.
+ * 
+ * SoCLib is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ * 
+ * SoCLib is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * General Public License for more details.
+ * 
+ * You should have received a copy of the GNU General Public License
+ * along with SoCLib; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301, USA.
+ * 
+ * SOCLIB_GPL_HEADER_END
+ *
+ * Copyright (c) UPMC, Lip6, SoC
+ *         Nicolas Pouillon <nipo@ssji.net>, 2006-2007
+ *
+ * Maintainers: abdelmalek.si-merabet@lip6.fr
+ */
+ENTRY(_start)
+
+SECTIONS
+{
+   . = 0xbfc00000;
+   .text : {
+      *(.text)
+/* load .text2 one page after .text */
+      . = ALIGN(0x1000);
+      *(.text2)
+   }
+   .rodata : {
+      *(.rodata)
+      . = ALIGN(4);
+   }
+   . = 0x00000000;
+   .data  : {
+      *(.data)
+   }
+   .sdata : {
+      *(.lit8)
+      *(.lit4)
+      *(.sdata)
+   }
+   _gp = .;
+   . = ALIGN(4);
+   _edata = .;
+   .sbss  : {
+      *(.sbss)
+      *(.scommon)
+   }
+   .bss   : {
+      *(.bss)
+      *(COMMON)
+   }
+   . = ALIGN(4);
+   _end = .;
+   _heap = .;
+   _stack = 0x00400000-16;
+}
Index: branches/v4/softs/tests_ccvcache_v4/test_itlb_ptprinval/run
===================================================================
--- branches/v4/softs/tests_ccvcache_v4/test_itlb_ptprinval/run	(revision 371)
+++ branches/v4/softs/tests_ccvcache_v4/test_itlb_ptprinval/run	(revision 371)
@@ -0,0 +1,33 @@
+#!/bin/sh 
+
+. ../common/common.sh
+
+check_output()
+{
+	egrep "^mmu started ptpr_b 0x0000BEEF$" run.out > /dev/null
+	if [ $? -ne 0 ]; then
+		echo "couldn't find string 1 in output - mtty not working ?" >> run.out
+		return 1
+	fi
+	egrep "^mmu started ptpr_a 0x0000DEAD$" run.out > /dev/null
+	if [ $? -ne 0 ]; then
+		echo "couldn't find string 2 in output - mtty not working ?" >> run.out
+		return 1
+	fi
+	return 0;
+}
+
+make --quiet || exit 1
+${SIMUL} > run.out 2>&1 
+if [ $? -eq 0 ]; then
+	if check_output; then
+		echo "test passsed";
+		make --quiet clean
+		exit 0;
+	fi
+	echo "test FAILED"
+	exit 1
+fi
+echo "test FAILED"
+exit 1
+
Index: branches/v4/softs/tests_ccvcache_v4/test_itlb_ptprinval/test.S
===================================================================
--- branches/v4/softs/tests_ccvcache_v4/test_itlb_ptprinval/test.S	(revision 371)
+++ branches/v4/softs/tests_ccvcache_v4/test_itlb_ptprinval/test.S	(revision 371)
@@ -0,0 +1,162 @@
+/*
+ * itlb inval on PTPR write: check that no stale entry exists in the itlb
+ * after MMU context swicth
+ */
+#include <registers.h>
+#include <misc.h>
+#include <vcache.h>
+	.text
+	.globl  _start
+_start:
+	.set noreorder
+	la	k0, TTY_BASE
+	la	k1, EXIT_BASE
+
+	PRINT(startstr)
+
+	/* reset cop0 status (keep BEV) */
+	lui	a0, 0x0040;
+	mtc0	a0, COP0_STATUS
+
+	la	a0, pte1_b
+	srl	a0, a0, 13
+	mtc2	a0, VC_PTPR
+	nop
+
+	li	a0, VC_TLB_EN_ITLB | VC_TLB_EN_DTLB | VC_TLB_EN_ICACHE | VC_TLB_EN_DCACHE
+	mtc2 	a0, VC_TLB_EN
+
+	PRINT(mmustr_b)
+	jal	doload
+	nop
+	PRINTX
+	PUTCHAR('\n')
+	la	a0, pte1_a
+	srl	a0, a0, 13
+	mtc2	a0, VC_PTPR
+	nop
+#if 0 /* works with this - this shows the old pte2 address is cached */
+	la	a0, pte2_a
+	lw	a1, 12(a0)
+	la	a0, pte2_b
+	sw	a1, 12(a0)
+#endif
+	PRINT(mmustr_a)
+	jal	doload
+	nop
+	PRINTX
+	PUTCHAR('\n')
+
+	/* we should get there */
+	EXIT(0)
+
+	.globl excep
+excep:
+	.set noreorder
+	PRINT(statusstr)
+	mfc0	a0, COP0_STATUS
+	PRINTX
+
+	PRINT(causestr)
+	mfc0	a0, COP0_CAUSE
+	PRINTX
+
+	PRINT(pcstr)
+	mfc0	a0, COP0_EXPC
+	PRINTX
+
+	PRINT(badvastr)
+	mfc0	a0, COP_0_BADVADDR
+	PRINTX
+
+	PUTCHAR('\n')
+	/* we should not get there */
+	EXIT(3)
+
+	.rodata:
+statusstr: .ascii "status \0"
+causestr: .ascii " cause \0"
+pcstr: .ascii " pc \0"
+badvastr: .ascii " badva \0"
+mmustr_a: .ascii "mmu started ptpr_a \0"
+mmustr_b: .ascii "mmu started ptpr_b \0"
+startstr: .ascii "start\n\0"
+
+	.org EXCEP_ADDRESS - BOOT_ADDRESS
+	.globl evect
+evect:
+	j	excep
+	nop
+
+	/*
+	 * code that will be switched by MMU switch.
+	 * we use a ldscript trick here, to load this function at
+	 * the appropriate address
+	 */
+	.section .text2, "ax"
+	.globl doload
+doload:
+	jr      ra
+	li      a0, MAGIC1
+	/* we should not get there */
+	EXIT(1)
+	nop
+	.org doload + 0x1000 /* in the second page, mapped by pte1_b */
+	jr ra
+	li      a0, MAGIC2
+	/* we should not get there */
+	EXIT(2)
+	nop
+
+	.data
+	.word MAGIC1
+testval:
+	.word MAGIC2
+	.globl pte2_a
+
+/*
+ * two PD with two different PTE2 for code: check that itlb points to
+ * the right one by executing 2 different code at the same address
+ */
+pte2_a:
+	.align 12
+	.word PTE2_V | PTE2_C | PTE2_X
+	.word BOOT_ADDRESS >> 12
+	.word PTE2_V | PTE2_C | PTE2_X
+	.word (BOOT_ADDRESS+0x1000) >> 12
+	.org pte2_a + 4092
+	.word 0
+	.globl pte2_b
+pte2_b:
+	.align 12
+	.word PTE2_V | PTE2_C | PTE2_X
+	.word BOOT_ADDRESS >> 12
+	.word PTE2_V | PTE2_C | PTE2_X
+	.word (BOOT_ADDRESS+0x2000) >> 12
+	.org pte2_b + 4092
+	.word 0
+	.globl pte1_a
+pte1_a:
+	.align 13
+	.word PTE1_V | PTE1_C | PTE1_W | 0x0 /* map PA 0 at VA 0 */
+	.word 0x0
+	.org pte1_a + (BOOT_ADDRESS >> 21) * 4
+	.word PTE1_V | PTE1_T | (0x1000 >> 12) /* map PA 0xbfc00000 at VA 0xbfc00000 with 4k page: check real address of pte2_a !!! */
+	.org pte1_a + (TTY_BASE >> 21) * 4
+	.word PTE1_V | PTE1_W | (TTY_BASE >> 21) /* map PA 0xd0200000 at VA 0xd0200000 */
+	.org pte1_a + (EXIT_BASE >> 21) * 4
+	.word PTE1_V | PTE1_W | (EXIT_BASE >> 21) /* map PA 0xe0000000 at VA 0xe0000000 */
+	.org pte1_a + 8192
+	.globl pte1_b
+pte1_b:
+	.align 13
+	.word PTE1_V | PTE1_C | PTE1_W | 0x0 /* map PA 0 at VA 0 */
+	.word 0x0
+	.org pte1_b + (BOOT_ADDRESS >> 21) * 4
+	.word PTE1_V | PTE1_T | (0x2000 >> 12) /* map PA 0xbfc00000 at VA 0xbfc00000 with 4k page: check real address of pte2_b !!! */
+	.org pte1_b + (TTY_BASE >> 21) * 4
+	.word PTE1_V | PTE1_W | (TTY_BASE >> 21) /* map PA 0xd0200000 at VA 0xd0200000 */
+	.org pte1_b + (EXIT_BASE >> 21) * 4
+	.word PTE1_V | PTE1_W | (EXIT_BASE >> 21) /* map PA 0xe0000000 at VA 0xe0000000 */
+	.org pte1_b + 8188
+	.word 0
Index: branches/v4/softs/tests_ccvcache_v4/test_llsc/Makefile
===================================================================
--- branches/v4/softs/tests_ccvcache_v4/test_llsc/Makefile	(revision 371)
+++ branches/v4/softs/tests_ccvcache_v4/test_llsc/Makefile	(revision 371)
@@ -0,0 +1,1 @@
+include ../Makefile.inc
Index: branches/v4/softs/tests_ccvcache_v4/test_llsc/run
===================================================================
--- branches/v4/softs/tests_ccvcache_v4/test_llsc/run	(revision 371)
+++ branches/v4/softs/tests_ccvcache_v4/test_llsc/run	(revision 371)
@@ -0,0 +1,28 @@
+#!/bin/sh 
+
+. ../common/common.sh
+
+check_output()
+{
+	egrep "^0x0000DEAD 0x0000DEAD 0x0000BEEF 0x0000DEAD$" run.out > /dev/null
+	if [ $? -eq 0 ]; then
+		return 0;
+	fi
+	echo "couldn't find string in output - mtty not working ?" >> run.out
+	return 1
+}
+
+make --quiet || exit 1
+${SIMUL} > run.out 2>&1 
+if [ $? -eq 0 ]; then
+	if check_output; then
+		echo "test passsed";
+		make --quiet clean
+		exit 0;
+	fi
+	echo "test FAILED"
+	exit 1
+fi
+echo "test FAILED"
+exit 1
+
Index: branches/v4/softs/tests_ccvcache_v4/test_llsc/test.S
===================================================================
--- branches/v4/softs/tests_ccvcache_v4/test_llsc/test.S	(revision 371)
+++ branches/v4/softs/tests_ccvcache_v4/test_llsc/test.S	(revision 371)
@@ -0,0 +1,113 @@
+/*
+ * Check interraction between cached read/write and ll/sc
+ */
+#include <registers.h>
+#include <misc.h>
+#include <vcache.h>
+
+	.text
+	.globl  _start
+_start:
+	.set noreorder
+	la	k0, TTY_BASE
+	la	k1, EXIT_BASE
+
+	/* reset cop0 status (keep BEV) */
+	lui	a0, 0x0040;
+	mtc0	a0, COP0_STATUS
+
+	la	a0, pte1
+	srl	a0, a0, 13
+	mtc2	a0, VC_PTPR
+	nop
+
+	li	a0, VC_TLB_EN_ITLB | VC_TLB_EN_DTLB | VC_TLB_EN_ICACHE | VC_TLB_EN_DCACHE
+	mtc2 	a0, VC_TLB_EN
+
+	/* make sure myvar is in cache */
+	la	s1, myvar 
+	lw	a0, 0(s1)
+	PRINTX
+	PUTCHAR(' ')
+
+	/* now write to myvar via ll/sc */
+	la	s1, myvar 
+1:
+	ll	a0, 0(s1)
+	li	a1, MAGIC2
+	sc	a1, 0(s1)
+	beqz	a1, 1b
+	nop
+
+	PRINTX /* print what we read with ll */
+	PUTCHAR(' ')
+
+	la	s1, myvar 
+	lw	a0, 0(s1) /* print the new value */
+	PRINTX
+	PUTCHAR(' ')
+
+	/* restore myvar value via normal write */
+	la	s1, myvar 
+	li	a1, MAGIC1
+	sw	a1, 0(s1)
+
+	/* read myvar */
+	lw	a0, 0(s1)
+	PRINTX
+	PUTCHAR('\n');
+	
+	EXIT(0)
+
+	.globl excep
+excep:
+	.set noreorder
+	PRINT(statusstr)
+	mfc0	a0, COP0_STATUS
+	PRINTX
+
+	PRINT(causestr)
+	mfc0	a0, COP0_CAUSE
+	PRINTX
+
+	PRINT(pcstr)
+	mfc0	a0, COP0_EXPC
+	PRINTX
+
+	PRINT(badvastr)
+	mfc0	a0, COP_0_BADVADDR
+	PRINTX
+
+	PUTCHAR('\n')
+	/* we should not get there */
+	EXIT(1)
+
+	.rodata:
+statusstr: .ascii "status \0"
+causestr: .ascii " cause \0"
+pcstr: .ascii " pc \0"
+badvastr: .ascii " badva \0"
+value:	.word 0x1234abcd
+string: .ascii "hello world \0"
+
+	.org EXCEP_ADDRESS - BOOT_ADDRESS
+	.globl evect
+evect:
+	j	excep
+	nop
+
+	.data
+myvar:	.word MAGIC1
+	.globl pte1
+pte1:
+	.align 13
+	.word PTE1_V | PTE1_W | 0x0 /* map PA 0 at VA 0 */
+	.org pte1 + (BOOT_ADDRESS >> 21) * 4
+	.word PTE1_V | PTE1_C | PTE1_X | (BOOT_ADDRESS >> 21) /* map PA 0xbfc00000 at VA 0xbfc00000 */
+	.org pte1 + (TTY_BASE >> 21) * 4
+	.word PTE1_V | PTE1_W | (TTY_BASE >> 21) /* map PA 0xd0200000 at VA 0xd0200000 */
+	.org pte1 + (EXIT_BASE >> 21) * 4
+	.word PTE1_V | PTE1_W | (EXIT_BASE >> 21) /* map PA 0xe0000000 at VA 0xe0000000 */
+	.org pte1 + 8192
+	.word 0
+
Index: branches/v4/softs/tests_ccvcache_v4/test_mmu_basic/Makefile
===================================================================
--- branches/v4/softs/tests_ccvcache_v4/test_mmu_basic/Makefile	(revision 371)
+++ branches/v4/softs/tests_ccvcache_v4/test_mmu_basic/Makefile	(revision 371)
@@ -0,0 +1,1 @@
+include ../Makefile.inc
Index: branches/v4/softs/tests_ccvcache_v4/test_mmu_basic/mtty0
===================================================================
--- branches/v4/softs/tests_ccvcache_v4/test_mmu_basic/mtty0	(revision 371)
+++ branches/v4/softs/tests_ccvcache_v4/test_mmu_basic/mtty0	(revision 371)
@@ -0,0 +1,4 @@
+[20hstart
+mmu started
+0x00200000: 0x0000DEAD
+0x00000000: status 0x00400006 cause 0x0000001C pc 0xBFC00098 badva 0x00000000
Index: branches/v4/softs/tests_ccvcache_v4/test_mmu_basic/run
===================================================================
--- branches/v4/softs/tests_ccvcache_v4/test_mmu_basic/run	(revision 371)
+++ branches/v4/softs/tests_ccvcache_v4/test_mmu_basic/run	(revision 371)
@@ -0,0 +1,33 @@
+#!/bin/sh 
+
+. ../common/common.sh
+
+check_output()
+{
+	egrep "^0x00200000: 0x0000DEAD$" run.out > /dev/null
+	if [ $? -ne 0 ]; then
+		echo "couldn't find string 1 in output - mtty not working ?" >> run.out
+		return 1
+	fi
+	egrep "^0x00000000: status 0x00400006 cause 0x0000001C pc 0xBFC00098 badva 0x00000000$" run.out > /dev/null
+	if [ $? -ne 0 ]; then
+		echo "couldn't find string 2 in output - mtty not working ?" >> run.out
+		return 1
+	fi
+	return 0;
+}
+
+make --quiet || exit 1
+${SIMUL} > run.out 2>&1 
+if [ $? -eq 0 ]; then
+	if check_output; then
+		echo "test passsed";
+		make --quiet clean
+		exit 0;
+	fi
+	echo "test FAILED"
+	exit 1
+fi
+echo "test FAILED"
+exit 1
+
Index: branches/v4/softs/tests_ccvcache_v4/test_mmu_basic/test.S
===================================================================
--- branches/v4/softs/tests_ccvcache_v4/test_mmu_basic/test.S	(revision 371)
+++ branches/v4/softs/tests_ccvcache_v4/test_mmu_basic/test.S	(revision 371)
@@ -0,0 +1,102 @@
+/*
+ * Basic MMU checks: we can read mapped addresses, we can't read unmapped
+ * addresses
+ */
+#include <registers.h>
+#include <misc.h>
+#include <vcache.h>
+
+	.text
+	.globl  _start
+_start:
+	.set noreorder
+	la	k0, TTY_BASE
+	la	k1, EXIT_BASE
+
+	PRINT(startstr)
+
+	la	a0, pte1
+	srl	a0, a0, 13
+	mtc2	a0, VC_PTPR
+	nop
+
+	li	a0, VC_TLB_EN_ITLB | VC_TLB_EN_DTLB | VC_TLB_EN_ICACHE | VC_TLB_EN_DCACHE
+	mtc2 	a0, VC_TLB_EN
+
+	PRINT(mmustr)
+
+	/* we can read our magic number at 0x00200000 */
+	la	s0, 0x00200000
+	move	a0, s0
+	PRINTX
+	PUTCHAR(':')
+	PUTCHAR(' ')
+	lw	a0, 0(s0)
+	PRINTX
+	PUTCHAR('\n')
+	/* but not at 0x00000000 */
+	la	s0, 0x00000000
+	move	a0, s0
+	PRINTX
+	PUTCHAR(':')
+	PUTCHAR(' ')
+	lw	a0, 0(s0) /* this should trigger the exception */
+	PRINTX
+
+	/* we shouldn't get there */
+        EXIT(1)
+
+	.globl excep
+excep:
+	.set noreorder
+	PRINT(statusstr)
+	mfc0	a0, COP0_STATUS
+	PRINTX
+
+	PRINT(causestr)
+	mfc0	a0, COP0_CAUSE
+	PRINTX
+
+	PRINT(pcstr)
+	mfc0	a0, COP0_EXPC
+	PRINTX
+
+	PRINT(badvastr)
+	mfc0	a0, COP_0_BADVADDR
+	PRINTX
+
+	li	a0, '\n'
+	sb	a0, 0(k0)
+
+        EXIT(0)
+
+	.rodata:
+statusstr: .ascii "status \0"
+causestr: .ascii " cause \0"
+pcstr: .ascii " pc \0"
+badvastr: .ascii " badva \0"
+mmustr:	.ascii "mmu started\n\0"
+startstr: .ascii "start\n\0"
+
+	.org EXCEP_ADDRESS - BOOT_ADDRESS
+	.globl evect
+evect:
+	j	excep
+	nop
+	.data
+testval:
+	.word MAGIC1
+	.align 13
+	.globl pte1
+pte1:
+	.word 0x0                            /* map PA 0 at VA 0 */
+	.word PTE1_V | PTE1_C | PTE1_W | 0x0 /* map PA 0 at VA 0x00200000 */
+	.org pte1 + (BOOT_ADDRESS >> 21) * 4
+	.word PTE1_V | PTE1_C | PTE1_X | (BOOT_ADDRESS >> 21) /* map PA 0xbfc00000 at VA 0xbfc00000 */
+	.org pte1 + (TTY_BASE >> 21) * 4
+	.word PTE1_V | PTE1_W | (TTY_BASE >> 21) /* map PA 0xd0200000 at VA 0xd0200000 */
+	.org pte1 + (EXIT_BASE >> 21) * 4
+	.word PTE1_V | PTE1_W | (EXIT_BASE >> 21) /* map PA 0xe0000000 at VA 0xe0000000 */
+	.org pte1 + 8192
+	.word 0
+
Index: branches/v4/softs/tests_ccvcache_v4/test_pte2i_ref/Makefile
===================================================================
--- branches/v4/softs/tests_ccvcache_v4/test_pte2i_ref/Makefile	(revision 371)
+++ branches/v4/softs/tests_ccvcache_v4/test_pte2i_ref/Makefile	(revision 371)
@@ -0,0 +1,2 @@
+LDSCRIPT=./ldscript
+include ../Makefile.inc
Index: branches/v4/softs/tests_ccvcache_v4/test_pte2i_ref/ldscript
===================================================================
--- branches/v4/softs/tests_ccvcache_v4/test_pte2i_ref/ldscript	(revision 371)
+++ branches/v4/softs/tests_ccvcache_v4/test_pte2i_ref/ldscript	(revision 371)
@@ -0,0 +1,67 @@
+/*
+ *
+ * SOCLIB_GPL_HEADER_BEGIN
+ * 
+ * This file is part of SoCLib, GNU GPLv2.
+ * 
+ * SoCLib is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ * 
+ * SoCLib is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * General Public License for more details.
+ * 
+ * You should have received a copy of the GNU General Public License
+ * along with SoCLib; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301, USA.
+ * 
+ * SOCLIB_GPL_HEADER_END
+ *
+ * Copyright (c) UPMC, Lip6, SoC
+ *         Nicolas Pouillon <nipo@ssji.net>, 2006-2007
+ *
+ * Maintainers: abdelmalek.si-merabet@lip6.fr
+ */
+ENTRY(_start)
+
+SECTIONS
+{
+   . = 0xbfc00000;
+   .text : {
+      *(.text)
+/* load .text2 one page after .text */
+      . = ALIGN(0x1000);
+      *(.text2)
+   }
+   .rodata : {
+      *(.rodata)
+      . = ALIGN(4);
+   }
+   . = 0x00000000;
+   .data  : {
+      *(.data)
+   }
+   .sdata : {
+      *(.lit8)
+      *(.lit4)
+      *(.sdata)
+   }
+   _gp = .;
+   . = ALIGN(4);
+   _edata = .;
+   .sbss  : {
+      *(.sbss)
+      *(.scommon)
+   }
+   .bss   : {
+      *(.bss)
+      *(COMMON)
+   }
+   . = ALIGN(4);
+   _end = .;
+   _heap = .;
+   _stack = 0x00400000-16;
+}
Index: branches/v4/softs/tests_ccvcache_v4/test_pte2i_ref/mtty0
===================================================================
--- branches/v4/softs/tests_ccvcache_v4/test_pte2i_ref/mtty0	(revision 371)
+++ branches/v4/softs/tests_ccvcache_v4/test_pte2i_ref/mtty0	(revision 371)
@@ -0,0 +1,2 @@
+[20hstart
+mmu started 0x8A000000 0xAA000000 0xAA000000
Index: branches/v4/softs/tests_ccvcache_v4/test_pte2i_ref/run
===================================================================
--- branches/v4/softs/tests_ccvcache_v4/test_pte2i_ref/run	(revision 371)
+++ branches/v4/softs/tests_ccvcache_v4/test_pte2i_ref/run	(revision 371)
@@ -0,0 +1,28 @@
+#!/bin/sh 
+
+. ../common/common.sh
+
+check_output()
+{
+	egrep "^mmu started 0x8A000000 0xAA000000 0xAA000000$" run.out > /dev/null
+	if [ $? -ne 0 ]; then
+		echo "couldn't find string in output - mtty not working ?" >> run.out
+		return 1
+	fi
+	return 0;
+}
+
+make --quiet || exit 1
+${SIMUL} > run.out 2>&1 
+if [ $? -eq 0 ]; then
+	if check_output; then
+		echo "test passsed";
+		make --quiet clean
+		exit 0;
+	fi
+	echo "test FAILED"
+	exit 1
+fi
+echo "test FAILED"
+exit 1
+
Index: branches/v4/softs/tests_ccvcache_v4/test_pte2i_ref/test.S
===================================================================
--- branches/v4/softs/tests_ccvcache_v4/test_pte2i_ref/test.S	(revision 371)
+++ branches/v4/softs/tests_ccvcache_v4/test_pte2i_ref/test.S	(revision 371)
@@ -0,0 +1,144 @@
+/*
+ * instruction fetch causes the PTE_L bit to be set
+ */
+#include <registers.h>
+#include <misc.h>
+#include <vcache.h>
+
+	.text
+	.globl  _start
+_start:
+	.set noreorder
+	la	k0, TTY_BASE
+	la	k1, EXIT_BASE
+
+	PRINT(startstr)
+
+	/* reset cop0 status (keep BEV) */
+	lui	a0, 0x0040;
+	mtc0	a0, COP0_STATUS
+
+	la	a0, pte1_a
+	srl	a0, a0, 13
+	mtc2	a0, VC_PTPR
+	nop
+
+	li	a0, VC_TLB_EN_ITLB | VC_TLB_EN_DTLB | VC_TLB_EN_ICACHE | VC_TLB_EN_DCACHE
+	mtc2 	a0, VC_TLB_EN
+
+	PRINT(mmustr)
+	la	s0, pte2_a
+	lw	s1, 8(s0)
+	move	a0, s1
+	PRINTX
+	PUTCHAR(' ')
+	la	a1, PTE2_L
+	and	a0, s1, a1
+	beq	a0, a1, fail /* PTE2_L already set, not good */
+	nop
+	jal	doload /* cause page to be referenced */
+	nop
+	lw	s1, 8(s0)
+	move	a0, s1
+	PRINTX
+	PUTCHAR(' ')
+	la	a1, PTE2_L
+	and	a0, s1, a1
+	bne	a0, a1, fail /* PTE2_L not set not good */
+	nop
+	/* check again, using ll */
+	ll	s1, 8(s0)
+	move	a0, s1
+	PRINTX
+	PUTCHAR('\n')
+	la	a1, PTE2_L
+	and	a0, s1, a1
+	bne	a0, a1, fail /* PTE2_L not set not good */
+	nop
+	EXIT(0)
+fail:
+	/* we should not get there */
+	EXIT(1)
+
+	.globl excep
+excep:
+	.set noreorder
+	PRINT(statusstr)
+	mfc0	a0, COP0_STATUS
+	PRINTX
+
+	PRINT(causestr)
+	mfc0	a0, COP0_CAUSE
+	PRINTX
+
+	PRINT(pcstr)
+	mfc0	a0, COP0_EXPC
+	PRINTX
+
+	PRINT(badvastr)
+	mfc0	a0, COP_0_BADVADDR
+	PRINTX
+
+	PUTCHAR('\n')
+	/* we should get there */
+	EXIT(0)
+
+	.rodata:
+statusstr: .ascii "status \0"
+causestr: .ascii " cause \0"
+pcstr: .ascii " pc \0"
+badvastr: .ascii " badva \0"
+mmustr: .ascii "mmu started \0"
+startstr: .ascii "start\n\0"
+
+	.org EXCEP_ADDRESS - BOOT_ADDRESS
+	.globl evect
+evect:
+	j	excep
+	nop
+
+	/*
+	 * code that will be switched by MMU switch.
+	 * we use a ldscript trick here, to load this function at
+	 * the appropriate address
+	 */
+	.section .text2, "ax"
+	.globl doload
+doload:
+	jr      ra
+	li      a0, MAGIC1
+	/* we should not get there */
+	EXIT(1)
+	nop
+
+	.data
+	.word MAGIC1
+testval:
+	.word MAGIC2
+	.globl pte2_a
+
+/*
+ * one PD with a level 2 PTP: we invalidate an entry in the PTP and
+ * check that the VA is no longer accessible
+ */
+pte2_a:
+	.align 12
+	.word PTE2_V | PTE2_C | PTE2_X
+	.word BOOT_ADDRESS >> 12
+	.word PTE2_V | PTE2_C | PTE2_X
+	.word (BOOT_ADDRESS+0x1000) >> 12
+	.org pte2_a + 4092
+	.word 0
+	.globl pte2_b
+	.globl pte1_a
+pte1_a:
+	.align 13
+	.word PTE1_V | PTE1_C | PTE1_W | 0x0 /* map PA 0 at VA 0 */
+	.word 0x0
+	.org pte1_a + (BOOT_ADDRESS >> 21) * 4
+	.word PTE1_V | PTE1_T | (0x1000 >> 12) /* map PA 0xbfc00000 at VA 0xbfc00000 with 4k page: check real address of pte2_a !!! */
+	.org pte1_a + (TTY_BASE >> 21) * 4
+	.word PTE1_V | PTE1_W | (TTY_BASE >> 21) /* map PA 0xd0200000 at VA 0xd0200000 */
+	.org pte1_a + (EXIT_BASE >> 21) * 4
+	.word PTE1_V | PTE1_W | (EXIT_BASE >> 21) /* map PA 0xe0000000 at VA 0xe0000000 */
+	.org pte1_a + 8192
Index: branches/v4/softs/tests_ccvcache_v4/test_pte2ll_ref/Makefile
===================================================================
--- branches/v4/softs/tests_ccvcache_v4/test_pte2ll_ref/Makefile	(revision 371)
+++ branches/v4/softs/tests_ccvcache_v4/test_pte2ll_ref/Makefile	(revision 371)
@@ -0,0 +1,2 @@
+LDSCRIPT=./ldscript
+include ../Makefile.inc
Index: branches/v4/softs/tests_ccvcache_v4/test_pte2ll_ref/ldscript
===================================================================
--- branches/v4/softs/tests_ccvcache_v4/test_pte2ll_ref/ldscript	(revision 371)
+++ branches/v4/softs/tests_ccvcache_v4/test_pte2ll_ref/ldscript	(revision 371)
@@ -0,0 +1,67 @@
+/*
+ *
+ * SOCLIB_GPL_HEADER_BEGIN
+ * 
+ * This file is part of SoCLib, GNU GPLv2.
+ * 
+ * SoCLib is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ * 
+ * SoCLib is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * General Public License for more details.
+ * 
+ * You should have received a copy of the GNU General Public License
+ * along with SoCLib; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301, USA.
+ * 
+ * SOCLIB_GPL_HEADER_END
+ *
+ * Copyright (c) UPMC, Lip6, SoC
+ *         Nicolas Pouillon <nipo@ssji.net>, 2006-2007
+ *
+ * Maintainers: abdelmalek.si-merabet@lip6.fr
+ */
+ENTRY(_start)
+
+SECTIONS
+{
+   . = 0xbfc00000;
+   .text : {
+      *(.text)
+/* load .text2 one page after .text */
+      . = ALIGN(0x1000);
+      *(.text2)
+   }
+   .rodata : {
+      *(.rodata)
+      . = ALIGN(4);
+   }
+   . = 0x00000000;
+   .data  : {
+      *(.data)
+   }
+   .sdata : {
+      *(.lit8)
+      *(.lit4)
+      *(.sdata)
+   }
+   _gp = .;
+   . = ALIGN(4);
+   _edata = .;
+   .sbss  : {
+      *(.sbss)
+      *(.scommon)
+   }
+   .bss   : {
+      *(.bss)
+      *(COMMON)
+   }
+   . = ALIGN(4);
+   _end = .;
+   _heap = .;
+   _stack = 0x00400000-16;
+}
Index: branches/v4/softs/tests_ccvcache_v4/test_pte2ll_ref/run
===================================================================
--- branches/v4/softs/tests_ccvcache_v4/test_pte2ll_ref/run	(revision 371)
+++ branches/v4/softs/tests_ccvcache_v4/test_pte2ll_ref/run	(revision 371)
@@ -0,0 +1,28 @@
+#!/bin/sh 
+
+. ../common/common.sh
+
+check_output()
+{
+	egrep "^mmu started 0x8A000000 0xAA000000 0xAA000000$" run.out > /dev/null
+	if [ $? -ne 0 ]; then
+		echo "couldn't find string in output - mtty not working ?" >> run.out
+		return 1
+	fi
+	return 0;
+}
+
+make --quiet || exit 1
+${SIMUL} > run.out 2>&1 
+if [ $? -eq 0 ]; then
+	if check_output; then
+		echo "test passsed";
+		make --quiet clean
+		exit 0;
+	fi
+	echo "test FAILED"
+	exit 1
+fi
+echo "test FAILED"
+exit 1
+
Index: branches/v4/softs/tests_ccvcache_v4/test_pte2ll_ref/test.S
===================================================================
--- branches/v4/softs/tests_ccvcache_v4/test_pte2ll_ref/test.S	(revision 371)
+++ branches/v4/softs/tests_ccvcache_v4/test_pte2ll_ref/test.S	(revision 371)
@@ -0,0 +1,132 @@
+/*
+ * pte2d_ref: a ll to data should set referenced bit in PTE
+ */
+#include <registers.h>
+#include <misc.h>
+#include <vcache.h>
+	.text
+	.globl  _start
+_start:
+	.set noreorder
+	la	k0, TTY_BASE
+	la	k1, EXIT_BASE
+
+	PRINT(startstr)
+
+	/* reset cop0 status (keep BEV) */
+	lui	a0, 0x0040;
+	mtc0	a0, COP0_STATUS
+
+	la	a0, pte1_a
+	srl	a0, a0, 13
+	mtc2	a0, VC_PTPR
+	nop
+
+	li	a0, VC_TLB_EN_ITLB | VC_TLB_EN_DTLB | VC_TLB_EN_ICACHE | VC_TLB_EN_DCACHE
+	mtc2 	a0, VC_TLB_EN
+
+	PRINT(mmustr)
+	la 	s0, pte2_a
+	lw	s1, 0(s0) /* get PTE */
+	move	a0, s1
+	PRINTX
+	PUTCHAR(' ')
+	la	a1, PTE2_L
+	and	a0, s1, a1
+	beq	a0, a1, fail /* PTE2_L already set, not good */
+	nop
+
+	la	t0, testval + 0x00200000
+	ll 	a0, 0(t0); /* cause page to be referenced */
+
+	lw	s1, 0(s0) /* get PTE */
+	move	a0, s1
+	PRINTX
+	PUTCHAR(' ')
+	la	a1, PTE2_L
+	and	a0, s1, a1
+	bne	a0, a1, fail /* PTE2_L not set, not good */
+	nop
+
+	/* check again, using ll */
+	ll	s1, 0(s0) /* get PTE */
+	move	a0, s1
+	PRINTX
+	PUTCHAR('\n')
+	la	a1, PTE2_L
+	and	a0, s1, a1
+	bne	a0, a1, fail /* PTE2_L not set, not good */
+	nop
+
+	EXIT(0)
+fail:
+	/* we should not get there */
+	EXIT(1)
+
+	.globl excep
+excep:
+	.set noreorder
+	PRINT(statusstr)
+	mfc0	a0, COP0_STATUS
+	PRINTX
+
+	PRINT(causestr)
+	mfc0	a0, COP0_CAUSE
+	PRINTX
+
+	PRINT(pcstr)
+	mfc0	a0, COP0_EXPC
+	PRINTX
+
+	PRINT(badvastr)
+	mfc0	a0, COP_0_BADVADDR
+	PRINTX
+
+	PUTCHAR('\n')
+	/* we should get there */
+	EXIT(0)
+
+	.rodata:
+statusstr: .ascii "status \0"
+causestr: .ascii " cause \0"
+pcstr: .ascii " pc \0"
+badvastr: .ascii " badva \0"
+mmustr: .ascii "mmu started \0"
+startstr: .ascii "start\n\0"
+
+	.org EXCEP_ADDRESS - BOOT_ADDRESS
+	.globl evect
+evect:
+	j	excep
+	nop
+
+	.data
+	/* first 2 pages is data that will be switched my mmu switch */
+data_a:
+	.word MAGIC1
+testval:
+	.word MAGIC2
+	.globl pte2_a
+/*
+ * one PD with a level 2 PTP: we invalidate an entry in the PTP and
+ * check that the VA is no longer accessible
+ */
+pte2_a:
+	.align 12
+	.word PTE2_V | PTE2_C | PTE2_X
+	.word 0x0000 >> 12 /* check real value of data_a */
+	.org pte2_a + 4092
+	.word 0
+	.globl pte2_b
+	.globl pte1_a
+pte1_a:
+	.align 13
+	.word PTE1_V | PTE1_C | PTE1_W | 0x0 /* map PA 0 at VA 0 */
+	.word PTE1_V | PTE1_T | (0x1000 >> 12) /* map PA 0x0 at VA 0x00200000 via pte2_a */
+	.org pte1_a + (BOOT_ADDRESS >> 21) * 4
+	.word PTE1_V | PTE1_C | PTE1_X | (BOOT_ADDRESS >> 21) /* map PA 0xbfc00000 at VA 0xbfc00000 */
+	.org pte1_a + (TTY_BASE >> 21) * 4
+	.word PTE1_V | PTE1_W | (TTY_BASE >> 21) /* map PA 0xd0200000 at VA 0xd0200000 */
+	.org pte1_a + (EXIT_BASE >> 21) * 4
+	.word PTE1_V | PTE1_W | (EXIT_BASE >> 21) /* map PA 0xe0000000 at VA 0xe0000000 */
+	.org pte1_a + 8192
Index: branches/v4/softs/tests_ccvcache_v4/test_pte2lw_ref/Makefile
===================================================================
--- branches/v4/softs/tests_ccvcache_v4/test_pte2lw_ref/Makefile	(revision 371)
+++ branches/v4/softs/tests_ccvcache_v4/test_pte2lw_ref/Makefile	(revision 371)
@@ -0,0 +1,2 @@
+LDSCRIPT=./ldscript
+include ../Makefile.inc
Index: branches/v4/softs/tests_ccvcache_v4/test_pte2lw_ref/ldscript
===================================================================
--- branches/v4/softs/tests_ccvcache_v4/test_pte2lw_ref/ldscript	(revision 371)
+++ branches/v4/softs/tests_ccvcache_v4/test_pte2lw_ref/ldscript	(revision 371)
@@ -0,0 +1,67 @@
+/*
+ *
+ * SOCLIB_GPL_HEADER_BEGIN
+ * 
+ * This file is part of SoCLib, GNU GPLv2.
+ * 
+ * SoCLib is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ * 
+ * SoCLib is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * General Public License for more details.
+ * 
+ * You should have received a copy of the GNU General Public License
+ * along with SoCLib; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301, USA.
+ * 
+ * SOCLIB_GPL_HEADER_END
+ *
+ * Copyright (c) UPMC, Lip6, SoC
+ *         Nicolas Pouillon <nipo@ssji.net>, 2006-2007
+ *
+ * Maintainers: abdelmalek.si-merabet@lip6.fr
+ */
+ENTRY(_start)
+
+SECTIONS
+{
+   . = 0xbfc00000;
+   .text : {
+      *(.text)
+/* load .text2 one page after .text */
+      . = ALIGN(0x1000);
+      *(.text2)
+   }
+   .rodata : {
+      *(.rodata)
+      . = ALIGN(4);
+   }
+   . = 0x00000000;
+   .data  : {
+      *(.data)
+   }
+   .sdata : {
+      *(.lit8)
+      *(.lit4)
+      *(.sdata)
+   }
+   _gp = .;
+   . = ALIGN(4);
+   _edata = .;
+   .sbss  : {
+      *(.sbss)
+      *(.scommon)
+   }
+   .bss   : {
+      *(.bss)
+      *(COMMON)
+   }
+   . = ALIGN(4);
+   _end = .;
+   _heap = .;
+   _stack = 0x00400000-16;
+}
Index: branches/v4/softs/tests_ccvcache_v4/test_pte2lw_ref/run
===================================================================
--- branches/v4/softs/tests_ccvcache_v4/test_pte2lw_ref/run	(revision 371)
+++ branches/v4/softs/tests_ccvcache_v4/test_pte2lw_ref/run	(revision 371)
@@ -0,0 +1,28 @@
+#!/bin/sh 
+
+. ../common/common.sh
+
+check_output()
+{
+	egrep "^mmu started 0x8A000000 0xAA000000 0xAA000000$" run.out > /dev/null
+	if [ $? -ne 0 ]; then
+		echo "couldn't find string in output - mtty not working ?" >> run.out
+		return 1
+	fi
+	return 0;
+}
+
+make --quiet || exit 1
+${SIMUL} > run.out 2>&1 
+if [ $? -eq 0 ]; then
+	if check_output; then
+		echo "test passsed";
+		make --quiet clean
+		exit 0;
+	fi
+	echo "test FAILED"
+	exit 1
+fi
+echo "test FAILED"
+exit 1
+
Index: branches/v4/softs/tests_ccvcache_v4/test_pte2lw_ref/test.S
===================================================================
--- branches/v4/softs/tests_ccvcache_v4/test_pte2lw_ref/test.S	(revision 371)
+++ branches/v4/softs/tests_ccvcache_v4/test_pte2lw_ref/test.S	(revision 371)
@@ -0,0 +1,132 @@
+/*
+ * pte2d_ref: a lw to data should set referenced bit in PTE
+ */
+#include <registers.h>
+#include <misc.h>
+#include <vcache.h>
+	.text
+	.globl  _start
+_start:
+	.set noreorder
+	la	k0, TTY_BASE
+	la	k1, EXIT_BASE
+
+	PRINT(startstr)
+
+	/* reset cop0 status (keep BEV) */
+	lui	a0, 0x0040;
+	mtc0	a0, COP0_STATUS
+
+	la	a0, pte1_a
+	srl	a0, a0, 13
+	mtc2	a0, VC_PTPR
+	nop
+
+	li	a0, VC_TLB_EN_ITLB | VC_TLB_EN_DTLB | VC_TLB_EN_ICACHE | VC_TLB_EN_DCACHE
+	mtc2 	a0, VC_TLB_EN
+
+	PRINT(mmustr)
+	la 	s0, pte2_a
+	lw	s1, 0(s0) /* get PTE */
+	move	a0, s1
+	PRINTX
+	PUTCHAR(' ')
+	la	a1, PTE2_L
+	and	a0, s1, a1
+	beq	a0, a1, fail /* PTE2_L already set, not good */
+	nop
+
+	la	t0, testval + 0x00200000
+	lw 	a0, 0(t0); /* cause page to be referenced */
+
+	lw	s1, 0(s0) /* get PTE */
+	move	a0, s1
+	PRINTX
+	PUTCHAR(' ')
+	la	a1, PTE2_L
+	and	a0, s1, a1
+	bne	a0, a1, fail /* PTE2_L not set, not good */
+	nop
+
+	/* check again, using ll */
+	ll	s1, 0(s0) /* get PTE */
+	move	a0, s1
+	PRINTX
+	PUTCHAR('\n')
+	la	a1, PTE2_L
+	and	a0, s1, a1
+	bne	a0, a1, fail /* PTE2_L not set, not good */
+	nop
+
+	EXIT(0)
+fail:
+	/* we should not get there */
+	EXIT(1)
+
+	.globl excep
+excep:
+	.set noreorder
+	PRINT(statusstr)
+	mfc0	a0, COP0_STATUS
+	PRINTX
+
+	PRINT(causestr)
+	mfc0	a0, COP0_CAUSE
+	PRINTX
+
+	PRINT(pcstr)
+	mfc0	a0, COP0_EXPC
+	PRINTX
+
+	PRINT(badvastr)
+	mfc0	a0, COP_0_BADVADDR
+	PRINTX
+
+	PUTCHAR('\n')
+	/* we should get there */
+	EXIT(0)
+
+	.rodata:
+statusstr: .ascii "status \0"
+causestr: .ascii " cause \0"
+pcstr: .ascii " pc \0"
+badvastr: .ascii " badva \0"
+mmustr: .ascii "mmu started \0"
+startstr: .ascii "start\n\0"
+
+	.org EXCEP_ADDRESS - BOOT_ADDRESS
+	.globl evect
+evect:
+	j	excep
+	nop
+
+	.data
+	/* first 2 pages is data that will be switched my mmu switch */
+data_a:
+	.word MAGIC1
+testval:
+	.word MAGIC2
+	.globl pte2_a
+/*
+ * one PD with a level 2 PTP: we invalidate an entry in the PTP and
+ * check that the VA is no longer accessible
+ */
+pte2_a:
+	.align 12
+	.word PTE2_V | PTE2_C | PTE2_X
+	.word 0x0000 >> 12 /* check real value of data_a */
+	.org pte2_a + 4092
+	.word 0
+	.globl pte2_b
+	.globl pte1_a
+pte1_a:
+	.align 13
+	.word PTE1_V | PTE1_C | PTE1_W | 0x0 /* map PA 0 at VA 0 */
+	.word PTE1_V | PTE1_T | (0x1000 >> 12) /* map PA 0x0 at VA 0x00200000 via pte2_a */
+	.org pte1_a + (BOOT_ADDRESS >> 21) * 4
+	.word PTE1_V | PTE1_C | PTE1_X | (BOOT_ADDRESS >> 21) /* map PA 0xbfc00000 at VA 0xbfc00000 */
+	.org pte1_a + (TTY_BASE >> 21) * 4
+	.word PTE1_V | PTE1_W | (TTY_BASE >> 21) /* map PA 0xd0200000 at VA 0xd0200000 */
+	.org pte1_a + (EXIT_BASE >> 21) * 4
+	.word PTE1_V | PTE1_W | (EXIT_BASE >> 21) /* map PA 0xe0000000 at VA 0xe0000000 */
+	.org pte1_a + 8192
Index: branches/v4/softs/tests_ccvcache_v4/test_pte2sc_dirty/Makefile
===================================================================
--- branches/v4/softs/tests_ccvcache_v4/test_pte2sc_dirty/Makefile	(revision 371)
+++ branches/v4/softs/tests_ccvcache_v4/test_pte2sc_dirty/Makefile	(revision 371)
@@ -0,0 +1,2 @@
+LDSCRIPT=./ldscript
+include ../Makefile.inc
Index: branches/v4/softs/tests_ccvcache_v4/test_pte2sc_dirty/ldscript
===================================================================
--- branches/v4/softs/tests_ccvcache_v4/test_pte2sc_dirty/ldscript	(revision 371)
+++ branches/v4/softs/tests_ccvcache_v4/test_pte2sc_dirty/ldscript	(revision 371)
@@ -0,0 +1,67 @@
+/*
+ *
+ * SOCLIB_GPL_HEADER_BEGIN
+ * 
+ * This file is part of SoCLib, GNU GPLv2.
+ * 
+ * SoCLib is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ * 
+ * SoCLib is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * General Public License for more details.
+ * 
+ * You should have received a copy of the GNU General Public License
+ * along with SoCLib; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301, USA.
+ * 
+ * SOCLIB_GPL_HEADER_END
+ *
+ * Copyright (c) UPMC, Lip6, SoC
+ *         Nicolas Pouillon <nipo@ssji.net>, 2006-2007
+ *
+ * Maintainers: abdelmalek.si-merabet@lip6.fr
+ */
+ENTRY(_start)
+
+SECTIONS
+{
+   . = 0xbfc00000;
+   .text : {
+      *(.text)
+/* load .text2 one page after .text */
+      . = ALIGN(0x1000);
+      *(.text2)
+   }
+   .rodata : {
+      *(.rodata)
+      . = ALIGN(4);
+   }
+   . = 0x00000000;
+   .data  : {
+      *(.data)
+   }
+   .sdata : {
+      *(.lit8)
+      *(.lit4)
+      *(.sdata)
+   }
+   _gp = .;
+   . = ALIGN(4);
+   _edata = .;
+   .sbss  : {
+      *(.sbss)
+      *(.scommon)
+   }
+   .bss   : {
+      *(.bss)
+      *(COMMON)
+   }
+   . = ALIGN(4);
+   _end = .;
+   _heap = .;
+   _stack = 0x00400000-16;
+}
Index: branches/v4/softs/tests_ccvcache_v4/test_pte2sc_dirty/mtty0
===================================================================
--- branches/v4/softs/tests_ccvcache_v4/test_pte2sc_dirty/mtty0	(revision 371)
+++ branches/v4/softs/tests_ccvcache_v4/test_pte2sc_dirty/mtty0	(revision 371)
@@ -0,0 +1,2 @@
+[20hstart
+mmu started 0x8E000000 0xAE400000 0xAE400000
Index: branches/v4/softs/tests_ccvcache_v4/test_pte2sc_dirty/run
===================================================================
--- branches/v4/softs/tests_ccvcache_v4/test_pte2sc_dirty/run	(revision 371)
+++ branches/v4/softs/tests_ccvcache_v4/test_pte2sc_dirty/run	(revision 371)
@@ -0,0 +1,28 @@
+#!/bin/sh 
+
+. ../common/common.sh
+
+check_output()
+{
+	egrep "^mmu started 0x8E000000 0xAE400000 0xAE400000$" run.out > /dev/null
+	if [ $? -ne 0 ]; then
+		echo "couldn't find string in output - mtty not working ?" >> run.out
+		return 1
+	fi
+	return 0;
+}
+
+make --quiet || exit 1
+${SIMUL} > run.out 2>&1 
+if [ $? -eq 0 ]; then
+	if check_output; then
+		echo "test passsed";
+		make --quiet clean
+		exit 0;
+	fi
+	echo "test FAILED"
+	exit 1
+fi
+echo "test FAILED"
+exit 1
+
Index: branches/v4/softs/tests_ccvcache_v4/test_pte2sc_dirty/test.S
===================================================================
--- branches/v4/softs/tests_ccvcache_v4/test_pte2sc_dirty/test.S	(revision 371)
+++ branches/v4/softs/tests_ccvcache_v4/test_pte2sc_dirty/test.S	(revision 371)
@@ -0,0 +1,137 @@
+/*
+ * pte2d_ref: a sc to data should set the dirty bits in PTE
+ */
+#include <registers.h>
+#include <misc.h>
+#include <vcache.h>
+	.text
+	.globl  _start
+_start:
+	.set noreorder
+	la	k0, TTY_BASE
+	la	k1, EXIT_BASE
+
+	PRINT(startstr)
+
+	/* reset cop0 status (keep BEV) */
+	lui	a0, 0x0040;
+	mtc0	a0, COP0_STATUS
+
+	la	a0, pte1_a
+	srl	a0, a0, 13
+	mtc2	a0, VC_PTPR
+	nop
+
+	li	a0, VC_TLB_EN_ITLB | VC_TLB_EN_DTLB | VC_TLB_EN_ICACHE | VC_TLB_EN_DCACHE
+	mtc2 	a0, VC_TLB_EN
+
+	PRINT(mmustr)
+	la 	s0, pte2_a
+	lw	s1, 0(s0) /* get PTE */
+	move	a0, s1
+	PRINTX
+	PUTCHAR(' ')
+	la	a1, (PTE2_L | PTE2_D)
+	and	a0, s1, a1
+	bne	a0, zero, fail /* PTE2_L or PTE2_D already set, not good */
+	nop
+
+	la	t0, testval + 0x00200000
+	la	a1, MAGIC3
+1:
+	ll	a0, 0(t0)
+	sc 	a1, 0(t0); /* cause page to be referenced and dirty */
+	beqz	a1, 1b
+	nop
+
+	lw	s1, 0(s0) /* get PTE */
+	move	a0, s1
+	PRINTX
+	PUTCHAR(' ')
+	la	a1, (PTE2_L | PTE2_D)
+	and	a0, s1, a1
+	bne	a0, a1, fail /* PTE2_L not set, not good */
+	nop
+
+	/* check again, using ll */
+	ll	s1, 0(s0) /* get PTE */
+	move	a0, s1
+	PRINTX
+	PUTCHAR('\n')
+	la	a1, (PTE2_L | PTE2_D)
+	and	a0, s1, a1
+	bne	a0, a1, fail /* PTE2_L not set, not good */
+	nop
+
+	EXIT(0)
+fail:
+	/* we should not get there */
+	EXIT(1)
+
+	.globl excep
+excep:
+	.set noreorder
+	PRINT(statusstr)
+	mfc0	a0, COP0_STATUS
+	PRINTX
+
+	PRINT(causestr)
+	mfc0	a0, COP0_CAUSE
+	PRINTX
+
+	PRINT(pcstr)
+	mfc0	a0, COP0_EXPC
+	PRINTX
+
+	PRINT(badvastr)
+	mfc0	a0, COP_0_BADVADDR
+	PRINTX
+
+	PUTCHAR('\n')
+	/* we should get there */
+	EXIT(0)
+
+	.rodata:
+statusstr: .ascii "status \0"
+causestr: .ascii " cause \0"
+pcstr: .ascii " pc \0"
+badvastr: .ascii " badva \0"
+mmustr: .ascii "mmu started \0"
+startstr: .ascii "start\n\0"
+
+	.org EXCEP_ADDRESS - BOOT_ADDRESS
+	.globl evect
+evect:
+	j	excep
+	nop
+
+	.data
+	/* first 2 pages is data that will be switched my mmu switch */
+data_a:
+	.word MAGIC1
+testval:
+	.word MAGIC2
+	.globl pte2_a
+/*
+ * one PD with a level 2 PTP: we invalidate an entry in the PTP and
+ * check that the VA is no longer accessible
+ */
+pte2_a:
+	.align 12
+	.word PTE2_V | PTE2_C | PTE2_X | PTE2_W
+	.word 0x0000 >> 12 /* check real value of data_a */
+	.org pte2_a + 4092
+	.word 0
+	.globl pte2_b
+	.globl pte1_a
+pte1_a:
+	.align 13
+	.word PTE1_V | PTE1_C | PTE1_W | 0x0 /* map PA 0 at VA 0 */
+	.word PTE1_V | PTE1_T | (0x1000 >> 12) /* map PA 0x0 at VA 0x00200000 via pte2_a */
+	.org pte1_a + (BOOT_ADDRESS >> 21) * 4
+	.word PTE1_V | PTE1_C | PTE1_X | (BOOT_ADDRESS >> 21) /* map PA 0xbfc00000 at VA 0xbfc00000 */
+	.org pte1_a + (TTY_BASE >> 21) * 4
+	.word PTE1_V | PTE1_W | (TTY_BASE >> 21) /* map PA 0xd0200000 at VA 0xd0200000 */
+	.org pte1_a + (EXIT_BASE >> 21) * 4
+	.word PTE1_V | PTE1_W | (EXIT_BASE >> 21) /* map PA 0xe0000000 at VA 0xe0000000 */
+	.org pte1_a + 8192
Index: branches/v4/softs/tests_ccvcache_v4/test_pte2sc_dirty/vcitty0
===================================================================
--- branches/v4/softs/tests_ccvcache_v4/test_pte2sc_dirty/vcitty0	(revision 371)
+++ branches/v4/softs/tests_ccvcache_v4/test_pte2sc_dirty/vcitty0	(revision 371)
@@ -0,0 +1,1 @@
+[20hstart
Index: branches/v4/softs/tests_ccvcache_v4/test_pte2sw_dirty/Makefile
===================================================================
--- branches/v4/softs/tests_ccvcache_v4/test_pte2sw_dirty/Makefile	(revision 371)
+++ branches/v4/softs/tests_ccvcache_v4/test_pte2sw_dirty/Makefile	(revision 371)
@@ -0,0 +1,2 @@
+LDSCRIPT=./ldscript
+include ../Makefile.inc
Index: branches/v4/softs/tests_ccvcache_v4/test_pte2sw_dirty/ldscript
===================================================================
--- branches/v4/softs/tests_ccvcache_v4/test_pte2sw_dirty/ldscript	(revision 371)
+++ branches/v4/softs/tests_ccvcache_v4/test_pte2sw_dirty/ldscript	(revision 371)
@@ -0,0 +1,67 @@
+/*
+ *
+ * SOCLIB_GPL_HEADER_BEGIN
+ * 
+ * This file is part of SoCLib, GNU GPLv2.
+ * 
+ * SoCLib is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ * 
+ * SoCLib is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * General Public License for more details.
+ * 
+ * You should have received a copy of the GNU General Public License
+ * along with SoCLib; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301, USA.
+ * 
+ * SOCLIB_GPL_HEADER_END
+ *
+ * Copyright (c) UPMC, Lip6, SoC
+ *         Nicolas Pouillon <nipo@ssji.net>, 2006-2007
+ *
+ * Maintainers: abdelmalek.si-merabet@lip6.fr
+ */
+ENTRY(_start)
+
+SECTIONS
+{
+   . = 0xbfc00000;
+   .text : {
+      *(.text)
+/* load .text2 one page after .text */
+      . = ALIGN(0x1000);
+      *(.text2)
+   }
+   .rodata : {
+      *(.rodata)
+      . = ALIGN(4);
+   }
+   . = 0x00000000;
+   .data  : {
+      *(.data)
+   }
+   .sdata : {
+      *(.lit8)
+      *(.lit4)
+      *(.sdata)
+   }
+   _gp = .;
+   . = ALIGN(4);
+   _edata = .;
+   .sbss  : {
+      *(.sbss)
+      *(.scommon)
+   }
+   .bss   : {
+      *(.bss)
+      *(COMMON)
+   }
+   . = ALIGN(4);
+   _end = .;
+   _heap = .;
+   _stack = 0x00400000-16;
+}
Index: branches/v4/softs/tests_ccvcache_v4/test_pte2sw_dirty/run
===================================================================
--- branches/v4/softs/tests_ccvcache_v4/test_pte2sw_dirty/run	(revision 371)
+++ branches/v4/softs/tests_ccvcache_v4/test_pte2sw_dirty/run	(revision 371)
@@ -0,0 +1,28 @@
+#!/bin/sh
+
+. ../common/common.sh
+
+check_output()
+{
+	egrep "^mmu started 0x8E000000 0xAE400000 0xAE400000$" run.out > /dev/null
+	if [ $? -ne 0 ]; then
+		echo "couldn't find string in output - mtty not working ?" >> run.out
+		return 1
+	fi
+	return 0;
+}
+
+make --quiet || exit 1
+${SIMUL} > run.out 2>&1 
+if [ $? -eq 0 ]; then
+	if check_output; then
+		echo "test passsed";
+		make --quiet clean
+		exit 0;
+	fi
+	echo "test FAILED"
+	exit 1
+fi
+echo "test FAILED"
+exit 1
+
Index: branches/v4/softs/tests_ccvcache_v4/test_pte2sw_dirty/test.S
===================================================================
--- branches/v4/softs/tests_ccvcache_v4/test_pte2sw_dirty/test.S	(revision 371)
+++ branches/v4/softs/tests_ccvcache_v4/test_pte2sw_dirty/test.S	(revision 371)
@@ -0,0 +1,132 @@
+/*
+ * pte2d_ref: a sw to data should set referenced and dirty bits in PTE
+ */
+#include <registers.h>
+#include <misc.h>
+#include <vcache.h>
+	.text
+	.globl  _start
+_start:
+	.set noreorder
+	la	k0, TTY_BASE
+	la	k1, EXIT_BASE
+
+	PRINT(startstr)
+
+	/* reset cop0 status (keep BEV) */
+	lui	a0, 0x0040;
+	mtc0	a0, COP0_STATUS
+
+	la	a0, pte1_a
+	srl	a0, a0, 13
+	mtc2	a0, VC_PTPR
+	nop
+
+	li	a0, VC_TLB_EN_ITLB | VC_TLB_EN_DTLB | VC_TLB_EN_ICACHE | VC_TLB_EN_DCACHE
+	mtc2 	a0, VC_TLB_EN
+
+	PRINT(mmustr)
+	la 	s0, pte2_a
+	lw	s1, 0(s0) /* get PTE */
+	move	a0, s1
+	PRINTX
+	PUTCHAR(' ')
+	la	a1, (PTE2_L | PTE2_D)
+	and	a0, s1, a1
+	bne	a0, zero, fail /* PTE2_L or PTE2_D already set, not good */
+	nop
+
+	la	t0, testval + 0x00200000
+	sw 	a0, 0(t0); /* cause page to be referenced and dirty */
+
+	lw	s1, 0(s0) /* get PTE */
+	move	a0, s1
+	PRINTX
+	PUTCHAR(' ')
+	la	a1, (PTE2_L | PTE2_D)
+	and	a0, s1, a1
+	bne	a0, a1, fail /* PTE2_L not set, not good */
+	nop
+
+	/* check again, using ll */
+	ll	s1, 0(s0) /* get PTE */
+	move	a0, s1
+	PRINTX
+	PUTCHAR('\n')
+	la	a1, (PTE2_L | PTE2_D)
+	and	a0, s1, a1
+	bne	a0, a1, fail /* PTE2_L not set, not good */
+	nop
+
+	EXIT(0)
+fail:
+	/* we should not get there */
+	EXIT(1)
+
+	.globl excep
+excep:
+	.set noreorder
+	PRINT(statusstr)
+	mfc0	a0, COP0_STATUS
+	PRINTX
+
+	PRINT(causestr)
+	mfc0	a0, COP0_CAUSE
+	PRINTX
+
+	PRINT(pcstr)
+	mfc0	a0, COP0_EXPC
+	PRINTX
+
+	PRINT(badvastr)
+	mfc0	a0, COP_0_BADVADDR
+	PRINTX
+
+	PUTCHAR('\n')
+	/* we should get there */
+	EXIT(0)
+
+	.rodata:
+statusstr: .ascii "status \0"
+causestr: .ascii " cause \0"
+pcstr: .ascii " pc \0"
+badvastr: .ascii " badva \0"
+mmustr: .ascii "mmu started \0"
+startstr: .ascii "start\n\0"
+
+	.org EXCEP_ADDRESS - BOOT_ADDRESS
+	.globl evect
+evect:
+	j	excep
+	nop
+
+	.data
+	/* first 2 pages is data that will be switched my mmu switch */
+data_a:
+	.word MAGIC1
+testval:
+	.word MAGIC2
+	.globl pte2_a
+/*
+ * one PD with a level 2 PTP: we invalidate an entry in the PTP and
+ * check that the VA is no longer accessible
+ */
+pte2_a:
+	.align 12
+	.word PTE2_V | PTE2_C | PTE2_X | PTE2_W
+	.word 0x0000 >> 12 /* check real value of data_a */
+	.org pte2_a + 4092
+	.word 0
+	.globl pte2_b
+	.globl pte1_a
+pte1_a:
+	.align 13
+	.word PTE1_V | PTE1_C | PTE1_W | 0x0 /* map PA 0 at VA 0 */
+	.word PTE1_V | PTE1_T | (0x1000 >> 12) /* map PA 0x0 at VA 0x00200000 via pte2_a */
+	.org pte1_a + (BOOT_ADDRESS >> 21) * 4
+	.word PTE1_V | PTE1_C | PTE1_X | (BOOT_ADDRESS >> 21) /* map PA 0xbfc00000 at VA 0xbfc00000 */
+	.org pte1_a + (TTY_BASE >> 21) * 4
+	.word PTE1_V | PTE1_W | (TTY_BASE >> 21) /* map PA 0xd0200000 at VA 0xd0200000 */
+	.org pte1_a + (EXIT_BASE >> 21) * 4
+	.word PTE1_V | PTE1_W | (EXIT_BASE >> 21) /* map PA 0xe0000000 at VA 0xe0000000 */
+	.org pte1_a + 8192
Index: branches/v4/softs/tests_ccvcache_v4/test_pte_llsc/Makefile
===================================================================
--- branches/v4/softs/tests_ccvcache_v4/test_pte_llsc/Makefile	(revision 371)
+++ branches/v4/softs/tests_ccvcache_v4/test_pte_llsc/Makefile	(revision 371)
@@ -0,0 +1,1 @@
+include ../Makefile.inc
Index: branches/v4/softs/tests_ccvcache_v4/test_pte_llsc/mtty0
===================================================================
--- branches/v4/softs/tests_ccvcache_v4/test_pte_llsc/mtty0	(revision 371)
+++ branches/v4/softs/tests_ccvcache_v4/test_pte_llsc/mtty0	(revision 371)
@@ -0,0 +1,1 @@
+[20h0x00000000 0xAC4000FF 0xAC4000FF 0x00000000
Index: branches/v4/softs/tests_ccvcache_v4/test_pte_llsc/run
===================================================================
--- branches/v4/softs/tests_ccvcache_v4/test_pte_llsc/run	(revision 371)
+++ branches/v4/softs/tests_ccvcache_v4/test_pte_llsc/run	(revision 371)
@@ -0,0 +1,28 @@
+#!/bin/sh 
+
+. ../common/common.sh
+
+check_output()
+{
+	egrep "^0x00000000 0xAC4000FF 0xAC4000FF 0x00000000$" run.out > /dev/null
+	if [ $? -eq 0 ]; then
+		return 0;
+	fi
+	echo "couldn't find string in output - mtty not working ?" >> run.out
+	return 1
+}
+
+make --quiet || exit 1
+${SIMUL} > run.out 2>&1 
+if [ $? -eq 0 ]; then
+	if check_output; then
+		echo "test passsed";
+		make --quiet clean
+		exit 0;
+	fi
+	echo "test FAILED"
+	exit 1
+fi
+echo "test FAILED"
+exit 1
+
Index: branches/v4/softs/tests_ccvcache_v4/test_pte_llsc/test.S
===================================================================
--- branches/v4/softs/tests_ccvcache_v4/test_pte_llsc/test.S	(revision 371)
+++ branches/v4/softs/tests_ccvcache_v4/test_pte_llsc/test.S	(revision 371)
@@ -0,0 +1,124 @@
+/*
+ * Check that the MMU doens't clobber the OS bits in PTEs, and interraction
+ * with ll/sc
+ */
+#include <registers.h>
+#include <misc.h>
+#include <vcache.h>
+
+	.text
+	.globl  _start
+_start:
+	.set noreorder
+	la	k0, TTY_BASE
+	la	k1, EXIT_BASE
+
+	/* reset cop0 status (keep BEV) */
+	lui	a0, 0x0040;
+	mtc0	a0, COP0_STATUS
+
+	la	a0, pte1
+	srl	a0, a0, 13
+	mtc2	a0, VC_PTPR
+	nop
+
+	li	a0, VC_TLB_EN_ITLB | VC_TLB_EN_DTLB | VC_TLB_EN_ICACHE | VC_TLB_EN_DCACHE
+	mtc2 	a0, VC_TLB_EN
+
+	/* do a swap of pte2[0] to make the entry valid */
+	la	s0, pte2 + 0x00200000
+1:	la	a1, PTE2_V | PTE2_C | PTE2_W | PTE2_os
+	ll	a0, 0(s0)
+	sc	a1, 0(s0)
+	beqz	a1, 1b
+	nop
+	PRINTX
+	PUTCHAR(' ')
+	/* now write to myvar via pte2[0] */
+	li	a0, MAGIC2
+	la	s1, myvar + 0x00200000
+	sw	a0, 0(s1)
+	/*
+	 * and invalidate pte2[0], again using a swap
+	 * check that we get the same value with lw and ll
+	 */
+	lw	s1, 0(s0)
+2:
+	move	a1, zero
+	ll	a0, 0(s0)
+	sc	a1, 0(s0)
+	beqz	a1, 2b
+	PRINTX
+	PUTCHAR(' ')
+	move	a0, s1
+	PRINTX
+	PUTCHAR(' ')
+	/* finally check what lw tells us now */
+	lw	a0, 0(s0)
+	PRINTX
+	PUTCHAR('\n')
+
+	EXIT(0)
+
+	.globl excep
+excep:
+	.set noreorder
+	PRINT(statusstr)
+	mfc0	a0, COP0_STATUS
+	PRINTX
+
+	PRINT(causestr)
+	mfc0	a0, COP0_CAUSE
+	PRINTX
+
+	PRINT(pcstr)
+	mfc0	a0, COP0_EXPC
+	PRINTX
+
+	PRINT(badvastr)
+	mfc0	a0, COP_0_BADVADDR
+	PRINTX
+
+	PUTCHAR('\n')
+	/* we should not get there */
+	EXIT(1)
+
+	.rodata:
+statusstr: .ascii "status \0"
+causestr: .ascii " cause \0"
+pcstr: .ascii " pc \0"
+badvastr: .ascii " badva \0"
+value:	.word 0x1234abcd
+string: .ascii "hello world \0"
+
+	.org EXCEP_ADDRESS - BOOT_ADDRESS
+	.globl evect
+evect:
+	j	excep
+	nop
+
+	.data
+myvar:	.word MAGIC1
+	.globl pte1
+pte2:
+	.align 12
+	.word 0	/* invalid for now */
+	.word 0x0000 >> 12 /* check real value of myvar */
+	.word PTE2_V | PTE2_C | PTE2_W | PTE2_os /* map pte2 too */
+	.word 0x1000 >> 12 /* check real address of pte2 */
+	.org pte2 + 4092
+	.word 0
+	.globl pte1
+pte1:
+	.align 13
+	.word PTE1_V | PTE1_C | PTE1_W | 0x0 /* map PA 0 at VA 0 */
+	.word PTE1_V | PTE1_T | (0x1000 >> 12) /* map PA 0x0 at VA 0x00200000 via pte2 */
+	.org pte1 + (BOOT_ADDRESS >> 21) * 4
+	.word PTE1_V | PTE1_C | PTE1_X | (BOOT_ADDRESS >> 21) /* map PA 0xbfc00000 at VA 0xbfc00000 */
+	.org pte1 + (TTY_BASE >> 21) * 4
+	.word PTE1_V | PTE1_W | (TTY_BASE >> 21) /* map PA 0xd0200000 at VA 0xd0200000 */
+	.org pte1 + (EXIT_BASE >> 21) * 4
+	.word PTE1_V | PTE1_W | (EXIT_BASE >> 21) /* map PA 0xe0000000 at VA 0xe0000000 */
+	.org pte1 + 8192
+	.word 0
+
Index: branches/v4/softs/tests_ccvcache_v4/test_ri/Makefile
===================================================================
--- branches/v4/softs/tests_ccvcache_v4/test_ri/Makefile	(revision 371)
+++ branches/v4/softs/tests_ccvcache_v4/test_ri/Makefile	(revision 371)
@@ -0,0 +1,1 @@
+include ../Makefile.inc
Index: branches/v4/softs/tests_ccvcache_v4/test_ri/run
===================================================================
--- branches/v4/softs/tests_ccvcache_v4/test_ri/run	(revision 371)
+++ branches/v4/softs/tests_ccvcache_v4/test_ri/run	(revision 371)
@@ -0,0 +1,28 @@
+#!/bin/sh 
+
+. ../common/common.sh
+
+check_output()
+{
+	egrep "^status 0x00400002 cause 0x00000028 pc 0xBFC00034 badva 0x00000000$" run.out > /dev/null
+	if [ $? -ne 0 ]; then
+		echo "couldn't find string 1 in output - mtty not working ?" >> run.out
+		return 1
+	fi
+	return 0;
+}
+
+make --quiet || exit 1
+${SIMUL} > run.out 2>&1 
+if [ $? -eq 0 ]; then
+	if check_output; then
+		echo "test passsed";
+		make --quiet clean
+		exit 0;
+	fi
+	echo "test FAILED"
+	exit 1
+fi
+echo "test FAILED"
+exit 1
+
Index: branches/v4/softs/tests_ccvcache_v4/test_ri/test.S
===================================================================
--- branches/v4/softs/tests_ccvcache_v4/test_ri/test.S	(revision 371)
+++ branches/v4/softs/tests_ccvcache_v4/test_ri/test.S	(revision 371)
@@ -0,0 +1,65 @@
+/*
+ * reserved instruction exception test: check that a reserved instruction
+ * generates an exception.
+ */
+#include <registers.h>
+#include <misc.h>
+
+	.text
+	.globl  _start
+_start:
+	.set noreorder
+	la	k0, TTY_BASE
+	la	k1, EXIT_BASE
+	la	sp, 0x00400000 - 16
+
+	PRINT(startstr)
+
+	/* reset cop0 status (keep BEV) */
+	lui	a0, 0x0040;
+	mtc0	a0, COP0_STATUS
+	nop
+	nop
+	nop
+	.word 0x60000000
+	EXIT(2)
+
+	.globl excep
+excep:
+	.set noreorder
+	PRINT(statusstr)
+	mfc0	a0, COP0_STATUS
+	PRINTX
+
+	PRINT(causestr)
+	mfc0	a0, COP0_CAUSE
+	PRINTX
+
+	PRINT(pcstr)
+	mfc0	a0, COP0_EXPC
+	PRINTX
+
+	PRINT(badvastr)
+	mfc0	a0, COP_0_BADVADDR
+	PRINTX
+	PUTCHAR('\n')
+#we should end there
+	EXIT(0)
+
+	.rodata:
+statusstr: .ascii "status \0"
+causestr: .ascii " cause \0"
+pcstr: .ascii " pc \0"
+badvastr: .ascii " badva \0"
+startstr: .ascii "start\n\0"
+usrstr: .ascii "usrmode\n\0"
+
+	.org EXCEP_ADDRESS - BOOT_ADDRESS
+	.globl evect
+evect:
+	j	excep
+	nop
+	.data
+	.word MAGIC1
+testval:
+	.word MAGIC2
Index: branches/v4/softs/tests_ccvcache_v4/test_ri_delayslot/Makefile
===================================================================
--- branches/v4/softs/tests_ccvcache_v4/test_ri_delayslot/Makefile	(revision 371)
+++ branches/v4/softs/tests_ccvcache_v4/test_ri_delayslot/Makefile	(revision 371)
@@ -0,0 +1,1 @@
+include ../Makefile.inc
Index: branches/v4/softs/tests_ccvcache_v4/test_ri_delayslot/run
===================================================================
--- branches/v4/softs/tests_ccvcache_v4/test_ri_delayslot/run	(revision 371)
+++ branches/v4/softs/tests_ccvcache_v4/test_ri_delayslot/run	(revision 371)
@@ -0,0 +1,28 @@
+#!/bin/sh 
+
+. ../common/common.sh
+
+check_output()
+{
+	egrep "^status 0x00400002 cause 0x80000028 pc 0xBFC00034 badva 0x00000000$" run.out > /dev/null
+	if [ $? -ne 0 ]; then
+		echo "couldn't find string 1 in output - mtty not working ?" >> run.out
+		return 1
+	fi
+	return 0;
+}
+
+make --quiet || exit 1
+${SIMUL} > run.out 2>&1 
+if [ $? -eq 0 ]; then
+	if check_output; then
+		echo "test passsed";
+		make --quiet clean
+		exit 0;
+	fi
+	echo "test FAILED"
+	exit 1
+fi
+echo "test FAILED"
+exit 1
+
Index: branches/v4/softs/tests_ccvcache_v4/test_ri_delayslot/test.S
===================================================================
--- branches/v4/softs/tests_ccvcache_v4/test_ri_delayslot/test.S	(revision 371)
+++ branches/v4/softs/tests_ccvcache_v4/test_ri_delayslot/test.S	(revision 371)
@@ -0,0 +1,86 @@
+/*
+ * reserved instruction exception test: check that a reserved instruction
+ * in a delay slot is properly handled
+ */
+#include <registers.h>
+#include <misc.h>
+
+	.text
+	.globl  _start
+_start:
+	.set noreorder
+	la	k0, TTY_BASE
+	la	k1, EXIT_BASE
+	la	sp, 0x00400000 - 16
+
+	PRINT(startstr)
+
+	/* reset cop0 status (keep BEV) */
+	lui	a0, 0x0040;
+	mtc0	a0, COP0_STATUS
+	nop
+	nop
+	nop
+	j	exit
+	.word 0x60000000
+	nop
+	/* we should not get there, */
+	EXIT(2)
+	.globl exit
+exit:
+	move	a0, v0
+	PRINTX
+	PUTCHAR(' ')
+	move	a0, v1
+	PRINTX
+	PUTCHAR('\n')
+	/* we should get there */
+	EXIT(0)
+
+	.globl excep
+excep:
+	.set noreorder
+	PRINT(statusstr)
+	mfc0	a0, COP0_STATUS
+	PRINTX
+
+	PRINT(causestr)
+	mfc0	a0, COP0_CAUSE
+	PRINTX
+
+	PRINT(pcstr)
+	mfc0	a0, COP0_EXPC
+	PRINTX
+
+	PRINT(badvastr)
+	mfc0	a0, COP_0_BADVADDR
+	PRINTX
+	PUTCHAR('\n')
+	la	a0, exit
+	mtc0	a0, COP0_EXPC
+	li	v0, MAGIC1
+	li	v1, MAGIC2
+	li	a3, 1
+	eret
+	nop
+
+#we should not end there
+	EXIT(1)
+
+	.rodata:
+statusstr: .ascii "status \0"
+causestr: .ascii " cause \0"
+pcstr: .ascii " pc \0"
+badvastr: .ascii " badva \0"
+startstr: .ascii "start\n\0"
+usrstr: .ascii "usrmode\n\0"
+
+	.org EXCEP_ADDRESS - BOOT_ADDRESS
+	.globl evect
+evect:
+	j	excep
+	nop
+	.data
+	.word MAGIC1
+testval:
+	.word MAGIC2
Index: branches/v4/softs/tests_ccvcache_v4/test_sanity/Makefile
===================================================================
--- branches/v4/softs/tests_ccvcache_v4/test_sanity/Makefile	(revision 371)
+++ branches/v4/softs/tests_ccvcache_v4/test_sanity/Makefile	(revision 371)
@@ -0,0 +1,1 @@
+include ../Makefile.inc
Index: branches/v4/softs/tests_ccvcache_v4/test_sanity/run
===================================================================
--- branches/v4/softs/tests_ccvcache_v4/test_sanity/run	(revision 371)
+++ branches/v4/softs/tests_ccvcache_v4/test_sanity/run	(revision 371)
@@ -0,0 +1,28 @@
+#!/bin/sh 
+
+. ../common/common.sh
+
+check_output()
+{
+	egrep "^hello world 0x1234ABCD$" run.out > /dev/null
+	if [ $? -eq 0 ]; then
+		return 0;
+	fi
+	echo "couldn't find string in output - mtty not working ?" >> run.out
+	return 1
+}
+
+make --quiet || exit 1
+${SIMUL} > run.out 2>&1 
+if [ $? -eq 0 ]; then
+	if check_output; then
+		echo "test passsed";
+		make --quiet clean
+		exit 0;
+	fi
+	echo "test FAILED"
+	exit 1
+fi
+echo "test FAILED"
+exit 1
+
Index: branches/v4/softs/tests_ccvcache_v4/test_sanity/test.S
===================================================================
--- branches/v4/softs/tests_ccvcache_v4/test_sanity/test.S	(revision 371)
+++ branches/v4/softs/tests_ccvcache_v4/test_sanity/test.S	(revision 371)
@@ -0,0 +1,42 @@
+/*
+ * Basic sanity checks:
+ *   we can run a program
+ *   we can write to ram
+ *   we can write to the tty
+ *   we can make the simulator exit
+ */
+#include <registers.h>
+#include <misc.h>
+
+	.text
+	.globl  _start
+_start:
+	.set noreorder
+	la	k0, TTY_BASE
+	la	k1, EXIT_BASE
+
+	la	t0, value
+	lw	t0, 0(t0)
+	la	t1, myvar
+	sw	t0, 0(t1)
+
+	la	a0, string
+	jal	print
+	nop
+
+	la	t1, myvar
+	lw	a0, 0(t1)
+	jal	printx
+	nop
+
+	li	a0, '\n'
+	sb	a0, 0(k0)
+
+	EXIT(0)
+
+	.rodata:
+value:	.word 0x1234abcd
+string: .ascii "hello world \0"
+
+	.data
+myvar:	.word 0
Index: branches/v4/softs/tests_ccvcache_v4/test_sc_no_ll/Makefile
===================================================================
--- branches/v4/softs/tests_ccvcache_v4/test_sc_no_ll/Makefile	(revision 371)
+++ branches/v4/softs/tests_ccvcache_v4/test_sc_no_ll/Makefile	(revision 371)
@@ -0,0 +1,1 @@
+include ../Makefile.inc
Index: branches/v4/softs/tests_ccvcache_v4/test_sc_no_ll/run
===================================================================
--- branches/v4/softs/tests_ccvcache_v4/test_sc_no_ll/run	(revision 371)
+++ branches/v4/softs/tests_ccvcache_v4/test_sc_no_ll/run	(revision 371)
@@ -0,0 +1,28 @@
+#!/bin/sh 
+
+. ../common/common.sh
+
+check_output()
+{
+	egrep "^0x0000DEAD 0x00000000$" run.out > /dev/null
+	if [ $? -eq 0 ]; then
+		return 0;
+	fi
+	echo "couldn't find string in output - mtty not working ?" >> run.out
+	return 1
+}
+
+make --quiet || exit 1
+${SIMUL} > run.out 2>&1 
+if [ $? -eq 0 ]; then
+	if check_output; then
+		echo "test passsed";
+		make --quiet clean
+		exit 0;
+	fi
+	echo "test FAILED"
+	exit 1
+fi
+echo "test FAILED"
+exit 1
+
Index: branches/v4/softs/tests_ccvcache_v4/test_sc_no_ll/test.S
===================================================================
--- branches/v4/softs/tests_ccvcache_v4/test_sc_no_ll/test.S	(revision 371)
+++ branches/v4/softs/tests_ccvcache_v4/test_sc_no_ll/test.S	(revision 371)
@@ -0,0 +1,104 @@
+/*
+ * check that a sc without ll does fail
+ */
+#include <registers.h>
+#include <misc.h>
+#include <vcache.h>
+
+	.text
+	.globl  _start
+_start:
+	.set noreorder
+	la	k0, TTY_BASE
+	la	k1, EXIT_BASE
+
+	/* reset cop0 status (keep BEV) */
+	lui	a0, 0x0040;
+	mtc0	a0, COP0_STATUS
+
+	la	a0, pte1
+	srl	a0, a0, 13
+	mtc2	a0, VC_PTPR
+	nop
+
+	li	a0, VC_TLB_EN_ITLB | VC_TLB_EN_DTLB | VC_TLB_EN_ICACHE | VC_TLB_EN_DCACHE
+	mtc2 	a0, VC_TLB_EN
+
+	/* make sure myvar is in cache */
+	la	s1, myvar 
+	lw	a0, 0(s1)
+	PRINTX
+	PUTCHAR(' ')
+
+	/* now write to myvar with sc, without ll first */
+	la	s1, myvar 
+1:
+	li	a1, MAGIC2
+	sc	a1, 0(s1)
+	beqz	a1, 2f
+	nop
+	
+	move a0, a1
+	PRINTX
+	/* we should not get there */
+	EXIT(1)
+
+2:
+	/* we jump here when the sc failed */
+	move a0, a1
+	PRINTX
+	PUTCHAR('\n');
+	EXIT(0)
+
+	.globl excep
+excep:
+	.set noreorder
+	PRINT(statusstr)
+	mfc0	a0, COP0_STATUS
+	PRINTX
+
+	PRINT(causestr)
+	mfc0	a0, COP0_CAUSE
+	PRINTX
+
+	PRINT(pcstr)
+	mfc0	a0, COP0_EXPC
+	PRINTX
+
+	PRINT(badvastr)
+	mfc0	a0, COP_0_BADVADDR
+	PRINTX
+
+	PUTCHAR('\n')
+	/* we should not get there */
+	EXIT(1)
+
+	.rodata:
+statusstr: .ascii "status \0"
+causestr: .ascii " cause \0"
+pcstr: .ascii " pc \0"
+badvastr: .ascii " badva \0"
+value:	.word 0x1234abcd
+string: .ascii "hello world \0"
+
+	.org EXCEP_ADDRESS - BOOT_ADDRESS
+	.globl evect
+evect:
+	j	excep
+	nop
+
+	.data
+myvar:	.word MAGIC1
+	.globl pte1
+pte1:
+	.align 13
+	.word PTE1_V | PTE1_W | 0x0 /* map PA 0 at VA 0 */
+	.org pte1 + (BOOT_ADDRESS >> 21) * 4
+	.word PTE1_V | PTE1_C | PTE1_X | (BOOT_ADDRESS >> 21) /* map PA 0xbfc00000 at VA 0xbfc00000 */
+	.org pte1 + (TTY_BASE >> 21) * 4
+	.word PTE1_V | PTE1_W | (TTY_BASE >> 21) /* map PA 0xd0200000 at VA 0xd0200000 */
+	.org pte1 + (EXIT_BASE >> 21) * 4
+	.word PTE1_V | PTE1_W | (EXIT_BASE >> 21) /* map PA 0xe0000000 at VA 0xe0000000 */
+	.org pte1 + 8192
+	.word 0
+
Index: branches/v4/softs/tests_ccvcache_v4/test_sc_update_cache/Makefile
===================================================================
--- branches/v4/softs/tests_ccvcache_v4/test_sc_update_cache/Makefile	(revision 371)
+++ branches/v4/softs/tests_ccvcache_v4/test_sc_update_cache/Makefile	(revision 371)
@@ -0,0 +1,1 @@
+include ../Makefile.inc
Index: branches/v4/softs/tests_ccvcache_v4/test_sc_update_cache/run
===================================================================
--- branches/v4/softs/tests_ccvcache_v4/test_sc_update_cache/run	(revision 371)
+++ branches/v4/softs/tests_ccvcache_v4/test_sc_update_cache/run	(revision 371)
@@ -0,0 +1,28 @@
+#!/bin/sh 
+
+. ../common/common.sh
+
+check_output()
+{
+	egrep "^0x0000DEAD 0x0000BEEF$" run.out > /dev/null
+	if [ $? -eq 0 ]; then
+		return 0;
+	fi
+	echo "couldn't find string in output - mtty not working ?" >> run.out
+	return 1
+}
+
+make --quiet || exit 1
+${SIMUL} > run.out 2>&1 
+if [ $? -eq 0 ]; then
+	if check_output; then
+		echo "test passsed";
+		make --quiet clean
+		exit 0;
+	fi
+	echo "test FAILED"
+	exit 1
+fi
+echo "test FAILED"
+exit 1
+
Index: branches/v4/softs/tests_ccvcache_v4/test_sc_update_cache/test.S
===================================================================
--- branches/v4/softs/tests_ccvcache_v4/test_sc_update_cache/test.S	(revision 371)
+++ branches/v4/softs/tests_ccvcache_v4/test_sc_update_cache/test.S	(revision 371)
@@ -0,0 +1,80 @@
+/*
+ * Check that lc also updates the local L1 cache.
+ */
+#include <registers.h>
+#include <misc.h>
+#include <vcache.h>
+	.text
+	.globl  _start
+_start:
+	.set noreorder
+	la	k0, TTY_BASE
+	la	k1, EXIT_BASE
+
+	/* reset cop0 status (keep BEV) */
+	lui	a0, 0x0040;
+	mtc0	a0, COP0_STATUS
+
+	/* enable caches */
+	li	a0, VC_TLB_EN_ICACHE | VC_TLB_EN_DCACHE
+	mtc2 	a0, VC_TLB_EN
+
+	/* fetch data in cache */
+	la	s0, myvar
+	lw	a0, 0(s0)
+	/* write magic value */
+	li	a0, MAGIC1
+	sw	a0, 0(s0)
+	/* ll/sc another value on the same address */
+2:
+	ll	a0, 0(s0)
+	PRINTX
+	PUTCHAR(' ')
+	li	a0, MAGIC2
+	sc	a0, 0(s0)
+	beqz	a0, 2b
+	/* now check that we got the right value in cache */
+	lw	a0, 0(s0)
+	PRINTX
+	PUTCHAR('\n')
+	EXIT(0)
+
+	.globl excep
+excep:
+	.set noreorder
+	PRINT(statusstr)
+	mfc0	a0, COP0_STATUS
+	PRINTX
+
+	PRINT(causestr)
+	mfc0	a0, COP0_CAUSE
+	PRINTX
+
+	PRINT(pcstr)
+	mfc0	a0, COP0_EXPC
+	PRINTX
+
+	PRINT(badvastr)
+	mfc0	a0, COP_0_BADVADDR
+	PRINTX
+
+	PUTCHAR('\n')
+	/* we should not get there */
+	EXIT(1)
+
+	.rodata:
+statusstr: .ascii "status \0"
+causestr: .ascii " cause \0"
+pcstr: .ascii " pc \0"
+badvastr: .ascii " badva \0"
+value:	.word 0x1234abcd
+string: .ascii "hello world \0"
+
+	.org EXCEP_ADDRESS - BOOT_ADDRESS
+	.globl evect
+evect:
+	j	excep
+	nop
+
+	.data
+myvar:	.word 0
Index: branches/v4/softs/tests_ccvcache_v4/test_sync/Makefile
===================================================================
--- branches/v4/softs/tests_ccvcache_v4/test_sync/Makefile	(revision 371)
+++ branches/v4/softs/tests_ccvcache_v4/test_sync/Makefile	(revision 371)
@@ -0,0 +1,1 @@
+include ../Makefile.inc
Index: branches/v4/softs/tests_ccvcache_v4/test_sync/mtty0
===================================================================
--- branches/v4/softs/tests_ccvcache_v4/test_sync/mtty0	(revision 371)
+++ branches/v4/softs/tests_ccvcache_v4/test_sync/mtty0	(revision 371)
@@ -0,0 +1,3 @@
+[20hstart
+mmustated
+@@@@@@
Index: branches/v4/softs/tests_ccvcache_v4/test_sync/run
===================================================================
--- branches/v4/softs/tests_ccvcache_v4/test_sync/run	(revision 371)
+++ branches/v4/softs/tests_ccvcache_v4/test_sync/run	(revision 371)
@@ -0,0 +1,28 @@
+#!/bin/sh 
+
+. ../common/common.sh 
+
+check_output()
+{
+	egrep "^@@@@@@$" run.out > /dev/null
+	if [ $? -ne 0 ]; then
+		echo "couldn't find string in output - mtty not working ?" >> run.out
+		return 1
+	fi
+	return 0;
+}
+
+make --quiet || exit 1
+${SIMUL} > run.out 2>&1 
+if [ $? -eq 0 ]; then
+	if check_output; then
+		echo "test passsed";
+		make --quiet clean
+		exit 0;
+	fi
+	echo "test FAILED"
+	exit 1
+fi
+echo "test FAILED"
+exit 1
+
Index: branches/v4/softs/tests_ccvcache_v4/test_sync/test.S
===================================================================
--- branches/v4/softs/tests_ccvcache_v4/test_sync/test.S	(revision 371)
+++ branches/v4/softs/tests_ccvcache_v4/test_sync/test.S	(revision 371)
@@ -0,0 +1,101 @@
+/*
+ * sync test: we map the tty cached. If sync doesn't work some chars will be
+ * lost because writes are combined in the write buffer.
+ */
+#include <registers.h>
+#include <misc.h>
+#include <vcache.h>
+
+	.text
+	.globl  _start
+_start:
+	.set noreorder
+	la	k0, TTY_BASE
+	la	k1, EXIT_BASE
+
+	PRINT_SYNC(startstr)
+
+	/* reset cop0 status (keep BEV) */
+	lui	a0, 0x0040;
+	mtc0	a0, COP0_STATUS
+
+	la	a0, pte1
+	srl	a0, a0, 13
+	mtc2	a0, VC_PTPR
+	nop
+
+	li	a0, VC_TLB_EN_ITLB | VC_TLB_EN_DTLB | VC_TLB_EN_ICACHE | VC_TLB_EN_DCACHE
+	mtc2 	a0, VC_TLB_EN
+
+	PRINT_SYNC(mmustr)
+
+	/*
+	 * print several chars quickly: without sync not all of them will
+	 * show up
+	 */
+#define WRITE_TTY sb a0, 0(k0); sync
+	la a0, '@'
+	WRITE_TTY
+	WRITE_TTY
+	WRITE_TTY
+	WRITE_TTY
+	WRITE_TTY
+	WRITE_TTY
+	PUTCHAR('\n')
+
+	/* we should get there */
+	EXIT(0)
+
+	.globl excep
+excep:
+	.set noreorder
+	PRINT(statusstr)
+	mfc0	a0, COP0_STATUS
+	PRINTX
+
+	PRINT(causestr)
+	mfc0	a0, COP0_CAUSE
+	PRINTX
+
+	PRINT(pcstr)
+	mfc0	a0, COP0_EXPC
+	PRINTX
+
+	PRINT(badvastr)
+	mfc0	a0, COP_0_BADVADDR
+	PRINTX
+
+	PUTCHAR('\n')
+	/* we should not get there */
+	EXIT(1)
+
+	.rodata:
+statusstr: .ascii "status \0"
+causestr: .ascii " cause \0"
+pcstr: .ascii " pc \0"
+badvastr: .ascii " badva \0"
+mmustr:	.ascii "mmu started\n\0"
+startstr: .ascii "start\n\0"
+
+	.org EXCEP_ADDRESS - BOOT_ADDRESS
+	.globl evect
+evect:
+	j	excep
+	nop
+	.data
+	.word MAGIC1
+testval:
+	.word MAGIC2
+	.globl pte1
+pte1:
+	.align 13
+	.word PTE1_V | PTE1_C | PTE1_W | 0x0 /* map PA 0 at VA 0 */
+	.org pte1 + (BOOT_ADDRESS >> 21) * 4
+	.word PTE1_V | PTE1_C | PTE1_X | (BOOT_ADDRESS >> 21) /* map PA 0xbfc00000 at VA 0xbfc00000 */
+	.org pte1 + (TTY_BASE >> 21) * 4
+	.word PTE1_V | PTE1_C | PTE1_W | (TTY_BASE >> 21) /* map PA 0xd0200000 at VA 0xd0200000 *cached!* */
+	.org pte1 + (EXIT_BASE >> 21) * 4
+	.word PTE1_V | PTE1_W | (EXIT_BASE >> 21) /* map PA 0xe0000000 at VA 0xe0000000 */
+	.org pte1 + 8192
+	.word 0
+
Index: branches/v4/softs/tests_ccvcache_v4/test_syscall/Makefile
===================================================================
--- branches/v4/softs/tests_ccvcache_v4/test_syscall/Makefile	(revision 371)
+++ branches/v4/softs/tests_ccvcache_v4/test_syscall/Makefile	(revision 371)
@@ -0,0 +1,1 @@
+include ../Makefile.inc
Index: branches/v4/softs/tests_ccvcache_v4/test_syscall/run
===================================================================
--- branches/v4/softs/tests_ccvcache_v4/test_syscall/run	(revision 371)
+++ branches/v4/softs/tests_ccvcache_v4/test_syscall/run	(revision 371)
@@ -0,0 +1,33 @@
+#!/bin/sh 
+
+. ../common/common.sh
+
+check_output()
+{
+	egrep "^status 0x00400012 cause 0x00000020 pc 0xBFC00050 badva 0x00000000$" run.out > /dev/null
+	if [ $? -ne 0 ]; then
+		echo "couldn't find string 1 in output - mtty not working ?" >> run.out
+		return 1
+	fi
+	egrep "^0x0000DEAD 0x0000BEEF$" run.out > /dev/null
+	if [ $? -ne 0 ]; then
+		echo "couldn't find string 2 in output - mtty not working ?" >> run.out
+		return 1
+	fi
+	return 0;
+}
+
+make --quiet || exit 1
+${SIMUL} > run.out 2>&1 
+if [ $? -eq 0 ]; then
+	if check_output; then
+		echo "test passsed";
+		make --quiet clean
+		exit 0;
+	fi
+	echo "test FAILED"
+	exit 1
+fi
+echo "test FAILED"
+exit 1
+
Index: branches/v4/softs/tests_ccvcache_v4/test_syscall/test.S
===================================================================
--- branches/v4/softs/tests_ccvcache_v4/test_syscall/test.S	(revision 371)
+++ branches/v4/softs/tests_ccvcache_v4/test_syscall/test.S	(revision 371)
@@ -0,0 +1,91 @@
+/*
+ * syscall test: check that a syscall generates an exception, and we can
+ * return 
+ */
+#include <registers.h>
+#include <misc.h>
+
+	.text
+	.globl  _start
+_start:
+	.set noreorder
+	la	k0, TTY_BASE
+	la	k1, EXIT_BASE
+	la	sp, 0x00400000 - 16
+
+	PRINT(startstr)
+
+	/* reset cop0 status (keep BEV) */
+	lui	a0, 0x0040;
+	mtc0	a0, COP0_STATUS
+	/* switch to user mode */
+	mfc0	a0, COP0_STATUS
+	ori	a0, 0x10
+	mtc0	a0, COP0_STATUS
+	nop
+	nop
+	nop
+	PRINT(usrstr)
+	syscall
+	bne a3, zero, exit
+	nop
+	/* we should not get there, a3 is not 0 */
+	EXIT(2)
+exit:
+	move	a0, v0
+	PRINTX
+	PUTCHAR(' ')
+	move	a0, v1
+	PRINTX
+	PUTCHAR('\n')
+	/* we should get there */
+	EXIT(0)
+
+	.globl excep
+excep:
+	.set noreorder
+	PRINT(statusstr)
+	mfc0	a0, COP0_STATUS
+	PRINTX
+
+	PRINT(causestr)
+	mfc0	a0, COP0_CAUSE
+	PRINTX
+
+	PRINT(pcstr)
+	mfc0	a0, COP0_EXPC
+	PRINTX
+
+	PRINT(badvastr)
+	mfc0	a0, COP_0_BADVADDR
+	PRINTX
+	PUTCHAR('\n')
+	mfc0	a0, COP0_EXPC
+	addiu	a0, a0, 4
+	mtc0	a0, COP0_EXPC
+	li	v0, MAGIC1
+	li	v1, MAGIC2
+	li	a3, 1
+	eret
+	nop
+
+#we should not end there
+	EXIT(1)
+
+	.rodata:
+statusstr: .ascii "status \0"
+causestr: .ascii " cause \0"
+pcstr: .ascii " pc \0"
+badvastr: .ascii " badva \0"
+startstr: .ascii "start\n\0"
+usrstr: .ascii "usrmode\n\0"
+
+	.org EXCEP_ADDRESS - BOOT_ADDRESS
+	.globl evect
+evect:
+	j	excep
+	nop
+	.data
+	.word MAGIC1
+testval:
+	.word MAGIC2
Index: branches/v4/softs/tests_ccvcache_v4/test_syscall_delayslot/Makefile
===================================================================
--- branches/v4/softs/tests_ccvcache_v4/test_syscall_delayslot/Makefile	(revision 371)
+++ branches/v4/softs/tests_ccvcache_v4/test_syscall_delayslot/Makefile	(revision 371)
@@ -0,0 +1,1 @@
+include ../Makefile.inc
Index: branches/v4/softs/tests_ccvcache_v4/test_syscall_delayslot/run
===================================================================
--- branches/v4/softs/tests_ccvcache_v4/test_syscall_delayslot/run	(revision 371)
+++ branches/v4/softs/tests_ccvcache_v4/test_syscall_delayslot/run	(revision 371)
@@ -0,0 +1,33 @@
+#!/bin/sh 
+
+. ../common/common.sh
+
+check_output()
+{
+	egrep "^status 0x00400012 cause 0x80000020 pc 0xBFC00050 badva 0x00000000$" run.out > /dev/null
+	if [ $? -ne 0 ]; then
+		echo "couldn't find string 1 in output - mtty not working ?" >> run.out
+		return 1
+	fi
+	egrep "^usrmode$" run.out > /dev/null
+	if [ $? -ne 0 ]; then
+		echo "couldn't find string 2 in output - mtty not working ?" >> run.out
+		return 1
+	fi
+	return 0;
+}
+
+make --quiet || exit 1
+${SIMUL} > run.out 2>&1 
+if [ $? -eq 0 ]; then
+	if check_output; then
+		echo "test passsed";
+		make --quiet clean
+		exit 0;
+	fi
+	echo "test FAILED"
+	exit 1
+fi
+echo "test FAILED"
+exit 1
+
Index: branches/v4/softs/tests_ccvcache_v4/test_syscall_delayslot/test.S
===================================================================
--- branches/v4/softs/tests_ccvcache_v4/test_syscall_delayslot/test.S	(revision 371)
+++ branches/v4/softs/tests_ccvcache_v4/test_syscall_delayslot/test.S	(revision 371)
@@ -0,0 +1,90 @@
+/*
+ * syscall test: check that a syscall in a delay slot is properly handled
+ */
+#include <registers.h>
+#include <misc.h>
+
+	.text
+	.globl  _start
+_start:
+	.set noreorder
+	la	k0, TTY_BASE
+	la	k1, EXIT_BASE
+	la	sp, 0x00400000 - 16
+
+	PRINT(startstr)
+
+	/* reset cop0 status (keep BEV) */
+	lui	a0, 0x0040;
+	mtc0	a0, COP0_STATUS
+	/* switch to user mode */
+	mfc0	a0, COP0_STATUS
+	ori	a0, 0x10
+	mtc0	a0, COP0_STATUS
+	nop
+	nop
+	nop
+	PRINT(usrstr)
+	j	exit
+	syscall
+	nop
+	/* we should not get there, */
+	EXIT(2)
+	.globl exit
+exit:
+	move	a0, v0
+	PRINTX
+	PUTCHAR(' ')
+	move	a0, v1
+	PRINTX
+	PUTCHAR('\n')
+	/* we should get there */
+	EXIT(0)
+
+	.globl excep
+excep:
+	.set noreorder
+	PRINT(statusstr)
+	mfc0	a0, COP0_STATUS
+	PRINTX
+
+	PRINT(causestr)
+	mfc0	a0, COP0_CAUSE
+	PRINTX
+
+	PRINT(pcstr)
+	mfc0	a0, COP0_EXPC
+	PRINTX
+
+	PRINT(badvastr)
+	mfc0	a0, COP_0_BADVADDR
+	PRINTX
+	PUTCHAR('\n')
+	la	a0, exit
+	mtc0	a0, COP0_EXPC
+	li	v0, MAGIC1
+	li	v1, MAGIC2
+	li	a3, 1
+	eret
+	nop
+
+#we should not end there
+	EXIT(1)
+
+	.rodata:
+statusstr: .ascii "status \0"
+causestr: .ascii " cause \0"
+pcstr: .ascii " pc \0"
+badvastr: .ascii " badva \0"
+startstr: .ascii "start\n\0"
+usrstr: .ascii "usrmode\n\0"
+
+	.org EXCEP_ADDRESS - BOOT_ADDRESS
+	.globl evect
+evect:
+	j	excep
+	nop
+	.data
+	.word MAGIC1
+testval:
+	.word MAGIC2
Index: branches/v4/softs/tests_ccvcache_v4/test_trap/Makefile
===================================================================
--- branches/v4/softs/tests_ccvcache_v4/test_trap/Makefile	(revision 371)
+++ branches/v4/softs/tests_ccvcache_v4/test_trap/Makefile	(revision 371)
@@ -0,0 +1,1 @@
+include ../Makefile.inc
Index: branches/v4/softs/tests_ccvcache_v4/test_trap/run
===================================================================
--- branches/v4/softs/tests_ccvcache_v4/test_trap/run	(revision 371)
+++ branches/v4/softs/tests_ccvcache_v4/test_trap/run	(revision 371)
@@ -0,0 +1,28 @@
+#!/bin/sh 
+
+. ../common/common.sh
+
+check_output()
+{
+	egrep "^status 0x00400002 cause 0x00000034 pc 0xBFC00034 badva 0x00000000$" run.out > /dev/null
+	if [ $? -ne 0 ]; then
+		echo "couldn't find string 1 in output - mtty not working ?" >> run.out
+		return 1
+	fi
+	return 0;
+}
+
+make --quiet || exit 1
+${SIMUL} > run.out 2>&1 
+if [ $? -eq 0 ]; then
+	if check_output; then
+		echo "test passsed";
+		make --quiet clean
+		exit 0;
+	fi
+	echo "test FAILED"
+	exit 1
+fi
+echo "test FAILED"
+exit 1
+
Index: branches/v4/softs/tests_ccvcache_v4/test_trap/test.S
===================================================================
--- branches/v4/softs/tests_ccvcache_v4/test_trap/test.S	(revision 371)
+++ branches/v4/softs/tests_ccvcache_v4/test_trap/test.S	(revision 371)
@@ -0,0 +1,64 @@
+/*
+ * trap test: check that a we can generate a trap
+ */
+#include <registers.h>
+#include <misc.h>
+
+	.text
+	.globl  _start
+_start:
+	.set noreorder
+	la	k0, TTY_BASE
+	la	k1, EXIT_BASE
+	la	sp, 0x00400000 - 16
+
+	PRINT(startstr)
+
+	/* reset cop0 status (keep BEV) */
+	lui	a0, 0x0040;
+	mtc0	a0, COP0_STATUS
+	nop
+	nop
+	nop
+	teq	zero, zero
+	EXIT(2)
+
+	.globl excep
+excep:
+	.set noreorder
+	PRINT(statusstr)
+	mfc0	a0, COP0_STATUS
+	PRINTX
+
+	PRINT(causestr)
+	mfc0	a0, COP0_CAUSE
+	PRINTX
+
+	PRINT(pcstr)
+	mfc0	a0, COP0_EXPC
+	PRINTX
+
+	PRINT(badvastr)
+	mfc0	a0, COP_0_BADVADDR
+	PRINTX
+	PUTCHAR('\n')
+#we should end there
+	EXIT(0)
+
+	.rodata:
+statusstr: .ascii "status \0"
+causestr: .ascii " cause \0"
+pcstr: .ascii " pc \0"
+badvastr: .ascii " badva \0"
+startstr: .ascii "start\n\0"
+usrstr: .ascii "usrmode\n\0"
+
+	.org EXCEP_ADDRESS - BOOT_ADDRESS
+	.globl evect
+evect:
+	j	excep
+	nop
+	.data
+	.word MAGIC1
+testval:
+	.word MAGIC2
Index: branches/v4/softs/tests_ccvcache_v4/test_trap_delayslot/Makefile
===================================================================
--- branches/v4/softs/tests_ccvcache_v4/test_trap_delayslot/Makefile	(revision 371)
+++ branches/v4/softs/tests_ccvcache_v4/test_trap_delayslot/Makefile	(revision 371)
@@ -0,0 +1,1 @@
+include ../Makefile.inc
Index: branches/v4/softs/tests_ccvcache_v4/test_trap_delayslot/run
===================================================================
--- branches/v4/softs/tests_ccvcache_v4/test_trap_delayslot/run	(revision 371)
+++ branches/v4/softs/tests_ccvcache_v4/test_trap_delayslot/run	(revision 371)
@@ -0,0 +1,28 @@
+#!/bin/sh 
+
+. ../common/common.sh
+
+check_output()
+{
+	egrep "^status 0x00400002 cause 0x80000034 pc 0xBFC00034 badva 0x00000000$" run.out > /dev/null
+	if [ $? -ne 0 ]; then
+		echo "couldn't find string 1 in output - mtty not working ?" >> run.out
+		return 1
+	fi
+	return 0;
+}
+
+make --quiet || exit 1
+${SIMUL} > run.out 2>&1 
+if [ $? -eq 0 ]; then
+	if check_output; then
+		echo "test passsed";
+		make --quiet clean
+		exit 0;
+	fi
+	echo "test FAILED"
+	exit 1
+fi
+echo "test FAILED"
+exit 1
+
Index: branches/v4/softs/tests_ccvcache_v4/test_trap_delayslot/test.S
===================================================================
--- branches/v4/softs/tests_ccvcache_v4/test_trap_delayslot/test.S	(revision 371)
+++ branches/v4/softs/tests_ccvcache_v4/test_trap_delayslot/test.S	(revision 371)
@@ -0,0 +1,85 @@
+/*
+ * trap test: check that a trap in a delay slot is
+ * properly handled
+ */
+#include <registers.h>
+#include <misc.h>
+
+	.text
+	.globl  _start
+_start:
+	.set noreorder
+	la	k0, TTY_BASE
+	la	k1, EXIT_BASE
+	la	sp, 0x00400000 - 16
+
+	PRINT(startstr)
+
+	/* reset cop0 status (keep BEV) */
+	lui	a0, 0x0040;
+	mtc0	a0, COP0_STATUS
+	nop
+	nop
+	nop
+	j exit
+	teq	zero, zero
+	/* we should not get there, */
+	EXIT(2)
+	.globl exit
+exit:
+	move	a0, v0
+	PRINTX
+	PUTCHAR(' ')
+	move	a0, v1
+	PRINTX
+	PUTCHAR('\n')
+	/* we should get there */
+	EXIT(0)
+
+	.globl excep
+excep:
+	.set noreorder
+	PRINT(statusstr)
+	mfc0	a0, COP0_STATUS
+	PRINTX
+
+	PRINT(causestr)
+	mfc0	a0, COP0_CAUSE
+	PRINTX
+
+	PRINT(pcstr)
+	mfc0	a0, COP0_EXPC
+	PRINTX
+
+	PRINT(badvastr)
+	mfc0	a0, COP_0_BADVADDR
+	PRINTX
+	PUTCHAR('\n')
+	la	a0, exit
+	mtc0	a0, COP0_EXPC
+	li	v0, MAGIC1
+	li	v1, MAGIC2
+	li	a3, 1
+	eret
+	nop
+
+#we should not end there
+	EXIT(1)
+
+	.rodata:
+statusstr: .ascii "status \0"
+causestr: .ascii " cause \0"
+pcstr: .ascii " pc \0"
+badvastr: .ascii " badva \0"
+startstr: .ascii "start\n\0"
+usrstr: .ascii "usrmode\n\0"
+
+	.org EXCEP_ADDRESS - BOOT_ADDRESS
+	.globl evect
+evect:
+	j	excep
+	nop
+	.data
+	.word MAGIC1
+testval:
+	.word MAGIC2
Index: branches/v4/softs/tests_ccvcache_v4/test_xicu_timer/Makefile
===================================================================
--- branches/v4/softs/tests_ccvcache_v4/test_xicu_timer/Makefile	(revision 371)
+++ branches/v4/softs/tests_ccvcache_v4/test_xicu_timer/Makefile	(revision 371)
@@ -0,0 +1,1 @@
+include ../Makefile.inc
Index: branches/v4/softs/tests_ccvcache_v4/test_xicu_timer/run
===================================================================
--- branches/v4/softs/tests_ccvcache_v4/test_xicu_timer/run	(revision 371)
+++ branches/v4/softs/tests_ccvcache_v4/test_xicu_timer/run	(revision 371)
@@ -0,0 +1,28 @@
+#!/bin/sh 
+
+. ../common/common.sh
+
+check_output()
+{
+	egrep "^status 0x00400403 cause 0x[08]0000400 pc 0xBFC00040 badva 0x00000000 xicu 0x[01][0-9A-F][01][0-9A-F]0001$" run.out > /dev/null
+	if [ $? -ne 0 ]; then
+		echo "couldn't find string in output - mtty not working ?" >> run.out
+		return 1
+	fi
+	return 0;
+}
+
+make --quiet || exit 1
+${SIMUL} > run.out 2>&1 
+if [ $? -eq 0 ]; then
+	if check_output; then
+		echo "test passsed";
+		make --quiet clean
+		exit 0;
+	fi
+	echo "test FAILED"
+	exit 1
+fi
+echo "test FAILED"
+exit 1
+
Index: branches/v4/softs/tests_ccvcache_v4/test_xicu_timer/test.S
===================================================================
--- branches/v4/softs/tests_ccvcache_v4/test_xicu_timer/test.S	(revision 371)
+++ branches/v4/softs/tests_ccvcache_v4/test_xicu_timer/test.S	(revision 371)
@@ -0,0 +1,89 @@
+/*
+ * Check that we can take an interrupt from the xicu timer0
+ */
+#include <registers.h>
+#include <misc.h>
+#include <xicu.h>
+
+	.text
+	.globl  _start
+_start:
+	.set noreorder
+	la	k0, TTY_BASE
+	la	k1, EXIT_BASE
+
+	/* reset cop0 status (keep BEV), enable interrupt 0 */
+	lui     a0, 0x0040;
+	addiu	a0, 0x0401;
+	mtc0    a0, COP0_STATUS
+
+	/* reset cause, make sure IV is off */
+	mtc0	zero, COP0_CAUSE
+
+	PRINT(startstr)
+
+	/* program xicu */
+	la	t0, XICU_BASE
+	/* clear pending interrupt */
+	lw	a0, XICU_PTI_ACK(0)(t0)
+	/* route PTI0 to irq 0 */
+	li	a0, 1 << 0
+	sw	a0, XICU_MSK_PTI_E(0)(t0)
+	/* interrupt in 10 cycles */
+	li	a0, 10
+	sw	a0, XICU_PTI_PER(0)(t0)
+
+1:	j 1b
+	nop
+	/* we should not end there */
+	EXIT(1)
+
+	.globl excep
+excep:
+	.set noreorder
+	PRINT(statusstr)
+	mfc0	a0, COP0_STATUS
+	PRINTX
+
+	PRINT(causestr)
+	mfc0	a0, COP0_CAUSE
+	PRINTX
+
+	PRINT(pcstr)
+	mfc0	a0, COP0_EXPC
+	PRINTX
+
+	PRINT(badvastr)
+	mfc0	a0, COP_0_BADVADDR
+	PRINTX
+
+	PRINT(xicustr)
+	la	t0, XICU_BASE
+	lw	a0, XICU_PRIO(0)(t0)
+	PRINTX
+
+	PUTCHAR('\n')
+	/* clear interrupt */
+	mfc0	a0, COP0_CAUSE
+	andi	t0, a0, 0xff00
+	xor	a0, a0, t0
+	mtc0	a0, COP0_CAUSE
+	/* we should end there */
+	EXIT(0)
+
+	.rodata:
+statusstr: .ascii "status \0"
+causestr: .ascii " cause \0"
+pcstr: .ascii " pc \0"
+badvastr: .ascii " badva \0"
+xicustr: .ascii " xicu \0"
+startstr: .ascii "start\n\0"
+eretstr: .ascii "eret\n\0"
+
+	.org EXCEP_ADDRESS - BOOT_ADDRESS
+	.globl evect
+evect:
+	j	excep
+	nop
+	.data
+myvar:	.word 0
Index: branches/v4/softs/tests_ccvcache_v4/tmp
===================================================================
--- branches/v4/softs/tests_ccvcache_v4/tmp	(revision 371)
+++ branches/v4/softs/tests_ccvcache_v4/tmp	(revision 371)
@@ -0,0 +1,72 @@
+-n test_sanity: 
+-n test_exceptions: 
+-n test_mmu_basic: 
+test FAILED
+-n test_excep_ls: 
+test FAILED
+-n test_excep_ls_delayslot: 
+-n test_excep_ls_llsc: 
+test FAILED
+-n test_excep_if: 
+test FAILED
+-n test_excep_if_delayslot: 
+test FAILED
+-n test_excep_if_llsc: 
+test FAILED
+-n test_exception_epc_modify: 
+-n test_dtlb_inval: 
+-n test_dtlb_inval2: 
+test FAILED
+-n test_dtlb_inval3: 
+test FAILED
+-n test_itlb_inval: 
+-n test_itlb_inval2: 
+test FAILED
+-n test_idtlb_inval: 
+test FAILED
+-n test_idtlb_inval2: 
+test FAILED
+-n test_idtlb_inval3: 
+test FAILED
+-n test_idtlb_inval4: 
+test FAILED
+-n test_dtlb_ptprinval: 
+-n test_itlb_ptprinval: 
+-n test_idtlb_ptprinval: 
+test FAILED
+-n test_sync: 
+-n test_sc_update_cache: 
+-n test_pte_llsc: 
+test FAILED
+-n test_interrupt: 
+-n test_interrupt_epc_modify: 
+-n test_xicu_timer: 
+-n test_interrupt_delayslot: 
+test FAILED
+-n test_interrupt_mask: 
+-n test_interrupt_external_mask: 
+-n test_excep_cop: 
+-n test_excep_cop_delayslot: 
+-n test_excep_cop1: 
+-n test_syscall: 
+-n test_syscall_delayslot: 
+-n test_breakpoint: 
+-n test_breakpoint_delayslot: 
+-n test_ri: 
+-n test_ri_delayslot: 
+-n test_ao: 
+-n test_ao_delayslot: 
+-n test_trap: 
+-n test_trap_delayslot: 
+-n test_fpe: 
+-n test_fpe_delayslot: 
+test FAILED
+-n test_dcache_inval_pa: 
+test FAILED
+-n test_icache_inval_pa: 
+test FAILED
+-n test_pte2i_ref: 
+-n test_pte2lw_ref: 
+-n test_pte2ll_ref: 
+-n test_pte2sw_dirty: 
+-n test_pte2sc_dirty: 
Index: branches/v4/softs/tsar_boot/Makefile
===================================================================
--- branches/v4/softs/tsar_boot/Makefile	(revision 371)
+++ branches/v4/softs/tsar_boot/Makefile	(revision 371)
@@ -0,0 +1,105 @@
+ifndef PLATFORM_DIR
+$(error please define PLATFORM_DIR 'make PLATFORM_DIR=foo')
+else
+
+LD	       := mipsel-unknown-elf-ld
+CC	       := mipsel-unknown-elf-gcc
+AS	       := mipsel-unknown-elf-as
+DU	       := mipsel-unknown-elf-objdump
+RM	       := rm -rf
+ECHO	   := echo
+MKDIR	   := mkdir
+DTC	       := dtc
+HEXDUMP	   := hexdump
+
+BUILD_DIR  := build
+SRCS_DIR   := src
+INCS_DIR   := include
+
+# =============================================================================
+# Include files paths
+# =============================================================================
+
+INCLUDE	   += -I. -I$(INCS_DIR) -I$(PLATFORM_DIR)
+
+# =============================================================================
+# Paths of sources in another directories
+# =============================================================================
+
+VPATH      += $(SRCS_DIR)
+VPATH      += $(PLATFORM_DIR)
+
+# =============================================================================
+# Object files
+# =============================================================================
+
+CFLAGS     := -Wall -mno-gpopt -ffreestanding -fomit-frame-pointer -mips32 \
+		      -ggdb -mlong-calls
+
+C_SRCS	   := boot_elf_loader.c boot_ioc.c boot_memcpy.c boot_tty.c exceptions.c
+ifndef SOCLIB
+C_SRCS	   += sdcard.c spi.c
+endif
+
+S_SRCS	   := reset.S
+
+OBJS       := $(subst .c,.o, $(notdir $(C_SRCS)))
+OBJS       += $(subst .S,.o, $(notdir $(S_SRCS)))
+OBJS       := $(addprefix $(BUILD_DIR)/, $(OBJS))
+
+TARGET     := bin.soft
+
+ifdef SOCLIB
+
+DEFS+= -DSOCLIB_IOC
+DTS=platform_soclib.dts
+$(info Making for $(PLATFORM_DIR), SocLib variant)
+
+else
+
+DTS=platform_fpga.dts
+$(info Making for $(PLATFORM_DIR), FPGA variant)
+
+endif
+
+ifdef SYSCLK_FREQ
+DEFS+= -DSYSCLK_FREQ
+endif
+
+
+all: $(TARGET)
+
+$(TARGET): $(BUILD_DIR) $(OBJS) $(PLATFORM_DIR)/ldscript $(BUILD_DIR)/platform.ld
+	$(ECHO) "[   LD   ]     $@"
+	$(LD) -o $@ -T $(PLATFORM_DIR)/ldscript $(OBJS)
+	$(DU) -D $@ > $@.txt
+
+$(BUILD_DIR)/platform.ld: $(BUILD_DIR)/platform.dtb
+	$(HEXDUMP) -v -e '"BYTE(0x" 1/1 "%02X" ")\n"' $< > $@
+
+$(BUILD_DIR)/platform.dtb: $(DTS)
+	${DTC} -O dtb -o $@ $<
+
+$(BUILD_DIR):
+	$(MKDIR) $@
+
+clean:
+	$(RM) $(TARGET).txt $(TARGET) *~ $(BUILD_DIR)
+
+distclean: clean
+
+# =============================================================================
+# Implicit makefile rules
+
+$(BUILD_DIR)/%.o: %.c
+	$(ECHO) "[   CC   ]     $(notdir $<)"
+	$(CC) $(DEFS) $(CFLAGS) $(INCLUDE) -c -o $@ $<
+	$(DU) -D $@ > $@.txt
+
+$(BUILD_DIR)/%.o: %.S
+	$(ECHO) "[   AS   ]     $(notdir $<)"
+	$(CC) $(DEFS) ${INCLUDE} -g -mips32 -c -o $@ $<
+	$(DU) -D $@ > $@.txt
+
+.SILENT:
+endif
Index: branches/v4/softs/tsar_boot/README.txt
===================================================================
--- branches/v4/softs/tsar_boot/README.txt	(revision 371)
+++ branches/v4/softs/tsar_boot/README.txt	(revision 371)
@@ -0,0 +1,74 @@
+TSAR BOOT LOADER
+
+Files:
+===============================================================================
+src/        Source files
+            The entry point of this boot loader is the file reset.S
+
+include/    Header files
+
+conf/       Platform specific files and ldscript.
+            For each platform, we must define a new directory.
+
+      --->  defs_platform.h:
+
+             This file is mandatory. This file defines the
+             NB_PROCS per cluster, the NB_CLUSTERS and the base address of
+             the TTY, IOC and XICU devices.
+             It defines also:
+              -> CACHE_COHERENCE
+                 This constant is used by the boot_ioc_read function to know
+                 if the buffer used to store the blocks from the block_device
+                 must be invalidated in the dcache after the transfert has
+                 finished.
+				 0 means invalidation must be made.
+
+              -> CACHE_LINE_SIZE
+                 This constant defines the size in bytes of a cache line.
+
+              -> IRQ_PER_PROC
+                 This constant is used to know how many XICU irq outputs are
+                 connected to each processor.
+
+      --->  platform_soclib.dts:
+
+             Device tree file. It is mandatory if compiling
+             for a SOCLIB platform. If the application to execute does not use
+             a device tree file, create an empty one.
+
+      --->  platform_fpga.dts:
+             Device tree file. It is mandatory if compiling
+             for a FPGA platform. If the application to execute does not use
+             a device tree file, create an empty one.
+
+      --->  ldscript:
+             LD script defining the segments of this boot loader.
+             We define two segments:
+                seg_stack_base: Base address of the stack used by processor 0
+                during the boot process.
+
+                seg_boot_base: Base address of the code and data defined for
+                this loader
+            
+Makefile    Makefile for compile the boot loader.
+            Arguments to pass:
+
+             ---> PLATFORM_DIR=conf/<platform_dir>
+    
+                   Defines the directory where to find the plateform specific
+                   files
+
+             ---> SOCLIB=1
+
+                   If using SOCLIB, define this flag to use the SOCLIB device
+                   drivers
+
+             ---> SYSCLK_FREQ=<value hz>
+
+                   If not SOCLIB platform, this flag allows us to choose the
+                   CLK frequency used in the hardware platform (i.e. FPGA).
+                   This information is used to configurate the SPI device
+                   which allow us to drive a SD card device.
+
+              i.e. make PLATFORM_DIR=conf/<platform_dir> SYSCLK_FREQ=50000000
+                   make PLATFORM_DIR=conf/<platform_dir> SOCLIB=1
Index: branches/v4/softs/tsar_boot/conf/platform_fpga_de2-115/defs_platform.h
===================================================================
--- branches/v4/softs/tsar_boot/conf/platform_fpga_de2-115/defs_platform.h	(revision 371)
+++ branches/v4/softs/tsar_boot/conf/platform_fpga_de2-115/defs_platform.h	(revision 371)
@@ -0,0 +1,12 @@
+#define NB_PROCS        4
+#define NB_CLUSTERS     1
+
+#define IRQ_PER_PROC    1
+
+#define CACHE_COHERENCE 1
+#define CACHE_LINE_SIZE 64//bytes
+
+#define IOC_BASE        0xFB000000
+#define VCIBD_BASE      0xFB000000
+#define TTY_BASE        0xFC000000
+#define ICU_BASE        0xFD000000
Index: branches/v4/softs/tsar_boot/conf/platform_fpga_de2-115/ldscript
===================================================================
--- branches/v4/softs/tsar_boot/conf/platform_fpga_de2-115/ldscript	(revision 371)
+++ branches/v4/softs/tsar_boot/conf/platform_fpga_de2-115/ldscript	(revision 371)
@@ -0,0 +1,29 @@
+/**********************************************************
+  File   : ldscript 
+  Author : Cesar Fuguet
+  Date   : June 2011
+**********************************************************/
+
+/* Definition of the base address for all segments */ 
+
+seg_stack_base    = 0x00100000;
+seg_boot_base     = 0xBFC00000;       /* le code de boot */
+
+/* Grouping sections into segments */
+
+ENTRY(boot)
+SECTIONS
+{
+    . = seg_boot_base;
+    .text : {
+        *(.boot)
+        *(.reset)
+    }
+
+    .data ALIGN(0x4) : {
+        *(.reset_data)
+        . = ALIGN(0x4);
+        dtb_addr = .;
+        INCLUDE "build/platform.ld";
+    }
+}
Index: branches/v4/softs/tsar_boot/conf/platform_fpga_de2-115/platform_fpga.dts
===================================================================
--- branches/v4/softs/tsar_boot/conf/platform_fpga_de2-115/platform_fpga.dts	(revision 371)
+++ branches/v4/softs/tsar_boot/conf/platform_fpga_de2-115/platform_fpga.dts	(revision 371)
@@ -0,0 +1,173 @@
+/dts-v1/;
+
+/ {
+    #address-cells = <0x1>;
+    #size-cells = <0x1>;
+
+    cpus {
+        #address-cells = <0x1>;
+        #size-cells = <0x0>;
+
+        Mips,32@0 {
+            device_type = "cpu";
+            icudev_type = "cpu:mips";
+            name = "Mips,32";
+            reg = <0x00000000>;
+        };
+
+        Mips,32@1 {
+            device_type = "cpu";
+            icudev_type = "cpu:mips";
+            name = "Mips,32";
+            reg = <0x00000001>;
+        };
+
+        Mips,32@2 {
+            device_type = "cpu";
+            icudev_type = "cpu:mips";
+            name = "Mips,32";
+            reg = <0x00000002>;
+        };
+
+        Mips,32@3 {
+            device_type = "cpu";
+            icudev_type = "cpu:mips";
+            name = "Mips,32";
+            reg = <0x00000003>;
+        };
+    };
+
+    memory@0x00000000 {
+        cached = <0x1>;
+        device_type = "memory";
+        reg = <0x00000000 0x07e00000>;
+    };
+
+    memory@0xbfc00000 {
+        cached = <0x1>;
+        device_type = "rom";
+        reg = <0xbfc00000 0x00400000>;
+    };
+
+    tty@0xfc000000 {
+        device_type = "vci:tty";
+        irq = <&{/xicu@0xfd000000} 0x0>;
+        reg = <0xfc000000 0x00000010>;
+        tty_count = <0x1>;
+    };
+
+    blockdevice@0xfb000000 {
+        device_type = "vci:ioc";
+        irq = <&{/xicu@0xfd000000} 0x1>;
+        reg = <0xfb000000 0x00000020>;
+    };
+
+    fb@0x07e00000 {
+	device_type = "vci:vga";
+	reg = <0x07e00000 0x200000
+	       0xFA000000 0x001000>;
+	mode = <16>;
+	width = <640>;
+	height = <480>; 
+    };
+
+    xicu@0xfd000000 {
+        device_type = "soclib:xicu:root";
+        input_lines = <0x2>;
+        ipis = <0x4>;
+        reg = <0xfd000000 0x00001000>;
+        timers = <0x4>;
+
+        out@0 {
+            device_type = "soclib:xicu:filter";
+            irq = <&{/cpus/Mips,32@0} 0x0>;
+            output_line = <0x0>;
+            parent = <&{/xicu@0xfd000000}>;
+        };
+
+        out@1 {
+            device_type = "soclib:xicu:filter";
+            irq = <&{/cpus/Mips,32@0} 0x1>;
+            output_line = <0x1>;
+            parent = <&{/xicu@0xfd000000}>;
+        };
+
+        out@2 {
+            device_type = "soclib:xicu:filter";
+            irq = <&{/cpus/Mips,32@0} 0x2>;
+            output_line = <0x2>;
+            parent = <&{/xicu@0xfd000000}>;
+        };
+
+        out@3 {
+            device_type = "soclib:xicu:filter";
+            irq = <&{/cpus/Mips,32@1} 0x0>;
+            output_line = <0x3>;
+            parent = <&{/xicu@0xfd000000}>;
+        };
+
+        out@4 {
+            device_type = "soclib:xicu:filter";
+            irq = <&{/cpus/Mips,32@1} 0x1>;
+            output_line = <0x4>;
+            parent = <&{/xicu@0xfd000000}>;
+        };
+
+        out@5 {
+            device_type = "soclib:xicu:filter";
+            irq = <&{/cpus/Mips,32@1} 0x2>;
+            output_line = <0x5>;
+            parent = <&{/xicu@0xfd000000}>;
+        };
+
+        out@6 {
+            device_type = "soclib:xicu:filter";
+            irq = <&{/cpus/Mips,32@2} 0x0>;
+            output_line = <0x6>;
+            parent = <&{/xicu@0xfd000000}>;
+        };
+
+        out@7 {
+            device_type = "soclib:xicu:filter";
+            irq = <&{/cpus/Mips,32@2} 0x1>;
+            output_line = <0x7>;
+            parent = <&{/xicu@0xfd000000}>;
+        };
+
+        out@8 {
+            device_type = "soclib:xicu:filter";
+            irq = <&{/cpus/Mips,32@2} 0x2>;
+            output_line = <0x8>;
+            parent = <&{/xicu@0xfd000000}>;
+        };
+
+        out@9 {
+            device_type = "soclib:xicu:filter";
+            irq = <&{/cpus/Mips,32@3} 0x0>;
+            output_line = <0x9>;
+            parent = <&{/xicu@0xfd000000}>;
+        };
+        out@10 {
+            device_type = "soclib:xicu:filter";
+            irq = <&{/cpus/Mips,32@3} 0x1>;
+            output_line = <0xa>;
+            parent = <&{/xicu@0xfd000000}>;
+        };
+
+        out@11 {
+            device_type = "soclib:xicu:filter";
+            irq = <&{/cpus/Mips,32@3} 0x2>;
+            output_line = <0xb>;
+            parent = <&{/xicu@0xfd000000}>;
+        };
+
+    };
+  topology {
+    #address-cells = <2>;
+    #size-cells = <0>;
+    cluster@0,0 {
+    	reg = <0 0>;
+    	devices = <&{/cpus/Mips,32@0} &{/cpus/Mips,32@1} &{/cpus/Mips,32@2} &{/cpus/Mips,32@3} &{/xicu@0xfd000000} &{/tty@0xfc000000} &{/blockdevice@0xfb000000} &{/fb@0x07e00000} >;
+    };
+  };
+};
Index: branches/v4/softs/tsar_boot/conf/platform_fpga_de2-115/platform_soclib.dts
===================================================================
--- branches/v4/softs/tsar_boot/conf/platform_fpga_de2-115/platform_soclib.dts	(revision 371)
+++ branches/v4/softs/tsar_boot/conf/platform_fpga_de2-115/platform_soclib.dts	(revision 371)
@@ -0,0 +1,176 @@
+/dts-v1/;
+
+/ {
+    #address-cells = <0x1>;
+    #size-cells = <0x1>;
+
+    cpus {
+        #address-cells = <0x1>;
+        #size-cells = <0x0>;
+
+        Mips,32@0 {
+            device_type = "cpu";
+            icudev_type = "cpu:mips";
+            name = "Mips,32";
+            reg = <0x00000000>;
+        };
+
+        Mips,32@1 {
+            device_type = "cpu";
+            icudev_type = "cpu:mips";
+            name = "Mips,32";
+            reg = <0x00000001>;
+        };
+
+        Mips,32@2 {
+            device_type = "cpu";
+            icudev_type = "cpu:mips";
+            name = "Mips,32";
+            reg = <0x00000002>;
+        };
+
+        Mips,32@3 {
+            device_type = "cpu";
+            icudev_type = "cpu:mips";
+            name = "Mips,32";
+            reg = <0x00000003>;
+        };
+    };
+
+    memory@0x00000000 {
+        cached = <0x1>;
+        device_type = "memory";
+        reg = <0x00000000 0x08000000>;
+    };
+
+    memory@0xbfc00000 {
+        cached = <0x1>;
+        device_type = "rom";
+        reg = <0xbfc00000 0x00400000>;
+    };
+
+    tty@0xfc000000 {
+        device_type = "soclib:tty";
+        irq = <&{/xicu@0xfd000000} 0x0>;
+        reg = <0xfc000000 0x00000010>;
+        tty_count = <0x1>;
+    };
+    simhelper@0xf1000000 {
+        device_type = "soclib:simhelper";
+        reg = <0xf1000000 0x00000010>;
+    };
+
+    blockdevice@0xfb000000 {
+        device_type = "soclib:blockdevice";
+        irq = <&{/xicu@0xfd000000} 0x1>;
+        reg = <0xfb000000 0x00000020>;
+    };
+
+    fb@0xf0000000 {
+	device_type = "soclib:frame_buffer";
+	reg = <0xf0000000 0x400000>;
+	mode = <32>;
+	width = <640>;
+	height = <480>; 
+    };
+
+    xicu@0xfd000000 {
+        device_type = "soclib:xicu:root";
+        input_lines = <0x2>;
+        ipis = <0x4>;
+        reg = <0xfd000000 0x00001000>;
+        timers = <0x4>;
+
+        out@0 {
+            device_type = "soclib:xicu:filter";
+            irq = <&{/cpus/Mips,32@0} 0x0>;
+            output_line = <0x0>;
+            parent = <&{/xicu@0xfd000000}>;
+        };
+
+        out@1 {
+            device_type = "soclib:xicu:filter";
+            irq = <&{/cpus/Mips,32@0} 0x1>;
+            output_line = <0x1>;
+            parent = <&{/xicu@0xfd000000}>;
+        };
+
+        out@2 {
+            device_type = "soclib:xicu:filter";
+            irq = <&{/cpus/Mips,32@0} 0x2>;
+            output_line = <0x2>;
+            parent = <&{/xicu@0xfd000000}>;
+        };
+
+        out@3 {
+            device_type = "soclib:xicu:filter";
+            irq = <&{/cpus/Mips,32@1} 0x0>;
+            output_line = <0x3>;
+            parent = <&{/xicu@0xfd000000}>;
+        };
+
+        out@4 {
+            device_type = "soclib:xicu:filter";
+            irq = <&{/cpus/Mips,32@1} 0x1>;
+            output_line = <0x4>;
+            parent = <&{/xicu@0xfd000000}>;
+        };
+
+        out@5 {
+            device_type = "soclib:xicu:filter";
+            irq = <&{/cpus/Mips,32@1} 0x2>;
+            output_line = <0x5>;
+            parent = <&{/xicu@0xfd000000}>;
+        };
+
+        out@6 {
+            device_type = "soclib:xicu:filter";
+            irq = <&{/cpus/Mips,32@2} 0x0>;
+            output_line = <0x6>;
+            parent = <&{/xicu@0xfd000000}>;
+        };
+
+        out@7 {
+            device_type = "soclib:xicu:filter";
+            irq = <&{/cpus/Mips,32@2} 0x1>;
+            output_line = <0x7>;
+            parent = <&{/xicu@0xfd000000}>;
+        };
+
+        out@8 {
+            device_type = "soclib:xicu:filter";
+            irq = <&{/cpus/Mips,32@2} 0x2>;
+            output_line = <0x8>;
+            parent = <&{/xicu@0xfd000000}>;
+        };
+
+        out@9 {
+            device_type = "soclib:xicu:filter";
+            irq = <&{/cpus/Mips,32@3} 0x0>;
+            output_line = <0x9>;
+            parent = <&{/xicu@0xfd000000}>;
+        };
+        out@10 {
+            device_type = "soclib:xicu:filter";
+            irq = <&{/cpus/Mips,32@3} 0x1>;
+            output_line = <0xa>;
+            parent = <&{/xicu@0xfd000000}>;
+        };
+
+        out@11 {
+            device_type = "soclib:xicu:filter";
+            irq = <&{/cpus/Mips,32@3} 0x2>;
+            output_line = <0xb>;
+            parent = <&{/xicu@0xfd000000}>;
+        };
+
+    };
+  topology {
+    #address-cells = <2>;
+    #size-cells = <0>;
+    cluster@0,0 {
+    	reg = <0 0>;
+    	devices = <&{/cpus/Mips,32@0} &{/cpus/Mips,32@1} &{/cpus/Mips,32@2} &{/cpus/Mips,32@3} &{/xicu@0xfd000000} &{/tty@0xfc000000} &{/simhelper@0xf1000000} &{/blockdevice@0xfb000000} &{/fb@0xf0000000} >;
+    };
+  };
+};
Index: branches/v4/softs/tsar_boot/conf/platform_vgsb_xicu_mmu/defs_platform.h
===================================================================
--- branches/v4/softs/tsar_boot/conf/platform_vgsb_xicu_mmu/defs_platform.h	(revision 371)
+++ branches/v4/softs/tsar_boot/conf/platform_vgsb_xicu_mmu/defs_platform.h	(revision 371)
@@ -0,0 +1,12 @@
+#define NB_PROCS        4
+#define NB_CLUSTERS     1
+
+#define IRQ_PER_PROC    1
+
+#define CACHE_COHERENCE 0
+#define CACHE_LINE_SIZE 16//bytes
+
+#define ICU_BASE        0x00F00000
+#define IOC_BASE        0x00F10000
+#define VCIBD_BASE      IOC_BASE
+#define TTY_BASE        0x00F20000
Index: branches/v4/softs/tsar_boot/conf/platform_vgsb_xicu_mmu/ldscript
===================================================================
--- branches/v4/softs/tsar_boot/conf/platform_vgsb_xicu_mmu/ldscript	(revision 371)
+++ branches/v4/softs/tsar_boot/conf/platform_vgsb_xicu_mmu/ldscript	(revision 371)
@@ -0,0 +1,29 @@
+/**********************************************************
+  File   : ldscript 
+  Author : Cesar Fuguet
+  Date   : June 2011
+**********************************************************/
+
+/* Definition of the base address for all segments */ 
+
+seg_stack_base    = 0x00108000;
+seg_boot_base     = 0xBFC00000;       /* le code de boot */
+
+/* Grouping sections into segments */
+
+ENTRY(boot)
+SECTIONS
+{
+    . = seg_boot_base;
+    .text : {
+        *(.boot)
+        *(.reset)
+    }
+
+    .data ALIGN(0x4) : {
+        *(.reset_data)
+        . = ALIGN(0x4);
+        dtb_addr = .;
+        INCLUDE "build/platform.ld";
+    }
+}
Index: branches/v4/softs/tsar_boot/include/block_device.h
===================================================================
--- branches/v4/softs/tsar_boot/include/block_device.h	(revision 371)
+++ branches/v4/softs/tsar_boot/include/block_device.h	(revision 371)
@@ -0,0 +1,67 @@
+/*
+ * SOCLIB_LGPL_HEADER_BEGIN
+ *
+ * This file is part of SoCLib, GNU LGPLv2.1.
+ *
+ * SoCLib is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU Lesser General Public License as published
+ * by the Free Software Foundation; version 2.1 of the License.
+ *
+ * SoCLib is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with SoCLib; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301 USA
+ *
+ * SOCLIB_LGPL_HEADER_END
+ *
+ * Copyright (c) UPMC, Lip6, Asim
+ *         Nicolas Pouillon <nipo@ssji.net>, 2007
+ *
+ * Maintainers: nipo
+ */
+#ifndef BLOCK_DEVICE_REGS_H
+#define BLOCK_DEVICE_REGS_H
+
+enum SoclibBlockDeviceRegisters {
+    BLOCK_DEVICE_BUFFER,
+    BLOCK_DEVICE_LBA,
+    BLOCK_DEVICE_COUNT,
+    BLOCK_DEVICE_OP,
+    BLOCK_DEVICE_STATUS,
+    BLOCK_DEVICE_IRQ_ENABLE,
+    BLOCK_DEVICE_SIZE,
+    BLOCK_DEVICE_BLOCK_SIZE,
+};
+
+enum SoclibBlockDeviceOp {
+    BLOCK_DEVICE_NOOP,
+    BLOCK_DEVICE_READ,
+    BLOCK_DEVICE_WRITE,
+};
+
+enum SoclibBlockDeviceStatus {
+    BLOCK_DEVICE_IDLE,
+    BLOCK_DEVICE_BUSY,
+    BLOCK_DEVICE_READ_SUCCESS,
+    BLOCK_DEVICE_WRITE_SUCCESS,
+    BLOCK_DEVICE_READ_ERROR,
+    BLOCK_DEVICE_WRITE_ERROR,
+    BLOCK_DEVICE_ERROR,
+};
+
+#endif /* BLOCK_DEVICE_REGS_H */
+
+// Local Variables:
+// tab-width: 4
+// c-basic-offset: 4
+// c-file-offsets:((innamespace . 0)(inline-open . 0))
+// indent-tabs-mode: nil
+// End:
+
+// vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4
+
Index: branches/v4/softs/tsar_boot/include/boot_ioc.h
===================================================================
--- branches/v4/softs/tsar_boot/include/boot_ioc.h	(revision 371)
+++ branches/v4/softs/tsar_boot/include/boot_ioc.h	(revision 371)
@@ -0,0 +1,65 @@
+#ifndef BOOT_IOC_H
+#define BOOT_IOC_H
+
+#ifndef SOCLIB_IOC
+    #include <sdcard.h>
+    #include <spi.h>
+#else
+    #include <block_device.h>
+#endif
+
+#include <defs.h>
+#include <boot_tty.h>
+#include <io.h>
+
+/**
+ * boot_ioc_read()
+ * 
+ * Transfer data from a file on the block device to a memory buffer.
+ *
+ * \param lba    : first block index on the disk
+ * \param buffer : base address of the memory buffer
+ * \param count  : number of blocks to be transfered
+ *
+ * \note This is a blocking function. The function returns once the transfer
+ *       has finished
+ */
+int boot_ioc_read(unsigned int lba, void* buffer, unsigned int count);
+
+/**
+ * boot_ioc_init()
+ *
+ * Initialize the SPI controller use to access a SD card
+ */
+int boot_ioc_init();
+
+/**
+ * boot_dbuf_invalidate()
+ *
+ * Invalidate all data cache lines corresponding to a memory buffer.
+ */
+#if (CACHE_COHERENCE == 0)
+void boot_dbuf_invalidate(
+        const void * buffer,
+        unsigned int line_size,
+        unsigned int size);
+#endif
+
+/**
+ * boot_ioc_write()
+ *
+ * Transfer data from a memory buffer to a file on the block_device.
+ *
+ * \param lba    : first block index on the disk
+ * \param buffer : base address of the memory buffer
+ * \param count  : number of blocks to be transfered
+ *
+ * \note The source buffer must be in user address space.
+ */
+//int boot_ioc_write(unsigned int lba, void* buffer, unsigned int count);
+
+#endif
+
+/*
+ * vim: tabstop=4 : shiftwidth=4 : expandtab
+ */
Index: branches/v4/softs/tsar_boot/include/boot_memcpy.h
===================================================================
--- branches/v4/softs/tsar_boot/include/boot_memcpy.h	(revision 371)
+++ branches/v4/softs/tsar_boot/include/boot_memcpy.h	(revision 371)
@@ -0,0 +1,6 @@
+#ifndef BOOT_MEMCPY_H
+#define BOOT_MEMCPY_H
+
+void * boot_memcpy(void *_dst, const void *_src, unsigned int size);
+
+#endif
Index: branches/v4/softs/tsar_boot/include/boot_tty.h
===================================================================
--- branches/v4/softs/tsar_boot/include/boot_tty.h	(revision 371)
+++ branches/v4/softs/tsar_boot/include/boot_tty.h	(revision 371)
@@ -0,0 +1,14 @@
+#ifndef BOOT_TTY_H
+#define BOOT_TTY_H
+
+#include <io.h>
+#include <tty.h>
+
+void boot_exit();
+int  boot_getc(char * c);
+void boot_putc(const char c);
+void boot_puts(const char *buffer);
+void boot_putx(unsigned int val);
+void boot_putd(unsigned int val);
+
+#endif
Index: branches/v4/softs/tsar_boot/include/defs.h
===================================================================
--- branches/v4/softs/tsar_boot/include/defs.h	(revision 371)
+++ branches/v4/softs/tsar_boot/include/defs.h	(revision 371)
@@ -0,0 +1,8 @@
+#include <defs_platform.h>
+
+#define BOOT_VERSION    0x00010001
+
+#define BOOT_STACK_SIZE 0x8000     /* 32 KB */
+#define BOOT_LOADER_LBA 2
+#define PHDR_ARRAY_SIZE	16
+
Index: branches/v4/softs/tsar_boot/include/elf-types.h
===================================================================
--- branches/v4/softs/tsar_boot/include/elf-types.h	(revision 371)
+++ branches/v4/softs/tsar_boot/include/elf-types.h	(revision 371)
@@ -0,0 +1,2645 @@
+/* This file defines standard ELF types, structures, and macros.
+   Copyright (C) 1995-2003,2004,2005,2006,2007 Free Software Foundation, Inc.
+   This file is part of the GNU C Library.
+
+   The GNU C Library is free software; you can redistribute it and/or
+   modify it under the terms of the GNU Lesser General Public
+   License as published by the Free Software Foundation; either
+   version 2.1 of the License, or (at your option) any later version.
+
+   The GNU C Library is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+   Lesser General Public License for more details.
+
+   You should have received a copy of the GNU Lesser General Public
+   License along with the GNU C Library; if not, write to the Free
+   Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
+   02111-1307 USA.  */
+
+#ifndef _ELF_TYPES_H
+#define	_ELF_TYPES_H
+
+/* Type for a 16-bit quantity.  */
+typedef unsigned short Elf32_Half;
+typedef unsigned short Elf64_Half;
+
+/* Types for signed and unsigned 32-bit quantities.  */
+typedef unsigned int   Elf32_Word;
+typedef	int            Elf32_Sword;
+typedef unsigned int   Elf64_Word;
+typedef	int            Elf64_Sword;
+
+/* Types for signed and unsigned 64-bit quantities.  */
+typedef unsigned long  Elf32_Xword;
+typedef	long           Elf32_Sxword;
+typedef unsigned long  Elf64_Xword;
+typedef	long           Elf64_Sxword;
+
+/* Type of addresses.  */
+typedef unsigned int   Elf32_Addr;
+typedef unsigned long  Elf64_Addr;
+
+/* Type of file offsets.  */
+typedef unsigned int   Elf32_Off;
+typedef unsigned long  Elf64_Off;
+
+/* Type for section indices, which are 16-bit quantities.  */
+typedef unsigned short Elf32_Section;
+typedef unsigned short Elf64_Section;
+
+/* Type for version symbol information.  */
+typedef Elf32_Half Elf32_Versym;
+typedef Elf64_Half Elf64_Versym;
+
+
+/* The ELF file header.  This appears at the start of every ELF file.  */
+
+#define EI_NIDENT (16)
+
+typedef struct
+{
+  unsigned char	e_ident[EI_NIDENT];	/* Magic number and other info */
+  Elf32_Half	e_type;			/* Object file type */
+  Elf32_Half	e_machine;		/* Architecture */
+  Elf32_Word	e_version;		/* Object file version */
+  Elf32_Addr	e_entry;		/* Entry point virtual address */
+  Elf32_Off	e_phoff;		/* Program header table file offset */
+  Elf32_Off	e_shoff;		/* Section header table file offset */
+  Elf32_Word	e_flags;		/* Processor-specific flags */
+  Elf32_Half	e_ehsize;		/* ELF header size in bytes */
+  Elf32_Half	e_phentsize;		/* Program header table entry size */
+  Elf32_Half	e_phnum;		/* Program header table entry count */
+  Elf32_Half	e_shentsize;		/* Section header table entry size */
+  Elf32_Half	e_shnum;		/* Section header table entry count */
+  Elf32_Half	e_shstrndx;		/* Section header string table index */
+} Elf32_Ehdr;
+
+typedef struct
+{
+  unsigned char	e_ident[EI_NIDENT];	/* Magic number and other info */
+  Elf64_Half	e_type;			/* Object file type */
+  Elf64_Half	e_machine;		/* Architecture */
+  Elf64_Word	e_version;		/* Object file version */
+  Elf64_Addr	e_entry;		/* Entry point virtual address */
+  Elf64_Off	e_phoff;		/* Program header table file offset */
+  Elf64_Off	e_shoff;		/* Section header table file offset */
+  Elf64_Word	e_flags;		/* Processor-specific flags */
+  Elf64_Half	e_ehsize;		/* ELF header size in bytes */
+  Elf64_Half	e_phentsize;		/* Program header table entry size */
+  Elf64_Half	e_phnum;		/* Program header table entry count */
+  Elf64_Half	e_shentsize;		/* Section header table entry size */
+  Elf64_Half	e_shnum;		/* Section header table entry count */
+  Elf64_Half	e_shstrndx;		/* Section header string table index */
+} Elf64_Ehdr;
+
+/* Fields in the e_ident array.  The EI_* macros are indices into the
+   array.  The macros under each EI_* macro are the values the byte
+   may have.  */
+
+#define EI_MAG0		0		/* File identification byte 0 index */
+#define ELFMAG0		0x7f		/* Magic number byte 0 */
+
+#define EI_MAG1		1		/* File identification byte 1 index */
+#define ELFMAG1		'E'		/* Magic number byte 1 */
+
+#define EI_MAG2		2		/* File identification byte 2 index */
+#define ELFMAG2		'L'		/* Magic number byte 2 */
+
+#define EI_MAG3		3		/* File identification byte 3 index */
+#define ELFMAG3		'F'		/* Magic number byte 3 */
+
+/* Conglomeration of the identification bytes, for easy testing as a word.  */
+#define	ELFMAG		"\177ELF"
+#define	SELFMAG		4
+
+#define EI_CLASS	4		/* File class byte index */
+#define ELFCLASSNONE	0		/* Invalid class */
+#define ELFCLASS32	1		/* 32-bit objects */
+#define ELFCLASS64	2		/* 64-bit objects */
+#define ELFCLASSNUM	3
+
+#define EI_DATA		5		/* Data encoding byte index */
+#define ELFDATANONE	0		/* Invalid data encoding */
+#define ELFDATA2LSB	1		/* 2's complement, little endian */
+#define ELFDATA2MSB	2		/* 2's complement, big endian */
+#define ELFDATANUM	3
+
+#define EI_VERSION	6		/* File version byte index */
+					/* Value must be EV_CURRENT */
+
+#define EI_OSABI	7		/* OS ABI identification */
+#define ELFOSABI_NONE		0	/* UNIX System V ABI */
+#define ELFOSABI_SYSV		0	/* Alias.  */
+#define ELFOSABI_HPUX		1	/* HP-UX */
+#define ELFOSABI_NETBSD		2	/* NetBSD.  */
+#define ELFOSABI_LINUX		3	/* Linux.  */
+#define ELFOSABI_SOLARIS	6	/* Sun Solaris.  */
+#define ELFOSABI_AIX		7	/* IBM AIX.  */
+#define ELFOSABI_IRIX		8	/* SGI Irix.  */
+#define ELFOSABI_FREEBSD	9	/* FreeBSD.  */
+#define ELFOSABI_TRU64		10	/* Compaq TRU64 UNIX.  */
+#define ELFOSABI_MODESTO	11	/* Novell Modesto.  */
+#define ELFOSABI_OPENBSD	12	/* OpenBSD.  */
+#define ELFOSABI_ARM		97	/* ARM */
+#define ELFOSABI_STANDALONE	255	/* Standalone (embedded) application */
+
+#define EI_ABIVERSION	8		/* ABI version */
+
+#define EI_PAD		9		/* Byte index of padding bytes */
+
+/* Legal values for e_type (object file type).  */
+
+#define ET_NONE		0		/* No file type */
+#define ET_REL		1		/* Relocatable file */
+#define ET_EXEC		2		/* Executable file */
+#define ET_DYN		3		/* Shared object file */
+#define ET_CORE		4		/* Core file */
+#define	ET_NUM		5		/* Number of defined types */
+#define ET_LOOS		0xfe00		/* OS-specific range start */
+#define ET_HIOS		0xfeff		/* OS-specific range end */
+#define ET_LOPROC	0xff00		/* Processor-specific range start */
+#define ET_HIPROC	0xffff		/* Processor-specific range end */
+
+/* Legal values for e_machine (architecture).  */
+
+#define EM_NONE		 0		/* No machine */
+#define EM_M32		 1		/* AT&T WE 32100 */
+#define EM_SPARC	 2		/* SUN SPARC */
+#define EM_386		 3		/* Intel 80386 */
+#define EM_68K		 4		/* Motorola m68k family */
+#define EM_88K		 5		/* Motorola m88k family */
+#define EM_860		 7		/* Intel 80860 */
+#define EM_MIPS		 8		/* MIPS R3000 big-endian */
+#define EM_S370		 9		/* IBM System/370 */
+#define EM_MIPS_RS3_LE	10		/* MIPS R3000 little-endian */
+
+#define EM_PARISC	15		/* HPPA */
+#define EM_VPP500	17		/* Fujitsu VPP500 */
+#define EM_SPARC32PLUS	18		/* Sun's "v8plus" */
+#define EM_960		19		/* Intel 80960 */
+#define EM_PPC		20		/* PowerPC */
+#define EM_PPC64	21		/* PowerPC 64-bit */
+#define EM_S390		22		/* IBM S390 */
+
+#define EM_V800		36		/* NEC V800 series */
+#define EM_FR20		37		/* Fujitsu FR20 */
+#define EM_RH32		38		/* TRW RH-32 */
+#define EM_RCE		39		/* Motorola RCE */
+#define EM_ARM		40		/* ARM */
+#define EM_FAKE_ALPHA	41		/* Digital Alpha */
+#define EM_SH		42		/* Hitachi SH */
+#define EM_SPARCV9	43		/* SPARC v9 64-bit */
+#define EM_TRICORE	44		/* Siemens Tricore */
+#define EM_ARC		45		/* Argonaut RISC Core */
+#define EM_H8_300	46		/* Hitachi H8/300 */
+#define EM_H8_300H	47		/* Hitachi H8/300H */
+#define EM_H8S		48		/* Hitachi H8S */
+#define EM_H8_500	49		/* Hitachi H8/500 */
+#define EM_IA_64	50		/* Intel Merced */
+#define EM_MIPS_X	51		/* Stanford MIPS-X */
+#define EM_COLDFIRE	52		/* Motorola Coldfire */
+#define EM_68HC12	53		/* Motorola M68HC12 */
+#define EM_MMA		54		/* Fujitsu MMA Multimedia Accelerator*/
+#define EM_PCP		55		/* Siemens PCP */
+#define EM_NCPU		56		/* Sony nCPU embeeded RISC */
+#define EM_NDR1		57		/* Denso NDR1 microprocessor */
+#define EM_STARCORE	58		/* Motorola Start*Core processor */
+#define EM_ME16		59		/* Toyota ME16 processor */
+#define EM_ST100	60		/* STMicroelectronic ST100 processor */
+#define EM_TINYJ	61		/* Advanced Logic Corp. Tinyj emb.fam*/
+#define EM_X86_64	62		/* AMD x86-64 architecture */
+#define EM_PDSP		63		/* Sony DSP Processor */
+
+#define EM_FX66		66		/* Siemens FX66 microcontroller */
+#define EM_ST9PLUS	67		/* STMicroelectronics ST9+ 8/16 mc */
+#define EM_ST7		68		/* STmicroelectronics ST7 8 bit mc */
+#define EM_68HC16	69		/* Motorola MC68HC16 microcontroller */
+#define EM_68HC11	70		/* Motorola MC68HC11 microcontroller */
+#define EM_68HC08	71		/* Motorola MC68HC08 microcontroller */
+#define EM_68HC05	72		/* Motorola MC68HC05 microcontroller */
+#define EM_SVX		73		/* Silicon Graphics SVx */
+#define EM_ST19		74		/* STMicroelectronics ST19 8 bit mc */
+#define EM_VAX		75		/* Digital VAX */
+#define EM_CRIS		76		/* Axis Communications 32-bit embedded processor */
+#define EM_JAVELIN	77		/* Infineon Technologies 32-bit embedded processor */
+#define EM_FIREPATH	78		/* Element 14 64-bit DSP Processor */
+#define EM_ZSP		79		/* LSI Logic 16-bit DSP Processor */
+#define EM_MMIX		80		/* Donald Knuth's educational 64-bit processor */
+#define EM_HUANY	81		/* Harvard University machine-independent object files */
+#define EM_PRISM	82		/* SiTera Prism */
+#define EM_AVR		83		/* Atmel AVR 8-bit microcontroller */
+#define EM_FR30		84		/* Fujitsu FR30 */
+#define EM_D10V		85		/* Mitsubishi D10V */
+#define EM_D30V		86		/* Mitsubishi D30V */
+#define EM_V850		87		/* NEC v850 */
+#define EM_M32R		88		/* Mitsubishi M32R */
+#define EM_MN10300	89		/* Matsushita MN10300 */
+#define EM_MN10200	90		/* Matsushita MN10200 */
+#define EM_PJ		91		/* picoJava */
+#define EM_OPENRISC	92		/* OpenRISC 32-bit embedded processor */
+#define EM_ARC_A5	93		/* ARC Cores Tangent-A5 */
+#define EM_XTENSA	94		/* Tensilica Xtensa Architecture */
+#define EM_NUM		95
+
+/* If it is necessary to assign new unofficial EM_* values, please
+   pick large random numbers (0x8523, 0xa7f2, etc.) to minimize the
+   chances of collision with official or non-GNU unofficial values.  */
+
+#define EM_ALPHA	0x9026
+
+/* Legal values for e_version (version).  */
+
+#define EV_NONE		0		/* Invalid ELF version */
+#define EV_CURRENT	1		/* Current version */
+#define EV_NUM		2
+
+/* Section header.  */
+
+typedef struct
+{
+  Elf32_Word	sh_name;		/* Section name (string tbl index) */
+  Elf32_Word	sh_type;		/* Section type */
+  Elf32_Word	sh_flags;		/* Section flags */
+  Elf32_Addr	sh_addr;		/* Section virtual addr at execution */
+  Elf32_Off	sh_offset;		/* Section file offset */
+  Elf32_Word	sh_size;		/* Section size in bytes */
+  Elf32_Word	sh_link;		/* Link to another section */
+  Elf32_Word	sh_info;		/* Additional section information */
+  Elf32_Word	sh_addralign;		/* Section alignment */
+  Elf32_Word	sh_entsize;		/* Entry size if section holds table */
+} Elf32_Shdr;
+
+typedef struct
+{
+  Elf64_Word	sh_name;		/* Section name (string tbl index) */
+  Elf64_Word	sh_type;		/* Section type */
+  Elf64_Xword	sh_flags;		/* Section flags */
+  Elf64_Addr	sh_addr;		/* Section virtual addr at execution */
+  Elf64_Off	sh_offset;		/* Section file offset */
+  Elf64_Xword	sh_size;		/* Section size in bytes */
+  Elf64_Word	sh_link;		/* Link to another section */
+  Elf64_Word	sh_info;		/* Additional section information */
+  Elf64_Xword	sh_addralign;		/* Section alignment */
+  Elf64_Xword	sh_entsize;		/* Entry size if section holds table */
+} Elf64_Shdr;
+
+/* Special section indices.  */
+
+#define SHN_UNDEF	0		/* Undefined section */
+#define SHN_LORESERVE	0xff00		/* Start of reserved indices */
+#define SHN_LOPROC	0xff00		/* Start of processor-specific */
+#define SHN_BEFORE	0xff00		/* Order section before all others
+					   (Solaris).  */
+#define SHN_AFTER	0xff01		/* Order section after all others
+					   (Solaris).  */
+#define SHN_HIPROC	0xff1f		/* End of processor-specific */
+#define SHN_LOOS	0xff20		/* Start of OS-specific */
+#define SHN_HIOS	0xff3f		/* End of OS-specific */
+#define SHN_ABS		0xfff1		/* Associated symbol is absolute */
+#define SHN_COMMON	0xfff2		/* Associated symbol is common */
+#define SHN_XINDEX	0xffff		/* Index is in extra table.  */
+#define SHN_HIRESERVE	0xffff		/* End of reserved indices */
+
+/* Legal values for sh_type (section type).  */
+
+#define SHT_NULL	  0		/* Section header table entry unused */
+#define SHT_PROGBITS	  1		/* Program data */
+#define SHT_SYMTAB	  2		/* Symbol table */
+#define SHT_STRTAB	  3		/* String table */
+#define SHT_RELA	  4		/* Relocation entries with addends */
+#define SHT_HASH	  5		/* Symbol hash table */
+#define SHT_DYNAMIC	  6		/* Dynamic linking information */
+#define SHT_NOTE	  7		/* Notes */
+#define SHT_NOBITS	  8		/* Program space with no data (bss) */
+#define SHT_REL		  9		/* Relocation entries, no addends */
+#define SHT_SHLIB	  10		/* Reserved */
+#define SHT_DYNSYM	  11		/* Dynamic linker symbol table */
+#define SHT_INIT_ARRAY	  14		/* Array of constructors */
+#define SHT_FINI_ARRAY	  15		/* Array of destructors */
+#define SHT_PREINIT_ARRAY 16		/* Array of pre-constructors */
+#define SHT_GROUP	  17		/* Section group */
+#define SHT_SYMTAB_SHNDX  18		/* Extended section indeces */
+#define	SHT_NUM		  19		/* Number of defined types.  */
+#define SHT_LOOS	  0x60000000	/* Start OS-specific.  */
+#define SHT_GNU_HASH	  0x6ffffff6	/* GNU-style hash table.  */
+#define SHT_GNU_LIBLIST	  0x6ffffff7	/* Prelink library list */
+#define SHT_CHECKSUM	  0x6ffffff8	/* Checksum for DSO content.  */
+#define SHT_LOSUNW	  0x6ffffffa	/* Sun-specific low bound.  */
+#define SHT_SUNW_move	  0x6ffffffa
+#define SHT_SUNW_COMDAT   0x6ffffffb
+#define SHT_SUNW_syminfo  0x6ffffffc
+#define SHT_GNU_verdef	  0x6ffffffd	/* Version definition section.  */
+#define SHT_GNU_verneed	  0x6ffffffe	/* Version needs section.  */
+#define SHT_GNU_versym	  0x6fffffff	/* Version symbol table.  */
+#define SHT_HISUNW	  0x6fffffff	/* Sun-specific high bound.  */
+#define SHT_HIOS	  0x6fffffff	/* End OS-specific type */
+#define SHT_LOPROC	  0x70000000	/* Start of processor-specific */
+#define SHT_HIPROC	  0x7fffffff	/* End of processor-specific */
+#define SHT_LOUSER	  0x80000000	/* Start of application-specific */
+#define SHT_HIUSER	  0x8fffffff	/* End of application-specific */
+
+/* Legal values for sh_flags (section flags).  */
+
+#define SHF_WRITE	     (1 << 0)	/* Writable */
+#define SHF_ALLOC	     (1 << 1)	/* Occupies memory during execution */
+#define SHF_EXECINSTR	     (1 << 2)	/* Executable */
+#define SHF_MERGE	     (1 << 4)	/* Might be merged */
+#define SHF_STRINGS	     (1 << 5)	/* Contains nul-terminated strings */
+#define SHF_INFO_LINK	     (1 << 6)	/* `sh_info' contains SHT index */
+#define SHF_LINK_ORDER	     (1 << 7)	/* Preserve order after combining */
+#define SHF_OS_NONCONFORMING (1 << 8)	/* Non-standard OS specific handling
+					   required */
+#define SHF_GROUP	     (1 << 9)	/* Section is member of a group.  */
+#define SHF_TLS		     (1 << 10)	/* Section hold thread-local data.  */
+#define SHF_MASKOS	     0x0ff00000	/* OS-specific.  */
+#define SHF_MASKPROC	     0xf0000000	/* Processor-specific */
+#define SHF_ORDERED	     (1 << 30)	/* Special ordering requirement
+					   (Solaris).  */
+#define SHF_EXCLUDE	     (1 << 31)	/* Section is excluded unless
+					   referenced or allocated (Solaris).*/
+
+/* Section group handling.  */
+#define GRP_COMDAT	0x1		/* Mark group as COMDAT.  */
+
+/* Symbol table entry.  */
+
+typedef struct
+{
+  Elf32_Word	st_name;		/* Symbol name (string tbl index) */
+  Elf32_Addr	st_value;		/* Symbol value */
+  Elf32_Word	st_size;		/* Symbol size */
+  unsigned char	st_info;		/* Symbol type and binding */
+  unsigned char	st_other;		/* Symbol visibility */
+  Elf32_Section	st_shndx;		/* Section index */
+} Elf32_Sym;
+
+typedef struct
+{
+  Elf64_Word	st_name;		/* Symbol name (string tbl index) */
+  unsigned char	st_info;		/* Symbol type and binding */
+  unsigned char st_other;		/* Symbol visibility */
+  Elf64_Section	st_shndx;		/* Section index */
+  Elf64_Addr	st_value;		/* Symbol value */
+  Elf64_Xword	st_size;		/* Symbol size */
+} Elf64_Sym;
+
+/* The syminfo section if available contains additional information about
+   every dynamic symbol.  */
+
+typedef struct
+{
+  Elf32_Half si_boundto;		/* Direct bindings, symbol bound to */
+  Elf32_Half si_flags;			/* Per symbol flags */
+} Elf32_Syminfo;
+
+typedef struct
+{
+  Elf64_Half si_boundto;		/* Direct bindings, symbol bound to */
+  Elf64_Half si_flags;			/* Per symbol flags */
+} Elf64_Syminfo;
+
+/* Possible values for si_boundto.  */
+#define SYMINFO_BT_SELF		0xffff	/* Symbol bound to self */
+#define SYMINFO_BT_PARENT	0xfffe	/* Symbol bound to parent */
+#define SYMINFO_BT_LOWRESERVE	0xff00	/* Beginning of reserved entries */
+
+/* Possible bitmasks for si_flags.  */
+#define SYMINFO_FLG_DIRECT	0x0001	/* Direct bound symbol */
+#define SYMINFO_FLG_PASSTHRU	0x0002	/* Pass-thru symbol for translator */
+#define SYMINFO_FLG_COPY	0x0004	/* Symbol is a copy-reloc */
+#define SYMINFO_FLG_LAZYLOAD	0x0008	/* Symbol bound to object to be lazy
+					   loaded */
+/* Syminfo version values.  */
+#define SYMINFO_NONE		0
+#define SYMINFO_CURRENT		1
+#define SYMINFO_NUM		2
+
+
+/* How to extract and insert information held in the st_info field.  */
+
+#define ELF32_ST_BIND(val)		(((unsigned char) (val)) >> 4)
+#define ELF32_ST_TYPE(val)		((val) & 0xf)
+#define ELF32_ST_INFO(bind, type)	(((bind) << 4) + ((type) & 0xf))
+
+/* Both Elf32_Sym and Elf64_Sym use the same one-byte st_info field.  */
+#define ELF64_ST_BIND(val)		ELF32_ST_BIND (val)
+#define ELF64_ST_TYPE(val)		ELF32_ST_TYPE (val)
+#define ELF64_ST_INFO(bind, type)	ELF32_ST_INFO ((bind), (type))
+
+/* Legal values for ST_BIND subfield of st_info (symbol binding).  */
+
+#define STB_LOCAL	0		/* Local symbol */
+#define STB_GLOBAL	1		/* Global symbol */
+#define STB_WEAK	2		/* Weak symbol */
+#define	STB_NUM		3		/* Number of defined types.  */
+#define STB_LOOS	10		/* Start of OS-specific */
+#define STB_HIOS	12		/* End of OS-specific */
+#define STB_LOPROC	13		/* Start of processor-specific */
+#define STB_HIPROC	15		/* End of processor-specific */
+
+/* Legal values for ST_TYPE subfield of st_info (symbol type).  */
+
+#define STT_NOTYPE	0		/* Symbol type is unspecified */
+#define STT_OBJECT	1		/* Symbol is a data object */
+#define STT_FUNC	2		/* Symbol is a code object */
+#define STT_SECTION	3		/* Symbol associated with a section */
+#define STT_FILE	4		/* Symbol's name is file name */
+#define STT_COMMON	5		/* Symbol is a common data object */
+#define STT_TLS		6		/* Symbol is thread-local data object*/
+#define	STT_NUM		7		/* Number of defined types.  */
+#define STT_LOOS	10		/* Start of OS-specific */
+#define STT_HIOS	12		/* End of OS-specific */
+#define STT_LOPROC	13		/* Start of processor-specific */
+#define STT_HIPROC	15		/* End of processor-specific */
+
+
+/* Symbol table indices are found in the hash buckets and chain table
+   of a symbol hash table section.  This special index value indicates
+   the end of a chain, meaning no further symbols are found in that bucket.  */
+
+#define STN_UNDEF	0		/* End of a chain.  */
+
+
+/* How to extract and insert information held in the st_other field.  */
+
+#define ELF32_ST_VISIBILITY(o)	((o) & 0x03)
+
+/* For ELF64 the definitions are the same.  */
+#define ELF64_ST_VISIBILITY(o)	ELF32_ST_VISIBILITY (o)
+
+/* Symbol visibility specification encoded in the st_other field.  */
+#define STV_DEFAULT	0		/* Default symbol visibility rules */
+#define STV_INTERNAL	1		/* Processor specific hidden class */
+#define STV_HIDDEN	2		/* Sym unavailable in other modules */
+#define STV_PROTECTED	3		/* Not preemptible, not exported */
+
+
+/* Relocation table entry without addend (in section of type SHT_REL).  */
+
+typedef struct
+{
+  Elf32_Addr	r_offset;		/* Address */
+  Elf32_Word	r_info;			/* Relocation type and symbol index */
+} Elf32_Rel;
+
+/* I have seen two different definitions of the Elf64_Rel and
+   Elf64_Rela structures, so we'll leave them out until Novell (or
+   whoever) gets their act together.  */
+/* The following, at least, is used on Sparc v9, MIPS, and Alpha.  */
+
+typedef struct
+{
+  Elf64_Addr	r_offset;		/* Address */
+  Elf64_Xword	r_info;			/* Relocation type and symbol index */
+} Elf64_Rel;
+
+/* Relocation table entry with addend (in section of type SHT_RELA).  */
+
+typedef struct
+{
+  Elf32_Addr	r_offset;		/* Address */
+  Elf32_Word	r_info;			/* Relocation type and symbol index */
+  Elf32_Sword	r_addend;		/* Addend */
+} Elf32_Rela;
+
+typedef struct
+{
+  Elf64_Addr	r_offset;		/* Address */
+  Elf64_Xword	r_info;			/* Relocation type and symbol index */
+  Elf64_Sxword	r_addend;		/* Addend */
+} Elf64_Rela;
+
+/* How to extract and insert information held in the r_info field.  */
+
+#define ELF32_R_SYM(val)		((val) >> 8)
+#define ELF32_R_TYPE(val)		((val) & 0xff)
+#define ELF32_R_INFO(sym, type)		(((sym) << 8) + ((type) & 0xff))
+
+#define ELF64_R_SYM(i)			((i) >> 32)
+#define ELF64_R_TYPE(i)			((i) & 0xffffffff)
+#define ELF64_R_INFO(sym,type)		((((Elf64_Xword) (sym)) << 32) + (type))
+
+/* Program segment header.  */
+
+typedef struct
+{
+  Elf32_Word	p_type;			/* Segment type */
+  Elf32_Off	p_offset;		/* Segment file offset */
+  Elf32_Addr	p_vaddr;		/* Segment virtual address */
+  Elf32_Addr	p_paddr;		/* Segment physical address */
+  Elf32_Word	p_filesz;		/* Segment size in file */
+  Elf32_Word	p_memsz;		/* Segment size in memory */
+  Elf32_Word	p_flags;		/* Segment flags */
+  Elf32_Word	p_align;		/* Segment alignment */
+} Elf32_Phdr;
+
+typedef struct
+{
+  Elf64_Word	p_type;			/* Segment type */
+  Elf64_Word	p_flags;		/* Segment flags */
+  Elf64_Off	p_offset;		/* Segment file offset */
+  Elf64_Addr	p_vaddr;		/* Segment virtual address */
+  Elf64_Addr	p_paddr;		/* Segment physical address */
+  Elf64_Xword	p_filesz;		/* Segment size in file */
+  Elf64_Xword	p_memsz;		/* Segment size in memory */
+  Elf64_Xword	p_align;		/* Segment alignment */
+} Elf64_Phdr;
+
+/* Legal values for p_type (segment type).  */
+
+#define	PT_NULL		0		/* Program header table entry unused */
+#define PT_LOAD		1		/* Loadable program segment */
+#define PT_DYNAMIC	2		/* Dynamic linking information */
+#define PT_INTERP	3		/* Program interpreter */
+#define PT_NOTE		4		/* Auxiliary information */
+#define PT_SHLIB	5		/* Reserved */
+#define PT_PHDR		6		/* Entry for header table itself */
+#define PT_TLS		7		/* Thread-local storage segment */
+#define	PT_NUM		8		/* Number of defined types */
+#define PT_LOOS		0x60000000	/* Start of OS-specific */
+#define PT_GNU_EH_FRAME	0x6474e550	/* GCC .eh_frame_hdr segment */
+#define PT_GNU_STACK	0x6474e551	/* Indicates stack executability */
+#define PT_GNU_RELRO	0x6474e552	/* Read-only after relocation */
+#define PT_LOSUNW	0x6ffffffa
+#define PT_SUNWBSS	0x6ffffffa	/* Sun Specific segment */
+#define PT_SUNWSTACK	0x6ffffffb	/* Stack segment */
+#define PT_HISUNW	0x6fffffff
+#define PT_HIOS		0x6fffffff	/* End of OS-specific */
+#define PT_LOPROC	0x70000000	/* Start of processor-specific */
+#define PT_HIPROC	0x7fffffff	/* End of processor-specific */
+
+/* Legal values for p_flags (segment flags).  */
+
+#define PF_X		(1 << 0)	/* Segment is executable */
+#define PF_W		(1 << 1)	/* Segment is writable */
+#define PF_R		(1 << 2)	/* Segment is readable */
+#define PF_MASKOS	0x0ff00000	/* OS-specific */
+#define PF_MASKPROC	0xf0000000	/* Processor-specific */
+
+/* Legal values for note segment descriptor types for core files. */
+
+#define NT_PRSTATUS	1		/* Contains copy of prstatus struct */
+#define NT_FPREGSET	2		/* Contains copy of fpregset struct */
+#define NT_PRPSINFO	3		/* Contains copy of prpsinfo struct */
+#define NT_PRXREG	4		/* Contains copy of prxregset struct */
+#define NT_TASKSTRUCT	4		/* Contains copy of task structure */
+#define NT_PLATFORM	5		/* String from sysinfo(SI_PLATFORM) */
+#define NT_AUXV		6		/* Contains copy of auxv array */
+#define NT_GWINDOWS	7		/* Contains copy of gwindows struct */
+#define NT_ASRS		8		/* Contains copy of asrset struct */
+#define NT_PSTATUS	10		/* Contains copy of pstatus struct */
+#define NT_PSINFO	13		/* Contains copy of psinfo struct */
+#define NT_PRCRED	14		/* Contains copy of prcred struct */
+#define NT_UTSNAME	15		/* Contains copy of utsname struct */
+#define NT_LWPSTATUS	16		/* Contains copy of lwpstatus struct */
+#define NT_LWPSINFO	17		/* Contains copy of lwpinfo struct */
+#define NT_PRFPXREG	20		/* Contains copy of fprxregset struct */
+#define NT_PRXFPREG	0x46e62b7f	/* Contains copy of user_fxsr_struct */
+
+/* Legal values for the note segment descriptor types for object files.  */
+
+#define NT_VERSION	1		/* Contains a version string.  */
+
+
+/* Dynamic section entry.  */
+
+typedef struct
+{
+  Elf32_Sword	d_tag;			/* Dynamic entry type */
+  union
+    {
+      Elf32_Word d_val;			/* Integer value */
+      Elf32_Addr d_ptr;			/* Address value */
+    } d_un;
+} Elf32_Dyn;
+
+typedef struct
+{
+  Elf64_Sxword	d_tag;			/* Dynamic entry type */
+  union
+    {
+      Elf64_Xword d_val;		/* Integer value */
+      Elf64_Addr d_ptr;			/* Address value */
+    } d_un;
+} Elf64_Dyn;
+
+/* Legal values for d_tag (dynamic entry type).  */
+
+#define DT_NULL		0		/* Marks end of dynamic section */
+#define DT_NEEDED	1		/* Name of needed library */
+#define DT_PLTRELSZ	2		/* Size in bytes of PLT relocs */
+#define DT_PLTGOT	3		/* Processor defined value */
+#define DT_HASH		4		/* Address of symbol hash table */
+#define DT_STRTAB	5		/* Address of string table */
+#define DT_SYMTAB	6		/* Address of symbol table */
+#define DT_RELA		7		/* Address of Rela relocs */
+#define DT_RELASZ	8		/* Total size of Rela relocs */
+#define DT_RELAENT	9		/* Size of one Rela reloc */
+#define DT_STRSZ	10		/* Size of string table */
+#define DT_SYMENT	11		/* Size of one symbol table entry */
+#define DT_INIT		12		/* Address of init function */
+#define DT_FINI		13		/* Address of termination function */
+#define DT_SONAME	14		/* Name of shared object */
+#define DT_RPATH	15		/* Library search path (deprecated) */
+#define DT_SYMBOLIC	16		/* Start symbol search here */
+#define DT_REL		17		/* Address of Rel relocs */
+#define DT_RELSZ	18		/* Total size of Rel relocs */
+#define DT_RELENT	19		/* Size of one Rel reloc */
+#define DT_PLTREL	20		/* Type of reloc in PLT */
+#define DT_DEBUG	21		/* For debugging; unspecified */
+#define DT_TEXTREL	22		/* Reloc might modify .text */
+#define DT_JMPREL	23		/* Address of PLT relocs */
+#define	DT_BIND_NOW	24		/* Process relocations of object */
+#define	DT_INIT_ARRAY	25		/* Array with addresses of init fct */
+#define	DT_FINI_ARRAY	26		/* Array with addresses of fini fct */
+#define	DT_INIT_ARRAYSZ	27		/* Size in bytes of DT_INIT_ARRAY */
+#define	DT_FINI_ARRAYSZ	28		/* Size in bytes of DT_FINI_ARRAY */
+#define DT_RUNPATH	29		/* Library search path */
+#define DT_FLAGS	30		/* Flags for the object being loaded */
+#define DT_ENCODING	32		/* Start of encoded range */
+#define DT_PREINIT_ARRAY 32		/* Array with addresses of preinit fct*/
+#define DT_PREINIT_ARRAYSZ 33		/* size in bytes of DT_PREINIT_ARRAY */
+#define	DT_NUM		34		/* Number used */
+#define DT_LOOS		0x6000000d	/* Start of OS-specific */
+#define DT_HIOS		0x6ffff000	/* End of OS-specific */
+#define DT_LOPROC	0x70000000	/* Start of processor-specific */
+#define DT_HIPROC	0x7fffffff	/* End of processor-specific */
+#define	DT_PROCNUM	DT_MIPS_NUM	/* Most used by any processor */
+
+/* DT_* entries which fall between DT_VALRNGHI & DT_VALRNGLO use the
+   Dyn.d_un.d_val field of the Elf*_Dyn structure.  This follows Sun's
+   approach.  */
+#define DT_VALRNGLO	0x6ffffd00
+#define DT_GNU_PRELINKED 0x6ffffdf5	/* Prelinking timestamp */
+#define DT_GNU_CONFLICTSZ 0x6ffffdf6	/* Size of conflict section */
+#define DT_GNU_LIBLISTSZ 0x6ffffdf7	/* Size of library list */
+#define DT_CHECKSUM	0x6ffffdf8
+#define DT_PLTPADSZ	0x6ffffdf9
+#define DT_MOVEENT	0x6ffffdfa
+#define DT_MOVESZ	0x6ffffdfb
+#define DT_FEATURE_1	0x6ffffdfc	/* Feature selection (DTF_*).  */
+#define DT_POSFLAG_1	0x6ffffdfd	/* Flags for DT_* entries, effecting
+					   the following DT_* entry.  */
+#define DT_SYMINSZ	0x6ffffdfe	/* Size of syminfo table (in bytes) */
+#define DT_SYMINENT	0x6ffffdff	/* Entry size of syminfo */
+#define DT_VALRNGHI	0x6ffffdff
+#define DT_VALTAGIDX(tag)	(DT_VALRNGHI - (tag))	/* Reverse order! */
+#define DT_VALNUM 12
+
+/* DT_* entries which fall between DT_ADDRRNGHI & DT_ADDRRNGLO use the
+   Dyn.d_un.d_ptr field of the Elf*_Dyn structure.
+
+   If any adjustment is made to the ELF object after it has been
+   built these entries will need to be adjusted.  */
+#define DT_ADDRRNGLO	0x6ffffe00
+#define DT_GNU_HASH	0x6ffffef5	/* GNU-style hash table.  */
+#define DT_TLSDESC_PLT	0x6ffffef6
+#define DT_TLSDESC_GOT	0x6ffffef7
+#define DT_GNU_CONFLICT	0x6ffffef8	/* Start of conflict section */
+#define DT_GNU_LIBLIST	0x6ffffef9	/* Library list */
+#define DT_CONFIG	0x6ffffefa	/* Configuration information.  */
+#define DT_DEPAUDIT	0x6ffffefb	/* Dependency auditing.  */
+#define DT_AUDIT	0x6ffffefc	/* Object auditing.  */
+#define	DT_PLTPAD	0x6ffffefd	/* PLT padding.  */
+#define	DT_MOVETAB	0x6ffffefe	/* Move table.  */
+#define DT_SYMINFO	0x6ffffeff	/* Syminfo table.  */
+#define DT_ADDRRNGHI	0x6ffffeff
+#define DT_ADDRTAGIDX(tag)	(DT_ADDRRNGHI - (tag))	/* Reverse order! */
+#define DT_ADDRNUM 11
+
+/* The versioning entry types.  The next are defined as part of the
+   GNU extension.  */
+#define DT_VERSYM	0x6ffffff0
+
+#define DT_RELACOUNT	0x6ffffff9
+#define DT_RELCOUNT	0x6ffffffa
+
+/* These were chosen by Sun.  */
+#define DT_FLAGS_1	0x6ffffffb	/* State flags, see DF_1_* below.  */
+#define	DT_VERDEF	0x6ffffffc	/* Address of version definition
+					   table */
+#define	DT_VERDEFNUM	0x6ffffffd	/* Number of version definitions */
+#define	DT_VERNEED	0x6ffffffe	/* Address of table with needed
+					   versions */
+#define	DT_VERNEEDNUM	0x6fffffff	/* Number of needed versions */
+#define DT_VERSIONTAGIDX(tag)	(DT_VERNEEDNUM - (tag))	/* Reverse order! */
+#define DT_VERSIONTAGNUM 16
+
+/* Sun added these machine-independent extensions in the "processor-specific"
+   range.  Be compatible.  */
+#define DT_AUXILIARY    0x7ffffffd      /* Shared object to load before self */
+#define DT_FILTER       0x7fffffff      /* Shared object to get values from */
+#define DT_EXTRATAGIDX(tag)	((Elf32_Word)-((Elf32_Sword) (tag) <<1>>1)-1)
+#define DT_EXTRANUM	3
+
+/* Values of `d_un.d_val' in the DT_FLAGS entry.  */
+#define DF_ORIGIN	0x00000001	/* Object may use DF_ORIGIN */
+#define DF_SYMBOLIC	0x00000002	/* Symbol resolutions starts here */
+#define DF_TEXTREL	0x00000004	/* Object contains text relocations */
+#define DF_BIND_NOW	0x00000008	/* No lazy binding for this object */
+#define DF_STATIC_TLS	0x00000010	/* Module uses the static TLS model */
+
+/* State flags selectable in the `d_un.d_val' element of the DT_FLAGS_1
+   entry in the dynamic section.  */
+#define DF_1_NOW	0x00000001	/* Set RTLD_NOW for this object.  */
+#define DF_1_GLOBAL	0x00000002	/* Set RTLD_GLOBAL for this object.  */
+#define DF_1_GROUP	0x00000004	/* Set RTLD_GROUP for this object.  */
+#define DF_1_NODELETE	0x00000008	/* Set RTLD_NODELETE for this object.*/
+#define DF_1_LOADFLTR	0x00000010	/* Trigger filtee loading at runtime.*/
+#define DF_1_INITFIRST	0x00000020	/* Set RTLD_INITFIRST for this object*/
+#define DF_1_NOOPEN	0x00000040	/* Set RTLD_NOOPEN for this object.  */
+#define DF_1_ORIGIN	0x00000080	/* $ORIGIN must be handled.  */
+#define DF_1_DIRECT	0x00000100	/* Direct binding enabled.  */
+#define DF_1_TRANS	0x00000200
+#define DF_1_INTERPOSE	0x00000400	/* Object is used to interpose.  */
+#define DF_1_NODEFLIB	0x00000800	/* Ignore default lib search path.  */
+#define DF_1_NODUMP	0x00001000	/* Object can't be dldump'ed.  */
+#define DF_1_CONFALT	0x00002000	/* Configuration alternative created.*/
+#define DF_1_ENDFILTEE	0x00004000	/* Filtee terminates filters search. */
+#define	DF_1_DISPRELDNE	0x00008000	/* Disp reloc applied at build time. */
+#define	DF_1_DISPRELPND	0x00010000	/* Disp reloc applied at run-time.  */
+
+/* Flags for the feature selection in DT_FEATURE_1.  */
+#define DTF_1_PARINIT	0x00000001
+#define DTF_1_CONFEXP	0x00000002
+
+/* Flags in the DT_POSFLAG_1 entry effecting only the next DT_* entry.  */
+#define DF_P1_LAZYLOAD	0x00000001	/* Lazyload following object.  */
+#define DF_P1_GROUPPERM	0x00000002	/* Symbols from next object are not
+					   generally available.  */
+
+/* Version definition sections.  */
+
+typedef struct
+{
+  Elf32_Half	vd_version;		/* Version revision */
+  Elf32_Half	vd_flags;		/* Version information */
+  Elf32_Half	vd_ndx;			/* Version Index */
+  Elf32_Half	vd_cnt;			/* Number of associated aux entries */
+  Elf32_Word	vd_hash;		/* Version name hash value */
+  Elf32_Word	vd_aux;			/* Offset in bytes to verdaux array */
+  Elf32_Word	vd_next;		/* Offset in bytes to next verdef
+					   entry */
+} Elf32_Verdef;
+
+typedef struct
+{
+  Elf64_Half	vd_version;		/* Version revision */
+  Elf64_Half	vd_flags;		/* Version information */
+  Elf64_Half	vd_ndx;			/* Version Index */
+  Elf64_Half	vd_cnt;			/* Number of associated aux entries */
+  Elf64_Word	vd_hash;		/* Version name hash value */
+  Elf64_Word	vd_aux;			/* Offset in bytes to verdaux array */
+  Elf64_Word	vd_next;		/* Offset in bytes to next verdef
+					   entry */
+} Elf64_Verdef;
+
+
+/* Legal values for vd_version (version revision).  */
+#define VER_DEF_NONE	0		/* No version */
+#define VER_DEF_CURRENT	1		/* Current version */
+#define VER_DEF_NUM	2		/* Given version number */
+
+/* Legal values for vd_flags (version information flags).  */
+#define VER_FLG_BASE	0x1		/* Version definition of file itself */
+#define VER_FLG_WEAK	0x2		/* Weak version identifier */
+
+/* Versym symbol index values.  */
+#define	VER_NDX_LOCAL		0	/* Symbol is local.  */
+#define	VER_NDX_GLOBAL		1	/* Symbol is global.  */
+#define	VER_NDX_LORESERVE	0xff00	/* Beginning of reserved entries.  */
+#define	VER_NDX_ELIMINATE	0xff01	/* Symbol is to be eliminated.  */
+
+/* Auxialiary version information.  */
+
+typedef struct
+{
+  Elf32_Word	vda_name;		/* Version or dependency names */
+  Elf32_Word	vda_next;		/* Offset in bytes to next verdaux
+					   entry */
+} Elf32_Verdaux;
+
+typedef struct
+{
+  Elf64_Word	vda_name;		/* Version or dependency names */
+  Elf64_Word	vda_next;		/* Offset in bytes to next verdaux
+					   entry */
+} Elf64_Verdaux;
+
+
+/* Version dependency section.  */
+
+typedef struct
+{
+  Elf32_Half	vn_version;		/* Version of structure */
+  Elf32_Half	vn_cnt;			/* Number of associated aux entries */
+  Elf32_Word	vn_file;		/* Offset of filename for this
+					   dependency */
+  Elf32_Word	vn_aux;			/* Offset in bytes to vernaux array */
+  Elf32_Word	vn_next;		/* Offset in bytes to next verneed
+					   entry */
+} Elf32_Verneed;
+
+typedef struct
+{
+  Elf64_Half	vn_version;		/* Version of structure */
+  Elf64_Half	vn_cnt;			/* Number of associated aux entries */
+  Elf64_Word	vn_file;		/* Offset of filename for this
+					   dependency */
+  Elf64_Word	vn_aux;			/* Offset in bytes to vernaux array */
+  Elf64_Word	vn_next;		/* Offset in bytes to next verneed
+					   entry */
+} Elf64_Verneed;
+
+
+/* Legal values for vn_version (version revision).  */
+#define VER_NEED_NONE	 0		/* No version */
+#define VER_NEED_CURRENT 1		/* Current version */
+#define VER_NEED_NUM	 2		/* Given version number */
+
+/* Auxiliary needed version information.  */
+
+typedef struct
+{
+  Elf32_Word	vna_hash;		/* Hash value of dependency name */
+  Elf32_Half	vna_flags;		/* Dependency specific information */
+  Elf32_Half	vna_other;		/* Unused */
+  Elf32_Word	vna_name;		/* Dependency name string offset */
+  Elf32_Word	vna_next;		/* Offset in bytes to next vernaux
+					   entry */
+} Elf32_Vernaux;
+
+typedef struct
+{
+  Elf64_Word	vna_hash;		/* Hash value of dependency name */
+  Elf64_Half	vna_flags;		/* Dependency specific information */
+  Elf64_Half	vna_other;		/* Unused */
+  Elf64_Word	vna_name;		/* Dependency name string offset */
+  Elf64_Word	vna_next;		/* Offset in bytes to next vernaux
+					   entry */
+} Elf64_Vernaux;
+
+
+/* Legal values for vna_flags.  */
+#define VER_FLG_WEAK	0x2		/* Weak version identifier */
+
+
+/* Auxiliary vector.  */
+
+/* This vector is normally only used by the program interpreter.  The
+   usual definition in an ABI supplement uses the name auxv_t.  The
+   vector is not usually defined in a standard <elf.h> file, but it
+   can't hurt.  We rename it to avoid conflicts.  The sizes of these
+   types are an arrangement between the exec server and the program
+   interpreter, so we don't fully specify them here.  */
+
+typedef struct
+{
+  unsigned int a_type;		/* Entry type */
+  union
+    {
+      unsigned int a_val;		/* Integer value */
+      /* We use to have pointer elements added here.  We cannot do that,
+	 though, since it does not work when using 32-bit definitions
+	 on 64-bit platforms and vice versa.  */
+    } a_un;
+} Elf32_auxv_t;
+
+typedef struct
+{
+  unsigned long a_type;		/* Entry type */
+  union
+    {
+      unsigned long a_val;		/* Integer value */
+      /* We use to have pointer elements added here.  We cannot do that,
+	 though, since it does not work when using 32-bit definitions
+	 on 64-bit platforms and vice versa.  */
+    } a_un;
+} Elf64_auxv_t;
+
+/* Legal values for a_type (entry type).  */
+
+#define AT_NULL		0		/* End of vector */
+#define AT_IGNORE	1		/* Entry should be ignored */
+#define AT_EXECFD	2		/* File descriptor of program */
+#define AT_PHDR		3		/* Program headers for program */
+#define AT_PHENT	4		/* Size of program header entry */
+#define AT_PHNUM	5		/* Number of program headers */
+#define AT_PAGESZ	6		/* System page size */
+#define AT_BASE		7		/* Base address of interpreter */
+#define AT_FLAGS	8		/* Flags */
+#define AT_ENTRY	9		/* Entry point of program */
+#define AT_NOTELF	10		/* Program is not ELF */
+#define AT_UID		11		/* Real uid */
+#define AT_EUID		12		/* Effective uid */
+#define AT_GID		13		/* Real gid */
+#define AT_EGID		14		/* Effective gid */
+#define AT_CLKTCK	17		/* Frequency of times() */
+
+/* Some more special a_type values describing the hardware.  */
+#define AT_PLATFORM	15		/* String identifying platform.  */
+#define AT_HWCAP	16		/* Machine dependent hints about
+					   processor capabilities.  */
+
+/* This entry gives some information about the FPU initialization
+   performed by the kernel.  */
+#define AT_FPUCW	18		/* Used FPU control word.  */
+
+/* Cache block sizes.  */
+#define AT_DCACHEBSIZE	19		/* Data cache block size.  */
+#define AT_ICACHEBSIZE	20		/* Instruction cache block size.  */
+#define AT_UCACHEBSIZE	21		/* Unified cache block size.  */
+
+/* A special ignored value for PPC, used by the kernel to control the
+   interpretation of the AUXV. Must be > 16.  */
+#define AT_IGNOREPPC	22		/* Entry should be ignored.  */
+
+#define	AT_SECURE	23		/* Boolean, was exec setuid-like?  */
+
+/* Pointer to the global system page used for system calls and other
+   nice things.  */
+#define AT_SYSINFO	32
+#define AT_SYSINFO_EHDR	33
+
+/* Shapes of the caches.  Bits 0-3 contains associativity; bits 4-7 contains
+   log2 of line size; mask those to get cache size.  */
+#define AT_L1I_CACHESHAPE	34
+#define AT_L1D_CACHESHAPE	35
+#define AT_L2_CACHESHAPE	36
+#define AT_L3_CACHESHAPE	37
+
+/* Note section contents.  Each entry in the note section begins with
+   a header of a fixed form.  */
+
+typedef struct
+{
+  Elf32_Word n_namesz;			/* Length of the note's name.  */
+  Elf32_Word n_descsz;			/* Length of the note's descriptor.  */
+  Elf32_Word n_type;			/* Type of the note.  */
+} Elf32_Nhdr;
+
+typedef struct
+{
+  Elf64_Word n_namesz;			/* Length of the note's name.  */
+  Elf64_Word n_descsz;			/* Length of the note's descriptor.  */
+  Elf64_Word n_type;			/* Type of the note.  */
+} Elf64_Nhdr;
+
+/* Known names of notes.  */
+
+/* Solaris entries in the note section have this name.  */
+#define ELF_NOTE_SOLARIS	"SUNW Solaris"
+
+/* Note entries for GNU systems have this name.  */
+#define ELF_NOTE_GNU		"GNU"
+
+
+/* Defined types of notes for Solaris.  */
+
+/* Value of descriptor (one word) is desired pagesize for the binary.  */
+#define ELF_NOTE_PAGESIZE_HINT	1
+
+
+/* Defined note types for GNU systems.  */
+
+/* ABI information.  The descriptor consists of words:
+   word 0: OS descriptor
+   word 1: major version of the ABI
+   word 2: minor version of the ABI
+   word 3: subminor version of the ABI
+*/
+#define NT_GNU_ABI_TAG	1
+#define ELF_NOTE_ABI	NT_GNU_ABI_TAG /* Old name.  */
+
+/* Known OSes.  These values can appear in word 0 of an
+   NT_GNU_ABI_TAG note section entry.  */
+#define ELF_NOTE_OS_LINUX	0
+#define ELF_NOTE_OS_GNU		1
+#define ELF_NOTE_OS_SOLARIS2	2
+#define ELF_NOTE_OS_FREEBSD	3
+
+/* Synthetic hwcap information.  The descriptor begins with two words:
+   word 0: number of entries
+   word 1: bitmask of enabled entries
+   Then follow variable-length entries, one byte followed by a
+   '\0'-terminated hwcap name string.  The byte gives the bit
+   number to test if enabled, (1U << bit) & bitmask.  */
+#define NT_GNU_HWCAP	2
+
+/* Build ID bits as generated by ld --build-id.
+   The descriptor consists of any nonzero number of bytes.  */
+#define NT_GNU_BUILD_ID	3
+
+
+/* Move records.  */
+typedef struct
+{
+  Elf32_Xword m_value;		/* Symbol value.  */
+  Elf32_Word m_info;		/* Size and index.  */
+  Elf32_Word m_poffset;		/* Symbol offset.  */
+  Elf32_Half m_repeat;		/* Repeat count.  */
+  Elf32_Half m_stride;		/* Stride info.  */
+} Elf32_Move;
+
+typedef struct
+{
+  Elf64_Xword m_value;		/* Symbol value.  */
+  Elf64_Xword m_info;		/* Size and index.  */
+  Elf64_Xword m_poffset;	/* Symbol offset.  */
+  Elf64_Half m_repeat;		/* Repeat count.  */
+  Elf64_Half m_stride;		/* Stride info.  */
+} Elf64_Move;
+
+/* Macro to construct move records.  */
+#define ELF32_M_SYM(info)	((info) >> 8)
+#define ELF32_M_SIZE(info)	((unsigned char) (info))
+#define ELF32_M_INFO(sym, size)	(((sym) << 8) + (unsigned char) (size))
+
+#define ELF64_M_SYM(info)	ELF32_M_SYM (info)
+#define ELF64_M_SIZE(info)	ELF32_M_SIZE (info)
+#define ELF64_M_INFO(sym, size)	ELF32_M_INFO (sym, size)
+
+
+/* Motorola 68k specific definitions.  */
+
+/* Values for Elf32_Ehdr.e_flags.  */
+#define EF_CPU32	0x00810000
+
+/* m68k relocs.  */
+
+#define R_68K_NONE	0		/* No reloc */
+#define R_68K_32	1		/* Direct 32 bit  */
+#define R_68K_16	2		/* Direct 16 bit  */
+#define R_68K_8		3		/* Direct 8 bit  */
+#define R_68K_PC32	4		/* PC relative 32 bit */
+#define R_68K_PC16	5		/* PC relative 16 bit */
+#define R_68K_PC8	6		/* PC relative 8 bit */
+#define R_68K_GOT32	7		/* 32 bit PC relative GOT entry */
+#define R_68K_GOT16	8		/* 16 bit PC relative GOT entry */
+#define R_68K_GOT8	9		/* 8 bit PC relative GOT entry */
+#define R_68K_GOT32O	10		/* 32 bit GOT offset */
+#define R_68K_GOT16O	11		/* 16 bit GOT offset */
+#define R_68K_GOT8O	12		/* 8 bit GOT offset */
+#define R_68K_PLT32	13		/* 32 bit PC relative PLT address */
+#define R_68K_PLT16	14		/* 16 bit PC relative PLT address */
+#define R_68K_PLT8	15		/* 8 bit PC relative PLT address */
+#define R_68K_PLT32O	16		/* 32 bit PLT offset */
+#define R_68K_PLT16O	17		/* 16 bit PLT offset */
+#define R_68K_PLT8O	18		/* 8 bit PLT offset */
+#define R_68K_COPY	19		/* Copy symbol at runtime */
+#define R_68K_GLOB_DAT	20		/* Create GOT entry */
+#define R_68K_JMP_SLOT	21		/* Create PLT entry */
+#define R_68K_RELATIVE	22		/* Adjust by program base */
+/* Keep this the last entry.  */
+#define R_68K_NUM	23
+
+/* Intel 80386 specific definitions.  */
+
+/* i386 relocs.  */
+
+#define R_386_NONE	   0		/* No reloc */
+#define R_386_32	   1		/* Direct 32 bit  */
+#define R_386_PC32	   2		/* PC relative 32 bit */
+#define R_386_GOT32	   3		/* 32 bit GOT entry */
+#define R_386_PLT32	   4		/* 32 bit PLT address */
+#define R_386_COPY	   5		/* Copy symbol at runtime */
+#define R_386_GLOB_DAT	   6		/* Create GOT entry */
+#define R_386_JMP_SLOT	   7		/* Create PLT entry */
+#define R_386_RELATIVE	   8		/* Adjust by program base */
+#define R_386_GOTOFF	   9		/* 32 bit offset to GOT */
+#define R_386_GOTPC	   10		/* 32 bit PC relative offset to GOT */
+#define R_386_32PLT	   11
+#define R_386_TLS_TPOFF	   14		/* Offset in static TLS block */
+#define R_386_TLS_IE	   15		/* Address of GOT entry for static TLS
+					   block offset */
+#define R_386_TLS_GOTIE	   16		/* GOT entry for static TLS block
+					   offset */
+#define R_386_TLS_LE	   17		/* Offset relative to static TLS
+					   block */
+#define R_386_TLS_GD	   18		/* Direct 32 bit for GNU version of
+					   general dynamic thread local data */
+#define R_386_TLS_LDM	   19		/* Direct 32 bit for GNU version of
+					   local dynamic thread local data
+					   in LE code */
+#define R_386_16	   20
+#define R_386_PC16	   21
+#define R_386_8		   22
+#define R_386_PC8	   23
+#define R_386_TLS_GD_32	   24		/* Direct 32 bit for general dynamic
+					   thread local data */
+#define R_386_TLS_GD_PUSH  25		/* Tag for pushl in GD TLS code */
+#define R_386_TLS_GD_CALL  26		/* Relocation for call to
+					   __tls_get_addr() */
+#define R_386_TLS_GD_POP   27		/* Tag for popl in GD TLS code */
+#define R_386_TLS_LDM_32   28		/* Direct 32 bit for local dynamic
+					   thread local data in LE code */
+#define R_386_TLS_LDM_PUSH 29		/* Tag for pushl in LDM TLS code */
+#define R_386_TLS_LDM_CALL 30		/* Relocation for call to
+					   __tls_get_addr() in LDM code */
+#define R_386_TLS_LDM_POP  31		/* Tag for popl in LDM TLS code */
+#define R_386_TLS_LDO_32   32		/* Offset relative to TLS block */
+#define R_386_TLS_IE_32	   33		/* GOT entry for negated static TLS
+					   block offset */
+#define R_386_TLS_LE_32	   34		/* Negated offset relative to static
+					   TLS block */
+#define R_386_TLS_DTPMOD32 35		/* ID of module containing symbol */
+#define R_386_TLS_DTPOFF32 36		/* Offset in TLS block */
+#define R_386_TLS_TPOFF32  37		/* Negated offset in static TLS block */
+/* Keep this the last entry.  */
+#define R_386_NUM	   38
+
+/* SUN SPARC specific definitions.  */
+
+/* Legal values for ST_TYPE subfield of st_info (symbol type).  */
+
+#define STT_SPARC_REGISTER	13	/* Global register reserved to app. */
+
+/* Values for Elf64_Ehdr.e_flags.  */
+
+#define EF_SPARCV9_MM		3
+#define EF_SPARCV9_TSO		0
+#define EF_SPARCV9_PSO		1
+#define EF_SPARCV9_RMO		2
+#define EF_SPARC_LEDATA		0x800000 /* little endian data */
+#define EF_SPARC_EXT_MASK	0xFFFF00
+#define EF_SPARC_32PLUS		0x000100 /* generic V8+ features */
+#define EF_SPARC_SUN_US1	0x000200 /* Sun UltraSPARC1 extensions */
+#define EF_SPARC_HAL_R1		0x000400 /* HAL R1 extensions */
+#define EF_SPARC_SUN_US3	0x000800 /* Sun UltraSPARCIII extensions */
+
+/* SPARC relocs.  */
+
+#define R_SPARC_NONE		0	/* No reloc */
+#define R_SPARC_8		1	/* Direct 8 bit */
+#define R_SPARC_16		2	/* Direct 16 bit */
+#define R_SPARC_32		3	/* Direct 32 bit */
+#define R_SPARC_DISP8		4	/* PC relative 8 bit */
+#define R_SPARC_DISP16		5	/* PC relative 16 bit */
+#define R_SPARC_DISP32		6	/* PC relative 32 bit */
+#define R_SPARC_WDISP30		7	/* PC relative 30 bit shifted */
+#define R_SPARC_WDISP22		8	/* PC relative 22 bit shifted */
+#define R_SPARC_HI22		9	/* High 22 bit */
+#define R_SPARC_22		10	/* Direct 22 bit */
+#define R_SPARC_13		11	/* Direct 13 bit */
+#define R_SPARC_LO10		12	/* Truncated 10 bit */
+#define R_SPARC_GOT10		13	/* Truncated 10 bit GOT entry */
+#define R_SPARC_GOT13		14	/* 13 bit GOT entry */
+#define R_SPARC_GOT22		15	/* 22 bit GOT entry shifted */
+#define R_SPARC_PC10		16	/* PC relative 10 bit truncated */
+#define R_SPARC_PC22		17	/* PC relative 22 bit shifted */
+#define R_SPARC_WPLT30		18	/* 30 bit PC relative PLT address */
+#define R_SPARC_COPY		19	/* Copy symbol at runtime */
+#define R_SPARC_GLOB_DAT	20	/* Create GOT entry */
+#define R_SPARC_JMP_SLOT	21	/* Create PLT entry */
+#define R_SPARC_RELATIVE	22	/* Adjust by program base */
+#define R_SPARC_UA32		23	/* Direct 32 bit unaligned */
+
+/* Additional Sparc64 relocs.  */
+
+#define R_SPARC_PLT32		24	/* Direct 32 bit ref to PLT entry */
+#define R_SPARC_HIPLT22		25	/* High 22 bit PLT entry */
+#define R_SPARC_LOPLT10		26	/* Truncated 10 bit PLT entry */
+#define R_SPARC_PCPLT32		27	/* PC rel 32 bit ref to PLT entry */
+#define R_SPARC_PCPLT22		28	/* PC rel high 22 bit PLT entry */
+#define R_SPARC_PCPLT10		29	/* PC rel trunc 10 bit PLT entry */
+#define R_SPARC_10		30	/* Direct 10 bit */
+#define R_SPARC_11		31	/* Direct 11 bit */
+#define R_SPARC_64		32	/* Direct 64 bit */
+#define R_SPARC_OLO10		33	/* 10bit with secondary 13bit addend */
+#define R_SPARC_HH22		34	/* Top 22 bits of direct 64 bit */
+#define R_SPARC_HM10		35	/* High middle 10 bits of ... */
+#define R_SPARC_LM22		36	/* Low middle 22 bits of ... */
+#define R_SPARC_PC_HH22		37	/* Top 22 bits of pc rel 64 bit */
+#define R_SPARC_PC_HM10		38	/* High middle 10 bit of ... */
+#define R_SPARC_PC_LM22		39	/* Low miggle 22 bits of ... */
+#define R_SPARC_WDISP16		40	/* PC relative 16 bit shifted */
+#define R_SPARC_WDISP19		41	/* PC relative 19 bit shifted */
+#define R_SPARC_7		43	/* Direct 7 bit */
+#define R_SPARC_5		44	/* Direct 5 bit */
+#define R_SPARC_6		45	/* Direct 6 bit */
+#define R_SPARC_DISP64		46	/* PC relative 64 bit */
+#define R_SPARC_PLT64		47	/* Direct 64 bit ref to PLT entry */
+#define R_SPARC_HIX22		48	/* High 22 bit complemented */
+#define R_SPARC_LOX10		49	/* Truncated 11 bit complemented */
+#define R_SPARC_H44		50	/* Direct high 12 of 44 bit */
+#define R_SPARC_M44		51	/* Direct mid 22 of 44 bit */
+#define R_SPARC_L44		52	/* Direct low 10 of 44 bit */
+#define R_SPARC_REGISTER	53	/* Global register usage */
+#define R_SPARC_UA64		54	/* Direct 64 bit unaligned */
+#define R_SPARC_UA16		55	/* Direct 16 bit unaligned */
+#define R_SPARC_TLS_GD_HI22	56
+#define R_SPARC_TLS_GD_LO10	57
+#define R_SPARC_TLS_GD_ADD	58
+#define R_SPARC_TLS_GD_CALL	59
+#define R_SPARC_TLS_LDM_HI22	60
+#define R_SPARC_TLS_LDM_LO10	61
+#define R_SPARC_TLS_LDM_ADD	62
+#define R_SPARC_TLS_LDM_CALL	63
+#define R_SPARC_TLS_LDO_HIX22	64
+#define R_SPARC_TLS_LDO_LOX10	65
+#define R_SPARC_TLS_LDO_ADD	66
+#define R_SPARC_TLS_IE_HI22	67
+#define R_SPARC_TLS_IE_LO10	68
+#define R_SPARC_TLS_IE_LD	69
+#define R_SPARC_TLS_IE_LDX	70
+#define R_SPARC_TLS_IE_ADD	71
+#define R_SPARC_TLS_LE_HIX22	72
+#define R_SPARC_TLS_LE_LOX10	73
+#define R_SPARC_TLS_DTPMOD32	74
+#define R_SPARC_TLS_DTPMOD64	75
+#define R_SPARC_TLS_DTPOFF32	76
+#define R_SPARC_TLS_DTPOFF64	77
+#define R_SPARC_TLS_TPOFF32	78
+#define R_SPARC_TLS_TPOFF64	79
+/* Keep this the last entry.  */
+#define R_SPARC_NUM		80
+
+/* For Sparc64, legal values for d_tag of Elf64_Dyn.  */
+
+#define DT_SPARC_REGISTER 0x70000001
+#define DT_SPARC_NUM	2
+
+/* Bits present in AT_HWCAP on SPARC.  */
+
+#define HWCAP_SPARC_FLUSH	1	/* The CPU supports flush insn.  */
+#define HWCAP_SPARC_STBAR	2
+#define HWCAP_SPARC_SWAP	4
+#define HWCAP_SPARC_MULDIV	8
+#define HWCAP_SPARC_V9		16	/* The CPU is v9, so v8plus is ok.  */
+#define HWCAP_SPARC_ULTRA3	32
+#define HWCAP_SPARC_BLKINIT	64	/* Sun4v with block-init/load-twin.  */
+#define HWCAP_SPARC_N2		128
+
+/* MIPS R3000 specific definitions.  */
+
+/* Legal values for e_flags field of Elf32_Ehdr.  */
+
+#define EF_MIPS_NOREORDER   1		/* A .noreorder directive was used */
+#define EF_MIPS_PIC	    2		/* Contains PIC code */
+#define EF_MIPS_CPIC	    4		/* Uses PIC calling sequence */
+#define EF_MIPS_XGOT	    8
+#define EF_MIPS_64BIT_WHIRL 16
+#define EF_MIPS_ABI2	    32
+#define EF_MIPS_ABI_ON32    64
+#define EF_MIPS_ARCH	    0xf0000000	/* MIPS architecture level */
+
+/* Legal values for MIPS architecture level.  */
+
+#define EF_MIPS_ARCH_1	    0x00000000	/* -mips1 code.  */
+#define EF_MIPS_ARCH_2	    0x10000000	/* -mips2 code.  */
+#define EF_MIPS_ARCH_3	    0x20000000	/* -mips3 code.  */
+#define EF_MIPS_ARCH_4	    0x30000000	/* -mips4 code.  */
+#define EF_MIPS_ARCH_5	    0x40000000	/* -mips5 code.  */
+#define EF_MIPS_ARCH_32	    0x60000000	/* MIPS32 code.  */
+#define EF_MIPS_ARCH_64	    0x70000000	/* MIPS64 code.  */
+
+/* The following are non-official names and should not be used.  */
+
+#define E_MIPS_ARCH_1	  0x00000000	/* -mips1 code.  */
+#define E_MIPS_ARCH_2	  0x10000000	/* -mips2 code.  */
+#define E_MIPS_ARCH_3	  0x20000000	/* -mips3 code.  */
+#define E_MIPS_ARCH_4	  0x30000000	/* -mips4 code.  */
+#define E_MIPS_ARCH_5	  0x40000000	/* -mips5 code.  */
+#define E_MIPS_ARCH_32	  0x60000000	/* MIPS32 code.  */
+#define E_MIPS_ARCH_64	  0x70000000	/* MIPS64 code.  */
+
+/* Special section indices.  */
+
+#define SHN_MIPS_ACOMMON    0xff00	/* Allocated common symbols */
+#define SHN_MIPS_TEXT	    0xff01	/* Allocated test symbols.  */
+#define SHN_MIPS_DATA	    0xff02	/* Allocated data symbols.  */
+#define SHN_MIPS_SCOMMON    0xff03	/* Small common symbols */
+#define SHN_MIPS_SUNDEFINED 0xff04	/* Small undefined symbols */
+
+/* Legal values for sh_type field of Elf32_Shdr.  */
+
+#define SHT_MIPS_LIBLIST       0x70000000 /* Shared objects used in link */
+#define SHT_MIPS_MSYM	       0x70000001
+#define SHT_MIPS_CONFLICT      0x70000002 /* Conflicting symbols */
+#define SHT_MIPS_GPTAB	       0x70000003 /* Global data area sizes */
+#define SHT_MIPS_UCODE	       0x70000004 /* Reserved for SGI/MIPS compilers */
+#define SHT_MIPS_DEBUG	       0x70000005 /* MIPS ECOFF debugging information*/
+#define SHT_MIPS_REGINFO       0x70000006 /* Register usage information */
+#define SHT_MIPS_PACKAGE       0x70000007
+#define SHT_MIPS_PACKSYM       0x70000008
+#define SHT_MIPS_RELD	       0x70000009
+#define SHT_MIPS_IFACE         0x7000000b
+#define SHT_MIPS_CONTENT       0x7000000c
+#define SHT_MIPS_OPTIONS       0x7000000d /* Miscellaneous options.  */
+#define SHT_MIPS_SHDR	       0x70000010
+#define SHT_MIPS_FDESC	       0x70000011
+#define SHT_MIPS_EXTSYM	       0x70000012
+#define SHT_MIPS_DENSE	       0x70000013
+#define SHT_MIPS_PDESC	       0x70000014
+#define SHT_MIPS_LOCSYM	       0x70000015
+#define SHT_MIPS_AUXSYM	       0x70000016
+#define SHT_MIPS_OPTSYM	       0x70000017
+#define SHT_MIPS_LOCSTR	       0x70000018
+#define SHT_MIPS_LINE	       0x70000019
+#define SHT_MIPS_RFDESC	       0x7000001a
+#define SHT_MIPS_DELTASYM      0x7000001b
+#define SHT_MIPS_DELTAINST     0x7000001c
+#define SHT_MIPS_DELTACLASS    0x7000001d
+#define SHT_MIPS_DWARF         0x7000001e /* DWARF debugging information.  */
+#define SHT_MIPS_DELTADECL     0x7000001f
+#define SHT_MIPS_SYMBOL_LIB    0x70000020
+#define SHT_MIPS_EVENTS	       0x70000021 /* Event section.  */
+#define SHT_MIPS_TRANSLATE     0x70000022
+#define SHT_MIPS_PIXIE	       0x70000023
+#define SHT_MIPS_XLATE	       0x70000024
+#define SHT_MIPS_XLATE_DEBUG   0x70000025
+#define SHT_MIPS_WHIRL	       0x70000026
+#define SHT_MIPS_EH_REGION     0x70000027
+#define SHT_MIPS_XLATE_OLD     0x70000028
+#define SHT_MIPS_PDR_EXCEPTION 0x70000029
+
+/* Legal values for sh_flags field of Elf32_Shdr.  */
+
+#define SHF_MIPS_GPREL	 0x10000000	/* Must be part of global data area */
+#define SHF_MIPS_MERGE	 0x20000000
+#define SHF_MIPS_ADDR	 0x40000000
+#define SHF_MIPS_STRINGS 0x80000000
+#define SHF_MIPS_NOSTRIP 0x08000000
+#define SHF_MIPS_LOCAL	 0x04000000
+#define SHF_MIPS_NAMES	 0x02000000
+#define SHF_MIPS_NODUPE	 0x01000000
+
+
+/* Symbol tables.  */
+
+/* MIPS specific values for `st_other'.  */
+#define STO_MIPS_DEFAULT		0x0
+#define STO_MIPS_INTERNAL		0x1
+#define STO_MIPS_HIDDEN			0x2
+#define STO_MIPS_PROTECTED		0x3
+#define STO_MIPS_SC_ALIGN_UNUSED	0xff
+
+/* MIPS specific values for `st_info'.  */
+#define STB_MIPS_SPLIT_COMMON		13
+
+/* Entries found in sections of type SHT_MIPS_GPTAB.  */
+
+typedef union
+{
+  struct
+    {
+      Elf32_Word gt_current_g_value;	/* -G value used for compilation */
+      Elf32_Word gt_unused;		/* Not used */
+    } gt_header;			/* First entry in section */
+  struct
+    {
+      Elf32_Word gt_g_value;		/* If this value were used for -G */
+      Elf32_Word gt_bytes;		/* This many bytes would be used */
+    } gt_entry;				/* Subsequent entries in section */
+} Elf32_gptab;
+
+/* Entry found in sections of type SHT_MIPS_REGINFO.  */
+
+typedef struct
+{
+  Elf32_Word	ri_gprmask;		/* General registers used */
+  Elf32_Word	ri_cprmask[4];		/* Coprocessor registers used */
+  Elf32_Sword	ri_gp_value;		/* $gp register value */
+} Elf32_RegInfo;
+
+/* Entries found in sections of type SHT_MIPS_OPTIONS.  */
+
+typedef struct
+{
+  unsigned char kind;		/* Determines interpretation of the
+				   variable part of descriptor.  */
+  unsigned char size;		/* Size of descriptor, including header.  */
+  Elf32_Section section;	/* Section header index of section affected,
+				   0 for global options.  */
+  Elf32_Word info;		/* Kind-specific information.  */
+} Elf_Options;
+
+/* Values for `kind' field in Elf_Options.  */
+
+#define ODK_NULL	0	/* Undefined.  */
+#define ODK_REGINFO	1	/* Register usage information.  */
+#define ODK_EXCEPTIONS	2	/* Exception processing options.  */
+#define ODK_PAD		3	/* Section padding options.  */
+#define ODK_HWPATCH	4	/* Hardware workarounds performed */
+#define ODK_FILL	5	/* record the fill value used by the linker. */
+#define ODK_TAGS	6	/* reserve space for desktop tools to write. */
+#define ODK_HWAND	7	/* HW workarounds.  'AND' bits when merging. */
+#define ODK_HWOR	8	/* HW workarounds.  'OR' bits when merging.  */
+
+/* Values for `info' in Elf_Options for ODK_EXCEPTIONS entries.  */
+
+#define OEX_FPU_MIN	0x1f	/* FPE's which MUST be enabled.  */
+#define OEX_FPU_MAX	0x1f00	/* FPE's which MAY be enabled.  */
+#define OEX_PAGE0	0x10000	/* page zero must be mapped.  */
+#define OEX_SMM		0x20000	/* Force sequential memory mode?  */
+#define OEX_FPDBUG	0x40000	/* Force floating point debug mode?  */
+#define OEX_PRECISEFP	OEX_FPDBUG
+#define OEX_DISMISS	0x80000	/* Dismiss invalid address faults?  */
+
+#define OEX_FPU_INVAL	0x10
+#define OEX_FPU_DIV0	0x08
+#define OEX_FPU_OFLO	0x04
+#define OEX_FPU_UFLO	0x02
+#define OEX_FPU_INEX	0x01
+
+/* Masks for `info' in Elf_Options for an ODK_HWPATCH entry.  */
+
+#define OHW_R4KEOP	0x1	/* R4000 end-of-page patch.  */
+#define OHW_R8KPFETCH	0x2	/* may need R8000 prefetch patch.  */
+#define OHW_R5KEOP	0x4	/* R5000 end-of-page patch.  */
+#define OHW_R5KCVTL	0x8	/* R5000 cvt.[ds].l bug.  clean=1.  */
+
+#define OPAD_PREFIX	0x1
+#define OPAD_POSTFIX	0x2
+#define OPAD_SYMBOL	0x4
+
+/* Entry found in `.options' section.  */
+
+typedef struct
+{
+  Elf32_Word hwp_flags1;	/* Extra flags.  */
+  Elf32_Word hwp_flags2;	/* Extra flags.  */
+} Elf_Options_Hw;
+
+/* Masks for `info' in ElfOptions for ODK_HWAND and ODK_HWOR entries.  */
+
+#define OHWA0_R4KEOP_CHECKED	0x00000001
+#define OHWA1_R4KEOP_CLEAN	0x00000002
+
+/* MIPS relocs.  */
+
+#define R_MIPS_NONE		0	/* No reloc */
+#define R_MIPS_16		1	/* Direct 16 bit */
+#define R_MIPS_32		2	/* Direct 32 bit */
+#define R_MIPS_REL32		3	/* PC relative 32 bit */
+#define R_MIPS_26		4	/* Direct 26 bit shifted */
+#define R_MIPS_HI16		5	/* High 16 bit */
+#define R_MIPS_LO16		6	/* Low 16 bit */
+#define R_MIPS_GPREL16		7	/* GP relative 16 bit */
+#define R_MIPS_LITERAL		8	/* 16 bit literal entry */
+#define R_MIPS_GOT16		9	/* 16 bit GOT entry */
+#define R_MIPS_PC16		10	/* PC relative 16 bit */
+#define R_MIPS_CALL16		11	/* 16 bit GOT entry for function */
+#define R_MIPS_GPREL32		12	/* GP relative 32 bit */
+
+#define R_MIPS_SHIFT5		16
+#define R_MIPS_SHIFT6		17
+#define R_MIPS_64		18
+#define R_MIPS_GOT_DISP		19
+#define R_MIPS_GOT_PAGE		20
+#define R_MIPS_GOT_OFST		21
+#define R_MIPS_GOT_HI16		22
+#define R_MIPS_GOT_LO16		23
+#define R_MIPS_SUB		24
+#define R_MIPS_INSERT_A		25
+#define R_MIPS_INSERT_B		26
+#define R_MIPS_DELETE		27
+#define R_MIPS_HIGHER		28
+#define R_MIPS_HIGHEST		29
+#define R_MIPS_CALL_HI16	30
+#define R_MIPS_CALL_LO16	31
+#define R_MIPS_SCN_DISP		32
+#define R_MIPS_REL16		33
+#define R_MIPS_ADD_IMMEDIATE	34
+#define R_MIPS_PJUMP		35
+#define R_MIPS_RELGOT		36
+#define R_MIPS_JALR		37
+#define R_MIPS_TLS_DTPMOD32	38	/* Module number 32 bit */
+#define R_MIPS_TLS_DTPREL32	39	/* Module-relative offset 32 bit */
+#define R_MIPS_TLS_DTPMOD64	40	/* Module number 64 bit */
+#define R_MIPS_TLS_DTPREL64	41	/* Module-relative offset 64 bit */
+#define R_MIPS_TLS_GD		42	/* 16 bit GOT offset for GD */
+#define R_MIPS_TLS_LDM		43	/* 16 bit GOT offset for LDM */
+#define R_MIPS_TLS_DTPREL_HI16	44	/* Module-relative offset, high 16 bits */
+#define R_MIPS_TLS_DTPREL_LO16	45	/* Module-relative offset, low 16 bits */
+#define R_MIPS_TLS_GOTTPREL	46	/* 16 bit GOT offset for IE */
+#define R_MIPS_TLS_TPREL32	47	/* TP-relative offset, 32 bit */
+#define R_MIPS_TLS_TPREL64	48	/* TP-relative offset, 64 bit */
+#define R_MIPS_TLS_TPREL_HI16	49	/* TP-relative offset, high 16 bits */
+#define R_MIPS_TLS_TPREL_LO16	50	/* TP-relative offset, low 16 bits */
+#define R_MIPS_GLOB_DAT		51
+/* Keep this the last entry.  */
+#define R_MIPS_NUM		52
+
+/* Legal values for p_type field of Elf32_Phdr.  */
+
+#define PT_MIPS_REGINFO	0x70000000	/* Register usage information */
+#define PT_MIPS_RTPROC  0x70000001	/* Runtime procedure table. */
+#define PT_MIPS_OPTIONS 0x70000002
+
+/* Special program header types.  */
+
+#define PF_MIPS_LOCAL	0x10000000
+
+/* Legal values for d_tag field of Elf32_Dyn.  */
+
+#define DT_MIPS_RLD_VERSION  0x70000001	/* Runtime linker interface version */
+#define DT_MIPS_TIME_STAMP   0x70000002	/* Timestamp */
+#define DT_MIPS_ICHECKSUM    0x70000003	/* Checksum */
+#define DT_MIPS_IVERSION     0x70000004	/* Version string (string tbl index) */
+#define DT_MIPS_FLAGS	     0x70000005	/* Flags */
+#define DT_MIPS_BASE_ADDRESS 0x70000006	/* Base address */
+#define DT_MIPS_MSYM	     0x70000007
+#define DT_MIPS_CONFLICT     0x70000008	/* Address of CONFLICT section */
+#define DT_MIPS_LIBLIST	     0x70000009	/* Address of LIBLIST section */
+#define DT_MIPS_LOCAL_GOTNO  0x7000000a	/* Number of local GOT entries */
+#define DT_MIPS_CONFLICTNO   0x7000000b	/* Number of CONFLICT entries */
+#define DT_MIPS_LIBLISTNO    0x70000010	/* Number of LIBLIST entries */
+#define DT_MIPS_SYMTABNO     0x70000011	/* Number of DYNSYM entries */
+#define DT_MIPS_UNREFEXTNO   0x70000012	/* First external DYNSYM */
+#define DT_MIPS_GOTSYM	     0x70000013	/* First GOT entry in DYNSYM */
+#define DT_MIPS_HIPAGENO     0x70000014	/* Number of GOT page table entries */
+#define DT_MIPS_RLD_MAP	     0x70000016	/* Address of run time loader map.  */
+#define DT_MIPS_DELTA_CLASS  0x70000017	/* Delta C++ class definition.  */
+#define DT_MIPS_DELTA_CLASS_NO    0x70000018 /* Number of entries in
+						DT_MIPS_DELTA_CLASS.  */
+#define DT_MIPS_DELTA_INSTANCE    0x70000019 /* Delta C++ class instances.  */
+#define DT_MIPS_DELTA_INSTANCE_NO 0x7000001a /* Number of entries in
+						DT_MIPS_DELTA_INSTANCE.  */
+#define DT_MIPS_DELTA_RELOC  0x7000001b /* Delta relocations.  */
+#define DT_MIPS_DELTA_RELOC_NO 0x7000001c /* Number of entries in
+					     DT_MIPS_DELTA_RELOC.  */
+#define DT_MIPS_DELTA_SYM    0x7000001d /* Delta symbols that Delta
+					   relocations refer to.  */
+#define DT_MIPS_DELTA_SYM_NO 0x7000001e /* Number of entries in
+					   DT_MIPS_DELTA_SYM.  */
+#define DT_MIPS_DELTA_CLASSSYM 0x70000020 /* Delta symbols that hold the
+					     class declaration.  */
+#define DT_MIPS_DELTA_CLASSSYM_NO 0x70000021 /* Number of entries in
+						DT_MIPS_DELTA_CLASSSYM.  */
+#define DT_MIPS_CXX_FLAGS    0x70000022 /* Flags indicating for C++ flavor.  */
+#define DT_MIPS_PIXIE_INIT   0x70000023
+#define DT_MIPS_SYMBOL_LIB   0x70000024
+#define DT_MIPS_LOCALPAGE_GOTIDX 0x70000025
+#define DT_MIPS_LOCAL_GOTIDX 0x70000026
+#define DT_MIPS_HIDDEN_GOTIDX 0x70000027
+#define DT_MIPS_PROTECTED_GOTIDX 0x70000028
+#define DT_MIPS_OPTIONS	     0x70000029 /* Address of .options.  */
+#define DT_MIPS_INTERFACE    0x7000002a /* Address of .interface.  */
+#define DT_MIPS_DYNSTR_ALIGN 0x7000002b
+#define DT_MIPS_INTERFACE_SIZE 0x7000002c /* Size of the .interface section. */
+#define DT_MIPS_RLD_TEXT_RESOLVE_ADDR 0x7000002d /* Address of rld_text_rsolve
+						    function stored in GOT.  */
+#define DT_MIPS_PERF_SUFFIX  0x7000002e /* Default suffix of dso to be added
+					   by rld on dlopen() calls.  */
+#define DT_MIPS_COMPACT_SIZE 0x7000002f /* (O32)Size of compact rel section. */
+#define DT_MIPS_GP_VALUE     0x70000030 /* GP value for aux GOTs.  */
+#define DT_MIPS_AUX_DYNAMIC  0x70000031 /* Address of aux .dynamic.  */
+#define DT_MIPS_NUM	     0x32
+
+/* Legal values for DT_MIPS_FLAGS Elf32_Dyn entry.  */
+
+#define RHF_NONE		   0		/* No flags */
+#define RHF_QUICKSTART		   (1 << 0)	/* Use quickstart */
+#define RHF_NOTPOT		   (1 << 1)	/* Hash size not power of 2 */
+#define RHF_NO_LIBRARY_REPLACEMENT (1 << 2)	/* Ignore LD_LIBRARY_PATH */
+#define RHF_NO_MOVE		   (1 << 3)
+#define RHF_SGI_ONLY		   (1 << 4)
+#define RHF_GUARANTEE_INIT	   (1 << 5)
+#define RHF_DELTA_C_PLUS_PLUS	   (1 << 6)
+#define RHF_GUARANTEE_START_INIT   (1 << 7)
+#define RHF_PIXIE		   (1 << 8)
+#define RHF_DEFAULT_DELAY_LOAD	   (1 << 9)
+#define RHF_REQUICKSTART	   (1 << 10)
+#define RHF_REQUICKSTARTED	   (1 << 11)
+#define RHF_CORD		   (1 << 12)
+#define RHF_NO_UNRES_UNDEF	   (1 << 13)
+#define RHF_RLD_ORDER_SAFE	   (1 << 14)
+
+/* Entries found in sections of type SHT_MIPS_LIBLIST.  */
+
+typedef struct
+{
+  Elf32_Word l_name;		/* Name (string table index) */
+  Elf32_Word l_time_stamp;	/* Timestamp */
+  Elf32_Word l_checksum;	/* Checksum */
+  Elf32_Word l_version;		/* Interface version */
+  Elf32_Word l_flags;		/* Flags */
+} Elf32_Lib;
+
+typedef struct
+{
+  Elf64_Word l_name;		/* Name (string table index) */
+  Elf64_Word l_time_stamp;	/* Timestamp */
+  Elf64_Word l_checksum;	/* Checksum */
+  Elf64_Word l_version;		/* Interface version */
+  Elf64_Word l_flags;		/* Flags */
+} Elf64_Lib;
+
+
+/* Legal values for l_flags.  */
+
+#define LL_NONE		  0
+#define LL_EXACT_MATCH	  (1 << 0)	/* Require exact match */
+#define LL_IGNORE_INT_VER (1 << 1)	/* Ignore interface version */
+#define LL_REQUIRE_MINOR  (1 << 2)
+#define LL_EXPORTS	  (1 << 3)
+#define LL_DELAY_LOAD	  (1 << 4)
+#define LL_DELTA	  (1 << 5)
+
+/* Entries found in sections of type SHT_MIPS_CONFLICT.  */
+
+typedef Elf32_Addr Elf32_Conflict;
+
+
+/* HPPA specific definitions.  */
+
+/* Legal values for e_flags field of Elf32_Ehdr.  */
+
+#define EF_PARISC_TRAPNIL	0x00010000 /* Trap nil pointer dereference.  */
+#define EF_PARISC_EXT		0x00020000 /* Program uses arch. extensions. */
+#define EF_PARISC_LSB		0x00040000 /* Program expects little endian. */
+#define EF_PARISC_WIDE		0x00080000 /* Program expects wide mode.  */
+#define EF_PARISC_NO_KABP	0x00100000 /* No kernel assisted branch
+					      prediction.  */
+#define EF_PARISC_LAZYSWAP	0x00400000 /* Allow lazy swapping.  */
+#define EF_PARISC_ARCH		0x0000ffff /* Architecture version.  */
+
+/* Defined values for `e_flags & EF_PARISC_ARCH' are:  */
+
+#define EFA_PARISC_1_0		    0x020b /* PA-RISC 1.0 big-endian.  */
+#define EFA_PARISC_1_1		    0x0210 /* PA-RISC 1.1 big-endian.  */
+#define EFA_PARISC_2_0		    0x0214 /* PA-RISC 2.0 big-endian.  */
+
+/* Additional section indeces.  */
+
+#define SHN_PARISC_ANSI_COMMON	0xff00	   /* Section for tenatively declared
+					      symbols in ANSI C.  */
+#define SHN_PARISC_HUGE_COMMON	0xff01	   /* Common blocks in huge model.  */
+
+/* Legal values for sh_type field of Elf32_Shdr.  */
+
+#define SHT_PARISC_EXT		0x70000000 /* Contains product specific ext. */
+#define SHT_PARISC_UNWIND	0x70000001 /* Unwind information.  */
+#define SHT_PARISC_DOC		0x70000002 /* Debug info for optimized code. */
+
+/* Legal values for sh_flags field of Elf32_Shdr.  */
+
+#define SHF_PARISC_SHORT	0x20000000 /* Section with short addressing. */
+#define SHF_PARISC_HUGE		0x40000000 /* Section far from gp.  */
+#define SHF_PARISC_SBP		0x80000000 /* Static branch prediction code. */
+
+/* Legal values for ST_TYPE subfield of st_info (symbol type).  */
+
+#define STT_PARISC_MILLICODE	13	/* Millicode function entry point.  */
+
+#define STT_HP_OPAQUE		(STT_LOOS + 0x1)
+#define STT_HP_STUB		(STT_LOOS + 0x2)
+
+/* HPPA relocs.  */
+
+#define R_PARISC_NONE		0	/* No reloc.  */
+#define R_PARISC_DIR32		1	/* Direct 32-bit reference.  */
+#define R_PARISC_DIR21L		2	/* Left 21 bits of eff. address.  */
+#define R_PARISC_DIR17R		3	/* Right 17 bits of eff. address.  */
+#define R_PARISC_DIR17F		4	/* 17 bits of eff. address.  */
+#define R_PARISC_DIR14R		6	/* Right 14 bits of eff. address.  */
+#define R_PARISC_PCREL32	9	/* 32-bit rel. address.  */
+#define R_PARISC_PCREL21L	10	/* Left 21 bits of rel. address.  */
+#define R_PARISC_PCREL17R	11	/* Right 17 bits of rel. address.  */
+#define R_PARISC_PCREL17F	12	/* 17 bits of rel. address.  */
+#define R_PARISC_PCREL14R	14	/* Right 14 bits of rel. address.  */
+#define R_PARISC_DPREL21L	18	/* Left 21 bits of rel. address.  */
+#define R_PARISC_DPREL14R	22	/* Right 14 bits of rel. address.  */
+#define R_PARISC_GPREL21L	26	/* GP-relative, left 21 bits.  */
+#define R_PARISC_GPREL14R	30	/* GP-relative, right 14 bits.  */
+#define R_PARISC_LTOFF21L	34	/* LT-relative, left 21 bits.  */
+#define R_PARISC_LTOFF14R	38	/* LT-relative, right 14 bits.  */
+#define R_PARISC_SECREL32	41	/* 32 bits section rel. address.  */
+#define R_PARISC_SEGBASE	48	/* No relocation, set segment base.  */
+#define R_PARISC_SEGREL32	49	/* 32 bits segment rel. address.  */
+#define R_PARISC_PLTOFF21L	50	/* PLT rel. address, left 21 bits.  */
+#define R_PARISC_PLTOFF14R	54	/* PLT rel. address, right 14 bits.  */
+#define R_PARISC_LTOFF_FPTR32	57	/* 32 bits LT-rel. function pointer. */
+#define R_PARISC_LTOFF_FPTR21L	58	/* LT-rel. fct ptr, left 21 bits. */
+#define R_PARISC_LTOFF_FPTR14R	62	/* LT-rel. fct ptr, right 14 bits. */
+#define R_PARISC_FPTR64		64	/* 64 bits function address.  */
+#define R_PARISC_PLABEL32	65	/* 32 bits function address.  */
+#define R_PARISC_PLABEL21L	66	/* Left 21 bits of fdesc address.  */
+#define R_PARISC_PLABEL14R	70	/* Right 14 bits of fdesc address.  */
+#define R_PARISC_PCREL64	72	/* 64 bits PC-rel. address.  */
+#define R_PARISC_PCREL22F	74	/* 22 bits PC-rel. address.  */
+#define R_PARISC_PCREL14WR	75	/* PC-rel. address, right 14 bits.  */
+#define R_PARISC_PCREL14DR	76	/* PC rel. address, right 14 bits.  */
+#define R_PARISC_PCREL16F	77	/* 16 bits PC-rel. address.  */
+#define R_PARISC_PCREL16WF	78	/* 16 bits PC-rel. address.  */
+#define R_PARISC_PCREL16DF	79	/* 16 bits PC-rel. address.  */
+#define R_PARISC_DIR64		80	/* 64 bits of eff. address.  */
+#define R_PARISC_DIR14WR	83	/* 14 bits of eff. address.  */
+#define R_PARISC_DIR14DR	84	/* 14 bits of eff. address.  */
+#define R_PARISC_DIR16F		85	/* 16 bits of eff. address.  */
+#define R_PARISC_DIR16WF	86	/* 16 bits of eff. address.  */
+#define R_PARISC_DIR16DF	87	/* 16 bits of eff. address.  */
+#define R_PARISC_GPREL64	88	/* 64 bits of GP-rel. address.  */
+#define R_PARISC_GPREL14WR	91	/* GP-rel. address, right 14 bits.  */
+#define R_PARISC_GPREL14DR	92	/* GP-rel. address, right 14 bits.  */
+#define R_PARISC_GPREL16F	93	/* 16 bits GP-rel. address.  */
+#define R_PARISC_GPREL16WF	94	/* 16 bits GP-rel. address.  */
+#define R_PARISC_GPREL16DF	95	/* 16 bits GP-rel. address.  */
+#define R_PARISC_LTOFF64	96	/* 64 bits LT-rel. address.  */
+#define R_PARISC_LTOFF14WR	99	/* LT-rel. address, right 14 bits.  */
+#define R_PARISC_LTOFF14DR	100	/* LT-rel. address, right 14 bits.  */
+#define R_PARISC_LTOFF16F	101	/* 16 bits LT-rel. address.  */
+#define R_PARISC_LTOFF16WF	102	/* 16 bits LT-rel. address.  */
+#define R_PARISC_LTOFF16DF	103	/* 16 bits LT-rel. address.  */
+#define R_PARISC_SECREL64	104	/* 64 bits section rel. address.  */
+#define R_PARISC_SEGREL64	112	/* 64 bits segment rel. address.  */
+#define R_PARISC_PLTOFF14WR	115	/* PLT-rel. address, right 14 bits.  */
+#define R_PARISC_PLTOFF14DR	116	/* PLT-rel. address, right 14 bits.  */
+#define R_PARISC_PLTOFF16F	117	/* 16 bits LT-rel. address.  */
+#define R_PARISC_PLTOFF16WF	118	/* 16 bits PLT-rel. address.  */
+#define R_PARISC_PLTOFF16DF	119	/* 16 bits PLT-rel. address.  */
+#define R_PARISC_LTOFF_FPTR64	120	/* 64 bits LT-rel. function ptr.  */
+#define R_PARISC_LTOFF_FPTR14WR	123	/* LT-rel. fct. ptr., right 14 bits. */
+#define R_PARISC_LTOFF_FPTR14DR	124	/* LT-rel. fct. ptr., right 14 bits. */
+#define R_PARISC_LTOFF_FPTR16F	125	/* 16 bits LT-rel. function ptr.  */
+#define R_PARISC_LTOFF_FPTR16WF	126	/* 16 bits LT-rel. function ptr.  */
+#define R_PARISC_LTOFF_FPTR16DF	127	/* 16 bits LT-rel. function ptr.  */
+#define R_PARISC_LORESERVE	128
+#define R_PARISC_COPY		128	/* Copy relocation.  */
+#define R_PARISC_IPLT		129	/* Dynamic reloc, imported PLT */
+#define R_PARISC_EPLT		130	/* Dynamic reloc, exported PLT */
+#define R_PARISC_TPREL32	153	/* 32 bits TP-rel. address.  */
+#define R_PARISC_TPREL21L	154	/* TP-rel. address, left 21 bits.  */
+#define R_PARISC_TPREL14R	158	/* TP-rel. address, right 14 bits.  */
+#define R_PARISC_LTOFF_TP21L	162	/* LT-TP-rel. address, left 21 bits. */
+#define R_PARISC_LTOFF_TP14R	166	/* LT-TP-rel. address, right 14 bits.*/
+#define R_PARISC_LTOFF_TP14F	167	/* 14 bits LT-TP-rel. address.  */
+#define R_PARISC_TPREL64	216	/* 64 bits TP-rel. address.  */
+#define R_PARISC_TPREL14WR	219	/* TP-rel. address, right 14 bits.  */
+#define R_PARISC_TPREL14DR	220	/* TP-rel. address, right 14 bits.  */
+#define R_PARISC_TPREL16F	221	/* 16 bits TP-rel. address.  */
+#define R_PARISC_TPREL16WF	222	/* 16 bits TP-rel. address.  */
+#define R_PARISC_TPREL16DF	223	/* 16 bits TP-rel. address.  */
+#define R_PARISC_LTOFF_TP64	224	/* 64 bits LT-TP-rel. address.  */
+#define R_PARISC_LTOFF_TP14WR	227	/* LT-TP-rel. address, right 14 bits.*/
+#define R_PARISC_LTOFF_TP14DR	228	/* LT-TP-rel. address, right 14 bits.*/
+#define R_PARISC_LTOFF_TP16F	229	/* 16 bits LT-TP-rel. address.  */
+#define R_PARISC_LTOFF_TP16WF	230	/* 16 bits LT-TP-rel. address.  */
+#define R_PARISC_LTOFF_TP16DF	231	/* 16 bits LT-TP-rel. address.  */
+#define R_PARISC_GNU_VTENTRY	232
+#define R_PARISC_GNU_VTINHERIT	233
+#define R_PARISC_TLS_GD21L	234	/* GD 21-bit left.  */
+#define R_PARISC_TLS_GD14R	235	/* GD 14-bit right.  */
+#define R_PARISC_TLS_GDCALL	236	/* GD call to __t_g_a.  */
+#define R_PARISC_TLS_LDM21L	237	/* LD module 21-bit left.  */
+#define R_PARISC_TLS_LDM14R	238	/* LD module 14-bit right.  */
+#define R_PARISC_TLS_LDMCALL	239	/* LD module call to __t_g_a.  */
+#define R_PARISC_TLS_LDO21L	240	/* LD offset 21-bit left.  */
+#define R_PARISC_TLS_LDO14R	241	/* LD offset 14-bit right.  */
+#define R_PARISC_TLS_DTPMOD32	242	/* DTP module 32-bit.  */
+#define R_PARISC_TLS_DTPMOD64	243	/* DTP module 64-bit.  */
+#define R_PARISC_TLS_DTPOFF32	244	/* DTP offset 32-bit.  */
+#define R_PARISC_TLS_DTPOFF64	245	/* DTP offset 32-bit.  */
+#define R_PARISC_TLS_LE21L	R_PARISC_TPREL21L
+#define R_PARISC_TLS_LE14R	R_PARISC_TPREL14R
+#define R_PARISC_TLS_IE21L	R_PARISC_LTOFF_TP21L
+#define R_PARISC_TLS_IE14R	R_PARISC_LTOFF_TP14R
+#define R_PARISC_TLS_TPREL32	R_PARISC_TPREL32
+#define R_PARISC_TLS_TPREL64	R_PARISC_TPREL64
+#define R_PARISC_HIRESERVE	255
+
+/* Legal values for p_type field of Elf32_Phdr/Elf64_Phdr.  */
+
+#define PT_HP_TLS		(PT_LOOS + 0x0)
+#define PT_HP_CORE_NONE		(PT_LOOS + 0x1)
+#define PT_HP_CORE_VERSION	(PT_LOOS + 0x2)
+#define PT_HP_CORE_KERNEL	(PT_LOOS + 0x3)
+#define PT_HP_CORE_COMM		(PT_LOOS + 0x4)
+#define PT_HP_CORE_PROC		(PT_LOOS + 0x5)
+#define PT_HP_CORE_LOADABLE	(PT_LOOS + 0x6)
+#define PT_HP_CORE_STACK	(PT_LOOS + 0x7)
+#define PT_HP_CORE_SHM		(PT_LOOS + 0x8)
+#define PT_HP_CORE_MMF		(PT_LOOS + 0x9)
+#define PT_HP_PARALLEL		(PT_LOOS + 0x10)
+#define PT_HP_FASTBIND		(PT_LOOS + 0x11)
+#define PT_HP_OPT_ANNOT		(PT_LOOS + 0x12)
+#define PT_HP_HSL_ANNOT		(PT_LOOS + 0x13)
+#define PT_HP_STACK		(PT_LOOS + 0x14)
+
+#define PT_PARISC_ARCHEXT	0x70000000
+#define PT_PARISC_UNWIND	0x70000001
+
+/* Legal values for p_flags field of Elf32_Phdr/Elf64_Phdr.  */
+
+#define PF_PARISC_SBP		0x08000000
+
+#define PF_HP_PAGE_SIZE		0x00100000
+#define PF_HP_FAR_SHARED	0x00200000
+#define PF_HP_NEAR_SHARED	0x00400000
+#define PF_HP_CODE		0x01000000
+#define PF_HP_MODIFY		0x02000000
+#define PF_HP_LAZYSWAP		0x04000000
+#define PF_HP_SBP		0x08000000
+
+
+/* Alpha specific definitions.  */
+
+/* Legal values for e_flags field of Elf64_Ehdr.  */
+
+#define EF_ALPHA_32BIT		1	/* All addresses must be < 2GB.  */
+#define EF_ALPHA_CANRELAX	2	/* Relocations for relaxing exist.  */
+
+/* Legal values for sh_type field of Elf64_Shdr.  */
+
+/* These two are primerily concerned with ECOFF debugging info.  */
+#define SHT_ALPHA_DEBUG		0x70000001
+#define SHT_ALPHA_REGINFO	0x70000002
+
+/* Legal values for sh_flags field of Elf64_Shdr.  */
+
+#define SHF_ALPHA_GPREL		0x10000000
+
+/* Legal values for st_other field of Elf64_Sym.  */
+#define STO_ALPHA_NOPV		0x80	/* No PV required.  */
+#define STO_ALPHA_STD_GPLOAD	0x88	/* PV only used for initial ldgp.  */
+
+/* Alpha relocs.  */
+
+#define R_ALPHA_NONE		0	/* No reloc */
+#define R_ALPHA_REFLONG		1	/* Direct 32 bit */
+#define R_ALPHA_REFQUAD		2	/* Direct 64 bit */
+#define R_ALPHA_GPREL32		3	/* GP relative 32 bit */
+#define R_ALPHA_LITERAL		4	/* GP relative 16 bit w/optimization */
+#define R_ALPHA_LITUSE		5	/* Optimization hint for LITERAL */
+#define R_ALPHA_GPDISP		6	/* Add displacement to GP */
+#define R_ALPHA_BRADDR		7	/* PC+4 relative 23 bit shifted */
+#define R_ALPHA_HINT		8	/* PC+4 relative 16 bit shifted */
+#define R_ALPHA_SREL16		9	/* PC relative 16 bit */
+#define R_ALPHA_SREL32		10	/* PC relative 32 bit */
+#define R_ALPHA_SREL64		11	/* PC relative 64 bit */
+#define R_ALPHA_GPRELHIGH	17	/* GP relative 32 bit, high 16 bits */
+#define R_ALPHA_GPRELLOW	18	/* GP relative 32 bit, low 16 bits */
+#define R_ALPHA_GPREL16		19	/* GP relative 16 bit */
+#define R_ALPHA_COPY		24	/* Copy symbol at runtime */
+#define R_ALPHA_GLOB_DAT	25	/* Create GOT entry */
+#define R_ALPHA_JMP_SLOT	26	/* Create PLT entry */
+#define R_ALPHA_RELATIVE	27	/* Adjust by program base */
+#define R_ALPHA_TLS_GD_HI	28
+#define R_ALPHA_TLSGD		29
+#define R_ALPHA_TLS_LDM		30
+#define R_ALPHA_DTPMOD64	31
+#define R_ALPHA_GOTDTPREL	32
+#define R_ALPHA_DTPREL64	33
+#define R_ALPHA_DTPRELHI	34
+#define R_ALPHA_DTPRELLO	35
+#define R_ALPHA_DTPREL16	36
+#define R_ALPHA_GOTTPREL	37
+#define R_ALPHA_TPREL64		38
+#define R_ALPHA_TPRELHI		39
+#define R_ALPHA_TPRELLO		40
+#define R_ALPHA_TPREL16		41
+/* Keep this the last entry.  */
+#define R_ALPHA_NUM		46
+
+/* Magic values of the LITUSE relocation addend.  */
+#define LITUSE_ALPHA_ADDR	0
+#define LITUSE_ALPHA_BASE	1
+#define LITUSE_ALPHA_BYTOFF	2
+#define LITUSE_ALPHA_JSR	3
+#define LITUSE_ALPHA_TLS_GD	4
+#define LITUSE_ALPHA_TLS_LDM	5
+
+/* Legal values for d_tag of Elf64_Dyn.  */
+#define DT_ALPHA_PLTRO		(DT_LOPROC + 0)
+#define DT_ALPHA_NUM		1
+
+/* PowerPC specific declarations */
+
+/* Values for Elf32/64_Ehdr.e_flags.  */
+#define EF_PPC_EMB		0x80000000	/* PowerPC embedded flag */
+
+/* Cygnus local bits below */
+#define EF_PPC_RELOCATABLE	0x00010000	/* PowerPC -mrelocatable flag*/
+#define EF_PPC_RELOCATABLE_LIB	0x00008000	/* PowerPC -mrelocatable-lib
+						   flag */
+
+/* PowerPC relocations defined by the ABIs */
+#define R_PPC_NONE		0
+#define R_PPC_ADDR32		1	/* 32bit absolute address */
+#define R_PPC_ADDR24		2	/* 26bit address, 2 bits ignored.  */
+#define R_PPC_ADDR16		3	/* 16bit absolute address */
+#define R_PPC_ADDR16_LO		4	/* lower 16bit of absolute address */
+#define R_PPC_ADDR16_HI		5	/* high 16bit of absolute address */
+#define R_PPC_ADDR16_HA		6	/* adjusted high 16bit */
+#define R_PPC_ADDR14		7	/* 16bit address, 2 bits ignored */
+#define R_PPC_ADDR14_BRTAKEN	8
+#define R_PPC_ADDR14_BRNTAKEN	9
+#define R_PPC_REL24		10	/* PC relative 26 bit */
+#define R_PPC_REL14		11	/* PC relative 16 bit */
+#define R_PPC_REL14_BRTAKEN	12
+#define R_PPC_REL14_BRNTAKEN	13
+#define R_PPC_GOT16		14
+#define R_PPC_GOT16_LO		15
+#define R_PPC_GOT16_HI		16
+#define R_PPC_GOT16_HA		17
+#define R_PPC_PLTREL24		18
+#define R_PPC_COPY		19
+#define R_PPC_GLOB_DAT		20
+#define R_PPC_JMP_SLOT		21
+#define R_PPC_RELATIVE		22
+#define R_PPC_LOCAL24PC		23
+#define R_PPC_UADDR32		24
+#define R_PPC_UADDR16		25
+#define R_PPC_REL32		26
+#define R_PPC_PLT32		27
+#define R_PPC_PLTREL32		28
+#define R_PPC_PLT16_LO		29
+#define R_PPC_PLT16_HI		30
+#define R_PPC_PLT16_HA		31
+#define R_PPC_SDAREL16		32
+#define R_PPC_SECTOFF		33
+#define R_PPC_SECTOFF_LO	34
+#define R_PPC_SECTOFF_HI	35
+#define R_PPC_SECTOFF_HA	36
+
+/* PowerPC relocations defined for the TLS access ABI.  */
+#define R_PPC_TLS		67 /* none	(sym+add)@tls */
+#define R_PPC_DTPMOD32		68 /* word32	(sym+add)@dtpmod */
+#define R_PPC_TPREL16		69 /* half16*	(sym+add)@tprel */
+#define R_PPC_TPREL16_LO	70 /* half16	(sym+add)@tprel@l */
+#define R_PPC_TPREL16_HI	71 /* half16	(sym+add)@tprel@h */
+#define R_PPC_TPREL16_HA	72 /* half16	(sym+add)@tprel@ha */
+#define R_PPC_TPREL32		73 /* word32	(sym+add)@tprel */
+#define R_PPC_DTPREL16		74 /* half16*	(sym+add)@dtprel */
+#define R_PPC_DTPREL16_LO	75 /* half16	(sym+add)@dtprel@l */
+#define R_PPC_DTPREL16_HI	76 /* half16	(sym+add)@dtprel@h */
+#define R_PPC_DTPREL16_HA	77 /* half16	(sym+add)@dtprel@ha */
+#define R_PPC_DTPREL32		78 /* word32	(sym+add)@dtprel */
+#define R_PPC_GOT_TLSGD16	79 /* half16*	(sym+add)@got@tlsgd */
+#define R_PPC_GOT_TLSGD16_LO	80 /* half16	(sym+add)@got@tlsgd@l */
+#define R_PPC_GOT_TLSGD16_HI	81 /* half16	(sym+add)@got@tlsgd@h */
+#define R_PPC_GOT_TLSGD16_HA	82 /* half16	(sym+add)@got@tlsgd@ha */
+#define R_PPC_GOT_TLSLD16	83 /* half16*	(sym+add)@got@tlsld */
+#define R_PPC_GOT_TLSLD16_LO	84 /* half16	(sym+add)@got@tlsld@l */
+#define R_PPC_GOT_TLSLD16_HI	85 /* half16	(sym+add)@got@tlsld@h */
+#define R_PPC_GOT_TLSLD16_HA	86 /* half16	(sym+add)@got@tlsld@ha */
+#define R_PPC_GOT_TPREL16	87 /* half16*	(sym+add)@got@tprel */
+#define R_PPC_GOT_TPREL16_LO	88 /* half16	(sym+add)@got@tprel@l */
+#define R_PPC_GOT_TPREL16_HI	89 /* half16	(sym+add)@got@tprel@h */
+#define R_PPC_GOT_TPREL16_HA	90 /* half16	(sym+add)@got@tprel@ha */
+#define R_PPC_GOT_DTPREL16	91 /* half16*	(sym+add)@got@dtprel */
+#define R_PPC_GOT_DTPREL16_LO	92 /* half16*	(sym+add)@got@dtprel@l */
+#define R_PPC_GOT_DTPREL16_HI	93 /* half16*	(sym+add)@got@dtprel@h */
+#define R_PPC_GOT_DTPREL16_HA	94 /* half16*	(sym+add)@got@dtprel@ha */
+
+/* Keep this the last entry.  */
+#define R_PPC_NUM		95
+
+/* The remaining relocs are from the Embedded ELF ABI, and are not
+   in the SVR4 ELF ABI.  */
+#define R_PPC_EMB_NADDR32	101
+#define R_PPC_EMB_NADDR16	102
+#define R_PPC_EMB_NADDR16_LO	103
+#define R_PPC_EMB_NADDR16_HI	104
+#define R_PPC_EMB_NADDR16_HA	105
+#define R_PPC_EMB_SDAI16	106
+#define R_PPC_EMB_SDA2I16	107
+#define R_PPC_EMB_SDA2REL	108
+#define R_PPC_EMB_SDA21		109	/* 16 bit offset in SDA */
+#define R_PPC_EMB_MRKREF	110
+#define R_PPC_EMB_RELSEC16	111
+#define R_PPC_EMB_RELST_LO	112
+#define R_PPC_EMB_RELST_HI	113
+#define R_PPC_EMB_RELST_HA	114
+#define R_PPC_EMB_BIT_FLD	115
+#define R_PPC_EMB_RELSDA	116	/* 16 bit relative offset in SDA */
+
+/* Diab tool relocations.  */
+#define R_PPC_DIAB_SDA21_LO	180	/* like EMB_SDA21, but lower 16 bit */
+#define R_PPC_DIAB_SDA21_HI	181	/* like EMB_SDA21, but high 16 bit */
+#define R_PPC_DIAB_SDA21_HA	182	/* like EMB_SDA21, adjusted high 16 */
+#define R_PPC_DIAB_RELSDA_LO	183	/* like EMB_RELSDA, but lower 16 bit */
+#define R_PPC_DIAB_RELSDA_HI	184	/* like EMB_RELSDA, but high 16 bit */
+#define R_PPC_DIAB_RELSDA_HA	185	/* like EMB_RELSDA, adjusted high 16 */
+
+/* GNU relocs used in PIC code sequences.  */
+#define R_PPC_REL16		249	/* word32   (sym-.) */
+#define R_PPC_REL16_LO		250	/* half16   (sym-.)@l */
+#define R_PPC_REL16_HI		251	/* half16   (sym-.)@h */
+#define R_PPC_REL16_HA		252	/* half16   (sym-.)@ha */
+
+/* This is a phony reloc to handle any old fashioned TOC16 references
+   that may still be in object files.  */
+#define R_PPC_TOC16		255
+
+/* PowerPC specific values for the Dyn d_tag field.  */
+#define DT_PPC_GOT		(DT_LOPROC + 0)
+#define DT_PPC_NUM		1
+
+/* PowerPC64 relocations defined by the ABIs */
+#define R_PPC64_NONE		R_PPC_NONE
+#define R_PPC64_ADDR32		R_PPC_ADDR32 /* 32bit absolute address */
+#define R_PPC64_ADDR24		R_PPC_ADDR24 /* 26bit address, word aligned */
+#define R_PPC64_ADDR16		R_PPC_ADDR16 /* 16bit absolute address */
+#define R_PPC64_ADDR16_LO	R_PPC_ADDR16_LO	/* lower 16bits of address */
+#define R_PPC64_ADDR16_HI	R_PPC_ADDR16_HI	/* high 16bits of address. */
+#define R_PPC64_ADDR16_HA	R_PPC_ADDR16_HA /* adjusted high 16bits.  */
+#define R_PPC64_ADDR14		R_PPC_ADDR14 /* 16bit address, word aligned */
+#define R_PPC64_ADDR14_BRTAKEN	R_PPC_ADDR14_BRTAKEN
+#define R_PPC64_ADDR14_BRNTAKEN	R_PPC_ADDR14_BRNTAKEN
+#define R_PPC64_REL24		R_PPC_REL24 /* PC-rel. 26 bit, word aligned */
+#define R_PPC64_REL14		R_PPC_REL14 /* PC relative 16 bit */
+#define R_PPC64_REL14_BRTAKEN	R_PPC_REL14_BRTAKEN
+#define R_PPC64_REL14_BRNTAKEN	R_PPC_REL14_BRNTAKEN
+#define R_PPC64_GOT16		R_PPC_GOT16
+#define R_PPC64_GOT16_LO	R_PPC_GOT16_LO
+#define R_PPC64_GOT16_HI	R_PPC_GOT16_HI
+#define R_PPC64_GOT16_HA	R_PPC_GOT16_HA
+
+#define R_PPC64_COPY		R_PPC_COPY
+#define R_PPC64_GLOB_DAT	R_PPC_GLOB_DAT
+#define R_PPC64_JMP_SLOT	R_PPC_JMP_SLOT
+#define R_PPC64_RELATIVE	R_PPC_RELATIVE
+
+#define R_PPC64_UADDR32		R_PPC_UADDR32
+#define R_PPC64_UADDR16		R_PPC_UADDR16
+#define R_PPC64_REL32		R_PPC_REL32
+#define R_PPC64_PLT32		R_PPC_PLT32
+#define R_PPC64_PLTREL32	R_PPC_PLTREL32
+#define R_PPC64_PLT16_LO	R_PPC_PLT16_LO
+#define R_PPC64_PLT16_HI	R_PPC_PLT16_HI
+#define R_PPC64_PLT16_HA	R_PPC_PLT16_HA
+
+#define R_PPC64_SECTOFF		R_PPC_SECTOFF
+#define R_PPC64_SECTOFF_LO	R_PPC_SECTOFF_LO
+#define R_PPC64_SECTOFF_HI	R_PPC_SECTOFF_HI
+#define R_PPC64_SECTOFF_HA	R_PPC_SECTOFF_HA
+#define R_PPC64_ADDR30		37 /* word30 (S + A - P) >> 2 */
+#define R_PPC64_ADDR64		38 /* doubleword64 S + A */
+#define R_PPC64_ADDR16_HIGHER	39 /* half16 #higher(S + A) */
+#define R_PPC64_ADDR16_HIGHERA	40 /* half16 #highera(S + A) */
+#define R_PPC64_ADDR16_HIGHEST	41 /* half16 #highest(S + A) */
+#define R_PPC64_ADDR16_HIGHESTA	42 /* half16 #highesta(S + A) */
+#define R_PPC64_UADDR64		43 /* doubleword64 S + A */
+#define R_PPC64_REL64		44 /* doubleword64 S + A - P */
+#define R_PPC64_PLT64		45 /* doubleword64 L + A */
+#define R_PPC64_PLTREL64	46 /* doubleword64 L + A - P */
+#define R_PPC64_TOC16		47 /* half16* S + A - .TOC */
+#define R_PPC64_TOC16_LO	48 /* half16 #lo(S + A - .TOC.) */
+#define R_PPC64_TOC16_HI	49 /* half16 #hi(S + A - .TOC.) */
+#define R_PPC64_TOC16_HA	50 /* half16 #ha(S + A - .TOC.) */
+#define R_PPC64_TOC		51 /* doubleword64 .TOC */
+#define R_PPC64_PLTGOT16	52 /* half16* M + A */
+#define R_PPC64_PLTGOT16_LO	53 /* half16 #lo(M + A) */
+#define R_PPC64_PLTGOT16_HI	54 /* half16 #hi(M + A) */
+#define R_PPC64_PLTGOT16_HA	55 /* half16 #ha(M + A) */
+
+#define R_PPC64_ADDR16_DS	56 /* half16ds* (S + A) >> 2 */
+#define R_PPC64_ADDR16_LO_DS	57 /* half16ds  #lo(S + A) >> 2 */
+#define R_PPC64_GOT16_DS	58 /* half16ds* (G + A) >> 2 */
+#define R_PPC64_GOT16_LO_DS	59 /* half16ds  #lo(G + A) >> 2 */
+#define R_PPC64_PLT16_LO_DS	60 /* half16ds  #lo(L + A) >> 2 */
+#define R_PPC64_SECTOFF_DS	61 /* half16ds* (R + A) >> 2 */
+#define R_PPC64_SECTOFF_LO_DS	62 /* half16ds  #lo(R + A) >> 2 */
+#define R_PPC64_TOC16_DS	63 /* half16ds* (S + A - .TOC.) >> 2 */
+#define R_PPC64_TOC16_LO_DS	64 /* half16ds  #lo(S + A - .TOC.) >> 2 */
+#define R_PPC64_PLTGOT16_DS	65 /* half16ds* (M + A) >> 2 */
+#define R_PPC64_PLTGOT16_LO_DS	66 /* half16ds  #lo(M + A) >> 2 */
+
+/* PowerPC64 relocations defined for the TLS access ABI.  */
+#define R_PPC64_TLS		67 /* none	(sym+add)@tls */
+#define R_PPC64_DTPMOD64	68 /* doubleword64 (sym+add)@dtpmod */
+#define R_PPC64_TPREL16		69 /* half16*	(sym+add)@tprel */
+#define R_PPC64_TPREL16_LO	70 /* half16	(sym+add)@tprel@l */
+#define R_PPC64_TPREL16_HI	71 /* half16	(sym+add)@tprel@h */
+#define R_PPC64_TPREL16_HA	72 /* half16	(sym+add)@tprel@ha */
+#define R_PPC64_TPREL64		73 /* doubleword64 (sym+add)@tprel */
+#define R_PPC64_DTPREL16	74 /* half16*	(sym+add)@dtprel */
+#define R_PPC64_DTPREL16_LO	75 /* half16	(sym+add)@dtprel@l */
+#define R_PPC64_DTPREL16_HI	76 /* half16	(sym+add)@dtprel@h */
+#define R_PPC64_DTPREL16_HA	77 /* half16	(sym+add)@dtprel@ha */
+#define R_PPC64_DTPREL64	78 /* doubleword64 (sym+add)@dtprel */
+#define R_PPC64_GOT_TLSGD16	79 /* half16*	(sym+add)@got@tlsgd */
+#define R_PPC64_GOT_TLSGD16_LO	80 /* half16	(sym+add)@got@tlsgd@l */
+#define R_PPC64_GOT_TLSGD16_HI	81 /* half16	(sym+add)@got@tlsgd@h */
+#define R_PPC64_GOT_TLSGD16_HA	82 /* half16	(sym+add)@got@tlsgd@ha */
+#define R_PPC64_GOT_TLSLD16	83 /* half16*	(sym+add)@got@tlsld */
+#define R_PPC64_GOT_TLSLD16_LO	84 /* half16	(sym+add)@got@tlsld@l */
+#define R_PPC64_GOT_TLSLD16_HI	85 /* half16	(sym+add)@got@tlsld@h */
+#define R_PPC64_GOT_TLSLD16_HA	86 /* half16	(sym+add)@got@tlsld@ha */
+#define R_PPC64_GOT_TPREL16_DS	87 /* half16ds*	(sym+add)@got@tprel */
+#define R_PPC64_GOT_TPREL16_LO_DS 88 /* half16ds (sym+add)@got@tprel@l */
+#define R_PPC64_GOT_TPREL16_HI	89 /* half16	(sym+add)@got@tprel@h */
+#define R_PPC64_GOT_TPREL16_HA	90 /* half16	(sym+add)@got@tprel@ha */
+#define R_PPC64_GOT_DTPREL16_DS	91 /* half16ds*	(sym+add)@got@dtprel */
+#define R_PPC64_GOT_DTPREL16_LO_DS 92 /* half16ds (sym+add)@got@dtprel@l */
+#define R_PPC64_GOT_DTPREL16_HI	93 /* half16	(sym+add)@got@dtprel@h */
+#define R_PPC64_GOT_DTPREL16_HA	94 /* half16	(sym+add)@got@dtprel@ha */
+#define R_PPC64_TPREL16_DS	95 /* half16ds*	(sym+add)@tprel */
+#define R_PPC64_TPREL16_LO_DS	96 /* half16ds	(sym+add)@tprel@l */
+#define R_PPC64_TPREL16_HIGHER	97 /* half16	(sym+add)@tprel@higher */
+#define R_PPC64_TPREL16_HIGHERA	98 /* half16	(sym+add)@tprel@highera */
+#define R_PPC64_TPREL16_HIGHEST	99 /* half16	(sym+add)@tprel@highest */
+#define R_PPC64_TPREL16_HIGHESTA 100 /* half16	(sym+add)@tprel@highesta */
+#define R_PPC64_DTPREL16_DS	101 /* half16ds* (sym+add)@dtprel */
+#define R_PPC64_DTPREL16_LO_DS	102 /* half16ds	(sym+add)@dtprel@l */
+#define R_PPC64_DTPREL16_HIGHER	103 /* half16	(sym+add)@dtprel@higher */
+#define R_PPC64_DTPREL16_HIGHERA 104 /* half16	(sym+add)@dtprel@highera */
+#define R_PPC64_DTPREL16_HIGHEST 105 /* half16	(sym+add)@dtprel@highest */
+#define R_PPC64_DTPREL16_HIGHESTA 106 /* half16	(sym+add)@dtprel@highesta */
+
+/* Keep this the last entry.  */
+#define R_PPC64_NUM		107
+
+/* PowerPC64 specific values for the Dyn d_tag field.  */
+#define DT_PPC64_GLINK  (DT_LOPROC + 0)
+#define DT_PPC64_OPD	(DT_LOPROC + 1)
+#define DT_PPC64_OPDSZ	(DT_LOPROC + 2)
+#define DT_PPC64_NUM    3
+
+
+/* ARM specific declarations */
+
+/* Processor specific flags for the ELF header e_flags field.  */
+#define EF_ARM_RELEXEC     0x01
+#define EF_ARM_HASENTRY    0x02
+#define EF_ARM_INTERWORK   0x04
+#define EF_ARM_APCS_26     0x08
+#define EF_ARM_APCS_FLOAT  0x10
+#define EF_ARM_PIC         0x20
+#define EF_ARM_ALIGN8      0x40		/* 8-bit structure alignment is in use */
+#define EF_ARM_NEW_ABI     0x80
+#define EF_ARM_OLD_ABI     0x100
+
+/* Other constants defined in the ARM ELF spec. version B-01.  */
+/* NB. These conflict with values defined above.  */
+#define EF_ARM_SYMSARESORTED	0x04
+#define EF_ARM_DYNSYMSUSESEGIDX 0x08
+#define EF_ARM_MAPSYMSFIRST	0x10
+#define EF_ARM_EABIMASK		0XFF000000
+
+#define EF_ARM_EABI_VERSION(flags) ((flags) & EF_ARM_EABIMASK)
+#define EF_ARM_EABI_UNKNOWN  0x00000000
+#define EF_ARM_EABI_VER1     0x01000000
+#define EF_ARM_EABI_VER2     0x02000000
+
+/* Additional symbol types for Thumb */
+#define STT_ARM_TFUNC      0xd
+
+/* ARM-specific values for sh_flags */
+#define SHF_ARM_ENTRYSECT  0x10000000   /* Section contains an entry point */
+#define SHF_ARM_COMDEF     0x80000000   /* Section may be multiply defined
+					   in the input to a link step */
+
+/* ARM-specific program header flags */
+#define PF_ARM_SB          0x10000000   /* Segment contains the location
+					   addressed by the static base */
+
+/* Processor specific values for the Phdr p_type field.  */
+#define PT_ARM_EXIDX	0x70000001	/* .ARM.exidx segment */
+
+/* ARM relocs.  */
+
+#define R_ARM_NONE		0	/* No reloc */
+#define R_ARM_PC24		1	/* PC relative 26 bit branch */
+#define R_ARM_ABS32		2	/* Direct 32 bit  */
+#define R_ARM_REL32		3	/* PC relative 32 bit */
+#define R_ARM_PC13		4
+#define R_ARM_ABS16		5	/* Direct 16 bit */
+#define R_ARM_ABS12		6	/* Direct 12 bit */
+#define R_ARM_THM_ABS5		7
+#define R_ARM_ABS8		8	/* Direct 8 bit */
+#define R_ARM_SBREL32		9
+#define R_ARM_THM_PC22		10
+#define R_ARM_THM_PC8		11
+#define R_ARM_AMP_VCALL9	12
+#define R_ARM_SWI24		13
+#define R_ARM_THM_SWI8		14
+#define R_ARM_XPC25		15
+#define R_ARM_THM_XPC22		16
+#define R_ARM_TLS_DTPMOD32	17	/* ID of module containing symbol */
+#define R_ARM_TLS_DTPOFF32	18	/* Offset in TLS block */
+#define R_ARM_TLS_TPOFF32	19	/* Offset in static TLS block */
+#define R_ARM_COPY		20	/* Copy symbol at runtime */
+#define R_ARM_GLOB_DAT		21	/* Create GOT entry */
+#define R_ARM_JUMP_SLOT		22	/* Create PLT entry */
+#define R_ARM_RELATIVE		23	/* Adjust by program base */
+#define R_ARM_GOTOFF		24	/* 32 bit offset to GOT */
+#define R_ARM_GOTPC		25	/* 32 bit PC relative offset to GOT */
+#define R_ARM_GOT32		26	/* 32 bit GOT entry */
+#define R_ARM_PLT32		27	/* 32 bit PLT address */
+#define R_ARM_ALU_PCREL_7_0	32
+#define R_ARM_ALU_PCREL_15_8	33
+#define R_ARM_ALU_PCREL_23_15	34
+#define R_ARM_LDR_SBREL_11_0	35
+#define R_ARM_ALU_SBREL_19_12	36
+#define R_ARM_ALU_SBREL_27_20	37
+#define R_ARM_GNU_VTENTRY	100
+#define R_ARM_GNU_VTINHERIT	101
+#define R_ARM_THM_PC11		102	/* thumb unconditional branch */
+#define R_ARM_THM_PC9		103	/* thumb conditional branch */
+#define R_ARM_TLS_GD32		104	/* PC-rel 32 bit for global dynamic
+					   thread local data */
+#define R_ARM_TLS_LDM32		105	/* PC-rel 32 bit for local dynamic
+					   thread local data */
+#define R_ARM_TLS_LDO32		106	/* 32 bit offset relative to TLS
+					   block */
+#define R_ARM_TLS_IE32		107	/* PC-rel 32 bit for GOT entry of
+					   static TLS block offset */
+#define R_ARM_TLS_LE32		108	/* 32 bit offset relative to static
+					   TLS block */
+#define R_ARM_RXPC25		249
+#define R_ARM_RSBREL32		250
+#define R_ARM_THM_RPC22		251
+#define R_ARM_RREL32		252
+#define R_ARM_RABS22		253
+#define R_ARM_RPC24		254
+#define R_ARM_RBASE		255
+/* Keep this the last entry.  */
+#define R_ARM_NUM		256
+
+/* IA-64 specific declarations.  */
+
+/* Processor specific flags for the Ehdr e_flags field.  */
+#define EF_IA_64_MASKOS		0x0000000f	/* os-specific flags */
+#define EF_IA_64_ABI64		0x00000010	/* 64-bit ABI */
+#define EF_IA_64_ARCH		0xff000000	/* arch. version mask */
+
+/* Processor specific values for the Phdr p_type field.  */
+#define PT_IA_64_ARCHEXT	(PT_LOPROC + 0)	/* arch extension bits */
+#define PT_IA_64_UNWIND		(PT_LOPROC + 1)	/* ia64 unwind bits */
+#define PT_IA_64_HP_OPT_ANOT	(PT_LOOS + 0x12)
+#define PT_IA_64_HP_HSL_ANOT	(PT_LOOS + 0x13)
+#define PT_IA_64_HP_STACK	(PT_LOOS + 0x14)
+
+/* Processor specific flags for the Phdr p_flags field.  */
+#define PF_IA_64_NORECOV	0x80000000	/* spec insns w/o recovery */
+
+/* Processor specific values for the Shdr sh_type field.  */
+#define SHT_IA_64_EXT		(SHT_LOPROC + 0) /* extension bits */
+#define SHT_IA_64_UNWIND	(SHT_LOPROC + 1) /* unwind bits */
+
+/* Processor specific flags for the Shdr sh_flags field.  */
+#define SHF_IA_64_SHORT		0x10000000	/* section near gp */
+#define SHF_IA_64_NORECOV	0x20000000	/* spec insns w/o recovery */
+
+/* Processor specific values for the Dyn d_tag field.  */
+#define DT_IA_64_PLT_RESERVE	(DT_LOPROC + 0)
+#define DT_IA_64_NUM		1
+
+/* IA-64 relocations.  */
+#define R_IA64_NONE		0x00	/* none */
+#define R_IA64_IMM14		0x21	/* symbol + addend, add imm14 */
+#define R_IA64_IMM22		0x22	/* symbol + addend, add imm22 */
+#define R_IA64_IMM64		0x23	/* symbol + addend, mov imm64 */
+#define R_IA64_DIR32MSB		0x24	/* symbol + addend, data4 MSB */
+#define R_IA64_DIR32LSB		0x25	/* symbol + addend, data4 LSB */
+#define R_IA64_DIR64MSB		0x26	/* symbol + addend, data8 MSB */
+#define R_IA64_DIR64LSB		0x27	/* symbol + addend, data8 LSB */
+#define R_IA64_GPREL22		0x2a	/* @gprel(sym + add), add imm22 */
+#define R_IA64_GPREL64I		0x2b	/* @gprel(sym + add), mov imm64 */
+#define R_IA64_GPREL32MSB	0x2c	/* @gprel(sym + add), data4 MSB */
+#define R_IA64_GPREL32LSB	0x2d	/* @gprel(sym + add), data4 LSB */
+#define R_IA64_GPREL64MSB	0x2e	/* @gprel(sym + add), data8 MSB */
+#define R_IA64_GPREL64LSB	0x2f	/* @gprel(sym + add), data8 LSB */
+#define R_IA64_LTOFF22		0x32	/* @ltoff(sym + add), add imm22 */
+#define R_IA64_LTOFF64I		0x33	/* @ltoff(sym + add), mov imm64 */
+#define R_IA64_PLTOFF22		0x3a	/* @pltoff(sym + add), add imm22 */
+#define R_IA64_PLTOFF64I	0x3b	/* @pltoff(sym + add), mov imm64 */
+#define R_IA64_PLTOFF64MSB	0x3e	/* @pltoff(sym + add), data8 MSB */
+#define R_IA64_PLTOFF64LSB	0x3f	/* @pltoff(sym + add), data8 LSB */
+#define R_IA64_FPTR64I		0x43	/* @fptr(sym + add), mov imm64 */
+#define R_IA64_FPTR32MSB	0x44	/* @fptr(sym + add), data4 MSB */
+#define R_IA64_FPTR32LSB	0x45	/* @fptr(sym + add), data4 LSB */
+#define R_IA64_FPTR64MSB	0x46	/* @fptr(sym + add), data8 MSB */
+#define R_IA64_FPTR64LSB	0x47	/* @fptr(sym + add), data8 LSB */
+#define R_IA64_PCREL60B		0x48	/* @pcrel(sym + add), brl */
+#define R_IA64_PCREL21B		0x49	/* @pcrel(sym + add), ptb, call */
+#define R_IA64_PCREL21M		0x4a	/* @pcrel(sym + add), chk.s */
+#define R_IA64_PCREL21F		0x4b	/* @pcrel(sym + add), fchkf */
+#define R_IA64_PCREL32MSB	0x4c	/* @pcrel(sym + add), data4 MSB */
+#define R_IA64_PCREL32LSB	0x4d	/* @pcrel(sym + add), data4 LSB */
+#define R_IA64_PCREL64MSB	0x4e	/* @pcrel(sym + add), data8 MSB */
+#define R_IA64_PCREL64LSB	0x4f	/* @pcrel(sym + add), data8 LSB */
+#define R_IA64_LTOFF_FPTR22	0x52	/* @ltoff(@fptr(s+a)), imm22 */
+#define R_IA64_LTOFF_FPTR64I	0x53	/* @ltoff(@fptr(s+a)), imm64 */
+#define R_IA64_LTOFF_FPTR32MSB	0x54	/* @ltoff(@fptr(s+a)), data4 MSB */
+#define R_IA64_LTOFF_FPTR32LSB	0x55	/* @ltoff(@fptr(s+a)), data4 LSB */
+#define R_IA64_LTOFF_FPTR64MSB	0x56	/* @ltoff(@fptr(s+a)), data8 MSB */
+#define R_IA64_LTOFF_FPTR64LSB	0x57	/* @ltoff(@fptr(s+a)), data8 LSB */
+#define R_IA64_SEGREL32MSB	0x5c	/* @segrel(sym + add), data4 MSB */
+#define R_IA64_SEGREL32LSB	0x5d	/* @segrel(sym + add), data4 LSB */
+#define R_IA64_SEGREL64MSB	0x5e	/* @segrel(sym + add), data8 MSB */
+#define R_IA64_SEGREL64LSB	0x5f	/* @segrel(sym + add), data8 LSB */
+#define R_IA64_SECREL32MSB	0x64	/* @secrel(sym + add), data4 MSB */
+#define R_IA64_SECREL32LSB	0x65	/* @secrel(sym + add), data4 LSB */
+#define R_IA64_SECREL64MSB	0x66	/* @secrel(sym + add), data8 MSB */
+#define R_IA64_SECREL64LSB	0x67	/* @secrel(sym + add), data8 LSB */
+#define R_IA64_REL32MSB		0x6c	/* data 4 + REL */
+#define R_IA64_REL32LSB		0x6d	/* data 4 + REL */
+#define R_IA64_REL64MSB		0x6e	/* data 8 + REL */
+#define R_IA64_REL64LSB		0x6f	/* data 8 + REL */
+#define R_IA64_LTV32MSB		0x74	/* symbol + addend, data4 MSB */
+#define R_IA64_LTV32LSB		0x75	/* symbol + addend, data4 LSB */
+#define R_IA64_LTV64MSB		0x76	/* symbol + addend, data8 MSB */
+#define R_IA64_LTV64LSB		0x77	/* symbol + addend, data8 LSB */
+#define R_IA64_PCREL21BI	0x79	/* @pcrel(sym + add), 21bit inst */
+#define R_IA64_PCREL22		0x7a	/* @pcrel(sym + add), 22bit inst */
+#define R_IA64_PCREL64I		0x7b	/* @pcrel(sym + add), 64bit inst */
+#define R_IA64_IPLTMSB		0x80	/* dynamic reloc, imported PLT, MSB */
+#define R_IA64_IPLTLSB		0x81	/* dynamic reloc, imported PLT, LSB */
+#define R_IA64_COPY		0x84	/* copy relocation */
+#define R_IA64_SUB		0x85	/* Addend and symbol difference */
+#define R_IA64_LTOFF22X		0x86	/* LTOFF22, relaxable.  */
+#define R_IA64_LDXMOV		0x87	/* Use of LTOFF22X.  */
+#define R_IA64_TPREL14		0x91	/* @tprel(sym + add), imm14 */
+#define R_IA64_TPREL22		0x92	/* @tprel(sym + add), imm22 */
+#define R_IA64_TPREL64I		0x93	/* @tprel(sym + add), imm64 */
+#define R_IA64_TPREL64MSB	0x96	/* @tprel(sym + add), data8 MSB */
+#define R_IA64_TPREL64LSB	0x97	/* @tprel(sym + add), data8 LSB */
+#define R_IA64_LTOFF_TPREL22	0x9a	/* @ltoff(@tprel(s+a)), imm2 */
+#define R_IA64_DTPMOD64MSB	0xa6	/* @dtpmod(sym + add), data8 MSB */
+#define R_IA64_DTPMOD64LSB	0xa7	/* @dtpmod(sym + add), data8 LSB */
+#define R_IA64_LTOFF_DTPMOD22	0xaa	/* @ltoff(@dtpmod(sym + add)), imm22 */
+#define R_IA64_DTPREL14		0xb1	/* @dtprel(sym + add), imm14 */
+#define R_IA64_DTPREL22		0xb2	/* @dtprel(sym + add), imm22 */
+#define R_IA64_DTPREL64I	0xb3	/* @dtprel(sym + add), imm64 */
+#define R_IA64_DTPREL32MSB	0xb4	/* @dtprel(sym + add), data4 MSB */
+#define R_IA64_DTPREL32LSB	0xb5	/* @dtprel(sym + add), data4 LSB */
+#define R_IA64_DTPREL64MSB	0xb6	/* @dtprel(sym + add), data8 MSB */
+#define R_IA64_DTPREL64LSB	0xb7	/* @dtprel(sym + add), data8 LSB */
+#define R_IA64_LTOFF_DTPREL22	0xba	/* @ltoff(@dtprel(s+a)), imm22 */
+
+/* SH specific declarations */
+
+/* SH relocs.  */
+#define	R_SH_NONE		0
+#define	R_SH_DIR32		1
+#define	R_SH_REL32		2
+#define	R_SH_DIR8WPN		3
+#define	R_SH_IND12W		4
+#define	R_SH_DIR8WPL		5
+#define	R_SH_DIR8WPZ		6
+#define	R_SH_DIR8BP		7
+#define	R_SH_DIR8W		8
+#define	R_SH_DIR8L		9
+#define	R_SH_SWITCH16		25
+#define	R_SH_SWITCH32		26
+#define	R_SH_USES		27
+#define	R_SH_COUNT		28
+#define	R_SH_ALIGN		29
+#define	R_SH_CODE		30
+#define	R_SH_DATA		31
+#define	R_SH_LABEL		32
+#define	R_SH_SWITCH8		33
+#define	R_SH_GNU_VTINHERIT	34
+#define	R_SH_GNU_VTENTRY	35
+#define	R_SH_TLS_GD_32		144
+#define	R_SH_TLS_LD_32		145
+#define	R_SH_TLS_LDO_32		146
+#define	R_SH_TLS_IE_32		147
+#define	R_SH_TLS_LE_32		148
+#define	R_SH_TLS_DTPMOD32	149
+#define	R_SH_TLS_DTPOFF32	150
+#define	R_SH_TLS_TPOFF32	151
+#define	R_SH_GOT32		160
+#define	R_SH_PLT32		161
+#define	R_SH_COPY		162
+#define	R_SH_GLOB_DAT		163
+#define	R_SH_JMP_SLOT		164
+#define	R_SH_RELATIVE		165
+#define	R_SH_GOTOFF		166
+#define	R_SH_GOTPC		167
+/* Keep this the last entry.  */
+#define	R_SH_NUM		256
+
+/* Additional s390 relocs */
+
+#define R_390_NONE		0	/* No reloc.  */
+#define R_390_8			1	/* Direct 8 bit.  */
+#define R_390_12		2	/* Direct 12 bit.  */
+#define R_390_16		3	/* Direct 16 bit.  */
+#define R_390_32		4	/* Direct 32 bit.  */
+#define R_390_PC32		5	/* PC relative 32 bit.	*/
+#define R_390_GOT12		6	/* 12 bit GOT offset.  */
+#define R_390_GOT32		7	/* 32 bit GOT offset.  */
+#define R_390_PLT32		8	/* 32 bit PC relative PLT address.  */
+#define R_390_COPY		9	/* Copy symbol at runtime.  */
+#define R_390_GLOB_DAT		10	/* Create GOT entry.  */
+#define R_390_JMP_SLOT		11	/* Create PLT entry.  */
+#define R_390_RELATIVE		12	/* Adjust by program base.  */
+#define R_390_GOTOFF32		13	/* 32 bit offset to GOT.	 */
+#define R_390_GOTPC		14	/* 32 bit PC relative offset to GOT.  */
+#define R_390_GOT16		15	/* 16 bit GOT offset.  */
+#define R_390_PC16		16	/* PC relative 16 bit.	*/
+#define R_390_PC16DBL		17	/* PC relative 16 bit shifted by 1.  */
+#define R_390_PLT16DBL		18	/* 16 bit PC rel. PLT shifted by 1.  */
+#define R_390_PC32DBL		19	/* PC relative 32 bit shifted by 1.  */
+#define R_390_PLT32DBL		20	/* 32 bit PC rel. PLT shifted by 1.  */
+#define R_390_GOTPCDBL		21	/* 32 bit PC rel. GOT shifted by 1.  */
+#define R_390_64		22	/* Direct 64 bit.  */
+#define R_390_PC64		23	/* PC relative 64 bit.	*/
+#define R_390_GOT64		24	/* 64 bit GOT offset.  */
+#define R_390_PLT64		25	/* 64 bit PC relative PLT address.  */
+#define R_390_GOTENT		26	/* 32 bit PC rel. to GOT entry >> 1. */
+#define R_390_GOTOFF16		27	/* 16 bit offset to GOT. */
+#define R_390_GOTOFF64		28	/* 64 bit offset to GOT. */
+#define R_390_GOTPLT12		29	/* 12 bit offset to jump slot.	*/
+#define R_390_GOTPLT16		30	/* 16 bit offset to jump slot.	*/
+#define R_390_GOTPLT32		31	/* 32 bit offset to jump slot.	*/
+#define R_390_GOTPLT64		32	/* 64 bit offset to jump slot.	*/
+#define R_390_GOTPLTENT		33	/* 32 bit rel. offset to jump slot.  */
+#define R_390_PLTOFF16		34	/* 16 bit offset from GOT to PLT. */
+#define R_390_PLTOFF32		35	/* 32 bit offset from GOT to PLT. */
+#define R_390_PLTOFF64		36	/* 16 bit offset from GOT to PLT. */
+#define R_390_TLS_LOAD		37	/* Tag for load insn in TLS code.  */
+#define R_390_TLS_GDCALL	38	/* Tag for function call in general
+					   dynamic TLS code. */
+#define R_390_TLS_LDCALL	39	/* Tag for function call in local
+					   dynamic TLS code. */
+#define R_390_TLS_GD32		40	/* Direct 32 bit for general dynamic
+					   thread local data.  */
+#define R_390_TLS_GD64		41	/* Direct 64 bit for general dynamic
+					  thread local data.  */
+#define R_390_TLS_GOTIE12	42	/* 12 bit GOT offset for static TLS
+					   block offset.  */
+#define R_390_TLS_GOTIE32	43	/* 32 bit GOT offset for static TLS
+					   block offset.  */
+#define R_390_TLS_GOTIE64	44	/* 64 bit GOT offset for static TLS
+					   block offset. */
+#define R_390_TLS_LDM32		45	/* Direct 32 bit for local dynamic
+					   thread local data in LE code.  */
+#define R_390_TLS_LDM64		46	/* Direct 64 bit for local dynamic
+					   thread local data in LE code.  */
+#define R_390_TLS_IE32		47	/* 32 bit address of GOT entry for
+					   negated static TLS block offset.  */
+#define R_390_TLS_IE64		48	/* 64 bit address of GOT entry for
+					   negated static TLS block offset.  */
+#define R_390_TLS_IEENT		49	/* 32 bit rel. offset to GOT entry for
+					   negated static TLS block offset.  */
+#define R_390_TLS_LE32		50	/* 32 bit negated offset relative to
+					   static TLS block.  */
+#define R_390_TLS_LE64		51	/* 64 bit negated offset relative to
+					   static TLS block.  */
+#define R_390_TLS_LDO32		52	/* 32 bit offset relative to TLS
+					   block.  */
+#define R_390_TLS_LDO64		53	/* 64 bit offset relative to TLS
+					   block.  */
+#define R_390_TLS_DTPMOD	54	/* ID of module containing symbol.  */
+#define R_390_TLS_DTPOFF	55	/* Offset in TLS block.	 */
+#define R_390_TLS_TPOFF		56	/* Negated offset in static TLS
+					   block.  */
+#define R_390_20		57	/* Direct 20 bit.  */
+#define R_390_GOT20		58	/* 20 bit GOT offset.  */
+#define R_390_GOTPLT20		59	/* 20 bit offset to jump slot.  */
+#define R_390_TLS_GOTIE20	60	/* 20 bit GOT offset for static TLS
+					   block offset.  */
+/* Keep this the last entry.  */
+#define R_390_NUM		61
+
+
+/* CRIS relocations.  */
+#define R_CRIS_NONE		0
+#define R_CRIS_8		1
+#define R_CRIS_16		2
+#define R_CRIS_32		3
+#define R_CRIS_8_PCREL		4
+#define R_CRIS_16_PCREL		5
+#define R_CRIS_32_PCREL		6
+#define R_CRIS_GNU_VTINHERIT	7
+#define R_CRIS_GNU_VTENTRY	8
+#define R_CRIS_COPY		9
+#define R_CRIS_GLOB_DAT		10
+#define R_CRIS_JUMP_SLOT	11
+#define R_CRIS_RELATIVE		12
+#define R_CRIS_16_GOT		13
+#define R_CRIS_32_GOT		14
+#define R_CRIS_16_GOTPLT	15
+#define R_CRIS_32_GOTPLT	16
+#define R_CRIS_32_GOTREL	17
+#define R_CRIS_32_PLT_GOTREL	18
+#define R_CRIS_32_PLT_PCREL	19
+
+#define R_CRIS_NUM		20
+
+
+/* AMD x86-64 relocations.  */
+#define R_X86_64_NONE		0	/* No reloc */
+#define R_X86_64_64		1	/* Direct 64 bit  */
+#define R_X86_64_PC32		2	/* PC relative 32 bit signed */
+#define R_X86_64_GOT32		3	/* 32 bit GOT entry */
+#define R_X86_64_PLT32		4	/* 32 bit PLT address */
+#define R_X86_64_COPY		5	/* Copy symbol at runtime */
+#define R_X86_64_GLOB_DAT	6	/* Create GOT entry */
+#define R_X86_64_JUMP_SLOT	7	/* Create PLT entry */
+#define R_X86_64_RELATIVE	8	/* Adjust by program base */
+#define R_X86_64_GOTPCREL	9	/* 32 bit signed PC relative
+					   offset to GOT */
+#define R_X86_64_32		10	/* Direct 32 bit zero extended */
+#define R_X86_64_32S		11	/* Direct 32 bit sign extended */
+#define R_X86_64_16		12	/* Direct 16 bit zero extended */
+#define R_X86_64_PC16		13	/* 16 bit sign extended pc relative */
+#define R_X86_64_8		14	/* Direct 8 bit sign extended  */
+#define R_X86_64_PC8		15	/* 8 bit sign extended pc relative */
+#define R_X86_64_DTPMOD64	16	/* ID of module containing symbol */
+#define R_X86_64_DTPOFF64	17	/* Offset in module's TLS block */
+#define R_X86_64_TPOFF64	18	/* Offset in initial TLS block */
+#define R_X86_64_TLSGD		19	/* 32 bit signed PC relative offset
+					   to two GOT entries for GD symbol */
+#define R_X86_64_TLSLD		20	/* 32 bit signed PC relative offset
+					   to two GOT entries for LD symbol */
+#define R_X86_64_DTPOFF32	21	/* Offset in TLS block */
+#define R_X86_64_GOTTPOFF	22	/* 32 bit signed PC relative offset
+					   to GOT entry for IE symbol */
+#define R_X86_64_TPOFF32	23	/* Offset in initial TLS block */
+
+#define R_X86_64_NUM		24
+
+
+/* AM33 relocations.  */
+#define R_MN10300_NONE		0	/* No reloc.  */
+#define R_MN10300_32		1	/* Direct 32 bit.  */
+#define R_MN10300_16		2	/* Direct 16 bit.  */
+#define R_MN10300_8		3	/* Direct 8 bit.  */
+#define R_MN10300_PCREL32	4	/* PC-relative 32-bit.  */
+#define R_MN10300_PCREL16	5	/* PC-relative 16-bit signed.  */
+#define R_MN10300_PCREL8	6	/* PC-relative 8-bit signed.  */
+#define R_MN10300_GNU_VTINHERIT	7	/* Ancient C++ vtable garbage... */
+#define R_MN10300_GNU_VTENTRY	8	/* ... collection annotation.  */
+#define R_MN10300_24		9	/* Direct 24 bit.  */
+#define R_MN10300_GOTPC32	10	/* 32-bit PCrel offset to GOT.  */
+#define R_MN10300_GOTPC16	11	/* 16-bit PCrel offset to GOT.  */
+#define R_MN10300_GOTOFF32	12	/* 32-bit offset from GOT.  */
+#define R_MN10300_GOTOFF24	13	/* 24-bit offset from GOT.  */
+#define R_MN10300_GOTOFF16	14	/* 16-bit offset from GOT.  */
+#define R_MN10300_PLT32		15	/* 32-bit PCrel to PLT entry.  */
+#define R_MN10300_PLT16		16	/* 16-bit PCrel to PLT entry.  */
+#define R_MN10300_GOT32		17	/* 32-bit offset to GOT entry.  */
+#define R_MN10300_GOT24		18	/* 24-bit offset to GOT entry.  */
+#define R_MN10300_GOT16		19	/* 16-bit offset to GOT entry.  */
+#define R_MN10300_COPY		20	/* Copy symbol at runtime.  */
+#define R_MN10300_GLOB_DAT	21	/* Create GOT entry.  */
+#define R_MN10300_JMP_SLOT	22	/* Create PLT entry.  */
+#define R_MN10300_RELATIVE	23	/* Adjust by program base.  */
+
+#define R_MN10300_NUM		24
+
+
+/* M32R relocs.  */
+#define R_M32R_NONE		0	/* No reloc. */
+#define R_M32R_16		1	/* Direct 16 bit. */
+#define R_M32R_32		2	/* Direct 32 bit. */
+#define R_M32R_24		3	/* Direct 24 bit. */
+#define R_M32R_10_PCREL		4	/* PC relative 10 bit shifted. */
+#define R_M32R_18_PCREL		5	/* PC relative 18 bit shifted. */
+#define R_M32R_26_PCREL		6	/* PC relative 26 bit shifted. */
+#define R_M32R_HI16_ULO		7	/* High 16 bit with unsigned low. */
+#define R_M32R_HI16_SLO		8	/* High 16 bit with signed low. */
+#define R_M32R_LO16		9	/* Low 16 bit. */
+#define R_M32R_SDA16		10	/* 16 bit offset in SDA. */
+#define R_M32R_GNU_VTINHERIT	11
+#define R_M32R_GNU_VTENTRY	12
+/* M32R relocs use SHT_RELA.  */
+#define R_M32R_16_RELA		33	/* Direct 16 bit. */
+#define R_M32R_32_RELA		34	/* Direct 32 bit. */
+#define R_M32R_24_RELA		35	/* Direct 24 bit. */
+#define R_M32R_10_PCREL_RELA	36	/* PC relative 10 bit shifted. */
+#define R_M32R_18_PCREL_RELA	37	/* PC relative 18 bit shifted. */
+#define R_M32R_26_PCREL_RELA	38	/* PC relative 26 bit shifted. */
+#define R_M32R_HI16_ULO_RELA	39	/* High 16 bit with unsigned low */
+#define R_M32R_HI16_SLO_RELA	40	/* High 16 bit with signed low */
+#define R_M32R_LO16_RELA	41	/* Low 16 bit */
+#define R_M32R_SDA16_RELA	42	/* 16 bit offset in SDA */
+#define R_M32R_RELA_GNU_VTINHERIT	43
+#define R_M32R_RELA_GNU_VTENTRY	44
+#define R_M32R_REL32		45	/* PC relative 32 bit.  */
+
+#define R_M32R_GOT24		48	/* 24 bit GOT entry */
+#define R_M32R_26_PLTREL	49	/* 26 bit PC relative to PLT shifted */
+#define R_M32R_COPY		50	/* Copy symbol at runtime */
+#define R_M32R_GLOB_DAT		51	/* Create GOT entry */
+#define R_M32R_JMP_SLOT		52	/* Create PLT entry */
+#define R_M32R_RELATIVE		53	/* Adjust by program base */
+#define R_M32R_GOTOFF		54	/* 24 bit offset to GOT */
+#define R_M32R_GOTPC24		55	/* 24 bit PC relative offset to GOT */
+#define R_M32R_GOT16_HI_ULO	56	/* High 16 bit GOT entry with unsigned
+					   low */
+#define R_M32R_GOT16_HI_SLO	57	/* High 16 bit GOT entry with signed
+					   low */
+#define R_M32R_GOT16_LO		58	/* Low 16 bit GOT entry */
+#define R_M32R_GOTPC_HI_ULO	59	/* High 16 bit PC relative offset to
+					   GOT with unsigned low */
+#define R_M32R_GOTPC_HI_SLO	60	/* High 16 bit PC relative offset to
+					   GOT with signed low */
+#define R_M32R_GOTPC_LO		61	/* Low 16 bit PC relative offset to
+					   GOT */
+#define R_M32R_GOTOFF_HI_ULO	62	/* High 16 bit offset to GOT
+					   with unsigned low */
+#define R_M32R_GOTOFF_HI_SLO	63	/* High 16 bit offset to GOT
+					   with signed low */
+#define R_M32R_GOTOFF_LO	64	/* Low 16 bit offset to GOT */
+#define R_M32R_NUM		256	/* Keep this the last entry. */
+
+#endif	/* elf.h */
+
+// Local Variables:
+// tab-width: 4
+// c-basic-offset: 4
+// c-file-offsets:((innamespace . 0)(inline-open . 0))
+// indent-tabs-mode: nil
+// End:
+
+// vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4
+
Index: branches/v4/softs/tsar_boot/include/io.h
===================================================================
--- branches/v4/softs/tsar_boot/include/io.h	(revision 371)
+++ branches/v4/softs/tsar_boot/include/io.h	(revision 371)
@@ -0,0 +1,64 @@
+/**
+ * \file	io.h
+ * \date	5 September 2012
+ * \author	Cesar Fuguet
+ *
+ * Utility functions to write or read memory mapped hardware registers
+ */
+#ifndef IO_H
+#define IO_H
+
+/**
+ * Read an 32 bits memory mapped hardware register
+ */
+static inline unsigned int ioread32(void * addr)
+{
+	return *(volatile unsigned int *) addr;
+}
+
+/**
+ * Read an 16 bits memory mapped hardware register
+ */
+static inline unsigned short ioread16(void * addr)
+{
+	return *(volatile unsigned short *) addr;
+}
+
+/**
+ * Read an 8 bits memory mapped hardware register
+ */
+static inline unsigned char ioread8(void * addr)
+{
+	return *(volatile unsigned char *) addr;
+}
+
+/**
+ * Write an 32 bits memory mapped hardware register
+ */
+static inline void iowrite32(void * addr, unsigned int value)
+{
+	*(volatile unsigned int *) addr = value;
+	asm volatile("sync");
+}
+
+/**
+ * Write an 16 bits memory mapped hardware register
+ */
+static inline void iowrite16(void * addr, unsigned short value)
+{
+	*(volatile unsigned short *) addr = value;
+	asm volatile("sync");
+}
+
+/**
+ * Write an 8 bits memory mapped hardware register
+ */
+static inline void iowrite8(void * addr, unsigned char value)
+{
+	*(volatile unsigned char *) addr = value;
+	asm volatile("sync");
+}
+
+#undef in_reset
+
+#endif
Index: branches/v4/softs/tsar_boot/include/mips32_registers.h
===================================================================
--- branches/v4/softs/tsar_boot/include/mips32_registers.h	(revision 371)
+++ branches/v4/softs/tsar_boot/include/mips32_registers.h	(revision 371)
@@ -0,0 +1,56 @@
+/********************************************************************************/
+/*	File        : mips32_registers.h											*/
+/*	Author      : Alain Greiner													*/
+/*	Date        : 26/03/2012													*/
+/*  Modified by : Cesar Fuguet 10/02/2013										*/
+/********************************************************************************/
+/* 	We define mnemonics for MIPS32 registers             	 					*/
+/********************************************************************************/
+
+#ifndef _MIPS32_REGISTERS_H
+#define _MIPS32_REGISTERS_H
+
+/* processor registers */
+
+#define zero            $0
+#define at              $at
+#define v0              $2
+#define v1              $3
+#define a0              $4
+#define a1              $5
+#define a2              $6
+#define a3              $7
+#define t0              $8
+#define t1              $9
+#define t2              $10
+#define t3              $11
+#define t4              $12
+#define t5              $13
+#define t6              $14
+#define t7              $15
+#define s0              $16
+#define s1              $17
+#define s2              $18
+#define s3              $19
+#define s4              $20
+#define s5              $21
+#define s6              $22
+#define s7              $23
+#define t8              $24
+#define t9              $25
+#define k0              $26
+#define k1              $27
+#define gp              $28
+#define sp              $29
+#define fp              $30
+#define ra              $31
+
+/* CP0 registers */
+
+#define CP0_COUNT       $9
+#define CP0_STATUS      $12,0
+#define CP0_CAUSE       $13,0
+#define CP0_EPC         $14,0
+#define CP0_EBASE       $15,1
+
+#endif
Index: branches/v4/softs/tsar_boot/include/sdcard.h
===================================================================
--- branches/v4/softs/tsar_boot/include/sdcard.h	(revision 371)
+++ branches/v4/softs/tsar_boot/include/sdcard.h	(revision 371)
@@ -0,0 +1,185 @@
+/**
+ * \file sdcard.h
+ * \date 30 August 2012
+ * \author Cesar fuguet <cesar.fuguet-tortolero@lip6.fr>
+ *
+ * This file defines the driver of a SD Card device using an SPI controller
+ */
+
+#ifndef SDCARD_H
+#define SDCARD_H
+
+#include <spi.h>
+
+/**
+ * \brief SD Card type definition
+ */
+struct sdcard_dev
+{ 
+    /** 
+     * SPI controller pointer 
+     */
+    struct spi_dev * spi;
+
+    /**
+     * Capacity of the SDCARD in terms of bytes
+     */
+    unsigned int capacity;
+
+    /**
+     * Block length of the SDCARD
+     */
+    unsigned int block_length;
+
+    /**
+     * Access pointer representing the offset in bytes used
+     * to read or write in the SDCARD.
+     *
+     * \note this driver is for cards SDSD, therefore this offset
+     *       must be multiple of the block length
+     */ 
+    unsigned int access_pointer;
+
+    /**
+     * Slave ID. This ID represents the number of the slave select signal
+     * used in the hardware platform
+     */
+    int    slave_id;
+};
+
+/**
+ * \param   sdcard  : uninitialized pointer. This parameter will contain
+ *                    a pointer to the initialized block device or NULL otherwise
+ * \param   spi     : initialized pointer to the spi controller
+ * \param   ss      : slave select signal number
+ *
+ * \return  0 when initialization succeeds or an error code value otherwise.
+ *          The error codes are defined in this header file.
+ *
+ * \brief   Initialize the block device
+ */
+int sdcard_dev_open(struct sdcard_dev * sdcard, struct spi_dev * spi, int ss);
+
+/**
+ * \param   sdcard  : Pointer to the initialized block device
+ * \param   buf     : Pointer to a memory segment wherein store
+ * \param   count   : number of bytes to read
+ *
+ * \return  0 when read succeeds or an error code value otherwise.
+ *          The error codes are defined in this header file.
+ *
+ * \brief   Read in the block device
+ *
+ * The read is made in the current block device access pointer.
+ * In the read succeeds, the block device access pointer is
+ * relocated to the next block.
+ */
+int sdcard_dev_read(struct sdcard_dev * sdcard, void * buf, unsigned int count);
+
+/**
+ * \param   sdcard  : Pointer to the initialized block device
+ * \param   buf     : Pointer to a memory segment wherein the
+ * \param   count   : number of blocks to write
+ *
+ * \return  0 when write succeeds or an error code value otherwise.
+ *          The error codes are defined in this header file.
+ *
+ * \brief   Write in the block device
+ *
+ * The write is made in the current block device access pointer.
+ * In the write succeeds, the block device access pointer is
+ * relocated to the next block.
+ */
+unsigned int sdcard_dev_write(struct sdcard_dev * sdcard, void * buf, unsigned int count);
+
+/**
+ * \param   sdcard  : Pointer to the initialized block device
+ * \param   pos     : Position where the block device access
+ *                    pointer must be move
+ *
+ * \return  void
+ *
+ * \brief   Change block device access pointer position
+ *  
+ * The block device access pointer is relocated in terms of blocks
+ */
+void sdcard_dev_lseek(struct sdcard_dev * sdcard, unsigned int pos);
+
+/**
+ * \param   sdcard  : Pointer to the initialized block device
+ *
+ * \return  block device capacity
+ *
+ * \brief   Get the block device capacity
+ * 
+ * The block device access pointer is relocated in terms of blocks
+ */
+unsigned int sdcard_dev_get_capacity(struct sdcard_dev * sdcard);
+
+/**
+ * \param   sdcard  : Pointer to the initialized block device
+ * \param   len     : Block device length to set
+ *
+ * \return  0 when succeed or error code value otherwise
+ *
+ * \brief   Set the block length of the device
+ */
+int sdcard_dev_set_blocklen(struct sdcard_dev * sdcard, unsigned int len);
+
+/**
+ * SD Card constants
+ */
+
+/** Number of retries after an unacknowledge command */
+#define SDCARD_COMMAND_TIMEOUT      100
+
+/** This command is a simple SD commmand */
+#define SDCARD_CMD                  0
+
+/** This is an application specific command */
+#define SDCARD_ACMD                 1
+
+/** The transmition is done in the negative edge of the clock */
+#define SDCARD_TX_NEGEDGE           0
+
+/** The transmition is done in the positive edge of the clock */
+#define SDCARD_TX_POSEDGE           1
+
+/** The reception is done in the negative edge of the clock */
+#define SDCARD_RX_NEGEDGE           0
+
+/** The reception is done in the positive edge of the clock */
+#define SDCARD_RX_POSEDGE           1
+
+/**
+ * SD Card macros
+ */
+
+/** Check if the response is valid */
+#define SDCARD_CHECK_R1_VALID(x)    (~x & SDCARD_R1_RSP_VALID) ? 1 : 0
+
+/**
+ * Check if there is an error in the response
+ *
+ * \note this macro must be used after verify that the response is
+ *       valid
+ */
+#define SDCARD_CHECK_R1_ERROR(x)    ( x & 0x7E)                ? 1 : 0
+
+/**
+ * SD Card Response 1 (R1) format constants
+ */
+#define SDCARD_R1_IN_IDLE_STATE     ( 1 << 0 ) /**< \brief R1 bit 0 */
+#define SDCARD_R1_ERASE_RESET       ( 1 << 1 ) /**< \brief R1 bit 1 */
+#define SDCARD_R1_ILLEGAL_CMD       ( 1 << 2 ) /**< \brief R1 bit 2 */
+#define SDCARD_R1_COM_CRC_ERR       ( 1 << 3 ) /**< \brief R1 bit 3 */
+#define SDCARD_R1_ERASE_SEQ_ERR     ( 1 << 4 ) /**< \brief R1 bit 4 */
+#define SDCARD_R1_ADDRESS_ERR       ( 1 << 5 ) /**< \brief R1 bit 5 */
+#define SDCARD_R1_PARAMETER_ERR     ( 1 << 6 ) /**< \brief R1 bit 6 */
+#define SDCARD_R1_RSP_VALID         ( 1 << 7 ) /**< \brief R1 bit 7 */
+
+#endif
+
+/*
+ * vim: tabstop=4 : shiftwidth=4 : expandtab : softtabstop=4
+ */
Index: branches/v4/softs/tsar_boot/include/spi.h
===================================================================
--- branches/v4/softs/tsar_boot/include/spi.h	(revision 371)
+++ branches/v4/softs/tsar_boot/include/spi.h	(revision 371)
@@ -0,0 +1,136 @@
+/**
+ * \file  : spi.h
+ * \date  : 30 August 2012
+ * \author: Cesar Fuguet <cesar.fuguet-tortolero@lip6.fr>
+ *
+ * This file contains the definition of a driver for the SPI controller
+ */
+
+#ifndef SPI_H
+#define SPI_H
+
+#include <io.h>
+
+/**
+ * SPI type definition
+ */
+struct spi_dev
+{
+    /**
+     * RX/TX registers of the SPI controller 
+     */
+    unsigned int rx_tx[4];
+
+    /**
+     * Control register of the SPI controller
+     */
+    unsigned int ctrl;
+
+    /**
+     * Divider register for the SPI controller generated clock signal
+     */
+    unsigned int divider;
+
+    /**
+     * Slave select register of the SPI controller
+     */
+    unsigned int ss;
+};
+
+/**
+ * \param   spi     : initialized pointer to a SPI controller.
+ * \param   byte    : Byte to send to the SPI controller
+ * \param   index   : index of the TX register in the SPI (TX[index])
+ *
+ * \return  void
+ *
+ * \brief   Send a byte to one of the tx buffer registers of the
+ *          SPI controller
+ */
+void spi_put_tx(struct spi_dev * spi, unsigned char byte, int index);
+
+/**
+ * \param   spi     : initialized pointer to a SPI controller.
+ * \param   index   : index of the RX register in the SPI (RX[index])
+ *
+ * \return  byte from the RX[index] register
+ *
+ * \brief   Get a byte from one of the rx buffer registers of the
+ *          SPI controller
+ */
+inline volatile unsigned char spi_get_rx(struct spi_dev * spi, int index);
+
+/**
+ * \param   spi     : initialized pointer to a SPI controller.
+ * \param   index   : index of the slave select signal to assert
+ *
+ * \return  void
+ *
+ * \brief   Set the index selected slave select signal (ss[index] <= '0')
+ */
+inline void spi_ss_assert(struct spi_dev * spi, int index);
+
+/**
+ * \param   spi     : initialized pointer to a SPI controller.
+ * \param   index   : index of the slave select signal to deassert
+ *
+ * \return  void
+ *
+ * \brief   Unset the index selected slave select signal (ss[index] <= '0')
+ */
+inline void spi_ss_deassert(struct spi_dev * spi, int index);
+
+/**
+ * \param   spi         : initialized pointer to a SPI controller.
+ * \param   spi_freq    : SPI Master to Slave clock frequency (in Hz)
+ * \param   sys_freq    : System clock frequency (in Hz)
+ * \param   char_len    : number to bits to transmit in one transfer
+ * \param   tx_edge     : when 0, the Master Out Slave In signal is changed
+ *                        on the falling edge of the clock
+ * \param   rx_edge     : when 0, the Master In Slave Out signal is latched
+ *                        on the falling edge of the clock
+ *
+ * \return  void
+ *
+ * \brief   Configure the SPI controller
+ * \note    Any of the arguments can be less than 0 if you want to keep the old value
+ */
+void spi_dev_config (
+        struct spi_dev * spi,
+        int spi_freq	    ,
+        int sys_freq		,
+        int char_len		,
+        int tx_edge			,
+        int rx_edge			);
+
+/**
+ * SPI macros and constants
+ */
+#define SPI_TX_POSEDGE         1           /**< MOSI is changed on neg edge   */
+#define SPI_TX_NEGEDGE         0           /**< MOSI is changed on pos edge   */
+#define SPI_RX_POSEDGE         1           /**< MISO is latched on pos edge   */
+#define SPI_RX_NEGEDGE         0           /**< MISO is latched on neg edge   */
+
+#define SPI_CTRL_ASS_EN        ( 1 << 13 ) /**< Auto Slave Sel Assertion      */
+#define SPI_CTRL_IE_EN         ( 1 << 12 ) /**< Interrupt Enable              */
+#define SPI_CTRL_LSB_EN        ( 1 << 11 ) /**< LSB are sent first            */
+#define SPI_CTRL_TXN_EN        ( 1 << 10 ) /**< MOSI is changed on neg edge   */
+#define SPI_CTRL_RXN_EN        ( 1 << 9  ) /**< MISO is latched on neg edge   */
+#define SPI_CTRL_GO_BSY        ( 1 << 8  ) /**< Start the transfer            */
+#define SPI_CTRL_CHAR_LEN_MASK (  0xFF   ) /**< Bits transmited in 1 transfer */
+#define SPI_RXTX_MASK          (  0xFF   ) /**< Mask for the an RX/TX value   */
+
+ /** 
+  * \param  x   :   Initialized pointer to the SPI controller
+  *
+  * \return 1 if there is an unfinished transfer in the SPI controller
+  *
+  * Check the GO_BUSY bit of the SPI Controller
+  */
+#define SPI_IS_BUSY(x)         ((ioread32(&x->ctrl) & SPI_CTRL_GO_BSY) != 0) ? 1 : 0
+
+#endif
+
+/*
+ * vim: tabstop=4 : shiftwidth=4 : expandtab : softtabstop=4
+ */
Index: branches/v4/softs/tsar_boot/include/tty.h
===================================================================
--- branches/v4/softs/tsar_boot/include/tty.h	(revision 371)
+++ branches/v4/softs/tsar_boot/include/tty.h	(revision 371)
@@ -0,0 +1,23 @@
+#ifndef TTY_REGS_H
+#define TTY_REGS_H
+
+enum SoclibTtyRegisters {
+    TTY_WRITE   = 0,
+    TTY_STATUS  = 1,
+    TTY_READ    = 2,
+    TTY_CONFIG  = 3,
+    /**/
+    TTY_SPAN    = 4,
+};
+
+#endif
+
+// Local Variables:
+// tab-width: 4;
+// c-basic-offset: 4;
+// c-file-offsets:((innamespace . 0)(inline-open . 0));
+// indent-tabs-mode: nil;
+// End:
+//
+// vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4
+
Index: branches/v4/softs/tsar_boot/src/boot_elf_loader.c
===================================================================
--- branches/v4/softs/tsar_boot/src/boot_elf_loader.c	(revision 371)
+++ branches/v4/softs/tsar_boot/src/boot_elf_loader.c	(revision 371)
@@ -0,0 +1,266 @@
+/**
+ * \file    : boot_loader_entry.c
+ * \date    : August 2012
+ * \author  : Cesar Fuguet
+ *
+ * This file defines an elf file loader which reads an executable elf file
+ * starting at a sector passed as argument of a disk and copy the different
+ * ELF program segments in the appropriate memory address using as information
+ * the virtual address read from the elf file.
+ */
+
+#include <boot_ioc.h>
+#include <elf-types.h>
+#include <boot_tty.h>
+#include <boot_memcpy.h>
+#include <defs.h>
+
+void * boot_elf_loader(unsigned int lba)
+{
+    /**
+     * Temporary variables used by the boot loader
+     */
+    unsigned char   boot_elf_loader_buffer[512];
+    Elf32_Ehdr      elf_header;
+    Elf32_Phdr      elf_pht[PHDR_ARRAY_SIZE];
+
+    unsigned char * buffer_ptr;
+    Elf32_Ehdr    * elf_header_ptr;
+    Elf32_Phdr    * elf_pht_ptr;
+
+    unsigned int nb_available;
+    unsigned int nb_rest;
+    unsigned int nb_read;
+    unsigned int nb_block;
+    unsigned int offset;
+    unsigned int pseg;
+    unsigned int i;
+    unsigned int segment_req;
+   
+    /*
+     * Loader state machine definition
+     */  
+    enum
+    {
+        ELF_HEADER_STATE,
+        ELF_PROGRAM_HEADER_STATE,
+        ELF_OFFSET_STATE,
+        ELF_SEGMENT_STATE,
+        ELF_END_STATE
+    } init_state;
+
+    boot_puts("Starting boot_elf_loader function...\n\r");
+
+    nb_block           = lba;
+
+    pseg               = 0;
+    nb_available       = 0;
+    nb_rest            = sizeof(Elf32_Ehdr);
+    offset             = 0;
+
+    elf_header_ptr     = (Elf32_Ehdr *) &elf_header;
+    elf_pht_ptr        = (Elf32_Phdr *) &elf_pht[0];
+
+    init_state         = ELF_HEADER_STATE;
+
+    while(init_state != ELF_END_STATE)
+    {
+        if (nb_available == 0)
+        {
+            buffer_ptr = &boot_elf_loader_buffer[0];
+
+            if ( boot_ioc_read(nb_block , buffer_ptr, 1) )
+            {
+                boot_puts (
+					"ERROR: "
+					"IOC_FAILED"
+					"\n"
+				);
+
+                boot_exit();
+            }
+           
+            nb_block    += 1;
+            nb_available = 512;
+        }
+
+        nb_read  = (nb_rest <= nb_available) ? nb_rest : nb_available;
+        offset  +=  nb_read;
+
+        switch(init_state)
+        {
+            /**
+             * Reading ELF executable header
+             */
+            case ELF_HEADER_STATE:
+                boot_memcpy(elf_header_ptr, buffer_ptr, nb_read);
+
+                nb_rest -= nb_read;
+
+                if(nb_rest == 0)
+                {
+                    nb_rest = elf_header_ptr->e_phnum * elf_header_ptr->e_phentsize;
+
+					/* Verification of ELF Magic Number */
+					if (
+						(elf_header_ptr->e_ident[EI_MAG0] != ELFMAG0) ||
+						(elf_header_ptr->e_ident[EI_MAG1] != ELFMAG1) ||
+						(elf_header_ptr->e_ident[EI_MAG2] != ELFMAG2) ||
+						(elf_header_ptr->e_ident[EI_MAG3] != ELFMAG3) )
+					{
+						boot_puts(
+							"ERROR: "
+							"Input file does not use ELF format"
+							"\n"
+						);	
+
+						boot_exit();
+					}
+
+					/* 
+					 * Verification of Program Headers table size. It must be
+					 * smaller than the work size allocated for the 
+					 * elf_pht[PHDR_ARRAY_SIZE] array
+					 **/
+                    if (elf_header_ptr->e_phnum > PHDR_ARRAY_SIZE)
+                    {
+                        boot_puts(
+							"ERROR: "
+							"ELF PHDR table size is bigger than "
+							"the allocated work space"
+							"\n"
+						);
+
+                        boot_exit();
+                    }
+
+                    init_state = ELF_PROGRAM_HEADER_STATE;
+                }
+
+                break;
+
+            /**
+             * Reading ELF program headers
+             */  
+            case ELF_PROGRAM_HEADER_STATE:
+                boot_memcpy(elf_pht_ptr, buffer_ptr, nb_read);
+
+                elf_pht_ptr = (Elf32_Phdr *)((unsigned char *) elf_pht_ptr + nb_read);
+                nb_rest    -= nb_read;
+
+                if(nb_rest == 0)
+                {
+                    elf_pht_ptr = (Elf32_Phdr *) &elf_pht[0];
+
+                    /*
+                     * Search the first not NULL segment in the ELF file
+                     */
+                    for (pseg = 0; pseg < elf_header_ptr->e_phnum; pseg++)
+                    {
+                        if(elf_pht_ptr[pseg].p_type == PT_LOAD)
+                        {
+                            nb_rest = elf_pht_ptr[pseg].p_offset - offset;
+                            break;
+                        }
+                    }
+
+                    init_state = ELF_OFFSET_STATE;
+                }
+
+                break;
+
+            /**
+             * Go to the offset of the first not null program segment in the ELF file
+             */
+            case ELF_OFFSET_STATE:
+                nb_rest -= nb_read;
+
+                if (nb_rest == 0)
+                {
+                    nb_rest    = elf_pht_ptr[pseg].p_filesz;
+                    init_state = ELF_SEGMENT_STATE;
+                }
+
+                break;
+
+            /**
+             * Reading ELF segments
+             */
+            case ELF_SEGMENT_STATE:
+                /**
+                 * Copying ELF segment data in memory segments using the virtual
+                 * address got from the ELF file
+                 */ 
+                segment_req = ((elf_pht_ptr[pseg].p_vaddr & 0xBFC00000) != 0xBFC00000);
+
+                if ( segment_req )
+                {
+                    boot_memcpy((unsigned char *) elf_pht_ptr[pseg].p_vaddr +
+                                (elf_pht_ptr[pseg].p_filesz - nb_rest),
+                                buffer_ptr,
+                                nb_read);
+                }
+    
+                nb_rest -= nb_read;
+
+                if ( nb_rest == 0 )
+                {
+                    if ( segment_req )
+                    {
+                        boot_puts("Copied segment at address ");
+                        boot_putx(elf_pht_ptr[pseg].p_vaddr);
+                        boot_puts("\n");
+
+                        /*
+                         * Fill remaining bytes with zeros (filesz < memsz)
+                         */
+                        for ( i = 0                                                        ;
+                              i < (elf_pht_ptr[pseg].p_memsz - elf_pht_ptr[pseg].p_filesz) ;
+                              i--                                                          )
+                        {
+                            *(unsigned char *)
+                            (elf_pht_ptr[pseg].p_vaddr + elf_pht_ptr[pseg].p_filesz + i) = 0;
+                        }
+                    }
+
+                    /*
+                     * Search the first not NULL segment in the ELF file
+                     */
+                    for ( pseg = pseg + 1; pseg < elf_header_ptr->e_phnum; pseg++) {
+                        if(elf_pht_ptr[pseg].p_type == PT_LOAD)
+                        {
+                            nb_rest = elf_pht_ptr[pseg].p_offset - offset;
+                            break;
+                        }
+                    }
+
+                    /*
+                     * Program loading finished
+                     */ 
+                    if(pseg == elf_header_ptr->e_phnum)
+                    {
+                        init_state = ELF_END_STATE;
+                        break;
+                    }
+
+                    init_state = ELF_OFFSET_STATE;
+                }
+                break;
+
+            default:
+                break;
+        }
+
+        buffer_ptr              += nb_read;
+        nb_available            -= nb_read;
+    }
+
+    boot_puts (
+		"Finishing boot_elf_loader function.\n"
+		"Entry point address: "
+	);
+    boot_putx(elf_header_ptr->e_entry);
+    boot_puts("\n");
+
+    return ((void *) elf_header_ptr->e_entry);
+}
Index: branches/v4/softs/tsar_boot/src/boot_ioc.c
===================================================================
--- branches/v4/softs/tsar_boot/src/boot_ioc.c	(revision 371)
+++ branches/v4/softs/tsar_boot/src/boot_ioc.c	(revision 371)
@@ -0,0 +1,197 @@
+#include <boot_ioc.h>
+
+#ifndef SOCLIB_IOC
+
+#ifndef SYSCLK_FREQ
+#warning "Using default value for SYSCLK_FREQ = 50000000"
+#define SYSCLK_FREQ 50000000U
+#endif
+
+static struct sdcard_dev  _sdcard_device;
+static struct spi_dev   * _spi_device   = ( struct spi_dev * )IOC_BASE;
+#endif
+
+
+int boot_ioc_init()
+{
+#ifdef SOCLIB_IOC
+    return 0;
+#else
+    unsigned char sdcard_rsp;
+
+    boot_puts("Initializing block device\n\r");
+
+    /**
+     * Initializing the SPI controller
+     */
+    spi_dev_config (
+      _spi_device   ,
+      200000        , /**< SPI_clk: 200 Khz */
+      SYSCLK_FREQ   , /**< Sys_clk          */
+      8             , /**< Charlen: 8       */
+      SPI_TX_NEGEDGE,
+      SPI_RX_POSEDGE
+    ); 
+
+    /**
+     * Initializing the SD Card
+     */
+    if ( (sdcard_rsp = sdcard_dev_open(&_sdcard_device, _spi_device, 0)) )
+        return sdcard_rsp;
+
+    if ( (sdcard_rsp = sdcard_dev_set_blocklen(&_sdcard_device, 512)) )
+        return sdcard_rsp;
+
+    /**
+     * Incrementing SDCARD clock frequency for normal function
+     */
+    spi_dev_config (
+        _spi_device ,
+        10000000    , /**< SPI_clkL 10 Mhz */
+        SYSCLK_FREQ , /**< Sys_clk         */
+        -1          , /**< Charlen: 8      */
+        -1          ,
+        -1
+    );
+
+    boot_puts("Finish block device initialization\n\r");
+
+    return 0;
+#endif
+}
+
+/**
+ * _boot_ioc_completed()
+ *
+ * This blocking function checks completion of an I/O transfer and reports errors.
+ *
+ * \note It returns 0 if the transfer is successfully completed.
+ *       It returns -1 if an error has been reported.
+ */
+#ifdef SOCLIB_IOC
+static int _boot_ioc_completed()
+{
+    unsigned int status = 0;
+
+
+    unsigned int * ioc_address = ( unsigned int * )VCIBD_BASE;
+  
+    while ( 1 )
+    { 
+        status = ioread32(&ioc_address[BLOCK_DEVICE_STATUS]);
+
+        if (( status == BLOCK_DEVICE_READ_SUCCESS ) ||
+            ( status == BLOCK_DEVICE_READ_ERROR  ))
+        break;
+    }
+    
+    return status;
+}
+#endif
+
+/**
+ * boot_ioc_read()
+ * 
+ * Transfer data from a file on the block device to a memory buffer.
+ *
+ * \param lba    : first block index on the disk
+ * \param buffer : base address of the memory buffer
+ * \param count  : number of blocks to be transfered
+ *
+ * \note This is a blocking function. The function returns once the transfer
+ *       has finished
+ */
+
+#ifdef SOCLIB_IOC
+///////////////////////////////////////////////////////////////////////////////
+// SOCLIB version of the boot_ioc_read function
+
+int boot_ioc_read(unsigned int lba, void* buffer, unsigned int count)
+{
+
+    unsigned int * ioc_address  = (unsigned int*)VCIBD_BASE;
+
+    // block_device configuration
+    iowrite32( &ioc_address[BLOCK_DEVICE_BUFFER],
+            ( unsigned int ) buffer );
+
+    iowrite32( &ioc_address[BLOCK_DEVICE_COUNT],
+            ( unsigned int ) count );
+
+    iowrite32( &ioc_address[BLOCK_DEVICE_LBA],
+            ( unsigned int ) lba );
+
+    iowrite32( &ioc_address[BLOCK_DEVICE_IRQ_ENABLE],
+            ( unsigned int ) 0 );
+
+    iowrite32( &ioc_address[BLOCK_DEVICE_OP],
+            ( unsigned int ) BLOCK_DEVICE_READ );
+
+    _boot_ioc_completed();
+
+#if (CACHE_COHERENCE == 0)
+    boot_dbuf_invalidate(buffer, CACHE_LINE_SIZE, count * 512);
+#endif
+    return 0;
+}
+
+#else
+///////////////////////////////////////////////////////////////////////////////
+// FPGA version of the boot_ioc_read function
+
+int boot_ioc_read(unsigned int lba, void* buffer, unsigned int count)
+{
+    unsigned int sdcard_rsp;
+
+    sdcard_dev_lseek(&_sdcard_device, lba);
+
+    unsigned int i;
+    for(i = 0; i < count; i++)
+    {
+        if (( sdcard_rsp = sdcard_dev_read (
+                        &_sdcard_device,
+                        (unsigned char *) buffer + (512 * i),
+                        512
+                        ) 
+            ))
+        {
+            boot_puts("ERROR during read on the SDCARD device. Code: "); 
+            boot_putx(sdcard_rsp);
+            boot_puts("\n\r");
+
+            return 1;
+        }   
+    }
+
+    return 0;
+}
+#endif
+
+/**
+ * _dcache_buf_invalidate()
+ *
+ * Invalidate all data cache lines corresponding to a memory 
+ * buffer (identified by an address and a size).
+ */
+#if (CACHE_COHERENCE == 0)
+void boot_dbuf_invalidate (
+        const void * buffer,
+        unsigned int line_size,
+        unsigned int size)
+{
+    unsigned int i;
+
+    // iterate on cache lines 
+    for (i = 0; i < size; i += line_size) {
+        asm volatile(
+            " cache %0, %1"
+            :// no outputs
+            :"i" (0x11), "R" (*((unsigned char *) buffer + i))
+            );
+    }
+}
+#endif
+
+/*
+ * vim: tabstop=4 : shiftwidth=4 : expandtab
+ */
Index: branches/v4/softs/tsar_boot/src/boot_memcpy.c
===================================================================
--- branches/v4/softs/tsar_boot/src/boot_memcpy.c	(revision 371)
+++ branches/v4/softs/tsar_boot/src/boot_memcpy.c	(revision 371)
@@ -0,0 +1,21 @@
+#include <boot_memcpy.h>
+
+void * boot_memcpy(void *_dst, const void *_src, unsigned int size)
+{
+    unsigned int *dst = _dst;
+    const unsigned int *src = _src;
+    if ( ! ((unsigned int)dst & 3) && ! ((unsigned int)src & 3) )
+        while (size > 3) {
+            *dst++ = *src++;
+            size -= 4;
+        }
+
+    unsigned char *cdst = (unsigned char*) dst;
+    unsigned char *csrc = (unsigned char*) src;
+
+    while (size--) {
+        *cdst++ = *csrc++;
+    }
+    return _dst;
+}
+
Index: branches/v4/softs/tsar_boot/src/boot_tty.c
===================================================================
--- branches/v4/softs/tsar_boot/src/boot_tty.c	(revision 371)
+++ branches/v4/softs/tsar_boot/src/boot_tty.c	(revision 371)
@@ -0,0 +1,91 @@
+#include <boot_tty.h>
+#include <defs.h>
+
+int boot_getc(char *c)
+{
+    unsigned int* tty_address = (unsigned int*) TTY_BASE;
+    if (ioread32(&tty_address[TTY_STATUS]) == 0)
+        return 0;
+
+    *c = ioread32(&tty_address[TTY_READ]);
+    return 1;
+}
+
+void boot_putc(const char c)
+{
+    unsigned int* tty_address = (unsigned int*) TTY_BASE;
+    iowrite32(&tty_address[TTY_WRITE], (unsigned int)c);
+
+    if (c == '\n')
+    {
+        iowrite32(&tty_address[TTY_WRITE], (unsigned int)'\r');
+    }
+}
+
+void boot_puts(const char *buffer) 
+{
+    unsigned int n;
+
+    for ( n=0; n<100; n++)
+    {
+        if (buffer[n] == 0) break;
+
+        boot_putc(buffer[n]);
+    }
+} 
+
+void boot_putx(unsigned int val)
+{
+    static const char HexaTab[] = "0123456789ABCDEF";
+    char              buf[11];
+    unsigned int      c;
+
+    buf[0]  = '0';
+    buf[1]  = 'x';
+    buf[10] = 0;
+
+    for ( c = 0 ; c < 8 ; c++ )
+    { 
+        buf[9-c] = HexaTab[val&0xF];
+        val = val >> 4;
+    }
+    boot_puts(buf);
+}
+
+void boot_putd(unsigned int val)
+{
+    static const char DecTab[] = "0123456789";
+    char              buf[11];
+    unsigned int      i;
+    unsigned int      first = 0;
+
+    buf[10] = 0;
+
+    for ( i = 0 ; i < 10 ; i++ )
+    {
+        if ((val != 0) || (i == 0))
+        {
+            buf[9-i] = DecTab[val % 10];
+            first    = 9-i;
+        }
+        else
+        {
+            break;
+        }
+        val /= 10;
+    }
+    boot_puts( &buf[first] );
+}
+
+void boot_exit()
+{
+    register int pid;
+    asm volatile( "mfc0 %0, $15, 1": "=r"(pid) );
+
+    boot_puts("\n!!! Exit Processor ");
+    boot_putx(pid);
+    boot_puts(" !!!\n");
+
+    while(1) asm volatile("nop");   // infinite loop...
+}
+
Index: branches/v4/softs/tsar_boot/src/exceptions.c
===================================================================
--- branches/v4/softs/tsar_boot/src/exceptions.c	(revision 371)
+++ branches/v4/softs/tsar_boot/src/exceptions.c	(revision 371)
@@ -0,0 +1,23 @@
+/**
+ * \file    : exceptions.c
+ * \date    : December 2012
+ * \author  : Manuel Bouyer
+ *
+ * This file defines a simple exeptions handler
+ */
+
+#include <boot_tty.h>
+
+void handle_except(int status, int cause, int epc)
+{
+	boot_puts("boot (default) exeption handler called: \r\n    status ");
+	boot_putx(status);
+	boot_puts("\r\n    cause  ");
+	boot_putx(cause);
+	boot_puts(" (exeption ");
+	boot_putx((cause >> 2) & 0x1f);
+	boot_puts(")\r\n    epc    ");
+	boot_putx(epc);
+	boot_puts("\r\n");
+	while (1);
+}
Index: branches/v4/softs/tsar_boot/src/reset.S
===================================================================
--- branches/v4/softs/tsar_boot/src/reset.S	(revision 371)
+++ branches/v4/softs/tsar_boot/src/reset.S	(revision 371)
@@ -0,0 +1,218 @@
+/**
+ * \file  : reset.S
+ * \date  : 01/12/2012
+ * \author: Cesar FUGUET & Manuel BOUYER & Alain Greiner
+ *
+ * This is a boot code for a generic multi-clusters / multi-processors
+ * TSAR architecture (up to 256 clusters / up to 4  processors per cluster). 
+ * There is one XICU, one TTY, one DMA and one stack segment per cluster.
+ * segment base adresses = base + cluster_segment_increment*cluster_id
+ *
+ * - Each processor initializes the Status Register (SR) to disable interrupts.
+ * - Each processor initializes the Count Register.
+ * - Each processor initialises its private XICU Write Triggered Interruption
+ *   mask register.
+ * - Only processor 0 initializes the stack pointer ($29).
+ * - Only processor 0 (boot processor) executes the boot_load_elf function to
+ *   load in memory the boot loader stored in the block BOOT_LOADER_LBA of 
+ *   the disk.
+ * - All non-boot processors wait in a low power consumption mode that the
+ *   processor 0 wakes them using the IPI (Inter Processor Interruption)
+ *   functionality of the XICU device.
+ */
+
+    #include <defs.h>
+    #include <mips32_registers.h>
+
+    .section .boot,"ax",@progbits
+
+    .extern seg_stack_base
+
+    .extern dtb_addr
+    .extern boot_putc
+    .extern boot_getc
+    .extern boot_ioc_read
+    .extern boot_elf_loader
+    .extern boot_memcpy
+    .extern boot_puts
+    .extern boot_putx
+    .extern boot_putd
+    .extern boot_ioc_init
+
+    .globl  boot                    /* Make reset an external symbol */
+    .ent    boot
+
+    .align  2
+    .set noreorder
+
+boot:
+    b       _boot                   /* 0xbfc0000 */
+    nop                             /* 0xbfc0004 */
+
+    /*  Addresses of the functions provided by this pre-loader */
+
+    .word   BOOT_VERSION            /* 0xbfc0008 */
+    .word   dtb_addr                /* 0xbfc000c */
+    .word   boot_putc               /* 0xbfc0010 */
+    .word   boot_getc               /* 0xbfc0014 */
+    .word   boot_ioc_read           /* 0xbfc0018 */
+    .word   boot_elf_loader         /* 0xbfc001C */
+    .word   boot_memcpy             /* 0xbfc0020 */
+    .word   boot_puts               /* 0xbfc0024 */
+    .word   boot_putx               /* 0xbfc0028 */
+    .word   boot_putd               /* 0xbfc002C */
+
+_boot:
+    /* Disable interruptions, keep STATUSbev enabled */
+
+    li      k0,     (1 << 22)
+    mtc0    k0,     CP0_STATUS
+
+    /* Computes proc_id, local_id, cluster_id, and cluster_increment */
+
+    mfc0    k0,     CP0_EBASE
+    andi    t0,     k0,     0x3FF   /* t0 <= proc_id (at most 1024 processors)    */
+
+    move    t3,     t0
+
+    la      k0,     NB_PROCS        /* k0 <= number of processors per cluster     */
+    divu    t3,     k0
+    mfhi    t1                      /* t1 <= local_id   = proc_id % NB_PROCS      */
+    mflo    t2                      /* t2 <= cluster_id = proc_id / NB_PROCS      */
+
+    la      k0,     NB_CLUSTERS
+    li      t3,     0x80000000
+    divu    t3,     k0
+    mflo    t4
+    sll     t4,     1               /* t4 <= cluster_increment = 4G / NB_CLUSTERS */
+
+    mult    t4,     t2 
+    mflo    t5                      /* t5 <= cluster_id * cluster_increment       */
+ 
+    /* Initialization of the count register in the coprocessor 0 */
+
+    mtc0    zero,   CP0_COUNT
+
+    /* In each cluster, the ICU base address depends on the cluster_id */
+
+    la      t3,     ICU_BASE
+    addu    t3,     t3,     t5      /* t3 <= ICU_BASE +                       */
+                                    /*       (cluster_id * cluster_increment) */
+
+    /**
+     * Compute the output index for the Write Triggered Interruption mask. 
+     * Each processor enable the WTI for its irq output 
+     * Each processor may have IRQ_PER_PROC private irq outputs from
+     * the XICU
+     */
+
+    move    t4,     t1              /* t4 <= local_id                   */
+    li      t5,     IRQ_PER_PROC    /* t5 <= IRQ_PER_PROC               */
+    multu   t4,     t5              
+    mflo    t6                      /* t6 <= IRQ_PER_PROC * local_id    */
+    sll     t4,     t6,     2       /* t4 <= OUT_INDEX = t6 * 4         */
+
+    li      t5,     (0xC << 7)      /* t5 <= FUNC      = XICU_MSK_WTI   */
+    or      t4,     t4,     t5      /* t4 <= FUNC | INDEX | 00          */
+    or      t5,     t3,     t4      /* t5 <= &XICU[MSK_WTI][OUT_INDEX]  */
+    
+    /* Compute and set WTI mask */
+
+    li      t4,     1
+    sllv    t4,     t4,     t1      /* Set XICU[MSK_WTI][INDEX][local_id] */
+    sw      t4,     0(t5)           /* XICU[MSK_WTI][INDEX] <= t4         */
+
+    /**
+     * We have:
+     * t0: global id
+     * t1: local id
+     * t2: cluster id
+     * t3: xicu base address
+     * 
+     * Only processor 0 in cluster 0 executes the boot loader 
+     */
+
+    bne     zero,   t0,     _reset_wait
+    nop
+
+    /* Initializes stack pointer */
+
+    la      k1,     seg_stack_base
+    li      k0,     BOOT_STACK_SIZE
+    addu    sp,     k1,     k0      /* sp <= seg_stack_base + BOOT_STACK_SIZE */
+
+#ifndef SOCLIB_IOC
+
+    /* Initialize the block device */
+
+    la      k0,     boot_ioc_init
+    jalr    k0
+    nop
+
+#endif
+
+    /**
+     * Jump to the boot elf loader routine 
+     * Passing as argument the block number in which it must be
+     * the executable elf file to load
+     */
+
+    la      k0,     boot_elf_loader
+    li      a0,     BOOT_LOADER_LBA
+    jalr    k0
+    nop
+
+    /** 
+     * We jump to the entry point address defined in the 
+     * ELF file. This address is returned by boot_elf_loader function.
+     * All function arguments are 0
+     */
+
+    move    a0,     zero
+    move    a1,     zero
+    move    a2,     zero
+    move    a3,     zero
+    jr      v0
+    nop
+
+/**
+ * Wait in low power consumption mode until the application wakes us.
+ * The application wakes up the non-boot CPUs using a IPI with a non-0
+ * value in the mailbox. This non-0 value is the address to jump to.
+ */
+
+_reset_wait:
+    /**
+     * We have:
+     * t0: global id
+     * t1: local id
+     * t2: cluster id
+     * t3: xicu base address
+     */
+
+    sll     t4,     t1,     2       /* t4 <= local_id * 4             */
+    addu    t5,     t4,     t3      /* t5 <= &XICU[WTI_REG][local_id] */
+
+    wait
+
+    lw      k0,     0(t5)           /* k0 <= XICU[WTI_REG][local_id]  */
+    jr      k0
+    nop
+
+/* Exception entry point */
+.org 0x0380
+_excep:
+    mfc0    a0, CP0_STATUS          /* first arg is status */
+    mfc0    a1, CP0_CAUSE           /* second arg is cause */
+    mfc0    a2, CP0_EPC             /* third argc is epc   */
+    nop
+    j       handle_except
+    nop
+
+    .end boot
+
+    .set reorder
+
+/*
+ * vim: tabstop=4 : shiftwidth=4 : expandtab
+ */
Index: branches/v4/softs/tsar_boot/src/sdcard.c
===================================================================
--- branches/v4/softs/tsar_boot/src/sdcard.c	(revision 371)
+++ branches/v4/softs/tsar_boot/src/sdcard.c	(revision 371)
@@ -0,0 +1,291 @@
+/**
+ * \file    : sdcard.c
+ * \date    : 30 August 2012
+ * \author  : Cesar Fuguet
+ *
+ * This file defines the driver of a SD Card device using an SPI controller
+ */
+
+#include <sdcard.h>
+
+/**
+ * \param   sdcard: Initialized pointer to the block device
+ *
+ * \return  void
+ *
+ * \brief   Enable SD Card select signal
+ */
+static void _sdcard_enable(struct sdcard_dev * sdcard)
+{
+    spi_ss_assert(sdcard->spi, sdcard->slave_id);
+}
+
+/**
+ * \param   sdcard: Initialized pointer to the block device
+ *
+ * \return  void
+ *
+ * \brief   Disable SD Card select signal
+ */
+static void _sdcard_disable(struct sdcard_dev * sdcard)
+{
+    spi_ss_deassert(sdcard->spi, sdcard->slave_id);
+}
+
+/**
+ * \param   tick_count: SD Card clock ticks number
+ *
+ * \return  void
+ *
+ * \brief   Enable SD Card clock
+ *          The tick count is byte measured (1 tick, 8 clock)
+ */
+static void _sdcard_gen_tick(struct sdcard_dev * sdcard, unsigned int tick_count)
+{
+    volatile register int i = 0;
+    while(i++ < tick_count) spi_put_tx(sdcard->spi, 0xFF, 0);
+}
+
+/**
+ * \param   sdcard: Initialized pointer to the block device
+ *
+ * \return  char from the SD card
+ *
+ * \brief   Get a byte from the SD Card
+ */
+static unsigned char _sdcard_receive_char(struct sdcard_dev * sdcard)
+{
+    _sdcard_gen_tick(sdcard, 1);
+
+    return spi_get_rx(sdcard->spi, 0);
+}
+
+/**
+ * \param   sdcard: Initialized pointer to the block device
+ *
+ * \return  sdcard response
+ *
+ * \brief   Wait for a valid response after the send of a command
+ *          This function can return if one of the next two conditions are true:
+ *           1. Bit valid received
+ *           2. Timeout (not valid bit received after SDCARD_COMMAND_TIMEOUT
+ *              wait ticks)
+ */
+static unsigned char _sdcard_wait_response(struct sdcard_dev * sdcard)
+{
+    unsigned char sdcard_rsp;
+    register int  iter;
+
+    iter       = 0;
+    sdcard_rsp = _sdcard_receive_char(sdcard);
+    while (
+            (iter < SDCARD_COMMAND_TIMEOUT) &&
+            !SDCARD_CHECK_R1_VALID(sdcard_rsp)
+          )
+    {
+        sdcard_rsp = _sdcard_receive_char(sdcard);
+        iter++;
+    }
+
+    return sdcard_rsp;
+}
+
+/**
+ * \params  sdcard: Initialized pointer to the block device
+ *
+ * \return  void
+ *
+ * \brief   Wait data block start marker
+ */
+static void _sdcard_wait_data_block(struct sdcard_dev * sdcard)
+{
+	while (_sdcard_receive_char(sdcard) != 0xFE);
+}
+
+/**
+ * \param   sdcard  : Initialized pointer to block device
+ * \param   index   : SD card CMD index
+ * \param   app     : Type of command, 0 for normal command or 1 for application specific
+ * \param   args    : SD card CMD arguments
+ *
+ * \return  response first byte
+ *
+ * \brief   Send command to the SD card
+ */
+static int _sdcard_send_command    (
+        struct sdcard_dev * sdcard ,
+        int                 index  ,
+        int                 app    ,
+        void *              args   ,
+        unsigned            crc7   )
+{
+    unsigned char sdcard_rsp;
+    unsigned char * _args;
+
+    _sdcard_gen_tick(sdcard, 5);  
+
+    if (app == SDCARD_ACMD)
+    {
+        spi_put_tx(sdcard->spi, 0x40 | 55         , 0 );/* CMD and START bit */
+        spi_put_tx(sdcard->spi, 0x00              , 0 );/* Argument[0]       */
+        spi_put_tx(sdcard->spi, 0x00              , 0 );/* Argument[1]       */
+        spi_put_tx(sdcard->spi, 0x00              , 0 );/* Argument[2]       */
+        spi_put_tx(sdcard->spi, 0x00              , 0 );/* Argument[3]       */
+        spi_put_tx(sdcard->spi, 0x01 | (crc7 << 1), 0 );/* END bit           */
+
+        sdcard_rsp = _sdcard_wait_response(sdcard);
+        if (SDCARD_CHECK_R1_ERROR(sdcard_rsp))
+        {
+            return sdcard_rsp;        
+        }
+    }
+
+    _args = (unsigned char *) args;
+
+    _sdcard_gen_tick(sdcard, 1);  
+
+    spi_put_tx(sdcard->spi, 0x40 | index      , 0 );
+    spi_put_tx(sdcard->spi, _args[0]          , 0 );
+    spi_put_tx(sdcard->spi, _args[1]          , 0 );
+    spi_put_tx(sdcard->spi, _args[2]          , 0 );
+    spi_put_tx(sdcard->spi, _args[3]          , 0 );
+    spi_put_tx(sdcard->spi, 0x01 | (crc7 << 1), 0 );
+
+    return _sdcard_wait_response(sdcard);
+}
+
+int sdcard_dev_open(struct sdcard_dev * sdcard, struct spi_dev * spi, int ss)
+{
+    unsigned char args[4];
+	unsigned char sdcard_rsp;
+	unsigned int  iter;
+
+	sdcard->spi      = spi;
+    sdcard->slave_id = ss;
+
+	/* 
+     * Supply SD card ramp up time (min 74 cycles)
+     */
+	_sdcard_gen_tick(sdcard, 10);
+
+    /* 
+     * Assert slave select signal
+     * Send CMD0 (Reset Command)
+     * Deassert slave select signal
+     */
+	_sdcard_enable(sdcard);
+
+    args[0] = 0;
+    args[1] = 0;
+    args[2] = 0;
+    args[3] = 0;
+	sdcard_rsp = _sdcard_send_command(sdcard, 0, SDCARD_CMD, args, 0x4A);
+	if ( sdcard_rsp != 0x01 )
+	{
+		return sdcard_rsp;
+	}
+
+	_sdcard_disable(sdcard);
+	_sdcard_enable(sdcard);
+
+	iter = 0;
+	while( iter++ < SDCARD_COMMAND_TIMEOUT )
+	{
+		sdcard_rsp = _sdcard_send_command(sdcard, 41, SDCARD_ACMD, args, 0x00);
+		if( sdcard_rsp == 0x01 )
+		{
+			continue;
+		}
+
+		break;
+	}
+
+	_sdcard_disable(sdcard);
+
+	return sdcard_rsp;
+}
+
+int sdcard_dev_read(struct sdcard_dev * sdcard, void * buf, unsigned int count)
+{
+    unsigned char args[4];
+    unsigned char sdcard_rsp;
+    register int  i;
+
+    for (i = 0; i < 4; i++)
+        args[i] = (sdcard->access_pointer >> (32 - (i+1)*8)) & 0xFF;
+
+    _sdcard_enable(sdcard);
+
+    sdcard_rsp = _sdcard_send_command(sdcard, 17, SDCARD_CMD, args, 0x00);
+    if ( SDCARD_CHECK_R1_ERROR(sdcard_rsp) )
+    {
+        _sdcard_disable(sdcard);
+        return sdcard_rsp;
+    }
+
+    _sdcard_wait_data_block(sdcard);
+
+    for ( i = 0; i < count; i++ )
+    {
+        *((char *) buf + i) = _sdcard_receive_char(sdcard);
+    }
+
+    /*
+     * Get the remainder of the block bytes and the CRC16 (comes
+     * at the end of the data block)
+     */
+    while( i++ < (sdcard->block_length + 2) ) _sdcard_receive_char(sdcard);
+
+    _sdcard_disable(sdcard);
+
+    /*
+     * Move the access pointer to the next block
+     */
+    sdcard->access_pointer += sdcard->block_length;
+
+    return 0;
+}
+
+unsigned int sdcard_dev_write(struct sdcard_dev *sdcard, void * buf, unsigned int count)
+{
+	return 0;
+}
+
+void sdcard_dev_lseek(struct sdcard_dev * sdcard, unsigned int blk_pos)
+{
+    sdcard->access_pointer = sdcard->block_length * blk_pos;
+}
+
+unsigned int sdcard_dev_get_capacity(struct sdcard_dev * sdcard)
+{
+	return sdcard->capacity;
+}
+
+int sdcard_dev_set_blocklen(struct sdcard_dev * sdcard, unsigned int len)
+{
+    unsigned char args[4];
+    unsigned char sdcard_rsp;
+    register int i;
+
+    for (i = 0; i < 4; i++)
+        args[i] = (len >> (32 - (i+1)*8)) & 0xFF;
+
+    _sdcard_enable(sdcard);
+
+    sdcard_rsp = _sdcard_send_command(sdcard, 16, SDCARD_CMD, args, 0x00);
+    if ( SDCARD_CHECK_R1_ERROR(sdcard_rsp) )
+    {
+        _sdcard_disable(sdcard);
+        return sdcard_rsp;
+    }
+
+    _sdcard_disable(sdcard);
+
+    sdcard->block_length = len;
+
+	return 0;
+}
+
+/*
+ * vim: tabstop=4 : shiftwidth=4 : expandtab : softtabstop=4
+ */
Index: branches/v4/softs/tsar_boot/src/spi.c
===================================================================
--- branches/v4/softs/tsar_boot/src/spi.c	(revision 371)
+++ branches/v4/softs/tsar_boot/src/spi.c	(revision 371)
@@ -0,0 +1,111 @@
+/*
+ * \file    spi.c
+ * \data    31 August 2012
+ * \author  Cesar Fuguet <cesar.fuguet-tortolero@lip6.fr>
+ */
+#include <spi.h>
+
+/**
+ * \param   spi :   Initialized pointer to the SPI controller
+ *
+ * \brief   Wait until the SPI controller has finished a transfer
+ *
+ * Wait until the GO_BUSY bit of the SPI controller be deasserted
+ */
+static void _spi_wait_if_busy(struct spi_dev * spi)
+{
+    volatile register int delay;
+
+    while(SPI_IS_BUSY(spi))
+    {
+        for (delay = 0; delay < 10000; delay++);
+    }
+}
+
+/**
+ * \param   spi : Initialized pointer to the SPI controller
+ *
+ * \return  void
+ *
+ * \brief   Init transfer of the tx registers to the selected slaves
+ */
+static void _spi_init_transfer(struct spi_dev * spi)
+{
+    unsigned int spi_ctrl = ioread32(&spi->ctrl);
+
+    iowrite32(&spi->ctrl, spi_ctrl | SPI_CTRL_GO_BSY);
+}
+
+/**
+ * \param   spi_freq    : Desired frequency for the generated clock from the SPI
+ *                        controller
+ * \param   sys_freq    : System clock frequency
+ *
+ * \brief   Calculated the value for the divider register in order to obtain the SPI
+ *          desired clock frequency 
+ */
+static unsigned int _spi_calc_divider_value  (
+    unsigned int spi_freq   ,
+    unsigned int sys_freq   )
+{
+    return ((sys_freq / (spi_freq * 2)) - 1);
+}
+
+void spi_put_tx(struct spi_dev * spi, unsigned char byte, int index)
+{
+    _spi_wait_if_busy(spi);
+    {
+        iowrite8(&spi->rx_tx[index % 4], byte);
+        _spi_init_transfer(spi);
+
+        asm volatile("sync");
+    }
+    _spi_wait_if_busy(spi);
+}
+
+volatile unsigned char spi_get_rx(struct spi_dev * spi, int index)
+{
+    return ioread8(&spi->rx_tx[index % 4]);
+}
+
+void spi_ss_assert(struct spi_dev * spi, int index)
+{
+    unsigned int spi_ss = ioread32(&spi->ss);
+
+    iowrite32(&spi->ss, spi_ss | (1 << index));
+}
+
+void spi_ss_deassert(struct spi_dev * spi, int index)
+{
+    unsigned int spi_ss = ioread32(&spi->ss);
+
+    iowrite32(&spi->ss, spi_ss & ~(1 << index));
+}
+
+void spi_dev_config (
+    struct spi_dev * spi,
+    int spi_freq     	,
+    int sys_freq        ,
+    int char_len		,
+    int tx_edge			,
+    int rx_edge			)
+{
+    unsigned int spi_ctrl = ioread32(&spi->ctrl);
+
+    if      ( tx_edge == 0 ) spi_ctrl |=  SPI_CTRL_TXN_EN;
+    else if ( tx_edge == 1 ) spi_ctrl &= ~SPI_CTRL_TXN_EN;
+    if      ( rx_edge == 0 ) spi_ctrl |=  SPI_CTRL_RXN_EN;
+    else if ( rx_edge == 1 ) spi_ctrl &= ~SPI_CTRL_RXN_EN;
+    if      ( char_len > 0 ) spi_ctrl  = (spi_ctrl & ~SPI_CTRL_CHAR_LEN_MASK) |
+                                         (char_len &  SPI_CTRL_CHAR_LEN_MASK);
+
+    iowrite32(&spi->ctrl, spi_ctrl);
+
+    if (spi_freq > 0 && sys_freq > 0)
+        iowrite32(&spi->divider, _spi_calc_divider_value(spi_freq, sys_freq));
+
+}
+
+/*
+ * vim: tabstop=4 : shiftwidth=4 : expandtab : softtabstop=4
+ */
